dc7af662ff
Add patch ported from SLE OBS-URL: https://build.opensuse.org/request/show/517991 OBS-URL: https://build.opensuse.org/package/show/devel:libraries:c_c++/leveldb?expand=0&rev=22
209 lines
5.8 KiB
Diff
209 lines
5.8 KiB
Diff
diff --git a/port/atomic_pointer.h b/port/atomic_pointer.h
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index 1c4c7aa..c2c34b1 100644
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--- a/port/atomic_pointer.h
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+++ b/port/atomic_pointer.h
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@@ -41,6 +41,18 @@
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#define ARCH_CPU_PPC_FAMILY 1
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#elif defined(__mips__)
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#define ARCH_CPU_MIPS_FAMILY 1
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+#elif defined(__ia64__)
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+#define ARCH_CPU_IA64_FAMILY 1
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+#elif defined(__alpha__)
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+#define ARCH_CPU_ALPHA_FAMILY 1
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+#elif defined(__s390x__) || defined(__s390__)
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+#define ARCH_CPU_S390_FAMILY 1
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+#elif defined(__sparc__) || defined(__sparc64__)
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+#define ARCH_CPU_SPARC_FAMILY 1
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+#elif defined(__sh__)
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+#define ARCH_CPU_SH_FAMILY 1
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+#elif defined(__hppa__) || defined(__parisc__)
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+#define ARCH_CPU_PARISC_FAMILY 1
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#endif
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namespace leveldb {
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@@ -55,14 +67,25 @@ namespace port {
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// Mac OS
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#elif defined(OS_MACOSX)
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ OSMemoryBarrier();
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+}
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+inline void WriteMemoryBarrier() {
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OSMemoryBarrier();
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}
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#define LEVELDB_HAVE_MEMORY_BARRIER
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+#define ReadMemoryBarrier MemoryBarrier()
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+#define WriteMemoryBarrier MemoryBarrier()
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+
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// Gcc on x86
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#elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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__asm__ __volatile__("" : : : "memory");
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@@ -71,7 +94,12 @@ inline void MemoryBarrier() {
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// Sun Studio
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#elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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+ asm volatile("" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
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// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
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asm volatile("" : : : "memory");
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@@ -91,24 +119,109 @@ typedef void (*LinuxKernelMemoryBarrierFunc)(void);
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// shows that the extra function call cost is completely negligible on
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// multi-core devices.
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//
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
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+}
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+inline void WriteMemoryBarrier() {
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(*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
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}
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#define LEVELDB_HAVE_MEMORY_BARRIER
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// ARM64
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#elif defined(ARCH_CPU_ARM64_FAMILY)
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-inline void MemoryBarrier() {
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+inline void ReadMemoryBarrier() {
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+ asm volatile("dmb sy" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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asm volatile("dmb sy" : : : "memory");
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}
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#define LEVELDB_HAVE_MEMORY_BARRIER
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// PPC
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#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__)
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-inline void MemoryBarrier() {
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- // TODO for some powerpc expert: is there a cheaper suitable variant?
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- // Perhaps by having separate barriers for acquire and release ops.
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- asm volatile("sync" : : : "memory");
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+
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+inline void ReadMemoryBarrier() {
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+#ifdef __powerpc64__
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+ __asm__ __volatile__ ("lwsync" : : : "memory");
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+#else
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+ __asm__ __volatile__ ("sync" : : : "memory");
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+#endif
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("sync" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// IA64
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+#elif defined(ARCH_CPU_IA64_FAMILY)
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__ ("mf" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("mf" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// ALPHA
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+#elif defined(ARCH_CPU_ALPHA_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__("mb" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__("wmb" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// S390
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+#elif defined(ARCH_CPU_S390_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ asm volatile("bcr 15,0" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ asm volatile("bcr 15,0" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// SPARC
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+#elif defined(ARCH_CPU_SPARC_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// SH
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+#elif defined(ARCH_CPU_SH_FAMILY)
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+#if defined(__SH4A__) || defined(__SH5__)
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__ ("synco": : :"memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("synco": : :"memory");
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+}
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+#else
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__ ("": : :"memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__ ("": : :"memory");
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+}
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+#endif
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+#define LEVELDB_HAVE_MEMORY_BARRIER
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+
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+// PARISC
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+#elif defined(ARCH_CPU_PARISC_FAMILY)
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+
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+inline void ReadMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory");
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+}
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+inline void WriteMemoryBarrier() {
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+ __asm__ __volatile__("" : : : "memory");
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}
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#define LEVELDB_HAVE_MEMORY_BARRIER
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@@ -133,11 +246,11 @@ class AtomicPointer {
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inline void NoBarrier_Store(void* v) { rep_ = v; }
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inline void* Acquire_Load() const {
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void* result = rep_;
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- MemoryBarrier();
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+ ReadMemoryBarrier();
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return result;
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}
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inline void Release_Store(void* v) {
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- MemoryBarrier();
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+ WriteMemoryBarrier();
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rep_ = v;
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}
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};
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@@ -235,6 +348,12 @@ class AtomicPointer {
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#undef ARCH_CPU_ARM_FAMILY
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#undef ARCH_CPU_ARM64_FAMILY
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#undef ARCH_CPU_PPC_FAMILY
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+#undef ARCH_CPU_IA64_FAMILY
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+#undef ARCH_CPU_ALPHA_FAMILY
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+#undef ARCH_CPU_S390_FAMILY
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+#undef ARCH_CPU_SPARC_FAMILY
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+#undef ARCH_CPU_SH_FAMILY
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+#undef ARCH_CPU_PARISC_FAMILY
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} // namespace port
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} // namespace leveldb
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