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leveldb/0001-debian-ports.patch
Dirk Mueller b7d50aa5a5 - update to 1.18: 
+ Replace the basic fprintf call with a call to fwrite
  + Fix ALL the header guards.
  + A new CONTRIBUTING file.
  + leveldb: Remove unused function 'ConsumeChar'.
  + leveldbutil: Remove unused member variables from WriteBatchItemPrinter.
  + Verify checksums of index/meta/filter blocks when paranoid_checks set.
  + Invoke all tools for iOS with xcrun. (This was causing problems with the new XCode 5.1.1 image on pulse.)
  + include only once, and fix the following linter warning: "Found C system header after C++ system header"
  + When encountering a corrupted table file, return Status::Corruption instead of Status::InvalidArgument.
  + Support cygwin as build platform, patch is from https://code.google.com/p/leveldb/issues/detail?id=188
  + Fix typo, merge patch from https://code.google.com/p/leveldb/issues/detail?id=159
  + Fix typos and comments, and address the following two issues:
  + Add missing db synchronize after "fillseq" in the benchmark.
  + Removed unused variable in SeekRandom: value (issue #201)

OBS-URL: https://build.opensuse.org/package/show/devel:libraries:c_c++/leveldb?expand=0&rev=14
2014-10-20 12:29:25 +00:00

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Description: Add support for most of Debian architectures
Author: Nobuhiro Iwamatsu <iwamatsu@debian.org>
---
port/atomic_pointer.h | 136 ++++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 126 insertions(+), 10 deletions(-)
Index: leveldb-1.18/port/atomic_pointer.h
===================================================================
--- leveldb-1.18.orig/port/atomic_pointer.h
+++ leveldb-1.18/port/atomic_pointer.h
@@ -37,6 +37,18 @@
#define ARCH_CPU_ARM_FAMILY 1
#elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__)
#define ARCH_CPU_PPC_FAMILY 1
+#elif defined(__ia64__)
+#define ARCH_CPU_IA64_FAMILY 1
+#elif defined(__alpha__)
+#define ARCH_CPU_ALPHA_FAMILY 1
+#elif defined(__s390x__) || defined(__s390__)
+#define ARCH_CPU_S390_FAMILY 1
+#elif defined(__sparc__) || defined(__sparc64__)
+#define ARCH_CPU_SPARC_FAMILY 1
+#elif defined(__sh__)
+#define ARCH_CPU_SH_FAMILY 1
+#elif defined(__hppa__) || defined(__parisc__)
+#define ARCH_CPU_PARISC_FAMILY 1
#endif
namespace leveldb {
@@ -49,16 +61,27 @@ namespace port {
// http://msdn.microsoft.com/en-us/library/ms684208(v=vs.85).aspx
#define LEVELDB_HAVE_MEMORY_BARRIER
+#define ReadMemoryBarrier MemoryBarrier()
+#define WriteMemoryBarrier MemoryBarrier()
+
// Mac OS
#elif defined(OS_MACOSX)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ OSMemoryBarrier();
+}
+inline void WriteMemoryBarrier() {
OSMemoryBarrier();
}
#define LEVELDB_HAVE_MEMORY_BARRIER
// Gcc on x86
#elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
+ __asm__ __volatile__("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
__asm__ __volatile__("" : : : "memory");
@@ -67,7 +90,12 @@ inline void MemoryBarrier() {
// Sun Studio
#elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ // See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
+ // this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
+ asm volatile("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
// See http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html for a discussion on
// this idiom. Also see http://en.wikipedia.org/wiki/Memory_ordering.
asm volatile("" : : : "memory");
@@ -87,17 +115,99 @@ typedef void (*LinuxKernelMemoryBarrierF
// shows that the extra function call cost is completely negligible on
// multi-core devices.
//
-inline void MemoryBarrier() {
+inline void ReadMemoryBarrier() {
+ (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
+}
+inline void WriteMemoryBarrier() {
(*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
}
#define LEVELDB_HAVE_MEMORY_BARRIER
// PPC
#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__)
-inline void MemoryBarrier() {
- // TODO for some powerpc expert: is there a cheaper suitable variant?
- // Perhaps by having separate barriers for acquire and release ops.
- asm volatile("sync" : : : "memory");
+
+inline void ReadMemoryBarrier() {
+#ifdef __powerpc64__
+ __asm__ __volatile__ ("lwsync" : : : "memory");
+#else
+ __asm__ __volatile__ ("sync" : : : "memory");
+#endif
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("sync" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// IA64
+#elif defined(ARCH_CPU_IA64_FAMILY)
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("mf" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("mf" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// ALPHA
+#elif defined(ARCH_CPU_ALPHA_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("mb" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("wmb" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// S390
+#elif defined(ARCH_CPU_S390_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ asm volatile("bcr 15,0" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ asm volatile("bcr 15,0" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// SPARC
+#elif defined(ARCH_CPU_SPARC_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory");
+}
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// SH
+#elif defined(ARCH_CPU_SH_FAMILY)
+#if defined(__SH4A__) || defined(__SH5__)
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("synco": : :"memory");
+}
+#else
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__ ("": : :"memory");
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__ ("": : :"memory");
+}
+#endif
+#define LEVELDB_HAVE_MEMORY_BARRIER
+
+// PARISC
+#elif defined(ARCH_CPU_PARISC_FAMILY)
+
+inline void ReadMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory")
+}
+inline void WriteMemoryBarrier() {
+ __asm__ __volatile__("" : : : "memory")
}
#define LEVELDB_HAVE_MEMORY_BARRIER
@@ -115,11 +225,11 @@ class AtomicPointer {
inline void NoBarrier_Store(void* v) { rep_ = v; }
inline void* Acquire_Load() const {
void* result = rep_;
- MemoryBarrier();
+ ReadMemoryBarrier();
return result;
}
inline void Release_Store(void* v) {
- MemoryBarrier();
+ WriteMemoryBarrier();
rep_ = v;
}
};
@@ -216,6 +326,12 @@ class AtomicPointer {
#undef ARCH_CPU_X86_FAMILY
#undef ARCH_CPU_ARM_FAMILY
#undef ARCH_CPU_PPC_FAMILY
+#undef ARCH_CPU_IA64_FAMILY
+#undef ARCH_CPU_ALPHA_FAMILY
+#undef ARCH_CPU_S390_FAMILY
+#undef ARCH_CPU_SPARC_FAMILY
+#undef ARCH_CPU_SH_FAMILY
+#undef ARCH_CPU_PARISC_FAMILY
} // namespace port
} // namespace leveldb
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