32 lines
853 B
Diff
32 lines
853 B
Diff
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From 58d008883165ba35c83041fa9ed84937163d5f76 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri, 6 Sep 2013 15:58:56 -0400
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Subject: [PATCH 1/1] radeon: pad CS to 8 DW
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Aligns the IB to 8 DWs. The aligns the IB to the
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CP fetch size. r6xx also require at least 4 DW
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alignment to avoid a hw bug.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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radeon/radeon_cs_gem.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
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index b963140..b87c6b1 100644
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--- a/radeon/radeon_cs_gem.c
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+++ b/radeon/radeon_cs_gem.c
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@@ -425,6 +425,9 @@ static int cs_gem_emit(struct radeon_cs_int *cs)
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unsigned i;
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int r;
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+ while (cs->cdw & 7)
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+ radeon_cs_write_dword((struct radeon_cs *)cs, 0x80000000);
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+
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#if CS_BOF_DUMP
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cs_gem_dump_bof(cs);
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#endif
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--
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1.8.4
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