4bcd09a4c9
New patch: update-cavium-thunderx2-with-now-public-events.patch OBS-URL: https://build.opensuse.org/package/show/devel:libraries:c_c++/libpfm?expand=0&rev=47
321 lines
9.0 KiB
Diff
321 lines
9.0 KiB
Diff
From: Steve Walk <steve.walk@cavium.com>
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Date: Tue Mar 20 09:37:56 2018 -0700
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Subject: update Cavium ThunderX2 with now public events
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Git-commit: 6c9e44b95a55b8bf62cbd64009c4c9b30964a66c
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References: jsc#SLE-10000
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Signed-off-by: Tony Jones <tonyj@suse.de>
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update Cavium ThunderX2 with now public events
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This patch adds new model specific events to the
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Cavium Thunder X2 core PMU. The updated list is based
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on publicly available documentation from Cavium which
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is available at:
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https://cavium.com/resources.html
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Signed-off-by: Steve Walk <steve.walk@cavium.com>
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diff --git a/lib/events/arm_cavium_tx2_events.h b/lib/events/arm_cavium_tx2_events.h
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index 67de9f8..198d33d 100644
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--- a/lib/events/arm_cavium_tx2_events.h
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+++ b/lib/events/arm_cavium_tx2_events.h
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@@ -23,6 +23,9 @@
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*
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* ARM Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile,
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* ARM DDI 0487B.a (ID033117)
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+ *
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+ * Cavium ThunderX2 C99XX PMU Events (Abridged), July 31, 2018
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+ * https://cavium.com/resources.html
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*/
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static const arm_entry_t arm_thunderx2_pe[]={
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@@ -161,6 +164,11 @@ static const arm_entry_t arm_thunderx2_pe[]={
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.code = 0x1C,
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.desc = "Instruction architecturally executed (condition check pass) Write to translation table base"
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},
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+ {.name = "CHAIN",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x1E,
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+ .desc = "For odd-numbered counters, increments the count by one for each overflow of the proceeding even counter"
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+ },
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{.name = "L1D_CACHE_ALLOCATE",
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.modmsk = ARMV8_ATTRS,
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.code = 0x1F,
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@@ -556,6 +564,274 @@ static const arm_entry_t arm_thunderx2_pe[]={
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.code = 0x91,
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.desc = "Release consistency instruction speculatively executed (store-release)"
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},
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-
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- /* END Cavium ThunderX2 specific events */
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+ {.name = "L1D_LHS_VANOTP",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC1,
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+ .desc = "A Load hit store retry"
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+ },
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+ {.name = "L1D_LHS_OVRLAP",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC2,
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+ .desc = "A Load hit store retry, VA match, PA mismatch"
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+ },
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+ {.name = "L1D_LHS_VANOSD",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC3,
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+ .desc = "A Load hit store retry, VA match, store data not issued"
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+ },
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+ {.name = "L1D_LHS_FWD",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC4,
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+ .desc = "A Load hit store forwarding. Load completes"
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+ },
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+ {.name = "L1D_BNKCFL",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC6,
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+ .desc = "Bank conflict load retry"
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+ },
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+ {.name = "L1D_LSMQ_FULL",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC7,
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+ .desc = "LSMQ retry"
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+ },
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+ {.name = "L1D_LSMQ_HIT",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC8,
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+ .desc = "LSMQ hit retry"
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+ },
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+ {.name = "L1D_EXPB_MISS",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xC9,
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+ .desc = "An external probe missed the L1"
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+ },
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+ {.name = "L1D_L2EV_MISS",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xCA,
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+ .desc = "An L2 evict operation missed the L1"
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+ },
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+ {.name = "L1D_EXPB_HITM",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xCB,
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+ .desc = "An external probe hit a modified line in the L1"
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+ },
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+ {.name = "L1D_L2EV_HITM",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xCC,
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+ .desc = "An L2 evict operation hit a modified line in the L1"
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+ },
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+ {.name = "L1D_EXPB_HIT",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xCD,
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+ .desc = "An external probe hit in the L1"
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+ },
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+ {.name = "L1D_L2EV_HIT",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xCE,
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+ .desc = "An L2 evict operation hit in the L1"
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+ },
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+ {.name = "L1D_EXPB_RETRY",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xCF,
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+ .desc = "An external probe hit was retried"
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+ },
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+ {.name = "L1D_L2EV_RETRY",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xD0,
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+ .desc = "An L2 evict operation was retried"
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+ },
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+ {.name = "L1D_ST_RMW",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xD1,
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+ .desc = "A read modify write store was drained and updated the L1"
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+ },
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+ {.name = "L1D_LSMQ00_LDREQ",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xD2,
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+ .desc = "A load has allocated LSMQ entry 0"
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+ },
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+ {.name = "L1D_LSMQ00_LDVLD",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xD3,
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+ .desc = "LSMQ entry 0 was initiated by a load"
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+ },
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+ {.name = "L1D_LSMQ15_STREQ",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xD4,
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+ .desc = "A store was allocated LSMQ entry 15"
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+ },
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+ {.name = "L1D_LSMQ15_STVLD",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xD5,
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+ .desc = "LSMQ entry 15 was initiated by a store"
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+ },
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+ {.name = "L1D_PB_FLUSH",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xD6,
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+ .desc = "LRQ ordering flush"
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+ },
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+ {.name = "BR_COND_MIS_PRED_RETIRED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xE0,
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+ .desc = "Conditional branch instruction executed, but mis-predicted"
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+ },
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+ {.name = "BR_IND_MIS_PRED_RETIRED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xE1,
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+ .desc = "Indirect branch instruction executed, but mis-predicted"
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+ },
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+ {.name = "BR_RETURN_MIS_PRED_RETIRED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xE2,
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+ .desc = "Return branch instruction executed, but mis-predicted"
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+ },
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+ {.name = "OP_RETIRED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xE8,
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+ .desc = "Uops executed"
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+ },
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+ {.name = "LD_OP_RETIRED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xE9,
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+ .desc = "Load uops executed"
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+ },
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+ {.name = "ST_OP_RETIRED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xEA,
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+ .desc = "Store uops executed"
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+ },
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+ {.name = "FUSED_OP_RETIRED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xEB,
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+ .desc = "Fused uops executed"
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+ },
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+ {.name = "IRQ_MASK",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xF8,
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+ .desc = "Cumulative duration of a PSTATE.I interrupt mask set to 1"
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+ },
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+ {.name = "FIQ_MASK",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xF9,
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+ .desc = "Cumulative duration of a PSTATE.F interrupt mask set to 1"
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+ },
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+ {.name = "SERROR_MASK",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0xFA,
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+ .desc = "Cumulative duration of PSTATE.A interrupt mask set to 1"
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+ },
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+ {.name = "WFIWFE_SLEEP",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x108,
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+ .desc = "Number of cycles in which CPU is in low power mode due to WFI/WFE instruction"
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+ },
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+ {.name = "L2TLB_4K_PAGE_MISS",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x127,
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+ .desc = "L2 TLB lookup miss using 4K page size"
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+ },
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+ {.name = "L2TLB_64K_PAGE_MISS",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x128,
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+ .desc = "L2 TLB lookup miss using 64K page size"
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+ },
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+ {.name = "L2TLB_2M_PAGE_MISS",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x129,
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+ .desc = "L2 TLB lookup miss using 2M page size"
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+ },
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+ {.name = "L2TLB_512M_PAGE_MISS",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x12A,
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+ .desc = "L2 TLB lookup miss using 512M page size"
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+ },
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+ {.name = "ISB_EMPTY",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x150,
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+ .desc = "Number of cycles during which micro-op skid-buffer is empty"
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+ },
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+ {.name = "ISB_FULL",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x151,
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+ .desc = "Number of cycles during which micro-op skid-buffer is back-pressuring decode"
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+ },
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+ {.name = "STALL_NOTSELECTED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x152,
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+ .desc = "Number of cycles during which thread was available for dispatch but not selected"
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+ },
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+ {.name = "ROB_RECYCLE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x153,
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+ .desc = "Number of cycles in which one or more valid micro-ops did not dispatch due to ROB full"
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+ },
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+ {.name = "ISSQ_RECYCLE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x154,
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+ .desc = "Number of cycles in which one or more valid micro-ops did not dispatch due to ISSQ full"
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+ },
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+ {.name = "GPR_RECYCLE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x155,
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+ .desc = "Number of cycles in which one or more valid micro-ops did not dispatch due to GPR full"
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+ },
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+ {.name = "FPR_RECYCLE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x156,
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+ .desc = "Number of cycles in which one or more valid micro-ops did not dispatch due to FPR full"
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+ },
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+ {.name = "LRQ_RECYCLE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x158,
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+ .desc = "Number of cycles in which one or more valid micro-ops did not dispatch due to LRQ full"
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+ },
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+ {.name = "SRQ_RECYCLE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x159,
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+ .desc = "Number of cycles in which one or more valid micro-ops did not dispatch due to SRQ full"
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+ },
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+ {.name = "BSR_RECYCLE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x15B,
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+ .desc = "Number of cycles in which one or more valid micro-ops did not dispatch due to BSR full"
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+ },
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+ {.name = "UOPSFUSED",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x164,
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+ .desc = "Number of fused micro-ops dispatched"
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+ },
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+ {.name = "L2D_TLBI_INT",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x20B,
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+ .desc = "Internal mmu tlbi cacheops"
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+ },
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+ {.name = "L2D_TLBI_EXT",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x20C,
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+ .desc = "External mmu tlbi cacheops"
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+ },
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+ {.name = "L2D_HWPF_DMD_HIT",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x218,
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+ .desc = "Scu ld/st requests that hit cache or msg for lines brought in by the hardware prefetcher"
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+ },
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+ {.name = "L2D_HWPF_REQ_VAL",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x219,
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+ .desc = "Scu hwpf requests into the pipeline"
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+ },
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+ {.name = "L2D_HWPF_REQ_LD",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x21A,
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+ .desc = "Scu hwpf ld requests into the pipeline"
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+ },
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+ {.name = "L2D_HWPF_REQ_MISS",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x21B,
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+ .desc = "Scu hwpf ld requests that miss"
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+ },
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+ {.name = "L2D_HWPF_NEXT_LINE",
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+ .modmsk = ARMV8_ATTRS,
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+ .code = 0x21C,
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+ .desc = "Scu hwpf next line requests generated"
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+ },
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};
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