2014-05-16 17:58:42 +02:00
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Add F10h decoding support
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Signed-off-by: Borislav Petkov <bp@suse.de>
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2018-09-24 15:47:13 +02:00
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Index: mcelog-1.60/amd.c
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2014-05-16 17:58:42 +02:00
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===================================================================
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2018-09-24 15:47:13 +02:00
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--- mcelog-1.60.orig/amd.c 2018-09-24 15:14:18.771885991 +0200
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+++ mcelog-1.60/amd.c 2018-09-24 15:15:05.902689347 +0200
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2014-05-16 17:58:42 +02:00
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@@ -14,7 +14,7 @@
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#include "mcelog.h"
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#include "amd.h"
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-static char *k8bank[] = {
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+static const char * const k8bank[] = {
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"data cache",
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"instruction cache",
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"bus unit",
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2016-05-09 16:33:31 +02:00
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@@ -22,28 +22,34 @@ static char *k8bank[] = {
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2014-05-16 17:58:42 +02:00
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"northbridge",
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"fixed-issue reoder"
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};
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-static char *transaction[] = {
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+static const char * const transaction[] = {
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"instruction", "data", "generic", "reserved"
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-};
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-static char *cachelevel[] = {
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+};
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+static const char * const cachelevel[] = {
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"0", "1", "2", "generic"
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};
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-static char *memtrans[] = {
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+static const char * const memtrans[] = {
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"generic error", "generic read", "generic write", "data read",
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"data write", "instruction fetch", "prefetch", "evict", "snoop",
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"?", "?", "?", "?", "?", "?", "?"
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};
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-static char *partproc[] = {
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- "local node origin", "local node response",
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- "local node observed", "generic participation"
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+static const char * const partproc[] = {
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+ "local node origin",
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+ "local node response",
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+ "local node observed",
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+ "generic participation"
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};
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-static char *timeout[] = {
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+static const char * const timeout[] = {
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"request didn't time out",
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"request timed out"
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};
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-static char *memoryio[] = {
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+static const char * const memoryio[] = {
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"memory", "res.", "i/o", "generic"
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};
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+
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+/* internal error type */
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+static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };
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+
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static char *nbextendederr[] = {
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"RAM ECC error",
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"CRC error",
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2016-05-09 16:33:31 +02:00
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@@ -65,6 +71,46 @@ static char *nbextendederr[] = {
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2014-05-16 17:58:42 +02:00
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"L3 Cache Tag Error",
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"L3 Cache LRU Error"
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};
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+
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+static const char * const mc4_mce_desc[] = {
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+ "DRAM ECC error detected on the NB",
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+ "CRC error detected on HT link",
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+ "Link-defined sync error packets detected on HT link",
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+ "HT Master abort",
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+ "HT Target abort",
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+ "Invalid GART PTE entry during GART table walk",
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+ "Unsupported atomic RMW received from an IO link",
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+ "Watchdog timeout due to lack of progress",
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+ "DRAM ECC error detected on the NB",
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+ "SVM DMA Exclusion Vector error",
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+ "HT data error detected on link",
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+ "Protocol error (link, L3, probe filter)",
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+ "NB internal arrays parity error",
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+ "DRAM addr/ctl signals parity error",
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+ "IO link transmission error",
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+ "L3 data cache ECC error", /* xec = 0x1c */
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+ "L3 cache tag error",
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+ "L3 LRU parity bits error",
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+ "ECC Error in the Probe Filter directory"
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+};
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+
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+static const char * const mc5_mce_desc[] = {
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+ "CPU Watchdog timer expire",
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+ "Wakeup array dest tag",
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+ "AG payload array",
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+ "EX payload array",
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+ "IDRF array",
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+ "Retire dispatch queue",
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+ "Mapper checkpoint array",
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+ "Physical register file EX0 port",
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+ "Physical register file EX1 port",
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+ "Physical register file AG0 port",
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+ "Physical register file AG1 port",
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+ "Flag register file",
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+ "DE error occurred",
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+ "Retire status queue"
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+};
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+
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static char *highbits[32] = {
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[31] = "valid",
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[30] = "error overflow (multiple errors)",
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2016-05-09 16:33:31 +02:00
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@@ -100,6 +146,21 @@ static char *k8threshold[] = {
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2014-05-16 17:58:42 +02:00
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"Unknown threshold counter",
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};
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+static u8 xec_mask = 0xf;
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+
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+enum cputype select_amd_cputype(u32 family)
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+{
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+ switch (family) {
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+ case 0xf:
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+ return CPU_K8;
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+ case 0x10:
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+ return CPU_F10H;
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+ default:
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+ break;
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+ }
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+
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+ return CPU_GENERIC;
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+}
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static void decode_k8_generic_errcode(u64 status)
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{
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2016-05-09 16:33:31 +02:00
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@@ -245,21 +306,393 @@ static decoder_t decoders[] = {
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2014-05-16 17:58:42 +02:00
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[5] = decode_k8_fr_mc,
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};
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-void decode_amd_mc(enum cputype cpu, struct mce *mce, int *ismemerr)
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+static bool k8_mc1_mce(u16 ec, u8 xec)
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+{
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+ u8 ll = LL(ec);
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+ bool ret = true;
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+
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+ if (!MEM_ERROR(ec))
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+ return false;
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+
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+ if (ll == 0x2)
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+ Wprintf("during a linefill from L2.\n");
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+ else if (ll == 0x1) {
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+ switch (R4(ec)) {
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+ case R4_IRD:
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+ Wprintf("Parity error during data load.\n");
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+ break;
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+
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+ case R4_EVICT:
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+ Wprintf("Copyback Parity/Victim error.\n");
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+ break;
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+
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+ case R4_SNOOP:
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+ Wprintf("Tag Snoop error.\n");
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+ break;
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+
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+ default:
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+ ret = false;
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+ break;
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+ }
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+ } else
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+ ret = false;
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+
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+ return ret;
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+}
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+
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+static bool f12h_mc0_mce(u16 ec, u8 xec)
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+{
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+ bool ret = false;
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+
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+ if (MEM_ERROR(ec)) {
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+ u8 ll = LL(ec);
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+ ret = true;
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+
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+ if (ll == LL_L2)
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+ Wprintf("aduring L1 linefill from L2.\n");
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+ else if (ll == LL_L1)
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+ Wprintf("Data/Tag %s error.\n", R4_MSG(ec));
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+ else
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+ ret = false;
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+ }
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+ return ret;
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+}
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+
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+static bool f10h_mc0_mce(u16 ec, u8 xec)
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+{
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+ if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
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+ Wprintf("during data scrub.\n");
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+ return true;
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+ }
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+ return f12h_mc0_mce(ec, xec);
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+}
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+
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+static void decode_mc0_mce(struct amd_decoder_ops *ops, struct mce *m)
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+{
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+ u16 ec = EC(m->status);
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+ u8 xec = XEC(m->status, xec_mask);
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+
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+ Wprintf(" MC0 Error: ");
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+
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+ /* TLB error signatures are the same across families */
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+ if (TLB_ERROR(ec)) {
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+ if (TT(ec) == TT_DATA) {
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+ Wprintf("%s TLB %s.\n", LL_MSG(ec),
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+ ((xec == 2) ? "locked miss"
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+ : (xec ? "multimatch" : "parity")));
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+ return;
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+ }
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+ } else if (ops->mc0_mce(ec, xec))
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+ ;
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+ else
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+ Eprintf("Corrupted MC0 MCE info?\n");
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+}
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+
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+static void decode_mc1_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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- if (mce->bank < NELE(decoders))
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- decoders[mce->bank](mce->status, ismemerr);
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- else if (mce->bank >= K8_MCE_THRESHOLD_BASE &&
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- mce->bank < K8_MCE_THRESHOLD_TOP)
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- decode_k8_threshold(mce->misc);
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+ u16 ec = EC(m->status);
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+ u8 xec = XEC(m->status, xec_mask);
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+
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+ Wprintf(" MC1 Error: ");
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+
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+ if (TLB_ERROR(ec))
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+ Wprintf("%s TLB %s.\n", LL_MSG(ec),
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+ (xec ? "multimatch" : "parity error"));
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+ else if (BUS_ERROR(ec)) {
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+ bool k8 = ((ops->cpu == AMD_K8) && (m->status & BIT_64(58)));
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+
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+ Wprintf("during %s.\n", (k8 ? "system linefill" : "NB data read"));
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+ } else if (ops->mc1_mce(ec, xec))
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+ ;
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else
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- Wprintf(" no decoder for unknown bank %u\n", mce->bank);
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+ Eprintf("Corrupted MC1 MCE info?\n");
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+}
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+
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+static bool k8_mc2_mce(u16 ec, u8 xec)
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+{
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+ bool ret = true;
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+
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+ if (xec == 0x1)
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+ Wprintf(" in the write data buffers.\n");
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+ else if (xec == 0x3)
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+ Wprintf(" in the victim data buffers.\n");
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+ else if (xec == 0x2 && MEM_ERROR(ec))
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+ Wprintf(": %s error in the L2 cache tags.\n", R4_MSG(ec));
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+ else if (xec == 0x0) {
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+ if (TLB_ERROR(ec))
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+ Wprintf(": %s error in a Page Descriptor Cache or "
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+ "Guest TLB.\n", TT_MSG(ec));
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+ else if (BUS_ERROR(ec))
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+ Wprintf(": %s/ECC error in data read from NB: %s.\n",
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+ R4_MSG(ec), PP_MSG(ec));
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+ else if (MEM_ERROR(ec)) {
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+ u8 r4 = R4(ec);
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+
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+ if (r4 >= 0x7)
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+ Wprintf(": %s error during data copyback.\n",
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+ R4_MSG(ec));
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+ else if (r4 <= 0x1)
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+ Wprintf(": %s parity/ECC error during data "
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+ "access from L2.\n", R4_MSG(ec));
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+ else
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+ ret = false;
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+ } else
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+ ret = false;
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+ } else
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+ ret = false;
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+
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+ return ret;
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+}
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+
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+static void decode_mc2_mce(struct amd_decoder_ops *ops, struct mce *m)
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+{
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+ u16 ec = EC(m->status);
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+ u8 xec = XEC(m->status, xec_mask);
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+
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+ Wprintf(" MC2 Error: ");
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+
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+ if (!ops->mc2_mce(ec, xec))
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+ Eprintf("Corrupted MC2 MCE info?\n");
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+}
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+
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+static void decode_mc3_mce(struct amd_decoder_ops *ops, struct mce *m)
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+{
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+ u16 ec = EC(m->status);
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+ u8 xec = XEC(m->status, xec_mask);
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+
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+ if (ops->cpu >= AMD_F14H) {
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+ Eprintf("You shouldn't be seeing MC3 MCE on this cpu family,"
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+ " please report on LKML.\n");
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+ return;
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+ }
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+
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+ Wprintf(" MC3 Error");
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+
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+ if (xec == 0x0) {
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+ u8 r4 = R4(ec);
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+
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+ if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
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+ goto wrong_mc3_mce;
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+
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+ Wprintf(" during %s.\n", R4_MSG(ec));
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+ } else
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+ goto wrong_mc3_mce;
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+
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+ return;
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+
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+wrong_mc3_mce:
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+ Eprintf("Corrupted MC3 MCE info?\n");
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+}
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+
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+static void decode_mc4_mce(struct amd_decoder_ops *ops, struct mce *m)
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+{
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+ u16 ec = EC(m->status);
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+ u8 xec = XEC(m->status, 0x1f);
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+ u8 offset = 0;
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+
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+ Wprintf(" MC4 Error: ");
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+
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+ switch (xec) {
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+ case 0x0 ... 0xe:
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+
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+ /* special handling for DRAM ECCs */
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+ if (xec == 0x0 || xec == 0x8) {
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+ /* no ECCs on F11h */
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+ if (ops->cpu == AMD_F11H)
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+ goto wrong_mc4_mce;
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+
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+ Wprintf("%s.\n", mc4_mce_desc[xec]);
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+ return;
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+ }
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+ break;
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+
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+ case 0xf:
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+ if (TLB_ERROR(ec))
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+ Wprintf("GART Table Walk data error.\n");
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+ else if (BUS_ERROR(ec))
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+ Wprintf("DMA Exclusion Vector Table Walk error.\n");
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+ else
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+ goto wrong_mc4_mce;
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+ return;
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+
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+ case 0x19:
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+ if (ops->cpu >= AMD_F15H || ops->cpu <= AMD_F16H)
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+ Wprintf("Compute Unit Data Error.\n");
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+ else
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|
|
+ goto wrong_mc4_mce;
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ case 0x1c ... 0x1f:
|
|
|
|
+ offset = 13;
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ default:
|
|
|
|
+ goto wrong_mc4_mce;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ Wprintf("%s.\n", mc4_mce_desc[xec - offset]);
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ wrong_mc4_mce:
|
|
|
|
+ Eprintf("Corrupted MC4 MCE info?\n");
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void decode_mc5_mce(struct amd_decoder_ops *ops, struct mce *m)
|
|
|
|
+{
|
|
|
|
+ u8 xec = XEC(m->status, xec_mask);
|
|
|
|
+
|
|
|
|
+ if (ops->cpu == AMD_K8 || ops->cpu == AMD_F11H)
|
|
|
|
+ goto wrong_mc5_mce;
|
|
|
|
+
|
|
|
|
+ Wprintf(" MC5 Error: ");
|
|
|
|
+
|
|
|
|
+ if (xec == 0x0 || xec == 0xc)
|
|
|
|
+ Wprintf("%s.\n", mc5_mce_desc[xec]);
|
|
|
|
+ else if (xec <= 0xd)
|
|
|
|
+ Wprintf("%s parity error.\n", mc5_mce_desc[xec]);
|
|
|
|
+ else
|
|
|
|
+ goto wrong_mc5_mce;
|
|
|
|
+
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ wrong_mc5_mce:
|
|
|
|
+ Eprintf("Corrupted MC5 MCE info?\n");
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static void decode_mc6_mce(struct mce *m)
|
|
|
|
+{
|
|
|
|
+ u8 xec = XEC(m->status, xec_mask);
|
|
|
|
+
|
|
|
|
+ Wprintf(" MC6 Error: ");
|
|
|
|
+
|
|
|
|
+ switch (xec) {
|
|
|
|
+ case 0x1:
|
|
|
|
+ Wprintf("Free List");
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ case 0x2:
|
|
|
|
+ Wprintf("Physical Register File");
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ case 0x3:
|
|
|
|
+ Wprintf("Retire Queue");
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ case 0x4:
|
|
|
|
+ Wprintf("Scheduler table");
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ case 0x5:
|
|
|
|
+ Wprintf("Status Register File");
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ default:
|
|
|
|
+ goto wrong_mc6_mce;
|
|
|
|
+ break;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ Wprintf(" parity error.\n");
|
|
|
|
+
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+ wrong_mc6_mce:
|
|
|
|
+ Eprintf("Corrupted MC6 MCE info?\n");
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static inline void amd_decode_err_code(u16 ec)
|
|
|
|
+{
|
|
|
|
+ if (INT_ERROR(ec)) {
|
|
|
|
+ Wprintf(" internal: %s\n", UU_MSG(ec));
|
|
|
|
+ return;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ Wprintf(" cache level: %s", LL_MSG(ec));
|
|
|
|
+
|
|
|
|
+ if (BUS_ERROR(ec))
|
|
|
|
+ Wprintf(", mem/io: %s", II_MSG(ec));
|
|
|
|
+ else
|
|
|
|
+ Wprintf(", tx: %s", TT_MSG(ec));
|
|
|
|
+
|
|
|
|
+ if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
|
|
|
|
+ Wprintf(", mem-tx: %s", R4_MSG(ec));
|
|
|
|
+
|
|
|
|
+ if (BUS_ERROR(ec))
|
|
|
|
+ Wprintf(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ Wprintf("\n");
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+struct amd_decoder_ops fam_ops[] = {
|
|
|
|
+ [AMD_F10H] = {
|
|
|
|
+ .cpu = AMD_F10H,
|
|
|
|
+ .mc0_mce = f10h_mc0_mce,
|
|
|
|
+ .mc1_mce = k8_mc1_mce,
|
|
|
|
+ .mc2_mce = k8_mc2_mce,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
|
|
|
|
+{
|
|
|
|
+ struct amd_decoder_ops *ops;
|
|
|
|
+
|
|
|
|
+ switch (cpu) {
|
|
|
|
+ case CPU_F10H:
|
|
|
|
+ ops = &fam_ops[AMD_F10H];
|
|
|
|
+ break;
|
|
|
|
+ default:
|
|
|
|
+ Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
|
|
|
|
+ return;
|
|
|
|
+ break;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ switch (mce->bank) {
|
|
|
|
+ case 0:
|
|
|
|
+ decode_mc0_mce(ops, mce);
|
|
|
|
+ break;
|
|
|
|
+ case 1:
|
|
|
|
+ decode_mc1_mce(ops, mce);
|
|
|
|
+ break;
|
|
|
|
+ case 2:
|
|
|
|
+ decode_mc2_mce(ops, mce);
|
|
|
|
+ break;
|
|
|
|
+ case 3:
|
|
|
|
+ decode_mc3_mce(ops, mce);
|
|
|
|
+ break;
|
|
|
|
+ case 4:
|
|
|
|
+ decode_mc4_mce(ops, mce);
|
|
|
|
+ break;
|
|
|
|
+ case 5:
|
|
|
|
+ decode_mc5_mce(ops, mce);
|
|
|
|
+ break;
|
|
|
|
+ case 6:
|
|
|
|
+ decode_mc6_mce(mce);
|
|
|
|
+ break;
|
|
|
|
+
|
|
|
|
+ default:
|
|
|
|
+ break;
|
|
|
|
+ }
|
|
|
|
+ amd_decode_err_code(mce->status & 0xffff);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+void decode_amd_mc(enum cputype cpu, struct mce *mce, int *ismemerr)
|
|
|
|
+{
|
|
|
|
+ if (cpu == CPU_K8) {
|
|
|
|
+ if (mce->bank < NELE(decoders))
|
|
|
|
+ decoders[mce->bank](mce->status, ismemerr);
|
|
|
|
+ else if (mce->bank >= K8_MCE_THRESHOLD_BASE &&
|
|
|
|
+ mce->bank < K8_MCE_THRESHOLD_TOP)
|
|
|
|
+ decode_k8_threshold(mce->misc);
|
|
|
|
+ else
|
|
|
|
+ Wprintf(" no decoder for unknown bank %u\n", mce->bank);
|
|
|
|
+ } else
|
|
|
|
+ __decode_amd_mc(cpu, mce);
|
|
|
|
}
|
|
|
|
|
|
|
|
char *k8_bank_name(unsigned num)
|
|
|
|
{
|
|
|
|
static char buf[64];
|
|
|
|
- char *s = "unknown";
|
|
|
|
+ const char *s = "unknown";
|
|
|
|
if (num < NELE(k8bank))
|
|
|
|
s = k8bank[num];
|
|
|
|
else if (num >= K8_MCE_THRESHOLD_BASE &&
|
2016-05-09 16:33:31 +02:00
|
|
|
@@ -270,13 +703,16 @@ char *k8_bank_name(unsigned num)
|
2014-05-16 17:58:42 +02:00
|
|
|
return buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
-int mce_filter_k8(struct mce *m)
|
|
|
|
-{
|
|
|
|
- /* Filter out GART errors */
|
|
|
|
- if (m->bank == 4) {
|
|
|
|
- unsigned short exterrcode = (m->status >> 16) & 0x0f;
|
|
|
|
- if (exterrcode == 5 && (m->status & (1ULL<<61)))
|
|
|
|
+int mce_filter_amd(struct mce *m)
|
|
|
|
+{
|
|
|
|
+ /*
|
|
|
|
+ * NB GART TLB error reporting is disabled by default.
|
|
|
|
+ */
|
|
|
|
+ if (m->bank == 4) {
|
|
|
|
+ u8 xec = (m->status >> 16) & 0x1f;
|
|
|
|
+
|
|
|
|
+ if (xec == 0x5 && (m->status & BIT_64(61)))
|
|
|
|
return 0;
|
|
|
|
- }
|
|
|
|
- return 1;
|
|
|
|
+ }
|
|
|
|
+ return 1;
|
|
|
|
}
|
2018-09-24 15:47:13 +02:00
|
|
|
Index: mcelog-1.60/amd.h
|
2014-05-16 17:58:42 +02:00
|
|
|
===================================================================
|
2018-09-24 15:47:13 +02:00
|
|
|
--- mcelog-1.60.orig/amd.h 2018-09-24 15:14:55.678081186 +0200
|
|
|
|
+++ mcelog-1.60/amd.h 2018-09-24 15:15:05.902689347 +0200
|
2014-05-16 17:58:42 +02:00
|
|
|
@@ -1,6 +1,25 @@
|
|
|
|
+#include <stdbool.h>
|
|
|
|
+
|
|
|
|
char *k8_bank_name(unsigned num);
|
|
|
|
void decode_amd_mc(enum cputype, struct mce *mce, int *ismemerr);
|
|
|
|
-int mce_filter_k8(struct mce *m);
|
|
|
|
+int mce_filter_amd(struct mce *m);
|
|
|
|
+enum cputype select_amd_cputype(u32 family);
|
|
|
|
+
|
|
|
|
+enum amdcpu {
|
|
|
|
+ AMD_K8 = 0,
|
|
|
|
+ AMD_F10H,
|
|
|
|
+ AMD_F11H,
|
|
|
|
+ AMD_F14H,
|
|
|
|
+ AMD_F15H,
|
|
|
|
+ AMD_F16H,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+struct amd_decoder_ops {
|
|
|
|
+ enum amdcpu cpu;
|
|
|
|
+ bool (*mc0_mce)(u16, u8);
|
|
|
|
+ bool (*mc1_mce)(u16, u8);
|
|
|
|
+ bool (*mc2_mce)(u16, u8);
|
|
|
|
+};
|
|
|
|
|
|
|
|
#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
|
|
|
|
#define K8_MCE_THRESHOLD_TOP (K8_MCE_THRESHOLD_BASE + 6 * 9)
|
2016-05-09 16:33:31 +02:00
|
|
|
@@ -10,6 +29,8 @@ int mce_filter_k8(struct mce *m);
|
2014-05-16 17:58:42 +02:00
|
|
|
#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
|
|
|
|
#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
|
|
|
|
|
|
|
|
+#define BIT_64(n) (1ULL << (n))
|
|
|
|
+
|
|
|
|
#define EC(x) ((x) & 0xffff)
|
|
|
|
#define XEC(x, mask) (((x) >> 16) & mask)
|
|
|
|
|
2016-05-09 16:33:31 +02:00
|
|
|
@@ -22,23 +43,20 @@ int mce_filter_k8(struct mce *m);
|
2014-05-16 17:58:42 +02:00
|
|
|
#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
|
|
|
|
|
|
|
|
#define TT(x) (((x) >> 2) & 0x3)
|
|
|
|
-#define TT_MSG(x) tt_msgs[TT(x)]
|
|
|
|
+#define TT_MSG(x) transaction[TT(x)]
|
|
|
|
#define II(x) (((x) >> 2) & 0x3)
|
|
|
|
-#define II_MSG(x) ii_msgs[II(x)]
|
|
|
|
+#define II_MSG(x) memoryio[II(x)]
|
|
|
|
#define LL(x) ((x) & 0x3)
|
|
|
|
-#define LL_MSG(x) ll_msgs[LL(x)]
|
|
|
|
+#define LL_MSG(x) cachelevel[LL(x)]
|
|
|
|
#define TO(x) (((x) >> 8) & 0x1)
|
|
|
|
-#define TO_MSG(x) to_msgs[TO(x)]
|
|
|
|
+#define TO_MSG(x) timeout[TO(x)]
|
|
|
|
#define PP(x) (((x) >> 9) & 0x3)
|
|
|
|
-#define PP_MSG(x) pp_msgs[PP(x)]
|
|
|
|
+#define PP_MSG(x) partproc[PP(x)]
|
|
|
|
#define UU(x) (((x) >> 8) & 0x3)
|
|
|
|
#define UU_MSG(x) uu_msgs[UU(x)]
|
|
|
|
|
|
|
|
#define R4(x) (((x) >> 4) & 0xf)
|
|
|
|
-#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
|
|
|
|
-
|
|
|
|
-#define CASE_AMD_CPUS \
|
|
|
|
- case CPU_K8
|
|
|
|
+#define R4_MSG(x) ((R4(x) < 9) ? memtrans[R4(x)] : "Wrong R4!")
|
|
|
|
|
|
|
|
enum tt_ids {
|
|
|
|
TT_INSTR = 0,
|
2016-05-09 16:33:31 +02:00
|
|
|
@@ -72,3 +90,7 @@ enum rrrr_ids {
|
2014-05-16 17:58:42 +02:00
|
|
|
R4_EVICT,
|
|
|
|
R4_SNOOP,
|
|
|
|
};
|
|
|
|
+
|
|
|
|
+#define CASE_AMD_CPUS \
|
|
|
|
+ case CPU_K8: \
|
|
|
|
+ case CPU_F10H
|
2018-09-24 15:47:13 +02:00
|
|
|
Index: mcelog-1.60/mcelog.h
|
2014-05-16 17:58:42 +02:00
|
|
|
===================================================================
|
2018-09-24 15:47:13 +02:00
|
|
|
--- mcelog-1.60.orig/mcelog.h 2018-09-24 15:14:09.599340401 +0200
|
|
|
|
+++ mcelog-1.60/mcelog.h 2018-09-24 15:15:05.902689347 +0200
|
|
|
|
@@ -117,6 +117,7 @@ enum cputype {
|
2014-05-16 17:58:42 +02:00
|
|
|
CPU_P6OLD,
|
|
|
|
CPU_CORE2, /* 65nm and 45nm */
|
|
|
|
CPU_K8,
|
|
|
|
+ CPU_F10H,
|
|
|
|
CPU_P4,
|
|
|
|
CPU_NEHALEM,
|
|
|
|
CPU_DUNNINGTON,
|
2018-09-24 15:47:13 +02:00
|
|
|
Index: mcelog-1.60/mcelog.c
|
2014-05-16 17:58:42 +02:00
|
|
|
===================================================================
|
2018-09-24 15:47:13 +02:00
|
|
|
--- mcelog-1.60.orig/mcelog.c 2018-09-24 15:14:18.775886227 +0200
|
|
|
|
+++ mcelog-1.60/mcelog.c 2018-09-24 15:15:05.906689585 +0200
|
|
|
|
@@ -147,19 +147,20 @@ static void resolveaddr(unsigned long lo
|
2014-05-16 17:58:42 +02:00
|
|
|
|
|
|
|
static int mce_filter(struct mce *m, unsigned recordlen)
|
|
|
|
{
|
|
|
|
- if (!filter_bogus)
|
|
|
|
+ if (!filter_bogus)
|
|
|
|
return 1;
|
|
|
|
+
|
|
|
|
/* Filter out known broken MCEs */
|
|
|
|
switch (cputype) {
|
|
|
|
- case CPU_K8:
|
|
|
|
- return mce_filter_k8(m);
|
|
|
|
+ CASE_AMD_CPUS:
|
|
|
|
+ return mce_filter_amd(m);
|
|
|
|
/* add more buggy CPUs here */
|
|
|
|
CASE_INTEL_CPUS:
|
|
|
|
return mce_filter_intel(m, recordlen);
|
|
|
|
default:
|
|
|
|
case CPU_GENERIC:
|
|
|
|
return 1;
|
|
|
|
- }
|
|
|
|
+ }
|
|
|
|
}
|
|
|
|
|
|
|
|
static void print_tsc(int cpunum, __u64 tsc, unsigned long time)
|
2018-09-24 15:47:13 +02:00
|
|
|
@@ -226,6 +227,7 @@ static char *cputype_name[] = {
|
2014-05-16 17:58:42 +02:00
|
|
|
[CPU_P6OLD] = "Intel PPro/P2/P3/old Xeon",
|
|
|
|
[CPU_CORE2] = "Intel Core", /* 65nm and 45nm */
|
|
|
|
[CPU_K8] = "AMD K8 and derivates",
|
|
|
|
+ [CPU_F10H] = "AMD Greyhound",
|
|
|
|
[CPU_P4] = "Intel P4",
|
|
|
|
[CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")",
|
|
|
|
[CPU_DUNNINGTON] = "Intel Xeon 7400 series",
|
2018-09-24 15:47:13 +02:00
|
|
|
@@ -255,6 +257,7 @@ static struct config_choice cpu_choices[
|
2014-05-16 17:58:42 +02:00
|
|
|
{ "p6old", CPU_P6OLD },
|
|
|
|
{ "core2", CPU_CORE2 },
|
|
|
|
{ "k8", CPU_K8 },
|
|
|
|
+ { "f10h", CPU_F10H },
|
|
|
|
{ "p4", CPU_P4 },
|
|
|
|
{ "dunnington", CPU_DUNNINGTON },
|
|
|
|
{ "xeon74xx", CPU_DUNNINGTON },
|
2018-09-24 15:47:13 +02:00
|
|
|
@@ -366,9 +369,7 @@ static enum cputype setup_cpuid(u32 cpuv
|
2014-05-16 17:58:42 +02:00
|
|
|
case X86_VENDOR_INTEL:
|
|
|
|
return select_intel_cputype(family, model);
|
|
|
|
case X86_VENDOR_AMD:
|
|
|
|
- if (family >= 15 && family <= 17)
|
|
|
|
- return CPU_K8;
|
|
|
|
- /* FALL THROUGH */
|
|
|
|
+ return select_amd_cputype(family);
|
|
|
|
default:
|
2016-12-17 14:05:01 +01:00
|
|
|
Eprintf("Unknown CPU type vendor %u family %u model %u",
|
2014-05-16 17:58:42 +02:00
|
|
|
cpuvendor, family, model);
|
2018-09-24 15:47:13 +02:00
|
|
|
@@ -551,14 +552,9 @@ int is_cpu_supported(void)
|
2014-05-16 17:58:42 +02:00
|
|
|
|
|
|
|
}
|
|
|
|
if (seen == ALL) {
|
|
|
|
- if (!strcmp(vendor,"AuthenticAMD")) {
|
|
|
|
- if (family == 15) {
|
|
|
|
- cputype = CPU_K8;
|
|
|
|
- } else if (family >= 16) {
|
2017-01-18 13:28:33 +01:00
|
|
|
- Eprintf("ERROR: AMD Processor family %d: mcelog does not support this processor. Please use the edac_mce_amd module instead.\n", family);
|
2014-05-16 17:58:42 +02:00
|
|
|
- return 0;
|
|
|
|
- }
|
|
|
|
- } else if (!strcmp(vendor,"GenuineIntel"))
|
|
|
|
+ if (!strcmp(vendor,"AuthenticAMD"))
|
|
|
|
+ cputype = select_amd_cputype(family);
|
|
|
|
+ else if (!strcmp(vendor,"GenuineIntel"))
|
|
|
|
cputype = select_intel_cputype(family, model);
|
|
|
|
/* Add checks for other CPUs here */
|
|
|
|
} else {
|