b5ebe45a82
OBS-URL: https://build.opensuse.org/request/show/728979 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=75
654 lines
18 KiB
Diff
654 lines
18 KiB
Diff
From 4388981628ad9e2daba956210284017e1133cb99 Mon Sep 17 00:00:00 2001
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From: Borislav Petkov <bp@suse.de>
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Date: Wed, 7 May 2014 22:41:15 +0200
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Subject: [PATCH] Start consolidating AMD-specific stuff
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... in order to concentrate decoding for all families in amd.[ch]. Pass
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down cpu type in decode_amd_mc.
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Signed-off-by: Borislav Petkov <bp@suse.de>
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---
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Makefile | 2 +-
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k8.c => amd.c | 9 +++++----
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k8.h => amd.h | 5 ++++-
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mcelog.c | 8 ++++----
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4 files changed, 14 insertions(+), 10 deletions(-)
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rename k8.c => amd.c (97%)
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rename k8.h => amd.h (79%)
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--- mcelog-1.64+git20190805.e53631f.orig/Makefile 2019-09-06 14:06:56.229228424 +0200
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+++ mcelog-1.64+git20190805.e53631f/Makefile 2019-09-06 14:09:39.241237130 +0200
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@@ -30,7 +30,7 @@
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.PHONY: install clean depend FORCE
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-OBJ := p4.o k8.o mcelog.o dmi.o tsc.o core2.o bitfield.o intel.o \
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+OBJ := p4.o amd.o mcelog.o dmi.o tsc.o core2.o bitfield.o intel.o \
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nehalem.o dunnington.o tulsa.o config.o memutil.o msg.o \
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eventloop.o leaky-bucket.o memdb.o server.o trigger.o \
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client.o cache.o sysfs.o yellow.o page.o rbtree.o \
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--- mcelog-1.64+git20190805.e53631f.orig/k8.c 2019-09-06 14:06:51.681228181 +0200
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+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
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@@ -1,281 +0,0 @@
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-/* Based on K8 decoding code written for the 2.4 kernel by Andi Kleen and
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- * Eric Morton. Hacked and extended for mcelog by AK.
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- *
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- * Original copyright:
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- * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
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- * Additional K8 decoding and simplification Copyright 2003 Eric Morton, Newisys Inc
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- * K8 threshold counters decoding Copyright 2005,2006 Jacob Shin, AMD Inc.
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- *
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- * Subject to the GNU General Public License
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- */
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-
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-#include <stdio.h>
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-#include "mcelog.h"
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-#include "k8.h"
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-
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-static char *k8bank[] = {
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- "data cache",
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- "instruction cache",
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- "bus unit",
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- "load/store unit",
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- "northbridge",
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- "fixed-issue reoder"
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-};
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-static char *transaction[] = {
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- "instruction", "data", "generic", "reserved"
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-};
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-static char *cachelevel[] = {
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- "0", "1", "2", "generic"
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-};
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-static char *memtrans[] = {
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- "generic error", "generic read", "generic write", "data read",
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- "data write", "instruction fetch", "prefetch", "evict", "snoop",
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- "?", "?", "?", "?", "?", "?", "?"
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-};
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-static char *partproc[] = {
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- "local node origin", "local node response",
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- "local node observed", "generic participation"
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-};
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-static char *timeout[] = {
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- "request didn't time out",
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- "request timed out"
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-};
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-static char *memoryio[] = {
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- "memory", "res.", "i/o", "generic"
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-};
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-static char *nbextendederr[] = {
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- "RAM ECC error",
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- "CRC error",
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- "Sync error",
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- "Master abort",
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- "Target abort",
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- "GART error",
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- "RMW error",
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- "Watchdog error",
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- "RAM Chipkill ECC error",
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- "DEV Error",
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- "Link Data Error",
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- "Link Protocol Error",
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- "NB Array Error",
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- "DRAM Parity Error",
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- "Link Retry",
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- "Tablew Walk Data Error",
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- "L3 Cache Data Error",
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- "L3 Cache Tag Error",
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- "L3 Cache LRU Error"
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-};
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-static char *highbits[32] = {
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- [31] = "valid",
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- [30] = "error overflow (multiple errors)",
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- [29] = "error uncorrected",
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- [28] = "error enable",
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- [27] = "misc error valid",
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- [26] = "error address valid",
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- [25] = "processor context corrupt",
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- [24] = "res24",
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- [23] = "res23",
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- /* 22-15 ecc syndrome bits */
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- [14] = "corrected ecc error",
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- [13] = "uncorrected ecc error",
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- [12] = "res12",
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- [11] = "L3 subcache in error bit 1",
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- [10] = "L3 subcache in error bit 0",
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- [9] = "sublink or DRAM channel",
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- [8] = "error found by scrub",
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- /* 7-4 ht link number of error */
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- [3] = "err cpu3",
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- [2] = "err cpu2",
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- [1] = "err cpu1",
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- [0] = "err cpu0",
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-};
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-static char *k8threshold[] = {
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- [0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknown threshold counter",
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- [K8_MCELOG_THRESHOLD_DRAM_ECC] = "MC4_MISC0 DRAM threshold",
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- [K8_MCELOG_THRESHOLD_LINK] = "MC4_MISC1 Link threshold",
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- [K8_MCELOG_THRESHOLD_L3_CACHE] = "MC4_MISC2 L3 Cache threshold",
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- [K8_MCELOG_THRESHOLD_FBDIMM] = "MC4_MISC3 FBDIMM threshold",
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- [K8_MCELOG_THRESHOLD_FBDIMM + 1 ...
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- K8_MCE_THRESHOLD_TOP - K8_MCE_THRESHOLD_BASE - 1] =
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- "Unknown threshold counter",
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-};
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-
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-
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-static void decode_k8_generic_errcode(u64 status)
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-{
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- unsigned short errcode = status & 0xffff;
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- int i;
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-
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- for (i=0; i<32; i++) {
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- if (i==31 || i==28 || i==26)
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- continue;
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- if (highbits[i] && (status & (1ULL<<(i+32)))) {
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- Wprintf( " bit%d = %s\n", i+32, highbits[i]);
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- }
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- }
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-
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- if ((errcode & 0xFFF0) == 0x0010) {
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- Wprintf( " TLB error '%s transaction, level %s'\n",
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- transaction[(errcode >> 2) & 3],
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- cachelevel[errcode & 3]);
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- }
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- else if ((errcode & 0xFF00) == 0x0100) {
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- Wprintf( " memory/cache error '%s mem transaction, %s transaction, level %s'\n",
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- memtrans[(errcode >> 4) & 0xf],
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- transaction[(errcode >> 2) & 3],
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- cachelevel[errcode & 3]);
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- }
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- else if ((errcode & 0xF800) == 0x0800) {
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- Wprintf( " bus error '%s, %s\n %s mem transaction\n %s access, level %s'\n",
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- partproc[(errcode >> 9) & 0x3],
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- timeout[(errcode >> 8) & 1],
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- memtrans[(errcode >> 4) & 0xf],
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- memoryio[(errcode >> 2) & 0x3],
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- cachelevel[(errcode & 0x3)]);
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- }
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-}
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-
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-static void decode_k8_dc_mc(u64 status, int *err)
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-{
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- unsigned short exterrcode = (status >> 16) & 0x0f;
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- unsigned short errcode = status & 0xffff;
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-
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- if(status&(3ULL<<45)) {
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- Wprintf( " Data cache ECC error (syndrome %x)",
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- (u32) (status >> 47) & 0xff);
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- if(status&(1ULL<<40)) {
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- Wprintf(" found by scrubber");
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- }
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- Wprintf("\n");
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- }
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-
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- if ((errcode & 0xFFF0) == 0x0010) {
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- Wprintf( " TLB parity error in %s array\n",
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- (exterrcode == 0) ? "physical" : "virtual");
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- }
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-
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- decode_k8_generic_errcode(status);
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-}
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-
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-static void decode_k8_ic_mc(u64 status, int *err)
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-{
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- unsigned short exterrcode = (status >> 16) & 0x0f;
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- unsigned short errcode = status & 0xffff;
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-
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- if(status&(3ULL<<45)) {
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- Wprintf(" Instruction cache ECC error\n");
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- }
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-
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- if ((errcode & 0xFFF0) == 0x0010) {
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- Wprintf(" TLB parity error in %s array\n",
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- (exterrcode == 0) ? "physical" : "virtual");
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- }
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-
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- decode_k8_generic_errcode(status);
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-}
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-
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-static void decode_k8_bu_mc(u64 status, int *err)
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-{
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- unsigned short exterrcode = (status >> 16) & 0x0f;
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-
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- if(status&(3ULL<<45)) {
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- Wprintf(" L2 cache ECC error\n");
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- }
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-
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- Wprintf(" %s array error\n",
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- (exterrcode == 0) ? "Bus or cache" : "Cache tag");
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-
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- decode_k8_generic_errcode(status);
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-}
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-
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-static void decode_k8_ls_mc(u64 status, int *err)
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-{
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- decode_k8_generic_errcode(status);
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-}
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-
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-static void decode_k8_nb_mc(u64 status, int *memerr)
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-{
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- unsigned short exterrcode = (status >> 16) & 0x0f;
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-
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- Wprintf(" Northbridge %s\n", nbextendederr[exterrcode]);
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-
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- switch (exterrcode) {
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- case 0:
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- *memerr = 1;
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- Wprintf(" ECC syndrome = %x\n",
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- (u32) (status >> 47) & 0xff);
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- break;
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- case 8:
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- *memerr = 1;
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- Wprintf(" Chipkill ECC syndrome = %x\n",
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- (u32) ((((status >> 24) & 0xff) << 8) | ((status >> 47) & 0xff)));
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- break;
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- case 1:
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- case 2:
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- case 3:
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- case 4:
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- case 6:
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- Wprintf(" link number = %x\n",
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- (u32) (status >> 36) & 0xf);
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- break;
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- }
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-
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- decode_k8_generic_errcode(status);
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-}
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-
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-static void decode_k8_fr_mc(u64 status, int *err)
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-{
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- decode_k8_generic_errcode(status);
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-}
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-
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-static void decode_k8_threshold(u64 misc)
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-{
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- if (misc & MCI_THRESHOLD_OVER)
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- Wprintf(" Threshold error count overflow\n");
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-}
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-
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-typedef void (*decoder_t)(u64, int *ismemerr);
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-
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-static decoder_t decoders[] = {
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- [0] = decode_k8_dc_mc,
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- [1] = decode_k8_ic_mc,
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- [2] = decode_k8_bu_mc,
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- [3] = decode_k8_ls_mc,
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- [4] = decode_k8_nb_mc,
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- [5] = decode_k8_fr_mc,
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-};
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-
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-void decode_k8_mc(struct mce *mce, int *ismemerr)
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-{
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- if (mce->bank < NELE(decoders))
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- decoders[mce->bank](mce->status, ismemerr);
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- else if (mce->bank >= K8_MCE_THRESHOLD_BASE &&
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- mce->bank < K8_MCE_THRESHOLD_TOP)
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- decode_k8_threshold(mce->misc);
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- else
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- Wprintf(" no decoder for unknown bank %u\n", mce->bank);
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-}
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-
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-char *k8_bank_name(unsigned num)
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-{
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- static char buf[64];
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- char *s = "unknown";
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- if (num < NELE(k8bank))
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- s = k8bank[num];
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- else if (num >= K8_MCE_THRESHOLD_BASE &&
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- num < K8_MCE_THRESHOLD_TOP)
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- s = k8threshold[num - K8_MCE_THRESHOLD_BASE];
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- buf[sizeof(buf)-1] = 0;
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- snprintf(buf, sizeof(buf) - 1, "%u %s", num, s);
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- return buf;
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-}
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-
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-int mce_filter_k8(struct mce *m)
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-{
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- /* Filter out GART errors */
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- if (m->bank == 4) {
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- unsigned short exterrcode = (m->status >> 16) & 0x0f;
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- if (exterrcode == 5 && (m->status & (1ULL<<61)))
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- return 0;
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- }
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- return 1;
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-}
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ mcelog-1.64+git20190805.e53631f/amd.c 2019-09-06 14:09:39.241237130 +0200
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@@ -0,0 +1,282 @@
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+/* Based on K8 decoding code written for the 2.4 kernel by Andi Kleen and
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+ * Eric Morton. Hacked and extended for mcelog by AK.
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+ * Extended to support all AMD families by Borislav Petkov, SUSE Labs.
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+ *
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+ * Original copyright:
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+ * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
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+ * Additional K8 decoding and simplification Copyright 2003 Eric Morton, Newisys Inc
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+ * K8 threshold counters decoding Copyright 2005,2006 Jacob Shin, AMD Inc.
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+ *
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+ * Subject to the GNU General Public License
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+ */
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+
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+#include <stdio.h>
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+#include "mcelog.h"
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+#include "amd.h"
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+
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+static char *k8bank[] = {
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+ "data cache",
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+ "instruction cache",
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+ "bus unit",
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+ "load/store unit",
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+ "northbridge",
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+ "fixed-issue reoder"
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+};
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+static char *transaction[] = {
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+ "instruction", "data", "generic", "reserved"
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+};
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+static char *cachelevel[] = {
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+ "0", "1", "2", "generic"
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+};
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+static char *memtrans[] = {
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+ "generic error", "generic read", "generic write", "data read",
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+ "data write", "instruction fetch", "prefetch", "evict", "snoop",
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+ "?", "?", "?", "?", "?", "?", "?"
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+};
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+static char *partproc[] = {
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+ "local node origin", "local node response",
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+ "local node observed", "generic participation"
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+};
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+static char *timeout[] = {
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+ "request didn't time out",
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+ "request timed out"
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+};
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+static char *memoryio[] = {
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+ "memory", "res.", "i/o", "generic"
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+};
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+static char *nbextendederr[] = {
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+ "RAM ECC error",
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+ "CRC error",
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+ "Sync error",
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+ "Master abort",
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+ "Target abort",
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+ "GART error",
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+ "RMW error",
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+ "Watchdog error",
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+ "RAM Chipkill ECC error",
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+ "DEV Error",
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+ "Link Data Error",
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+ "Link Protocol Error",
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+ "NB Array Error",
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+ "DRAM Parity Error",
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+ "Link Retry",
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+ "Tablew Walk Data Error",
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+ "L3 Cache Data Error",
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+ "L3 Cache Tag Error",
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+ "L3 Cache LRU Error"
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+};
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+static char *highbits[32] = {
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+ [31] = "valid",
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+ [30] = "error overflow (multiple errors)",
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+ [29] = "error uncorrected",
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+ [28] = "error enable",
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+ [27] = "misc error valid",
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+ [26] = "error address valid",
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+ [25] = "processor context corrupt",
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+ [24] = "res24",
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+ [23] = "res23",
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+ /* 22-15 ecc syndrome bits */
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+ [14] = "corrected ecc error",
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+ [13] = "uncorrected ecc error",
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+ [12] = "res12",
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+ [11] = "L3 subcache in error bit 1",
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+ [10] = "L3 subcache in error bit 0",
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+ [9] = "sublink or DRAM channel",
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+ [8] = "error found by scrub",
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+ /* 7-4 ht link number of error */
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+ [3] = "err cpu3",
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+ [2] = "err cpu2",
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+ [1] = "err cpu1",
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+ [0] = "err cpu0",
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+};
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+static char *k8threshold[] = {
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+ [0 ... K8_MCELOG_THRESHOLD_DRAM_ECC - 1] = "Unknow threshold counter",
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+ [K8_MCELOG_THRESHOLD_DRAM_ECC] = "MC4_MISC0 DRAM threshold",
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+ [K8_MCELOG_THRESHOLD_LINK] = "MC4_MISC1 Link threshold",
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+ [K8_MCELOG_THRESHOLD_L3_CACHE] = "MC4_MISC2 L3 Cache threshold",
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+ [K8_MCELOG_THRESHOLD_FBDIMM] = "MC4_MISC3 FBDIMM threshold",
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+ [K8_MCELOG_THRESHOLD_FBDIMM + 1 ...
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+ K8_MCE_THRESHOLD_TOP - K8_MCE_THRESHOLD_BASE - 1] =
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+ "Unknown threshold counter",
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+};
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+
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+
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+static void decode_k8_generic_errcode(u64 status)
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+{
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+ unsigned short errcode = status & 0xffff;
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+ int i;
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+
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+ for (i=0; i<32; i++) {
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+ if (i==31 || i==28 || i==26)
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+ continue;
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+ if (highbits[i] && (status & (1ULL<<(i+32)))) {
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+ Wprintf( " bit%d = %s\n", i+32, highbits[i]);
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+ }
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+ }
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+
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+ if ((errcode & 0xFFF0) == 0x0010) {
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+ Wprintf( " TLB error '%s transaction, level %s'\n",
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+ transaction[(errcode >> 2) & 3],
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+ cachelevel[errcode & 3]);
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+ }
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+ else if ((errcode & 0xFF00) == 0x0100) {
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+ Wprintf( " memory/cache error '%s mem transaction, %s transaction, level %s'\n",
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+ memtrans[(errcode >> 4) & 0xf],
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+ transaction[(errcode >> 2) & 3],
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+ cachelevel[errcode & 3]);
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+ }
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+ else if ((errcode & 0xF800) == 0x0800) {
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+ Wprintf( " bus error '%s, %s\n %s mem transaction\n %s access, level %s'\n",
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|
+ partproc[(errcode >> 9) & 0x3],
|
|
+ timeout[(errcode >> 8) & 1],
|
|
+ memtrans[(errcode >> 4) & 0xf],
|
|
+ memoryio[(errcode >> 2) & 0x3],
|
|
+ cachelevel[(errcode & 0x3)]);
|
|
+ }
|
|
+}
|
|
+
|
|
+static void decode_k8_dc_mc(u64 status, int *err)
|
|
+{
|
|
+ unsigned short exterrcode = (status >> 16) & 0x0f;
|
|
+ unsigned short errcode = status & 0xffff;
|
|
+
|
|
+ if(status&(3ULL<<45)) {
|
|
+ Wprintf( " Data cache ECC error (syndrome %x)",
|
|
+ (u32) (status >> 47) & 0xff);
|
|
+ if(status&(1ULL<<40)) {
|
|
+ Wprintf(" found by scrubber");
|
|
+ }
|
|
+ Wprintf("\n");
|
|
+ }
|
|
+
|
|
+ if ((errcode & 0xFFF0) == 0x0010) {
|
|
+ Wprintf( " TLB parity error in %s array\n",
|
|
+ (exterrcode == 0) ? "physical" : "virtual");
|
|
+ }
|
|
+
|
|
+ decode_k8_generic_errcode(status);
|
|
+}
|
|
+
|
|
+static void decode_k8_ic_mc(u64 status, int *err)
|
|
+{
|
|
+ unsigned short exterrcode = (status >> 16) & 0x0f;
|
|
+ unsigned short errcode = status & 0xffff;
|
|
+
|
|
+ if(status&(3ULL<<45)) {
|
|
+ Wprintf(" Instruction cache ECC error\n");
|
|
+ }
|
|
+
|
|
+ if ((errcode & 0xFFF0) == 0x0010) {
|
|
+ Wprintf(" TLB parity error in %s array\n",
|
|
+ (exterrcode == 0) ? "physical" : "virtual");
|
|
+ }
|
|
+
|
|
+ decode_k8_generic_errcode(status);
|
|
+}
|
|
+
|
|
+static void decode_k8_bu_mc(u64 status, int *err)
|
|
+{
|
|
+ unsigned short exterrcode = (status >> 16) & 0x0f;
|
|
+
|
|
+ if(status&(3ULL<<45)) {
|
|
+ Wprintf(" L2 cache ECC error\n");
|
|
+ }
|
|
+
|
|
+ Wprintf(" %s array error\n",
|
|
+ (exterrcode == 0) ? "Bus or cache" : "Cache tag");
|
|
+
|
|
+ decode_k8_generic_errcode(status);
|
|
+}
|
|
+
|
|
+static void decode_k8_ls_mc(u64 status, int *err)
|
|
+{
|
|
+ decode_k8_generic_errcode(status);
|
|
+}
|
|
+
|
|
+static void decode_k8_nb_mc(u64 status, int *memerr)
|
|
+{
|
|
+ unsigned short exterrcode = (status >> 16) & 0x0f;
|
|
+
|
|
+ Wprintf(" Northbridge %s\n", nbextendederr[exterrcode]);
|
|
+
|
|
+ switch (exterrcode) {
|
|
+ case 0:
|
|
+ *memerr = 1;
|
|
+ Wprintf(" ECC syndrome = %x\n",
|
|
+ (u32) (status >> 47) & 0xff);
|
|
+ break;
|
|
+ case 8:
|
|
+ *memerr = 1;
|
|
+ Wprintf(" Chipkill ECC syndrome = %x\n",
|
|
+ (u32) ((((status >> 24) & 0xff) << 8) | ((status >> 47) & 0xff)));
|
|
+ break;
|
|
+ case 1:
|
|
+ case 2:
|
|
+ case 3:
|
|
+ case 4:
|
|
+ case 6:
|
|
+ Wprintf(" link number = %x\n",
|
|
+ (u32) (status >> 36) & 0xf);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ decode_k8_generic_errcode(status);
|
|
+}
|
|
+
|
|
+static void decode_k8_fr_mc(u64 status, int *err)
|
|
+{
|
|
+ decode_k8_generic_errcode(status);
|
|
+}
|
|
+
|
|
+static void decode_k8_threshold(u64 misc)
|
|
+{
|
|
+ if (misc & MCI_THRESHOLD_OVER)
|
|
+ Wprintf(" Threshold error count overflow\n");
|
|
+}
|
|
+
|
|
+typedef void (*decoder_t)(u64, int *ismemerr);
|
|
+
|
|
+static decoder_t decoders[] = {
|
|
+ [0] = decode_k8_dc_mc,
|
|
+ [1] = decode_k8_ic_mc,
|
|
+ [2] = decode_k8_bu_mc,
|
|
+ [3] = decode_k8_ls_mc,
|
|
+ [4] = decode_k8_nb_mc,
|
|
+ [5] = decode_k8_fr_mc,
|
|
+};
|
|
+
|
|
+void decode_amd_mc(enum cputype cpu, struct mce *mce, int *ismemerr)
|
|
+{
|
|
+ if (mce->bank < NELE(decoders))
|
|
+ decoders[mce->bank](mce->status, ismemerr);
|
|
+ else if (mce->bank >= K8_MCE_THRESHOLD_BASE &&
|
|
+ mce->bank < K8_MCE_THRESHOLD_TOP)
|
|
+ decode_k8_threshold(mce->misc);
|
|
+ else
|
|
+ Wprintf(" no decoder for unknown bank %u\n", mce->bank);
|
|
+}
|
|
+
|
|
+char *k8_bank_name(unsigned num)
|
|
+{
|
|
+ static char buf[64];
|
|
+ char *s = "unknown";
|
|
+ if (num < NELE(k8bank))
|
|
+ s = k8bank[num];
|
|
+ else if (num >= K8_MCE_THRESHOLD_BASE &&
|
|
+ num < K8_MCE_THRESHOLD_TOP)
|
|
+ s = k8threshold[num - K8_MCE_THRESHOLD_BASE];
|
|
+ buf[sizeof(buf)-1] = 0;
|
|
+ snprintf(buf, sizeof(buf) - 1, "%u %s", num, s);
|
|
+ return buf;
|
|
+}
|
|
+
|
|
+int mce_filter_k8(struct mce *m)
|
|
+{
|
|
+ /* Filter out GART errors */
|
|
+ if (m->bank == 4) {
|
|
+ unsigned short exterrcode = (m->status >> 16) & 0x0f;
|
|
+ if (exterrcode == 5 && (m->status & (1ULL<<61)))
|
|
+ return 0;
|
|
+ }
|
|
+ return 1;
|
|
+}
|
|
--- mcelog-1.64+git20190805.e53631f.orig/k8.h 2019-09-06 14:06:51.681228181 +0200
|
|
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
|
|
@@ -1,11 +0,0 @@
|
|
-char *k8_bank_name(unsigned num);
|
|
-void decode_k8_mc(struct mce *mce, int *ismemerr);
|
|
-int mce_filter_k8(struct mce *m);
|
|
-
|
|
-#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
|
|
-#define K8_MCE_THRESHOLD_TOP (K8_MCE_THRESHOLD_BASE + 6 * 9)
|
|
-
|
|
-#define K8_MCELOG_THRESHOLD_DRAM_ECC (4 * 9 + 0)
|
|
-#define K8_MCELOG_THRESHOLD_LINK (4 * 9 + 1)
|
|
-#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
|
|
-#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
|
|
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
|
|
+++ mcelog-1.64+git20190805.e53631f/amd.h 2019-09-06 14:09:39.245237130 +0200
|
|
@@ -0,0 +1,14 @@
|
|
+char *k8_bank_name(unsigned num);
|
|
+void decode_amd_mc(enum cputype, struct mce *mce, int *ismemerr);
|
|
+int mce_filter_k8(struct mce *m);
|
|
+
|
|
+#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
|
|
+#define K8_MCE_THRESHOLD_TOP (K8_MCE_THRESHOLD_BASE + 6 * 9)
|
|
+
|
|
+#define K8_MCELOG_THRESHOLD_DRAM_ECC (4 * 9 + 0)
|
|
+#define K8_MCELOG_THRESHOLD_LINK (4 * 9 + 1)
|
|
+#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
|
|
+#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
|
|
+
|
|
+#define CASE_AMD_CPUS \
|
|
+ case CPU_K8
|
|
--- mcelog-1.64+git20190805.e53631f.orig/mcelog.c 2019-09-06 14:06:56.229228424 +0200
|
|
+++ mcelog-1.64+git20190805.e53631f/mcelog.c 2019-09-06 14:09:39.245237130 +0200
|
|
@@ -41,7 +41,7 @@
|
|
#include <fnmatch.h>
|
|
#include "mcelog.h"
|
|
#include "paths.h"
|
|
-#include "k8.h"
|
|
+#include "amd.h"
|
|
#include "intel.h"
|
|
#include "p4.h"
|
|
#include "dmi.h"
|
|
@@ -430,9 +430,9 @@
|
|
time_t t = m->time;
|
|
Wprintf("TIME %llu %s", m->time, ctime(&t));
|
|
}
|
|
- switch (cputype) {
|
|
- case CPU_K8:
|
|
- decode_k8_mc(m, &ismemerr);
|
|
+ switch (cputype) {
|
|
+ CASE_AMD_CPUS:
|
|
+ decode_amd_mc(cputype, m, &ismemerr);
|
|
break;
|
|
CASE_INTEL_CPUS:
|
|
decode_intel_mc(m, cputype, &ismemerr, recordlen);
|