1c1607eb66
- Add mce decoding support for latest AMD CPUs (bnc#871881). - Implementation done by Borislav Petkov <bp@suse.de> * Add patches/Start-consolidating-AMD-specific-stuff.patch * Add add-defines.patch * Add add-f10h-support.patch * Add add-f11h-support.patch * Add add-f12h-support.patch * Add add-f14h-support.patch * Add add-f15h-support.patch * Add add-f16h-support.patch OBS-URL: https://build.opensuse.org/request/show/234343 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=35
132 lines
3.2 KiB
Diff
132 lines
3.2 KiB
Diff
Add F16h decoding support
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Signed-off-by: Borislav Petkov <bp@suse.de>
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Index: mcelog-1.0.1/amd.c
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===================================================================
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--- mcelog-1.0.1.orig/amd.c
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+++ mcelog-1.0.1/amd.c
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@@ -200,6 +200,8 @@ enum cputype select_amd_cputype(u32 fami
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return CPU_F14H;
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case 0x15:
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return CPU_F15H;
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+ case 0x16:
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+ return CPU_F16H;
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default:
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break;
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}
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@@ -687,6 +689,47 @@ static bool f15h_mc2_mce(u16 ec, u8 xec)
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return ret;
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}
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+static bool f16h_mc2_mce(u16 ec, u8 xec)
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+{
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+ u8 r4 = R4(ec);
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+
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+ if (!MEM_ERROR(ec))
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+ return false;
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+
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+ switch (xec) {
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+ case 0x04 ... 0x05:
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+ Wprintf("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
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+ break;
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+
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+ case 0x09 ... 0x0b:
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+ case 0x0d ... 0x0f:
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+ Wprintf("ECC error in L2 tag (%s).\n",
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+ ((r4 == R4_GEN) ? "BankReq" :
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+ ((r4 == R4_SNOOP) ? "Prb" : "Fill")));
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+ break;
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+
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+ case 0x10 ... 0x19:
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+ case 0x1b:
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+ Wprintf("ECC error in L2 data array (%s).\n",
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+ (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" :
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+ ((r4 == R4_GEN) ? "Attr" :
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+ ((r4 == R4_EVICT) ? "Vict" : "Fill"))));
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+ break;
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+
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+ case 0x1c ... 0x1d:
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+ case 0x1f:
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+ Wprintf("Parity error in L2 attribute bits (%s).\n",
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+ ((r4 == R4_RD) ? "Hit" :
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+ ((r4 == R4_GEN) ? "Attr" : "Fill")));
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+ break;
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+
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+ default:
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+ return false;
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+ }
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+
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+ return true;
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+}
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+
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static void decode_mc2_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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u16 ec = EC(m->status);
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@@ -897,6 +940,12 @@ struct amd_decoder_ops fam_ops[] = {
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.mc1_mce = f15h_mc1_mce,
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.mc2_mce = f15h_mc2_mce,
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},
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+ [AMD_F16H] = {
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+ .cpu = AMD_F16H,
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+ .mc0_mce = cat_mc0_mce,
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+ .mc1_mce = cat_mc1_mce,
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+ .mc2_mce = f16h_mc2_mce,
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+ },
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};
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static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
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@@ -920,6 +969,10 @@ static void __decode_amd_mc(enum cputype
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xec_mask = 0x1f;
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ops = &fam_ops[AMD_F15H];
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break;
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+ case CPU_F16H:
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+ xec_mask = 0x1f;
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+ ops = &fam_ops[AMD_F16H];
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+ break;
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default:
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Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
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return;
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Index: mcelog-1.0.1/mcelog.h
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===================================================================
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--- mcelog-1.0.1.orig/mcelog.h
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+++ mcelog-1.0.1/mcelog.h
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@@ -112,6 +112,7 @@ enum cputype {
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CPU_F12H,
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CPU_F14H,
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CPU_F15H,
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+ CPU_F16H,
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CPU_P4,
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CPU_NEHALEM,
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CPU_DUNNINGTON,
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Index: mcelog-1.0.1/amd.h
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===================================================================
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--- mcelog-1.0.1.orig/amd.h
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+++ mcelog-1.0.1/amd.h
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@@ -98,4 +98,5 @@ enum rrrr_ids {
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case CPU_F11H: \
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case CPU_F12H: \
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case CPU_F14H: \
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- case CPU_F15H
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+ case CPU_F15H: \
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+ case CPU_F16H
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Index: mcelog-1.0.1/mcelog.c
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===================================================================
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--- mcelog-1.0.1.orig/mcelog.c
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+++ mcelog-1.0.1/mcelog.c
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@@ -227,6 +227,7 @@ static char *cputype_name[] = {
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[CPU_F12H] = "AMD Llano",
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[CPU_F14H] = "AMD Bobcat",
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[CPU_F15H] = "AMD Bulldozer",
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+ [CPU_F16H] = "AMD Jaguar",
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[CPU_P4] = "Intel P4",
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[CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")",
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[CPU_DUNNINGTON] = "Intel Xeon 7400 series",
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@@ -250,6 +251,7 @@ static struct config_choice cpu_choices[
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{ "f12h", CPU_F12H },
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{ "f14h", CPU_F14H },
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{ "f15h", CPU_F15H },
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+ { "f16h", CPU_F16H },
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{ "p4", CPU_P4 },
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{ "dunnington", CPU_DUNNINGTON },
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{ "xeon74xx", CPU_DUNNINGTON },
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