mcelog/add-f11h-support.patch
Thomas Renninger 69342a5d53 Accepting request 974669 from home:kodymo
- Update to version 181:
  * mcelog: Add support for Raptorlake
- Adopt patches to latest git version
M    Start-consolidating-AMD-specific-stuff.patch
M    add-f10h-support.patch
M    add-f11h-support.patch
M    add-f12h-support.patch
M    add-f14h-support.patch
M    add-f15h-support.patch
M    add-f16h-support.patch
M    email.patch
M    fix_setgroups_missing_call.patch
M    mcelog_invert_prefill_db_warning.patch
- Use Python3 shebang instead of python
A    python3_shebang
- Use Github URL

- Update to version 180:
  * Fix warnings in sysfs.c
  * mcelog: Change "DDR4" string to "DDR" for i10nm platforms
  * Fix logrotate syntax
  * remove outdated mcelog.conf.5 manual file
  * add furture print function for Python2
  * fix python errors in genconfig.py
  * fix the buf not freed in read_field
  * mcelog: Print warning for locked down kernel
  * mcelog: Handle sysfs files without length
  * Fix make test fail

OBS-URL: https://build.opensuse.org/request/show/974669
OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=99
2022-05-03 14:52:12 +00:00

107 lines
2.7 KiB
Diff

Add F11h decoding support
Signed-off-by: Borislav Petkov <bp@suse.de>
---
amd.c | 21 +++++++++++++++++++++
amd.h | 3 ++-
mcelog.c | 2 ++
mcelog.h | 1 +
4 files changed, 26 insertions(+), 1 deletion(-)
Index: mcelog-181/amd.c
===================================================================
--- mcelog-181.orig/amd.c
+++ mcelog-181/amd.c
@@ -155,6 +155,8 @@ enum cputype select_amd_cputype(u32 fami
return CPU_K8;
case 0x10:
return CPU_F10H;
+ case 0x11:
+ return CPU_F11H;
default:
break;
}
@@ -367,6 +369,16 @@ static bool f10h_mc0_mce(u16 ec, u8 xec)
return f12h_mc0_mce(ec, xec);
}
+static bool k8_mc0_mce(u16 ec, u8 xec)
+{
+ if (BUS_ERROR(ec)) {
+ Wprintf("during system linefill.\n");
+ return true;
+ }
+
+ return f10h_mc0_mce(ec, xec);
+}
+
static void decode_mc0_mce(struct amd_decoder_ops *ops, struct mce *m)
{
u16 ec = EC(m->status);
@@ -630,6 +642,12 @@ struct amd_decoder_ops fam_ops[] = {
.mc1_mce = k8_mc1_mce,
.mc2_mce = k8_mc2_mce,
},
+ [AMD_F11H] = {
+ .cpu = AMD_F11H,
+ .mc0_mce = k8_mc0_mce,
+ .mc1_mce = k8_mc1_mce,
+ .mc2_mce = k8_mc2_mce,
+ },
};
static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
@@ -640,6 +658,9 @@ static void __decode_amd_mc(enum cputype
case CPU_F10H:
ops = &fam_ops[AMD_F10H];
break;
+ case CPU_F11H:
+ ops = &fam_ops[AMD_F11H];
+ break;
default:
Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
return;
Index: mcelog-181/amd.h
===================================================================
--- mcelog-181.orig/amd.h
+++ mcelog-181/amd.h
@@ -93,4 +93,5 @@ enum rrrr_ids {
#define CASE_AMD_CPUS \
case CPU_K8: \
- case CPU_F10H
+ case CPU_F10H: \
+ case CPU_F11H
Index: mcelog-181/mcelog.c
===================================================================
--- mcelog-181.orig/mcelog.c
+++ mcelog-181/mcelog.c
@@ -230,6 +230,7 @@ static char *cputype_name[] = {
[CPU_CORE2] = "Intel Core", /* 65nm and 45nm */
[CPU_K8] = "AMD K8 and derivates",
[CPU_F10H] = "AMD Greyhound",
+ [CPU_F11H] = "AMD Griffin",
[CPU_P4] = "Intel P4",
[CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")",
[CPU_DUNNINGTON] = "Intel Xeon 7400 series",
@@ -271,6 +272,7 @@ static struct config_choice cpu_choices[
{ "core2", CPU_CORE2 },
{ "k8", CPU_K8 },
{ "f10h", CPU_F10H },
+ { "f11h", CPU_F11H },
{ "p4", CPU_P4 },
{ "dunnington", CPU_DUNNINGTON },
{ "xeon74xx", CPU_DUNNINGTON },
Index: mcelog-181/mcelog.h
===================================================================
--- mcelog-181.orig/mcelog.h
+++ mcelog-181/mcelog.h
@@ -120,6 +120,7 @@ enum cputype {
CPU_CORE2, /* 65nm and 45nm */
CPU_K8,
CPU_F10H,
+ CPU_F11H,
CPU_P4,
CPU_NEHALEM,
CPU_DUNNINGTON,