1c1607eb66
- Add mce decoding support for latest AMD CPUs (bnc#871881). - Implementation done by Borislav Petkov <bp@suse.de> * Add patches/Start-consolidating-AMD-specific-stuff.patch * Add add-defines.patch * Add add-f10h-support.patch * Add add-f11h-support.patch * Add add-f12h-support.patch * Add add-f14h-support.patch * Add add-f15h-support.patch * Add add-f16h-support.patch OBS-URL: https://build.opensuse.org/request/show/234343 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=35
74 lines
1.7 KiB
Diff
74 lines
1.7 KiB
Diff
Add AMD-specific defines and helpers
|
|
|
|
Signed-off-by: Borislav Petkov <bp@suse.de>
|
|
Index: mcelog/amd.h
|
|
===================================================================
|
|
--- mcelog.orig/amd.h 2014-05-08 01:10:26.000000000 +0200
|
|
+++ mcelog/amd.h 2014-05-08 01:18:50.000000000 +0200
|
|
@@ -10,5 +10,65 @@ int mce_filter_k8(struct mce *m);
|
|
#define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2)
|
|
#define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3)
|
|
|
|
+#define EC(x) ((x) & 0xffff)
|
|
+#define XEC(x, mask) (((x) >> 16) & mask)
|
|
+
|
|
+#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
|
|
+#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
|
|
+
|
|
+#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
|
|
+#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
|
|
+#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
|
|
+#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
|
|
+
|
|
+#define TT(x) (((x) >> 2) & 0x3)
|
|
+#define TT_MSG(x) tt_msgs[TT(x)]
|
|
+#define II(x) (((x) >> 2) & 0x3)
|
|
+#define II_MSG(x) ii_msgs[II(x)]
|
|
+#define LL(x) ((x) & 0x3)
|
|
+#define LL_MSG(x) ll_msgs[LL(x)]
|
|
+#define TO(x) (((x) >> 8) & 0x1)
|
|
+#define TO_MSG(x) to_msgs[TO(x)]
|
|
+#define PP(x) (((x) >> 9) & 0x3)
|
|
+#define PP_MSG(x) pp_msgs[PP(x)]
|
|
+#define UU(x) (((x) >> 8) & 0x3)
|
|
+#define UU_MSG(x) uu_msgs[UU(x)]
|
|
+
|
|
+#define R4(x) (((x) >> 4) & 0xf)
|
|
+#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
|
|
+
|
|
#define CASE_AMD_CPUS \
|
|
case CPU_K8
|
|
+
|
|
+enum tt_ids {
|
|
+ TT_INSTR = 0,
|
|
+ TT_DATA,
|
|
+ TT_GEN,
|
|
+ TT_RESV,
|
|
+};
|
|
+
|
|
+enum ll_ids {
|
|
+ LL_RESV = 0,
|
|
+ LL_L1,
|
|
+ LL_L2,
|
|
+ LL_LG,
|
|
+};
|
|
+
|
|
+enum ii_ids {
|
|
+ II_MEM = 0,
|
|
+ II_RESV,
|
|
+ II_IO,
|
|
+ II_GEN,
|
|
+};
|
|
+
|
|
+enum rrrr_ids {
|
|
+ R4_GEN = 0,
|
|
+ R4_RD,
|
|
+ R4_WR,
|
|
+ R4_DRD,
|
|
+ R4_DWR,
|
|
+ R4_IRD,
|
|
+ R4_PREF,
|
|
+ R4_EVICT,
|
|
+ R4_SNOOP,
|
|
+};
|