1c1607eb66
- Add mce decoding support for latest AMD CPUs (bnc#871881). - Implementation done by Borislav Petkov <bp@suse.de> * Add patches/Start-consolidating-AMD-specific-stuff.patch * Add add-defines.patch * Add add-f10h-support.patch * Add add-f11h-support.patch * Add add-f12h-support.patch * Add add-f14h-support.patch * Add add-f15h-support.patch * Add add-f16h-support.patch OBS-URL: https://build.opensuse.org/request/show/234343 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=35
260 lines
5.9 KiB
Diff
260 lines
5.9 KiB
Diff
Add F15h decoding support
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Signed-off-by: Borislav Petkov <bp@suse.de>
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Index: mcelog-1.0.1/amd.c
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===================================================================
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--- mcelog-1.0.1.orig/amd.c
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+++ mcelog-1.0.1/amd.c
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@@ -72,6 +72,43 @@ static char *nbextendederr[] = {
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"L3 Cache LRU Error"
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};
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+static const char * const f15h_mc1_mce_desc[] = {
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+ "UC during a demand linefill from L2",
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+ "Parity error during data load from IC",
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+ "Parity error for IC valid bit",
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+ "Main tag parity error",
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+ "Parity error in prediction queue",
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+ "PFB data/address parity error",
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+ "Parity error in the branch status reg",
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+ "PFB promotion address error",
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+ "Tag error during probe/victimization",
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+ "Parity error for IC probe tag valid bit",
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+ "PFB non-cacheable bit parity error",
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+ "PFB valid bit parity error", /* xec = 0xd */
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+ "Microcode Patch Buffer", /* xec = 010 */
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+ "uop queue",
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+ "insn buffer",
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+ "predecode buffer",
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+ "fetch address FIFO"
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+};
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+
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+static const char * const f15h_mc2_mce_desc[] = {
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+ "Fill ECC error on data fills", /* xec = 0x4 */
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+ "Fill parity error on insn fills",
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+ "Prefetcher request FIFO parity error",
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+ "PRQ address parity error",
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+ "PRQ data parity error",
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+ "WCC Tag ECC error",
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+ "WCC Data ECC error",
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+ "WCB Data parity error",
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+ "VB Data ECC or parity error",
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+ "L2 Tag ECC error", /* xec = 0x10 */
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+ "Hard L2 Tag ECC error",
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+ "Multiple hits on L2 tag",
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+ "XAB parity error",
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+ "PRB address parity error"
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+};
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+
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static const char * const mc4_mce_desc[] = {
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"DRAM ECC error detected on the NB",
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"CRC error detected on HT link",
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@@ -161,6 +198,8 @@ enum cputype select_amd_cputype(u32 fami
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return CPU_F12H;
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case 0x14:
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return CPU_F14H;
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+ case 0x15:
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+ return CPU_F15H;
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default:
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break;
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}
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@@ -435,6 +474,53 @@ static bool cat_mc0_mce(u16 ec, u8 xec)
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return ret;
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}
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+static bool f15h_mc0_mce(u16 ec, u8 xec)
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+{
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+ bool ret = true;
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+
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+ if (MEM_ERROR(ec)) {
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+
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+ switch (xec) {
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+ case 0x0:
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+ Wprintf("Data Array access error.\n");
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+ break;
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+
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+ case 0x1:
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+ Wprintf("UC error during a linefill from L2/NB.\n");
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+ break;
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+
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+ case 0x2:
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+ case 0x11:
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+ Wprintf("STQ access error.\n");
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+ break;
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+
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+ case 0x3:
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+ Wprintf("SCB access error.\n");
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+ break;
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+
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+ case 0x10:
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+ Wprintf("Tag error.\n");
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+ break;
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+
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+ case 0x12:
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+ Wprintf("LDQ access error.\n");
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+ break;
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+
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+ default:
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+ ret = false;
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+ }
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+ } else if (BUS_ERROR(ec)) {
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+
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+ if (!xec)
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+ Wprintf("System Read Data Error.\n");
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+ else
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+ Wprintf(" Internal error condition type %d.\n", xec);
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+ } else
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+ ret = false;
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+
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+ return ret;
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+}
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+
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static void decode_mc0_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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u16 ec = EC(m->status);
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@@ -481,6 +567,36 @@ static bool cat_mc1_mce(u16 ec, u8 xec)
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return ret;
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}
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+static bool f15h_mc1_mce(u16 ec, u8 xec)
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+{
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+ bool ret = true;
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+
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+ if (!MEM_ERROR(ec))
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+ return false;
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+
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+ switch (xec) {
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+ case 0x0 ... 0xa:
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+ Wprintf("%s.\n", f15h_mc1_mce_desc[xec]);
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+ break;
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+
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+ case 0xd:
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+ Wprintf("%s.\n", f15h_mc1_mce_desc[xec-2]);
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+ break;
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+
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+ case 0x10:
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+ Wprintf("%s.\n", f15h_mc1_mce_desc[xec-4]);
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+ break;
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+
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+ case 0x11 ... 0x14:
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+ Wprintf("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
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+ break;
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+
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+ default:
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+ ret = false;
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+ }
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+ return ret;
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+}
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+
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static void decode_mc1_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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u16 ec = EC(m->status);
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@@ -537,6 +653,40 @@ static bool k8_mc2_mce(u16 ec, u8 xec)
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return ret;
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}
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+static bool f15h_mc2_mce(u16 ec, u8 xec)
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+{
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+ bool ret = true;
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+
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+ if (TLB_ERROR(ec)) {
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+ if (xec == 0x0)
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+ Wprintf("Data parity TLB read error.\n");
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+ else if (xec == 0x1)
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+ Wprintf("Poison data provided for TLB fill.\n");
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+ else
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+ ret = false;
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+ } else if (BUS_ERROR(ec)) {
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+ if (xec > 2)
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+ ret = false;
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+
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+ Wprintf("Error during attempted NB data read.\n");
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+ } else if (MEM_ERROR(ec)) {
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+ switch (xec) {
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+ case 0x4 ... 0xc:
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+ Wprintf("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
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+ break;
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+
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+ case 0x10 ... 0x14:
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+ Wprintf("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
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+ break;
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+
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+ default:
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+ ret = false;
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+ }
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+ }
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+
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+ return ret;
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+}
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+
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static void decode_mc2_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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u16 ec = EC(m->status);
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@@ -741,6 +891,12 @@ struct amd_decoder_ops fam_ops[] = {
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.mc1_mce = cat_mc1_mce,
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.mc2_mce = k8_mc2_mce,
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},
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+ [AMD_F15H] = {
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+ .cpu = AMD_F15H,
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+ .mc0_mce = f15h_mc0_mce,
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+ .mc1_mce = f15h_mc1_mce,
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+ .mc2_mce = f15h_mc2_mce,
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+ },
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};
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static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
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@@ -760,6 +916,10 @@ static void __decode_amd_mc(enum cputype
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case CPU_F14H:
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ops = &fam_ops[AMD_F14H];
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break;
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+ case CPU_F15H:
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+ xec_mask = 0x1f;
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+ ops = &fam_ops[AMD_F15H];
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+ break;
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default:
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Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
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return;
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Index: mcelog-1.0.1/mcelog.h
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===================================================================
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--- mcelog-1.0.1.orig/mcelog.h
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+++ mcelog-1.0.1/mcelog.h
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@@ -111,6 +111,7 @@ enum cputype {
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CPU_F11H,
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CPU_F12H,
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CPU_F14H,
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+ CPU_F15H,
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CPU_P4,
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CPU_NEHALEM,
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CPU_DUNNINGTON,
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Index: mcelog-1.0.1/amd.h
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===================================================================
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--- mcelog-1.0.1.orig/amd.h
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+++ mcelog-1.0.1/amd.h
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@@ -97,4 +97,5 @@ enum rrrr_ids {
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case CPU_F10H: \
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case CPU_F11H: \
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case CPU_F12H: \
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- case CPU_F14H
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+ case CPU_F14H: \
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+ case CPU_F15H
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Index: mcelog-1.0.1/mcelog.c
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===================================================================
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--- mcelog-1.0.1.orig/mcelog.c
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+++ mcelog-1.0.1/mcelog.c
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@@ -226,6 +226,7 @@ static char *cputype_name[] = {
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[CPU_F11H] = "AMD Griffin",
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[CPU_F12H] = "AMD Llano",
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[CPU_F14H] = "AMD Bobcat",
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+ [CPU_F15H] = "AMD Bulldozer",
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[CPU_P4] = "Intel P4",
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[CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")",
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[CPU_DUNNINGTON] = "Intel Xeon 7400 series",
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@@ -248,6 +249,7 @@ static struct config_choice cpu_choices[
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{ "f11h", CPU_F11H },
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{ "f12h", CPU_F12H },
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{ "f14h", CPU_F14H },
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+ { "f15h", CPU_F15H },
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{ "p4", CPU_P4 },
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{ "dunnington", CPU_DUNNINGTON },
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{ "xeon74xx", CPU_DUNNINGTON },
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