4e419281e8
- update to 0.42.0: * run subcommand: * Introduce a new run subcommand capable of running targets until a time limit or EOT (suited for CI/CD workflows) * Supports semihosting console output/input and SWV output * Standard I/O routing: * Add new abstraction layer to unify STDIO routing for each core * Routing support for console, telnet, file and off * >Note: Currently only output is supported * CMSIS-Toolbox Run and Debug Management integration: * Add configuration layer in session options, which sits below command line arguments * Disable *.cbuild-run.yml processing if the target_override option is set * Improve port assignment logic for multi-core GDBServer and telnet configurations * Add processing for connect mode configuration * Add processing for pre-reset and post-reset options in load-setup configuration * Improve error messages for missing or invalid *.cbuild- run.yml file * Improve checking for required files * Raise a warning instead of an error for missing SVD files * Load SVD files only when available and when used by the subcommand * Flash programming: * Add new session options for configuring pre-reset and post-reset type in load subcommand * Relax flash algorithm requirement to require only RO section
Dirk Mueller2026-01-26 08:23:06 +00:00
a9283848e5
Accepting request 1317216 from devel:languages:python
Ana Guerrero2025-11-12 20:14:27 +00:00
9e39181dc2
- update to 0.40.0: * Add support for multiple concurrent GDB client connections to the same GDB server * Improve logging with support for multiple concurrent GDB clients * Report correct target architecture and align registers with GDB feature names * Add missing secure/non-secure core registers (CONTROL, FAULTMASK, BASEPRI, and PRIMASK) * Update ResetType API for clearer reset handling * Remove reset fallback mechanism for CMSIS-Pack based targets to prevent unintended behavior * Support custom reset sequence execution defined in CMSIS-Pack * Refine debug sequence error handling and breakpoint management across resets * Remove implicit resets between loading multiple application files * Set Reset Catch on all cores when performing primary-core reset before flashing * Perform a hardware reset (nSRST) after flashing to ensure a clean post-load state * CMSIS-Toolbox Run and Debug Management integration: * Add CMSIS-Pack related commands to commander interface
Dirk Mueller2025-11-11 23:45:02 +00:00
ef39852048
- update to 0.39.0: * CMSIS-Toolbox Run and Debug Management integration: * Set debugger protocol based on information from *.cbuild- run.yml file * Set output file type based on information from *.cbuild- run.yml file * Raise critical error if *.cbuild-run.yml file path is invalid * Show warning when packs required by*.cbuild-run.yml file are missing * Improve TransferError Exception messages to be more descriptive * Increase number of transfer retries after WAIT response * Probe: more reliable probe detection when probe is connected after pyOCD is started - update to 0.38.0: * Add CoreSight AP specific CSW handling for AHB-AP, AXI-AP, APB-AP * Add more debug logging information for cbuild-run targets * Add support for SW breakpoints when cache is present * Cortex-M: configure AP for cacheable access when cache is present * Flash algorithms: relax memory layout rules and add RAM alignment and minimum stack size checking - update to 0.37.0: * With this release, Python 3.7 is no longer supported. The minimum Python version is now 3.8.0. * CMSIS-Toolbox Run and Debug Management integration: * add a --cbuild-run option across subcommands * select target based on cbuild-runDirk Mueller2025-10-10 11:55:36 +00:00
db970b5e50
Accepting request 1223445 from devel:languages:python
Ana Guerrero2024-11-12 18:21:39 +00:00
42dbb98a0b
- update to 0.36.0: * Allow FlashBuilder to work when program page size is larger than sector erase size (@BrianPugh) * Very basic implementation to get a "connect" LED status display (@rgrr) * Add Trace Funnel Coresight component (@rapgenic) * Cortex-M CPU type detection improvements * Debug sequences: support pname on DebugPort* sequences * Add MAX32666FTHR board (@ozersa) * Add STMicro STM32 H743 and H723 targets (@unsanded) * nRF91 family improvements (@maxd-nordic) * Add HDSC HC32F448 hc32a460xe and hc32a4a0xi. (@lennvn) * Add airm2m air001 target (@kaidegit) * Add airm2m air32f103 target (@HalfSweet) * Add STMicro STM32H7B0 Target (@BrianPugh) * Add NXP S32K344 target (@PetervdPerk-NXP) * Add Realtek RTL8762C (@suphammer) * Add some missing ST and NXP board IDs * Fix HC32l130 32k+ flash error (@kaidegit) * Fix HC32L13x size and enable double buffering (@kaidegit) * Infineon PSoC6: remove unnecessary sleep during reset (@te- johan) * Remove part number match for NXP MIMXRTxxxx series family * RTT: fix CB not found (@tdasika) * CMSIS-DAP: Windows performance regression fix * Debug sequences: fix assignment expressions. * flash: fix some type errors, sort imports * Removed extraneous space character in the default cortex_m target warning message (@BenjaminSoelberg) * Flash loader: fix missing import of RamRegion
Dirk Mueller2024-11-11 21:04:00 +00:00
6cbe7e33e9
Accepting request 1100995 from devel:languages:python
Ana Guerrero2023-07-27 14:52:54 +00:00
62bd9361e0
- Switch to setuptools_scm, rather than setuptools_scm_git_archive. - Switch to pyproject macros. - Stop using greedy globs in %files.
Steve Kowalik2023-07-27 07:27:37 +00:00
f8f4735783
Accepting request 807685 from devel:languages:python
Yuchen Lin2020-05-26 15:18:36 +00:00
0fc28f12d7
Accepting request 807623 from home:pgajdos:python
Tomáš Chvátal
2020-05-20 11:39:02 +00:00
8a1391e5dd
- Update to 0.22.0: * Fixed regression with Cypress PSoC6 targets (#680) and merged in cumulative PSoC6 updates from Cypress. * Resolved a number of issues (but not all) with NXP LPC55S69. * Update ST NUCLEO-H743ZI. * Correct the wrong part number for MIMXRT1064-EVK board. * Correct part number for ST NUCLEO-WB55RG board. * Fix location of input data for flash algorithms in STM32F412xx target. * Address an issue with the built-in target STM32L031x6 by disabling double buffered flash programming.
Tomáš Chvátal
2019-09-10 12:49:31 +00:00