qemu/increase-x86_64-physical-bits-to-42.patch

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From: Bruce Rogers <brogers@suse.com>
Date: Fri, 17 May 2013 16:49:58 -0600
Subject: increase x86_64 physical bits to 42
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Allow for guests with higher amounts of ram. The current thought
is that 2TB specified on qemu commandline would be an appropriate
limit. Note that this requires the next higher bit value since
the highest address is actually more than 2TB due to the pci
memory hole.
Signed-off-by: Bruce Rogers <brogers@suse.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target/i386/tcg/helper-tcg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
Accepting request 941047 from home:dfaggioli:devel:Virtualization - Add an audio-oss sub-package - Add some new (mostly documentation) files in the package - Remove option --audio-drv-list because audio is detected by meson automatically in latest version. - Remove options --disable-jemalloc and --disable-tcmalloc which are changed in v6.2.0. - Update to v 6.2.0. For full release notese, see: * https://wiki.qemu.org/ChangeLog/6.2. Be sure to also check the following pages: * https://qemu-project.gitlab.io/qemu/about/removed-features.html * https://qemu-project.gitlab.io/qemu/about/deprecated.html Some notable changes: * virtio-mem: guest memory dumps are now fully supported, along with pre-copy/post-copy migration and background guest snapshots * QMP: support for nw DEVICE_UNPLUG_GUEST_ERROR to detect guest-reported hotplug failures * TCG: improvements to TCG plugin argument syntax, and multi-core support for cache plugin * 68k: improved support for Apple’s NuBus, including ability to load declaration ROMs, and slot IRQ support * ARM: macOS hosts with Apple Silicon CPUs now support ‘hvf’ accelerator for AArch64 guests * ARM: emulation support for Fujitsu A64FX processor model * ARM: emulation support for kudo-mbc machine type * ARM: M-profile MVE extension is now supported for Cortex-M55 * ARM: ‘virt’ machine now supports an emulated ITS (Interrupt Translation Service) and supports more than 123 CPUs in emulation mode * ARM: xlnx-zcu102 and xlnx-versal-virt machines now support BBRAM and eFUSE devices * PowerPC: improved POWER10 support for the ‘powernv’ machine type * PowerPC: initial support for POWER10 DD2.0 CPU model * PowerPC: support for FORM2 PAPR NUMA descriptions for ‘pseries’ machine type * RISC-V: support for Zb[abcs] instruction set extensions * RISC-V: support for vhost-user and numa mem options across all boards * RISC-V: SiFive PWM support * x86: support for new Snowridge-v4 CPU model * x86: guest support for Intel SGX * x86: AMD SEV guests now support measurement of kernel binary when doing direct kernel boot (not using a bootloader) * Patches dropped: 9pfs-fix-crash-in-v9fs_walk.patch block-introduce-max_hw_iov-for-use-in-sc.patch hmp-Unbreak-change-vnc.patch hw-acpi-ich9-Add-compat-prop-to-keep-HPC.patch hw-i386-acpi-build-Deny-control-on-PCIe-.patch i386-cpu-Remove-AVX_VNNI-feature-from-Co.patch net-vmxnet3-validate-configuration-value.patch pcie-rename-native-hotplug-to-x-native-h.patch plugins-do-not-limit-exported-symbols-if.patch plugins-execlog-removed-unintended-s-at-.patch qemu-nbd-Change-default-cache-mode-to-wr.patch qemu-sockets-fix-unix-socket-path-copy-a.patch target-arm-Don-t-skip-M-profile-reset-en.patch target-i386-add-missing-bits-to-CR4_RESE.patch tcg-arm-Fix-tcg_out_vec_op-function-sign.patch uas-add-stream-number-sanity-checks.patch vhost-vsock-fix-migration-issue-when-seq.patch virtio-balloon-don-t-start-free-page-hin.patch virtio-mem-pci-Fix-memory-leak-when-crea.patch virtio-net-fix-use-after-unmap-free-for-.patch OBS-URL: https://build.opensuse.org/request/show/941047 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=681
2021-12-17 11:07:39 +01:00
index 0a4401e917f9a0b40fb95bf947fd..ef916d40e8c9497853b265a1e7b4 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -26,7 +26,7 @@
#define TARGET_MAX_INSN_SIZE 16
#if defined(TARGET_X86_64)
-# define TCG_PHYS_ADDR_BITS 40
+# define TCG_PHYS_ADDR_BITS 42
#else
# define TCG_PHYS_ADDR_BITS 36
#endif