37 lines
1.5 KiB
Diff
37 lines
1.5 KiB
Diff
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From: Zenghui Yu <yuzenghui@huawei.com>
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Date: Fri, 2 Apr 2021 16:47:31 +0800
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Subject: hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync}
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interrupts
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Git-commit: 0c38f607836af40921ea2b58676b7c4a9fe33bef
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The GSIV values in SMMUv3 IORT node are not correct as they don't match
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the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
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our emulated vSMMU.
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Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
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Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
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Acked-by: Eric Auger <eric.auger@redhat.com>
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Message-id: 20210402084731.93-1-yuzenghui@huawei.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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hw/arm/virt-acpi-build.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
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index 9747a6458f0bfd34a3c2b3fda96a..6cd17c58c5535ee7277292b7372f 100644
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--- a/hw/arm/virt-acpi-build.c
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+++ b/hw/arm/virt-acpi-build.c
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@@ -287,8 +287,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
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smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
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smmu->event_gsiv = cpu_to_le32(irq);
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smmu->pri_gsiv = cpu_to_le32(irq + 1);
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- smmu->gerr_gsiv = cpu_to_le32(irq + 2);
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- smmu->sync_gsiv = cpu_to_le32(irq + 3);
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+ smmu->sync_gsiv = cpu_to_le32(irq + 2);
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+ smmu->gerr_gsiv = cpu_to_le32(irq + 3);
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/* Identity RID mapping covering the whole input RID range */
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idmap = &smmu->id_mapping_array[0];
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