60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
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From: Vitaly Chikunov <vt@altlinux.org>
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Date: Mon, 9 Mar 2020 23:45:57 +0300
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Subject: target/ppc: Fix rlwinm on ppc64
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Git-commit: 94f040aaecf4e41cc68991b80204b1b6886bbdd0
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rlwinm cannot just AND with Mask if shift value is zero on ppc64 when
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Mask Begin is greater than Mask End and high bits are set to 1.
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Note that PowerISA 3.0B says that for `rlwinm' ROTL32 is used, and
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ROTL32 is defined (in 3.3.14) so that rotated value should have two
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copies of lower word of the source value.
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This seems to be another incarnation of the fix from 820724d170
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("target-ppc: Fix rlwimi, rlwinm, rlwnm again"), except I leave
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optimization when Mask value is less than 32 bits.
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Fixes: 7b4d326f47 ("target-ppc: Use the new deposit and extract ops")
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Vitaly Chikunov <vt@altlinux.org>
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Message-Id: <20200309204557.14836-1-vt@altlinux.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/ppc/translate.c | 20 +++++++++++---------
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1 file changed, 11 insertions(+), 9 deletions(-)
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diff --git a/target/ppc/translate.c b/target/ppc/translate.c
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index f5fe5d06118a7c86d11f38767fab..f87f6eeaf7d988896c61b025320a 100644
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--- a/target/ppc/translate.c
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+++ b/target/ppc/translate.c
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@@ -1938,15 +1938,17 @@ static void gen_rlwinm(DisasContext *ctx)
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me += 32;
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#endif
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mask = MASK(mb, me);
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- if (sh == 0) {
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- tcg_gen_andi_tl(t_ra, t_rs, mask);
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- } else if (mask <= 0xffffffffu) {
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- TCGv_i32 t0 = tcg_temp_new_i32();
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- tcg_gen_trunc_tl_i32(t0, t_rs);
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- tcg_gen_rotli_i32(t0, t0, sh);
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- tcg_gen_andi_i32(t0, t0, mask);
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- tcg_gen_extu_i32_tl(t_ra, t0);
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- tcg_temp_free_i32(t0);
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+ if (mask <= 0xffffffffu) {
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+ if (sh == 0) {
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+ tcg_gen_andi_tl(t_ra, t_rs, mask);
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+ } else {
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+ TCGv_i32 t0 = tcg_temp_new_i32();
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+ tcg_gen_trunc_tl_i32(t0, t_rs);
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+ tcg_gen_rotli_i32(t0, t0, sh);
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+ tcg_gen_andi_i32(t0, t0, mask);
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+ tcg_gen_extu_i32_tl(t_ra, t0);
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+ tcg_temp_free_i32(t0);
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+ }
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} else {
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#if defined(TARGET_PPC64)
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tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
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