47 lines
1.8 KiB
Diff
47 lines
1.8 KiB
Diff
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From: =?UTF-8?q?Alex=20Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Fri, 31 Jan 2020 15:34:39 +0000
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Subject: target/arm: fix TCG leak for fcvt half->double
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Git-commit: aeab8e5eb220cc5ff84b0b68b9afccc611bf0fcd
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When support for the AHP flag was added we inexplicably only freed the
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new temps in one of the two legs. Move those tcg_temp_free to the same
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level as the allocation to fix that leak.
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Fixes: 486624fcd3eac
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Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
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Message-id: 20200131153439.26027-1-alex.bennee@linaro.org
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/arm/translate-a64.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
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index d4bebbe62958ed2264e8db880bac..045da9266717203d85258110ed10 100644
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--- a/target/arm/translate-a64.c
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+++ b/target/arm/translate-a64.c
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@@ -5778,8 +5778,6 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
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TCGv_i32 tcg_rd = tcg_temp_new_i32();
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gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
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write_fp_sreg(s, rd, tcg_rd);
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- tcg_temp_free_ptr(tcg_fpst);
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- tcg_temp_free_i32(tcg_ahp);
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tcg_temp_free_i32(tcg_rd);
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} else {
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/* Half to double */
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@@ -5789,6 +5787,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
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tcg_temp_free_i64(tcg_rd);
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}
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tcg_temp_free_i32(tcg_rn);
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+ tcg_temp_free_ptr(tcg_fpst);
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+ tcg_temp_free_i32(tcg_ahp);
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break;
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}
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default:
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