38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Sat, 28 Mar 2020 18:16:10 -0700
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Subject: tcg/i386: Fix INDEX_op_dup2_vec
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Git-commit: e20cb81d9c5a3d0f9c08f3642728a210a1c162c9
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We were only constructing the 64-bit element, and not
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replicating the 64-bit element across the rest of the vector.
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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tcg/i386/tcg-target.inc.c | 10 +++++++---
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1 file changed, 7 insertions(+), 3 deletions(-)
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diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
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index 9d8ed974e011152d2df4cba613ad..77b78c941c5afcd065a8e153dca7 100644
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--- a/tcg/i386/tcg-target.inc.c
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+++ b/tcg/i386/tcg-target.inc.c
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@@ -2855,9 +2855,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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goto gen_simd;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_dup2_vec:
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- /* Constraints have already placed both 32-bit inputs in xmm regs. */
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- insn = OPC_PUNPCKLDQ;
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- goto gen_simd;
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+ /* First merge the two 32-bit inputs to a single 64-bit element. */
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+ tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2);
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+ /* Then replicate the 64-bit elements across the rest of the vector. */
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+ if (type != TCG_TYPE_V64) {
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+ tcg_out_dup_vec(s, type, MO_64, a0, a0);
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+ }
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+ break;
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#endif
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case INDEX_op_abs_vec:
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insn = abs_insn[vece];
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