43 lines
1.7 KiB
Diff
43 lines
1.7 KiB
Diff
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
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Date: Mon, 2 Dec 2019 22:09:43 +0100
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Subject: arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()
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Git-commit: 0c7f8c43daf6556078e51de98aa13f069e505985
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This change ensures that the FPU can be accessed in Non-Secure mode
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when the CPU core is reset using the arm_set_cpu_on() function call.
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The NSACR.{CP11,CP10} bits define the exception level required to
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access the FPU in Non-Secure mode. Without these bits set, the CPU
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will give an undefined exception trap on the first FPU access for the
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secondary cores under Linux.
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This is necessary because in this power-control codepath QEMU
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is effectively emulating a bit of EL3 firmware, and has to set
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the CPU up as the EL3 firmware would.
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Fixes: fc1120a7f5
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
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[PMM: added clarifying para to commit message]
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/arm/arm-powerctl.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
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index f77a950db67276513977af686aa9..b064513d44a86932bbd70b06b3ca 100644
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--- a/target/arm/arm-powerctl.c
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+++ b/target/arm/arm-powerctl.c
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@@ -104,6 +104,9 @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
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/* Processor is not in secure mode */
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target_cpu->env.cp15.scr_el3 |= SCR_NS;
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+ /* Set NSACR.{CP11,CP10} so NS can access the FPU */
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+ target_cpu->env.cp15.nsacr |= 3 << 10;
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+
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/*
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* If QEMU is providing the equivalent of EL3 firmware, then we need
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* to make sure a CPU targeting EL2 comes out of reset with a
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