From: Zenghui Yu Date: Fri, 2 Apr 2021 16:47:31 +0800 Subject: hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts Git-commit: 0c38f607836af40921ea2b58676b7c4a9fe33bef The GSIV values in SMMUv3 IORT node are not correct as they don't match the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by our emulated vSMMU. Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table") Signed-off-by: Zenghui Yu Acked-by: Eric Auger Message-id: 20210402084731.93-1-yuzenghui@huawei.com Signed-off-by: Peter Maydell Signed-off-by: Bruce Rogers --- hw/arm/virt-acpi-build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9747a6458f0bfd34a3c2b3fda96a..6cd17c58c5535ee7277292b7372f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -287,8 +287,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); smmu->event_gsiv = cpu_to_le32(irq); smmu->pri_gsiv = cpu_to_le32(irq + 1); - smmu->gerr_gsiv = cpu_to_le32(irq + 2); - smmu->sync_gsiv = cpu_to_le32(irq + 3); + smmu->sync_gsiv = cpu_to_le32(irq + 2); + smmu->gerr_gsiv = cpu_to_le32(irq + 3); /* Identity RID mapping covering the whole input RID range */ idmap = &smmu->id_mapping_array[0];