From: Paolo Bonzini <pbonzini@redhat.com>
Date: Wed, 13 Nov 2019 15:54:35 +0100
Subject: target/i386: add PSCHANGE_NO bit for the ARCH_CAPABILITIES MSR

Git-commit: 7f7a585d5bd3c7f1275d28c77d9d67513c1de36c
Reference: bsc#1155812 CVE-2018-12207

This is required to disable ITLB multihit mitigations in nested
hypervisors.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Bruce Rogers <brogers@suse.com>
---
 target/i386/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 19751e37a71fee27944526fe507c..5191367f89ee4d1131c4309633de 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1188,7 +1188,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
         .type = MSR_FEATURE_WORD,
         .feat_names = {
             "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
-            "ssb-no", "mds-no", NULL, NULL,
+            "ssb-no", "mds-no", "pschange-mc-no", NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,