b7616307b7
Include SLE feature requests, misc upstream stable bug fixes, and repair Jira feature references OBS-URL: https://build.opensuse.org/request/show/762845 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=521
50 lines
2.1 KiB
Diff
50 lines
2.1 KiB
Diff
From: Simon Veith <sveith@amazon.de>
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Date: Fri, 20 Dec 2019 14:03:00 +0000
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Subject: hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro
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Git-commit: a7f65ceb851af5a5b639c6e30801076d848db2c2
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The bit offsets in the EVT_SET_ADDR2 macro do not match those specified
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in the ARM SMMUv3 Architecture Specification. In all events that use
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this macro, e.g. F_WALK_EABT, the faulting fetch address or IPA actually
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occupies the 32-bit words 6 and 7 in the event record contiguously, with
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the upper and lower unused bits clear due to alignment or maximum
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supported address bits. How many bits are clear depends on the
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individual event type.
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Update the macro to write to the correct words in the event record so
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that guest drivers can obtain accurate address information on events.
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ref. ARM IHI 0070C, sections 7.3.12 through 7.3.16.
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Signed-off-by: Simon Veith <sveith@amazon.de>
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Acked-by: Eric Auger <eric.auger@redhat.com>
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Tested-by: Eric Auger <eric.auger@redhat.com>
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Message-id: 1576509312-13083-6-git-send-email-sveith@amazon.de
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Cc: Eric Auger <eric.auger@redhat.com>
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Cc: qemu-devel@nongnu.org
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Cc: qemu-arm@nongnu.org
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Acked-by: Eric Auger <eric.auger@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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hw/arm/smmuv3-internal.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
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index 042b4358084b6b87e8b9e42d5622..4112394129e0069018a5967cb685 100644
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--- a/hw/arm/smmuv3-internal.h
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+++ b/hw/arm/smmuv3-internal.h
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@@ -461,8 +461,8 @@ typedef struct SMMUEventInfo {
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} while (0)
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#define EVT_SET_ADDR2(x, addr) \
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do { \
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- (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \
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- (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\
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+ (x)->word[7] = (uint32_t)(addr >> 32); \
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+ (x)->word[6] = (uint32_t)(addr & 0xffffffff); \
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} while (0)
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void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
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