12286f39d2
- Include upstream patches designated as stable material and reviewed for applicability to include here. NOTE that the PIIX4 patch has migration implications: the change will also be applied to the SLE-15-SP2 qemu, and a live migration from that version to this SLE-15-SP3 qemu would require this patch to be applied for a successful migration if PIIX4 southbridge is used in the machine emulation (x86 i440fx) block-rbd-fix-memory-leak-in-qemu_rbd_co.patch block-rbd-Fix-memory-leak-in-qemu_rbd_co.patch cpu-core-Fix-help-of-CPU-core-device-typ.patch hw-arm-virt-acpi-build-Fix-GSIV-values-o.patch hw-block-fdc-Fix-fallback-property-on-sy.patch hw-isa-Kconfig-Add-missing-dependency-VI.patch hw-isa-piix4-Migrate-Reset-Control-Regis.patch hw-virtio-pci-Added-AER-capability.patch hw-virtio-pci-Added-counter-for-pcie-cap.patch s390x-css-report-errors-from-ccw_dstream.patch target-xtensa-fix-meson.build-rule-for-x.patch util-fix-use-after-free-in-module_load_o.patch virtio-pci-compat-page-aligned-ATS.patch OBS-URL: https://build.opensuse.org/request/show/885459 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=634
85 lines
3.1 KiB
Diff
85 lines
3.1 KiB
Diff
From: Andrew Melnychenko <andrew@daynix.com>
|
|
Date: Thu, 3 Dec 2020 13:07:13 +0200
|
|
Subject: hw/virtio-pci Added AER capability.
|
|
|
|
Git-commit: fdfa3b1d6f9edd97c807df496a0d8e9ea49240da
|
|
|
|
Added AER capability for virtio-pci devices.
|
|
Also added property for devices, by default AER is disabled.
|
|
|
|
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
|
|
Message-Id: <20201203110713.204938-3-andrew@daynix.com>
|
|
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
|
|
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
|
|
Signed-off-by: Bruce Rogers <brogers@suse.com>
|
|
[BR: needed for stable commit d83f46d189a26fa32434139954d264326f199a45]
|
|
---
|
|
hw/virtio/virtio-pci.c | 16 ++++++++++++++++
|
|
hw/virtio/virtio-pci.h | 4 ++++
|
|
2 files changed, 20 insertions(+)
|
|
|
|
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
|
|
index ceaa233129c529b604f461e45336..f863f69ede4f4bf1c09fc39a5035 100644
|
|
--- a/hw/virtio/virtio-pci.c
|
|
+++ b/hw/virtio/virtio-pci.c
|
|
@@ -1817,6 +1817,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
|
|
*/
|
|
pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
|
|
|
|
+ if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
|
|
+ pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
|
|
+ PCI_ERR_SIZEOF, NULL);
|
|
+ last_pcie_cap_offset += PCI_ERR_SIZEOF;
|
|
+ }
|
|
+
|
|
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
|
|
/* Init error enabling flags */
|
|
pcie_cap_deverr_init(pci_dev);
|
|
@@ -1858,7 +1864,15 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
|
|
|
|
static void virtio_pci_exit(PCIDevice *pci_dev)
|
|
{
|
|
+ VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
|
|
+ bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
|
|
+ !pci_bus_is_root(pci_get_bus(pci_dev));
|
|
+
|
|
msix_uninit_exclusive_bar(pci_dev);
|
|
+ if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
|
|
+ pci_is_express(pci_dev)) {
|
|
+ pcie_aer_exit(pci_dev);
|
|
+ }
|
|
}
|
|
|
|
static void virtio_pci_reset(DeviceState *qdev)
|
|
@@ -1911,6 +1925,8 @@ static Property virtio_pci_properties[] = {
|
|
VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
|
|
DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
|
|
VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
|
|
+ DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
|
|
+ VIRTIO_PCI_FLAG_AER_BIT, false),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
|
|
index 06e2af12de64c32f8c26c7f9e858..d7d5d403a9483f5f7e0f0f9b4110 100644
|
|
--- a/hw/virtio/virtio-pci.h
|
|
+++ b/hw/virtio/virtio-pci.h
|
|
@@ -41,6 +41,7 @@ enum {
|
|
VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
|
|
VIRTIO_PCI_FLAG_INIT_PM_BIT,
|
|
VIRTIO_PCI_FLAG_INIT_FLR_BIT,
|
|
+ VIRTIO_PCI_FLAG_AER_BIT,
|
|
};
|
|
|
|
/* Need to activate work-arounds for buggy guests at vmstate load. */
|
|
@@ -80,6 +81,9 @@ enum {
|
|
/* Init Function Level Reset capability */
|
|
#define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
|
|
|
|
+/* Advanced Error Reporting capability */
|
|
+#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
|
|
+
|
|
typedef struct {
|
|
MSIMessage msg;
|
|
int virq;
|