6dea1703fb
- Add Cooperlake vcpu model (jira-SLE-10195) i386-Add-MSR-feature-bit-for-MDS-NO.patch i386-Add-macro-for-stibp.patch i386-Add-new-CPU-model-Cooperlake.patch target-i386-Add-new-bit-definitions-of-M.patch target-i386-Add-missed-features-to-Coope.patch - Add HMAT support (jira-SLE-10228) (the test case for this series isn't included because we aren't set up to handle binary patches) numa-Extend-CLI-to-provide-initiator-inf.patch numa-Extend-CLI-to-provide-memory-latenc.patch numa-Extend-CLI-to-provide-memory-side-c.patch hmat-acpi-Build-Memory-Proximity-Domain-.patch hmat-acpi-Build-System-Locality-Latency-.patch hmat-acpi-Build-Memory-Side-Cache-Inform.patch tests-numa-Add-case-for-QMP-build-HMAT.patch OBS-URL: https://build.opensuse.org/request/show/762501 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=520
33 lines
1.1 KiB
Diff
33 lines
1.1 KiB
Diff
From: Bruce Rogers <brogers@suse.com>
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Date: Fri, 17 May 2013 16:49:58 -0600
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Subject: increase x86_64 physical bits to 42
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Allow for guests with higher amounts of ram. The current thought
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is that 2TB specified on qemu commandline would be an appropriate
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limit. Note that this requires the next higher bit value since
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the highest address is actually more than 2TB due to the pci
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memory hole.
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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Signed-off-by: Andreas Färber <afaerber@suse.de>
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---
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target/i386/cpu.h | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 594326a7946798aba6ac42415164..5da6b243db2824f79676e4e1bbae 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -1934,7 +1934,7 @@ uint64_t cpu_get_tsc(CPUX86State *env);
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/* XXX: This value should match the one returned by CPUID
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* and in exec.c */
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# if defined(TARGET_X86_64)
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-# define TCG_PHYS_ADDR_BITS 40
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+# define TCG_PHYS_ADDR_BITS 42
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# else
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# define TCG_PHYS_ADDR_BITS 36
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# endif
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