6dea1703fb
- Add Cooperlake vcpu model (jira-SLE-10195) i386-Add-MSR-feature-bit-for-MDS-NO.patch i386-Add-macro-for-stibp.patch i386-Add-new-CPU-model-Cooperlake.patch target-i386-Add-new-bit-definitions-of-M.patch target-i386-Add-missed-features-to-Coope.patch - Add HMAT support (jira-SLE-10228) (the test case for this series isn't included because we aren't set up to handle binary patches) numa-Extend-CLI-to-provide-initiator-inf.patch numa-Extend-CLI-to-provide-memory-latenc.patch numa-Extend-CLI-to-provide-memory-side-c.patch hmat-acpi-Build-Memory-Proximity-Domain-.patch hmat-acpi-Build-System-Locality-Latency-.patch hmat-acpi-Build-Memory-Side-Cache-Inform.patch tests-numa-Add-case-for-QMP-build-HMAT.patch OBS-URL: https://build.opensuse.org/request/show/762501 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=520
33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From: Cathy Zhang <cathy.zhang@intel.com>
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Date: Tue, 22 Oct 2019 15:35:26 +0800
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Subject: i386: Add MSR feature bit for MDS-NO
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Git commit: 77b168d221191156c47fcd8d1c47329dfdb9439e
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References: JIRA-SLE-10195
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Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow
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CPU models to report the feature when host supports it.
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Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Reviewed-by: Tao Xu <tao3.xu@intel.com>
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Message-Id: <1571729728-23284-2-git-send-email-cathy.zhang@intel.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/i386/cpu.h | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index cde2a16b941adeb1123d5d7411f3..39d37e12256069b92c7998590849 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -838,6 +838,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define MSR_ARCH_CAP_RSBA (1U << 2)
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#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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+#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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