6dea1703fb
- Add Cooperlake vcpu model (jira-SLE-10195) i386-Add-MSR-feature-bit-for-MDS-NO.patch i386-Add-macro-for-stibp.patch i386-Add-new-CPU-model-Cooperlake.patch target-i386-Add-new-bit-definitions-of-M.patch target-i386-Add-missed-features-to-Coope.patch - Add HMAT support (jira-SLE-10228) (the test case for this series isn't included because we aren't set up to handle binary patches) numa-Extend-CLI-to-provide-initiator-inf.patch numa-Extend-CLI-to-provide-memory-latenc.patch numa-Extend-CLI-to-provide-memory-side-c.patch hmat-acpi-Build-Memory-Proximity-Domain-.patch hmat-acpi-Build-System-Locality-Latency-.patch hmat-acpi-Build-Memory-Side-Cache-Inform.patch tests-numa-Add-case-for-QMP-build-HMAT.patch OBS-URL: https://build.opensuse.org/request/show/762501 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=520
36 lines
1.3 KiB
Diff
36 lines
1.3 KiB
Diff
From: Cathy Zhang <cathy.zhang@intel.com>
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Date: Tue, 22 Oct 2019 15:35:27 +0800
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Subject: i386: Add macro for stibp
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Git commit: 5af514d0cb314f43bc53f2aefb437f6451d64d0c
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References: JIRA-SLE-10195
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stibp feature is already added through the following commit.
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https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955
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Add a macro for it to allow CPU models to report it when host supports.
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Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Reviewed-by: Tao Xu <tao3.xu@intel.com>
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Message-Id: <1571729728-23284-3-git-send-email-cathy.zhang@intel.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/i386/cpu.h | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 39d37e12256069b92c7998590849..af282936a785a25f651d0db1a8cf 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -771,6 +771,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
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/* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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+/* Single Thread Indirect Branch Predictors */
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+#define CPUID_7_0_EDX_STIBP (1U << 27)
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/* Arch Capabilities */
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#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
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/* Core Capability */
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