6dea1703fb
- Add Cooperlake vcpu model (jira-SLE-10195) i386-Add-MSR-feature-bit-for-MDS-NO.patch i386-Add-macro-for-stibp.patch i386-Add-new-CPU-model-Cooperlake.patch target-i386-Add-new-bit-definitions-of-M.patch target-i386-Add-missed-features-to-Coope.patch - Add HMAT support (jira-SLE-10228) (the test case for this series isn't included because we aren't set up to handle binary patches) numa-Extend-CLI-to-provide-initiator-inf.patch numa-Extend-CLI-to-provide-memory-latenc.patch numa-Extend-CLI-to-provide-memory-side-c.patch hmat-acpi-Build-Memory-Proximity-Domain-.patch hmat-acpi-Build-System-Locality-Latency-.patch hmat-acpi-Build-Memory-Side-Cache-Inform.patch tests-numa-Add-case-for-QMP-build-HMAT.patch OBS-URL: https://build.opensuse.org/request/show/762501 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=520
45 lines
1.7 KiB
Diff
45 lines
1.7 KiB
Diff
From: Xiaoyao Li <xiaoyao.li@intel.com>
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Date: Wed, 8 Jan 2020 13:32:39 +0100
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Subject: target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
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Git-commit: 0000000000000000000000000000000000000000
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References: JIRA-SLE-1015
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The bit 6, 7 and 8 of MSR_IA32_ARCH_CAPABILITIES are recently disclosed
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for some security issues. Add the definitions for them to be used by named
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CPU models.
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Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20191225063018.20038-2-xiaoyao.li@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/i386/cpu.h | 13 ++++++++-----
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1 file changed, 8 insertions(+), 5 deletions(-)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index af282936a785a25f651d0db1a8cf..594326a7946798aba6ac42415164 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -835,12 +835,15 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
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/* MSR Feature Bits */
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-#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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-#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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-#define MSR_ARCH_CAP_RSBA (1U << 2)
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+#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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+#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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+#define MSR_ARCH_CAP_RSBA (1U << 2)
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#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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-#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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-#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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+#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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+#define MSR_ARCH_CAP_MDS_NO (1U << 5)
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+#define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
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+#define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
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+#define MSR_ARCH_CAP_TAA_NO (1U << 8)
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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