9cc71e44f4
- Stable fixes from upstream * Patches added: block-introduce-max_hw_iov-for-use-in-sc.patch hmp-Unbreak-change-vnc.patch qemu-nbd-Change-default-cache-mode-to-wr.patch target-arm-Don-t-skip-M-profile-reset-en.patch vhost-vsock-fix-migration-issue-when-seq.patch virtio-mem-pci-Fix-memory-leak-when-crea.patch virtio-net-fix-use-after-unmap-free-for-.patch OBS-URL: https://build.opensuse.org/request/show/924265 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=675
89 lines
3.5 KiB
Diff
89 lines
3.5 KiB
Diff
From: Peter Maydell <peter.maydell@linaro.org>
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Date: Mon, 20 Sep 2021 09:54:33 +0100
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Subject: target/arm: Don't skip M-profile reset entirely in user mode
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Git-commit: b62ceeaf8096fdbbbfdc6087da0028bc4a4dd77e
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Currently all of the M-profile specific code in arm_cpu_reset() is
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inside a !defined(CONFIG_USER_ONLY) ifdef block. This is
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unintentional: it happened because originally the only
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M-profile-specific handling was the setup of the initial SP and PC
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from the vector table, which is system-emulation only. But then we
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added a lot of other M-profile setup to the same "if (ARM_FEATURE_M)"
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code block without noticing that it was all inside a not-user-mode
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ifdef. This has generally been harmless, but with the addition of
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v8.1M low-overhead-loop support we ran into a problem: the reset of
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FPSCR.LTPSIZE to 4 was only being done for system emulation mode, so
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if a user-mode guest tried to execute the LE instruction it would
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incorrectly take a UsageFault.
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Adjust the ifdefs so only the really system-emulation specific parts
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are covered. Because this means we now run some reset code that sets
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up initial values in the FPCCR and similar FPU related registers,
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explicitly set up the registers controlling FPU context handling in
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user-emulation mode so that the FPU works by design and not by
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chance.
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/613
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20210914120725.24992-2-peter.maydell@linaro.org
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Signed-off-by: Li Zhang <li.zhang@suse.com>
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---
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target/arm/cpu.c | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c
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index 2866dd765882c87eb773493d04cd..af60c07ca1421558cae5cc2e3128 100644
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--- a/target/arm/cpu.c
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+++ b/target/arm/cpu.c
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@@ -265,12 +265,15 @@ static void arm_cpu_reset(DeviceState *dev)
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env->uncached_cpsr = ARM_CPU_MODE_SVC;
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}
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env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
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+#endif
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if (arm_feature(env, ARM_FEATURE_M)) {
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+#ifndef CONFIG_USER_ONLY
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uint32_t initial_msp; /* Loaded from 0x0 */
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uint32_t initial_pc; /* Loaded from 0x4 */
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uint8_t *rom;
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uint32_t vecbase;
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+#endif
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if (cpu_isar_feature(aa32_lob, cpu)) {
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/*
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@@ -324,6 +327,8 @@ static void arm_cpu_reset(DeviceState *dev)
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env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
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R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
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}
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+
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+#ifndef CONFIG_USER_ONLY
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/* Unlike A/R profile, M profile defines the reset LR value */
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env->regs[14] = 0xffffffff;
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@@ -352,8 +357,22 @@ static void arm_cpu_reset(DeviceState *dev)
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env->regs[13] = initial_msp & 0xFFFFFFFC;
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env->regs[15] = initial_pc & ~1;
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env->thumb = initial_pc & 1;
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+#else
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+ /*
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+ * For user mode we run non-secure and with access to the FPU.
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+ * The FPU context is active (ie does not need further setup)
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+ * and is owned by non-secure.
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+ */
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+ env->v7m.secure = false;
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+ env->v7m.nsacr = 0xcff;
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+ env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
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+ env->v7m.fpccr[M_REG_S] &=
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+ ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
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+ env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
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+#endif
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}
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+#ifndef CONFIG_USER_ONLY
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/* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
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* executing as AArch32 then check if highvecs are enabled and
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* adjust the PC accordingly.
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