0f796dd004
Update to v4.1.0. Also includes other major packaging changes as follows: There is a new package maintenance workflow - see README.PACKAGING for details. The sibling packages qemu-linux-user and qemu-testsuite are now created with the Build Service's MultiBuild feature. This also necessitates combining the qemu-linux-user changelog content back into qemu's. Luckily the delta there is quite small. Note that the qemu spec file is now that much busier, but added section markers should help reduce the confusion. Also qemu is being enabled for RISCV host compatibility, so some changes are related to that as well. OBS-URL: https://build.opensuse.org/request/show/730437 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=487
160 lines
3.8 KiB
Diff
160 lines
3.8 KiB
Diff
From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Mon, 18 Mar 2019 15:43:53 +0100
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Subject: ati: add edid support.
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Git-commit: 588eb12163b51c4d402383369456ce1cd1ec86ab
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Read EDID blob via i2c, store in VBE_edid.
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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vgasrc/atiext.c | 114 ++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 114 insertions(+)
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diff --git a/roms/seabios/vgasrc/atiext.c b/roms/seabios/vgasrc/atiext.c
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index 0586279ce214fac7d2a7e6c87a94..8c9e6966db47f083646193d7faf6 100644
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--- a/roms/seabios/vgasrc/atiext.c
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+++ b/roms/seabios/vgasrc/atiext.c
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@@ -19,6 +19,8 @@
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#define MM_DATA 0x0004
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#define CRTC_GEN_CNTL 0x0050
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#define CRTC_EXT_CNTL 0x0054
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+#define GPIO_VGA_DDC 0x0060
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+#define GPIO_DVI_DDC 0x0064
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#define CRTC_H_TOTAL_DISP 0x0200
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#define CRTC_V_TOTAL_DISP 0x0208
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#define CRTC_OFFSET 0x0224
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@@ -106,6 +108,20 @@ static inline void ati_write(u32 reg, u32 val)
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}
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}
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+static inline u32 ati_read(u32 reg)
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+{
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+ u32 io_addr = GET_GLOBAL(ati_io_addr);
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+ u32 val;
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+
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+ if (reg < 0x100) {
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+ val = inl(io_addr + reg);
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+ } else {
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+ outl(reg, io_addr + MM_INDEX);
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+ reg = inl(io_addr + MM_DATA);
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+ }
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+ return val;
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+}
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+
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static void ati_clear(u32 offset, u32 size)
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{
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u8 data[64];
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@@ -180,6 +196,97 @@ ati_set_mode(struct vgamode_s *vmode_g, int flags)
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return stdvga_set_mode(vmode_g, flags);
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}
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+/****************************************************************
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+ * edid
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+ ****************************************************************/
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+
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+static void
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+ati_i2c_set_scl_sda(int scl, int sda)
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+{
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+ u32 data = 0;
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+
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+ if (!scl)
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+ data |= (1 << 17);
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+ if (!sda)
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+ data |= (1 << 16);
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+ ati_write(GPIO_DVI_DDC, data);
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+}
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+
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+static int
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+ati_i2c_get_sda(void)
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+{
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+ u32 data = ati_read(GPIO_DVI_DDC);
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+
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+ return data & (1 << 8) ? 1 : 0;
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+}
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+
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+static void ati_i2c_start(void)
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+{
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+ ati_i2c_set_scl_sda(1, 1);
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+ ati_i2c_set_scl_sda(1, 0);
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+ ati_i2c_set_scl_sda(0, 0);
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+}
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+
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+static void ati_i2c_ack(void)
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+{
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+ ati_i2c_set_scl_sda(0, 0);
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+ ati_i2c_set_scl_sda(1, 0);
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+ ati_i2c_set_scl_sda(0, 0);
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+}
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+
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+static void ati_i2c_stop(void)
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+{
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+ ati_i2c_set_scl_sda(0, 0);
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+ ati_i2c_set_scl_sda(1, 0);
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+ ati_i2c_set_scl_sda(1, 1);
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+}
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+
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+static void ati_i2c_send_byte(u8 byte)
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+{
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+ int i, bit;
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+
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+ for (i = 0; i < 8; i++) {
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+ bit = (1 << (7-i)) & byte ? 1 : 0;
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+ ati_i2c_set_scl_sda(0, bit);
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+ ati_i2c_set_scl_sda(1, bit);
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+ ati_i2c_set_scl_sda(0, bit);
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+ }
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+}
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+
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+static u8 ati_i2c_recv_byte(void)
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+{
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+ u8 byte = 0;
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+ int i, bit;
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+
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+ for (i = 0; i < 8; i++) {
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+ ati_i2c_set_scl_sda(0, 1);
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+ ati_i2c_set_scl_sda(1, 1);
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+ bit = ati_i2c_get_sda();
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+ ati_i2c_set_scl_sda(0, 1);
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+ if (bit)
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+ byte |= (1 << (7-i));
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+ }
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+
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+ return byte;
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+}
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+
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+static void ati_i2c_edid(void)
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+{
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+ u8 byte;
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+ int i;
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+
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+ dprintf(1, "ati: reading edid blob\n");
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+ ati_i2c_start();
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+ ati_i2c_send_byte(0x50 << 1 | 1);
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+ ati_i2c_ack();
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+ for (i = 0; i < 128; i++) {
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+ byte = ati_i2c_recv_byte();
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+ ati_i2c_ack();
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+ SET_VGA(VBE_edid[i], byte);
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+ }
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+ ati_i2c_stop();
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+}
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+
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/****************************************************************
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* init
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****************************************************************/
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@@ -241,5 +348,12 @@ ati_setup(void)
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}
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}
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+ u16 device = pci_config_readw(bdf, PCI_DEVICE_ID);
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+ switch (device) {
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+ case 0x5159:
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+ ati_i2c_edid();
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+ break;
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+ }
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+
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return 0;
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}
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