b7616307b7
Include SLE feature requests, misc upstream stable bug fixes, and repair Jira feature references OBS-URL: https://build.opensuse.org/request/show/762845 OBS-URL: https://build.opensuse.org/package/show/Virtualization/qemu?expand=0&rev=521
89 lines
5.0 KiB
Diff
89 lines
5.0 KiB
Diff
From: Xiaoyao Li <xiaoyao.li@intel.com>
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Date: Wed, 8 Jan 2020 13:32:40 +0100
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Subject: target/i386: Add missed features to Cooperlake CPU model
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Git-commit: 0000000000000000000000000000000000000000
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References: jsc#SLE-7923
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It lacks VMX features and two security feature bits (disclosed recently) in
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MSR_IA32_ARCH_CAPABILITIES in current Cooperlake CPU model, so add them.
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Fixes: 22a866b6166d ("i386: Add new CPU model Cooperlake")
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Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20191225063018.20038-3-xiaoyao.li@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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---
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target/i386/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 50 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 8a1993ac64bd763b7bb70c98b8b8..876bd166652365397514ada0dec7 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -3201,7 +3201,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
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.features[FEAT_ARCH_CAPABILITIES] =
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MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
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- MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO,
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+ MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
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+ MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
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.features[FEAT_7_1_EAX] =
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CPUID_7_1_EAX_AVX512_BF16,
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/*
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@@ -3216,6 +3217,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_XSAVE_XGETBV1,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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+ /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
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+ .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
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+ MSR_VMX_BASIC_TRUE_CTLS,
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+ .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
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+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
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+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
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+ .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
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+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
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+ MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
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+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
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+ .features[FEAT_VMX_EXIT_CTLS] =
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+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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+ VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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+ .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
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+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
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+ .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
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+ VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
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+ VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
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+ .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
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+ VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
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+ VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
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+ VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
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+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
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+ VMX_CPU_BASED_MONITOR_TRAP_FLAG |
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+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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+ .features[FEAT_VMX_SECONDARY_CTLS] =
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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+ VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
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+ VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
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+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
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+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
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+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
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+ VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
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+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
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+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
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+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
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.xlevel = 0x80000008,
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.model_id = "Intel Xeon Processor (Cooperlake)",
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},
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