merge
OBS-URL: https://build.opensuse.org/package/show/hardware/rasdaemon?expand=0&rev=10
This commit is contained in:
Git OBS Bridge
parent
1207cc5edc
commit
ea7fda5cdb
236
broadwell_de_mscod.patch
Normal file
236
broadwell_de_mscod.patch
Normal file
@ -0,0 +1,236 @@
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From: Aristeu Rozanski <arozansk@redhat.com>
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Subject: Add Broadwell DE MSCOD values
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Patch-Mainline: yes
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Git-commit: e7b88730f8a753a50fa0b8d1f7027f79baa05ca4
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Git-repo: git.fedorahosted.org/git/rasdaemon.git
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Signed-off-by: Thomas Renninger <trenn@suse.de>
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Based on mcelog commit id 32252e9c37e97ea5083d90d2cf194bb85a4a0cda.
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Signed-off-by: Aristeu Rozanski <arozansk@redhat.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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diff --git a/Makefile.am b/Makefile.am
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index a1cb02a..a8477d3 100644
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--- a/Makefile.am
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+++ b/Makefile.am
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@@ -29,7 +29,7 @@ if WITH_MCE
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mce-intel-p4-p6.c mce-intel-nehalem.c \
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mce-intel-dunnington.c mce-intel-tulsa.c \
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mce-intel-sb.c mce-intel-ivb.c mce-intel-haswell.c \
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- mce-intel-knl.c
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+ mce-intel-knl.c mce-intel-broadwell-de.c
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endif
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if WITH_EXTLOG
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rasdaemon_SOURCES += ras-extlog-handler.c
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diff --git a/mce-intel-broadwell-de.c b/mce-intel-broadwell-de.c
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new file mode 100644
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index 0000000..d52c82e
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--- /dev/null
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+++ b/mce-intel-broadwell-de.c
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@@ -0,0 +1,146 @@
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+/*
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+ * The code below came from Tony Luck's mcelog code,
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+ * released under GNU Public General License, v.2
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|
+ *
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|
+ * This program is free software; you can redistribute it and/or modify
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|
+ * it under the terms of the GNU General Public License as published by
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||||||
|
+ * the Free Software Foundation; either version 2 of the License, or
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|
+ * (at your option) any later version.
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||||||
|
+ *
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|
+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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|
+ * GNU General Public License for more details.
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||||||
|
+ *
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|
+ * You should have received a copy of the GNU General Public License
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||||||
|
+ * along with this program; if not, write to the Free Software
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||||||
|
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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+*/
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+
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+#include <string.h>
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+#include <stdio.h>
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+
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+#include "ras-mce-handler.h"
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+#include "bitfield.h"
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+
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+/* See IA32 SDM Vol3B Table 16-24 */
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+
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+static char *pcu_1[] = {
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+ [0x00] = "No Error",
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+ [0x09] = "MC_MESSAGE_CHANNEL_TIMEOUT",
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+ [0x13] = "MC_DMI_TRAINING_TIMEOUT",
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+ [0x15] = "MC_DMI_CPU_RESET_ACK_TIMEOUT",
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+ [0x1E] = "MC_VR_ICC_MAX_LT_FUSED_ICC_MAX",
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|
+ [0x25] = "MC_SVID_COMMAN_TIMEOUT",
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+ [0x26] = "MCA_PKGC_DIRECT_WAKE_RING_TIMEOUT",
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+ [0x29] = "MC_VR_VOUT_MAC_LT_FUSED_SVID",
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+ [0x2B] = "MC_PKGC_WATCHDOG_HANG_CBZ_DOWN",
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|
+ [0x2C] = "MC_PKGC_WATCHDOG_HANG_CBZ_UP",
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|
+ [0x44] = "MC_CRITICAL_VR_FAILED",
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+ [0x46] = "MC_VID_RAMP_DOWN_FAILED",
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+ [0x49] = "MC_SVID_WRITE_REG_VOUT_MAX_FAILED",
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|
+ [0x4B] = "MC_BOOT_VID_TIMEOUT_DRAM_0",
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|
+ [0x4F] = "MC_SVID_COMMAND_ERROR",
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|
+ [0x52] = "MC_FIVR_CATAS_OVERVOL_FAULT",
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|
+ [0x53] = "MC_FIVR_CATAS_OVERCUR_FAULT",
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+ [0x57] = "MC_SVID_PKGC_REQUEST_FAILED",
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+ [0x58] = "MC_SVID_IMON_REQUEST_FAILED",
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|
+ [0x59] = "MC_SVID_ALERT_REQUEST_FAILED",
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|
+ [0x62] = "MC_INVALID_PKGS_RSP_QPI",
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|
+ [0x64] = "MC_INVALID_PKG_STATE_CONFIG",
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|
+ [0x67] = "MC_HA_IMC_RW_BLOCK_ACK_TIMEOUT",
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|
+ [0x6A] = "MC_MSGCH_PMREQ_CMP_TIMEOUT",
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|
+ [0x72] = "MC_WATCHDOG_TIMEOUT_PKGS_MASTER",
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|
+ [0x81] = "MC_RECOVERABLE_DIE_THERMAL_TOO_HOT"
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|
+};
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|
+
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|
+static struct field pcu_mc4[] = {
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+ FIELD(24, pcu_1),
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|
+ {}
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+};
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+
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|
+/* See IA32 SDM Vol3B Table 16-18 */
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|
+
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|
+static struct field memctrl_mc9[] = {
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|
+ SBITFIELD(16, "Address parity error"),
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|
+ SBITFIELD(17, "HA Wrt buffer Data parity error"),
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|
+ SBITFIELD(18, "HA Wrt byte enable parity error"),
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|
+ SBITFIELD(19, "Corrected patrol scrub error"),
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|
+ SBITFIELD(20, "Uncorrected patrol scrub error"),
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|
+ SBITFIELD(21, "Corrected spare error"),
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|
+ SBITFIELD(22, "Uncorrected spare error"),
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|
+ SBITFIELD(23, "Corrected memory read error"),
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|
+ SBITFIELD(24, "iMC, WDB, parity errors"),
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|
+ {}
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|
+};
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+
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+void broadwell_de_decode_model(struct ras_events *ras, struct mce_event *e)
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+{
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+ uint64_t status = e->status;
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+ uint32_t mca = status & 0xffff;
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+ unsigned rank0 = -1, rank1 = -1, chan;
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+
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|
+ switch (e->bank) {
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|
+ case 4:
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|
+ switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) {
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|
+ case 0x402: case 0x403:
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|
+ mce_snprintf(e->mcastatus_msg, "Internal errors ");
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+ break;
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|
+ case 0x406:
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|
+ mce_snprintf(e->mcastatus_msg, "Intel TXT errors ");
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+ break;
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|
+ case 0x407:
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+ mce_snprintf(e->mcastatus_msg, "Other UBOX Internal errors ");
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|
+ break;
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|
+ }
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|
+ if (EXTRACT(status, 16, 19) & 3)
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|
+ mce_snprintf(e->mcastatus_msg, "PCU internal error ");
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+ if (EXTRACT(status, 20, 23) & 4)
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+ mce_snprintf(e->mcastatus_msg, "Ubox error ");
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+ decode_bitfield(e, status, pcu_mc4);
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+ break;
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+ case 9: case 10:
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+ mce_snprintf(e->mcastatus_msg, "MemCtrl: ");
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|
+ decode_bitfield(e, status, memctrl_mc9);
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|
+ break;
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+ }
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+
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|
+ /*
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+ * Memory error specific code. Returns if the error is not a MC one
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+ */
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+
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|
+ /* Check if the error is at the memory controller */
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+ if ((mca >> 7) != 1)
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+ return;
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+
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+ /* Ignore unless this is an corrected extended error from an iMC bank */
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+ if (e->bank < 9 || e->bank > 16 || (status & MCI_STATUS_UC) ||
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+ !test_prefix(7, status & 0xefff))
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+ return;
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+
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+ /*
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+ * Parse the reported channel and ranks
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+ */
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+
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+ chan = EXTRACT(status, 0, 3);
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+ if (chan == 0xf)
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+ return;
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+
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+ mce_snprintf(e->mc_location, "memory_channel=%d", chan);
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+
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+ if (EXTRACT(e->misc, 62, 62)) {
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+ rank0 = EXTRACT(e->misc, 46, 50);
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+ if (EXTRACT(e->misc, 63, 63))
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+ rank1 = EXTRACT(e->misc, 51, 55);
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+ }
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+
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+ /*
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+ * FIXME: The conversion from rank to dimm requires to parse the
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+ * DMI tables and call failrank2dimm().
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|
+ */
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|
+ if (rank0 != -1 && rank1 != -1)
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|
+ mce_snprintf(e->mc_location, "ranks=%d and %d",
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|
+ rank0, rank1);
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|
+ else if (rank0 != -1)
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|
+ mce_snprintf(e->mc_location, "rank=%d", rank0);
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|
+}
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diff --git a/mce-intel.c b/mce-intel.c
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index 032f4e0..b132903 100644
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--- a/mce-intel.c
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+++ b/mce-intel.c
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@@ -401,6 +401,9 @@ int parse_intel_event(struct ras_events *ras, struct mce_event *e)
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case CPU_KNIGHTS_LANDING:
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knl_decode_model(ras, e);
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|
break;
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|
+ case CPU_BROADWELL_DE:
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|
+ broadwell_de_decode_model(ras, e);
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|
+ break;
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|
default:
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|
break;
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|
}
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diff --git a/ras-mce-handler.c b/ras-mce-handler.c
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index 3b0b05b..b58d6e0 100644
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|
--- a/ras-mce-handler.c
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+++ b/ras-mce-handler.c
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@@ -50,6 +50,7 @@ static char *cputype_name[] = {
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|
[CPU_HASWELL] = "Haswell",
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|
[CPU_HASWELL_EPEX] = "Intel Xeon v3 (Haswell) EP/EX",
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|
[CPU_BROADWELL] = "Broadwell",
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|
+ [CPU_BROADWELL_DE] = "Broadwell DE",
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|
[CPU_KNIGHTS_LANDING] = "Knights Landing",
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|
};
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|
|
||||||
|
@@ -90,8 +91,9 @@ static enum cputype select_intel_cputype(struct ras_events *ras)
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|
return CPU_HASWELL;
|
||||||
|
else if (mce->model == 0x3f)
|
||||||
|
return CPU_HASWELL_EPEX;
|
||||||
|
- else if (mce->model == 0x3d || mce->model == 0x4f ||
|
||||||
|
- mce->model == 0x56)
|
||||||
|
+ else if (mce->model == 0x56)
|
||||||
|
+ return CPU_BROADWELL_DE;
|
||||||
|
+ else if (mce->model == 0x3d || mce->model == 0x4f)
|
||||||
|
return CPU_BROADWELL;
|
||||||
|
else if (mce->model == 0x57)
|
||||||
|
return CPU_KNIGHTS_LANDING;
|
||||||
|
diff --git a/ras-mce-handler.h b/ras-mce-handler.h
|
||||||
|
index 5466743..2648048 100644
|
||||||
|
--- a/ras-mce-handler.h
|
||||||
|
+++ b/ras-mce-handler.h
|
||||||
|
@@ -45,6 +45,7 @@ enum cputype {
|
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|
CPU_HASWELL,
|
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|
CPU_HASWELL_EPEX,
|
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|
CPU_BROADWELL,
|
||||||
|
+ CPU_BROADWELL_DE,
|
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|
CPU_KNIGHTS_LANDING,
|
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|
};
|
||||||
|
|
||||||
|
@@ -121,6 +122,7 @@ void ivb_decode_model(struct ras_events *ras, struct mce_event *e);
|
||||||
|
void hsw_decode_model(struct ras_events *ras, struct mce_event *e);
|
||||||
|
void knl_decode_model(struct ras_events *ras, struct mce_event *e);
|
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|
void tulsa_decode_model(struct mce_event *e);
|
||||||
|
+void broadwell_de_decode_model(struct ras_events *ras, struct mce_event *e);
|
||||||
|
|
||||||
|
/* Software defined banks */
|
||||||
|
#define MCE_EXTENDED_BANK 128
|
||||||
281
broadwell_ep_ex_mscod.patch
Normal file
281
broadwell_ep_ex_mscod.patch
Normal file
@ -0,0 +1,281 @@
|
|||||||
|
From: Aristeu Rozanski <arozansk@redhat.com>
|
||||||
|
Subject: Add Broadwell EP/EX MSCOD values
|
||||||
|
Patch-Mainline: yes
|
||||||
|
Git-commit: 0dd44fca9d756990acf01cd2cdaa585f369168bc
|
||||||
|
Git-repo: git.fedorahosted.org/git/rasdaemon.git
|
||||||
|
|
||||||
|
Signed-off-by: Thomas Renninger <trenn@suse.de>
|
||||||
|
|
||||||
|
Based on mcelog commit id 32252e9c37e97ea5083d90d2cf194bb85a4a0cda.
|
||||||
|
|
||||||
|
Signed-off-by: Aristeu Rozanski <arozansk@redhat.com>
|
||||||
|
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
|
||||||
|
|
||||||
|
diff --git a/Makefile.am b/Makefile.am
|
||||||
|
index a8477d3..c9e4481 100644
|
||||||
|
--- a/Makefile.am
|
||||||
|
+++ b/Makefile.am
|
||||||
|
@@ -29,7 +29,8 @@ if WITH_MCE
|
||||||
|
mce-intel-p4-p6.c mce-intel-nehalem.c \
|
||||||
|
mce-intel-dunnington.c mce-intel-tulsa.c \
|
||||||
|
mce-intel-sb.c mce-intel-ivb.c mce-intel-haswell.c \
|
||||||
|
- mce-intel-knl.c mce-intel-broadwell-de.c
|
||||||
|
+ mce-intel-knl.c mce-intel-broadwell-de.c \
|
||||||
|
+ mce-intel-broadwell-epex.c
|
||||||
|
endif
|
||||||
|
if WITH_EXTLOG
|
||||||
|
rasdaemon_SOURCES += ras-extlog-handler.c
|
||||||
|
diff --git a/mce-intel-broadwell-epex.c b/mce-intel-broadwell-epex.c
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000..f7cd3b6
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/mce-intel-broadwell-epex.c
|
||||||
|
@@ -0,0 +1,191 @@
|
||||||
|
+/*
|
||||||
|
+ * The code below came from Tony Luck's mcelog code,
|
||||||
|
+ * released under GNU Public General License, v.2
|
||||||
|
+ *
|
||||||
|
+ * This program is free software; you can redistribute it and/or modify
|
||||||
|
+ * it under the terms of the GNU General Public License as published by
|
||||||
|
+ * the Free Software Foundation; either version 2 of the License, or
|
||||||
|
+ * (at your option) any later version.
|
||||||
|
+ *
|
||||||
|
+ * This program is distributed in the hope that it will be useful,
|
||||||
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+ * GNU General Public License for more details.
|
||||||
|
+ *
|
||||||
|
+ * You should have received a copy of the GNU General Public License
|
||||||
|
+ * along with this program; if not, write to the Free Software
|
||||||
|
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
+*/
|
||||||
|
+
|
||||||
|
+#include <string.h>
|
||||||
|
+#include <stdio.h>
|
||||||
|
+
|
||||||
|
+#include "ras-mce-handler.h"
|
||||||
|
+#include "bitfield.h"
|
||||||
|
+
|
||||||
|
+/* See IA32 SDM Vol3B Table 16-20 */
|
||||||
|
+
|
||||||
|
+static char *pcu_1[] = {
|
||||||
|
+ [0x00] = "No Error",
|
||||||
|
+ [0x09] = "MC_MESSAGE_CHANNEL_TIMEOUT",
|
||||||
|
+ [0x0D] = "MC_IMC_FORCE_SR_S3_TIMEOUT",
|
||||||
|
+ [0x0E] = "MC_CPD_UNCPD_SD_TIMEOUT",
|
||||||
|
+ [0x13] = "MC_DMI_TRAINING_TIMEOUT",
|
||||||
|
+ [0x15] = "MC_DMI_CPU_RESET_ACK_TIMEOUT",
|
||||||
|
+ [0x1E] = "MC_VR_ICC_MAX_LT_FUSED_ICC_MAX",
|
||||||
|
+ [0x25] = "MC_SVID_COMMAN_TIMEOUT",
|
||||||
|
+ [0x29] = "MC_VR_VOUT_MAC_LT_FUSED_SVID",
|
||||||
|
+ [0x2B] = "MC_PKGC_WATCHDOG_HANG_CBZ_DOWN",
|
||||||
|
+ [0x2C] = "MC_PKGC_WATCHDOG_HANG_CBZ_UP",
|
||||||
|
+ [0x39] = "MC_PKGC_WATCHDOG_HANG_C3_UP_SF",
|
||||||
|
+ [0x44] = "MC_CRITICAL_VR_FAILED",
|
||||||
|
+ [0x45] = "MC_ICC_MAX_NOTSUPPORTED",
|
||||||
|
+ [0x46] = "MC_VID_RAMP_DOWN_FAILED",
|
||||||
|
+ [0x47] = "MC_EXCL_MODE_NO_PMREQ_CMP",
|
||||||
|
+ [0x48] = "MC_SVID_READ_REG_ICC_MAX_FAILED",
|
||||||
|
+ [0x49] = "MC_SVID_WRITE_REG_VOUT_MAX_FAILED",
|
||||||
|
+ [0x4B] = "MC_BOOT_VID_TIMEOUT_DRAM_0",
|
||||||
|
+ [0x4C] = "MC_BOOT_VID_TIMEOUT_DRAM_1",
|
||||||
|
+ [0x4D] = "MC_BOOT_VID_TIMEOUT_DRAM_2",
|
||||||
|
+ [0x4E] = "MC_BOOT_VID_TIMEOUT_DRAM_3",
|
||||||
|
+ [0x4F] = "MC_SVID_COMMAND_ERROR",
|
||||||
|
+ [0x52] = "MC_FIVR_CATAS_OVERVOL_FAULT",
|
||||||
|
+ [0x53] = "MC_FIVR_CATAS_OVERCUR_FAULT",
|
||||||
|
+ [0x57] = "MC_SVID_PKGC_REQUEST_FAILED",
|
||||||
|
+ [0x58] = "MC_SVID_IMON_REQUEST_FAILED",
|
||||||
|
+ [0x59] = "MC_SVID_ALERT_REQUEST_FAILED",
|
||||||
|
+ [0x60] = "MC_INVALID_PKGS_REQ_PCH",
|
||||||
|
+ [0x61] = "MC_INVALID_PKGS_REQ_QPI",
|
||||||
|
+ [0x62] = "MC_INVALID_PKGS_RSP_QPI",
|
||||||
|
+ [0x63] = "MC_INVALID_PKGS_RSP_PCH",
|
||||||
|
+ [0x64] = "MC_INVALID_PKG_STATE_CONFIG",
|
||||||
|
+ [0x67] = "MC_HA_IMC_RW_BLOCK_ACK_TIMEOUT",
|
||||||
|
+ [0x68] = "MC_IMC_RW_SMBUS_TIMEOUT",
|
||||||
|
+ [0x69] = "MC_HA_FAILSTS_CHANGE_DETECTED",
|
||||||
|
+ [0x6A] = "MC_MSGCH_PMREQ_CMP_TIMEOUT",
|
||||||
|
+ [0x70] = "MC_WATCHDOG_TIMEOUT_PKGC_SLAVE",
|
||||||
|
+ [0x71] = "MC_WATCHDOG_TIMEOUT_PKGC_MASTER",
|
||||||
|
+ [0x72] = "MC_WATCHDOG_TIMEOUT_PKGS_MASTER",
|
||||||
|
+ [0x7C] = "MC_BIOS_RST_CPL_INVALID_SEQ",
|
||||||
|
+ [0x7D] = "MC_MORE_THAN_ONE_TXT_AGENT",
|
||||||
|
+ [0x81] = "MC_RECOVERABLE_DIE_THERMAL_TOO_HOT"
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct field pcu_mc4[] = {
|
||||||
|
+ FIELD(24, pcu_1),
|
||||||
|
+ {}
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+/* See IA32 SDM Vol3B Table 16-21 */
|
||||||
|
+
|
||||||
|
+static char *qpi[] = {
|
||||||
|
+ [0x02] = "Intel QPI physical layer detected drift buffer alarm",
|
||||||
|
+ [0x03] = "Intel QPI physical layer detected latency buffer rollover",
|
||||||
|
+ [0x10] = "Intel QPI link layer detected control error from R3QPI",
|
||||||
|
+ [0x11] = "Rx entered LLR abort state on CRC error",
|
||||||
|
+ [0x12] = "Unsupported or undefined packet",
|
||||||
|
+ [0x13] = "Intel QPI link layer control error",
|
||||||
|
+ [0x15] = "RBT used un-initialized value",
|
||||||
|
+ [0x20] = "Intel QPI physical layer detected a QPI in-band reset but aborted initialization",
|
||||||
|
+ [0x21] = "Link failover data self healing",
|
||||||
|
+ [0x22] = "Phy detected in-band reset (no width change)",
|
||||||
|
+ [0x23] = "Link failover clock failover",
|
||||||
|
+ [0x30] = "Rx detected CRC error - successful LLR after Phy re-init",
|
||||||
|
+ [0x31] = "Rx detected CRC error - successful LLR wihout Phy re-init",
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct field qpi_mc[] = {
|
||||||
|
+ FIELD(16, qpi),
|
||||||
|
+ {}
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+/* See IA32 SDM Vol3B Table 16-26 */
|
||||||
|
+
|
||||||
|
+static struct field memctrl_mc9[] = {
|
||||||
|
+ SBITFIELD(16, "DDR3 address parity error"),
|
||||||
|
+ SBITFIELD(17, "Uncorrected HA write data error"),
|
||||||
|
+ SBITFIELD(18, "Uncorrected HA data byte enable error"),
|
||||||
|
+ SBITFIELD(19, "Corrected patrol scrub error"),
|
||||||
|
+ SBITFIELD(20, "Uncorrected patrol scrub error"),
|
||||||
|
+ SBITFIELD(21, "Corrected spare error"),
|
||||||
|
+ SBITFIELD(22, "Uncorrected spare error"),
|
||||||
|
+ SBITFIELD(24, "iMC write data buffer parity error"),
|
||||||
|
+ SBITFIELD(25, "DDR4 command address parity error"),
|
||||||
|
+ {}
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+void broadwell_epex_decode_model(struct ras_events *ras, struct mce_event *e)
|
||||||
|
+{
|
||||||
|
+ uint64_t status = e->status;
|
||||||
|
+ uint32_t mca = status & 0xffff;
|
||||||
|
+ unsigned rank0 = -1, rank1 = -1, chan;
|
||||||
|
+
|
||||||
|
+ switch (e->bank) {
|
||||||
|
+ case 4:
|
||||||
|
+ switch (EXTRACT(status, 0, 15) & ~(1ull << 12)) {
|
||||||
|
+ case 0x402: case 0x403:
|
||||||
|
+ mce_snprintf(e->mcastatus_msg, "Internal errors ");
|
||||||
|
+ break;
|
||||||
|
+ case 0x406:
|
||||||
|
+ mce_snprintf(e->mcastatus_msg, "Intel TXT errors ");
|
||||||
|
+ break;
|
||||||
|
+ case 0x407:
|
||||||
|
+ mce_snprintf(e->mcastatus_msg, "Other UBOX Internal errors ");
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+ if (EXTRACT(status, 16, 19))
|
||||||
|
+ mce_snprintf(e->mcastatus_msg, "PCU internal error ");
|
||||||
|
+ decode_bitfield(e, status, pcu_mc4);
|
||||||
|
+ break;
|
||||||
|
+ case 5:
|
||||||
|
+ case 20:
|
||||||
|
+ case 21:
|
||||||
|
+ mce_snprintf(e->mcastatus_msg, "QPI: ");
|
||||||
|
+ decode_bitfield(e, status, qpi_mc);
|
||||||
|
+ break;
|
||||||
|
+ case 9: case 10: case 11: case 12:
|
||||||
|
+ case 13: case 14: case 15: case 16:
|
||||||
|
+ mce_snprintf(e->mcastatus_msg, "MemCtrl: ");
|
||||||
|
+ decode_bitfield(e, status, memctrl_mc9);
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * Memory error specific code. Returns if the error is not a MC one
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+ /* Check if the error is at the memory controller */
|
||||||
|
+ if ((mca >> 7) != 1)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ /* Ignore unless this is an corrected extended error from an iMC bank */
|
||||||
|
+ if (e->bank < 9 || e->bank > 16 || (status & MCI_STATUS_UC) ||
|
||||||
|
+ !test_prefix(7, status & 0xefff))
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * Parse the reported channel and ranks
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+ chan = EXTRACT(status, 0, 3);
|
||||||
|
+ if (chan == 0xf)
|
||||||
|
+ return;
|
||||||
|
+
|
||||||
|
+ mce_snprintf(e->mc_location, "memory_channel=%d", chan);
|
||||||
|
+
|
||||||
|
+ if (EXTRACT(e->misc, 62, 62)) {
|
||||||
|
+ rank0 = EXTRACT(e->misc, 46, 50);
|
||||||
|
+ if (EXTRACT(e->misc, 63, 63))
|
||||||
|
+ rank1 = EXTRACT(e->misc, 51, 55);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * FIXME: The conversion from rank to dimm requires to parse the
|
||||||
|
+ * DMI tables and call failrank2dimm().
|
||||||
|
+ */
|
||||||
|
+ if (rank0 != -1 && rank1 != -1)
|
||||||
|
+ mce_snprintf(e->mc_location, "ranks=%d and %d",
|
||||||
|
+ rank0, rank1);
|
||||||
|
+ else if (rank0 != -1)
|
||||||
|
+ mce_snprintf(e->mc_location, "rank=%d", rank0);
|
||||||
|
+}
|
||||||
|
diff --git a/mce-intel.c b/mce-intel.c
|
||||||
|
index b132903..bf68d9b 100644
|
||||||
|
--- a/mce-intel.c
|
||||||
|
+++ b/mce-intel.c
|
||||||
|
@@ -404,6 +404,9 @@ int parse_intel_event(struct ras_events *ras, struct mce_event *e)
|
||||||
|
case CPU_BROADWELL_DE:
|
||||||
|
broadwell_de_decode_model(ras, e);
|
||||||
|
break;
|
||||||
|
+ case CPU_BROADWELL_EPEX:
|
||||||
|
+ broadwell_epex_decode_model(ras, e);
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
diff --git a/ras-mce-handler.c b/ras-mce-handler.c
|
||||||
|
index b58d6e0..b875512 100644
|
||||||
|
--- a/ras-mce-handler.c
|
||||||
|
+++ b/ras-mce-handler.c
|
||||||
|
@@ -51,6 +51,7 @@ static char *cputype_name[] = {
|
||||||
|
[CPU_HASWELL_EPEX] = "Intel Xeon v3 (Haswell) EP/EX",
|
||||||
|
[CPU_BROADWELL] = "Broadwell",
|
||||||
|
[CPU_BROADWELL_DE] = "Broadwell DE",
|
||||||
|
+ [CPU_BROADWELL_EPEX] = "Broadwell EP/EX",
|
||||||
|
[CPU_KNIGHTS_LANDING] = "Knights Landing",
|
||||||
|
};
|
||||||
|
|
||||||
|
@@ -93,7 +94,9 @@ static enum cputype select_intel_cputype(struct ras_events *ras)
|
||||||
|
return CPU_HASWELL_EPEX;
|
||||||
|
else if (mce->model == 0x56)
|
||||||
|
return CPU_BROADWELL_DE;
|
||||||
|
- else if (mce->model == 0x3d || mce->model == 0x4f)
|
||||||
|
+ else if (mce->model == 0x4f)
|
||||||
|
+ return CPU_BROADWELL_EPEX;
|
||||||
|
+ else if (mce->model == 0x3d)
|
||||||
|
return CPU_BROADWELL;
|
||||||
|
else if (mce->model == 0x57)
|
||||||
|
return CPU_KNIGHTS_LANDING;
|
||||||
|
diff --git a/ras-mce-handler.h b/ras-mce-handler.h
|
||||||
|
index 2648048..c5a3717 100644
|
||||||
|
--- a/ras-mce-handler.h
|
||||||
|
+++ b/ras-mce-handler.h
|
||||||
|
@@ -46,6 +46,7 @@ enum cputype {
|
||||||
|
CPU_HASWELL_EPEX,
|
||||||
|
CPU_BROADWELL,
|
||||||
|
CPU_BROADWELL_DE,
|
||||||
|
+ CPU_BROADWELL_EPEX,
|
||||||
|
CPU_KNIGHTS_LANDING,
|
||||||
|
};
|
||||||
|
|
||||||
|
@@ -123,6 +124,7 @@ void hsw_decode_model(struct ras_events *ras, struct mce_event *e);
|
||||||
|
void knl_decode_model(struct ras_events *ras, struct mce_event *e);
|
||||||
|
void tulsa_decode_model(struct mce_event *e);
|
||||||
|
void broadwell_de_decode_model(struct ras_events *ras, struct mce_event *e);
|
||||||
|
+void broadwell_epex_decode_model(struct ras_events *ras, struct mce_event *e);
|
||||||
|
|
||||||
|
/* Software defined banks */
|
||||||
|
#define MCE_EXTENDED_BANK 128
|
||||||
@ -1,3 +1,10 @@
|
|||||||
|
-------------------------------------------------------------------
|
||||||
|
Tue May 31 09:54:13 UTC 2016 - trenn@suse.de
|
||||||
|
|
||||||
|
- Add MSCOD values for broadwell de/ep/ex processors
|
||||||
|
* Add broadwell_de_mscod.patch
|
||||||
|
* Add broadwell_ep_ex_mscod.patch
|
||||||
|
|
||||||
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
||||||
Mon Mar 7 15:40:41 UTC 2016 - fvogt@suse.com
|
Mon Mar 7 15:40:41 UTC 2016 - fvogt@suse.com
|
||||||
|
|
||||||
|
|||||||
@ -24,6 +24,8 @@ License: GPL-2.0
|
|||||||
Group: Hardware/Other
|
Group: Hardware/Other
|
||||||
Url: https://git.fedorahosted.org/cgit/rasdaemon.git
|
Url: https://git.fedorahosted.org/cgit/rasdaemon.git
|
||||||
Source: https://git.fedorahosted.org/cgit/rasdaemon.git/snapshot/%{name}-%{version}.tar.xz
|
Source: https://git.fedorahosted.org/cgit/rasdaemon.git/snapshot/%{name}-%{version}.tar.xz
|
||||||
|
Patch0: broadwell_de_mscod.patch
|
||||||
|
Patch1: broadwell_ep_ex_mscod.patch
|
||||||
BuildRequires: autoconf
|
BuildRequires: autoconf
|
||||||
BuildRequires: automake
|
BuildRequires: automake
|
||||||
BuildRequires: gcc
|
BuildRequires: gcc
|
||||||
@ -51,6 +53,8 @@ an utility for reporting current error counts from the EDAC sysfs files.
|
|||||||
|
|
||||||
%prep
|
%prep
|
||||||
%setup -q
|
%setup -q
|
||||||
|
%patch0 -p1
|
||||||
|
%patch1 -p1
|
||||||
|
|
||||||
%build
|
%build
|
||||||
autoreconf -fvi
|
autoreconf -fvi
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user