111 lines
4.2 KiB
Diff
111 lines
4.2 KiB
Diff
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Subject: [PATCH] [FEAT VS1804] zipl: Consolidate STAGE{2,3} macros
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From: Marc Hartmayer <mhartmay@linux.ibm.com>
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Summary: genprotimg: Introduce new tool for the creation of PV images
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Description: genprotimg takes a kernel, host-key documents, optionally an
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initrd, optionally a file with the kernel command line, and it
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generates a single, loadable image file. The image consists of a
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concatenation of a plain text boot loader, the encrypted
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components for kernel, initrd, and cmdline, and the
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integrity-protected PV header, containing metadata necessary for
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running the guest in PV mode. It's possible to use this image file
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as a kernel for zIPL or for a direct kernel boot using QEMU.
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Upstream-ID: 4762e65acbc4efe7142ccb5fd2ef86073737ebd8
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Problem-ID: VS1804
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Upstream-Description:
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zipl: Consolidate STAGE{2,3} macros
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Increase consistency with the other macros by moving and renaming
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the STAGE{2,3} macros in zipl.h.
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Signed-off-by: Philipp Rudo <prudo@linux.ibm.com>
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Reviewed-by: Stefan Haberland <sth@linux.ibm.com>
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Signed-off-by: Jan Höppner <hoeppner@linux.ibm.com>
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Signed-off-by: Marc Hartmayer <mhartmay@linux.ibm.com>
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---
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zipl/include/zipl.h | 8 ++++----
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zipl/src/boot.c | 4 ++--
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zipl/src/bootmap.c | 6 +++---
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3 files changed, 9 insertions(+), 9 deletions(-)
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--- a/zipl/include/zipl.h
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+++ b/zipl/include/zipl.h
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@@ -19,13 +19,12 @@
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#define ZIPL_MAGIC_SIZE 4
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#define DISK_LAYOUT_ID 0x00000001
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+#define STAGE3_ENTRY 0xa000UL
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#define IMAGE_ENTRY 0x10000UL
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#define IMAGE_ENTRY_KDUMP 0x10010UL
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-#define ZIPL_STAGE2_LOAD_ADDRESS 0x2000UL
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-#define ZIPL_STAGE3_ENTRY_ADDRESS 0xa000UL
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-#define DEFAULT_STAGE3_ADDRESS 0xa000UL
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-#define DEFAULT_STAGE3_PARAMS_ADDRESS 0x9000UL
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+#define STAGE2_LOAD_ADDRESS 0x2000UL
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+#define STAGE3_LOAD_ADDRESS 0xa000UL
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#define IMAGE_LOAD_ADDRESS IMAGE_ENTRY
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#define ADDRESS_LIMIT 0x80000000UL
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@@ -38,6 +37,7 @@
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#define STAGE3_HEAP_ADDRESS 0x2000UL
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#define STAGE3_STACK_SIZE 0x1000UL
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#define STAGE3_STACK_ADDRESS 0xF000UL
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+#define STAGE3_PARAMS_ADDRESS 0x9000UL
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#define PSW_ADDRESS_MASK 0x000000007fffffffUL
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#define PSW_LOAD 0x0008000080000000UL
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--- a/zipl/src/boot.c
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+++ b/zipl/src/boot.c
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@@ -195,7 +195,7 @@ boot_init_fba_stage1b(struct boot_fba_st
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stage1b->locdata[i].blocknr =
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(uint32_t) stage2_list[i].linear.block;
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stage1b->locread[i].read.address_lo =
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- ZIPL_STAGE2_LOAD_ADDRESS + i * FBA_BLK_SIZE;
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+ STAGE2_LOAD_ADDRESS + i * FBA_BLK_SIZE;
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}
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/* Terminate CCW chain */
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stage1b->locread[i - 1].read.flags &= ~CCW_FLAG_CC;
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@@ -220,7 +220,7 @@ boot_init_eckd_stage1b(struct boot_eckd_
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stage1b->seek[i].head = stage2_list[i].chs.head |
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((stage2_list[i].chs.cyl >> 12) & 0xfff0);
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stage1b->seek[i].sec = stage2_list[i].chs.sec;
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- stage1b->ssrt[i].read.address_lo = ZIPL_STAGE2_LOAD_ADDRESS +
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+ stage1b->ssrt[i].read.address_lo = STAGE2_LOAD_ADDRESS +
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i * stage2_list[i].chs.size;
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stage1b->ssrt[i].read.flags = CCW_FLAG_CC | CCW_FLAG_SLI;
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}
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--- a/zipl/src/bootmap.c
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+++ b/zipl/src/bootmap.c
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@@ -627,7 +627,7 @@ add_ipl_program(int fd, struct job_ipl_d
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}
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/* Add stage 3 loader to bootmap */
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- rc = add_component_file(fd, ZIPL_STAGE3_PATH, DEFAULT_STAGE3_ADDRESS,
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+ rc = add_component_file(fd, ZIPL_STAGE3_PATH, STAGE3_LOAD_ADDRESS,
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signature_size, VOID_ADD(table, offset), 1,
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info, target, &comp_loc[comp_nr]);
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if (rc) {
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@@ -654,7 +654,7 @@ add_ipl_program(int fd, struct job_ipl_d
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}
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rc = add_component_buffer(fd, stage3_params, stage3_params_size,
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(component_data) (uint64_t)
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- DEFAULT_STAGE3_PARAMS_ADDRESS,
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+ STAGE3_PARAMS_ADDRESS,
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VOID_ADD(table, offset), info,
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&comp_loc[comp_nr], component_load);
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free(stage3_params);
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@@ -792,7 +792,7 @@ add_ipl_program(int fd, struct job_ipl_d
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create_component_entry(VOID_ADD(table, offset), NULL,
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component_execute,
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(component_data) (uint64_t)
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- (ZIPL_STAGE3_ENTRY_ADDRESS | PSW_LOAD),
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+ (STAGE3_ENTRY | PSW_LOAD),
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info);
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/* Write component table */
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rc = disk_write_block_aligned(fd, table, info->phy_block_size,
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