Accepting request 792036 from home:markkp:branches:Base:System
- Added s390-tools-sles15sp2-01-cpumf-add-new-deflate-counters-for-z15.patch (bsc#1167853) lscpumf: New z15 CPU-MF counters not available, so add the definition for the new deflate counters. - Updated read_values (bsc#1167815, jsc#SLE-10675) * Differentiate between IBM Z and IBM LinuxONE machines * Query and print the status of secure boot for the LPAR. OBS-URL: https://build.opensuse.org/request/show/792036 OBS-URL: https://build.opensuse.org/package/show/Base:System/s390-tools?expand=0&rev=95
This commit is contained in:
Mark Post
Git OBS Bridge
parent
ec45615fc4
commit
ce4e84587f
167
read_values.c
167
read_values.c
@ -1,6 +1,6 @@
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/********************************************************************************/
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/* */
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/* Copyright (C) 2014-2015, 2019 SUSE LLC */
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/* Copyright (C) 2014-2015, 2019-2020 SUSE LLC */
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/* */
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/* All rights reserved.
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@ -15,6 +15,7 @@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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*/
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#define _GNU_SOURCE
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#include <sys/utsname.h>
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#include <ctype.h>
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#include <stddef.h>
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#include <stdio.h>
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@ -36,9 +37,9 @@ enum datatypes {
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#define WITHOUT_KEY 0
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#define WITH_KEY 1
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static char *versionstring = "Version 1.0 2015-10-12 13:31";
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static char *versionstring = "Version 1.0.2 2020-03-30 23:30";
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static char *version = "1.0.0";
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static char *version = "1.0.2";
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void *configuration_handle = NULL;
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int layers = -1;
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@ -47,33 +48,39 @@ int layers = -1;
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* List of machine types
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*/
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struct machinetype {
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enum qc_model_families model_families;
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char *typenumber;
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char *fullname;
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} machinetypes[] = {
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{ "2064", "2064 = z900 IBM eServer zSeries 900" },
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{ "2066", "2066 = z800 IBM eServer zSeries 800" },
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{ "2084", "2084 = z990 IBM eServer zSeries 990" },
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{ "2086", "2086 = z890 IBM eServer zSeries 890" },
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{ "2094", "2094 = z9-EC IBM System z9 Enterprise Class" },
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{ "2096", "2096 = z9-BC IBM System z9 Business Class" },
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{ "2097", "2097 = z10-EC IBM System z10 Enterprise Class" },
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{ "2098", "2098 = z10-BC IBM System z10 Business Class" },
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{ "2817", "2817 = z196 IBM zEnterprise 196" },
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{ "2818", "2818 = z114 IBM zEnterprise 114" },
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{ "2827", "2827 = z12-EC IBM zEnterprise EC12" },
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{ "2828", "2828 = z12-BC IBM zEnterprise BC12" },
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{ "2964", "2964 = z13 IBM z13" },
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{ "2965", "2965 = z13s IBM z13s (single frame)" },
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{ "3906", "3906 = z14 IBM z14" },
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{ "3907", "3907 = z14 ZR1 IBM z14 ZR1" },
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{ "8561", "8561 = z15 IBM z15" },
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{ QC_TYPE_FAMILY_IBMZ, "2064", "2064 = z900 IBM eServer zSeries 900" },
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{ QC_TYPE_FAMILY_IBMZ, "2066", "2066 = z800 IBM eServer zSeries 800" },
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{ QC_TYPE_FAMILY_IBMZ, "2084", "2084 = z990 IBM eServer zSeries 990" },
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{ QC_TYPE_FAMILY_IBMZ, "2086", "2086 = z890 IBM eServer zSeries 890" },
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{ QC_TYPE_FAMILY_IBMZ, "2094", "2094 = z9-EC IBM System z9 Enterprise Class" },
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{ QC_TYPE_FAMILY_IBMZ, "2096", "2096 = z9-BC IBM System z9 Business Class" },
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{ QC_TYPE_FAMILY_IBMZ, "2097", "2097 = z10-EC IBM System z10 Enterprise Class" },
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{ QC_TYPE_FAMILY_IBMZ, "2098", "2098 = z10-BC IBM System z10 Business Class" },
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{ QC_TYPE_FAMILY_IBMZ, "2817", "2817 = z196 IBM zEnterprise 196" },
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{ QC_TYPE_FAMILY_IBMZ, "2818", "2818 = z114 IBM zEnterprise 114" },
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{ QC_TYPE_FAMILY_IBMZ, "2827", "2827 = z12-EC IBM zEnterprise EC12" },
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{ QC_TYPE_FAMILY_IBMZ, "2828", "2828 = z12-BC IBM zEnterprise BC12" },
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{ QC_TYPE_FAMILY_IBMZ, "2964", "2964 = z13 IBM z13" },
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{ QC_TYPE_FAMILY_LINUXONE, "2964", "2964 = IBM LinuxONE Emperor" },
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{ QC_TYPE_FAMILY_IBMZ, "2965", "2965 = z13s IBM z13s (single frame)" },
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{ QC_TYPE_FAMILY_LINUXONE, "2965", "2965 = IBM LinuxONE Rockhopper" },
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{ QC_TYPE_FAMILY_IBMZ, "3906", "3906 = z14 IBM z14" },
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{ QC_TYPE_FAMILY_LINUXONE, "3906", "3906 = IBM LinuxONE Emperor II" },
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{ QC_TYPE_FAMILY_IBMZ, "3907", "3907 = z14 ZR1 IBM z14 ZR1" },
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{ QC_TYPE_FAMILY_LINUXONE, "3907", "3907 = IBM LinuxONE Rockhopper II" },
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{ QC_TYPE_FAMILY_IBMZ, "8561", "8561 = z15 IBM z15" },
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{ QC_TYPE_FAMILY_LINUXONE, "8561", "8561 = IBM LinuxONE III" },
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};
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int debug = 0;
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/******************************************************************************/
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/* */
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/* */
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/* Print the program version */
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/* */
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/******************************************************************************/
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void print_version()
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@ -126,7 +133,7 @@ float result_float = 0.0;
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}
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} /* endif */
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else {
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printf("Fehler: erg = %d, result_string = %s \n", erg, (result_string == NULL? "NULL": result_string));
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printf("Error: erg = %d, result_string = %s \n", erg, (result_string == NULL? "NULL": result_string));
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/* TODO qc_get_attribute_string returned error */
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}
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} /* print_attribute */
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@ -172,12 +179,24 @@ void print_cputype()
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int i, search;
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int erg;
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const char *cpu_type = NULL;
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int family_type = -1;
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/*
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* First find out whether we run on an IBM Z, or a LinuxONE system
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*/
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erg = qc_get_attribute_int(configuration_handle, qc_type_family, 0, &family_type);
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if (erg <= 0 || family_type == -1) {
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printf("Error reading family type\n");
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return;
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} /* endif */
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/*
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* Now get the machine ID
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*/
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erg = qc_get_attribute_string(configuration_handle, qc_type, 0, &cpu_type);
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if (erg == 1 && cpu_type != NULL) {
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for (i = 0, search = 1; (i < sizeof(machinetypes) / sizeof(struct machinetype)) && search ; i++)
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{
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if (strcmp(cpu_type, machinetypes[i].typenumber) == 0) {
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if ((family_type == machinetypes[i].model_families) && (strcmp(cpu_type, machinetypes[i].typenumber) == 0)) {
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printf("%s\n", machinetypes[i].fullname);
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search = 0;
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} /* endif */
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@ -218,13 +237,13 @@ void print_scc()
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print_version();
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print_attribute("Type", 0, qc_type, string, WITH_KEY);
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print_attribute("Sequence Code", 0, qc_sequence_code, string, WITH_KEY);
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print_attribute("CPUs Total", 0, qc_num_cpu_total, integer, WITH_KEY);
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print_attribute("CPUs IFL", 0, qc_num_cpu_total, integer, WITH_KEY);
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print_attribute("CPUs Total", 0, qc_num_ifl_total, integer, WITH_KEY);
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print_attribute("CPUs IFL", 0, qc_num_ifl_total, integer, WITH_KEY);
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print_attribute("LPAR Number", 1, qc_partition_number, integer, WITH_KEY);
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print_attribute("LPAR Name", 1, qc_layer_name, string, WITH_KEY);
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print_attribute("LPAR Characteristics", 1, qc_partition_char, string, WITH_KEY);
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print_attribute("LPAR CPUs Total", 1, qc_num_cpu_total, integer, WITH_KEY);
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print_attribute("LPAR CPUs IFL", 1, qc_num_cpu_total, integer, WITH_KEY);
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print_attribute("LPAR CPUs Total", 1, qc_num_ifl_total, integer, WITH_KEY);
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print_attribute("LPAR CPUs IFL", 1, qc_num_ifl_total, integer, WITH_KEY);
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if (layers > 2) {
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/*
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* This means, that eather zKVM or z/Vm is running
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@ -237,6 +256,81 @@ if (layers > 2) {
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return;
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} /* print_scc */
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/******************************************************************************/
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/* */
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/* print out whether secure boot is enabled */
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/* */
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/******************************************************************************/
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void print_secure_mode()
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{
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int erg;
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int release_major;
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int release_sub;
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int release_minor;
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const char *cpu_type = NULL;
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/*
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* First we have to check whether we have the appropriate kernel Level (>= 5.3)
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*/
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struct utsname uts;
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erg = uname(&uts);
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if (erg != 0) {
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perror ("Error executing uname(): ");
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return;
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} /* endif */
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#if 0
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printf("sysname: %s\n", uts.sysname);
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printf("nodename: %s\n", uts.nodename);
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printf("release: %s\n", uts.release);
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#endif
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/*
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* A release number looks like: m.s.mi
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* where m, s, mi are numbers with one ore more digits
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* Minimum kernel version is 5.3
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*/
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erg = sscanf(uts.release,"%d.%d.%d-%*s", &release_major, &release_sub, &release_minor);
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if ( release_major < 5 ) {
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goto return_does_not_exist;
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}
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if ( release_sub < 3 ) {
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goto return_does_not_exist;
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}
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#if 0
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printf("Translated successfully: %d\n", erg);
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printf("release_major: %d\n", release_major);
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printf("release_sub: %d\n", release_sub);
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printf("release_minor: %d\n", release_minor);
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printf("version: %s\n", uts.version);
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printf("machine: %s\n", uts.machine);
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printf("Print_secure called\n");
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#endif
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/*
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* Only the following machines support secure boot: z14, z14 ZR1, z15
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* 3906, 3907, 8561
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*/
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erg = qc_get_attribute_string(configuration_handle, qc_type, 0, &cpu_type);
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if (erg == 1 && cpu_type != NULL) {
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if (strcmp(cpu_type, "3906") != 0) {
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if (strcmp(cpu_type, "3907") != 0) {
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if (strcmp(cpu_type, "8561") != 0) {
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goto return_does_not_exist;
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} /* endif */
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} /* endif */
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} /* endif */
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} /* endif */
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print_attribute("Secure mode on", 1, qc_has_secure, integer, WITH_KEY);
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print_attribute("Secure mode used", 1, qc_secure, integer, WITH_KEY);
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return;
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return_does_not_exist:
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/*
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* Software or hardware does not support secure boot.
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*/
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puts("Secure mode on: 0\nSecure mode used: 0");
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return;
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} /* print_secure_mode */
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/******************************************************************************/
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/* */
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/* print out the uuid for this machine */
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@ -267,7 +361,7 @@ return;
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void print_user_attribute(char *key, char *attribute_param, int layer)
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{
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return;
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} /* print_uuid */
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} /* print_user_attribute */
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/******************************************************************************/
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@ -285,6 +379,7 @@ puts("help:\n\
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-h this help\n\
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-L <keyword> List the requested list (Attribute, Recognised)\n\
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-s create Info for SCC\n\
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-S report whether secure boot is switched on\n\
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-u create uuid\n\
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-V print version string\n\
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");
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@ -312,6 +407,7 @@ int opt;
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int read_sysinfo_opt;
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int print_attr;
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int print_cpu;
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int print_secure;
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int print_help;
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int list_attr;
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int create_scc;
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@ -325,6 +421,7 @@ void *configuration_handle_tmp = NULL;
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read_sysinfo_opt =
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print_attr =
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print_cpu =
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print_secure =
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print_help =
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list_attr =
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create_scc =
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@ -336,7 +433,7 @@ void *configuration_handle_tmp = NULL;
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print_cpu++;
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} /* endif */
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else {
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while ((opt = getopt(argc, argv, "a:cd:hL:suV")) != -1) {
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while ((opt = getopt(argc, argv, "a:cd:hL:sSuV")) != -1) {
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switch (opt)
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{
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case 'a':
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@ -367,6 +464,10 @@ void *configuration_handle_tmp = NULL;
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read_sysinfo_opt++;
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create_scc++;
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break;
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case 'S': /* print out whether secure boot is enabled */
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read_sysinfo_opt++;
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print_secure++;
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break;
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case 'u': /* create UUID */
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read_sysinfo_opt++;
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create_uuid++;
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@ -391,8 +492,8 @@ void *configuration_handle_tmp = NULL;
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return -erg;
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} /* endif */
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} /* endif */
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if ((print_attr + print_cpu + list_attr + create_scc + create_uuid) > 1) {
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fputs("Only one of the options a, c, L, s or u can be specified.",stderr);
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if ((print_attr + print_cpu + print_secure + list_attr + create_scc + create_uuid) > 1) {
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fputs("Only one of the options a, c, L, s, S or u can be specified.\n",stderr);
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return 1;
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} /* endif */
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/* still not im[plemented thatfore set to zero */
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@ -405,6 +506,10 @@ void *configuration_handle_tmp = NULL;
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print_cputype();
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goto main_exit;
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} /* endif */
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if (print_secure != 0) {
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print_secure_mode();
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goto main_exit;
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} /* endif */
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if (list_attr != 0) {
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list(list_attribute_param);
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goto main_exit;
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@ -0,0 +1,442 @@
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Subject: [PATCH] [BZ 184585] cpumf/data: Add new deflate counters for IBM z15
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From: Thomas Richter <tmricht@linux.ibm.com>
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Description: lscpumf: New z15 CPU-MF counters not available
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Symptom: Command lscpumf -c does not show the new
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deflate counters on IBM z15.
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Problem: The new counter names have not been published
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in document SA23-2261-06 by the time te code was
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release.
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Solution: Add the definition for the new deflate counters.
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Reproduction: Run command lscpumf -c and check for counters
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rf7, rfc, r107 and r108.
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Upstream-ID: 5d2871d626de6c2b3ab6b12783b87a8b3564cb56
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Problem-ID: 184585
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Upstream-Description:
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cpumf/data: Add new deflate counters for IBM z15
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Add support for new deflate counters:
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- Counter 247: cycles CPU spent obtaining access to Deflate unit
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- Counter 252: cycles CPU is using Deflate unit
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- Counter 264: Increments by one for every DEFLATE CONVERSION CALL
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instruction executed.
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- Counter 265: Increments by one for every DEFLATE CONVERSION CALL
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instruction executed that ended in Condition Codes
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0, 1 or 2.
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|
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Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
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Signed-off-by: Jan Hoeppner <hoeppner@linux.ibm.com>
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|
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|
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Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
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---
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cpumf/Makefile | 3
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cpumf/data/cpum-cf-extended-z15.ctr | 376 ++++++++++++++++++++++++++++++++++++
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cpumf/data/cpum-cf-hw-counter.map | 5
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3 files changed, 380 insertions(+), 4 deletions(-)
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|
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--- a/cpumf/Makefile
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+++ b/cpumf/Makefile
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@@ -9,7 +9,8 @@ DATA_FILES = cpum-cf-hw-counter.map \
|
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cpum-cf-csvn-12345.ctr cpum-cf-csvn-6.ctr \
|
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cpum-cf-extended-z10.ctr cpum-cf-extended-z196.ctr \
|
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cpum-cf-extended-zEC12.ctr cpum-sf-modes.ctr \
|
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- cpum-cf-extended-z13.ctr cpum-cf-extended-z14.ctr
|
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+ cpum-cf-extended-z13.ctr cpum-cf-extended-z14.ctr \
|
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+ cpum-cf-extended-z15.ctr
|
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LIB_FILES = bin/cpumf_helper
|
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USRBIN_SCRIPTS = bin/lscpumf
|
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USRSBIN_SCRIPTS = bin/chcpumf
|
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--- /dev/null
|
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+++ b/cpumf/data/cpum-cf-extended-z15.ctr
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@@ -0,0 +1,376 @@
|
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+# Counter decriptions for the
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||||
+# IBM z14 extended counter and MT-diagnostic counter set
|
||||
+#
|
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+# Notes for transactional-execution mode symbolic names:
|
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+# TX .. transactional-execution mode
|
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+# NC .. nonconstrained
|
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+# C .. constrained
|
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+#
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+# Undefined counters in the extended counter set:
|
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+# 142
|
||||
+# 158-161
|
||||
+# 176-223
|
||||
+# 227-231
|
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+# 233-242
|
||||
+# 246-255
|
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+# Undefined counters in the MT-diagnostic counter set:
|
||||
+# 450-495
|
||||
+#
|
||||
+#
|
||||
+# Extended Counter Set
|
||||
+# ---------------------------------------------------------------------
|
||||
+Counter:128 Name:L1D_RO_EXCL_WRITES
|
||||
+Short-Description:L1D Read-only Exclusive Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache where the line was
|
||||
+originally in a Read-Only state in the cache but has been updated
|
||||
+to be in the Exclusive state that allows stores to the cache line
|
||||
+.
|
||||
+Counter:129 Name:DTLB2_WRITES
|
||||
+Short-Description:DTLB2 Writes
|
||||
+Description:
|
||||
+A translation has been written into The Translation Lookaside
|
||||
+Buffer 2 (TLB2) and the request was made by the data cache
|
||||
+.
|
||||
+Counter:130 Name:DTLB2_MISSES
|
||||
+Short-Description:DTLB2 Misses
|
||||
+Description:
|
||||
+A TLB2 miss is in progress for a request made by the data cache.
|
||||
+Incremented by one for every TLB2 miss in progress for the Level-1
|
||||
+Data cache on this cycle
|
||||
+.
|
||||
+Counter:131 Name:DTLB2_HPAGE_WRITES
|
||||
+Short-Description:DTLB2 One-Megabyte Page Writes
|
||||
+Description:
|
||||
+A translation entry was written into the Combined Region and Segment
|
||||
+Table Entry array in the Level-2 TLB for a one-megabyte page
|
||||
+.
|
||||
+Counter:132 Name:DTLB2_GPAGE_WRITES
|
||||
+Short-Description:DTLB2 Two-Gigabyte Page Writes
|
||||
+Description:
|
||||
+A translation entry for a two-gigabyte page was written into the
|
||||
+Level-2 TLB
|
||||
+.
|
||||
+Counter:133 Name:L1D_L2D_SOURCED_WRITES
|
||||
+Short-Description:L1D L2D Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the
|
||||
+returned cache line was sourced from the Level-2 Data cache
|
||||
+.
|
||||
+Counter:134 Name:ITLB2_WRITES
|
||||
+Short-Description:ITLB2 Writes
|
||||
+Description:
|
||||
+A translation entry has been written into the Translation Lookaside
|
||||
+Buffer 2 (TLB2) and the request was made by the instruction cache
|
||||
+.
|
||||
+Counter:135 Name:ITLB2_MISSES
|
||||
+Short-Description:ITLB2 Misses
|
||||
+Description:
|
||||
+A TLB2 miss is in progress for a request made by the instruction cache.
|
||||
+Incremented by one for every TLB2 miss in progress for the Level-1
|
||||
+Instruction cache in a cycle
|
||||
+.
|
||||
+Counter:136 Name:L1I_L2I_SOURCED_WRITES
|
||||
+Short-Description:L1I L2I Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from the Level-2 Instruction cache
|
||||
+.
|
||||
+Counter:137 Name:TLB2_PTE_WRITES
|
||||
+Short-Description:TLB2 PTE Writes
|
||||
+Description:
|
||||
+A translation entry was written into the Page Table Entry array in the
|
||||
+Level-2 TLB
|
||||
+.
|
||||
+Counter:138 Name:TLB2_CRSTE_WRITES
|
||||
+Short-Description:TLB2 CRSTE Writes
|
||||
+Description:
|
||||
+Translation entries were written into the Combined Region and Segment
|
||||
+Table Entry array and the Page Table Entry array in the Level-2 TLB
|
||||
+.
|
||||
+Counter:139 Name:TLB2_ENGINES_BUSY
|
||||
+Short-Description:TLB2 Engines Busy
|
||||
+Description:
|
||||
+The number of Level-2 TLB translation engines busy in a cycle
|
||||
+.
|
||||
+Counter:140 Name:TX_C_TEND
|
||||
+Short-Description:Completed TEND instructions in constrained TX mode
|
||||
+Description:
|
||||
+A TEND instruction has completed in a constrained transactional-execution
|
||||
+mode
|
||||
+.
|
||||
+Counter:141 Name:TX_NC_TEND
|
||||
+Short-Description:Completed TEND instructions in non-constrained TX mode
|
||||
+Description:
|
||||
+A TEND instruction has completed in a non-constrained
|
||||
+transactional-execution mode
|
||||
+.
|
||||
+Counter:143 Name:L1C_TLB2_MISSES
|
||||
+Short-Description:L1C TLB2 Misses
|
||||
+Description:
|
||||
+Increments by one for any cycle where a level-1 cache or level-2 TLB miss
|
||||
+is in progress
|
||||
+.
|
||||
+Counter:144 Name:L1D_ONCHIP_L3_SOURCED_WRITES
|
||||
+Short-Description:L1D On-Chip L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an On-Chip Level-3 cache without intervention
|
||||
+.
|
||||
+Counter:145 Name:L1D_ONCHIP_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1D On-Chip Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from On-Chip memory
|
||||
+.
|
||||
+Counter:146 Name:L1D_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1D On-Chip L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an On-Chip Level-3 cache with intervention
|
||||
+.
|
||||
+Counter:147 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES
|
||||
+Short-Description:L1D On-Cluster L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from On-Cluster Level-3 cache withountervention
|
||||
+.
|
||||
+Counter:148 Name:L1D_ONCLUSTER_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1D On-Cluster Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an On-Cluster memory
|
||||
+.
|
||||
+Counter:149 Name:L1D_ONCLUSTER_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1D On-Cluster L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an On-Cluster Level-3 cache with intervention
|
||||
+.
|
||||
+Counter:150 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES
|
||||
+Short-Description:L1D Off-Cluster L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an Off-Cluster Level-3 cache without
|
||||
+intervention
|
||||
+.
|
||||
+Counter:151 Name:L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1D Off-Cluster Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from Off-Cluster memory
|
||||
+.
|
||||
+Counter:152 Name:L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1D Off-Cluster L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an Off-Cluster Level-3 cache with intervention
|
||||
+.
|
||||
+Counter:153 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES
|
||||
+Short-Description:L1D Off-Drawer L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an Off-Drawer Level-3 cache without
|
||||
+intervention
|
||||
+.
|
||||
+Counter:154 Name:L1D_OFFDRAWER_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1D Off-Drawer Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from Off-Drawer memory
|
||||
+.
|
||||
+Counter:155 Name:L1D_OFFDRAWER_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1D Off-Drawer L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from an Off-Drawer Level-3 cache with intervention
|
||||
+.
|
||||
+Counter:156 Name:L1D_ONDRAWER_L4_SOURCED_WRITES
|
||||
+Short-Description:L1D On-Drawer L4 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from On-Drawer Level-4 cache
|
||||
+.
|
||||
+Counter:157 Name:L1D_OFFDRAWER_L4_SOURCED_WRITES
|
||||
+Short-Description:L1D Off-Drawer L4 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from Off-Drawer Level-4 cache
|
||||
+.
|
||||
+Counter:158 Name:L1D_ONCHIP_L3_SOURCED_WRITES_RO
|
||||
+Short-Description:L1D On-Chip L3 Sourced Writes read-only
|
||||
+Description:
|
||||
+A directory write to the Level-1 Data cache directory where the returned
|
||||
+cache line was sourced from On-Chip L3 but a read-only invalidate was
|
||||
+done to remove other copies of the cache line
|
||||
+.
|
||||
+Counter:162 Name:L1I_ONCHIP_L3_SOURCED_WRITES
|
||||
+Short-Description:L1I On-Chip L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache ine was sourced from an On-Chip Level-3 cache without
|
||||
+intervention
|
||||
+.
|
||||
+Counter:163 Name:L1I_ONCHIP_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1I On-Chip Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache ine was sourced from On-Chip memory
|
||||
+.
|
||||
+Counter:164 Name:L1I_ONCHIP_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1I On-Chip L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache ine was sourced from an On-Chip Level-3 cache with
|
||||
+intervention
|
||||
+.
|
||||
+Counter:165 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES
|
||||
+Short-Description:L1I On-Cluster L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from an On-Cluster Level-3 cache without
|
||||
+intervention
|
||||
+.
|
||||
+Counter:166 Name:L1I_ONCLUSTER_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1I On-Cluster Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from an On-Cluster memory
|
||||
+.
|
||||
+Counter:167 Name:L1I_ONCLUSTER_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1I On-Cluster L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from On-Cluster Level-3 cache with
|
||||
+intervention
|
||||
+.
|
||||
+Counter:168 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES
|
||||
+Short-Description:L1I Off-Cluster L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from an Off-Cluster Level-3 cache without
|
||||
+intervention
|
||||
+.
|
||||
+Counter:169 Name:L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1I Off-Cluster Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from Off-Cluster memory
|
||||
+.
|
||||
+Counter:170 Name:L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1I Off-Cluster L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from an Off-Cluster Level-3 cache with
|
||||
+intervention
|
||||
+.
|
||||
+Counter:171 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES
|
||||
+Short-Description:L1I Off-Drawer L3 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from an Off-Drawer Level-3 cache without
|
||||
+intervention
|
||||
+.
|
||||
+Counter:172 Name:L1I_OFFDRAWER_MEMORY_SOURCED_WRITES
|
||||
+Short-Description:L1I Off-Drawer Memory Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from Off-Drawer memory
|
||||
+.
|
||||
+Counter:173 Name:L1I_OFFDRAWER_L3_SOURCED_WRITES_IV
|
||||
+Short-Description:L1I Off-Drawer L3 Sourced Writes with Intervention
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from an Off-Drawer Level-3 cache with
|
||||
+intervention
|
||||
+.
|
||||
+Counter:174 Name:L1I_ONDRAWER_L4_SOURCED_WRITES
|
||||
+Short-Description:L1I On-Drawer L4 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from On-Drawer Level-4 cache
|
||||
+.
|
||||
+Counter:175 Name:L1I_OFFDRAWER_L4_SOURCED_WRITES
|
||||
+Short-Description:L1I Off-Drawer L4 Sourced Writes
|
||||
+Description:
|
||||
+A directory write to the Level-1 Instruction cache directory where the
|
||||
+returned cache line was sourced from Off-Drawer Level-4 cache
|
||||
+.
|
||||
+Counter:224 Name:BCD_DFP_EXECUTION_SLOTS
|
||||
+Short-Description:BCD DFP Execution Slots
|
||||
+Description:
|
||||
+Count of floating point execution slots used for finished Binary Coded
|
||||
+Decimal to Decimal Floating Point conversions. Instructions: CDZT,
|
||||
+CXZT, CZDT, CZXT
|
||||
+.
|
||||
+Counter:225 Name:VX_BCD_EXECUTION_SLOTS
|
||||
+Short-Description:VX BCD Execution Slots
|
||||
+Description:
|
||||
+Count of floating point execution slots used for finished vector arithmetic
|
||||
+Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP,
|
||||
+VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG
|
||||
+.
|
||||
+Counter:226 Name:DECIMAL_INSTRUCTIONS
|
||||
+Short-Description:Decimal Instructions
|
||||
+Description:
|
||||
+Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED,
|
||||
+EDMK, MP, SRP, SP, ZAP
|
||||
+.
|
||||
+Counter:232 Name:LAST_HOST_TRANSLATIONS
|
||||
+Short-Description:Last host translation done
|
||||
+Description:
|
||||
+Last Host Translation done
|
||||
+.
|
||||
+Counter:243 Name:TX_NC_TABORT
|
||||
+Short-Description:Aborted transactions in non-constrained TX mode
|
||||
+Description:
|
||||
+A transaction abort has occurred in a non-constrained
|
||||
+transactional-execution mode
|
||||
+.
|
||||
+Counter:244 Name:TX_C_TABORT_NO_SPECIAL
|
||||
+Short-Description:Aborted transactions in constrained TX mode not using special completion logic
|
||||
+Description:
|
||||
+A transaction abort has occurred in a constrained transactional-execution
|
||||
+mode and the CPU is not using any special logic to allow the transaction
|
||||
+to complete
|
||||
+.
|
||||
+Counter:245 Name:TX_C_TABORT_SPECIAL
|
||||
+Short-Description:Aborted transactions in constrained TX mode using special completion logic
|
||||
+Description:
|
||||
+A transaction abort has occurred in a constrained transactional-execution
|
||||
+mode and the CPU is using special logic to allow the transaction to
|
||||
+complete
|
||||
+.
|
||||
+Counter:247 Name:DFLT_ACCESS
|
||||
+Short-Description:Cycles CPU spent obtaining access to Deflate unit
|
||||
+Description:
|
||||
+Cycles CPU spent obtaining access to Deflate unit
|
||||
+.
|
||||
+Counter:252 Name:DFLT_CYCLES
|
||||
+Short-Description:Cycles CPU is using Deflate unit
|
||||
+Description:
|
||||
+Cycles CPU is using Deflate unit
|
||||
+.
|
||||
+Counter:264 Name:DFLT_CC
|
||||
+Short-Description:Increments by one for every DEFLATE CONVERSION CALL instruction executed
|
||||
+Description:
|
||||
+Increments by one for every DEFLATE CONVERSION CALL instruction executed
|
||||
+.
|
||||
+Counter:265 Name:DFLT_CCERROR
|
||||
+Short-Description:Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2
|
||||
+Description:
|
||||
+Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2
|
||||
+.
|
||||
+#
|
||||
+# MT-diagnostic counter set
|
||||
+# ---------------------------------------------------------------------
|
||||
+Counter:448 Name:MT_DIAG_CYCLES_ONE_THR_ACTIVE
|
||||
+Short-Description:Cycle count with one thread active
|
||||
+Description:
|
||||
+Cycle count with one thread active
|
||||
+.
|
||||
+Counter:449 Name:MT_DIAG_CYCLES_TWO_THR_ACTIVE
|
||||
+Short-Description:Cycle count with two threads active
|
||||
+Description:
|
||||
+Cycle count with two threads active
|
||||
+.
|
||||
--- a/cpumf/data/cpum-cf-hw-counter.map
|
||||
+++ b/cpumf/data/cpum-cf-hw-counter.map
|
||||
@@ -28,7 +28,6 @@
|
||||
2965 => 'cpum-cf-extended-z13.ctr',
|
||||
3906 => 'cpum-cf-extended-z14.ctr',
|
||||
3907 => 'cpum-cf-extended-z14.ctr',
|
||||
- # Identical with z14
|
||||
- 8561 => 'cpum-cf-extended-z14.ctr',
|
||||
- 8562 => 'cpum-cf-extended-z14.ctr',
|
||||
+ 8561 => 'cpum-cf-extended-z15.ctr',
|
||||
+ 8562 => 'cpum-cf-extended-z15.ctr',
|
||||
};
|
||||
@ -1,3 +1,14 @@
|
||||
-------------------------------------------------------------------
|
||||
Tue Apr 7 18:52:02 UTC 2020 - Mark Post <mpost@suse.com>
|
||||
|
||||
- Added s390-tools-sles15sp2-01-cpumf-add-new-deflate-counters-for-z15.patch
|
||||
(bsc#1167853)
|
||||
lscpumf: New z15 CPU-MF counters not available, so add the
|
||||
definition for the new deflate counters.
|
||||
- Updated read_values (bsc#1167815, jsc#SLE-10675)
|
||||
* Differentiate between IBM Z and IBM LinuxONE machines
|
||||
* Query and print the status of secure boot for the LPAR.
|
||||
|
||||
-------------------------------------------------------------------
|
||||
Thu Mar 19 19:22:19 UTC 2020 - Mark Post <mpost@suse.com>
|
||||
|
||||
|
||||
@ -187,6 +187,7 @@ Patch97: s390-tools-sles15sp2-01-zipl-Add-missing-options-to-help-output.
|
||||
Patch98: s390-tools-sles15sp2-02-zipl-allow-stand-alone-secure-option-on-command-l.patch
|
||||
Patch99: s390-tools-sles15sp2-03-zipl-correct-secure-boot-config-handling.patch
|
||||
Patch100: s390-tools-sles15sp2-04-zipl-fix-zipl.conf-man-page-example-for-secure-boot.patch
|
||||
Patch101: s390-tools-sles15sp2-01-cpumf-add-new-deflate-counters-for-z15.patch
|
||||
|
||||
# SUSE patches
|
||||
Patch900: s390-tools-sles12-zipl_boot_msg.patch
|
||||
|
||||
Loading…
Reference in New Issue
Block a user