From 0060a0156a098e90c692c9432f84c47295bbfc4a422f47c9bc369a9e7f62fe51 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Mon, 19 Oct 2020 09:00:01 +0000 Subject: [PATCH] Accepting request 840225 from hardware:boot:staging OBS-URL: https://build.opensuse.org/request/show/840225 OBS-URL: https://build.opensuse.org/package/show/hardware:boot/u-boot?expand=0&rev=104 --- ...-XXX-openSUSE-XXX-Prepend-partition-.patch | 2 +- ...-Revert-Revert-omap3-Use-raw-SPL-by-.patch | 6 +- ...-rpi-Use-firmware-provided-device-tr.patch | 36 +- ...-Temp-workaround-for-Chromebook-snow.patch | 6 +- ...-tools-zynqmpbif-Add-support-for-loa.patch | 2 +- ...-boo-1123170-Remove-ubifs-support-fr.patch | 23 +- ...-boo-1144161-Remove-nand-mtd-spi-dfu.patch | 28 +- 0008-Kconfig-add-btrfs-to-distro-boot.patch | 6 +- ...-configs-Re-sync-with-CONFIG_DISTRO_.patch | 30 +- 0010-configs-am335x_evm-disable-BTRFS.patch | 6 +- ...-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch | 37 - ...-sunxi-dts-OrangePi-Zero-Add-SPI-ali.patch | 42 ++ ...-sunxi-dts-OrangePi-Zero-Enable-SPI-.patch | 29 + ...-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch | 66 -- ...-sunxi-Enable-SPI-support-on-Orange-.patch | 32 + ...-uboot-fs-btrfs-Fix-LZO-false-decomp.patch | 124 ---- ...-usb-xhci-Add-missing-cache-flush-in.patch | 35 - ...-usb-xhci-Use-only-32-bit-accesses-i.patch | 62 -- ...-pci-Move-some-PCIe-register-offset-.patch | 79 --- ...-rpi4-shorten-a-mapping-for-the-DRAM.patch | 27 - ...-rpi4-add-a-mapping-for-the-PCIe-XHC.patch | 70 -- ...-linux-bitfield.h-Add-primitives-for.patch | 77 --- ...-pci-Add-some-PCI-Express-capability.patch | 38 -- ...-pci-Add-driver-for-Broadcom-STB-PCI.patch | 646 ------------------ ...-config-Enable-support-for-the-XHCI-.patch | 138 ---- ...-arm-rpi-Add-function-to-trigger-VL8.patch | 117 ---- ...-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch | 85 --- ...-config-Enable-USB-Keyboard-support-.patch | 40 -- ...-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch | 56 -- _multibuild | 2 + u-boot-2020.04.tar.bz2 | 3 - u-boot-2020.04.tar.bz2.sig | Bin 586 -> 0 bytes u-boot-2020.10.tar.bz2 | 3 + u-boot-2020.10.tar.bz2.sig | Bin 0 -> 458 bytes u-boot.changes | 96 +++ u-boot.spec | 42 +- update_git.sh | 4 +- 37 files changed, 307 insertions(+), 1788 deletions(-) delete mode 100644 0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch create mode 100644 0011-sunxi-dts-OrangePi-Zero-Add-SPI-ali.patch create mode 100644 0012-sunxi-dts-OrangePi-Zero-Enable-SPI-.patch delete mode 100644 0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch create mode 100644 0013-sunxi-Enable-SPI-support-on-Orange-.patch delete mode 100644 0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch delete mode 100644 0014-usb-xhci-Add-missing-cache-flush-in.patch delete mode 100644 0015-usb-xhci-Use-only-32-bit-accesses-i.patch delete mode 100644 0016-pci-Move-some-PCIe-register-offset-.patch delete mode 100644 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch delete mode 100644 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch delete mode 100644 0019-linux-bitfield.h-Add-primitives-for.patch delete mode 100644 0020-pci-Add-some-PCI-Express-capability.patch delete mode 100644 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch delete mode 100644 0022-config-Enable-support-for-the-XHCI-.patch delete mode 100644 0023-arm-rpi-Add-function-to-trigger-VL8.patch delete mode 100644 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch delete mode 100644 0025-config-Enable-USB-Keyboard-support-.patch delete mode 100644 0026-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch delete mode 100644 u-boot-2020.04.tar.bz2 delete mode 100644 u-boot-2020.04.tar.bz2.sig create mode 100644 u-boot-2020.10.tar.bz2 create mode 100644 u-boot-2020.10.tar.bz2.sig diff --git a/0001-XXX-openSUSE-XXX-Prepend-partition-.patch b/0001-XXX-openSUSE-XXX-Prepend-partition-.patch index 2547e2b..a62605b 100644 --- a/0001-XXX-openSUSE-XXX-Prepend-partition-.patch +++ b/0001-XXX-openSUSE-XXX-Prepend-partition-.patch @@ -1,4 +1,4 @@ -From 5637f1acf10c604ef8f25d43eb4d4fa1d6d4b4e4 Mon Sep 17 00:00:00 2001 +From ccd4f771c00d944160654731d27f3654ec5edcc0 Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Wed, 13 Apr 2016 13:44:29 +0200 Subject: [PATCH] XXX openSUSE XXX: Prepend partition 3 (and 4 for chromebook diff --git a/0002-Revert-Revert-omap3-Use-raw-SPL-by-.patch b/0002-Revert-Revert-omap3-Use-raw-SPL-by-.patch index fb415fc..0e02923 100644 --- a/0002-Revert-Revert-omap3-Use-raw-SPL-by-.patch +++ b/0002-Revert-Revert-omap3-Use-raw-SPL-by-.patch @@ -1,4 +1,4 @@ -From 4a9ece206c304a7dd8d05797102f333a7ccb5777 Mon Sep 17 00:00:00 2001 +From 0e5ee623eb68459199c41161e67bffe422e89096 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Mon, 2 May 2016 23:25:07 +0200 Subject: [PATCH] Revert "Revert "omap3: Use raw SPL by default for mmc1"" @@ -9,10 +9,10 @@ This reverts commit 7fa75d0ac5502db813d109c1df7bd0da34688685. 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c -index 734fa9d9e6..a35451f195 100644 +index cb9d7fdb15..50dec906df 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c -@@ -132,8 +132,6 @@ void save_omap_boot_params(void) +@@ -133,8 +133,6 @@ void save_omap_boot_params(void) (boot_device <= MMC_BOOT_DEVICES_END)) { switch (boot_device) { case BOOT_DEVICE_MMC1: diff --git a/0003-rpi-Use-firmware-provided-device-tr.patch b/0003-rpi-Use-firmware-provided-device-tr.patch index 876c229..5cbd823 100644 --- a/0003-rpi-Use-firmware-provided-device-tr.patch +++ b/0003-rpi-Use-firmware-provided-device-tr.patch @@ -1,6 +1,6 @@ -From 224598332df1ec7783e5abdecb72482c7715f81e Mon Sep 17 00:00:00 2001 -From: Alexander Graf -Date: Wed, 21 Feb 2018 17:41:13 +0100 +From e3661467c146494f9a2bbdaa7ae25e9f07c6d24a Mon Sep 17 00:00:00 2001 +From: Guillaume Gardet +Date: Fri, 18 Sep 2020 15:27:37 +0200 Subject: [PATCH] rpi: Use firmware provided device tree Currently the firmware generates a device tree for us that we could @@ -28,7 +28,7 @@ Signed-off-by: Guillaume Gardet 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig -index cecc16cbfc..17a10f1ccc 100644 +index bba5e12b12..0241f4c6d3 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y @@ -37,11 +37,11 @@ index cecc16cbfc..17a10f1ccc 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-zero-w" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig -index 762a72a574..96236ab82f 100644 +index 1c2bbb29ce..9573e475f4 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y @@ -50,11 +50,11 @@ index 762a72a574..96236ab82f 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2836-rpi-2-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig -index 5ca31648f9..2f7c233e93 100644 +index b8a3d17f43..252df994e6 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y @@ -63,11 +63,11 @@ index 5ca31648f9..2f7c233e93 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig -index 51d5a717d5..a7e134fc48 100644 +index 9b281a4f15..1e9ee6122e 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y @@ -76,11 +76,11 @@ index 51d5a717d5..a7e134fc48 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig -index dbbc818e14..1b88bb9255 100644 +index b5ad53c37b..223fc03275 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y @@ -89,6 +89,6 @@ index dbbc818e14..1b88bb9255 100644 CONFIG_CMD_FS_UUID=y -CONFIG_OF_EMBED=y +CONFIG_OF_BOARD=y - CONFIG_DEFAULT_DEVICE_TREE="bcm2835-rpi-b" - CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" + CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/0004-Temp-workaround-for-Chromebook-snow.patch b/0004-Temp-workaround-for-Chromebook-snow.patch index 40767e7..f14f38f 100644 --- a/0004-Temp-workaround-for-Chromebook-snow.patch +++ b/0004-Temp-workaround-for-Chromebook-snow.patch @@ -1,4 +1,4 @@ -From 91c18e17e22e76454d0ed7f75a1a1ec6c6637084 Mon Sep 17 00:00:00 2001 +From 19be21a06d5b85f6be87c1ccd2631aff79e0e416 Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Mon, 9 Apr 2018 10:28:26 +0200 Subject: [PATCH] Temp workaround for Chromebook snow to avoid the 'unable to @@ -9,10 +9,10 @@ Subject: [PATCH] Temp workaround for Chromebook snow to avoid the 'unable to 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c -index 1224540811..5c1cac97e4 100644 +index 7702f4be3f..ff2cd946fc 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c -@@ -600,7 +600,8 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, +@@ -603,7 +603,8 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, cfg->host_caps |= MMC_MODE_4BIT; cfg->host_caps &= ~MMC_MODE_8BIT; } diff --git a/0005-tools-zynqmpbif-Add-support-for-loa.patch b/0005-tools-zynqmpbif-Add-support-for-loa.patch index b8088ae..737c8fc 100644 --- a/0005-tools-zynqmpbif-Add-support-for-loa.patch +++ b/0005-tools-zynqmpbif-Add-support-for-loa.patch @@ -1,4 +1,4 @@ -From f4562a3ff7fa2116a443cf040ed9ed878a7a2d11 Mon Sep 17 00:00:00 2001 +From c7f8d2ca5bf0464a9164f84b264dc39cd1e655ee Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Thu, 26 Apr 2018 13:30:32 +0200 Subject: [PATCH] tools: zynqmpbif: Add support for load=after diff --git a/0006-boo-1123170-Remove-ubifs-support-fr.patch b/0006-boo-1123170-Remove-ubifs-support-fr.patch index e3ac0a0..970de25 100644 --- a/0006-boo-1123170-Remove-ubifs-support-fr.patch +++ b/0006-boo-1123170-Remove-ubifs-support-fr.patch @@ -1,19 +1,19 @@ -From be3112208a9246eb6f0bd15947154db0bef65d26 Mon Sep 17 00:00:00 2001 -From: Guillaume GARDET -Date: Tue, 29 Jan 2019 11:38:12 +0100 +From 8731159e77b49b6d89cc4ae5364dfe10ffacc49e Mon Sep 17 00:00:00 2001 +From: Guillaume Gardet +Date: Fri, 18 Sep 2020 15:28:41 +0200 Subject: [PATCH] boo#1123170: Remove ubifs support from omap3_beagle to keep a small u-boot.img --- - configs/omap3_beagle_defconfig | 2 +- + configs/omap3_beagle_defconfig | 3 ++- include/configs/omap3_beagle.h | 1 - - 2 files changed, 1 insertion(+), 2 deletions(-) + 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig -index ed7cb8f2ff..03dc3b27d4 100644 +index 1447dab344..86c2435b62 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig -@@ -38,7 +38,6 @@ CONFIG_CMD_FS_UUID=y +@@ -43,7 +43,6 @@ CONFIG_CMD_FS_UUID=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)" @@ -21,19 +21,20 @@ index ed7cb8f2ff..03dc3b27d4 100644 # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y -@@ -73,6 +72,7 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +@@ -78,6 +77,8 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 - CONFIG_SPL_NAND_SIMPLE=y + CONFIG_DM_ETH=y ++CONFIG_SPL_NAND_SIMPLE=y +CONFIG_MTD_UBI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h -index bc8aa7adf5..ee1d36003e 100644 +index 6563335f91..bc19317387 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h -@@ -82,7 +82,6 @@ +@@ -81,7 +81,6 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ diff --git a/0007-boo-1144161-Remove-nand-mtd-spi-dfu.patch b/0007-boo-1144161-Remove-nand-mtd-spi-dfu.patch index 3bb1a10..902111a 100644 --- a/0007-boo-1144161-Remove-nand-mtd-spi-dfu.patch +++ b/0007-boo-1144161-Remove-nand-mtd-spi-dfu.patch @@ -1,23 +1,26 @@ -From 349eb7b2fb80724040951accfa440fe61b71bff8 Mon Sep 17 00:00:00 2001 +From cb0db60f92f6ac66898888dea5fbeef784b59354 Mon Sep 17 00:00:00 2001 From: Guillaume Gardet -Date: Mon, 16 Dec 2019 17:51:17 +0100 +Date: Fri, 18 Sep 2020 15:29:27 +0200 Subject: [PATCH] boo#1144161: Remove nand/mtd/spi/dfu/fastboot support from am335x_evm to keep a small u-boot.img --- - configs/am335x_evm_defconfig | 23 ++--------------------- - 1 file changed, 2 insertions(+), 21 deletions(-) + configs/am335x_evm_defconfig | 31 ++----------------------------- + 1 file changed, 2 insertions(+), 29 deletions(-) diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig -index 335aa8cfa1..ccb11c9b2a 100644 +index 0d814530d4..78202a55c7 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig -@@ -15,21 +15,16 @@ CONFIG_ARCH_MISC_INIT=y +@@ -17,25 +17,16 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_ETH_SUPPORT=y # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y +-CONFIG_SPL_NAND_DRIVERS=y +-CONFIG_SPL_NAND_ECC=y +-CONFIG_SPL_NAND_BASE=y +# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NET_SUPPORT=y CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL" @@ -30,20 +33,25 @@ index 335aa8cfa1..ccb11c9b2a 100644 -CONFIG_CMD_NAND=y +# CONFIG_CMD_DM is not set # CONFIG_CMD_SETEXPR is not set +-CONFIG_BOOTP_DNS2=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y - CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" -@@ -40,32 +35,19 @@ CONFIG_SPL_ENV_IS_NOWHERE=y + CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle" +@@ -47,38 +38,21 @@ CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CLK=y CONFIG_CLK_CDCE9XX=y +-CONFIG_DFU_TFTP=y -CONFIG_DFU_MMC=y -CONFIG_DFU_NAND=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y +-CONFIG_FASTBOOT_FLASH=y +-CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y @@ -54,6 +62,8 @@ index 335aa8cfa1..ccb11c9b2a 100644 -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_WINBOND=y + CONFIG_PHY_ATHEROS=y + CONFIG_PHY_SMSC=y CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y @@ -69,7 +79,7 @@ index 335aa8cfa1..ccb11c9b2a 100644 CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y -@@ -73,7 +55,6 @@ CONFIG_USB_GADGET=y +@@ -86,7 +60,6 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 diff --git a/0008-Kconfig-add-btrfs-to-distro-boot.patch b/0008-Kconfig-add-btrfs-to-distro-boot.patch index 766453d..f9dbfa4 100644 --- a/0008-Kconfig-add-btrfs-to-distro-boot.patch +++ b/0008-Kconfig-add-btrfs-to-distro-boot.patch @@ -1,4 +1,4 @@ -From b54dd0d97ff8affb76cd83b26b1f2b56cb87f43a Mon Sep 17 00:00:00 2001 +From 063a11190ec974996e4e6b827974db15d9bc47d3 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 17 Jan 2020 20:59:02 +0100 Subject: [PATCH] Kconfig: add btrfs to distro boot @@ -13,10 +13,10 @@ Signed-off-by: Matthias Brugger 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig -index f698e0a94f..8d104486c1 100644 +index 883e3f71d0..bdfd7b7078 100644 --- a/Kconfig +++ b/Kconfig -@@ -93,6 +93,7 @@ config DISTRO_DEFAULTS +@@ -143,6 +143,7 @@ config DISTRO_DEFAULTS select HUSH_PARSER select SUPPORT_RAW_INITRD select SYS_LONGHELP diff --git a/0009-configs-Re-sync-with-CONFIG_DISTRO_.patch b/0009-configs-Re-sync-with-CONFIG_DISTRO_.patch index 4d37080..9f6cb2b 100644 --- a/0009-configs-Re-sync-with-CONFIG_DISTRO_.patch +++ b/0009-configs-Re-sync-with-CONFIG_DISTRO_.patch @@ -1,4 +1,4 @@ -From c2dd94a9854d148a77cee50f3f9b4757db3a060f Mon Sep 17 00:00:00 2001 +From 4738cf1c8ebce2343671591663eedc394813da43 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Wed, 29 Jan 2020 09:56:06 +0100 Subject: [PATCH] configs: Re-sync with CONFIG_DISTRO_DEFAULTS @@ -18,10 +18,10 @@ Signed-off-by: Matthias Brugger 5 files changed, 2 insertions(+), 4 deletions(-) diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig -index 71a4d7fccb..f07e017b0e 100644 +index c3ca796d51..9c102948c0 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig -@@ -63,7 +63,6 @@ CONFIG_CMD_REGULATOR=y +@@ -75,7 +75,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AES=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y @@ -30,10 +30,10 @@ index 71a4d7fccb..f07e017b0e 100644 CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT4_WRITE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig -index f96891ecae..694880f71f 100644 +index 6e9f029cc9..92ffe48432 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig -@@ -72,7 +72,6 @@ CONFIG_CMD_REGULATOR=y +@@ -87,7 +87,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_AES=y CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y @@ -42,29 +42,29 @@ index f96891ecae..694880f71f 100644 CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT4_WRITE=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig -index ca34457ddd..5a4204eaf6 100644 +index 8fdd21c0d3..61d8c3f7c4 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig -@@ -50,3 +50,5 @@ CONFIG_TIMER=y - CONFIG_SPL_TIMER=y - CONFIG_DESIGNWARE_APB_TIMER=y +@@ -55,3 +55,5 @@ CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_DWC2=y # CONFIG_SPL_WDT is not set +# CONFIG_CMD_BTRFS is not set +# CONFIG_FS_BTRFS is not set diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig -index 2e637044c1..a6140ce92f 100644 +index c63c9d24ed..934fccc533 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig -@@ -33,7 +33,6 @@ CONFIG_CMD_TFTPPUT=y +@@ -36,7 +36,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y -CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y - CONFIG_OF_BOARD_FIXUP=y + CONFIG_ENV_OVERWRITE=y diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig -index f3ed9917d5..0c48800873 100644 +index 536be77ca7..e834f92828 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -50,7 +50,6 @@ CONFIG_CMD_CACHE=y @@ -73,5 +73,5 @@ index f3ed9917d5..0c48800873 100644 CONFIG_CMD_HASH=y -CONFIG_CMD_BTRFS=y # CONFIG_SPL_PARTITION_UUIDS is not set - CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" - CONFIG_ENV_IS_IN_SPI_FLASH=y + CONFIG_ENV_OVERWRITE=y + CONFIG_USE_ENV_SPI_MAX_HZ=y diff --git a/0010-configs-am335x_evm-disable-BTRFS.patch b/0010-configs-am335x_evm-disable-BTRFS.patch index b253fbf..c79a9da 100644 --- a/0010-configs-am335x_evm-disable-BTRFS.patch +++ b/0010-configs-am335x_evm-disable-BTRFS.patch @@ -1,4 +1,4 @@ -From 0403d42def8d2ea3251f131a05ff9f76de2b602a Mon Sep 17 00:00:00 2001 +From f6c178cc6540fc57888e06c36f1813910f5432ed Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Wed, 29 Jan 2020 10:26:43 +0100 Subject: [PATCH] configs: am335x_evm: disable BTRFS @@ -11,10 +11,10 @@ Signed-off-by: Matthias Brugger 1 file changed, 2 insertions(+) diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig -index ccb11c9b2a..1894678eea 100644 +index 78202a55c7..1d32f9589a 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig -@@ -61,3 +61,5 @@ CONFIG_DYNAMIC_CRC_TABLE=y +@@ -66,3 +66,5 @@ CONFIG_DYNAMIC_CRC_TABLE=y CONFIG_RSA=y CONFIG_LZO=y # CONFIG_OF_LIBFDT_OVERLAY is not set diff --git a/0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch b/0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch deleted file mode 100644 index 4270cc0..0000000 --- a/0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From bf743c28432ba1eea23e0b05c582762b4b6fe1b7 Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Thu, 20 Feb 2020 17:36:31 +0100 -Subject: [PATCH] net: bcmgenet: Don't set ID_MODE_DIS when not using RGMII - -As per Linux's driver, ID_MODE_DIS is only set when the PHY interface is -RGMII. Don't enable it for the rest of setups. - -This has been seen to misconfigure RPi4's PHY when booting Linux. - -Upstream submission: -https://patchwork.ozlabs.org/patch/1241570/ - -Fixes: d53e3fa385 ("net: Add support for Broadcom GENETv5 Ethernet -controller") -Signed-off-by: Nicolas Saenz Julienne -Signed-off-by: Matthias Brugger ---- - drivers/net/bcmgenet.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c -index 8f4848aec6..e971b556ac 100644 ---- a/drivers/net/bcmgenet.c -+++ b/drivers/net/bcmgenet.c -@@ -448,7 +448,10 @@ static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) - } - - clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, -- RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); -+ RGMII_LINK | RGMII_MODE_EN); -+ -+ if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII) -+ setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS); - - writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); - diff --git a/0011-sunxi-dts-OrangePi-Zero-Add-SPI-ali.patch b/0011-sunxi-dts-OrangePi-Zero-Add-SPI-ali.patch new file mode 100644 index 0000000..7462858 --- /dev/null +++ b/0011-sunxi-dts-OrangePi-Zero-Add-SPI-ali.patch @@ -0,0 +1,42 @@ +From c47d520bbeedb976159c3f3fb2e4c490b1b56d83 Mon Sep 17 00:00:00 2001 +From: Michal Suchanek +Date: Tue, 29 Sep 2020 10:13:33 +0200 +Subject: [PATCH] sunxi: dts: OrangePi Zero: Add SPI aliases to make bus usable + with u-boot. + +The u-boot code relies on aliases to assign bus number. + +Signed-off-by: Michal Suchanek +Signed-off-by: Matthias Brugger +--- + arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 1 + + arch/arm/dts/sunxi-spi-u-boot.dtsi | 8 ++++++++ + 2 files changed, 9 insertions(+) + create mode 100644 arch/arm/dts/sunxi-spi-u-boot.dtsi + +diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +index f19ed981da..3f0d0281ba 100644 +--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts ++++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +@@ -46,6 +46,7 @@ + /dts-v1/; + #include "sun8i-h3.dtsi" + #include "sunxi-common-regulators.dtsi" ++#include "sunxi-spi-u-boot.dtsi" + + #include + #include +diff --git a/arch/arm/dts/sunxi-spi-u-boot.dtsi b/arch/arm/dts/sunxi-spi-u-boot.dtsi +new file mode 100644 +index 0000000000..df89d02ff2 +--- /dev/null ++++ b/arch/arm/dts/sunxi-spi-u-boot.dtsi +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/ { ++ ++ aliases { ++ spi0 = &spi0; ++ spi1 = &spi1; ++ }; ++}; diff --git a/0012-sunxi-dts-OrangePi-Zero-Enable-SPI-.patch b/0012-sunxi-dts-OrangePi-Zero-Enable-SPI-.patch new file mode 100644 index 0000000..7f07724 --- /dev/null +++ b/0012-sunxi-dts-OrangePi-Zero-Enable-SPI-.patch @@ -0,0 +1,29 @@ +From 6b1054580c7d2fce12c3aea4a4fe7874dad54684 Mon Sep 17 00:00:00 2001 +From: Michal Suchanek +Date: Mon, 28 Sep 2020 23:02:01 +0200 +Subject: [PATCH] sunxi: dts: OrangePi Zero: Enable SPI flash. + +This flash is optional but new boards do have it, and on boards that +don't the pins are routed to the flash pads anyway. + +Signed-off-by: Michal Suchanek +Signed-off-by: Matthias Brugger +--- + arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +index 3f0d0281ba..b08e84c616 100644 +--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts ++++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +@@ -164,8 +164,8 @@ + }; + + &spi0 { +- /* Disable SPI NOR by default: it optional on Orange Pi Zero boards */ +- status = "disabled"; ++ /* Enable SPI NOR by default: it optional on Orange Pi Zero boards */ ++ status = "okay"; + + flash@0 { + #address-cells = <1>; diff --git a/0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch b/0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch deleted file mode 100644 index 0456715..0000000 --- a/0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 35fec3c2ae56857f07d5f68a48da84d010a62429 Mon Sep 17 00:00:00 2001 -From: Qu Wenruo -Date: Thu, 19 Mar 2020 20:30:05 +0800 -Subject: [PATCH] uboot: fs/btrfs: Use LZO_LEN to replace immediate number - -Just a cleanup. The immediate number makes my eye hurt. - -Signed-off-by: Qu Wenruo -Signed-off-by: Matthias Brugger ---- - fs/btrfs/compression.c | 22 ++++++++++++---------- - 1 file changed, 12 insertions(+), 10 deletions(-) - -diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c -index 346875d45a..4ef44ce114 100644 ---- a/fs/btrfs/compression.c -+++ b/fs/btrfs/compression.c -@@ -12,36 +12,38 @@ - #include - #include - -+/* Header for each segment, LE32, recording the compressed size */ -+#define LZO_LEN 4 - static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) - { - u32 tot_len, in_len, res; - size_t out_len; - int ret; - -- if (clen < 4) -+ if (clen < LZO_LEN) - return -1; - - tot_len = le32_to_cpu(get_unaligned((u32 *)cbuf)); -- cbuf += 4; -- clen -= 4; -- tot_len -= 4; -+ cbuf += LZO_LEN; -+ clen -= LZO_LEN; -+ tot_len -= LZO_LEN; - - if (tot_len == 0 && dlen) - return -1; -- if (tot_len < 4) -+ if (tot_len < LZO_LEN) - return -1; - - res = 0; - -- while (tot_len > 4) { -+ while (tot_len > LZO_LEN) { - in_len = le32_to_cpu(get_unaligned((u32 *)cbuf)); -- cbuf += 4; -- clen -= 4; -+ cbuf += LZO_LEN; -+ clen -= LZO_LEN; - -- if (in_len > clen || tot_len < 4 + in_len) -+ if (in_len > clen || tot_len < LZO_LEN + in_len) - return -1; - -- tot_len -= 4 + in_len; -+ tot_len -= (LZO_LEN + in_len); - - out_len = dlen; - ret = lzo1x_decompress_safe(cbuf, in_len, dbuf, &out_len); diff --git a/0013-sunxi-Enable-SPI-support-on-Orange-.patch b/0013-sunxi-Enable-SPI-support-on-Orange-.patch new file mode 100644 index 0000000..cda0252 --- /dev/null +++ b/0013-sunxi-Enable-SPI-support-on-Orange-.patch @@ -0,0 +1,32 @@ +From cb19bc680c9353acb48d0f90f3e91292701ef1bb Mon Sep 17 00:00:00 2001 +From: Michal Suchanek +Date: Mon, 28 Sep 2020 23:02:02 +0200 +Subject: [PATCH] sunxi: Enable SPI support on Orange Pi Zero + +Enable support for SPI flash and the sf command. + +Signed-off-by: Michal Suchanek +Signed-off-by: Matthias Brugger +--- + configs/orangepi_zero_defconfig | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig +index 998c95d151..1087baece1 100644 +--- a/configs/orangepi_zero_defconfig ++++ b/configs/orangepi_zero_defconfig +@@ -8,6 +8,14 @@ CONFIG_SPL_SPI_SUNXI=y + CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_SPI=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_WINBOND=y + CONFIG_SUN8I_EMAC=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_OHCI_HCD=y diff --git a/0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch b/0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch deleted file mode 100644 index 72bc280..0000000 --- a/0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch +++ /dev/null @@ -1,124 +0,0 @@ -From 82ad3674e71029334b519ff8c2bc077df82c2243 Mon Sep 17 00:00:00 2001 -From: Qu Wenruo -Date: Thu, 19 Mar 2020 20:30:06 +0800 -Subject: [PATCH] uboot: fs/btrfs: Fix LZO false decompression error caused by - pending zero - -[BUG] -For certain btrfs files with compressed file extent, uboot will fail to -load it: - - btrfs_read_extent_reg: disk_bytenr=14229504 disk_len=73728 offset=0 nr_bytes=131 - 072 - decompress_lzo: tot_len=70770 - decompress_lzo: in_len=1389 - decompress_lzo: in_len=2400 - decompress_lzo: in_len=3002 - decompress_lzo: in_len=1379 - decompress_lzo: in_len=88539136 - decompress_lzo: header error, in_len=88539136 clen=65534 tot_len=62580 - -NOTE: except the last line, all other lines are debug output. - -[CAUSE] -Btrfs lzo compression uses its own format to record compressed size -(segmant header, LE32). - -However to make decompression easier, we never put such segment header -across page boundary. - -In above case, the xxd dump of the lzo compressed data looks like this: - -00001fe0: 4cdc 02fc 0bfd 02c0 dc02 0d13 0100 0001 L............... -00001ff0: 0000 0008 0300 0000 0000 0011 0000|0000 ................ -00002000: 4705 0000 0001 cc02 0000 0000 0000 1e01 G............... - -'|' is the "expected" segment header start position. - -But in that page, there are only 2 bytes left, can't contain the 4 bytes -segment header. - -So btrfs compression will skip that 2 bytes, put the segment header in -next page directly. - -Uboot doesn't have such check, and read the header with 2 bytes offset, -result 0x05470000 (88539136), other than the expected result -0x00000547 (1351), resulting above error. - -[FIX] -Follow the btrfs-progs restore implementation, by introducing tot_in to -record total processed bytes (including headers), and do proper page -boundary skip to fix it. - -Signed-off-by: Qu Wenruo -Signed-off-by: Matthias Brugger ---- - fs/btrfs/compression.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/fs/btrfs/compression.c b/fs/btrfs/compression.c -index 4ef44ce114..2a6ac8bb10 100644 ---- a/fs/btrfs/compression.c -+++ b/fs/btrfs/compression.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -17,6 +18,7 @@ - static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) - { - u32 tot_len, in_len, res; -+ u32 tot_in = 0; - size_t out_len; - int ret; - -@@ -27,6 +29,7 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) - cbuf += LZO_LEN; - clen -= LZO_LEN; - tot_len -= LZO_LEN; -+ tot_in += LZO_LEN; - - if (tot_len == 0 && dlen) - return -1; -@@ -36,6 +39,9 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) - res = 0; - - while (tot_len > LZO_LEN) { -+ size_t mod_page; -+ size_t rem_page; -+ - in_len = le32_to_cpu(get_unaligned((u32 *)cbuf)); - cbuf += LZO_LEN; - clen -= LZO_LEN; -@@ -44,6 +50,7 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) - return -1; - - tot_len -= (LZO_LEN + in_len); -+ tot_in += (LZO_LEN + in_len); - - out_len = dlen; - ret = lzo1x_decompress_safe(cbuf, in_len, dbuf, &out_len); -@@ -56,6 +63,19 @@ static u32 decompress_lzo(const u8 *cbuf, u32 clen, u8 *dbuf, u32 dlen) - dlen -= out_len; - - res += out_len; -+ -+ /* -+ * If the 4 bytes header does not fit to the rest of the page we -+ * have to move to next one, or we read some garbage. -+ */ -+ mod_page = tot_in % PAGE_SIZE; -+ rem_page = PAGE_SIZE - mod_page; -+ if (rem_page < LZO_LEN) { -+ cbuf += rem_page; -+ tot_in += rem_page; -+ clen -= rem_page; -+ tot_len -= rem_page; -+ } - } - - return res; diff --git a/0014-usb-xhci-Add-missing-cache-flush-in.patch b/0014-usb-xhci-Add-missing-cache-flush-in.patch deleted file mode 100644 index 5a51849..0000000 --- a/0014-usb-xhci-Add-missing-cache-flush-in.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 96a515925eddcb28645391a0605710cfa79e7351 Mon Sep 17 00:00:00 2001 -From: Sylwester Nawrocki -Date: Mon, 4 May 2020 14:45:14 +0200 -Subject: [PATCH] usb: xhci: Add missing cache flush in the scratchpad array - initialization - -In current code there is no cache flush after initializing the scratchpad -buffer array with the scratchpad buffer pointers. This leads to a failure -of the "slot enable" command on the rpi4 board (Broadcom STB PCIe -controller + VL805 USB hub) - the very first TRB transfer on the command -ring fails and there is a timeout while waiting for the command completion -event. After adding the missing cache flush everything seems to be working -as expected. - -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne ---- - drivers/usb/host/xhci-mem.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c -index 93450ee3b7..729bdc3c84 100644 ---- a/drivers/usb/host/xhci-mem.c -+++ b/drivers/usb/host/xhci-mem.c -@@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) - scratchpad->sp_array[i] = cpu_to_le64(ptr); - } - -+ xhci_flush_cache((uintptr_t)scratchpad->sp_array, -+ sizeof(u64) * num_sp); -+ - return 0; - - fail_sp3: diff --git a/0015-usb-xhci-Use-only-32-bit-accesses-i.patch b/0015-usb-xhci-Use-only-32-bit-accesses-i.patch deleted file mode 100644 index 5507952..0000000 --- a/0015-usb-xhci-Use-only-32-bit-accesses-i.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 919357cfab0b8a07184b676b50c3a31582e3dcdc Mon Sep 17 00:00:00 2001 -From: Sylwester Nawrocki -Date: Mon, 4 May 2020 14:45:15 +0200 -Subject: [PATCH] usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq - -There might be hardware configurations where 64-bit data accesses -to XHCI registers are not supported properly. This patch removes -the readq/writeq so always two 32-bit accesses are used to read/write -64-bit XHCI registers, similarly as it is done in Linux kernel. - -This patch fixes operation of the XHCI controller on RPI4 Broadcom -BCM2711 SoC based board, where the VL805 USB XHCI controller is -connected to the PCIe Root Complex, which is attached to the system -through the SCB bridge. - -Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely -the 64-bit wide register accesses initiated by the CPU are not properly -translated to a sequence of 32-bit PCIe accesses. -xhci_readq(), for example, always returns same value in upper and lower -32-bits, e.g. 0xabcd1234abcd1234 instead of 0x00000000abcd1234. - -Cc: Sergey Temerkhanov -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne ---- - include/usb/xhci.h | 8 -------- - 1 file changed, 8 deletions(-) - -diff --git a/include/usb/xhci.h b/include/usb/xhci.h -index 6017504488..c16106a2fc 100644 ---- a/include/usb/xhci.h -+++ b/include/usb/xhci.h -@@ -1111,28 +1111,20 @@ static inline void xhci_writel(uint32_t volatile *regs, const unsigned int val) - */ - static inline u64 xhci_readq(__le64 volatile *regs) - { --#if BITS_PER_LONG == 64 -- return readq(regs); --#else - __u32 *ptr = (__u32 *)regs; - u64 val_lo = readl(ptr); - u64 val_hi = readl(ptr + 1); - return val_lo + (val_hi << 32); --#endif - } - - static inline void xhci_writeq(__le64 volatile *regs, const u64 val) - { --#if BITS_PER_LONG == 64 -- writeq(val, regs); --#else - __u32 *ptr = (__u32 *)regs; - u32 val_lo = lower_32_bits(val); - /* FIXME */ - u32 val_hi = upper_32_bits(val); - writel(val_lo, ptr); - writel(val_hi, ptr + 1); --#endif - } - - int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, diff --git a/0016-pci-Move-some-PCIe-register-offset-.patch b/0016-pci-Move-some-PCIe-register-offset-.patch deleted file mode 100644 index d4eb737..0000000 --- a/0016-pci-Move-some-PCIe-register-offset-.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 18844a477d00a24fdeff913c4c277d53ee98094d Mon Sep 17 00:00:00 2001 -From: Sylwester Nawrocki -Date: Mon, 4 May 2020 14:45:16 +0200 -Subject: [PATCH] pci: Move some PCIe register offset definitions to a common - header - -Some PCI Express register offsets are currently defined in multiple -drivers, move them to a common header to avoid re-definitions and -as a pre-requisite for adding new PCIe driver. -While at it replace some spaces with tabs. - -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne ---- - drivers/pci/pci-rcar-gen3.c | 8 -------- - drivers/pci/pcie_intel_fpga.c | 3 --- - include/pci.h | 13 +++++++++++-- - 3 files changed, 11 insertions(+), 13 deletions(-) - -diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c -index 30eff67dca..393f1c9ca9 100644 ---- a/drivers/pci/pci-rcar-gen3.c -+++ b/drivers/pci/pci-rcar-gen3.c -@@ -117,14 +117,6 @@ - #define RCAR_PCI_MAX_RESOURCES 4 - #define MAX_NR_INBOUND_MAPS 6 - --#define PCI_EXP_FLAGS 2 /* Capabilities register */ --#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ --#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ --#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ --#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ --#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ --#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -- - enum { - RCAR_PCI_ACCESS_READ, - RCAR_PCI_ACCESS_WRITE, -diff --git a/drivers/pci/pcie_intel_fpga.c b/drivers/pci/pcie_intel_fpga.c -index 6a9f29c5c8..69363a077a 100644 ---- a/drivers/pci/pcie_intel_fpga.c -+++ b/drivers/pci/pcie_intel_fpga.c -@@ -65,9 +65,6 @@ - #define IS_ROOT_PORT(pcie, bdf) \ - ((PCI_BUS(bdf) == pcie->first_busno) ? true : false) - --#define PCI_EXP_LNKSTA 18 /* Link Status */ --#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -- - /** - * struct intel_fpga_pcie - Intel FPGA PCIe controller state - * @bus: Pointer to the PCI bus -diff --git a/include/pci.h b/include/pci.h -index 174ddd4460..5bf91a43af 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -471,10 +471,19 @@ - #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */ - - /* PCI Express capabilities */ -+#define PCI_EXP_FLAGS 2 /* Capabilities register */ -+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ - #define PCI_EXP_DEVCAP 4 /* Device capabilities */ --#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ -+#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ - #define PCI_EXP_DEVCTL 8 /* Device Control */ --#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ -+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ -+#define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ -+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ -+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ - - /* Include the ID list */ - diff --git a/0017-rpi4-shorten-a-mapping-for-the-DRAM.patch b/0017-rpi4-shorten-a-mapping-for-the-DRAM.patch deleted file mode 100644 index de22373..0000000 --- a/0017-rpi4-shorten-a-mapping-for-the-DRAM.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 4db83106c1da071b0e4ee56675bdbf448f2961fc Mon Sep 17 00:00:00 2001 -From: Marek Szyprowski -Date: Mon, 4 May 2020 14:45:17 +0200 -Subject: [PATCH] rpi4: shorten a mapping for the DRAM - -Remove the overlap between DRAM and device's IO area. - -Signed-off-by: Marek Szyprowski -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Nicolas Saenz Julienne ---- - arch/arm/mach-bcm283x/init.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 9966d6c833..42953561a7 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -38,7 +38,7 @@ static struct mm_region bcm2711_mem_map[] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -- .size = 0xfe000000UL, -+ .size = 0xfc000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { diff --git a/0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch b/0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch deleted file mode 100644 index 77a5d1b..0000000 --- a/0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch +++ /dev/null @@ -1,70 +0,0 @@ -From c64da6a3c2950b925e95fb892e381ce89a869c8e Mon Sep 17 00:00:00 2001 -From: Marek Szyprowski -Date: Mon, 4 May 2020 14:45:18 +0200 -Subject: [PATCH] rpi4: add a mapping for the PCIe XHCI controller MMIO - registers (ARM 64bit) - -Create a non-cacheable mapping for the 0x600000000 physical memory region, -where MMIO registers for the PCIe XHCI controller are instantiated by the -PCIe bridge. - -Signed-off-by: Marek Szyprowski -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Nicolas Saenz Julienne ---- - arch/arm/mach-bcm283x/init.c | 18 +++++++++++++++--- - 1 file changed, 15 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c -index 42953561a7..6a748da171 100644 ---- a/arch/arm/mach-bcm283x/init.c -+++ b/arch/arm/mach-bcm283x/init.c -@@ -11,10 +11,15 @@ - #include - #include - -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS 0x600000000UL -+#define BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE 0x800000UL -+ - #ifdef CONFIG_ARM64 - #include - --static struct mm_region bcm283x_mem_map[] = { -+#define MAX_MAP_MAX_ENTRIES (4) -+ -+static struct mm_region bcm283x_mem_map[MAX_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -@@ -34,7 +39,7 @@ static struct mm_region bcm283x_mem_map[] = { - } - }; - --static struct mm_region bcm2711_mem_map[] = { -+static struct mm_region bcm2711_mem_map[MAX_MAP_MAX_ENTRIES] = { - { - .virt = 0x00000000UL, - .phys = 0x00000000UL, -@@ -48,6 +53,13 @@ static struct mm_region bcm2711_mem_map[] = { - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN -+ }, { -+ .virt = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .phys = BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS, -+ .size = BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, -+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | -+ PTE_BLOCK_NON_SHARE | -+ PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, -@@ -71,7 +83,7 @@ static void _rpi_update_mem_map(struct mm_region *pd) - { - int i; - -- for (i = 0; i < 2; i++) { -+ for (i = 0; i < MAX_MAP_MAX_ENTRIES; i++) { - mem_map[i].virt = pd[i].virt; - mem_map[i].phys = pd[i].phys; - mem_map[i].size = pd[i].size; diff --git a/0019-linux-bitfield.h-Add-primitives-for.patch b/0019-linux-bitfield.h-Add-primitives-for.patch deleted file mode 100644 index 740276a..0000000 --- a/0019-linux-bitfield.h-Add-primitives-for.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 897da38f243dd23eeaa5e1103bbd9f7d47bc0f7f Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Mon, 4 May 2020 14:45:20 +0200 -Subject: [PATCH] linux/bitfield.h: Add primitives for manipulating bitfields - both in host- and fixed-endian - -Imports Al Viro's original Linux commit 00b0c9b82663a, which contains -an in depth explanation and two fixes from Johannes Berg: - e7d4a95da86e0 "bitfield: fix *_encode_bits()", - 37a3862e12382 "bitfield: add u8 helpers". - -Signed-off-by: Nicolas Saenz Julienne -[s.nawrocki: added empty lines between functions and macros] -Signed-off-by: Sylwester Nawrocki ---- - include/linux/bitfield.h | 50 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 50 insertions(+) - -diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h -index 8b9d6fff00..7acba4c524 100644 ---- a/include/linux/bitfield.h -+++ b/include/linux/bitfield.h -@@ -103,4 +103,54 @@ - (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ - }) - -+extern void __compiletime_error("value doesn't fit into mask") -+__field_overflow(void); -+extern void __compiletime_error("bad bitfield mask") -+__bad_mask(void); -+static __always_inline u64 field_multiplier(u64 field) -+{ -+ if ((field | (field - 1)) & ((field | (field - 1)) + 1)) -+ __bad_mask(); -+ return field & -field; -+} -+static __always_inline u64 field_mask(u64 field) -+{ -+ return field / field_multiplier(field); -+} -+ -+#define ____MAKE_OP(type,base,to,from) \ -+static __always_inline __##type type##_encode_bits(base v, base field) \ -+{ \ -+ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ -+ __field_overflow(); \ -+ return to((v & field_mask(field)) * field_multiplier(field)); \ -+} \ -+static __always_inline __##type type##_replace_bits(__##type old, \ -+ base val, base field) \ -+{ \ -+ return (old & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline void type##p_replace_bits(__##type *p, \ -+ base val, base field) \ -+{ \ -+ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ -+} \ -+static __always_inline base type##_get_bits(__##type v, base field) \ -+{ \ -+ return (from(v) & field)/field_multiplier(field); \ -+} -+ -+#define __MAKE_OP(size) \ -+ ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ -+ ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ -+ ____MAKE_OP(u##size,u##size,,) -+ -+____MAKE_OP(u8,u8,,) -+__MAKE_OP(16) -+__MAKE_OP(32) -+__MAKE_OP(64) -+ -+#undef __MAKE_OP -+#undef ____MAKE_OP -+ - #endif diff --git a/0020-pci-Add-some-PCI-Express-capability.patch b/0020-pci-Add-some-PCI-Express-capability.patch deleted file mode 100644 index c8cca6f..0000000 --- a/0020-pci-Add-some-PCI-Express-capability.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 278f85de3e80c3240448bb133af65520294ec590 Mon Sep 17 00:00:00 2001 -From: Sylwester Nawrocki -Date: Mon, 4 May 2020 14:45:21 +0200 -Subject: [PATCH] pci: Add some PCI Express capability register offset - definitions - -Add PCI Express capability definitions required by the Broadcom -STB PCIe controller driver. - -Signed-off-by: Sylwester Nawrocki -Reviewed-by: Bin Meng -Reviewed-by: Nicolas Saenz Julienne ---- - include/pci.h | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/include/pci.h b/include/pci.h -index 5bf91a43af..5307478b44 100644 ---- a/include/pci.h -+++ b/include/pci.h -@@ -479,11 +479,17 @@ - #define PCI_EXP_DEVCTL 8 /* Device Control */ - #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ - #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ -+#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ -+#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ - #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ - #define PCI_EXP_LNKSTA 18 /* Link Status */ -+#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ -+#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ -+#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ - #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ - #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ - #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ -+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ - - /* Include the ID list */ - diff --git a/0021-pci-Add-driver-for-Broadcom-STB-PCI.patch b/0021-pci-Add-driver-for-Broadcom-STB-PCI.patch deleted file mode 100644 index 22d0c65..0000000 --- a/0021-pci-Add-driver-for-Broadcom-STB-PCI.patch +++ /dev/null @@ -1,646 +0,0 @@ -From 04b021d3e62a886e243af767667abe76d1939db4 Mon Sep 17 00:00:00 2001 -From: Sylwester Nawrocki -Date: Mon, 4 May 2020 14:45:22 +0200 -Subject: [PATCH] pci: Add driver for Broadcom STB PCIe controller - -This patch adds basic driver for the Broadcom STB PCIe host controller. -The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI -handling removed. The inbound access memory region is not currently -parsed from dma-ranges DT property and a fixed 4GB region is used. - -The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805 -USB Host Controller. - -Signed-off-by: Nicolas Saenz Julienne -Signed-off-by: Sylwester Nawrocki ---- - drivers/pci/Kconfig | 6 + - drivers/pci/Makefile | 1 + - drivers/pci/pcie_brcmstb.c | 594 +++++++++++++++++++++++++++++++++++++ - 3 files changed, 601 insertions(+) - create mode 100644 drivers/pci/pcie_brcmstb.c - -diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig -index 437cd9a055..056a021194 100644 ---- a/drivers/pci/Kconfig -+++ b/drivers/pci/Kconfig -@@ -197,4 +197,10 @@ config PCIE_MEDIATEK - Say Y here if you want to enable Gen2 PCIe controller, - which could be found on MT7623 SoC family. - -+config PCI_BRCMSTB -+ bool "Broadcom STB PCIe controller" -+ depends on DM_PCI -+ depends on ARCH_BCM283X -+ help -+ Say Y here if you want to enable Broadcom STB PCIe controller support. - endif -diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile -index c051ecc9f3..3e53b1f717 100644 ---- a/drivers/pci/Makefile -+++ b/drivers/pci/Makefile -@@ -43,3 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o - obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o - obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o - obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o -+obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o -diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c -new file mode 100644 -index 0000000000..d1d86bcab0 ---- /dev/null -+++ b/drivers/pci/pcie_brcmstb.c -@@ -0,0 +1,594 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Broadcom STB PCIe controller driver -+ * -+ * Copyright (C) 2020 Samsung Electronics Co., Ltd. -+ * -+ * Based on upstream Linux kernel driver: -+ * drivers/pci/controller/pcie-brcmstb.c -+ * Copyright (C) 2009 - 2017 Broadcom -+ * -+ * Based driver by Nicolas Saenz Julienne -+ * Copyright (C) 2020 Nicolas Saenz Julienne -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */ -+#define BRCM_PCIE_CAP_REGS 0x00ac -+ -+/* Broadcom STB PCIe Register Offsets */ -+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 -+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc -+#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0 -+ -+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c -+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff -+ -+#define PCIE_RC_DL_MDIO_ADDR 0x1100 -+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104 -+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108 -+ -+#define PCIE_MISC_MISC_CTRL 0x4008 -+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 -+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 -+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 -+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0 -+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c -+#define PCIE_MEM_WIN0_LO(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 -+#define PCIE_MEM_WIN0_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) -+ -+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c -+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f -+ -+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 -+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f -+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 -+ -+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c -+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f -+ -+#define PCIE_MISC_PCIE_STATUS 0x4068 -+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80 -+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20 -+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10 -+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40 -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 -+#define PCIE_MEM_WIN0_BASE_LIMIT(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff -+#define PCIE_MEM_WIN0_BASE_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) -+ -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 -+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff -+#define PCIE_MEM_WIN0_LIMIT_HI(win) \ -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) -+ -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 -+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 -+ -+#define PCIE_MSI_INTR2_CLR 0x4508 -+#define PCIE_MSI_INTR2_MASK_SET 0x4510 -+ -+#define PCIE_EXT_CFG_DATA 0x8000 -+ -+#define PCIE_EXT_CFG_INDEX 0x9000 -+#define PCIE_EXT_BUSNUM_SHIFT 20 -+#define PCIE_EXT_SLOT_SHIFT 15 -+#define PCIE_EXT_FUNC_SHIFT 12 -+ -+#define PCIE_RGR1_SW_INIT_1 0x9210 -+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 -+#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 -+ -+/* PCIe parameters */ -+#define BRCM_NUM_PCIE_OUT_WINS 0x4 -+ -+/* MDIO registers */ -+#define MDIO_PORT0 0x0 -+#define MDIO_DATA_MASK 0x7fffffff -+#define MDIO_PORT_MASK 0xf0000 -+#define MDIO_REGAD_MASK 0xffff -+#define MDIO_CMD_MASK 0xfff00000 -+#define MDIO_CMD_READ 0x1 -+#define MDIO_CMD_WRITE 0x0 -+#define MDIO_DATA_DONE_MASK 0x80000000 -+#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0) -+#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1) -+#define SSC_REGS_ADDR 0x1100 -+#define SET_ADDR_OFFSET 0x1f -+#define SSC_CNTL_OFFSET 0x2 -+#define SSC_CNTL_OVRD_EN_MASK 0x8000 -+#define SSC_CNTL_OVRD_VAL_MASK 0x4000 -+#define SSC_STATUS_OFFSET 0x1 -+#define SSC_STATUS_SSC_MASK 0x400 -+#define SSC_STATUS_PLL_LOCK_MASK 0x800 -+ -+struct brcm_pcie { -+ void __iomem *base; -+ -+ int gen; -+ bool ssc; -+}; -+ -+#define msleep(a) udelay((a) * 1000) -+ -+/* -+ * This is to convert the size of the inbound "BAR" region to the -+ * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE -+ */ -+static int brcm_pcie_encode_ibar_size(u64 size) -+{ -+ int log2_in = ilog2(size); -+ -+ if (log2_in >= 12 && log2_in <= 15) -+ /* Covers 4KB to 32KB (inclusive) */ -+ return (log2_in - 12) + 0x1c; -+ else if (log2_in >= 16 && log2_in <= 37) -+ /* Covers 64KB to 32GB, (inclusive) */ -+ return log2_in - 15; -+ /* Something is awry so disable */ -+ return 0; -+} -+ -+/* Configuration space read/write support */ -+static inline int brcm_pcie_cfg_index(pci_dev_t bdf, int reg) -+{ -+ return (PCI_DEV(bdf) << PCIE_EXT_SLOT_SHIFT) -+ | (PCI_FUNC(bdf) << PCIE_EXT_FUNC_SHIFT) -+ | (PCI_BUS(bdf) << PCIE_EXT_BUSNUM_SHIFT) -+ | (reg & ~3); -+} -+ -+/* The controller is capable of serving in both RC and EP roles */ -+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) -+{ -+ u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); -+ -+ return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val); -+} -+ -+static bool brcm_pcie_link_up(struct brcm_pcie *pcie) -+{ -+ u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); -+ u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val); -+ u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val); -+ -+ return dla && plu; -+} -+ -+static int brcm_pcie_config_address(struct udevice *udev, pci_dev_t bdf, -+ uint offset, void **paddress) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(udev); -+ unsigned int bus = PCI_BUS(bdf); -+ unsigned int dev = PCI_DEV(bdf); -+ int idx; -+ -+ /* -+ * Busses 0 (host PCIe bridge) and 1 (its immediate child) -+ * are limited to a single device each -+ */ -+ if ((bus == (udev->seq + 1)) && dev > 0) -+ return -ENODEV; -+ -+ /* Accesses to the RC go right to the RC registers if PCI device == 0 */ -+ if (bus == udev->seq) { -+ if (PCI_DEV(bdf)) -+ return -ENODEV; -+ -+ *paddress = pcie->base + offset; -+ return 0; -+ } -+ -+ /* For devices, write to the config space index register */ -+ idx = brcm_pcie_cfg_index(bdf, 0); -+ -+ writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); -+ *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset; -+ -+ return 0; -+} -+ -+static int brcm_pcie_read_config(struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong *valuep, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_read_config(bus, brcm_pcie_config_address, -+ bdf, offset, valuep, size); -+} -+ -+static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf, -+ uint offset, ulong value, -+ enum pci_size_t size) -+{ -+ return pci_generic_mmap_write_config(bus, brcm_pcie_config_address, -+ bdf, offset, value, size); -+} -+ -+static const char *link_speed_to_str(unsigned int s) -+{ -+ static const char * const speed_str[] = { "??", "2.5", "5.0", "8.0" }; -+ -+ if (s >= ARRAY_SIZE(speed_str)) -+ s = 0; -+ -+ return speed_str[s]; -+} -+ -+static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) -+{ -+ u32 tmp; -+ -+ tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); -+ u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK); -+ writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); -+} -+ -+static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) -+{ -+ u32 tmp; -+ -+ tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1); -+ u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK); -+ writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1); -+} -+ -+static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) -+{ -+ u32 pkt = 0; -+ -+ pkt |= FIELD_PREP(MDIO_PORT_MASK, port); -+ pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad); -+ pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd); -+ -+ return pkt; -+} -+ -+/* Negative return value indicates error */ -+static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) -+{ -+ int tries; -+ u32 data; -+ -+ writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), -+ base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ -+ data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); -+ for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { -+ udelay(10); -+ data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); -+ } -+ -+ *val = FIELD_GET(MDIO_DATA_MASK, data); -+ return MDIO_RD_DONE(data) ? 0 : -EIO; -+} -+ -+/* Negative return value indicates error */ -+static int brcm_pcie_mdio_write(void __iomem *base, u8 port, -+ u8 regad, u16 wrdata) -+{ -+ int tries; -+ u32 data; -+ -+ writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), -+ base + PCIE_RC_DL_MDIO_ADDR); -+ readl(base + PCIE_RC_DL_MDIO_ADDR); -+ writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); -+ -+ data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); -+ for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { -+ udelay(10); -+ data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); -+ } -+ -+ return MDIO_WT_DONE(data) ? 0 : -EIO; -+} -+ -+/* -+ * Configures device for Spread Spectrum Clocking (SSC) mode; negative -+ * return value indicates error. -+ */ -+static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) -+{ -+ void __iomem *base = pcie->base; -+ int pll, ssc; -+ int ret; -+ u32 tmp; -+ -+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, -+ SSC_REGS_ADDR); -+ if (ret < 0) -+ return ret; -+ -+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); -+ if (ret < 0) -+ return ret; -+ -+ u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK); -+ u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK); -+ ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); -+ if (ret < 0) -+ return ret; -+ -+ udelay(1000); -+ ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); -+ if (ret < 0) -+ return ret; -+ -+ ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); -+ pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp); -+ -+ return ssc && pll ? 0 : -EIO; -+} -+ -+/* Limits operation to a specific generation (1, 2, or 3) */ -+static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) -+{ -+ void __iomem *base = pcie->base; -+ -+ u16 lnkctl2 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); -+ u32 lnkcap = readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); -+ -+ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen; -+ writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); -+ -+ lnkctl2 = (lnkctl2 & ~0xf) | gen; -+ writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); -+} -+ -+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, -+ unsigned int win, u64 phys_addr, -+ u64 pcie_addr, u64 size) -+{ -+ void __iomem *base = pcie->base; -+ u32 phys_addr_mb_high, limit_addr_mb_high; -+ phys_addr_t phys_addr_mb, limit_addr_mb; -+ int high_addr_shift; -+ u32 tmp; -+ -+ /* Set the base of the pcie_addr window */ -+ writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win)); -+ writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win)); -+ -+ /* Write the addr base & limit lower bits (in MBs) */ -+ phys_addr_mb = phys_addr / SZ_1M; -+ limit_addr_mb = (phys_addr + size - 1) / SZ_1M; -+ -+ tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win)); -+ u32p_replace_bits(&tmp, phys_addr_mb, -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK); -+ u32p_replace_bits(&tmp, limit_addr_mb, -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win)); -+ -+ /* Write the cpu & limit addr upper bits */ -+ high_addr_shift = PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT; -+ phys_addr_mb_high = phys_addr_mb >> high_addr_shift; -+ tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win)); -+ u32p_replace_bits(&tmp, phys_addr_mb_high, -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win)); -+ -+ limit_addr_mb_high = limit_addr_mb >> high_addr_shift; -+ tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win)); -+ u32p_replace_bits(&tmp, limit_addr_mb_high, -+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK); -+ writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win)); -+} -+ -+static int brcm_pcie_probe(struct udevice *dev) -+{ -+ struct udevice *ctlr = pci_get_controller(dev); -+ struct pci_controller *hose = dev_get_uclass_priv(ctlr); -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ void __iomem *base = pcie->base; -+ bool ssc_good = false; -+ int num_out_wins = 0; -+ u64 rc_bar2_offset, rc_bar2_size; -+ unsigned int scb_size_val; -+ int i, ret; -+ u16 nlw, cls, lnksta; -+ u32 tmp; -+ -+ /* Reset the bridge */ -+ brcm_pcie_bridge_sw_init_set(pcie, 1); -+ -+ udelay(150); -+ -+ /* Take the bridge out of reset */ -+ brcm_pcie_bridge_sw_init_set(pcie, 0); -+ -+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); -+ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; -+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); -+ /* Wait for SerDes to be stable */ -+ udelay(150); -+ -+ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ -+ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); -+ u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); -+ u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128, -+ PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); -+ writel(tmp, base + PCIE_MISC_MISC_CTRL); -+ -+ /* -+ * TODO: When support for other SoCs than BCM2711 is added we may -+ * need to use the base address and size(s) provided in the dma-ranges -+ * property. -+ */ -+ rc_bar2_offset = 0; -+ rc_bar2_size = 0xc0000000; -+ -+ tmp = lower_32_bits(rc_bar2_offset); -+ u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), -+ PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK); -+ writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO); -+ writel(upper_32_bits(rc_bar2_offset), -+ base + PCIE_MISC_RC_BAR2_CONFIG_HI); -+ -+ scb_size_val = rc_bar2_size ? -+ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */ -+ tmp = readl(base + PCIE_MISC_MISC_CTRL); -+ u32p_replace_bits(&tmp, scb_size_val, -+ PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK); -+ writel(tmp, base + PCIE_MISC_MISC_CTRL); -+ -+ /* Disable the PCIe->GISB memory window (RC_BAR1) */ -+ tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO); -+ tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK; -+ writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO); -+ -+ /* Disable the PCIe->SCB memory window (RC_BAR3) */ -+ tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO); -+ tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK; -+ writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO); -+ -+ /* Mask all interrupts since we are not handling any yet */ -+ writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET); -+ -+ /* Clear any interrupts we find on boot */ -+ writel(0xffffffff, base + PCIE_MSI_INTR2_CLR); -+ -+ if (pcie->gen) -+ brcm_pcie_set_gen(pcie, pcie->gen); -+ -+ /* Unassert the fundamental reset */ -+ brcm_pcie_perst_set(pcie, 0); -+ -+ /* Give the RC/EP time to wake up, before trying to configure RC. -+ * Intermittently check status for link-up, up to a total of 100ms. -+ */ -+ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) -+ msleep(5); -+ -+ if (!brcm_pcie_link_up(pcie)) { -+ printf("PCIe BRCM: link down\n"); -+ return -ENODEV; -+ } -+ -+ if (!brcm_pcie_rc_mode(pcie)) { -+ printf("PCIe misconfigured; is in EP mode\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < hose->region_count; i++) { -+ struct pci_region *reg = &hose->regions[i]; -+ -+ if (reg->flags != PCI_REGION_MEM) -+ continue; -+ -+ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) -+ return -EINVAL; -+ -+ brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start, -+ reg->bus_start, reg->size); -+ -+ num_out_wins++; -+ } -+ -+ /* -+ * For config space accesses on the RC, show the right class for -+ * a PCIe-PCIe bridge (the default setting is to be EP mode). -+ */ -+ tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3); -+ u32p_replace_bits(&tmp, 0x060400, -+ PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK); -+ writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3); -+ -+ if (pcie->ssc) { -+ ret = brcm_pcie_set_ssc(pcie); -+ if (ret == 0) -+ ssc_good = true; -+ else -+ printf("PCIe BRCM: failed attempt to enter SSC mode\n"); -+ } -+ -+ lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA); -+ cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta); -+ nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); -+ -+ printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls), -+ nlw, ssc_good ? "(SSC)" : "(!SSC)"); -+ -+ /* PCIe->SCB endian mode for BAR */ -+ tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); -+ u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN, -+ PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); -+ writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); -+ -+ /* -+ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 -+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. -+ */ -+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); -+ tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; -+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); -+ -+ return 0; -+} -+ -+static int brcm_pcie_ofdata_to_platdata(struct udevice *dev) -+{ -+ struct brcm_pcie *pcie = dev_get_priv(dev); -+ ofnode dn = dev_ofnode(dev); -+ u32 max_link_speed; -+ int ret; -+ -+ /* Get the controller base address */ -+ pcie->base = dev_read_addr_ptr(dev); -+ if (!pcie->base) -+ return -EINVAL; -+ -+ pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc"); -+ -+ ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed); -+ if (ret < 0 || max_link_speed > 4) -+ pcie->gen = 0; -+ else -+ pcie->gen = max_link_speed; -+ -+ return 0; -+} -+ -+static const struct dm_pci_ops brcm_pcie_ops = { -+ .read_config = brcm_pcie_read_config, -+ .write_config = brcm_pcie_write_config, -+}; -+ -+static const struct udevice_id brcm_pcie_ids[] = { -+ { .compatible = "brcm,bcm2711-pcie" }, -+ { } -+}; -+ -+U_BOOT_DRIVER(pcie_brcm_base) = { -+ .name = "pcie_brcm", -+ .id = UCLASS_PCI, -+ .ops = &brcm_pcie_ops, -+ .of_match = brcm_pcie_ids, -+ .probe = brcm_pcie_probe, -+ .ofdata_to_platdata = brcm_pcie_ofdata_to_platdata, -+ .priv_auto_alloc_size = sizeof(struct brcm_pcie), -+}; diff --git a/0022-config-Enable-support-for-the-XHCI-.patch b/0022-config-Enable-support-for-the-XHCI-.patch deleted file mode 100644 index b446b28..0000000 --- a/0022-config-Enable-support-for-the-XHCI-.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 7c75345077bc8f04a6a736b8e960df9799de20ac Mon Sep 17 00:00:00 2001 -From: Marek Szyprowski -Date: Mon, 4 May 2020 14:45:23 +0200 -Subject: [PATCH] config: Enable support for the XHCI controller on RPI4 board - -This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI -and USB commands. To get it working one has to call the following commands: -"pci enum; usb start;", thus such commands have been added to the default -"preboot" environment variable. One has to update their environment if it -is already configured to get this feature working out of the box. - -Signed-off-by: Marek Szyprowski -Signed-off-by: Sylwester Nawrocki ---- - configs/rpi_4_32b_defconfig | 9 +++++++++ - configs/rpi_4_defconfig | 9 +++++++++ - configs/rpi_arm64_defconfig | 8 +++++++- - 3 files changed, 25 insertions(+), 1 deletion(-) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index 72cda5d949..1315f7449f 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_DFU=y - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y - CONFIG_ENV_FAT_INTERFACE="mmc" -@@ -28,6 +32,9 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set -@@ -40,6 +47,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 - CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 - CONFIG_USB_GADGET_DWC2_OTG=y - CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_DM_VIDEO=y - # CONFIG_VIDEO_BPP8 is not set - # CONFIG_VIDEO_BPP16 is not set -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index 6d148dab07..5051b8812f 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -8,6 +8,8 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -+CONFIG_USE_PREBOOT=y -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set -@@ -15,6 +17,8 @@ CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_DFU=y - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y - CONFIG_ENV_FAT_INTERFACE="mmc" -@@ -28,6 +32,9 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set -@@ -40,6 +47,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 - CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 - CONFIG_USB_GADGET_DWC2_OTG=y - CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_DM_VIDEO=y - # CONFIG_VIDEO_BPP8 is not set - # CONFIG_VIDEO_BPP16 is not set -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index fea86be8b0..f12d1e340c 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -7,13 +7,14 @@ CONFIG_NR_DRAM_BANKS=2 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_USE_PREBOOT=y --CONFIG_PREBOOT="usb start" -+CONFIG_PREBOOT="pci enum; usb start;" - CONFIG_MISC_INIT_R=y - # CONFIG_DISPLAY_CPUINFO is not set - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_GPIO=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y - CONFIG_CMD_USB=y - CONFIG_CMD_FS_UUID=y - CONFIG_OF_BOARD=y -@@ -26,11 +27,16 @@ CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_BCM2835=y - CONFIG_DM_ETH=y - CONFIG_BCMGENET=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_PCI_BRCMSTB=y - CONFIG_PINCTRL=y - # CONFIG_PINCTRL_GENERIC is not set - # CONFIG_REQUIRE_SERIAL_CONSOLE is not set - CONFIG_USB=y - CONFIG_DM_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PCI=y - CONFIG_USB_DWC2=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y diff --git a/0023-arm-rpi-Add-function-to-trigger-VL8.patch b/0023-arm-rpi-Add-function-to-trigger-VL8.patch deleted file mode 100644 index d4e314a..0000000 --- a/0023-arm-rpi-Add-function-to-trigger-VL8.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 3f74d0b9505c8718bfea156599e35ca260975780 Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Tue, 5 May 2020 18:26:06 +0200 -Subject: [PATCH] arm: rpi: Add function to trigger VL805's firmware load - -On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware -may either be loaded directly from an EEPROM or, if not present, by the -SoC's VideCore (the SoC's co-processor). Introduce the function that -informs VideCore that VL805 may need its firmware loaded. - -Signed-off-by: Nicolas Saenz Julienne ---- - arch/arm/mach-bcm283x/include/mach/mbox.h | 13 +++++++ - arch/arm/mach-bcm283x/include/mach/msg.h | 7 ++++ - arch/arm/mach-bcm283x/msg.c | 45 +++++++++++++++++++++++ - 3 files changed, 65 insertions(+) - -diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h -index 60e226ce1d..2ae2d3d97c 100644 ---- a/arch/arm/mach-bcm283x/include/mach/mbox.h -+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h -@@ -491,6 +491,19 @@ struct bcm2835_mbox_tag_set_palette { - } body; - }; - -+#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 -+ -+struct bcm2835_mbox_tag_pci_dev_addr { -+ struct bcm2835_mbox_tag_hdr tag_hdr; -+ union { -+ struct { -+ u32 dev_addr; -+ } req; -+ struct { -+ } resp; -+ } body; -+}; -+ - /* - * Pass a raw u32 message to the VC, and receive a raw u32 back. - * -diff --git a/arch/arm/mach-bcm283x/include/mach/msg.h b/arch/arm/mach-bcm283x/include/mach/msg.h -index 4afb08631b..f5213dd0e0 100644 ---- a/arch/arm/mach-bcm283x/include/mach/msg.h -+++ b/arch/arm/mach-bcm283x/include/mach/msg.h -@@ -48,4 +48,11 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, - int pixel_order, int alpha_mode, ulong *fb_basep, - ulong *fb_sizep, int *pitchp); - -+/** -+ * bcm2711_notify_vl805_reset() - get vl805's firmware loaded -+ * -+ * @return 0 if OK, -EIO on error -+ */ -+int bcm2711_notify_vl805_reset(void); -+ - #endif -diff --git a/arch/arm/mach-bcm283x/msg.c b/arch/arm/mach-bcm283x/msg.c -index 94b75283f8..f8ef531652 100644 ---- a/arch/arm/mach-bcm283x/msg.c -+++ b/arch/arm/mach-bcm283x/msg.c -@@ -40,6 +40,12 @@ struct msg_setup { - u32 end_tag; - }; - -+struct msg_notify_vl805_reset { -+ struct bcm2835_mbox_hdr hdr; -+ struct bcm2835_mbox_tag_pci_dev_addr dev_addr; -+ u32 end_tag; -+}; -+ - int bcm2835_power_on_module(u32 module) - { - ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1); -@@ -151,3 +157,42 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp, - - return 0; - } -+ -+/* -+ * The Raspberry Pi 4 gets its USB functionality from VL805, a PCIe chip that -+ * implements xHCI. After a PCI reset, VL805's firmware may either be loaded -+ * directly from an EEPROM or, if not present, by the SoC's co-processor, -+ * VideoCore. RPi4's VideoCore OS contains both the non public firmware load -+ * logic and the VL805 firmware blob. This function triggers the aforementioned -+ * process. -+ */ -+int bcm2711_notify_vl805_reset(void) -+{ -+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset, -+ msg_notify_vl805_reset, 1); -+ int ret; -+ -+ BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset); -+ BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr, -+ NOTIFY_XHCI_RESET); -+ -+ /* -+ * The pci device address is expected like this: -+ * -+ * PCI_BUS << 20 | PCI_SLOT << 15 | PCI_FUNC << 12 -+ * -+ * But since RPi4's PCIe setup is hardwired, we know the address in -+ * advance. -+ */ -+ msg_notify_vl805_reset->dev_addr.body.req.dev_addr = 0x100000; -+ -+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, -+ &msg_notify_vl805_reset->hdr); -+ if (ret) { -+ printf("bcm2711: Faild to load vl805's firmware, %d\n", ret); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ diff --git a/0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch b/0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch deleted file mode 100644 index 5910122..0000000 --- a/0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch +++ /dev/null @@ -1,85 +0,0 @@ -From e5fa3a00fbbe9b19f0fa76e0c497e9d5acf940d6 Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Tue, 5 May 2020 18:26:07 +0200 -Subject: [PATCH] usb: xhci: Load Raspberry Pi 4 VL805's firmware - -When needed, RPi4's co-processor (called VideoCore) has to be instructed -to load VL805's firmware (the chip providing xHCI support). VideCore's -firmware expects the board's PCIe bus to be already configured in order -for it to load the xHCI chip firmware. So we have to make sure this -happens in between the PCIe configuration and xHCI startup. - -Introduce a callback in xhci_pci_probe() to run this platform specific -routine. - -Signed-off-by: Nicolas Saenz Julienne ---- - board/raspberrypi/rpi/rpi.c | 6 ++++++ - drivers/usb/host/xhci-pci.c | 6 ++++++ - include/usb/xhci.h | 3 +++ - 3 files changed, 15 insertions(+) - -diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c -index e367ba3092..dcaf45fbf2 100644 ---- a/board/raspberrypi/rpi/rpi.c -+++ b/board/raspberrypi/rpi/rpi.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -494,3 +495,8 @@ int ft_board_setup(void *blob, bd_t *bd) - - return 0; - } -+ -+void xhci_pci_fixup(struct udevice *dev) -+{ -+ bcm2711_notify_vl805_reset(); -+} -diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c -index c1f60da541..1285dde1ef 100644 ---- a/drivers/usb/host/xhci-pci.c -+++ b/drivers/usb/host/xhci-pci.c -@@ -11,6 +11,10 @@ - #include - #include - -+__weak void xhci_pci_fixup(struct udevice *dev) -+{ -+} -+ - static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, - struct xhci_hcor **ret_hcor) - { -@@ -40,6 +44,8 @@ static int xhci_pci_probe(struct udevice *dev) - struct xhci_hccr *hccr; - struct xhci_hcor *hcor; - -+ xhci_pci_fixup(dev); -+ - xhci_pci_init(dev, &hccr, &hcor); - - return xhci_register(dev, hccr, hcor); -diff --git a/include/usb/xhci.h b/include/usb/xhci.h -index c16106a2fc..57feed7603 100644 ---- a/include/usb/xhci.h -+++ b/include/usb/xhci.h -@@ -16,6 +16,7 @@ - #ifndef HOST_XHCI_H_ - #define HOST_XHCI_H_ - -+#include - #include - #include - #include -@@ -1281,4 +1282,6 @@ extern struct dm_usb_ops xhci_usb_ops; - - struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev); - -+extern void xhci_pci_fixup(struct udevice *dev); -+ - #endif /* HOST_XHCI_H_ */ diff --git a/0025-config-Enable-USB-Keyboard-support-.patch b/0025-config-Enable-USB-Keyboard-support-.patch deleted file mode 100644 index 8871d1f..0000000 --- a/0025-config-Enable-USB-Keyboard-support-.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 8ae0b68bf17266338e1b5a91cc987f8f2dcba1ab Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Tue, 5 May 2020 16:51:29 +0200 -Subject: [PATCH] config: Enable USB Keyboard support on RPi4 - -Supporting USB keyboards out of the box is both handy for development -and production. Notably if u-boot is used to boot into GRUB. - -Signed-off-by: Nicolas Saenz Julienne -Reviewed-by: Sylwester Nawrocki -Reviewed-by: Bin Meng ---- - configs/rpi_4_32b_defconfig | 1 + - configs/rpi_4_defconfig | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index 1315f7449f..2c5539102e 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -49,6 +49,7 @@ CONFIG_USB_GADGET_DWC2_OTG=y - CONFIG_USB_GADGET_DOWNLOAD=y - CONFIG_USB_XHCI_HCD=y - CONFIG_USB_XHCI_PCI=y -+CONFIG_USB_KEYBOARD=y - CONFIG_DM_VIDEO=y - # CONFIG_VIDEO_BPP8 is not set - # CONFIG_VIDEO_BPP16 is not set -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index 5051b8812f..6f34ae9fbd 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -49,6 +49,7 @@ CONFIG_USB_GADGET_DWC2_OTG=y - CONFIG_USB_GADGET_DOWNLOAD=y - CONFIG_USB_XHCI_HCD=y - CONFIG_USB_XHCI_PCI=y -+CONFIG_USB_KEYBOARD=y - CONFIG_DM_VIDEO=y - # CONFIG_VIDEO_BPP8 is not set - # CONFIG_VIDEO_BPP16 is not set diff --git a/0026-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch b/0026-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch deleted file mode 100644 index 0e00843..0000000 --- a/0026-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 48529fd9c115753681dadb215af891cc860c5d29 Mon Sep 17 00:00:00 2001 -From: Matthias Brugger -Date: Fri, 29 May 2020 16:42:22 +0200 -Subject: [PATCH] configs: rpi: set NR_DRAM_BANKS to four - -With the new RPi4 which has 8 GB of RAM, we can have up to four DRAM -banks. Bump up the configuration files to detect all the memory in -U-Boot. - -Signed-off-by: Matthias Brugger -(cherry picked from commit a61cf765f7e3a4ba80453150e16acaaecbd913ac) ---- - configs/rpi_4_32b_defconfig | 2 +- - configs/rpi_4_defconfig | 2 +- - configs/rpi_arm64_defconfig | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig -index 2c5539102e..6a9fa49e3d 100644 ---- a/configs/rpi_4_32b_defconfig -+++ b/configs/rpi_4_32b_defconfig -@@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000 - CONFIG_TARGET_RPI_4_32B=y - CONFIG_SYS_MALLOC_F_LEN=0x2000 - CONFIG_ENV_SIZE=0x4000 --CONFIG_NR_DRAM_BANKS=2 -+CONFIG_NR_DRAM_BANKS=4 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig -index 6f34ae9fbd..137c03e4d8 100644 ---- a/configs/rpi_4_defconfig -+++ b/configs/rpi_4_defconfig -@@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x00080000 - CONFIG_TARGET_RPI_4=y - CONFIG_SYS_MALLOC_F_LEN=0x2000 - CONFIG_ENV_SIZE=0x4000 --CONFIG_NR_DRAM_BANKS=2 -+CONFIG_NR_DRAM_BANKS=4 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig -index f12d1e340c..ea73bee5ac 100644 ---- a/configs/rpi_arm64_defconfig -+++ b/configs/rpi_arm64_defconfig -@@ -3,7 +3,7 @@ CONFIG_ARCH_BCM283X=y - CONFIG_SYS_TEXT_BASE=0x00080000 - CONFIG_TARGET_RPI_ARM64=y - CONFIG_SYS_MALLOC_F_LEN=0x2000 --CONFIG_NR_DRAM_BANKS=2 -+CONFIG_NR_DRAM_BANKS=4 - CONFIG_DISTRO_DEFAULTS=y - CONFIG_OF_BOARD_SETUP=y - CONFIG_USE_PREBOOT=y diff --git a/_multibuild b/_multibuild index e485592..8ae9988 100644 --- a/_multibuild +++ b/_multibuild @@ -36,6 +36,7 @@ ls1012afrdmqspi melea1000 merriia80optimus + mt7623nbpir2 mvebudb-88f3720 mvebudbarmada8k mvebuespressobin-88f3720 @@ -54,6 +55,7 @@ omap4panda orangepipc orangepipc2 + orangepizero p2371-2180 p2771-0000-500 p3450-0000 diff --git a/u-boot-2020.04.tar.bz2 b/u-boot-2020.04.tar.bz2 deleted file mode 100644 index 264bda2..0000000 --- a/u-boot-2020.04.tar.bz2 +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372 -size 15065656 diff --git a/u-boot-2020.04.tar.bz2.sig b/u-boot-2020.04.tar.bz2.sig deleted file mode 100644 index b789fd7a03db3a878c956647e1e17d2bf5b5e5cd78204c1654a2985ff38dd0cd..0000000000000000000000000000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 586 zcmV-Q0=4~#0!IV@0SW*y79j-aa@#NOSUVTjn{ zSSuZW#+NNPeHJy;h&xfA%-;`5bu#%?XuL1F1i50_xOkCWm5N^y@s9n#6Uj-x73?i> z7n8V}Ei4y%Z(hnZw{pF9;z`yE6$y*@^?lq>P$r)133#=uZ_xwJd6P+zHbqhD9joOU zdIR3uEVW=0uVXhx7j}~f%4=S@DuCbI+-eRW0zCncpAdKstbp(1MiF| zErnUDxlhSQNA7rv8@Qp~RB!WQIM8|V*Q)IOI&;C>i!sQ3ZAZy!_eh3pj^?{fY`<@V z4~=AZybJ6TuiQ*7@Ci)DVx9tR{mPod459zS!)+;mfDK}W#+;Fa(ccf7rvGhyZd_!d z`N$G_f};yIt{P#!s5v&*EucrN(ly0LX+HDHV%uR{`%kfU+!d{2P-VL3vlFnF#^qyo Ypd&(mWR{Q6bYw=NshUx+`#WW*6-C|>FOCeJe32#xN~6Ycoxk|(=Yqq9Dg zk1kyx2`b?(u z84P0|jlK}*N@S1)xKoL1{=K`&acCM$V+bkaTF+y&X=vSC5F38y?gJITmjC(NosIp& zVueoE-Pz~khX>-J2{-76il8p$`$kxW)&e>)@}WXpcbjs|0F?S&HG|TK=rO#vV>z5w zy0JfB3rG~L2NTqvO=2QqMKpw78O-n5*>m6(CxwHZ!_$~4E;}(JA=UTH{=jDg*y6CO z*ycjTFuaKS + +- Update to v2020.10 + +------------------------------------------------------------------- +Tue Oct 6 13:05:30 UTC 2020 - Andreas Schwab + +- Enable SPL on SiFive FU540 + +------------------------------------------------------------------- +Thu Oct 1 14:45:44 UTC 2020 - Matthias Brugger + +Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.10 +* Patches added: + 0011-sunxi-dts-OrangePi-Zero-Add-SPI-ali.patch + 0012-sunxi-dts-OrangePi-Zero-Enable-SPI-.patch + 0013-sunxi-Enable-SPI-support-on-Orange-.patch + +------------------------------------------------------------------- +Wed Sep 30 18:31:44 UTC 2020 - Michal Suchanek + +- Add Orange Pi Zero build + +------------------------------------------------------------------- +Thu Sep 29 14:57:56 UTC 2020 - Matthias Brugger + +- Add Bananpi-R2 build + +------------------------------------------------------------------- +Tue Sep 29 12:56:10 UTC 2020 - Guillaume GARDET + +* Update to v2020.10-rc5 +Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.10 +* Patches dropped: + 0011-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch + +------------------------------------------------------------------- +Fri Sep 18 13:41:20 UTC 2020 - Guillaume GARDET + +* Update to v2020.10-rc4 +Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.10 +* Patches dropped: + 0011-usb-xhci-Add-missing-cache-flush-in.patch + 0012-usb-xhci-Use-only-32-bit-accesses-i.patch + 0013-pci-Move-some-PCIe-register-offset-.patch + 0014-rpi4-shorten-a-mapping-for-the-DRAM.patch + 0015-rpi4-add-a-mapping-for-the-PCIe-XHC.patch + 0016-linux-bitfield.h-Add-primitives-for.patch + 0017-pci-Add-some-PCI-Express-capability.patch + 0018-pci-Add-driver-for-Broadcom-STB-PCI.patch + 0019-config-Enable-support-for-the-XHCI-.patch + 0020-arm-rpi-Add-function-to-trigger-VL8.patch + 0021-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch + 0022-config-Enable-USB-Keyboard-support-.patch + 0023-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch +* Patches added: + 0011-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch + ------------------------------------------------------------------- Sun Aug 9 19:41:12 UTC 2020 - Matwey Kornilov - Use python3 for pyelftools +------------------------------------------------------------------- +Wed Jul 15 11:29:18 UTC 2020 - Guillaume GARDET + +* Update to v2020.07 + Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.07 +* Patches dropped: + 0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch + 0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch + 0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch + 0014-usb-xhci-Add-missing-cache-flush-in.patch + 0015-usb-xhci-Use-only-32-bit-accesses-i.patch + 0016-pci-Move-some-PCIe-register-offset-.patch + 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch + 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch + 0019-linux-bitfield.h-Add-primitives-for.patch + 0020-pci-Add-some-PCI-Express-capability.patch + 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch + 0022-config-Enable-support-for-the-XHCI-.patch + 0023-arm-rpi-Add-function-to-trigger-VL8.patch + 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch + 0025-config-Enable-USB-Keyboard-support-.patch + 0026-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch +* Patches added: + 0011-usb-xhci-Add-missing-cache-flush-in.patch + 0012-usb-xhci-Use-only-32-bit-accesses-i.patch + 0013-pci-Move-some-PCIe-register-offset-.patch + 0014-rpi4-shorten-a-mapping-for-the-DRAM.patch + 0015-rpi4-add-a-mapping-for-the-PCIe-XHC.patch + 0016-linux-bitfield.h-Add-primitives-for.patch + 0017-pci-Add-some-PCI-Express-capability.patch + 0018-pci-Add-driver-for-Broadcom-STB-PCI.patch + 0019-config-Enable-support-for-the-XHCI-.patch + 0020-arm-rpi-Add-function-to-trigger-VL8.patch + 0021-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch + 0022-config-Enable-USB-Keyboard-support-.patch + 0023-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch + ------------------------------------------------------------------- Tue Jun 2 06:54:36 UTC 2020 - Matthias Brugger diff --git a/u-boot.spec b/u-boot.spec index 6d44a43..0c7b34e 100644 --- a/u-boot.spec +++ b/u-boot.spec @@ -83,6 +83,11 @@ %define sunxi_spl 1 %define binext .itb %endif + +%if "%target" == "mt7623nbpir2" +%define is_armv7 1 +%endif + %if "%target" == "orangepipc2" %define is_h5 1 %define is_armv8 1 @@ -95,7 +100,7 @@ %define sunxi_spl 1 %define binext .itb %endif -%if "%target" == "bananapi" || "%target" == "cubieboard" || "%target" == "cubieboard2" || "%target" == "cubietruck" || "%target" == "melea1000" || "%target" == "a10-olinuxino-lime" || "%target" == "a13-olinuxino" || "%target" == "a13-olinuxinom" || "%target" == "a20-olinuxino-lime" || "%target" == "a20-olinuxino-lime2" || "%target" == "a20-olinuxinomicro" || "%target" == "nanopineo" || "%target" == "orangepipc" || "%target" == "hyundaia7hd" || "%target" == "lamobor1" || "%target" == "bananapim2plush3" +%if "%target" == "bananapi" || "%target" == "cubieboard" || "%target" == "cubieboard2" || "%target" == "cubietruck" || "%target" == "melea1000" || "%target" == "a10-olinuxino-lime" || "%target" == "a13-olinuxino" || "%target" == "a13-olinuxinom" || "%target" == "a20-olinuxino-lime" || "%target" == "a20-olinuxino-lime2" || "%target" == "a20-olinuxinomicro" || "%target" == "nanopineo" || "%target" == "orangepipc" || "%target" == "hyundaia7hd" || "%target" == "lamobor1" || "%target" == "bananapim2plush3" || "%target" == "orangepizero" %define is_armv7 1 %define binext .img %define sunxi_spl 1 @@ -154,12 +159,15 @@ %endif %if "%target" == "qemu-riscv64" || "%target" == "qemu-riscv64smode" || "%target" == "sifivefu540" %define is_riscv64 1 +%if "%target" == "sifivefu540" +%define binext .itb +%endif %endif %if "%target" == "qemu-ppce500" %define is_ppc 1 %endif # archive_version differs from version for RC version only -%define archive_version 2020.04 +%define archive_version 2020.10 %if "%{target}" == "" ExclusiveArch: do_not_build %else @@ -191,7 +199,7 @@ ExclusiveArch: do_not_build %endif %bcond_with uboot_atf %bcond_with uboot_atf_pine64 -Version: 2020.04 +Version: 2020.10 Release: 0 Summary: The U-Boot firmware for the %target platform License: GPL-2.0-only @@ -213,22 +221,9 @@ Patch0007: 0007-boo-1144161-Remove-nand-mtd-spi-dfu.patch Patch0008: 0008-Kconfig-add-btrfs-to-distro-boot.patch Patch0009: 0009-configs-Re-sync-with-CONFIG_DISTRO_.patch Patch0010: 0010-configs-am335x_evm-disable-BTRFS.patch -Patch0011: 0011-net-bcmgenet-Don-t-set-ID_MODE_DIS-.patch -Patch0012: 0012-uboot-fs-btrfs-Use-LZO_LEN-to-repla.patch -Patch0013: 0013-uboot-fs-btrfs-Fix-LZO-false-decomp.patch -Patch0014: 0014-usb-xhci-Add-missing-cache-flush-in.patch -Patch0015: 0015-usb-xhci-Use-only-32-bit-accesses-i.patch -Patch0016: 0016-pci-Move-some-PCIe-register-offset-.patch -Patch0017: 0017-rpi4-shorten-a-mapping-for-the-DRAM.patch -Patch0018: 0018-rpi4-add-a-mapping-for-the-PCIe-XHC.patch -Patch0019: 0019-linux-bitfield.h-Add-primitives-for.patch -Patch0020: 0020-pci-Add-some-PCI-Express-capability.patch -Patch0021: 0021-pci-Add-driver-for-Broadcom-STB-PCI.patch -Patch0022: 0022-config-Enable-support-for-the-XHCI-.patch -Patch0023: 0023-arm-rpi-Add-function-to-trigger-VL8.patch -Patch0024: 0024-usb-xhci-Load-Raspberry-Pi-4-VL805-.patch -Patch0025: 0025-config-Enable-USB-Keyboard-support-.patch -Patch0026: 0026-configs-rpi-set-NR_DRAM_BANKS-to-fo.patch +Patch0011: 0011-sunxi-dts-OrangePi-Zero-Add-SPI-ali.patch +Patch0012: 0012-sunxi-dts-OrangePi-Zero-Enable-SPI-.patch +Patch0013: 0013-sunxi-Enable-SPI-support-on-Orange-.patch # Patches: end BuildRequires: bc BuildRequires: bison @@ -306,6 +301,9 @@ BuildRequires: zynqmp-dts # For mountpoint Requires(post): util-linux %endif +%if "%{name}" == "u-boot-sifivefu540" +BuildRequires: opensbi-sifivefu540 >= 0.7 +%endif %if %x_loader == 1 Obsoletes: x-loader-%target Provides: x-loader-%target @@ -377,6 +375,9 @@ export BL31=%{_datadir}/arm-trusted-firmware-sun50ia64/bl31.bin %if 0%{?is_h6} export BL31=%{_datadir}/arm-trusted-firmware-sun50ih6/bl31.bin %endif +%if "%{name}" == "u-boot-sifivefu540" +export OPENSBI=%{_datadir}/opensbi/opensbi-sifive-fu540.bin +%endif %if %{with uboot_atf} %if "%{name}" == "u-boot-rock64-rk3328" @@ -524,6 +525,9 @@ echo -e "\nkernel_address=0x11000000" >> %{buildroot}%{uboot_dir}/ubootconfig.tx %if "%{name}" == "u-boot-rpi4" || "%{name}" == "u-boot-rpiarm64" echo -e "# Boot in AArch64 mode\narm_64bit=1" > %{buildroot}%{uboot_dir}/ubootconfig.txt %endif +%if "%{name}" == "u-boot-sifivefu540" +install -D -m 0644 spl/u-boot-spl.bin %{buildroot}%{uboot_dir}/u-boot-spl.bin +%endif %if 0%{?is_rpi} %post diff --git a/update_git.sh b/update_git.sh index 1de623a..e4e1668 100644 --- a/update_git.sh +++ b/update_git.sh @@ -13,8 +13,8 @@ set -e GIT_TREE=git://github.com/openSUSE/u-boot.git GIT_LOCAL_TREE=~/git/u-boot-opensuse -GIT_BRANCH=tumbleweed-2020.04 -GIT_UPSTREAM_TAG=v2020.04 +GIT_BRANCH=tumbleweed-2020.10 +GIT_UPSTREAM_TAG=v2020.10 GIT_DIR=/dev/shm/u-boot-factory-git-dir CMP_DIR=/dev/shm/u-boot-factory-cmp-dir