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Accepting request 768266 from hardware:boot

Browse Source 
Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.01
  Add support for Jetson Nano.
  Enable btrfs by default. (jsc#SLE-10302)
  Add network support for RPi4 (jsc#SLE-7276)
* Patches added:
  0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch
  0011-net-Add-support-for-Broadcom-GENETv.patch
  0012-rpi4-Update-memory-map-to-accommoda.patch
  0013-rpi4-Enable-GENET-Ethernet-controll.patch
  0014-Kconfig-add-btrfs-to-distro-boot.patch
  0015-configs-Re-sync-with-CONFIG_DISTRO_.patch
  0016-configs-am335x_evm-disable-BTRFS.patch

- Fix firefly-rk3288 and tinker-rk3288 by using TPL instead of SPL
  (SPL too big)

- Fix mx6qsabrelite build

- Update to v2020.01:
  * Now requires python 3.5+ (2.x support dropped)
  * Add Orange Pi Zero Plus 2 support
  * Platfrom fixes: atmel, fsl, imx, Marvell, RPi, rockchip, sunxi, TI
  * EFI fixes
  * I2C fixes
  * MMC fixes
  * SPI fixes
  * USB fixes
- Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.01
  * Patches dropped:
    0009-libfdt-fdt_address_cells-and-fdt_si.patch
    0010-libfdt-return-correct-value-if-size.patch
    0011-libfdt-Allow-size-cells-of-0.patch
    0012-dm-Fix-default-address-cells-return.patch
    0013-arm-arm11-allow-unaligned-memory-ac.patch
    0014-fdt-fix-bcm283x-dm-pre-reloc-defini.patch
    0015-arm-dts-bcm283x-Rename-U-Boot-file.patch
    0016-drivers-bcm283x-Set-pre-location-fl.patch
    0017-pinctrl-bcm283x-Add-compatible-for-.patch
    0018-rpi-push-fw_dtb_pointer-in-the-.dat.patch
    0019-ARM-bcm283x-Move-BCM283x_BASE-to-a-.patch
    0020-ARM-bcm283x-Set-rpi_bcm283x_base-at.patch
    0021-ARM-bcm283x-Set-memory-map-at-run-t.patch
    0022-ARM-defconfig-add-unified-config-fo.patch
    0023-boo-1144161-Remove-nand-mtd-spi-dfu.patch
    0024-rpi-fix-dram-bank-initialization.patch
    0025-rpi-Enable-DRAM-bank-initialization.patch
    0026-ARM-defconfig-Fix-32bit-config-for-.patch
  * Patches added:
    0009-boo-1144161-Remove-nand-mtd-spi-dfu.patch

OBS-URL: https://build.opensuse.org/request/show/768266
OBS-URL: https://build.opensuse.org/package/show/openSUSE:Factory/u-boot?expand=0&rev=121
This commit is contained in:
Dominique Leuenberger 2020-01-29 12:15:48 +00:00 committed by Git OBS Bridge
commit f003106d9f
41 changed files with 1988 additions and 1298 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
0001-XXX-openSUSE-XXX-Prepend-partition-.patch
View File

@ -1,4 +1,4 @@
From 5c52feb96a63368a7b8d7fa09e03e72dd9518474 Mon Sep 17 00:00:00 2001
From b7b82306b7a5bd33c353c53341b143966b41d2bc Mon Sep 17 00:00:00 2001
From: Guillaume GARDET <guillaume.gardet@free.fr>
Date: Wed, 13 Apr 2016 13:44:29 +0200
Subject: [PATCH] XXX openSUSE XXX: Prepend partition 2 (and 3 fo chromebook
@ -10,7 +10,7 @@ Subject: [PATCH] XXX openSUSE XXX: Prepend partition 2 (and 3 fo chromebook
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 3570a32dff..a8b93ca50b 100644
index fc0935fa21..54fe9391fd 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -141,7 +141,7 @@
@ -22,7 +22,7 @@ index 3570a32dff..a8b93ca50b 100644
"scan_dev_for_efi=" \
"setenv efi_fdtfile ${fdtfile}; " \
BOOTENV_EFI_SET_FDTFILE_FALLBACK \
@@ -465,7 +465,7 @@
@@ -466,7 +466,7 @@
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} -bootable devplist; " \
"env exists devplist || setenv devplist 1; " \

2
0002-Revert-Revert-omap3-Use-raw-SPL-by-.patch
View File

@ -1,4 +1,4 @@
From cd627d9bf2149929301bafdcea8deb097f09986a Mon Sep 17 00:00:00 2001
From 1798872d0b37adcdd850c46d949338ef3b428e0d Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Mon, 2 May 2016 23:25:07 +0200
Subject: [PATCH] Revert "Revert "omap3: Use raw SPL by default for mmc1""

12
0003-rpi-Use-firmware-provided-device-tr.patch
View File

@ -1,4 +1,4 @@
From 79010f19df5787e201b2c9e7c6f54d70ac5c2ef6 Mon Sep 17 00:00:00 2001
From 741743044fdc2008ea45ac7f271daa567c4dd9f0 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Wed, 21 Feb 2018 17:41:13 +0100
Subject: [PATCH] rpi: Use firmware provided device tree
@ -28,7 +28,7 @@ Signed-off-by: Guillaume Gardet <guillaume.gardet@free.fr>
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index fe5a7763a6..ed7f9381e9 100644
index 75c6c9c447..6e7fe71bbf 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
@ -41,7 +41,7 @@ index fe5a7763a6..ed7f9381e9 100644
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index bf331c0ad0..52e3c3b234 100644
index 4e8204ef88..b5b7a08698 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y
@ -54,7 +54,7 @@ index bf331c0ad0..52e3c3b234 100644
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index c2417a0ec9..191962f0f7 100644
index d50953287c..4b9f61b2b2 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y
@ -67,7 +67,7 @@ index c2417a0ec9..191962f0f7 100644
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 4fa682539c..03a2356d3d 100644
index c0c0955131..ce7813fb1f 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -18,7 +18,7 @@ CONFIG_CMD_GPIO=y
@ -80,7 +80,7 @@ index 4fa682539c..03a2356d3d 100644
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 2c04b3334e..bf00d8b669 100644
index 2f4c7da6dc..063ec9f196 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -17,7 +17,7 @@ CONFIG_CMD_GPIO=y

6
0004-Temp-workaround-for-Chromebook-snow.patch
View File

@ -1,4 +1,4 @@
From 9fb72dbb5f4bb92e9ce294f91aaf1f48af92e6c0 Mon Sep 17 00:00:00 2001
From f0bc44197a99ff78759064332e88bc6656ae3c38 Mon Sep 17 00:00:00 2001
From: Guillaume GARDET <guillaume.gardet@free.fr>
Date: Mon, 9 Apr 2018 10:28:26 +0200
Subject: [PATCH] Temp workaround for Chromebook snow to avoid the 'unable to
@ -9,10 +9,10 @@ Subject: [PATCH] Temp workaround for Chromebook snow to avoid the 'unable to
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index ebe7bcdd90..de0c11852a 100644
index 1224540811..5c1cac97e4 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -599,7 +599,8 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
@@ -600,7 +600,8 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
cfg->host_caps |= MMC_MODE_4BIT;
cfg->host_caps &= ~MMC_MODE_8BIT;
}

2
0005-zynqmp-Add-generic-target.patch
View File

@ -1,4 +1,4 @@
From 5cca414fc09b0819289d32d2994eb21daa82c068 Mon Sep 17 00:00:00 2001
From 2e8cd6c9e8d9cc22a40cd98d45a0f2797587c280 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Tue, 24 Apr 2018 21:25:23 +0200
Subject: [PATCH] zynqmp: Add generic target

4
0006-tools-zynqmpbif-Add-support-for-loa.patch
View File

@ -1,4 +1,4 @@
From dc7797478604d41d2f002f885cd2a8cd3d22fd19 Mon Sep 17 00:00:00 2001
From 8ee3e6d2312ebdd3868520fb528249816c3cb975 Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Thu, 26 Apr 2018 13:30:32 +0200
Subject: [PATCH] tools: zynqmpbif: Add support for load=after
@ -34,7 +34,7 @@ Signed-off-by: Alexander Graf <agraf@suse.de>
1 file changed, 15 insertions(+)
diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c
index 8c47107c7b..591bec8e59 100644
index 82ce0ac1a5..b4302fa67e 100644
--- a/tools/zynqmpbif.c
+++ b/tools/zynqmpbif.c
@@ -42,6 +42,7 @@ enum bif_flag {

12
0007-boo-1123170-Remove-ubifs-support-fr.patch
View File

@ -1,4 +1,4 @@
From e9bcf78e73609a32d15699f0a6bc2e0cd9e08b0d Mon Sep 17 00:00:00 2001
From 98e9215b94ac8e2e5a8d545ad05b2ff0f9429bcc Mon Sep 17 00:00:00 2001
From: Guillaume GARDET <guillaume.gardet@free.fr>
Date: Tue, 29 Jan 2019 11:38:12 +0100
Subject: [PATCH] boo#1123170: Remove ubifs support from omap3_beagle to keep a
@ -10,7 +10,7 @@ Subject: [PATCH] boo#1123170: Remove ubifs support from omap3_beagle to keep a
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index bf49de4704..90ae0c3b90 100644
index ed7cb8f2ff..03dc3b27d4 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -38,7 +38,6 @@ CONFIG_CMD_FS_UUID=y
@ -21,7 +21,7 @@ index bf49de4704..90ae0c3b90 100644
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
@@ -72,6 +71,7 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
@@ -73,6 +72,7 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
@ -30,14 +30,14 @@ index bf49de4704..90ae0c3b90 100644
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index e8c60838b7..99cd59d40e 100644
index bc8aa7adf5..ee1d36003e 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -83,7 +83,6 @@
@@ -82,7 +82,6 @@
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(LEGACY_MMC, legacy_mmc, 0) \
- func(UBIFS, ubifs, 0) \
func(NAND, nand, 0)
#else /* !CONFIG_NAND */
#else /* !CONFIG_MTD_RAW_NAND */

2
0008-zynqmp-generic-fix-compilation.patch
View File

@ -1,4 +1,4 @@
From c34095d98fe8d6422ea8a71e8f1df9e5a7caf2c0 Mon Sep 17 00:00:00 2001
From 115e64c42f32f158728ef1747b707adbb61d8bd2 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Tue, 5 Mar 2019 18:09:04 +0100
Subject: [PATCH] zynqmp: generic: fix compilation

31
0023-boo-1144161-Remove-nand-mtd-spi-dfu.patch → 0009-boo-1144161-Remove-nand-mtd-spi-dfu.patch
View File

@ -1,18 +1,18 @@
From f0deddd8100d62928b9d6a69a89557565314f7bd Mon Sep 17 00:00:00 2001
From: Guillaume GARDET <guillaume.gardet@free.fr>
Date: Thu, 5 Dec 2019 15:17:52 +0100
From 06001132d3503a4e2db4d71fe380bb75115930f7 Mon Sep 17 00:00:00 2001
From: Guillaume Gardet <guillaume.gardet@arm.com>
Date: Mon, 16 Dec 2019 17:51:17 +0100
Subject: [PATCH] boo#1144161: Remove nand/mtd/spi/dfu/fastboot support from
am335x_evm to keep a small u-boot.img
---
configs/am335x_evm_defconfig | 23 +++--------------------
1 file changed, 3 insertions(+), 20 deletions(-)
configs/am335x_evm_defconfig | 23 ++---------------------
1 file changed, 2 insertions(+), 21 deletions(-)
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 2aa9b65caf..1bdb2bf091 100644
index 335aa8cfa1..ccb11c9b2a 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -15,21 +15,17 @@ CONFIG_ARCH_MISC_INIT=y
@@ -15,21 +15,16 @@ CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_ETH_SUPPORT=y
# CONFIG_SPL_FS_EXT4 is not set
@ -26,9 +26,9 @@ index 2aa9b65caf..1bdb2bf091 100644
CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x00080000
+# CONFIG_CMD_DM is not set
# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_NAND=y
+# CONFIG_CMD_DM is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
@ -36,10 +36,10 @@ index 2aa9b65caf..1bdb2bf091 100644
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
@@ -37,32 +33,20 @@ CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bone
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_ENV_IS_NOWHERE=y
@@ -40,32 +35,19 @@ CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK=y
CONFIG_CLK_CDCE9XX=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_NAND=y
-CONFIG_DFU_RAM=y
@ -49,12 +49,11 @@ index 2aa9b65caf..1bdb2bf091 100644
CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=24000000
-CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_MTD_DEVICE=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
@ -70,7 +69,7 @@ index 2aa9b65caf..1bdb2bf091 100644
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
@@ -70,7 +54,6 @@ CONFIG_USB_GADGET=y
@@ -73,7 +55,6 @@ CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022

100
0009-libfdt-fdt_address_cells-and-fdt_si.patch
View File

@ -1,100 +0,0 @@
From 082fa10793d12601ba9480c5d57a06c531505a82 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Thu, 5 Sep 2019 10:48:46 +0200
Subject: [PATCH] libfdt: fdt_address_cells() and fdt_size_cells()
Add internal fdt_cells() to avoid copy and paste. Fix typo in
fdt_size_cells() documentation comment.
This is based in upstream commit:
c12b2b0 ("libfdt: fdt_address_cells() and fdt_size_cells()")
but misses the test cases, as we don't implement them in U-Boot.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit b3bec26ecd6ef446a9c11504d414a50453eefe62)
---
scripts/dtc/libfdt/fdt_addresses.c | 35 +++++++++++-------------------
scripts/dtc/libfdt/libfdt.h | 2 +-
2 files changed, 14 insertions(+), 23 deletions(-)
diff --git a/scripts/dtc/libfdt/fdt_addresses.c b/scripts/dtc/libfdt/fdt_addresses.c
index eff4dbcc72..49537b578d 100644
--- a/scripts/dtc/libfdt/fdt_addresses.c
+++ b/scripts/dtc/libfdt/fdt_addresses.c
@@ -1,6 +1,7 @@
/*
* libfdt - Flat Device Tree manipulation
* Copyright (C) 2014 David Gibson <david@gibson.dropbear.id.au>
+ * Copyright (C) 2018 embedded brains GmbH
*
* libfdt is dual licensed: you can use it either under the terms of
* the GPL, or the BSD license, at your option.
@@ -55,42 +56,32 @@
#include "libfdt_internal.h"
-int fdt_address_cells(const void *fdt, int nodeoffset)
+static int fdt_cells(const void *fdt, int nodeoffset, const char *name)
{
- const fdt32_t *ac;
+ const fdt32_t *c;
int val;
int len;
- ac = fdt_getprop(fdt, nodeoffset, "#address-cells", &len);
- if (!ac)
+ c = fdt_getprop(fdt, nodeoffset, name, &len);
+ if (!c)
return 2;
- if (len != sizeof(*ac))
+ if (len != sizeof(*c))
return -FDT_ERR_BADNCELLS;
- val = fdt32_to_cpu(*ac);
+ val = fdt32_to_cpu(*c);
if ((val <= 0) || (val > FDT_MAX_NCELLS))
return -FDT_ERR_BADNCELLS;
return val;
}
-int fdt_size_cells(const void *fdt, int nodeoffset)
+int fdt_address_cells(const void *fdt, int nodeoffset)
{
- const fdt32_t *sc;
- int val;
- int len;
-
- sc = fdt_getprop(fdt, nodeoffset, "#size-cells", &len);
- if (!sc)
- return 2;
-
- if (len != sizeof(*sc))
- return -FDT_ERR_BADNCELLS;
-
- val = fdt32_to_cpu(*sc);
- if ((val < 0) || (val > FDT_MAX_NCELLS))
- return -FDT_ERR_BADNCELLS;
+ return fdt_cells(fdt, nodeoffset, "#address-cells");
+}
- return val;
+int fdt_size_cells(const void *fdt, int nodeoffset)
+{
+ return fdt_cells(fdt, nodeoffset, "#size-cells");
}
diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h
index cf86ddba88..66f01fec53 100644
--- a/scripts/dtc/libfdt/libfdt.h
+++ b/scripts/dtc/libfdt/libfdt.h
@@ -1109,7 +1109,7 @@ int fdt_address_cells(const void *fdt, int nodeoffset);
*
* returns:
* 0 <= n < FDT_MAX_NCELLS, on success
- * 2, if the node has no #address-cells property
+ * 2, if the node has no #size-cells property
* -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
* #size-cells property
* -FDT_ERR_BADMAGIC,

845
0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch Normal file
View File

@ -0,0 +1,845 @@
From f7f2956544c8c09e18d73ef53e3742120a352870 Mon Sep 17 00:00:00 2001
From: Thierry Reding <treding@nvidia.com>
Date: Mon, 15 Apr 2019 11:32:39 +0200
Subject: [PATCH] ARM: tegra: Add NVIDIA Jetson Nano Developer Kit support
v5: https://www.mail-archive.com/u-boot@lists.denx.de/msg322738.html
The Jetson Nano Developer Kit is a Tegra X1 based development board. It
is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
used for storage.
HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
Ethernet controller provides onboard network connectivity.
A 40-pin header on the board can be used to extend the capabilities and
exposed interfaces of the Jetson Nano.
[Yousaf]: fix build. add fdtfile in environment.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/tegra210-p3450-0000.dts | 135 +++++++++
arch/arm/mach-tegra/tegra210/Kconfig | 7 +
board/nvidia/p3450-0000/Kconfig | 12 +
board/nvidia/p3450-0000/MAINTAINERS | 6 +
board/nvidia/p3450-0000/Makefile | 8 +
board/nvidia/p3450-0000/p3450-0000.c | 198 +++++++++++++
.../p3450-0000/pinmux-config-p3450-0000.h | 265 ++++++++++++++++++
configs/p3450-0000_defconfig | 55 ++++
include/configs/p3450-0000.h | 37 +++
10 files changed, 725 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/tegra210-p3450-0000.dts
create mode 100644 board/nvidia/p3450-0000/Kconfig
create mode 100644 board/nvidia/p3450-0000/MAINTAINERS
create mode 100644 board/nvidia/p3450-0000/Makefile
create mode 100644 board/nvidia/p3450-0000/p3450-0000.c
create mode 100644 board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
create mode 100644 configs/p3450-0000_defconfig
create mode 100644 include/configs/p3450-0000.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0127a91a82..ae93b71660 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -179,7 +179,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
tegra210-p2371-2180.dtb \
- tegra210-p2571.dtb
+ tegra210-p2571.dtb \
+ tegra210-p3450-0000.dtb
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts
new file mode 100644
index 0000000000..d45ee9afc0
--- /dev/null
+++ b/arch/arm/dts/tegra210-p3450-0000.dts
@@ -0,0 +1,135 @@
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+ model = "NVIDIA Jetson Nano Developer Kit";
+ compatible = "nvidia,p3450-0000", "nvidia,tegra210";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
+ i2c0 = "/i2c@7000d000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ sdhci0 = "/sdhci@700b0000";
+ spi0 = "/spi@70410000";
+ usb0 = "/usb@7d000000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0xc0000000>;
+ };
+
+ pcie@1003000 {
+ status = "okay";
+
+ pci@1,0 {
+ status = "okay";
+ };
+
+ pci@2,0 {
+ status = "okay";
+
+ ethernet@0,0 {
+ reg = <0x000000 0 0 0 0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+ };
+
+ serial@70006000 {
+ status = "okay";
+ };
+
+ padctl@7009f000 {
+ pinctrl-0 = <&padctl_default>;
+ pinctrl-names = "default";
+
+ padctl_default: pinmux {
+ xusb {
+ nvidia,lanes = "otg-1", "otg-2";
+ nvidia,function = "xusb";
+ nvidia,iddq = <0>;
+ };
+
+ usb3 {
+ nvidia,lanes = "pcie-5", "pcie-6";
+ nvidia,function = "usb3";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x1 {
+ nvidia,lanes = "pcie-0";
+ nvidia,function = "pcie-x1";
+ nvidia,iddq = <0>;
+ };
+
+ pcie-x4 {
+ nvidia,lanes = "pcie-1", "pcie-2",
+ "pcie-3", "pcie-4";
+ nvidia,function = "pcie-x4";
+ nvidia,iddq = <0>;
+ };
+
+ sata {
+ nvidia,lanes = "sata-0";
+ nvidia,function = "sata";
+ nvidia,iddq = <0>;
+ };
+ };
+ };
+
+ sdhci@700b0000 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ spi@70410000 {
+ status = "okay";
+ };
+
+ usb@7d000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index 3637473051..97ed8e05f4 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -35,6 +35,12 @@ config TARGET_P2571
help
P2571 is a P2530 married to a P1963 I/O board
+config TARGET_P3450_0000
+ bool "NVIDIA Jetson Nano Developer Kit"
+ select BOARD_LATE_INIT
+ help
+ P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
+
endchoice
config SYS_SOC
@@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
source "board/nvidia/p2371-2180/Kconfig"
source "board/nvidia/p2571/Kconfig"
+source "board/nvidia/p3450-0000/Kconfig"
endif
diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig
new file mode 100644
index 0000000000..7a08cd8867
--- /dev/null
+++ b/board/nvidia/p3450-0000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P3450_0000
+
+config SYS_BOARD
+ default "p3450-0000"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "p3450-0000"
+
+endif
diff --git a/board/nvidia/p3450-0000/MAINTAINERS b/board/nvidia/p3450-0000/MAINTAINERS
new file mode 100644
index 0000000000..40700066bf
--- /dev/null
+++ b/board/nvidia/p3450-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P3450-0000 BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/p3450-0000/
+F: include/configs/p3450-0000.h
+F: configs/p3450-0000_defconfig
diff --git a/board/nvidia/p3450-0000/Makefile b/board/nvidia/p3450-0000/Makefile
new file mode 100644
index 0000000000..993c506d82
--- /dev/null
+++ b/board/nvidia/p3450-0000/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2018
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p3450-0000.o
diff --git a/board/nvidia/p3450-0000/p3450-0000.c b/board/nvidia/p3450-0000/p3450-0000.c
new file mode 100644
index 0000000000..c7aa76a14e
--- /dev/null
+++ b/board/nvidia/p3450-0000/p3450-0000.c
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2018
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <linux/libfdt.h>
+#include <pca953x.h>
+#include <asm/arch-tegra/cboot.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "../p2571/max77620_init.h"
+#include "pinmux-config-p3450-0000.h"
+
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO2 to 3.3V for SD card power */
+ debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return;
+ }
+ /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xF2;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
+
+ /* Disable LDO4 discharge */
+ ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret) {
+ printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
+ } else {
+ val &= ~BIT(1); /* ADE */
+ ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
+ }
+
+ /* Set MBLPD */
+ ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret) {
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ } else {
+ val |= BIT(6); /* MBLPD */
+ ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
+ }
+}
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_clear_tristate_input_clamping();
+
+ gpio_config_table(p3450_0000_gpio_inits,
+ ARRAY_SIZE(p3450_0000_gpio_inits));
+
+ pinmux_config_pingrp_table(p3450_0000_pingrps,
+ ARRAY_SIZE(p3450_0000_pingrps));
+
+ pinmux_config_drvgrp_table(p3450_0000_drvgrps,
+ ARRAY_SIZE(p3450_0000_drvgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX77620 LDO1 to 1.05V for PEX power */
+ debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
+ ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
+ return -1;
+ }
+ /* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
+ val = 0xCA;
+ ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
+
+ return 0;
+}
+#endif /* PCI */
+
+static void ft_mac_address_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
+ const char *path;
+ int offset, err;
+
+ err = cboot_get_ethaddr(cboot_fdt, local_mac);
+ if (err < 0)
+ memset(local_mac, 0, ETH_ALEN);
+
+ path = fdt_get_alias(fdt, "ethernet");
+ if (!path)
+ return;
+
+ debug("ethernet alias found: %s\n", path);
+
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0) {
+ printf("ethernet alias points to absent node %s\n", path);
+ return;
+ }
+
+ if (is_valid_ethaddr(local_mac)) {
+ err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
+ ETH_ALEN);
+ if (!err)
+ debug("Local MAC address set: %pM\n", local_mac);
+ }
+
+ if (eth_env_get_enetaddr("ethaddr", mac)) {
+ if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
+ err = fdt_setprop(fdt, offset, "mac-address", mac,
+ ETH_ALEN);
+ if (!err)
+ debug("MAC address set: %pM\n", mac);
+ }
+ }
+}
+
+static int ft_copy_carveout(void *dst, const void *src, const char *node)
+{
+ struct fdt_memory fb;
+ int err;
+
+ err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to get carveout for %s: %d\n", node,
+ err);
+
+ return err;
+ }
+
+ err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
+ &fb);
+ if (err < 0) {
+ printf("failed to set carveout for %s: %d\n", node, err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void ft_carveout_setup(void *fdt)
+{
+ const void *cboot_fdt = (const void *)cboot_boot_x0;
+ static const char * const nodes[] = {
+ "/host1x@50000000/dc@54200000",
+ "/host1x@50000000/dc@54240000",
+ };
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < ARRAY_SIZE(nodes); i++) {
+ printf("copying carveout for %s...\n", nodes[i]);
+
+ err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
+ if (err < 0) {
+ if (err != -FDT_ERR_NOTFOUND)
+ printf("failed to copy carveout for %s: %d\n",
+ nodes[i], err);
+
+ continue;
+ }
+ }
+}
+
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ ft_mac_address_setup(fdt);
+ ft_carveout_setup(fdt);
+
+ return 0;
+}
diff --git a/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
new file mode 100644
index 0000000000..722da49735
--- /dev/null
+++ b/board/nvidia/p3450-0000/pinmux-config-p3450-0000.h
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
+ *
+ * To generate this file, use the tegra-pinmux-scripts tool available from
+ * https://github.com/NVIDIA/tegra-pinmux-scripts
+ * Run "board-to-uboot.py p3450-0000".
+ */
+
+#ifndef _PINMUX_CONFIG_P3450_0000_H_
+#define _PINMUX_CONFIG_P3450_0000_H_
+
+#define GPIO_INIT(_port, _gpio, _init) \
+ { \
+ .gpio = TEGRA_GPIO(_port, _gpio), \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config p3450_0000_gpio_inits[] = {
+ /* port, pin, init_val */
+ GPIO_INIT(A, 5, IN),
+ GPIO_INIT(A, 6, OUT1),
+ GPIO_INIT(B, 4, IN),
+ GPIO_INIT(B, 5, IN),
+ GPIO_INIT(B, 6, IN),
+ GPIO_INIT(B, 7, IN),
+ GPIO_INIT(C, 0, IN),
+ GPIO_INIT(C, 1, IN),
+ GPIO_INIT(C, 2, IN),
+ GPIO_INIT(C, 3, IN),
+ GPIO_INIT(C, 4, IN),
+ GPIO_INIT(E, 6, IN),
+ GPIO_INIT(G, 2, IN),
+ GPIO_INIT(G, 3, IN),
+ GPIO_INIT(H, 0, OUT0),
+ GPIO_INIT(H, 2, IN),
+ GPIO_INIT(H, 3, OUT0),
+ GPIO_INIT(H, 4, OUT0),
+ GPIO_INIT(H, 5, IN),
+ GPIO_INIT(H, 6, IN),
+ GPIO_INIT(H, 7, OUT0),
+ GPIO_INIT(I, 0, OUT0),
+ GPIO_INIT(I, 1, IN),
+ GPIO_INIT(I, 2, OUT0),
+ GPIO_INIT(J, 4, IN),
+ GPIO_INIT(J, 5, IN),
+ GPIO_INIT(J, 6, IN),
+ GPIO_INIT(J, 7, IN),
+ GPIO_INIT(S, 5, IN),
+ GPIO_INIT(S, 7, OUT0),
+ GPIO_INIT(T, 0, OUT0),
+ GPIO_INIT(V, 0, IN),
+ GPIO_INIT(V, 1, IN),
+ GPIO_INIT(X, 3, OUT1),
+ GPIO_INIT(X, 4, IN),
+ GPIO_INIT(X, 5, IN),
+ GPIO_INIT(X, 6, IN),
+ GPIO_INIT(Y, 1, IN),
+ GPIO_INIT(Y, 2, IN),
+ GPIO_INIT(Z, 0, IN),
+ GPIO_INIT(Z, 2, IN),
+ GPIO_INIT(Z, 3, OUT0),
+ GPIO_INIT(BB, 0, IN),
+ GPIO_INIT(CC, 4, IN),
+ GPIO_INIT(DD, 0, IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config p3450_0000_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
+ PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
+ PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
+ PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PA6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MOSI_PB4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_MISO_PB5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_SCK_PB6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI2_CS0_PB7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_RTS_PD3, UARTC, UP, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_CLK_PE4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RX_PG1, UARTB, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_RTS_PG2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART2_CTS_PG3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(NFC_INT_PI1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART4_CTS_PI7, UARTD, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(DAP4_FS_PJ4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_DIN_PJ5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_DOUT_PJ6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP4_SCLK_PJ7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_AF_EN_PS5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RX_PU1, UARTA, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_RTS_PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(UART1_CTS_PU3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_PWM_PV0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_RST_PV6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(ALS_PROX_INT_PX3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_VOL_DOWN_PX7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(LCD_TE_PY2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(CLK_32K_OUT_PY5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(DVFS_CLK_PBB2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
+ PINCFG(HDMI_INT_DP_HPD_PCC1, DP, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PCC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
+ PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(DP_HPD0_PCC6, DP, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
+ PINCFG(SPI2_CS1_PDD0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CPU_PWR_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config p3450_0000_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_P3450_0000_H */
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
new file mode 100644
index 0000000000..3a95028279
--- /dev/null
+++ b/configs/p3450-0000_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_SYS_TEXT_BASE=0x80080000
+CONFIG_TEGRA210=y
+CONFIG_TARGET_P3450_0000=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_STDIO_DEREGISTER=y
+CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_RTL8169=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_TEGRA114_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0955
+CONFIG_USB_GADGET_PRODUCT_NUM=0x701a
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_ENV_IS_IN_MMC is not set
diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h
new file mode 100644
index 0000000000..7fc21820a7
--- /dev/null
+++ b/include/configs/p3450-0000.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018-2019 NVIDIA Corporation. All rights reserved.
+ */
+
+#ifndef _P3450_0000_H
+#define _P3450_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* Only MMC1/PXE/DHCP for now, add USB back in later when supported */
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY 19200000
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+ "fdtfile=tegra210-p3450-0000.dtb\0"
+
+#endif /* _P3450_0000_H */

74
0010-libfdt-return-correct-value-if-size.patch
View File

@ -1,74 +0,0 @@
From 364d2cbad906064fa386f6170f9f1d927eb69ae8 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Thu, 5 Sep 2019 10:48:47 +0200
Subject: [PATCH] libfdt: return correct value if #size-cells property is not
present
According to the device tree specification, the default value for
was not present.
This patch also makes fdt_address_cells() and fdt_size_cells() conform
to the behaviour documented in libfdt.h. The defaults are only returned
if fdt_getprop() returns -FDT_ERR_NOTFOUND, otherwise the actual error
is returned.
This is based on upstream commit:
aa7254d ("libfdt: return correct value if #size-cells property is not present")
but misses the test case part, as we don't implement them in U-Boot.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
(cherry picked from commit 9328f2adca50bd0b90f291230894fc46bc564665)
---
scripts/dtc/libfdt/fdt_addresses.c | 16 +++++++++++++---
scripts/dtc/libfdt/libfdt.h | 2 +-
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/scripts/dtc/libfdt/fdt_addresses.c b/scripts/dtc/libfdt/fdt_addresses.c
index 49537b578d..f13a87dfa0 100644
--- a/scripts/dtc/libfdt/fdt_addresses.c
+++ b/scripts/dtc/libfdt/fdt_addresses.c
@@ -64,7 +64,7 @@ static int fdt_cells(const void *fdt, int nodeoffset, const char *name)
c = fdt_getprop(fdt, nodeoffset, name, &len);
if (!c)
- return 2;
+ return len;
if (len != sizeof(*c))
return -FDT_ERR_BADNCELLS;
@@ -78,10 +78,20 @@ static int fdt_cells(const void *fdt, int nodeoffset, const char *name)
int fdt_address_cells(const void *fdt, int nodeoffset)
{
- return fdt_cells(fdt, nodeoffset, "#address-cells");
+ int val;
+
+ val = fdt_cells(fdt, nodeoffset, "#address-cells");
+ if (val == -FDT_ERR_NOTFOUND)
+ return 2;
+ return val;
}
int fdt_size_cells(const void *fdt, int nodeoffset)
{
- return fdt_cells(fdt, nodeoffset, "#size-cells");
+ int val;
+
+ val = fdt_cells(fdt, nodeoffset, "#size-cells");
+ if (val == -FDT_ERR_NOTFOUND)
+ return 1;
+ return val;
}
diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h
index 66f01fec53..5c778b115b 100644
--- a/scripts/dtc/libfdt/libfdt.h
+++ b/scripts/dtc/libfdt/libfdt.h
@@ -1109,7 +1109,7 @@ int fdt_address_cells(const void *fdt, int nodeoffset);
*
* returns:
* 0 <= n < FDT_MAX_NCELLS, on success
- * 2, if the node has no #size-cells property
+ * 1, if the node has no #size-cells property
* -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
* #size-cells property
* -FDT_ERR_BADMAGIC,

62
0011-libfdt-Allow-size-cells-of-0.patch
View File

@ -1,62 +0,0 @@
From 4ec9166e183805f15df73ec48b5750f386828f51 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Thu, 5 Sep 2019 10:48:48 +0200
Subject: [PATCH] libfdt: Allow #size-cells of 0
The commit "libfdt: fdt_address_cells() and fdt_size_cells()" introduced
a bug as it consolidated code between the helpers for getting
be 0, and is frequently found so in practice for /cpus. IEEE1275 only
requires implementations to handle 1..4 for #address-cells, although one
could make a case for #address-cells == #size-cells == 0 being used to
represent a bridge with a single port.
While we're there, it's not totally obvious that the existing implicit
cast of a u32 to int will give the correct results according to strict C,
although it does work in practice. Straighten that up to cast only after
we've made our range checks.
This is based on upstream commit:
b8d6eca ("libfdt: Allow #size-cells of 0")
but misses the test cases,as we don't implement them in U-Boot.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
(cherry picked from commit 28e8a01e3e92755cb9e4d57f8fa25146c5aa698c)
---
scripts/dtc/libfdt/fdt_addresses.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/scripts/dtc/libfdt/fdt_addresses.c b/scripts/dtc/libfdt/fdt_addresses.c
index f13a87dfa0..788c143113 100644
--- a/scripts/dtc/libfdt/fdt_addresses.c
+++ b/scripts/dtc/libfdt/fdt_addresses.c
@@ -59,7 +59,7 @@
static int fdt_cells(const void *fdt, int nodeoffset, const char *name)
{
const fdt32_t *c;
- int val;
+ uint32_t val;
int len;
c = fdt_getprop(fdt, nodeoffset, name, &len);
@@ -70,10 +70,10 @@ static int fdt_cells(const void *fdt, int nodeoffset, const char *name)
return -FDT_ERR_BADNCELLS;
val = fdt32_to_cpu(*c);
- if ((val <= 0) || (val > FDT_MAX_NCELLS))
+ if (val > FDT_MAX_NCELLS)
return -FDT_ERR_BADNCELLS;
- return val;
+ return (int)val;
}
int fdt_address_cells(const void *fdt, int nodeoffset)
@@ -81,6 +81,8 @@ int fdt_address_cells(const void *fdt, int nodeoffset)
int val;
val = fdt_cells(fdt, nodeoffset, "#address-cells");
+ if (val == 0)
+ return -FDT_ERR_BADNCELLS;
if (val == -FDT_ERR_NOTFOUND)
return 2;
return val;

788
0011-net-Add-support-for-Broadcom-GENETv.patch Normal file
View File

@ -0,0 +1,788 @@
From 52441f422edb2bb34090832d1aa44f4851fc0667 Mon Sep 17 00:00:00 2001
From: Amit Singh Tomar <amittomer25@gmail.com>
Date: Mon, 27 Jan 2020 01:14:42 +0000
Subject: [PATCH] net: Add support for Broadcom GENETv5 Ethernet controller
The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs
and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4.
There is no publicly available documentation, so this driver is based
on the Linux driver. Compared to that the queue management is
drastically simplified, also we only support version 5 of the IP and
RGMII connections between MAC and PHY, as used on the RPi4.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: heavy cleanup and a few fixes]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/bcmgenet.c | 729 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 737 insertions(+)
create mode 100644 drivers/net/bcmgenet.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 142a2c6953..999714dd39 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -136,6 +136,13 @@ config BCM6368_ETH
help
This driver supports the BCM6368 Ethernet MAC.
+config BCMGENET
+ bool "BCMGENET V5 support"
+ depends on DM_ETH
+ select PHYLIB
+ help
+ This driver supports the BCMGENET Ethernet MAC.
+
config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support"
depends on DM_ETH
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 30991834ec..6e0a68834d 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
+obj-$(CONFIG_BCMGENET) += bcmgenet.o
obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c
new file mode 100644
index 0000000000..8f4848aec6
--- /dev/null
+++ b/drivers/net/bcmgenet.c
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com>
+ *
+ * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4)
+ * This driver is based on the Linux driver:
+ * drivers/net/ethernet/broadcom/genet/bcmgenet.c
+ * which is: Copyright (c) 2014-2017 Broadcom
+ *
+ * The hardware supports multiple queues (16 priority queues and one
+ * default queue), both for RX and TX. There are 256 DMA descriptors (both
+ * for TX and RX), and they live in MMIO registers. The hardware allows
+ * assigning descriptor ranges to queues, but we choose the most simple setup:
+ * All 256 descriptors are assigned to the default queue (#16).
+ * Also the Linux driver supports multiple generations of the MAC, whereas
+ * we only support v5, as used in the Raspberry Pi 4.
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <dm/of_access.h>
+#include <dm/ofnode.h>
+#include <linux/iopoll.h>
+#include <linux/sizes.h>
+#include <asm/dma-mapping.h>
+#include <wait_bit.h>
+
+/* Register definitions derived from Linux source */
+#define SYS_REV_CTRL 0x00
+
+#define SYS_PORT_CTRL 0x04
+#define PORT_MODE_EXT_GPHY 3
+
+#define GENET_SYS_OFF 0x0000
+#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08)
+#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c)
+
+#define GENET_EXT_OFF 0x0080
+#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c)
+#define RGMII_LINK BIT(4)
+#define OOB_DISABLE BIT(5)
+#define RGMII_MODE_EN BIT(6)
+#define ID_MODE_DIS BIT(16)
+
+#define GENET_RBUF_OFF 0x0300
+#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4)
+#define RBUF_CTRL (GENET_RBUF_OFF + 0x00)
+#define RBUF_ALIGN_2B BIT(1)
+
+#define GENET_UMAC_OFF 0x0800
+#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580)
+#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014)
+#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c)
+#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010)
+#define UMAC_CMD (GENET_UMAC_OFF + 0x008)
+#define MDIO_CMD (GENET_UMAC_OFF + 0x614)
+#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334)
+#define MDIO_START_BUSY BIT(29)
+#define MDIO_READ_FAIL BIT(28)
+#define MDIO_RD (2 << 26)
+#define MDIO_WR BIT(26)
+#define MDIO_PMD_SHIFT 21
+#define MDIO_PMD_MASK 0x1f
+#define MDIO_REG_SHIFT 16
+#define MDIO_REG_MASK 0x1f
+
+#define CMD_TX_EN BIT(0)
+#define CMD_RX_EN BIT(1)
+#define UMAC_SPEED_10 0
+#define UMAC_SPEED_100 1
+#define UMAC_SPEED_1000 2
+#define UMAC_SPEED_2500 3
+#define CMD_SPEED_SHIFT 2
+#define CMD_SPEED_MASK 3
+#define CMD_SW_RESET BIT(13)
+#define CMD_LCL_LOOP_EN BIT(15)
+#define CMD_TX_EN BIT(0)
+#define CMD_RX_EN BIT(1)
+
+#define MIB_RESET_RX BIT(0)
+#define MIB_RESET_RUNT BIT(1)
+#define MIB_RESET_TX BIT(2)
+
+/* total number of Buffer Descriptors, same for Rx/Tx */
+#define TOTAL_DESCS 256
+#define RX_DESCS TOTAL_DESCS
+#define TX_DESCS TOTAL_DESCS
+
+#define DEFAULT_Q 0x10
+
+/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
+ * 1536 is multiple of 256 bytes
+ */
+#define ENET_BRCM_TAG_LEN 6
+#define ENET_PAD 8
+#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \
+ VLAN_HLEN + ENET_BRCM_TAG_LEN + \
+ ETH_FCS_LEN + ENET_PAD)
+
+/* Tx/Rx Dma Descriptor common bits */
+#define DMA_EN BIT(0)
+#define DMA_RING_BUF_EN_SHIFT 0x01
+#define DMA_RING_BUF_EN_MASK 0xffff
+#define DMA_BUFLENGTH_MASK 0x0fff
+#define DMA_BUFLENGTH_SHIFT 16
+#define DMA_RING_SIZE_SHIFT 16
+#define DMA_OWN 0x8000
+#define DMA_EOP 0x4000
+#define DMA_SOP 0x2000
+#define DMA_WRAP 0x1000
+#define DMA_MAX_BURST_LENGTH 0x8
+/* Tx specific DMA descriptor bits */
+#define DMA_TX_UNDERRUN 0x0200
+#define DMA_TX_APPEND_CRC 0x0040
+#define DMA_TX_OW_CRC 0x0020
+#define DMA_TX_DO_CSUM 0x0010
+#define DMA_TX_QTAG_SHIFT 7
+
+/* DMA rings size */
+#define DMA_RING_SIZE 0x40
+#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1))
+
+/* DMA descriptor */
+#define DMA_DESC_LENGTH_STATUS 0x00
+#define DMA_DESC_ADDRESS_LO 0x04
+#define DMA_DESC_ADDRESS_HI 0x08
+#define DMA_DESC_SIZE 12
+
+#define GENET_RX_OFF 0x2000
+#define GENET_RDMA_REG_OFF \
+ (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
+#define GENET_TX_OFF 0x4000
+#define GENET_TDMA_REG_OFF \
+ (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
+
+#define DMA_FC_THRESH_HI (RX_DESCS >> 4)
+#define DMA_FC_THRESH_LO 5
+#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \
+ DMA_FC_THRESH_HI)
+
+#define DMA_XOFF_THRESHOLD_SHIFT 16
+
+#define TDMA_RING_REG_BASE \
+ (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
+#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00)
+#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08)
+#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c)
+#define DMA_RING_BUF_SIZE 0x10
+#define DMA_START_ADDR 0x14
+#define DMA_END_ADDR 0x1c
+#define DMA_MBUF_DONE_THRESH 0x24
+#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28)
+#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c)
+
+#define RDMA_RING_REG_BASE \
+ (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
+#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00)
+#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08)
+#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c)
+#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28)
+#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c)
+
+#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
+#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
+#define DMA_RING_CFG 0x00
+#define DMA_CTRL 0x04
+#define DMA_SCB_BURST_SIZE 0x0c
+
+#define RX_BUF_LENGTH 2048
+#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS)
+#define RX_BUF_OFFSET 2
+
+struct bcmgenet_eth_priv {
+ char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+ void *mac_reg;
+ void *tx_desc_base;
+ void *rx_desc_base;
+ int tx_index;
+ int rx_index;
+ int c_index;
+ int phyaddr;
+ u32 interface;
+ u32 speed;
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+};
+
+static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv)
+{
+ u32 reg;
+
+ reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
+ reg |= BIT(1);
+ writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
+ udelay(10);
+
+ reg &= ~BIT(1);
+ writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
+ udelay(10);
+
+ writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
+ udelay(10);
+
+ writel(0, priv->mac_reg + UMAC_CMD);
+
+ writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
+ udelay(2);
+ writel(0, priv->mac_reg + UMAC_CMD);
+
+ /* clear tx/rx counter */
+ writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
+ priv->mac_reg + UMAC_MIB_CTRL);
+ writel(0, priv->mac_reg + UMAC_MIB_CTRL);
+
+ writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN);
+
+ /* init rx registers, enable ip header optimization */
+ reg = readl(priv->mac_reg + RBUF_CTRL);
+ reg |= RBUF_ALIGN_2B;
+ writel(reg, (priv->mac_reg + RBUF_CTRL));
+
+ writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL));
+}
+
+static int bcmgenet_gmac_write_hwaddr(struct udevice *dev)
+{
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ uchar *addr = pdata->enetaddr;
+ u32 reg;
+
+ reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
+ writel_relaxed(reg, priv->mac_reg + UMAC_MAC0);
+
+ reg = addr[4] << 8 | addr[5];
+ writel_relaxed(reg, priv->mac_reg + UMAC_MAC1);
+
+ return 0;
+}
+
+static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv)
+{
+ clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN);
+ clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN);
+
+ writel(1, priv->mac_reg + UMAC_TX_FLUSH);
+ udelay(10);
+ writel(0, priv->mac_reg + UMAC_TX_FLUSH);
+}
+
+static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv)
+{
+ u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
+
+ writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL);
+
+ setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl);
+}
+
+static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE;
+ u32 len_stat = length << DMA_BUFLENGTH_SHIFT;
+ ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN);
+ u32 prod_index, cons;
+ u32 tries = 100;
+
+ prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX);
+
+ /* There is actually no reason for the rounding here, but the ARMv7
+ * implementation of flush_dcache_range() checks for aligned
+ * boundaries of the flushed range.
+ * Adjust them here to pass that check and avoid misleading messages.
+ */
+ flush_dcache_range(packet_aligned,
+ packet_aligned + roundup(length, ARCH_DMA_MINALIGN));
+
+ len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
+ len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
+
+ /* Set-up packet for transmission */
+ writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO));
+ writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI));
+ writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS));
+
+ /* Increment index and start transmission */
+ if (++priv->tx_index >= TX_DESCS)
+ priv->tx_index = 0;
+
+ prod_index++;
+
+ /* Start Transmisson */
+ writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX);
+
+ do {
+ cons = readl(priv->mac_reg + TDMA_CONS_INDEX);
+ } while ((cons & 0xffff) < prod_index && --tries);
+ if (!tries)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+/* Check whether all cache lines affected by an invalidate are within
+ * the buffer, to make sure we don't accidentally lose unrelated dirty
+ * data stored nearby.
+ * Alignment of the buffer start address will be checked in the implementation
+ * of invalidate_dcache_range().
+ */
+static void invalidate_dcache_check(unsigned long addr, size_t size,
+ size_t buffer_size)
+{
+ size_t inval_size = roundup(size, ARCH_DMA_MINALIGN);
+
+ if (unlikely(inval_size > buffer_size))
+ printf("WARNING: Cache invalidate area exceeds buffer size\n");
+
+ invalidate_dcache_range(addr, addr + inval_size);
+}
+
+static int bcmgenet_gmac_eth_recv(struct udevice *dev,
+ int flags, uchar **packetp)
+{
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE;
+ u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
+ u32 length, addr;
+
+ if (prod_index == priv->c_index)
+ return -EAGAIN;
+
+ length = readl(desc_base + DMA_DESC_LENGTH_STATUS);
+ length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
+ addr = readl(desc_base + DMA_DESC_ADDRESS_LO);
+
+ invalidate_dcache_check(addr, length, RX_BUF_LENGTH);
+
+ /* To cater for the IP header alignment the hardware does.
+ * This would actually not be needed if we don't program
+ * RBUF_ALIGN_2B
+ */
+ *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET;
+
+ return length - RX_BUF_OFFSET;
+}
+
+static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+
+ /* Tell the MAC we have consumed that last receive buffer. */
+ priv->c_index = (priv->c_index + 1) & 0xFFFF;
+ writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
+
+ /* Forward our descriptor pointer, wrapping around if needed. */
+ if (++priv->rx_index >= RX_DESCS)
+ priv->rx_index = 0;
+
+ return 0;
+}
+
+static void rx_descs_init(struct bcmgenet_eth_priv *priv)
+{
+ char *rxbuffs = &priv->rxbuffer[0];
+ u32 len_stat, i;
+ void *desc_base = priv->rx_desc_base;
+
+ priv->c_index = 0;
+
+ len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
+
+ for (i = 0; i < RX_DESCS; i++) {
+ writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
+ desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO);
+ writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
+ desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI);
+ writel(len_stat,
+ desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS);
+ }
+}
+
+static void rx_ring_init(struct bcmgenet_eth_priv *priv)
+{
+ writel(DMA_MAX_BURST_LENGTH,
+ priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE);
+
+ writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR);
+ writel(0x0, priv->mac_reg + RDMA_READ_PTR);
+ writel(0x0, priv->mac_reg + RDMA_WRITE_PTR);
+ writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1,
+ priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR);
+
+ writel(0x0, priv->mac_reg + RDMA_PROD_INDEX);
+ writel(0x0, priv->mac_reg + RDMA_CONS_INDEX);
+ writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
+ priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
+ writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH);
+ writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG);
+}
+
+static void tx_ring_init(struct bcmgenet_eth_priv *priv)
+{
+ writel(DMA_MAX_BURST_LENGTH,
+ priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE);
+
+ writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR);
+ writel(0x0, priv->mac_reg + TDMA_READ_PTR);
+ writel(0x0, priv->mac_reg + TDMA_WRITE_PTR);
+ writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1,
+ priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR);
+ writel(0x0, priv->mac_reg + TDMA_PROD_INDEX);
+ writel(0x0, priv->mac_reg + TDMA_CONS_INDEX);
+ writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH);
+ writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD);
+ writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
+ priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
+
+ writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG);
+}
+
+static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv)
+{
+ struct phy_device *phy_dev = priv->phydev;
+ u32 speed;
+
+ switch (phy_dev->speed) {
+ case SPEED_1000:
+ speed = UMAC_SPEED_1000;
+ break;
+ case SPEED_100:
+ speed = UMAC_SPEED_100;
+ break;
+ case SPEED_10:
+ speed = UMAC_SPEED_10;
+ break;
+ default:
+ printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed);
+ return -EINVAL;
+ }
+
+ clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
+ RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
+
+ writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
+
+ return 0;
+}
+
+static int bcmgenet_gmac_eth_start(struct udevice *dev)
+{
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF;
+ priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF;
+ priv->tx_index = 0x0;
+ priv->rx_index = 0x0;
+
+ bcmgenet_umac_reset(priv);
+
+ bcmgenet_gmac_write_hwaddr(dev);
+
+ /* Disable RX/TX DMA and flush TX queues */
+ bcmgenet_disable_dma(priv);
+
+ rx_ring_init(priv);
+ rx_descs_init(priv);
+
+ tx_ring_init(priv);
+
+ /* Enable RX/TX DMA */
+ bcmgenet_enable_dma(priv);
+
+ /* read PHY properties over the wire from generic PHY set-up */
+ ret = phy_startup(priv->phydev);
+ if (ret) {
+ printf("bcmgenet: PHY startup failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Update MAC registers based on PHY property */
+ ret = bcmgenet_adjust_link(priv);
+ if (ret) {
+ printf("bcmgenet: adjust PHY link failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Enable Rx/Tx */
+ setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
+
+ return 0;
+}
+
+static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev)
+{
+ struct phy_device *phydev;
+ int ret;
+
+ phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
+ if (!phydev)
+ return -ENODEV;
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ if (priv->speed) {
+ ret = phy_set_supported(priv->phydev, priv->speed);
+ if (ret)
+ return ret;
+ }
+ phydev->advertising = phydev->supported;
+
+ phy_connect_dev(phydev, dev);
+
+ priv->phydev = phydev;
+ phy_config(priv->phydev);
+
+ return 0;
+}
+
+static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv)
+{
+ setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY);
+}
+
+static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 value)
+{
+ struct udevice *dev = bus->priv;
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ u32 val;
+
+ /* Prepare the read operation */
+ val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |
+ (reg << MDIO_REG_SHIFT) | (0xffff & value);
+ writel_relaxed(val, priv->mac_reg + MDIO_CMD);
+
+ /* Start MDIO transaction */
+ bcmgenet_mdio_start(priv);
+
+ return wait_for_bit_32(priv->mac_reg + MDIO_CMD,
+ MDIO_START_BUSY, false, 20, true);
+}
+
+static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct udevice *dev = bus->priv;
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ u32 val;
+ int ret;
+
+ /* Prepare the read operation */
+ val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
+ writel_relaxed(val, priv->mac_reg + MDIO_CMD);
+
+ /* Start MDIO transaction */
+ bcmgenet_mdio_start(priv);
+
+ ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD,
+ MDIO_START_BUSY, false, 20, true);
+ if (ret)
+ return ret;
+
+ val = readl_relaxed(priv->mac_reg + MDIO_CMD);
+
+ return val & 0xffff;
+}
+
+static int bcmgenet_mdio_init(const char *name, struct udevice *priv)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ debug("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus->read = bcmgenet_mdio_read;
+ bus->write = bcmgenet_mdio_write;
+ snprintf(bus->name, sizeof(bus->name), name);
+ bus->priv = (void *)priv;
+
+ return mdio_register(bus);
+}
+
+/* We only support RGMII (as used on the RPi4). */
+static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv)
+{
+ phy_interface_t phy_mode = priv->interface;
+
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL);
+ break;
+ default:
+ printf("unknown phy mode: %d\n", priv->interface);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int bcmgenet_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ ofnode mdio_node;
+ const char *name;
+ u32 reg;
+ int ret;
+ u8 major;
+
+ priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE);
+ priv->interface = pdata->phy_interface;
+ priv->speed = pdata->max_speed;
+
+ /* Read GENET HW version */
+ reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL);
+ major = (reg >> 24) & 0x0f;
+ if (major != 6) {
+ if (major == 5)
+ major = 4;
+ else if (major == 0)
+ major = 1;
+
+ printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f);
+ return -ENODEV;
+ }
+
+ ret = bcmgenet_interface_set(priv);
+ if (ret)
+ return ret;
+
+ writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
+ udelay(10);
+ /* disable MAC while updating its registers */
+ writel(0, priv->mac_reg + UMAC_CMD);
+ /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
+ writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
+
+ mdio_node = dev_read_first_subnode(dev);
+ name = ofnode_get_name(mdio_node);
+
+ ret = bcmgenet_mdio_init(name, dev);
+ if (ret)
+ return ret;
+
+ priv->bus = miiphy_get_dev_by_name(name);
+
+ return bcmgenet_phy_init(priv, dev);
+}
+
+static void bcmgenet_gmac_eth_stop(struct udevice *dev)
+{
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+
+ clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
+
+ bcmgenet_disable_dma(priv);
+}
+
+static const struct eth_ops bcmgenet_gmac_eth_ops = {
+ .start = bcmgenet_gmac_eth_start,
+ .write_hwaddr = bcmgenet_gmac_write_hwaddr,
+ .send = bcmgenet_gmac_eth_send,
+ .recv = bcmgenet_gmac_eth_recv,
+ .free_pkt = bcmgenet_gmac_free_pkt,
+ .stop = bcmgenet_gmac_eth_stop,
+};
+
+static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args phy_node;
+ const char *phy_mode;
+ int ret;
+
+ pdata->iobase = dev_read_addr(dev);
+
+ /* Get phy mode from DT */
+ pdata->phy_interface = -1;
+ phy_mode = dev_read_string(dev, "phy-mode");
+ if (phy_mode)
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+ if (pdata->phy_interface == -1) {
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+ return -EINVAL;
+ }
+
+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phy_node);
+ if (!ret) {
+ ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr);
+ ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed);
+ }
+
+ return 0;
+}
+
+/* The BCM2711 implementation has a limited burst length compared to a generic
+ * GENETv5 version, but we go with that shorter value (8) in both cases, for
+ * the sake of simplicity.
+ */
+static const struct udevice_id bcmgenet_eth_ids[] = {
+ {.compatible = "brcm,genet-v5"},
+ {.compatible = "brcm,bcm2711-genet-v5"},
+ {}
+};
+
+U_BOOT_DRIVER(eth_bcmgenet) = {
+ .name = "eth_bcmgenet",
+ .id = UCLASS_ETH,
+ .of_match = bcmgenet_eth_ids,
+ .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata,
+ .probe = bcmgenet_eth_probe,
+ .ops = &bcmgenet_gmac_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};

28
0012-dm-Fix-default-address-cells-return.patch
View File

@ -1,28 +0,0 @@
From 5e1c2ca428cb26dfcea48c759ae63d281ade8d49 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Thu, 5 Sep 2019 10:48:49 +0200
Subject: [PATCH] dm: Fix default address cells return value
Default address cells value on the livetree access function
returns the wrong value. Fix this so that the value returned
corresponds to the device tree specification.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
(cherry picked from commit 477b4084f76f7fa16e4d8483525c6d0070b47364)
---
include/dm/of.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dm/of.h b/include/dm/of.h
index 461e25aa19..6bef73b441 100644
--- a/include/dm/of.h
+++ b/include/dm/of.h
@@ -111,7 +111,7 @@ static inline const char *of_node_full_name(const struct device_node *np)
/* Default #address and #size cells */
#if !defined(OF_ROOT_NODE_ADDR_CELLS_DEFAULT)
-#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1
+#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
#endif

34
0012-rpi4-Update-memory-map-to-accommoda.patch Normal file
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@ -0,0 +1,34 @@
From 76c24dca74ae4142400b36a37a5e563aafbcef76 Mon Sep 17 00:00:00 2001
From: Amit Singh Tomar <amittomer25@gmail.com>
Date: Mon, 27 Jan 2020 01:14:43 +0000
Subject: [PATCH] rpi4: Update memory map to accommodate scb devices
Some of the devices(for instance, pcie and gnet controller) sitting on
SCB bus falls behind/below the memory range that we currenty have.
This patch updates the memory range to map those devices correctly.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/mach-bcm283x/init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 3b5f45b431..9966d6c833 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -42,9 +42,9 @@ static struct mm_region bcm2711_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
- .virt = 0xfe000000UL,
- .phys = 0xfe000000UL,
- .size = 0x01800000UL,
+ .virt = 0xfc000000UL,
+ .phys = 0xfc000000UL,
+ .size = 0x03800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN

64
0013-arm-arm11-allow-unaligned-memory-ac.patch
View File

@ -1,64 +0,0 @@
From 50ae76602cfb1079a3062a18c1767dce525985f0 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: Tue, 19 Nov 2019 04:02:10 +0100
Subject: [PATCH] arm: arm11: allow unaligned memory access
The UEFI spec mandates that unaligned memory access should be enabled if
supported by the CPU architecture.
This patch implements the function unaligned_access() to set the enable
unaligned data support flag and to clear the aligned flag in the system
control register (SCTLR). It is called when UEFI related commands like
bootefi are invoked.
Reported-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
arch/arm/cpu/arm11/Makefile | 4 ++++
arch/arm/cpu/arm11/sctlr.S | 25 +++++++++++++++++++++++++
2 files changed, 29 insertions(+)
create mode 100644 arch/arm/cpu/arm11/sctlr.S
diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile
index 5d721fce12..5dfa01ae8d 100644
--- a/arch/arm/cpu/arm11/Makefile
+++ b/arch/arm/cpu/arm11/Makefile
@@ -4,3 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y = cpu.o
+
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_EFI_LOADER) += sctlr.o
+endif
diff --git a/arch/arm/cpu/arm11/sctlr.S b/arch/arm/cpu/arm11/sctlr.S
new file mode 100644
index 0000000000..74a7fc4a25
--- /dev/null
+++ b/arch/arm/cpu/arm11/sctlr.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Routines to access the system control register
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * void allow_unaligned(void) - allow unaligned access
+ *
+ * This routine sets the enable unaligned data support flag and clears the
+ * aligned flag in the system control register.
+ * After calling this routine unaligned access does no longer leads to a
+ * data abort or undefined behavior but is handled by the CPU.
+ * For details see the "ARM Architecture Reference Manual" for ARMv6.
+ */
+ENTRY(allow_unaligned)
+ mrc p15, 0, r0, c1, c0, 0 @ load system control register
+ orr r0, r0, #1 << 22 @ set unaligned data support flag
+ bic r0, r0, #2 @ clear aligned flag
+ mcr p15, 0, r0, c1, c0, 0 @ write system control register
+ bx lr @ return
+ENDPROC(allow_unaligned)

58
0013-rpi4-Enable-GENET-Ethernet-controll.patch Normal file
View File

@ -0,0 +1,58 @@
From 5d079e211ea775b44a2af059b9b4fb4d03fd5359 Mon Sep 17 00:00:00 2001
From: Amit Singh Tomar <amittomer25@gmail.com>
Date: Mon, 27 Jan 2020 01:14:44 +0000
Subject: [PATCH] rpi4: Enable GENET Ethernet controller
The Raspberry Pi 4 SoC features an integrated Gigabit Ethernet
controller, connected as a platform device.
Enable the new driver in the three applicable defconfigs, to allow
TFTP booting on the board.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
[Andre: Add joined and 32-bit configs]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
configs/rpi_4_32b_defconfig | 2 ++
configs/rpi_4_defconfig | 2 ++
configs/rpi_arm64_defconfig | 1 +
3 files changed, 5 insertions(+)
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 00f80f71ad..e7ea88bd4b 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_DM_ETH=y
+CONFIG_BCMGENET=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 8cf1bb81ff..b0f9cf1c0e 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_DM_ETH=y
+CONFIG_BCMGENET=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index 10fbe0db92..00b3096481 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -36,6 +36,7 @@ CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_BCMGENET=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_BPP32=y
CONFIG_SYS_WHITE_ON_BLACK=y

26
0014-Kconfig-add-btrfs-to-distro-boot.patch Normal file
View File

@ -0,0 +1,26 @@
From 4fbba802d7b1d852acbffeb735196560f1ac39b7 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Fri, 17 Jan 2020 20:59:02 +0100
Subject: [PATCH] Kconfig: add btrfs to distro boot
Some distributions use btrfs as the default file system.
Enable btrfs support by default when using distro boot for all
architectures but riscv, as it breaks compilation due to size problems.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/Kconfig b/Kconfig
index 92fc4fc135..b61ebf22f6 100644
--- a/Kconfig
+++ b/Kconfig
@@ -93,6 +93,7 @@ config DISTRO_DEFAULTS
select HUSH_PARSER
select SUPPORT_RAW_INITRD
select SYS_LONGHELP
+ imply CMD_BTRFS if !RISCV && !MIPS
imply CMD_MII if NET
imply USB_STORAGE
imply USE_BOOTCOMMAND

33
0014-fdt-fix-bcm283x-dm-pre-reloc-defini.patch
View File

@ -1,33 +0,0 @@
From 9526bad11cfe6be9e542360ae2db0f51e82d66e7 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Fri, 8 Nov 2019 14:49:46 +0100
Subject: [PATCH] fdt: fix bcm283x dm-pre-reloc definitions
In commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we deleted the label for the node soc from bcm283x.dtsi
As we don't need to add the property dm-pre-reloc to the soc node,
we can delete it from bcm283x-uboot.dtsi
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/dts/bcm283x-uboot.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/bcm283x-uboot.dtsi b/arch/arm/dts/bcm283x-uboot.dtsi
index 6cc1aa3f93..36548dad62 100644
--- a/arch/arm/dts/bcm283x-uboot.dtsi
+++ b/arch/arm/dts/bcm283x-uboot.dtsi
@@ -6,10 +6,6 @@
* (C) Copyright 2016 Fabian Vogt <fvogt@suse.com>
*/
-&soc {
- u-boot,dm-pre-reloc;
-};
-
&uart0 {
skip-init;
u-boot,dm-pre-reloc;

33
0015-arm-dts-bcm283x-Rename-U-Boot-file.patch
View File

@ -1,33 +0,0 @@
From f23fa9de638a899bd26b4a7d95fd0cc4fb63ec2c Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Fri, 8 Nov 2019 14:49:47 +0100
Subject: [PATCH] arm: dts: bcm283x: Rename U-Boot file
Rename the file bcm283x-uboot.dtsi so that it get
automatically include through the scripts/Makefile.lib
using $(CONFIG_SYS_SOC))-u-boot.dtsi
Without this uarts and pincontroller miss the property dm-pre-reloc
and the first call to bcm283x_mu_serial_ofdata_to_platdata() fails
as the pins are not set correctly.
As a result the U-Boot banner isn't shown on boot.
Before commmit
143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state")
we included bcm283x-uboot.dtsi directly in the device-tree file.
Which got deleted by the metioned commit.
This is a much robuster solution.
Reported-by: Tom Rini <trini@konsulko.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/dts/{bcm283x-uboot.dtsi => bcm283x-u-boot.dtsi} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename arch/arm/dts/{bcm283x-uboot.dtsi => bcm283x-u-boot.dtsi} (100%)
diff --git a/arch/arm/dts/bcm283x-uboot.dtsi b/arch/arm/dts/bcm283x-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/bcm283x-uboot.dtsi
rename to arch/arm/dts/bcm283x-u-boot.dtsi

77
0015-configs-Re-sync-with-CONFIG_DISTRO_.patch Normal file
View File

@ -0,0 +1,77 @@
From 9e3dd9d492f3c6b7b525e77ecbd43e451a0c39d2 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Wed, 29 Jan 2020 09:56:06 +0100
Subject: [PATCH] configs: Re-sync with CONFIG_DISTRO_DEFAULTS
CONFIG_DISTRO_DEFAULTS now enables CMD_BTRFS by default,
we can delete the config option in the corresponding default
configs. Other boards won't build with btrfs enabled so disable
the support by default.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
configs/sandbox64_defconfig | 1 -
configs/sandbox_defconfig | 1 -
configs/socfpga_arria10_defconfig | 2 ++
configs/turris_mox_defconfig | 1 -
configs/turris_omnia_defconfig | 1 -
5 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index cc536ff0ba..1d625a9a84 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -63,7 +63,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AES=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_BTRFS=y
CONFIG_CMD_CBFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 64245f7cdc..95b4d06171 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -71,7 +71,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_CMD_AES=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_BTRFS=y
CONFIG_CMD_CBFS=y
CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index b4826548eb..fa7a5681ec 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -50,3 +50,5 @@ CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
# CONFIG_SPL_WDT is not set
+# CONFIG_CMD_BTRFS is not set
+# CONFIG_FS_BTRFS is not set
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index b88cc4b842..89a1c73957 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -32,7 +32,6 @@ CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
-CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MAC_PARTITION=y
CONFIG_OF_BOARD_FIXUP=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index b6cb9a5f9d..160f1de656 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -49,7 +49,6 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_AES=y
CONFIG_CMD_HASH=y
-CONFIG_CMD_BTRFS=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
CONFIG_ENV_IS_IN_SPI_FLASH=y

22
0016-configs-am335x_evm-disable-BTRFS.patch Normal file
View File

@ -0,0 +1,22 @@
From 357c8c498b31d5f05dd6d0b73b4d41b62228ac56 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Wed, 29 Jan 2020 10:26:43 +0100
Subject: [PATCH] configs: am335x_evm: disable BTRFS
Disable BTRFS as otherwise the image get's too big.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
configs/am335x_evm_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index ccb11c9b2a..1894678eea 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -61,3 +61,5 @@ CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_RSA=y
CONFIG_LZO=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
+# CONFIG_CMD_BTRFS is not set
+# CONFIG_FS_BTRFS is not set

60
0016-drivers-bcm283x-Set-pre-location-fl.patch
View File

@ -1,60 +0,0 @@
From 0b0820f5ed04171d9b73a149ea0d3470fcea71d1 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Fri, 8 Nov 2019 14:49:48 +0100
Subject: [PATCH] drivers: bcm283x: Set pre-location flag for OF_BOARD
U-Boot support on Raspberry Pi 4 relies on the device-tree
provided by the firmware. The blob does not contain the
U-Boot specific pre-loc-rel properties. The result is, that
the U-Boot banner is not printed.
We fix this by setting the DM_FLAG_PRE_RELOC flag in the driver,
if we rely on a device-tree provided by the firmware.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 2 +-
drivers/serial/serial_bcm283x_mu.c | 2 +-
drivers/serial/serial_bcm283x_pl011.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index 3be080d29e..1bb91d6eed 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
@@ -148,7 +148,7 @@ U_BOOT_DRIVER(pinctrl_bcm283x) = {
.priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv),
.ops = &bcm283x_pinctrl_ops,
.probe = bcm283x_pinctl_probe,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
#endif
};
diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c
index bd1d89ec83..a6ffc84b96 100644
--- a/drivers/serial/serial_bcm283x_mu.c
+++ b/drivers/serial/serial_bcm283x_mu.c
@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_bcm283x_mu) = {
.platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
.probe = bcm283x_mu_serial_probe,
.ops = &bcm283x_mu_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
#endif
.priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv),
diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c
index 2527bb8b1c..7d8ab7b716 100644
--- a/drivers/serial/serial_bcm283x_pl011.c
+++ b/drivers/serial/serial_bcm283x_pl011.c
@@ -90,7 +90,7 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = {
.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
.probe = pl01x_serial_probe,
.ops = &bcm283x_pl011_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
+#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD)
.flags = DM_FLAG_PRE_RELOC,
#endif
.priv_auto_alloc_size = sizeof(struct pl01x_priv),

26
0017-pinctrl-bcm283x-Add-compatible-for-.patch
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@ -1,26 +0,0 @@
From 54f64870ec3aa2ed8d0b5694f1f3f8df5853ee95 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Wed, 6 Nov 2019 15:28:25 +0100
Subject: [PATCH] pinctrl: bcm283x: Add compatible for RPi4
The Raspberry Pi 4 upstream kernel device tree instroduces
a new compatible for the pinctroller. Add this to the driver
so that we can boot with the upstream kernel DT.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
index 1bb91d6eed..eb720f09f8 100644
--- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
+++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c
@@ -99,6 +99,7 @@ static int bcm283x_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
static const struct udevice_id bcm2835_pinctrl_id[] = {
{.compatible = "brcm,bcm2835-gpio"},
+ {.compatible = "brcm,bcm2711-gpio"},
{}
};

68
0018-rpi-push-fw_dtb_pointer-in-the-.dat.patch
View File

@ -1,68 +0,0 @@
From 9dfd6a0669ac5e299229b90baaa27efe8cc8e927 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Tue, 19 Nov 2019 16:01:02 +0100
Subject: [PATCH] rpi: push fw_dtb_pointer in the .data section
The fw_dtb_pointer was defined in the assembly code, which makes him
live in section .text_rest
Put that's not necessary, we can push the variable in the .data section.
This will prevent relocation errors like:
board/raspberrypi/rpi/rpi.c:317:(.text.board_get_usable_ram_top+0x8):
relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol
`fw_dtb_pointer' defined in .text section in board/raspberrypi/rpi/built-in.o
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
board/raspberrypi/rpi/lowlevel_init.S | 12 ++----------
board/raspberrypi/rpi/rpi.c | 7 +++++--
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/board/raspberrypi/rpi/lowlevel_init.S b/board/raspberrypi/rpi/lowlevel_init.S
index 435eed521f..8c39b3e12e 100644
--- a/board/raspberrypi/rpi/lowlevel_init.S
+++ b/board/raspberrypi/rpi/lowlevel_init.S
@@ -6,15 +6,6 @@
#include <config.h>
-.align 8
-.global fw_dtb_pointer
-fw_dtb_pointer:
-#ifdef CONFIG_ARM64
- .dword 0x0
-#else
- .word 0x0
-#endif
-
/*
* Routine: save_boot_params (called after reset from start.S)
* Description: save ATAG/FDT address provided by the firmware at boot time
@@ -28,7 +19,8 @@ save_boot_params:
adr x8, fw_dtb_pointer
str x0, [x8]
#else
- str r2, fw_dtb_pointer
+ ldr r8, =fw_dtb_pointer
+ str r2, [r8]
#endif
/* Returns */
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 9e0abdda31..e84a1db14a 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -27,8 +27,11 @@
DECLARE_GLOBAL_DATA_PTR;
-/* From lowlevel_init.S */
-extern unsigned long fw_dtb_pointer;
+/* Assigned in lowlevel_init.S
+ * Push the variable into the .data section so that it
+ * does not get cleared later.
+ */
+unsigned long __section(".data") fw_dtb_pointer;
/* TODO(sjg@chromium.org): Move these to the msg.c file */
struct msg_get_arm_mem {

232
0019-ARM-bcm283x-Move-BCM283x_BASE-to-a-.patch
View File

@ -1,232 +0,0 @@
From 3f5c91a5809b13ee0f2f75bda107398fede7536a Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Tue, 19 Nov 2019 16:01:03 +0100
Subject: [PATCH] ARM: bcm283x: Move BCM283x_BASE to a global variable
We move the per SOC define BCM283x_BASE to a global variable.
This is a first step to provide a single binary for several bcm283x
SoCs.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/mach-bcm283x/include/mach/base.h | 11 +++++++++++
arch/arm/mach-bcm283x/include/mach/mbox.h | 4 +++-
arch/arm/mach-bcm283x/include/mach/sdhci.h | 5 ++++-
arch/arm/mach-bcm283x/include/mach/timer.h | 7 ++++++-
arch/arm/mach-bcm283x/include/mach/wdog.h | 5 ++++-
arch/arm/mach-bcm283x/init.c | 8 ++++++++
arch/arm/mach-bcm283x/mbox.c | 1 +
arch/arm/mach-bcm283x/reset.c | 20 +++++++++++++++-----
include/configs/rpi.h | 4 ++++
9 files changed, 56 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/mach-bcm283x/include/mach/base.h
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
new file mode 100644
index 0000000000..c4ae39852f
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2019 Matthias Brugger
+ */
+
+#ifndef _BCM283x_BASE_H_
+#define _BCM283x_BASE_H_
+
+extern unsigned long rpi_bcm283x_base;
+
+#endif
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index 0b6c2543d5..60e226ce1d 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -7,6 +7,7 @@
#define _BCM2835_MBOX_H
#include <linux/compiler.h>
+#include <asm/arch/base.h>
/*
* The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
@@ -37,7 +38,8 @@
/* Raw mailbox HW */
-#define BCM2835_MBOX_PHYSADDR (CONFIG_BCM283x_BASE + 0x0000b880)
+#define BCM2835_MBOX_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
+ rpi_bcm283x_base + 0x0000b880; })
struct bcm2835_mbox_regs {
u32 read;
diff --git a/arch/arm/mach-bcm283x/include/mach/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h
index b443c379d8..7323690687 100644
--- a/arch/arm/mach-bcm283x/include/mach/sdhci.h
+++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h
@@ -6,7 +6,10 @@
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
-#define BCM2835_SDHCI_BASE (CONFIG_BCM283x_BASE + 0x00300000)
+#include <asm/arch/base.h>
+
+#define BCM2835_SDHCI_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
+ rpi_bcm283x_base + 0x00300000; })
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
diff --git a/arch/arm/mach-bcm283x/include/mach/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h
index 014355e759..54f733a956 100644
--- a/arch/arm/mach-bcm283x/include/mach/timer.h
+++ b/arch/arm/mach-bcm283x/include/mach/timer.h
@@ -6,7 +6,12 @@
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
-#define BCM2835_TIMER_PHYSADDR (CONFIG_BCM283x_BASE + 0x00003000)
+#ifndef __ASSEMBLY__
+#include <asm/arch/base.h>
+#endif
+
+#define BCM2835_TIMER_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
+ rpi_bcm283x_base + 0x00003000; })
#define BCM2835_TIMER_CS_M3 (1 << 3)
#define BCM2835_TIMER_CS_M2 (1 << 2)
diff --git a/arch/arm/mach-bcm283x/include/mach/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h
index 8292b3cf1f..9942666720 100644
--- a/arch/arm/mach-bcm283x/include/mach/wdog.h
+++ b/arch/arm/mach-bcm283x/include/mach/wdog.h
@@ -6,7 +6,10 @@
#ifndef _BCM2835_WDOG_H
#define _BCM2835_WDOG_H
-#define BCM2835_WDOG_PHYSADDR (CONFIG_BCM283x_BASE + 0x00100000)
+#include <asm/arch/base.h>
+
+#define BCM2835_WDOG_PHYSADDR ({ BUG_ON(!rpi_bcm283x_base); \
+ rpi_bcm283x_base + 0x00100000; })
struct bcm2835_wdog_regs {
u32 unknown0[7];
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 97414415a6..d36017e823 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -8,6 +8,8 @@
#include <common.h>
+unsigned long rpi_bcm283x_base;
+
int arch_cpu_init(void)
{
icache_enable();
@@ -15,6 +17,12 @@ int arch_cpu_init(void)
return 0;
}
+int mach_cpu_init(void)
+{
+ rpi_bcm283x_base = CONFIG_BCM283x_BASE;
+
+ return 0;
+}
#ifdef CONFIG_ARMV7_LPAE
void enable_caches(void)
{
diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 3c67f68c17..467d0d5fba 100644
--- a/arch/arm/mach-bcm283x/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/base.h>
#include <asm/arch/mbox.h>
#include <phys2bus.h>
diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c
index b3da0c7cd6..cd8138d702 100644
--- a/arch/arm/mach-bcm283x/reset.c
+++ b/arch/arm/mach-bcm283x/reset.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/base.h>
#include <asm/arch/wdog.h>
#include <efi_loader.h>
@@ -25,10 +26,10 @@
void hw_watchdog_disable(void) {}
-__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
- (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs;
-void __efi_runtime reset_cpu(ulong ticks)
+static void __efi_runtime
+__reset_cpu(struct bcm2835_wdog_regs *wdog_regs, ulong ticks)
{
uint32_t rstc, timeout;
@@ -46,6 +47,14 @@ void __efi_runtime reset_cpu(ulong ticks)
writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc);
}
+void reset_cpu(ulong ticks)
+{
+ struct bcm2835_wdog_regs *regs =
+ (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+
+ __reset_cpu(regs, 0);
+}
+
#ifdef CONFIG_EFI_LOADER
void __efi_runtime EFIAPI efi_reset_system(
@@ -58,7 +67,7 @@ void __efi_runtime EFIAPI efi_reset_system(
if (reset_type == EFI_RESET_COLD ||
reset_type == EFI_RESET_WARM ||
reset_type == EFI_RESET_PLATFORM_SPECIFIC) {
- reset_cpu(0);
+ __reset_cpu(wdog_regs, 0);
} else if (reset_type == EFI_RESET_SHUTDOWN) {
/*
* We set the watchdog hard reset bit here to distinguish this reset
@@ -69,7 +78,7 @@ void __efi_runtime EFIAPI efi_reset_system(
val |= BCM2835_WDOG_PASSWORD;
val |= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT;
writel(val, &wdog_regs->rsts);
- reset_cpu(0);
+ __reset_cpu(wdog_regs, 0);
}
while (1) { }
@@ -77,6 +86,7 @@ void __efi_runtime EFIAPI efi_reset_system(
efi_status_t efi_reset_system_init(void)
{
+ wdog_regs = (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
return efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
}
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 77d2d5458a..69b09f3f72 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -9,6 +9,10 @@
#include <linux/sizes.h>
#include <asm/arch/timer.h>
+#ifndef __ASSEMBLY__
+#include <asm/arch/base.h>
+#endif
+
#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

71
0020-ARM-bcm283x-Set-rpi_bcm283x_base-at.patch
View File

@ -1,71 +0,0 @@
From 068815ca7495a41e28b62e119e54e956eb7bc8d7 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Tue, 19 Nov 2019 16:01:04 +0100
Subject: [PATCH] ARM: bcm283x: Set rpi_bcm283x_base at run-time
As part of the effort to create one binary for several bcm83x SoCs
we read the IO base address from device-tree.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/mach-bcm283x/Kconfig | 6 ------
arch/arm/mach-bcm283x/init.c | 20 ++++++++++++++++++--
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index b08275f598..e8e0ff0eb4 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -202,10 +202,4 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "rpi"
-config BCM283x_BASE
- hex
- default "0x20000000" if BCM2835
- default "0x3f000000" if BCM2836 || BCM2837
- default "0xfe000000" if BCM2711
-
endmenu
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index d36017e823..b3f3dfabea 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -7,8 +7,10 @@
*/
#include <common.h>
+#include <dm/device.h>
+#include <fdt_support.h>
-unsigned long rpi_bcm283x_base;
+unsigned long rpi_bcm283x_base = 0x3f000000;
int arch_cpu_init(void)
{
@@ -19,10 +21,24 @@ int arch_cpu_init(void)
int mach_cpu_init(void)
{
- rpi_bcm283x_base = CONFIG_BCM283x_BASE;
+ int ret, soc_offset;
+ u64 io_base, size;
+
+ /* Get IO base from device tree */
+ soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
+ if (soc_offset < 0)
+ return soc_offset;
+
+ ret = fdt_read_range((void *)gd->fdt_blob, soc_offset, 0, NULL,
+ &io_base, &size);
+ if (ret)
+ return ret;
+
+ rpi_bcm283x_base = io_base;
return 0;
}
+
#ifdef CONFIG_ARMV7_LPAE
void enable_caches(void)
{

181
0021-ARM-bcm283x-Set-memory-map-at-run-t.patch
View File

@ -1,181 +0,0 @@
From 2954695f440f60b19f379e83b950031fcbacfb2f Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Tue, 19 Nov 2019 16:01:05 +0100
Subject: [PATCH] ARM: bcm283x: Set memory map at run-time
For bcm283x based on arm64 we also have to change the mm_region.
Add assign this in mach_cpu_init() so we can create now one binary
for RPi3 and RPi4.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/mach-bcm283x/init.c | 92 ++++++++++++++++++++++++++++++++++++
board/raspberrypi/rpi/rpi.c | 45 ------------------
2 files changed, 92 insertions(+), 45 deletions(-)
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index b3f3dfabea..6fb41a99b2 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -10,6 +10,96 @@
#include <dm/device.h>
#include <fdt_support.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region bcm283x_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x3f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x3f000000UL,
+ .phys = 0x3f000000UL,
+ .size = 0x01000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+static struct mm_region bcm2711_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xfe000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xfe000000UL,
+ .phys = 0xfe000000UL,
+ .size = 0x01800000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm283x_mem_map;
+
+/*
+ * I/O address space varies on different chip versions.
+ * We set the base address by inspecting the DTB.
+ */
+static const struct udevice_id board_ids[] = {
+ { .compatible = "brcm,bcm2837", .data = (ulong)&bcm283x_mem_map},
+ { .compatible = "brcm,bcm2838", .data = (ulong)&bcm2711_mem_map},
+ { .compatible = "brcm,bcm2711", .data = (ulong)&bcm2711_mem_map},
+ { },
+};
+
+static void _rpi_update_mem_map(struct mm_region *pd)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ mem_map[i].virt = pd[i].virt;
+ mem_map[i].phys = pd[i].phys;
+ mem_map[i].size = pd[i].size;
+ mem_map[i].attrs = pd[i].attrs;
+ }
+}
+
+static void rpi_update_mem_map(void)
+{
+ int ret;
+ struct mm_region *mm;
+ const struct udevice_id *of_match = board_ids;
+
+ while (of_match->compatible) {
+ ret = fdt_node_check_compatible(gd->fdt_blob, 0,
+ of_match->compatible);
+ if (!ret) {
+ mm = (struct mm_region *)of_match->data;
+ _rpi_update_mem_map(mm);
+ break;
+ }
+
+ of_match++;
+ }
+}
+#else
+static void rpi_update_mem_map(void) {}
+#endif
+
unsigned long rpi_bcm283x_base = 0x3f000000;
int arch_cpu_init(void)
@@ -24,6 +114,8 @@ int mach_cpu_init(void)
int ret, soc_offset;
u64 io_base, size;
+ rpi_update_mem_map();
+
/* Get IO base from device tree */
soc_offset = fdt_path_offset(gd->fdt_blob, "/soc");
if (soc_offset < 0)
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index e84a1db14a..3d4afaf653 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -251,51 +251,6 @@ static uint32_t rev_scheme;
static uint32_t rev_type;
static const struct rpi_model *model;
-#ifdef CONFIG_ARM64
-#ifndef CONFIG_BCM2711
-static struct mm_region bcm283x_mem_map[] = {
- {
- .virt = 0x00000000UL,
- .phys = 0x00000000UL,
- .size = 0x3f000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x3f000000UL,
- .phys = 0x3f000000UL,
- .size = 0x01000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-#else
-static struct mm_region bcm283x_mem_map[] = {
- {
- .virt = 0x00000000UL,
- .phys = 0x00000000UL,
- .size = 0xfe000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xfe000000UL,
- .phys = 0xfe000000UL,
- .size = 0x01800000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-#endif
-struct mm_region *mem_map = bcm283x_mem_map;
-#endif
-
int dram_init(void)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);

86
0022-ARM-defconfig-add-unified-config-fo.patch
View File

@ -1,86 +0,0 @@
From 51b57e87c48f5a75971817ae80a2fd113f26da74 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Wed, 6 Nov 2019 15:41:03 +0100
Subject: [PATCH] ARM: defconfig: add unified config for RPi3 and RPi4
Provide a defconfig which allows us to boot Raspberrry Pi 4
and Raspberry Pi 3 Model B/B+
Instead of using the embedded DTB as done in RPi3 we use the
devicetree provided by the firmware.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
arch/arm/mach-bcm283x/Kconfig | 7 ++++++
configs/rpi_arm64_defconfig | 45 +++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 configs/rpi_arm64_defconfig
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index e8e0ff0eb4..00419bf254 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -188,6 +188,13 @@ config TARGET_RPI_4
This option creates a build targeting the ARMv8/AArch64 ISA.
select BCM2711_64B
+config TARGET_RPI_ARM64
+ bool "Raspberry Pi one binary 64-bit build"
+ help
+ Support for all armv8 based Raspberry Pi variants, such as
+ the RPi 4 model B, in AArch64 (64-bit) mode.
+ select ARM64
+
endchoice
config SYS_BOARD
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
new file mode 100644
index 0000000000..f4e113f58c
--- /dev/null
+++ b/configs/rpi_arm64_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARM=y
+CONFIG_ARM64=y
+CONFIG_TARGET_RPI_ARM64=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_SYS_TEXT_BASE=0x00080000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT_OVERLAY=y

43
0024-rpi-fix-dram-bank-initialization.patch
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@ -1,43 +0,0 @@
From 6903bb74d467121c2d2c99b4272fe4363e8f2f64 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Thu, 5 Dec 2019 18:53:13 +0100
Subject: [PATCH] rpi: fix dram bank initialization
To update the dram bank information from device-tree we use
fdtdec_decode_ram_size() which expectes the the size-cells and
address-cells to be defined in the memory node. For normal system RAM
these values are defined in the root node. When the values differ from
the default values defined in the spec, we can end up with wrong RAM
bank information.
Switch to the "standard" way to update the RAM bank information to
avoid this.
Fixes: 9de5b89e4c ("rpi4: enable dram bank initialization")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
(cherry picked from commit e19cfcc07ac5da8b3a04e21875ec542d994865d4)
---
board/raspberrypi/rpi/rpi.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 3d4afaf653..76f1c55b65 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -274,8 +274,13 @@ int dram_init(void)
#ifdef CONFIG_BCM2711
int dram_init_banksize(void)
{
- return fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
- (phys_size_t *)&gd->ram_size, gd->bd);
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
}
#endif
#endif

39
0025-rpi-Enable-DRAM-bank-initialization.patch
View File

@ -1,39 +0,0 @@
From 8dcbd1a138d5accd339ec990750070bef537cd45 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Thu, 5 Dec 2019 18:53:14 +0100
Subject: [PATCH] rpi: Enable DRAM bank initialization on arm64
Up to now we only update the DRAM banks when we are define
CONFIG_BCM2711. But our one binary approach uses a config that supports
BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on
Raspberry Pi 4, even if it has more RAM.
Fix this by calling dram_init_banksize.
Fixes: 5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
(cherry picked from commit a63f81c242090682ea4907fa6475d8057208cb05)
---
board/raspberrypi/rpi/rpi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 76f1c55b65..17d463e16f 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -271,7 +271,6 @@ int dram_init(void)
}
#ifdef CONFIG_OF_BOARD
-#ifdef CONFIG_BCM2711
int dram_init_banksize(void)
{
int ret;
@@ -283,7 +282,6 @@ int dram_init_banksize(void)
return fdtdec_setup_mem_size_base();
}
#endif
-#endif
static void set_fdtfile(void)
{

30
0026-ARM-defconfig-Fix-32bit-config-for-.patch
View File

@ -1,30 +0,0 @@
From 25da6429ff2aeb00119b2ba43cc59149d7e07b5a Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Thu, 5 Dec 2019 18:53:15 +0100
Subject: [PATCH] ARM: defconfig: Fix 32bit config for RPi4
The rpi_4_32b_defconfig states that only one DRAM bank is present. This
leads to a wrong configuration of the available DRAM. Fix this by
setting the DRAM bank config accordingly.
Fixes: 193279d784 ("RPI: Add defconfigs for rpi4 (32/64)")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
(cherry picked from commit e5167465a1740f0cac05be44f3e2a4e334eb527a)
---
configs/rpi_4_32b_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index dc696906fd..ec7330a98d 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -3,7 +3,7 @@ CONFIG_ARCH_BCM283X=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_TARGET_RPI_4_32B=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set

1
_multibuild
View File

@ -55,6 +55,7 @@
<flavor>orangepipc2</flavor>
<flavor>p2371-2180</flavor>
<flavor>p2771-0000-500</flavor>
<flavor>p3450-0000</flavor>
<flavor>paz00</flavor>
<flavor>pcm051rev3</flavor>
<flavor>pine64plus</flavor>

3
u-boot-2019.10.tar.bz2
View File

@ -1,3 +0,0 @@
version https://git-lfs.github.com/spec/v1
oid sha256:8d6d6070739522dd236cba7055b8736bfe92b4fac0ea18ad809829ca79667014
size 14214608

BIN
u-boot-2019.10.tar.bz2.sig
View File

Binary file not shown.

3
u-boot-2020.01.tar.bz2 Normal file
View File

@ -0,0 +1,3 @@
version https://git-lfs.github.com/spec/v1
oid sha256:aa453c603208b1b27bd03525775a7f79b443adec577fdc6e8f06974025a135f1
size 14716125

BIN
u-boot-2020.01.tar.bz2.sig Normal file
View File

Binary file not shown.

62
u-boot.changes
View File

@ -1,8 +1,70 @@
-------------------------------------------------------------------
Wed Jan 29 09:28:32 UTC 2020 - Matthias Brugger <mbrugger@suse.com>
Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.01
Add support for Jetson Nano.
Enable btrfs by default. (jsc#SLE-10302)
Add network support for RPi4 (jsc#SLE-7276)
* Patches added:
0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch
0011-net-Add-support-for-Broadcom-GENETv.patch
0012-rpi4-Update-memory-map-to-accommoda.patch
0013-rpi4-Enable-GENET-Ethernet-controll.patch
0014-Kconfig-add-btrfs-to-distro-boot.patch
0015-configs-Re-sync-with-CONFIG_DISTRO_.patch
0016-configs-am335x_evm-disable-BTRFS.patch
-------------------------------------------------------------------
Wed Jan 22 08:09:47 UTC 2020 - Guillaume GARDET <guillaume.gardet@opensuse.org>
- Package u-boot.img instead of u-boot.bin for snow and spring
-------------------------------------------------------------------
Fri Jan 10 10:45:00 UTC 2020 - Guillaume GARDET <guillaume.gardet@opensuse.org>
- Fix firefly-rk3288 and tinker-rk3288 by using TPL instead of SPL
(SPL too big)
-------------------------------------------------------------------
Fri Jan 10 09:53:50 UTC 2020 - Guillaume GARDET <guillaume.gardet@opensuse.org>
- Fix mx6qsabrelite build
-------------------------------------------------------------------
Tue Jan 7 08:32:01 UTC 2020 - Guillaume GARDET <guillaume.gardet@opensuse.org>
- Update to v2020.01:
* Now requires python 3.5+ (2.x support dropped)
* Add Orange Pi Zero Plus 2 support
* Platfrom fixes: atmel, fsl, imx, Marvell, RPi, rockchip, sunxi, TI
* EFI fixes
* I2C fixes
* MMC fixes
* SPI fixes
* USB fixes
- Patch queue updated from git://github.com/openSUSE/u-boot.git tumbleweed-2020.01
* Patches dropped:
0009-libfdt-fdt_address_cells-and-fdt_si.patch
0010-libfdt-return-correct-value-if-size.patch
0011-libfdt-Allow-size-cells-of-0.patch
0012-dm-Fix-default-address-cells-return.patch
0013-arm-arm11-allow-unaligned-memory-ac.patch
0014-fdt-fix-bcm283x-dm-pre-reloc-defini.patch
0015-arm-dts-bcm283x-Rename-U-Boot-file.patch
0016-drivers-bcm283x-Set-pre-location-fl.patch
0017-pinctrl-bcm283x-Add-compatible-for-.patch
0018-rpi-push-fw_dtb_pointer-in-the-.dat.patch
0019-ARM-bcm283x-Move-BCM283x_BASE-to-a-.patch
0020-ARM-bcm283x-Set-rpi_bcm283x_base-at.patch
0021-ARM-bcm283x-Set-memory-map-at-run-t.patch
0022-ARM-defconfig-add-unified-config-fo.patch
0023-boo-1144161-Remove-nand-mtd-spi-dfu.patch
0024-rpi-fix-dram-bank-initialization.patch
0025-rpi-Enable-DRAM-bank-initialization.patch
0026-ARM-defconfig-Fix-32bit-config-for-.patch
* Patches added:
0009-boo-1144161-Remove-nand-mtd-spi-dfu.patch
-------------------------------------------------------------------
Fri Dec 20 11:08:03 UTC 2019 - Guillaume GARDET <guillaume.gardet@opensuse.org>

56
u-boot.spec
View File

@ -22,6 +22,7 @@
%define mvebu_spl 0
%define x_loader 0
%define rockchip_spl 0
%define rockchip_tpl 0
%define rockchip_idb 0
%define sunxi_spl 0
%define arndale_spl 0
@ -49,7 +50,7 @@
%endif
%if "%target" == "firefly-rk3288" || "%target" == "tinker-rk3288"
%define is_armv7 1
%define rockchip_spl 1
%define rockchip_tpl 1
%define soc_name "rk3288"
%if "%target" == "firefly-rk3288"
%define rkimages rksd rkimage
@ -103,10 +104,14 @@
%define is_armv7 1
%define binext .img
%endif
%if "%target" == "mx53loco" || "%target" == "mx6qsabrelite"
%if "%target" == "mx53loco"
%define is_armv7 1
%define binext .imx
%endif
%if "%target" == "mx6qsabrelite"
%define is_armv7 1
%define binext -dtb.imx
%endif
%if "%target" == "mx6cuboxi" || "%target" == "udoo" || "%target" == "udooneo"
%define imx6_spl 1
%define is_armv7 1
@ -127,7 +132,7 @@
%if "%target" == "dragonboard410c" || "%target" == "dragonboard820c"
%define is_armv8 1
%endif
%if "%target" == "geekbox" || "%target" == "hikey" || "%target" == "khadas-vim" || "%target" == "khadas-vim2" || "%target" == "libretech-ac" || "%target" == "libretech-cc" || "%target" == "ls1012afrdmqspi" || "%target" == "mvebudb-88f3720" || "%target" == "mvebudbarmada8k" || "%target" == "mvebuespressobin-88f3720" || "%target" == "mvebumcbin-88f8040" || "%target" == "odroid-c2" || "%target" == "p2371-2180" || "%target" == "p2771-0000-500" || "%target" == "poplar"
%if "%target" == "geekbox" || "%target" == "hikey" || "%target" == "khadas-vim" || "%target" == "khadas-vim2" || "%target" == "libretech-ac" || "%target" == "libretech-cc" || "%target" == "ls1012afrdmqspi" || "%target" == "mvebudb-88f3720" || "%target" == "mvebudbarmada8k" || "%target" == "mvebuespressobin-88f3720" || "%target" == "mvebumcbin-88f8040" || "%target" == "odroid-c2" || "%target" == "p2371-2180" || "%target" == "p2771-0000-500" || "%target" == "p3450-0000" || "%target" == "poplar"
%define is_armv8 1
%endif
%if "%target" == "avnetultra96rev1" || "%target" == "xilinxzynqmpgeneric" || "%target" == "xilinxzynqmpzcu102rev10"
@ -152,7 +157,7 @@
%define is_ppc 1
%endif
# archive_version differs from version for RC version only
%define archive_version 2019.10
%define archive_version 2020.01
%if "%{target}" == ""
ExclusiveArch: do_not_build
%else
@ -184,7 +189,7 @@ ExclusiveArch: do_not_build
%endif
%bcond_with uboot_atf
%bcond_with uboot_atf_pine64
Version: 2019.10
Version: 2020.01
Release: 0
Summary: The U-Boot firmware for the %target platform
License: GPL-2.0-only
@ -204,24 +209,14 @@ Patch0005: 0005-zynqmp-Add-generic-target.patch
Patch0006: 0006-tools-zynqmpbif-Add-support-for-loa.patch
Patch0007: 0007-boo-1123170-Remove-ubifs-support-fr.patch
Patch0008: 0008-zynqmp-generic-fix-compilation.patch
Patch0009: 0009-libfdt-fdt_address_cells-and-fdt_si.patch
Patch0010: 0010-libfdt-return-correct-value-if-size.patch
Patch0011: 0011-libfdt-Allow-size-cells-of-0.patch
Patch0012: 0012-dm-Fix-default-address-cells-return.patch
Patch0013: 0013-arm-arm11-allow-unaligned-memory-ac.patch
Patch0014: 0014-fdt-fix-bcm283x-dm-pre-reloc-defini.patch
Patch0015: 0015-arm-dts-bcm283x-Rename-U-Boot-file.patch
Patch0016: 0016-drivers-bcm283x-Set-pre-location-fl.patch
Patch0017: 0017-pinctrl-bcm283x-Add-compatible-for-.patch
Patch0018: 0018-rpi-push-fw_dtb_pointer-in-the-.dat.patch
Patch0019: 0019-ARM-bcm283x-Move-BCM283x_BASE-to-a-.patch
Patch0020: 0020-ARM-bcm283x-Set-rpi_bcm283x_base-at.patch
Patch0021: 0021-ARM-bcm283x-Set-memory-map-at-run-t.patch
Patch0022: 0022-ARM-defconfig-add-unified-config-fo.patch
Patch0023: 0023-boo-1144161-Remove-nand-mtd-spi-dfu.patch
Patch0024: 0024-rpi-fix-dram-bank-initialization.patch
Patch0025: 0025-rpi-Enable-DRAM-bank-initialization.patch
Patch0026: 0026-ARM-defconfig-Fix-32bit-config-for-.patch
Patch0009: 0009-boo-1144161-Remove-nand-mtd-spi-dfu.patch
Patch0010: 0010-ARM-tegra-Add-NVIDIA-Jetson-Nano-De.patch
Patch0011: 0011-net-Add-support-for-Broadcom-GENETv.patch
Patch0012: 0012-rpi4-Update-memory-map-to-accommoda.patch
Patch0013: 0013-rpi4-Enable-GENET-Ethernet-controll.patch
Patch0014: 0014-Kconfig-add-btrfs-to-distro-boot.patch
Patch0015: 0015-configs-Re-sync-with-CONFIG_DISTRO_.patch
Patch0016: 0016-configs-am335x_evm-disable-BTRFS.patch
# Patches: end
BuildRequires: bc
BuildRequires: bison
@ -231,7 +226,7 @@ BuildRequires: flex
# u-boot-clearfog (tools/kwbimage.c) needs openssl to build
BuildRequires: libopenssl-devel
BuildRequires: pkgconfig
BuildRequires: python-devel
BuildRequires: python3-devel
BuildRequires: swig
BuildRequires: pkgconfig(sdl)
Conflicts: u-boot-loader
@ -408,6 +403,13 @@ for t in %{rkimages}; do
./tools/mkimage -n %soc_name -d spl/u-boot-spl.bin -T $t u-boot-spl.$t || exit 1
done
%endif
%if %rockchip_tpl == 1
for t in %{rkimages}; do
./tools/mkimage -n %soc_name -d tpl/u-boot-tpl.bin -T $t u-boot-tpl.$t || exit 1
cat spl/u-boot-spl-dtb.bin >> u-boot-tpl.$t
done
%endif
%endif
%install
@ -466,6 +468,12 @@ for t in %{rkimages}; do
install -D -m 0644 u-boot-spl.$t %{buildroot}%{uboot_dir}/u-boot-spl.$t
done
%endif
%if %rockchip_tpl == 1
install -D -m 0644 tpl/u-boot-tpl.bin %{buildroot}%{uboot_dir}/u-boot-tpl.bin
for t in %{rkimages}; do
install -D -m 0644 u-boot-tpl.$t %{buildroot}%{uboot_dir}/u-boot-tpl.$t
done
%endif
%if %rockchip_idb == 1
install -D -m 0644 idbloader.img %{buildroot}%{uboot_dir}/idbloader.img
%endif

4
update_git.sh
View File

@ -13,8 +13,8 @@ set -e
GIT_TREE=git://github.com/openSUSE/u-boot.git
GIT_LOCAL_TREE=~/git/u-boot-opensuse
GIT_BRANCH=tumbleweed-2019.10
GIT_UPSTREAM_TAG=v2019.10
GIT_BRANCH=tumbleweed-2020.01
GIT_UPSTREAM_TAG=v2020.01
GIT_DIR=/dev/shm/u-boot-factory-git-dir
CMP_DIR=/dev/shm/u-boot-factory-cmp-dir