111 lines
3.2 KiB
Diff
111 lines
3.2 KiB
Diff
From a28b57b475d5c20e00d80b1ee0d085f1bf635afb Mon Sep 17 00:00:00 2001
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From: Matthias Brugger <matthias.bgg@gmail.com>
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Date: Thu, 23 May 2024 17:46:10 +0200
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Subject: [PATCH] riscv: dts: jh7110: Update qspi node with upstream
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Upstream node uses a specific SoC compatible to make the kernel driver
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work. Copy over the upstream node to fullfill that need.
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Signed-off-by: Matthias Brugger <mbrugger@suse.com>
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---
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.../jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +-
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.../dts/jh7110-starfive-visionfive-2.dtsi | 29 ++++++++++++++++---
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arch/riscv/dts/jh7110.dtsi | 19 +++++++-----
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3 files changed, 37 insertions(+), 13 deletions(-)
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diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
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index 3012466b305..a69d8fcb391 100644
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--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
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+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
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@@ -40,7 +40,7 @@
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&qspi {
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bootph-pre-ram;
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- nor-flash@0 {
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+ nor_flash@0 {
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bootph-pre-ram;
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};
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};
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diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
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index e11babc1cde..375449b73a8 100644
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--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
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+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
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@@ -305,17 +305,38 @@
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};
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&qspi {
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- spi-max-frequency = <250000000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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status = "okay";
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- nor-flash@0 {
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+ nor_flash: nor_flash@0 {
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compatible = "jedec,spi-nor";
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- reg=<0>;
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- spi-max-frequency = <100000000>;
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+ reg = <0>;
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+ cdns,read-delay = <5>;
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+ spi-max-frequency = <12000000>;
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cdns,tshsl-ns = <1>;
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cdns,tsd2d-ns = <1>;
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cdns,tchsh-ns = <1>;
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cdns,tslch-ns = <1>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ spl@0 {
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+ reg = <0x0 0x80000>;
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+ };
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+ uboot-env@f0000 {
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+ reg = <0xf0000 0x10000>;
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+ };
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+ uboot@100000 {
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+ reg = <0x100000 0x400000>;
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+ };
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+ reserved-data@600000 {
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+ reg = <0x600000 0xa00000>;
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+ };
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+ };
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};
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};
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diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
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index 2cdc683d49b..2b331e58497 100644
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--- a/arch/riscv/dts/jh7110.dtsi
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+++ b/arch/riscv/dts/jh7110.dtsi
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@@ -480,19 +480,22 @@
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};
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qspi: spi@13010000 {
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- compatible = "cdns,qspi-nor";
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- reg = <0x0 0x13010000 0x0 0x10000
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- 0x0 0x21000000 0x0 0x400000>;
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- clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
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- clock-names = "clk_ref";
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+ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
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+ reg = <0x0 0x13010000 0x0 0x10000>,
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+ <0x0 0x21000000 0x0 0x400000>;
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+ interrupts = <25>;
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+ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
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+ <&syscrg JH7110_SYSCLK_QSPI_AHB>,
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+ <&syscrg JH7110_SYSCLK_QSPI_APB>;
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+ clock-names = "ref", "ahb", "apb";
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resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
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<&syscrg JH7110_SYSRST_QSPI_AHB>,
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<&syscrg JH7110_SYSRST_QSPI_REF>;
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- reset-names = "rst_apb", "rst_ahb", "rst_ref";
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+ reset-names = "qspi", "qspi-ocp", "rstc_ref";
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cdns,fifo-depth = <256>;
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cdns,fifo-width = <4>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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+ cdns,trigger-address = <0x0>;
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+ status = "disabled";
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};
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syscrg: clock-controller@13020000 {
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