From ac63b33d3eca2b780b240cde29d8e7e6154e538264a2a6557ab785a2d429cac6 Mon Sep 17 00:00:00 2001 From: Marcus Meissner Date: Tue, 9 Jun 2020 17:45:20 +0000 Subject: [PATCH] Accepting request 813007 from home:msmeissn:branches:Base:System - Updated Intel CPU Microcode to 20200609 (bsc#1172466) Fixes for: - CVE-2020-0543: Fixed a side channel attack against special registers which could have resulted in leaking of read values to cores other than the one which called it. This attack is known as Special Register Buffer Data Sampling (SRBDS) or "CrossTalk" (bsc#1154824). - CVE-2020-0548,CVE-2020-0549: Additional ucode updates were supplied to mitigate the Vector Register and L1D Eviction Sampling aka "CacheOutAttack" attacks. (bsc#1156353) == 20200602_DEMO Release == -- Updates upon 20200520 release -- Processor Identifier Version Products Model Stepping F-MO-S/PI Old->New ---- new platforms ---------------------------------------- ---- updated platforms ------------------------------------ HSW C0 6-3c-3/32 00000027->00000028 Core Gen4 BDW-U/Y E0/F0 6-3d-4/c0 0000002e->0000002f Core Gen5 HSW-U C0/D0 6-45-1/72 00000025->00000026 Core Gen4 HSW-H C0 6-46-1/32 0000001b->0000001c Core Gen4 BDW-H/E3 E0/G0 6-47-1/22 00000021->00000022 Core Gen5 SKL-U/Y D0 6-4e-3/c0 000000d6->000000dc Core Gen6 Mobile SKL-U23e K1 6-4e-3/c0 000000d6->000000dc Core Gen6 Mobile SKX-SP B1 6-55-3/97 01000151->01000157 Xeon Scalable SKX-SP H0/M0/U0 6-55-4/b7 02000065->02006906 Xeon Scalable SKX-D M1 6-55-4/b7 02000065->02006906 Xeon D-21xx CLX-SP B0 6-55-6/bf 0400002c->04002f01 Xeon Scalable Gen2 CLX-SP B1 6-55-7/bf 0500002c->04002f01 Xeon Scalable Gen2 SKL-H/S R0/N0 6-5e-3/36 000000d6->000000dc Core Gen6; Xeon E3 v5 AML-Y22 H0 6-8e-9/10 000000ca->000000d6 Core Gen8 Mobile KBL-U/Y H0 6-8e-9/c0 000000ca->000000d6 Core Gen7 Mobile OBS-URL: https://build.opensuse.org/request/show/813007 OBS-URL: https://build.opensuse.org/package/show/Base:System/ucode-intel?expand=0&rev=79 --- microcode-20191115.tar.gz | 3 --- microcode-20200609.tar.gz | 3 +++ ucode-intel.changes | 56 +++++++++++++++++++++++++++++++++++++++ ucode-intel.spec | 8 +++--- 4 files changed, 63 insertions(+), 7 deletions(-) delete mode 100644 microcode-20191115.tar.gz create mode 100644 microcode-20200609.tar.gz diff --git a/microcode-20191115.tar.gz b/microcode-20191115.tar.gz deleted file mode 100644 index 9665ece..0000000 --- a/microcode-20191115.tar.gz +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:14b26d27be70774948b8cb582e298f5317263b8b8bb1fe8e41260eae54f531dc -size 2998063 diff --git a/microcode-20200609.tar.gz b/microcode-20200609.tar.gz new file mode 100644 index 0000000..c924884 --- /dev/null +++ b/microcode-20200609.tar.gz @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6c5295265abd03a7cdc815b85bff4f98387f813826a88935904bc2bbc783d5e4 +size 3043809 diff --git a/ucode-intel.changes b/ucode-intel.changes index e1c6822..55ea4d8 100644 --- a/ucode-intel.changes +++ b/ucode-intel.changes @@ -1,3 +1,59 @@ +------------------------------------------------------------------- +Wed Jun 3 14:44:24 UTC 2020 - Marcus Meissner + +- Updated Intel CPU Microcode to 20200609 (bsc#1172466) + + Fixes for: + - CVE-2020-0543: Fixed a side channel attack against special registers + which could have resulted in leaking of read values to cores other + than the one which called it. This attack is known as Special Register + Buffer Data Sampling (SRBDS) or "CrossTalk" (bsc#1154824). + - CVE-2020-0548,CVE-2020-0549: Additional ucode updates were supplied to + mitigate the Vector Register and L1D Eviction Sampling aka "CacheOutAttack" + attacks. (bsc#1156353) + + == 20200602_DEMO Release == + -- Updates upon 20200520 release -- + Processor Identifier Version Products + Model Stepping F-MO-S/PI Old->New + ---- new platforms ---------------------------------------- + + ---- updated platforms ------------------------------------ + HSW C0 6-3c-3/32 00000027->00000028 Core Gen4 + BDW-U/Y E0/F0 6-3d-4/c0 0000002e->0000002f Core Gen5 + HSW-U C0/D0 6-45-1/72 00000025->00000026 Core Gen4 + HSW-H C0 6-46-1/32 0000001b->0000001c Core Gen4 + BDW-H/E3 E0/G0 6-47-1/22 00000021->00000022 Core Gen5 + SKL-U/Y D0 6-4e-3/c0 000000d6->000000dc Core Gen6 Mobile + SKL-U23e K1 6-4e-3/c0 000000d6->000000dc Core Gen6 Mobile + SKX-SP B1 6-55-3/97 01000151->01000157 Xeon Scalable + SKX-SP H0/M0/U0 6-55-4/b7 02000065->02006906 Xeon Scalable + SKX-D M1 6-55-4/b7 02000065->02006906 Xeon D-21xx + CLX-SP B0 6-55-6/bf 0400002c->04002f01 Xeon Scalable Gen2 + CLX-SP B1 6-55-7/bf 0500002c->04002f01 Xeon Scalable Gen2 + SKL-H/S R0/N0 6-5e-3/36 000000d6->000000dc Core Gen6; Xeon E3 v5 + AML-Y22 H0 6-8e-9/10 000000ca->000000d6 Core Gen8 Mobile + KBL-U/Y H0 6-8e-9/c0 000000ca->000000d6 Core Gen7 Mobile + CFL-U43e D0 6-8e-a/c0 000000ca->000000d6 Core Gen8 Mobile + WHL-U W0 6-8e-b/d0 000000ca->000000d6 Core Gen8 Mobile + AML-Y42 V0 6-8e-c/94 000000ca->000000d6 Core Gen10 Mobile + CML-Y42 V0 6-8e-c/94 000000ca->000000d6 Core Gen10 Mobile + WHL-U V0 6-8e-c/94 000000ca->000000d6 Core Gen8 Mobile + KBL-G/H/S/E3 B0 6-9e-9/2a 000000ca->000000d6 Core Gen7; Xeon E3 v6 + CFL-H/S/E3 U0 6-9e-a/22 000000ca->000000d6 Core Gen8 Desktop, Mobile, Xeon E + CFL-S B0 6-9e-b/02 000000ca->000000d6 Core Gen8 + CFL-H/S P0 6-9e-c/22 000000ca->000000d6 Core Gen9 + CFL-H R0 6-9e-d/22 000000ca->000000d6 Core Gen9 Mobile + +- Updated Intel CPU Microcode to 20200520 + + Processor Identifier Version Products + Model Stepping F-MO-S/PI Old->New + ---- new platforms ---------------------------------------- + ---- updated platforms ------------------------------------ + SNB-E/EN/EP C1/M0 6-2d-6/6d 0000061f->00000621 Xeon E3/E5, Core X + SNB-E/EN/EP C2/M1 6-2d-7/6d 00000718->0000071a Xeon E3/E5, Core X + ------------------------------------------------------------------- Tue Nov 19 06:06:55 UTC 2019 - Marcus Meissner diff --git a/ucode-intel.spec b/ucode-intel.spec index 9ec3ea9..01cbc93 100644 --- a/ucode-intel.spec +++ b/ucode-intel.spec @@ -1,7 +1,7 @@ # # spec file for package ucode-intel # -# Copyright (c) 2019 SUSE LINUX GmbH, Nuernberg, Germany. +# Copyright (c) 2020 SUSE LLC # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -12,19 +12,19 @@ # license that conforms to the Open Source Definition (Version 1.9) # published by the Open Source Initiative. -# Please submit bugfixes or comments via http://bugs.opensuse.org/ +# Please submit bugfixes or comments via https://bugs.opensuse.org/ # Name: ucode-intel -Version: 20191115 +Version: 20200609 Release: 0 Summary: Microcode Updates for Intel x86/x86-64 CPUs License: SUSE-Firmware Group: Hardware/Other BuildRequires: suse-module-tools #License is: Intel Software License Agreement -Url: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files +URL: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files Source0: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-%version.tar.gz Source1: ucode-intel-rpmlintrc Supplements: modalias(x86cpu:vendor%3A0000%3Afamily%3A*%3Amodel%3A*%3Afeature%3A*)