diff --git a/VEX-r2803.diff b/VEX-r2803.diff deleted file mode 100644 index f74a57f..0000000 --- a/VEX-r2803.diff +++ /dev/null @@ -1,21176 +0,0 @@ -Index: VEX/auxprogs/genoffsets.c -=================================================================== ---- VEX/auxprogs/genoffsets.c.orig -+++ VEX/auxprogs/genoffsets.c -@@ -51,6 +51,7 @@ - #include "../pub/libvex_guest_ppc32.h" - #include "../pub/libvex_guest_ppc64.h" - #include "../pub/libvex_guest_arm.h" -+#include "../pub/libvex_guest_arm64.h" - #include "../pub/libvex_guest_s390x.h" - #include "../pub/libvex_guest_mips32.h" - #include "../pub/libvex_guest_mips64.h" -@@ -159,6 +160,19 @@ void foo ( void ) - GENOFFSET(ARM,arm,R14); - GENOFFSET(ARM,arm,R15T); - -+ // arm64 -+ GENOFFSET(ARM64,arm64,X0); -+ GENOFFSET(ARM64,arm64,X1); -+ GENOFFSET(ARM64,arm64,X2); -+ GENOFFSET(ARM64,arm64,X3); -+ GENOFFSET(ARM64,arm64,X4); -+ GENOFFSET(ARM64,arm64,X5); -+ GENOFFSET(ARM64,arm64,X6); -+ GENOFFSET(ARM64,arm64,X7); -+ GENOFFSET(ARM64,arm64,X8); -+ GENOFFSET(ARM64,arm64,SP); -+ GENOFFSET(ARM64,arm64,PC); -+ - // s390x - GENOFFSET(S390X,s390x,r2); - GENOFFSET(S390X,s390x,r3); -Index: VEX/priv/host_arm64_defs.c -=================================================================== ---- /dev/null -+++ VEX/priv/host_arm64_defs.c -@@ -0,0 +1,5930 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin host_arm64_defs.c ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "libvex_basictypes.h" -+#include "libvex.h" -+#include "libvex_trc_values.h" -+ -+#include "main_util.h" -+#include "host_generic_regs.h" -+#include "host_arm64_defs.h" -+ -+//ZZ UInt arm_hwcaps = 0; -+ -+ -+/* --------- Registers. --------- */ -+ -+/* The usual HReg abstraction. We use the following classes only: -+ X regs (64 bit int) -+ D regs (64 bit float, also used for 32 bit float) -+ Q regs (128 bit vector) -+*/ -+ -+void ppHRegARM64 ( HReg reg ) { -+ Int r; -+ /* Be generic for all virtual regs. */ -+ if (hregIsVirtual(reg)) { -+ ppHReg(reg); -+ return; -+ } -+ /* But specific for real regs. */ -+ switch (hregClass(reg)) { -+ case HRcInt64: -+ r = hregNumber(reg); -+ vassert(r >= 0 && r < 31); -+ vex_printf("x%d", r); -+ return; -+ case HRcFlt64: -+ r = hregNumber(reg); -+ vassert(r >= 0 && r < 32); -+ vex_printf("d%d", r); -+ return; -+ case HRcVec128: -+ r = hregNumber(reg); -+ vassert(r >= 0 && r < 32); -+ vex_printf("q%d", r); -+ return; -+ default: -+ vpanic("ppHRegARM64"); -+ } -+} -+ -+static void ppHRegARM64asSreg ( HReg reg ) { -+ ppHRegARM64(reg); -+ vex_printf("(S-reg)"); -+} -+ -+HReg hregARM64_X0 ( void ) { return mkHReg(0, HRcInt64, False); } -+HReg hregARM64_X1 ( void ) { return mkHReg(1, HRcInt64, False); } -+HReg hregARM64_X2 ( void ) { return mkHReg(2, HRcInt64, False); } -+HReg hregARM64_X3 ( void ) { return mkHReg(3, HRcInt64, False); } -+HReg hregARM64_X4 ( void ) { return mkHReg(4, HRcInt64, False); } -+HReg hregARM64_X5 ( void ) { return mkHReg(5, HRcInt64, False); } -+HReg hregARM64_X6 ( void ) { return mkHReg(6, HRcInt64, False); } -+HReg hregARM64_X7 ( void ) { return mkHReg(7, HRcInt64, False); } -+//ZZ HReg hregARM_R8 ( void ) { return mkHReg(8, HRcInt32, False); } -+HReg hregARM64_X9 ( void ) { return mkHReg(9, HRcInt64, False); } -+HReg hregARM64_X10 ( void ) { return mkHReg(10, HRcInt64, False); } -+HReg hregARM64_X11 ( void ) { return mkHReg(11, HRcInt64, False); } -+HReg hregARM64_X12 ( void ) { return mkHReg(12, HRcInt64, False); } -+HReg hregARM64_X13 ( void ) { return mkHReg(13, HRcInt64, False); } -+HReg hregARM64_X14 ( void ) { return mkHReg(14, HRcInt64, False); } -+HReg hregARM64_X15 ( void ) { return mkHReg(15, HRcInt64, False); } -+HReg hregARM64_X21 ( void ) { return mkHReg(21, HRcInt64, False); } -+HReg hregARM64_X22 ( void ) { return mkHReg(22, HRcInt64, False); } -+HReg hregARM64_X23 ( void ) { return mkHReg(23, HRcInt64, False); } -+HReg hregARM64_X24 ( void ) { return mkHReg(24, HRcInt64, False); } -+HReg hregARM64_X25 ( void ) { return mkHReg(25, HRcInt64, False); } -+HReg hregARM64_X26 ( void ) { return mkHReg(26, HRcInt64, False); } -+HReg hregARM64_X27 ( void ) { return mkHReg(27, HRcInt64, False); } -+HReg hregARM64_X28 ( void ) { return mkHReg(28, HRcInt64, False); } -+ -+// Should really use D8 .. D15 for class F64, since they are callee -+// save -+HReg hregARM64_D8 ( void ) { return mkHReg(8, HRcFlt64, False); } -+HReg hregARM64_D9 ( void ) { return mkHReg(9, HRcFlt64, False); } -+HReg hregARM64_D10 ( void ) { return mkHReg(10, HRcFlt64, False); } -+HReg hregARM64_D11 ( void ) { return mkHReg(11, HRcFlt64, False); } -+HReg hregARM64_D12 ( void ) { return mkHReg(12, HRcFlt64, False); } -+HReg hregARM64_D13 ( void ) { return mkHReg(13, HRcFlt64, False); } -+//ZZ HReg hregARM_S26 ( void ) { return mkHReg(26, HRcFlt32, False); } -+//ZZ HReg hregARM_S27 ( void ) { return mkHReg(27, HRcFlt32, False); } -+//ZZ HReg hregARM_S28 ( void ) { return mkHReg(28, HRcFlt32, False); } -+//ZZ HReg hregARM_S29 ( void ) { return mkHReg(29, HRcFlt32, False); } -+//ZZ HReg hregARM_S30 ( void ) { return mkHReg(30, HRcFlt32, False); } -+HReg hregARM64_Q16 ( void ) { return mkHReg(16, HRcVec128, False); } -+HReg hregARM64_Q17 ( void ) { return mkHReg(17, HRcVec128, False); } -+HReg hregARM64_Q18 ( void ) { return mkHReg(18, HRcVec128, False); } -+//ZZ HReg hregARM_Q11 ( void ) { return mkHReg(11, HRcVec128, False); } -+//ZZ HReg hregARM_Q12 ( void ) { return mkHReg(12, HRcVec128, False); } -+//ZZ HReg hregARM_Q13 ( void ) { return mkHReg(13, HRcVec128, False); } -+//ZZ HReg hregARM_Q14 ( void ) { return mkHReg(14, HRcVec128, False); } -+//ZZ HReg hregARM_Q15 ( void ) { return mkHReg(15, HRcVec128, False); } -+ -+void getAllocableRegs_ARM64 ( Int* nregs, HReg** arr ) -+{ -+ Int i = 0; -+ *nregs = 24; -+ *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); -+ -+ // callee saves ones (22 to 28) are listed first, since we prefer -+ // them if they're available -+ (*arr)[i++] = hregARM64_X22(); -+ (*arr)[i++] = hregARM64_X23(); -+ (*arr)[i++] = hregARM64_X24(); -+ (*arr)[i++] = hregARM64_X25(); -+ (*arr)[i++] = hregARM64_X26(); -+ (*arr)[i++] = hregARM64_X27(); -+ (*arr)[i++] = hregARM64_X28(); -+ -+ (*arr)[i++] = hregARM64_X0(); -+ (*arr)[i++] = hregARM64_X1(); -+ (*arr)[i++] = hregARM64_X2(); -+ (*arr)[i++] = hregARM64_X3(); -+ (*arr)[i++] = hregARM64_X4(); -+ (*arr)[i++] = hregARM64_X5(); -+ (*arr)[i++] = hregARM64_X6(); -+ (*arr)[i++] = hregARM64_X7(); -+ // X8 .. who knows. -+ // X9 is a chaining/spill temporary, not available to regalloc. -+ -+ // Do we really need all these? -+ //(*arr)[i++] = hregARM64_X10(); -+ //(*arr)[i++] = hregARM64_X11(); -+ //(*arr)[i++] = hregARM64_X12(); -+ //(*arr)[i++] = hregARM64_X13(); -+ //(*arr)[i++] = hregARM64_X14(); -+ //(*arr)[i++] = hregARM64_X15(); -+ // X21 is the guest state pointer, not available to regalloc. -+ -+ // vector regs. Unfortunately not callee-saved. -+ (*arr)[i++] = hregARM64_Q16(); -+ (*arr)[i++] = hregARM64_Q17(); -+ (*arr)[i++] = hregARM64_Q18(); -+ -+ // F64 regs, all of which are callee-saved -+ (*arr)[i++] = hregARM64_D8(); -+ (*arr)[i++] = hregARM64_D9(); -+ (*arr)[i++] = hregARM64_D10(); -+ (*arr)[i++] = hregARM64_D11(); -+ (*arr)[i++] = hregARM64_D12(); -+ (*arr)[i++] = hregARM64_D13(); -+ -+ // unavail: x21 as GSP -+ // x9 is used as a spill/reload/chaining/call temporary -+ // x8 is unassigned -+ // x30 as LR -+ // x31 because dealing with the SP-vs-ZR overloading is too -+ // confusing, and we don't need to do so, so let's just avoid -+ // the problem -+ // -+ // Currently, we have 15 allocatable integer registers: -+ // 0 1 2 3 4 5 6 7 22 23 24 25 26 27 28 -+ // -+ // Hence for the allocatable integer registers we have: -+ // -+ // callee-saved: 22 23 24 25 26 27 28 -+ // caller-saved: 0 1 2 3 4 5 6 7 -+ // -+ // If the set of available registers changes or if the e/r status -+ // changes, be sure to re-check/sync the definition of -+ // getHRegUsage for ARMInstr_Call too. -+ vassert(i == *nregs); -+} -+ -+ -+ -+/* --------- Condition codes, ARM64 encoding. --------- */ -+ -+static const HChar* showARM64CondCode ( ARM64CondCode cond ) { -+ switch (cond) { -+ case ARM64cc_EQ: return "eq"; -+ case ARM64cc_NE: return "ne"; -+ case ARM64cc_CS: return "cs"; -+ case ARM64cc_CC: return "cc"; -+ case ARM64cc_MI: return "mi"; -+ case ARM64cc_PL: return "pl"; -+ case ARM64cc_VS: return "vs"; -+ case ARM64cc_VC: return "vc"; -+ case ARM64cc_HI: return "hi"; -+ case ARM64cc_LS: return "ls"; -+ case ARM64cc_GE: return "ge"; -+ case ARM64cc_LT: return "lt"; -+ case ARM64cc_GT: return "gt"; -+ case ARM64cc_LE: return "le"; -+ case ARM64cc_AL: return "al"; // default -+ case ARM64cc_NV: return "nv"; -+ default: vpanic("showARM64CondCode"); -+ } -+} -+ -+ -+/* --------- Memory address expressions (amodes). --------- */ -+ -+ARM64AMode* ARM64AMode_RI9 ( HReg reg, Int simm9 ) { -+ ARM64AMode* am = LibVEX_Alloc(sizeof(ARM64AMode)); -+ am->tag = ARM64am_RI9; -+ am->ARM64am.RI9.reg = reg; -+ am->ARM64am.RI9.simm9 = simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ return am; -+} -+ -+ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB ) { -+ ARM64AMode* am = LibVEX_Alloc(sizeof(ARM64AMode)); -+ am->tag = ARM64am_RI12; -+ am->ARM64am.RI12.reg = reg; -+ am->ARM64am.RI12.uimm12 = uimm12; -+ am->ARM64am.RI12.szB = szB; -+ vassert(uimm12 >= 0 && uimm12 <= 4095); -+ switch (szB) { -+ case 1: case 2: case 4: case 8: break; -+ default: vassert(0); -+ } -+ return am; -+} -+ -+ARM64AMode* ARM64AMode_RR ( HReg base, HReg index ) { -+ ARM64AMode* am = LibVEX_Alloc(sizeof(ARM64AMode)); -+ am->tag = ARM64am_RR; -+ am->ARM64am.RR.base = base; -+ am->ARM64am.RR.index = index; -+ return am; -+} -+ -+static void ppARM64AMode ( ARM64AMode* am ) { -+ switch (am->tag) { -+ case ARM64am_RI9: -+ vex_printf("%d(", am->ARM64am.RI9.simm9); -+ ppHRegARM64(am->ARM64am.RI9.reg); -+ vex_printf(")"); -+ break; -+ case ARM64am_RI12: -+ vex_printf("%u(", (UInt)am->ARM64am.RI12.szB -+ * (UInt)am->ARM64am.RI12.uimm12); -+ ppHRegARM64(am->ARM64am.RI12.reg); -+ vex_printf(")"); -+ break; -+ case ARM64am_RR: -+ vex_printf("("); -+ ppHRegARM64(am->ARM64am.RR.base); -+ vex_printf(","); -+ ppHRegARM64(am->ARM64am.RR.index); -+ vex_printf(")"); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64AMode ( HRegUsage* u, ARM64AMode* am ) { -+ switch (am->tag) { -+ case ARM64am_RI9: -+ addHRegUse(u, HRmRead, am->ARM64am.RI9.reg); -+ return; -+ case ARM64am_RI12: -+ addHRegUse(u, HRmRead, am->ARM64am.RI12.reg); -+ return; -+ case ARM64am_RR: -+ addHRegUse(u, HRmRead, am->ARM64am.RR.base); -+ addHRegUse(u, HRmRead, am->ARM64am.RR.index); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64Amode"); -+ } -+} -+ -+static void mapRegs_ARM64AMode ( HRegRemap* m, ARM64AMode* am ) { -+ switch (am->tag) { -+ case ARM64am_RI9: -+ am->ARM64am.RI9.reg = lookupHRegRemap(m, am->ARM64am.RI9.reg); -+ return; -+ case ARM64am_RI12: -+ am->ARM64am.RI12.reg = lookupHRegRemap(m, am->ARM64am.RI12.reg); -+ return; -+ case ARM64am_RR: -+ am->ARM64am.RR.base = lookupHRegRemap(m, am->ARM64am.RR.base); -+ am->ARM64am.RR.index = lookupHRegRemap(m, am->ARM64am.RR.index); -+ return; -+ default: -+ vpanic("mapRegs_ARM64Amode"); -+ } -+} -+ -+ -+//ZZ /* --------- Mem AModes: Addressing Mode 2 --------- */ -+//ZZ -+//ZZ ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 ) { -+//ZZ ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); -+//ZZ am->tag = ARMam2_RI; -+//ZZ am->ARMam2.RI.reg = reg; -+//ZZ am->ARMam2.RI.simm9 = simm9; -+//ZZ vassert(-255 <= simm9 && simm9 <= 255); -+//ZZ return am; -+//ZZ } -+//ZZ ARMAMode2* ARMAMode2_RR ( HReg base, HReg index ) { -+//ZZ ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); -+//ZZ am->tag = ARMam2_RR; -+//ZZ am->ARMam2.RR.base = base; -+//ZZ am->ARMam2.RR.index = index; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ void ppARMAMode2 ( ARMAMode2* am ) { -+//ZZ switch (am->tag) { -+//ZZ case ARMam2_RI: -+//ZZ vex_printf("%d(", am->ARMam2.RI.simm9); -+//ZZ ppHRegARM(am->ARMam2.RI.reg); -+//ZZ vex_printf(")"); -+//ZZ break; -+//ZZ case ARMam2_RR: -+//ZZ vex_printf("("); -+//ZZ ppHRegARM(am->ARMam2.RR.base); -+//ZZ vex_printf(","); -+//ZZ ppHRegARM(am->ARMam2.RR.index); -+//ZZ vex_printf(")"); -+//ZZ break; -+//ZZ default: -+//ZZ vassert(0); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void addRegUsage_ARMAMode2 ( HRegUsage* u, ARMAMode2* am ) { -+//ZZ switch (am->tag) { -+//ZZ case ARMam2_RI: -+//ZZ addHRegUse(u, HRmRead, am->ARMam2.RI.reg); -+//ZZ return; -+//ZZ case ARMam2_RR: -+//ZZ // addHRegUse(u, HRmRead, am->ARMam2.RR.base); -+//ZZ // addHRegUse(u, HRmRead, am->ARMam2.RR.index); -+//ZZ // return; -+//ZZ default: -+//ZZ vpanic("addRegUsage_ARMAmode2"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void mapRegs_ARMAMode2 ( HRegRemap* m, ARMAMode2* am ) { -+//ZZ switch (am->tag) { -+//ZZ case ARMam2_RI: -+//ZZ am->ARMam2.RI.reg = lookupHRegRemap(m, am->ARMam2.RI.reg); -+//ZZ return; -+//ZZ case ARMam2_RR: -+//ZZ //am->ARMam2.RR.base =lookupHRegRemap(m, am->ARMam2.RR.base); -+//ZZ //am->ARMam2.RR.index = lookupHRegRemap(m, am->ARMam2.RR.index); -+//ZZ //return; -+//ZZ default: -+//ZZ vpanic("mapRegs_ARMAmode2"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* --------- Mem AModes: Addressing Mode VFP --------- */ -+//ZZ -+//ZZ ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 ) { -+//ZZ ARMAModeV* am = LibVEX_Alloc(sizeof(ARMAModeV)); -+//ZZ vassert(simm11 >= -1020 && simm11 <= 1020); -+//ZZ vassert(0 == (simm11 & 3)); -+//ZZ am->reg = reg; -+//ZZ am->simm11 = simm11; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ void ppARMAModeV ( ARMAModeV* am ) { -+//ZZ vex_printf("%d(", am->simm11); -+//ZZ ppHRegARM(am->reg); -+//ZZ vex_printf(")"); -+//ZZ } -+//ZZ -+//ZZ static void addRegUsage_ARMAModeV ( HRegUsage* u, ARMAModeV* am ) { -+//ZZ addHRegUse(u, HRmRead, am->reg); -+//ZZ } -+//ZZ -+//ZZ static void mapRegs_ARMAModeV ( HRegRemap* m, ARMAModeV* am ) { -+//ZZ am->reg = lookupHRegRemap(m, am->reg); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* --------- Mem AModes: Addressing Mode Neon ------- */ -+//ZZ -+//ZZ ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { -+//ZZ ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN)); -+//ZZ am->tag = ARMamN_RR; -+//ZZ am->ARMamN.RR.rN = rN; -+//ZZ am->ARMamN.RR.rM = rM; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ ARMAModeN *mkARMAModeN_R ( HReg rN ) { -+//ZZ ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN)); -+//ZZ am->tag = ARMamN_R; -+//ZZ am->ARMamN.R.rN = rN; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ static void addRegUsage_ARMAModeN ( HRegUsage* u, ARMAModeN* am ) { -+//ZZ if (am->tag == ARMamN_R) { -+//ZZ addHRegUse(u, HRmRead, am->ARMamN.R.rN); -+//ZZ } else { -+//ZZ addHRegUse(u, HRmRead, am->ARMamN.RR.rN); -+//ZZ addHRegUse(u, HRmRead, am->ARMamN.RR.rM); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void mapRegs_ARMAModeN ( HRegRemap* m, ARMAModeN* am ) { -+//ZZ if (am->tag == ARMamN_R) { -+//ZZ am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN); -+//ZZ } else { -+//ZZ am->ARMamN.RR.rN = lookupHRegRemap(m, am->ARMamN.RR.rN); -+//ZZ am->ARMamN.RR.rM = lookupHRegRemap(m, am->ARMamN.RR.rM); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ void ppARMAModeN ( ARMAModeN* am ) { -+//ZZ vex_printf("["); -+//ZZ if (am->tag == ARMamN_R) { -+//ZZ ppHRegARM(am->ARMamN.R.rN); -+//ZZ } else { -+//ZZ ppHRegARM(am->ARMamN.RR.rN); -+//ZZ } -+//ZZ vex_printf("]"); -+//ZZ if (am->tag == ARMamN_RR) { -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(am->ARMamN.RR.rM); -+//ZZ } -+//ZZ } -+ -+ -+/* --------- Reg or uimm12<<{0,12} operands --------- */ -+ -+ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ) { -+ ARM64RIA* riA = LibVEX_Alloc(sizeof(ARM64RIA)); -+ riA->tag = ARM64riA_I12; -+ riA->ARM64riA.I12.imm12 = imm12; -+ riA->ARM64riA.I12.shift = shift; -+ vassert(imm12 < 4096); -+ vassert(shift == 0 || shift == 12); -+ return riA; -+} -+ARM64RIA* ARM64RIA_R ( HReg reg ) { -+ ARM64RIA* riA = LibVEX_Alloc(sizeof(ARM64RIA)); -+ riA->tag = ARM64riA_R; -+ riA->ARM64riA.R.reg = reg; -+ return riA; -+} -+ -+static void ppARM64RIA ( ARM64RIA* riA ) { -+ switch (riA->tag) { -+ case ARM64riA_I12: -+ vex_printf("#%u",(UInt)(riA->ARM64riA.I12.imm12 -+ << riA->ARM64riA.I12.shift)); -+ break; -+ case ARM64riA_R: -+ ppHRegARM64(riA->ARM64riA.R.reg); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64RIA ( HRegUsage* u, ARM64RIA* riA ) { -+ switch (riA->tag) { -+ case ARM64riA_I12: -+ return; -+ case ARM64riA_R: -+ addHRegUse(u, HRmRead, riA->ARM64riA.R.reg); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64RIA"); -+ } -+} -+ -+static void mapRegs_ARM64RIA ( HRegRemap* m, ARM64RIA* riA ) { -+ switch (riA->tag) { -+ case ARM64riA_I12: -+ return; -+ case ARM64riA_R: -+ riA->ARM64riA.R.reg = lookupHRegRemap(m, riA->ARM64riA.R.reg); -+ return; -+ default: -+ vpanic("mapRegs_ARM64RIA"); -+ } -+} -+ -+ -+/* --------- Reg or "bitfield" (logic immediate) operands --------- */ -+ -+ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS ) { -+ ARM64RIL* riL = LibVEX_Alloc(sizeof(ARM64RIL)); -+ riL->tag = ARM64riL_I13; -+ riL->ARM64riL.I13.bitN = bitN; -+ riL->ARM64riL.I13.immR = immR; -+ riL->ARM64riL.I13.immS = immS; -+ vassert(bitN < 2); -+ vassert(immR < 64); -+ vassert(immS < 64); -+ return riL; -+} -+ARM64RIL* ARM64RIL_R ( HReg reg ) { -+ ARM64RIL* riL = LibVEX_Alloc(sizeof(ARM64RIL)); -+ riL->tag = ARM64riL_R; -+ riL->ARM64riL.R.reg = reg; -+ return riL; -+} -+ -+static void ppARM64RIL ( ARM64RIL* riL ) { -+ switch (riL->tag) { -+ case ARM64riL_I13: -+ vex_printf("#nrs(%u,%u,%u)", -+ (UInt)riL->ARM64riL.I13.bitN, -+ (UInt)riL->ARM64riL.I13.immR, -+ (UInt)riL->ARM64riL.I13.immS); -+ break; -+ case ARM64riL_R: -+ ppHRegARM64(riL->ARM64riL.R.reg); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64RIL ( HRegUsage* u, ARM64RIL* riL ) { -+ switch (riL->tag) { -+ case ARM64riL_I13: -+ return; -+ case ARM64riL_R: -+ addHRegUse(u, HRmRead, riL->ARM64riL.R.reg); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64RIL"); -+ } -+} -+ -+static void mapRegs_ARM64RIL ( HRegRemap* m, ARM64RIL* riL ) { -+ switch (riL->tag) { -+ case ARM64riL_I13: -+ return; -+ case ARM64riL_R: -+ riL->ARM64riL.R.reg = lookupHRegRemap(m, riL->ARM64riL.R.reg); -+ return; -+ default: -+ vpanic("mapRegs_ARM64RIL"); -+ } -+} -+ -+ -+/* --------------- Reg or uimm6 operands --------------- */ -+ -+ARM64RI6* ARM64RI6_I6 ( UInt imm6 ) { -+ ARM64RI6* ri6 = LibVEX_Alloc(sizeof(ARM64RI6)); -+ ri6->tag = ARM64ri6_I6; -+ ri6->ARM64ri6.I6.imm6 = imm6; -+ vassert(imm6 > 0 && imm6 < 64); -+ return ri6; -+} -+ARM64RI6* ARM64RI6_R ( HReg reg ) { -+ ARM64RI6* ri6 = LibVEX_Alloc(sizeof(ARM64RI6)); -+ ri6->tag = ARM64ri6_R; -+ ri6->ARM64ri6.R.reg = reg; -+ return ri6; -+} -+ -+static void ppARM64RI6 ( ARM64RI6* ri6 ) { -+ switch (ri6->tag) { -+ case ARM64ri6_I6: -+ vex_printf("#%u", ri6->ARM64ri6.I6.imm6); -+ break; -+ case ARM64ri6_R: -+ ppHRegARM64(ri6->ARM64ri6.R.reg); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64RI6 ( HRegUsage* u, ARM64RI6* ri6 ) { -+ switch (ri6->tag) { -+ case ARM64ri6_I6: -+ return; -+ case ARM64ri6_R: -+ addHRegUse(u, HRmRead, ri6->ARM64ri6.R.reg); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64RI6"); -+ } -+} -+ -+static void mapRegs_ARM64RI6 ( HRegRemap* m, ARM64RI6* ri6 ) { -+ switch (ri6->tag) { -+ case ARM64ri6_I6: -+ return; -+ case ARM64ri6_R: -+ ri6->ARM64ri6.R.reg = lookupHRegRemap(m, ri6->ARM64ri6.R.reg); -+ return; -+ default: -+ vpanic("mapRegs_ARM64RI6"); -+ } -+} -+ -+ -+//ZZ /* -------- Neon Immediate operatnd --------- */ -+//ZZ -+//ZZ ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 ) { -+//ZZ ARMNImm* i = LibVEX_Alloc(sizeof(ARMNImm)); -+//ZZ i->type = type; -+//ZZ i->imm8 = imm8; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ULong ARMNImm_to_Imm64 ( ARMNImm* imm ) { -+//ZZ int i, j; -+//ZZ ULong y, x = imm->imm8; -+//ZZ switch (imm->type) { -+//ZZ case 3: -+//ZZ x = x << 8; /* fallthrough */ -+//ZZ case 2: -+//ZZ x = x << 8; /* fallthrough */ -+//ZZ case 1: -+//ZZ x = x << 8; /* fallthrough */ -+//ZZ case 0: -+//ZZ return (x << 32) | x; -+//ZZ case 5: -+//ZZ case 6: -+//ZZ if (imm->type == 5) -+//ZZ x = x << 8; -+//ZZ else -+//ZZ x = (x << 8) | x; -+//ZZ /* fallthrough */ -+//ZZ case 4: -+//ZZ x = (x << 16) | x; -+//ZZ return (x << 32) | x; -+//ZZ case 8: -+//ZZ x = (x << 8) | 0xFF; -+//ZZ /* fallthrough */ -+//ZZ case 7: -+//ZZ x = (x << 8) | 0xFF; -+//ZZ return (x << 32) | x; -+//ZZ case 9: -+//ZZ x = 0; -+//ZZ for (i = 7; i >= 0; i--) { -+//ZZ y = ((ULong)imm->imm8 >> i) & 1; -+//ZZ for (j = 0; j < 8; j++) { -+//ZZ x = (x << 1) | y; -+//ZZ } -+//ZZ } -+//ZZ return x; -+//ZZ case 10: -+//ZZ x |= (x & 0x80) << 5; -+//ZZ x |= (~x & 0x40) << 5; -+//ZZ x &= 0x187F; /* 0001 1000 0111 1111 */ -+//ZZ x |= (x & 0x40) << 4; -+//ZZ x |= (x & 0x40) << 3; -+//ZZ x |= (x & 0x40) << 2; -+//ZZ x |= (x & 0x40) << 1; -+//ZZ x = x << 19; -+//ZZ x = (x << 32) | x; -+//ZZ return x; -+//ZZ default: -+//ZZ vpanic("ARMNImm_to_Imm64"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ ARMNImm* Imm64_to_ARMNImm ( ULong x ) { -+//ZZ ARMNImm tmp; -+//ZZ if ((x & 0xFFFFFFFF) == (x >> 32)) { -+//ZZ if ((x & 0xFFFFFF00) == 0) -+//ZZ return ARMNImm_TI(0, x & 0xFF); -+//ZZ if ((x & 0xFFFF00FF) == 0) -+//ZZ return ARMNImm_TI(1, (x >> 8) & 0xFF); -+//ZZ if ((x & 0xFF00FFFF) == 0) -+//ZZ return ARMNImm_TI(2, (x >> 16) & 0xFF); -+//ZZ if ((x & 0x00FFFFFF) == 0) -+//ZZ return ARMNImm_TI(3, (x >> 24) & 0xFF); -+//ZZ if ((x & 0xFFFF00FF) == 0xFF) -+//ZZ return ARMNImm_TI(7, (x >> 8) & 0xFF); -+//ZZ if ((x & 0xFF00FFFF) == 0xFFFF) -+//ZZ return ARMNImm_TI(8, (x >> 16) & 0xFF); -+//ZZ if ((x & 0xFFFF) == ((x >> 16) & 0xFFFF)) { -+//ZZ if ((x & 0xFF00) == 0) -+//ZZ return ARMNImm_TI(4, x & 0xFF); -+//ZZ if ((x & 0x00FF) == 0) -+//ZZ return ARMNImm_TI(5, (x >> 8) & 0xFF); -+//ZZ if ((x & 0xFF) == ((x >> 8) & 0xFF)) -+//ZZ return ARMNImm_TI(6, x & 0xFF); -+//ZZ } -+//ZZ if ((x & 0x7FFFF) == 0) { -+//ZZ tmp.type = 10; -+//ZZ tmp.imm8 = ((x >> 19) & 0x7F) | ((x >> 24) & 0x80); -+//ZZ if (ARMNImm_to_Imm64(&tmp) == x) -+//ZZ return ARMNImm_TI(tmp.type, tmp.imm8); -+//ZZ } -+//ZZ } else { -+//ZZ /* This can only be type 9. */ -+//ZZ tmp.imm8 = (((x >> 56) & 1) << 7) -+//ZZ | (((x >> 48) & 1) << 6) -+//ZZ | (((x >> 40) & 1) << 5) -+//ZZ | (((x >> 32) & 1) << 4) -+//ZZ | (((x >> 24) & 1) << 3) -+//ZZ | (((x >> 16) & 1) << 2) -+//ZZ | (((x >> 8) & 1) << 1) -+//ZZ | (((x >> 0) & 1) << 0); -+//ZZ tmp.type = 9; -+//ZZ if (ARMNImm_to_Imm64 (&tmp) == x) -+//ZZ return ARMNImm_TI(tmp.type, tmp.imm8); -+//ZZ } -+//ZZ return NULL; -+//ZZ } -+//ZZ -+//ZZ void ppARMNImm (ARMNImm* i) { -+//ZZ ULong x = ARMNImm_to_Imm64(i); -+//ZZ vex_printf("0x%llX%llX", x, x); -+//ZZ } -+//ZZ -+//ZZ /* -- Register or scalar operand --- */ -+//ZZ -+//ZZ ARMNRS* mkARMNRS(ARMNRS_tag tag, HReg reg, UInt index) -+//ZZ { -+//ZZ ARMNRS *p = LibVEX_Alloc(sizeof(ARMNRS)); -+//ZZ p->tag = tag; -+//ZZ p->reg = reg; -+//ZZ p->index = index; -+//ZZ return p; -+//ZZ } -+//ZZ -+//ZZ void ppARMNRS(ARMNRS *p) -+//ZZ { -+//ZZ ppHRegARM(p->reg); -+//ZZ if (p->tag == ARMNRS_Scalar) { -+//ZZ vex_printf("[%d]", p->index); -+//ZZ } -+//ZZ } -+ -+/* --------- Instructions. --------- */ -+ -+static const HChar* showARM64LogicOp ( ARM64LogicOp op ) { -+ switch (op) { -+ case ARM64lo_AND: return "and"; -+ case ARM64lo_OR: return "orr"; -+ case ARM64lo_XOR: return "eor"; -+ default: vpanic("showARM64LogicOp"); -+ } -+} -+ -+static const HChar* showARM64ShiftOp ( ARM64ShiftOp op ) { -+ switch (op) { -+ case ARM64sh_SHL: return "lsl"; -+ case ARM64sh_SHR: return "lsr"; -+ case ARM64sh_SAR: return "asr"; -+ default: vpanic("showARM64ShiftOp"); -+ } -+} -+ -+static const HChar* showARM64UnaryOp ( ARM64UnaryOp op ) { -+ switch (op) { -+ case ARM64un_NEG: return "neg"; -+ case ARM64un_NOT: return "not"; -+ case ARM64un_CLZ: return "clz"; -+ default: vpanic("showARM64UnaryOp"); -+ } -+} -+ -+static const HChar* showARM64MulOp ( ARM64MulOp op ) { -+ switch (op) { -+ case ARM64mul_PLAIN: return "mul "; -+ case ARM64mul_ZX: return "umulh"; -+ case ARM64mul_SX: return "smulh"; -+ default: vpanic("showARM64MulOp"); -+ } -+} -+ -+static void characteriseARM64CvtOp ( /*OUT*/HChar* syn, -+ /*OUT*/UInt* fszB, /*OUT*/UInt* iszB, -+ ARM64CvtOp op ) { -+ switch (op) { -+ case ARM64cvt_F32_I32S: -+ *syn = 's'; *fszB = 4; *iszB = 4; break; -+ case ARM64cvt_F64_I32S: -+ *syn = 's'; *fszB = 8; *iszB = 4; break; -+ case ARM64cvt_F32_I64S: -+ *syn = 's'; *fszB = 4; *iszB = 8; break; -+ case ARM64cvt_F64_I64S: -+ *syn = 's'; *fszB = 8; *iszB = 8; break; -+ case ARM64cvt_F32_I32U: -+ *syn = 'u'; *fszB = 4; *iszB = 4; break; -+ case ARM64cvt_F64_I32U: -+ *syn = 'u'; *fszB = 8; *iszB = 4; break; -+ case ARM64cvt_F32_I64U: -+ *syn = 'u'; *fszB = 4; *iszB = 8; break; -+ case ARM64cvt_F64_I64U: -+ *syn = 'u'; *fszB = 8; *iszB = 8; break; -+ default: -+ vpanic("characteriseARM64CvtOp"); -+ } -+} -+ -+static const HChar* showARM64FpBinOp ( ARM64FpBinOp op ) { -+ switch (op) { -+ case ARM64fpb_ADD: return "add"; -+ case ARM64fpb_SUB: return "sub"; -+ case ARM64fpb_MUL: return "mul"; -+ case ARM64fpb_DIV: return "div"; -+ default: vpanic("showARM64FpBinOp"); -+ } -+} -+ -+static const HChar* showARM64FpUnaryOp ( ARM64FpUnaryOp op ) { -+ switch (op) { -+ case ARM64fpu_NEG: return "neg "; -+ case ARM64fpu_ABS: return "abs "; -+ case ARM64fpu_SQRT: return "sqrt "; -+ case ARM64fpu_RINT: return "rinti"; -+ default: vpanic("showARM64FpUnaryOp"); -+ } -+} -+ -+//ZZ const HChar* showARMNeonBinOp ( ARMNeonBinOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VAND: return "vand"; -+//ZZ case ARMneon_VORR: return "vorr"; -+//ZZ case ARMneon_VXOR: return "veor"; -+//ZZ case ARMneon_VADD: return "vadd"; -+//ZZ case ARMneon_VRHADDS: return "vrhadd"; -+//ZZ case ARMneon_VRHADDU: return "vrhadd"; -+//ZZ case ARMneon_VADDFP: return "vadd"; -+//ZZ case ARMneon_VPADDFP: return "vpadd"; -+//ZZ case ARMneon_VABDFP: return "vabd"; -+//ZZ case ARMneon_VSUB: return "vsub"; -+//ZZ case ARMneon_VSUBFP: return "vsub"; -+//ZZ case ARMneon_VMINU: return "vmin"; -+//ZZ case ARMneon_VMINS: return "vmin"; -+//ZZ case ARMneon_VMINF: return "vmin"; -+//ZZ case ARMneon_VMAXU: return "vmax"; -+//ZZ case ARMneon_VMAXS: return "vmax"; -+//ZZ case ARMneon_VMAXF: return "vmax"; -+//ZZ case ARMneon_VQADDU: return "vqadd"; -+//ZZ case ARMneon_VQADDS: return "vqadd"; -+//ZZ case ARMneon_VQSUBU: return "vqsub"; -+//ZZ case ARMneon_VQSUBS: return "vqsub"; -+//ZZ case ARMneon_VCGTU: return "vcgt"; -+//ZZ case ARMneon_VCGTS: return "vcgt"; -+//ZZ case ARMneon_VCGTF: return "vcgt"; -+//ZZ case ARMneon_VCGEF: return "vcgt"; -+//ZZ case ARMneon_VCGEU: return "vcge"; -+//ZZ case ARMneon_VCGES: return "vcge"; -+//ZZ case ARMneon_VCEQ: return "vceq"; -+//ZZ case ARMneon_VCEQF: return "vceq"; -+//ZZ case ARMneon_VPADD: return "vpadd"; -+//ZZ case ARMneon_VPMINU: return "vpmin"; -+//ZZ case ARMneon_VPMINS: return "vpmin"; -+//ZZ case ARMneon_VPMINF: return "vpmin"; -+//ZZ case ARMneon_VPMAXU: return "vpmax"; -+//ZZ case ARMneon_VPMAXS: return "vpmax"; -+//ZZ case ARMneon_VPMAXF: return "vpmax"; -+//ZZ case ARMneon_VEXT: return "vext"; -+//ZZ case ARMneon_VMUL: return "vmuli"; -+//ZZ case ARMneon_VMULLU: return "vmull"; -+//ZZ case ARMneon_VMULLS: return "vmull"; -+//ZZ case ARMneon_VMULP: return "vmul"; -+//ZZ case ARMneon_VMULFP: return "vmul"; -+//ZZ case ARMneon_VMULLP: return "vmul"; -+//ZZ case ARMneon_VQDMULH: return "vqdmulh"; -+//ZZ case ARMneon_VQRDMULH: return "vqrdmulh"; -+//ZZ case ARMneon_VQDMULL: return "vqdmull"; -+//ZZ case ARMneon_VTBL: return "vtbl"; -+//ZZ case ARMneon_VRECPS: return "vrecps"; -+//ZZ case ARMneon_VRSQRTS: return "vrecps"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonBinOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VAND: -+//ZZ case ARMneon_VORR: -+//ZZ case ARMneon_VXOR: -+//ZZ return ""; -+//ZZ case ARMneon_VADD: -+//ZZ case ARMneon_VSUB: -+//ZZ case ARMneon_VEXT: -+//ZZ case ARMneon_VMUL: -+//ZZ case ARMneon_VPADD: -+//ZZ case ARMneon_VTBL: -+//ZZ case ARMneon_VCEQ: -+//ZZ return ".i"; -+//ZZ case ARMneon_VRHADDU: -+//ZZ case ARMneon_VMINU: -+//ZZ case ARMneon_VMAXU: -+//ZZ case ARMneon_VQADDU: -+//ZZ case ARMneon_VQSUBU: -+//ZZ case ARMneon_VCGTU: -+//ZZ case ARMneon_VCGEU: -+//ZZ case ARMneon_VMULLU: -+//ZZ case ARMneon_VPMINU: -+//ZZ case ARMneon_VPMAXU: -+//ZZ return ".u"; -+//ZZ case ARMneon_VRHADDS: -+//ZZ case ARMneon_VMINS: -+//ZZ case ARMneon_VMAXS: -+//ZZ case ARMneon_VQADDS: -+//ZZ case ARMneon_VQSUBS: -+//ZZ case ARMneon_VCGTS: -+//ZZ case ARMneon_VCGES: -+//ZZ case ARMneon_VQDMULL: -+//ZZ case ARMneon_VMULLS: -+//ZZ case ARMneon_VPMINS: -+//ZZ case ARMneon_VPMAXS: -+//ZZ case ARMneon_VQDMULH: -+//ZZ case ARMneon_VQRDMULH: -+//ZZ return ".s"; -+//ZZ case ARMneon_VMULP: -+//ZZ case ARMneon_VMULLP: -+//ZZ return ".p"; -+//ZZ case ARMneon_VADDFP: -+//ZZ case ARMneon_VABDFP: -+//ZZ case ARMneon_VPADDFP: -+//ZZ case ARMneon_VSUBFP: -+//ZZ case ARMneon_VMULFP: -+//ZZ case ARMneon_VMINF: -+//ZZ case ARMneon_VMAXF: -+//ZZ case ARMneon_VPMINF: -+//ZZ case ARMneon_VPMAXF: -+//ZZ case ARMneon_VCGTF: -+//ZZ case ARMneon_VCGEF: -+//ZZ case ARMneon_VCEQF: -+//ZZ case ARMneon_VRECPS: -+//ZZ case ARMneon_VRSQRTS: -+//ZZ return ".f"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonBinOpDataType"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOp ( ARMNeonUnOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_COPY: return "vmov"; -+//ZZ case ARMneon_COPYLS: return "vmov"; -+//ZZ case ARMneon_COPYLU: return "vmov"; -+//ZZ case ARMneon_COPYN: return "vmov"; -+//ZZ case ARMneon_COPYQNSS: return "vqmovn"; -+//ZZ case ARMneon_COPYQNUS: return "vqmovun"; -+//ZZ case ARMneon_COPYQNUU: return "vqmovn"; -+//ZZ case ARMneon_NOT: return "vmvn"; -+//ZZ case ARMneon_EQZ: return "vceq"; -+//ZZ case ARMneon_CNT: return "vcnt"; -+//ZZ case ARMneon_CLS: return "vcls"; -+//ZZ case ARMneon_CLZ: return "vclz"; -+//ZZ case ARMneon_DUP: return "vdup"; -+//ZZ case ARMneon_PADDLS: return "vpaddl"; -+//ZZ case ARMneon_PADDLU: return "vpaddl"; -+//ZZ case ARMneon_VQSHLNSS: return "vqshl"; -+//ZZ case ARMneon_VQSHLNUU: return "vqshl"; -+//ZZ case ARMneon_VQSHLNUS: return "vqshlu"; -+//ZZ case ARMneon_REV16: return "vrev16"; -+//ZZ case ARMneon_REV32: return "vrev32"; -+//ZZ case ARMneon_REV64: return "vrev64"; -+//ZZ case ARMneon_VCVTFtoU: return "vcvt"; -+//ZZ case ARMneon_VCVTFtoS: return "vcvt"; -+//ZZ case ARMneon_VCVTUtoF: return "vcvt"; -+//ZZ case ARMneon_VCVTStoF: return "vcvt"; -+//ZZ case ARMneon_VCVTFtoFixedU: return "vcvt"; -+//ZZ case ARMneon_VCVTFtoFixedS: return "vcvt"; -+//ZZ case ARMneon_VCVTFixedUtoF: return "vcvt"; -+//ZZ case ARMneon_VCVTFixedStoF: return "vcvt"; -+//ZZ case ARMneon_VCVTF32toF16: return "vcvt"; -+//ZZ case ARMneon_VCVTF16toF32: return "vcvt"; -+//ZZ case ARMneon_VRECIP: return "vrecip"; -+//ZZ case ARMneon_VRECIPF: return "vrecipf"; -+//ZZ case ARMneon_VNEGF: return "vneg"; -+//ZZ case ARMneon_ABS: return "vabs"; -+//ZZ case ARMneon_VABSFP: return "vabsfp"; -+//ZZ case ARMneon_VRSQRTEFP: return "vrsqrtefp"; -+//ZZ case ARMneon_VRSQRTE: return "vrsqrte"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_COPY: -+//ZZ case ARMneon_NOT: -+//ZZ return ""; -+//ZZ case ARMneon_COPYN: -+//ZZ case ARMneon_EQZ: -+//ZZ case ARMneon_CNT: -+//ZZ case ARMneon_DUP: -+//ZZ case ARMneon_REV16: -+//ZZ case ARMneon_REV32: -+//ZZ case ARMneon_REV64: -+//ZZ return ".i"; -+//ZZ case ARMneon_COPYLU: -+//ZZ case ARMneon_PADDLU: -+//ZZ case ARMneon_COPYQNUU: -+//ZZ case ARMneon_VQSHLNUU: -+//ZZ case ARMneon_VRECIP: -+//ZZ case ARMneon_VRSQRTE: -+//ZZ return ".u"; -+//ZZ case ARMneon_CLS: -+//ZZ case ARMneon_CLZ: -+//ZZ case ARMneon_COPYLS: -+//ZZ case ARMneon_PADDLS: -+//ZZ case ARMneon_COPYQNSS: -+//ZZ case ARMneon_COPYQNUS: -+//ZZ case ARMneon_VQSHLNSS: -+//ZZ case ARMneon_VQSHLNUS: -+//ZZ case ARMneon_ABS: -+//ZZ return ".s"; -+//ZZ case ARMneon_VRECIPF: -+//ZZ case ARMneon_VNEGF: -+//ZZ case ARMneon_VABSFP: -+//ZZ case ARMneon_VRSQRTEFP: -+//ZZ return ".f"; -+//ZZ case ARMneon_VCVTFtoU: return ".u32.f32"; -+//ZZ case ARMneon_VCVTFtoS: return ".s32.f32"; -+//ZZ case ARMneon_VCVTUtoF: return ".f32.u32"; -+//ZZ case ARMneon_VCVTStoF: return ".f32.s32"; -+//ZZ case ARMneon_VCVTF16toF32: return ".f32.f16"; -+//ZZ case ARMneon_VCVTF32toF16: return ".f16.f32"; -+//ZZ case ARMneon_VCVTFtoFixedU: return ".u32.f32"; -+//ZZ case ARMneon_VCVTFtoFixedS: return ".s32.f32"; -+//ZZ case ARMneon_VCVTFixedUtoF: return ".f32.u32"; -+//ZZ case ARMneon_VCVTFixedStoF: return ".f32.s32"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnOpDataType"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_SETELEM: return "vmov"; -+//ZZ case ARMneon_GETELEMU: return "vmov"; -+//ZZ case ARMneon_GETELEMS: return "vmov"; -+//ZZ case ARMneon_VDUP: return "vdup"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnarySOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_SETELEM: -+//ZZ case ARMneon_VDUP: -+//ZZ return ".i"; -+//ZZ case ARMneon_GETELEMS: -+//ZZ return ".s"; -+//ZZ case ARMneon_GETELEMU: -+//ZZ return ".u"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnarySOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VSHL: return "vshl"; -+//ZZ case ARMneon_VSAL: return "vshl"; -+//ZZ case ARMneon_VQSHL: return "vqshl"; -+//ZZ case ARMneon_VQSAL: return "vqshl"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonShiftOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VSHL: -+//ZZ case ARMneon_VQSHL: -+//ZZ return ".u"; -+//ZZ case ARMneon_VSAL: -+//ZZ case ARMneon_VQSAL: -+//ZZ return ".s"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonShiftOpDataType"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonDualOp ( ARMNeonDualOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_TRN: return "vtrn"; -+//ZZ case ARMneon_ZIP: return "vzip"; -+//ZZ case ARMneon_UZP: return "vuzp"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonDualOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_TRN: -+//ZZ case ARMneon_ZIP: -+//ZZ case ARMneon_UZP: -+//ZZ return "i"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonDualOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static const HChar* showARMNeonDataSize_wrk ( UInt size ) -+//ZZ { -+//ZZ switch (size) { -+//ZZ case 0: return "8"; -+//ZZ case 1: return "16"; -+//ZZ case 2: return "32"; -+//ZZ case 3: return "64"; -+//ZZ default: vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static const HChar* showARMNeonDataSize ( ARMInstr* i ) -+//ZZ { -+//ZZ switch (i->tag) { -+//ZZ case ARMin_NBinary: -+//ZZ if (i->ARMin.NBinary.op == ARMneon_VEXT) -+//ZZ return "8"; -+//ZZ if (i->ARMin.NBinary.op == ARMneon_VAND || -+//ZZ i->ARMin.NBinary.op == ARMneon_VORR || -+//ZZ i->ARMin.NBinary.op == ARMneon_VXOR) -+//ZZ return ""; -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NBinary.size); -+//ZZ case ARMin_NUnary: -+//ZZ if (i->ARMin.NUnary.op == ARMneon_COPY || -+//ZZ i->ARMin.NUnary.op == ARMneon_NOT || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTF32toF16|| -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTF16toF32|| -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTStoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTUtoF) -+//ZZ return ""; -+//ZZ if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUS) { -+//ZZ UInt size; -+//ZZ size = i->ARMin.NUnary.size; -+//ZZ if (size & 0x40) -+//ZZ return "64"; -+//ZZ if (size & 0x20) -+//ZZ return "32"; -+//ZZ if (size & 0x10) -+//ZZ return "16"; -+//ZZ if (size & 0x08) -+//ZZ return "8"; -+//ZZ vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NUnary.size); -+//ZZ case ARMin_NUnaryS: -+//ZZ if (i->ARMin.NUnaryS.op == ARMneon_VDUP) { -+//ZZ int size; -+//ZZ size = i->ARMin.NUnaryS.size; -+//ZZ if ((size & 1) == 1) -+//ZZ return "8"; -+//ZZ if ((size & 3) == 2) -+//ZZ return "16"; -+//ZZ if ((size & 7) == 4) -+//ZZ return "32"; -+//ZZ vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NUnaryS.size); -+//ZZ case ARMin_NShift: -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NShift.size); -+//ZZ case ARMin_NDual: -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NDual.size); -+//ZZ default: -+//ZZ vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ } -+ -+ARM64Instr* ARM64Instr_Arith ( HReg dst, -+ HReg argL, ARM64RIA* argR, Bool isAdd ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Arith; -+ i->ARM64in.Arith.dst = dst; -+ i->ARM64in.Arith.argL = argL; -+ i->ARM64in.Arith.argR = argR; -+ i->ARM64in.Arith.isAdd = isAdd; -+ return i; -+} -+ARM64Instr* ARM64Instr_Cmp ( HReg argL, ARM64RIA* argR, Bool is64 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Cmp; -+ i->ARM64in.Cmp.argL = argL; -+ i->ARM64in.Cmp.argR = argR; -+ i->ARM64in.Cmp.is64 = is64; -+ return i; -+} -+ARM64Instr* ARM64Instr_Logic ( HReg dst, -+ HReg argL, ARM64RIL* argR, ARM64LogicOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Logic; -+ i->ARM64in.Logic.dst = dst; -+ i->ARM64in.Logic.argL = argL; -+ i->ARM64in.Logic.argR = argR; -+ i->ARM64in.Logic.op = op; -+ return i; -+} -+ARM64Instr* ARM64Instr_Test ( HReg argL, ARM64RIL* argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Test; -+ i->ARM64in.Test.argL = argL; -+ i->ARM64in.Test.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_Shift ( HReg dst, -+ HReg argL, ARM64RI6* argR, ARM64ShiftOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Shift; -+ i->ARM64in.Shift.dst = dst; -+ i->ARM64in.Shift.argL = argL; -+ i->ARM64in.Shift.argR = argR; -+ i->ARM64in.Shift.op = op; -+ return i; -+} -+ARM64Instr* ARM64Instr_Unary ( HReg dst, HReg src, ARM64UnaryOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Unary; -+ i->ARM64in.Unary.dst = dst; -+ i->ARM64in.Unary.src = src; -+ i->ARM64in.Unary.op = op; -+ return i; -+} -+ARM64Instr* ARM64Instr_MovI ( HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_MovI; -+ i->ARM64in.MovI.dst = dst; -+ i->ARM64in.MovI.src = src; -+ vassert(hregClass(src) == HRcInt64); -+ vassert(hregClass(dst) == HRcInt64); -+ return i; -+} -+ARM64Instr* ARM64Instr_Imm64 ( HReg dst, ULong imm64 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Imm64; -+ i->ARM64in.Imm64.dst = dst; -+ i->ARM64in.Imm64.imm64 = imm64; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt64; -+ i->ARM64in.LdSt64.isLoad = isLoad; -+ i->ARM64in.LdSt64.rD = rD; -+ i->ARM64in.LdSt64.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt32; -+ i->ARM64in.LdSt32.isLoad = isLoad; -+ i->ARM64in.LdSt32.rD = rD; -+ i->ARM64in.LdSt32.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt16; -+ i->ARM64in.LdSt16.isLoad = isLoad; -+ i->ARM64in.LdSt16.rD = rD; -+ i->ARM64in.LdSt16.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt8; -+ i->ARM64in.LdSt8.isLoad = isLoad; -+ i->ARM64in.LdSt8.rD = rD; -+ i->ARM64in.LdSt8.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, Bool toFastEP ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_XDirect; -+ i->ARM64in.XDirect.dstGA = dstGA; -+ i->ARM64in.XDirect.amPC = amPC; -+ i->ARM64in.XDirect.cond = cond; -+ i->ARM64in.XDirect.toFastEP = toFastEP; -+ return i; -+} -+ARM64Instr* ARM64Instr_XIndir ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_XIndir; -+ i->ARM64in.XIndir.dstGA = dstGA; -+ i->ARM64in.XIndir.amPC = amPC; -+ i->ARM64in.XIndir.cond = cond; -+ return i; -+} -+ARM64Instr* ARM64Instr_XAssisted ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, IRJumpKind jk ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_XAssisted; -+ i->ARM64in.XAssisted.dstGA = dstGA; -+ i->ARM64in.XAssisted.amPC = amPC; -+ i->ARM64in.XAssisted.cond = cond; -+ i->ARM64in.XAssisted.jk = jk; -+ return i; -+} -+ARM64Instr* ARM64Instr_CSel ( HReg dst, HReg argL, HReg argR, -+ ARM64CondCode cond ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_CSel; -+ i->ARM64in.CSel.dst = dst; -+ i->ARM64in.CSel.argL = argL; -+ i->ARM64in.CSel.argR = argR; -+ i->ARM64in.CSel.cond = cond; -+ return i; -+} -+ARM64Instr* ARM64Instr_Call ( ARM64CondCode cond, HWord target, Int nArgRegs, -+ RetLoc rloc ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Call; -+ i->ARM64in.Call.cond = cond; -+ i->ARM64in.Call.target = target; -+ i->ARM64in.Call.nArgRegs = nArgRegs; -+ i->ARM64in.Call.rloc = rloc; -+ vassert(is_sane_RetLoc(rloc)); -+ return i; -+} -+extern ARM64Instr* ARM64Instr_AddToSP ( Int simm ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_AddToSP; -+ i->ARM64in.AddToSP.simm = simm; -+ vassert(-4096 < simm && simm < 4096); -+ vassert(0 == (simm & 0xF)); -+ return i; -+} -+extern ARM64Instr* ARM64Instr_FromSP ( HReg dst ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_FromSP; -+ i->ARM64in.FromSP.dst = dst; -+ return i; -+} -+ARM64Instr* ARM64Instr_Mul ( HReg dst, HReg argL, HReg argR, -+ ARM64MulOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Mul; -+ i->ARM64in.Mul.dst = dst; -+ i->ARM64in.Mul.argL = argL; -+ i->ARM64in.Mul.argR = argR; -+ i->ARM64in.Mul.op = op; -+ return i; -+} -+//ZZ ARMInstr* ARMInstr_Mul ( ARMMulOp op ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_Mul; -+//ZZ i->ARMin.Mul.op = op; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_LdrEX ( Int szB ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_LdrEX; -+//ZZ i->ARMin.LdrEX.szB = szB; -+//ZZ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_StrEX ( Int szB ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_StrEX; -+//ZZ i->ARMin.StrEX.szB = szB; -+//ZZ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); -+//ZZ return i; -+//ZZ } -+ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VLdStS; -+ i->ARM64in.VLdStS.isLoad = isLoad; -+ i->ARM64in.VLdStS.sD = sD; -+ i->ARM64in.VLdStS.rN = rN; -+ i->ARM64in.VLdStS.uimm12 = uimm12; -+ vassert(uimm12 < 16384 && 0 == (uimm12 & 3)); -+ return i; -+} -+ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, UInt uimm12 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VLdStD; -+ i->ARM64in.VLdStD.isLoad = isLoad; -+ i->ARM64in.VLdStD.dD = dD; -+ i->ARM64in.VLdStD.rN = rN; -+ i->ARM64in.VLdStD.uimm12 = uimm12; -+ vassert(uimm12 < 32768 && 0 == (uimm12 & 7)); -+ return i; -+} -+ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VLdStQ; -+ i->ARM64in.VLdStQ.isLoad = isLoad; -+ i->ARM64in.VLdStQ.rQ = rQ; -+ i->ARM64in.VLdStQ.rN = rN; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCvtI2F; -+ i->ARM64in.VCvtI2F.how = how; -+ i->ARM64in.VCvtI2F.rD = rD; -+ i->ARM64in.VCvtI2F.rS = rS; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS, -+ UChar armRM ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCvtF2I; -+ i->ARM64in.VCvtF2I.how = how; -+ i->ARM64in.VCvtF2I.rD = rD; -+ i->ARM64in.VCvtF2I.rS = rS; -+ i->ARM64in.VCvtF2I.armRM = armRM; -+ vassert(armRM <= 3); -+ return i; -+} -+ARM64Instr* ARM64Instr_VCvtSD ( Bool sToD, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCvtSD; -+ i->ARM64in.VCvtSD.sToD = sToD; -+ i->ARM64in.VCvtSD.dst = dst; -+ i->ARM64in.VCvtSD.src = src; -+ return i; -+} -+ARM64Instr* ARM64Instr_VUnaryD ( ARM64FpUnaryOp op, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VUnaryD; -+ i->ARM64in.VUnaryD.op = op; -+ i->ARM64in.VUnaryD.dst = dst; -+ i->ARM64in.VUnaryD.src = src; -+ return i; -+} -+ARM64Instr* ARM64Instr_VUnaryS ( ARM64FpUnaryOp op, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VUnaryS; -+ i->ARM64in.VUnaryS.op = op; -+ i->ARM64in.VUnaryS.dst = dst; -+ i->ARM64in.VUnaryS.src = src; -+ return i; -+} -+ARM64Instr* ARM64Instr_VBinD ( ARM64FpBinOp op, -+ HReg dst, HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VBinD; -+ i->ARM64in.VBinD.op = op; -+ i->ARM64in.VBinD.dst = dst; -+ i->ARM64in.VBinD.argL = argL; -+ i->ARM64in.VBinD.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_VBinS ( ARM64FpBinOp op, -+ HReg dst, HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VBinS; -+ i->ARM64in.VBinS.op = op; -+ i->ARM64in.VBinS.dst = dst; -+ i->ARM64in.VBinS.argL = argL; -+ i->ARM64in.VBinS.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCmpD ( HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCmpD; -+ i->ARM64in.VCmpD.argL = argL; -+ i->ARM64in.VCmpD.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCmpS ( HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCmpS; -+ i->ARM64in.VCmpS.argL = argL; -+ i->ARM64in.VCmpS.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_FPCR ( Bool toFPCR, HReg iReg ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_FPCR; -+ i->ARM64in.FPCR.toFPCR = toFPCR; -+ i->ARM64in.FPCR.iReg = iReg; -+ return i; -+} -+//ZZ ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg dst, HReg argL, HReg argR ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VAluS; -+//ZZ i->ARMin.VAluS.op = op; -+//ZZ i->ARMin.VAluS.dst = dst; -+//ZZ i->ARMin.VAluS.argL = argL; -+//ZZ i->ARMin.VAluS.argR = argR; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VCMovD ( ARMCondCode cond, HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VCMovD; -+//ZZ i->ARMin.VCMovD.cond = cond; -+//ZZ i->ARMin.VCMovD.dst = dst; -+//ZZ i->ARMin.VCMovD.src = src; -+//ZZ vassert(cond != ARMcc_AL); -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VCMovS ( ARMCondCode cond, HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VCMovS; -+//ZZ i->ARMin.VCMovS.cond = cond; -+//ZZ i->ARMin.VCMovS.dst = dst; -+//ZZ i->ARMin.VCMovS.src = src; -+//ZZ vassert(cond != ARMcc_AL); -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VXferD; -+//ZZ i->ARMin.VXferD.toD = toD; -+//ZZ i->ARMin.VXferD.dD = dD; -+//ZZ i->ARMin.VXferD.rHi = rHi; -+//ZZ i->ARMin.VXferD.rLo = rLo; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VXferS; -+//ZZ i->ARMin.VXferS.toS = toS; -+//ZZ i->ARMin.VXferS.fD = fD; -+//ZZ i->ARMin.VXferS.rLo = rLo; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned, -+//ZZ HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VCvtID; -+//ZZ i->ARMin.VCvtID.iToD = iToD; -+//ZZ i->ARMin.VCvtID.syned = syned; -+//ZZ i->ARMin.VCvtID.dst = dst; -+//ZZ i->ARMin.VCvtID.src = src; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_MFence ( void ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_MFence; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_CLREX( void ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_CLREX; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg dD, ARMAModeN *amode ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NLdStD; -+//ZZ i->ARMin.NLdStD.isLoad = isLoad; -+//ZZ i->ARMin.NLdStD.dD = dD; -+//ZZ i->ARMin.NLdStD.amode = amode; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp op, HReg dQ, HReg nQ, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NUnary; -+//ZZ i->ARMin.NUnary.op = op; -+//ZZ i->ARMin.NUnary.src = nQ; -+//ZZ i->ARMin.NUnary.dst = dQ; -+//ZZ i->ARMin.NUnary.size = size; -+//ZZ i->ARMin.NUnary.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS op, ARMNRS* dst, ARMNRS* src, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NUnaryS; -+//ZZ i->ARMin.NUnaryS.op = op; -+//ZZ i->ARMin.NUnaryS.src = src; -+//ZZ i->ARMin.NUnaryS.dst = dst; -+//ZZ i->ARMin.NUnaryS.size = size; -+//ZZ i->ARMin.NUnaryS.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NDual ( ARMNeonDualOp op, HReg nQ, HReg mQ, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NDual; -+//ZZ i->ARMin.NDual.op = op; -+//ZZ i->ARMin.NDual.arg1 = nQ; -+//ZZ i->ARMin.NDual.arg2 = mQ; -+//ZZ i->ARMin.NDual.size = size; -+//ZZ i->ARMin.NDual.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp op, -+//ZZ HReg dst, HReg argL, HReg argR, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NBinary; -+//ZZ i->ARMin.NBinary.op = op; -+//ZZ i->ARMin.NBinary.argL = argL; -+//ZZ i->ARMin.NBinary.argR = argR; -+//ZZ i->ARMin.NBinary.dst = dst; -+//ZZ i->ARMin.NBinary.size = size; -+//ZZ i->ARMin.NBinary.Q = Q; -+//ZZ return i; -+//ZZ } -+ -+ARM64Instr* ARM64Instr_VImmQ (HReg rQ, UShort imm) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VImmQ; -+ i->ARM64in.VImmQ.rQ = rQ; -+ i->ARM64in.VImmQ.imm = imm; -+ return i; -+} -+ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VDfromX; -+ i->ARM64in.VDfromX.rD = rD; -+ i->ARM64in.VDfromX.rX = rX; -+ return i; -+} -+ARM64Instr* ARM64Instr_VQfromXX ( HReg rQ, HReg rXhi, HReg rXlo ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VQfromXX; -+ i->ARM64in.VQfromXX.rQ = rQ; -+ i->ARM64in.VQfromXX.rXhi = rXhi; -+ i->ARM64in.VQfromXX.rXlo = rXlo; -+ return i; -+} -+ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VXfromQ; -+ i->ARM64in.VXfromQ.rX = rX; -+ i->ARM64in.VXfromQ.rQ = rQ; -+ i->ARM64in.VXfromQ.laneNo = laneNo; -+ vassert(laneNo <= 1); -+ return i; -+} -+ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VMov; -+ i->ARM64in.VMov.szB = szB; -+ i->ARM64in.VMov.dst = dst; -+ i->ARM64in.VMov.src = src; -+ switch (szB) { -+ case 16: -+ vassert(hregClass(src) == HRcVec128); -+ vassert(hregClass(dst) == HRcVec128); -+ break; -+ case 8: -+ vassert(hregClass(src) == HRcFlt64); -+ vassert(hregClass(dst) == HRcFlt64); -+ break; -+ default: -+ vpanic("ARM64Instr_VMov"); -+ } -+ return i; -+} -+ -+//ZZ ARMInstr* ARMInstr_NCMovQ ( ARMCondCode cond, HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NCMovQ; -+//ZZ i->ARMin.NCMovQ.cond = cond; -+//ZZ i->ARMin.NCMovQ.dst = dst; -+//ZZ i->ARMin.NCMovQ.src = src; -+//ZZ vassert(cond != ARMcc_AL); -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp op, -+//ZZ HReg dst, HReg argL, HReg argR, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NShift; -+//ZZ i->ARMin.NShift.op = op; -+//ZZ i->ARMin.NShift.argL = argL; -+//ZZ i->ARMin.NShift.argR = argR; -+//ZZ i->ARMin.NShift.dst = dst; -+//ZZ i->ARMin.NShift.size = size; -+//ZZ i->ARMin.NShift.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NShl64 ( HReg dst, HReg src, UInt amt ) -+//ZZ { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NShl64; -+//ZZ i->ARMin.NShl64.dst = dst; -+//ZZ i->ARMin.NShl64.src = src; -+//ZZ i->ARMin.NShl64.amt = amt; -+//ZZ vassert(amt >= 1 && amt <= 63); -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ /* Helper copy-pasted from isel.c */ -+//ZZ static Bool fitsIn8x4 ( UInt* u8, UInt* u4, UInt u ) -+//ZZ { -+//ZZ UInt i; -+//ZZ for (i = 0; i < 16; i++) { -+//ZZ if (0 == (u & 0xFFFFFF00)) { -+//ZZ *u8 = u; -+//ZZ *u4 = i; -+//ZZ return True; -+//ZZ } -+//ZZ u = ROR32(u, 30); -+//ZZ } -+//ZZ vassert(i == 16); -+//ZZ return False; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) { -+//ZZ UInt u8, u4; -+//ZZ ARMInstr *i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ /* Try to generate single ADD if possible */ -+//ZZ if (fitsIn8x4(&u8, &u4, imm32)) { -+//ZZ i->tag = ARMin_Alu; -+//ZZ i->ARMin.Alu.op = ARMalu_ADD; -+//ZZ i->ARMin.Alu.dst = rD; -+//ZZ i->ARMin.Alu.argL = rN; -+//ZZ i->ARMin.Alu.argR = ARMRI84_I84(u8, u4); -+//ZZ } else { -+//ZZ i->tag = ARMin_Add32; -+//ZZ i->ARMin.Add32.rD = rD; -+//ZZ i->ARMin.Add32.rN = rN; -+//ZZ i->ARMin.Add32.imm32 = imm32; -+//ZZ } -+//ZZ return i; -+//ZZ } -+ -+ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter, -+ ARM64AMode* amFailAddr ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_EvCheck; -+ i->ARM64in.EvCheck.amCounter = amCounter; -+ i->ARM64in.EvCheck.amFailAddr = amFailAddr; -+ return i; -+} -+ -+//ZZ ARMInstr* ARMInstr_ProfInc ( void ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_ProfInc; -+//ZZ return i; -+//ZZ } -+ -+/* ... */ -+ -+void ppARM64Instr ( ARM64Instr* i ) { -+ switch (i->tag) { -+ case ARM64in_Arith: -+ vex_printf("%s ", i->ARM64in.Arith.isAdd ? "add" : "sub"); -+ ppHRegARM64(i->ARM64in.Arith.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Arith.argL); -+ vex_printf(", "); -+ ppARM64RIA(i->ARM64in.Arith.argR); -+ return; -+ case ARM64in_Cmp: -+ vex_printf("cmp%s ", i->ARM64in.Cmp.is64 ? " " : "(w)" ); -+ ppHRegARM64(i->ARM64in.Cmp.argL); -+ vex_printf(", "); -+ ppARM64RIA(i->ARM64in.Cmp.argR); -+ return; -+ case ARM64in_Logic: -+ vex_printf("%s ", showARM64LogicOp(i->ARM64in.Logic.op)); -+ ppHRegARM64(i->ARM64in.Logic.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Logic.argL); -+ vex_printf(", "); -+ ppARM64RIL(i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Test: -+ vex_printf("tst "); -+ ppHRegARM64(i->ARM64in.Test.argL); -+ vex_printf(", "); -+ ppARM64RIL(i->ARM64in.Test.argR); -+ return; -+ case ARM64in_Shift: -+ vex_printf("%s ", showARM64ShiftOp(i->ARM64in.Shift.op)); -+ ppHRegARM64(i->ARM64in.Shift.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Shift.argL); -+ vex_printf(", "); -+ ppARM64RI6(i->ARM64in.Shift.argR); -+ return; -+ case ARM64in_Unary: -+ vex_printf("%s ", showARM64UnaryOp(i->ARM64in.Unary.op)); -+ ppHRegARM64(i->ARM64in.Unary.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Unary.src); -+ return; -+ case ARM64in_MovI: -+ vex_printf("mov "); -+ ppHRegARM64(i->ARM64in.MovI.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.MovI.src); -+ return; -+ case ARM64in_Imm64: -+ vex_printf("imm64 "); -+ ppHRegARM64(i->ARM64in.Imm64.dst); -+ vex_printf(", 0x%llx", i->ARM64in.Imm64.imm64); -+ return; -+ case ARM64in_LdSt64: -+ if (i->ARM64in.LdSt64.isLoad) { -+ vex_printf("ldr "); -+ ppHRegARM64(i->ARM64in.LdSt64.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt64.amode); -+ } else { -+ vex_printf("str "); -+ ppARM64AMode(i->ARM64in.LdSt64.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt64.rD); -+ } -+ return; -+ case ARM64in_LdSt32: -+ if (i->ARM64in.LdSt32.isLoad) { -+ vex_printf("ldruw "); -+ ppHRegARM64(i->ARM64in.LdSt32.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt32.amode); -+ } else { -+ vex_printf("strw "); -+ ppARM64AMode(i->ARM64in.LdSt32.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt32.rD); -+ } -+ return; -+ case ARM64in_LdSt16: -+ if (i->ARM64in.LdSt16.isLoad) { -+ vex_printf("ldruh "); -+ ppHRegARM64(i->ARM64in.LdSt16.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt16.amode); -+ } else { -+ vex_printf("strh "); -+ ppARM64AMode(i->ARM64in.LdSt16.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt16.rD); -+ } -+ return; -+ case ARM64in_LdSt8: -+ if (i->ARM64in.LdSt8.isLoad) { -+ vex_printf("ldrub "); -+ ppHRegARM64(i->ARM64in.LdSt8.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt8.amode); -+ } else { -+ vex_printf("strb "); -+ ppARM64AMode(i->ARM64in.LdSt8.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt8.rD); -+ } -+ return; -+ case ARM64in_XDirect: -+ vex_printf("(xDirect) "); -+ vex_printf("if (%%pstate.%s) { ", -+ showARM64CondCode(i->ARM64in.XDirect.cond)); -+ vex_printf("imm64 x9,0x%llx; ", i->ARM64in.XDirect.dstGA); -+ vex_printf("str x9,"); -+ ppARM64AMode(i->ARM64in.XDirect.amPC); -+ vex_printf("; imm64-exactly4 x9,$disp_cp_chain_me_to_%sEP; ", -+ i->ARM64in.XDirect.toFastEP ? "fast" : "slow"); -+ vex_printf("blr x9 }"); -+ return; -+ case ARM64in_XIndir: -+ vex_printf("(xIndir) "); -+ vex_printf("if (%%pstate.%s) { ", -+ showARM64CondCode(i->ARM64in.XIndir.cond)); -+ vex_printf("str "); -+ ppHRegARM64(i->ARM64in.XIndir.dstGA); -+ vex_printf(","); -+ ppARM64AMode(i->ARM64in.XIndir.amPC); -+ vex_printf("; imm64 x9,$disp_cp_xindir; "); -+ vex_printf("br x9 }"); -+ return; -+ case ARM64in_XAssisted: -+ vex_printf("(xAssisted) "); -+ vex_printf("if (%%pstate.%s) { ", -+ showARM64CondCode(i->ARM64in.XAssisted.cond)); -+ vex_printf("str "); -+ ppHRegARM64(i->ARM64in.XAssisted.dstGA); -+ vex_printf(","); -+ ppARM64AMode(i->ARM64in.XAssisted.amPC); -+ vex_printf("; movw x21,$IRJumpKind_to_TRCVAL(%d); ", -+ (Int)i->ARM64in.XAssisted.jk); -+ vex_printf("imm64 x9,$disp_cp_xassisted; "); -+ vex_printf("br x9 }"); -+ return; -+ case ARM64in_CSel: -+ vex_printf("csel "); -+ ppHRegARM64(i->ARM64in.CSel.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.CSel.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.CSel.argR); -+ vex_printf(", %s", showARM64CondCode(i->ARM64in.CSel.cond)); -+ return; -+ case ARM64in_Call: -+ vex_printf("call%s ", -+ i->ARM64in.Call.cond==ARM64cc_AL -+ ? " " : showARM64CondCode(i->ARM64in.Call.cond)); -+ vex_printf("0x%lx [nArgRegs=%d, ", -+ i->ARM64in.Call.target, i->ARM64in.Call.nArgRegs); -+ ppRetLoc(i->ARM64in.Call.rloc); -+ vex_printf("]"); -+ return; -+ case ARM64in_AddToSP: { -+ Int simm = i->ARM64in.AddToSP.simm; -+ vex_printf("%s xsp, xsp, #%d", simm < 0 ? "sub" : "add", -+ simm < 0 ? -simm : simm); -+ return; -+ } -+ case ARM64in_FromSP: -+ vex_printf("mov "); -+ ppHRegARM64(i->ARM64in.FromSP.dst); -+ vex_printf(", xsp"); -+ return; -+ case ARM64in_Mul: -+ vex_printf("%s ", showARM64MulOp(i->ARM64in.Mul.op)); -+ ppHRegARM64(i->ARM64in.Mul.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Mul.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Mul.argR); -+ return; -+//ZZ case ARMin_LdrEX: { -+//ZZ const HChar* sz = ""; -+//ZZ switch (i->ARMin.LdrEX.szB) { -+//ZZ case 1: sz = "b"; break; case 2: sz = "h"; break; -+//ZZ case 8: sz = "d"; break; case 4: break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ vex_printf("ldrex%s %sr2, [r4]", -+//ZZ sz, i->ARMin.LdrEX.szB == 8 ? "r3:" : ""); -+//ZZ return; -+//ZZ } -+//ZZ case ARMin_StrEX: { -+//ZZ const HChar* sz = ""; -+//ZZ switch (i->ARMin.StrEX.szB) { -+//ZZ case 1: sz = "b"; break; case 2: sz = "h"; break; -+//ZZ case 8: sz = "d"; break; case 4: break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ vex_printf("strex%s r0, %sr2, [r4]", -+//ZZ sz, i->ARMin.StrEX.szB == 8 ? "r3:" : ""); -+//ZZ return; -+//ZZ } -+ case ARM64in_VLdStS: -+ if (i->ARM64in.VLdStS.isLoad) { -+ vex_printf("ldr "); -+ ppHRegARM64asSreg(i->ARM64in.VLdStS.sD); -+ vex_printf(", %u(", i->ARM64in.VLdStS.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStS.rN); -+ vex_printf(")"); -+ } else { -+ vex_printf("str "); -+ vex_printf("%u(", i->ARM64in.VLdStS.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStS.rN); -+ vex_printf("), "); -+ ppHRegARM64asSreg(i->ARM64in.VLdStS.sD); -+ } -+ return; -+ case ARM64in_VLdStD: -+ if (i->ARM64in.VLdStD.isLoad) { -+ vex_printf("ldr "); -+ ppHRegARM64(i->ARM64in.VLdStD.dD); -+ vex_printf(", %u(", i->ARM64in.VLdStD.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStD.rN); -+ vex_printf(")"); -+ } else { -+ vex_printf("str "); -+ vex_printf("%u(", i->ARM64in.VLdStD.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStD.rN); -+ vex_printf("), "); -+ ppHRegARM64(i->ARM64in.VLdStD.dD); -+ } -+ return; -+ case ARM64in_VLdStQ: -+ if (i->ARM64in.VLdStQ.isLoad) -+ vex_printf("ld1.2d {"); -+ else -+ vex_printf("st1.2d {"); -+ ppHRegARM64(i->ARM64in.VLdStQ.rQ); -+ vex_printf("}, ["); -+ ppHRegARM64(i->ARM64in.VLdStQ.rN); -+ vex_printf("]"); -+ return; -+ case ARM64in_VCvtI2F: { -+ HChar syn = '?'; -+ UInt fszB = 0; -+ UInt iszB = 0; -+ characteriseARM64CvtOp(&syn, &fszB, &iszB, i->ARM64in.VCvtI2F.how); -+ vex_printf("%ccvtf ", syn); -+ ppHRegARM64(i->ARM64in.VCvtI2F.rD); -+ vex_printf("(%c-reg), ", fszB == 4 ? 'S' : 'D'); -+ ppHRegARM64(i->ARM64in.VCvtI2F.rS); -+ vex_printf("(%c-reg)", iszB == 4 ? 'W' : 'X'); -+ return; -+ } -+ case ARM64in_VCvtF2I: { -+ HChar syn = '?'; -+ UInt fszB = 0; -+ UInt iszB = 0; -+ HChar rmo = '?'; -+ characteriseARM64CvtOp(&syn, &fszB, &iszB, i->ARM64in.VCvtF2I.how); -+ UChar armRM = i->ARM64in.VCvtF2I.armRM; -+ if (armRM < 4) rmo = "npmz"[armRM]; -+ vex_printf("fcvt%c%c ", rmo, syn); -+ ppHRegARM64(i->ARM64in.VCvtF2I.rD); -+ vex_printf("(%c-reg), ", iszB == 4 ? 'W' : 'X'); -+ ppHRegARM64(i->ARM64in.VCvtF2I.rS); -+ vex_printf("(%c-reg)", fszB == 4 ? 'S' : 'D'); -+ return; -+ } -+ case ARM64in_VCvtSD: -+ vex_printf("fcvt%s ", i->ARM64in.VCvtSD.sToD ? "s2d" : "d2s"); -+ if (i->ARM64in.VCvtSD.sToD) { -+ ppHRegARM64(i->ARM64in.VCvtSD.dst); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VCvtSD.src); -+ } else { -+ ppHRegARM64asSreg(i->ARM64in.VCvtSD.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VCvtSD.src); -+ } -+ return; -+ case ARM64in_VUnaryD: -+ vex_printf("f%s ", showARM64FpUnaryOp(i->ARM64in.VUnaryD.op)); -+ ppHRegARM64(i->ARM64in.VUnaryD.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VUnaryD.src); -+ return; -+ case ARM64in_VUnaryS: -+ vex_printf("f%s ", showARM64FpUnaryOp(i->ARM64in.VUnaryS.op)); -+ ppHRegARM64asSreg(i->ARM64in.VUnaryS.dst); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VUnaryS.src); -+ return; -+ case ARM64in_VBinD: -+ vex_printf("f%s ", showARM64FpBinOp(i->ARM64in.VBinD.op)); -+ ppHRegARM64(i->ARM64in.VBinD.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VBinD.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VBinD.argR); -+ return; -+ case ARM64in_VBinS: -+ vex_printf("f%s ", showARM64FpBinOp(i->ARM64in.VBinS.op)); -+ ppHRegARM64asSreg(i->ARM64in.VBinS.dst); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VBinS.argL); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VBinS.argR); -+ return; -+ case ARM64in_VCmpD: -+ vex_printf("fcmp "); -+ ppHRegARM64(i->ARM64in.VCmpD.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VCmpD.argR); -+ return; -+ case ARM64in_VCmpS: -+ vex_printf("fcmp "); -+ ppHRegARM64asSreg(i->ARM64in.VCmpS.argL); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VCmpS.argR); -+ return; -+ case ARM64in_FPCR: -+ if (i->ARM64in.FPCR.toFPCR) { -+ vex_printf("msr fpcr, "); -+ ppHRegARM64(i->ARM64in.FPCR.iReg); -+ } else { -+ vex_printf("mrs "); -+ ppHRegARM64(i->ARM64in.FPCR.iReg); -+ vex_printf(", fpcr"); -+ } -+ return; -+//ZZ case ARMin_VAluS: -+//ZZ vex_printf("f%-3ss ", showARMVfpOp(i->ARMin.VAluS.op)); -+//ZZ ppHRegARM(i->ARMin.VAluS.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VAluS.argL); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VAluS.argR); -+//ZZ return; -+//ZZ case ARMin_VCMovD: -+//ZZ vex_printf("fcpyd%s ", showARMCondCode(i->ARMin.VCMovD.cond)); -+//ZZ ppHRegARM(i->ARMin.VCMovD.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VCMovD.src); -+//ZZ return; -+//ZZ case ARMin_VCMovS: -+//ZZ vex_printf("fcpys%s ", showARMCondCode(i->ARMin.VCMovS.cond)); -+//ZZ ppHRegARM(i->ARMin.VCMovS.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VCMovS.src); -+//ZZ return; -+//ZZ case ARMin_VXferD: -+//ZZ vex_printf("vmov "); -+//ZZ if (i->ARMin.VXferD.toD) { -+//ZZ ppHRegARM(i->ARMin.VXferD.dD); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.rLo); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.rHi); -+//ZZ } else { -+//ZZ ppHRegARM(i->ARMin.VXferD.rLo); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.rHi); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.dD); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VXferS: -+//ZZ vex_printf("vmov "); -+//ZZ if (i->ARMin.VXferS.toS) { -+//ZZ ppHRegARM(i->ARMin.VXferS.fD); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferS.rLo); -+//ZZ } else { -+//ZZ ppHRegARM(i->ARMin.VXferS.rLo); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferS.fD); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VCvtID: { -+//ZZ const HChar* nm = "?"; -+//ZZ if (i->ARMin.VCvtID.iToD) { -+//ZZ nm = i->ARMin.VCvtID.syned ? "fsitod" : "fuitod"; -+//ZZ } else { -+//ZZ nm = i->ARMin.VCvtID.syned ? "ftosid" : "ftouid"; -+//ZZ } -+//ZZ vex_printf("%s ", nm); -+//ZZ ppHRegARM(i->ARMin.VCvtID.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VCvtID.src); -+//ZZ return; -+//ZZ } -+//ZZ case ARMin_MFence: -+//ZZ vex_printf("(mfence) dsb sy; dmb sy; isb"); -+//ZZ return; -+//ZZ case ARMin_CLREX: -+//ZZ vex_printf("clrex"); -+//ZZ return; -+//ZZ case ARMin_NLdStD: -+//ZZ if (i->ARMin.NLdStD.isLoad) -+//ZZ vex_printf("vld1.32 {"); -+//ZZ else -+//ZZ vex_printf("vst1.32 {"); -+//ZZ ppHRegARM(i->ARMin.NLdStD.dD); -+//ZZ vex_printf("} "); -+//ZZ ppARMAModeN(i->ARMin.NLdStD.amode); -+//ZZ return; -+//ZZ case ARMin_NUnary: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonUnOp(i->ARMin.NUnary.op), -+//ZZ showARMNeonUnOpDataType(i->ARMin.NUnary.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppHRegARM(i->ARMin.NUnary.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NUnary.src); -+//ZZ if (i->ARMin.NUnary.op == ARMneon_EQZ) -+//ZZ vex_printf(", #0"); -+//ZZ if (i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF) { -+//ZZ vex_printf(", #%d", i->ARMin.NUnary.size); -+//ZZ } -+//ZZ if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUS) { -+//ZZ UInt size; -+//ZZ size = i->ARMin.NUnary.size; -+//ZZ if (size & 0x40) { -+//ZZ vex_printf(", #%d", size - 64); -+//ZZ } else if (size & 0x20) { -+//ZZ vex_printf(", #%d", size - 32); -+//ZZ } else if (size & 0x10) { -+//ZZ vex_printf(", #%d", size - 16); -+//ZZ } else if (size & 0x08) { -+//ZZ vex_printf(", #%d", size - 8); -+//ZZ } -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_NUnaryS: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonUnOpS(i->ARMin.NUnaryS.op), -+//ZZ showARMNeonUnOpSDataType(i->ARMin.NUnaryS.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppARMNRS(i->ARMin.NUnaryS.dst); -+//ZZ vex_printf(", "); -+//ZZ ppARMNRS(i->ARMin.NUnaryS.src); -+//ZZ return; -+//ZZ case ARMin_NShift: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonShiftOp(i->ARMin.NShift.op), -+//ZZ showARMNeonShiftOpDataType(i->ARMin.NShift.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppHRegARM(i->ARMin.NShift.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NShift.argL); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NShift.argR); -+//ZZ return; -+//ZZ case ARMin_NShl64: -+//ZZ vex_printf("vshl.i64 "); -+//ZZ ppHRegARM(i->ARMin.NShl64.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NShl64.src); -+//ZZ vex_printf(", #%u", i->ARMin.NShl64.amt); -+//ZZ return; -+//ZZ case ARMin_NDual: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonDualOp(i->ARMin.NDual.op), -+//ZZ showARMNeonDualOpDataType(i->ARMin.NDual.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppHRegARM(i->ARMin.NDual.arg1); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NDual.arg2); -+//ZZ return; -+//ZZ case ARMin_NBinary: -+//ZZ vex_printf("%s%s%s", -+//ZZ showARMNeonBinOp(i->ARMin.NBinary.op), -+//ZZ showARMNeonBinOpDataType(i->ARMin.NBinary.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ vex_printf(" "); -+//ZZ ppHRegARM(i->ARMin.NBinary.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NBinary.argL); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NBinary.argR); -+//ZZ return; -+ case ARM64in_VImmQ: -+ vex_printf("qimm "); -+ ppHRegARM64(i->ARM64in.VImmQ.rQ); -+ vex_printf(", Bits16toBytes16(0x%x)", (UInt)i->ARM64in.VImmQ.imm); -+ return; -+ case ARM64in_VDfromX: -+ vex_printf("fmov "); -+ ppHRegARM64(i->ARM64in.VDfromX.rD); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VDfromX.rX); -+ return; -+ case ARM64in_VQfromXX: -+ vex_printf("qFromXX "); -+ ppHRegARM64(i->ARM64in.VQfromXX.rQ); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VQfromXX.rXhi); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VQfromXX.rXlo); -+ return; -+ case ARM64in_VXfromQ: -+ vex_printf("mov "); -+ ppHRegARM64(i->ARM64in.VXfromQ.rX); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VXfromQ.rQ); -+ vex_printf(".d[%u]", i->ARM64in.VXfromQ.laneNo); -+ return; -+ case ARM64in_VMov: { -+ UChar aux = '?'; -+ switch (i->ARM64in.VMov.szB) { -+ case 16: aux = 'q'; break; -+ case 8: aux = 'd'; break; -+ case 4: aux = 's'; break; -+ default: break; -+ } -+ vex_printf("mov(%c) ", aux); -+ ppHRegARM64(i->ARM64in.VMov.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VMov.src); -+ return; -+ } -+//ZZ case ARMin_NCMovQ: -+//ZZ vex_printf("vmov%s ", showARMCondCode(i->ARMin.NCMovQ.cond)); -+//ZZ ppHRegARM(i->ARMin.NCMovQ.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NCMovQ.src); -+//ZZ return; -+//ZZ case ARMin_Add32: -+//ZZ vex_printf("add32 "); -+//ZZ ppHRegARM(i->ARMin.Add32.rD); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.Add32.rN); -+//ZZ vex_printf(", "); -+//ZZ vex_printf("%d", i->ARMin.Add32.imm32); -+//ZZ return; -+ case ARM64in_EvCheck: -+ vex_printf("(evCheck) ldr w9,"); -+ ppARM64AMode(i->ARM64in.EvCheck.amCounter); -+ vex_printf("; subs w9,w9,$1; str w9,"); -+ ppARM64AMode(i->ARM64in.EvCheck.amCounter); -+ vex_printf("; bpl nofail; ldr x9,"); -+ ppARM64AMode(i->ARM64in.EvCheck.amFailAddr); -+ vex_printf("; br x9; nofail:"); -+ return; -+//ZZ case ARMin_ProfInc: -+//ZZ vex_printf("(profInc) movw r12,LO16($NotKnownYet); " -+//ZZ "movw r12,HI16($NotKnownYet); " -+//ZZ "ldr r11,[r12]; " -+//ZZ "adds r11,r11,$1; " -+//ZZ "str r11,[r12]; " -+//ZZ "ldr r11,[r12+4]; " -+//ZZ "adc r11,r11,$0; " -+//ZZ "str r11,[r12+4]"); -+//ZZ return; -+ default: -+ vex_printf("ppARM64Instr: unhandled case (tag %d)", (Int)i->tag); -+ vpanic("ppARM64Instr(1)"); -+ return; -+ } -+} -+ -+ -+/* --------- Helpers for register allocation. --------- */ -+ -+void getRegUsage_ARM64Instr ( HRegUsage* u, ARM64Instr* i, Bool mode64 ) -+{ -+ vassert(mode64 == True); -+ initHRegUsage(u); -+ switch (i->tag) { -+ case ARM64in_Arith: -+ addHRegUse(u, HRmWrite, i->ARM64in.Arith.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Arith.argL); -+ addRegUsage_ARM64RIA(u, i->ARM64in.Arith.argR); -+ return; -+ case ARM64in_Cmp: -+ addHRegUse(u, HRmRead, i->ARM64in.Cmp.argL); -+ addRegUsage_ARM64RIA(u, i->ARM64in.Cmp.argR); -+ return; -+ case ARM64in_Logic: -+ addHRegUse(u, HRmWrite, i->ARM64in.Logic.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Logic.argL); -+ addRegUsage_ARM64RIL(u, i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Test: -+ addHRegUse(u, HRmRead, i->ARM64in.Test.argL); -+ addRegUsage_ARM64RIL(u, i->ARM64in.Test.argR); -+ return; -+ case ARM64in_Shift: -+ addHRegUse(u, HRmWrite, i->ARM64in.Shift.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Shift.argL); -+ addRegUsage_ARM64RI6(u, i->ARM64in.Shift.argR); -+ return; -+ case ARM64in_Unary: -+ addHRegUse(u, HRmWrite, i->ARM64in.Unary.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Unary.src); -+ return; -+ case ARM64in_MovI: -+ addHRegUse(u, HRmWrite, i->ARM64in.MovI.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.MovI.src); -+ return; -+ case ARM64in_Imm64: -+ addHRegUse(u, HRmWrite, i->ARM64in.Imm64.dst); -+ return; -+ case ARM64in_LdSt64: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt64.amode); -+ if (i->ARM64in.LdSt64.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt64.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt64.rD); -+ } -+ return; -+ case ARM64in_LdSt32: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt32.amode); -+ if (i->ARM64in.LdSt32.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt32.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt32.rD); -+ } -+ return; -+ case ARM64in_LdSt16: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt16.amode); -+ if (i->ARM64in.LdSt16.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt16.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt16.rD); -+ } -+ return; -+ case ARM64in_LdSt8: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt8.amode); -+ if (i->ARM64in.LdSt8.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt8.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt8.rD); -+ } -+ return; -+ /* XDirect/XIndir/XAssisted are also a bit subtle. They -+ conditionally exit the block. Hence we only need to list (1) -+ the registers that they read, and (2) the registers that they -+ write in the case where the block is not exited. (2) is -+ empty, hence only (1) is relevant here. */ -+ case ARM64in_XDirect: -+ addRegUsage_ARM64AMode(u, i->ARM64in.XDirect.amPC); -+ return; -+ case ARM64in_XIndir: -+ addHRegUse(u, HRmRead, i->ARM64in.XIndir.dstGA); -+ addRegUsage_ARM64AMode(u, i->ARM64in.XIndir.amPC); -+ return; -+ case ARM64in_XAssisted: -+ addHRegUse(u, HRmRead, i->ARM64in.XAssisted.dstGA); -+ addRegUsage_ARM64AMode(u, i->ARM64in.XAssisted.amPC); -+ return; -+ case ARM64in_CSel: -+ addHRegUse(u, HRmWrite, i->ARM64in.CSel.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.CSel.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.CSel.argR); -+ return; -+ case ARM64in_Call: -+ /* logic and comments copied/modified from x86 back end */ -+ /* This is a bit subtle. */ -+ /* First off, claim it trashes all the caller-saved regs -+ which fall within the register allocator's jurisdiction. -+ These I believe to be x0 to x7. Also need to be -+ careful about vector regs. */ -+ addHRegUse(u, HRmWrite, hregARM64_X0()); -+ addHRegUse(u, HRmWrite, hregARM64_X1()); -+ addHRegUse(u, HRmWrite, hregARM64_X2()); -+ addHRegUse(u, HRmWrite, hregARM64_X3()); -+ addHRegUse(u, HRmWrite, hregARM64_X4()); -+ addHRegUse(u, HRmWrite, hregARM64_X5()); -+ addHRegUse(u, HRmWrite, hregARM64_X6()); -+ addHRegUse(u, HRmWrite, hregARM64_X7()); -+ addHRegUse(u, HRmWrite, hregARM64_Q16()); -+ addHRegUse(u, HRmWrite, hregARM64_Q17()); -+ addHRegUse(u, HRmWrite, hregARM64_Q18()); -+ /* Now we have to state any parameter-carrying registers -+ which might be read. This depends on nArgRegs. */ -+ switch (i->ARM64in.Call.nArgRegs) { -+ case 8: addHRegUse(u, HRmRead, hregARM64_X7()); /*fallthru*/ -+ case 7: addHRegUse(u, HRmRead, hregARM64_X6()); /*fallthru*/ -+ case 6: addHRegUse(u, HRmRead, hregARM64_X5()); /*fallthru*/ -+ case 5: addHRegUse(u, HRmRead, hregARM64_X4()); /*fallthru*/ -+ case 4: addHRegUse(u, HRmRead, hregARM64_X3()); /*fallthru*/ -+ case 3: addHRegUse(u, HRmRead, hregARM64_X2()); /*fallthru*/ -+ case 2: addHRegUse(u, HRmRead, hregARM64_X1()); /*fallthru*/ -+ case 1: addHRegUse(u, HRmRead, hregARM64_X0()); break; -+ case 0: break; -+ default: vpanic("getRegUsage_ARM64:Call:regparms"); -+ } -+ /* Finally, there is the issue that the insn trashes a -+ register because the literal target address has to be -+ loaded into a register. However, we reserve x9 for that -+ purpose so there's no further complexity here. Stating x9 -+ as trashed is pointless since it's not under the control -+ of the allocator, but what the hell. */ -+ addHRegUse(u, HRmWrite, hregARM64_X9()); -+ return; -+ case ARM64in_AddToSP: -+ /* Only changes SP, but regalloc doesn't control that, hence -+ we don't care. */ -+ return; -+ case ARM64in_FromSP: -+ addHRegUse(u, HRmWrite, i->ARM64in.FromSP.dst); -+ return; -+ case ARM64in_Mul: -+ addHRegUse(u, HRmWrite, i->ARM64in.Mul.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Mul.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.Mul.argR); -+ return; -+//ZZ case ARMin_LdrEX: -+//ZZ addHRegUse(u, HRmRead, hregARM_R4()); -+//ZZ addHRegUse(u, HRmWrite, hregARM_R2()); -+//ZZ if (i->ARMin.LdrEX.szB == 8) -+//ZZ addHRegUse(u, HRmWrite, hregARM_R3()); -+//ZZ return; -+//ZZ case ARMin_StrEX: -+//ZZ addHRegUse(u, HRmRead, hregARM_R4()); -+//ZZ addHRegUse(u, HRmWrite, hregARM_R0()); -+//ZZ addHRegUse(u, HRmRead, hregARM_R2()); -+//ZZ if (i->ARMin.StrEX.szB == 8) -+//ZZ addHRegUse(u, HRmRead, hregARM_R3()); -+//ZZ return; -+ case ARM64in_VLdStS: -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStS.rN); -+ if (i->ARM64in.VLdStS.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.VLdStS.sD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStS.sD); -+ } -+ return; -+ case ARM64in_VLdStD: -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStD.rN); -+ if (i->ARM64in.VLdStD.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.VLdStD.dD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStD.dD); -+ } -+ return; -+ case ARM64in_VLdStQ: -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStQ.rN); -+ if (i->ARM64in.VLdStQ.isLoad) -+ addHRegUse(u, HRmWrite, i->ARM64in.VLdStQ.rQ); -+ else -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStQ.rQ); -+ return; -+ case ARM64in_VCvtI2F: -+ addHRegUse(u, HRmRead, i->ARM64in.VCvtI2F.rS); -+ addHRegUse(u, HRmWrite, i->ARM64in.VCvtI2F.rD); -+ return; -+ case ARM64in_VCvtF2I: -+ addHRegUse(u, HRmRead, i->ARM64in.VCvtF2I.rS); -+ addHRegUse(u, HRmWrite, i->ARM64in.VCvtF2I.rD); -+ return; -+ case ARM64in_VCvtSD: -+ addHRegUse(u, HRmWrite, i->ARM64in.VCvtSD.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VCvtSD.src); -+ return; -+ case ARM64in_VUnaryD: -+ addHRegUse(u, HRmWrite, i->ARM64in.VUnaryD.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VUnaryD.src); -+ return; -+ case ARM64in_VUnaryS: -+ addHRegUse(u, HRmWrite, i->ARM64in.VUnaryS.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VUnaryS.src); -+ return; -+ case ARM64in_VBinD: -+ addHRegUse(u, HRmWrite, i->ARM64in.VBinD.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinD.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinD.argR); -+ return; -+ case ARM64in_VBinS: -+ addHRegUse(u, HRmWrite, i->ARM64in.VBinS.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinS.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinS.argR); -+ return; -+ case ARM64in_VCmpD: -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpD.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpD.argR); -+ return; -+ case ARM64in_VCmpS: -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpS.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpS.argR); -+ return; -+ case ARM64in_FPCR: -+ if (i->ARM64in.FPCR.toFPCR) -+ addHRegUse(u, HRmRead, i->ARM64in.FPCR.iReg); -+ else -+ addHRegUse(u, HRmWrite, i->ARM64in.FPCR.iReg); -+ return; -+//ZZ case ARMin_VAluS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VAluS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VAluS.argL); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VAluS.argR); -+//ZZ return; -+//ZZ case ARMin_VUnaryS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VUnaryS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VUnaryS.src); -+//ZZ return; -+//ZZ case ARMin_VCMovD: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VCMovD.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovD.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovD.src); -+//ZZ return; -+//ZZ case ARMin_VCMovS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VCMovS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovS.src); -+//ZZ return; -+//ZZ case ARMin_VXferD: -+//ZZ if (i->ARMin.VXferD.toD) { -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferD.dD); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferD.rHi); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferD.rLo); -+//ZZ } else { -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferD.dD); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferD.rHi); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferD.rLo); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VXferS: -+//ZZ if (i->ARMin.VXferS.toS) { -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferS.fD); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferS.rLo); -+//ZZ } else { -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferS.fD); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferS.rLo); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VCvtID: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VCvtID.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCvtID.src); -+//ZZ return; -+//ZZ case ARMin_MFence: -+//ZZ return; -+//ZZ case ARMin_CLREX: -+//ZZ return; -+//ZZ case ARMin_NLdStD: -+//ZZ if (i->ARMin.NLdStD.isLoad) -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NLdStD.dD); -+//ZZ else -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NLdStD.dD); -+//ZZ addRegUsage_ARMAModeN(u, i->ARMin.NLdStD.amode); -+//ZZ return; -+//ZZ case ARMin_NUnary: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NUnary.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NUnary.src); -+//ZZ return; -+//ZZ case ARMin_NUnaryS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NUnaryS.dst->reg); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NUnaryS.src->reg); -+//ZZ return; -+//ZZ case ARMin_NShift: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NShift.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NShift.argL); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NShift.argR); -+//ZZ return; -+//ZZ case ARMin_NShl64: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NShl64.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NShl64.src); -+//ZZ return; -+//ZZ case ARMin_NDual: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NDual.arg1); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NDual.arg2); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NDual.arg1); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NDual.arg2); -+//ZZ return; -+ case ARM64in_VImmQ: -+ addHRegUse(u, HRmWrite, i->ARM64in.VImmQ.rQ); -+ return; -+ case ARM64in_VDfromX: -+ addHRegUse(u, HRmWrite, i->ARM64in.VDfromX.rD); -+ addHRegUse(u, HRmRead, i->ARM64in.VDfromX.rX); -+ return; -+ case ARM64in_VQfromXX: -+ addHRegUse(u, HRmWrite, i->ARM64in.VQfromXX.rQ); -+ addHRegUse(u, HRmRead, i->ARM64in.VQfromXX.rXhi); -+ addHRegUse(u, HRmRead, i->ARM64in.VQfromXX.rXlo); -+ return; -+ case ARM64in_VXfromQ: -+ addHRegUse(u, HRmWrite, i->ARM64in.VXfromQ.rX); -+ addHRegUse(u, HRmRead, i->ARM64in.VXfromQ.rQ); -+ return; -+ case ARM64in_VMov: -+ addHRegUse(u, HRmWrite, i->ARM64in.VMov.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VMov.src); -+ return; -+//ZZ case ARMin_NBinary: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NBinary.dst); -+//ZZ /* TODO: sometimes dst is also being read! */ -+//ZZ // XXX fix this -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NBinary.argL); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NBinary.argR); -+//ZZ return; -+//ZZ case ARMin_NCMovQ: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NCMovQ.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NCMovQ.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NCMovQ.src); -+//ZZ return; -+//ZZ case ARMin_Add32: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.Add32.rD); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.Add32.rN); -+//ZZ return; -+ case ARM64in_EvCheck: -+ /* We expect both amodes only to mention x21, so this is in -+ fact pointless, since x21 isn't allocatable, but -+ anyway.. */ -+ addRegUsage_ARM64AMode(u, i->ARM64in.EvCheck.amCounter); -+ addRegUsage_ARM64AMode(u, i->ARM64in.EvCheck.amFailAddr); -+ addHRegUse(u, HRmWrite, hregARM64_X9()); /* also unavail to RA */ -+ return; -+//ZZ case ARMin_ProfInc: -+//ZZ addHRegUse(u, HRmWrite, hregARM_R12()); -+//ZZ addHRegUse(u, HRmWrite, hregARM_R11()); -+//ZZ return; -+ default: -+ ppARM64Instr(i); -+ vpanic("getRegUsage_ARM64Instr"); -+ } -+} -+ -+ -+void mapRegs_ARM64Instr ( HRegRemap* m, ARM64Instr* i, Bool mode64 ) -+{ -+ vassert(mode64 == True); -+ switch (i->tag) { -+ case ARM64in_Arith: -+ i->ARM64in.Arith.dst = lookupHRegRemap(m, i->ARM64in.Arith.dst); -+ i->ARM64in.Arith.argL = lookupHRegRemap(m, i->ARM64in.Arith.argL); -+ mapRegs_ARM64RIA(m, i->ARM64in.Arith.argR); -+ return; -+ case ARM64in_Cmp: -+ i->ARM64in.Cmp.argL = lookupHRegRemap(m, i->ARM64in.Cmp.argL); -+ mapRegs_ARM64RIA(m, i->ARM64in.Cmp.argR); -+ return; -+ case ARM64in_Logic: -+ i->ARM64in.Logic.dst = lookupHRegRemap(m, i->ARM64in.Logic.dst); -+ i->ARM64in.Logic.argL = lookupHRegRemap(m, i->ARM64in.Logic.argL); -+ mapRegs_ARM64RIL(m, i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Test: -+ i->ARM64in.Test.argL = lookupHRegRemap(m, i->ARM64in.Test.argL); -+ mapRegs_ARM64RIL(m, i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Shift: -+ i->ARM64in.Shift.dst = lookupHRegRemap(m, i->ARM64in.Shift.dst); -+ i->ARM64in.Shift.argL = lookupHRegRemap(m, i->ARM64in.Shift.argL); -+ mapRegs_ARM64RI6(m, i->ARM64in.Shift.argR); -+ return; -+ case ARM64in_Unary: -+ i->ARM64in.Unary.dst = lookupHRegRemap(m, i->ARM64in.Unary.dst); -+ i->ARM64in.Unary.src = lookupHRegRemap(m, i->ARM64in.Unary.src); -+ return; -+ case ARM64in_MovI: -+ i->ARM64in.MovI.dst = lookupHRegRemap(m, i->ARM64in.MovI.dst); -+ i->ARM64in.MovI.src = lookupHRegRemap(m, i->ARM64in.MovI.src); -+ return; -+ case ARM64in_Imm64: -+ i->ARM64in.Imm64.dst = lookupHRegRemap(m, i->ARM64in.Imm64.dst); -+ return; -+ case ARM64in_LdSt64: -+ i->ARM64in.LdSt64.rD = lookupHRegRemap(m, i->ARM64in.LdSt64.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt64.amode); -+ return; -+ case ARM64in_LdSt32: -+ i->ARM64in.LdSt32.rD = lookupHRegRemap(m, i->ARM64in.LdSt32.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt32.amode); -+ return; -+ case ARM64in_LdSt16: -+ i->ARM64in.LdSt16.rD = lookupHRegRemap(m, i->ARM64in.LdSt16.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt16.amode); -+ return; -+ case ARM64in_LdSt8: -+ i->ARM64in.LdSt8.rD = lookupHRegRemap(m, i->ARM64in.LdSt8.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt8.amode); -+ return; -+ case ARM64in_XDirect: -+ mapRegs_ARM64AMode(m, i->ARM64in.XDirect.amPC); -+ return; -+ case ARM64in_XIndir: -+ i->ARM64in.XIndir.dstGA -+ = lookupHRegRemap(m, i->ARM64in.XIndir.dstGA); -+ mapRegs_ARM64AMode(m, i->ARM64in.XIndir.amPC); -+ return; -+ case ARM64in_XAssisted: -+ i->ARM64in.XAssisted.dstGA -+ = lookupHRegRemap(m, i->ARM64in.XAssisted.dstGA); -+ mapRegs_ARM64AMode(m, i->ARM64in.XAssisted.amPC); -+ return; -+ case ARM64in_CSel: -+ i->ARM64in.CSel.dst = lookupHRegRemap(m, i->ARM64in.CSel.dst); -+ i->ARM64in.CSel.argL = lookupHRegRemap(m, i->ARM64in.CSel.argL); -+ i->ARM64in.CSel.argR = lookupHRegRemap(m, i->ARM64in.CSel.argR); -+ return; -+ case ARM64in_Call: -+ return; -+ case ARM64in_AddToSP: -+ return; -+ case ARM64in_FromSP: -+ i->ARM64in.FromSP.dst = lookupHRegRemap(m, i->ARM64in.FromSP.dst); -+ return; -+ case ARM64in_Mul: -+ i->ARM64in.Mul.dst = lookupHRegRemap(m, i->ARM64in.Mul.dst); -+ i->ARM64in.Mul.argL = lookupHRegRemap(m, i->ARM64in.Mul.argL); -+ i->ARM64in.Mul.argR = lookupHRegRemap(m, i->ARM64in.Mul.argR); -+ break; -+//ZZ case ARMin_Mul: -+//ZZ return; -+//ZZ case ARMin_LdrEX: -+//ZZ return; -+//ZZ case ARMin_StrEX: -+//ZZ return; -+ case ARM64in_VLdStS: -+ i->ARM64in.VLdStS.sD = lookupHRegRemap(m, i->ARM64in.VLdStS.sD); -+ i->ARM64in.VLdStS.rN = lookupHRegRemap(m, i->ARM64in.VLdStS.rN); -+ return; -+ case ARM64in_VLdStD: -+ i->ARM64in.VLdStD.dD = lookupHRegRemap(m, i->ARM64in.VLdStD.dD); -+ i->ARM64in.VLdStD.rN = lookupHRegRemap(m, i->ARM64in.VLdStD.rN); -+ return; -+ case ARM64in_VLdStQ: -+ i->ARM64in.VLdStQ.rQ = lookupHRegRemap(m, i->ARM64in.VLdStQ.rQ); -+ i->ARM64in.VLdStQ.rN = lookupHRegRemap(m, i->ARM64in.VLdStQ.rN); -+ return; -+ case ARM64in_VCvtI2F: -+ i->ARM64in.VCvtI2F.rS = lookupHRegRemap(m, i->ARM64in.VCvtI2F.rS); -+ i->ARM64in.VCvtI2F.rD = lookupHRegRemap(m, i->ARM64in.VCvtI2F.rD); -+ return; -+ case ARM64in_VCvtF2I: -+ i->ARM64in.VCvtF2I.rS = lookupHRegRemap(m, i->ARM64in.VCvtF2I.rS); -+ i->ARM64in.VCvtF2I.rD = lookupHRegRemap(m, i->ARM64in.VCvtF2I.rD); -+ return; -+ case ARM64in_VCvtSD: -+ i->ARM64in.VCvtSD.dst = lookupHRegRemap(m, i->ARM64in.VCvtSD.dst); -+ i->ARM64in.VCvtSD.src = lookupHRegRemap(m, i->ARM64in.VCvtSD.src); -+ return; -+ case ARM64in_VUnaryD: -+ i->ARM64in.VUnaryD.dst = lookupHRegRemap(m, i->ARM64in.VUnaryD.dst); -+ i->ARM64in.VUnaryD.src = lookupHRegRemap(m, i->ARM64in.VUnaryD.src); -+ return; -+ case ARM64in_VUnaryS: -+ i->ARM64in.VUnaryS.dst = lookupHRegRemap(m, i->ARM64in.VUnaryS.dst); -+ i->ARM64in.VUnaryS.src = lookupHRegRemap(m, i->ARM64in.VUnaryS.src); -+ return; -+ case ARM64in_VBinD: -+ i->ARM64in.VBinD.dst = lookupHRegRemap(m, i->ARM64in.VBinD.dst); -+ i->ARM64in.VBinD.argL = lookupHRegRemap(m, i->ARM64in.VBinD.argL); -+ i->ARM64in.VBinD.argR = lookupHRegRemap(m, i->ARM64in.VBinD.argR); -+ return; -+ case ARM64in_VBinS: -+ i->ARM64in.VBinS.dst = lookupHRegRemap(m, i->ARM64in.VBinS.dst); -+ i->ARM64in.VBinS.argL = lookupHRegRemap(m, i->ARM64in.VBinS.argL); -+ i->ARM64in.VBinS.argR = lookupHRegRemap(m, i->ARM64in.VBinS.argR); -+ return; -+ case ARM64in_VCmpD: -+ i->ARM64in.VCmpD.argL = lookupHRegRemap(m, i->ARM64in.VCmpD.argL); -+ i->ARM64in.VCmpD.argR = lookupHRegRemap(m, i->ARM64in.VCmpD.argR); -+ return; -+ case ARM64in_VCmpS: -+ i->ARM64in.VCmpS.argL = lookupHRegRemap(m, i->ARM64in.VCmpS.argL); -+ i->ARM64in.VCmpS.argR = lookupHRegRemap(m, i->ARM64in.VCmpS.argR); -+ return; -+ case ARM64in_FPCR: -+ i->ARM64in.FPCR.iReg = lookupHRegRemap(m, i->ARM64in.FPCR.iReg); -+ return; -+//ZZ case ARMin_VAluS: -+//ZZ i->ARMin.VAluS.dst = lookupHRegRemap(m, i->ARMin.VAluS.dst); -+//ZZ i->ARMin.VAluS.argL = lookupHRegRemap(m, i->ARMin.VAluS.argL); -+//ZZ i->ARMin.VAluS.argR = lookupHRegRemap(m, i->ARMin.VAluS.argR); -+//ZZ return; -+//ZZ case ARMin_VCMovD: -+//ZZ i->ARMin.VCMovD.dst = lookupHRegRemap(m, i->ARMin.VCMovD.dst); -+//ZZ i->ARMin.VCMovD.src = lookupHRegRemap(m, i->ARMin.VCMovD.src); -+//ZZ return; -+//ZZ case ARMin_VCMovS: -+//ZZ i->ARMin.VCMovS.dst = lookupHRegRemap(m, i->ARMin.VCMovS.dst); -+//ZZ i->ARMin.VCMovS.src = lookupHRegRemap(m, i->ARMin.VCMovS.src); -+//ZZ return; -+//ZZ case ARMin_VXferD: -+//ZZ i->ARMin.VXferD.dD = lookupHRegRemap(m, i->ARMin.VXferD.dD); -+//ZZ i->ARMin.VXferD.rHi = lookupHRegRemap(m, i->ARMin.VXferD.rHi); -+//ZZ i->ARMin.VXferD.rLo = lookupHRegRemap(m, i->ARMin.VXferD.rLo); -+//ZZ return; -+//ZZ case ARMin_VXferS: -+//ZZ i->ARMin.VXferS.fD = lookupHRegRemap(m, i->ARMin.VXferS.fD); -+//ZZ i->ARMin.VXferS.rLo = lookupHRegRemap(m, i->ARMin.VXferS.rLo); -+//ZZ return; -+//ZZ case ARMin_VCvtID: -+//ZZ i->ARMin.VCvtID.dst = lookupHRegRemap(m, i->ARMin.VCvtID.dst); -+//ZZ i->ARMin.VCvtID.src = lookupHRegRemap(m, i->ARMin.VCvtID.src); -+//ZZ return; -+//ZZ case ARMin_MFence: -+//ZZ return; -+//ZZ case ARMin_CLREX: -+//ZZ return; -+//ZZ case ARMin_NLdStD: -+//ZZ i->ARMin.NLdStD.dD = lookupHRegRemap(m, i->ARMin.NLdStD.dD); -+//ZZ mapRegs_ARMAModeN(m, i->ARMin.NLdStD.amode); -+//ZZ return; -+//ZZ case ARMin_NUnary: -+//ZZ i->ARMin.NUnary.src = lookupHRegRemap(m, i->ARMin.NUnary.src); -+//ZZ i->ARMin.NUnary.dst = lookupHRegRemap(m, i->ARMin.NUnary.dst); -+//ZZ return; -+//ZZ case ARMin_NUnaryS: -+//ZZ i->ARMin.NUnaryS.src->reg -+//ZZ = lookupHRegRemap(m, i->ARMin.NUnaryS.src->reg); -+//ZZ i->ARMin.NUnaryS.dst->reg -+//ZZ = lookupHRegRemap(m, i->ARMin.NUnaryS.dst->reg); -+//ZZ return; -+//ZZ case ARMin_NShift: -+//ZZ i->ARMin.NShift.dst = lookupHRegRemap(m, i->ARMin.NShift.dst); -+//ZZ i->ARMin.NShift.argL = lookupHRegRemap(m, i->ARMin.NShift.argL); -+//ZZ i->ARMin.NShift.argR = lookupHRegRemap(m, i->ARMin.NShift.argR); -+//ZZ return; -+//ZZ case ARMin_NShl64: -+//ZZ i->ARMin.NShl64.dst = lookupHRegRemap(m, i->ARMin.NShl64.dst); -+//ZZ i->ARMin.NShl64.src = lookupHRegRemap(m, i->ARMin.NShl64.src); -+//ZZ return; -+//ZZ case ARMin_NDual: -+//ZZ i->ARMin.NDual.arg1 = lookupHRegRemap(m, i->ARMin.NDual.arg1); -+//ZZ i->ARMin.NDual.arg2 = lookupHRegRemap(m, i->ARMin.NDual.arg2); -+//ZZ return; -+ case ARM64in_VImmQ: -+ i->ARM64in.VImmQ.rQ = lookupHRegRemap(m, i->ARM64in.VImmQ.rQ); -+ return; -+ case ARM64in_VDfromX: -+ i->ARM64in.VDfromX.rD -+ = lookupHRegRemap(m, i->ARM64in.VDfromX.rD); -+ i->ARM64in.VDfromX.rX -+ = lookupHRegRemap(m, i->ARM64in.VDfromX.rX); -+ return; -+ case ARM64in_VQfromXX: -+ i->ARM64in.VQfromXX.rQ -+ = lookupHRegRemap(m, i->ARM64in.VQfromXX.rQ); -+ i->ARM64in.VQfromXX.rXhi -+ = lookupHRegRemap(m, i->ARM64in.VQfromXX.rXhi); -+ i->ARM64in.VQfromXX.rXlo -+ = lookupHRegRemap(m, i->ARM64in.VQfromXX.rXlo); -+ return; -+ case ARM64in_VXfromQ: -+ i->ARM64in.VXfromQ.rX -+ = lookupHRegRemap(m, i->ARM64in.VXfromQ.rX); -+ i->ARM64in.VXfromQ.rQ -+ = lookupHRegRemap(m, i->ARM64in.VXfromQ.rQ); -+ return; -+ case ARM64in_VMov: -+ i->ARM64in.VMov.dst = lookupHRegRemap(m, i->ARM64in.VMov.dst); -+ i->ARM64in.VMov.src = lookupHRegRemap(m, i->ARM64in.VMov.src); -+ return; -+ -+//ZZ case ARMin_NBinary: -+//ZZ i->ARMin.NBinary.argL = lookupHRegRemap(m, i->ARMin.NBinary.argL); -+//ZZ i->ARMin.NBinary.argR = lookupHRegRemap(m, i->ARMin.NBinary.argR); -+//ZZ i->ARMin.NBinary.dst = lookupHRegRemap(m, i->ARMin.NBinary.dst); -+//ZZ return; -+//ZZ case ARMin_NCMovQ: -+//ZZ i->ARMin.NCMovQ.dst = lookupHRegRemap(m, i->ARMin.NCMovQ.dst); -+//ZZ i->ARMin.NCMovQ.src = lookupHRegRemap(m, i->ARMin.NCMovQ.src); -+//ZZ return; -+//ZZ case ARMin_Add32: -+//ZZ i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD); -+//ZZ i->ARMin.Add32.rN = lookupHRegRemap(m, i->ARMin.Add32.rN); -+//ZZ return; -+ case ARM64in_EvCheck: -+ /* We expect both amodes only to mention x21, so this is in -+ fact pointless, since x21 isn't allocatable, but -+ anyway.. */ -+ mapRegs_ARM64AMode(m, i->ARM64in.EvCheck.amCounter); -+ mapRegs_ARM64AMode(m, i->ARM64in.EvCheck.amFailAddr); -+ return; -+//ZZ case ARMin_ProfInc: -+//ZZ /* hardwires r11 and r12 -- nothing to modify. */ -+//ZZ return; -+ default: -+ ppARM64Instr(i); -+ vpanic("mapRegs_ARM64Instr"); -+ } -+} -+ -+/* Figure out if i represents a reg-reg move, and if so assign the -+ source and destination to *src and *dst. If in doubt say No. Used -+ by the register allocator to do move coalescing. -+*/ -+Bool isMove_ARM64Instr ( ARM64Instr* i, HReg* src, HReg* dst ) -+{ -+ switch (i->tag) { -+ case ARM64in_MovI: -+ *src = i->ARM64in.MovI.src; -+ *dst = i->ARM64in.MovI.dst; -+ return True; -+ case ARM64in_VMov: -+ *src = i->ARM64in.VMov.src; -+ *dst = i->ARM64in.VMov.dst; -+ return True; -+ default: -+ break; -+ } -+ -+ return False; -+} -+ -+ -+/* Generate arm spill/reload instructions under the direction of the -+ register allocator. Note it's critical these don't write the -+ condition codes. */ -+ -+void genSpill_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offsetB, Bool mode64 ) -+{ -+ HRegClass rclass; -+ vassert(offsetB >= 0); -+ vassert(!hregIsVirtual(rreg)); -+ vassert(mode64 == True); -+ *i1 = *i2 = NULL; -+ rclass = hregClass(rreg); -+ switch (rclass) { -+ case HRcInt64: -+ vassert(0 == (offsetB & 7)); -+ offsetB >>= 3; -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_LdSt64( -+ False/*!isLoad*/, -+ rreg, -+ ARM64AMode_RI12(hregARM64_X21(), offsetB, 8) -+ ); -+ return; -+ case HRcFlt64: -+ vassert(0 == (offsetB & 7)); -+ vassert(offsetB >= 0 && offsetB < 32768); -+ *i1 = ARM64Instr_VLdStD(False/*!isLoad*/, -+ rreg, hregARM64_X21(), offsetB); -+ return; -+ case HRcVec128: { -+ HReg x21 = hregARM64_X21(); // baseblock -+ HReg x9 = hregARM64_X9(); // spill temporary -+ vassert(0 == (offsetB & 15)); // check sane alignment -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_Arith(x9, x21, ARM64RIA_I12(offsetB, 0), True); -+ *i2 = ARM64Instr_VLdStQ(False/*!isLoad*/, rreg, x9); -+ return; -+ } -+ default: -+ ppHRegClass(rclass); -+ vpanic("genSpill_ARM: unimplemented regclass"); -+ } -+} -+ -+void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offsetB, Bool mode64 ) -+{ -+ HRegClass rclass; -+ vassert(offsetB >= 0); -+ vassert(!hregIsVirtual(rreg)); -+ vassert(mode64 == True); -+ *i1 = *i2 = NULL; -+ rclass = hregClass(rreg); -+ switch (rclass) { -+ case HRcInt64: -+ vassert(0 == (offsetB & 7)); -+ offsetB >>= 3; -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_LdSt64( -+ True/*isLoad*/, -+ rreg, -+ ARM64AMode_RI12(hregARM64_X21(), offsetB, 8) -+ ); -+ return; -+ case HRcFlt64: -+ vassert(0 == (offsetB & 7)); -+ vassert(offsetB >= 0 && offsetB < 32768); -+ *i1 = ARM64Instr_VLdStD(True/*isLoad*/, -+ rreg, hregARM64_X21(), offsetB); -+ return; -+ case HRcVec128: { -+ HReg x21 = hregARM64_X21(); // baseblock -+ HReg x9 = hregARM64_X9(); // spill temporary -+ vassert(0 == (offsetB & 15)); // check sane alignment -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_Arith(x9, x21, ARM64RIA_I12(offsetB, 0), True); -+ *i2 = ARM64Instr_VLdStQ(True/*isLoad*/, rreg, x9); -+ return; -+ } -+ default: -+ ppHRegClass(rclass); -+ vpanic("genReload_ARM: unimplemented regclass"); -+ } -+} -+ -+ -+//ZZ /* Emit an instruction into buf and return the number of bytes used. -+//ZZ Note that buf is not the insn's final place, and therefore it is -+//ZZ imperative to emit position-independent code. */ -+ -+static inline UChar iregNo ( HReg r ) -+{ -+ UInt n; -+ vassert(hregClass(r) == HRcInt64); -+ vassert(!hregIsVirtual(r)); -+ n = hregNumber(r); -+ vassert(n <= 30); -+ return toUChar(n); -+} -+ -+static inline UChar dregNo ( HReg r ) -+{ -+ UInt n; -+ vassert(hregClass(r) == HRcFlt64); -+ vassert(!hregIsVirtual(r)); -+ n = hregNumber(r); -+ vassert(n <= 31); -+ return toUChar(n); -+} -+ -+static inline UChar qregNo ( HReg r ) -+{ -+ UInt n; -+ vassert(hregClass(r) == HRcVec128); -+ vassert(!hregIsVirtual(r)); -+ n = hregNumber(r); -+ vassert(n <= 31); -+ return toUChar(n); -+} -+ -+#define BITS4(zzb3,zzb2,zzb1,zzb0) \ -+ (((zzb3) << 3) | ((zzb2) << 2) | ((zzb1) << 1) | (zzb0)) -+ -+#define X00 BITS4(0,0, 0,0) -+#define X01 BITS4(0,0, 0,1) -+#define X10 BITS4(0,0, 1,0) -+#define X11 BITS4(0,0, 1,1) -+ -+#define X000 BITS4(0, 0,0,0) -+#define X001 BITS4(0, 0,0,1) -+#define X010 BITS4(0, 0,1,0) -+#define X011 BITS4(0, 0,1,1) -+#define X100 BITS4(0, 1,0,0) -+#define X101 BITS4(0, 1,0,1) -+#define X110 BITS4(0, 1,1,0) -+#define X111 BITS4(0, 1,1,1) -+ -+#define BITS8(zzb7,zzb6,zzb5,zzb4,zzb3,zzb2,zzb1,zzb0) \ -+ ((BITS4(zzb7,zzb6,zzb5,zzb4) << 4) | BITS4(zzb3,zzb2,zzb1,zzb0)) -+ -+#define X0000 BITS4(0,0,0,0) -+#define X0001 BITS4(0,0,0,1) -+#define X0010 BITS4(0,0,1,0) -+#define X0011 BITS4(0,0,1,1) -+ -+#define X00000 BITS8(0,0,0, 0,0,0,0,0) -+#define X00111 BITS8(0,0,0, 0,0,1,1,1) -+#define X01000 BITS8(0,0,0, 0,1,0,0,0) -+#define X10000 BITS8(0,0,0, 1,0,0,0,0) -+#define X11000 BITS8(0,0,0, 1,1,0,0,0) -+#define X11110 BITS8(0,0,0, 1,1,1,1,0) -+#define X11111 BITS8(0,0,0, 1,1,1,1,1) -+ -+#define X000000 BITS8(0,0, 0,0,0,0,0,0) -+#define X000100 BITS8(0,0, 0,0,0,1,0,0) -+#define X001000 BITS8(0,0, 0,0,1,0,0,0) -+#define X001001 BITS8(0,0, 0,0,1,0,0,1) -+#define X001010 BITS8(0,0, 0,0,1,0,1,0) -+#define X001111 BITS8(0,0, 0,0,1,1,1,1) -+#define X010000 BITS8(0,0, 0,1,0,0,0,0) -+#define X010001 BITS8(0,0, 0,1,0,0,0,1) -+#define X011010 BITS8(0,0, 0,1,1,0,1,0) -+#define X011111 BITS8(0,0, 0,1,1,1,1,1) -+#define X100100 BITS8(0,0, 1,0,0,1,0,0) -+#define X100101 BITS8(0,0, 1,0,0,1,0,1) -+#define X100110 BITS8(0,0, 1,0,0,1,1,0) -+#define X110000 BITS8(0,0, 1,1,0,0,0,0) -+#define X110001 BITS8(0,0, 1,1,0,0,0,1) -+#define X111000 BITS8(0,0, 1,1,1,0,0,0) -+#define X111001 BITS8(0,0, 1,1,1,0,0,1) -+#define X111101 BITS8(0,0, 1,1,1,1,0,1) -+ -+#define X00100000 BITS8(0,0,1,0,0,0,0,0) -+#define X00100001 BITS8(0,0,1,0,0,0,0,1) -+#define X00100010 BITS8(0,0,1,0,0,0,1,0) -+#define X00100011 BITS8(0,0,1,0,0,0,1,1) -+#define X01010000 BITS8(0,1,0,1,0,0,0,0) -+#define X01010001 BITS8(0,1,0,1,0,0,0,1) -+#define X01010100 BITS8(0,1,0,1,0,1,0,0) -+#define X01011000 BITS8(0,1,0,1,1,0,0,0) -+#define X01100000 BITS8(0,1,1,0,0,0,0,0) -+#define X01100001 BITS8(0,1,1,0,0,0,0,1) -+#define X01100010 BITS8(0,1,1,0,0,0,1,0) -+#define X01100011 BITS8(0,1,1,0,0,0,1,1) -+#define X01110000 BITS8(0,1,1,1,0,0,0,0) -+#define X11000001 BITS8(1,1,0,0,0,0,0,1) -+#define X11000011 BITS8(1,1,0,0,0,0,1,1) -+#define X11010100 BITS8(1,1,0,1,0,1,0,0) -+#define X11010110 BITS8(1,1,0,1,0,1,1,0) -+#define X11011000 BITS8(1,1,0,1,1,0,0,0) -+#define X11011010 BITS8(1,1,0,1,1,0,1,0) -+#define X11011110 BITS8(1,1,0,1,1,1,1,0) -+#define X11110001 BITS8(1,1,1,1,0,0,0,1) -+#define X11110011 BITS8(1,1,1,1,0,0,1,1) -+ -+ -+/* --- 4 fields --- */ -+ -+static inline UInt X_8_19_1_4 ( UInt f1, UInt f2, UInt f3, UInt f4 ) { -+ vassert(8+19+1+4 == 32); -+ vassert(f1 < (1<<8)); -+ vassert(f2 < (1<<19)); -+ vassert(f3 < (1<<1)); -+ vassert(f4 < (1<<4)); -+ UInt w = 0; -+ w = (w << 8) | f1; -+ w = (w << 19) | f2; -+ w = (w << 1) | f3; -+ w = (w << 4) | f4; -+ return w; -+} -+ -+/* --- 5 fields --- */ -+ -+static inline UInt X_3_6_2_16_5 ( UInt f1, UInt f2, -+ UInt f3, UInt f4, UInt f5 ) { -+ vassert(3+6+2+16+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<2)); -+ vassert(f4 < (1<<16)); -+ vassert(f5 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 6) | f2; -+ w = (w << 2) | f3; -+ w = (w << 16) | f4; -+ w = (w << 5) | f5; -+ return w; -+} -+ -+/* --- 6 fields --- */ -+ -+static inline UInt X_2_6_2_12_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6 ) { -+ vassert(2+6+2+12+5+5 == 32); -+ vassert(f1 < (1<<2)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<2)); -+ vassert(f4 < (1<<12)); -+ vassert(f5 < (1<<5)); -+ vassert(f6 < (1<<5)); -+ UInt w = 0; -+ w = (w << 2) | f1; -+ w = (w << 6) | f2; -+ w = (w << 2) | f3; -+ w = (w << 12) | f4; -+ w = (w << 5) | f5; -+ w = (w << 5) | f6; -+ return w; -+} -+ -+static inline UInt X_3_8_5_6_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6 ) { -+ vassert(3+8+5+6+5+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<8)); -+ vassert(f3 < (1<<5)); -+ vassert(f4 < (1<<6)); -+ vassert(f5 < (1<<5)); -+ vassert(f6 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 8) | f2; -+ w = (w << 5) | f3; -+ w = (w << 6) | f4; -+ w = (w << 5) | f5; -+ w = (w << 5) | f6; -+ return w; -+} -+ -+static inline UInt X_3_5_8_6_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6 ) { -+ vassert(3+8+5+6+5+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<5)); -+ vassert(f3 < (1<<8)); -+ vassert(f4 < (1<<6)); -+ vassert(f5 < (1<<5)); -+ vassert(f6 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 5) | f2; -+ w = (w << 8) | f3; -+ w = (w << 6) | f4; -+ w = (w << 5) | f5; -+ w = (w << 5) | f6; -+ return w; -+} -+ -+/* --- 7 fields --- */ -+ -+static inline UInt X_2_6_3_9_2_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6, UInt f7 ) { -+ vassert(2+6+3+9+2+5+5 == 32); -+ vassert(f1 < (1<<2)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<3)); -+ vassert(f4 < (1<<9)); -+ vassert(f5 < (1<<2)); -+ vassert(f6 < (1<<5)); -+ vassert(f7 < (1<<5)); -+ UInt w = 0; -+ w = (w << 2) | f1; -+ w = (w << 6) | f2; -+ w = (w << 3) | f3; -+ w = (w << 9) | f4; -+ w = (w << 2) | f5; -+ w = (w << 5) | f6; -+ w = (w << 5) | f7; -+ return w; -+} -+ -+static inline UInt X_3_6_1_6_6_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6, UInt f7 ) { -+ vassert(3+6+1+6+6+5+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<1)); -+ vassert(f4 < (1<<6)); -+ vassert(f5 < (1<<6)); -+ vassert(f6 < (1<<5)); -+ vassert(f7 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 6) | f2; -+ w = (w << 1) | f3; -+ w = (w << 6) | f4; -+ w = (w << 6) | f5; -+ w = (w << 5) | f6; -+ w = (w << 5) | f7; -+ return w; -+} -+ -+ -+//ZZ #define X0000 BITS4(0,0,0,0) -+//ZZ #define X0001 BITS4(0,0,0,1) -+//ZZ #define X0010 BITS4(0,0,1,0) -+//ZZ #define X0011 BITS4(0,0,1,1) -+//ZZ #define X0100 BITS4(0,1,0,0) -+//ZZ #define X0101 BITS4(0,1,0,1) -+//ZZ #define X0110 BITS4(0,1,1,0) -+//ZZ #define X0111 BITS4(0,1,1,1) -+//ZZ #define X1000 BITS4(1,0,0,0) -+//ZZ #define X1001 BITS4(1,0,0,1) -+//ZZ #define X1010 BITS4(1,0,1,0) -+//ZZ #define X1011 BITS4(1,0,1,1) -+//ZZ #define X1100 BITS4(1,1,0,0) -+//ZZ #define X1101 BITS4(1,1,0,1) -+//ZZ #define X1110 BITS4(1,1,1,0) -+//ZZ #define X1111 BITS4(1,1,1,1) -+/* -+#define XXXXX___(zzx7,zzx6,zzx5,zzx4,zzx3) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12)) -+ -+#define XXXXXX__(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8)) -+ -+#define XXXXX__X(zzx7,zzx6,zzx5,zzx4,zzx3,zzx0) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12) | (((zzx0) & 0xF) << 0)) -+ -+#define XXX___XX(zzx7,zzx6,zzx5,zzx1,zzx0) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx1) & 0xF) << 4) | \ -+ (((zzx0) & 0xF) << 0)) -+ -+#define XXXXXXXX(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2,zzx1,zzx0) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8) | \ -+ (((zzx1) & 0xF) << 4) | (((zzx0) & 0xF) << 0)) -+ -+#define XX______(zzx7,zzx6) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24)) -+*/ -+//ZZ /* Generate a skeletal insn that involves an a RI84 shifter operand. -+//ZZ Returns a word which is all zeroes apart from bits 25 and 11..0, -+//ZZ since it is those that encode the shifter operand (at least to the -+//ZZ extent that we care about it.) */ -+//ZZ static UInt skeletal_RI84 ( ARMRI84* ri ) -+//ZZ { -+//ZZ UInt instr; -+//ZZ if (ri->tag == ARMri84_I84) { -+//ZZ vassert(0 == (ri->ARMri84.I84.imm4 & ~0x0F)); -+//ZZ vassert(0 == (ri->ARMri84.I84.imm8 & ~0xFF)); -+//ZZ instr = 1 << 25; -+//ZZ instr |= (ri->ARMri84.I84.imm4 << 8); -+//ZZ instr |= ri->ARMri84.I84.imm8; -+//ZZ } else { -+//ZZ instr = 0 << 25; -+//ZZ instr |= iregNo(ri->ARMri84.R.reg); -+//ZZ } -+//ZZ return instr; -+//ZZ } -+//ZZ -+//ZZ /* Ditto for RI5. Resulting word is zeroes apart from bit 4 and bits -+//ZZ 11..7. */ -+//ZZ static UInt skeletal_RI5 ( ARMRI5* ri ) -+//ZZ { -+//ZZ UInt instr; -+//ZZ if (ri->tag == ARMri5_I5) { -+//ZZ UInt imm5 = ri->ARMri5.I5.imm5; -+//ZZ vassert(imm5 >= 1 && imm5 <= 31); -+//ZZ instr = 0 << 4; -+//ZZ instr |= imm5 << 7; -+//ZZ } else { -+//ZZ instr = 1 << 4; -+//ZZ instr |= iregNo(ri->ARMri5.R.reg) << 8; -+//ZZ } -+//ZZ return instr; -+//ZZ } -+ -+ -+/* Get an immediate into a register, using only that register. */ -+static UInt* imm64_to_iregNo ( UInt* p, Int xD, ULong imm64 ) -+{ -+ if (imm64 == 0) { -+ // This has to be special-cased, since the logic below -+ // will leave the register unchanged in this case. -+ // MOVZ xD, #0, LSL #0 -+ *p++ = X_3_6_2_16_5(X110, X100101, X00, 0/*imm16*/, xD); -+ return p; -+ } -+ -+ // There must be at least one non-zero halfword. Find the -+ // lowest nonzero such, and use MOVZ to install it and zero -+ // out the rest of the register. -+ UShort h[4]; -+ h[3] = (UShort)((imm64 >> 48) & 0xFFFF); -+ h[2] = (UShort)((imm64 >> 32) & 0xFFFF); -+ h[1] = (UShort)((imm64 >> 16) & 0xFFFF); -+ h[0] = (UShort)((imm64 >> 0) & 0xFFFF); -+ -+ UInt i; -+ for (i = 0; i < 4; i++) { -+ if (h[i] != 0) -+ break; -+ } -+ vassert(i < 4); -+ -+ // MOVZ xD, h[i], LSL (16*i) -+ *p++ = X_3_6_2_16_5(X110, X100101, i, h[i], xD); -+ -+ // Work on upwards through h[i], using MOVK to stuff in any -+ // remaining nonzero elements. -+ i++; -+ for (; i < 4; i++) { -+ if (h[i] == 0) -+ continue; -+ // MOVK xD, h[i], LSL (16*i) -+ *p++ = X_3_6_2_16_5(X111, X100101, i, h[i], xD); -+ } -+ -+ return p; -+} -+ -+/* Get an immediate into a register, using only that register, and -+ generating exactly 4 instructions, regardless of the value of the -+ immediate. This is used when generating sections of code that need -+ to be patched later, so as to guarantee a specific size. */ -+static UInt* imm64_to_iregNo_EXACTLY4 ( UInt* p, Int xD, ULong imm64 ) -+{ -+ UShort h[4]; -+ h[3] = (UShort)((imm64 >> 48) & 0xFFFF); -+ h[2] = (UShort)((imm64 >> 32) & 0xFFFF); -+ h[1] = (UShort)((imm64 >> 16) & 0xFFFF); -+ h[0] = (UShort)((imm64 >> 0) & 0xFFFF); -+ // Work on upwards through h[i], using MOVK to stuff in the -+ // remaining elements. -+ UInt i; -+ for (i = 0; i < 4; i++) { -+ if (i == 0) { -+ // MOVZ xD, h[0], LSL (16*0) -+ *p++ = X_3_6_2_16_5(X110, X100101, i, h[i], xD); -+ } else { -+ // MOVK xD, h[i], LSL (16*i) -+ *p++ = X_3_6_2_16_5(X111, X100101, i, h[i], xD); -+ } -+ } -+ return p; -+} -+ -+/* Check whether p points at a 4-insn sequence cooked up by -+ imm64_to_iregNo_EXACTLY4(). */ -+static Bool is_imm64_to_iregNo_EXACTLY4 ( UInt* p, Int xD, ULong imm64 ) -+{ -+ UShort h[4]; -+ h[3] = (UShort)((imm64 >> 48) & 0xFFFF); -+ h[2] = (UShort)((imm64 >> 32) & 0xFFFF); -+ h[1] = (UShort)((imm64 >> 16) & 0xFFFF); -+ h[0] = (UShort)((imm64 >> 0) & 0xFFFF); -+ // Work on upwards through h[i], using MOVK to stuff in the -+ // remaining elements. -+ UInt i; -+ for (i = 0; i < 4; i++) { -+ UInt expected; -+ if (i == 0) { -+ // MOVZ xD, h[0], LSL (16*0) -+ expected = X_3_6_2_16_5(X110, X100101, i, h[i], xD); -+ } else { -+ // MOVK xD, h[i], LSL (16*i) -+ expected = X_3_6_2_16_5(X111, X100101, i, h[i], xD); -+ } -+ if (p[i] != expected) -+ return False; -+ } -+ return True; -+} -+ -+ -+/* Generate a 8 bit store or 8-to-64 unsigned widening load from/to -+ rD, using the given amode for the address. */ -+static UInt* do_load_or_store8 ( UInt* p, -+ Bool isLoad, UInt wD, ARM64AMode* am ) -+{ -+ vassert(wD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STURB Wd, [Xn|SP + simm9]: 00 111000 000 simm9 00 n d -+ LDURB Wd, [Xn|SP + simm9]: 00 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt instr = X_2_6_3_9_2_5_5(X00, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, -+ iregNo(am->ARM64am.RI9.reg), wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STRB Wd, [Xn|SP + uimm12 * 1]: 00 111 001 00 imm12 n d -+ LDRB Wd, [Xn|SP + uimm12 * 1]: 00 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 1); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X00, X111001, isLoad ? X01 : X00, -+ uimm12, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STRB Xd, [Xn|SP, Xm]: 00 111 000 001 m 011 0 10 n d -+ LDRB Xd, [Xn|SP, Xm]: 00 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X001, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store8"); -+ vassert(0); -+} -+ -+ -+/* Generate a 16 bit store or 16-to-64 unsigned widening load from/to -+ rD, using the given amode for the address. */ -+static UInt* do_load_or_store16 ( UInt* p, -+ Bool isLoad, UInt wD, ARM64AMode* am ) -+{ -+ vassert(wD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STURH Wd, [Xn|SP + simm9]: 01 111000 000 simm9 00 n d -+ LDURH Wd, [Xn|SP + simm9]: 01 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt instr = X_2_6_3_9_2_5_5(X01, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, -+ iregNo(am->ARM64am.RI9.reg), wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STRH Wd, [Xn|SP + uimm12 * 2]: 01 111 001 00 imm12 n d -+ LDRH Wd, [Xn|SP + uimm12 * 2]: 01 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 2); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X01, X111001, isLoad ? X01 : X00, -+ uimm12, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STRH Xd, [Xn|SP, Xm]: 01 111 000 001 m 011 0 10 n d -+ LDRH Xd, [Xn|SP, Xm]: 01 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X011, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store16"); -+ vassert(0); -+} -+ -+ -+/* Generate a 32 bit store or 32-to-64 unsigned widening load from/to -+ rD, using the given amode for the address. */ -+static UInt* do_load_or_store32 ( UInt* p, -+ Bool isLoad, UInt wD, ARM64AMode* am ) -+{ -+ vassert(wD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STUR Wd, [Xn|SP + simm9]: 10 111000 000 simm9 00 n d -+ LDUR Wd, [Xn|SP + simm9]: 10 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt instr = X_2_6_3_9_2_5_5(X10, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, -+ iregNo(am->ARM64am.RI9.reg), wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STR Wd, [Xn|SP + uimm12 * 4]: 10 111 001 00 imm12 n d -+ LDR Wd, [Xn|SP + uimm12 * 4]: 10 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 4); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X10, X111001, isLoad ? X01 : X00, -+ uimm12, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STR Wd, [Xn|SP, Xm]: 10 111 000 001 m 011 0 10 n d -+ LDR Wd, [Xn|SP, Xm]: 10 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X101, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store32"); -+ vassert(0); -+} -+ -+ -+/* Generate a 64 bit load or store to/from xD, using the given amode -+ for the address. */ -+static UInt* do_load_or_store64 ( UInt* p, -+ Bool isLoad, UInt xD, ARM64AMode* am ) -+{ -+ /* In all these cases, Rn can't be 31 since that means SP. */ -+ vassert(xD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STUR Xd, [Xn|SP + simm9]: 11 111000 000 simm9 00 n d -+ LDUR Xd, [Xn|SP + simm9]: 11 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt xN = iregNo(am->ARM64am.RI9.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_3_9_2_5_5(X11, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, xN, xD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STR Xd, [Xn|SP + uimm12 * 8]: 11 111 001 00 imm12 n d -+ LDR Xd, [Xn|SP + uimm12 * 8]: 11 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 8); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X11, X111001, isLoad ? X01 : X00, -+ uimm12, xN, xD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STR Xd, [Xn|SP, Xm]: 11 111 000 001 m 011 0 10 n d -+ LDR Xd, [Xn|SP, Xm]: 11 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X111, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, xD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store64"); -+ vassert(0); -+} -+ -+ -+/* Emit an instruction into buf and return the number of bytes used. -+ Note that buf is not the insn's final place, and therefore it is -+ imperative to emit position-independent code. If the emitted -+ instruction was a profiler inc, set *is_profInc to True, else -+ leave it unchanged. */ -+ -+Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, -+ UChar* buf, Int nbuf, ARM64Instr* i, -+ Bool mode64, -+ void* disp_cp_chain_me_to_slowEP, -+ void* disp_cp_chain_me_to_fastEP, -+ void* disp_cp_xindir, -+ void* disp_cp_xassisted ) -+{ -+ UInt* p = (UInt*)buf; -+ vassert(nbuf >= 32); -+ vassert(mode64 == True); -+ vassert(0 == (((HWord)buf) & 3)); -+ -+ switch (i->tag) { -+ case ARM64in_Arith: { -+ UInt rD = iregNo(i->ARM64in.Arith.dst); -+ UInt rN = iregNo(i->ARM64in.Arith.argL); -+ ARM64RIA* argR = i->ARM64in.Arith.argR; -+ switch (argR->tag) { -+ case ARM64riA_I12: -+ *p++ = X_2_6_2_12_5_5( -+ i->ARM64in.Arith.isAdd ? X10 : X11, -+ X010001, -+ argR->ARM64riA.I12.shift == 12 ? X01 : X00, -+ argR->ARM64riA.I12.imm12, rN, rD -+ ); -+ break; -+ case ARM64riA_R: { -+ UInt rM = iregNo(i->ARM64in.Arith.argR->ARM64riA.R.reg); -+ *p++ = X_3_8_5_6_5_5( -+ i->ARM64in.Arith.isAdd ? X100 : X110, -+ X01011000, rM, X000000, rN, rD -+ ); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Cmp: { -+ UInt rD = 31; /* XZR, we are going to dump the result */ -+ UInt rN = iregNo(i->ARM64in.Cmp.argL); -+ ARM64RIA* argR = i->ARM64in.Cmp.argR; -+ Bool is64 = i->ARM64in.Cmp.is64; -+ switch (argR->tag) { -+ case ARM64riA_I12: -+ /* 1 11 10001 sh imm12 Rn Rd = SUBS Xd, Xn, #imm */ -+ /* 0 11 10001 sh imm12 Rn Rd = SUBS Wd, Wn, #imm */ -+ *p++ = X_2_6_2_12_5_5( -+ is64 ? X11 : X01, X110001, -+ argR->ARM64riA.I12.shift == 12 ? X01 : X00, -+ argR->ARM64riA.I12.imm12, rN, rD); -+ break; -+ case ARM64riA_R: { -+ /* 1 11 01011 00 0 Rm 000000 Rn Rd = SUBS Xd, Xn, Xm */ -+ /* 0 11 01011 00 0 Rm 000000 Rn Rd = SUBS Wd, Wn, Wm */ -+ UInt rM = iregNo(i->ARM64in.Cmp.argR->ARM64riA.R.reg); -+ *p++ = X_3_8_5_6_5_5(is64 ? X111 : X011, -+ X01011000, rM, X000000, rN, rD); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Logic: { -+ UInt rD = iregNo(i->ARM64in.Logic.dst); -+ UInt rN = iregNo(i->ARM64in.Logic.argL); -+ ARM64RIL* argR = i->ARM64in.Logic.argR; -+ UInt opc = 0; /* invalid */ -+ vassert(rD < 31); -+ vassert(rN < 31); -+ switch (i->ARM64in.Logic.op) { -+ case ARM64lo_OR: opc = X101; break; -+ case ARM64lo_AND: opc = X100; break; -+ case ARM64lo_XOR: opc = X110; break; -+ default: break; -+ } -+ vassert(opc != 0); -+ switch (argR->tag) { -+ case ARM64riL_I13: { -+ /* 1 01 100100 N immR immS Rn Rd = ORR , Xn, #imm */ -+ /* 1 00 100100 N immR immS Rn Rd = AND , Xn, #imm */ -+ /* 1 10 100100 N immR immS Rn Rd = EOR , Xn, #imm */ -+ *p++ = X_3_6_1_6_6_5_5( -+ opc, X100100, argR->ARM64riL.I13.bitN, -+ argR->ARM64riL.I13.immR, argR->ARM64riL.I13.immS, -+ rN, rD -+ ); -+ break; -+ } -+ case ARM64riL_R: { -+ /* 1 01 01010 00 0 m 000000 n d = ORR Xd, Xn, Xm */ -+ /* 1 00 01010 00 0 m 000000 n d = AND Xd, Xn, Xm */ -+ /* 1 10 01010 00 0 m 000000 n d = EOR Xd, Xn, Xm */ -+ UInt rM = iregNo(argR->ARM64riL.R.reg); -+ vassert(rM < 31); -+ *p++ = X_3_8_5_6_5_5(opc, X01010000, rM, X000000, rN, rD); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Test: { -+ UInt rD = 31; /* XZR, we are going to dump the result */ -+ UInt rN = iregNo(i->ARM64in.Test.argL); -+ ARM64RIL* argR = i->ARM64in.Test.argR; -+ switch (argR->tag) { -+ case ARM64riL_I13: { -+ /* 1 11 100100 N immR immS Rn Rd = ANDS Xd, Xn, #imm */ -+ *p++ = X_3_6_1_6_6_5_5( -+ X111, X100100, argR->ARM64riL.I13.bitN, -+ argR->ARM64riL.I13.immR, argR->ARM64riL.I13.immS, -+ rN, rD -+ ); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Shift: { -+ UInt rD = iregNo(i->ARM64in.Shift.dst); -+ UInt rN = iregNo(i->ARM64in.Shift.argL); -+ ARM64RI6* argR = i->ARM64in.Shift.argR; -+ vassert(rD < 31); -+ vassert(rN < 31); -+ switch (argR->tag) { -+ case ARM64ri6_I6: { -+ /* 110 1001101 (63-sh) (64-sh) nn dd LSL Xd, Xn, sh */ -+ /* 110 1001101 sh 63 nn dd LSR Xd, Xn, sh */ -+ /* 100 1001101 sh 63 nn dd ASR Xd, Xn, sh */ -+ UInt sh = argR->ARM64ri6.I6.imm6; -+ vassert(sh > 0 && sh < 64); -+ switch (i->ARM64in.Shift.op) { -+ case ARM64sh_SHL: -+ *p++ = X_3_6_1_6_6_5_5(X110, X100110, -+ 1, 64-sh, 63-sh, rN, rD); -+ break; -+ case ARM64sh_SHR: -+ *p++ = X_3_6_1_6_6_5_5(X110, X100110, 1, sh, 63, rN, rD); -+ break; -+ case ARM64sh_SAR: -+ *p++ = X_3_6_1_6_6_5_5(X100, X100110, 1, sh, 63, rN, rD); -+ break; -+ default: -+ vassert(0); -+ } -+ break; -+ } -+ case ARM64ri6_R: { -+ /* 100 1101 0110 mm 001000 nn dd LSL Xd, Xn, Xm */ -+ /* 100 1101 0110 mm 001001 nn dd LSR Xd, Xn, Xm */ -+ /* 100 1101 0110 mm 001010 nn dd ASR Xd, Xn, Xm */ -+ UInt rM = iregNo(argR->ARM64ri6.R.reg); -+ vassert(rM < 31); -+ UInt subOpc = 0; -+ switch (i->ARM64in.Shift.op) { -+ case ARM64sh_SHL: subOpc = X001000; break; -+ case ARM64sh_SHR: subOpc = X001001; break; -+ case ARM64sh_SAR: subOpc = X001010; break; -+ default: vassert(0); -+ } -+ *p++ = X_3_8_5_6_5_5(X100, X11010110, rM, subOpc, rN, rD); -+ break; -+ } -+ default: -+ vassert(0); -+ } -+ goto done; -+ } -+ case ARM64in_Unary: { -+ UInt rDst = iregNo(i->ARM64in.Unary.dst); -+ UInt rSrc = iregNo(i->ARM64in.Unary.src); -+ switch (i->ARM64in.Unary.op) { -+ case ARM64un_CLZ: -+ /* 1 10 1101 0110 00000 00010 0 nn dd CLZ Xd, Xn */ -+ /* 1 10 1101 0110 00000 00010 1 nn dd CLS Xd, Xn (unimp) */ -+ *p++ = X_3_8_5_6_5_5(X110, -+ X11010110, X00000, X000100, rSrc, rDst); -+ goto done; -+ case ARM64un_NEG: -+ /* 1 10 01011 000 m 000000 11111 d NEG Xd,Xm */ -+ /* 0 10 01011 000 m 000000 11111 d NEG Wd,Wm (unimp) */ -+ *p++ = X_3_8_5_6_5_5(X110, -+ X01011000, rSrc, X000000, X11111, rDst); -+ goto done; -+ case ARM64un_NOT: { -+ /* 1 01 01010 00 1 m 000000 11111 d MVN Xd,Xm */ -+ *p++ = X_3_8_5_6_5_5(X101, -+ X01010001, rSrc, X000000, X11111, rDst); -+ goto done; -+ } -+ default: -+ break; -+ } -+ goto bad; -+ } -+ case ARM64in_MovI: { -+ /* We generate the "preferred form", ORR Xd, XZR, Xm -+ 101 01010 00 0 m 000000 11111 d -+ */ -+ UInt instr = 0xAA0003E0; -+ UInt d = iregNo(i->ARM64in.MovI.dst); -+ UInt m = iregNo(i->ARM64in.MovI.src); -+ *p++ = instr | ((m & 31) << 16) | ((d & 31) << 0); -+ goto done; -+ } -+ case ARM64in_Imm64: { -+ p = imm64_to_iregNo( p, iregNo(i->ARM64in.Imm64.dst), -+ i->ARM64in.Imm64.imm64 ); -+ goto done; -+ } -+ case ARM64in_LdSt64: { -+ p = do_load_or_store64( p, i->ARM64in.LdSt64.isLoad, -+ iregNo(i->ARM64in.LdSt64.rD), -+ i->ARM64in.LdSt64.amode ); -+ goto done; -+ } -+ case ARM64in_LdSt32: { -+ p = do_load_or_store32( p, i->ARM64in.LdSt32.isLoad, -+ iregNo(i->ARM64in.LdSt32.rD), -+ i->ARM64in.LdSt32.amode ); -+ goto done; -+ } -+ case ARM64in_LdSt16: { -+ p = do_load_or_store16( p, i->ARM64in.LdSt16.isLoad, -+ iregNo(i->ARM64in.LdSt16.rD), -+ i->ARM64in.LdSt16.amode ); -+ goto done; -+ } -+ case ARM64in_LdSt8: { -+ p = do_load_or_store8( p, i->ARM64in.LdSt8.isLoad, -+ iregNo(i->ARM64in.LdSt8.rD), -+ i->ARM64in.LdSt8.amode ); -+ goto done; -+ } -+//ZZ case ARMin_LdSt32: -+//ZZ case ARMin_LdSt8U: { -+//ZZ UInt bL, bB; -+//ZZ HReg rD; -+//ZZ ARMAMode1* am; -+//ZZ ARMCondCode cc; -+//ZZ if (i->tag == ARMin_LdSt32) { -+//ZZ bB = 0; -+//ZZ bL = i->ARMin.LdSt32.isLoad ? 1 : 0; -+//ZZ am = i->ARMin.LdSt32.amode; -+//ZZ rD = i->ARMin.LdSt32.rD; -+//ZZ cc = i->ARMin.LdSt32.cc; -+//ZZ } else { -+//ZZ bB = 1; -+//ZZ bL = i->ARMin.LdSt8U.isLoad ? 1 : 0; -+//ZZ am = i->ARMin.LdSt8U.amode; -+//ZZ rD = i->ARMin.LdSt8U.rD; -+//ZZ cc = i->ARMin.LdSt8U.cc; -+//ZZ } -+//ZZ vassert(cc != ARMcc_NV); -+//ZZ if (am->tag == ARMam1_RI) { -+//ZZ Int simm12; -+//ZZ UInt instr, bP; -+//ZZ if (am->ARMam1.RI.simm13 < 0) { -+//ZZ bP = 0; -+//ZZ simm12 = -am->ARMam1.RI.simm13; -+//ZZ } else { -+//ZZ bP = 1; -+//ZZ simm12 = am->ARMam1.RI.simm13; -+//ZZ } -+//ZZ vassert(simm12 >= 0 && simm12 <= 4095); -+//ZZ instr = XXXXX___(cc,X0101,BITS4(bP,bB,0,bL), -+//ZZ iregNo(am->ARMam1.RI.reg), -+//ZZ iregNo(rD)); -+//ZZ instr |= simm12; -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } else { -+//ZZ // RR case -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+//ZZ case ARMin_LdSt16: { -+//ZZ HReg rD = i->ARMin.LdSt16.rD; -+//ZZ UInt bS = i->ARMin.LdSt16.signedLoad ? 1 : 0; -+//ZZ UInt bL = i->ARMin.LdSt16.isLoad ? 1 : 0; -+//ZZ ARMAMode2* am = i->ARMin.LdSt16.amode; -+//ZZ ARMCondCode cc = i->ARMin.LdSt16.cc; -+//ZZ vassert(cc != ARMcc_NV); -+//ZZ if (am->tag == ARMam2_RI) { -+//ZZ HReg rN = am->ARMam2.RI.reg; -+//ZZ Int simm8; -+//ZZ UInt bP, imm8hi, imm8lo, instr; -+//ZZ if (am->ARMam2.RI.simm9 < 0) { -+//ZZ bP = 0; -+//ZZ simm8 = -am->ARMam2.RI.simm9; -+//ZZ } else { -+//ZZ bP = 1; -+//ZZ simm8 = am->ARMam2.RI.simm9; -+//ZZ } -+//ZZ vassert(simm8 >= 0 && simm8 <= 255); -+//ZZ imm8hi = (simm8 >> 4) & 0xF; -+//ZZ imm8lo = simm8 & 0xF; -+//ZZ vassert(!(bL == 0 && bS == 1)); // "! signed store" -+//ZZ /**/ if (bL == 0 && bS == 0) { -+//ZZ // strh -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,0), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1011, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } -+//ZZ else if (bL == 1 && bS == 0) { -+//ZZ // ldrh -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1011, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } -+//ZZ else if (bL == 1 && bS == 1) { -+//ZZ // ldrsh -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1111, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } -+//ZZ else vassert(0); // ill-constructed insn -+//ZZ } else { -+//ZZ // RR case -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+//ZZ case ARMin_Ld8S: { -+//ZZ HReg rD = i->ARMin.Ld8S.rD; -+//ZZ ARMAMode2* am = i->ARMin.Ld8S.amode; -+//ZZ ARMCondCode cc = i->ARMin.Ld8S.cc; -+//ZZ vassert(cc != ARMcc_NV); -+//ZZ if (am->tag == ARMam2_RI) { -+//ZZ HReg rN = am->ARMam2.RI.reg; -+//ZZ Int simm8; -+//ZZ UInt bP, imm8hi, imm8lo, instr; -+//ZZ if (am->ARMam2.RI.simm9 < 0) { -+//ZZ bP = 0; -+//ZZ simm8 = -am->ARMam2.RI.simm9; -+//ZZ } else { -+//ZZ bP = 1; -+//ZZ simm8 = am->ARMam2.RI.simm9; -+//ZZ } -+//ZZ vassert(simm8 >= 0 && simm8 <= 255); -+//ZZ imm8hi = (simm8 >> 4) & 0xF; -+//ZZ imm8lo = simm8 & 0xF; -+//ZZ // ldrsb -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1101, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } else { -+//ZZ // RR case -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+ -+ case ARM64in_XDirect: { -+ /* NB: what goes on here has to be very closely coordinated -+ with chainXDirect_ARM64 and unchainXDirect_ARM64 below. */ -+ /* We're generating chain-me requests here, so we need to be -+ sure this is actually allowed -- no-redir translations -+ can't use chain-me's. Hence: */ -+ vassert(disp_cp_chain_me_to_slowEP != NULL); -+ vassert(disp_cp_chain_me_to_fastEP != NULL); -+ -+ /* Use ptmp for backpatching conditional jumps. */ -+ UInt* ptmp = NULL; -+ -+ /* First off, if this is conditional, create a conditional -+ jump over the rest of it. Or at least, leave a space for -+ it that we will shortly fill in. */ -+ if (i->ARM64in.XDirect.cond != ARM64cc_AL) { -+ vassert(i->ARM64in.XDirect.cond != ARM64cc_NV); -+ ptmp = p; -+ *p++ = 0; -+ } -+ -+ /* Update the guest PC. */ -+ /* imm64 x9, dstGA */ -+ /* str x9, amPC */ -+ p = imm64_to_iregNo(p, /*x*/9, i->ARM64in.XDirect.dstGA); -+ p = do_load_or_store64(p, False/*!isLoad*/, -+ /*x*/9, i->ARM64in.XDirect.amPC); -+ -+ /* --- FIRST PATCHABLE BYTE follows --- */ -+ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're -+ calling to) backs up the return address, so as to find the -+ address of the first patchable byte. So: don't change the -+ number of instructions (5) below. */ -+ /* movw x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[15:0] */ -+ /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[31:15], lsl 16 */ -+ /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[47:32], lsl 32 */ -+ /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[63:48], lsl 48 */ -+ /* blr x9 */ -+ void* disp_cp_chain_me -+ = i->ARM64in.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP -+ : disp_cp_chain_me_to_slowEP; -+ p = imm64_to_iregNo_EXACTLY4(p, /*x*/9, -+ Ptr_to_ULong(disp_cp_chain_me)); -+ *p++ = 0xD63F0120; -+ /* --- END of PATCHABLE BYTES --- */ -+ -+ /* Fix up the conditional jump, if there was one. */ -+ if (i->ARM64in.XDirect.cond != ARM64cc_AL) { -+ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */ -+ vassert(delta > 0 && delta < 40); -+ vassert((delta & 3) == 0); -+ UInt notCond = 1 ^ (UInt)i->ARM64in.XDirect.cond; -+ vassert(notCond <= 13); /* Neither AL nor NV */ -+ vassert(ptmp != NULL); -+ delta = delta >> 2; -+ *ptmp = X_8_19_1_4(X01010100, delta & ((1<<19)-1), 0, notCond); -+ } -+ goto done; -+ } -+ -+ case ARM64in_XIndir: { -+ // XIndir is more or less the same as XAssisted, except -+ // we don't have a trc value to hand back, so there's no -+ // write to r21 -+ /* Use ptmp for backpatching conditional jumps. */ -+ //UInt* ptmp = NULL; -+ -+ /* First off, if this is conditional, create a conditional -+ jump over the rest of it. Or at least, leave a space for -+ it that we will shortly fill in. */ -+ if (i->ARM64in.XIndir.cond != ARM64cc_AL) { -+ vassert(0); //ATC -+//ZZ vassert(i->ARMin.XIndir.cond != ARMcc_NV); -+//ZZ ptmp = p; -+//ZZ *p++ = 0; -+ } -+ -+ /* Update the guest PC. */ -+ /* str r-dstGA, amPC */ -+ p = do_load_or_store64(p, False/*!isLoad*/, -+ iregNo(i->ARM64in.XIndir.dstGA), -+ i->ARM64in.XIndir.amPC); -+ -+ /* imm64 x9, VG_(disp_cp_xindir) */ -+ /* br x9 */ -+ p = imm64_to_iregNo(p, /*x*/9, Ptr_to_ULong(disp_cp_xindir)); -+ *p++ = 0xD61F0120; /* br x9 */ -+ -+ /* Fix up the conditional jump, if there was one. */ -+ if (i->ARM64in.XIndir.cond != ARM64cc_AL) { -+ vassert(0); //ATC -+//ZZ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */ -+//ZZ vassert(delta > 0 && delta < 40); -+//ZZ vassert((delta & 3) == 0); -+//ZZ UInt notCond = 1 ^ (UInt)i->ARMin.XIndir.cond; -+//ZZ vassert(notCond <= 13); /* Neither AL nor NV */ -+//ZZ delta = (delta >> 2) - 2; -+//ZZ *ptmp = XX______(notCond, X1010) | (delta & 0xFFFFFF); -+ } -+ goto done; -+ } -+ -+ case ARM64in_XAssisted: { -+ /* Use ptmp for backpatching conditional jumps. */ -+ UInt* ptmp = NULL; -+ -+ /* First off, if this is conditional, create a conditional -+ jump over the rest of it. Or at least, leave a space for -+ it that we will shortly fill in. I think this can only -+ ever happen when VEX is driven by the switchbacker. */ -+ if (i->ARM64in.XAssisted.cond != ARM64cc_AL) { -+ vassert(i->ARM64in.XDirect.cond != ARM64cc_NV); -+ ptmp = p; -+ *p++ = 0; -+ } -+ -+ /* Update the guest PC. */ -+ /* str r-dstGA, amPC */ -+ p = do_load_or_store64(p, False/*!isLoad*/, -+ iregNo(i->ARM64in.XAssisted.dstGA), -+ i->ARM64in.XAssisted.amPC); -+ -+ /* movw r21, $magic_number */ -+ UInt trcval = 0; -+ switch (i->ARM64in.XAssisted.jk) { -+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break; -+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break; -+ //case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break; -+ //case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break; -+ //case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; -+ //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; -+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -+ //case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; -+ //case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; -+ //case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; -+ //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; -+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break; -+ /* We don't expect to see the following being assisted. */ -+ //case Ijk_Ret: -+ //case Ijk_Call: -+ /* fallthrough */ -+ default: -+ ppIRJumpKind(i->ARM64in.XAssisted.jk); -+ vpanic("emit_ARM64Instr.ARM64in_XAssisted: " -+ "unexpected jump kind"); -+ } -+ vassert(trcval != 0); -+ p = imm64_to_iregNo(p, /*x*/21, (ULong)trcval); -+ -+ /* imm64 x9, VG_(disp_cp_xassisted) */ -+ /* br x9 */ -+ p = imm64_to_iregNo(p, /*x*/9, Ptr_to_ULong(disp_cp_xassisted)); -+ *p++ = 0xD61F0120; /* br x9 */ -+ -+ /* Fix up the conditional jump, if there was one. */ -+ if (i->ARM64in.XAssisted.cond != ARM64cc_AL) { -+ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */ -+ vassert(delta > 0 && delta < 40); -+ vassert((delta & 3) == 0); -+ UInt notCond = 1 ^ (UInt)i->ARM64in.XDirect.cond; -+ vassert(notCond <= 13); /* Neither AL nor NV */ -+ vassert(ptmp != NULL); -+ delta = delta >> 2; -+ *ptmp = X_8_19_1_4(X01010100, delta & ((1<<19)-1), 0, notCond); -+ } -+ goto done; -+ } -+ -+ case ARM64in_CSel: { -+ /* 100 1101 0100 mm cond 00 nn dd = CSEL Xd, Xn, Xm, cond */ -+ UInt dd = iregNo(i->ARM64in.CSel.dst); -+ UInt nn = iregNo(i->ARM64in.CSel.argL); -+ UInt mm = iregNo(i->ARM64in.CSel.argR); -+ UInt cond = (UInt)i->ARM64in.CSel.cond; -+ vassert(dd < 31 && nn < 31 && mm < 31 && cond < 16); -+ *p++ = X_3_8_5_6_5_5(X100, X11010100, mm, cond << 2, nn, dd); -+ goto done; -+ } -+ -+ case ARM64in_Call: { -+ /* We'll use x9 as a scratch register to put the target -+ address in. */ -+ if (i->ARM64in.Call.cond != ARM64cc_AL -+ && i->ARM64in.Call.rloc.pri != RLPri_None) { -+ /* The call might not happen (it isn't unconditional) and -+ it returns a result. In this case we will need to -+ generate a control flow diamond to put 0x555..555 in -+ the return register(s) in the case where the call -+ doesn't happen. If this ever becomes necessary, maybe -+ copy code from the 32-bit ARM equivalent. Until that -+ day, just give up. */ -+ goto bad; -+ } -+ -+ UInt* ptmp = NULL; -+ if (i->ARM64in.Call.cond != ARM64cc_AL) { -+ /* Create a hole to put a conditional branch in. We'll -+ patch it once we know the branch length. */ -+ ptmp = p; -+ *p++ = 0; -+ } -+ -+ // x9 = &target -+ p = imm64_to_iregNo( (UInt*)p, -+ /*x*/9, (ULong)i->ARM64in.Call.target ); -+ // blr x9 -+ *p++ = 0xD63F0120; -+ -+ // Patch the hole if necessary -+ if (i->ARM64in.Call.cond != ARM64cc_AL) { -+ ULong dist = (ULong)(p - ptmp); -+ /* imm64_to_iregNo produces between 1 and 4 insns, and -+ then there's the BLR itself. Hence: */ -+ vassert(dist >= 2 && dist <= 5); -+ vassert(ptmp != NULL); -+ // 01010100 simm19 0 cond = B.cond (here + simm19 << 2) -+ *ptmp = X_8_19_1_4(X01010100, dist, 0, -+ 1 ^ (UInt)i->ARM64in.Call.cond); -+ } else { -+ vassert(ptmp == NULL); -+ } -+ -+ goto done; -+ } -+ -+ case ARM64in_AddToSP: { -+ /* 10,0 10001 00 imm12 11111 11111 ADD xsp, xsp, #imm12 -+ 11,0 10001 00 imm12 11111 11111 SUB xsp, xsp, #imm12 -+ */ -+ Int simm12 = i->ARM64in.AddToSP.simm; -+ vassert(-4096 < simm12 && simm12 < 4096); -+ vassert(0 == (simm12 & 0xF)); -+ if (simm12 >= 0) { -+ *p++ = X_2_6_2_12_5_5(X10, X010001, X00, simm12, X11111, X11111); -+ } else { -+ *p++ = X_2_6_2_12_5_5(X11, X010001, X00, -simm12, X11111, X11111); -+ } -+ goto done; -+ } -+ -+ case ARM64in_FromSP: { -+ /* 10,0 10001 00 0..(12)..0 11111 dd MOV Xd, xsp */ -+ UInt dd = iregNo(i->ARM64in.FromSP.dst); -+ vassert(dd < 31); -+ *p++ = X_2_6_2_12_5_5(X10, X010001, X00, 0, X11111, dd); -+ goto done; -+ } -+ -+ case ARM64in_Mul: { -+ /* 100 11011 110 mm 011111 nn dd UMULH Xd, Xn,Xm -+ 100 11011 010 mm 011111 nn dd SMULH Xd, Xn,Xm -+ 100 11011 000 mm 011111 nn dd MUL Xd, Xn,Xm -+ */ -+ UInt dd = iregNo(i->ARM64in.Mul.dst); -+ UInt nn = iregNo(i->ARM64in.Mul.argL); -+ UInt mm = iregNo(i->ARM64in.Mul.argR); -+ vassert(dd < 31 && nn < 31 && mm < 31); -+ switch (i->ARM64in.Mul.op) { -+ case ARM64mul_ZX: -+ *p++ = X_3_8_5_6_5_5(X100, X11011110, mm, X011111, nn, dd); -+ goto done; -+ //case ARM64mul_SX: -+ // *p++ = X_3_8_5_6_5_5(X100, X11011010, mm, X011111, nn, dd); -+ // goto done; -+ case ARM64mul_PLAIN: -+ *p++ = X_3_8_5_6_5_5(X100, X11011000, mm, X011111, nn, dd); -+ goto done; -+ default: -+ vassert(0); -+ } -+ goto bad; -+ } -+//ZZ case ARMin_LdrEX: { -+//ZZ /* E1D42F9F ldrexb r2, [r4] -+//ZZ E1F42F9F ldrexh r2, [r4] -+//ZZ E1942F9F ldrex r2, [r4] -+//ZZ E1B42F9F ldrexd r2, r3, [r4] -+//ZZ */ -+//ZZ switch (i->ARMin.LdrEX.szB) { -+//ZZ case 1: *p++ = 0xE1D42F9F; goto done; -+//ZZ case 2: *p++ = 0xE1F42F9F; goto done; -+//ZZ case 4: *p++ = 0xE1942F9F; goto done; -+//ZZ case 8: *p++ = 0xE1B42F9F; goto done; -+//ZZ default: break; -+//ZZ } -+//ZZ goto bad; -+//ZZ } -+//ZZ case ARMin_StrEX: { -+//ZZ /* E1C40F92 strexb r0, r2, [r4] -+//ZZ E1E40F92 strexh r0, r2, [r4] -+//ZZ E1840F92 strex r0, r2, [r4] -+//ZZ E1A40F92 strexd r0, r2, r3, [r4] -+//ZZ */ -+//ZZ switch (i->ARMin.StrEX.szB) { -+//ZZ case 1: *p++ = 0xE1C40F92; goto done; -+//ZZ case 2: *p++ = 0xE1E40F92; goto done; -+//ZZ case 4: *p++ = 0xE1840F92; goto done; -+//ZZ case 8: *p++ = 0xE1A40F92; goto done; -+//ZZ default: break; -+//ZZ } -+//ZZ goto bad; -+//ZZ } -+ case ARM64in_VLdStS: { -+ /* 10 111101 01 imm12 n t LDR St, [Xn|SP, #imm12 * 4] -+ 10 111101 00 imm12 n t STR St, [Xn|SP, #imm12 * 4] -+ */ -+ UInt sD = dregNo(i->ARM64in.VLdStS.sD); -+ UInt rN = iregNo(i->ARM64in.VLdStS.rN); -+ UInt uimm12 = i->ARM64in.VLdStS.uimm12; -+ Bool isLD = i->ARM64in.VLdStS.isLoad; -+ vassert(uimm12 < 16384 && 0 == (uimm12 & 3)); -+ uimm12 >>= 2; -+ vassert(uimm12 < (1<<12)); -+ vassert(sD < 32); -+ vassert(rN < 31); -+ *p++ = X_2_6_2_12_5_5(X10, X111101, isLD ? X01 : X00, -+ uimm12, rN, sD); -+ goto done; -+ } -+ case ARM64in_VLdStD: { -+ /* 11 111101 01 imm12 n t LDR Dt, [Xn|SP, #imm12 * 8] -+ 11 111101 00 imm12 n t STR Dt, [Xn|SP, #imm12 * 8] -+ */ -+ UInt dD = dregNo(i->ARM64in.VLdStD.dD); -+ UInt rN = iregNo(i->ARM64in.VLdStD.rN); -+ UInt uimm12 = i->ARM64in.VLdStD.uimm12; -+ Bool isLD = i->ARM64in.VLdStD.isLoad; -+ vassert(uimm12 < 32768 && 0 == (uimm12 & 7)); -+ uimm12 >>= 3; -+ vassert(uimm12 < (1<<12)); -+ vassert(dD < 32); -+ vassert(rN < 31); -+ *p++ = X_2_6_2_12_5_5(X11, X111101, isLD ? X01 : X00, -+ uimm12, rN, dD); -+ goto done; -+ } -+ case ARM64in_VLdStQ: { -+ /* 0100 1100 0000 0000 0111 11 rN rQ st1 {vQ.2d}, [] -+ 0100 1100 0100 0000 0111 11 rN rQ ld1 {vQ.2d}, [] -+ */ -+ UInt rQ = qregNo(i->ARM64in.VLdStQ.rQ); -+ UInt rN = iregNo(i->ARM64in.VLdStQ.rN); -+ vassert(rQ < 32); -+ vassert(rN < 31); -+ if (i->ARM64in.VLdStQ.isLoad) { -+ *p++ = 0x4C407C00 | (rN << 5) | rQ; -+ } else { -+ *p++ = 0x4C007C00 | (rN << 5) | rQ; -+ } -+ goto done; -+ } -+ case ARM64in_VCvtI2F: { -+ /* 31 28 23 21 20 18 15 9 4 -+ 000 11110 00 1 00 010 000000 n d SCVTF Sd, Wn -+ 000 11110 01 1 00 010 000000 n d SCVTF Dd, Wn -+ 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn x -+ 100 11110 01 1 00 010 000000 n d SCVTF Dd, Xn -+ 000 11110 00 1 00 011 000000 n d UCVTF Sd, Wn -+ 000 11110 01 1 00 011 000000 n d UCVTF Dd, Wn -+ 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn -+ 100 11110 01 1 00 011 000000 n d UCVTF Dd, Xn -+ */ -+ UInt rN = iregNo(i->ARM64in.VCvtI2F.rS); -+ UInt rD = dregNo(i->ARM64in.VCvtI2F.rD); -+ ARM64CvtOp how = i->ARM64in.VCvtI2F.how; -+ /* Just handle cases as they show up. */ -+ switch (how) { -+ case ARM64cvt_F32_I32S: /* SCVTF Sd, Wn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100010, X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I32S: /* SCVTF Dd, Wn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100010, X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I64S: /* SCVTF Sd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X00100010, X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64S: /* SCVTF Dd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100010, X000000, rN, rD); -+ break; -+ /* UCVTF Sd, Wn ATC */ -+ case ARM64cvt_F64_I32U: /* UCVTF Dd, Wn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100011, X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I64U: /* UCVTF Sd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X00100011, X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64U: /* UCVTF Dd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100011, X000000, rN, rD); -+ break; -+ default: -+ goto bad; //ATC -+ } -+ goto done; -+ } -+ case ARM64in_VCvtF2I: { -+ /* 30 23 20 18 15 9 4 -+ sf 00,11110,0x 1 00 000,000000 n d FCVTNS Rd, Fn (round to -+ sf 00,11110,0x 1 00 001,000000 n d FCVTNU Rd, Fn nearest) -+ ---------------- 01 -------------- FCVTP-------- (round to +inf) -+ ---------------- 10 -------------- FCVTM-------- (round to -inf) -+ ---------------- 11 -------------- FCVTZ-------- (round to zero) -+ -+ Rd is Xd when sf==1, Wd when sf==0 -+ Fn is Dn when x==1, Sn when x==0 -+ 20:19 carry the rounding mode, using the same encoding as FPCR -+ */ -+ UInt rD = iregNo(i->ARM64in.VCvtF2I.rD); -+ UInt rN = dregNo(i->ARM64in.VCvtF2I.rS); -+ ARM64CvtOp how = i->ARM64in.VCvtF2I.how; -+ UChar armRM = i->ARM64in.VCvtF2I.armRM; -+ /* Just handle cases as they show up. */ -+ switch (how) { -+ case ARM64cvt_F64_I32S: /* FCVTxS Wd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100000 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I32U: /* FCVTxU Wd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100001 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64S: /* FCVTxS Xd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100000 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64U: /* FCVTxU Xd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100001 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ /* */ -+ case ARM64cvt_F32_I32S: /* FCVTxS Wd, Sn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100000 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ /* */ -+ case ARM64cvt_F32_I64U: /* FCVTxU Xd, Sn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X00100001 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ default: -+ goto bad; //ATC -+ } -+ goto done; -+ } -+ case ARM64in_VCvtSD: { -+ /* 31 23 21 16 14 9 4 -+ 000,11110, 00 10001 0,1 10000 n d FCVT Dd, Sn (S->D) -+ ---------- 01 ----- 0,0 --------- FCVT Sd, Dn (D->S) -+ Rounding, when dst is smaller than src, is per the FPCR. -+ */ -+ UInt dd = dregNo(i->ARM64in.VCvtSD.dst); -+ UInt nn = dregNo(i->ARM64in.VCvtSD.src); -+ if (i->ARM64in.VCvtSD.sToD) { -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100010, X110000, nn, dd); -+ } else { -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100010, X010000, nn, dd); -+ } -+ goto done; -+ } -+ case ARM64in_FPCR: { -+ Bool toFPCR = i->ARM64in.FPCR.toFPCR; -+ UInt iReg = iregNo(i->ARM64in.FPCR.iReg); -+ if (toFPCR) { -+ /* 0xD51B44 000 Rt MSR fpcr, rT */ -+ *p++ = 0xD51B4400 | (iReg & 0x1F); -+ goto done; -+ } -+ goto bad; // FPCR -> iReg case currently ATC -+ } -+ case ARM64in_VUnaryD: { -+ /* 31 23 21 16 14 9 4 -+ 000,11110 01 1,0000 0,0 10000 n d FMOV Dd, Dn (not handled) -+ ------------------- 0,1 --------- FABS ------ -+ ------------------- 1,0 --------- FNEG ------ -+ ------------------- 1,1 --------- FQSRT ----- -+ */ -+ UInt dD = dregNo(i->ARM64in.VUnaryD.dst); -+ UInt dN = dregNo(i->ARM64in.VUnaryD.src); -+ UInt b16 = 2; /* impossible */ -+ UInt b15 = 2; /* impossible */ -+ switch (i->ARM64in.VUnaryD.op) { -+ case ARM64fpu_NEG: b16 = 1; b15 = 0; break; -+ case ARM64fpu_SQRT: b16 = 1; b15 = 1; break; -+ case ARM64fpu_ABS: b16 = 0; b15 = 1; break; -+ default: break; -+ } -+ if (b16 < 2 && b15 < 2) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, (X0000 << 1) | b16, -+ (b15 << 5) | X10000, dN, dD); -+ goto done; -+ } -+ /* -+ 000, 11110 01 1,001 11,1 10000 n d FRINTI Dd, Dm (round per FPCR) -+ */ -+ if (i->ARM64in.VUnaryD.op == ARM64fpu_RINT) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, X00111, X110000, dN, dD); -+ goto done; -+ } -+ goto bad; -+ } -+ case ARM64in_VUnaryS: { -+ /* 31 23 21 16 14 9 4 -+ 000,11110 00 1,0000 0,0 10000 n d FMOV Sd, Sn (not handled) -+ ------------------- 0,1 --------- FABS ------ -+ ------------------- 1,0 --------- FNEG ------ -+ ------------------- 1,1 --------- FQSRT ----- -+ */ -+ UInt sD = dregNo(i->ARM64in.VUnaryS.dst); -+ UInt sN = dregNo(i->ARM64in.VUnaryS.src); -+ UInt b16 = 2; /* impossible */ -+ UInt b15 = 2; /* impossible */ -+ switch (i->ARM64in.VUnaryS.op) { -+ case ARM64fpu_NEG: b16 = 1; b15 = 0; break; -+ case ARM64fpu_SQRT: b16 = 1; b15 = 1; break; -+ case ARM64fpu_ABS: b16 = 0; b15 = 1; break; -+ default: break; -+ } -+ if (b16 < 2 && b15 < 2) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110001, (X0000 << 1) | b16, -+ (b15 << 5) | X10000, sN, sD); -+ goto done; -+ } -+ /* -+ 000, 11110 00 1,001 11,1 10000 n d FRINTI Sd, Sm (round per FPCR) -+ */ -+ if (i->ARM64in.VUnaryS.op == ARM64fpu_RINT) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110001, X00111, X110000, sN, sD); -+ goto done; -+ } -+ goto bad; -+ } -+ case ARM64in_VBinD: { -+ /* 31 23 20 15 11 9 4 -+ ---------------- 0000 ------ FMUL -------- -+ 000 11110 011 m 0001 10 n d FDIV Dd,Dn,Dm -+ ---------------- 0010 ------ FADD -------- -+ ---------------- 0011 ------ FSUB -------- -+ */ -+ UInt dD = dregNo(i->ARM64in.VBinD.dst); -+ UInt dN = dregNo(i->ARM64in.VBinD.argL); -+ UInt dM = dregNo(i->ARM64in.VBinD.argR); -+ UInt b1512 = 16; /* impossible */ -+ switch (i->ARM64in.VBinD.op) { -+ case ARM64fpb_DIV: b1512 = X0001; break; -+ case ARM64fpb_MUL: b1512 = X0000; break; -+ case ARM64fpb_SUB: b1512 = X0011; break; -+ case ARM64fpb_ADD: b1512 = X0010; break; -+ default: goto bad; -+ } -+ vassert(b1512 < 16); -+ *p++ -+ = X_3_8_5_6_5_5(X000, X11110011, dM, (b1512 << 2) | X10, dN, dD); -+ goto done; -+ } -+ case ARM64in_VBinS: { -+ /* 31 23 20 15 11 9 4 -+ ---------------- 0000 ------ FMUL -------- -+ 000 11110 001 m 0001 10 n d FDIV Dd,Dn,Dm -+ ---------------- 0010 ------ FADD -------- -+ ---------------- 0011 ------ FSUB -------- -+ */ -+ UInt sD = dregNo(i->ARM64in.VBinS.dst); -+ UInt sN = dregNo(i->ARM64in.VBinS.argL); -+ UInt sM = dregNo(i->ARM64in.VBinS.argR); -+ UInt b1512 = 16; /* impossible */ -+ switch (i->ARM64in.VBinS.op) { -+ case ARM64fpb_DIV: b1512 = X0001; break; -+ case ARM64fpb_MUL: b1512 = X0000; break; -+ case ARM64fpb_SUB: b1512 = X0011; break; -+ case ARM64fpb_ADD: b1512 = X0010; break; -+ default: goto bad; -+ } -+ vassert(b1512 < 16); -+ *p++ -+ = X_3_8_5_6_5_5(X000, X11110001, sM, (b1512 << 2) | X10, sN, sD); -+ goto done; -+ } -+ case ARM64in_VCmpD: { -+ /* 000 11110 01 1 m 00 1000 n 00 000 FCMP Dn, Dm */ -+ UInt dN = dregNo(i->ARM64in.VCmpD.argL); -+ UInt dM = dregNo(i->ARM64in.VCmpD.argR); -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, dM, X001000, dN, X00000); -+ goto done; -+ } -+ case ARM64in_VCmpS: { -+ /* 000 11110 00 1 m 00 1000 n 00 000 FCMP Sn, Sm */ -+ UInt sN = dregNo(i->ARM64in.VCmpS.argL); -+ UInt sM = dregNo(i->ARM64in.VCmpS.argR); -+ *p++ = X_3_8_5_6_5_5(X000, X11110001, sM, X001000, sN, X00000); -+ goto done; -+ } -+//ZZ case ARMin_VAluS: { -+//ZZ UInt dN = fregNo(i->ARMin.VAluS.argL); -+//ZZ UInt dD = fregNo(i->ARMin.VAluS.dst); -+//ZZ UInt dM = fregNo(i->ARMin.VAluS.argR); -+//ZZ UInt bN = dN & 1; -+//ZZ UInt bD = dD & 1; -+//ZZ UInt bM = dM & 1; -+//ZZ UInt pqrs = X1111; /* undefined */ -+//ZZ switch (i->ARMin.VAluS.op) { -+//ZZ case ARMvfp_ADD: pqrs = X0110; break; -+//ZZ case ARMvfp_SUB: pqrs = X0111; break; -+//ZZ case ARMvfp_MUL: pqrs = X0100; break; -+//ZZ case ARMvfp_DIV: pqrs = X1000; break; -+//ZZ default: goto bad; -+//ZZ } -+//ZZ vassert(pqrs != X1111); -+//ZZ UInt bP = (pqrs >> 3) & 1; -+//ZZ UInt bQ = (pqrs >> 2) & 1; -+//ZZ UInt bR = (pqrs >> 1) & 1; -+//ZZ UInt bS = (pqrs >> 0) & 1; -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,bD,bQ,bR), -+//ZZ (dN >> 1), (dD >> 1), -+//ZZ X1010, BITS4(bN,bS,bM,0), (dM >> 1)); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VUnaryS: { -+//ZZ UInt fD = fregNo(i->ARMin.VUnaryS.dst); -+//ZZ UInt fM = fregNo(i->ARMin.VUnaryS.src); -+//ZZ UInt insn = 0; -+//ZZ switch (i->ARMin.VUnaryS.op) { -+//ZZ case ARMvfpu_COPY: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000, -+//ZZ (fD >> 1), X1010, BITS4(0,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ case ARMvfpu_ABS: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000, -+//ZZ (fD >> 1), X1010, BITS4(1,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ case ARMvfpu_NEG: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001, -+//ZZ (fD >> 1), X1010, BITS4(0,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ case ARMvfpu_SQRT: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001, -+//ZZ (fD >> 1), X1010, BITS4(1,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VCMovD: { -+//ZZ UInt cc = (UInt)i->ARMin.VCMovD.cond; -+//ZZ UInt dD = dregNo(i->ARMin.VCMovD.dst); -+//ZZ UInt dM = dregNo(i->ARMin.VCMovD.src); -+//ZZ vassert(cc < 16 && cc != ARMcc_AL); -+//ZZ UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VCMovS: { -+//ZZ UInt cc = (UInt)i->ARMin.VCMovS.cond; -+//ZZ UInt fD = fregNo(i->ARMin.VCMovS.dst); -+//ZZ UInt fM = fregNo(i->ARMin.VCMovS.src); -+//ZZ vassert(cc < 16 && cc != ARMcc_AL); -+//ZZ UInt insn = XXXXXXXX(cc, X1110, BITS4(1,(fD & 1),1,1), -+//ZZ X0000,(fD >> 1),X1010, -+//ZZ BITS4(0,1,(fM & 1),0), (fM >> 1)); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VXferD: { -+//ZZ UInt dD = dregNo(i->ARMin.VXferD.dD); -+//ZZ UInt rHi = iregNo(i->ARMin.VXferD.rHi); -+//ZZ UInt rLo = iregNo(i->ARMin.VXferD.rLo); -+//ZZ /* vmov dD, rLo, rHi is -+//ZZ E C 4 rHi rLo B (0,0,dD[4],1) dD[3:0] -+//ZZ vmov rLo, rHi, dD is -+//ZZ E C 5 rHi rLo B (0,0,dD[4],1) dD[3:0] -+//ZZ */ -+//ZZ UInt insn -+//ZZ = XXXXXXXX(0xE, 0xC, i->ARMin.VXferD.toD ? 4 : 5, -+//ZZ rHi, rLo, 0xB, -+//ZZ BITS4(0,0, ((dD >> 4) & 1), 1), (dD & 0xF)); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VXferS: { -+//ZZ UInt fD = fregNo(i->ARMin.VXferS.fD); -+//ZZ UInt rLo = iregNo(i->ARMin.VXferS.rLo); -+//ZZ /* vmov fD, rLo is -+//ZZ E E 0 fD[4:1] rLo A (fD[0],0,0,1) 0 -+//ZZ vmov rLo, fD is -+//ZZ E E 1 fD[4:1] rLo A (fD[0],0,0,1) 0 -+//ZZ */ -+//ZZ UInt insn -+//ZZ = XXXXXXXX(0xE, 0xE, i->ARMin.VXferS.toS ? 0 : 1, -+//ZZ (fD >> 1) & 0xF, rLo, 0xA, -+//ZZ BITS4((fD & 1),0,0,1), 0); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VCvtID: { -+//ZZ Bool iToD = i->ARMin.VCvtID.iToD; -+//ZZ Bool syned = i->ARMin.VCvtID.syned; -+//ZZ if (iToD && syned) { -+//ZZ // FSITOD: I32S-in-freg to F64-in-dreg -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, -+//ZZ X1011, BITS4(1,1,(regF & 1),0), -+//ZZ (regF >> 1) & 0xF); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ if (iToD && (!syned)) { -+//ZZ // FUITOD: I32U-in-freg to F64-in-dreg -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, -+//ZZ X1011, BITS4(0,1,(regF & 1),0), -+//ZZ (regF >> 1) & 0xF); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ if ((!iToD) && syned) { -+//ZZ // FTOSID: F64-in-dreg to I32S-in-freg -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1), -+//ZZ X1101, (regF >> 1) & 0xF, -+//ZZ X1011, X0100, regD); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ if ((!iToD) && (!syned)) { -+//ZZ // FTOUID: F64-in-dreg to I32U-in-freg -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1), -+//ZZ X1100, (regF >> 1) & 0xF, -+//ZZ X1011, X0100, regD); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ /*UNREACHED*/ -+//ZZ vassert(0); -+//ZZ } -+//ZZ case ARMin_MFence: { -+//ZZ // It's not clear (to me) how these relate to the ARMv7 -+//ZZ // versions, so let's just use the v7 versions as they -+//ZZ // are at least well documented. -+//ZZ //*p++ = 0xEE070F9A; /* mcr 15,0,r0,c7,c10,4 (DSB) */ -+//ZZ //*p++ = 0xEE070FBA; /* mcr 15,0,r0,c7,c10,5 (DMB) */ -+//ZZ //*p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4 (ISB) */ -+//ZZ *p++ = 0xF57FF04F; /* DSB sy */ -+//ZZ *p++ = 0xF57FF05F; /* DMB sy */ -+//ZZ *p++ = 0xF57FF06F; /* ISB */ -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_CLREX: { -+//ZZ *p++ = 0xF57FF01F; /* clrex */ -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NLdStD: { -+//ZZ UInt regD = dregNo(i->ARMin.NLdStD.dD); -+//ZZ UInt regN, regM; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt bL = i->ARMin.NLdStD.isLoad ? 1 : 0; -+//ZZ UInt insn; -+//ZZ vassert(hregClass(i->ARMin.NLdStD.dD) == HRcFlt64); -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NLdStD.amode->tag == ARMamN_RR) { -+//ZZ regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rN); -+//ZZ regM = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rM); -+//ZZ } else { -+//ZZ regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.R.rN); -+//ZZ regM = 15; -+//ZZ } -+//ZZ insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), -+//ZZ regN, regD, X0111, X1000, regM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NUnaryS: { -+//ZZ UInt Q = i->ARMin.NUnaryS.Q ? 1 : 0; -+//ZZ UInt regD, D; -+//ZZ UInt regM, M; -+//ZZ UInt size = i->ARMin.NUnaryS.size; -+//ZZ UInt insn; -+//ZZ UInt opc, opc1, opc2; -+//ZZ switch (i->ARMin.NUnaryS.op) { -+//ZZ case ARMneon_VDUP: -+//ZZ if (i->ARMin.NUnaryS.size >= 16) -+//ZZ goto bad; -+//ZZ if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Reg) -+//ZZ goto bad; -+//ZZ if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ regD = (hregClass(i->ARMin.NUnaryS.dst->reg) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) -+//ZZ : dregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ regM = (hregClass(i->ARMin.NUnaryS.src->reg) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) -+//ZZ : dregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ D = regD >> 4; -+//ZZ M = regM >> 4; -+//ZZ regD &= 0xf; -+//ZZ regM &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), -+//ZZ (i->ARMin.NUnaryS.size & 0xf), regD, -+//ZZ X1100, BITS4(0,Q,M,0), regM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ case ARMneon_SETELEM: -+//ZZ regD = Q ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) : -+//ZZ dregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ regM = iregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ M = regM >> 4; -+//ZZ D = regD >> 4; -+//ZZ regM &= 0xF; -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ switch (size) { -+//ZZ case 0: -+//ZZ if (i->ARMin.NUnaryS.dst->index > 7) -+//ZZ goto bad; -+//ZZ opc = X1000 | i->ARMin.NUnaryS.dst->index; -+//ZZ break; -+//ZZ case 1: -+//ZZ if (i->ARMin.NUnaryS.dst->index > 3) -+//ZZ goto bad; -+//ZZ opc = X0001 | (i->ARMin.NUnaryS.dst->index << 1); -+//ZZ break; -+//ZZ case 2: -+//ZZ if (i->ARMin.NUnaryS.dst->index > 1) -+//ZZ goto bad; -+//ZZ opc = X0000 | (i->ARMin.NUnaryS.dst->index << 2); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ opc1 = (opc >> 2) & 3; -+//ZZ opc2 = opc & 3; -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0), -+//ZZ regD, regM, X1011, -+//ZZ BITS4(D,(opc2 >> 1),(opc2 & 1),1), X0000); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ case ARMneon_GETELEMU: -+//ZZ regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) : -+//ZZ dregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ regD = iregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ M = regM >> 4; -+//ZZ D = regD >> 4; -+//ZZ regM &= 0xF; -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ switch (size) { -+//ZZ case 0: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 7) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 8; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 7) -+//ZZ goto bad; -+//ZZ opc = X1000 | i->ARMin.NUnaryS.src->index; -+//ZZ break; -+//ZZ case 1: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 3) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 4; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 3) -+//ZZ goto bad; -+//ZZ opc = X0001 | (i->ARMin.NUnaryS.src->index << 1); -+//ZZ break; -+//ZZ case 2: -+//ZZ goto bad; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ opc1 = (opc >> 2) & 3; -+//ZZ opc2 = opc & 3; -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1), -+//ZZ regM, regD, X1011, -+//ZZ BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ case ARMneon_GETELEMS: -+//ZZ regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) : -+//ZZ dregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ regD = iregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ M = regM >> 4; -+//ZZ D = regD >> 4; -+//ZZ regM &= 0xF; -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ switch (size) { -+//ZZ case 0: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 7) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 8; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 7) -+//ZZ goto bad; -+//ZZ opc = X1000 | i->ARMin.NUnaryS.src->index; -+//ZZ break; -+//ZZ case 1: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 3) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 4; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 3) -+//ZZ goto bad; -+//ZZ opc = X0001 | (i->ARMin.NUnaryS.src->index << 1); -+//ZZ break; -+//ZZ case 2: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 1) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 2; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 1) -+//ZZ goto bad; -+//ZZ opc = X0000 | (i->ARMin.NUnaryS.src->index << 2); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ opc1 = (opc >> 2) & 3; -+//ZZ opc2 = opc & 3; -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1), -+//ZZ regM, regD, X1011, -+//ZZ BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+//ZZ case ARMin_NUnary: { -+//ZZ UInt Q = i->ARMin.NUnary.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NUnary.dst) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnary.dst) << 1) -+//ZZ : dregNo(i->ARMin.NUnary.dst); -+//ZZ UInt regM, M; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt sz1 = i->ARMin.NUnary.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NUnary.size & 1; -+//ZZ UInt sz = i->ARMin.NUnary.size; -+//ZZ UInt insn; -+//ZZ UInt F = 0; /* TODO: floating point EQZ ??? */ -+//ZZ if (i->ARMin.NUnary.op != ARMneon_DUP) { -+//ZZ regM = (hregClass(i->ARMin.NUnary.src) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnary.src) << 1) -+//ZZ : dregNo(i->ARMin.NUnary.src); -+//ZZ M = regM >> 4; -+//ZZ } else { -+//ZZ regM = iregNo(i->ARMin.NUnary.src); -+//ZZ M = regM >> 4; -+//ZZ } -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ switch (i->ARMin.NUnary.op) { -+//ZZ case ARMneon_COPY: /* VMOV reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regM, regD, X0001, -+//ZZ BITS4(M,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYN: /* VMOVN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(0,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYQNSS: /* VQMOVN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(1,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYQNUS: /* VQMOVUN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(0,1,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYQNUU: /* VQMOVN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(1,1,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYLS: /* VMOVL regQ, regD */ -+//ZZ if (sz >= 3) -+//ZZ goto bad; -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0), -+//ZZ BITS4((sz == 0) ? 1 : 0,0,0,0), -+//ZZ regD, X1010, BITS4(0,0,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYLU: /* VMOVL regQ, regD */ -+//ZZ if (sz >= 3) -+//ZZ goto bad; -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0), -+//ZZ BITS4((sz == 0) ? 1 : 0,0,0,0), -+//ZZ regD, X1010, BITS4(0,0,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_NOT: /* VMVN reg, reg*/ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_EQZ: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1), -+//ZZ regD, BITS4(0,F,0,1), BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_CNT: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_CLZ: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0100, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_CLS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0100, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_ABS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1), -+//ZZ regD, X0011, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_DUP: -+//ZZ sz1 = i->ARMin.NUnary.size == 0 ? 1 : 0; -+//ZZ sz2 = i->ARMin.NUnary.size == 1 ? 1 : 0; -+//ZZ vassert(sz1 + sz2 < 2); -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1, sz1, Q, 0), regD, regM, -+//ZZ X1011, BITS4(D,0,sz2,1), X0000); -+//ZZ break; -+//ZZ case ARMneon_REV16: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, BITS4(0,0,0,1), BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_REV32: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, BITS4(0,0,0,0), BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_REV64: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, BITS4(0,0,0,0), BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_PADDLU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0010, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_PADDLS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0010, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHLNUU: -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ (1 << 3) | (D << 2) | ((sz >> 4) & 3), -+//ZZ sz & 0xf, regD, X0111, -+//ZZ BITS4(sz >> 6,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHLNSS: -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ (1 << 3) | (D << 2) | ((sz >> 4) & 3), -+//ZZ sz & 0xf, regD, X0111, -+//ZZ BITS4(sz >> 6,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHLNUS: -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ (1 << 3) | (D << 2) | ((sz >> 4) & 3), -+//ZZ sz & 0xf, regD, X0110, -+//ZZ BITS4(sz >> 6,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTStoF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTUtoF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoFixedU: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1111, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoFixedS: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1111, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFixedUtoF: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1110, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFixedStoF: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1110, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTF32toF16: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0110, -+//ZZ BITS4(0,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTF16toF32: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0111, -+//ZZ BITS4(0,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRECIP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRECIPF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VABSFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRSQRTEFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRSQRTE: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VNEGF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NDual: { -+//ZZ UInt Q = i->ARMin.NDual.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NDual.arg1) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NDual.arg1) << 1) -+//ZZ : dregNo(i->ARMin.NDual.arg1); -+//ZZ UInt regM = (hregClass(i->ARMin.NDual.arg2) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NDual.arg2) << 1) -+//ZZ : dregNo(i->ARMin.NDual.arg2); -+//ZZ UInt D = regD >> 4; -+//ZZ UInt M = regM >> 4; -+//ZZ UInt sz1 = i->ARMin.NDual.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NDual.size & 1; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ switch (i->ARMin.NDual.op) { -+//ZZ case ARMneon_TRN: /* VTRN reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0000, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_ZIP: /* VZIP reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0001, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_UZP: /* VUZP reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0001, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NBinary: { -+//ZZ UInt Q = i->ARMin.NBinary.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NBinary.dst) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NBinary.dst) << 1) -+//ZZ : dregNo(i->ARMin.NBinary.dst); -+//ZZ UInt regN = (hregClass(i->ARMin.NBinary.argL) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NBinary.argL) << 1) -+//ZZ : dregNo(i->ARMin.NBinary.argL); -+//ZZ UInt regM = (hregClass(i->ARMin.NBinary.argR) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NBinary.argR) << 1) -+//ZZ : dregNo(i->ARMin.NBinary.argR); -+//ZZ UInt sz1 = i->ARMin.NBinary.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NBinary.size & 1; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt N = regN >> 4; -+//ZZ UInt M = regM >> 4; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ regN &= 0xF; -+//ZZ switch (i->ARMin.NBinary.op) { -+//ZZ case ARMneon_VAND: /* VAND reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X0001, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VORR: /* VORR reg, reg, reg*/ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X0001, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VXOR: /* VEOR reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X0001, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VADD: /* VADD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1000, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VSUB: /* VSUB reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1000, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMINU: /* VMIN.Uxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMINS: /* VMIN.Sxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMAXU: /* VMAX.Uxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMAXS: /* VMAX.Sxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRHADDS: /* VRHADD.Sxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0001, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRHADDU: /* VRHADD.Uxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0001, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQADDU: /* VQADD unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0000, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQADDS: /* VQADD signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0000, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSUBU: /* VQSUB unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSUBS: /* VQSUB signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGTU: /* VCGT unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGTS: /* VCGT signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGEU: /* VCGE unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGES: /* VCGE signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCEQ: /* VCEQ reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1000, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VEXT: /* VEXT.8 reg, reg, #imm4*/ -+//ZZ if (i->ARMin.NBinary.size >= 16) -+//ZZ goto bad; -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,1,1), regN, regD, -+//ZZ i->ARMin.NBinary.size & 0xf, BITS4(N,Q,M,0), -+//ZZ regM); -+//ZZ break; -+//ZZ case ARMneon_VMUL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1001, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULLU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1100, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULLS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1100, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1001, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULLP: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1110, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQDMULH: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQRDMULH: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQDMULL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1101, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VTBL: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), regN, regD, -+//ZZ X1000, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPADD: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1011, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VPADDFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMINU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMINS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMAXU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMAXS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VADDFP: /* VADD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VSUBFP: /* VADD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VABDFP: /* VABD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMINF: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMAXF: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMINF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMAXF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRECPS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1111, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGTF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, X1110, -+//ZZ BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGEF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X1110, -+//ZZ BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCEQF: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1110, -+//ZZ BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRSQRTS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X1111, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NShift: { -+//ZZ UInt Q = i->ARMin.NShift.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NShift.dst) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NShift.dst) << 1) -+//ZZ : dregNo(i->ARMin.NShift.dst); -+//ZZ UInt regM = (hregClass(i->ARMin.NShift.argL) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NShift.argL) << 1) -+//ZZ : dregNo(i->ARMin.NShift.argL); -+//ZZ UInt regN = (hregClass(i->ARMin.NShift.argR) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NShift.argR) << 1) -+//ZZ : dregNo(i->ARMin.NShift.argR); -+//ZZ UInt sz1 = i->ARMin.NShift.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NShift.size & 1; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt N = regN >> 4; -+//ZZ UInt M = regM >> 4; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ regN &= 0xF; -+//ZZ switch (i->ARMin.NShift.op) { -+//ZZ case ARMneon_VSHL: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VSAL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHL: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSAL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NShl64: { -+//ZZ HReg regDreg = i->ARMin.NShl64.dst; -+//ZZ HReg regMreg = i->ARMin.NShl64.src; -+//ZZ UInt amt = i->ARMin.NShl64.amt; -+//ZZ vassert(amt >= 1 && amt <= 63); -+//ZZ vassert(hregClass(regDreg) == HRcFlt64); -+//ZZ vassert(hregClass(regMreg) == HRcFlt64); -+//ZZ UInt regD = dregNo(regDreg); -+//ZZ UInt regM = dregNo(regMreg); -+//ZZ UInt D = (regD >> 4) & 1; -+//ZZ UInt Vd = regD & 0xF; -+//ZZ UInt L = 1; -+//ZZ UInt Q = 0; /* always 64-bit */ -+//ZZ UInt M = (regM >> 4) & 1; -+//ZZ UInt Vm = regM & 0xF; -+//ZZ UInt insn = XXXXXXXX(X1111,X0010, BITS4(1,D,(amt>>5)&1,(amt>>4)&1), -+//ZZ amt & 0xF, Vd, X0101, BITS4(L,Q,M,1), Vm); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+ case ARM64in_VImmQ: { -+ UInt rQ = qregNo(i->ARM64in.VImmQ.rQ); -+ UShort imm = i->ARM64in.VImmQ.imm; -+ if (imm == 0) { -+ /* movi rQ.4s, #0x0 == 0x4F 0x00 0x04 000 rQ */ -+ vassert(rQ < 32); -+ *p++ = 0x4F000400 | rQ; -+ goto done; -+ } -+ goto bad; /* zero is the only handled case right now */ -+ } -+ -+ case ARM64in_VDfromX: { -+ /* INS Vd.D[0], rX -+ 0100 1110 0000 1000 0001 11 nn dd INS Vd.D[0], Xn -+ This isn't wonderful, in the sense that the upper half of -+ the vector register stays unchanged and thus the insn is -+ data dependent on its output register. */ -+ UInt dd = dregNo(i->ARM64in.VDfromX.rD); -+ UInt xx = iregNo(i->ARM64in.VDfromX.rX); -+ vassert(xx < 31); -+ *p++ = 0x4E081C00 | X_2_6_2_12_5_5(0,0,0,0,xx,dd); -+ goto done; -+ } -+ -+ case ARM64in_VQfromXX: { -+ /* What we really generate is a two insn sequence: -+ INS Vd.D[0], Xlo; INS Vd.D[1], Xhi -+ 0100 1110 0000 1000 0001 11 nn dd INS Vd.D[0], Xn -+ 0100 1110 0001 1000 0001 11 nn dd INS Vd.D[1], Xn -+ */ -+ UInt qq = qregNo(i->ARM64in.VQfromXX.rQ); -+ UInt xhi = iregNo(i->ARM64in.VQfromXX.rXhi); -+ UInt xlo = iregNo(i->ARM64in.VQfromXX.rXlo); -+ vassert(xhi < 31 && xlo < 31); -+ *p++ = 0x4E081C00 | X_2_6_2_12_5_5(0,0,0,0,xlo,qq); -+ *p++ = 0x4E181C00 | X_2_6_2_12_5_5(0,0,0,0,xhi,qq); -+ goto done; -+ } -+ -+ case ARM64in_VXfromQ: { -+ /* 010 0111 0000 01000 001111 nn dd UMOV Xd, Vn.D[0] -+ 010 0111 0000 11000 001111 nn dd UMOV Xd, Vn.D[1] -+ */ -+ UInt dd = iregNo(i->ARM64in.VXfromQ.rX); -+ UInt nn = qregNo(i->ARM64in.VXfromQ.rQ); -+ UInt laneNo = i->ARM64in.VXfromQ.laneNo; -+ vassert(dd < 31); -+ vassert(laneNo < 2); -+ *p++ = X_3_8_5_6_5_5(X010, X01110000, -+ laneNo == 1 ? X11000 : X01000, X001111, nn, dd); -+ goto done; -+ } -+ -+ case ARM64in_VMov: { -+ /* 000 11110 00 10000 00 10000 n d FMOV Sd, Sn -+ 000 11110 01 10000 00 10000 n d FMOV Dd, Dn -+ 010 01110 10 1 n 0 00111 n d MOV Vd.16b, Vn.16b -+ */ -+ HReg rD = i->ARM64in.VMov.dst; -+ HReg rN = i->ARM64in.VMov.src; -+ switch (i->ARM64in.VMov.szB) { -+ case 8: { -+ UInt dd = dregNo(rD); -+ UInt nn = dregNo(rN); -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, X00000, X010000, nn, dd); -+ goto done; -+ } -+ default: -+ break; -+ } -+ goto bad; -+ } -+//ZZ case ARMin_NeonImm: { -+//ZZ UInt Q = (hregClass(i->ARMin.NeonImm.dst) == HRcVec128) ? 1 : 0; -+//ZZ UInt regD = Q ? (qregNo(i->ARMin.NeonImm.dst) << 1) : -+//ZZ dregNo(i->ARMin.NeonImm.dst); -+//ZZ UInt D = regD >> 4; -+//ZZ UInt imm = i->ARMin.NeonImm.imm->imm8; -+//ZZ UInt tp = i->ARMin.NeonImm.imm->type; -+//ZZ UInt j = imm >> 7; -+//ZZ UInt imm3 = (imm >> 4) & 0x7; -+//ZZ UInt imm4 = imm & 0xF; -+//ZZ UInt cmode, op; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ if (tp == 9) -+//ZZ op = 1; -+//ZZ else -+//ZZ op = 0; -+//ZZ switch (tp) { -+//ZZ case 0: -+//ZZ case 1: -+//ZZ case 2: -+//ZZ case 3: -+//ZZ case 4: -+//ZZ case 5: -+//ZZ cmode = tp << 1; -+//ZZ break; -+//ZZ case 9: -+//ZZ case 6: -+//ZZ cmode = 14; -+//ZZ break; -+//ZZ case 7: -+//ZZ cmode = 12; -+//ZZ break; -+//ZZ case 8: -+//ZZ cmode = 13; -+//ZZ break; -+//ZZ case 10: -+//ZZ cmode = 15; -+//ZZ break; -+//ZZ default: -+//ZZ vpanic("ARMin_NeonImm"); -+//ZZ -+//ZZ } -+//ZZ insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD, -+//ZZ cmode, BITS4(0,Q,op,1), imm4); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NCMovQ: { -+//ZZ UInt cc = (UInt)i->ARMin.NCMovQ.cond; -+//ZZ UInt qM = qregNo(i->ARMin.NCMovQ.src) << 1; -+//ZZ UInt qD = qregNo(i->ARMin.NCMovQ.dst) << 1; -+//ZZ UInt vM = qM & 0xF; -+//ZZ UInt vD = qD & 0xF; -+//ZZ UInt M = (qM >> 4) & 1; -+//ZZ UInt D = (qD >> 4) & 1; -+//ZZ vassert(cc < 16 && cc != ARMcc_AL && cc != ARMcc_NV); -+//ZZ /* b!cc here+8: !cc A00 0000 */ -+//ZZ UInt insn = XXXXXXXX(cc ^ 1, 0xA, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0); -+//ZZ *p++ = insn; -+//ZZ /* vmov qD, qM */ -+//ZZ insn = XXXXXXXX(0xF, 0x2, BITS4(0,D,1,0), -+//ZZ vM, vD, BITS4(0,0,0,1), BITS4(M,1,M,1), vM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_Add32: { -+//ZZ UInt regD = iregNo(i->ARMin.Add32.rD); -+//ZZ UInt regN = iregNo(i->ARMin.Add32.rN); -+//ZZ UInt imm32 = i->ARMin.Add32.imm32; -+//ZZ vassert(regD != regN); -+//ZZ /* MOV regD, imm32 */ -+//ZZ p = imm32_to_iregNo((UInt *)p, regD, imm32); -+//ZZ /* ADD regD, regN, regD */ -+//ZZ UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+ -+ case ARM64in_EvCheck: { -+ /* The sequence is fixed (canned) except for the two amodes -+ supplied by the insn. These don't change the length, though. -+ We generate: -+ ldr w9, [x21 + #8] 8 == offsetof(host_EvC_COUNTER) -+ subs w9, w9, #1 -+ str w9, [x21 + #8] 8 == offsetof(host_EvC_COUNTER) -+ bpl nofail -+ ldr x9, [x21 + #0] 0 == offsetof(host_EvC_FAILADDR) -+ br x9 -+ nofail: -+ */ -+ UInt* p0 = p; -+ p = do_load_or_store32(p, True/*isLoad*/, /*w*/9, -+ i->ARM64in.EvCheck.amCounter); -+ *p++ = 0x71000529; /* subs w9, w9, #1 */ -+ p = do_load_or_store32(p, False/*!isLoad*/, /*w*/9, -+ i->ARM64in.EvCheck.amCounter); -+ *p++ = 0x54000065; /* bpl nofail */ -+ p = do_load_or_store64(p, True/*isLoad*/, /*x*/9, -+ i->ARM64in.EvCheck.amFailAddr); -+ *p++ = 0xD61F0120; /* br x9 */ -+ /* nofail: */ -+ -+ /* Crosscheck */ -+ vassert(evCheckSzB_ARM64() == (UChar*)p - (UChar*)p0); -+ goto done; -+ } -+ -+//ZZ case ARMin_ProfInc: { -+//ZZ /* We generate: -+//ZZ (ctrP is unknown now, so use 0x65556555 in the -+//ZZ expectation that a later call to LibVEX_patchProfCtr -+//ZZ will be used to fill in the immediate fields once the -+//ZZ right value is known.) -+//ZZ movw r12, lo16(0x65556555) -+//ZZ movt r12, lo16(0x65556555) -+//ZZ ldr r11, [r12] -+//ZZ adds r11, r11, #1 -+//ZZ str r11, [r12] -+//ZZ ldr r11, [r12+4] -+//ZZ adc r11, r11, #0 -+//ZZ str r11, [r12+4] -+//ZZ */ -+//ZZ p = imm32_to_iregNo_EXACTLY2(p, /*r*/12, 0x65556555); -+//ZZ *p++ = 0xE59CB000; -+//ZZ *p++ = 0xE29BB001; -+//ZZ *p++ = 0xE58CB000; -+//ZZ *p++ = 0xE59CB004; -+//ZZ *p++ = 0xE2ABB000; -+//ZZ *p++ = 0xE58CB004; -+//ZZ /* Tell the caller .. */ -+//ZZ vassert(!(*is_profInc)); -+//ZZ *is_profInc = True; -+//ZZ goto done; -+//ZZ } -+ -+ /* ... */ -+ default: -+ goto bad; -+ } -+ -+ bad: -+ ppARM64Instr(i); -+ vpanic("emit_ARM64Instr"); -+ /*NOTREACHED*/ -+ -+ done: -+ vassert(((UChar*)p) - &buf[0] <= 36); -+ return ((UChar*)p) - &buf[0]; -+} -+ -+ -+/* How big is an event check? See case for ARM64in_EvCheck in -+ emit_ARM64Instr just above. That crosschecks what this returns, so -+ we can tell if we're inconsistent. */ -+Int evCheckSzB_ARM64 ( void ) -+{ -+ return 24; -+} -+ -+ -+/* NB: what goes on here has to be very closely coordinated with the -+ emitInstr case for XDirect, above. */ -+VexInvalRange chainXDirect_ARM64 ( void* place_to_chain, -+ void* disp_cp_chain_me_EXPECTED, -+ void* place_to_jump_to ) -+{ -+ /* What we're expecting to see is: -+ movw x9, disp_cp_chain_me_to_EXPECTED[15:0] -+ movk x9, disp_cp_chain_me_to_EXPECTED[31:15], lsl 16 -+ movk x9, disp_cp_chain_me_to_EXPECTED[47:32], lsl 32 -+ movk x9, disp_cp_chain_me_to_EXPECTED[63:48], lsl 48 -+ blr x9 -+ viz -+ <16 bytes generated by imm64_to_iregNo_EXACTLY4> -+ D6 3F 01 20 -+ */ -+ UInt* p = (UInt*)place_to_chain; -+ vassert(0 == (3 & (HWord)p)); -+ vassert(is_imm64_to_iregNo_EXACTLY4( -+ p, /*x*/9, Ptr_to_ULong(disp_cp_chain_me_EXPECTED))); -+ vassert(p[4] == 0xD63F0120); -+ /* And what we want to change it to is: -+ movw x9, place_to_jump_to[15:0] -+ movk x9, place_to_jump_to[31:15], lsl 16 -+ movk x9, place_to_jump_to[47:32], lsl 32 -+ movk x9, place_to_jump_to[63:48], lsl 48 -+ br x9 -+ viz -+ <16 bytes generated by imm64_to_iregNo_EXACTLY4> -+ D6 1F 01 20 -+ -+ The replacement has the same length as the original. -+ */ -+ -+ (void)imm64_to_iregNo_EXACTLY4( -+ p, /*x*/9, Ptr_to_ULong(place_to_jump_to)); -+ p[4] = 0xD61F0120; -+ -+ VexInvalRange vir = {(HWord)p, 20}; -+ return vir; -+} -+ -+ -+//ZZ /* NB: what goes on here has to be very closely coordinated with the -+//ZZ emitInstr case for XDirect, above. */ -+//ZZ VexInvalRange unchainXDirect_ARM ( void* place_to_unchain, -+//ZZ void* place_to_jump_to_EXPECTED, -+//ZZ void* disp_cp_chain_me ) -+//ZZ { -+//ZZ /* What we're expecting to see is: -+//ZZ (general case) -+//ZZ movw r12, lo16(place_to_jump_to_EXPECTED) -+//ZZ movt r12, lo16(place_to_jump_to_EXPECTED) -+//ZZ bx r12 -+//ZZ viz -+//ZZ <8 bytes generated by imm32_to_iregNo_EXACTLY2> -+//ZZ E1 2F FF 1C -+//ZZ ---OR--- -+//ZZ in the case where the displacement falls within 26 bits -+//ZZ b disp24; undef; undef -+//ZZ viz -+//ZZ EA <3 bytes == disp24> -+//ZZ FF 00 00 00 -+//ZZ FF 00 00 00 -+//ZZ */ -+//ZZ UInt* p = (UInt*)place_to_unchain; -+//ZZ vassert(0 == (3 & (HWord)p)); -+//ZZ -+//ZZ Bool valid = False; -+//ZZ if (is_imm32_to_iregNo_EXACTLY2( -+//ZZ p, /*r*/12, (UInt)Ptr_to_ULong(place_to_jump_to_EXPECTED)) -+//ZZ && p[2] == 0xE12FFF1C) { -+//ZZ valid = True; /* it's the long form */ -+//ZZ if (0) -+//ZZ vex_printf("QQQ unchainXDirect_ARM: found long form\n"); -+//ZZ } else -+//ZZ if ((p[0] >> 24) == 0xEA && p[1] == 0xFF000000 && p[2] == 0xFF000000) { -+//ZZ /* It's the short form. Check the displacement is right. */ -+//ZZ Int simm24 = p[0] & 0x00FFFFFF; -+//ZZ simm24 <<= 8; simm24 >>= 8; -+//ZZ if ((UChar*)p + (simm24 << 2) + 8 == (UChar*)place_to_jump_to_EXPECTED) { -+//ZZ valid = True; -+//ZZ if (0) -+//ZZ vex_printf("QQQ unchainXDirect_ARM: found short form\n"); -+//ZZ } -+//ZZ } -+//ZZ vassert(valid); -+//ZZ -+//ZZ /* And what we want to change it to is: -+//ZZ movw r12, lo16(disp_cp_chain_me) -+//ZZ movt r12, hi16(disp_cp_chain_me) -+//ZZ blx r12 -+//ZZ viz -+//ZZ <8 bytes generated by imm32_to_iregNo_EXACTLY2> -+//ZZ E1 2F FF 3C -+//ZZ */ -+//ZZ (void)imm32_to_iregNo_EXACTLY2( -+//ZZ p, /*r*/12, (UInt)Ptr_to_ULong(disp_cp_chain_me)); -+//ZZ p[2] = 0xE12FFF3C; -+//ZZ VexInvalRange vir = {(HWord)p, 12}; -+//ZZ return vir; -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* Patch the counter address into a profile inc point, as previously -+//ZZ created by the ARMin_ProfInc case for emit_ARMInstr. */ -+//ZZ VexInvalRange patchProfInc_ARM ( void* place_to_patch, -+//ZZ ULong* location_of_counter ) -+//ZZ { -+//ZZ vassert(sizeof(ULong*) == 4); -+//ZZ UInt* p = (UInt*)place_to_patch; -+//ZZ vassert(0 == (3 & (HWord)p)); -+//ZZ vassert(is_imm32_to_iregNo_EXACTLY2(p, /*r*/12, 0x65556555)); -+//ZZ vassert(p[2] == 0xE59CB000); -+//ZZ vassert(p[3] == 0xE29BB001); -+//ZZ vassert(p[4] == 0xE58CB000); -+//ZZ vassert(p[5] == 0xE59CB004); -+//ZZ vassert(p[6] == 0xE2ABB000); -+//ZZ vassert(p[7] == 0xE58CB004); -+//ZZ imm32_to_iregNo_EXACTLY2(p, /*r*/12, -+//ZZ (UInt)Ptr_to_ULong(location_of_counter)); -+//ZZ VexInvalRange vir = {(HWord)p, 8}; -+//ZZ return vir; -+//ZZ } -+//ZZ -+//ZZ -+//ZZ #undef BITS4 -+//ZZ #undef X0000 -+//ZZ #undef X0001 -+//ZZ #undef X0010 -+//ZZ #undef X0011 -+//ZZ #undef X0100 -+//ZZ #undef X0101 -+//ZZ #undef X0110 -+//ZZ #undef X0111 -+//ZZ #undef X1000 -+//ZZ #undef X1001 -+//ZZ #undef X1010 -+//ZZ #undef X1011 -+//ZZ #undef X1100 -+//ZZ #undef X1101 -+//ZZ #undef X1110 -+//ZZ #undef X1111 -+//ZZ #undef XXXXX___ -+//ZZ #undef XXXXXX__ -+//ZZ #undef XXX___XX -+//ZZ #undef XXXXX__X -+//ZZ #undef XXXXXXXX -+//ZZ #undef XX______ -+ -+/*---------------------------------------------------------------*/ -+/*--- end host_arm64_defs.c ---*/ -+/*---------------------------------------------------------------*/ -Index: VEX/priv/host_arm64_defs.h -=================================================================== ---- /dev/null -+++ VEX/priv/host_arm64_defs.h -@@ -0,0 +1,1036 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin host_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VEX_HOST_ARM64_DEFS_H -+#define __VEX_HOST_ARM64_DEFS_H -+ -+#include "libvex_basictypes.h" -+#include "libvex.h" // VexArch -+#include "host_generic_regs.h" // HReg -+ -+//ZZ extern UInt arm_hwcaps; -+ -+ -+/* --------- Registers. --------- */ -+ -+//ZZ /* The usual HReg abstraction. -+//ZZ There are 16 general purpose regs. -+//ZZ */ -+ -+extern void ppHRegARM64 ( HReg ); -+ -+extern HReg hregARM64_X0 ( void ); -+extern HReg hregARM64_X1 ( void ); -+extern HReg hregARM64_X2 ( void ); -+extern HReg hregARM64_X3 ( void ); -+extern HReg hregARM64_X4 ( void ); -+extern HReg hregARM64_X5 ( void ); -+extern HReg hregARM64_X6 ( void ); -+extern HReg hregARM64_X7 ( void ); -+//ZZ extern HReg hregARM_R8 ( void ); -+extern HReg hregARM64_X9 ( void ); -+extern HReg hregARM64_X10 ( void ); -+extern HReg hregARM64_X11 ( void ); -+extern HReg hregARM64_X12 ( void ); -+extern HReg hregARM64_X13 ( void ); -+extern HReg hregARM64_X14 ( void ); -+extern HReg hregARM64_X15 ( void ); -+extern HReg hregARM64_X21 ( void ); -+extern HReg hregARM64_X22 ( void ); -+extern HReg hregARM64_X23 ( void ); -+extern HReg hregARM64_X24 ( void ); -+extern HReg hregARM64_X25 ( void ); -+extern HReg hregARM64_X26 ( void ); -+extern HReg hregARM64_X27 ( void ); -+extern HReg hregARM64_X28 ( void ); -+extern HReg hregARM64_D8 ( void ); -+extern HReg hregARM64_D9 ( void ); -+extern HReg hregARM64_D10 ( void ); -+extern HReg hregARM64_D11 ( void ); -+extern HReg hregARM64_D12 ( void ); -+extern HReg hregARM64_D13 ( void ); -+extern HReg hregARM64_Q16 ( void ); -+extern HReg hregARM64_Q17 ( void ); -+extern HReg hregARM64_Q18 ( void ); -+ -+/* Number of registers used arg passing in function calls */ -+#define ARM64_N_ARGREGS 8 /* x0 .. x7 */ -+ -+ -+/* --------- Condition codes. --------- */ -+ -+typedef -+ enum { -+ ARM64cc_EQ = 0, /* equal : Z=1 */ -+ ARM64cc_NE = 1, /* not equal : Z=0 */ -+ -+ ARM64cc_CS = 2, /* >=u (higher or same) : C=1 */ -+ ARM64cc_CC = 3, /* u (higher) : C=1 && Z=0 */ -+ ARM64cc_LS = 9, /* <=u (lower or same) : !(C=1 && Z=0) */ -+ -+ ARM64cc_GE = 10, /* >=s (signed greater or equal) : N=V */ -+ ARM64cc_LT = 11, /* s (signed greater) : Z=0 && N=V */ -+ ARM64cc_LE = 13, /* <=s (signed less or equal) : !(Z=0 && N=V) */ -+ -+ ARM64cc_AL = 14, /* always (unconditional) */ -+ ARM64cc_NV = 15 /* in 64-bit mode also means "always" */ -+ } -+ ARM64CondCode; -+ -+ -+/* --------- Memory address expressions (amodes). --------- */ -+ -+typedef -+ enum { -+ ARM64am_RI9=1, /* reg + simm9 */ -+ ARM64am_RI12, /* reg + uimm12 * szB (iow, scaled by access size) */ -+ ARM64am_RR /* reg1 + reg2 */ -+ } -+ ARM64AModeTag; -+ -+typedef -+ struct { -+ ARM64AModeTag tag; -+ union { -+ struct { -+ HReg reg; -+ Int simm9; /* -256 .. +255 */ -+ } RI9; -+ struct { -+ HReg reg; -+ UInt uimm12; /* 0 .. 4095 */ -+ UChar szB; /* 1, 2, 4, 8 (16 ?) */ -+ } RI12; -+ struct { -+ HReg base; -+ HReg index; -+ } RR; -+ } ARM64am; -+ } -+ ARM64AMode; -+ -+extern ARM64AMode* ARM64AMode_RI9 ( HReg reg, Int simm9 ); -+extern ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB ); -+extern ARM64AMode* ARM64AMode_RR ( HReg base, HReg index ); -+ -+ -+/* --------- Reg or uimm12 or (uimm12 << 12) operands --------- */ -+ -+typedef -+ enum { -+ ARM64riA_I12=4, /* uimm12 << 0 or 12 only */ -+ ARM64riA_R /* reg */ -+ } -+ ARM64RIATag; -+ -+typedef -+ struct { -+ ARM64RIATag tag; -+ union { -+ struct { -+ UShort imm12; /* 0 .. 4095 */ -+ UChar shift; /* 0 or 12 only */ -+ } I12; -+ struct { -+ HReg reg; -+ } R; -+ } ARM64riA; -+ } -+ ARM64RIA; -+ -+extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ); -+extern ARM64RIA* ARM64RIA_R ( HReg ); -+ -+ -+/* --------- Reg or "bitfield" (logic immediate) operands --------- */ -+ -+typedef -+ enum { -+ ARM64riL_I13=6, /* wierd-o bitfield immediate, 13 bits in total */ -+ ARM64riL_R /* reg */ -+ } -+ ARM64RILTag; -+ -+typedef -+ struct { -+ ARM64RILTag tag; -+ union { -+ struct { -+ UChar bitN; /* 0 .. 1 */ -+ UChar immR; /* 0 .. 63 */ -+ UChar immS; /* 0 .. 63 */ -+ } I13; -+ struct { -+ HReg reg; -+ } R; -+ } ARM64riL; -+ } -+ ARM64RIL; -+ -+extern ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS ); -+extern ARM64RIL* ARM64RIL_R ( HReg ); -+ -+ -+/* --------------- Reg or uimm6 operands --------------- */ -+ -+typedef -+ enum { -+ ARM64ri6_I6=8, /* uimm6, 1 .. 63 only */ -+ ARM64ri6_R /* reg */ -+ } -+ ARM64RI6Tag; -+ -+typedef -+ struct { -+ ARM64RI6Tag tag; -+ union { -+ struct { -+ UInt imm6; /* 1 .. 63 */ -+ } I6; -+ struct { -+ HReg reg; -+ } R; -+ } ARM64ri6; -+ } -+ ARM64RI6; -+ -+extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 ); -+extern ARM64RI6* ARM64RI6_R ( HReg ); -+ -+ -+/* --------------------- Instructions --------------------- */ -+ -+typedef -+ enum { -+ ARM64lo_AND=10, -+ ARM64lo_OR, -+ ARM64lo_XOR -+ } -+ ARM64LogicOp; -+ -+typedef -+ enum { -+ ARM64sh_SHL=13, -+ ARM64sh_SHR, -+ ARM64sh_SAR -+ } -+ ARM64ShiftOp; -+ -+typedef -+ enum { -+ ARM64un_NEG=16, -+ ARM64un_NOT, -+ ARM64un_CLZ, -+ } -+ ARM64UnaryOp; -+ -+typedef -+ enum { -+ ARM64mul_PLAIN=60, /* lo64(64 * 64) */ -+ ARM64mul_ZX, /* hi64(64 *u 64) */ -+ ARM64mul_SX /* hi64(64 *s 64) */ -+ } -+ ARM64MulOp; -+ -+typedef -+ /* These characterise an integer-FP conversion, but don't imply any -+ particular direction. */ -+ enum { -+ ARM64cvt_F32_I32S=65, -+ ARM64cvt_F64_I32S, -+ ARM64cvt_F32_I64S, -+ ARM64cvt_F64_I64S, -+ ARM64cvt_F32_I32U, -+ ARM64cvt_F64_I32U, -+ ARM64cvt_F32_I64U, -+ ARM64cvt_F64_I64U, -+ ARM64cvt_INVALID -+ } -+ ARM64CvtOp; -+ -+typedef -+ enum { -+ ARM64fpb_ADD=75, -+ ARM64fpb_SUB, -+ ARM64fpb_MUL, -+ ARM64fpb_DIV, -+ ARM64fpb_INVALID -+ } -+ ARM64FpBinOp; -+ -+typedef -+ enum { -+ ARM64fpu_NEG=82, -+ ARM64fpu_ABS, -+ ARM64fpu_SQRT, -+ ARM64fpu_RINT, -+ ARM64fpu_INVALID -+ } -+ ARM64FpUnaryOp; -+ -+//ZZ extern const HChar* showARMVfpUnaryOp ( ARMVfpUnaryOp op ); -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_VAND=90, -+//ZZ ARMneon_VORR, -+//ZZ ARMneon_VXOR, -+//ZZ ARMneon_VADD, -+//ZZ ARMneon_VADDFP, -+//ZZ ARMneon_VRHADDS, -+//ZZ ARMneon_VRHADDU, -+//ZZ ARMneon_VPADDFP, -+//ZZ ARMneon_VABDFP, -+//ZZ ARMneon_VSUB, -+//ZZ ARMneon_VSUBFP, -+//ZZ ARMneon_VMAXU, -+//ZZ ARMneon_VMAXS, -+//ZZ ARMneon_VMAXF, -+//ZZ ARMneon_VMINU, -+//ZZ ARMneon_VMINS, -+//ZZ ARMneon_VMINF, -+//ZZ ARMneon_VQADDU, -+//ZZ ARMneon_VQADDS, -+//ZZ ARMneon_VQSUBU, -+//ZZ ARMneon_VQSUBS, -+//ZZ ARMneon_VCGTU, -+//ZZ ARMneon_VCGTS, -+//ZZ ARMneon_VCGEU, -+//ZZ ARMneon_VCGES, -+//ZZ ARMneon_VCGTF, -+//ZZ ARMneon_VCGEF, -+//ZZ ARMneon_VCEQ, -+//ZZ ARMneon_VCEQF, -+//ZZ ARMneon_VEXT, -+//ZZ ARMneon_VMUL, -+//ZZ ARMneon_VMULFP, -+//ZZ ARMneon_VMULLU, -+//ZZ ARMneon_VMULLS, -+//ZZ ARMneon_VMULP, -+//ZZ ARMneon_VMULLP, -+//ZZ ARMneon_VQDMULH, -+//ZZ ARMneon_VQRDMULH, -+//ZZ ARMneon_VPADD, -+//ZZ ARMneon_VPMINU, -+//ZZ ARMneon_VPMINS, -+//ZZ ARMneon_VPMINF, -+//ZZ ARMneon_VPMAXU, -+//ZZ ARMneon_VPMAXS, -+//ZZ ARMneon_VPMAXF, -+//ZZ ARMneon_VTBL, -+//ZZ ARMneon_VQDMULL, -+//ZZ ARMneon_VRECPS, -+//ZZ ARMneon_VRSQRTS, -+//ZZ /* ... */ -+//ZZ } -+//ZZ ARMNeonBinOp; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_VSHL=150, -+//ZZ ARMneon_VSAL, /* Yah, not SAR but SAL */ -+//ZZ ARMneon_VQSHL, -+//ZZ ARMneon_VQSAL -+//ZZ } -+//ZZ ARMNeonShiftOp; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_COPY=160, -+//ZZ ARMneon_COPYLU, -+//ZZ ARMneon_COPYLS, -+//ZZ ARMneon_COPYN, -+//ZZ ARMneon_COPYQNSS, -+//ZZ ARMneon_COPYQNUS, -+//ZZ ARMneon_COPYQNUU, -+//ZZ ARMneon_NOT, -+//ZZ ARMneon_EQZ, -+//ZZ ARMneon_DUP, -+//ZZ ARMneon_PADDLS, -+//ZZ ARMneon_PADDLU, -+//ZZ ARMneon_CNT, -+//ZZ ARMneon_CLZ, -+//ZZ ARMneon_CLS, -+//ZZ ARMneon_VCVTxFPxINT, -+//ZZ ARMneon_VQSHLNSS, -+//ZZ ARMneon_VQSHLNUU, -+//ZZ ARMneon_VQSHLNUS, -+//ZZ ARMneon_VCVTFtoU, -+//ZZ ARMneon_VCVTFtoS, -+//ZZ ARMneon_VCVTUtoF, -+//ZZ ARMneon_VCVTStoF, -+//ZZ ARMneon_VCVTFtoFixedU, -+//ZZ ARMneon_VCVTFtoFixedS, -+//ZZ ARMneon_VCVTFixedUtoF, -+//ZZ ARMneon_VCVTFixedStoF, -+//ZZ ARMneon_VCVTF16toF32, -+//ZZ ARMneon_VCVTF32toF16, -+//ZZ ARMneon_REV16, -+//ZZ ARMneon_REV32, -+//ZZ ARMneon_REV64, -+//ZZ ARMneon_ABS, -+//ZZ ARMneon_VNEGF, -+//ZZ ARMneon_VRECIP, -+//ZZ ARMneon_VRECIPF, -+//ZZ ARMneon_VABSFP, -+//ZZ ARMneon_VRSQRTEFP, -+//ZZ ARMneon_VRSQRTE -+//ZZ /* ... */ -+//ZZ } -+//ZZ ARMNeonUnOp; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_SETELEM=200, -+//ZZ ARMneon_GETELEMU, -+//ZZ ARMneon_GETELEMS, -+//ZZ ARMneon_VDUP, -+//ZZ } -+//ZZ ARMNeonUnOpS; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_TRN=210, -+//ZZ ARMneon_ZIP, -+//ZZ ARMneon_UZP -+//ZZ /* ... */ -+//ZZ } -+//ZZ ARMNeonDualOp; -+//ZZ -+//ZZ extern const HChar* showARMNeonBinOp ( ARMNeonBinOp op ); -+//ZZ extern const HChar* showARMNeonUnOp ( ARMNeonUnOp op ); -+//ZZ extern const HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ); -+//ZZ extern const HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ); -+//ZZ extern const HChar* showARMNeonDualOp ( ARMNeonDualOp op ); -+//ZZ extern const HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ); -+//ZZ extern const HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ); -+//ZZ extern const HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ); -+//ZZ extern const HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ); -+//ZZ extern const HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ); -+ -+typedef -+ enum { -+ /* baseline */ -+ ARM64in_Arith=1220, -+ ARM64in_Cmp, -+ ARM64in_Logic, -+ ARM64in_Test, -+ ARM64in_Shift, -+ ARM64in_Unary, -+ ARM64in_MovI, /* int reg-reg move */ -+ ARM64in_Imm64, -+ ARM64in_LdSt64, -+ ARM64in_LdSt32, /* w/ ZX loads */ -+ ARM64in_LdSt16, /* w/ ZX loads */ -+ ARM64in_LdSt8, /* w/ ZX loads */ -+ ARM64in_XDirect, /* direct transfer to GA */ -+ ARM64in_XIndir, /* indirect transfer to GA */ -+ ARM64in_XAssisted, /* assisted transfer to GA */ -+ ARM64in_CSel, -+ ARM64in_Call, -+ ARM64in_AddToSP, /* move SP by small, signed constant */ -+ ARM64in_FromSP, /* move SP to integer register */ -+ ARM64in_Mul, -+//ZZ ARMin_LdrEX, -+//ZZ ARMin_StrEX, -+ /* vector */ -+ ARM64in_VLdStS, /* 32-bit FP load/store, with imm offset */ -+ ARM64in_VLdStD, /* 64-bit FP load/store, with imm offset */ -+ ARM64in_VLdStQ, -+ ARM64in_VCvtI2F, -+ ARM64in_VCvtF2I, -+ ARM64in_VCvtSD, -+ ARM64in_VUnaryD, -+ ARM64in_VUnaryS, -+ ARM64in_VBinD, -+ ARM64in_VBinS, -+ ARM64in_VCmpD, -+ ARM64in_VCmpS, -+ ARM64in_FPCR, -+//ZZ ARMin_VAluS, -+//ZZ ARMin_VCMovD, -+//ZZ ARMin_VCMovS, -+//ZZ ARMin_VXferD, -+//ZZ ARMin_VXferS, -+//ZZ ARMin_VCvtID, -+//ZZ ARMin_MFence, -+//ZZ ARMin_CLREX, -+//ZZ /* Neon */ -+//ZZ ARMin_NLdStD, -+//ZZ ARMin_NUnary, -+//ZZ ARMin_NUnaryS, -+//ZZ ARMin_NDual, -+//ZZ ARMin_NBinary, -+//ZZ ARMin_NBinaryS, -+//ZZ ARMin_NShift, -+//ZZ ARMin_NShl64, // special case 64-bit shift of Dreg by immediate -+ ARM64in_VImmQ, -+ ARM64in_VDfromX, /* Move an Xreg to a Dreg */ -+ ARM64in_VQfromXX, /* Move 2 Xregs to a Qreg */ -+ ARM64in_VXfromQ, /* Move half a Qreg to an Xreg */ -+ ARM64in_VMov, /* vector reg-reg move, 16, 8 or 4 bytes */ -+ /* infrastructure */ -+ ARM64in_EvCheck, /* Event check */ -+//ZZ ARMin_ProfInc /* 64-bit profile counter increment */ -+ } -+ ARM64InstrTag; -+ -+/* Destinations are on the LEFT (first operand) */ -+ -+typedef -+ struct { -+ ARM64InstrTag tag; -+ union { -+ /* --- INTEGER INSTRUCTIONS --- */ -+ /* 64 bit ADD/SUB reg, reg or uimm12<<{0,12} */ -+ struct { -+ HReg dst; -+ HReg argL; -+ ARM64RIA* argR; -+ Bool isAdd; -+ } Arith; -+ /* 64 or 32 bit CMP reg, reg or aimm (SUB and set flags) */ -+ struct { -+ HReg argL; -+ ARM64RIA* argR; -+ Bool is64; -+ } Cmp; -+ /* 64 bit AND/OR/XOR reg, reg or bitfield-immediate */ -+ struct { -+ HReg dst; -+ HReg argL; -+ ARM64RIL* argR; -+ ARM64LogicOp op; -+ } Logic; -+ /* 64 bit TST reg, reg or bimm (AND and set flags) */ -+ struct { -+ HReg argL; -+ ARM64RIL* argR; -+ } Test; -+ /* 64 bit SHL/SHR/SAR, 2nd arg is reg or imm */ -+ struct { -+ HReg dst; -+ HReg argL; -+ ARM64RI6* argR; -+ ARM64ShiftOp op; -+ } Shift; -+ /* NOT/NEG/CLZ, 64 bit only */ -+ struct { -+ HReg dst; -+ HReg src; -+ ARM64UnaryOp op; -+ } Unary; -+ /* MOV dst, src -- reg-reg move for integer registers */ -+ struct { -+ HReg dst; -+ HReg src; -+ } MovI; -+ /* Pseudo-insn; make a 64-bit immediate */ -+ struct { -+ HReg dst; -+ ULong imm64; -+ } Imm64; -+ /* 64-bit load or store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt64; -+ /* zx-32-to-64-bit load, or 32-bit store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt32; -+ /* zx-16-to-64-bit load, or 16-bit store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt16; -+ /* zx-8-to-64-bit load, or 8-bit store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt8; -+ /* Update the guest PC value, then exit requesting to chain -+ to it. May be conditional. Urr, use of Addr64 implicitly -+ assumes that wordsize(guest) == wordsize(host). */ -+ struct { -+ Addr64 dstGA; /* next guest address */ -+ ARM64AMode* amPC; /* amode in guest state for PC */ -+ ARM64CondCode cond; /* can be ARM64cc_AL */ -+ Bool toFastEP; /* chain to the slow or fast point? */ -+ } XDirect; -+ /* Boring transfer to a guest address not known at JIT time. -+ Not chainable. May be conditional. */ -+ struct { -+ HReg dstGA; -+ ARM64AMode* amPC; -+ ARM64CondCode cond; /* can be ARM64cc_AL */ -+ } XIndir; -+ /* Assisted transfer to a guest address, most general case. -+ Not chainable. May be conditional. */ -+ struct { -+ HReg dstGA; -+ ARM64AMode* amPC; -+ ARM64CondCode cond; /* can be ARM64cc_AL */ -+ IRJumpKind jk; -+ } XAssisted; -+ /* CSEL: dst = if cond then argL else argR. cond may be anything. */ -+ struct { -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ ARM64CondCode cond; -+ } CSel; -+ /* Pseudo-insn. Call target (an absolute address), on given -+ condition (which could be ARM64cc_AL). */ -+ struct { -+ RetLoc rloc; /* where the return value will be */ -+ HWord target; -+ ARM64CondCode cond; -+ Int nArgRegs; /* # regs carrying args: 0 .. 8 */ -+ } Call; -+ /* move SP by small, signed constant */ -+ struct { -+ Int simm; /* needs to be 0 % 16 and in the range -4095 -+ .. 4095 inclusive */ -+ } AddToSP; -+ /* move SP to integer register */ -+ struct { -+ HReg dst; -+ } FromSP; -+ /* Integer multiply, with 3 variants: -+ (PLAIN) lo64(64 * 64) -+ (ZX) hi64(64 *u 64) -+ (SX) hi64(64 *s 64) -+ */ -+ struct { -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ ARM64MulOp op; -+ } Mul; -+//ZZ /* LDREX{,H,B} r2, [r4] and -+//ZZ LDREXD r2, r3, [r4] (on LE hosts, transferred value is r3:r2) -+//ZZ Again, hardwired registers since this is not performance -+//ZZ critical, and there are possibly constraints on the -+//ZZ registers that we can't express in the register allocator.*/ -+//ZZ struct { -+//ZZ Int szB; /* 1, 2, 4 or 8 */ -+//ZZ } LdrEX; -+//ZZ /* STREX{,H,B} r0, r2, [r4] and -+//ZZ STREXD r0, r2, r3, [r4] (on LE hosts, transferred value is r3:r2) -+//ZZ r0 = SC( [r4] = r2 ) (8, 16, 32 bit transfers) -+//ZZ r0 = SC( [r4] = r3:r2) (64 bit transfers) -+//ZZ Ditto comment re fixed registers. */ -+//ZZ struct { -+//ZZ Int szB; /* 1, 2, 4 or 8 */ -+//ZZ } StrEX; -+ /* --- INSTRUCTIONS INVOLVING VECTOR REGISTERS --- */ -+ /* 32-bit Fp load/store */ -+ struct { -+ Bool isLoad; -+ HReg sD; -+ HReg rN; -+ UInt uimm12; /* 0 .. 16380 inclusive, 0 % 4 */ -+ } VLdStS; -+ /* 64-bit Fp load/store */ -+ struct { -+ Bool isLoad; -+ HReg dD; -+ HReg rN; -+ UInt uimm12; /* 0 .. 32760 inclusive, 0 % 8 */ -+ } VLdStD; -+ /* 128-bit Vector load/store. */ -+ struct { -+ Bool isLoad; -+ HReg rQ; // data -+ HReg rN; // address -+ } VLdStQ; -+ /* Scalar conversion of int to float. */ -+ struct { -+ ARM64CvtOp how; -+ HReg rD; // dst, a D or S register -+ HReg rS; // src, a W or X register -+ } VCvtI2F; -+ /* Scalar conversion of float to int, w/ specified RM. */ -+ struct { -+ ARM64CvtOp how; -+ HReg rD; // dst, a W or X register -+ HReg rS; // src, a D or S register -+ UChar armRM; // ARM encoded RM: -+ // 00=nearest, 01=+inf, 10=-inf, 11=zero -+ } VCvtF2I; -+ /* Convert between 32-bit and 64-bit FP values (both -+ ways). (FCVT) */ -+ struct { -+ Bool sToD; /* True: F32->F64. False: F64->F32 */ -+ HReg dst; -+ HReg src; -+ } VCvtSD; -+ /* 64-bit FP unary */ -+ struct { -+ ARM64FpUnaryOp op; -+ HReg dst; -+ HReg src; -+ } VUnaryD; -+ /* 32-bit FP unary */ -+ struct { -+ ARM64FpUnaryOp op; -+ HReg dst; -+ HReg src; -+ } VUnaryS; -+ /* 64-bit FP binary arithmetic */ -+ struct { -+ ARM64FpBinOp op; -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ } VBinD; -+ /* 32-bit FP binary arithmetic */ -+ struct { -+ ARM64FpBinOp op; -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ } VBinS; -+ /* 64-bit FP compare */ -+ struct { -+ HReg argL; -+ HReg argR; -+ } VCmpD; -+ /* 32-bit FP compare */ -+ struct { -+ HReg argL; -+ HReg argR; -+ } VCmpS; -+ /* Move a 32-bit value to/from the FPCR */ -+ struct { -+ Bool toFPCR; -+ HReg iReg; -+ } FPCR; -+//ZZ /* 32-bit FP binary arithmetic */ -+//ZZ struct { -+//ZZ ARMVfpOp op; -+//ZZ HReg dst; -+//ZZ HReg argL; -+//ZZ HReg argR; -+//ZZ } VAluS; -+//ZZ /* 64-bit FP mov src to dst on the given condition, which may -+//ZZ not be ARMcc_AL. */ -+//ZZ struct { -+//ZZ ARMCondCode cond; -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ } VCMovD; -+//ZZ /* 32-bit FP mov src to dst on the given condition, which may -+//ZZ not be ARMcc_AL. */ -+//ZZ struct { -+//ZZ ARMCondCode cond; -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ } VCMovS; -+//ZZ /* Transfer a VFP D reg to/from two integer registers (VMOV) */ -+//ZZ struct { -+//ZZ Bool toD; -+//ZZ HReg dD; -+//ZZ HReg rHi; -+//ZZ HReg rLo; -+//ZZ } VXferD; -+//ZZ /* Transfer a VFP S reg to/from an integer register (VMOV) */ -+//ZZ struct { -+//ZZ Bool toS; -+//ZZ HReg fD; -+//ZZ HReg rLo; -+//ZZ } VXferS; -+//ZZ /* Convert between 32-bit ints and 64-bit FP values (both ways -+//ZZ and both signednesses). (FSITOD, FUITOD, FTOSID, FTOUID) */ -+//ZZ struct { -+//ZZ Bool iToD; /* True: I32->F64. False: F64->I32 */ -+//ZZ Bool syned; /* True: I32 is signed. False: I32 is unsigned */ -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ } VCvtID; -+//ZZ /* Mem fence. An insn which fences all loads and stores as -+//ZZ much as possible before continuing. On ARM we emit the -+//ZZ sequence -+//ZZ mcr 15,0,r0,c7,c10,4 (DSB) -+//ZZ mcr 15,0,r0,c7,c10,5 (DMB) -+//ZZ mcr 15,0,r0,c7,c5,4 (ISB) -+//ZZ which is probably total overkill, but better safe than -+//ZZ sorry. -+//ZZ */ -+//ZZ struct { -+//ZZ } MFence; -+//ZZ /* A CLREX instruction. */ -+//ZZ struct { -+//ZZ } CLREX; -+//ZZ /* Neon data processing instruction: 3 registers of the same -+//ZZ length */ -+//ZZ struct { -+//ZZ ARMNeonBinOp op; -+//ZZ HReg dst; -+//ZZ HReg argL; -+//ZZ HReg argR; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NBinary; -+//ZZ struct { -+//ZZ ARMNeonBinOp op; -+//ZZ ARMNRS* dst; -+//ZZ ARMNRS* argL; -+//ZZ ARMNRS* argR; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NBinaryS; -+//ZZ struct { -+//ZZ ARMNeonShiftOp op; -+//ZZ HReg dst; -+//ZZ HReg argL; -+//ZZ HReg argR; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NShift; -+//ZZ struct { -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ UInt amt; /* 1..63 only */ -+//ZZ } NShl64; -+//ZZ struct { -+//ZZ Bool isLoad; -+//ZZ HReg dD; -+//ZZ ARMAModeN *amode; -+//ZZ } NLdStD -+//ZZ struct { -+//ZZ ARMNeonUnOpS op; -+//ZZ ARMNRS* dst; -+//ZZ ARMNRS* src; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NUnaryS; -+//ZZ struct { -+//ZZ ARMNeonUnOp op; -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NUnary; -+//ZZ /* Takes two arguments and modifies them both. */ -+//ZZ struct { -+//ZZ ARMNeonDualOp op; -+//ZZ HReg arg1; -+//ZZ HReg arg2; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NDual; -+ struct { -+ HReg rQ; -+ UShort imm; /* Same 1-bit-per-byte encoding as IR */ -+ } VImmQ; -+ struct { -+ HReg rD; -+ HReg rX; -+ } VDfromX; -+ struct { -+ HReg rQ; -+ HReg rXhi; -+ HReg rXlo; -+ } VQfromXX; -+ struct { -+ HReg rX; -+ HReg rQ; -+ UInt laneNo; /* either 0 or 1 */ -+ } VXfromQ; -+ /* MOV dst, src -- reg-reg move for vector registers */ -+ struct { -+ UInt szB; // 16=mov qD,qS; 8=mov dD,dS; 4=mov sD,sS -+ HReg dst; -+ HReg src; -+ } VMov; -+ struct { -+ ARM64AMode* amCounter; -+ ARM64AMode* amFailAddr; -+ } EvCheck; -+//ZZ struct { -+//ZZ /* No fields. The address of the counter to inc is -+//ZZ installed later, post-translation, by patching it in, -+//ZZ as it is not known at translation time. */ -+//ZZ } ProfInc; -+ } ARM64in; -+ } -+ ARM64Instr; -+ -+//ZZ -+extern ARM64Instr* ARM64Instr_Arith ( HReg, HReg, ARM64RIA*, Bool isAdd ); -+extern ARM64Instr* ARM64Instr_Cmp ( HReg, ARM64RIA*, Bool is64 ); -+extern ARM64Instr* ARM64Instr_Logic ( HReg, HReg, ARM64RIL*, ARM64LogicOp ); -+extern ARM64Instr* ARM64Instr_Test ( HReg, ARM64RIL* ); -+extern ARM64Instr* ARM64Instr_Shift ( HReg, HReg, ARM64RI6*, ARM64ShiftOp ); -+extern ARM64Instr* ARM64Instr_Unary ( HReg, HReg, ARM64UnaryOp ); -+//ZZ extern ARMInstr* ARMInstr_CmpOrTst ( Bool isCmp, HReg, ARMRI84* ); -+extern ARM64Instr* ARM64Instr_MovI ( HReg, HReg ); -+extern ARM64Instr* ARM64Instr_Imm64 ( HReg, ULong ); -+extern ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg, ARM64AMode* ); -+extern ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg, ARM64AMode* ); -+extern ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg, ARM64AMode* ); -+extern ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg, ARM64AMode* ); -+//ZZ extern ARMInstr* ARMInstr_Ld8S ( ARMCondCode, HReg, ARMAMode2* ); -+extern ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, Bool toFastEP ); -+extern ARM64Instr* ARM64Instr_XIndir ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond ); -+extern ARM64Instr* ARM64Instr_XAssisted ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, IRJumpKind jk ); -+extern ARM64Instr* ARM64Instr_CSel ( HReg dst, HReg argL, HReg argR, -+ ARM64CondCode cond ); -+extern ARM64Instr* ARM64Instr_Call ( ARM64CondCode, HWord, Int nArgRegs, -+ RetLoc rloc ); -+extern ARM64Instr* ARM64Instr_AddToSP ( Int simm ); -+extern ARM64Instr* ARM64Instr_FromSP ( HReg dst ); -+extern ARM64Instr* ARM64Instr_Mul ( HReg dst, HReg argL, HReg argR, -+ ARM64MulOp op ); -+ -+//ZZ extern ARMInstr* ARMInstr_Mul ( ARMMulOp op ); -+//ZZ extern ARMInstr* ARMInstr_LdrEX ( Int szB ); -+//ZZ extern ARMInstr* ARMInstr_StrEX ( Int szB ); -+extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, -+ UInt uimm12 /* 0 .. 16380, 0 % 4 */ ); -+extern ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, -+ UInt uimm12 /* 0 .. 32760, 0 % 8 */ ); -+extern ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ); -+extern ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ); -+extern ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS, -+ UChar armRM ); -+extern ARM64Instr* ARM64Instr_VCvtSD ( Bool sToD, HReg dst, HReg src ); -+extern ARM64Instr* ARM64Instr_VUnaryD ( ARM64FpUnaryOp op, HReg dst, HReg src ); -+extern ARM64Instr* ARM64Instr_VUnaryS ( ARM64FpUnaryOp op, HReg dst, HReg src ); -+extern ARM64Instr* ARM64Instr_VBinD ( ARM64FpBinOp op, HReg, HReg, HReg ); -+extern ARM64Instr* ARM64Instr_VBinS ( ARM64FpBinOp op, HReg, HReg, HReg ); -+extern ARM64Instr* ARM64Instr_VCmpD ( HReg argL, HReg argR ); -+extern ARM64Instr* ARM64Instr_VCmpS ( HReg argL, HReg argR ); -+extern ARM64Instr* ARM64Instr_FPCR ( Bool toFPCR, HReg iReg ); -+//ZZ extern ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg, HReg, HReg ); -+//ZZ extern ARMInstr* ARMInstr_VCMovD ( ARMCondCode, HReg dst, HReg src ); -+//ZZ extern ARMInstr* ARMInstr_VCMovS ( ARMCondCode, HReg dst, HReg src ); -+//ZZ extern ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ); -+//ZZ extern ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ); -+//ZZ extern ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned, -+//ZZ HReg dst, HReg src ); -+//ZZ extern ARMInstr* ARMInstr_MFence ( void ); -+//ZZ extern ARMInstr* ARMInstr_CLREX ( void ); -+//ZZ extern ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg, ARMAModeN* ); -+//ZZ extern ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp, HReg, HReg, UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS, ARMNRS*, ARMNRS*, -+//ZZ UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NDual ( ARMNeonDualOp, HReg, HReg, UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp, HReg, HReg, HReg, -+//ZZ UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp, HReg, HReg, HReg, -+//ZZ UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NShl64 ( HReg, HReg, UInt ); -+extern ARM64Instr* ARM64Instr_VImmQ ( HReg, UShort ); -+extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX ); -+extern ARM64Instr* ARM64Instr_VQfromXX( HReg rQ, HReg rXhi, HReg rXlo ); -+extern ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo ); -+extern ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src ); -+ -+extern ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter, -+ ARM64AMode* amFailAddr ); -+//ZZ extern ARMInstr* ARMInstr_ProfInc ( void ); -+ -+extern void ppARM64Instr ( ARM64Instr* ); -+ -+ -+/* Some functions that insulate the register allocator from details -+ of the underlying instruction set. */ -+extern void getRegUsage_ARM64Instr ( HRegUsage*, ARM64Instr*, Bool ); -+extern void mapRegs_ARM64Instr ( HRegRemap*, ARM64Instr*, Bool ); -+extern Bool isMove_ARM64Instr ( ARM64Instr*, HReg*, HReg* ); -+extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, -+ UChar* buf, Int nbuf, ARM64Instr* i, -+ Bool mode64, -+ void* disp_cp_chain_me_to_slowEP, -+ void* disp_cp_chain_me_to_fastEP, -+ void* disp_cp_xindir, -+ void* disp_cp_xassisted ); -+ -+extern void genSpill_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offset, Bool ); -+extern void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offset, Bool ); -+ -+extern void getAllocableRegs_ARM64 ( Int*, HReg** ); -+extern HInstrArray* iselSB_ARM64 ( IRSB*, -+ VexArch, -+ VexArchInfo*, -+ VexAbiInfo*, -+ Int offs_Host_EvC_Counter, -+ Int offs_Host_EvC_FailAddr, -+ Bool chainingAllowed, -+ Bool addProfInc, -+ Addr64 max_ga ); -+ -+/* How big is an event check? This is kind of a kludge because it -+ depends on the offsets of host_EvC_FAILADDR and -+ host_EvC_COUNTER. */ -+extern Int evCheckSzB_ARM64 ( void ); -+ -+/* Perform a chaining and unchaining of an XDirect jump. */ -+extern VexInvalRange chainXDirect_ARM64 ( void* place_to_chain, -+ void* disp_cp_chain_me_EXPECTED, -+ void* place_to_jump_to ); -+ -+//ZZ extern VexInvalRange unchainXDirect_ARM ( void* place_to_unchain, -+//ZZ void* place_to_jump_to_EXPECTED, -+//ZZ void* disp_cp_chain_me ); -+//ZZ -+//ZZ /* Patch the counter location into an existing ProfInc point. */ -+//ZZ extern VexInvalRange patchProfInc_ARM ( void* place_to_patch, -+//ZZ ULong* location_of_counter ); -+ -+ -+#endif /* ndef __VEX_HOST_ARM64_DEFS_H */ -+ -+/*---------------------------------------------------------------*/ -+/*--- end host_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -Index: VEX/priv/ir_opt.c -=================================================================== ---- VEX/priv/ir_opt.c.orig -+++ VEX/priv/ir_opt.c -@@ -1178,6 +1178,14 @@ static Bool isZeroU32 ( IRExpr* e ) - && e->Iex.Const.con->Ico.U32 == 0); - } - -+/* Is this literally IRExpr_Const(IRConst_U64(0)) ? */ -+static Bool isZeroU64 ( IRExpr* e ) -+{ -+ return toBool( e->tag == Iex_Const -+ && e->Iex.Const.con->tag == Ico_U64 -+ && e->Iex.Const.con->Ico.U64 == 0); -+} -+ - /* Is this an integer constant with value 0 ? */ - static Bool isZeroU ( IRExpr* e ) - { -@@ -1224,6 +1232,7 @@ static IRExpr* mkZeroOfPrimopResultType - case Iop_Xor16: return IRExpr_Const(IRConst_U16(0)); - case Iop_Sub32: - case Iop_Xor32: return IRExpr_Const(IRConst_U32(0)); -+ case Iop_And64: - case Iop_Sub64: - case Iop_Xor64: return IRExpr_Const(IRConst_U64(0)); - case Iop_XorV128: return IRExpr_Const(IRConst_V128(0)); -@@ -2149,6 +2158,14 @@ static IRExpr* fold_Expr ( IRExpr** env, - e2 = e->Iex.Binop.arg1; - break; - } -+ if (/* could handle other And cases here too, but so -+ far not */ -+ e->Iex.Binop.op == Iop_And64 -+ && (isZeroU64(e->Iex.Binop.arg1) -+ || isZeroU64(e->Iex.Binop.arg2))) { -+ e2 = mkZeroOfPrimopResultType(e->Iex.Binop.op); -+ break; -+ } - break; - - case Iop_OrV128: -Index: VEX/priv/host_arm64_isel.c -=================================================================== ---- /dev/null -+++ VEX/priv/host_arm64_isel.c -@@ -0,0 +1,6928 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin host_arm64_isel.c ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "libvex_basictypes.h" -+#include "libvex_ir.h" -+#include "libvex.h" -+#include "ir_match.h" -+ -+#include "main_util.h" -+#include "main_globals.h" -+#include "host_generic_regs.h" -+#include "host_generic_simd64.h" // for 32-bit SIMD helpers -+#include "host_arm64_defs.h" -+ -+ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ /*--- ARMvfp control word stuff ---*/ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ -+//ZZ /* Vex-generated code expects to run with the FPU set as follows: all -+//ZZ exceptions masked, round-to-nearest, non-vector mode, with the NZCV -+//ZZ flags cleared, and FZ (flush to zero) disabled. Curiously enough, -+//ZZ this corresponds to a FPSCR value of zero. -+//ZZ -+//ZZ fpscr should therefore be zero on entry to Vex-generated code, and -+//ZZ should be unchanged at exit. (Or at least the bottom 28 bits -+//ZZ should be zero). -+//ZZ */ -+//ZZ -+//ZZ #define DEFAULT_FPSCR 0 -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISelEnv ---*/ -+/*---------------------------------------------------------*/ -+ -+/* This carries around: -+ -+ - A mapping from IRTemp to IRType, giving the type of any IRTemp we -+ might encounter. This is computed before insn selection starts, -+ and does not change. -+ -+ - A mapping from IRTemp to HReg. This tells the insn selector -+ which virtual register is associated with each IRTemp temporary. -+ This is computed before insn selection starts, and does not -+ change. We expect this mapping to map precisely the same set of -+ IRTemps as the type mapping does. -+ -+ |vregmap| holds the primary register for the IRTemp. -+ |vregmapHI| is only used for 128-bit integer-typed -+ IRTemps. It holds the identity of a second -+ 64-bit virtual HReg, which holds the high half -+ of the value. -+ -+ - The code array, that is, the insns selected so far. -+ -+ - A counter, for generating new virtual registers. -+ -+ - The host hardware capabilities word. This is set at the start -+ and does not change. -+ -+ - A Bool for indicating whether we may generate chain-me -+ instructions for control flow transfers, or whether we must use -+ XAssisted. -+ -+ - The maximum guest address of any guest insn in this block. -+ Actually, the address of the highest-addressed byte from any insn -+ in this block. Is set at the start and does not change. This is -+ used for detecting jumps which are definitely forward-edges from -+ this block, and therefore can be made (chained) to the fast entry -+ point of the destination, thereby avoiding the destination's -+ event check. -+ -+ - An IRExpr*, which may be NULL, holding the IR expression (an -+ IRRoundingMode-encoded value) to which the FPU's rounding mode -+ was most recently set. Setting to NULL is always safe. Used to -+ avoid redundant settings of the FPU's rounding mode, as -+ described in set_FPCR_rounding_mode below. -+ -+ Note, this is all (well, mostly) host-independent. -+*/ -+ -+typedef -+ struct { -+ /* Constant -- are set at the start and do not change. */ -+ IRTypeEnv* type_env; -+ -+ HReg* vregmap; -+ HReg* vregmapHI; -+ Int n_vregmap; -+ -+ UInt hwcaps; -+ -+ Bool chainingAllowed; -+ Addr64 max_ga; -+ -+ /* These are modified as we go along. */ -+ HInstrArray* code; -+ Int vreg_ctr; -+ -+ IRExpr* previous_rm; -+ } -+ ISelEnv; -+ -+static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp ) -+{ -+ vassert(tmp >= 0); -+ vassert(tmp < env->n_vregmap); -+ return env->vregmap[tmp]; -+} -+ -+static void addInstr ( ISelEnv* env, ARM64Instr* instr ) -+{ -+ addHInstr(env->code, instr); -+ if (vex_traceflags & VEX_TRACE_VCODE) { -+ ppARM64Instr(instr); -+ vex_printf("\n"); -+ } -+} -+ -+static HReg newVRegI ( ISelEnv* env ) -+{ -+ HReg reg = mkHReg(env->vreg_ctr, HRcInt64, True/*virtual reg*/); -+ env->vreg_ctr++; -+ return reg; -+} -+ -+static HReg newVRegD ( ISelEnv* env ) -+{ -+ HReg reg = mkHReg(env->vreg_ctr, HRcFlt64, True/*virtual reg*/); -+ env->vreg_ctr++; -+ return reg; -+} -+ -+//ZZ static HReg newVRegF ( ISelEnv* env ) -+//ZZ { -+//ZZ HReg reg = mkHReg(env->vreg_ctr, HRcFlt32, True/*virtual reg*/); -+//ZZ env->vreg_ctr++; -+//ZZ return reg; -+//ZZ } -+ -+static HReg newVRegV ( ISelEnv* env ) -+{ -+ HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); -+ env->vreg_ctr++; -+ return reg; -+} -+ -+//ZZ /* These are duplicated in guest_arm_toIR.c */ -+//ZZ static IRExpr* unop ( IROp op, IRExpr* a ) -+//ZZ { -+//ZZ return IRExpr_Unop(op, a); -+//ZZ } -+//ZZ -+//ZZ static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) -+//ZZ { -+//ZZ return IRExpr_Binop(op, a1, a2); -+//ZZ } -+//ZZ -+//ZZ static IRExpr* bind ( Int binder ) -+//ZZ { -+//ZZ return IRExpr_Binder(binder); -+//ZZ } -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Forward declarations ---*/ -+/*---------------------------------------------------------*/ -+ -+/* These are organised as iselXXX and iselXXX_wrk pairs. The -+ iselXXX_wrk do the real work, but are not to be called directly. -+ For each XXX, iselXXX calls its iselXXX_wrk counterpart, then -+ checks that all returned registers are virtual. You should not -+ call the _wrk version directly. -+ -+ Because some forms of ARM64 memory amodes are implicitly scaled by -+ the access size, iselIntExpr_AMode takes an IRType which tells it -+ the type of the access for which the amode is to be used. This -+ type needs to be correct, else you'll get incorrect code. -+*/ -+static ARM64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, -+ IRExpr* e, IRType dty ); -+static ARM64AMode* iselIntExpr_AMode ( ISelEnv* env, -+ IRExpr* e, IRType dty ); -+ -+static ARM64RIA* iselIntExpr_RIA_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64RIA* iselIntExpr_RIA ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64RIL* iselIntExpr_RIL_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64RIL* iselIntExpr_RIL ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64RI6* iselIntExpr_RI6_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64RI6* iselIntExpr_RI6 ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64CondCode iselCondCode ( ISelEnv* env, IRExpr* e ); -+ -+static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ); -+ -+static void iselInt128Expr_wrk ( /*OUT*/HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ); -+static void iselInt128Expr ( /*OUT*/HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ); -+ -+ -+//ZZ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, -+//ZZ ISelEnv* env, IRExpr* e ); -+//ZZ static void iselInt64Expr ( HReg* rHi, HReg* rLo, -+//ZZ ISelEnv* env, IRExpr* e ); -+ -+static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ); -+ -+static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ); -+ -+//ZZ static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ); -+//ZZ static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e ); -+ -+static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselV128Expr ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64RIL* mb_mkARM64RIL_I ( ULong imm64 ); -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Misc helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Generate an amode suitable for a 64-bit sized access relative to -+ the baseblock register (X21). This generates an RI12 amode, which -+ means its scaled by the access size, which is why the access size -+ -- 64 bit -- is stated explicitly here. Consequently |off| needs -+ to be divisible by 8. */ -+static ARM64AMode* mk_baseblock_64bit_access_amode ( UInt off ) -+{ -+ vassert(off < (8 << 12)); /* otherwise it's unrepresentable */ -+ vassert((off & 7) == 0); /* ditto */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 3, 8/*scale*/); -+} -+ -+/* Ditto, for 32 bit accesses. */ -+static ARM64AMode* mk_baseblock_32bit_access_amode ( UInt off ) -+{ -+ vassert(off < (4 << 12)); /* otherwise it's unrepresentable */ -+ vassert((off & 3) == 0); /* ditto */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 2, 4/*scale*/); -+} -+ -+/* Ditto, for 16 bit accesses. */ -+static ARM64AMode* mk_baseblock_16bit_access_amode ( UInt off ) -+{ -+ vassert(off < (2 << 12)); /* otherwise it's unrepresentable */ -+ vassert((off & 1) == 0); /* ditto */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 1, 2/*scale*/); -+} -+ -+/* Ditto, for 8 bit accesses. */ -+static ARM64AMode* mk_baseblock_8bit_access_amode ( UInt off ) -+{ -+ vassert(off < (1 << 12)); /* otherwise it's unrepresentable */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 0, 1/*scale*/); -+} -+ -+static HReg mk_baseblock_128bit_access_addr ( ISelEnv* env, UInt off ) -+{ -+ vassert(off < (1<<12)); -+ HReg r = newVRegI(env); -+ addInstr(env, ARM64Instr_Arith(r, hregARM64_X21(), -+ ARM64RIA_I12(off,0), True/*isAdd*/)); -+ return r; -+} -+ -+static HReg get_baseblock_register ( void ) -+{ -+ return hregARM64_X21(); -+} -+ -+/* Generate code to zero extend a 32 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_z_32_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RIL* mask = ARM64RIL_I13(1, 0, 31); /* encodes 0xFFFFFFFF */ -+ addInstr(env, ARM64Instr_Logic(dst, src, mask, ARM64lo_AND)); -+ return dst; -+} -+ -+/* Generate code to sign extend a 16 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_s_16_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n48 = ARM64RI6_I6(48); -+ addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SAR)); -+ return dst; -+} -+ -+/* Generate code to zero extend a 16 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_z_16_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n48 = ARM64RI6_I6(48); -+ addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SHR)); -+ return dst; -+} -+ -+/* Generate code to sign extend a 32 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_s_32_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n32 = ARM64RI6_I6(32); -+ addInstr(env, ARM64Instr_Shift(dst, src, n32, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n32, ARM64sh_SAR)); -+ return dst; -+} -+ -+/* Generate code to sign extend a 8 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_s_8_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n56 = ARM64RI6_I6(56); -+ addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n56, ARM64sh_SAR)); -+ return dst; -+} -+ -+static HReg widen_z_8_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n56 = ARM64RI6_I6(56); -+ addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n56, ARM64sh_SHR)); -+ return dst; -+} -+ -+/* Is this IRExpr_Const(IRConst_U64(0)) ? */ -+static Bool isZeroU64 ( IRExpr* e ) { -+ if (e->tag != Iex_Const) return False; -+ IRConst* con = e->Iex.Const.con; -+ vassert(con->tag == Ico_U64); -+ return con->Ico.U64 == 0; -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: FP rounding mode helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Set the FP rounding mode: 'mode' is an I32-typed expression -+ denoting a value in the range 0 .. 3, indicating a round mode -+ encoded as per type IRRoundingMode -- the first four values only -+ (Irrm_NEAREST, Irrm_NegINF, Irrm_PosINF, Irrm_ZERO). Set the PPC -+ FSCR to have the same rounding. -+ -+ For speed & simplicity, we're setting the *entire* FPCR here. -+ -+ Setting the rounding mode is expensive. So this function tries to -+ avoid repeatedly setting the rounding mode to the same thing by -+ first comparing 'mode' to the 'mode' tree supplied in the previous -+ call to this function, if any. (The previous value is stored in -+ env->previous_rm.) If 'mode' is a single IR temporary 't' and -+ env->previous_rm is also just 't', then the setting is skipped. -+ -+ This is safe because of the SSA property of IR: an IR temporary can -+ only be defined once and so will have the same value regardless of -+ where it appears in the block. Cool stuff, SSA. -+ -+ A safety condition: all attempts to set the RM must be aware of -+ this mechanism - by being routed through the functions here. -+ -+ Of course this only helps if blocks where the RM is set more than -+ once and it is set to the same value each time, *and* that value is -+ held in the same IR temporary each time. In order to assure the -+ latter as much as possible, the IR optimiser takes care to do CSE -+ on any block with any sign of floating point activity. -+*/ -+static -+void set_FPCR_rounding_mode ( ISelEnv* env, IRExpr* mode ) -+{ -+ vassert(typeOfIRExpr(env->type_env,mode) == Ity_I32); -+ -+ /* Do we need to do anything? */ -+ if (env->previous_rm -+ && env->previous_rm->tag == Iex_RdTmp -+ && mode->tag == Iex_RdTmp -+ && env->previous_rm->Iex.RdTmp.tmp == mode->Iex.RdTmp.tmp) { -+ /* no - setting it to what it was before. */ -+ vassert(typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32); -+ return; -+ } -+ -+ /* No luck - we better set it, and remember what we set it to. */ -+ env->previous_rm = mode; -+ -+ /* Only supporting the rounding-mode bits - the rest of FPCR is set -+ to zero - so we can set the whole register at once (faster). */ -+ -+ /* This isn't simple, because 'mode' carries an IR rounding -+ encoding, and we need to translate that to an ARM64 FP one: -+ The IR encoding: -+ 00 to nearest (the default) -+ 10 to +infinity -+ 01 to -infinity -+ 11 to zero -+ The ARM64 FP encoding: -+ 00 to nearest -+ 01 to +infinity -+ 10 to -infinity -+ 11 to zero -+ Easy enough to do; just swap the two bits. -+ */ -+ HReg irrm = iselIntExpr_R(env, mode); -+ HReg tL = newVRegI(env); -+ HReg tR = newVRegI(env); -+ HReg t3 = newVRegI(env); -+ /* tL = irrm << 1; -+ tR = irrm >> 1; if we're lucky, these will issue together -+ tL &= 2; -+ tR &= 1; ditto -+ t3 = tL | tR; -+ t3 <<= 22; -+ fmxr fpscr, t3 -+ */ -+ ARM64RIL* ril_one = mb_mkARM64RIL_I(1); -+ ARM64RIL* ril_two = mb_mkARM64RIL_I(2); -+ vassert(ril_one && ril_two); -+ addInstr(env, ARM64Instr_Shift(tL, irrm, ARM64RI6_I6(1), ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(tR, irrm, ARM64RI6_I6(1), ARM64sh_SHR)); -+ addInstr(env, ARM64Instr_Logic(tL, tL, ril_two, ARM64lo_AND)); -+ addInstr(env, ARM64Instr_Logic(tR, tR, ril_one, ARM64lo_AND)); -+ addInstr(env, ARM64Instr_Logic(t3, tL, ARM64RIL_R(tR), ARM64lo_OR)); -+ addInstr(env, ARM64Instr_Shift(t3, t3, ARM64RI6_I6(22), ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_FPCR(True/*toFPCR*/, t3)); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Function call helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Used only in doHelperCall. See big comment in doHelperCall re -+ handling of register-parameter args. This function figures out -+ whether evaluation of an expression might require use of a fixed -+ register. If in doubt return True (safe but suboptimal). -+*/ -+static -+Bool mightRequireFixedRegs ( IRExpr* e ) -+{ -+ if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(e))) { -+ // These are always "safe" -- either a copy of SP in some -+ // arbitrary vreg, or a copy of x21, respectively. -+ return False; -+ } -+ /* Else it's a "normal" expression. */ -+ switch (e->tag) { -+ case Iex_RdTmp: case Iex_Const: case Iex_Get: -+ return False; -+ default: -+ return True; -+ } -+} -+ -+ -+/* Do a complete function call. |guard| is a Ity_Bit expression -+ indicating whether or not the call happens. If guard==NULL, the -+ call is unconditional. |retloc| is set to indicate where the -+ return value is after the call. The caller (of this fn) must -+ generate code to add |stackAdjustAfterCall| to the stack pointer -+ after the call is done. Returns True iff it managed to handle this -+ combination of arg/return types, else returns False. */ -+ -+static -+Bool doHelperCall ( /*OUT*/UInt* stackAdjustAfterCall, -+ /*OUT*/RetLoc* retloc, -+ ISelEnv* env, -+ IRExpr* guard, -+ IRCallee* cee, IRType retTy, IRExpr** args ) -+{ -+ ARM64CondCode cc; -+ HReg argregs[ARM64_N_ARGREGS]; -+ HReg tmpregs[ARM64_N_ARGREGS]; -+ Bool go_fast; -+ Int n_args, i, nextArgReg; -+ ULong target; -+ -+ vassert(ARM64_N_ARGREGS == 8); -+ -+ /* Set default returns. We'll update them later if needed. */ -+ *stackAdjustAfterCall = 0; -+ *retloc = mk_RetLoc_INVALID(); -+ -+ /* These are used for cross-checking that IR-level constraints on -+ the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */ -+ UInt nVECRETs = 0; -+ UInt nBBPTRs = 0; -+ -+ /* Marshal args for a call and do the call. -+ -+ This function only deals with a tiny set of possibilities, which -+ cover all helpers in practice. The restrictions are that only -+ arguments in registers are supported, hence only -+ ARM64_N_REGPARMS x 64 integer bits in total can be passed. In -+ fact the only supported arg type is I64. -+ -+ The return type can be I{64,32} or V128. In the V128 case, it -+ is expected that |args| will contain the special node -+ IRExpr_VECRET(), in which case this routine generates code to -+ allocate space on the stack for the vector return value. Since -+ we are not passing any scalars on the stack, it is enough to -+ preallocate the return space before marshalling any arguments, -+ in this case. -+ -+ |args| may also contain IRExpr_BBPTR(), in which case the -+ value in x21 is passed as the corresponding argument. -+ -+ Generating code which is both efficient and correct when -+ parameters are to be passed in registers is difficult, for the -+ reasons elaborated in detail in comments attached to -+ doHelperCall() in priv/host-x86/isel.c. Here, we use a variant -+ of the method described in those comments. -+ -+ The problem is split into two cases: the fast scheme and the -+ slow scheme. In the fast scheme, arguments are computed -+ directly into the target (real) registers. This is only safe -+ when we can be sure that computation of each argument will not -+ trash any real registers set by computation of any other -+ argument. -+ -+ In the slow scheme, all args are first computed into vregs, and -+ once they are all done, they are moved to the relevant real -+ regs. This always gives correct code, but it also gives a bunch -+ of vreg-to-rreg moves which are usually redundant but are hard -+ for the register allocator to get rid of. -+ -+ To decide which scheme to use, all argument expressions are -+ first examined. If they are all so simple that it is clear they -+ will be evaluated without use of any fixed registers, use the -+ fast scheme, else use the slow scheme. Note also that only -+ unconditional calls may use the fast scheme, since having to -+ compute a condition expression could itself trash real -+ registers. -+ -+ Note this requires being able to examine an expression and -+ determine whether or not evaluation of it might use a fixed -+ register. That requires knowledge of how the rest of this insn -+ selector works. Currently just the following 3 are regarded as -+ safe -- hopefully they cover the majority of arguments in -+ practice: IRExpr_Tmp IRExpr_Const IRExpr_Get. -+ */ -+ -+ /* Note that the cee->regparms field is meaningless on ARM64 hosts -+ (since there is only one calling convention) and so we always -+ ignore it. */ -+ -+ n_args = 0; -+ for (i = 0; args[i]; i++) { -+ IRExpr* arg = args[i]; -+ if (UNLIKELY(arg->tag == Iex_VECRET)) { -+ nVECRETs++; -+ } else if (UNLIKELY(arg->tag == Iex_BBPTR)) { -+ nBBPTRs++; -+ } -+ n_args++; -+ } -+ -+ /* If this fails, the IR is ill-formed */ -+ vassert(nBBPTRs == 0 || nBBPTRs == 1); -+ -+ /* If we have a VECRET, allocate space on the stack for the return -+ value, and record the stack pointer after that. */ -+ HReg r_vecRetAddr = INVALID_HREG; -+ if (nVECRETs == 1) { -+ vassert(retTy == Ity_V128 || retTy == Ity_V256); -+ vassert(retTy != Ity_V256); // we don't handle that yet (if ever) -+ r_vecRetAddr = newVRegI(env); -+ addInstr(env, ARM64Instr_AddToSP(-16)); -+ addInstr(env, ARM64Instr_FromSP(r_vecRetAddr)); -+ } else { -+ // If either of these fail, the IR is ill-formed -+ vassert(retTy != Ity_V128 && retTy != Ity_V256); -+ vassert(nVECRETs == 0); -+ } -+ -+ argregs[0] = hregARM64_X0(); -+ argregs[1] = hregARM64_X1(); -+ argregs[2] = hregARM64_X2(); -+ argregs[3] = hregARM64_X3(); -+ argregs[4] = hregARM64_X4(); -+ argregs[5] = hregARM64_X5(); -+ argregs[6] = hregARM64_X6(); -+ argregs[7] = hregARM64_X7(); -+ -+ tmpregs[0] = tmpregs[1] = tmpregs[2] = tmpregs[3] = INVALID_HREG; -+ tmpregs[4] = tmpregs[5] = tmpregs[6] = tmpregs[7] = INVALID_HREG; -+ -+ /* First decide which scheme (slow or fast) is to be used. First -+ assume the fast scheme, and select slow if any contraindications -+ (wow) appear. */ -+ -+ go_fast = True; -+ -+ if (guard) { -+ if (guard->tag == Iex_Const -+ && guard->Iex.Const.con->tag == Ico_U1 -+ && guard->Iex.Const.con->Ico.U1 == True) { -+ /* unconditional */ -+ } else { -+ /* Not manifestly unconditional -- be conservative. */ -+ go_fast = False; -+ } -+ } -+ -+ if (go_fast) { -+ for (i = 0; i < n_args; i++) { -+ if (mightRequireFixedRegs(args[i])) { -+ go_fast = False; -+ break; -+ } -+ } -+ } -+ -+ if (go_fast) { -+ if (retTy == Ity_V128 || retTy == Ity_V256) -+ go_fast = False; -+ } -+ -+ /* At this point the scheme to use has been established. Generate -+ code to get the arg values into the argument rregs. If we run -+ out of arg regs, give up. */ -+ -+ if (go_fast) { -+ -+ /* FAST SCHEME */ -+ nextArgReg = 0; -+ -+ for (i = 0; i < n_args; i++) { -+ IRExpr* arg = args[i]; -+ -+ IRType aTy = Ity_INVALID; -+ if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg))) -+ aTy = typeOfIRExpr(env->type_env, args[i]); -+ -+ if (nextArgReg >= ARM64_N_ARGREGS) -+ return False; /* out of argregs */ -+ -+ if (aTy == Ity_I64) { -+ addInstr(env, ARM64Instr_MovI( argregs[nextArgReg], -+ iselIntExpr_R(env, args[i]) )); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_BBPTR) { -+ vassert(0); //ATC -+ addInstr(env, ARM64Instr_MovI( argregs[nextArgReg], -+ hregARM64_X21() )); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_VECRET) { -+ // because of the go_fast logic above, we can't get here, -+ // since vector return values makes us use the slow path -+ // instead. -+ vassert(0); -+ } -+ else -+ return False; /* unhandled arg type */ -+ } -+ -+ /* Fast scheme only applies for unconditional calls. Hence: */ -+ cc = ARM64cc_AL; -+ -+ } else { -+ -+ /* SLOW SCHEME; move via temporaries */ -+ nextArgReg = 0; -+ -+ for (i = 0; i < n_args; i++) { -+ IRExpr* arg = args[i]; -+ -+ IRType aTy = Ity_INVALID; -+ if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg))) -+ aTy = typeOfIRExpr(env->type_env, args[i]); -+ -+ if (nextArgReg >= ARM64_N_ARGREGS) -+ return False; /* out of argregs */ -+ -+ if (aTy == Ity_I64) { -+ tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_BBPTR) { -+ vassert(0); //ATC -+ tmpregs[nextArgReg] = hregARM64_X21(); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_VECRET) { -+ vassert(!hregIsInvalid(r_vecRetAddr)); -+ tmpregs[nextArgReg] = r_vecRetAddr; -+ nextArgReg++; -+ } -+ else -+ return False; /* unhandled arg type */ -+ } -+ -+ /* Now we can compute the condition. We can't do it earlier -+ because the argument computations could trash the condition -+ codes. Be a bit clever to handle the common case where the -+ guard is 1:Bit. */ -+ cc = ARM64cc_AL; -+ if (guard) { -+ if (guard->tag == Iex_Const -+ && guard->Iex.Const.con->tag == Ico_U1 -+ && guard->Iex.Const.con->Ico.U1 == True) { -+ /* unconditional -- do nothing */ -+ } else { -+ cc = iselCondCode( env, guard ); -+ } -+ } -+ -+ /* Move the args to their final destinations. */ -+ for (i = 0; i < nextArgReg; i++) { -+ vassert(!(hregIsInvalid(tmpregs[i]))); -+ /* None of these insns, including any spill code that might -+ be generated, may alter the condition codes. */ -+ addInstr( env, ARM64Instr_MovI( argregs[i], tmpregs[i] ) ); -+ } -+ -+ } -+ -+ /* Should be assured by checks above */ -+ vassert(nextArgReg <= ARM64_N_ARGREGS); -+ -+ /* Do final checks, set the return values, and generate the call -+ instruction proper. */ -+ vassert(nBBPTRs == 0 || nBBPTRs == 1); -+ vassert(nVECRETs == (retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0); -+ vassert(*stackAdjustAfterCall == 0); -+ vassert(is_RetLoc_INVALID(*retloc)); -+ switch (retTy) { -+ case Ity_INVALID: -+ /* Function doesn't return a value. */ -+ *retloc = mk_RetLoc_simple(RLPri_None); -+ break; -+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: -+ *retloc = mk_RetLoc_simple(RLPri_Int); -+ break; -+ case Ity_V128: -+ *retloc = mk_RetLoc_spRel(RLPri_V128SpRel, 0); -+ *stackAdjustAfterCall = 16; -+ break; -+ case Ity_V256: -+ vassert(0); // ATC -+ *retloc = mk_RetLoc_spRel(RLPri_V256SpRel, 0); -+ *stackAdjustAfterCall = 32; -+ break; -+ default: -+ /* IR can denote other possible return types, but we don't -+ handle those here. */ -+ vassert(0); -+ } -+ -+ /* Finally, generate the call itself. This needs the *retloc value -+ set in the switch above, which is why it's at the end. */ -+ -+ /* nextArgReg doles out argument registers. Since these are -+ assigned in the order x0 .. x7, its numeric value at this point, -+ which must be between 0 and 8 inclusive, is going to be equal to -+ the number of arg regs in use for the call. Hence bake that -+ number into the call (we'll need to know it when doing register -+ allocation, to know what regs the call reads.) */ -+ -+ target = (HWord)Ptr_to_ULong(cee->addr); -+ addInstr(env, ARM64Instr_Call( cc, target, nextArgReg, *retloc )); -+ -+ return True; /* success */ -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Integer expressions (64/32 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Select insns for an integer-typed expression, and add them to the -+ code list. Return a reg holding the result. This reg will be a -+ virtual register. THE RETURNED REG MUST NOT BE MODIFIED. If you -+ want to modify it, ask for a new vreg, copy it in there, and modify -+ the copy. The register allocator will do its best to map both -+ vregs to the same real register, so the copies will often disappear -+ later in the game. -+ -+ This should handle expressions of 64- and 32-bit type. All results -+ are returned in a 64-bit register. For 32-bit expressions, the -+ upper 32 bits are arbitrary, so you should mask or sign extend -+ partial values if necessary. -+*/ -+ -+/* --------------------- AMode --------------------- */ -+ -+/* Return an AMode which computes the value of the specified -+ expression, possibly also adding insns to the code list as a -+ result. The expression may only be a 64-bit one. -+*/ -+ -+static Bool isValidScale ( UChar scale ) -+{ -+ switch (scale) { -+ case 1: case 2: case 4: case 8: /* case 16: ??*/ return True; -+ default: return False; -+ } -+} -+ -+static Bool sane_AMode ( ARM64AMode* am ) -+{ -+ switch (am->tag) { -+ case ARM64am_RI9: -+ return -+ toBool( hregClass(am->ARM64am.RI9.reg) == HRcInt64 -+ && (hregIsVirtual(am->ARM64am.RI9.reg) -+ /* || sameHReg(am->ARM64am.RI9.reg, -+ hregARM64_X21()) */ ) -+ && am->ARM64am.RI9.simm9 >= -256 -+ && am->ARM64am.RI9.simm9 <= 255 ); -+ case ARM64am_RI12: -+ return -+ toBool( hregClass(am->ARM64am.RI12.reg) == HRcInt64 -+ && (hregIsVirtual(am->ARM64am.RI12.reg) -+ /* || sameHReg(am->ARM64am.RI12.reg, -+ hregARM64_X21()) */ ) -+ && am->ARM64am.RI12.uimm12 < 4096 -+ && isValidScale(am->ARM64am.RI12.szB) ); -+ case ARM64am_RR: -+ return -+ toBool( hregClass(am->ARM64am.RR.base) == HRcInt64 -+ && hregIsVirtual(am->ARM64am.RR.base) -+ && hregClass(am->ARM64am.RR.index) == HRcInt64 -+ && hregIsVirtual(am->ARM64am.RR.index) ); -+ default: -+ vpanic("sane_AMode: unknown ARM64 AMode1 tag"); -+ } -+} -+ -+static -+ARM64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e, IRType dty ) -+{ -+ ARM64AMode* am = iselIntExpr_AMode_wrk(env, e, dty); -+ vassert(sane_AMode(am)); -+ return am; -+} -+ -+static -+ARM64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType dty ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64); -+ -+ ULong szBbits = 0; -+ switch (dty) { -+ case Ity_I64: szBbits = 3; break; -+ case Ity_I32: szBbits = 2; break; -+ case Ity_I16: szBbits = 1; break; -+ case Ity_I8: szBbits = 0; break; -+ default: vassert(0); -+ } -+ -+ /* {Add64,Sub64}(expr,simm9). We don't care about |dty| here since -+ we're going to create an amode suitable for LDU* or STU* -+ instructions, which use unscaled immediate offsets. */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_Add64 || e->Iex.Binop.op == Iop_Sub64) -+ && e->Iex.Binop.arg2->tag == Iex_Const -+ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64) { -+ Long simm = (Long)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; -+ if (simm >= -256 && simm <= 255) { -+ HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ return ARM64AMode_RI9(reg, (Int)simm); -+ } -+ } -+ -+ /* Add64(expr, uimm12 * transfer-size) */ -+ if (e->tag == Iex_Binop -+ && e->Iex.Binop.op == Iop_Add64 -+ && e->Iex.Binop.arg2->tag == Iex_Const -+ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64) { -+ ULong uimm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; -+ ULong szB = 1 << szBbits; -+ if (0 == (uimm & (szB-1)) /* "uimm is szB-aligned" */ -+ && (uimm >> szBbits) < 4096) { -+ HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ return ARM64AMode_RI12(reg, (UInt)(uimm >> szBbits), (UChar)szB); -+ } -+ } -+ -+ /* Add64(expr1, expr2) */ -+ if (e->tag == Iex_Binop -+ && e->Iex.Binop.op == Iop_Add64) { -+ HReg reg1 = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg reg2 = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ return ARM64AMode_RR(reg1, reg2); -+ } -+ -+ /* Doesn't match anything in particular. Generate it into -+ a register and use that. */ -+ HReg reg = iselIntExpr_R(env, e); -+ return ARM64AMode_RI9(reg, 0); -+} -+ -+//ZZ /* --------------------- AModeV --------------------- */ -+//ZZ -+//ZZ /* Return an AModeV which computes the value of the specified -+//ZZ expression, possibly also adding insns to the code list as a -+//ZZ result. The expression may only be a 32-bit one. -+//ZZ */ -+//ZZ -+//ZZ static Bool sane_AModeV ( ARMAModeV* am ) -+//ZZ { -+//ZZ return toBool( hregClass(am->reg) == HRcInt32 -+//ZZ && hregIsVirtual(am->reg) -+//ZZ && am->simm11 >= -1020 && am->simm11 <= 1020 -+//ZZ && 0 == (am->simm11 & 3) ); -+//ZZ } -+//ZZ -+//ZZ static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ ARMAModeV* am = iselIntExpr_AModeV_wrk(env, e); -+//ZZ vassert(sane_AModeV(am)); -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ IRType ty = typeOfIRExpr(env->type_env,e); -+//ZZ vassert(ty == Ity_I32); -+//ZZ -+//ZZ /* {Add32,Sub32}(expr, simm8 << 2) */ -+//ZZ if (e->tag == Iex_Binop -+//ZZ && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32) -+//ZZ && e->Iex.Binop.arg2->tag == Iex_Const -+//ZZ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32) { -+//ZZ Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; -+//ZZ if (simm >= -1020 && simm <= 1020 && 0 == (simm & 3)) { -+//ZZ HReg reg; -+//ZZ if (e->Iex.Binop.op == Iop_Sub32) -+//ZZ simm = -simm; -+//ZZ reg = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ return mkARMAModeV(reg, simm); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* Doesn't match anything in particular. Generate it into -+//ZZ a register and use that. */ -+//ZZ { -+//ZZ HReg reg = iselIntExpr_R(env, e); -+//ZZ return mkARMAModeV(reg, 0); -+//ZZ } -+//ZZ -+//ZZ } -+//ZZ -+//ZZ /* -------------------- AModeN -------------------- */ -+//ZZ -+//ZZ static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ return iselIntExpr_AModeN_wrk(env, e); -+//ZZ } -+//ZZ -+//ZZ static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ HReg reg = iselIntExpr_R(env, e); -+//ZZ return mkARMAModeN_R(reg); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* --------------------- RI84 --------------------- */ -+//ZZ -+//ZZ /* Select instructions to generate 'e' into a RI84. If mayInv is -+//ZZ true, then the caller will also accept an I84 form that denotes -+//ZZ 'not e'. In this case didInv may not be NULL, and *didInv is set -+//ZZ to True. This complication is so as to allow generation of an RI84 -+//ZZ which is suitable for use in either an AND or BIC instruction, -+//ZZ without knowing (before this call) which one. -+//ZZ */ -+//ZZ static ARMRI84* iselIntExpr_RI84 ( /*OUT*/Bool* didInv, Bool mayInv, -+//ZZ ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ ARMRI84* ri; -+//ZZ if (mayInv) -+//ZZ vassert(didInv != NULL); -+//ZZ ri = iselIntExpr_RI84_wrk(didInv, mayInv, env, e); -+//ZZ /* sanity checks ... */ -+//ZZ switch (ri->tag) { -+//ZZ case ARMri84_I84: -+//ZZ return ri; -+//ZZ case ARMri84_R: -+//ZZ vassert(hregClass(ri->ARMri84.R.reg) == HRcInt32); -+//ZZ vassert(hregIsVirtual(ri->ARMri84.R.reg)); -+//ZZ return ri; -+//ZZ default: -+//ZZ vpanic("iselIntExpr_RI84: unknown arm RI84 tag"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* DO NOT CALL THIS DIRECTLY ! */ -+//ZZ static ARMRI84* iselIntExpr_RI84_wrk ( /*OUT*/Bool* didInv, Bool mayInv, -+//ZZ ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ IRType ty = typeOfIRExpr(env->type_env,e); -+//ZZ vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8); -+//ZZ -+//ZZ if (didInv) *didInv = False; -+//ZZ -+//ZZ /* special case: immediate */ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ UInt u, u8 = 0x100, u4 = 0x10; /* both invalid */ -+//ZZ switch (e->Iex.Const.con->tag) { -+//ZZ case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; -+//ZZ case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break; -+//ZZ case Ico_U8: u = 0xFF & (e->Iex.Const.con->Ico.U8); break; -+//ZZ default: vpanic("iselIntExpr_RI84.Iex_Const(armh)"); -+//ZZ } -+//ZZ if (fitsIn8x4(&u8, &u4, u)) { -+//ZZ return ARMRI84_I84( (UShort)u8, (UShort)u4 ); -+//ZZ } -+//ZZ if (mayInv && fitsIn8x4(&u8, &u4, ~u)) { -+//ZZ vassert(didInv); -+//ZZ *didInv = True; -+//ZZ return ARMRI84_I84( (UShort)u8, (UShort)u4 ); -+//ZZ } -+//ZZ /* else fail, fall through to default case */ -+//ZZ } -+//ZZ -+//ZZ /* default case: calculate into a register and return that */ -+//ZZ { -+//ZZ HReg r = iselIntExpr_R ( env, e ); -+//ZZ return ARMRI84_R(r); -+//ZZ } -+//ZZ } -+ -+ -+/* --------------------- RIA --------------------- */ -+ -+/* Select instructions to generate 'e' into a RIA. */ -+ -+static ARM64RIA* iselIntExpr_RIA ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64RIA* ri = iselIntExpr_RIA_wrk(env, e); -+ /* sanity checks ... */ -+ switch (ri->tag) { -+ case ARM64riA_I12: -+ vassert(ri->ARM64riA.I12.imm12 < 4096); -+ vassert(ri->ARM64riA.I12.shift == 0 || ri->ARM64riA.I12.shift == 12); -+ return ri; -+ case ARM64riA_R: -+ vassert(hregClass(ri->ARM64riA.R.reg) == HRcInt64); -+ vassert(hregIsVirtual(ri->ARM64riA.R.reg)); -+ return ri; -+ default: -+ vpanic("iselIntExpr_RIA: unknown arm RIA tag"); -+ } -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static ARM64RIA* iselIntExpr_RIA_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I32); -+ -+ /* special case: immediate */ -+ if (e->tag == Iex_Const) { -+ ULong u = 0xF000000ULL; /* invalid */ -+ switch (e->Iex.Const.con->tag) { -+ case Ico_U64: u = e->Iex.Const.con->Ico.U64; break; -+ case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; -+ default: vpanic("iselIntExpr_RIA.Iex_Const(arm64)"); -+ } -+ if (0 == (u & ~(0xFFFULL << 0))) -+ return ARM64RIA_I12((UShort)((u >> 0) & 0xFFFULL), 0); -+ if (0 == (u & ~(0xFFFULL << 12))) -+ return ARM64RIA_I12((UShort)((u >> 12) & 0xFFFULL), 12); -+ /* else fail, fall through to default case */ -+ } -+ -+ /* default case: calculate into a register and return that */ -+ { -+ HReg r = iselIntExpr_R ( env, e ); -+ return ARM64RIA_R(r); -+ } -+} -+ -+ -+/* --------------------- RIL --------------------- */ -+ -+/* Select instructions to generate 'e' into a RIL. At this point we -+ have to deal with the strange bitfield-immediate encoding for logic -+ instructions. */ -+ -+ -+// The following four functions -+// CountLeadingZeros CountTrailingZeros CountSetBits isImmLogical -+// are copied, with modifications, from -+// https://github.com/armvixl/vixl/blob/master/src/a64/assembler-a64.cc -+// which has the following copyright notice: -+/* -+ Copyright 2013, ARM Limited -+ All rights reserved. -+ -+ Redistribution and use in source and binary forms, with or without -+ modification, are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright notice, -+ this list of conditions and the following disclaimer in the documentation -+ and/or other materials provided with the distribution. -+ * Neither the name of ARM Limited nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND -+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+static Int CountLeadingZeros(ULong value, Int width) -+{ -+ vassert(width == 32 || width == 64); -+ Int count = 0; -+ ULong bit_test = 1ULL << (width - 1); -+ while ((count < width) && ((bit_test & value) == 0)) { -+ count++; -+ bit_test >>= 1; -+ } -+ return count; -+} -+ -+static Int CountTrailingZeros(ULong value, Int width) -+{ -+ vassert(width == 32 || width == 64); -+ Int count = 0; -+ while ((count < width) && (((value >> count) & 1) == 0)) { -+ count++; -+ } -+ return count; -+} -+ -+static Int CountSetBits(ULong value, Int width) -+{ -+ // TODO: Other widths could be added here, as the implementation already -+ // supports them. -+ vassert(width == 32 || width == 64); -+ -+ // Mask out unused bits to ensure that they are not counted. -+ value &= (0xffffffffffffffffULL >> (64-width)); -+ -+ // Add up the set bits. -+ // The algorithm works by adding pairs of bit fields together iteratively, -+ // where the size of each bit field doubles each time. -+ // An example for an 8-bit value: -+ // Bits: h g f e d c b a -+ // \ | \ | \ | \ | -+ // value = h+g f+e d+c b+a -+ // \ | \ | -+ // value = h+g+f+e d+c+b+a -+ // \ | -+ // value = h+g+f+e+d+c+b+a -+ value = ((value >> 1) & 0x5555555555555555) + (value & 0x5555555555555555); -+ value = ((value >> 2) & 0x3333333333333333) + (value & 0x3333333333333333); -+ value = ((value >> 4) & 0x0f0f0f0f0f0f0f0f) + (value & 0x0f0f0f0f0f0f0f0f); -+ value = ((value >> 8) & 0x00ff00ff00ff00ff) + (value & 0x00ff00ff00ff00ff); -+ value = ((value >> 16) & 0x0000ffff0000ffff) + (value & 0x0000ffff0000ffff); -+ value = ((value >> 32) & 0x00000000ffffffff) + (value & 0x00000000ffffffff); -+ -+ return value; -+} -+ -+static Bool isImmLogical ( /*OUT*/UInt* n, -+ /*OUT*/UInt* imm_s, /*OUT*/UInt* imm_r, -+ ULong value, UInt width ) -+{ -+ // Test if a given value can be encoded in the immediate field of a -+ // logical instruction. -+ -+ // If it can be encoded, the function returns true, and values -+ // pointed to by n, imm_s and imm_r are updated with immediates -+ // encoded in the format required by the corresponding fields in the -+ // logical instruction. If it can not be encoded, the function -+ // returns false, and the values pointed to by n, imm_s and imm_r -+ // are undefined. -+ vassert(n != NULL && imm_s != NULL && imm_r != NULL); -+ vassert(width == 32 || width == 64); -+ -+ // Logical immediates are encoded using parameters n, imm_s and imm_r using -+ // the following table: -+ // -+ // N imms immr size S R -+ // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) -+ // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) -+ // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) -+ // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) -+ // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) -+ // 0 11110s xxxxxr 2 UInt(s) UInt(r) -+ // (s bits must not be all set) -+ // -+ // A pattern is constructed of size bits, where the least significant S+1 -+ // bits are set. The pattern is rotated right by R, and repeated across a -+ // 32 or 64-bit value, depending on destination register width. -+ // -+ // To test if an arbitrary immediate can be encoded using this scheme, an -+ // iterative algorithm is used. -+ // -+ // TODO: This code does not consider using X/W register overlap to support -+ // 64-bit immediates where the top 32-bits are zero, and the bottom 32-bits -+ // are an encodable logical immediate. -+ -+ // 1. If the value has all set or all clear bits, it can't be encoded. -+ if ((value == 0) || (value == 0xffffffffffffffffULL) || -+ ((width == 32) && (value == 0xffffffff))) { -+ return False; -+ } -+ -+ UInt lead_zero = CountLeadingZeros(value, width); -+ UInt lead_one = CountLeadingZeros(~value, width); -+ UInt trail_zero = CountTrailingZeros(value, width); -+ UInt trail_one = CountTrailingZeros(~value, width); -+ UInt set_bits = CountSetBits(value, width); -+ -+ // The fixed bits in the immediate s field. -+ // If width == 64 (X reg), start at 0xFFFFFF80. -+ // If width == 32 (W reg), start at 0xFFFFFFC0, as the iteration for 64-bit -+ // widths won't be executed. -+ Int imm_s_fixed = (width == 64) ? -128 : -64; -+ Int imm_s_mask = 0x3F; -+ -+ for (;;) { -+ // 2. If the value is two bits wide, it can be encoded. -+ if (width == 2) { -+ *n = 0; -+ *imm_s = 0x3C; -+ *imm_r = (value & 3) - 1; -+ return True; -+ } -+ -+ *n = (width == 64) ? 1 : 0; -+ *imm_s = ((imm_s_fixed | (set_bits - 1)) & imm_s_mask); -+ if ((lead_zero + set_bits) == width) { -+ *imm_r = 0; -+ } else { -+ *imm_r = (lead_zero > 0) ? (width - trail_zero) : lead_one; -+ } -+ -+ // 3. If the sum of leading zeros, trailing zeros and set bits is equal to -+ // the bit width of the value, it can be encoded. -+ if (lead_zero + trail_zero + set_bits == width) { -+ return True; -+ } -+ -+ // 4. If the sum of leading ones, trailing ones and unset bits in the -+ // value is equal to the bit width of the value, it can be encoded. -+ if (lead_one + trail_one + (width - set_bits) == width) { -+ return True; -+ } -+ -+ // 5. If the most-significant half of the bitwise value is equal to the -+ // least-significant half, return to step 2 using the least-significant -+ // half of the value. -+ ULong mask = (1ULL << (width >> 1)) - 1; -+ if ((value & mask) == ((value >> (width >> 1)) & mask)) { -+ width >>= 1; -+ set_bits >>= 1; -+ imm_s_fixed >>= 1; -+ continue; -+ } -+ -+ // 6. Otherwise, the value can't be encoded. -+ return False; -+ } -+} -+ -+ -+/* Create a RIL for the given immediate, if it is representable, or -+ return NULL if not. */ -+ -+static ARM64RIL* mb_mkARM64RIL_I ( ULong imm64 ) -+{ -+ UInt n = 0, imm_s = 0, imm_r = 0; -+ Bool ok = isImmLogical(&n, &imm_s, &imm_r, imm64, 64); -+ if (!ok) return NULL; -+ vassert(n < 2 && imm_s < 64 && imm_r < 64); -+ return ARM64RIL_I13(n, imm_r, imm_s); -+} -+ -+/* So, finally .. */ -+ -+static ARM64RIL* iselIntExpr_RIL ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64RIL* ri = iselIntExpr_RIL_wrk(env, e); -+ /* sanity checks ... */ -+ switch (ri->tag) { -+ case ARM64riL_I13: -+ vassert(ri->ARM64riL.I13.bitN < 2); -+ vassert(ri->ARM64riL.I13.immR < 64); -+ vassert(ri->ARM64riL.I13.immS < 64); -+ return ri; -+ case ARM64riL_R: -+ vassert(hregClass(ri->ARM64riL.R.reg) == HRcInt64); -+ vassert(hregIsVirtual(ri->ARM64riL.R.reg)); -+ return ri; -+ default: -+ vpanic("iselIntExpr_RIL: unknown arm RIL tag"); -+ } -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static ARM64RIL* iselIntExpr_RIL_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I32); -+ -+ /* special case: immediate */ -+ if (e->tag == Iex_Const) { -+ ARM64RIL* maybe = NULL; -+ if (ty == Ity_I64) { -+ vassert(e->Iex.Const.con->tag == Ico_U64); -+ maybe = mb_mkARM64RIL_I(e->Iex.Const.con->Ico.U64); -+ } else { -+ vassert(ty == Ity_I32); -+ vassert(e->Iex.Const.con->tag == Ico_U32); -+ UInt u32 = e->Iex.Const.con->Ico.U32; -+ ULong u64 = (ULong)u32; -+ /* First try with 32 leading zeroes. */ -+ maybe = mb_mkARM64RIL_I(u64); -+ /* If that doesn't work, try with 2 copies, since it doesn't -+ matter what winds up in the upper 32 bits. */ -+ if (!maybe) { -+ maybe = mb_mkARM64RIL_I((u64 << 32) | u64); -+ } -+ } -+ if (maybe) return maybe; -+ /* else fail, fall through to default case */ -+ } -+ -+ /* default case: calculate into a register and return that */ -+ { -+ HReg r = iselIntExpr_R ( env, e ); -+ return ARM64RIL_R(r); -+ } -+} -+ -+ -+/* --------------------- RI6 --------------------- */ -+ -+/* Select instructions to generate 'e' into a RI6. */ -+ -+static ARM64RI6* iselIntExpr_RI6 ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64RI6* ri = iselIntExpr_RI6_wrk(env, e); -+ /* sanity checks ... */ -+ switch (ri->tag) { -+ case ARM64ri6_I6: -+ vassert(ri->ARM64ri6.I6.imm6 < 64); -+ vassert(ri->ARM64ri6.I6.imm6 > 0); -+ return ri; -+ case ARM64ri6_R: -+ vassert(hregClass(ri->ARM64ri6.R.reg) == HRcInt64); -+ vassert(hregIsVirtual(ri->ARM64ri6.R.reg)); -+ return ri; -+ default: -+ vpanic("iselIntExpr_RI6: unknown arm RI6 tag"); -+ } -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static ARM64RI6* iselIntExpr_RI6_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I8); -+ -+ /* special case: immediate */ -+ if (e->tag == Iex_Const) { -+ switch (e->Iex.Const.con->tag) { -+ case Ico_U8: { -+ UInt u = e->Iex.Const.con->Ico.U8; -+ if (u > 0 && u < 64) -+ return ARM64RI6_I6(u); -+ break; -+ default: -+ break; -+ } -+ } -+ /* else fail, fall through to default case */ -+ } -+ -+ /* default case: calculate into a register and return that */ -+ { -+ HReg r = iselIntExpr_R ( env, e ); -+ return ARM64RI6_R(r); -+ } -+} -+ -+ -+/* ------------------- CondCode ------------------- */ -+ -+/* Generate code to evaluated a bit-typed expression, returning the -+ condition code which would correspond when the expression would -+ notionally have returned 1. */ -+ -+static ARM64CondCode iselCondCode ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64CondCode cc = iselCondCode_wrk(env,e); -+ vassert(cc != ARM64cc_NV); -+ return cc; -+} -+ -+static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ vassert(e); -+ vassert(typeOfIRExpr(env->type_env,e) == Ity_I1); -+ -+ /* var */ -+ if (e->tag == Iex_RdTmp) { -+ HReg rTmp = lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ /* Cmp doesn't modify rTmp; so this is OK. */ -+ ARM64RIL* one = mb_mkARM64RIL_I(1); -+ vassert(one); -+ addInstr(env, ARM64Instr_Test(rTmp, one)); -+ return ARM64cc_NE; -+ } -+ -+ /* Not1(e) */ -+ if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) { -+ /* Generate code for the arg, and negate the test condition */ -+ ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg); -+ if (cc == ARM64cc_AL || cc == ARM64cc_NV) { -+ return ARM64cc_AL; -+ } else { -+ return 1 ^ cc; -+ } -+ } -+ -+ /* --- patterns rooted at: 64to1 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_64to1) { -+ HReg rTmp = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIL* one = mb_mkARM64RIL_I(1); -+ vassert(one); /* '1' must be representable */ -+ addInstr(env, ARM64Instr_Test(rTmp, one)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- patterns rooted at: CmpNEZ8 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_CmpNEZ8) { -+ HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIL* xFF = mb_mkARM64RIL_I(0xFF); -+ addInstr(env, ARM64Instr_Test(r1, xFF)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- patterns rooted at: CmpNEZ64 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_CmpNEZ64) { -+ HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIA* zero = ARM64RIA_I12(0,0); -+ addInstr(env, ARM64Instr_Cmp(r1, zero, True/*is64*/)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- patterns rooted at: CmpNEZ32 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_CmpNEZ32) { -+ HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIA* zero = ARM64RIA_I12(0,0); -+ addInstr(env, ARM64Instr_Cmp(r1, zero, False/*!is64*/)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- Cmp*64*(x,y) --- */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_CmpEQ64 -+ || e->Iex.Binop.op == Iop_CmpNE64 -+ || e->Iex.Binop.op == Iop_CmpLT64S -+ || e->Iex.Binop.op == Iop_CmpLT64U -+ || e->Iex.Binop.op == Iop_CmpLE64S -+ || e->Iex.Binop.op == Iop_CmpLE64U)) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Cmp(argL, argR, True/*is64*/)); -+ switch (e->Iex.Binop.op) { -+ case Iop_CmpEQ64: return ARM64cc_EQ; -+ case Iop_CmpNE64: return ARM64cc_NE; -+ case Iop_CmpLT64S: return ARM64cc_LT; -+ case Iop_CmpLT64U: return ARM64cc_CC; -+ case Iop_CmpLE64S: return ARM64cc_LE; -+ case Iop_CmpLE64U: return ARM64cc_LS; -+ default: vpanic("iselCondCode(arm64): CmpXX64"); -+ } -+ } -+ -+ /* --- Cmp*32*(x,y) --- */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_CmpEQ32 -+ || e->Iex.Binop.op == Iop_CmpNE32 -+ || e->Iex.Binop.op == Iop_CmpLT32S -+ || e->Iex.Binop.op == Iop_CmpLT32U -+ || e->Iex.Binop.op == Iop_CmpLE32S -+ || e->Iex.Binop.op == Iop_CmpLE32U)) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Cmp(argL, argR, False/*!is64*/)); -+ switch (e->Iex.Binop.op) { -+ case Iop_CmpEQ32: return ARM64cc_EQ; -+ case Iop_CmpNE32: return ARM64cc_NE; -+ case Iop_CmpLT32S: return ARM64cc_LT; -+ case Iop_CmpLT32U: return ARM64cc_CC; -+ case Iop_CmpLE32S: return ARM64cc_LE; -+ case Iop_CmpLE32U: return ARM64cc_LS; -+ default: vpanic("iselCondCode(arm64): CmpXX32"); -+ } -+ } -+ -+//ZZ /* const */ -+//ZZ /* Constant 1:Bit */ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ HReg r; -+//ZZ vassert(e->Iex.Const.con->tag == Ico_U1); -+//ZZ vassert(e->Iex.Const.con->Ico.U1 == True -+//ZZ || e->Iex.Const.con->Ico.U1 == False); -+//ZZ r = newVRegI(env); -+//ZZ addInstr(env, ARMInstr_Imm32(r, 0)); -+//ZZ addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, r, ARMRI84_R(r))); -+//ZZ return e->Iex.Const.con->Ico.U1 ? ARMcc_EQ : ARMcc_NE; -+//ZZ } -+//ZZ -+//ZZ // JRS 2013-Jan-03: this seems completely nonsensical -+//ZZ /* --- CasCmpEQ* --- */ -+//ZZ /* Ist_Cas has a dummy argument to compare with, so comparison is -+//ZZ always true. */ -+//ZZ //if (e->tag == Iex_Binop -+//ZZ // && (e->Iex.Binop.op == Iop_CasCmpEQ32 -+//ZZ // || e->Iex.Binop.op == Iop_CasCmpEQ16 -+//ZZ // || e->Iex.Binop.op == Iop_CasCmpEQ8)) { -+//ZZ // return ARMcc_AL; -+//ZZ //} -+ -+ ppIRExpr(e); -+ vpanic("iselCondCode"); -+} -+ -+ -+/* --------------------- Reg --------------------- */ -+ -+static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselIntExpr_R_wrk(env, e); -+ /* sanity checks ... */ -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(r) == HRcInt64); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8); -+ -+ switch (e->tag) { -+ -+ /* --------- TEMP --------- */ -+ case Iex_RdTmp: { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ /* --------- LOAD --------- */ -+ case Iex_Load: { -+ HReg dst = newVRegI(env); -+ -+ if (e->Iex.Load.end != Iend_LE) -+ goto irreducible; -+ -+ if (ty == Ity_I64) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt64(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ if (ty == Ity_I32) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ if (ty == Ity_I16) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt16(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ if (ty == Ity_I8) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ break; -+ } -+ -+ /* --------- BINARY OP --------- */ -+ case Iex_Binop: { -+ -+ ARM64LogicOp lop = 0; /* invalid */ -+ ARM64ShiftOp sop = 0; /* invalid */ -+ -+ /* Special-case 0-x into a Neg instruction. Not because it's -+ particularly useful but more so as to give value flow using -+ this instruction, so as to check its assembly correctness for -+ implementation of Left32/Left64. */ -+ switch (e->Iex.Binop.op) { -+ case Iop_Sub64: -+ if (isZeroU64(e->Iex.Binop.arg1)) { -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Unary(dst, argR, ARM64un_NEG)); -+ return dst; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ /* ADD/SUB */ -+ switch (e->Iex.Binop.op) { -+ case Iop_Add64: case Iop_Add32: -+ case Iop_Sub64: case Iop_Sub32: { -+ Bool isAdd = e->Iex.Binop.op == Iop_Add64 -+ || e->Iex.Binop.op == Iop_Add32; -+ HReg dst = newVRegI(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Arith(dst, argL, argR, isAdd)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ -+ /* AND/OR/XOR */ -+ switch (e->Iex.Binop.op) { -+ case Iop_And64: case Iop_And32: lop = ARM64lo_AND; goto log_binop; -+ case Iop_Or64: case Iop_Or32: lop = ARM64lo_OR; goto log_binop; -+ case Iop_Xor64: case Iop_Xor32: lop = ARM64lo_XOR; goto log_binop; -+ log_binop: { -+ HReg dst = newVRegI(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIL* argR = iselIntExpr_RIL(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Logic(dst, argL, argR, lop)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ -+ /* SHL/SHR/SAR */ -+ switch (e->Iex.Binop.op) { -+ case Iop_Shr64: sop = ARM64sh_SHR; goto sh_binop; -+ case Iop_Sar64: sop = ARM64sh_SAR; goto sh_binop; -+ case Iop_Shl64: case Iop_Shl32: sop = ARM64sh_SHL; goto sh_binop; -+ sh_binop: { -+ HReg dst = newVRegI(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RI6* argR = iselIntExpr_RI6(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Shift(dst, argL, argR, sop)); -+ return dst; -+ } -+ case Iop_Shr32: -+ case Iop_Sar32: { -+ Bool zx = e->Iex.Binop.op == Iop_Shr32; -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RI6* argR = iselIntExpr_RI6(env, e->Iex.Binop.arg2); -+ HReg dst = zx ? widen_z_32_to_64(env, argL) -+ : widen_s_32_to_64(env, argL); -+ addInstr(env, ARM64Instr_Shift(dst, dst, argR, ARM64sh_SHR)); -+ return dst; -+ } -+ default: break; -+ } -+ -+ /* MUL */ -+ if (e->Iex.Binop.op == Iop_Mul64 || e->Iex.Binop.op == Iop_Mul32) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Mul(dst, argL, argR, ARM64mul_PLAIN)); -+ return dst; -+ } -+ -+ /* MULL */ -+ if (e->Iex.Binop.op == Iop_MullU32 || e->Iex.Binop.op == Iop_MullS32) { -+ Bool isS = e->Iex.Binop.op == Iop_MullS32; -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg extL = (isS ? widen_s_32_to_64 : widen_z_32_to_64)(env, argL); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg extR = (isS ? widen_s_32_to_64 : widen_z_32_to_64)(env, argR); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Mul(dst, extL, extR, ARM64mul_PLAIN)); -+ return dst; -+ } -+ -+ /* Handle misc other ops. */ -+ -+//ZZ if (e->Iex.Binop.op == Iop_Max32U) { -+//ZZ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg dst = newVRegI(env); -+//ZZ addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL, -+//ZZ ARMRI84_R(argR))); -+//ZZ addInstr(env, mk_iMOVds_RR(dst, argL)); -+//ZZ addInstr(env, ARMInstr_CMov(ARMcc_LO, dst, ARMRI84_R(argR))); -+//ZZ return dst; -+//ZZ } -+ -+ if (e->Iex.Binop.op == Iop_32HLto64) { -+ HReg hi32s = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg lo32s = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg lo32 = widen_z_32_to_64(env, lo32s); -+ HReg hi32 = newVRegI(env); -+ addInstr(env, ARM64Instr_Shift(hi32, hi32s, ARM64RI6_I6(32), -+ ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Logic(hi32, hi32, ARM64RIL_R(lo32), -+ ARM64lo_OR)); -+ return hi32; -+ } -+ -+ if (e->Iex.Binop.op == Iop_CmpF64 || e->Iex.Binop.op == Iop_CmpF32) { -+ Bool isD = e->Iex.Binop.op == Iop_CmpF64; -+ HReg dL = (isD ? iselDblExpr : iselFltExpr)(env, e->Iex.Binop.arg1); -+ HReg dR = (isD ? iselDblExpr : iselFltExpr)(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ HReg imm = newVRegI(env); -+ /* Do the compare (FCMP), which sets NZCV in PSTATE. Then -+ create in dst, the IRCmpF64Result encoded result. */ -+ addInstr(env, (isD ? ARM64Instr_VCmpD : ARM64Instr_VCmpS)(dL, dR)); -+ addInstr(env, ARM64Instr_Imm64(dst, 0)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x40)); // 0x40 = Ircr_EQ -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_EQ)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x01)); // 0x01 = Ircr_LT -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_MI)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x00)); // 0x00 = Ircr_GT -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_GT)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x45)); // 0x45 = Ircr_UN -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_VS)); -+ return dst; -+ } -+ -+ { /* local scope */ -+ ARM64CvtOp cvt_op = ARM64cvt_INVALID; -+ Bool srcIsD = False; -+ switch (e->Iex.Binop.op) { -+ case Iop_F64toI64S: -+ cvt_op = ARM64cvt_F64_I64S; srcIsD = True; break; -+ case Iop_F64toI64U: -+ cvt_op = ARM64cvt_F64_I64U; srcIsD = True; break; -+ case Iop_F64toI32S: -+ cvt_op = ARM64cvt_F64_I32S; srcIsD = True; break; -+ case Iop_F64toI32U: -+ cvt_op = ARM64cvt_F64_I32U; srcIsD = True; break; -+ case Iop_F32toI32S: -+ cvt_op = ARM64cvt_F32_I32S; srcIsD = False; break; -+ case Iop_F32toI64U: -+ cvt_op = ARM64cvt_F32_I64U; srcIsD = False; break; -+ default: -+ break; -+ } -+ if (cvt_op != ARM64cvt_INVALID) { -+ /* This is all a bit dodgy, because we can't handle a -+ non-constant (not-known-at-JIT-time) rounding mode -+ indication. That's because there's no instruction -+ AFAICS that does this conversion but rounds according to -+ FPCR.RM, so we have to bake the rounding mode into the -+ instruction right now. But that should be OK because -+ (1) the front end attaches a literal Irrm_ value to the -+ conversion binop, and (2) iropt will never float that -+ off via CSE, into a literal. Hence we should always -+ have an Irrm_ value as the first arg. */ -+ IRExpr* arg1 = e->Iex.Binop.arg1; -+ if (arg1->tag != Iex_Const) goto irreducible; -+ IRConst* arg1con = arg1->Iex.Const.con; -+ vassert(arg1con->tag == Ico_U32); // else ill-typed IR -+ UInt irrm = arg1con->Ico.U32; -+ /* Find the ARM-encoded equivalent for |irrm|. */ -+ UInt armrm = 4; /* impossible */ -+ switch (irrm) { -+ case Irrm_NEAREST: armrm = 0; break; -+ case Irrm_NegINF: armrm = 2; break; -+ case Irrm_PosINF: armrm = 1; break; -+ case Irrm_ZERO: armrm = 3; break; -+ default: goto irreducible; -+ } -+ HReg src = (srcIsD ? iselDblExpr : iselFltExpr) -+ (env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_VCvtF2I(cvt_op, dst, src, armrm)); -+ return dst; -+ } -+ } /* local scope */ -+ -+//ZZ if (e->Iex.Binop.op == Iop_GetElem8x8 -+//ZZ || e->Iex.Binop.op == Iop_GetElem16x4 -+//ZZ || e->Iex.Binop.op == Iop_GetElem32x2) { -+//ZZ HReg res = newVRegI(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt index, size; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM target supports GetElem with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_GetElem8x8: vassert(index < 8); size = 0; break; -+//ZZ case Iop_GetElem16x4: vassert(index < 4); size = 1; break; -+//ZZ case Iop_GetElem32x2: vassert(index < 2); size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ if (e->Iex.Binop.op == Iop_GetElem8x16 -+//ZZ || e->Iex.Binop.op == Iop_GetElem16x8 -+//ZZ || e->Iex.Binop.op == Iop_GetElem32x4) { -+//ZZ HReg res = newVRegI(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt index, size; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM target supports GetElem with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_GetElem8x16: vassert(index < 16); size = 0; break; -+//ZZ case Iop_GetElem16x8: vassert(index < 8); size = 1; break; -+//ZZ case Iop_GetElem32x4: vassert(index < 4); size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ size, True)); -+//ZZ return res; -+//ZZ } -+ -+ /* All cases involving host-side helper calls. */ -+ void* fn = NULL; -+ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Add16x2: -+//ZZ fn = &h_generic_calc_Add16x2; break; -+//ZZ case Iop_Sub16x2: -+//ZZ fn = &h_generic_calc_Sub16x2; break; -+//ZZ case Iop_HAdd16Ux2: -+//ZZ fn = &h_generic_calc_HAdd16Ux2; break; -+//ZZ case Iop_HAdd16Sx2: -+//ZZ fn = &h_generic_calc_HAdd16Sx2; break; -+//ZZ case Iop_HSub16Ux2: -+//ZZ fn = &h_generic_calc_HSub16Ux2; break; -+//ZZ case Iop_HSub16Sx2: -+//ZZ fn = &h_generic_calc_HSub16Sx2; break; -+//ZZ case Iop_QAdd16Sx2: -+//ZZ fn = &h_generic_calc_QAdd16Sx2; break; -+//ZZ case Iop_QAdd16Ux2: -+//ZZ fn = &h_generic_calc_QAdd16Ux2; break; -+//ZZ case Iop_QSub16Sx2: -+//ZZ fn = &h_generic_calc_QSub16Sx2; break; -+//ZZ case Iop_Add8x4: -+//ZZ fn = &h_generic_calc_Add8x4; break; -+//ZZ case Iop_Sub8x4: -+//ZZ fn = &h_generic_calc_Sub8x4; break; -+//ZZ case Iop_HAdd8Ux4: -+//ZZ fn = &h_generic_calc_HAdd8Ux4; break; -+//ZZ case Iop_HAdd8Sx4: -+//ZZ fn = &h_generic_calc_HAdd8Sx4; break; -+//ZZ case Iop_HSub8Ux4: -+//ZZ fn = &h_generic_calc_HSub8Ux4; break; -+//ZZ case Iop_HSub8Sx4: -+//ZZ fn = &h_generic_calc_HSub8Sx4; break; -+//ZZ case Iop_QAdd8Sx4: -+//ZZ fn = &h_generic_calc_QAdd8Sx4; break; -+//ZZ case Iop_QAdd8Ux4: -+//ZZ fn = &h_generic_calc_QAdd8Ux4; break; -+//ZZ case Iop_QSub8Sx4: -+//ZZ fn = &h_generic_calc_QSub8Sx4; break; -+//ZZ case Iop_QSub8Ux4: -+//ZZ fn = &h_generic_calc_QSub8Ux4; break; -+//ZZ case Iop_Sad8Ux4: -+//ZZ fn = &h_generic_calc_Sad8Ux4; break; -+//ZZ case Iop_QAdd32S: -+//ZZ fn = &h_generic_calc_QAdd32S; break; -+//ZZ case Iop_QSub32S: -+//ZZ fn = &h_generic_calc_QSub32S; break; -+//ZZ case Iop_QSub16Ux2: -+//ZZ fn = &h_generic_calc_QSub16Ux2; break; -+ case Iop_DivU32: -+ fn = &h_calc_udiv32_w_arm_semantics; break; -+ case Iop_DivS32: -+ fn = &h_calc_sdiv32_w_arm_semantics; break; -+ case Iop_DivU64: -+ fn = &h_calc_udiv64_w_arm_semantics; break; -+ case Iop_DivS64: -+ fn = &h_calc_sdiv64_w_arm_semantics; break; -+ default: -+ break; -+ } -+ -+ if (fn) { -+ HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg res = newVRegI(env); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X0(), regL)); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X1(), regR)); -+ addInstr(env, ARM64Instr_Call( ARM64cc_AL, (HWord)Ptr_to_ULong(fn), -+ 2, mk_RetLoc_simple(RLPri_Int) )); -+ addInstr(env, ARM64Instr_MovI(res, hregARM64_X0())); -+ return res; -+ } -+ -+ break; -+ } -+ -+ /* --------- UNARY OP --------- */ -+ case Iex_Unop: { -+ -+ switch (e->Iex.Unop.op) { -+ case Iop_16Uto64: { -+ /* This probably doesn't occur often enough to be worth -+ rolling the extension into the load. */ -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_z_16_to_64(env, src); -+ return dst; -+ } -+ case Iop_32Uto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ if (arg->tag == Iex_Load) { -+ /* This correctly zero extends because _LdSt32 is -+ defined to do a zero extending load. */ -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I32); -+ addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ /* else be lame and mask it */ -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_z_32_to_64(env, src); -+ return dst; -+ } -+ case Iop_8Uto32: /* Just freeload on the 8Uto64 case */ -+ case Iop_8Uto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ if (arg->tag == Iex_Load) { -+ /* This correctly zero extends because _LdSt8 is -+ defined to do a zero extending load. */ -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I8); -+ addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ /* else be lame and mask it */ -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_z_8_to_64(env, src); -+ return dst; -+ } -+ case Iop_128HIto64: { -+ HReg rHi, rLo; -+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+ return rHi; /* and abandon rLo */ -+ } -+ case Iop_8Sto32: case Iop_8Sto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_s_8_to_64(env, src); -+ return dst; -+ } -+ case Iop_16Sto32: case Iop_16Sto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_s_16_to_64(env, src); -+ return dst; -+ } -+ case Iop_32Sto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_s_32_to_64(env, src); -+ return dst; -+ } -+ case Iop_Not32: -+ case Iop_Not64: { -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NOT)); -+ return dst; -+ } -+ case Iop_Clz64: { -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_CLZ)); -+ return dst; -+ } -+ case Iop_Left32: -+ case Iop_Left64: { -+ /* Left64(src) = src | -src. Left32 can use the same -+ implementation since in that case we don't care what -+ the upper 32 bits become. */ -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG)); -+ addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src), -+ ARM64lo_OR)); -+ return dst; -+ } -+ case Iop_CmpwNEZ64: { -+ /* CmpwNEZ64(src) = (src == 0) ? 0...0 : 1...1 -+ = Left64(src) >>s 63 */ -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG)); -+ addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src), -+ ARM64lo_OR)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SAR)); -+ return dst; -+ } -+ case Iop_CmpwNEZ32: { -+ /* CmpwNEZ32(src) = CmpwNEZ64(src & 0xFFFFFFFF) -+ = Left64(src & 0xFFFFFFFF) >>s 63 */ -+ HReg dst = newVRegI(env); -+ HReg pre = iselIntExpr_R(env, e->Iex.Unop.arg); -+ HReg src = widen_z_32_to_64(env, pre); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG)); -+ addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src), -+ ARM64lo_OR)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SAR)); -+ return dst; -+ } -+ case Iop_V128to64: case Iop_V128HIto64: { -+ HReg dst = newVRegI(env); -+ HReg src = iselV128Expr(env, e->Iex.Unop.arg); -+ UInt laneNo = (e->Iex.Unop.op == Iop_V128HIto64) ? 1 : 0; -+ addInstr(env, ARM64Instr_VXfromQ(dst, src, laneNo)); -+ return dst; -+ } -+ case Iop_1Sto32: -+ case Iop_1Sto64: { -+ /* As with the iselStmt case for 'tmp:I1 = expr', we could -+ do a lot better here if it ever became necessary. */ -+ HReg zero = newVRegI(env); -+ HReg one = newVRegI(env); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Imm64(zero, 0)); -+ addInstr(env, ARM64Instr_Imm64(one, 1)); -+ ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_CSel(dst, one, zero, cc)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SAR)); -+ return dst; -+ } -+ -+//ZZ case Iop_64HIto32: { -+//ZZ HReg rHi, rLo; -+//ZZ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+//ZZ return rHi; /* and abandon rLo .. poor wee thing :-) */ -+//ZZ } -+//ZZ case Iop_64to32: { -+//ZZ HReg rHi, rLo; -+//ZZ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+//ZZ return rLo; /* similar stupid comment to the above ... */ -+//ZZ } -+//ZZ case Iop_64to8: { -+//ZZ HReg rHi, rLo; -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); -+//ZZ rHi = tHi; -+//ZZ rLo = tLo; -+//ZZ } else { -+//ZZ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+//ZZ } -+//ZZ return rLo; -+//ZZ } -+//ZZ -+//ZZ case Iop_1Uto32: -+//ZZ /* 1Uto32(tmp). Since I1 values generated into registers -+//ZZ are guaranteed to have value either only zero or one, -+//ZZ we can simply return the value of the register in this -+//ZZ case. */ -+//ZZ if (e->Iex.Unop.arg->tag == Iex_RdTmp) { -+//ZZ HReg dst = lookupIRTemp(env, e->Iex.Unop.arg->Iex.RdTmp.tmp); -+//ZZ return dst; -+//ZZ } -+//ZZ /* else fall through */ -+//ZZ case Iop_1Uto8: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); -+//ZZ addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_1Sto32: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+//ZZ ARMRI5* amt = ARMRI5_I5(31); -+//ZZ /* This is really rough. We could do much better here; -+//ZZ perhaps mvn{cond} dst, #0 as the second insn? -+//ZZ (same applies to 1Sto64) */ -+//ZZ addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); -+//ZZ addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt)); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt)); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_Clz32: { -+//ZZ /* Count leading zeroes; easy on ARM. */ -+//ZZ HReg dst = newVRegI(env); -+//ZZ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_CLZ, dst, src)); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_CmpwNEZ32: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src)); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, ARMRI5_I5(31))); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_ReinterpF32asI32: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferS(False/*!toS*/, src, dst)); -+//ZZ return dst; -+//ZZ } -+ -+ case Iop_64to32: -+ case Iop_64to16: -+ case Iop_64to8: -+ /* These are no-ops. */ -+ return iselIntExpr_R(env, e->Iex.Unop.arg); -+ -+ default: -+ break; -+ } -+ -+//ZZ /* All Unop cases involving host-side helper calls. */ -+//ZZ void* fn = NULL; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_CmpNEZ16x2: -+//ZZ fn = &h_generic_calc_CmpNEZ16x2; break; -+//ZZ case Iop_CmpNEZ8x4: -+//ZZ fn = &h_generic_calc_CmpNEZ8x4; break; -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ -+//ZZ if (fn) { -+//ZZ HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ HReg res = newVRegI(env); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R0(), arg)); -+//ZZ addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), -+//ZZ 1, RetLocInt )); -+//ZZ addInstr(env, mk_iMOVds_RR(res, hregARM_R0())); -+//ZZ return res; -+//ZZ } -+ -+ break; -+ } -+ -+ /* --------- GET --------- */ -+ case Iex_Get: { -+ if (ty == Ity_I64 -+ && 0 == (e->Iex.Get.offset & 7) && e->Iex.Get.offset < 8192-8) { -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = mk_baseblock_64bit_access_amode(e->Iex.Get.offset); -+ addInstr(env, ARM64Instr_LdSt64(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ if (ty == Ity_I32 -+ && 0 == (e->Iex.Get.offset & 3) && e->Iex.Get.offset < 4096-4) { -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = mk_baseblock_32bit_access_amode(e->Iex.Get.offset); -+ addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ break; -+ } -+ -+ /* --------- CCALL --------- */ -+ case Iex_CCall: { -+ HReg dst = newVRegI(env); -+ vassert(ty == e->Iex.CCall.retty); -+ -+ /* be very restrictive for now. Only 64-bit ints allowed for -+ args, and 64 bits for return type. Don't forget to change -+ the RetLoc if more types are allowed in future. */ -+ if (e->Iex.CCall.retty != Ity_I64) -+ goto irreducible; -+ -+ /* Marshal args, do the call, clear stack. */ -+ UInt addToSp = 0; -+ RetLoc rloc = mk_RetLoc_INVALID(); -+ Bool ok = doHelperCall( &addToSp, &rloc, env, NULL/*guard*/, -+ e->Iex.CCall.cee, e->Iex.CCall.retty, -+ e->Iex.CCall.args ); -+ /* */ -+ if (ok) { -+ vassert(is_sane_RetLoc(rloc)); -+ vassert(rloc.pri == RLPri_Int); -+ vassert(addToSp == 0); -+ addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0())); -+ return dst; -+ } -+ /* else fall through; will hit the irreducible: label */ -+ } -+ -+ /* --------- LITERAL --------- */ -+ /* 64-bit literals */ -+ case Iex_Const: { -+ ULong u = 0; -+ HReg dst = newVRegI(env); -+ switch (e->Iex.Const.con->tag) { -+ case Ico_U64: u = e->Iex.Const.con->Ico.U64; break; -+ case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; -+ case Ico_U16: u = e->Iex.Const.con->Ico.U16; break; -+ case Ico_U8: u = e->Iex.Const.con->Ico.U8; break; -+ default: ppIRExpr(e); vpanic("iselIntExpr_R.Iex_Const(arm64)"); -+ } -+ addInstr(env, ARM64Instr_Imm64(dst, u)); -+ return dst; -+ } -+ -+ /* --------- MULTIPLEX --------- */ -+ case Iex_ITE: { -+ /* ITE(ccexpr, iftrue, iffalse) */ -+ if (ty == Ity_I64 || ty == Ity_I32) { -+ ARM64CondCode cc; -+ HReg r1 = iselIntExpr_R(env, e->Iex.ITE.iftrue); -+ HReg r0 = iselIntExpr_R(env, e->Iex.ITE.iffalse); -+ HReg dst = newVRegI(env); -+ cc = iselCondCode(env, e->Iex.ITE.cond); -+ addInstr(env, ARM64Instr_CSel(dst, r1, r0, cc)); -+ return dst; -+ } -+ break; -+ } -+ -+ default: -+ break; -+ } /* switch (e->tag) */ -+ -+ /* We get here if no pattern matched. */ -+ irreducible: -+ ppIRExpr(e); -+ vpanic("iselIntExpr_R: cannot reduce tree"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Integer expressions (128 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Compute a 128-bit value into a register pair, which is returned as -+ the first two parameters. As with iselIntExpr_R, these may be -+ either real or virtual regs; in any case they must not be changed -+ by subsequent code emitted by the caller. */ -+ -+static void iselInt128Expr ( HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ) -+{ -+ iselInt128Expr_wrk(rHi, rLo, env, e); -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(*rHi) == HRcInt64); -+ vassert(hregIsVirtual(*rHi)); -+ vassert(hregClass(*rLo) == HRcInt64); -+ vassert(hregIsVirtual(*rLo)); -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ) -+{ -+ vassert(e); -+ vassert(typeOfIRExpr(env->type_env,e) == Ity_I128); -+ -+ /* --------- BINARY ops --------- */ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ /* 64 x 64 -> 128 multiply */ -+ case Iop_MullU64: -+ /*case Iop_MullS64:*/ { -+ Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg dstLo = newVRegI(env); -+ HReg dstHi = newVRegI(env); -+ addInstr(env, ARM64Instr_Mul(dstLo, argL, argR, -+ ARM64mul_PLAIN)); -+ addInstr(env, ARM64Instr_Mul(dstHi, argL, argR, -+ syned ? ARM64mul_SX : ARM64mul_ZX)); -+ *rHi = dstHi; -+ *rLo = dstLo; -+ return; -+ } -+ /* 64HLto128(e1,e2) */ -+ case Iop_64HLto128: -+ *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ return; -+ default: -+ break; -+ } -+ } /* if (e->tag == Iex_Binop) */ -+ -+ ppIRExpr(e); -+ vpanic("iselInt128Expr(arm64)"); -+} -+ -+ -+//ZZ /* -------------------- 64-bit -------------------- */ -+//ZZ -+//ZZ /* Compute a 64-bit value into a register pair, which is returned as -+//ZZ the first two parameters. As with iselIntExpr_R, these may be -+//ZZ either real or virtual regs; in any case they must not be changed -+//ZZ by subsequent code emitted by the caller. */ -+//ZZ -+//ZZ static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ iselInt64Expr_wrk(rHi, rLo, env, e); -+//ZZ # if 0 -+//ZZ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+//ZZ # endif -+//ZZ vassert(hregClass(*rHi) == HRcInt32); -+//ZZ vassert(hregIsVirtual(*rHi)); -+//ZZ vassert(hregClass(*rLo) == HRcInt32); -+//ZZ vassert(hregIsVirtual(*rLo)); -+//ZZ } -+//ZZ -+//ZZ /* DO NOT CALL THIS DIRECTLY ! */ -+//ZZ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ vassert(e); -+//ZZ vassert(typeOfIRExpr(env->type_env,e) == Ity_I64); -+//ZZ -+//ZZ /* 64-bit literal */ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ ULong w64 = e->Iex.Const.con->Ico.U64; -+//ZZ UInt wHi = toUInt(w64 >> 32); -+//ZZ UInt wLo = toUInt(w64); -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ vassert(e->Iex.Const.con->tag == Ico_U64); -+//ZZ addInstr(env, ARMInstr_Imm32(tHi, wHi)); -+//ZZ addInstr(env, ARMInstr_Imm32(tLo, wLo)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* read 64-bit IRTemp */ -+//ZZ if (e->tag == Iex_RdTmp) { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg tmp = iselNeon64Expr(env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ } else { -+//ZZ lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit load */ -+//ZZ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+//ZZ HReg tLo, tHi, rA; -+//ZZ vassert(e->Iex.Load.ty == Ity_I64); -+//ZZ rA = iselIntExpr_R(env, e->Iex.Load.addr); -+//ZZ tHi = newVRegI(env); -+//ZZ tLo = newVRegI(env); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, -+//ZZ tHi, ARMAMode1_RI(rA, 4))); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, -+//ZZ tLo, ARMAMode1_RI(rA, 0))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit GET */ -+//ZZ if (e->tag == Iex_Get) { -+//ZZ ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 0); -+//ZZ ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 4); -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tHi, am4)); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tLo, am0)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* --------- BINARY ops --------- */ -+//ZZ if (e->tag == Iex_Binop) { -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ -+//ZZ /* 32 x 32 -> 64 multiply */ -+//ZZ case Iop_MullS32: -+//ZZ case Iop_MullU32: { -+//ZZ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ ARMMulOp mop = e->Iex.Binop.op == Iop_MullS32 -+//ZZ ? ARMmul_SX : ARMmul_ZX; -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL)); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR)); -+//ZZ addInstr(env, ARMInstr_Mul(mop)); -+//ZZ addInstr(env, mk_iMOVds_RR(tHi, hregARM_R1())); -+//ZZ addInstr(env, mk_iMOVds_RR(tLo, hregARM_R0())); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ case Iop_Or64: { -+//ZZ HReg xLo, xHi, yLo, yHi; -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -+//ZZ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, xHi, ARMRI84_R(yHi))); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, xLo, ARMRI84_R(yLo))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ case Iop_Add64: { -+//ZZ HReg xLo, xHi, yLo, yHi; -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -+//ZZ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_ADDS, tLo, xLo, ARMRI84_R(yLo))); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_ADC, tHi, xHi, ARMRI84_R(yHi))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* 32HLto64(e1,e2) */ -+//ZZ case Iop_32HLto64: { -+//ZZ *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* --------- UNARY ops --------- */ -+//ZZ if (e->tag == Iex_Unop) { -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ -+//ZZ /* ReinterpF64asI64 */ -+//ZZ case Iop_ReinterpF64asI64: { -+//ZZ HReg dstHi = newVRegI(env); -+//ZZ HReg dstLo = newVRegI(env); -+//ZZ HReg src = iselDblExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferD(False/*!toD*/, src, dstHi, dstLo)); -+//ZZ *rHi = dstHi; -+//ZZ *rLo = dstLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* Left64(e) */ -+//ZZ case Iop_Left64: { -+//ZZ HReg yLo, yHi; -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg zero = newVRegI(env); -+//ZZ /* yHi:yLo = arg */ -+//ZZ iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg); -+//ZZ /* zero = 0 */ -+//ZZ addInstr(env, ARMInstr_Imm32(zero, 0)); -+//ZZ /* tLo = 0 - yLo, and set carry */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_SUBS, -+//ZZ tLo, zero, ARMRI84_R(yLo))); -+//ZZ /* tHi = 0 - yHi - carry */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_SBC, -+//ZZ tHi, zero, ARMRI84_R(yHi))); -+//ZZ /* So now we have tHi:tLo = -arg. To finish off, or 'arg' -+//ZZ back in, so as to give the final result -+//ZZ tHi:tLo = arg | -arg. */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, tHi, ARMRI84_R(yHi))); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, tLo, ARMRI84_R(yLo))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* CmpwNEZ64(e) */ -+//ZZ case Iop_CmpwNEZ64: { -+//ZZ HReg srcLo, srcHi; -+//ZZ HReg tmp1 = newVRegI(env); -+//ZZ HReg tmp2 = newVRegI(env); -+//ZZ /* srcHi:srcLo = arg */ -+//ZZ iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg); -+//ZZ /* tmp1 = srcHi | srcLo */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, -+//ZZ tmp1, srcHi, ARMRI84_R(srcLo))); -+//ZZ /* tmp2 = (tmp1 | -tmp1) >>s 31 */ -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, tmp2, tmp1)); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, -+//ZZ tmp2, tmp2, ARMRI84_R(tmp1))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, -+//ZZ tmp2, tmp2, ARMRI5_I5(31))); -+//ZZ *rHi = tmp2; -+//ZZ *rLo = tmp2; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ case Iop_1Sto64: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+//ZZ ARMRI5* amt = ARMRI5_I5(31); -+//ZZ /* This is really rough. We could do much better here; -+//ZZ perhaps mvn{cond} dst, #0 as the second insn? -+//ZZ (same applies to 1Sto32) */ -+//ZZ addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); -+//ZZ addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt)); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt)); -+//ZZ *rHi = dst; -+//ZZ *rLo = dst; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } /* if (e->tag == Iex_Unop) */ -+//ZZ -+//ZZ /* --------- MULTIPLEX --------- */ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ IRType tyC; -+//ZZ HReg r1hi, r1lo, r0hi, r0lo, dstHi, dstLo; -+//ZZ ARMCondCode cc; -+//ZZ tyC = typeOfIRExpr(env->type_env,e->Iex.ITE.cond); -+//ZZ vassert(tyC == Ity_I1); -+//ZZ iselInt64Expr(&r1hi, &r1lo, env, e->Iex.ITE.iftrue); -+//ZZ iselInt64Expr(&r0hi, &r0lo, env, e->Iex.ITE.iffalse); -+//ZZ dstHi = newVRegI(env); -+//ZZ dstLo = newVRegI(env); -+//ZZ addInstr(env, mk_iMOVds_RR(dstHi, r1hi)); -+//ZZ addInstr(env, mk_iMOVds_RR(dstLo, r1lo)); -+//ZZ cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_CMov(cc ^ 1, dstHi, ARMRI84_R(r0hi))); -+//ZZ addInstr(env, ARMInstr_CMov(cc ^ 1, dstLo, ARMRI84_R(r0lo))); -+//ZZ *rHi = dstHi; -+//ZZ *rLo = dstLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* It is convenient sometimes to call iselInt64Expr even when we -+//ZZ have NEON support (e.g. in do_helper_call we need 64-bit -+//ZZ arguments as 2 x 32 regs). */ -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg tmp = iselNeon64Expr(env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return ; -+//ZZ } -+//ZZ -+//ZZ ppIRExpr(e); -+//ZZ vpanic("iselInt64Expr"); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ /*--- ISEL: Vector (NEON) expressions (64 bit) ---*/ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ -+//ZZ static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ HReg r = iselNeon64Expr_wrk( env, e ); -+//ZZ vassert(hregClass(r) == HRcFlt64); -+//ZZ vassert(hregIsVirtual(r)); -+//ZZ return r; -+//ZZ } -+//ZZ -+//ZZ /* DO NOT CALL THIS DIRECTLY */ -+//ZZ static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ IRType ty = typeOfIRExpr(env->type_env, e); -+//ZZ MatchInfo mi; -+//ZZ vassert(e); -+//ZZ vassert(ty == Ity_I64); -+//ZZ -+//ZZ if (e->tag == Iex_RdTmp) { -+//ZZ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+//ZZ } -+//ZZ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit load */ -+//ZZ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+//ZZ HReg res = newVRegD(env); -+//ZZ ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr); -+//ZZ vassert(ty == Ity_I64); -+//ZZ addInstr(env, ARMInstr_NLdStD(True, res, am)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit GET */ -+//ZZ if (e->tag == Iex_Get) { -+//ZZ HReg addr = newVRegI(env); -+//ZZ HReg res = newVRegD(env); -+//ZZ vassert(ty == Ity_I64); -+//ZZ addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset)); -+//ZZ addInstr(env, ARMInstr_NLdStD(True, res, mkARMAModeN_R(addr))); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* --------- BINARY ops --------- */ -+//ZZ if (e->tag == Iex_Binop) { -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ -+//ZZ /* 32 x 32 -> 64 multiply */ -+//ZZ case Iop_MullS32: -+//ZZ case Iop_MullU32: { -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_And64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VAND, -+//ZZ res, argL, argR, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Or64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, argL, argR, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Xor64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VXOR, -+//ZZ res, argL, argR, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 32HLto64(e1,e2) */ -+//ZZ case Iop_32HLto64: { -+//ZZ HReg rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ HReg rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg res = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_Add8x8: -+//ZZ case Iop_Add16x4: -+//ZZ case Iop_Add32x2: -+//ZZ case Iop_Add64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Add8x8: size = 0; break; -+//ZZ case Iop_Add16x4: size = 1; break; -+//ZZ case Iop_Add32x2: size = 2; break; -+//ZZ case Iop_Add64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VADD, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Add32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recps32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrts32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveHI32x2: -+//ZZ case Iop_InterleaveLO32x2: -+//ZZ case Iop_InterleaveOddLanes8x8: -+//ZZ case Iop_InterleaveEvenLanes8x8: -+//ZZ case Iop_InterleaveOddLanes16x4: -+//ZZ case Iop_InterleaveEvenLanes16x4: { -+//ZZ HReg rD = newVRegD(env); -+//ZZ HReg rM = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveOddLanes8x8: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveEvenLanes8x8: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveOddLanes16x4: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveEvenLanes16x4: resRd = True; size = 1; break; -+//ZZ case Iop_InterleaveHI32x2: resRd = False; size = 2; break; -+//ZZ case Iop_InterleaveLO32x2: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, False)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 4 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveHI8x8: -+//ZZ case Iop_InterleaveLO8x8: -+//ZZ case Iop_InterleaveHI16x4: -+//ZZ case Iop_InterleaveLO16x4: { -+//ZZ HReg rD = newVRegD(env); -+//ZZ HReg rM = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveHI8x8: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveLO8x8: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveHI16x4: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveLO16x4: resRd = True; size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, False)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 4 verified 18 Apr 2013 -+//ZZ case Iop_CatOddLanes8x8: -+//ZZ case Iop_CatEvenLanes8x8: -+//ZZ case Iop_CatOddLanes16x4: -+//ZZ case Iop_CatEvenLanes16x4: { -+//ZZ HReg rD = newVRegD(env); -+//ZZ HReg rM = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CatOddLanes8x8: resRd = False; size = 0; break; -+//ZZ case Iop_CatEvenLanes8x8: resRd = True; size = 0; break; -+//ZZ case Iop_CatOddLanes16x4: resRd = False; size = 1; break; -+//ZZ case Iop_CatEvenLanes16x4: resRd = True; size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, False)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ case Iop_QAdd8Ux8: -+//ZZ case Iop_QAdd16Ux4: -+//ZZ case Iop_QAdd32Ux2: -+//ZZ case Iop_QAdd64Ux1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Ux8: size = 0; break; -+//ZZ case Iop_QAdd16Ux4: size = 1; break; -+//ZZ case Iop_QAdd32Ux2: size = 2; break; -+//ZZ case Iop_QAdd64Ux1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QAdd8Sx8: -+//ZZ case Iop_QAdd16Sx4: -+//ZZ case Iop_QAdd32Sx2: -+//ZZ case Iop_QAdd64Sx1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Sx8: size = 0; break; -+//ZZ case Iop_QAdd16Sx4: size = 1; break; -+//ZZ case Iop_QAdd32Sx2: size = 2; break; -+//ZZ case Iop_QAdd64Sx1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub8x8: -+//ZZ case Iop_Sub16x4: -+//ZZ case Iop_Sub32x2: -+//ZZ case Iop_Sub64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sub8x8: size = 0; break; -+//ZZ case Iop_Sub16x4: size = 1; break; -+//ZZ case Iop_Sub32x2: size = 2; break; -+//ZZ case Iop_Sub64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Ux8: -+//ZZ case Iop_QSub16Ux4: -+//ZZ case Iop_QSub32Ux2: -+//ZZ case Iop_QSub64Ux1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Ux8: size = 0; break; -+//ZZ case Iop_QSub16Ux4: size = 1; break; -+//ZZ case Iop_QSub32Ux2: size = 2; break; -+//ZZ case Iop_QSub64Ux1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Sx8: -+//ZZ case Iop_QSub16Sx4: -+//ZZ case Iop_QSub32Sx2: -+//ZZ case Iop_QSub64Sx1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Sx8: size = 0; break; -+//ZZ case Iop_QSub16Sx4: size = 1; break; -+//ZZ case Iop_QSub32Sx2: size = 2; break; -+//ZZ case Iop_QSub64Sx1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Ux8: -+//ZZ case Iop_Max16Ux4: -+//ZZ case Iop_Max32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Ux8: size = 0; break; -+//ZZ case Iop_Max16Ux4: size = 1; break; -+//ZZ case Iop_Max32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Sx8: -+//ZZ case Iop_Max16Sx4: -+//ZZ case Iop_Max32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Sx8: size = 0; break; -+//ZZ case Iop_Max16Sx4: size = 1; break; -+//ZZ case Iop_Max32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Ux8: -+//ZZ case Iop_Min16Ux4: -+//ZZ case Iop_Min32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Ux8: size = 0; break; -+//ZZ case Iop_Min16Ux4: size = 1; break; -+//ZZ case Iop_Min32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Sx8: -+//ZZ case Iop_Min16Sx4: -+//ZZ case Iop_Min32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Sx8: size = 0; break; -+//ZZ case Iop_Min16Sx4: size = 1; break; -+//ZZ case Iop_Min32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sar8x8: -+//ZZ case Iop_Sar16x4: -+//ZZ case Iop_Sar32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegD(env); -+//ZZ HReg zero = newVRegD(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sar8x8: size = 0; break; -+//ZZ case Iop_Sar16x4: size = 1; break; -+//ZZ case Iop_Sar32x2: size = 2; break; -+//ZZ case Iop_Sar64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR2, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sal8x8: -+//ZZ case Iop_Sal16x4: -+//ZZ case Iop_Sal32x2: -+//ZZ case Iop_Sal64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sal8x8: size = 0; break; -+//ZZ case Iop_Sal16x4: size = 1; break; -+//ZZ case Iop_Sal32x2: size = 2; break; -+//ZZ case Iop_Sal64x1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shr8x8: -+//ZZ case Iop_Shr16x4: -+//ZZ case Iop_Shr32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegD(env); -+//ZZ HReg zero = newVRegD(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shr8x8: size = 0; break; -+//ZZ case Iop_Shr16x4: size = 1; break; -+//ZZ case Iop_Shr32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR2, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shl8x8: -+//ZZ case Iop_Shl16x4: -+//ZZ case Iop_Shl32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shl8x8: size = 0; break; -+//ZZ case Iop_Shl16x4: size = 1; break; -+//ZZ case Iop_Shl32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShl8x8: -+//ZZ case Iop_QShl16x4: -+//ZZ case Iop_QShl32x2: -+//ZZ case Iop_QShl64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShl8x8: size = 0; break; -+//ZZ case Iop_QShl16x4: size = 1; break; -+//ZZ case Iop_QShl32x2: size = 2; break; -+//ZZ case Iop_QShl64x1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSHL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSal8x8: -+//ZZ case Iop_QSal16x4: -+//ZZ case Iop_QSal32x2: -+//ZZ case Iop_QSal64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSal8x8: size = 0; break; -+//ZZ case Iop_QSal16x4: size = 1; break; -+//ZZ case Iop_QSal32x2: size = 2; break; -+//ZZ case Iop_QSal64x1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSAL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8x8: -+//ZZ case Iop_QShlN16x4: -+//ZZ case Iop_QShlN32x2: -+//ZZ case Iop_QShlN64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8x8: size = 8 | imm; break; -+//ZZ case Iop_QShlN16x4: size = 16 | imm; break; -+//ZZ case Iop_QShlN32x2: size = 32 | imm; break; -+//ZZ case Iop_QShlN64x1: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, -+//ZZ res, argL, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8Sx8: -+//ZZ case Iop_QShlN16Sx4: -+//ZZ case Iop_QShlN32Sx2: -+//ZZ case Iop_QShlN64Sx1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8Sx8: size = 8 | imm; break; -+//ZZ case Iop_QShlN16Sx4: size = 16 | imm; break; -+//ZZ case Iop_QShlN32Sx2: size = 32 | imm; break; -+//ZZ case Iop_QShlN64Sx1: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, -+//ZZ res, argL, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSalN8x8: -+//ZZ case Iop_QSalN16x4: -+//ZZ case Iop_QSalN32x2: -+//ZZ case Iop_QSalN64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSalN8x8: size = 8 | imm; break; -+//ZZ case Iop_QSalN16x4: size = 16 | imm; break; -+//ZZ case Iop_QSalN32x2: size = 32 | imm; break; -+//ZZ case Iop_QSalN64x1: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, -+//ZZ res, argL, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_ShrN8x8: -+//ZZ case Iop_ShrN16x4: -+//ZZ case Iop_ShrN32x2: -+//ZZ case Iop_Shr64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegI(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_ShrN8x8: size = 0; break; -+//ZZ case Iop_ShrN16x4: size = 1; break; -+//ZZ case Iop_ShrN32x2: size = 2; break; -+//ZZ case Iop_Shr64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, tmp, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_ShlN8x8: -+//ZZ case Iop_ShlN16x4: -+//ZZ case Iop_ShlN32x2: -+//ZZ case Iop_Shl64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ /* special-case Shl64(x, imm8) since the Neon front -+//ZZ end produces a lot of those for V{LD,ST}{1,2,3,4}. */ -+//ZZ if (e->Iex.Binop.op == Iop_Shl64 -+//ZZ && e->Iex.Binop.arg2->tag == Iex_Const) { -+//ZZ vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8); -+//ZZ Int nshift = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ if (nshift >= 1 && nshift <= 63) { -+//ZZ addInstr(env, ARMInstr_NShl64(res, argL, nshift)); -+//ZZ return res; -+//ZZ } -+//ZZ /* else fall through to general case */ -+//ZZ } -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_ShlN8x8: size = 0; break; -+//ZZ case Iop_ShlN16x4: size = 1; break; -+//ZZ case Iop_ShlN32x2: size = 2; break; -+//ZZ case Iop_Shl64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, -+//ZZ tmp, argR, 0, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, tmp, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_SarN8x8: -+//ZZ case Iop_SarN16x4: -+//ZZ case Iop_SarN32x2: -+//ZZ case Iop_Sar64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegI(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_SarN8x8: size = 0; break; -+//ZZ case Iop_SarN16x4: size = 1; break; -+//ZZ case Iop_SarN32x2: size = 2; break; -+//ZZ case Iop_Sar64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, tmp, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT8Ux8: -+//ZZ case Iop_CmpGT16Ux4: -+//ZZ case Iop_CmpGT32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Ux8: size = 0; break; -+//ZZ case Iop_CmpGT16Ux4: size = 1; break; -+//ZZ case Iop_CmpGT32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT8Sx8: -+//ZZ case Iop_CmpGT16Sx4: -+//ZZ case Iop_CmpGT32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Sx8: size = 0; break; -+//ZZ case Iop_CmpGT16Sx4: size = 1; break; -+//ZZ case Iop_CmpGT32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ8x8: -+//ZZ case Iop_CmpEQ16x4: -+//ZZ case Iop_CmpEQ32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpEQ8x8: size = 0; break; -+//ZZ case Iop_CmpEQ16x4: size = 1; break; -+//ZZ case Iop_CmpEQ32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul8x8: -+//ZZ case Iop_Mul16x4: -+//ZZ case Iop_Mul32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mul8x8: size = 0; break; -+//ZZ case Iop_Mul16x4: size = 1; break; -+//ZZ case Iop_Mul32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMUL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QDMulHi16Sx4: -+//ZZ case Iop_QDMulHi32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QDMulHi16Sx4: size = 1; break; -+//ZZ case Iop_QDMulHi32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QRDMulHi16Sx4: -+//ZZ case Iop_QRDMulHi32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QRDMulHi16Sx4: size = 1; break; -+//ZZ case Iop_QRDMulHi32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_PwAdd8x8: -+//ZZ case Iop_PwAdd16x4: -+//ZZ case Iop_PwAdd32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAdd8x8: size = 0; break; -+//ZZ case Iop_PwAdd16x4: size = 1; break; -+//ZZ case Iop_PwAdd32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPADD, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAdd32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPADDFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin8Ux8: -+//ZZ case Iop_PwMin16Ux4: -+//ZZ case Iop_PwMin32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMin8Ux8: size = 0; break; -+//ZZ case Iop_PwMin16Ux4: size = 1; break; -+//ZZ case Iop_PwMin32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin8Sx8: -+//ZZ case Iop_PwMin16Sx4: -+//ZZ case Iop_PwMin32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMin8Sx8: size = 0; break; -+//ZZ case Iop_PwMin16Sx4: size = 1; break; -+//ZZ case Iop_PwMin32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax8Ux8: -+//ZZ case Iop_PwMax16Ux4: -+//ZZ case Iop_PwMax32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMax8Ux8: size = 0; break; -+//ZZ case Iop_PwMax16Ux4: size = 1; break; -+//ZZ case Iop_PwMax32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax8Sx8: -+//ZZ case Iop_PwMax16Sx4: -+//ZZ case Iop_PwMax32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMax8Sx8: size = 0; break; -+//ZZ case Iop_PwMax16Sx4: size = 1; break; -+//ZZ case Iop_PwMax32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Perm8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VTBL, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PolynomialMul8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGE32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F32ToFixed32Ux2_RZ: -+//ZZ case Iop_F32ToFixed32Sx2_RZ: -+//ZZ case Iop_Fixed32UToF32x2_RN: -+//ZZ case Iop_Fixed32SToF32x2_RN: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ ARMNeonUnOp op; -+//ZZ UInt imm6; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports FP <-> Fixed conversion with constant " -+//ZZ "second argument less than 33 only\n"); -+//ZZ } -+//ZZ imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ vassert(imm6 <= 32 && imm6 > 0); -+//ZZ imm6 = 64 - imm6; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_F32ToFixed32Ux2_RZ: op = ARMneon_VCVTFtoFixedU; break; -+//ZZ case Iop_F32ToFixed32Sx2_RZ: op = ARMneon_VCVTFtoFixedS; break; -+//ZZ case Iop_Fixed32UToF32x2_RN: op = ARMneon_VCVTFixedUtoF; break; -+//ZZ case Iop_Fixed32SToF32x2_RN: op = ARMneon_VCVTFixedStoF; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False)); -+//ZZ return res; -+//ZZ } -+//ZZ /* -+//ZZ FIXME: is this here or not? -+//ZZ case Iop_VDup8x8: -+//ZZ case Iop_VDup16x4: -+//ZZ case Iop_VDup32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ UInt size = 0; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_VDup8x8: imm4 = (index << 1) + 1; break; -+//ZZ case Iop_VDup16x4: imm4 = (index << 2) + 2; break; -+//ZZ case Iop_VDup32x2: imm4 = (index << 3) + 4; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ if (imm4 >= 16) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VDUP, -+//ZZ res, argL, imm4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ */ -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* --------- UNARY ops --------- */ -+//ZZ if (e->tag == Iex_Unop) { -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ -+//ZZ /* 32Uto64 */ -+//ZZ case Iop_32Uto64: { -+//ZZ HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ HReg rHi = newVRegI(env); -+//ZZ HReg res = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_Imm32(rHi, 0)); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 32Sto64 */ -+//ZZ case Iop_32Sto64: { -+//ZZ HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ HReg rHi = newVRegI(env); -+//ZZ addInstr(env, mk_iMOVds_RR(rHi, rLo)); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, rHi, rHi, ARMRI5_I5(31))); -+//ZZ HReg res = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* The next 3 are pass-throughs */ -+//ZZ /* ReinterpF64asI64 */ -+//ZZ case Iop_ReinterpF64asI64: -+//ZZ /* Left64(e) */ -+//ZZ case Iop_Left64: -+//ZZ /* CmpwNEZ64(e) */ -+//ZZ case Iop_1Sto64: { -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_Not64: { -+//ZZ DECLARE_PATTERN(p_veqz_8x8); -+//ZZ DECLARE_PATTERN(p_veqz_16x4); -+//ZZ DECLARE_PATTERN(p_veqz_32x2); -+//ZZ DECLARE_PATTERN(p_vcge_8sx8); -+//ZZ DECLARE_PATTERN(p_vcge_16sx4); -+//ZZ DECLARE_PATTERN(p_vcge_32sx2); -+//ZZ DECLARE_PATTERN(p_vcge_8ux8); -+//ZZ DECLARE_PATTERN(p_vcge_16ux4); -+//ZZ DECLARE_PATTERN(p_vcge_32ux2); -+//ZZ DEFINE_PATTERN(p_veqz_8x8, -+//ZZ unop(Iop_Not64, unop(Iop_CmpNEZ8x8, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_16x4, -+//ZZ unop(Iop_Not64, unop(Iop_CmpNEZ16x4, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_32x2, -+//ZZ unop(Iop_Not64, unop(Iop_CmpNEZ32x2, bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8sx8, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT8Sx8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16sx4, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT16Sx4, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32sx2, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT32Sx2, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8ux8, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT8Ux8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16ux4, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT16Ux4, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32ux2, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT32Ux2, bind(1), bind(0)))); -+//ZZ if (matchIRExpr(&mi, p_veqz_8x8, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_16x4, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_32x2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8sx8, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16sx4, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 1, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32sx2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8ux8, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16ux4, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 1, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32ux2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } else { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ case Iop_Dup8x8: -+//ZZ case Iop_Dup16x4: -+//ZZ case Iop_Dup32x2: { -+//ZZ HReg res, arg; -+//ZZ UInt size; -+//ZZ DECLARE_PATTERN(p_vdup_8x8); -+//ZZ DECLARE_PATTERN(p_vdup_16x4); -+//ZZ DECLARE_PATTERN(p_vdup_32x2); -+//ZZ DEFINE_PATTERN(p_vdup_8x8, -+//ZZ unop(Iop_Dup8x8, binop(Iop_GetElem8x8, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_16x4, -+//ZZ unop(Iop_Dup16x4, binop(Iop_GetElem16x4, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_32x2, -+//ZZ unop(Iop_Dup32x2, binop(Iop_GetElem32x2, bind(0), bind(1)))); -+//ZZ if (matchIRExpr(&mi, p_vdup_8x8, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 1) + 1; -+//ZZ if (index < 8) { -+//ZZ res = newVRegD(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, False -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_16x4, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 2) + 2; -+//ZZ if (index < 4) { -+//ZZ res = newVRegD(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, False -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_32x2, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 3) + 4; -+//ZZ if (index < 2) { -+//ZZ res = newVRegD(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, False -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } -+//ZZ arg = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ res = newVRegD(env); -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Dup8x8: size = 0; break; -+//ZZ case Iop_Dup16x4: size = 1; break; -+//ZZ case Iop_Dup32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Abs8x8: -+//ZZ case Iop_Abs16x4: -+//ZZ case Iop_Abs32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Abs8x8: size = 0; break; -+//ZZ case Iop_Abs16x4: size = 1; break; -+//ZZ case Iop_Abs32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse64_8x8: -+//ZZ case Iop_Reverse64_16x4: -+//ZZ case Iop_Reverse64_32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse64_8x8: size = 0; break; -+//ZZ case Iop_Reverse64_16x4: size = 1; break; -+//ZZ case Iop_Reverse64_32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV64, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse32_8x8: -+//ZZ case Iop_Reverse32_16x4: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse32_8x8: size = 0; break; -+//ZZ case Iop_Reverse32_16x4: size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV32, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse16_8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV16, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpwNEZ64: { -+//ZZ HReg x_lsh = newVRegD(env); -+//ZZ HReg x_rsh = newVRegD(env); -+//ZZ HReg lsh_amt = newVRegD(env); -+//ZZ HReg rsh_amt = newVRegD(env); -+//ZZ HReg zero = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg tmp2 = newVRegD(env); -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg x = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, False)); -+//ZZ addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32))); -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ rsh_amt, zero, lsh_amt, 2, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_lsh, x, lsh_amt, 3, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_rsh, x, rsh_amt, 3, False)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ tmp, x_lsh, x_rsh, 0, False)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, tmp, x, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpNEZ8x8: -+//ZZ case Iop_CmpNEZ16x4: -+//ZZ case Iop_CmpNEZ32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_CmpNEZ8x8: size = 0; break; -+//ZZ case Iop_CmpNEZ16x4: size = 1; break; -+//ZZ case Iop_CmpNEZ32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_NarrowUn16to8x8: -+//ZZ case Iop_NarrowUn32to16x4: -+//ZZ case Iop_NarrowUn64to32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_NarrowUn16to8x8: size = 0; break; -+//ZZ case Iop_NarrowUn32to16x4: size = 1; break; -+//ZZ case Iop_NarrowUn64to32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYN, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QNarrowUn16Sto8Sx8: -+//ZZ case Iop_QNarrowUn32Sto16Sx4: -+//ZZ case Iop_QNarrowUn64Sto32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QNarrowUn16Sto8Sx8: size = 0; break; -+//ZZ case Iop_QNarrowUn32Sto16Sx4: size = 1; break; -+//ZZ case Iop_QNarrowUn64Sto32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QNarrowUn16Sto8Ux8: -+//ZZ case Iop_QNarrowUn32Sto16Ux4: -+//ZZ case Iop_QNarrowUn64Sto32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QNarrowUn16Sto8Ux8: size = 0; break; -+//ZZ case Iop_QNarrowUn32Sto16Ux4: size = 1; break; -+//ZZ case Iop_QNarrowUn64Sto32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QNarrowUn16Uto8Ux8: -+//ZZ case Iop_QNarrowUn32Uto16Ux4: -+//ZZ case Iop_QNarrowUn64Uto32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QNarrowUn16Uto8Ux8: size = 0; break; -+//ZZ case Iop_QNarrowUn32Uto16Ux4: size = 1; break; -+//ZZ case Iop_QNarrowUn64Uto32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Sx8: -+//ZZ case Iop_PwAddL16Sx4: -+//ZZ case Iop_PwAddL32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Sx8: size = 0; break; -+//ZZ case Iop_PwAddL16Sx4: size = 1; break; -+//ZZ case Iop_PwAddL32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Ux8: -+//ZZ case Iop_PwAddL16Ux4: -+//ZZ case Iop_PwAddL32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Ux8: size = 0; break; -+//ZZ case Iop_PwAddL16Ux4: size = 1; break; -+//ZZ case Iop_PwAddL32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cnt8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CNT, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Clz8Sx8: -+//ZZ case Iop_Clz16Sx4: -+//ZZ case Iop_Clz32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Clz8Sx8: size = 0; break; -+//ZZ case Iop_Clz16Sx4: size = 1; break; -+//ZZ case Iop_Clz32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cls8Sx8: -+//ZZ case Iop_Cls16Sx4: -+//ZZ case Iop_Cls32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Cls8Sx8: size = 0; break; -+//ZZ case Iop_Cls16Sx4: size = 1; break; -+//ZZ case Iop_Cls32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Sx2_RZ: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Ux2_RZ: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32StoFx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32UtoFx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F32toF16x4: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF, -+//ZZ res, argL, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP, -+//ZZ res, argL, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Abs32Fx2: { -+//ZZ DECLARE_PATTERN(p_vabd_32fx2); -+//ZZ DEFINE_PATTERN(p_vabd_32fx2, -+//ZZ unop(Iop_Abs32Fx2, -+//ZZ binop(Iop_Sub32Fx2, -+//ZZ bind(0), -+//ZZ bind(1)))); -+//ZZ if (matchIRExpr(&mi, p_vabd_32fx2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } else { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ case Iop_Rsqrte32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrte32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Neg32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } /* if (e->tag == Iex_Unop) */ -+//ZZ -+//ZZ if (e->tag == Iex_Triop) { -+//ZZ IRTriop *triop = e->Iex.Triop.details; -+//ZZ -+//ZZ switch (triop->op) { -+//ZZ case Iop_Extract64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, triop->arg1); -+//ZZ HReg argR = iselNeon64Expr(env, triop->arg2); -+//ZZ UInt imm4; -+//ZZ if (triop->arg3->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) { -+//ZZ vpanic("ARM target supports Iop_Extract64 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ imm4 = triop->arg3->Iex.Const.con->Ico.U8; -+//ZZ if (imm4 >= 8) { -+//ZZ vpanic("ARM target supports Iop_Extract64 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VEXT, -+//ZZ res, argL, argR, imm4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_SetElem8x8: -+//ZZ case Iop_SetElem16x4: -+//ZZ case Iop_SetElem32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg dreg = iselNeon64Expr(env, triop->arg1); -+//ZZ HReg arg = iselIntExpr_R(env, triop->arg3); -+//ZZ UInt index, size; -+//ZZ if (triop->arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, triop->arg2) != Ity_I8) { -+//ZZ vpanic("ARM target supports SetElem with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ index = triop->arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (triop->op) { -+//ZZ case Iop_SetElem8x8: vassert(index < 8); size = 0; break; -+//ZZ case Iop_SetElem16x4: vassert(index < 4); size = 1; break; -+//ZZ case Iop_SetElem32x2: vassert(index < 2); size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnaryS(ARMneon_SETELEM, -+//ZZ mkARMNRS(ARMNRS_Scalar, res, index), -+//ZZ mkARMNRS(ARMNRS_Reg, arg, 0), -+//ZZ size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* --------- MULTIPLEX --------- */ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ ppIRExpr(e); -+//ZZ vpanic("iselNeon64Expr"); -+//ZZ } -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Vector (NEON) expressions (128 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+static HReg iselV128Expr ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselV128Expr_wrk( env, e ); -+ vassert(hregClass(r) == HRcVec128); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY */ -+static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env, e); -+ vassert(e); -+ vassert(ty == Ity_V128); -+ -+ if (e->tag == Iex_RdTmp) { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ if (e->tag == Iex_Const) { -+ /* Only a very limited range of constants is handled. */ -+ vassert(e->Iex.Const.con->tag == Ico_V128); -+ UShort con = e->Iex.Const.con->Ico.V128; -+ if (con == 0x0000) { -+ HReg res = newVRegV(env); -+ addInstr(env, ARM64Instr_VImmQ(res, con)); -+ return res; -+ } -+ /* Unhandled */ -+ goto v128_expr_bad; -+ } -+ -+ if (e->tag == Iex_Load) { -+ HReg res = newVRegV(env); -+ HReg rN = iselIntExpr_R(env, e->Iex.Load.addr); -+ vassert(ty == Ity_V128); -+ addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, rN)); -+ return res; -+ } -+ -+ if (e->tag == Iex_Get) { -+ UInt offs = (UInt)e->Iex.Get.offset; -+ if (offs < (1<<12)) { -+ HReg addr = mk_baseblock_128bit_access_addr(env, offs); -+ HReg res = newVRegV(env); -+ vassert(ty == Ity_V128); -+ addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, addr)); -+ return res; -+ } -+ goto v128_expr_bad; -+ } -+ -+//ZZ if (e->tag == Iex_Unop) { -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_NotV128: { -+//ZZ DECLARE_PATTERN(p_veqz_8x16); -+//ZZ DECLARE_PATTERN(p_veqz_16x8); -+//ZZ DECLARE_PATTERN(p_veqz_32x4); -+//ZZ DECLARE_PATTERN(p_vcge_8sx16); -+//ZZ DECLARE_PATTERN(p_vcge_16sx8); -+//ZZ DECLARE_PATTERN(p_vcge_32sx4); -+//ZZ DECLARE_PATTERN(p_vcge_8ux16); -+//ZZ DECLARE_PATTERN(p_vcge_16ux8); -+//ZZ DECLARE_PATTERN(p_vcge_32ux4); -+//ZZ DEFINE_PATTERN(p_veqz_8x16, -+//ZZ unop(Iop_NotV128, unop(Iop_CmpNEZ8x16, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_16x8, -+//ZZ unop(Iop_NotV128, unop(Iop_CmpNEZ16x8, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_32x4, -+//ZZ unop(Iop_NotV128, unop(Iop_CmpNEZ32x4, bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8sx16, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT8Sx16, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16sx8, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT16Sx8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32sx4, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT32Sx4, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8ux16, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT8Ux16, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16ux8, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT16Ux8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32ux4, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT32Ux4, bind(1), bind(0)))); -+//ZZ if (matchIRExpr(&mi, p_veqz_8x16, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_16x8, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_32x4, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8sx16, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 0, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16sx8, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 1, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32sx4, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8ux16, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 0, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16ux8, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 1, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32ux4, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } else { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ case Iop_Dup8x16: -+//ZZ case Iop_Dup16x8: -+//ZZ case Iop_Dup32x4: { -+//ZZ HReg res, arg; -+//ZZ UInt size; -+//ZZ DECLARE_PATTERN(p_vdup_8x16); -+//ZZ DECLARE_PATTERN(p_vdup_16x8); -+//ZZ DECLARE_PATTERN(p_vdup_32x4); -+//ZZ DEFINE_PATTERN(p_vdup_8x16, -+//ZZ unop(Iop_Dup8x16, binop(Iop_GetElem8x8, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_16x8, -+//ZZ unop(Iop_Dup16x8, binop(Iop_GetElem16x4, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_32x4, -+//ZZ unop(Iop_Dup32x4, binop(Iop_GetElem32x2, bind(0), bind(1)))); -+//ZZ if (matchIRExpr(&mi, p_vdup_8x16, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 1) + 1; -+//ZZ if (index < 8) { -+//ZZ res = newVRegV(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, True -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_16x8, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 2) + 2; -+//ZZ if (index < 4) { -+//ZZ res = newVRegV(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, True -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_32x4, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 3) + 4; -+//ZZ if (index < 2) { -+//ZZ res = newVRegV(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, True -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } -+//ZZ arg = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ res = newVRegV(env); -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Dup8x16: size = 0; break; -+//ZZ case Iop_Dup16x8: size = 1; break; -+//ZZ case Iop_Dup32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Abs8x16: -+//ZZ case Iop_Abs16x8: -+//ZZ case Iop_Abs32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Abs8x16: size = 0; break; -+//ZZ case Iop_Abs16x8: size = 1; break; -+//ZZ case Iop_Abs32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse64_8x16: -+//ZZ case Iop_Reverse64_16x8: -+//ZZ case Iop_Reverse64_32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse64_8x16: size = 0; break; -+//ZZ case Iop_Reverse64_16x8: size = 1; break; -+//ZZ case Iop_Reverse64_32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV64, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse32_8x16: -+//ZZ case Iop_Reverse32_16x8: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse32_8x16: size = 0; break; -+//ZZ case Iop_Reverse32_16x8: size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV32, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse16_8x16: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV16, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpNEZ64x2: { -+//ZZ HReg x_lsh = newVRegV(env); -+//ZZ HReg x_rsh = newVRegV(env); -+//ZZ HReg lsh_amt = newVRegV(env); -+//ZZ HReg rsh_amt = newVRegV(env); -+//ZZ HReg zero = newVRegV(env); -+//ZZ HReg tmp = newVRegV(env); -+//ZZ HReg tmp2 = newVRegV(env); -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg x = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, True)); -+//ZZ addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32))); -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ rsh_amt, zero, lsh_amt, 2, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_lsh, x, lsh_amt, 3, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_rsh, x, rsh_amt, 3, True)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ tmp, x_lsh, x_rsh, 0, True)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, tmp, x, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpNEZ8x16: -+//ZZ case Iop_CmpNEZ16x8: -+//ZZ case Iop_CmpNEZ32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg tmp = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_CmpNEZ8x16: size = 0; break; -+//ZZ case Iop_CmpNEZ16x8: size = 1; break; -+//ZZ case Iop_CmpNEZ32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Widen8Uto16x8: -+//ZZ case Iop_Widen16Uto32x4: -+//ZZ case Iop_Widen32Uto64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Widen8Uto16x8: size = 0; break; -+//ZZ case Iop_Widen16Uto32x4: size = 1; break; -+//ZZ case Iop_Widen32Uto64x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Widen8Sto16x8: -+//ZZ case Iop_Widen16Sto32x4: -+//ZZ case Iop_Widen32Sto64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Widen8Sto16x8: size = 0; break; -+//ZZ case Iop_Widen16Sto32x4: size = 1; break; -+//ZZ case Iop_Widen32Sto64x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Sx16: -+//ZZ case Iop_PwAddL16Sx8: -+//ZZ case Iop_PwAddL32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Sx16: size = 0; break; -+//ZZ case Iop_PwAddL16Sx8: size = 1; break; -+//ZZ case Iop_PwAddL32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Ux16: -+//ZZ case Iop_PwAddL16Ux8: -+//ZZ case Iop_PwAddL32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Ux16: size = 0; break; -+//ZZ case Iop_PwAddL16Ux8: size = 1; break; -+//ZZ case Iop_PwAddL32Ux4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cnt8x16: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Clz8Sx16: -+//ZZ case Iop_Clz16Sx8: -+//ZZ case Iop_Clz32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Clz8Sx16: size = 0; break; -+//ZZ case Iop_Clz16Sx8: size = 1; break; -+//ZZ case Iop_Clz32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cls8Sx16: -+//ZZ case Iop_Cls16Sx8: -+//ZZ case Iop_Cls32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Cls8Sx16: size = 0; break; -+//ZZ case Iop_Cls16Sx8: size = 1; break; -+//ZZ case Iop_Cls32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Sx4_RZ: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Ux4_RZ: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32StoFx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32UtoFx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F16toF32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF16toF32, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Abs32Fx4: { -+//ZZ DECLARE_PATTERN(p_vabd_32fx4); -+//ZZ DEFINE_PATTERN(p_vabd_32fx4, -+//ZZ unop(Iop_Abs32Fx4, -+//ZZ binop(Iop_Sub32Fx4, -+//ZZ bind(0), -+//ZZ bind(1)))); -+//ZZ if (matchIRExpr(&mi, p_vabd_32fx4, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP, -+//ZZ res, argL, argR, 0, True)); -+//ZZ return res; -+//ZZ } else { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ case Iop_Rsqrte32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrte32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Neg32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF, -+//ZZ res, arg, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ /* ... */ -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ case Iop_64HLtoV128: { -+ HReg res = newVRegV(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_VQfromXX(res, argL, argR)); -+ return res; -+ } -+//ZZ case Iop_AndV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VAND, -+//ZZ res, argL, argR, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_OrV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, argL, argR, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_XorV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VXOR, -+//ZZ res, argL, argR, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Add8x16: -+//ZZ case Iop_Add16x8: -+//ZZ case Iop_Add32x4: -+//ZZ case Iop_Add64x2: { -+//ZZ /* -+//ZZ FIXME: remove this if not used -+//ZZ DECLARE_PATTERN(p_vrhadd_32sx4); -+//ZZ ULong one = (1LL << 32) | 1LL; -+//ZZ DEFINE_PATTERN(p_vrhadd_32sx4, -+//ZZ binop(Iop_Add32x4, -+//ZZ binop(Iop_Add32x4, -+//ZZ binop(Iop_SarN32x4, -+//ZZ bind(0), -+//ZZ mkU8(1)), -+//ZZ binop(Iop_SarN32x4, -+//ZZ bind(1), -+//ZZ mkU8(1))), -+//ZZ binop(Iop_SarN32x4, -+//ZZ binop(Iop_Add32x4, -+//ZZ binop(Iop_Add32x4, -+//ZZ binop(Iop_AndV128, -+//ZZ bind(0), -+//ZZ mkU128(one)), -+//ZZ binop(Iop_AndV128, -+//ZZ bind(1), -+//ZZ mkU128(one))), -+//ZZ mkU128(one)), -+//ZZ mkU8(1)))); -+//ZZ */ -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Add8x16: size = 0; break; -+//ZZ case Iop_Add16x8: size = 1; break; -+//ZZ case Iop_Add32x4: size = 2; break; -+//ZZ case Iop_Add64x2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VADD"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VADD, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Add32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recps32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrts32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveEvenLanes8x16: -+//ZZ case Iop_InterleaveOddLanes8x16: -+//ZZ case Iop_InterleaveEvenLanes16x8: -+//ZZ case Iop_InterleaveOddLanes16x8: -+//ZZ case Iop_InterleaveEvenLanes32x4: -+//ZZ case Iop_InterleaveOddLanes32x4: { -+//ZZ HReg rD = newVRegV(env); -+//ZZ HReg rM = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveOddLanes8x16: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveEvenLanes8x16: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveOddLanes16x8: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveEvenLanes16x8: resRd = True; size = 1; break; -+//ZZ case Iop_InterleaveOddLanes32x4: resRd = False; size = 2; break; -+//ZZ case Iop_InterleaveEvenLanes32x4: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, True)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveHI8x16: -+//ZZ case Iop_InterleaveLO8x16: -+//ZZ case Iop_InterleaveHI16x8: -+//ZZ case Iop_InterleaveLO16x8: -+//ZZ case Iop_InterleaveHI32x4: -+//ZZ case Iop_InterleaveLO32x4: { -+//ZZ HReg rD = newVRegV(env); -+//ZZ HReg rM = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveHI8x16: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveLO8x16: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveHI16x8: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveLO16x8: resRd = True; size = 1; break; -+//ZZ case Iop_InterleaveHI32x4: resRd = False; size = 2; break; -+//ZZ case Iop_InterleaveLO32x4: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, True)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_CatOddLanes8x16: -+//ZZ case Iop_CatEvenLanes8x16: -+//ZZ case Iop_CatOddLanes16x8: -+//ZZ case Iop_CatEvenLanes16x8: -+//ZZ case Iop_CatOddLanes32x4: -+//ZZ case Iop_CatEvenLanes32x4: { -+//ZZ HReg rD = newVRegV(env); -+//ZZ HReg rM = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CatOddLanes8x16: resRd = False; size = 0; break; -+//ZZ case Iop_CatEvenLanes8x16: resRd = True; size = 0; break; -+//ZZ case Iop_CatOddLanes16x8: resRd = False; size = 1; break; -+//ZZ case Iop_CatEvenLanes16x8: resRd = True; size = 1; break; -+//ZZ case Iop_CatOddLanes32x4: resRd = False; size = 2; break; -+//ZZ case Iop_CatEvenLanes32x4: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, True)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ case Iop_QAdd8Ux16: -+//ZZ case Iop_QAdd16Ux8: -+//ZZ case Iop_QAdd32Ux4: -+//ZZ case Iop_QAdd64Ux2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Ux16: size = 0; break; -+//ZZ case Iop_QAdd16Ux8: size = 1; break; -+//ZZ case Iop_QAdd32Ux4: size = 2; break; -+//ZZ case Iop_QAdd64Ux2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQADDU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QAdd8Sx16: -+//ZZ case Iop_QAdd16Sx8: -+//ZZ case Iop_QAdd32Sx4: -+//ZZ case Iop_QAdd64Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Sx16: size = 0; break; -+//ZZ case Iop_QAdd16Sx8: size = 1; break; -+//ZZ case Iop_QAdd32Sx4: size = 2; break; -+//ZZ case Iop_QAdd64Sx2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQADDS"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub8x16: -+//ZZ case Iop_Sub16x8: -+//ZZ case Iop_Sub32x4: -+//ZZ case Iop_Sub64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sub8x16: size = 0; break; -+//ZZ case Iop_Sub16x8: size = 1; break; -+//ZZ case Iop_Sub32x4: size = 2; break; -+//ZZ case Iop_Sub64x2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VSUB"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Ux16: -+//ZZ case Iop_QSub16Ux8: -+//ZZ case Iop_QSub32Ux4: -+//ZZ case Iop_QSub64Ux2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Ux16: size = 0; break; -+//ZZ case Iop_QSub16Ux8: size = 1; break; -+//ZZ case Iop_QSub32Ux4: size = 2; break; -+//ZZ case Iop_QSub64Ux2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQSUBU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Sx16: -+//ZZ case Iop_QSub16Sx8: -+//ZZ case Iop_QSub32Sx4: -+//ZZ case Iop_QSub64Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Sx16: size = 0; break; -+//ZZ case Iop_QSub16Sx8: size = 1; break; -+//ZZ case Iop_QSub32Sx4: size = 2; break; -+//ZZ case Iop_QSub64Sx2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQSUBS"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Ux16: -+//ZZ case Iop_Max16Ux8: -+//ZZ case Iop_Max32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Ux16: size = 0; break; -+//ZZ case Iop_Max16Ux8: size = 1; break; -+//ZZ case Iop_Max32Ux4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Sx16: -+//ZZ case Iop_Max16Sx8: -+//ZZ case Iop_Max32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Sx16: size = 0; break; -+//ZZ case Iop_Max16Sx8: size = 1; break; -+//ZZ case Iop_Max32Sx4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Ux16: -+//ZZ case Iop_Min16Ux8: -+//ZZ case Iop_Min32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Ux16: size = 0; break; -+//ZZ case Iop_Min16Ux8: size = 1; break; -+//ZZ case Iop_Min32Ux4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Sx16: -+//ZZ case Iop_Min16Sx8: -+//ZZ case Iop_Min32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Sx16: size = 0; break; -+//ZZ case Iop_Min16Sx8: size = 1; break; -+//ZZ case Iop_Min32Sx4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sar8x16: -+//ZZ case Iop_Sar16x8: -+//ZZ case Iop_Sar32x4: -+//ZZ case Iop_Sar64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegV(env); -+//ZZ HReg zero = newVRegV(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sar8x16: size = 0; break; -+//ZZ case Iop_Sar16x8: size = 1; break; -+//ZZ case Iop_Sar32x4: size = 2; break; -+//ZZ case Iop_Sar64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR2, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sal8x16: -+//ZZ case Iop_Sal16x8: -+//ZZ case Iop_Sal32x4: -+//ZZ case Iop_Sal64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sal8x16: size = 0; break; -+//ZZ case Iop_Sal16x8: size = 1; break; -+//ZZ case Iop_Sal32x4: size = 2; break; -+//ZZ case Iop_Sal64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shr8x16: -+//ZZ case Iop_Shr16x8: -+//ZZ case Iop_Shr32x4: -+//ZZ case Iop_Shr64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegV(env); -+//ZZ HReg zero = newVRegV(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shr8x16: size = 0; break; -+//ZZ case Iop_Shr16x8: size = 1; break; -+//ZZ case Iop_Shr32x4: size = 2; break; -+//ZZ case Iop_Shr64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR2, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shl8x16: -+//ZZ case Iop_Shl16x8: -+//ZZ case Iop_Shl32x4: -+//ZZ case Iop_Shl64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shl8x16: size = 0; break; -+//ZZ case Iop_Shl16x8: size = 1; break; -+//ZZ case Iop_Shl32x4: size = 2; break; -+//ZZ case Iop_Shl64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShl8x16: -+//ZZ case Iop_QShl16x8: -+//ZZ case Iop_QShl32x4: -+//ZZ case Iop_QShl64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShl8x16: size = 0; break; -+//ZZ case Iop_QShl16x8: size = 1; break; -+//ZZ case Iop_QShl32x4: size = 2; break; -+//ZZ case Iop_QShl64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSHL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSal8x16: -+//ZZ case Iop_QSal16x8: -+//ZZ case Iop_QSal32x4: -+//ZZ case Iop_QSal64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSal8x16: size = 0; break; -+//ZZ case Iop_QSal16x8: size = 1; break; -+//ZZ case Iop_QSal32x4: size = 2; break; -+//ZZ case Iop_QSal64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSAL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8x16: -+//ZZ case Iop_QShlN16x8: -+//ZZ case Iop_QShlN32x4: -+//ZZ case Iop_QShlN64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8x16: size = 8 | imm; break; -+//ZZ case Iop_QShlN16x8: size = 16 | imm; break; -+//ZZ case Iop_QShlN32x4: size = 32 | imm; break; -+//ZZ case Iop_QShlN64x2: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, -+//ZZ res, argL, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8Sx16: -+//ZZ case Iop_QShlN16Sx8: -+//ZZ case Iop_QShlN32Sx4: -+//ZZ case Iop_QShlN64Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNASxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8Sx16: size = 8 | imm; break; -+//ZZ case Iop_QShlN16Sx8: size = 16 | imm; break; -+//ZZ case Iop_QShlN32Sx4: size = 32 | imm; break; -+//ZZ case Iop_QShlN64Sx2: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, -+//ZZ res, argL, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSalN8x16: -+//ZZ case Iop_QSalN16x8: -+//ZZ case Iop_QSalN32x4: -+//ZZ case Iop_QSalN64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSalN8x16: size = 8 | imm; break; -+//ZZ case Iop_QSalN16x8: size = 16 | imm; break; -+//ZZ case Iop_QSalN32x4: size = 32 | imm; break; -+//ZZ case Iop_QSalN64x2: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, -+//ZZ res, argL, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_ShrN8x16: -+//ZZ case Iop_ShrN16x8: -+//ZZ case Iop_ShrN32x4: -+//ZZ case Iop_ShrN64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg tmp = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegI(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_ShrN8x16: size = 0; break; -+//ZZ case Iop_ShrN16x8: size = 1; break; -+//ZZ case Iop_ShrN32x4: size = 2; break; -+//ZZ case Iop_ShrN64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, -+//ZZ tmp, argR2, 0, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, tmp, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_ShlN8x16: -+//ZZ case Iop_ShlN16x8: -+//ZZ case Iop_ShlN32x4: -+//ZZ case Iop_ShlN64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg tmp = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_ShlN8x16: size = 0; break; -+//ZZ case Iop_ShlN16x8: size = 1; break; -+//ZZ case Iop_ShlN32x4: size = 2; break; -+//ZZ case Iop_ShlN64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, tmp, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_SarN8x16: -+//ZZ case Iop_SarN16x8: -+//ZZ case Iop_SarN32x4: -+//ZZ case Iop_SarN64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg tmp = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegI(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_SarN8x16: size = 0; break; -+//ZZ case Iop_SarN16x8: size = 1; break; -+//ZZ case Iop_SarN32x4: size = 2; break; -+//ZZ case Iop_SarN64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, tmp, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT8Ux16: -+//ZZ case Iop_CmpGT16Ux8: -+//ZZ case Iop_CmpGT32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Ux16: size = 0; break; -+//ZZ case Iop_CmpGT16Ux8: size = 1; break; -+//ZZ case Iop_CmpGT32Ux4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT8Sx16: -+//ZZ case Iop_CmpGT16Sx8: -+//ZZ case Iop_CmpGT32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Sx16: size = 0; break; -+//ZZ case Iop_CmpGT16Sx8: size = 1; break; -+//ZZ case Iop_CmpGT32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ8x16: -+//ZZ case Iop_CmpEQ16x8: -+//ZZ case Iop_CmpEQ32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpEQ8x16: size = 0; break; -+//ZZ case Iop_CmpEQ16x8: size = 1; break; -+//ZZ case Iop_CmpEQ32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul8x16: -+//ZZ case Iop_Mul16x8: -+//ZZ case Iop_Mul32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mul8x16: size = 0; break; -+//ZZ case Iop_Mul16x8: size = 1; break; -+//ZZ case Iop_Mul32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMUL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mull8Ux8: -+//ZZ case Iop_Mull16Ux4: -+//ZZ case Iop_Mull32Ux2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mull8Ux8: size = 0; break; -+//ZZ case Iop_Mull16Ux4: size = 1; break; -+//ZZ case Iop_Mull32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULLU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_Mull8Sx8: -+//ZZ case Iop_Mull16Sx4: -+//ZZ case Iop_Mull32Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mull8Sx8: size = 0; break; -+//ZZ case Iop_Mull16Sx4: size = 1; break; -+//ZZ case Iop_Mull32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULLS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QDMulHi16Sx8: -+//ZZ case Iop_QDMulHi32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QDMulHi16Sx8: size = 1; break; -+//ZZ case Iop_QDMulHi32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QRDMulHi16Sx8: -+//ZZ case Iop_QRDMulHi32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QRDMulHi16Sx8: size = 1; break; -+//ZZ case Iop_QRDMulHi32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QDMulLong16Sx4: -+//ZZ case Iop_QDMulLong32Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QDMulLong16Sx4: size = 1; break; -+//ZZ case Iop_QDMulLong32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PolynomialMul8x16: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGE32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_PolynomialMull8x8: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULLP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F32ToFixed32Ux4_RZ: -+//ZZ case Iop_F32ToFixed32Sx4_RZ: -+//ZZ case Iop_Fixed32UToF32x4_RN: -+//ZZ case Iop_Fixed32SToF32x4_RN: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ ARMNeonUnOp op; -+//ZZ UInt imm6; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports FP <-> Fixed conversion with constant " -+//ZZ "second argument less than 33 only\n"); -+//ZZ } -+//ZZ imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ vassert(imm6 <= 32 && imm6 > 0); -+//ZZ imm6 = 64 - imm6; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_F32ToFixed32Ux4_RZ: op = ARMneon_VCVTFtoFixedU; break; -+//ZZ case Iop_F32ToFixed32Sx4_RZ: op = ARMneon_VCVTFtoFixedS; break; -+//ZZ case Iop_Fixed32UToF32x4_RN: op = ARMneon_VCVTFixedUtoF; break; -+//ZZ case Iop_Fixed32SToF32x4_RN: op = ARMneon_VCVTFixedStoF; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True)); -+//ZZ return res; -+//ZZ } -+//ZZ /* -+//ZZ FIXME remove if not used -+//ZZ case Iop_VDup8x16: -+//ZZ case Iop_VDup16x8: -+//ZZ case Iop_VDup32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt imm4; -+//ZZ UInt index; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_VDup8x16: imm4 = (index << 1) + 1; break; -+//ZZ case Iop_VDup16x8: imm4 = (index << 2) + 2; break; -+//ZZ case Iop_VDup32x4: imm4 = (index << 3) + 4; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ if (imm4 >= 16) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VDUP, -+//ZZ res, argL, imm4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ */ -+//ZZ case Iop_PwAdd8x16: -+//ZZ case Iop_PwAdd16x8: -+//ZZ case Iop_PwAdd32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAdd8x16: size = 0; break; -+//ZZ case Iop_PwAdd16x8: size = 1; break; -+//ZZ case Iop_PwAdd32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPADD, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+ /* ... */ -+ default: -+ break; -+ } /* switch on the binop */ -+ } /* if (e->tag == Iex_Binop) */ -+ -+//ZZ if (e->tag == Iex_Triop) { -+//ZZ IRTriop *triop = e->Iex.Triop.details; -+//ZZ -+//ZZ switch (triop->op) { -+//ZZ case Iop_ExtractV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, triop->arg1); -+//ZZ HReg argR = iselNeonExpr(env, triop->arg2); -+//ZZ UInt imm4; -+//ZZ if (triop->arg3->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) { -+//ZZ vpanic("ARM target supports Iop_ExtractV128 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ imm4 = triop->arg3->Iex.Const.con->Ico.U8; -+//ZZ if (imm4 >= 16) { -+//ZZ vpanic("ARM target supports Iop_ExtractV128 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VEXT, -+//ZZ res, argL, argR, imm4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ ARMCondCode cc; -+//ZZ HReg r1 = iselNeonExpr(env, e->Iex.ITE.iftrue); -+//ZZ HReg r0 = iselNeonExpr(env, e->Iex.ITE.iffalse); -+//ZZ HReg dst = newVRegV(env); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, r1, 4, True)); -+//ZZ cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_NCMovQ(cc ^ 1, dst, r0)); -+//ZZ return dst; -+//ZZ } -+ -+ v128_expr_bad: -+ ppIRExpr(e); -+ vpanic("iselV128Expr_wrk"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Floating point expressions (64 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Compute a 64-bit floating point value into a register, the identity -+ of which is returned. As with iselIntExpr_R, the reg may be either -+ real or virtual; in any case it must not be changed by subsequent -+ code emitted by the caller. */ -+ -+static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselDblExpr_wrk( env, e ); -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(r) == HRcFlt64); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY */ -+static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(e); -+ vassert(ty == Ity_F64); -+ -+ if (e->tag == Iex_RdTmp) { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ if (e->tag == Iex_Const) { -+ IRConst* con = e->Iex.Const.con; -+ if (con->tag == Ico_F64i) { -+ HReg src = newVRegI(env); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_Imm64(src, con->Ico.F64i)); -+ addInstr(env, ARM64Instr_VDfromX(dst, src)); -+ return dst; -+ } -+ } -+ -+ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+ vassert(e->Iex.Load.ty == Ity_F64); -+ HReg addr = iselIntExpr_R(env, e->Iex.Load.addr); -+ HReg res = newVRegD(env); -+ addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, res, addr, 0)); -+ return res; -+ } -+ -+ if (e->tag == Iex_Get) { -+ Int offs = e->Iex.Get.offset; -+ if (offs >= 0 && offs < 32768 && 0 == (offs & 7)) { -+ HReg rD = newVRegD(env); -+ HReg rN = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, rD, rN, offs)); -+ return rD; -+ } -+ } -+ -+ if (e->tag == Iex_Unop) { -+ switch (e->Iex.Unop.op) { -+//ZZ case Iop_ReinterpI64asF64: { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ return iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ } else { -+//ZZ HReg srcHi, srcLo; -+//ZZ HReg dst = newVRegD(env); -+//ZZ iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo)); -+//ZZ return dst; -+//ZZ } -+//ZZ } -+ case Iop_NegF64: { -+ HReg src = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_NEG, dst, src)); -+ return dst; -+ } -+ case Iop_AbsF64: { -+ HReg src = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_ABS, dst, src)); -+ return dst; -+ } -+ case Iop_F32toF64: { -+ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtSD(True/*sToD*/, dst, src)); -+ return dst; -+ } -+ case Iop_I32UtoF64: -+ case Iop_I32StoF64: { -+ /* Rounding mode is not involved here, since the -+ conversion can always be done without loss of -+ precision. */ -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ Bool syned = e->Iex.Unop.op == Iop_I32StoF64; -+ ARM64CvtOp cvt_op = syned ? ARM64cvt_F64_I32S : ARM64cvt_F64_I32U; -+ addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dst, src)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ case Iop_RoundF64toInt: { -+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_RINT, dst, src)); -+ return dst; -+ } -+ case Iop_SqrtF64: { -+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_SQRT, dst, src)); -+ return dst; -+ } -+ case Iop_I64StoF64: -+ case Iop_I64UtoF64: { -+ ARM64CvtOp cvt_op = e->Iex.Binop.op == Iop_I64StoF64 -+ ? ARM64cvt_F64_I64S : ARM64cvt_F64_I64U; -+ HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ HReg dstS = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dstS, srcI)); -+ return dstS; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Triop) { -+ IRTriop* triop = e->Iex.Triop.details; -+ ARM64FpBinOp dblop = ARM64fpb_INVALID; -+ switch (triop->op) { -+ case Iop_DivF64: dblop = ARM64fpb_DIV; break; -+ case Iop_MulF64: dblop = ARM64fpb_MUL; break; -+ case Iop_SubF64: dblop = ARM64fpb_SUB; break; -+ case Iop_AddF64: dblop = ARM64fpb_ADD; break; -+ default: break; -+ } -+ if (dblop != ARM64fpb_INVALID) { -+ HReg argL = iselDblExpr(env, triop->arg2); -+ HReg argR = iselDblExpr(env, triop->arg3); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, triop->arg1); -+ addInstr(env, ARM64Instr_VBinD(dblop, dst, argL, argR)); -+ return dst; -+ } -+ } -+ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ if (ty == Ity_F64 -+//ZZ && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) { -+//ZZ HReg r1 = iselDblExpr(env, e->Iex.ITE.iftrue); -+//ZZ HReg r0 = iselDblExpr(env, e->Iex.ITE.iffalse); -+//ZZ HReg dst = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, r1)); -+//ZZ ARMCondCode cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_VCMovD(cc ^ 1, dst, r0)); -+//ZZ return dst; -+//ZZ } -+//ZZ } -+ -+ ppIRExpr(e); -+ vpanic("iselDblExpr_wrk"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Floating point expressions (32 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Compute a 32-bit floating point value into a register, the identity -+ of which is returned. As with iselIntExpr_R, the reg may be either -+ real or virtual; in any case it must not be changed by subsequent -+ code emitted by the caller. Values are generated into HRcFlt64 -+ registers despite the values themselves being Ity_F32s. */ -+ -+static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselFltExpr_wrk( env, e ); -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(r) == HRcFlt64); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY */ -+static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(e); -+ vassert(ty == Ity_F32); -+ -+ if (e->tag == Iex_RdTmp) { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ if (e->tag == Iex_Const) { -+ /* This is something of a kludge. Since a 32 bit floating point -+ zero is just .. all zeroes, just create a 64 bit zero word -+ and transfer it. This avoids having to create a SfromW -+ instruction for this specific case. */ -+ IRConst* con = e->Iex.Const.con; -+ if (con->tag == Ico_F32i && con->Ico.F32i == 0) { -+ HReg src = newVRegI(env); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_Imm64(src, 0)); -+ addInstr(env, ARM64Instr_VDfromX(dst, src)); -+ return dst; -+ } -+ } -+ -+//ZZ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+//ZZ ARMAModeV* am; -+//ZZ HReg res = newVRegF(env); -+//ZZ vassert(e->Iex.Load.ty == Ity_F32); -+//ZZ am = iselIntExpr_AModeV(env, e->Iex.Load.addr); -+//ZZ addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am)); -+//ZZ return res; -+//ZZ } -+ -+ if (e->tag == Iex_Get) { -+ Int offs = e->Iex.Get.offset; -+ if (offs >= 0 && offs < 16384 && 0 == (offs & 3)) { -+ HReg rD = newVRegD(env); -+ HReg rN = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStS(True/*isLoad*/, rD, rN, offs)); -+ return rD; -+ } -+ } -+ -+ if (e->tag == Iex_Unop) { -+ switch (e->Iex.Unop.op) { -+//ZZ case Iop_ReinterpI32asF32: { -+//ZZ HReg dst = newVRegF(env); -+//ZZ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src)); -+//ZZ return dst; -+//ZZ } -+ case Iop_NegF32: { -+ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_NEG, dst, src)); -+ return dst; -+ } -+ case Iop_AbsF32: { -+ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_ABS, dst, src)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ case Iop_RoundF32toInt: { -+ HReg src = iselFltExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_RINT, dst, src)); -+ return dst; -+ } -+ case Iop_SqrtF32: { -+ HReg src = iselFltExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_SQRT, dst, src)); -+ return dst; -+ } -+ case Iop_F64toF32: { -+ HReg srcD = iselDblExpr(env, e->Iex.Binop.arg2); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ HReg dstS = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtSD(False/*dToS*/, dstS, srcD)); -+ return dstS; -+ } -+ case Iop_I32StoF32: -+ case Iop_I64UtoF32: -+ case Iop_I64StoF32: { -+ ARM64CvtOp cvt_op = ARM64cvt_INVALID; -+ switch (e->Iex.Binop.op) { -+ case Iop_I32StoF32: cvt_op = ARM64cvt_F32_I32S; break; -+ case Iop_I64UtoF32: cvt_op = ARM64cvt_F32_I64U; break; -+ case Iop_I64StoF32: cvt_op = ARM64cvt_F32_I64S; break; -+ default: vassert(0); -+ } -+ HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ HReg dstS = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dstS, srcI)); -+ return dstS; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Triop) { -+ IRTriop* triop = e->Iex.Triop.details; -+ ARM64FpBinOp sglop = ARM64fpb_INVALID; -+ switch (triop->op) { -+ case Iop_DivF32: sglop = ARM64fpb_DIV; break; -+ case Iop_MulF32: sglop = ARM64fpb_MUL; break; -+ case Iop_SubF32: sglop = ARM64fpb_SUB; break; -+ case Iop_AddF32: sglop = ARM64fpb_ADD; break; -+ default: break; -+ } -+ if (sglop != ARM64fpb_INVALID) { -+ HReg argL = iselFltExpr(env, triop->arg2); -+ HReg argR = iselFltExpr(env, triop->arg3); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, triop->arg1); -+ addInstr(env, ARM64Instr_VBinS(sglop, dst, argL, argR)); -+ return dst; -+ } -+ } -+ -+//ZZ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ if (ty == Ity_F32 -+//ZZ && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) { -+//ZZ ARMCondCode cc; -+//ZZ HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue); -+//ZZ HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse); -+//ZZ HReg dst = newVRegF(env); -+//ZZ addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, r1)); -+//ZZ cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_VCMovS(cc ^ 1, dst, r0)); -+//ZZ return dst; -+//ZZ } -+//ZZ } -+ -+ ppIRExpr(e); -+ vpanic("iselFltExpr_wrk"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Statements ---*/ -+/*---------------------------------------------------------*/ -+ -+static void iselStmt ( ISelEnv* env, IRStmt* stmt ) -+{ -+ if (vex_traceflags & VEX_TRACE_VCODE) { -+ vex_printf("\n-- "); -+ ppIRStmt(stmt); -+ vex_printf("\n"); -+ } -+ switch (stmt->tag) { -+ -+ /* --------- STORE --------- */ -+ /* little-endian write to memory */ -+ case Ist_Store: { -+ IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); -+ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); -+ IREndness end = stmt->Ist.Store.end; -+ -+ if (tya != Ity_I64 || end != Iend_LE) -+ goto stmt_fail; -+ -+ if (tyd == Ity_I64) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt64(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I32) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt32(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I16) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt16(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I8) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt8(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_V128) { -+ HReg qD = iselV128Expr(env, stmt->Ist.Store.data); -+ HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr); -+ addInstr(env, ARM64Instr_VLdStQ(False/*!isLoad*/, qD, addr)); -+ return; -+ } -+ if (tyd == Ity_F64) { -+ HReg dD = iselDblExpr(env, stmt->Ist.Store.data); -+ HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr); -+ addInstr(env, ARM64Instr_VLdStD(False/*!isLoad*/, dD, addr, 0)); -+ return; -+ } -+ -+//ZZ if (tyd == Ity_I16) { -+//ZZ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+//ZZ ARMAMode2* am = iselIntExpr_AMode2(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_LdSt16(ARMcc_AL, -+//ZZ False/*!isLoad*/, -+//ZZ False/*!isSignedLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_I8) { -+//ZZ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+//ZZ ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_LdSt8U(ARMcc_AL, False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_I64) { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_NLdStD(False, dD, am)); -+//ZZ } else { -+//ZZ HReg rDhi, rDlo, rA; -+//ZZ iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data); -+//ZZ rA = iselIntExpr_R(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDhi, -+//ZZ ARMAMode1_RI(rA,4))); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDlo, -+//ZZ ARMAMode1_RI(rA,0))); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F64) { -+//ZZ HReg dD = iselDblExpr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, dD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F32) { -+//ZZ HReg fD = iselFltExpr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_V128) { -+//ZZ HReg qD = iselNeonExpr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_NLdStQ(False, qD, am)); -+//ZZ return; -+//ZZ } -+ -+ break; -+ } -+ -+//ZZ /* --------- CONDITIONAL STORE --------- */ -+//ZZ /* conditional little-endian write to memory */ -+//ZZ case Ist_StoreG: { -+//ZZ IRStoreG* sg = stmt->Ist.StoreG.details; -+//ZZ IRType tya = typeOfIRExpr(env->type_env, sg->addr); -+//ZZ IRType tyd = typeOfIRExpr(env->type_env, sg->data); -+//ZZ IREndness end = sg->end; -+//ZZ -+//ZZ if (tya != Ity_I32 || end != Iend_LE) -+//ZZ goto stmt_fail; -+//ZZ -+//ZZ switch (tyd) { -+//ZZ case Ity_I8: -+//ZZ case Ity_I32: { -+//ZZ HReg rD = iselIntExpr_R(env, sg->data); -+//ZZ ARMAMode1* am = iselIntExpr_AMode1(env, sg->addr); -+//ZZ ARMCondCode cc = iselCondCode(env, sg->guard); -+//ZZ addInstr(env, (tyd == Ity_I32 ? ARMInstr_LdSt32 : ARMInstr_LdSt8U) -+//ZZ (cc, False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ case Ity_I16: { -+//ZZ HReg rD = iselIntExpr_R(env, sg->data); -+//ZZ ARMAMode2* am = iselIntExpr_AMode2(env, sg->addr); -+//ZZ ARMCondCode cc = iselCondCode(env, sg->guard); -+//ZZ addInstr(env, ARMInstr_LdSt16(cc, -+//ZZ False/*!isLoad*/, -+//ZZ False/*!isSignedLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ break; -+//ZZ } -+//ZZ -+//ZZ /* --------- CONDITIONAL LOAD --------- */ -+//ZZ /* conditional little-endian load from memory */ -+//ZZ case Ist_LoadG: { -+//ZZ IRLoadG* lg = stmt->Ist.LoadG.details; -+//ZZ IRType tya = typeOfIRExpr(env->type_env, lg->addr); -+//ZZ IREndness end = lg->end; -+//ZZ -+//ZZ if (tya != Ity_I32 || end != Iend_LE) -+//ZZ goto stmt_fail; -+//ZZ -+//ZZ switch (lg->cvt) { -+//ZZ case ILGop_8Uto32: -+//ZZ case ILGop_Ident32: { -+//ZZ HReg rAlt = iselIntExpr_R(env, lg->alt); -+//ZZ ARMAMode1* am = iselIntExpr_AMode1(env, lg->addr); -+//ZZ HReg rD = lookupIRTemp(env, lg->dst); -+//ZZ addInstr(env, mk_iMOVds_RR(rD, rAlt)); -+//ZZ ARMCondCode cc = iselCondCode(env, lg->guard); -+//ZZ addInstr(env, (lg->cvt == ILGop_Ident32 ? ARMInstr_LdSt32 -+//ZZ : ARMInstr_LdSt8U) -+//ZZ (cc, True/*isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ case ILGop_16Sto32: -+//ZZ case ILGop_16Uto32: -+//ZZ case ILGop_8Sto32: { -+//ZZ HReg rAlt = iselIntExpr_R(env, lg->alt); -+//ZZ ARMAMode2* am = iselIntExpr_AMode2(env, lg->addr); -+//ZZ HReg rD = lookupIRTemp(env, lg->dst); -+//ZZ addInstr(env, mk_iMOVds_RR(rD, rAlt)); -+//ZZ ARMCondCode cc = iselCondCode(env, lg->guard); -+//ZZ if (lg->cvt == ILGop_8Sto32) { -+//ZZ addInstr(env, ARMInstr_Ld8S(cc, rD, am)); -+//ZZ } else { -+//ZZ vassert(lg->cvt == ILGop_16Sto32 || lg->cvt == ILGop_16Uto32); -+//ZZ Bool sx = lg->cvt == ILGop_16Sto32; -+//ZZ addInstr(env, ARMInstr_LdSt16(cc, True/*isLoad*/, sx, rD, am)); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ break; -+//ZZ } -+ -+ /* --------- PUT --------- */ -+ /* write guest state, fixed offset */ -+ case Ist_Put: { -+ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Put.data); -+ UInt offs = (UInt)stmt->Ist.Put.offset; -+ if (tyd == Ity_I64 && 0 == (offs & 7) && offs < (8<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_64bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt64(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I32 && 0 == (offs & 3) && offs < (4<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_32bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt32(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I16 && 0 == (offs & 1) && offs < (2<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_16bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt16(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I8 && offs < (1<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_8bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt8(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_V128 && offs < (1<<12)) { -+ HReg qD = iselV128Expr(env, stmt->Ist.Put.data); -+ HReg addr = mk_baseblock_128bit_access_addr(env, offs); -+ addInstr(env, ARM64Instr_VLdStQ(False/*!isLoad*/, qD, addr)); -+ return; -+ } -+ if (tyd == Ity_F64 && 0 == (offs & 7) && offs < (8<<12)) { -+ HReg dD = iselDblExpr(env, stmt->Ist.Put.data); -+ HReg bbp = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStD(False/*!isLoad*/, dD, bbp, offs)); -+ return; -+ } -+ if (tyd == Ity_F32 && 0 == (offs & 3) && offs < (4<<12)) { -+ HReg dD = iselFltExpr(env, stmt->Ist.Put.data); -+ HReg bbp = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStS(False/*!isLoad*/, dD, bbp, offs)); -+ return; -+ } -+ -+//ZZ if (tyd == Ity_I64) { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg addr = newVRegI(env); -+//ZZ HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), -+//ZZ stmt->Ist.Put.offset)); -+//ZZ addInstr(env, ARMInstr_NLdStD(False, qD, mkARMAModeN_R(addr))); -+//ZZ } else { -+//ZZ HReg rDhi, rDlo; -+//ZZ ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), -+//ZZ stmt->Ist.Put.offset + 0); -+//ZZ ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), -+//ZZ stmt->Ist.Put.offset + 4); -+//ZZ iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, -+//ZZ rDhi, am4)); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, -+//ZZ rDlo, am0)); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F64) { -+//ZZ // XXX This won't work if offset > 1020 or is not 0 % 4. -+//ZZ // In which case we'll have to generate more longwinded code. -+//ZZ ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset); -+//ZZ HReg rD = iselDblExpr(env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F32) { -+//ZZ // XXX This won't work if offset > 1020 or is not 0 % 4. -+//ZZ // In which case we'll have to generate more longwinded code. -+//ZZ ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset); -+//ZZ HReg rD = iselFltExpr(env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+ break; -+ } -+ -+ /* --------- TMP --------- */ -+ /* assign value to temporary */ -+ case Ist_WrTmp: { -+ IRTemp tmp = stmt->Ist.WrTmp.tmp; -+ IRType ty = typeOfIRTemp(env->type_env, tmp); -+ -+ if (ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8) { -+ /* We could do a lot better here. But for the time being: */ -+ HReg dst = lookupIRTemp(env, tmp); -+ HReg rD = iselIntExpr_R(env, stmt->Ist.WrTmp.data); -+ addInstr(env, ARM64Instr_MovI(dst, rD)); -+ return; -+ } -+ if (ty == Ity_I1) { -+ /* Here, we are generating a I1 value into a 64 bit register. -+ Make sure the value in the register is only zero or one, -+ but no other. This allows optimisation of the -+ 1Uto64(tmp:I1) case, by making it simply a copy of the -+ register holding 'tmp'. The point being that the value in -+ the register holding 'tmp' can only have been created -+ here. LATER: that seems dangerous; safer to do 'tmp & 1' -+ in that case. Also, could do this just with a single CINC -+ insn. */ -+ HReg zero = newVRegI(env); -+ HReg one = newVRegI(env); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_Imm64(zero, 0)); -+ addInstr(env, ARM64Instr_Imm64(one, 1)); -+ ARM64CondCode cc = iselCondCode(env, stmt->Ist.WrTmp.data); -+ addInstr(env, ARM64Instr_CSel(dst, one, zero, cc)); -+ return; -+ } -+ if (ty == Ity_F64) { -+ HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_VMov(8, dst, src)); -+ return; -+ } -+ if (ty == Ity_F32) { -+ HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_VMov(8/*yes, really*/, dst, src)); -+ return; -+ } -+ if (ty == Ity_V128) { -+ HReg src = iselV128Expr(env, stmt->Ist.WrTmp.data); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_VMov(16, dst, src)); -+ return; -+ } -+ break; -+ } -+ -+ /* --------- Call to DIRTY helper --------- */ -+ /* call complex ("dirty") helper function */ -+ case Ist_Dirty: { -+ IRDirty* d = stmt->Ist.Dirty.details; -+ -+ /* Figure out the return type, if any. */ -+ IRType retty = Ity_INVALID; -+ if (d->tmp != IRTemp_INVALID) -+ retty = typeOfIRTemp(env->type_env, d->tmp); -+ -+ Bool retty_ok = False; -+ switch (retty) { -+ case Ity_INVALID: /* function doesn't return anything */ -+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: -+ case Ity_V128: -+ retty_ok = True; break; -+ default: -+ break; -+ } -+ if (!retty_ok) -+ break; /* will go to stmt_fail: */ -+ -+ /* Marshal args, do the call, and set the return value to 0x555..555 -+ if this is a conditional call that returns a value and the -+ call is skipped. */ -+ UInt addToSp = 0; -+ RetLoc rloc = mk_RetLoc_INVALID(); -+ doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args ); -+ vassert(is_sane_RetLoc(rloc)); -+ -+ /* Now figure out what to do with the returned value, if any. */ -+ switch (retty) { -+ case Ity_INVALID: { -+ /* No return value. Nothing to do. */ -+ vassert(d->tmp == IRTemp_INVALID); -+ vassert(rloc.pri == RLPri_None); -+ vassert(addToSp == 0); -+ return; -+ } -+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: { -+ vassert(rloc.pri == RLPri_Int); -+ vassert(addToSp == 0); -+ /* The returned value is in x0. Park it in the register -+ associated with tmp. */ -+ HReg dst = lookupIRTemp(env, d->tmp); -+ addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0()) ); -+ return; -+ } -+ case Ity_V128: { -+ /* The returned value is on the stack, and *retloc tells -+ us where. Fish it off the stack and then move the -+ stack pointer upwards to clear it, as directed by -+ doHelperCall. */ -+ vassert(rloc.pri == RLPri_V128SpRel); -+ vassert(rloc.spOff < 256); // stay sane -+ vassert(addToSp >= 16); // ditto -+ vassert(addToSp < 256); // ditto -+ HReg dst = lookupIRTemp(env, d->tmp); -+ HReg tmp = newVRegI(env); // the address of the returned value -+ addInstr(env, ARM64Instr_FromSP(tmp)); // tmp = SP -+ addInstr(env, ARM64Instr_Arith(tmp, tmp, -+ ARM64RIA_I12((UShort)rloc.spOff, 0), -+ True/*isAdd*/ )); -+ addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, dst, tmp)); -+ addInstr(env, ARM64Instr_AddToSP(addToSp)); -+ return; -+ } -+ default: -+ /*NOTREACHED*/ -+ vassert(0); -+ } -+ break; -+ } -+ -+//ZZ /* --------- Load Linked and Store Conditional --------- */ -+//ZZ case Ist_LLSC: { -+//ZZ if (stmt->Ist.LLSC.storedata == NULL) { -+//ZZ /* LL */ -+//ZZ IRTemp res = stmt->Ist.LLSC.result; -+//ZZ IRType ty = typeOfIRTemp(env->type_env, res); -+//ZZ if (ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8) { -+//ZZ Int szB = 0; -+//ZZ HReg r_dst = lookupIRTemp(env, res); -+//ZZ HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr); -+//ZZ switch (ty) { -+//ZZ case Ity_I8: szB = 1; break; -+//ZZ case Ity_I16: szB = 2; break; -+//ZZ case Ity_I32: szB = 4; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R4(), raddr)); -+//ZZ addInstr(env, ARMInstr_LdrEX(szB)); -+//ZZ addInstr(env, mk_iMOVds_RR(r_dst, hregARM_R2())); -+//ZZ return; -+//ZZ } -+//ZZ if (ty == Ity_I64) { -+//ZZ HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R4(), raddr)); -+//ZZ addInstr(env, ARMInstr_LdrEX(8)); -+//ZZ /* Result is in r3:r2. On a non-NEON capable CPU, we must -+//ZZ move it into a result register pair. On a NEON capable -+//ZZ CPU, the result register will be a 64 bit NEON -+//ZZ register, so we must move it there instead. */ -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg dst = lookupIRTemp(env, res); -+//ZZ addInstr(env, ARMInstr_VXferD(True, dst, hregARM_R3(), -+//ZZ hregARM_R2())); -+//ZZ } else { -+//ZZ HReg r_dst_hi, r_dst_lo; -+//ZZ lookupIRTemp64(&r_dst_hi, &r_dst_lo, env, res); -+//ZZ addInstr(env, mk_iMOVds_RR(r_dst_lo, hregARM_R2())); -+//ZZ addInstr(env, mk_iMOVds_RR(r_dst_hi, hregARM_R3())); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ /*NOTREACHED*/ -+//ZZ vassert(0); -+//ZZ } else { -+//ZZ /* SC */ -+//ZZ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.storedata); -+//ZZ if (tyd == Ity_I32 || tyd == Ity_I16 || tyd == Ity_I8) { -+//ZZ Int szB = 0; -+//ZZ HReg rD = iselIntExpr_R(env, stmt->Ist.LLSC.storedata); -+//ZZ HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr); -+//ZZ switch (tyd) { -+//ZZ case Ity_I8: szB = 1; break; -+//ZZ case Ity_I16: szB = 2; break; -+//ZZ case Ity_I32: szB = 4; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R2(), rD)); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R4(), rA)); -+//ZZ addInstr(env, ARMInstr_StrEX(szB)); -+//ZZ } else { -+//ZZ vassert(tyd == Ity_I64); -+//ZZ /* This is really ugly. There is no is/is-not NEON -+//ZZ decision akin to the case for LL, because iselInt64Expr -+//ZZ fudges this for us, and always gets the result into two -+//ZZ GPRs even if this means moving it from a NEON -+//ZZ register. */ -+//ZZ HReg rDhi, rDlo; -+//ZZ iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.LLSC.storedata); -+//ZZ HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R2(), rDlo)); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R3(), rDhi)); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R4(), rA)); -+//ZZ addInstr(env, ARMInstr_StrEX(8)); -+//ZZ } -+//ZZ /* now r0 is 1 if failed, 0 if success. Change to IR -+//ZZ conventions (0 is fail, 1 is success). Also transfer -+//ZZ result to r_res. */ -+//ZZ IRTemp res = stmt->Ist.LLSC.result; -+//ZZ IRType ty = typeOfIRTemp(env->type_env, res); -+//ZZ HReg r_res = lookupIRTemp(env, res); -+//ZZ ARMRI84* one = ARMRI84_I84(1,0); -+//ZZ vassert(ty == Ity_I1); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_XOR, r_res, hregARM_R0(), one)); -+//ZZ /* And be conservative -- mask off all but the lowest bit */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_AND, r_res, r_res, one)); -+//ZZ return; -+//ZZ } -+//ZZ break; -+//ZZ } -+//ZZ -+//ZZ /* --------- MEM FENCE --------- */ -+//ZZ case Ist_MBE: -+//ZZ switch (stmt->Ist.MBE.event) { -+//ZZ case Imbe_Fence: -+//ZZ addInstr(env, ARMInstr_MFence()); -+//ZZ return; -+//ZZ case Imbe_CancelReservation: -+//ZZ addInstr(env, ARMInstr_CLREX()); -+//ZZ return; -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ break; -+ -+ /* --------- INSTR MARK --------- */ -+ /* Doesn't generate any executable code ... */ -+ case Ist_IMark: -+ return; -+ -+ /* --------- NO-OP --------- */ -+ case Ist_NoOp: -+ return; -+ -+ /* --------- EXIT --------- */ -+ case Ist_Exit: { -+ if (stmt->Ist.Exit.dst->tag != Ico_U64) -+ vpanic("isel_arm: Ist_Exit: dst is not a 64-bit value"); -+ -+ ARM64CondCode cc -+ = iselCondCode(env, stmt->Ist.Exit.guard); -+ ARM64AMode* amPC -+ = mk_baseblock_64bit_access_amode(stmt->Ist.Exit.offsIP); -+ -+ -+ /* Case: boring transfer to known address */ -+ if (stmt->Ist.Exit.jk == Ijk_Boring -+ /*ATC || stmt->Ist.Exit.jk == Ijk_Call */ -+ /*ATC || stmt->Ist.Exit.jk == Ijk_Ret */ ) { -+ if (env->chainingAllowed) { -+ /* .. almost always true .. */ -+ /* Skip the event check at the dst if this is a forwards -+ edge. */ -+ Bool toFastEP -+ = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga; -+ if (0) vex_printf("%s", toFastEP ? "Y" : ","); -+ addInstr(env, ARM64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64, -+ amPC, cc, toFastEP)); -+ } else { -+ /* .. very occasionally .. */ -+ /* We can't use chaining, so ask for an assisted transfer, -+ as that's the only alternative that is allowable. */ -+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, cc, Ijk_Boring)); -+ } -+ return; -+ } -+ -+//ZZ /* Case: assisted transfer to arbitrary address */ -+//ZZ switch (stmt->Ist.Exit.jk) { -+//ZZ /* Keep this list in sync with that in iselNext below */ -+//ZZ case Ijk_ClientReq: -+//ZZ case Ijk_NoDecode: -+//ZZ case Ijk_NoRedir: -+//ZZ case Ijk_Sys_syscall: -+//ZZ case Ijk_TInval: -+//ZZ case Ijk_Yield: -+//ZZ { -+//ZZ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -+//ZZ addInstr(env, ARMInstr_XAssisted(r, amR15T, cc, -+//ZZ stmt->Ist.Exit.jk)); -+//ZZ return; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+ -+ /* Do we ever expect to see any other kind? */ -+ goto stmt_fail; -+ } -+ -+ default: break; -+ } -+ stmt_fail: -+ ppIRStmt(stmt); -+ vpanic("iselStmt"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Basic block terminators (Nexts) ---*/ -+/*---------------------------------------------------------*/ -+ -+static void iselNext ( ISelEnv* env, -+ IRExpr* next, IRJumpKind jk, Int offsIP ) -+{ -+ if (vex_traceflags & VEX_TRACE_VCODE) { -+ vex_printf( "\n-- PUT(%d) = ", offsIP); -+ ppIRExpr( next ); -+ vex_printf( "; exit-"); -+ ppIRJumpKind(jk); -+ vex_printf( "\n"); -+ } -+ -+ /* Case: boring transfer to known address */ -+ if (next->tag == Iex_Const) { -+ IRConst* cdst = next->Iex.Const.con; -+ vassert(cdst->tag == Ico_U64); -+ if (jk == Ijk_Boring || jk == Ijk_Call) { -+ /* Boring transfer to known address */ -+ ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP); -+ if (env->chainingAllowed) { -+ /* .. almost always true .. */ -+ /* Skip the event check at the dst if this is a forwards -+ edge. */ -+ Bool toFastEP -+ = ((Addr64)cdst->Ico.U64) > env->max_ga; -+ if (0) vex_printf("%s", toFastEP ? "X" : "."); -+ addInstr(env, ARM64Instr_XDirect(cdst->Ico.U64, -+ amPC, ARM64cc_AL, -+ toFastEP)); -+ } else { -+ /* .. very occasionally .. */ -+ /* We can't use chaining, so ask for an assisted transfer, -+ as that's the only alternative that is allowable. */ -+ HReg r = iselIntExpr_R(env, next); -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, -+ Ijk_Boring)); -+ } -+ return; -+ } -+ } -+ -+ /* Case: call/return (==boring) transfer to any address */ -+ switch (jk) { -+ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: { -+ HReg r = iselIntExpr_R(env, next); -+ ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP); -+ if (env->chainingAllowed) { -+ addInstr(env, ARM64Instr_XIndir(r, amPC, ARM64cc_AL)); -+ } else { -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, -+ Ijk_Boring)); -+ } -+ return; -+ } -+ default: -+ break; -+ } -+ -+ /* Case: assisted transfer to arbitrary address */ -+ switch (jk) { -+ /* Keep this list in sync with that for Ist_Exit above */ -+ case Ijk_ClientReq: -+ case Ijk_NoDecode: -+//ZZ case Ijk_NoRedir: -+ case Ijk_Sys_syscall: -+//ZZ case Ijk_TInval: -+//ZZ case Ijk_Yield: -+ { -+ HReg r = iselIntExpr_R(env, next); -+ ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP); -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, jk)); -+ return; -+ } -+ default: -+ break; -+ } -+ -+ vex_printf( "\n-- PUT(%d) = ", offsIP); -+ ppIRExpr( next ); -+ vex_printf( "; exit-"); -+ ppIRJumpKind(jk); -+ vex_printf( "\n"); -+ vassert(0); // are we expecting any other kind? -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- Insn selector top-level ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Translate an entire SB to arm64 code. */ -+ -+HInstrArray* iselSB_ARM64 ( IRSB* bb, -+ VexArch arch_host, -+ VexArchInfo* archinfo_host, -+ VexAbiInfo* vbi/*UNUSED*/, -+ Int offs_Host_EvC_Counter, -+ Int offs_Host_EvC_FailAddr, -+ Bool chainingAllowed, -+ Bool addProfInc, -+ Addr64 max_ga ) -+{ -+ Int i, j; -+ HReg hreg, hregHI; -+ ISelEnv* env; -+ UInt hwcaps_host = archinfo_host->hwcaps; -+ ARM64AMode *amCounter, *amFailAddr; -+ -+ /* sanity ... */ -+ vassert(arch_host == VexArchARM64); -+ -+ /* guard against unexpected space regressions */ -+ vassert(sizeof(ARM64Instr) <= 32); -+ -+ /* Make up an initial environment to use. */ -+ env = LibVEX_Alloc(sizeof(ISelEnv)); -+ env->vreg_ctr = 0; -+ -+ /* Set up output code array. */ -+ env->code = newHInstrArray(); -+ -+ /* Copy BB's type env. */ -+ env->type_env = bb->tyenv; -+ -+ /* Make up an IRTemp -> virtual HReg mapping. This doesn't -+ change as we go along. */ -+ env->n_vregmap = bb->tyenv->types_used; -+ env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); -+ env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); -+ -+ /* and finally ... */ -+ env->chainingAllowed = chainingAllowed; -+ env->hwcaps = hwcaps_host; -+ env->previous_rm = NULL; -+ env->max_ga = max_ga; -+ -+ /* For each IR temporary, allocate a suitably-kinded virtual -+ register. */ -+ j = 0; -+ for (i = 0; i < env->n_vregmap; i++) { -+ hregHI = hreg = INVALID_HREG; -+ switch (bb->tyenv->types[i]) { -+ case Ity_I1: -+ case Ity_I8: case Ity_I16: case Ity_I32: case Ity_I64: -+ hreg = mkHReg(j++, HRcInt64, True); -+ break; -+ case Ity_I128: -+ hreg = mkHReg(j++, HRcInt64, True); -+ hregHI = mkHReg(j++, HRcInt64, True); -+ break; -+ case Ity_F32: // we'll use HRcFlt64 regs for F32 too -+ case Ity_F64: -+ hreg = mkHReg(j++, HRcFlt64, True); -+ break; -+ case Ity_V128: -+ hreg = mkHReg(j++, HRcVec128, True); -+ break; -+ default: -+ ppIRType(bb->tyenv->types[i]); -+ vpanic("iselBB(arm64): IRTemp type"); -+ } -+ env->vregmap[i] = hreg; -+ env->vregmapHI[i] = hregHI; -+ } -+ env->vreg_ctr = j; -+ -+ /* The very first instruction must be an event check. */ -+ amCounter = ARM64AMode_RI9(hregARM64_X21(), offs_Host_EvC_Counter); -+ amFailAddr = ARM64AMode_RI9(hregARM64_X21(), offs_Host_EvC_FailAddr); -+ addInstr(env, ARM64Instr_EvCheck(amCounter, amFailAddr)); -+ -+ /* Possibly a block counter increment (for profiling). At this -+ point we don't know the address of the counter, so just pretend -+ it is zero. It will have to be patched later, but before this -+ translation is used, by a call to LibVEX_patchProfCtr. */ -+ if (addProfInc) { -+ vassert(0); -+ //addInstr(env, ARM64Instr_ProfInc()); -+ } -+ -+ /* Ok, finally we can iterate over the statements. */ -+ for (i = 0; i < bb->stmts_used; i++) -+ iselStmt(env, bb->stmts[i]); -+ -+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP); -+ -+ /* record the number of vregs we used. */ -+ env->code->n_vregs = env->vreg_ctr; -+ return env->code; -+} -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- end host_arm64_isel.c ---*/ -+/*---------------------------------------------------------------*/ -Index: VEX/priv/guest_arm64_toIR.c -=================================================================== ---- /dev/null -+++ VEX/priv/guest_arm64_toIR.c -@@ -0,0 +1,5087 @@ -+/* -*- mode: C; c-basic-offset: 3; -*- */ -+ -+/*--------------------------------------------------------------------*/ -+/*--- begin guest_arm64_toIR.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+//ZZ /* XXXX thumb to check: -+//ZZ that all cases where putIRegT writes r15, we generate a jump. -+//ZZ -+//ZZ All uses of newTemp assign to an IRTemp and not a UInt -+//ZZ -+//ZZ For all thumb loads and stores, including VFP ones, new-ITSTATE is -+//ZZ backed out before the memory op, and restored afterwards. This -+//ZZ needs to happen even after we go uncond. (and for sure it doesn't -+//ZZ happen for VFP loads/stores right now). -+//ZZ -+//ZZ VFP on thumb: check that we exclude all r13/r15 cases that we -+//ZZ should. -+//ZZ -+//ZZ XXXX thumb to do: improve the ITSTATE-zeroing optimisation by -+//ZZ taking into account the number of insns guarded by an IT. -+//ZZ -+//ZZ remove the nasty hack, in the spechelper, of looking for Or32(..., -+//ZZ 0xE0) in as the first arg to armg_calculate_condition, and instead -+//ZZ use Slice44 as specified in comments in the spechelper. -+//ZZ -+//ZZ add specialisations for armg_calculate_flag_c and _v, as they -+//ZZ are moderately often needed in Thumb code. -+//ZZ -+//ZZ Correctness: ITSTATE handling in Thumb SVCs is wrong. -+//ZZ -+//ZZ Correctness (obscure): in m_transtab, when invalidating code -+//ZZ address ranges, invalidate up to 18 bytes after the end of the -+//ZZ range. This is because the ITSTATE optimisation at the top of -+//ZZ _THUMB_WRK below analyses up to 18 bytes before the start of any -+//ZZ given instruction, and so might depend on the invalidated area. -+//ZZ */ -+//ZZ -+//ZZ /* Limitations, etc -+//ZZ -+//ZZ - pretty dodgy exception semantics for {LD,ST}Mxx and {LD,ST}RD. -+//ZZ These instructions are non-restartable in the case where the -+//ZZ transfer(s) fault. -+//ZZ -+//ZZ - SWP: the restart jump back is Ijk_Boring; it should be -+//ZZ Ijk_NoRedir but that's expensive. See comments on casLE() in -+//ZZ guest_x86_toIR.c. -+//ZZ */ -+ -+/* "Special" instructions. -+ -+ This instruction decoder can decode four special instructions -+ which mean nothing natively (are no-ops as far as regs/mem are -+ concerned) but have meaning for supporting Valgrind. A special -+ instruction is flagged by a 16-byte preamble: -+ -+ 93CC0D8C 93CC358C 93CCCD8C 93CCF58C -+ (ror x12, x12, #3; ror x12, x12, #13 -+ ror x12, x12, #51; ror x12, x12, #61) -+ -+ Following that, one of the following 3 are allowed -+ (standard interpretation in parentheses): -+ -+ AA0A014A (orr x10,x10,x10) X3 = client_request ( X4 ) -+ AA0B016B (orr x11,x11,x11) X3 = guest_NRADDR -+ AA0C018C (orr x12,x12,x12) branch-and-link-to-noredir X8 -+ AA090129 (orr x9,x9,x9) IR injection -+ -+ Any other bytes following the 16-byte preamble are illegal and -+ constitute a failure in instruction decoding. This all assumes -+ that the preamble will never occur except in specific code -+ fragments designed for Valgrind to catch. -+*/ -+ -+/* Translates ARM64 code to IR. */ -+ -+#include "libvex_basictypes.h" -+#include "libvex_ir.h" -+#include "libvex.h" -+#include "libvex_guest_arm64.h" -+ -+#include "main_util.h" -+#include "main_globals.h" -+#include "guest_generic_bb_to_IR.h" -+#include "guest_arm64_defs.h" -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Globals ---*/ -+/*------------------------------------------------------------*/ -+ -+/* These are set at the start of the translation of a instruction, so -+ that we don't have to pass them around endlessly. CONST means does -+ not change during translation of the instruction. -+*/ -+ -+/* CONST: is the host bigendian? We need to know this in order to do -+ sub-register accesses to the SIMD/FP registers correctly. */ -+static Bool host_is_bigendian; -+ -+/* CONST: The guest address for the instruction currently being -+ translated. */ -+static Addr64 guest_PC_curr_instr; -+ -+/* MOD: The IRSB* into which we're generating code. */ -+static IRSB* irsb; -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Debugging output ---*/ -+/*------------------------------------------------------------*/ -+ -+#define DIP(format, args...) \ -+ if (vex_traceflags & VEX_TRACE_FE) \ -+ vex_printf(format, ## args) -+ -+#define DIS(buf, format, args...) \ -+ if (vex_traceflags & VEX_TRACE_FE) \ -+ vex_sprintf(buf, format, ## args) -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helper bits and pieces for deconstructing the ---*/ -+/*--- arm insn stream. ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Do a little-endian load of a 32-bit word, regardless of the -+ endianness of the underlying host. */ -+static inline UInt getUIntLittleEndianly ( UChar* p ) -+{ -+ UInt w = 0; -+ w = (w << 8) | p[3]; -+ w = (w << 8) | p[2]; -+ w = (w << 8) | p[1]; -+ w = (w << 8) | p[0]; -+ return w; -+} -+ -+/* Sign extend a N-bit value up to 64 bits, by copying -+ bit N-1 into all higher positions. */ -+static ULong sx_to_64 ( ULong x, UInt n ) -+{ -+ vassert(n > 1 && n < 64); -+ Long r = (Long)x; -+ r = (r << (64-n)) >> (64-n); -+ return (ULong)r; -+} -+ -+//ZZ /* Do a little-endian load of a 16-bit word, regardless of the -+//ZZ endianness of the underlying host. */ -+//ZZ static inline UShort getUShortLittleEndianly ( UChar* p ) -+//ZZ { -+//ZZ UShort w = 0; -+//ZZ w = (w << 8) | p[1]; -+//ZZ w = (w << 8) | p[0]; -+//ZZ return w; -+//ZZ } -+//ZZ -+//ZZ static UInt ROR32 ( UInt x, UInt sh ) { -+//ZZ vassert(sh >= 0 && sh < 32); -+//ZZ if (sh == 0) -+//ZZ return x; -+//ZZ else -+//ZZ return (x << (32-sh)) | (x >> sh); -+//ZZ } -+//ZZ -+//ZZ static Int popcount32 ( UInt x ) -+//ZZ { -+//ZZ Int res = 0, i; -+//ZZ for (i = 0; i < 32; i++) { -+//ZZ res += (x & 1); -+//ZZ x >>= 1; -+//ZZ } -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ static UInt setbit32 ( UInt x, Int ix, UInt b ) -+//ZZ { -+//ZZ UInt mask = 1 << ix; -+//ZZ x &= ~mask; -+//ZZ x |= ((b << ix) & mask); -+//ZZ return x; -+//ZZ } -+ -+#define BITS2(_b1,_b0) \ -+ (((_b1) << 1) | (_b0)) -+ -+#define BITS3(_b2,_b1,_b0) \ -+ (((_b2) << 2) | ((_b1) << 1) | (_b0)) -+ -+#define BITS4(_b3,_b2,_b1,_b0) \ -+ (((_b3) << 3) | ((_b2) << 2) | ((_b1) << 1) | (_b0)) -+ -+#define BITS8(_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \ -+ | BITS4((_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS5(_b4,_b3,_b2,_b1,_b0) \ -+ (BITS8(0,0,0,(_b4),(_b3),(_b2),(_b1),(_b0))) -+#define BITS6(_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (BITS8(0,0,(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+#define BITS7(_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (BITS8(0,(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS9(_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (((_b8) << 8) \ -+ | BITS8((_b7),(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS10(_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (((_b9) << 9) | ((_b8) << 8) \ -+ | BITS8((_b7),(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS11(_b10,_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (((_b10) << 10) \ -+ | BITS10(_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0)) -+ -+// produces _uint[_bMax:_bMin] -+#define SLICE_UInt(_uint,_bMax,_bMin) \ -+ (( ((UInt)(_uint)) >> (_bMin)) \ -+ & (UInt)((1ULL << ((_bMax) - (_bMin) + 1)) - 1ULL)) -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helper bits and pieces for creating IR fragments. ---*/ -+/*------------------------------------------------------------*/ -+ -+static IRExpr* mkV128 ( UShort w ) -+{ -+ return IRExpr_Const(IRConst_V128(w)); -+} -+ -+static IRExpr* mkU64 ( ULong i ) -+{ -+ return IRExpr_Const(IRConst_U64(i)); -+} -+ -+static IRExpr* mkU32 ( UInt i ) -+{ -+ return IRExpr_Const(IRConst_U32(i)); -+} -+ -+static IRExpr* mkU8 ( UInt i ) -+{ -+ vassert(i < 256); -+ return IRExpr_Const(IRConst_U8( (UChar)i )); -+} -+ -+static IRExpr* mkexpr ( IRTemp tmp ) -+{ -+ return IRExpr_RdTmp(tmp); -+} -+ -+static IRExpr* unop ( IROp op, IRExpr* a ) -+{ -+ return IRExpr_Unop(op, a); -+} -+ -+static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) -+{ -+ return IRExpr_Binop(op, a1, a2); -+} -+ -+static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) -+{ -+ return IRExpr_Triop(op, a1, a2, a3); -+} -+ -+static IRExpr* loadLE ( IRType ty, IRExpr* addr ) -+{ -+ return IRExpr_Load(Iend_LE, ty, addr); -+} -+ -+/* Add a statement to the list held by "irbb". */ -+static void stmt ( IRStmt* st ) -+{ -+ addStmtToIRSB( irsb, st ); -+} -+ -+static void assign ( IRTemp dst, IRExpr* e ) -+{ -+ stmt( IRStmt_WrTmp(dst, e) ); -+} -+ -+static void storeLE ( IRExpr* addr, IRExpr* data ) -+{ -+ stmt( IRStmt_Store(Iend_LE, addr, data) ); -+} -+ -+//ZZ static void storeGuardedLE ( IRExpr* addr, IRExpr* data, IRTemp guardT ) -+//ZZ { -+//ZZ if (guardT == IRTemp_INVALID) { -+//ZZ /* unconditional */ -+//ZZ storeLE(addr, data); -+//ZZ } else { -+//ZZ stmt( IRStmt_StoreG(Iend_LE, addr, data, -+//ZZ binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0))) ); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void loadGuardedLE ( IRTemp dst, IRLoadGOp cvt, -+//ZZ IRExpr* addr, IRExpr* alt, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ if (guardT == IRTemp_INVALID) { -+//ZZ /* unconditional */ -+//ZZ IRExpr* loaded = NULL; -+//ZZ switch (cvt) { -+//ZZ case ILGop_Ident32: -+//ZZ loaded = loadLE(Ity_I32, addr); break; -+//ZZ case ILGop_8Uto32: -+//ZZ loaded = unop(Iop_8Uto32, loadLE(Ity_I8, addr)); break; -+//ZZ case ILGop_8Sto32: -+//ZZ loaded = unop(Iop_8Sto32, loadLE(Ity_I8, addr)); break; -+//ZZ case ILGop_16Uto32: -+//ZZ loaded = unop(Iop_16Uto32, loadLE(Ity_I16, addr)); break; -+//ZZ case ILGop_16Sto32: -+//ZZ loaded = unop(Iop_16Sto32, loadLE(Ity_I16, addr)); break; -+//ZZ default: -+//ZZ vassert(0); -+//ZZ } -+//ZZ vassert(loaded != NULL); -+//ZZ assign(dst, loaded); -+//ZZ } else { -+//ZZ /* Generate a guarded load into 'dst', but apply 'cvt' to the -+//ZZ loaded data before putting the data in 'dst'. If the load -+//ZZ does not take place, 'alt' is placed directly in 'dst'. */ -+//ZZ stmt( IRStmt_LoadG(Iend_LE, cvt, dst, addr, alt, -+//ZZ binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0))) ); -+//ZZ } -+//ZZ } -+ -+/* Generate a new temporary of the given type. */ -+static IRTemp newTemp ( IRType ty ) -+{ -+ vassert(isPlausibleIRType(ty)); -+ return newIRTemp( irsb->tyenv, ty ); -+} -+ -+//ZZ /* Produces a value in 0 .. 3, which is encoded as per the type -+//ZZ IRRoundingMode. */ -+//ZZ static IRExpr* /* :: Ity_I32 */ get_FAKE_roundingmode ( void ) -+//ZZ { -+//ZZ return mkU32(Irrm_NEAREST); -+//ZZ } -+//ZZ -+//ZZ /* Generate an expression for SRC rotated right by ROT. */ -+//ZZ static IRExpr* genROR32( IRTemp src, Int rot ) -+//ZZ { -+//ZZ vassert(rot >= 0 && rot < 32); -+//ZZ if (rot == 0) -+//ZZ return mkexpr(src); -+//ZZ return -+//ZZ binop(Iop_Or32, -+//ZZ binop(Iop_Shl32, mkexpr(src), mkU8(32 - rot)), -+//ZZ binop(Iop_Shr32, mkexpr(src), mkU8(rot))); -+//ZZ } -+//ZZ -+//ZZ static IRExpr* mkU128 ( ULong i ) -+//ZZ { -+//ZZ return binop(Iop_64HLtoV128, mkU64(i), mkU64(i)); -+//ZZ } -+//ZZ -+//ZZ /* Generate a 4-aligned version of the given expression if -+//ZZ the given condition is true. Else return it unchanged. */ -+//ZZ static IRExpr* align4if ( IRExpr* e, Bool b ) -+//ZZ { -+//ZZ if (b) -+//ZZ return binop(Iop_And32, e, mkU32(~3)); -+//ZZ else -+//ZZ return e; -+//ZZ } -+ -+/* Other IR construction helpers. */ -+static IROp mkAND ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_And32; -+ case Ity_I64: return Iop_And64; -+ default: vpanic("mkAND"); -+ } -+} -+ -+static IROp mkOR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Or32; -+ case Ity_I64: return Iop_Or64; -+ default: vpanic("mkOR"); -+ } -+} -+ -+static IROp mkXOR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Xor32; -+ case Ity_I64: return Iop_Xor64; -+ default: vpanic("mkXOR"); -+ } -+} -+ -+static IROp mkSHL ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Shl32; -+ case Ity_I64: return Iop_Shl64; -+ default: vpanic("mkSHL"); -+ } -+} -+ -+static IROp mkSHR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Shr32; -+ case Ity_I64: return Iop_Shr64; -+ default: vpanic("mkSHR"); -+ } -+} -+ -+static IROp mkSAR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Sar32; -+ case Ity_I64: return Iop_Sar64; -+ default: vpanic("mkSAR"); -+ } -+} -+ -+static IROp mkNOT ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Not32; -+ case Ity_I64: return Iop_Not64; -+ default: vpanic("mkNOT"); -+ } -+} -+ -+static IROp mkADD ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Add32; -+ case Ity_I64: return Iop_Add64; -+ default: vpanic("mkADD"); -+ } -+} -+ -+static IROp mkSUB ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Sub32; -+ case Ity_I64: return Iop_Sub64; -+ default: vpanic("mkSUB"); -+ } -+} -+ -+static IROp mkADDF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_AddF32; -+ case Ity_F64: return Iop_AddF64; -+ default: vpanic("mkADDF"); -+ } -+} -+ -+static IROp mkSUBF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_SubF32; -+ case Ity_F64: return Iop_SubF64; -+ default: vpanic("mkSUBF"); -+ } -+} -+ -+static IROp mkMULF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_MulF32; -+ case Ity_F64: return Iop_MulF64; -+ default: vpanic("mkMULF"); -+ } -+} -+ -+static IROp mkDIVF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_DivF32; -+ case Ity_F64: return Iop_DivF64; -+ default: vpanic("mkMULF"); -+ } -+} -+ -+static IROp mkNEGF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_NegF32; -+ case Ity_F64: return Iop_NegF64; -+ default: vpanic("mkNEGF"); -+ } -+} -+ -+static IROp mkABSF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_AbsF32; -+ case Ity_F64: return Iop_AbsF64; -+ default: vpanic("mkNEGF"); -+ } -+} -+ -+static IROp mkSQRTF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_SqrtF32; -+ case Ity_F64: return Iop_SqrtF64; -+ default: vpanic("mkNEGF"); -+ } -+} -+ -+static IRExpr* mkU ( IRType ty, ULong imm ) { -+ switch (ty) { -+ case Ity_I32: return mkU32((UInt)(imm & 0xFFFFFFFFULL)); -+ case Ity_I64: return mkU64(imm); -+ default: vpanic("mkU"); -+ } -+} -+ -+/* Generate IR to create 'arg rotated right by imm', for sane values -+ of 'ty' and 'imm'. */ -+static IRTemp mathROR ( IRType ty, IRTemp arg, UInt imm ) -+{ -+ UInt w = 0; -+ if (ty == Ity_I64) { -+ w = 64; -+ } else { -+ vassert(ty == Ity_I32); -+ w = 32; -+ } -+ vassert(w != 0); -+ vassert(imm < w); -+ if (imm == 0) { -+ return arg; -+ } -+ IRTemp res = newTemp(ty); -+ assign(res, binop(mkOR(ty), -+ binop(mkSHL(ty), mkexpr(arg), mkU8(w - imm)), -+ binop(mkSHR(ty), mkexpr(arg), mkU8(imm)) )); -+ return res; -+} -+ -+/* Generate IR to set the returned temp to either all-zeroes or -+ all ones, as a copy of arg. */ -+static IRTemp mathREPLICATE ( IRType ty, IRTemp arg, UInt imm ) -+{ -+ UInt w = 0; -+ if (ty == Ity_I64) { -+ w = 64; -+ } else { -+ vassert(ty == Ity_I32); -+ w = 32; -+ } -+ vassert(w != 0); -+ vassert(imm < w); -+ IRTemp res = newTemp(ty); -+ assign(res, binop(mkSAR(ty), -+ binop(mkSHL(ty), mkexpr(arg), mkU8(w - 1 - imm)), -+ mkU8(w - 1))); -+ return res; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helpers for accessing guest registers. ---*/ -+/*------------------------------------------------------------*/ -+ -+#define OFFB_X0 offsetof(VexGuestARM64State,guest_X0) -+#define OFFB_X1 offsetof(VexGuestARM64State,guest_X1) -+#define OFFB_X2 offsetof(VexGuestARM64State,guest_X2) -+#define OFFB_X3 offsetof(VexGuestARM64State,guest_X3) -+#define OFFB_X4 offsetof(VexGuestARM64State,guest_X4) -+#define OFFB_X5 offsetof(VexGuestARM64State,guest_X5) -+#define OFFB_X6 offsetof(VexGuestARM64State,guest_X6) -+#define OFFB_X7 offsetof(VexGuestARM64State,guest_X7) -+#define OFFB_X8 offsetof(VexGuestARM64State,guest_X8) -+#define OFFB_X9 offsetof(VexGuestARM64State,guest_X9) -+#define OFFB_X10 offsetof(VexGuestARM64State,guest_X10) -+#define OFFB_X11 offsetof(VexGuestARM64State,guest_X11) -+#define OFFB_X12 offsetof(VexGuestARM64State,guest_X12) -+#define OFFB_X13 offsetof(VexGuestARM64State,guest_X13) -+#define OFFB_X14 offsetof(VexGuestARM64State,guest_X14) -+#define OFFB_X15 offsetof(VexGuestARM64State,guest_X15) -+#define OFFB_X16 offsetof(VexGuestARM64State,guest_X16) -+#define OFFB_X17 offsetof(VexGuestARM64State,guest_X17) -+#define OFFB_X18 offsetof(VexGuestARM64State,guest_X18) -+#define OFFB_X19 offsetof(VexGuestARM64State,guest_X19) -+#define OFFB_X20 offsetof(VexGuestARM64State,guest_X20) -+#define OFFB_X21 offsetof(VexGuestARM64State,guest_X21) -+#define OFFB_X22 offsetof(VexGuestARM64State,guest_X22) -+#define OFFB_X23 offsetof(VexGuestARM64State,guest_X23) -+#define OFFB_X24 offsetof(VexGuestARM64State,guest_X24) -+#define OFFB_X25 offsetof(VexGuestARM64State,guest_X25) -+#define OFFB_X26 offsetof(VexGuestARM64State,guest_X26) -+#define OFFB_X27 offsetof(VexGuestARM64State,guest_X27) -+#define OFFB_X28 offsetof(VexGuestARM64State,guest_X28) -+#define OFFB_X29 offsetof(VexGuestARM64State,guest_X29) -+#define OFFB_X30 offsetof(VexGuestARM64State,guest_X30) -+ -+#define OFFB_SP offsetof(VexGuestARM64State,guest_SP) -+#define OFFB_PC offsetof(VexGuestARM64State,guest_PC) -+ -+#define OFFB_CC_OP offsetof(VexGuestARM64State,guest_CC_OP) -+#define OFFB_CC_DEP1 offsetof(VexGuestARM64State,guest_CC_DEP1) -+#define OFFB_CC_DEP2 offsetof(VexGuestARM64State,guest_CC_DEP2) -+#define OFFB_CC_NDEP offsetof(VexGuestARM64State,guest_CC_NDEP) -+ -+#define OFFB_TPIDR_EL0 offsetof(VexGuestARM64State,guest_TPIDR_EL0) -+#define OFFB_NRADDR offsetof(VexGuestARM64State,guest_NRADDR) -+ -+#define OFFB_Q0 offsetof(VexGuestARM64State,guest_Q0) -+#define OFFB_Q1 offsetof(VexGuestARM64State,guest_Q1) -+#define OFFB_Q2 offsetof(VexGuestARM64State,guest_Q2) -+#define OFFB_Q3 offsetof(VexGuestARM64State,guest_Q3) -+#define OFFB_Q4 offsetof(VexGuestARM64State,guest_Q4) -+#define OFFB_Q5 offsetof(VexGuestARM64State,guest_Q5) -+#define OFFB_Q6 offsetof(VexGuestARM64State,guest_Q6) -+#define OFFB_Q7 offsetof(VexGuestARM64State,guest_Q7) -+#define OFFB_Q8 offsetof(VexGuestARM64State,guest_Q8) -+#define OFFB_Q9 offsetof(VexGuestARM64State,guest_Q9) -+#define OFFB_Q10 offsetof(VexGuestARM64State,guest_Q10) -+#define OFFB_Q11 offsetof(VexGuestARM64State,guest_Q11) -+#define OFFB_Q12 offsetof(VexGuestARM64State,guest_Q12) -+#define OFFB_Q13 offsetof(VexGuestARM64State,guest_Q13) -+#define OFFB_Q14 offsetof(VexGuestARM64State,guest_Q14) -+#define OFFB_Q15 offsetof(VexGuestARM64State,guest_Q15) -+#define OFFB_Q16 offsetof(VexGuestARM64State,guest_Q16) -+#define OFFB_Q17 offsetof(VexGuestARM64State,guest_Q17) -+#define OFFB_Q18 offsetof(VexGuestARM64State,guest_Q18) -+#define OFFB_Q19 offsetof(VexGuestARM64State,guest_Q19) -+#define OFFB_Q20 offsetof(VexGuestARM64State,guest_Q20) -+#define OFFB_Q21 offsetof(VexGuestARM64State,guest_Q21) -+#define OFFB_Q22 offsetof(VexGuestARM64State,guest_Q22) -+#define OFFB_Q23 offsetof(VexGuestARM64State,guest_Q23) -+#define OFFB_Q24 offsetof(VexGuestARM64State,guest_Q24) -+#define OFFB_Q25 offsetof(VexGuestARM64State,guest_Q25) -+#define OFFB_Q26 offsetof(VexGuestARM64State,guest_Q26) -+#define OFFB_Q27 offsetof(VexGuestARM64State,guest_Q27) -+#define OFFB_Q28 offsetof(VexGuestARM64State,guest_Q28) -+#define OFFB_Q29 offsetof(VexGuestARM64State,guest_Q29) -+#define OFFB_Q30 offsetof(VexGuestARM64State,guest_Q30) -+#define OFFB_Q31 offsetof(VexGuestARM64State,guest_Q31) -+ -+#define OFFB_FPCR offsetof(VexGuestARM64State,guest_FPCR) -+#define OFFB_FPSR offsetof(VexGuestARM64State,guest_FPSR) -+//ZZ #define OFFB_TPIDRURO offsetof(VexGuestARMState,guest_TPIDRURO) -+//ZZ #define OFFB_ITSTATE offsetof(VexGuestARMState,guest_ITSTATE) -+//ZZ #define OFFB_QFLAG32 offsetof(VexGuestARMState,guest_QFLAG32) -+//ZZ #define OFFB_GEFLAG0 offsetof(VexGuestARMState,guest_GEFLAG0) -+//ZZ #define OFFB_GEFLAG1 offsetof(VexGuestARMState,guest_GEFLAG1) -+//ZZ #define OFFB_GEFLAG2 offsetof(VexGuestARMState,guest_GEFLAG2) -+//ZZ #define OFFB_GEFLAG3 offsetof(VexGuestARMState,guest_GEFLAG3) -+ -+#define OFFB_TISTART offsetof(VexGuestARM64State,guest_TISTART) -+#define OFFB_TILEN offsetof(VexGuestARM64State,guest_TILEN) -+ -+ -+/* ---------------- Integer registers ---------------- */ -+ -+static Int offsetIReg64 ( UInt iregNo ) -+{ -+ /* Do we care about endianness here? We do if sub-parts of integer -+ registers are accessed. */ -+ switch (iregNo) { -+ case 0: return OFFB_X0; -+ case 1: return OFFB_X1; -+ case 2: return OFFB_X2; -+ case 3: return OFFB_X3; -+ case 4: return OFFB_X4; -+ case 5: return OFFB_X5; -+ case 6: return OFFB_X6; -+ case 7: return OFFB_X7; -+ case 8: return OFFB_X8; -+ case 9: return OFFB_X9; -+ case 10: return OFFB_X10; -+ case 11: return OFFB_X11; -+ case 12: return OFFB_X12; -+ case 13: return OFFB_X13; -+ case 14: return OFFB_X14; -+ case 15: return OFFB_X15; -+ case 16: return OFFB_X16; -+ case 17: return OFFB_X17; -+ case 18: return OFFB_X18; -+ case 19: return OFFB_X19; -+ case 20: return OFFB_X20; -+ case 21: return OFFB_X21; -+ case 22: return OFFB_X22; -+ case 23: return OFFB_X23; -+ case 24: return OFFB_X24; -+ case 25: return OFFB_X25; -+ case 26: return OFFB_X26; -+ case 27: return OFFB_X27; -+ case 28: return OFFB_X28; -+ case 29: return OFFB_X29; -+ case 30: return OFFB_X30; -+ /* but not 31 */ -+ default: vassert(0); -+ } -+} -+ -+static Int offsetIReg64orSP ( UInt iregNo ) -+{ -+ return iregNo == 31 ? OFFB_SP : offsetIReg64(iregNo); -+} -+ -+static const HChar* nameIReg64orZR ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ static const HChar* names[32] -+ = { "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", -+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", -+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", -+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "xzr" }; -+ return names[iregNo]; -+} -+ -+static const HChar* nameIReg64orSP ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return "sp"; -+ } -+ vassert(iregNo < 31); -+ return nameIReg64orZR(iregNo); -+} -+ -+static IRExpr* getIReg64orSP ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ return IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 ); -+} -+ -+static IRExpr* getIReg64orZR ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return mkU64(0); -+ } -+ vassert(iregNo < 31); -+ return IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 ); -+} -+ -+static void putIReg64orSP ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), e) ); -+} -+ -+static void putIReg64orZR ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); -+ if (iregNo == 31) { -+ return; -+ } -+ vassert(iregNo < 31); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), e) ); -+} -+ -+static const HChar* nameIReg32orZR ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ static const HChar* names[32] -+ = { "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", -+ "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", -+ "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", -+ "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr" }; -+ return names[iregNo]; -+} -+ -+static const HChar* nameIReg32orSP ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return "wsp"; -+ } -+ vassert(iregNo < 31); -+ return nameIReg32orZR(iregNo); -+} -+ -+static IRExpr* getIReg32orSP ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ return unop(Iop_64to32, -+ IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 )); -+} -+ -+static IRExpr* getIReg32orZR ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return mkU32(0); -+ } -+ vassert(iregNo < 31); -+ return unop(Iop_64to32, -+ IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 )); -+} -+ -+static void putIReg32orSP ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), unop(Iop_32Uto64, e)) ); -+} -+ -+static void putIReg32orZR ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); -+ if (iregNo == 31) { -+ return; -+ } -+ vassert(iregNo < 31); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), unop(Iop_32Uto64, e)) ); -+} -+ -+static const HChar* nameIRegOrSP ( Bool is64, UInt iregNo ) -+{ -+ vassert(is64 == True || is64 == False); -+ return is64 ? nameIReg64orSP(iregNo) : nameIReg32orSP(iregNo); -+} -+ -+static const HChar* nameIRegOrZR ( Bool is64, UInt iregNo ) -+{ -+ vassert(is64 == True || is64 == False); -+ return is64 ? nameIReg64orZR(iregNo) : nameIReg32orZR(iregNo); -+} -+ -+static IRExpr* getIRegOrZR ( Bool is64, UInt iregNo ) -+{ -+ vassert(is64 == True || is64 == False); -+ return is64 ? getIReg64orZR(iregNo) : getIReg32orZR(iregNo); -+} -+ -+static void putIRegOrZR ( Bool is64, UInt iregNo, IRExpr* e ) -+{ -+ vassert(is64 == True || is64 == False); -+ if (is64) putIReg64orZR(iregNo, e); else putIReg32orZR(iregNo, e); -+} -+ -+static void putPC ( IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); -+ stmt( IRStmt_Put(OFFB_PC, e) ); -+} -+ -+ -+/* ---------------- Vector (Q) registers ---------------- */ -+ -+static Int offsetQReg128 ( UInt qregNo ) -+{ -+ /* We don't care about endianness at this point. It only becomes -+ relevant when dealing with sections of these registers.*/ -+ switch (qregNo) { -+ case 0: return OFFB_Q0; -+ case 1: return OFFB_Q1; -+ case 2: return OFFB_Q2; -+ case 3: return OFFB_Q3; -+ case 4: return OFFB_Q4; -+ case 5: return OFFB_Q5; -+ case 6: return OFFB_Q6; -+ case 7: return OFFB_Q7; -+ case 8: return OFFB_Q8; -+ case 9: return OFFB_Q9; -+ case 10: return OFFB_Q10; -+ case 11: return OFFB_Q11; -+ case 12: return OFFB_Q12; -+ case 13: return OFFB_Q13; -+ case 14: return OFFB_Q14; -+ case 15: return OFFB_Q15; -+ case 16: return OFFB_Q16; -+ case 17: return OFFB_Q17; -+ case 18: return OFFB_Q18; -+ case 19: return OFFB_Q19; -+ case 20: return OFFB_Q20; -+ case 21: return OFFB_Q21; -+ case 22: return OFFB_Q22; -+ case 23: return OFFB_Q23; -+ case 24: return OFFB_Q24; -+ case 25: return OFFB_Q25; -+ case 26: return OFFB_Q26; -+ case 27: return OFFB_Q27; -+ case 28: return OFFB_Q28; -+ case 29: return OFFB_Q29; -+ case 30: return OFFB_Q30; -+ case 31: return OFFB_Q31; -+ default: vassert(0); -+ } -+} -+ -+ -+/* Write to a complete Qreg. */ -+static void putQReg128 ( UInt qregNo, IRExpr* e ) -+{ -+ vassert(qregNo < 32); -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); -+ stmt( IRStmt_Put(offsetQReg128(qregNo), e) ); -+} -+ -+/* Read a complete Qreg. */ -+static IRExpr* getQReg128 ( UInt qregNo ) -+{ -+ vassert(qregNo < 32); -+ return IRExpr_Get(offsetQReg128(qregNo), Ity_V128); -+} -+ -+/* Produce the IR type for some sub-part of a vector. For 32- and 64- -+ bit sub-parts we can choose either integer or float types, and -+ choose float on the basis that that is the common use case and so -+ will give least interference with Put-to-Get forwarding later -+ on. */ -+static IRType preferredVectorSubTypeFromSize ( UInt szB ) -+{ -+ switch (szB) { -+ case 1: return Ity_I8; -+ case 2: return Ity_I16; -+ case 4: return Ity_I32; //Ity_F32; -+ case 8: return Ity_F64; -+ case 16: return Ity_V128; -+ default: vassert(0); -+ } -+} -+ -+/* Find the offset of the szB'th least significant bytes of the given -+ Qreg. This requires knowing the endianness of the host. */ -+static Int offsetQReg ( UInt szB, UInt qregNo ) -+{ -+ vassert(!host_is_bigendian); -+ Int base = offsetQReg128(qregNo); -+ /* Since we're dealing with a little-endian host, all of the -+ sub-parts will have the same offset as the base register. But -+ we still need to check that szB is valid. */ -+ switch (szB) { -+ case 1: case 2: case 4: case 8: case 16: break; -+ default: vassert(0); -+ } -+ return base; -+} -+ -+static void putQReg ( UInt qregNo, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(irsb->tyenv, e); -+ Int off = offsetQReg(sizeofIRType(ty), qregNo); -+ switch (ty) { -+ case Ity_I8: break; -+ case Ity_I16: break; -+ case Ity_I32: break; -+ case Ity_F32: break; -+ case Ity_I64: break; -+ case Ity_F64: break; -+ case Ity_V128: break; -+ default: vassert(0); // Other cases are ATC -+ } -+ stmt(IRStmt_Put(off, e)); -+} -+ -+static IRExpr* getQReg ( IRType ty, UInt qregNo ) -+{ -+ Int off = offsetQReg(sizeofIRType(ty), qregNo); -+ switch (ty) { -+ case Ity_I32: break; -+ case Ity_F32: break; -+ case Ity_I64: break; -+ case Ity_F64: break; -+ case Ity_V128: break; -+ default: vassert(0); // Other cases are ATC -+ } -+ return IRExpr_Get(off, ty); -+} -+ -+static const HChar* nameQReg ( UInt szB, UInt qregNo ) -+{ -+ static const HChar* namesQ[32] -+ = { "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", -+ "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", -+ "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", -+ "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" }; -+ static const HChar* namesD[32] -+ = { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", -+ "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", -+ "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31" }; -+ static const HChar* namesS[32] -+ = { "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", -+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", -+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", -+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31" }; -+ static const HChar* namesH[32] -+ = { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", -+ "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", -+ "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", -+ "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31" }; -+ static const HChar* namesB[32] -+ = { "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", -+ "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", -+ "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", -+ "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31" }; -+ vassert(qregNo < 32); -+ switch (szB) { -+ case 1: return namesB[qregNo]; -+ case 2: return namesH[qregNo]; -+ case 4: return namesS[qregNo]; -+ case 8: return namesD[qregNo]; -+ case 16: return namesQ[qregNo]; -+ default: vassert(0); -+ } -+ /*NOTREACHED*/ -+} -+ -+/* Find the offset of the most significant half (8 bytes) of the given -+ Qreg. This requires knowing the endianness of the host. */ -+static Int offsetQReg64HI ( UInt qregNo ) -+{ -+ vassert(!host_is_bigendian); -+ Int base = offsetQReg128(qregNo); -+ /* Since the host is little endian, the least significant half is -+ at the lower offset. So add 8 to get the MS half offset. */ -+ return base+8; -+} -+ -+static IRExpr* getQReg64HI ( UInt qregNo ) -+{ -+ return IRExpr_Get(offsetQReg64HI(qregNo), Ity_I64); -+} -+ -+static void putQReg64HI ( UInt qregNo, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(irsb->tyenv, e); -+ Int off = offsetQReg64HI(qregNo); -+ switch (ty) { -+ case Ity_I64: break; -+ case Ity_F64: break; -+ default: vassert(0); // Other cases are plain wrong -+ } -+ stmt(IRStmt_Put(off, e)); -+} -+ -+//ZZ /* ---------------- Misc registers ---------------- */ -+//ZZ -+//ZZ static void putMiscReg32 ( UInt gsoffset, -+//ZZ IRExpr* e, /* :: Ity_I32 */ -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */) -+//ZZ { -+//ZZ switch (gsoffset) { -+//ZZ case OFFB_FPSCR: break; -+//ZZ case OFFB_QFLAG32: break; -+//ZZ case OFFB_GEFLAG0: break; -+//ZZ case OFFB_GEFLAG1: break; -+//ZZ case OFFB_GEFLAG2: break; -+//ZZ case OFFB_GEFLAG3: break; -+//ZZ default: vassert(0); /* awaiting more cases */ -+//ZZ } -+//ZZ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); -+//ZZ -+//ZZ if (guardT == IRTemp_INVALID) { -+//ZZ /* unconditional write */ -+//ZZ stmt(IRStmt_Put(gsoffset, e)); -+//ZZ } else { -+//ZZ stmt(IRStmt_Put( -+//ZZ gsoffset, -+//ZZ IRExpr_ITE( binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0)), -+//ZZ e, IRExpr_Get(gsoffset, Ity_I32) ) -+//ZZ )); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static IRTemp get_ITSTATE ( void ) -+//ZZ { -+//ZZ ASSERT_IS_THUMB; -+//ZZ IRTemp t = newTemp(Ity_I32); -+//ZZ assign(t, IRExpr_Get( OFFB_ITSTATE, Ity_I32)); -+//ZZ return t; -+//ZZ } -+//ZZ -+//ZZ static void put_ITSTATE ( IRTemp t ) -+//ZZ { -+//ZZ ASSERT_IS_THUMB; -+//ZZ stmt( IRStmt_Put( OFFB_ITSTATE, mkexpr(t)) ); -+//ZZ } -+//ZZ -+//ZZ static IRTemp get_QFLAG32 ( void ) -+//ZZ { -+//ZZ IRTemp t = newTemp(Ity_I32); -+//ZZ assign(t, IRExpr_Get( OFFB_QFLAG32, Ity_I32)); -+//ZZ return t; -+//ZZ } -+//ZZ -+//ZZ static void put_QFLAG32 ( IRTemp t, IRTemp condT ) -+//ZZ { -+//ZZ putMiscReg32( OFFB_QFLAG32, mkexpr(t), condT ); -+//ZZ } -+//ZZ -+//ZZ /* Stickily set the 'Q' flag (APSR bit 27) of the APSR (Application Program -+//ZZ Status Register) to indicate that overflow or saturation occurred. -+//ZZ Nb: t must be zero to denote no saturation, and any nonzero -+//ZZ value to indicate saturation. */ -+//ZZ static void or_into_QFLAG32 ( IRExpr* e, IRTemp condT ) -+//ZZ { -+//ZZ IRTemp old = get_QFLAG32(); -+//ZZ IRTemp nyu = newTemp(Ity_I32); -+//ZZ assign(nyu, binop(Iop_Or32, mkexpr(old), e) ); -+//ZZ put_QFLAG32(nyu, condT); -+//ZZ } -+ -+ -+/* ---------------- FPCR stuff ---------------- */ -+ -+/* Generate IR to get hold of the rounding mode bits in FPCR, and -+ convert them to IR format. Bind the final result to the -+ returned temp. */ -+static IRTemp /* :: Ity_I32 */ mk_get_IR_rounding_mode ( void ) -+{ -+ /* The ARMvfp encoding for rounding mode bits is: -+ 00 to nearest -+ 01 to +infinity -+ 10 to -infinity -+ 11 to zero -+ We need to convert that to the IR encoding: -+ 00 to nearest (the default) -+ 10 to +infinity -+ 01 to -infinity -+ 11 to zero -+ Which can be done by swapping bits 0 and 1. -+ The rmode bits are at 23:22 in FPSCR. -+ */ -+ IRTemp armEncd = newTemp(Ity_I32); -+ IRTemp swapped = newTemp(Ity_I32); -+ /* Fish FPCR[23:22] out, and slide to bottom. Doesn't matter that -+ we don't zero out bits 24 and above, since the assignment to -+ 'swapped' will mask them out anyway. */ -+ assign(armEncd, -+ binop(Iop_Shr32, IRExpr_Get(OFFB_FPCR, Ity_I32), mkU8(22))); -+ /* Now swap them. */ -+ assign(swapped, -+ binop(Iop_Or32, -+ binop(Iop_And32, -+ binop(Iop_Shl32, mkexpr(armEncd), mkU8(1)), -+ mkU32(2)), -+ binop(Iop_And32, -+ binop(Iop_Shr32, mkexpr(armEncd), mkU8(1)), -+ mkU32(1)) -+ )); -+ return swapped; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helpers for flag handling and conditional insns ---*/ -+/*------------------------------------------------------------*/ -+ -+static const HChar* nameARM64Condcode ( ARM64Condcode cond ) -+{ -+ switch (cond) { -+ case ARM64CondEQ: return "eq"; -+ case ARM64CondNE: return "ne"; -+ case ARM64CondCS: return "cs"; // or 'hs' -+ case ARM64CondCC: return "cc"; // or 'lo' -+ case ARM64CondMI: return "mi"; -+ case ARM64CondPL: return "pl"; -+ case ARM64CondVS: return "vs"; -+ case ARM64CondVC: return "vc"; -+ case ARM64CondHI: return "hi"; -+ case ARM64CondLS: return "ls"; -+ case ARM64CondGE: return "ge"; -+ case ARM64CondLT: return "lt"; -+ case ARM64CondGT: return "gt"; -+ case ARM64CondLE: return "le"; -+ case ARM64CondAL: return "al"; -+ case ARM64CondNV: return "nv"; -+ default: vpanic("name_ARM64Condcode"); -+ } -+} -+ -+/* and a handy shorthand for it */ -+static const HChar* nameCC ( ARM64Condcode cond ) { -+ return nameARM64Condcode(cond); -+} -+ -+ -+/* Build IR to calculate some particular condition from stored -+ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression of type -+ Ity_I64, suitable for narrowing. Although the return type is -+ Ity_I64, the returned value is either 0 or 1. 'cond' must be -+ :: Ity_I64 and must denote the condition to compute in -+ bits 7:4, and be zero everywhere else. -+*/ -+static IRExpr* mk_arm64g_calculate_condition_dyn ( IRExpr* cond ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I64); -+ /* And 'cond' had better produce a value in which only bits 7:4 are -+ nonzero. However, obviously we can't assert for that. */ -+ -+ /* So what we're constructing for the first argument is -+ "(cond << 4) | stored-operation". -+ However, as per comments above, 'cond' must be supplied -+ pre-shifted to this function. -+ -+ This pairing scheme requires that the ARM64_CC_OP_ values all fit -+ in 4 bits. Hence we are passing a (COND, OP) pair in the lowest -+ 8 bits of the first argument. */ -+ IRExpr** args -+ = mkIRExprVec_4( -+ binop(Iop_Or64, IRExpr_Get(OFFB_CC_OP, Ity_I64), cond), -+ IRExpr_Get(OFFB_CC_DEP1, Ity_I64), -+ IRExpr_Get(OFFB_CC_DEP2, Ity_I64), -+ IRExpr_Get(OFFB_CC_NDEP, Ity_I64) -+ ); -+ IRExpr* call -+ = mkIRExprCCall( -+ Ity_I64, -+ 0/*regparm*/, -+ "arm64g_calculate_condition", &arm64g_calculate_condition, -+ args -+ ); -+ -+ /* Exclude the requested condition, OP and NDEP from definedness -+ checking. We're only interested in DEP1 and DEP2. */ -+ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+ return call; -+} -+ -+ -+/* Build IR to calculate some particular condition from stored -+ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression of type -+ Ity_I64, suitable for narrowing. Although the return type is -+ Ity_I64, the returned value is either 0 or 1. -+*/ -+static IRExpr* mk_arm64g_calculate_condition ( ARM64Condcode cond ) -+{ -+ /* First arg is "(cond << 4) | condition". This requires that the -+ ARM64_CC_OP_ values all fit in 4 bits. Hence we are passing a -+ (COND, OP) pair in the lowest 8 bits of the first argument. */ -+ vassert(cond >= 0 && cond <= 15); -+ return mk_arm64g_calculate_condition_dyn( mkU64(cond << 4) ); -+} -+ -+ -+//ZZ /* Build IR to calculate just the carry flag from stored -+//ZZ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: -+//ZZ Ity_I32. */ -+//ZZ static IRExpr* mk_armg_calculate_flag_c ( void ) -+//ZZ { -+//ZZ IRExpr** args -+//ZZ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP1, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP2, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); -+//ZZ IRExpr* call -+//ZZ = mkIRExprCCall( -+//ZZ Ity_I32, -+//ZZ 0/*regparm*/, -+//ZZ "armg_calculate_flag_c", &armg_calculate_flag_c, -+//ZZ args -+//ZZ ); -+//ZZ /* Exclude OP and NDEP from definedness checking. We're only -+//ZZ interested in DEP1 and DEP2. */ -+//ZZ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+//ZZ return call; -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* Build IR to calculate just the overflow flag from stored -+//ZZ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: -+//ZZ Ity_I32. */ -+//ZZ static IRExpr* mk_armg_calculate_flag_v ( void ) -+//ZZ { -+//ZZ IRExpr** args -+//ZZ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP1, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP2, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); -+//ZZ IRExpr* call -+//ZZ = mkIRExprCCall( -+//ZZ Ity_I32, -+//ZZ 0/*regparm*/, -+//ZZ "armg_calculate_flag_v", &armg_calculate_flag_v, -+//ZZ args -+//ZZ ); -+//ZZ /* Exclude OP and NDEP from definedness checking. We're only -+//ZZ interested in DEP1 and DEP2. */ -+//ZZ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+//ZZ return call; -+//ZZ } -+ -+ -+/* Build IR to calculate N Z C V in bits 31:28 of the -+ returned word. */ -+static IRExpr* mk_arm64g_calculate_flags_nzcv ( void ) -+{ -+ IRExpr** args -+ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I64), -+ IRExpr_Get(OFFB_CC_DEP1, Ity_I64), -+ IRExpr_Get(OFFB_CC_DEP2, Ity_I64), -+ IRExpr_Get(OFFB_CC_NDEP, Ity_I64) ); -+ IRExpr* call -+ = mkIRExprCCall( -+ Ity_I64, -+ 0/*regparm*/, -+ "arm64g_calculate_flags_nzcv", &arm64g_calculate_flags_nzcv, -+ args -+ ); -+ /* Exclude OP and NDEP from definedness checking. We're only -+ interested in DEP1 and DEP2. */ -+ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+ return call; -+} -+ -+ -+/* Build IR to set the flags thunk, in the most general case. */ -+static -+void setFlags_D1_D2_ND ( UInt cc_op, -+ IRTemp t_dep1, IRTemp t_dep2, IRTemp t_ndep ) -+{ -+ vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I64)); -+ vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I64)); -+ vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I64)); -+ vassert(cc_op >= ARM64G_CC_OP_COPY && cc_op < ARM64G_CC_OP_NUMBER); -+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(cc_op) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(t_dep1) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkexpr(t_dep2) )); -+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(t_ndep) )); -+} -+ -+/* Build IR to set the flags thunk after ADD or SUB. */ -+static -+void setFlags_ADD_SUB ( Bool is64, Bool isSUB, IRTemp argL, IRTemp argR ) -+{ -+ IRTemp argL64 = IRTemp_INVALID; -+ IRTemp argR64 = IRTemp_INVALID; -+ IRTemp z64 = newTemp(Ity_I64); -+ if (is64) { -+ argL64 = argL; -+ argR64 = argR; -+ } else { -+ argL64 = newTemp(Ity_I64); -+ argR64 = newTemp(Ity_I64); -+ assign(argL64, unop(Iop_32Uto64, mkexpr(argL))); -+ assign(argR64, unop(Iop_32Uto64, mkexpr(argR))); -+ } -+ assign(z64, mkU64(0)); -+ UInt cc_op = ARM64G_CC_OP_NUMBER; -+ /**/ if ( isSUB && is64) { cc_op = ARM64G_CC_OP_SUB64; } -+ else if ( isSUB && !is64) { cc_op = ARM64G_CC_OP_SUB32; } -+ else if (!isSUB && is64) { cc_op = ARM64G_CC_OP_ADD64; } -+ else if (!isSUB && !is64) { cc_op = ARM64G_CC_OP_ADD32; } -+ else { vassert(0); } -+ setFlags_D1_D2_ND(cc_op, argL64, argR64, z64); -+} -+ -+/* Build IR to set the flags thunk after ADD or SUB, if the given -+ condition evaluates to True at run time. If not, the flags are set -+ to the specified NZCV value. */ -+static -+void setFlags_ADD_SUB_conditionally ( -+ Bool is64, Bool isSUB, -+ IRTemp cond, IRTemp argL, IRTemp argR, UInt nzcv -+ ) -+{ -+ /* Generate IR as follows: -+ CC_OP = ITE(cond, OP_{ADD,SUB}{32,64}, OP_COPY) -+ CC_DEP1 = ITE(cond, argL64, nzcv << 28) -+ CC_DEP2 = ITE(cond, argR64, 0) -+ CC_NDEP = 0 -+ */ -+ -+ IRTemp z64 = newTemp(Ity_I64); -+ assign(z64, mkU64(0)); -+ -+ /* Establish the operation and operands for the True case. */ -+ IRTemp t_dep1 = IRTemp_INVALID; -+ IRTemp t_dep2 = IRTemp_INVALID; -+ UInt t_op = ARM64G_CC_OP_NUMBER; -+ /**/ if ( isSUB && is64) { t_op = ARM64G_CC_OP_SUB64; } -+ else if ( isSUB && !is64) { t_op = ARM64G_CC_OP_SUB32; } -+ else if (!isSUB && is64) { t_op = ARM64G_CC_OP_ADD64; } -+ else if (!isSUB && !is64) { t_op = ARM64G_CC_OP_ADD32; } -+ else { vassert(0); } -+ /* */ -+ if (is64) { -+ t_dep1 = argL; -+ t_dep2 = argR; -+ } else { -+ t_dep1 = newTemp(Ity_I64); -+ t_dep2 = newTemp(Ity_I64); -+ assign(t_dep1, unop(Iop_32Uto64, mkexpr(argL))); -+ assign(t_dep2, unop(Iop_32Uto64, mkexpr(argR))); -+ } -+ -+ /* Establish the operation and operands for the False case. */ -+ IRTemp f_dep1 = newTemp(Ity_I64); -+ IRTemp f_dep2 = z64; -+ UInt f_op = ARM64G_CC_OP_COPY; -+ assign(f_dep1, mkU64(nzcv << 28)); -+ -+ /* Final thunk values */ -+ IRTemp dep1 = newTemp(Ity_I64); -+ IRTemp dep2 = newTemp(Ity_I64); -+ IRTemp op = newTemp(Ity_I64); -+ -+ assign(op, IRExpr_ITE(mkexpr(cond), mkU64(t_op), mkU64(f_op))); -+ assign(dep1, IRExpr_ITE(mkexpr(cond), mkexpr(t_dep1), mkexpr(f_dep1))); -+ assign(dep2, IRExpr_ITE(mkexpr(cond), mkexpr(t_dep2), mkexpr(f_dep2))); -+ -+ /* finally .. */ -+ stmt( IRStmt_Put( OFFB_CC_OP, mkexpr(op) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(dep1) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkexpr(dep2) )); -+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(z64) )); -+} -+ -+/* Build IR to set the flags thunk after AND/OR/XOR or variants thereof. */ -+static -+void setFlags_LOGIC ( Bool is64, IRTemp res ) -+{ -+ IRTemp res64 = IRTemp_INVALID; -+ IRTemp z64 = newTemp(Ity_I64); -+ UInt cc_op = ARM64G_CC_OP_NUMBER; -+ if (is64) { -+ res64 = res; -+ cc_op = ARM64G_CC_OP_LOGIC64; -+ } else { -+ res64 = newTemp(Ity_I64); -+ assign(res64, unop(Iop_32Uto64, mkexpr(res))); -+ cc_op = ARM64G_CC_OP_LOGIC32; -+ } -+ assign(z64, mkU64(0)); -+ setFlags_D1_D2_ND(cc_op, res64, z64, z64); -+} -+ -+/* Build IR to set the flags thunk to a given NZCV value. NZCV is -+ located in bits 31:28 of the supplied value. */ -+static -+void setFlags_COPY ( IRTemp nzcv_28x0 ) -+{ -+ IRTemp z64 = newTemp(Ity_I64); -+ assign(z64, mkU64(0)); -+ setFlags_D1_D2_ND(ARM64G_CC_OP_COPY, nzcv_28x0, z64, z64); -+} -+ -+ -+//ZZ /* Minor variant of the above that sets NDEP to zero (if it -+//ZZ sets it at all) */ -+//ZZ static void setFlags_D1_D2 ( UInt cc_op, IRTemp t_dep1, -+//ZZ IRTemp t_dep2, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ IRTemp z32 = newTemp(Ity_I32); -+//ZZ assign( z32, mkU32(0) ); -+//ZZ setFlags_D1_D2_ND( cc_op, t_dep1, t_dep2, z32, guardT ); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* Minor variant of the above that sets DEP2 to zero (if it -+//ZZ sets it at all) */ -+//ZZ static void setFlags_D1_ND ( UInt cc_op, IRTemp t_dep1, -+//ZZ IRTemp t_ndep, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ IRTemp z32 = newTemp(Ity_I32); -+//ZZ assign( z32, mkU32(0) ); -+//ZZ setFlags_D1_D2_ND( cc_op, t_dep1, z32, t_ndep, guardT ); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* Minor variant of the above that sets DEP2 and NDEP to zero (if it -+//ZZ sets them at all) */ -+//ZZ static void setFlags_D1 ( UInt cc_op, IRTemp t_dep1, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ IRTemp z32 = newTemp(Ity_I32); -+//ZZ assign( z32, mkU32(0) ); -+//ZZ setFlags_D1_D2_ND( cc_op, t_dep1, z32, z32, guardT ); -+//ZZ } -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Misc math helpers ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Generates a 64-bit byte swap. */ -+static IRTemp math_BSWAP64 ( IRTemp t1 ) -+{ -+ IRTemp t2 = newTemp(Ity_I64); -+ IRTemp m8 = newTemp(Ity_I64); -+ IRTemp s8 = newTemp(Ity_I64); -+ IRTemp m16 = newTemp(Ity_I64); -+ IRTemp s16 = newTemp(Ity_I64); -+ IRTemp m32 = newTemp(Ity_I64); -+ assign( m8, mkU64(0xFF00FF00FF00FF00ULL) ); -+ assign( s8, -+ binop(Iop_Or64, -+ binop(Iop_Shr64, -+ binop(Iop_And64,mkexpr(t1),mkexpr(m8)), -+ mkU8(8)), -+ binop(Iop_And64, -+ binop(Iop_Shl64,mkexpr(t1),mkU8(8)), -+ mkexpr(m8)) -+ ) -+ ); -+ -+ assign( m16, mkU64(0xFFFF0000FFFF0000ULL) ); -+ assign( s16, -+ binop(Iop_Or64, -+ binop(Iop_Shr64, -+ binop(Iop_And64,mkexpr(s8),mkexpr(m16)), -+ mkU8(16)), -+ binop(Iop_And64, -+ binop(Iop_Shl64,mkexpr(s8),mkU8(16)), -+ mkexpr(m16)) -+ ) -+ ); -+ -+ assign( m32, mkU64(0xFFFFFFFF00000000ULL) ); -+ assign( t2, -+ binop(Iop_Or64, -+ binop(Iop_Shr64, -+ binop(Iop_And64,mkexpr(s16),mkexpr(m32)), -+ mkU8(32)), -+ binop(Iop_And64, -+ binop(Iop_Shl64,mkexpr(s16),mkU8(32)), -+ mkexpr(m32)) -+ ) -+ ); -+ return t2; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- FP comparison helpers ---*/ -+/*------------------------------------------------------------*/ -+ -+/* irRes :: Ity_I32 holds a floating point comparison result encoded -+ as an IRCmpF64Result. Generate code to convert it to an -+ ARM64-encoded (N,Z,C,V) group in the lowest 4 bits of an I64 value. -+ Assign a new temp to hold that value, and return the temp. */ -+static -+IRTemp mk_convert_IRCmpF64Result_to_NZCV ( IRTemp irRes32 ) -+{ -+ IRTemp ix = newTemp(Ity_I64); -+ IRTemp termL = newTemp(Ity_I64); -+ IRTemp termR = newTemp(Ity_I64); -+ IRTemp nzcv = newTemp(Ity_I64); -+ IRTemp irRes = newTemp(Ity_I64); -+ -+ /* This is where the fun starts. We have to convert 'irRes' from -+ an IR-convention return result (IRCmpF64Result) to an -+ ARM-encoded (N,Z,C,V) group. The final result is in the bottom -+ 4 bits of 'nzcv'. */ -+ /* Map compare result from IR to ARM(nzcv) */ -+ /* -+ FP cmp result | IR | ARM(nzcv) -+ -------------------------------- -+ UN 0x45 0011 -+ LT 0x01 1000 -+ GT 0x00 0010 -+ EQ 0x40 0110 -+ */ -+ /* Now since you're probably wondering WTF .. -+ -+ ix fishes the useful bits out of the IR value, bits 6 and 0, and -+ places them side by side, giving a number which is 0, 1, 2 or 3. -+ -+ termL is a sequence cooked up by GNU superopt. It converts ix -+ into an almost correct value NZCV value (incredibly), except -+ for the case of UN, where it produces 0100 instead of the -+ required 0011. -+ -+ termR is therefore a correction term, also computed from ix. It -+ is 1 in the UN case and 0 for LT, GT and UN. Hence, to get -+ the final correct value, we subtract termR from termL. -+ -+ Don't take my word for it. There's a test program at the bottom -+ of guest_arm_toIR.c, to try this out with. -+ */ -+ assign(irRes, unop(Iop_32Uto64, mkexpr(irRes32))); -+ -+ assign( -+ ix, -+ binop(Iop_Or64, -+ binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(irRes), mkU8(5)), -+ mkU64(3)), -+ binop(Iop_And64, mkexpr(irRes), mkU64(1)))); -+ -+ assign( -+ termL, -+ binop(Iop_Add64, -+ binop(Iop_Shr64, -+ binop(Iop_Sub64, -+ binop(Iop_Shl64, -+ binop(Iop_Xor64, mkexpr(ix), mkU64(1)), -+ mkU8(62)), -+ mkU64(1)), -+ mkU8(61)), -+ mkU64(1))); -+ -+ assign( -+ termR, -+ binop(Iop_And64, -+ binop(Iop_And64, -+ mkexpr(ix), -+ binop(Iop_Shr64, mkexpr(ix), mkU8(1))), -+ mkU64(1))); -+ -+ assign(nzcv, binop(Iop_Sub64, mkexpr(termL), mkexpr(termR))); -+ return nzcv; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Data processing (immediate) ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Helper functions for supporting "DecodeBitMasks" */ -+ -+static ULong dbm_ROR ( Int width, ULong x, Int rot ) -+{ -+ vassert(width > 0 && width <= 64); -+ vassert(rot >= 0 && rot < width); -+ if (rot == 0) return x; -+ ULong res = x >> rot; -+ res |= (x << (width - rot)); -+ if (width < 64) -+ res &= ((1ULL << width) - 1); -+ return res; -+} -+ -+static ULong dbm_RepTo64( Int esize, ULong x ) -+{ -+ switch (esize) { -+ case 64: -+ return x; -+ case 32: -+ x &= 0xFFFFFFFF; x |= (x << 32); -+ return x; -+ case 16: -+ x &= 0xFFFF; x |= (x << 16); x |= (x << 32); -+ return x; -+ case 8: -+ x &= 0xFF; x |= (x << 8); x |= (x << 16); x |= (x << 32); -+ return x; -+ case 4: -+ x &= 0xF; x |= (x << 4); x |= (x << 8); -+ x |= (x << 16); x |= (x << 32); -+ return x; -+ case 2: -+ x &= 0x3; x |= (x << 2); x |= (x << 4); x |= (x << 8); -+ x |= (x << 16); x |= (x << 32); -+ return x; -+ default: -+ break; -+ } -+ vpanic("dbm_RepTo64"); -+ /*NOTREACHED*/ -+ return 0; -+} -+ -+static Int dbm_highestSetBit ( ULong x ) -+{ -+ Int i; -+ for (i = 63; i >= 0; i--) { -+ if (x & (1ULL << i)) -+ return i; -+ } -+ vassert(x == 0); -+ return -1; -+} -+ -+static -+Bool dbm_DecodeBitMasks ( /*OUT*/ULong* wmask, /*OUT*/ULong* tmask, -+ ULong immN, ULong imms, ULong immr, Bool immediate, -+ UInt M /*32 or 64*/) -+{ -+ vassert(immN < (1ULL << 1)); -+ vassert(imms < (1ULL << 6)); -+ vassert(immr < (1ULL << 6)); -+ vassert(immediate == False || immediate == True); -+ vassert(M == 32 || M == 64); -+ -+ Int len = dbm_highestSetBit( ((immN << 6) & 64) | ((~imms) & 63) ); -+ if (len < 1) { /* printf("fail1\n"); */ return False; } -+ vassert(len <= 6); -+ vassert(M >= (1 << len)); -+ -+ vassert(len >= 1 && len <= 6); -+ ULong levels = // (zeroes(6 - len) << (6-len)) | ones(len); -+ (1 << len) - 1; -+ vassert(levels >= 1 && levels <= 63); -+ -+ if (immediate && ((imms & levels) == levels)) { -+ /* printf("fail2 imms %llu levels %llu len %d\n", imms, levels, len); */ -+ return False; -+ } -+ -+ ULong S = imms & levels; -+ ULong R = immr & levels; -+ Int diff = S - R; -+ diff &= 63; -+ Int esize = 1 << len; -+ vassert(2 <= esize && esize <= 64); -+ -+ /* Be careful of these (1ULL << (S+1)) - 1 expressions, and the -+ same below with d. S can be 63 in which case we have an out of -+ range and hence undefined shift. */ -+ vassert(S >= 0 && S <= 63); -+ vassert(esize >= (S+1)); -+ ULong elem_s = // Zeroes(esize-(S+1)):Ones(S+1) -+ //(1ULL << (S+1)) - 1; -+ ((1ULL << S) - 1) + (1ULL << S); -+ -+ Int d = // diff -+ diff & ((1 << len)-1); -+ vassert(esize >= (d+1)); -+ vassert(d >= 0 && d <= 63); -+ -+ ULong elem_d = // Zeroes(esize-(d+1)):Ones(d+1) -+ //(1ULL << (d+1)) - 1; -+ ((1ULL << d) - 1) + (1ULL << d); -+ -+ if (esize != 64) vassert(elem_s < (1ULL << esize)); -+ if (esize != 64) vassert(elem_d < (1ULL << esize)); -+ -+ if (wmask) *wmask = dbm_RepTo64(esize, dbm_ROR(esize, elem_s, R)); -+ if (tmask) *tmask = dbm_RepTo64(esize, elem_d); -+ -+ return True; -+} -+ -+ -+static -+Bool dis_ARM64_data_processing_immediate(/*MB_OUT*/DisResult* dres, -+ UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* insn[28:23] -+ 10000x PC-rel addressing -+ 10001x Add/subtract (immediate) -+ 100100 Logical (immediate) -+ 100101 Move Wide (immediate) -+ 100110 Bitfield -+ 100111 Extract -+ */ -+ -+ /* ------------------ ADD/SUB{,S} imm12 ------------------ */ -+ if (INSN(28,24) == BITS5(1,0,0,0,1)) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSub = INSN(30,30) == 1; -+ Bool setCC = INSN(29,29) == 1; -+ UInt sh = INSN(23,22); -+ UInt uimm12 = INSN(21,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ const HChar* nm = isSub ? "sub" : "add"; -+ if (sh >= 2) { -+ /* Invalid; fall through */ -+ } else { -+ vassert(sh <= 1); -+ uimm12 <<= (12 * sh); -+ if (is64) { -+ IRTemp argL = newTemp(Ity_I64); -+ IRTemp argR = newTemp(Ity_I64); -+ IRTemp res = newTemp(Ity_I64); -+ assign(argL, getIReg64orSP(nn)); -+ assign(argR, mkU64(uimm12)); -+ assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64, -+ mkexpr(argL), mkexpr(argR))); -+ if (setCC) { -+ putIReg64orZR(dd, mkexpr(res)); -+ setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR); -+ DIP("%ss %s, %s, 0x%x\n", -+ nm, nameIReg64orZR(dd), nameIReg64orSP(nn), uimm12); -+ } else { -+ putIReg64orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%x\n", -+ nm, nameIReg64orSP(dd), nameIReg64orSP(nn), uimm12); -+ } -+ } else { -+ IRTemp argL = newTemp(Ity_I32); -+ IRTemp argR = newTemp(Ity_I32); -+ IRTemp res = newTemp(Ity_I32); -+ assign(argL, getIReg32orSP(nn)); -+ assign(argR, mkU32(uimm12)); -+ assign(res, binop(isSub ? Iop_Sub32 : Iop_Add32, -+ mkexpr(argL), mkexpr(argR))); -+ if (setCC) { -+ putIReg32orZR(dd, mkexpr(res)); -+ setFlags_ADD_SUB(False/*!is64*/, isSub, argL, argR); -+ DIP("%ss %s, %s, 0x%x\n", -+ nm, nameIReg32orZR(dd), nameIReg32orSP(nn), uimm12); -+ } else { -+ putIReg32orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%x\n", -+ nm, nameIReg32orSP(dd), nameIReg32orSP(nn), uimm12); -+ } -+ } -+ return True; -+ } -+ } -+ -+ /* -------------------- ADR/ADRP -------------------- */ -+ if (INSN(28,24) == BITS5(1,0,0,0,0)) { -+ UInt bP = INSN(31,31); -+ UInt immLo = INSN(30,29); -+ UInt immHi = INSN(23,5); -+ UInt rD = INSN(4,0); -+ ULong uimm = (immHi << 2) | immLo; -+ ULong simm = sx_to_64(uimm, 21); -+ ULong val; -+ if (bP) { -+ val = (guest_PC_curr_instr & 0xFFFFFFFFFFFFF000ULL) + (simm << 12); -+ } else { -+ val = guest_PC_curr_instr + simm; -+ } -+ putIReg64orZR(rD, mkU64(val)); -+ DIP("adr%s %s, 0x%llx\n", bP ? "p" : "", nameIReg64orZR(rD), val); -+ return True; -+ } -+ -+ /* -------------------- LOGIC(imm) -------------------- */ -+ if (INSN(28,23) == BITS6(1,0,0,1,0,0)) { -+ /* 31 30 28 22 21 15 9 4 -+ sf op 100100 N immr imms Rn Rd -+ op=00: AND Rd|SP, Rn, #imm -+ op=01: ORR Rd|SP, Rn, #imm -+ op=10: EOR Rd|SP, Rn, #imm -+ op=11: ANDS Rd|ZR, Rn, #imm -+ */ -+ Bool is64 = INSN(31,31) == 1; -+ UInt op = INSN(30,29); -+ UInt N = INSN(22,22); -+ UInt immR = INSN(21,16); -+ UInt immS = INSN(15,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ ULong imm = 0; -+ Bool ok; -+ if (N == 1 && !is64) -+ goto after_logic_imm; /* not allowed; fall through */ -+ ok = dbm_DecodeBitMasks(&imm, NULL, -+ N, immS, immR, True, is64 ? 64 : 32); -+ if (!ok) -+ goto after_logic_imm; -+ -+ const HChar* names[4] = { "and", "orr", "eor", "ands" }; -+ const IROp ops64[4] = { Iop_And64, Iop_Or64, Iop_Xor64, Iop_And64 }; -+ const IROp ops32[4] = { Iop_And32, Iop_Or32, Iop_Xor32, Iop_And32 }; -+ -+ vassert(op < 4); -+ if (is64) { -+ IRExpr* argL = getIReg64orZR(nn); -+ IRExpr* argR = mkU64(imm); -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, binop(ops64[op], argL, argR)); -+ if (op < 3) { -+ putIReg64orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%llx\n", names[op], -+ nameIReg64orSP(dd), nameIReg64orZR(nn), imm); -+ } else { -+ putIReg64orZR(dd, mkexpr(res)); -+ setFlags_LOGIC(True/*is64*/, res); -+ DIP("%s %s, %s, 0x%llx\n", names[op], -+ nameIReg64orZR(dd), nameIReg64orZR(nn), imm); -+ } -+ } else { -+ IRExpr* argL = getIReg32orZR(nn); -+ IRExpr* argR = mkU32((UInt)imm); -+ IRTemp res = newTemp(Ity_I32); -+ assign(res, binop(ops32[op], argL, argR)); -+ if (op < 3) { -+ putIReg32orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%x\n", names[op], -+ nameIReg32orSP(dd), nameIReg32orZR(nn), (UInt)imm); -+ } else { -+ putIReg32orZR(dd, mkexpr(res)); -+ setFlags_LOGIC(False/*!is64*/, res); -+ DIP("%s %s, %s, 0x%x\n", names[op], -+ nameIReg32orZR(dd), nameIReg32orZR(nn), (UInt)imm); -+ } -+ } -+ return True; -+ } -+ after_logic_imm: -+ -+ /* -------------------- MOV{Z,N,K} -------------------- */ -+ if (INSN(28,23) == BITS6(1,0,0,1,0,1)) { -+ /* 31 30 28 22 20 4 -+ | | | | | | -+ sf 10 100 101 hw imm16 Rd MOV(Z) Rd, (imm16 << (16*hw)) -+ sf 00 100 101 hw imm16 Rd MOV(N) Rd, ~(imm16 << (16*hw)) -+ sf 11 100 101 hw imm16 Rd MOV(K) Rd, (imm16 << (16*hw)) -+ */ -+ Bool is64 = INSN(31,31) == 1; -+ UInt subopc = INSN(30,29); -+ UInt hw = INSN(22,21); -+ UInt imm16 = INSN(20,5); -+ UInt dd = INSN(4,0); -+ if (subopc == BITS2(0,1) || (!is64 && hw >= 2)) { -+ /* invalid; fall through */ -+ } else { -+ ULong imm64 = ((ULong)imm16) << (16 * hw); -+ if (!is64) -+ vassert(imm64 < 0x100000000ULL); -+ switch (subopc) { -+ case BITS2(1,0): // MOVZ -+ putIRegOrZR(is64, dd, is64 ? mkU64(imm64) : mkU32((UInt)imm64)); -+ DIP("movz %s, 0x%llx\n", nameIRegOrZR(is64, dd), imm64); -+ break; -+ case BITS2(0,0): // MOVN -+ imm64 = ~imm64; -+ if (!is64) -+ imm64 &= 0xFFFFFFFFULL; -+ putIRegOrZR(is64, dd, is64 ? mkU64(imm64) : mkU32((UInt)imm64)); -+ DIP("movn %s, 0x%llx\n", nameIRegOrZR(is64, dd), imm64); -+ break; -+ case BITS2(1,1): // MOVK -+ /* This is more complex. We are inserting a slice into -+ the destination register, so we need to have the old -+ value of it. */ -+ if (is64) { -+ IRTemp old = newTemp(Ity_I64); -+ assign(old, getIReg64orZR(dd)); -+ ULong mask = 0xFFFFULL << (16 * hw); -+ IRExpr* res -+ = binop(Iop_Or64, -+ binop(Iop_And64, mkexpr(old), mkU64(~mask)), -+ mkU64(imm64)); -+ putIReg64orZR(dd, res); -+ DIP("movk %s, 0x%x, lsl %u\n", -+ nameIReg64orZR(dd), imm16, 16*hw); -+ } else { -+ IRTemp old = newTemp(Ity_I32); -+ assign(old, getIReg32orZR(dd)); -+ vassert(hw <= 1); -+ UInt mask = 0xFFFF << (16 * hw); -+ IRExpr* res -+ = binop(Iop_Or32, -+ binop(Iop_And32, mkexpr(old), mkU32(~mask)), -+ mkU32((UInt)imm64)); -+ putIReg32orZR(dd, res); -+ DIP("movk %s, 0x%x, lsl %u\n", -+ nameIReg32orZR(dd), imm16, 16*hw); -+ } -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ } -+ -+ /* -------------------- {U,S,}BFM -------------------- */ -+ /* 30 28 22 21 15 9 4 -+ -+ sf 10 100110 N immr imms nn dd -+ UBFM Wd, Wn, #immr, #imms when sf=0, N=0, immr[5]=0, imms[5]=0 -+ UBFM Xd, Xn, #immr, #imms when sf=1, N=1 -+ -+ sf 00 100110 N immr imms nn dd -+ SBFM Wd, Wn, #immr, #imms when sf=0, N=0, immr[5]=0, imms[5]=0 -+ SBFM Xd, Xn, #immr, #imms when sf=1, N=1 -+ -+ sf 01 100110 N immr imms nn dd -+ BFM Wd, Wn, #immr, #imms when sf=0, N=0, immr[5]=0, imms[5]=0 -+ BFM Xd, Xn, #immr, #imms when sf=1, N=1 -+ */ -+ if (INSN(28,23) == BITS6(1,0,0,1,1,0)) { -+ UInt sf = INSN(31,31); -+ UInt opc = INSN(30,29); -+ UInt N = INSN(22,22); -+ UInt immR = INSN(21,16); -+ UInt immS = INSN(15,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool inZero = False; -+ Bool extend = False; -+ const HChar* nm = "???"; -+ /* skip invalid combinations */ -+ switch (opc) { -+ case BITS2(0,0): -+ inZero = True; extend = True; nm = "sbfm"; break; -+ case BITS2(0,1): -+ inZero = False; extend = False; nm = "bfm"; break; -+ case BITS2(1,0): -+ inZero = True; extend = False; nm = "ubfm"; break; -+ case BITS2(1,1): -+ goto after_bfm; /* invalid */ -+ default: -+ vassert(0); -+ } -+ if (sf == 1 && N != 1) goto after_bfm; -+ if (sf == 0 && (N != 0 || ((immR >> 5) & 1) != 0 -+ || ((immS >> 5) & 1) != 0)) goto after_bfm; -+ ULong wmask = 0, tmask = 0; -+ Bool ok = dbm_DecodeBitMasks(&wmask, &tmask, -+ N, immS, immR, False, sf == 1 ? 64 : 32); -+ if (!ok) goto after_bfm; /* hmmm */ -+ -+ Bool is64 = sf == 1; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ -+ IRTemp dst = newTemp(ty); -+ IRTemp src = newTemp(ty); -+ IRTemp bot = newTemp(ty); -+ IRTemp top = newTemp(ty); -+ IRTemp res = newTemp(ty); -+ assign(dst, inZero ? mkU(ty,0) : getIRegOrZR(is64, dd)); -+ assign(src, getIRegOrZR(is64, nn)); -+ /* perform bitfield move on low bits */ -+ assign(bot, binop(mkOR(ty), -+ binop(mkAND(ty), mkexpr(dst), mkU(ty, ~wmask)), -+ binop(mkAND(ty), mkexpr(mathROR(ty, src, immR)), -+ mkU(ty, wmask)))); -+ /* determine extension bits (sign, zero or dest register) */ -+ assign(top, mkexpr(extend ? mathREPLICATE(ty, src, immS) : dst)); -+ /* combine extension bits and result bits */ -+ assign(res, binop(mkOR(ty), -+ binop(mkAND(ty), mkexpr(top), mkU(ty, ~tmask)), -+ binop(mkAND(ty), mkexpr(bot), mkU(ty, tmask)))); -+ putIRegOrZR(is64, dd, mkexpr(res)); -+ DIP("%s %s, %s, immR=%u, immS=%u\n", -+ nm, nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), immR, immS); -+ return True; -+ } -+ after_bfm: -+ -+ /* ---------------------- EXTR ---------------------- */ -+ /* 30 28 22 20 15 9 4 -+ 1 00 100111 10 m imm6 n d EXTR Xd, Xn, Xm, #imm6 -+ 0 00 100111 00 m imm6 n d EXTR Wd, Wn, Wm, #imm6 when #imm6 < 32 -+ */ -+ if (INSN(30,23) == BITS8(0,0,1,0,0,1,1,1) && INSN(21,21) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ UInt imm6 = INSN(15,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool valid = True; -+ if (INSN(31,31) != INSN(22,22)) -+ valid = False; -+ if (!is64 && imm6 >= 32) -+ valid = False; -+ if (!valid) goto after_extr; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp srcHi = newTemp(ty); -+ IRTemp srcLo = newTemp(ty); -+ IRTemp res = newTemp(ty); -+ assign(srcHi, getIRegOrZR(is64, nn)); -+ assign(srcLo, getIRegOrZR(is64, mm)); -+ if (imm6 == 0) { -+ assign(res, mkexpr(srcLo)); -+ } else { -+ UInt szBits = 8 * sizeofIRType(ty); -+ vassert(imm6 > 0 && imm6 < szBits); -+ assign(res, binop(mkOR(ty), -+ binop(mkSHL(ty), mkexpr(srcHi), mkU8(szBits-imm6)), -+ binop(mkSHR(ty), mkexpr(srcLo), mkU8(imm6)))); -+ } -+ putIRegOrZR(is64, dd, mkexpr(res)); -+ DIP("extr %s, %s, %s, #%u\n", -+ nameIRegOrZR(is64,dd), -+ nameIRegOrZR(is64,nn), nameIRegOrZR(is64,mm), imm6); -+ return True; -+ } -+ after_extr: -+ -+ vex_printf("ARM64 front end: data_processing_immediate\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Data processing (register) instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+static const HChar* nameSH ( UInt sh ) { -+ switch (sh) { -+ case 0: return "lsl"; -+ case 1: return "lsr"; -+ case 2: return "asr"; -+ case 3: return "ror"; -+ default: vassert(0); -+ } -+} -+ -+/* Generate IR to get a register value, possibly shifted by an -+ immediate. Returns either a 32- or 64-bit temporary holding the -+ result. After the shift, the value can optionally be NOT-ed -+ too. -+ -+ sh_how coding: 00=SHL, 01=SHR, 10=SAR, 11=ROR. sh_amt may only be -+ in the range 0 to (is64 ? 64 : 32)-1. For some instructions, ROR -+ isn't allowed, but it's the job of the caller to check that. -+*/ -+static IRTemp getShiftedIRegOrZR ( Bool is64, -+ UInt sh_how, UInt sh_amt, UInt regNo, -+ Bool invert ) -+{ -+ vassert(sh_how < 4); -+ vassert(sh_amt < (is64 ? 64 : 32)); -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp t0 = newTemp(ty); -+ assign(t0, getIRegOrZR(is64, regNo)); -+ IRTemp t1 = newTemp(ty); -+ switch (sh_how) { -+ case BITS2(0,0): -+ assign(t1, binop(mkSHL(ty), mkexpr(t0), mkU8(sh_amt))); -+ break; -+ case BITS2(0,1): -+ assign(t1, binop(mkSHR(ty), mkexpr(t0), mkU8(sh_amt))); -+ break; -+ case BITS2(1,0): -+ assign(t1, binop(mkSAR(ty), mkexpr(t0), mkU8(sh_amt))); -+ break; -+ case BITS2(1,1): -+ assign(t1, mkexpr(mathROR(ty, t0, sh_amt))); -+ break; -+ default: -+ vassert(0); -+ } -+ if (invert) { -+ IRTemp t2 = newTemp(ty); -+ assign(t2, unop(mkNOT(ty), mkexpr(t1))); -+ return t2; -+ } else { -+ return t1; -+ } -+} -+ -+ -+static -+Bool dis_ARM64_data_processing_register(/*MB_OUT*/DisResult* dres, -+ UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ------------------- ADD/SUB(reg) ------------------- */ -+ /* x==0 => 32 bit op x==1 => 64 bit op -+ sh: 00=LSL, 01=LSR, 10=ASR, 11=ROR(NOT ALLOWED) -+ -+ 31 30 29 28 23 21 20 15 9 4 -+ | | | | | | | | | | -+ x 0 0 01011 sh 0 Rm imm6 Rn Rd ADD Rd,Rn, sh(Rm,imm6) -+ x 0 1 01011 sh 0 Rm imm6 Rn Rd ADDS Rd,Rn, sh(Rm,imm6) -+ x 1 0 01011 sh 0 Rm imm6 Rn Rd SUB Rd,Rn, sh(Rm,imm6) -+ x 1 1 01011 sh 0 Rm imm6 Rn Rd SUBS Rd,Rn, sh(Rm,imm6) -+ */ -+ if (INSN(28,24) == BITS5(0,1,0,1,1) && INSN(21,21) == 0) { -+ UInt bX = INSN(31,31); -+ UInt bOP = INSN(30,30); /* 0: ADD, 1: SUB */ -+ UInt bS = INSN(29, 29); /* set flags? */ -+ UInt sh = INSN(23,22); -+ UInt rM = INSN(20,16); -+ UInt imm6 = INSN(15,10); -+ UInt rN = INSN(9,5); -+ UInt rD = INSN(4,0); -+ Bool isSUB = bOP == 1; -+ Bool is64 = bX == 1; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ if ((!is64 && imm6 > 31) || sh == BITS2(1,1)) { -+ /* invalid; fall through */ -+ } else { -+ IRTemp argL = newTemp(ty); -+ assign(argL, getIRegOrZR(is64, rN)); -+ IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, False); -+ IROp op = isSUB ? mkSUB(ty) : mkADD(ty); -+ IRTemp res = newTemp(ty); -+ assign(res, binop(op, mkexpr(argL), mkexpr(argR))); -+ if (rD != 31) putIRegOrZR(is64, rD, mkexpr(res)); -+ if (bS) { -+ setFlags_ADD_SUB(is64, isSUB, argL, argR); -+ } -+ DIP("%s%s %s, %s, %s, %s #%u\n", -+ bOP ? "sub" : "add", bS ? "s" : "", -+ nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), -+ nameIRegOrZR(is64, rM), nameSH(sh), imm6); -+ return True; -+ } -+ } -+ -+ /* -------------------- LOGIC(reg) -------------------- */ -+ /* x==0 => 32 bit op x==1 => 64 bit op -+ N==0 => inv? is no-op (no inversion) -+ N==1 => inv? is NOT -+ sh: 00=LSL, 01=LSR, 10=ASR, 11=ROR -+ -+ 31 30 28 23 21 20 15 9 4 -+ | | | | | | | | | -+ x 00 01010 sh N Rm imm6 Rn Rd AND Rd,Rn, inv?(sh(Rm,imm6)) -+ x 01 01010 sh N Rm imm6 Rn Rd ORR Rd,Rn, inv?(sh(Rm,imm6)) -+ x 10 01010 sh N Rm imm6 Rn Rd EOR Rd,Rn, inv?(sh(Rm,imm6)) -+ x 11 01010 sh N Rm imm6 Rn Rd ANDS Rd,Rn, inv?(sh(Rm,imm6)) -+ With N=1, the names are: BIC ORN EON BICS -+ */ -+ if (INSN(28,24) == BITS5(0,1,0,1,0)) { -+ UInt bX = INSN(31,31); -+ UInt sh = INSN(23,22); -+ UInt bN = INSN(21,21); -+ UInt rM = INSN(20,16); -+ UInt imm6 = INSN(15,10); -+ UInt rN = INSN(9,5); -+ UInt rD = INSN(4,0); -+ Bool is64 = bX == 1; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ if (!is64 && imm6 > 31) { -+ /* invalid; fall though */ -+ } else { -+ IRTemp argL = newTemp(ty); -+ assign(argL, getIRegOrZR(is64, rN)); -+ IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, bN == 1); -+ IROp op = Iop_INVALID; -+ switch (INSN(30,29)) { -+ case BITS2(0,0): case BITS2(1,1): op = mkAND(ty); break; -+ case BITS2(0,1): op = mkOR(ty); break; -+ case BITS2(1,0): op = mkXOR(ty); break; -+ default: vassert(0); -+ } -+ IRTemp res = newTemp(ty); -+ assign(res, binop(op, mkexpr(argL), mkexpr(argR))); -+ if (INSN(30,29) == BITS2(1,1)) { -+ setFlags_LOGIC(is64, res); -+ } -+ putIRegOrZR(is64, rD, mkexpr(res)); -+ -+ static const HChar* names_op[8] -+ = { "and", "orr", "eor", "ands", "bic", "orn", "eon", "bics" }; -+ vassert(((bN << 2) | INSN(30,29)) < 8); -+ const HChar* nm_op = names_op[(bN << 2) | INSN(30,29)]; -+ /* Special-case the printing of "MOV" */ -+ if (rN == 31/*zr*/ && sh == 0/*LSL*/ && imm6 == 0 && bN == 0) { -+ DIP("mov %s, %s\n", nameIRegOrZR(is64, rD), -+ nameIRegOrZR(is64, rM)); -+ } else { -+ DIP("%s %s, %s, %s, %s #%u\n", nm_op, -+ nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), -+ nameIRegOrZR(is64, rM), nameSH(sh), imm6); -+ } -+ return True; -+ } -+ } -+ -+ /* -------------------- {U,S}MULH -------------------- */ -+ /* 31 23 22 20 15 9 4 -+ 10011011 1 10 Rm 011111 Rn Rd UMULH Xd,Xn,Xm -+ 10011011 0 10 Rm 011111 Rn Rd SMULH Xd,Xn,Xm -+ */ -+ if (INSN(31,24) == BITS8(1,0,0,1,1,0,1,1) -+ && INSN(22,21) == BITS2(1,0) && INSN(15,10) == BITS6(0,1,1,1,1,1) -+ && INSN(23,23) == 1/*ATC*/) { -+ Bool isU = INSN(23,23) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ putIReg64orZR(dd, unop(Iop_128HIto64, -+ binop(isU ? Iop_MullU64 : Iop_MullS64, -+ getIReg64orZR(nn), getIReg64orZR(mm)))); -+ DIP("%cmulh %s, %s, %s\n", -+ isU ? 'u' : 's', -+ nameIReg64orZR(dd), nameIReg64orZR(nn), nameIReg64orZR(mm)); -+ return True; -+ } -+ -+ /* -------------------- M{ADD,SUB} -------------------- */ -+ /* 31 30 20 15 14 9 4 -+ sf 00 11011 000 m 0 a n r MADD Rd,Rn,Rm,Ra d = a+m*n -+ sf 00 11011 000 m 1 a n r MADD Rd,Rn,Rm,Ra d = a-m*n -+ */ -+ if (INSN(30,21) == BITS10(0,0,1,1,0,1,1,0,0,0)) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ Bool isAdd = INSN(15,15) == 0; -+ UInt aa = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (is64) { -+ putIReg64orZR( -+ dd, -+ binop(isAdd ? Iop_Add64 : Iop_Sub64, -+ getIReg64orZR(aa), -+ binop(Iop_Mul64, getIReg64orZR(mm), getIReg64orZR(nn)))); -+ } else { -+ putIReg32orZR( -+ dd, -+ binop(isAdd ? Iop_Add32 : Iop_Sub32, -+ getIReg32orZR(aa), -+ binop(Iop_Mul32, getIReg32orZR(mm), getIReg32orZR(nn)))); -+ } -+ DIP("%s %s, %s, %s, %s\n", -+ isAdd ? "madd" : "msub", -+ nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), -+ nameIRegOrZR(is64, mm), nameIRegOrZR(is64, aa)); -+ return True; -+ } -+ -+ /* ---------------- CS{EL,INC,INV,NEG} ---------------- */ -+ /* 31 30 28 20 15 11 9 4 -+ sf 00 1101 0100 mm cond 00 nn dd CSEL Rd,Rn,Rm -+ sf 00 1101 0100 mm cond 01 nn dd CSINC Rd,Rn,Rm -+ sf 10 1101 0100 mm cond 00 nn dd CSINV Rd,Rn,Rm -+ sf 10 1101 0100 mm cond 01 nn dd CSNEG Rd,Rn,Rm -+ In all cases, the operation is: Rd = if cond then Rn else OP(Rm) -+ */ -+ if (INSN(29,21) == BITS9(0, 1,1,0,1, 0,1,0,0) && INSN(11,11) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt b30 = INSN(30,30); -+ UInt mm = INSN(20,16); -+ UInt cond = INSN(15,12); -+ UInt b10 = INSN(10,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt op = (b30 << 1) | b10; /* 00=id 01=inc 10=inv 11=neg */ -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRExpr* argL = getIRegOrZR(is64, nn); -+ IRExpr* argR = getIRegOrZR(is64, mm); -+ switch (op) { -+ case BITS2(0,0): -+ break; -+ case BITS2(0,1): -+ argR = binop(mkADD(ty), argR, mkU(ty,1)); -+ break; -+ case BITS2(1,0): -+ argR = unop(mkNOT(ty), argR); -+ break; -+ case BITS2(1,1): -+ argR = binop(mkSUB(ty), mkU(ty,0), argR); -+ break; -+ default: -+ vassert(0); -+ } -+ putIRegOrZR( -+ is64, dd, -+ IRExpr_ITE(unop(Iop_64to1, mk_arm64g_calculate_condition(cond)), -+ argL, argR) -+ ); -+ const HChar* op_nm[4] = { "csel", "csinc", "csinv", "csneg" }; -+ DIP("%s %s, %s, %s, %s\n", op_nm[op], -+ nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), -+ nameIRegOrZR(is64, mm), nameCC(cond)); -+ return True; -+ } -+ -+ /* -------------- ADD/SUB(extended reg) -------------- */ -+ /* 28 20 15 12 9 4 -+ 000 01011 00 1 m opt imm3 n d ADD Wd|SP, Wn|SP, Wm ext&lsld -+ 100 01011 00 1 m opt imm3 n d ADD Xd|SP, Xn|SP, Rm ext&lsld -+ -+ 001 01011 00 1 m opt imm3 n d ADDS Wd, Wn|SP, Wm ext&lsld -+ 101 01011 00 1 m opt imm3 n d ADDS Xd, Xn|SP, Rm ext&lsld -+ -+ 010 01011 00 1 m opt imm3 n d SUB Wd|SP, Wn|SP, Wm ext&lsld -+ 110 01011 00 1 m opt imm3 n d SUB Xd|SP, Xn|SP, Rm ext&lsld -+ -+ 011 01011 00 1 m opt imm3 n d SUBS Wd, Wn|SP, Wm ext&lsld -+ 111 01011 00 1 m opt imm3 n d SUBS Xd, Xn|SP, Rm ext&lsld -+ -+ The 'm' operand is extended per opt, thusly: -+ -+ 000 Xm & 0xFF UXTB -+ 001 Xm & 0xFFFF UXTH -+ 010 Xm & (2^32)-1 UXTW -+ 011 Xm UXTX -+ -+ 100 Xm sx from bit 7 SXTB -+ 101 Xm sx from bit 15 SXTH -+ 110 Xm sx from bit 31 SXTW -+ 111 Xm SXTX -+ -+ In the 64 bit case (bit31 == 1), UXTX and SXTX are the identity -+ operation on Xm. In the 32 bit case, UXTW, UXTX, SXTW and SXTX -+ are the identity operation on Wm. -+ -+ After extension, the value is shifted left by imm3 bits, which -+ may only be in the range 0 .. 4 inclusive. -+ */ -+ if (INSN(28,21) == BITS8(0,1,0,1,1,0,0,1) && INSN(12,10) <= 4) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSub = INSN(30,30) == 1; -+ Bool setCC = INSN(29,29) == 1; -+ UInt mm = INSN(20,16); -+ UInt opt = INSN(15,13); -+ UInt imm3 = INSN(12,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ const HChar* nameExt[8] = { "uxtb", "uxth", "uxtw", "uxtx", -+ "sxtb", "sxth", "sxtw", "sxtx" }; -+ /* Do almost the same thing in the 32- and 64-bit cases. */ -+ IRTemp xN = newTemp(Ity_I64); -+ IRTemp xM = newTemp(Ity_I64); -+ assign(xN, getIReg64orSP(nn)); -+ assign(xM, getIReg64orZR(mm)); -+ IRExpr* xMw = mkexpr(xM); /* "xM widened" */ -+ Int shSX = 0; -+ /* widen Xm .. */ -+ switch (opt) { -+ case BITS3(0,0,0): // UXTB -+ xMw = binop(Iop_And64, xMw, mkU64(0xFF)); break; -+ case BITS3(0,0,1): // UXTH -+ xMw = binop(Iop_And64, xMw, mkU64(0xFFFF)); break; -+ case BITS3(0,1,0): // UXTW -- noop for the 32bit case -+ if (is64) { -+ xMw = unop(Iop_32Uto64, unop(Iop_64to32, xMw)); -+ } -+ break; -+ case BITS3(0,1,1): // UXTX -- always a noop -+ break; -+ case BITS3(1,0,0): // SXTB -+ shSX = 56; goto sxTo64; -+ case BITS3(1,0,1): // SXTH -+ shSX = 48; goto sxTo64; -+ case BITS3(1,1,0): // SXTW -- noop for the 32bit case -+ if (is64) { -+ shSX = 32; goto sxTo64; -+ } -+ break; -+ case BITS3(1,1,1): // SXTX -- always a noop -+ break; -+ sxTo64: -+ vassert(shSX >= 32); -+ xMw = binop(Iop_Sar64, binop(Iop_Shl64, xMw, mkU8(shSX)), -+ mkU8(shSX)); -+ break; -+ default: -+ vassert(0); -+ } -+ /* and now shift */ -+ IRTemp argL = xN; -+ IRTemp argR = newTemp(Ity_I64); -+ assign(argR, binop(Iop_Shl64, xMw, mkU8(imm3))); -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64, -+ mkexpr(argL), mkexpr(argR))); -+ if (is64) { -+ if (setCC) { -+ putIReg64orZR(dd, mkexpr(res)); -+ setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR); -+ } else { -+ putIReg64orSP(dd, mkexpr(res)); -+ } -+ } else { -+ if (setCC) { -+ IRTemp argL32 = newTemp(Ity_I32); -+ IRTemp argR32 = newTemp(Ity_I32); -+ putIReg32orZR(dd, unop(Iop_64to32, mkexpr(res))); -+ assign(argL32, unop(Iop_64to32, mkexpr(argL))); -+ assign(argR32, unop(Iop_64to32, mkexpr(argR))); -+ setFlags_ADD_SUB(False/*!is64*/, isSub, argL32, argR32); -+ } else { -+ putIReg32orSP(dd, unop(Iop_64to32, mkexpr(res))); -+ } -+ } -+ DIP("%s%s %s, %s, %s %s lsl %u\n", -+ isSub ? "sub" : "add", setCC ? "s" : "", -+ setCC ? nameIRegOrZR(is64, dd) : nameIRegOrSP(is64, dd), -+ nameIRegOrSP(is64, nn), nameIRegOrSP(is64, mm), -+ nameExt[opt], imm3); -+ return True; -+ } -+ -+ /* ---------------- CCMP/CCMN(imm) ---------------- */ -+ /* Bizarrely, these appear in the "data processing register" -+ category, even though they are operations against an -+ immediate. */ -+ /* 31 29 20 15 11 9 3 -+ sf 1 111010010 imm5 cond 10 Rn 0 nzcv CCMP Rn, #imm5, #nzcv, cond -+ sf 0 111010010 imm5 cond 10 Rn 0 nzcv CCMN Rn, #imm5, #nzcv, cond -+ -+ Operation is: -+ (CCMP) flags = if cond then flags-after-sub(Rn,imm5) else nzcv -+ (CCMN) flags = if cond then flags-after-add(Rn,imm5) else nzcv -+ */ -+ if (INSN(29,21) == BITS9(1,1,1,0,1,0,0,1,0) -+ && INSN(11,10) == BITS2(1,0) && INSN(4,4) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSUB = INSN(30,30) == 1; -+ UInt imm5 = INSN(20,16); -+ UInt cond = INSN(15,12); -+ UInt nn = INSN(9,5); -+ UInt nzcv = INSN(3,0); -+ -+ IRTemp condT = newTemp(Ity_I1); -+ assign(condT, unop(Iop_64to1, mk_arm64g_calculate_condition(cond))); -+ -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp argL = newTemp(ty); -+ IRTemp argR = newTemp(ty); -+ -+ if (is64) { -+ assign(argL, getIReg64orZR(nn)); -+ assign(argR, mkU64(imm5)); -+ } else { -+ assign(argL, getIReg32orZR(nn)); -+ assign(argR, mkU32(imm5)); -+ } -+ setFlags_ADD_SUB_conditionally(is64, isSUB, condT, argL, argR, nzcv); -+ -+ DIP("ccm%c %s, #%u, #%u, %s\n", -+ isSUB ? 'p' : 'n', nameIRegOrZR(is64, nn), -+ imm5, nzcv, nameCC(cond)); -+ return True; -+ } -+ -+ /* ---------------- CCMP/CCMN(reg) ---------------- */ -+ /* 31 29 20 15 11 9 3 -+ sf 1 111010010 Rm cond 00 Rn 0 nzcv CCMP Rn, Rm, #nzcv, cond -+ sf 0 111010010 Rm cond 00 Rn 0 nzcv CCMN Rn, Rm, #nzcv, cond -+ Operation is: -+ (CCMP) flags = if cond then flags-after-sub(Rn,Rm) else nzcv -+ (CCMN) flags = if cond then flags-after-add(Rn,Rm) else nzcv -+ */ -+ if (INSN(29,21) == BITS9(1,1,1,0,1,0,0,1,0) -+ && INSN(11,10) == BITS2(0,0) && INSN(4,4) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSUB = INSN(30,30) == 1; -+ UInt mm = INSN(20,16); -+ UInt cond = INSN(15,12); -+ UInt nn = INSN(9,5); -+ UInt nzcv = INSN(3,0); -+ -+ IRTemp condT = newTemp(Ity_I1); -+ assign(condT, unop(Iop_64to1, mk_arm64g_calculate_condition(cond))); -+ -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp argL = newTemp(ty); -+ IRTemp argR = newTemp(ty); -+ -+ if (is64) { -+ assign(argL, getIReg64orZR(nn)); -+ assign(argR, getIReg64orZR(mm)); -+ } else { -+ assign(argL, getIReg32orZR(nn)); -+ assign(argR, getIReg32orZR(mm)); -+ } -+ setFlags_ADD_SUB_conditionally(is64, isSUB, condT, argL, argR, nzcv); -+ -+ DIP("ccm%c %s, %s, #%u, %s\n", -+ isSUB ? 'p' : 'n', nameIRegOrZR(is64, nn), -+ nameIRegOrZR(is64, mm), nzcv, nameCC(cond)); -+ return True; -+ } -+ -+ -+ /* -------------- REV/REV16/REV32/RBIT -------------- */ -+ /* 31 30 28 20 15 11 9 4 -+ -+ 1 10 11010110 00000 0000 11 n d REV Xd, Xn -+ 0 10 11010110 00000 0000 10 n d REV Wd, Wn -+ -+ 1 10 11010110 00000 0000 01 n d REV16 Xd, Xn -+ 0 10 11010110 00000 0000 01 n d REV16 Wd, Wn -+ -+ 1 10 11010110 00000 0000 10 n d REV32 Xd, Xn -+ -+ 1 10 11010110 00000 0000 00 n d RBIT Xd, Xn -+ 0 10 11010110 00000 0000 00 n d RBIT Wd, Wn -+ */ -+ /* Only REV is currently implemented. */ -+ if (INSN(30,21) == BITS10(1,0,1,1,0,1,0,1,1,0) -+ && INSN(20,11) == BITS10(0,0,0,0,0,0,0,0,0,1) -+ && INSN(31,31) == INSN(10,10)) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp src = newTemp(Ity_I64); -+ IRTemp dst = IRTemp_INVALID; -+ if (is64) { -+ assign(src, getIReg64orZR(nn)); -+ dst = math_BSWAP64(src); -+ putIReg64orZR(dd, mkexpr(dst)); -+ } else { -+ assign(src, binop(Iop_Shl64, getIReg64orZR(nn), mkU8(32))); -+ dst = math_BSWAP64(src); -+ putIReg32orZR(dd, unop(Iop_64to32, mkexpr(dst))); -+ } -+ DIP("rev %s, %s\n", nameIRegOrZR(is64,dd), nameIRegOrZR(is64,nn)); -+ return True; -+ } -+ -+ /* -------------------- CLZ/CLS -------------------- */ -+ /* 30 28 24 20 15 9 4 -+ sf 10 1101 0110 00000 00010 0 n d CLZ Rd, Rn -+ sf 10 1101 0110 00000 00010 1 n d CLS Rd, Rn -+ */ -+ if (INSN(30,21) == BITS10(1,0,1,1,0,1,0,1,1,0) -+ && INSN(20,11) == BITS10(0,0,0,0,0,0,0,0,1,0)) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isCLS = INSN(10,10) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp src = newTemp(Ity_I64); -+ IRTemp dst = newTemp(Ity_I64); -+ if (!isCLS) { // CLS not yet supported -+ if (is64) { -+ assign(src, getIReg64orZR(nn)); -+ assign(dst, IRExpr_ITE(binop(Iop_CmpEQ64, mkexpr(src), mkU64(0)), -+ mkU64(64), -+ unop(Iop_Clz64, mkexpr(src)))); -+ putIReg64orZR(dd, mkexpr(dst)); -+ } else { -+ assign(src, binop(Iop_Shl64, -+ unop(Iop_32Uto64, getIReg32orZR(nn)), mkU8(32))); -+ assign(dst, IRExpr_ITE(binop(Iop_CmpEQ64, mkexpr(src), mkU64(0)), -+ mkU64(32), -+ unop(Iop_Clz64, mkexpr(src)))); -+ putIReg32orZR(dd, unop(Iop_64to32, mkexpr(dst))); -+ } -+ DIP("cl%c %s, %s\n", -+ isCLS ? 's' : 'z', nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn)); -+ return True; -+ } -+ } -+ -+ /* -------------------- LSLV/LSRV/ASRV -------------------- */ -+ /* 30 28 20 15 11 9 4 -+ sf 00 1101 0110 m 0010 00 n d LSLV Rd,Rn,Rm -+ sf 00 1101 0110 m 0010 01 n d LSRV Rd,Rn,Rm -+ sf 00 1101 0110 m 0010 10 n d ASRV Rd,Rn,Rm -+ */ -+ if (INSN(30,21) == BITS10(0,0,1,1,0,1,0,1,1,0) -+ && INSN(15,12) == BITS4(0,0,1,0) && INSN(11,10) < BITS2(1,1)) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ UInt op = INSN(11,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp srcL = newTemp(ty); -+ IRTemp srcR = newTemp(Ity_I8); -+ IRTemp res = newTemp(ty); -+ IROp iop = Iop_INVALID; -+ assign(srcL, getIRegOrZR(is64, nn)); -+ assign(srcR, -+ unop(Iop_64to8, -+ binop(Iop_And64, -+ getIReg64orZR(mm), mkU64(is64 ? 63 : 31)))); -+ switch (op) { -+ case BITS2(0,0): iop = mkSHL(ty); break; -+ case BITS2(0,1): iop = mkSHR(ty); break; -+ case BITS2(1,0): iop = mkSAR(ty); break; -+ default: vassert(0); -+ } -+ assign(res, binop(iop, mkexpr(srcL), mkexpr(srcR))); -+ putIRegOrZR(is64, dd, mkexpr(res)); -+ vassert(op < 3); -+ const HChar* names[3] = { "lslv", "lsrv", "asrv" }; -+ DIP("%s %s, %s, %s\n", -+ names[op], nameIRegOrZR(is64,dd), -+ nameIRegOrZR(is64,nn), nameIRegOrZR(is64,mm)); -+ return True; -+ } -+ -+ /* -------------------- SDIV/UDIV -------------------- */ -+ /* 30 28 20 15 10 9 4 -+ sf 00 1101 0110 m 00001 1 n d SDIV Rd,Rn,Rm -+ sf 00 1101 0110 m 00001 0 n d UDIV Rd,Rn,Rm -+ */ -+ if (INSN(30,21) == BITS10(0,0,1,1,0,1,0,1,1,0) -+ && INSN(15,11) == BITS5(0,0,0,0,1)) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ Bool isS = INSN(10,10) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (isS) { -+ putIRegOrZR(is64, dd, binop(is64 ? Iop_DivS64 : Iop_DivS32, -+ getIRegOrZR(is64, nn), -+ getIRegOrZR(is64, mm))); -+ } else { -+ putIRegOrZR(is64, dd, binop(is64 ? Iop_DivU64 : Iop_DivU32, -+ getIRegOrZR(is64, nn), -+ getIRegOrZR(is64, mm))); -+ } -+ DIP("%cdiv %s, %s, %s\n", isS ? 's' : 'u', -+ nameIRegOrZR(is64, dd), -+ nameIRegOrZR(is64, nn), nameIRegOrZR(is64, mm)); -+ return True; -+ } -+ -+ /* ------------------ {S,U}M{ADD,SUB}L ------------------ */ -+ /* 31 23 20 15 14 9 4 -+ 1001 1011 101 m 0 a n d UMADDL Xd,Wn,Wm,Xa -+ 1001 1011 001 m 0 a n d SMADDL Xd,Wn,Wm,Xa -+ 1001 1011 101 m 1 a n d UMSUBL Xd,Wn,Wm,Xa -+ 1001 1011 001 m 1 a n d SMSUBL Xd,Wn,Wm,Xa -+ with operation -+ Xd = Xa +/- (Wn *u/s Wm) -+ */ -+ if (INSN(31,24) == BITS8(1,0,0,1,1,0,1,1) && INSN(22,21) == BITS2(0,1)) { -+ Bool isU = INSN(23,23) == 1; -+ UInt mm = INSN(20,16); -+ Bool isAdd = INSN(15,15) == 0; -+ UInt aa = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp wN = newTemp(Ity_I32); -+ IRTemp wM = newTemp(Ity_I32); -+ IRTemp xA = newTemp(Ity_I64); -+ IRTemp muld = newTemp(Ity_I64); -+ IRTemp res = newTemp(Ity_I64); -+ assign(wN, getIReg32orZR(nn)); -+ assign(wM, getIReg32orZR(mm)); -+ assign(xA, getIReg64orZR(aa)); -+ assign(muld, binop(isU ? Iop_MullU32 : Iop_MullS32, -+ mkexpr(wN), mkexpr(wM))); -+ assign(res, binop(isAdd ? Iop_Add64 : Iop_Sub64, -+ mkexpr(xA), mkexpr(muld))); -+ putIReg64orZR(dd, mkexpr(res)); -+ DIP("%cm%sl %s, %s, %s, %s\n", isU ? 'u' : 's', isAdd ? "add" : "sub", -+ nameIReg64orZR(dd), nameIReg32orZR(nn), -+ nameIReg32orZR(mm), nameIReg64orZR(aa)); -+ return True; -+ } -+ vex_printf("ARM64 front end: data_processing_register\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Load and Store instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Generate the EA for a "reg + reg" style amode. This is done from -+ parts of the insn, but for sanity checking sake it takes the whole -+ insn. This appears to depend on insn[15:12], with opt=insn[15:13] -+ and S=insn[12]: -+ -+ The possible forms, along with their opt:S values, are: -+ 011:0 Xn|SP + Xm -+ 111:0 Xn|SP + Xm -+ 011:1 Xn|SP + Xm * transfer_szB -+ 111:1 Xn|SP + Xm * transfer_szB -+ 010:0 Xn|SP + 32Uto64(Wm) -+ 010:1 Xn|SP + 32Uto64(Wm) * transfer_szB -+ 110:0 Xn|SP + 32Sto64(Wm) -+ 110:1 Xn|SP + 32Sto64(Wm) * transfer_szB -+ -+ Rm is insn[20:16]. Rn is insn[9:5]. Rt is insn[4:0]. Log2 of -+ the transfer size is insn[23,31,30]. For integer loads/stores, -+ insn[23] is zero, hence szLg2 can be at most 3 in such cases. -+ -+ If the decoding fails, it returns IRTemp_INVALID. -+ -+ isInt is True iff this is decoding is for transfers to/from integer -+ registers. If False it is for transfers to/from vector registers. -+*/ -+static IRTemp gen_indexed_EA ( /*OUT*/HChar* buf, UInt insn, Bool isInt ) -+{ -+ UInt optS = SLICE_UInt(insn, 15, 12); -+ UInt mm = SLICE_UInt(insn, 20, 16); -+ UInt nn = SLICE_UInt(insn, 9, 5); -+ UInt szLg2 = (isInt ? 0 : (SLICE_UInt(insn, 23, 23) << 2)) -+ | SLICE_UInt(insn, 31, 30); // Log2 of the size -+ -+ buf[0] = 0; -+ -+ /* Sanity checks, that this really is a load/store insn. */ -+ if (SLICE_UInt(insn, 11, 10) != BITS2(1,0)) -+ goto fail; -+ -+ if (isInt -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,0,1,1)/*LDR*/ -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,0,0,1)/*STR*/ -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,1,0,1)/*LDRSbhw Xt*/ -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,1,1,1))/*LDRSbhw Wt*/ -+ goto fail; -+ -+ if (!isInt -+ && SLICE_UInt(insn, 29, 24) != BITS6(1,1,1,1,0,0)) /*LDR/STR*/ -+ goto fail; -+ -+ /* Throw out non-verified but possibly valid cases. */ -+ switch (szLg2) { -+ case BITS3(0,0,0): break; // 8 bit, valid for both int and vec -+ case BITS3(0,0,1): break; // 16 bit, valid for both int and vec -+ case BITS3(0,1,0): break; // 32 bit, valid for both int and vec -+ case BITS3(0,1,1): break; // 64 bit, valid for both int and vec -+ case BITS3(1,0,0): // can only ever be valid for the vector case -+ if (isInt) goto fail; else goto fail; -+ case BITS3(1,0,1): // these sizes are never valid -+ case BITS3(1,1,0): -+ case BITS3(1,1,1): goto fail; -+ -+ default: vassert(0); -+ } -+ -+ IRExpr* rhs = NULL; -+ switch (optS) { -+ case BITS4(1,1,1,0): goto fail; //ATC -+ case BITS4(0,1,1,0): -+ rhs = getIReg64orZR(mm); -+ vex_sprintf(buf, "[%s, %s]", -+ nameIReg64orZR(nn), nameIReg64orZR(mm)); -+ break; -+ case BITS4(1,1,1,1): goto fail; //ATC -+ case BITS4(0,1,1,1): -+ rhs = binop(Iop_Shl64, getIReg64orZR(mm), mkU8(szLg2)); -+ vex_sprintf(buf, "[%s, %s lsl %u]", -+ nameIReg64orZR(nn), nameIReg64orZR(mm), szLg2); -+ break; -+ case BITS4(0,1,0,0): -+ rhs = unop(Iop_32Uto64, getIReg32orZR(mm)); -+ vex_sprintf(buf, "[%s, %s uxtx]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm)); -+ break; -+ case BITS4(0,1,0,1): -+ rhs = binop(Iop_Shl64, -+ unop(Iop_32Uto64, getIReg32orZR(mm)), mkU8(szLg2)); -+ vex_sprintf(buf, "[%s, %s uxtx, lsl %u]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm), szLg2); -+ break; -+ case BITS4(1,1,0,0): -+ rhs = unop(Iop_32Sto64, getIReg32orZR(mm)); -+ vex_sprintf(buf, "[%s, %s sxtx]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm)); -+ break; -+ case BITS4(1,1,0,1): -+ rhs = binop(Iop_Shl64, -+ unop(Iop_32Sto64, getIReg32orZR(mm)), mkU8(szLg2)); -+ vex_sprintf(buf, "[%s, %s sxtx, lsl %u]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm), szLg2); -+ break; -+ default: -+ /* The rest appear to be genuinely invalid */ -+ goto fail; -+ } -+ -+ vassert(rhs); -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, binop(Iop_Add64, getIReg64orSP(nn), rhs)); -+ return res; -+ -+ fail: -+ vex_printf("gen_indexed_EA: unhandled case optS == 0x%x\n", optS); -+ return IRTemp_INVALID; -+} -+ -+ -+/* Generate an 8/16/32/64 bit integer store to ADDR for the lowest -+ bits of DATAE :: Ity_I64. */ -+static void gen_narrowing_store ( UInt szB, IRTemp addr, IRExpr* dataE ) -+{ -+ IRExpr* addrE = mkexpr(addr); -+ switch (szB) { -+ case 8: -+ storeLE(addrE, dataE); -+ break; -+ case 4: -+ storeLE(addrE, unop(Iop_64to32, dataE)); -+ break; -+ case 2: -+ storeLE(addrE, unop(Iop_64to16, dataE)); -+ break; -+ case 1: -+ storeLE(addrE, unop(Iop_64to8, dataE)); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+ -+/* Generate an 8/16/32/64 bit unsigned widening load from ADDR, -+ placing the result in an Ity_I64 temporary. */ -+static IRTemp gen_zwidening_load ( UInt szB, IRTemp addr ) -+{ -+ IRTemp res = newTemp(Ity_I64); -+ IRExpr* addrE = mkexpr(addr); -+ switch (szB) { -+ case 8: -+ assign(res, loadLE(Ity_I64,addrE)); -+ break; -+ case 4: -+ assign(res, unop(Iop_32Uto64, loadLE(Ity_I32,addrE))); -+ break; -+ case 2: -+ assign(res, unop(Iop_16Uto64, loadLE(Ity_I16,addrE))); -+ break; -+ case 1: -+ assign(res, unop(Iop_8Uto64, loadLE(Ity_I8,addrE))); -+ break; -+ default: -+ vassert(0); -+ } -+ return res; -+} -+ -+ -+static -+Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ------------ LDR,STR (immediate, uimm12) ----------- */ -+ /* uimm12 is scaled by the transfer size -+ -+ 31 29 26 21 9 4 -+ | | | | | | -+ 11 111 00100 imm12 nn tt STR Xt, [Xn|SP, #imm12 * 8] -+ 11 111 00101 imm12 nn tt LDR Xt, [Xn|SP, #imm12 * 8] -+ -+ 10 111 00100 imm12 nn tt STR Wt, [Xn|SP, #imm12 * 4] -+ 10 111 00101 imm12 nn tt LDR Wt, [Xn|SP, #imm12 * 4] -+ -+ 01 111 00100 imm12 nn tt STRH Wt, [Xn|SP, #imm12 * 2] -+ 01 111 00101 imm12 nn tt LDRH Wt, [Xn|SP, #imm12 * 2] -+ -+ 00 111 00100 imm12 nn tt STRB Wt, [Xn|SP, #imm12 * 1] -+ 00 111 00101 imm12 nn tt LDRB Wt, [Xn|SP, #imm12 * 1] -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,1,0)) { -+ UInt szLg2 = INSN(31,30); -+ UInt szB = 1 << szLg2; -+ Bool isLD = INSN(22,22) == 1; -+ UInt offs = INSN(21,10) * szB; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp ta = newTemp(Ity_I64); -+ assign(ta, binop(Iop_Add64, getIReg64orSP(nn), mkU64(offs))); -+ if (nn == 31) { /* FIXME generate stack alignment check */ } -+ vassert(szLg2 < 4); -+ if (isLD) { -+ putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, ta))); -+ } else { -+ gen_narrowing_store(szB, ta, getIReg64orZR(tt)); -+ } -+ const HChar* ld_name[4] = { "ldrb", "ldrh", "ldr", "ldr" }; -+ const HChar* st_name[4] = { "strb", "strh", "str", "str" }; -+ DIP("%s %s, [%s, #%u]\n", -+ (isLD ? ld_name : st_name)[szLg2], nameIRegOrZR(szB == 8, tt), -+ nameIReg64orSP(nn), offs); -+ return True; -+ } -+ -+ /* ------------ LDUR,STUR (immediate, simm9) ----------- */ -+ /* -+ 31 29 26 20 11 9 4 -+ | | | | | | | -+ (at-Rn-then-Rn=EA) | | | -+ sz 111 00000 0 imm9 01 Rn Rt STR Rt, [Xn|SP], #simm9 -+ sz 111 00001 0 imm9 01 Rn Rt LDR Rt, [Xn|SP], #simm9 -+ -+ (at-EA-then-Rn=EA) -+ sz 111 00000 0 imm9 11 Rn Rt STR Rt, [Xn|SP, #simm9]! -+ sz 111 00001 0 imm9 11 Rn Rt LDR Rt, [Xn|SP, #simm9]! -+ -+ (at-EA) -+ sz 111 00000 0 imm9 00 Rn Rt STR Rt, [Xn|SP, #simm9] -+ sz 111 00001 0 imm9 00 Rn Rt LDR Rt, [Xn|SP, #simm9] -+ -+ simm9 is unscaled. -+ -+ The case 'wback && Rn == Rt && Rt != 31' is disallowed. In the -+ load case this is because would create two competing values for -+ Rt. In the store case the reason is unclear, but the spec -+ disallows it anyway. -+ -+ Stores are narrowing, loads are unsigned widening. sz encodes -+ the transfer size in the normal way: 00=1, 01=2, 10=4, 11=8. -+ */ -+ if ((INSN(29,21) & BITS9(1,1,1, 1,1,1,1,0, 1)) -+ == BITS9(1,1,1, 0,0,0,0,0, 0)) { -+ UInt szLg2 = INSN(31,30); -+ UInt szB = 1 << szLg2; -+ Bool isLoad = INSN(22,22) == 1; -+ UInt imm9 = INSN(20,12); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ Bool wBack = INSN(10,10) == 1; -+ UInt how = INSN(11,10); -+ if (how == BITS2(1,0) || (wBack && nn == tt && tt != 31)) { -+ /* undecodable; fall through */ -+ } else { -+ if (nn == 31) { /* FIXME generate stack alignment check */ } -+ -+ // Compute the transfer address TA and the writeback address WA. -+ IRTemp tRN = newTemp(Ity_I64); -+ assign(tRN, getIReg64orSP(nn)); -+ IRTemp tEA = newTemp(Ity_I64); -+ Long simm9 = (Long)sx_to_64(imm9, 9); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ -+ IRTemp tTA = newTemp(Ity_I64); -+ IRTemp tWA = newTemp(Ity_I64); -+ switch (how) { -+ case BITS2(0,1): -+ assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,1): -+ assign(tTA, mkexpr(tEA)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(0,0): -+ assign(tTA, mkexpr(tEA)); /* tWA is unused */ break; -+ default: -+ vassert(0); /* NOTREACHED */ -+ } -+ -+ if (isLoad) { -+ putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, tTA))); -+ } else { -+ gen_narrowing_store(szB, tTA, getIReg64orZR(tt)); -+ } -+ -+ if (wBack) -+ putIReg64orSP(nn, mkexpr(tEA)); -+ -+ const HChar* ld_name[4] = { "ldurb", "ldurh", "ldur", "ldur" }; -+ const HChar* st_name[4] = { "sturb", "sturh", "stur", "stur" }; -+ const HChar* fmt_str = NULL; -+ switch (how) { -+ case BITS2(0,1): -+ fmt_str = "%s %s, [%s], #%lld (at-Rn-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,1): -+ fmt_str = "%s %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n"; -+ break; -+ case BITS2(0,0): -+ fmt_str = "%s %s, [%s, #%lld] (at-Rn)\n"; -+ break; -+ default: -+ vassert(0); -+ } -+ DIP(fmt_str, (isLoad ? ld_name : st_name)[szLg2], -+ nameIRegOrZR(szB == 8, tt), -+ nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ } -+ -+ /* -------- LDP,STP (immediate, simm7) (INT REGS) -------- */ -+ /* L==1 => mm==LD -+ L==0 => mm==ST -+ x==0 => 32 bit transfers, and zero extended loads -+ x==1 => 64 bit transfers -+ simm7 is scaled by the (single-register) transfer size -+ -+ (at-Rn-then-Rn=EA) -+ x0 101 0001 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP], #imm -+ -+ (at-EA-then-Rn=EA) -+ x0 101 0011 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm]! -+ -+ (at-EA) -+ x0 101 0010 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm] -+ */ -+ -+ UInt insn_30_23 = INSN(30,23); -+ if (insn_30_23 == BITS8(0,1,0,1,0,0,0,1) -+ || insn_30_23 == BITS8(0,1,0,1,0,0,1,1) -+ || insn_30_23 == BITS8(0,1,0,1,0,0,1,0)) { -+ UInt bL = INSN(22,22); -+ UInt bX = INSN(31,31); -+ UInt bWBack = INSN(23,23); -+ UInt rT1 = INSN(4,0); -+ UInt rN = INSN(9,5); -+ UInt rT2 = INSN(14,10); -+ Long simm7 = (Long)sx_to_64(INSN(21,15), 7); -+ if ((bWBack && (rT1 == rN || rT2 == rN) && rN != 31) -+ || (bL && rT1 == rT2)) { -+ /* undecodable; fall through */ -+ } else { -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ -+ // Compute the transfer address TA and the writeback address WA. -+ IRTemp tRN = newTemp(Ity_I64); -+ assign(tRN, getIReg64orSP(rN)); -+ IRTemp tEA = newTemp(Ity_I64); -+ simm7 = (bX ? 8 : 4) * simm7; -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm7))); -+ -+ IRTemp tTA = newTemp(Ity_I64); -+ IRTemp tWA = newTemp(Ity_I64); -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,1): -+ assign(tTA, mkexpr(tEA)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,0): -+ assign(tTA, mkexpr(tEA)); /* tWA is unused */ break; -+ default: -+ vassert(0); /* NOTREACHED */ -+ } -+ -+ /* Normally rN would be updated after the transfer. However, in -+ the special case typifed by -+ stp x29, x30, [sp,#-112]! -+ it is necessary to update SP before the transfer, (1) -+ because Memcheck will otherwise complain about a write -+ below the stack pointer, and (2) because the segfault -+ stack extension mechanism will otherwise extend the stack -+ only down to SP before the instruction, which might not be -+ far enough, if the -112 bit takes the actual access -+ address to the next page. -+ */ -+ Bool earlyWBack -+ = bWBack && simm7 < 0 -+ && INSN(24,23) == BITS2(1,1) && rN == 31 && bL == 0; -+ -+ if (bWBack && earlyWBack) -+ putIReg64orSP(rN, mkexpr(tEA)); -+ -+ /**/ if (bL == 1 && bX == 1) { -+ // 64 bit load -+ putIReg64orZR(rT1, loadLE(Ity_I64, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(0)))); -+ putIReg64orZR(rT2, loadLE(Ity_I64, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(8)))); -+ } else if (bL == 1 && bX == 0) { -+ vassert(0); //ATC -+ // 32 bit load -+ putIReg32orZR(rT1, loadLE(Ity_I32, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(0)))); -+ putIReg32orZR(rT2, loadLE(Ity_I32, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(4)))); -+ } else if (bL == 0 && bX == 1) { -+ // 64 bit store -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(0)), -+ getIReg64orZR(rT1)); -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(8)), -+ getIReg64orZR(rT2)); -+ } else { -+ vassert(bL == 0 && bX == 0); -+ vassert(0); //ATC -+ // 32 bit store -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(0)), -+ getIReg32orZR(rT1)); -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(4)), -+ getIReg32orZR(rT2)); -+ } -+ -+ if (bWBack && !earlyWBack) -+ putIReg64orSP(rN, mkexpr(tEA)); -+ -+ const HChar* fmt_str = NULL; -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,1): -+ fmt_str = "%sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,0): -+ fmt_str = "%sp %s, %s, [%s, #%lld] (at-Rn)\n"; -+ break; -+ default: -+ vassert(0); -+ } -+ DIP(fmt_str, bL == 0 ? "st" : "ld", -+ nameIRegOrZR(bX == 1, rT1), -+ nameIRegOrZR(bX == 1, rT2), -+ nameIReg64orSP(rN), simm7); -+ return True; -+ } -+ } -+ -+ /* ---------------- LDR (literal, int reg) ---------------- */ -+ /* 31 29 23 4 -+ 00 011 000 imm19 Rt LDR Wt, [PC + sxTo64(imm19 << 2)] -+ 01 011 000 imm19 Rt LDR Xt, [PC + sxTo64(imm19 << 2)] -+ 10 011 000 imm19 Rt LDRSW Xt, [PC + sxTo64(imm19 << 2)] -+ 11 011 000 imm19 Rt prefetch [PC + sxTo64(imm19 << 2)] -+ Just handles the first two cases for now. -+ */ -+ if (INSN(29,24) == BITS6(0,1,1,0,0,0) && INSN(31,31) == 0) { -+ UInt imm19 = INSN(23,5); -+ UInt rT = INSN(4,0); -+ UInt bX = INSN(30,30); -+ ULong ea = guest_PC_curr_instr + sx_to_64(imm19 << 2, 21); -+ if (bX) { -+ putIReg64orZR(rT, loadLE(Ity_I64, mkU64(ea))); -+ } else { -+ putIReg32orZR(rT, loadLE(Ity_I32, mkU64(ea))); -+ } -+ DIP("ldr %s, 0x%llx (literal)\n", nameIRegOrZR(bX == 1, rT), ea); -+ return True; -+ } -+ -+ /* -------------- {LD,ST}R (integer register) --------------- */ -+ /* 31 29 20 15 12 11 9 4 -+ | | | | | | | | -+ 11 111000011 Rm option S 10 Rn Rt LDR Xt, [Xn|SP, R{ext/sh}] -+ 10 111000011 Rm option S 10 Rn Rt LDR Wt, [Xn|SP, R{ext/sh}] -+ 01 111000011 Rm option S 10 Rn Rt LDRH Wt, [Xn|SP, R{ext/sh}] -+ 00 111000011 Rm option S 10 Rn Rt LDRB Wt, [Xn|SP, R{ext/sh}] -+ -+ 11 111000001 Rm option S 10 Rn Rt STR Xt, [Xn|SP, R{ext/sh}] -+ 10 111000001 Rm option S 10 Rn Rt STR Wt, [Xn|SP, R{ext/sh}] -+ 01 111000001 Rm option S 10 Rn Rt STRH Wt, [Xn|SP, R{ext/sh}] -+ 00 111000001 Rm option S 10 Rn Rt STRB Wt, [Xn|SP, R{ext/sh}] -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,0) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ HChar dis_buf[64]; -+ UInt szLg2 = INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt tt = INSN(4,0); -+ IRTemp ea = gen_indexed_EA(dis_buf, insn, True/*to/from int regs*/); -+ if (ea != IRTemp_INVALID) { -+ switch (szLg2) { -+ case 3: /* 64 bit */ -+ if (isLD) { -+ putIReg64orZR(tt, loadLE(Ity_I64, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getIReg64orZR(tt)); -+ DIP("str %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } -+ break; -+ case 2: /* 32 bit */ -+ if (isLD) { -+ putIReg32orZR(tt, loadLE(Ity_I32, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getIReg32orZR(tt)); -+ DIP("str %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ break; -+ case 1: /* 16 bit */ -+ if (isLD) { -+ putIReg64orZR(tt, unop(Iop_16Uto64, -+ loadLE(Ity_I16, mkexpr(ea)))); -+ DIP("ldruh %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), unop(Iop_64to16, getIReg64orZR(tt))); -+ DIP("strh %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ break; -+ case 0: /* 8 bit */ -+ if (isLD) { -+ putIReg64orZR(tt, unop(Iop_8Uto64, -+ loadLE(Ity_I8, mkexpr(ea)))); -+ DIP("ldrub %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), unop(Iop_64to8, getIReg64orZR(tt))); -+ DIP("strb %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ } -+ -+ /* -------------- LDRS{B,H,W} (uimm12) -------------- */ -+ /* 31 29 26 23 21 9 4 -+ 10 111 001 10 imm12 n t LDRSW Xt, [Xn|SP, #pimm12 * 4] -+ 01 111 001 1x imm12 n t LDRSH Rt, [Xn|SP, #pimm12 * 2] -+ 00 111 001 1x imm12 n t LDRSB Rt, [Xn|SP, #pimm12 * 1] -+ where -+ Rt is Wt when x==1, Xt when x==0 -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,1,1)) { -+ /* Further checks on bits 31:30 and 22 */ -+ Bool valid = False; -+ switch ((INSN(31,30) << 1) | INSN(22,22)) { -+ case BITS3(1,0,0): -+ case BITS3(0,1,0): case BITS3(0,1,1): -+ case BITS3(0,0,0): case BITS3(0,0,1): -+ valid = True; -+ break; -+ } -+ if (valid) { -+ UInt szLg2 = INSN(31,30); -+ UInt bitX = INSN(22,22); -+ UInt imm12 = INSN(21,10); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ UInt szB = 1 << szLg2; -+ IRExpr* ea = binop(Iop_Add64, -+ getIReg64orSP(nn), mkU64(imm12 * szB)); -+ switch (szB) { -+ case 4: -+ vassert(bitX == 0); -+ putIReg64orZR(tt, unop(Iop_32Sto64, loadLE(Ity_I32, ea))); -+ DIP("ldrsw %s, [%s, #%u]\n", nameIReg64orZR(tt), -+ nameIReg64orSP(nn), imm12 * szB); -+ break; -+ case 2: -+ if (bitX == 1) { -+ putIReg32orZR(tt, unop(Iop_16Sto32, loadLE(Ity_I16, ea))); -+ } else { -+ putIReg64orZR(tt, unop(Iop_16Sto64, loadLE(Ity_I16, ea))); -+ } -+ DIP("ldrsh %s, [%s, #%u]\n", -+ nameIRegOrZR(bitX == 0, tt), -+ nameIReg64orSP(nn), imm12 * szB); -+ break; -+ case 1: -+ if (bitX == 1) { -+ putIReg32orZR(tt, unop(Iop_8Sto32, loadLE(Ity_I8, ea))); -+ } else { -+ putIReg64orZR(tt, unop(Iop_8Sto64, loadLE(Ity_I8, ea))); -+ } -+ DIP("ldrsb %s, [%s, #%u]\n", -+ nameIRegOrZR(bitX == 0, tt), -+ nameIReg64orSP(nn), imm12 * szB); -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------- LDRS{B,H,W} (simm9, upd) -------------- */ -+ /* (at-Rn-then-Rn=EA) -+ 31 29 23 21 20 11 9 4 -+ 00 111 000 1x 0 imm9 01 n t LDRSB Rt, [Xn|SP], #simm9 -+ 01 111 000 1x 0 imm9 01 n t LDRSH Rt, [Xn|SP], #simm9 -+ 10 111 000 10 0 imm9 01 n t LDRSW Xt, [Xn|SP], #simm9 -+ -+ (at-EA-then-Rn=EA) -+ 00 111 000 1x 0 imm9 11 n t LDRSB Rt, [Xn|SP, #simm9]! -+ 01 111 000 1x 0 imm9 11 n t LDRSH Rt, [Xn|SP, #simm9]! -+ 10 111 000 10 0 imm9 11 n t LDRSW Xt, [Xn|SP, #simm9]! -+ where -+ Rt is Wt when x==1, Xt when x==0 -+ transfer-at-Rn when [11]==0, at EA when [11]==1 -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,1) -+ && INSN(21,21) == 0 && INSN(10,10) == 1) { -+ /* Further checks on bits 31:30 and 22 */ -+ Bool valid = False; -+ switch ((INSN(31,30) << 1) | INSN(22,22)) { -+ case BITS3(1,0,0): // LDRSW Xt -+ case BITS3(0,1,0): case BITS3(0,1,1): // LDRSH Xt, Wt -+ case BITS3(0,0,0): case BITS3(0,0,1): // LDRSB Xt, Wt -+ valid = True; -+ break; -+ } -+ if (valid) { -+ UInt szLg2 = INSN(31,30); -+ UInt imm9 = INSN(20,12); -+ Bool atRN = INSN(11,11) == 0; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tRN = newTemp(Ity_I64); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRTemp tTA = IRTemp_INVALID; -+ ULong simm9 = sx_to_64(imm9, 9); -+ Bool is64 = INSN(22,22) == 0; -+ assign(tRN, getIReg64orSP(nn)); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ tTA = atRN ? tRN : tEA; -+ HChar ch = '?'; -+ /* There are 5 cases: -+ byte load, SX to 64 -+ byte load, SX to 32, ZX to 64 -+ halfword load, SX to 64 -+ halfword load, SX to 32, ZX to 64 -+ word load, SX to 64 -+ The ifs below handle them in the listed order. -+ */ -+ if (szLg2 == 0) { -+ ch = 'b'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_8Sto64, -+ loadLE(Ity_I8, mkexpr(tTA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_8Sto32, -+ loadLE(Ity_I8, mkexpr(tTA)))); -+ } -+ } -+ else if (szLg2 == 1) { -+ ch = 'h'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_16Sto64, -+ loadLE(Ity_I16, mkexpr(tTA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_16Sto32, -+ loadLE(Ity_I16, mkexpr(tTA)))); -+ } -+ } -+ else if (szLg2 == 2 && is64) { -+ ch = 'w'; -+ putIReg64orZR(tt, unop(Iop_32Sto64, -+ loadLE(Ity_I32, mkexpr(tTA)))); -+ } -+ else { -+ vassert(0); -+ } -+ putIReg64orSP(nn, mkexpr(tEA)); -+ DIP(atRN ? "ldrs%c %s, [%s], #%lld\n" : "ldrs%c %s, [%s, #%lld]!", -+ ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------- LDRS{B,H,W} (simm9, noUpd) -------------- */ -+ /* 31 29 23 21 20 11 9 4 -+ 00 111 000 1x 0 imm9 00 n t LDURSB Rt, [Xn|SP, #simm9] -+ 01 111 000 1x 0 imm9 00 n t LDURSH Rt, [Xn|SP, #simm9] -+ 10 111 000 10 0 imm9 00 n t LDURSW Xt, [Xn|SP, #simm9] -+ where -+ Rt is Wt when x==1, Xt when x==0 -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,1) -+ && INSN(21,21) == 0 && INSN(11,10) == BITS2(0,0)) { -+ /* Further checks on bits 31:30 and 22 */ -+ Bool valid = False; -+ switch ((INSN(31,30) << 1) | INSN(22,22)) { -+ case BITS3(1,0,0): // LDURSW Xt -+ case BITS3(0,1,0): case BITS3(0,1,1): // LDURSH Xt, Wt -+ case BITS3(0,0,0): case BITS3(0,0,1): // LDURSB Xt, Wt -+ valid = True; -+ break; -+ } -+ if (valid) { -+ UInt szLg2 = INSN(31,30); -+ UInt imm9 = INSN(20,12); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tRN = newTemp(Ity_I64); -+ IRTemp tEA = newTemp(Ity_I64); -+ ULong simm9 = sx_to_64(imm9, 9); -+ Bool is64 = INSN(22,22) == 0; -+ assign(tRN, getIReg64orSP(nn)); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ HChar ch = '?'; -+ /* There are 5 cases: -+ byte load, SX to 64 -+ byte load, SX to 32, ZX to 64 -+ halfword load, SX to 64 -+ halfword load, SX to 32, ZX to 64 -+ word load, SX to 64 -+ The ifs below handle them in the listed order. -+ */ -+ if (szLg2 == 0) { -+ ch = 'b'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_8Sto64, -+ loadLE(Ity_I8, mkexpr(tEA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_8Sto32, -+ loadLE(Ity_I8, mkexpr(tEA)))); -+ } -+ } -+ else if (szLg2 == 1) { -+ ch = 'h'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_16Sto64, -+ loadLE(Ity_I16, mkexpr(tEA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_16Sto32, -+ loadLE(Ity_I16, mkexpr(tEA)))); -+ } -+ } -+ else if (szLg2 == 2 && is64) { -+ ch = 'w'; -+ putIReg64orZR(tt, unop(Iop_32Sto64, -+ loadLE(Ity_I32, mkexpr(tEA)))); -+ } -+ else { -+ vassert(0); -+ } -+ DIP("ldurs%c %s, [%s, #%lld]", -+ ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------- LDP,STP (immediate, simm7) (FP&VEC) -------- */ -+ /* L==1 => mm==LD -+ L==0 => mm==ST -+ sz==00 => 32 bit (S) transfers -+ sz==01 => 64 bit (D) transfers -+ sz==10 => 128 bit (Q) transfers -+ sz==11 isn't allowed -+ simm7 is scaled by the (single-register) transfer size -+ -+ 31 29 22 21 14 9 4 -+ sz 101 1001 L imm7 t2 n t1 mmP SDQt1, SDQt2, [Xn|SP], #imm -+ (at-Rn-then-Rn=EA) -+ -+ sz 101 1011 L imm7 t2 n t1 mmP SDQt1, SDQt2, [Xn|SP, #imm]! -+ (at-EA-then-Rn=EA) -+ -+ sz 101 1010 L imm7 t2 n t1 mmP SDQt1, SDQt2, [Xn|SP, #imm] -+ (at-EA) -+ */ -+ -+ UInt insn_29_23 = INSN(29,23); -+ if (insn_29_23 == BITS7(1,0,1,1,0,0,1) -+ || insn_29_23 == BITS7(1,0,1,1,0,1,1) -+ || insn_29_23 == BITS7(1,0,1,1,0,1,0)) { -+ UInt szSlg2 = INSN(31,30); // log2 of the xfer size in 32-bit units -+ Bool isLD = INSN(22,22) == 1; -+ Bool wBack = INSN(23,23) == 1; -+ Long simm7 = (Long)sx_to_64(INSN(21,15), 7); -+ UInt tt2 = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt tt1 = INSN(4,0); -+ if (szSlg2 == BITS2(1,1) || (isLD && tt1 == tt2)) { -+ /* undecodable; fall through */ -+ } else { -+ if (nn == 31) { /* FIXME generate stack alignment check */ } -+ -+ // Compute the transfer address TA and the writeback address WA. -+ UInt szB = 4 << szSlg2; /* szB is the per-register size */ -+ IRTemp tRN = newTemp(Ity_I64); -+ assign(tRN, getIReg64orSP(nn)); -+ IRTemp tEA = newTemp(Ity_I64); -+ simm7 = szB * simm7; -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm7))); -+ -+ IRTemp tTA = newTemp(Ity_I64); -+ IRTemp tWA = newTemp(Ity_I64); -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,1): -+ assign(tTA, mkexpr(tEA)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,0): -+ assign(tTA, mkexpr(tEA)); /* tWA is unused */ break; -+ default: -+ vassert(0); /* NOTREACHED */ -+ } -+ -+ IRType ty = Ity_INVALID; -+ switch (szB) { -+ case 4: ty = Ity_F32; break; -+ case 8: ty = Ity_F64; break; -+ case 16: ty = Ity_V128; break; -+ default: vassert(0); -+ } -+ -+ if (isLD) { -+ putQReg(tt1, -+ loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(0)))); -+ putQReg(tt2, -+ loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(szB)))); -+ } else { -+ storeLE(binop(Iop_Add64, mkexpr(tTA), mkU64(0)), -+ getQReg(ty, tt1)); -+ storeLE(binop(Iop_Add64, mkexpr(tTA), mkU64(szB)), -+ getQReg(ty, tt2)); -+ } -+ -+ if (wBack) -+ putIReg64orSP(nn, mkexpr(tEA)); -+ -+ const HChar* fmt_str = NULL; -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,1): -+ fmt_str = "%sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,0): -+ fmt_str = "%sp %s, %s, [%s, #%lld] (at-Rn)\n"; -+ break; -+ default: -+ vassert(0); -+ } -+ DIP(fmt_str, isLD ? "ld" : "st", -+ nameQReg(szB, tt1), nameQReg(szB, tt2), -+ nameIReg64orSP(nn), simm7); -+ return True; -+ } -+ } -+ -+ /* -------------- {LD,ST}R (vector register) --------------- */ -+ /* 31 29 23 20 15 12 11 9 4 -+ | | | | | | | | | -+ 00 111100 011 Rm option S 10 Rn Rt LDR Bt, [Xn|SP, R{ext/sh}] -+ 01 111100 011 Rm option S 10 Rn Rt LDR Ht, [Xn|SP, R{ext/sh}] -+ 10 111100 011 Rm option S 10 Rn Rt LDR St, [Xn|SP, R{ext/sh}] -+ 11 111100 011 Rm option S 10 Rn Rt LDR Dt, [Xn|SP, R{ext/sh}] -+ 00 111100 111 Rm option S 10 Rn Rt LDR Qt, [Xn|SP, R{ext/sh}] -+ -+ 00 111100 001 Rm option S 10 Rn Rt STR Bt, [Xn|SP, R{ext/sh}] -+ 01 111100 001 Rm option S 10 Rn Rt STR Ht, [Xn|SP, R{ext/sh}] -+ 10 111100 001 Rm option S 10 Rn Rt STR St, [Xn|SP, R{ext/sh}] -+ 11 111100 001 Rm option S 10 Rn Rt STR Dt, [Xn|SP, R{ext/sh}] -+ 00 111100 101 Rm option S 10 Rn Rt STR Qt, [Xn|SP, R{ext/sh}] -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,0) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ HChar dis_buf[64]; -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt tt = INSN(4,0); -+ if (szLg2 >= 4) goto after_LDR_STR_vector_register; -+ IRTemp ea = gen_indexed_EA(dis_buf, insn, False/*to/from vec regs*/); -+ if (ea == IRTemp_INVALID) goto after_LDR_STR_vector_register; -+ switch (szLg2) { -+ case 0: /* 8 bit */ -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQReg(tt, loadLE(Ity_I8, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQReg(1, tt), dis_buf); -+ } else { -+ vassert(0); //ATC -+ storeLE(mkexpr(ea), getQReg(Ity_I8, tt)); -+ DIP("str %s, %s\n", nameQReg(1, tt), dis_buf); -+ } -+ break; -+ case 1: -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQReg(tt, loadLE(Ity_I16, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQReg(2, tt), dis_buf); -+ } else { -+ vassert(0); //ATC -+ storeLE(mkexpr(ea), getQReg(Ity_I16, tt)); -+ DIP("str %s, %s\n", nameQReg(2, tt), dis_buf); -+ } -+ break; -+ case 2: /* 32 bit */ -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQReg(tt, loadLE(Ity_I32, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQReg(4, tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getQReg(Ity_I32, tt)); -+ DIP("str %s, %s\n", nameQReg(4, tt), dis_buf); -+ } -+ break; -+ case 3: /* 64 bit */ -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQReg(tt, loadLE(Ity_I64, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQReg(8, tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getQReg(Ity_I64, tt)); -+ DIP("str %s, %s\n", nameQReg(8, tt), dis_buf); -+ } -+ break; -+ case 4: return False; //ATC -+ default: vassert(0); -+ } -+ return True; -+ } -+ after_LDR_STR_vector_register: -+ -+ /* ---------- LDRS{B,H,W} (integer register, SX) ---------- */ -+ /* 31 29 22 20 15 12 11 9 4 -+ | | | | | | | | | -+ 10 1110001 01 Rm opt S 10 Rn Rt LDRSW Xt, [Xn|SP, R{ext/sh}] -+ -+ 01 1110001 01 Rm opt S 10 Rn Rt LDRSH Xt, [Xn|SP, R{ext/sh}] -+ 01 1110001 11 Rm opt S 10 Rn Rt LDRSH Wt, [Xn|SP, R{ext/sh}] -+ -+ 00 1110001 01 Rm opt S 10 Rn Rt LDRSB Xt, [Xn|SP, R{ext/sh}] -+ 00 1110001 11 Rm opt S 10 Rn Rt LDRSB Wt, [Xn|SP, R{ext/sh}] -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,1) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ HChar dis_buf[64]; -+ UInt szLg2 = INSN(31,30); -+ Bool sxTo64 = INSN(22,22) == 0; // else sx to 32 and zx to 64 -+ UInt tt = INSN(4,0); -+ if (szLg2 == 3) goto after_LDRS_integer_register; -+ IRTemp ea = gen_indexed_EA(dis_buf, insn, True/*to/from int regs*/); -+ if (ea == IRTemp_INVALID) goto after_LDRS_integer_register; -+ /* Enumerate the 5 variants explicitly. */ -+ if (szLg2 == 2/*32 bit*/ && sxTo64) { -+ putIReg64orZR(tt, unop(Iop_32Sto64, loadLE(Ity_I32, mkexpr(ea)))); -+ DIP("ldrsw %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ return True; -+ } -+ else -+ if (szLg2 == 1/*16 bit*/) { -+ if (sxTo64) { -+ putIReg64orZR(tt, unop(Iop_16Sto64, loadLE(Ity_I16, mkexpr(ea)))); -+ DIP("ldrsh %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } else { -+ putIReg32orZR(tt, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(ea)))); -+ DIP("ldrsh %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ return True; -+ } -+ else -+ if (szLg2 == 0/*8 bit*/) { -+ if (sxTo64) { -+ putIReg64orZR(tt, unop(Iop_8Sto64, loadLE(Ity_I8, mkexpr(ea)))); -+ DIP("ldrsb %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } else { -+ putIReg32orZR(tt, unop(Iop_8Sto32, loadLE(Ity_I8, mkexpr(ea)))); -+ DIP("ldrsb %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ return True; -+ } -+ /* else it's an invalid combination */ -+ } -+ after_LDRS_integer_register: -+ -+ /* -------- LDR/STR (immediate, SIMD&FP, unsigned offset) -------- */ -+ /* This is the Unsigned offset variant only. The Post-Index and -+ Pre-Index variants are below. -+ -+ 31 29 23 21 9 4 -+ 00 111 101 01 imm12 n t LDR Bt, [Xn|SP + imm12 * 1] -+ 01 111 101 01 imm12 n t LDR Ht, [Xn|SP + imm12 * 2] -+ 10 111 101 01 imm12 n t LDR St, [Xn|SP + imm12 * 4] -+ 11 111 101 01 imm12 n t LDR Dt, [Xn|SP + imm12 * 8] -+ 00 111 101 11 imm12 n t LDR Qt, [Xn|SP + imm12 * 16] -+ -+ 00 111 101 00 imm12 n t STR Bt, [Xn|SP + imm12 * 1] -+ 01 111 101 00 imm12 n t STR Ht, [Xn|SP + imm12 * 2] -+ 10 111 101 00 imm12 n t STR St, [Xn|SP + imm12 * 4] -+ 11 111 101 00 imm12 n t STR Dt, [Xn|SP + imm12 * 8] -+ 00 111 101 10 imm12 n t STR Qt, [Xn|SP + imm12 * 16] -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,1) -+ && ((INSN(23,23) << 2) | INSN(31,30)) <= 4) { -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt pimm12 = INSN(21,10) << szLg2; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRType ty = preferredVectorSubTypeFromSize(1 << szLg2); -+ assign(tEA, binop(Iop_Add64, getIReg64orSP(nn), mkU64(pimm12))); -+ if (isLD) { -+ if (szLg2 < 4) { -+ putQReg128(tt, mkV128(0x0000)); -+ } -+ putQReg(tt, loadLE(ty, mkexpr(tEA))); -+ } else { -+ storeLE(mkexpr(tEA), getQReg(ty, tt)); -+ } -+ DIP("%s %s, [%s, #%u]\n", -+ isLD ? "ldr" : "str", -+ nameQReg(1 << szLg2, tt), nameIReg64orSP(nn), pimm12); -+ return True; -+ } -+ -+ /* -------- LDR/STR (immediate, SIMD&FP, pre/post index) -------- */ -+ /* These are the Post-Index and Pre-Index variants. -+ -+ 31 29 23 20 11 9 4 -+ (at-Rn-then-Rn=EA) -+ 00 111 100 01 0 imm9 01 n t LDR Bt, [Xn|SP], #simm -+ 01 111 100 01 0 imm9 01 n t LDR Ht, [Xn|SP], #simm -+ 10 111 100 01 0 imm9 01 n t LDR St, [Xn|SP], #simm -+ 11 111 100 01 0 imm9 01 n t LDR Dt, [Xn|SP], #simm -+ 00 111 100 11 0 imm9 01 n t LDR Qt, [Xn|SP], #simm -+ -+ (at-EA-then-Rn=EA) -+ 00 111 100 01 0 imm9 11 n t LDR Bt, [Xn|SP, #simm]! -+ 01 111 100 01 0 imm9 11 n t LDR Ht, [Xn|SP, #simm]! -+ 10 111 100 01 0 imm9 11 n t LDR St, [Xn|SP, #simm]! -+ 11 111 100 01 0 imm9 11 n t LDR Dt, [Xn|SP, #simm]! -+ 00 111 100 11 0 imm9 11 n t LDR Qt, [Xn|SP, #simm]! -+ -+ Stores are the same except with bit 22 set to 0. -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,0) -+ && ((INSN(23,23) << 2) | INSN(31,30)) <= 4 -+ && INSN(21,21) == 0 && INSN(10,10) == 1) { -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt imm9 = INSN(20,12); -+ Bool atRN = INSN(11,11) == 0; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tRN = newTemp(Ity_I64); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRTemp tTA = IRTemp_INVALID; -+ IRType ty = preferredVectorSubTypeFromSize(1 << szLg2); -+ ULong simm9 = sx_to_64(imm9, 9); -+ assign(tRN, getIReg64orSP(nn)); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ tTA = atRN ? tRN : tEA; -+ if (isLD) { -+ if (szLg2 < 4) { -+ putQReg128(tt, mkV128(0x0000)); -+ } -+ putQReg(tt, loadLE(ty, mkexpr(tTA))); -+ } else { -+ storeLE(mkexpr(tTA), getQReg(ty, tt)); -+ } -+ putIReg64orSP(nn, mkexpr(tEA)); -+ DIP(atRN ? "%s %s, [%s], #%lld\n" : "%s %s, [%s, #%lld]!\n", -+ isLD ? "ldr" : "str", -+ nameQReg(1 << szLg2, tt), nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ -+ /* -------- LDUR/STUR (unscaled offset, SIMD&FP) -------- */ -+ /* 31 29 23 20 11 9 4 -+ 00 111 100 01 0 imm9 00 n t LDR Bt, [Xn|SP, #simm] -+ 01 111 100 01 0 imm9 00 n t LDR Ht, [Xn|SP, #simm] -+ 10 111 100 01 0 imm9 00 n t LDR St, [Xn|SP, #simm] -+ 11 111 100 01 0 imm9 00 n t LDR Dt, [Xn|SP, #simm] -+ 00 111 100 11 0 imm9 00 n t LDR Qt, [Xn|SP, #simm] -+ -+ 00 111 100 00 0 imm9 00 n t STR Bt, [Xn|SP, #simm] -+ 01 111 100 00 0 imm9 00 n t STR Ht, [Xn|SP, #simm] -+ 10 111 100 00 0 imm9 00 n t STR St, [Xn|SP, #simm] -+ 11 111 100 00 0 imm9 00 n t STR Dt, [Xn|SP, #simm] -+ 00 111 100 10 0 imm9 00 n t STR Qt, [Xn|SP, #simm] -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,0) -+ && ((INSN(23,23) << 2) | INSN(31,30)) <= 4 -+ && INSN(21,21) == 0 && INSN(11,10) == BITS2(0,0)) { -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt imm9 = INSN(20,12); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ ULong simm9 = sx_to_64(imm9, 9); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRType ty = preferredVectorSubTypeFromSize(1 << szLg2); -+ assign(tEA, binop(Iop_Add64, getIReg64orSP(nn), mkU64(simm9))); -+ if (isLD) { -+ if (szLg2 < 4) { -+ putQReg128(tt, mkV128(0x0000)); -+ } -+ putQReg(tt, loadLE(ty, mkexpr(tEA))); -+ } else { -+ storeLE(mkexpr(tEA), getQReg(ty, tt)); -+ } -+ DIP("%s %s, [%s, #%lld]\n", -+ isLD ? "ldur" : "stur", -+ nameQReg(1 << szLg2, tt), nameIReg64orSP(nn), (Long)simm9); -+ return True; -+ } -+ -+ /* ---------------- LDR (literal, SIMD&FP) ---------------- */ -+ /* 31 29 23 4 -+ 00 011 100 imm19 t LDR St, [PC + sxTo64(imm19 << 2)] -+ 01 011 100 imm19 t LDR Dt, [PC + sxTo64(imm19 << 2)] -+ 10 011 100 imm19 t LDR Qt, [PC + sxTo64(imm19 << 2)] -+ */ -+ if (INSN(29,24) == BITS6(0,1,1,1,0,0) && INSN(31,30) < BITS2(1,1)) { -+ UInt szB = 4 << INSN(31,30); -+ UInt imm19 = INSN(23,5); -+ UInt tt = INSN(4,0); -+ ULong ea = guest_PC_curr_instr + sx_to_64(imm19 << 2, 21); -+ IRType ty = preferredVectorSubTypeFromSize(szB); -+ putQReg(tt, loadLE(ty, mkU64(ea))); -+ DIP("ldr %s, 0x%llx (literal)\n", nameQReg(szB, tt), ea); -+ return True; -+ } -+ -+ /* FIXME Temporary hacks to get through ld.so FIXME */ -+ -+ /* ------------------ ST1 variants ------------------ */ -+ /* st1 {vT.2d}, [], #16. -+ Note that #16 is implied and cannot be set to any -+ other value. -+ 0100 1100 1001 1111 0111 11 N T -+ FIXME doesn't this assume that the host is little endian? -+ */ -+ if ((insn & 0xFFFFFC00) == 0x4C9F7C00) { -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ storeLE(mkexpr(tEA), getQReg128(vT)); -+ putIReg64orSP(rN, binop(Iop_Add64, mkexpr(tEA), mkU64(16))); -+ DIP("st1 {v%u.2d}, [%s], #16\n", vT, nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* ------------------ LD1 variants ------------------ */ -+ /* 31 23 -+ 0100 1100 0100 0000 0111 11 N T LD1 {vT.2d}, [Xn|SP] -+ 0100 1100 0000 0000 0111 11 N T ST1 {vT.2d}, [Xn|SP] -+ 0100 1100 0100 0000 0111 00 N T LD1 {vT.16b}, [Xn|SP] -+ 0100 1100 0000 0000 0111 00 N T ST1 {vT.16b}, [Xn|SP] -+ FIXME doesn't this assume that the host is little endian? -+ */ -+ if ( (insn & 0xFFFFFC00) == 0x4C407C00 // LD1 {vT.2d}, [Xn|SP] -+ || (insn & 0xFFFFFC00) == 0x4C007C00 // ST1 {vT.2d}, [Xn|SP] -+ || (insn & 0xFFFFFC00) == 0x4C407000 // LD1 {vT.16b}, [Xn|SP] -+ || (insn & 0xFFFFFC00) == 0x4C007000 // ST1 {vT.16b}, [Xn|SP] -+ ) { -+ Bool isLD = INSN(22,22) == 1; -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ if (isLD) { -+ putQReg128(vT, loadLE(Ity_V128, mkexpr(tEA))); -+ } else { -+ storeLE(mkexpr(tEA), getQReg128(vT)); -+ } -+ DIP("%s {v%u.%s}, [%s]\n", isLD ? "ld1" : "st1", -+ vT, INSN(11,10) == BITS2(0,0) ? "16b" : "2d", -+ nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* -------------------- LD{A}XR -------------------- */ -+ /* FIXME: this is a hack; needs real atomicity stuff. */ -+ /* 31 29 20 19 9 4 -+ 1x(size) 001000010 1 1111 1 11111 n t LDAXR Rt, [Xn|SP] -+ 1x(size) 001000010 1 1111 0 11111 n t LDXR Rt, [Xn|SP] -+ */ -+ if (INSN(29,20) == BITS10(0,0,1,0,0,0,0,1,0,1) -+ && (INSN(19,10) == BITS10(1,1,1,1,1,1,1,1,1,1) -+ || INSN(19,10) == BITS10(1,1,1,1,0,1,1,1,1,1)) -+ && INSN(31,31) == 1) { -+ Bool is64 = INSN(30,30) == 1; -+ Bool isA = INSN(15,15) == 1; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ if (is64) { -+ putIReg64orZR(tt, loadLE(Ity_I64, getIReg64orSP(nn))); -+ } else { -+ putIReg32orZR(tt, loadLE(Ity_I32, getIReg64orSP(nn))); -+ } -+ DIP("ld%sxr %s, [%s]\n", -+ isA ? "s" : "", nameIRegOrZR(is64, tt), nameIReg64orSP(nn)); -+ return True; -+ } -+ -+ /* -------------------- ST{L}XR -------------------- */ -+ /* FIXME: this is a hack; needs real atomicity stuff. */ -+ /* 31 29 20 15 14 9 4 -+ 1x(size) 001000000 s 0 11111 n t STXR Ws, Rt, [Xn|SP] -+ 1x(size) 001000000 s 1 11111 n t STLXR Ws, Rt, [Xn|SP] -+ with the result coding that Ws == 0 iff the store succeeded -+ */ -+ if (INSN(29,21) == BITS9(0,0,1,0,0,0,0,0,0) -+ && INSN(14,10) == BITS5(1,1,1,1,1) && INSN(31,31) == 1) { -+ Bool is64 = INSN(30,30) == 1; -+ UInt ss = INSN(20,16); -+ Bool isL = INSN(15,15) == 1; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ if (is64) { -+ storeLE(getIReg64orSP(nn), getIReg64orZR(tt)); -+ } else { -+ storeLE(getIReg64orSP(nn), getIReg32orZR(tt)); -+ } -+ putIReg32orZR(ss, mkU32(0)); -+ DIP("st%sxr %s, %s, [%s]\n", -+ isL ? "s" : "", -+ nameIReg32orZR(ss), nameIRegOrZR(is64, tt), nameIReg64orSP(nn)); -+ return True; -+ } -+ -+ vex_printf("ARM64 front end: load_store\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Control flow and misc instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+static -+Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ---------------------- B cond ----------------------- */ -+ /* 31 24 4 3 -+ 0101010 0 imm19 0 cond */ -+ if (INSN(31,24) == BITS8(0,1,0,1,0,1,0,0) && INSN(4,4) == 0) { -+ UInt cond = INSN(3,0); -+ ULong uimm64 = INSN(23,5) << 2; -+ Long simm64 = (Long)sx_to_64(uimm64, 21); -+ vassert(dres->whatNext == Dis_Continue); -+ vassert(dres->len == 4); -+ vassert(dres->continueAt == 0); -+ vassert(dres->jk_StopHere == Ijk_INVALID); -+ stmt( IRStmt_Exit(unop(Iop_64to1, mk_arm64g_calculate_condition(cond)), -+ Ijk_Boring, -+ IRConst_U64(guest_PC_curr_instr + simm64), -+ OFFB_PC) ); -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("b.%s 0x%llx\n", nameCC(cond), guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* -------------------- B{L} uncond -------------------- */ -+ if (INSN(30,26) == BITS5(0,0,1,0,1)) { -+ /* 000101 imm26 B (PC + sxTo64(imm26 << 2)) -+ 100101 imm26 B (PC + sxTo64(imm26 << 2)) -+ */ -+ UInt bLink = INSN(31,31); -+ ULong uimm64 = INSN(25,0) << 2; -+ Long simm64 = (Long)sx_to_64(uimm64, 28); -+ if (bLink) { -+ putIReg64orSP(30, mkU64(guest_PC_curr_instr + 4)); -+ } -+ putPC(mkU64(guest_PC_curr_instr + simm64)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Call; -+ DIP("b%s 0x%llx\n", bLink == 1 ? "l" : "", -+ guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* --------------------- B{L} reg --------------------- */ -+ /* 31 24 22 20 15 9 4 -+ 1101011 00 10 11111 000000 nn 00000 RET Rn -+ 1101011 00 01 11111 000000 nn 00000 CALL Rn -+ 1101011 00 00 11111 000000 nn 00000 JMP Rn -+ */ -+ if (INSN(31,23) == BITS9(1,1,0,1,0,1,1,0,0) -+ && INSN(20,16) == BITS5(1,1,1,1,1) -+ && INSN(15,10) == BITS6(0,0,0,0,0,0) -+ && INSN(4,0) == BITS5(0,0,0,0,0)) { -+ UInt branch_type = INSN(22,21); -+ UInt nn = INSN(9,5); -+ if (branch_type == BITS2(1,0) /* RET */) { -+ putPC(getIReg64orZR(nn)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Ret; -+ DIP("ret %s\n", nameIReg64orZR(nn)); -+ return True; -+ } -+ if (branch_type == BITS2(0,1) /* CALL */) { -+ putIReg64orSP(30, mkU64(guest_PC_curr_instr + 4)); -+ putPC(getIReg64orZR(nn)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Call; -+ DIP("blr %s\n", nameIReg64orZR(nn)); -+ return True; -+ } -+ if (branch_type == BITS2(0,0) /* JMP */) { -+ putPC(getIReg64orZR(nn)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("jmp %s\n", nameIReg64orZR(nn)); -+ return True; -+ } -+ } -+ -+ /* -------------------- CB{N}Z -------------------- */ -+ /* sf 011 010 1 imm19 Rt CBNZ Xt|Wt, (PC + sxTo64(imm19 << 2)) -+ sf 011 010 0 imm19 Rt CBZ Xt|Wt, (PC + sxTo64(imm19 << 2)) -+ */ -+ if (INSN(30,25) == BITS6(0,1,1,0,1,0)) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool bIfZ = INSN(24,24) == 0; -+ ULong uimm64 = INSN(23,5) << 2; -+ UInt rT = INSN(4,0); -+ Long simm64 = (Long)sx_to_64(uimm64, 21); -+ IRExpr* cond = NULL; -+ if (is64) { -+ cond = binop(bIfZ ? Iop_CmpEQ64 : Iop_CmpNE64, -+ getIReg64orZR(rT), mkU64(0)); -+ } else { -+ cond = binop(bIfZ ? Iop_CmpEQ32 : Iop_CmpNE32, -+ getIReg32orZR(rT), mkU32(0)); -+ } -+ stmt( IRStmt_Exit(cond, -+ Ijk_Boring, -+ IRConst_U64(guest_PC_curr_instr + simm64), -+ OFFB_PC) ); -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("cb%sz %s, 0x%llx\n", -+ bIfZ ? "" : "n", nameIRegOrZR(is64, rT), -+ guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* -------------------- TB{N}Z -------------------- */ -+ /* 31 30 24 23 18 5 4 -+ b5 011 011 1 b40 imm14 t TBNZ Xt, #(b5:b40), (PC + sxTo64(imm14 << 2)) -+ b5 011 011 0 b40 imm14 t TBZ Xt, #(b5:b40), (PC + sxTo64(imm14 << 2)) -+ */ -+ if (INSN(30,25) == BITS6(0,1,1,0,1,1)) { -+ UInt b5 = INSN(31,31); -+ Bool bIfZ = INSN(24,24) == 0; -+ UInt b40 = INSN(23,19); -+ UInt imm14 = INSN(18,5); -+ UInt tt = INSN(4,0); -+ UInt bitNo = (b5 << 5) | b40; -+ ULong uimm64 = imm14 << 2; -+ Long simm64 = sx_to_64(uimm64, 16); -+ IRExpr* cond -+ = binop(bIfZ ? Iop_CmpEQ64 : Iop_CmpNE64, -+ binop(Iop_And64, -+ binop(Iop_Shr64, getIReg64orZR(tt), mkU8(bitNo)), -+ mkU64(1)), -+ mkU64(0)); -+ stmt( IRStmt_Exit(cond, -+ Ijk_Boring, -+ IRConst_U64(guest_PC_curr_instr + simm64), -+ OFFB_PC) ); -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("tb%sz %s, #%u, 0x%llx\n", -+ bIfZ ? "" : "n", nameIReg64orZR(tt), bitNo, -+ guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* -------------------- SVC -------------------- */ -+ /* 11010100 000 imm16 000 01 -+ Don't bother with anything except the imm16==0 case. -+ */ -+ if (INSN(31,0) == 0xD4000001) { -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Sys_syscall; -+ DIP("svc #0\n"); -+ return True; -+ } -+ -+ /* ------------------ M{SR,RS} ------------------ */ -+ /* Only handles the case where the system register is TPIDR_EL0. -+ 0xD51BD0 010 Rt MSR tpidr_el0, rT -+ 0xD53BD0 010 Rt MRS rT, tpidr_el0 -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51BD040 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53BD040 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ stmt( IRStmt_Put( OFFB_TPIDR_EL0, getIReg64orZR(tt)) ); -+ DIP("msr tpidr_el0, %s\n", nameIReg64orZR(tt)); -+ } else { -+ putIReg64orZR(tt, IRExpr_Get( OFFB_TPIDR_EL0, Ity_I64 )); -+ DIP("mrs %s, tpidr_el0\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ /* Cases for FPCR -+ 0xD51B44 000 Rt MSR fpcr, rT -+ 0xD53B44 000 Rt MSR rT, fpcr -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4400 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4400 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ stmt( IRStmt_Put( OFFB_FPCR, getIReg32orZR(tt)) ); -+ DIP("msr fpcr, %s\n", nameIReg64orZR(tt)); -+ } else { -+ putIReg32orZR(tt, IRExpr_Get(OFFB_FPCR, Ity_I32)); -+ DIP("mrs %s, fpcr\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ /* Cases for FPSR -+ 0xD51B44 001 Rt MSR fpcr, rT -+ 0xD53B44 001 Rt MSR rT, fpcr -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4420 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4420 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ stmt( IRStmt_Put( OFFB_FPSR, getIReg32orZR(tt)) ); -+ DIP("msr fpsr, %s\n", nameIReg64orZR(tt)); -+ } else { -+ putIReg32orZR(tt, IRExpr_Get(OFFB_FPSR, Ity_I32)); -+ DIP("mrs %s, fpsr\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ /* Cases for NZCV -+ D51B42 000 Rt MSR nzcv, rT -+ D53B42 000 Rt MRS rT, nzcv -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4200 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4200 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ IRTemp t = newTemp(Ity_I64); -+ assign(t, binop(Iop_And64, getIReg64orZR(tt), mkU64(0xF0000000ULL))); -+ setFlags_COPY(t); -+ DIP("msr %s, nzcv\n", nameIReg32orZR(tt)); -+ } else { -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, mk_arm64g_calculate_flags_nzcv()); -+ putIReg32orZR(tt, unop(Iop_64to32, mkexpr(res))); -+ DIP("mrs %s, nzcv\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ -+ /* FIXME Temporary hacks to get through ld.so FIXME */ -+ /* ------------------ ISB ------------------ */ -+ if (INSN(31,0) == 0xD5033FDF) { -+ /* FIXME: not really a nop */ -+ DIP("isb\n"); -+ return True; -+ } -+ if (INSN(31,0) == 0xD5033BBF) { -+ /* FIXME: not really a nop */ -+ DIP("dmb ish\n"); -+ return True; -+ } -+ -+ //fail: -+ vex_printf("ARM64 front end: branch_etc\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- SIMD and FP instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Generate N copies of |bit| in the bottom of a ULong. */ -+static ULong Replicate ( ULong bit, Int N ) -+{ -+ vassert(bit <= 1 && N >= 1 && N < 64); -+ if (bit == 0) { -+ return 0; -+ } else { -+ /* Careful. This won't work for N == 64. */ -+ return (1ULL << N) - 1; -+ } -+} -+ -+static ULong VFPExpandImm ( ULong imm8, Int N ) -+{ -+ vassert(imm8 <= 0xFF); -+ vassert(N == 32 || N == 64); -+ Int E = ((N == 32) ? 8 : 11) - 2; // The spec incorrectly omits the -2. -+ Int F = N - E - 1; -+ ULong imm8_6 = (imm8 >> 6) & 1; -+ /* sign: 1 bit */ -+ /* exp: E bits */ -+ /* frac: F bits */ -+ ULong sign = (imm8 >> 7) & 1; -+ ULong exp = ((imm8_6 ^ 1) << (E-1)) | Replicate(imm8_6, E-1); -+ ULong frac = ((imm8 & 63) << (F-6)) | Replicate(0, F-6); -+ vassert(sign < (1ULL << 1)); -+ vassert(exp < (1ULL << E)); -+ vassert(frac < (1ULL << F)); -+ vassert(1 + E + F == N); -+ ULong res = (sign << (E+F)) | (exp << F) | frac; -+ return res; -+} -+ -+static -+Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ---------------- FMOV (general) ---------------- */ -+ /* case 30 23 20 18 15 9 4 -+ (1) 0 00 11110 00 1 00 111 000000 n d FMOV Sd, Wn -+ (2) 1 00 11110 01 1 00 111 000000 n d FMOV Dd, Xn -+ (3) 1 00 11110 10 1 01 111 000000 n d FMOV Vd.D[1], Xn -+ -+ (4) 0 00 11110 00 1 00 110 000000 n d FMOV Wd, Sn -+ (5) 1 00 11110 01 1 00 110 000000 n d FMOV Xd, Dn -+ (6) 1 00 11110 10 1 01 110 000000 n d FMOV Xd, Vn.D[1] -+ */ -+ if (INSN(30,24) == BITS7(0,0,1,1,1,1,0) -+ && INSN(21,21) == 1 && INSN(15,10) == BITS6(0,0,0,0,0,0)) { -+ UInt sf = INSN(31,31); -+ UInt ty = INSN(23,22); // type -+ UInt rm = INSN(20,19); // rmode -+ UInt op = INSN(18,16); // opcode -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt ix = 0; // case -+ if (sf == 0) { -+ if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,1)) -+ ix = 1; -+ else -+ if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,0)) -+ ix = 4; -+ } else { -+ vassert(sf == 1); -+ if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,1)) -+ ix = 2; -+ else -+ if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,0)) -+ ix = 5; -+ else -+ if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,1)) -+ ix = 3; -+ else -+ if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,0)) -+ ix = 6; -+ } -+ if (ix > 0) { -+ switch (ix) { -+ case 1: -+ putQReg128(dd, mkV128(0)); -+ putQReg(dd, getIReg32orZR(nn)); -+ DIP("fmov s%u, w%u\n", dd, nn); -+ break; -+ case 2: -+ putQReg128(dd, mkV128(0)); -+ putQReg(dd, getIReg64orZR(nn)); -+ DIP("fmov d%u, x%u\n", dd, nn); -+ break; -+ case 3: -+ putQReg64HI(dd, getIReg64orZR(nn)); -+ DIP("fmov v%u.d[1], x%u\n", dd, nn); -+ break; -+ case 4: -+ putIReg32orZR(dd, getQReg(Ity_I32, nn)); -+ DIP("fmov w%u, s%u\n", dd, nn); -+ break; -+ case 5: -+ putIReg64orZR(dd, getQReg(Ity_I64, nn)); -+ DIP("fmov x%u, d%u\n", dd, nn); -+ break; -+ case 6: -+ putIReg64orZR(dd, getQReg64HI(nn)); -+ DIP("fmov x%u, v%u.d[1]\n", dd, nn); -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ /* undecodable; fall through */ -+ } -+ -+ /* -------------- FMOV (scalar, immediate) -------------- */ -+ /* 31 28 23 20 12 9 4 -+ 000 11110 00 1 imm8 100 00000 d FMOV Sd, #imm -+ 000 11110 01 1 imm8 100 00000 d FMOV Dd, #imm -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,21) == 1 && INSN(12,5) == BITS8(1,0,0,0,0,0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt imm8 = INSN(20,13); -+ UInt dd = INSN(4,0); -+ ULong imm = VFPExpandImm(imm8, isD ? 64 : 32); -+ if (!isD) { -+ vassert(0 == (imm & 0xFFFFFFFF00000000)); -+ } -+ putQReg128(dd, mkV128(0)); -+ putQReg(dd, isD ? mkU64(imm) : mkU32(imm & 0xFFFFFFFFULL)); -+ DIP("fmov %s, #0x%llx\n", nameQReg(isD ? 8 : 4, dd), imm); -+ return True; -+ } -+ -+ /* -------------- {S,U}CVTF (scalar, integer) -------------- */ -+ /* 31 28 23 21 20 18 15 9 4 ix -+ 000 11110 00 1 00 010 000000 n d SCVTF Sd, Wn 0 -+ 000 11110 01 1 00 010 000000 n d SCVTF Dd, Wn 1 -+ 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn 2 -+ 100 11110 01 1 00 010 000000 n d SCVTF Dd, Xn 3 -+ -+ 000 11110 00 1 00 011 000000 n d UCVTF Sd, Wn 4 -+ 000 11110 01 1 00 011 000000 n d UCVTF Dd, Wn 5 -+ 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn 6 -+ 100 11110 01 1 00 011 000000 n d UCVTF Dd, Xn 7 -+ -+ These are signed/unsigned conversion from integer registers to -+ FP registers, all 4 32/64-bit combinations, rounded per FPCR. -+ */ -+ if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) && INSN(21,17) == BITS5(1,0,0,0,1) -+ && INSN(15,10) == BITS6(0,0,0,0,0,0)) { -+ Bool isI64 = INSN(31,31) == 1; -+ Bool isF64 = INSN(22,22) == 1; -+ Bool isU = INSN(16,16) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0); -+ const IROp ops[8] -+ = { Iop_I32StoF32, Iop_I32StoF64, Iop_I64StoF32, Iop_I64StoF64, -+ Iop_I32UtoF32, Iop_I32UtoF64, Iop_I64UtoF32, Iop_I64UtoF64 }; -+ IRExpr* src = getIRegOrZR(isI64, nn); -+ IRExpr* res = (isF64 && !isI64) -+ ? unop(ops[ix], src) -+ : binop(ops[ix], mkexpr(mk_get_IR_rounding_mode()), src); -+ putQReg128(dd, mkV128(0)); -+ putQReg(dd, res); -+ DIP("%ccvtf %s, %s\n", -+ isU ? 'u' : 's', nameQReg(isF64 ? 8 : 4, dd), -+ nameIRegOrZR(isI64, nn)); -+ return True; -+ } -+ -+ /* -------------- F{ADD,SUB,MUL,DIV} (scalar) -------------- */ -+ /* 31 23 20 15 11 9 4 -+ ---------------- 0000 ------ FMUL -------- -+ 000 11110 001 m 0001 10 n d FDIV Sd,Sn,Sm -+ 000 11110 011 m 0001 10 n d FDIV Dd,Dn,Dm -+ ---------------- 0010 ------ FADD -------- -+ ---------------- 0011 ------ FSUB -------- -+ ---------------- 1000 ------ FNMUL -------- -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt op = INSN(15,12); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IROp iop = Iop_INVALID; -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ UInt szB = isD ? 8 : 4; -+ Bool neg = False; -+ const HChar* nm = "???"; -+ switch (op) { -+ case BITS4(0,0,0,0): nm = "fmul"; iop = mkMULF(ty); break; -+ case BITS4(0,0,0,1): nm = "fdiv"; iop = mkDIVF(ty); break; -+ case BITS4(0,0,1,0): nm = "fadd"; iop = mkADDF(ty); break; -+ case BITS4(0,0,1,1): nm = "fsub"; iop = mkSUBF(ty); break; -+ case BITS4(1,0,0,0): nm = "fnmul"; iop = mkMULF(ty); -+ neg = True; break; -+ default: return False; -+ } -+ vassert(iop != Iop_INVALID); -+ IRExpr* resE = triop(iop, mkexpr(mk_get_IR_rounding_mode()), -+ getQReg(ty, nn), getQReg(ty, mm)); -+ IRTemp res = newTemp(ty); -+ assign(res, neg ? unop(mkNEGF(ty),resE) : resE); -+ putQReg128(dd, mkV128(0)); -+ putQReg(dd, mkexpr(res)); -+ DIP("%s %s, %s, %s\n", -+ nm, nameQReg(szB, dd), nameQReg(szB, nn), nameQReg(szB, mm)); -+ return True; -+ } -+ -+ /* ------------ F{MOV,ABS,NEG,SQRT} D/D or S/S ------------ */ -+ /* 31 23 21 16 14 9 4 -+ 000 11110 00 10000 00 10000 n d FMOV Sd, Sn -+ 000 11110 01 10000 00 10000 n d FMOV Dd, Dn -+ ------------------ 01 --------- FABS ------ -+ ------------------ 10 --------- FNEG ------ -+ ------------------ 11 --------- FQSRT ----- -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,17) == BITS5(1,0,0,0,0) -+ && INSN(14,10) == BITS5(1,0,0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt opc = INSN(16,15); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ UInt szB = isD ? 8 : 4; -+ IRTemp res = newTemp(ty); -+ if (opc == BITS2(0,0)) { -+ assign(res, getQReg(ty, nn)); -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(res)); -+ DIP("fmov %s, %s\n", nameQReg(szB, dd), nameQReg(szB, nn)); -+ return True; -+ } -+ if (opc == BITS2(1,0) || opc == BITS2(0,1)) { -+ Bool isAbs = opc == BITS2(0,1); -+ IROp op = isAbs ? mkABSF(ty) : mkNEGF(ty); -+ assign(res, unop(op, getQReg(ty, nn))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(res)); -+ DIP("%s %s, %s\n", isAbs ? "fabs" : "fneg", -+ nameQReg(szB, dd), nameQReg(szB, nn)); -+ return True; -+ } -+ if (opc == BITS2(1,1)) { -+ assign(res, -+ binop(mkSQRTF(ty), -+ mkexpr(mk_get_IR_rounding_mode()), getQReg(ty, nn))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(res)); -+ DIP("fsqrt %s, %s\n", nameQReg(szB, dd), nameQReg(szB, nn)); -+ return True; -+ } -+ /* else fall through; other cases are ATC */ -+ } -+ -+ /* -------------------- FCMP,FCMPE -------------------- */ -+ /* 31 23 20 15 9 4 -+ 000 11110 01 1 m 00 1000 n 10 000 FCMPE Dn, Dm -+ 000 11110 01 1 00000 00 1000 n 11 000 FCMPE Dn, #0.0 -+ 000 11110 01 1 m 00 1000 n 00 000 FCMP Dn, Dm -+ 000 11110 01 1 00000 00 1000 n 01 000 FCMP Dn, #0.0 -+ -+ 000 11110 00 1 m 00 1000 n 10 000 FCMPE Sn, Sm -+ 000 11110 00 1 00000 00 1000 n 11 000 FCMPE Sn, #0.0 -+ 000 11110 00 1 m 00 1000 n 00 000 FCMP Sn, Sm -+ 000 11110 00 1 00000 00 1000 n 01 000 FCMP Sn, #0.0 -+ -+ FCMPE generates Invalid Operation exn if either arg is any kind -+ of NaN. FCMP generates Invalid Operation exn if either arg is a -+ signalling NaN. We ignore this detail here and produce the same -+ IR for both. -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) && INSN(21,21) == 1 -+ && INSN(15,10) == BITS6(0,0,1,0,0,0) && INSN(2,0) == BITS3(0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ Bool isCMPE = INSN(4,4) == 1; -+ Bool cmpZero = INSN(3,3) == 1; -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ UInt szB = isD ? 8 : 4; -+ Bool valid = True; -+ if (cmpZero && mm != 0) valid = False; -+ if (valid) { -+ IRTemp argL = newTemp(ty); -+ IRTemp argR = newTemp(ty); -+ IRTemp irRes = newTemp(Ity_I32); -+ assign(argL, getQReg(ty, nn)); -+ assign(argR, -+ cmpZero -+ ? (IRExpr_Const(isD ? IRConst_F64i(0) : IRConst_F32i(0))) -+ : getQReg(ty, mm)); -+ assign(irRes, binop(isD ? Iop_CmpF64 : Iop_CmpF32, -+ mkexpr(argL), mkexpr(argR))); -+ IRTemp nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes); -+ IRTemp nzcv_28x0 = newTemp(Ity_I64); -+ assign(nzcv_28x0, binop(Iop_Shl64, mkexpr(nzcv), mkU8(28))); -+ setFlags_COPY(nzcv_28x0); -+ DIP("fcmp%s %s, %s\n", isCMPE ? "e" : "", -+ nameQReg(szB, nn), cmpZero ? "#0.0" : nameQReg(szB, mm)); -+ return True; -+ } -+ } -+ -+ /* -------------------- F{N}M{ADD,SUB} -------------------- */ -+ /* 31 22 20 15 14 9 4 ix -+ 000 11111 0 sz 0 m 0 a n d 0 FMADD Fd,Fn,Fm,Fa -+ 000 11111 0 sz 0 m 1 a n d 1 FMSUB Fd,Fn,Fm,Fa -+ 000 11111 0 sz 1 m 0 a n d 2 FNMADD Fd,Fn,Fm,Fa -+ 000 11111 0 sz 1 m 1 a n d 3 FNMSUB Fd,Fn,Fm,Fa -+ where Fx=Dx when sz=1, Fx=Sx when sz=0 -+ -+ -----SPEC------ ----IMPL---- -+ fmadd a + n * m a + n * m -+ fmsub a + (-n) * m a - n * m -+ fnmadd (-a) + (-n) * m -(a + n * m) -+ fnmsub (-a) + n * m -(a - n * m) -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,1,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt aa = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt ix = (INSN(21,21) << 1) | INSN(15,15); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ UInt szB = isD ? 8 : 4; -+ IROp opADD = mkADDF(ty); -+ IROp opSUB = mkSUBF(ty); -+ IROp opMUL = mkMULF(ty); -+ IROp opNEG = mkNEGF(ty); -+ IRTemp res = newTemp(ty); -+ IRExpr* eA = getQReg(ty, aa); -+ IRExpr* eN = getQReg(ty, nn); -+ IRExpr* eM = getQReg(ty, mm); -+ IRExpr* rm = mkexpr(mk_get_IR_rounding_mode()); -+ IRExpr* eNxM = triop(opMUL, rm, eN, eM); -+ switch (ix) { -+ case 0: assign(res, triop(opADD, rm, eA, eNxM)); break; -+ case 1: assign(res, triop(opSUB, rm, eA, eNxM)); break; -+ case 2: assign(res, unop(opNEG, triop(opADD, rm, eA, eNxM))); break; -+ case 3: assign(res, unop(opNEG, triop(opSUB, rm, eA, eNxM))); break; -+ default: vassert(0); -+ } -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(res)); -+ const HChar* names[4] = { "fmadd", "fmsub", "fnmadd", "fnmsub" }; -+ DIP("%s %s, %s, %s, %s\n", -+ names[ix], nameQReg(szB, dd), nameQReg(szB, nn), -+ nameQReg(szB, mm), nameQReg(szB, aa)); -+ return True; -+ } -+ -+ /* -------- FCVT{N,P,M,Z}{S,U} (scalar, integer) -------- */ -+ /* 30 23 20 18 15 9 4 -+ sf 00 11110 0x 1 00 000 000000 n d FCVTNS Rd, Fn (round to -+ sf 00 11110 0x 1 00 001 000000 n d FCVTNU Rd, Fn nearest) -+ ---------------- 01 -------------- FCVTP-------- (round to +inf) -+ ---------------- 10 -------------- FCVTM-------- (round to -inf) -+ ---------------- 11 -------------- FCVTZ-------- (round to zero) -+ -+ Rd is Xd when sf==1, Wd when sf==0 -+ Fn is Dn when x==1, Sn when x==0 -+ 20:19 carry the rounding mode, using the same encoding as FPCR -+ */ -+ if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) && INSN(21,21) == 1 -+ && INSN(18,17) == BITS2(0,0) && INSN(15,10) == BITS6(0,0,0,0,0,0)) { -+ Bool isI64 = INSN(31,31) == 1; -+ Bool isF64 = INSN(22,22) == 1; -+ UInt rm = INSN(20,19); -+ Bool isU = INSN(16,16) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ /* Decide on the IR rounding mode to use. */ -+ IRRoundingMode irrm = 8; /*impossible*/ -+ HChar ch = '?'; -+ switch (rm) { -+ case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break; -+ case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break; -+ case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break; -+ case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break; -+ default: vassert(0); -+ } -+ vassert(irrm != 8); -+ /* Decide on the conversion primop, based on the source size, -+ dest size and signedness (8 possibilities). Case coding: -+ F32 ->s I32 0 -+ F32 ->u I32 1 -+ F32 ->s I64 2 -+ F32 ->u I64 3 -+ F64 ->s I32 4 -+ F64 ->u I32 5 -+ F64 ->s I64 6 -+ F64 ->u I64 7 -+ */ -+ UInt ix = (isF64 ? 4 : 0) | (isI64 ? 2 : 0) | (isU ? 1 : 0); -+ vassert(ix < 8); -+ const IROp ops[8] -+ = { Iop_F32toI32S, Iop_F32toI32U, Iop_F32toI64S, Iop_F32toI64U, -+ Iop_F64toI32S, Iop_F64toI32U, Iop_F64toI64S, Iop_F64toI64U }; -+ IROp op = ops[ix]; -+ // A bit of ATCery: bounce all cases we haven't seen an example of. -+ if (/* F32toI32S */ -+ (op == Iop_F32toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Sn */ -+ /* F32toI32U */ -+ /* F32toI64S */ -+ /* F32toI64U */ -+ || (op == Iop_F32toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Sn */ -+ /* F64toI32S */ -+ || (op == Iop_F64toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Dn */ -+ || (op == Iop_F64toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Dn */ -+ || (op == Iop_F64toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Dn */ -+ /* F64toI32U */ -+ || (op == Iop_F64toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Dn */ -+ || (op == Iop_F64toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Dn */ -+ /* F64toI64S */ -+ || (op == Iop_F64toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Dn */ -+ /* F64toI64U */ -+ || (op == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */ -+ ) { -+ /* validated */ -+ } else { -+ return False; -+ } -+ UInt srcSzB = isF64 ? 8 : 4; -+ IRType srcTy = isF64 ? Ity_F64 : Ity_F32; -+ IRType dstTy = isI64 ? Ity_I64 : Ity_I32; -+ IRTemp src = newTemp(srcTy); -+ IRTemp dst = newTemp(dstTy); -+ assign(src, getQReg(srcTy, nn)); -+ assign(dst, binop(op, mkU32(irrm), mkexpr(src))); -+ putIRegOrZR(isI64, dd, mkexpr(dst)); -+ DIP("fcvt%c%c %s, %s\n", ch, isU ? 'u' : 's', -+ nameIRegOrZR(isI64, dd), nameQReg(srcSzB, nn)); -+ return True; -+ } -+ -+ /* ---------------- FRINT{I,M,P,Z} (scalar) ---------------- */ -+ /* 31 23 21 17 14 9 4 -+ 000 11110 0x 1001 111 10000 n d FRINTI Fd, Fm (round per FPCR) -+ rm -+ x==0 => S-registers, x==1 => D-registers -+ rm (17:15) encodings: -+ 111 per FPCR (FRINTI) -+ 001 +inf (FRINTP) -+ 010 -inf (FRINTM) -+ 011 zero (FRINTZ) -+ 000 tieeven -+ 100 tieaway -+ 110 per FPCR + "exact = TRUE" -+ 101 unallocated -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,18) == BITS4(1,0,0,1) && INSN(14,10) == BITS5(1,0,0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt rm = INSN(17,15); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ UInt szB = isD ? 8 : 4; -+ IRExpr* irrmE = NULL; -+ UChar ch = '?'; -+ switch (rm) { -+ case BITS3(0,1,1): ch = 'z'; irrmE = mkU32(Irrm_ZERO); break; -+ case BITS3(0,1,0): ch = 'm'; irrmE = mkU32(Irrm_NegINF); break; -+ case BITS3(0,0,1): ch = 'p'; irrmE = mkU32(Irrm_PosINF); break; -+ default: break; -+ } -+ if (irrmE) { -+ IRTemp src = newTemp(ty); -+ IRTemp dst = newTemp(ty); -+ assign(src, getQReg(ty, nn)); -+ assign(dst, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt, -+ irrmE, mkexpr(src))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(dst)); -+ DIP("frint%c %s, %s\n", ch, nameQReg(szB, dd), nameQReg(szB, nn)); -+ return True; -+ } -+ /* else unhandled rounding mode case -- fall through */ -+ } -+ -+ /* ------------------ FCVT (scalar) ------------------ */ -+ /* 31 23 21 16 14 9 4 -+ 000 11110 11 10001 00 10000 n d FCVT Sd, Hn (unimp) -+ --------- 11 ----- 01 --------- FCVT Dd, Hn (unimp) -+ --------- 00 ----- 11 --------- FCVT Hd, Sn (unimp) -+ --------- 00 ----- 01 --------- FCVT Dd, Sn (unimp) -+ --------- 01 ----- 11 --------- FCVT Hd, Dn (unimp) -+ --------- 01 ----- 00 --------- FCVT Sd, Dn (unimp) -+ Rounding, when dst is smaller than src, is per the FPCR. -+ */ -+ if (INSN(31,24) == BITS8(0,0,0,1,1,1,1,0) -+ && INSN(21,17) == BITS5(1,0,0,0,1) -+ && INSN(14,10) == BITS5(1,0,0,0,0)) { -+ UInt b2322 = INSN(23,22); -+ UInt b1615 = INSN(16,15); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (b2322 == BITS2(0,0) && b1615 == BITS2(0,1)) { -+ /* Convert S to D */ -+ IRTemp res = newTemp(Ity_F64); -+ assign(res, unop(Iop_F32toF64, getQReg(Ity_F32, nn))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(res)); -+ DIP("fcvt %s, %s\n", nameQReg(8, dd), nameQReg(4, nn)); -+ return True; -+ } -+ if (b2322 == BITS2(0,1) && b1615 == BITS2(0,0)) { -+ /* Convert D to S */ -+ IRTemp res = newTemp(Ity_F32); -+ assign(res, binop(Iop_F64toF32, mkexpr(mk_get_IR_rounding_mode()), -+ getQReg(Ity_F64, nn))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(res)); -+ DIP("fcvt %s, %s\n", nameQReg(4, dd), nameQReg(8, nn)); -+ return True; -+ } -+ /* else unhandled */ -+ } -+ -+ /* ------------------ FABD (scalar) ------------------ */ -+ /* 31 23 20 15 9 4 -+ 011 11110 111 m 110101 n d FABD Dd, Dn, Dm -+ 011 11110 101 m 110101 n d FABD Sd, Sn, Sm -+ */ -+ if (INSN(31,23) == BITS9(0,1,1,1,1,1,1,0,1) && INSN(21,21) == 1 -+ && INSN(15,10) == BITS6(1,1,0,1,0,1)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ UInt szB = isD ? 8 : 4; -+ IRTemp res = newTemp(ty); -+ assign(res, unop(mkABSF(ty), triop(mkSUBF(ty), -+ mkexpr(mk_get_IR_rounding_mode()), -+ getQReg(ty,nn), getQReg(ty,mm)))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQReg(dd, mkexpr(res)); -+ DIP("fabd %s, %s, %s\n", -+ nameQReg(szB, dd), nameQReg(szB, nn), nameQReg(szB, mm)); -+ return True; -+ } -+ -+ /* FIXME Temporary hacks to get through ld.so FIXME */ -+ -+ /* ------------------ movi vD.4s, #0x0 ------------------ */ -+ /* 0x4F 0x00 0x04 000 vD */ -+ if ((insn & 0xFFFFFFE0) == 0x4F000400) { -+ UInt vD = INSN(4,0); -+ putQReg128(vD, mkV128(0x0000)); -+ DIP("movi v%u.4s, #0x0\n", vD); -+ return True; -+ } -+ -+ /* ------------------ dup vD.2d, xN ------------------ */ -+ /* 0x4E 0x08 0000 11 xN(5) vD(5) */ -+ if ((insn & 0xFFFFFC00) == 0x4E080C00) { -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp src64 = newTemp(Ity_I64); -+ assign(src64, getIReg64orZR(nn)); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, binop(Iop_64HLtoV128, mkexpr(src64), mkexpr(src64))); -+ putQReg128(dd, mkexpr(res)); -+ DIP("dup v%u.2d, x%u\n", dd, nn); -+ return True; -+ } -+ -+ /* ---------------- MOV vD.16b, vN.16b ---------------- */ -+ /* 31 23 20 15 9 4 -+ 010 01110 101 m 000111 n d ORR vD.16b, vN.16b, vM.16b -+ This only handles the N == M case. -+ */ -+ if (INSN(31,24) == BITS8(0,1,0,0,1,1,1,0) -+ && INSN(23,21) == BITS3(1,0,1) && INSN(15,10) == BITS6(0,0,0,1,1,1)) { -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (mm == nn) { -+ putQReg128(dd, getQReg128(nn)); -+ DIP("mov v%u.16b, v%u.16b\n", dd, nn); -+ return True; -+ } -+ /* else it's really an ORR; fall through. */ -+ } -+ -+ vex_printf("ARM64 front end: simd_and_fp\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Disassemble a single ARM64 instruction ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Disassemble a single ARM64 instruction into IR. The instruction -+ has is located at |guest_instr| and has guest IP of -+ |guest_PC_curr_instr|, which will have been set before the call -+ here. Returns True iff the instruction was decoded, in which case -+ *dres will be set accordingly, or False, in which case *dres should -+ be ignored by the caller. */ -+ -+static -+Bool disInstr_ARM64_WRK ( -+ /*MB_OUT*/DisResult* dres, -+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), -+ Bool resteerCisOk, -+ void* callback_opaque, -+ UChar* guest_instr, -+ VexArchInfo* archinfo, -+ VexAbiInfo* abiinfo -+ ) -+{ -+ // A macro to fish bits out of 'insn'. -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+//ZZ DisResult dres; -+//ZZ UInt insn; -+//ZZ //Bool allow_VFP = False; -+//ZZ //UInt hwcaps = archinfo->hwcaps; -+//ZZ IRTemp condT; /* :: Ity_I32 */ -+//ZZ UInt summary; -+//ZZ HChar dis_buf[128]; // big enough to hold LDMIA etc text -+//ZZ -+//ZZ /* What insn variants are we supporting today? */ -+//ZZ //allow_VFP = (0 != (hwcaps & VEX_HWCAPS_ARM_VFP)); -+//ZZ // etc etc -+ -+ /* Set result defaults. */ -+ dres->whatNext = Dis_Continue; -+ dres->len = 4; -+ dres->continueAt = 0; -+ dres->jk_StopHere = Ijk_INVALID; -+ -+ /* At least this is simple on ARM64: insns are all 4 bytes long, and -+ 4-aligned. So just fish the whole thing out of memory right now -+ and have done. */ -+ UInt insn = getUIntLittleEndianly( guest_instr ); -+ -+ if (0) vex_printf("insn: 0x%x\n", insn); -+ -+ DIP("\t(arm64) 0x%llx: ", (ULong)guest_PC_curr_instr); -+ -+ vassert(0 == (guest_PC_curr_instr & 3ULL)); -+ -+ /* ----------------------------------------------------------- */ -+ -+ /* Spot "Special" instructions (see comment at top of file). */ -+ { -+ UChar* code = (UChar*)guest_instr; -+ /* Spot the 16-byte preamble: -+ 93CC0D8C ror x12, x12, #3 -+ 93CC358C ror x12, x12, #13 -+ 93CCCD8C ror x12, x12, #51 -+ 93CCF58C ror x12, x12, #61 -+ */ -+ UInt word1 = 0x93CC0D8C; -+ UInt word2 = 0x93CC358C; -+ UInt word3 = 0x93CCCD8C; -+ UInt word4 = 0x93CCF58C; -+ if (getUIntLittleEndianly(code+ 0) == word1 && -+ getUIntLittleEndianly(code+ 4) == word2 && -+ getUIntLittleEndianly(code+ 8) == word3 && -+ getUIntLittleEndianly(code+12) == word4) { -+ /* Got a "Special" instruction preamble. Which one is it? */ -+ if (getUIntLittleEndianly(code+16) == 0xAA0A014A -+ /* orr x10,x10,x10 */) { -+ /* X3 = client_request ( X4 ) */ -+ DIP("x3 = client_request ( x4 )\n"); -+ putPC(mkU64( guest_PC_curr_instr + 20 )); -+ dres->jk_StopHere = Ijk_ClientReq; -+ dres->whatNext = Dis_StopHere; -+ return True; -+ } -+ else -+ if (getUIntLittleEndianly(code+16) == 0xAA0B016B -+ /* orr x11,x11,x11 */) { -+ /* X3 = guest_NRADDR */ -+ DIP("x3 = guest_NRADDR\n"); -+ dres->len = 20; -+ putIReg64orZR(3, IRExpr_Get( OFFB_NRADDR, Ity_I64 )); -+ return True; -+ } -+ else -+ if (getUIntLittleEndianly(code+16) == 0xAA0C018C -+ /* orr x12,x12,x12 */) { -+ /* branch-and-link-to-noredir X8 */ -+ DIP("branch-and-link-to-noredir x8\n"); -+ putIReg64orZR(30, mkU64(guest_PC_curr_instr + 20)); -+ putPC(getIReg64orZR(8)); -+ dres->jk_StopHere = Ijk_NoRedir; -+ dres->whatNext = Dis_StopHere; -+ return True; -+ } -+ else -+ if (getUIntLittleEndianly(code+16) == 0xAA090129 -+ /* orr x9,x9,x9 */) { -+ /* IR injection */ -+ DIP("IR injection\n"); -+ vex_inject_ir(irsb, Iend_LE); -+ // Invalidate the current insn. The reason is that the IRop we're -+ // injecting here can change. In which case the translation has to -+ // be redone. For ease of handling, we simply invalidate all the -+ // time. -+ stmt(IRStmt_Put(OFFB_TISTART, mkU64(guest_PC_curr_instr))); -+ stmt(IRStmt_Put(OFFB_TILEN, mkU64(20))); -+ putPC(mkU64( guest_PC_curr_instr + 20 )); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_TInval; -+ return True; -+ } -+ /* We don't know what it is. */ -+ return False; -+ /*NOTREACHED*/ -+ } -+ } -+ -+ /* ----------------------------------------------------------- */ -+ -+ /* Main ARM64 instruction decoder starts here. */ -+ -+ Bool ok = False; -+ -+ /* insn[28:25] determines the top-level grouping, so let's start -+ off with that. -+ -+ For all of these dis_ARM64_ functions, we pass *dres with the -+ normal default results "insn OK, 4 bytes long, keep decoding" so -+ they don't need to change it. However, decodes of control-flow -+ insns may cause *dres to change. -+ */ -+ switch (INSN(28,25)) { -+ case BITS4(1,0,0,0): case BITS4(1,0,0,1): -+ // Data processing - immediate -+ ok = dis_ARM64_data_processing_immediate(dres, insn); -+ break; -+ case BITS4(1,0,1,0): case BITS4(1,0,1,1): -+ // Branch, exception generation and system instructions -+ ok = dis_ARM64_branch_etc(dres, insn); -+ break; -+ case BITS4(0,1,0,0): case BITS4(0,1,1,0): -+ case BITS4(1,1,0,0): case BITS4(1,1,1,0): -+ // Loads and stores -+ ok = dis_ARM64_load_store(dres, insn); -+ break; -+ case BITS4(0,1,0,1): case BITS4(1,1,0,1): -+ // Data processing - register -+ ok = dis_ARM64_data_processing_register(dres, insn); -+ break; -+ case BITS4(0,1,1,1): case BITS4(1,1,1,1): -+ // Data processing - SIMD and floating point -+ ok = dis_ARM64_simd_and_fp(dres, insn); -+ break; -+ case BITS4(0,0,0,0): case BITS4(0,0,0,1): -+ case BITS4(0,0,1,0): case BITS4(0,0,1,1): -+ // UNALLOCATED -+ break; -+ default: -+ vassert(0); /* Can't happen */ -+ } -+ -+ /* If the next-level down decoders failed, make sure |dres| didn't -+ get changed. */ -+ if (!ok) { -+ vassert(dres->whatNext == Dis_Continue); -+ vassert(dres->len == 4); -+ vassert(dres->continueAt == 0); -+ vassert(dres->jk_StopHere == Ijk_INVALID); -+ } -+ -+ return ok; -+ -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Top-level fn ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Disassemble a single instruction into IR. The instruction -+ is located in host memory at &guest_code[delta]. */ -+ -+DisResult disInstr_ARM64 ( IRSB* irsb_IN, -+ Bool (*resteerOkFn) ( void*, Addr64 ), -+ Bool resteerCisOk, -+ void* callback_opaque, -+ UChar* guest_code_IN, -+ Long delta_IN, -+ Addr64 guest_IP, -+ VexArch guest_arch, -+ VexArchInfo* archinfo, -+ VexAbiInfo* abiinfo, -+ Bool host_bigendian_IN, -+ Bool sigill_diag_IN ) -+{ -+ DisResult dres; -+ vex_bzero(&dres, sizeof(dres)); -+ -+ /* Set globals (see top of this file) */ -+ vassert(guest_arch == VexArchARM64); -+ -+ irsb = irsb_IN; -+ host_is_bigendian = host_bigendian_IN; -+ guest_PC_curr_instr = (Addr64)guest_IP; -+ -+ /* Try to decode */ -+ Bool ok = disInstr_ARM64_WRK( &dres, -+ resteerOkFn, resteerCisOk, callback_opaque, -+ (UChar*)&guest_code_IN[delta_IN], -+ archinfo, abiinfo ); -+ if (ok) { -+ /* All decode successes end up here. */ -+ vassert(dres.len == 4 /*|| dres.len == 20*/); -+ switch (dres.whatNext) { -+ case Dis_Continue: -+ putPC( mkU64(dres.len + guest_PC_curr_instr) ); -+ break; -+ case Dis_ResteerU: -+ case Dis_ResteerC: -+ putPC(mkU64(dres.continueAt)); -+ break; -+ case Dis_StopHere: -+ break; -+ default: -+ vassert(0); -+ } -+ DIP("\n"); -+ } else { -+ /* All decode failures end up here. */ -+ if (sigill_diag_IN) { -+ Int i, j; -+ UChar buf[64]; -+ UInt insn -+ = getUIntLittleEndianly( (UChar*)&guest_code_IN[delta_IN] ); -+ vex_bzero(buf, sizeof(buf)); -+ for (i = j = 0; i < 32; i++) { -+ if (i > 0) { -+ if ((i & 7) == 0) buf[j++] = ' '; -+ else if ((i & 3) == 0) buf[j++] = '\''; -+ } -+ buf[j++] = (insn & (1<<(31-i))) ? '1' : '0'; -+ } -+ vex_printf("disInstr(arm64): unhandled instruction 0x%08x\n", insn); -+ vex_printf("disInstr(arm64): %s\n", buf); -+ } -+ -+ /* Tell the dispatcher that this insn cannot be decoded, and so -+ has not been executed, and (is currently) the next to be -+ executed. PC should be up-to-date since it is made so at the -+ start of each insn, but nevertheless be paranoid and update -+ it again right now. */ -+ putPC( mkU64(guest_PC_curr_instr) ); -+ dres.whatNext = Dis_StopHere; -+ dres.len = 0; -+ dres.continueAt = 0; -+ dres.jk_StopHere = Ijk_NoDecode; -+ } -+ return dres; -+} -+ -+/*--------------------------------------------------------------------*/ -+/*--- end guest_arm64_toIR.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: VEX/priv/host_generic_simd64.c -=================================================================== ---- VEX/priv/host_generic_simd64.c.orig -+++ VEX/priv/host_generic_simd64.c -@@ -1553,7 +1553,11 @@ ULong h_calc_BCDtoDPB( ULong bcd ) - - /* ----------------------------------------------------- */ - /* Signed and unsigned integer division, that behave like -- the ARMv7 UDIV ansd SDIV instructions. */ -+ the ARMv7 UDIV ansd SDIV instructions. -+ -+ sdiv32 also behaves like 64-bit v8 SDIV on w-regs. -+ udiv32 also behaves like 64-bit v8 UDIV on w-regs. -+*/ - /* ----------------------------------------------------- */ - - UInt h_calc_udiv32_w_arm_semantics ( UInt x, UInt y ) -@@ -1564,17 +1568,40 @@ UInt h_calc_udiv32_w_arm_semantics ( UIn - return x / y; - } - -+ULong h_calc_udiv64_w_arm_semantics ( ULong x, ULong y ) -+{ -+ // Division by zero --> zero -+ if (UNLIKELY(y == 0)) return 0; -+ // C requires rounding towards zero, which is also what we need. -+ return x / y; -+} -+ - Int h_calc_sdiv32_w_arm_semantics ( Int x, Int y ) - { - // Division by zero --> zero - if (UNLIKELY(y == 0)) return 0; -- // The single case that produces an unpresentable result -+ // The single case that produces an unrepresentable result - if (UNLIKELY( ((UInt)x) == ((UInt)0x80000000) - && ((UInt)y) == ((UInt)0xFFFFFFFF) )) - return (Int)(UInt)0x80000000; - // Else return the result rounded towards zero. C89 says - // this is implementation defined (in the signed case), but gcc - // promises to round towards zero. Nevertheless, at startup, -+ // in main_main.c, do a check for that. -+ return x / y; -+} -+ -+Long h_calc_sdiv64_w_arm_semantics ( Long x, Long y ) -+{ -+ // Division by zero --> zero -+ if (UNLIKELY(y == 0)) return 0; -+ // The single case that produces an unrepresentable result -+ if (UNLIKELY( ((ULong)x) == ((ULong)0x8000000000000000ULL ) -+ && ((ULong)y) == ((ULong)0xFFFFFFFFFFFFFFFFULL ) )) -+ return (Long)(ULong)0x8000000000000000ULL; -+ // Else return the result rounded towards zero. C89 says -+ // this is implementation defined (in the signed case), but gcc -+ // promises to round towards zero. Nevertheless, at startup, - // in main_main.c, do a check for that. - return x / y; - } -Index: VEX/priv/host_generic_simd64.h -=================================================================== ---- VEX/priv/host_generic_simd64.h.orig -+++ VEX/priv/host_generic_simd64.h -@@ -166,8 +166,11 @@ extern ULong h_calc_BCDtoDPB ( ULong bcd - - // Signed and unsigned integer division, that behave like - // the ARMv7 UDIV and SDIV instructions. --extern UInt h_calc_udiv32_w_arm_semantics ( UInt, UInt ); --extern Int h_calc_sdiv32_w_arm_semantics ( Int, Int ); -+extern UInt h_calc_udiv32_w_arm_semantics ( UInt, UInt ); -+extern ULong h_calc_udiv64_w_arm_semantics ( ULong, ULong ); -+extern Int h_calc_sdiv32_w_arm_semantics ( Int, Int ); -+extern Long h_calc_sdiv64_w_arm_semantics ( Long, Long ); -+ - - #endif /* ndef __VEX_HOST_GENERIC_SIMD64_H */ - -Index: VEX/priv/guest_arm64_helpers.c -=================================================================== ---- /dev/null -+++ VEX/priv/guest_arm64_helpers.c -@@ -0,0 +1,1292 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin guest_arm64_helpers.c ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "libvex_basictypes.h" -+#include "libvex_emnote.h" -+#include "libvex_guest_arm64.h" -+#include "libvex_ir.h" -+#include "libvex.h" -+ -+#include "main_util.h" -+#include "main_globals.h" -+#include "guest_generic_bb_to_IR.h" -+#include "guest_arm64_defs.h" -+ -+ -+/* This file contains helper functions for arm guest code. Calls to -+ these functions are generated by the back end. These calls are of -+ course in the host machine code and this file will be compiled to -+ host machine code, so that all makes sense. -+ -+ Only change the signatures of these helper functions very -+ carefully. If you change the signature here, you'll have to change -+ the parameters passed to it in the IR calls constructed by -+ guest_arm64_toIR.c. -+*/ -+ -+ -+/* Set to 1 to get detailed profiling info about individual N, Z, C -+ and V flag evaluation. */ -+#define PROFILE_NZCV_FLAGS 0 -+ -+#if PROFILE_NZCV_FLAGS -+ -+static UInt tab_eval[ARM64G_CC_OP_NUMBER][16]; -+static UInt initted = 0; -+static UInt tot_evals = 0; -+ -+static void initCounts ( void ) -+{ -+ UInt i, j; -+ for (i = 0; i < ARM64G_CC_OP_NUMBER; i++) { -+ for (j = 0; j < 16; j++) { -+ tab_eval[i][j] = 0; -+ } -+ } -+ initted = 1; -+} -+ -+static void showCounts ( void ) -+{ -+ const HChar* nameCC[16] -+ = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", -+ "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" }; -+ UInt i, j; -+ ULong sum = 0; -+ vex_printf("\nCC_OP 0 1 2 3 " -+ " 4 5 6\n"); -+ vex_printf( "--------------------------------------------------" -+ "--------------------------\n"); -+ for (j = 0; j < 16; j++) { -+ vex_printf("%2d %s ", j, nameCC[j]); -+ for (i = 0; i < ARM64G_CC_OP_NUMBER; i++) { -+ vex_printf("%9d ", tab_eval[i][j]); -+ sum += tab_eval[i][j]; -+ } -+ vex_printf("\n"); -+ } -+ vex_printf("(In total %llu calls)\n", sum); -+} -+ -+#define NOTE_EVAL(_cc_op, _cond) \ -+ do { \ -+ if (!initted) initCounts(); \ -+ vassert( ((UInt)(_cc_op)) < ARM64G_CC_OP_NUMBER); \ -+ vassert( ((UInt)(_cond)) < 16); \ -+ tab_eval[(UInt)(_cc_op)][(UInt)(cond)]++; \ -+ tot_evals++; \ -+ if (0 == (tot_evals & 0x7FFF)) \ -+ showCounts(); \ -+ } while (0) -+ -+#endif /* PROFILE_NZCV_FLAGS */ -+ -+ -+/* Calculate the N flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_n ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong nf = (cc_dep1 >> ARM64G_CC_SHIFT_N) & 1; -+ return nf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong nf = (ULong)(res >> 31); -+ return nf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong nf = (ULong)(res >> 63); -+ return nf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL - argR; -+ ULong nf = (ULong)(res >> 31); -+ return nf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL - argR; -+ ULong nf = res >> 63; -+ return nf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt nf = res >> 31; -+//ZZ return nf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL - argR - (oldC ^ 1); -+//ZZ UInt nf = res >> 31; -+//ZZ return nf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: { -+ /* (res, unused, unused) */ -+ UInt res = (UInt)cc_dep1; -+ ULong nf = res >> 31; -+ return nf; -+ } -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ ULong res = cc_dep1; -+ ULong nf = res >> 63; -+ return nf; -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt res = cc_dep1; -+//ZZ UInt nf = res >> 31; -+//ZZ return nf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt resHi32 = cc_dep2; -+//ZZ UInt nf = resHi32 >> 31; -+//ZZ return nf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_n" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_n"); -+ } -+} -+ -+ -+/* Calculate the Z flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_z ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong zf = (cc_dep1 >> ARM64G_CC_SHIFT_Z) & 1; -+ return zf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL - argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL - argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt zf = res == 0; -+//ZZ return zf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL - argR - (oldC ^ 1); -+//ZZ UInt zf = res == 0; -+//ZZ return zf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: { -+ /* (res, unused, unused) */ -+ UInt res = (UInt)cc_dep1; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ ULong res = cc_dep1; -+ ULong zf = res == 0; -+ return zf; -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt res = cc_dep1; -+//ZZ UInt zf = res == 0; -+//ZZ return zf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt resLo32 = cc_dep1; -+//ZZ UInt resHi32 = cc_dep2; -+//ZZ UInt zf = (resHi32|resLo32) == 0; -+//ZZ return zf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_z" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_z"); -+ } -+} -+ -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate the C flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_c ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong cf = (cc_dep1 >> ARM64G_CC_SHIFT_C) & 1; -+ return cf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong cf = res < argL; -+ return cf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong cf = res < argL; -+ return cf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ ULong cf = argL >= argR; -+ return cf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong cf = argL >= argR; -+ return cf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt cf = oldC ? (res <= argL) : (res < argL); -+//ZZ return cf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt cf = oldC ? (argL >= argR) : (argL > argR); -+//ZZ return cf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ return 0; // C after logic is zero on arm64 -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt oldC = (cc_dep3 >> 1) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt cf = oldC; -+//ZZ return cf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt oldC = (cc_dep3 >> 1) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt cf = oldC; -+//ZZ return cf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_c" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_c"); -+ } -+} -+ -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate the V flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_v ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong vf = (cc_dep1 >> ARM64G_CC_SHIFT_V) & 1; -+ return vf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong vf = (ULong)(((res ^ argL) & (res ^ argR)) >> 31); -+ return vf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong vf = ((res ^ argL) & (res ^ argR)) >> 63; -+ return vf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL - argR; -+ ULong vf = (ULong)(((argL ^ argR) & (argL ^ res)) >> 31); -+ return vf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL - argR; -+ ULong vf = (((argL ^ argR) & (argL ^ res))) >> 63; -+ return vf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt vf = ((res ^ argL) & (res ^ argR)) >> 31; -+//ZZ return vf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL - argR - (oldC ^ 1); -+//ZZ UInt vf = ((argL ^ argR) & (argL ^ res)) >> 31; -+//ZZ return vf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ return 0; // V after logic is zero on arm64 -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt oldV = (cc_dep3 >> 0) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt vf = oldV; -+//ZZ return vf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt oldV = (cc_dep3 >> 0) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt vf = oldV; -+//ZZ return vf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_v" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_v"); -+ } -+} -+ -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate NZCV from the supplied thunk components, in the positions -+ they appear in the CPSR, viz bits 31:28 for N Z C V respectively. -+ Returned bits 27:0 are zero. */ -+ULong arm64g_calculate_flags_nzcv ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ ULong f; -+ ULong res = 0; -+ f = 1 & arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_N); -+ f = 1 & arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_Z); -+ f = 1 & arm64g_calculate_flag_c(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_C); -+ f = 1 & arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_V); -+ return res; -+} -+ -+//ZZ -+//ZZ /* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+//ZZ /* Calculate the QC flag from the arguments, in the lowest bit -+//ZZ of the word (bit 0). Urr, having this out of line is bizarre. -+//ZZ Push back inline. */ -+//ZZ UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2, -+//ZZ UInt resR1, UInt resR2 ) -+//ZZ { -+//ZZ if (resL1 != resR1 || resL2 != resR2) -+//ZZ return 1; -+//ZZ else -+//ZZ return 0; -+//ZZ } -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate the specified condition from the thunk components, in the -+ lowest bit of the word (bit 0). Returned bits 63:1 are zero. */ -+ULong arm64g_calculate_condition ( /* ARM64Condcode << 4 | cc_op */ -+ ULong cond_n_op , -+ ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ ULong cond = cond_n_op >> 4; -+ ULong cc_op = cond_n_op & 0xF; -+ ULong inv = cond & 1; -+ ULong nf, zf, vf, cf; -+ -+# if PROFILE_NZCV_FLAGS -+ NOTE_EVAL(cc_op, cond); -+# endif -+ -+ // vex_printf("XXXXXXXX %llx %llx %llx %llx\n", -+ // cond_n_op, cc_dep1, cc_dep2, cc_dep3); -+ -+ switch (cond) { -+ case ARM64CondEQ: // Z=1 => z -+ case ARM64CondNE: // Z=0 -+ zf = arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ zf; -+ -+ case ARM64CondCS: // C=1 => c -+ case ARM64CondCC: // C=0 -+ cf = arm64g_calculate_flag_c(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ cf; -+ -+ case ARM64CondMI: // N=1 => n -+ case ARM64CondPL: // N=0 -+ nf = arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ nf; -+ -+ case ARM64CondVS: // V=1 => v -+ case ARM64CondVC: // V=0 -+ vf = arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ vf; -+ -+ case ARM64CondHI: // C=1 && Z=0 => c & ~z -+ case ARM64CondLS: // C=0 || Z=1 -+ cf = arm64g_calculate_flag_c(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ zf = arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ (1 & (cf & ~zf)); -+ -+ case ARM64CondGE: // N=V => ~(n^v) -+ case ARM64CondLT: // N!=V -+ nf = arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ vf = arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ (1 & ~(nf ^ vf)); -+ -+ case ARM64CondGT: // Z=0 && N=V => ~z & ~(n^v) => ~(z | (n^v)) -+ case ARM64CondLE: // Z=1 || N!=V -+ nf = arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ vf = arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ zf = arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ (1 & ~(zf | (nf ^ vf))); -+ -+ case ARM64CondAL: // 1 -+ case ARM64CondNV: // 1 -+ return 1; -+ -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_condition(ARM64)" -+ "( %llu, %llu, 0x%llx, 0x%llx, 0x%llx )\n", -+ cond, cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("armg_calculate_condition(ARM64)"); -+ } -+} -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- Flag-helpers translation-time function specialisers. ---*/ -+/*--- These help iropt specialise calls the above run-time ---*/ -+/*--- flags functions. ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* Used by the optimiser to try specialisations. Returns an -+ equivalent expression, or NULL if none. */ -+ -+static Bool isU64 ( IRExpr* e, ULong n ) -+{ -+ return -+ toBool( e->tag == Iex_Const -+ && e->Iex.Const.con->tag == Ico_U64 -+ && e->Iex.Const.con->Ico.U64 == n ); -+} -+ -+IRExpr* guest_arm64_spechelper ( const HChar* function_name, -+ IRExpr** args, -+ IRStmt** precedingStmts, -+ Int n_precedingStmts ) -+{ -+# define unop(_op,_a1) IRExpr_Unop((_op),(_a1)) -+# define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2)) -+# define mkU64(_n) IRExpr_Const(IRConst_U64(_n)) -+# define mkU8(_n) IRExpr_Const(IRConst_U8(_n)) -+ -+ Int i, arity = 0; -+ for (i = 0; args[i]; i++) -+ arity++; -+//ZZ # if 0 -+//ZZ vex_printf("spec request:\n"); -+//ZZ vex_printf(" %s ", function_name); -+//ZZ for (i = 0; i < arity; i++) { -+//ZZ vex_printf(" "); -+//ZZ ppIRExpr(args[i]); -+//ZZ } -+//ZZ vex_printf("\n"); -+//ZZ # endif -+ -+ /* --------- specialising "arm64g_calculate_condition" --------- */ -+ -+ if (vex_streq(function_name, "arm64g_calculate_condition")) { -+ -+ /* specialise calls to the "arm64g_calculate_condition" function. -+ Not sure whether this is strictly necessary, but: the -+ replacement IR must produce only the values 0 or 1. Bits -+ 63:1 are required to be zero. */ -+ IRExpr *cond_n_op, *cc_dep1, *cc_dep2 ; //, *cc_ndep; -+ vassert(arity == 4); -+ cond_n_op = args[0]; /* (ARM64Condcode << 4) | ARM64G_CC_OP_* */ -+ cc_dep1 = args[1]; -+ cc_dep2 = args[2]; -+ //cc_ndep = args[3]; -+ -+ /*---------------- SUB64 ----------------*/ -+ -+ /* 0, 1 */ -+ if (isU64(cond_n_op, (ARM64CondEQ << 4) | ARM64G_CC_OP_SUB64)) { -+ /* EQ after SUB --> test argL == argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpEQ64, cc_dep1, cc_dep2)); -+ } -+ if (isU64(cond_n_op, (ARM64CondNE << 4) | ARM64G_CC_OP_SUB64)) { -+ /* NE after SUB --> test argL != argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpNE64, cc_dep1, cc_dep2)); -+ } -+ -+ /* 2, 3 */ -+ if (isU64(cond_n_op, (ARM64CondCS << 4) | ARM64G_CC_OP_SUB64)) { -+ /* CS after SUB --> test argL >=u argR -+ --> test argR <=u argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64U, cc_dep2, cc_dep1)); -+ } -+ if (isU64(cond_n_op, (ARM64CondCC << 4) | ARM64G_CC_OP_SUB64)) { -+ /* CC after SUB --> test argL test argL <=u argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64U, cc_dep1, cc_dep2)); -+ } -+ if (isU64(cond_n_op, (ARM64CondHI << 4) | ARM64G_CC_OP_SUB64)) { -+ /* HI after SUB --> test argL >u argR -+ --> test argR test argL test argL >=s argR -+ --> test argR <=s argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64S, cc_dep2, cc_dep1)); -+ } -+ -+ /* 12, 13 */ -+ if (isU64(cond_n_op, (ARM64CondGT << 4) | ARM64G_CC_OP_SUB64)) { -+ /* GT after SUB --> test argL >s argR -+ --> test argR test argL <=s argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64S, cc_dep1, cc_dep2)); -+ } -+ -+ /*---------------- SUB32 ----------------*/ -+ -+ /* 0, 1 */ -+ if (isU64(cond_n_op, (ARM64CondEQ << 4) | ARM64G_CC_OP_SUB32)) { -+ /* EQ after SUB --> test argL == argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpEQ32, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ if (isU64(cond_n_op, (ARM64CondNE << 4) | ARM64G_CC_OP_SUB32)) { -+ /* NE after SUB --> test argL != argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpNE32, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ -+ /* 2, 3 */ -+ if (isU64(cond_n_op, (ARM64CondCS << 4) | ARM64G_CC_OP_SUB32)) { -+ /* CS after SUB --> test argL >=u argR -+ --> test argR <=u argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32U, unop(Iop_64to32, cc_dep2), -+ unop(Iop_64to32, cc_dep1))); -+ } -+ if (isU64(cond_n_op, (ARM64CondCC << 4) | ARM64G_CC_OP_SUB32)) { -+ /* CC after SUB --> test argL test argL <=u argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32U, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ if (isU64(cond_n_op, (ARM64CondHI << 4) | ARM64G_CC_OP_SUB32)) { -+ /* HI after SUB --> test argL >u argR -+ --> test argR test argL test argL >=s argR -+ --> test argR <=s argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32S, unop(Iop_64to32, cc_dep2), -+ unop(Iop_64to32, cc_dep1))); -+ } -+ -+ /* 12, 13 */ -+ if (isU64(cond_n_op, (ARM64CondGT << 4) | ARM64G_CC_OP_SUB32)) { -+ /* GT after SUB --> test argL >s argR -+ --> test argR test argL <=s argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32S, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ -+//ZZ /*---------------- SBB ----------------*/ -+//ZZ -+//ZZ if (isU32(cond_n_op, (ARMCondHS << 4) | ARMG_CC_OP_SBB)) { -+//ZZ /* This seems to happen a lot in softfloat code, eg __divdf3+140 */ -+//ZZ /* thunk is: (dep1=argL, dep2=argR, ndep=oldC) */ -+//ZZ /* HS after SBB (same as C after SBB below) -+//ZZ --> oldC ? (argL >=u argR) : (argL >u argR) -+//ZZ --> oldC ? (argR <=u argL) : (argR test res == 0 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpEQ32, cc_dep1, mkU32(0))); -+//ZZ } -+//ZZ if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_LOGIC)) { -+//ZZ /* NE after LOGIC --> test res != 0 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpNE32, cc_dep1, mkU32(0))); -+//ZZ } -+//ZZ -+//ZZ if (isU32(cond_n_op, (ARMCondPL << 4) | ARMG_CC_OP_LOGIC)) { -+//ZZ /* PL after LOGIC --> test (res >> 31) == 0 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpEQ32, -+//ZZ binop(Iop_Shr32, cc_dep1, mkU8(31)), -+//ZZ mkU32(0))); -+//ZZ } -+//ZZ if (isU32(cond_n_op, (ARMCondMI << 4) | ARMG_CC_OP_LOGIC)) { -+//ZZ /* MI after LOGIC --> test (res >> 31) == 1 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpEQ32, -+//ZZ binop(Iop_Shr32, cc_dep1, mkU8(31)), -+//ZZ mkU32(1))); -+//ZZ } -+ -+ /*---------------- COPY ----------------*/ -+ -+ if (isU64(cond_n_op, (ARM64CondEQ << 4) | ARM64G_CC_OP_COPY)) { -+ /* EQ after COPY --> (cc_dep1 >> ARM64G_CC_SHIFT_Z) & 1 */ -+ return binop(Iop_And64, -+ binop(Iop_Shr64, cc_dep1, -+ mkU8(ARM64G_CC_SHIFT_Z)), -+ mkU64(1)); -+ } -+ if (isU64(cond_n_op, (ARM64CondNE << 4) | ARM64G_CC_OP_COPY)) { -+ /* NE after COPY --> ((cc_dep1 >> ARM64G_CC_SHIFT_Z) ^ 1) & 1 */ -+ return binop(Iop_And64, -+ binop(Iop_Xor64, -+ binop(Iop_Shr64, cc_dep1, -+ mkU8(ARM64G_CC_SHIFT_Z)), -+ mkU64(1)), -+ mkU64(1)); -+ } -+ -+//ZZ /*----------------- AL -----------------*/ -+//ZZ -+//ZZ /* A critically important case for Thumb code. -+//ZZ -+//ZZ What we're trying to spot is the case where cond_n_op is an -+//ZZ expression of the form Or32(..., 0xE0) since that means the -+//ZZ caller is asking for CondAL and we can simply return 1 -+//ZZ without caring what the ... part is. This is a potentially -+//ZZ dodgy kludge in that it assumes that the ... part has zeroes -+//ZZ in bits 7:4, so that the result of the Or32 is guaranteed to -+//ZZ be 0xE in bits 7:4. Given that the places where this first -+//ZZ arg are constructed (in guest_arm_toIR.c) are very -+//ZZ constrained, we can get away with this. To make this -+//ZZ guaranteed safe would require to have a new primop, Slice44 -+//ZZ or some such, thusly -+//ZZ -+//ZZ Slice44(arg1, arg2) = 0--(24)--0 arg1[7:4] arg2[3:0] -+//ZZ -+//ZZ and we would then look for Slice44(0xE0, ...) -+//ZZ which would give the required safety property. -+//ZZ -+//ZZ It would be infeasibly expensive to scan backwards through -+//ZZ the entire block looking for an assignment to the temp, so -+//ZZ just look at the previous 16 statements. That should find it -+//ZZ if it is an interesting case, as a result of how the -+//ZZ boilerplate guff at the start of each Thumb insn translation -+//ZZ is made. -+//ZZ */ -+//ZZ if (cond_n_op->tag == Iex_RdTmp) { -+//ZZ Int j; -+//ZZ IRTemp look_for = cond_n_op->Iex.RdTmp.tmp; -+//ZZ Int limit = n_precedingStmts - 16; -+//ZZ if (limit < 0) limit = 0; -+//ZZ if (0) vex_printf("scanning %d .. %d\n", n_precedingStmts-1, limit); -+//ZZ for (j = n_precedingStmts - 1; j >= limit; j--) { -+//ZZ IRStmt* st = precedingStmts[j]; -+//ZZ if (st->tag == Ist_WrTmp -+//ZZ && st->Ist.WrTmp.tmp == look_for -+//ZZ && st->Ist.WrTmp.data->tag == Iex_Binop -+//ZZ && st->Ist.WrTmp.data->Iex.Binop.op == Iop_Or32 -+//ZZ && isU32(st->Ist.WrTmp.data->Iex.Binop.arg2, (ARMCondAL << 4))) -+//ZZ return mkU32(1); -+//ZZ } -+//ZZ /* Didn't find any useful binding to the first arg -+//ZZ in the previous 16 stmts. */ -+//ZZ } -+ } -+ -+//ZZ /* --------- specialising "armg_calculate_flag_c" --------- */ -+//ZZ -+//ZZ else -+//ZZ if (vex_streq(function_name, "armg_calculate_flag_c")) { -+//ZZ -+//ZZ /* specialise calls to the "armg_calculate_flag_c" function. -+//ZZ Note that the returned value must be either 0 or 1; nonzero -+//ZZ bits 31:1 are not allowed. In turn, incoming oldV and oldC -+//ZZ values (from the thunk) are assumed to have bits 31:1 -+//ZZ clear. */ -+//ZZ IRExpr *cc_op, *cc_dep1, *cc_dep2, *cc_ndep; -+//ZZ vassert(arity == 4); -+//ZZ cc_op = args[0]; /* ARMG_CC_OP_* */ -+//ZZ cc_dep1 = args[1]; -+//ZZ cc_dep2 = args[2]; -+//ZZ cc_ndep = args[3]; -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_LOGIC)) { -+//ZZ /* Thunk args are (result, shco, oldV) */ -+//ZZ /* C after LOGIC --> shco */ -+//ZZ return cc_dep2; -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SUB)) { -+//ZZ /* Thunk args are (argL, argR, unused) */ -+//ZZ /* C after SUB --> argL >=u argR -+//ZZ --> argR <=u argL */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpLE32U, cc_dep2, cc_dep1)); -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SBB)) { -+//ZZ /* This happens occasionally in softfloat code, eg __divdf3+140 */ -+//ZZ /* thunk is: (dep1=argL, dep2=argR, ndep=oldC) */ -+//ZZ /* C after SBB (same as HS after SBB above) -+//ZZ --> oldC ? (argL >=u argR) : (argL >u argR) -+//ZZ --> oldC ? (argR <=u argL) : (argR oldV */ -+//ZZ return cc_ndep; -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SUB)) { -+//ZZ /* Thunk args are (argL, argR, unused) */ -+//ZZ /* V after SUB -+//ZZ --> let res = argL - argR -+//ZZ in ((argL ^ argR) & (argL ^ res)) >> 31 -+//ZZ --> ((argL ^ argR) & (argL ^ (argL - argR))) >> 31 -+//ZZ */ -+//ZZ IRExpr* argL = cc_dep1; -+//ZZ IRExpr* argR = cc_dep2; -+//ZZ return -+//ZZ binop(Iop_Shr32, -+//ZZ binop(Iop_And32, -+//ZZ binop(Iop_Xor32, argL, argR), -+//ZZ binop(Iop_Xor32, argL, binop(Iop_Sub32, argL, argR)) -+//ZZ ), -+//ZZ mkU8(31) -+//ZZ ); -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SBB)) { -+//ZZ /* This happens occasionally in softfloat code, eg __divdf3+140 */ -+//ZZ /* thunk is: (dep1=argL, dep2=argR, ndep=oldC) */ -+//ZZ /* V after SBB -+//ZZ --> let res = argL - argR - (oldC ^ 1) -+//ZZ in (argL ^ argR) & (argL ^ res) & 1 -+//ZZ */ -+//ZZ return -+//ZZ binop( -+//ZZ Iop_And32, -+//ZZ binop( -+//ZZ Iop_And32, -+//ZZ // argL ^ argR -+//ZZ binop(Iop_Xor32, cc_dep1, cc_dep2), -+//ZZ // argL ^ (argL - argR - (oldC ^ 1)) -+//ZZ binop(Iop_Xor32, -+//ZZ cc_dep1, -+//ZZ binop(Iop_Sub32, -+//ZZ binop(Iop_Sub32, cc_dep1, cc_dep2), -+//ZZ binop(Iop_Xor32, cc_ndep, mkU32(1))) -+//ZZ ) -+//ZZ ), -+//ZZ mkU32(1) -+//ZZ ); -+//ZZ } -+//ZZ -+//ZZ } -+ -+# undef unop -+# undef binop -+# undef mkU64 -+# undef mkU8 -+ -+ return NULL; -+} -+ -+ -+/*----------------------------------------------*/ -+/*--- The exported fns .. ---*/ -+/*----------------------------------------------*/ -+ -+//ZZ /* VISIBLE TO LIBVEX CLIENT */ -+//ZZ #if 0 -+//ZZ void LibVEX_GuestARM_put_flags ( UInt flags_native, -+//ZZ /*OUT*/VexGuestARMState* vex_state ) -+//ZZ { -+//ZZ vassert(0); // FIXME -+//ZZ -+//ZZ /* Mask out everything except N Z V C. */ -+//ZZ flags_native -+//ZZ &= (ARMG_CC_MASK_N | ARMG_CC_MASK_Z | ARMG_CC_MASK_V | ARMG_CC_MASK_C); -+//ZZ -+//ZZ vex_state->guest_CC_OP = ARMG_CC_OP_COPY; -+//ZZ vex_state->guest_CC_DEP1 = flags_native; -+//ZZ vex_state->guest_CC_DEP2 = 0; -+//ZZ vex_state->guest_CC_NDEP = 0; -+//ZZ } -+//ZZ #endif -+ -+/* VISIBLE TO LIBVEX CLIENT */ -+ULong LibVEX_GuestARM64_get_nzcv ( /*IN*/const VexGuestARM64State* vex_state ) -+{ -+ ULong nzcv = 0; -+ // NZCV -+ nzcv |= arm64g_calculate_flags_nzcv( -+ vex_state->guest_CC_OP, -+ vex_state->guest_CC_DEP1, -+ vex_state->guest_CC_DEP2, -+ vex_state->guest_CC_NDEP -+ ); -+ vassert(0 == (nzcv & 0xFFFFFFFF0FFFFFFFULL)); -+//ZZ // Q -+//ZZ if (vex_state->guest_QFLAG32 > 0) -+//ZZ cpsr |= (1 << 27); -+//ZZ // GE -+//ZZ if (vex_state->guest_GEFLAG0 > 0) -+//ZZ cpsr |= (1 << 16); -+//ZZ if (vex_state->guest_GEFLAG1 > 0) -+//ZZ cpsr |= (1 << 17); -+//ZZ if (vex_state->guest_GEFLAG2 > 0) -+//ZZ cpsr |= (1 << 18); -+//ZZ if (vex_state->guest_GEFLAG3 > 0) -+//ZZ cpsr |= (1 << 19); -+//ZZ // M -+//ZZ cpsr |= (1 << 4); // 0b10000 means user-mode -+//ZZ // J,T J (bit 24) is zero by initialisation above -+//ZZ // T we copy from R15T[0] -+//ZZ if (vex_state->guest_R15T & 1) -+//ZZ cpsr |= (1 << 5); -+//ZZ // ITSTATE we punt on for the time being. Could compute it -+//ZZ // if needed though. -+//ZZ // E, endianness, 0 (littleendian) from initialisation above -+//ZZ // A,I,F disable some async exceptions. Not sure about these. -+//ZZ // Leave as zero for the time being. -+ return nzcv; -+} -+ -+/* VISIBLE TO LIBVEX CLIENT */ -+void LibVEX_GuestARM64_initialise ( /*OUT*/VexGuestARM64State* vex_state ) -+{ -+ vex_bzero(vex_state, sizeof(*vex_state)); -+//ZZ vex_state->host_EvC_FAILADDR = 0; -+//ZZ vex_state->host_EvC_COUNTER = 0; -+//ZZ -+//ZZ vex_state->guest_R0 = 0; -+//ZZ vex_state->guest_R1 = 0; -+//ZZ vex_state->guest_R2 = 0; -+//ZZ vex_state->guest_R3 = 0; -+//ZZ vex_state->guest_R4 = 0; -+//ZZ vex_state->guest_R5 = 0; -+//ZZ vex_state->guest_R6 = 0; -+//ZZ vex_state->guest_R7 = 0; -+//ZZ vex_state->guest_R8 = 0; -+//ZZ vex_state->guest_R9 = 0; -+//ZZ vex_state->guest_R10 = 0; -+//ZZ vex_state->guest_R11 = 0; -+//ZZ vex_state->guest_R12 = 0; -+//ZZ vex_state->guest_R13 = 0; -+//ZZ vex_state->guest_R14 = 0; -+//ZZ vex_state->guest_R15T = 0; /* NB: implies ARM mode */ -+//ZZ -+ vex_state->guest_CC_OP = ARM64G_CC_OP_COPY; -+//ZZ vex_state->guest_CC_DEP1 = 0; -+//ZZ vex_state->guest_CC_DEP2 = 0; -+//ZZ vex_state->guest_CC_NDEP = 0; -+//ZZ vex_state->guest_QFLAG32 = 0; -+//ZZ vex_state->guest_GEFLAG0 = 0; -+//ZZ vex_state->guest_GEFLAG1 = 0; -+//ZZ vex_state->guest_GEFLAG2 = 0; -+//ZZ vex_state->guest_GEFLAG3 = 0; -+//ZZ -+//ZZ vex_state->guest_EMNOTE = EmNote_NONE; -+//ZZ vex_state->guest_TISTART = 0; -+//ZZ vex_state->guest_TILEN = 0; -+//ZZ vex_state->guest_NRADDR = 0; -+//ZZ vex_state->guest_IP_AT_SYSCALL = 0; -+//ZZ -+//ZZ vex_state->guest_D0 = 0; -+//ZZ vex_state->guest_D1 = 0; -+//ZZ vex_state->guest_D2 = 0; -+//ZZ vex_state->guest_D3 = 0; -+//ZZ vex_state->guest_D4 = 0; -+//ZZ vex_state->guest_D5 = 0; -+//ZZ vex_state->guest_D6 = 0; -+//ZZ vex_state->guest_D7 = 0; -+//ZZ vex_state->guest_D8 = 0; -+//ZZ vex_state->guest_D9 = 0; -+//ZZ vex_state->guest_D10 = 0; -+//ZZ vex_state->guest_D11 = 0; -+//ZZ vex_state->guest_D12 = 0; -+//ZZ vex_state->guest_D13 = 0; -+//ZZ vex_state->guest_D14 = 0; -+//ZZ vex_state->guest_D15 = 0; -+//ZZ vex_state->guest_D16 = 0; -+//ZZ vex_state->guest_D17 = 0; -+//ZZ vex_state->guest_D18 = 0; -+//ZZ vex_state->guest_D19 = 0; -+//ZZ vex_state->guest_D20 = 0; -+//ZZ vex_state->guest_D21 = 0; -+//ZZ vex_state->guest_D22 = 0; -+//ZZ vex_state->guest_D23 = 0; -+//ZZ vex_state->guest_D24 = 0; -+//ZZ vex_state->guest_D25 = 0; -+//ZZ vex_state->guest_D26 = 0; -+//ZZ vex_state->guest_D27 = 0; -+//ZZ vex_state->guest_D28 = 0; -+//ZZ vex_state->guest_D29 = 0; -+//ZZ vex_state->guest_D30 = 0; -+//ZZ vex_state->guest_D31 = 0; -+//ZZ -+//ZZ /* ARM encoded; zero is the default as it happens (result flags -+//ZZ (NZCV) cleared, FZ disabled, round to nearest, non-vector mode, -+//ZZ all exns masked, all exn sticky bits cleared). */ -+//ZZ vex_state->guest_FPSCR = 0; -+//ZZ -+//ZZ vex_state->guest_TPIDRURO = 0; -+//ZZ -+//ZZ /* Not in a Thumb IT block. */ -+//ZZ vex_state->guest_ITSTATE = 0; -+//ZZ -+//ZZ vex_state->padding1 = 0; -+//ZZ vex_state->padding2 = 0; -+//ZZ vex_state->padding3 = 0; -+//ZZ vex_state->padding4 = 0; -+//ZZ vex_state->padding5 = 0; -+} -+ -+ -+/*-----------------------------------------------------------*/ -+/*--- Describing the arm guest state, for the benefit ---*/ -+/*--- of iropt and instrumenters. ---*/ -+/*-----------------------------------------------------------*/ -+ -+/* Figure out if any part of the guest state contained in minoff -+ .. maxoff requires precise memory exceptions. If in doubt return -+ True (but this generates significantly slower code). -+ -+ We enforce precise exns for guest SP, PC, 29(FP), 30(LR). -+ That might be overkill (for 29 and 30); I don't know. -+*/ -+Bool guest_arm64_state_requires_precise_mem_exns ( Int minoff, -+ Int maxoff) -+{ -+ Int sp_min = offsetof(VexGuestARM64State, guest_SP); -+ Int sp_max = sp_min + 8 - 1; -+ Int pc_min = offsetof(VexGuestARM64State, guest_PC); -+ Int pc_max = pc_min + 8 - 1; -+ -+ if (maxoff < sp_min || minoff > sp_max) { -+ /* no overlap with sp */ -+ if (vex_control.iropt_register_updates == VexRegUpdSpAtMemAccess) -+ return False; // We only need to check stack pointer. -+ } else { -+ return True; -+ } -+ -+ if (maxoff < pc_min || minoff > pc_max) { -+ /* no overlap with pc */ -+ } else { -+ return True; -+ } -+ -+ /* Guessing that we need PX for FP, but I don't really know. */ -+ Int x29_min = offsetof(VexGuestARM64State, guest_X29); -+ Int x29_max = x29_min + 8 - 1; -+ -+ if (maxoff < x29_min || minoff > x29_max) { -+ /* no overlap with x29 */ -+ } else { -+ return True; -+ } -+ -+ /* Guessing that we need PX for LR, but I don't really know. */ -+ Int x30_min = offsetof(VexGuestARM64State, guest_X30); -+ Int x30_max = x30_min + 8 - 1; -+ -+ if (maxoff < x30_min || minoff > x30_max) { -+ /* no overlap with r30 */ -+ } else { -+ return True; -+ } -+ -+ return False; -+} -+ -+ -+#define ALWAYSDEFD(field) \ -+ { offsetof(VexGuestARM64State, field), \ -+ (sizeof ((VexGuestARM64State*)0)->field) } -+VexGuestLayout -+ arm64Guest_layout -+ = { -+ /* Total size of the guest state, in bytes. */ -+ .total_sizeB = sizeof(VexGuestARM64State), -+ -+ /* Describe the stack pointer. */ -+ .offset_SP = offsetof(VexGuestARM64State,guest_SP), -+ .sizeof_SP = 8, -+ -+ /* Describe the instruction pointer. */ -+ .offset_IP = offsetof(VexGuestARM64State,guest_PC), -+ .sizeof_IP = 8, -+ -+ /* Describe any sections to be regarded by Memcheck as -+ 'always-defined'. */ -+ .n_alwaysDefd = 10, -+ -+ /* flags thunk: OP is always defd, whereas DEP1 and DEP2 -+ have to be tracked. See detailed comment in gdefs.h on -+ meaning of thunk fields. */ -+ .alwaysDefd -+ = { /* 0 */ ALWAYSDEFD(guest_PC), -+ /* 1 */ ALWAYSDEFD(guest_CC_OP), -+ /* 2 */ ALWAYSDEFD(guest_CC_NDEP), -+ /* 3 */ ALWAYSDEFD(guest_EMNOTE), -+ /* 4 */ ALWAYSDEFD(guest_TISTART), -+ /* 5 */ ALWAYSDEFD(guest_TILEN), -+ /* 6 */ ALWAYSDEFD(guest_NRADDR), -+ /* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL), -+ /* 8 */ ALWAYSDEFD(guest_FPCR), -+ /* 9 */ ALWAYSDEFD(guest_FPSR) -+ } -+ }; -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- end guest_arm64_helpers.c ---*/ -+/*---------------------------------------------------------------*/ -Index: VEX/priv/guest_s390_helpers.c -=================================================================== ---- VEX/priv/guest_s390_helpers.c.orig -+++ VEX/priv/guest_s390_helpers.c -@@ -154,11 +154,11 @@ LibVEX_GuestS390X_initialise(VexGuestS39 - Bool - guest_s390x_state_requires_precise_mem_exns(Int minoff, Int maxoff) - { -- Int lr_min = S390X_GUEST_OFFSET(guest_LR); -+ Int lr_min = S390X_GUEST_OFFSET(guest_s390_LR); - Int lr_max = lr_min + 8 - 1; -- Int sp_min = S390X_GUEST_OFFSET(guest_SP); -+ Int sp_min = S390X_GUEST_OFFSET(guest_s390_SP); - Int sp_max = sp_min + 8 - 1; -- Int fp_min = S390X_GUEST_OFFSET(guest_FP); -+ Int fp_min = S390X_GUEST_OFFSET(guest_s390_FP); - Int fp_max = fp_min + 8 - 1; - Int ia_min = S390X_GUEST_OFFSET(guest_IA); - Int ia_max = ia_min + 8 - 1; -@@ -203,11 +203,11 @@ VexGuestLayout s390xGuest_layout = { - .total_sizeB = sizeof(VexGuestS390XState), - - /* Describe the stack pointer. */ -- .offset_SP = S390X_GUEST_OFFSET(guest_SP), -+ .offset_SP = S390X_GUEST_OFFSET(guest_s390_SP), - .sizeof_SP = 8, - - /* Describe the frame pointer. */ -- .offset_FP = S390X_GUEST_OFFSET(guest_FP), -+ .offset_FP = S390X_GUEST_OFFSET(guest_s390_FP), - .sizeof_FP = 8, - - /* Describe the instruction pointer. */ -Index: VEX/priv/main_main.c -=================================================================== ---- VEX/priv/main_main.c.orig -+++ VEX/priv/main_main.c -@@ -38,6 +38,7 @@ - #include "libvex_guest_x86.h" - #include "libvex_guest_amd64.h" - #include "libvex_guest_arm.h" -+#include "libvex_guest_arm64.h" - #include "libvex_guest_ppc32.h" - #include "libvex_guest_ppc64.h" - #include "libvex_guest_s390x.h" -@@ -53,6 +54,7 @@ - #include "host_amd64_defs.h" - #include "host_ppc_defs.h" - #include "host_arm_defs.h" -+#include "host_arm64_defs.h" - #include "host_s390_defs.h" - #include "host_mips_defs.h" - -@@ -60,6 +62,7 @@ - #include "guest_x86_defs.h" - #include "guest_amd64_defs.h" - #include "guest_arm_defs.h" -+#include "guest_arm64_defs.h" - #include "guest_ppc_defs.h" - #include "guest_s390_defs.h" - #include "guest_mips_defs.h" -@@ -417,6 +420,30 @@ VexTranslateResult LibVEX_Translate ( Ve - vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); - break; - -+ case VexArchARM64: -+ mode64 = True; -+ getAllocableRegs_ARM64 ( &n_available_real_regs, -+ &available_real_regs ); -+ isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARM64Instr; -+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) -+ getRegUsage_ARM64Instr; -+ mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) -+ mapRegs_ARM64Instr; -+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) -+ genSpill_ARM64; -+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) -+ genReload_ARM64; -+ ppInstr = (void(*)(HInstr*, Bool)) ppARM64Instr; -+ ppReg = (void(*)(HReg)) ppHRegARM64; -+ iselSB = iselSB_ARM64; -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ void*,void*,void*,void*)) -+ emit_ARM64Instr; -+ host_is_bigendian = False; -+ host_word_type = Ity_I64; -+ vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_host.hwcaps)); -+ break; -+ - case VexArchMIPS32: - mode64 = False; - getAllocableRegs_MIPS ( &n_available_real_regs, -@@ -593,6 +620,26 @@ VexTranslateResult LibVEX_Translate ( Ve - vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); - break; - -+ case VexArchARM64: -+ preciseMemExnsFn = guest_arm64_state_requires_precise_mem_exns; -+ disInstrFn = disInstr_ARM64; -+ specHelper = guest_arm64_spechelper; -+ guest_sizeB = sizeof(VexGuestARM64State); -+ guest_word_type = Ity_I64; -+ guest_layout = &arm64Guest_layout; -+ offB_TISTART = offsetof(VexGuestARM64State,guest_TISTART); -+ offB_TILEN = offsetof(VexGuestARM64State,guest_TILEN); -+ offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC); -+ szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC ); -+ offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER); -+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR); -+ vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_guest.hwcaps)); -+ vassert(0 == sizeof(VexGuestARM64State) % 16); -+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_TISTART) == 8); -+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_TILEN ) == 8); -+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_NRADDR ) == 8); -+ break; -+ - case VexArchMIPS32: - preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns; - disInstrFn = disInstr_MIPS; -@@ -958,6 +1005,8 @@ VexInvalRange LibVEX_Chain ( VexArch arc - chainXDirect = chainXDirect_AMD64; break; - case VexArchARM: - chainXDirect = chainXDirect_ARM; break; -+ case VexArchARM64: -+ chainXDirect = chainXDirect_ARM64; break; - case VexArchS390X: - chainXDirect = chainXDirect_S390; break; - case VexArchPPC32: -@@ -1038,6 +1087,8 @@ Int LibVEX_evCheckSzB ( VexArch arch_hos - cached = evCheckSzB_AMD64(); break; - case VexArchARM: - cached = evCheckSzB_ARM(); break; -+ case VexArchARM64: -+ cached = evCheckSzB_ARM64(); break; - case VexArchS390X: - cached = evCheckSzB_S390(); break; - case VexArchPPC32: -@@ -1152,6 +1203,7 @@ const HChar* LibVEX_ppVexArch ( VexArch - case VexArchX86: return "X86"; - case VexArchAMD64: return "AMD64"; - case VexArchARM: return "ARM"; -+ case VexArchARM64: return "ARM64"; - case VexArchPPC32: return "PPC32"; - case VexArchPPC64: return "PPC64"; - case VexArchS390X: return "S390X"; -@@ -1381,6 +1433,15 @@ static const HChar* show_hwcaps_arm ( UI - return NULL; - } - -+static const HChar* show_hwcaps_arm64 ( UInt hwcaps ) -+{ -+ /* Since there are no variants, just insist that hwcaps is zero, -+ and declare it invalid otherwise. */ -+ if (hwcaps == 0) -+ return "baseline"; -+ return NULL; -+} -+ - static const HChar* show_hwcaps_s390x ( UInt hwcaps ) - { - static const HChar prefix[] = "s390x"; -@@ -1472,6 +1533,7 @@ static const HChar* show_hwcaps ( VexArc - case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); - case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); - case VexArchARM: return show_hwcaps_arm(hwcaps); -+ case VexArchARM64: return show_hwcaps_arm64(hwcaps); - case VexArchS390X: return show_hwcaps_s390x(hwcaps); - case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); - case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); -Index: VEX/priv/guest_arm64_defs.h -=================================================================== ---- /dev/null -+++ VEX/priv/guest_arm64_defs.h -@@ -0,0 +1,244 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin guest_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VEX_GUEST_ARM64_DEFS_H -+#define __VEX_GUEST_ARM64_DEFS_H -+ -+#include "libvex_basictypes.h" -+#include "guest_generic_bb_to_IR.h" // DisResult -+ -+/*---------------------------------------------------------*/ -+/*--- arm64 to IR conversion ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Convert one ARM64 insn to IR. See the type DisOneInstrFn in -+ bb_to_IR.h. */ -+extern -+DisResult disInstr_ARM64 ( IRSB* irbb, -+ Bool (*resteerOkFn) ( void*, Addr64 ), -+ Bool resteerCisOk, -+ void* callback_opaque, -+ UChar* guest_code, -+ Long delta, -+ Addr64 guest_IP, -+ VexArch guest_arch, -+ VexArchInfo* archinfo, -+ VexAbiInfo* abiinfo, -+ Bool host_bigendian, -+ Bool sigill_diag ); -+ -+/* Used by the optimiser to specialise calls to helpers. */ -+extern -+IRExpr* guest_arm64_spechelper ( const HChar* function_name, -+ IRExpr** args, -+ IRStmt** precedingStmts, -+ Int n_precedingStmts ); -+ -+/* Describes to the optimser which part of the guest state require -+ precise memory exceptions. This is logically part of the guest -+ state description. */ -+extern -+Bool guest_arm64_state_requires_precise_mem_exns ( Int, Int ); -+ -+extern -+VexGuestLayout arm64Guest_layout; -+ -+ -+/*---------------------------------------------------------*/ -+/*--- arm64 guest helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* --- CLEAN HELPERS --- */ -+ -+/* Calculate NZCV from the supplied thunk components, in the positions -+ they appear in the CPSR, viz bits 31:28 for N Z C V respectively. -+ Returned bits 63:32 and 27:0 are zero. */ -+extern -+ULong arm64g_calculate_flags_nzcv ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ); -+ -+//ZZ /* Calculate the C flag from the thunk components, in the lowest bit -+//ZZ of the word (bit 0). */ -+//ZZ extern -+//ZZ UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1, -+//ZZ UInt cc_dep2, UInt cc_dep3 ); -+//ZZ -+//ZZ /* Calculate the V flag from the thunk components, in the lowest bit -+//ZZ of the word (bit 0). */ -+//ZZ extern -+//ZZ UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1, -+//ZZ UInt cc_dep2, UInt cc_dep3 ); -+//ZZ -+/* Calculate the specified condition from the thunk components, in the -+ lowest bit of the word (bit 0). */ -+extern -+ULong arm64g_calculate_condition ( /* ARM64Condcode << 4 | cc_op */ -+ ULong cond_n_op , -+ ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ); -+ -+//ZZ /* Calculate the QC flag from the thunk components, in the lowest bit -+//ZZ of the word (bit 0). */ -+//ZZ extern -+//ZZ UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2, -+//ZZ UInt resR1, UInt resR2 ); -+ -+ -+/*---------------------------------------------------------*/ -+/*--- Condition code stuff ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Flag masks. Defines positions of flag bits in the NZCV -+ register. */ -+#define ARM64G_CC_SHIFT_N 31 -+#define ARM64G_CC_SHIFT_Z 30 -+#define ARM64G_CC_SHIFT_C 29 -+#define ARM64G_CC_SHIFT_V 28 -+//ZZ #define ARMG_CC_SHIFT_Q 27 -+//ZZ -+//ZZ #define ARMG_CC_MASK_N (1 << ARMG_CC_SHIFT_N) -+//ZZ #define ARMG_CC_MASK_Z (1 << ARMG_CC_SHIFT_Z) -+//ZZ #define ARMG_CC_MASK_C (1 << ARMG_CC_SHIFT_C) -+//ZZ #define ARMG_CC_MASK_V (1 << ARMG_CC_SHIFT_V) -+//ZZ #define ARMG_CC_MASK_Q (1 << ARMG_CC_SHIFT_Q) -+ -+/* Flag thunk descriptors. A four-word thunk is used to record -+ details of the most recent flag-setting operation, so NZCV can -+ be computed later if needed. -+ -+ The four words are: -+ -+ CC_OP, which describes the operation. -+ -+ CC_DEP1, CC_DEP2, CC_NDEP. These are arguments to the -+ operation. We want set up the mcx_masks in flag helper calls -+ involving these fields so that Memcheck "believes" that the -+ resulting flags are data-dependent on both CC_DEP1 and -+ CC_DEP2. Hence the name DEP. -+ -+ When building the thunk, it is always necessary to write words into -+ CC_DEP1/2 and NDEP, even if those args are not used given the CC_OP -+ field. This is important because otherwise Memcheck could give -+ false positives as it does not understand the relationship between -+ the CC_OP field and CC_DEP1/2/NDEP, and so believes that the -+ definedness of the stored flags always depends on all 3 DEP values. -+ -+ A summary of the field usages is: -+ -+ OP DEP1 DEP2 DEP3 -+ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -+ -+ OP_COPY curr_NZCV:28x0 unused unused -+ OP_ADD32 argL argR unused -+ OP_ADD64 argL argR unused -+ OP_SUB32 argL argR unused -+ OP_SUB64 argL argR unused -+//ZZ OP_ADC argL argR 31x0:old_C -+//ZZ OP_SBB argL argR 31x0:old_C -+ OP_LOGIC32 result unused unused -+ OP_LOGIC64 result unused unused -+//ZZ OP_MUL result unused 30x0:old_C:old_V -+//ZZ OP_MULL resLO32 resHI32 30x0:old_C:old_V -+//ZZ */ -+ -+enum { -+ ARM64G_CC_OP_COPY=0, /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0 -+ just copy DEP1 to output */ -+ -+ ARM64G_CC_OP_ADD32, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+ ARM64G_CC_OP_ADD64, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+ ARM64G_CC_OP_SUB32, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+ ARM64G_CC_OP_SUB64, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+//ZZ ARMG_CC_OP_ADC, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), -+//ZZ DEP3 = oldC (in LSB) */ -+//ZZ -+//ZZ ARMG_CC_OP_SBB, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), -+//ZZ DEP3 = oldC (in LSB) */ -+ -+ ARM64G_CC_OP_LOGIC32, /* DEP1 = result, DEP2 = 0, DEP3 = 0 */ -+ ARM64G_CC_OP_LOGIC64, /* DEP1 = result, DEP2 = 0, DEP3 = 0 */ -+ -+//ZZ ARMG_CC_OP_MUL, /* DEP1 = result, DEP2 = 0, DEP3 = oldC:old_V -+//ZZ (in bits 1:0) */ -+//ZZ -+//ZZ ARMG_CC_OP_MULL, /* DEP1 = resLO32, DEP2 = resHI32, DEP3 = oldC:old_V -+//ZZ (in bits 1:0) */ -+ -+ ARM64G_CC_OP_NUMBER -+}; -+ -+/* XXXX because of the calling conventions for -+ arm64g_calculate_condition, all these OP values MUST be in the range -+ 0 .. 15 only (viz, 4-bits). */ -+ -+ -+ -+/* Defines conditions which we can ask for */ -+ -+typedef -+ enum { -+ ARM64CondEQ = 0, /* equal : Z=1 */ -+ ARM64CondNE = 1, /* not equal : Z=0 */ -+ -+ ARM64CondCS = 2, /* >=u (higher or same) (aka HS) : C=1 */ -+ ARM64CondCC = 3, /* u (higher) : C=1 && Z=0 */ -+ ARM64CondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */ -+ -+ ARM64CondGE = 10, /* >=s (signed greater or equal) : N=V */ -+ ARM64CondLT = 11, /* s (signed greater) : Z=0 && N=V */ -+ ARM64CondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ -+ -+ ARM64CondAL = 14, /* always (unconditional) : 1 */ -+ ARM64CondNV = 15 /* always (unconditional) : 1 */ -+ } -+ ARM64Condcode; -+ -+#endif /* ndef __VEX_GUEST_ARM64_DEFS_H */ -+ -+/*---------------------------------------------------------------*/ -+/*--- end guest_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -Index: VEX/pub/libvex.h -=================================================================== ---- VEX/pub/libvex.h.orig -+++ VEX/pub/libvex.h -@@ -55,6 +55,7 @@ typedef - VexArchX86, - VexArchAMD64, - VexArchARM, -+ VexArchARM64, - VexArchPPC32, - VexArchPPC64, - VexArchS390X, -@@ -172,6 +173,9 @@ typedef - /* Get an ARM architecure level from HWCAPS */ - #define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f) - -+/* ARM64: baseline capability is AArch64 v8. */ -+/* (no definitions since no variants so far) */ -+ - /* MIPS baseline capability */ - /* Assigned Company values for bits 23:16 of the PRId Register - (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from -@@ -213,6 +217,7 @@ typedef - extern const HChar* LibVEX_ppVexArch ( VexArch ); - extern const HChar* LibVEX_ppVexHwCaps ( VexArch, UInt ); - -+ - /* The various kinds of caches */ - typedef enum { - DATA_CACHE, -@@ -907,6 +912,14 @@ extern void LibVEX_InitIRI ( const IRICB - ~~~~~ - Same as ppc32. - -+ arm32 -+ ~~~~~ -+ r8 is GSP. -+ -+ arm64 -+ ~~~~~ -+ r21 is GSP. -+ - ALL GUEST ARCHITECTURES - ~~~~~~~~~~~~~~~~~~~~~~~ - The guest state must contain two pseudo-registers, guest_TISTART -Index: VEX/pub/libvex_guest_arm64.h -=================================================================== ---- /dev/null -+++ VEX/pub/libvex_guest_arm64.h -@@ -0,0 +1,190 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin libvex_guest_arm64.h ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __LIBVEX_PUB_GUEST_ARM64_H -+#define __LIBVEX_PUB_GUEST_ARM64_H -+ -+#include "libvex_basictypes.h" -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- Vex's representation of the ARM64 CPU state. ---*/ -+/*---------------------------------------------------------------*/ -+ -+typedef -+ struct { -+ /* Event check fail addr and counter. */ -+ /* 0 */ ULong host_EvC_FAILADDR; -+ /* 8 */ UInt host_EvC_COUNTER; -+ /* 12 */ UInt pad0; -+ /* 16 */ -+ ULong guest_X0; -+ ULong guest_X1; -+ ULong guest_X2; -+ ULong guest_X3; -+ ULong guest_X4; -+ ULong guest_X5; -+ ULong guest_X6; -+ ULong guest_X7; -+ ULong guest_X8; -+ ULong guest_X9; -+ ULong guest_X10; -+ ULong guest_X11; -+ ULong guest_X12; -+ ULong guest_X13; -+ ULong guest_X14; -+ ULong guest_X15; -+ ULong guest_X16; -+ ULong guest_X17; -+ ULong guest_X18; -+ ULong guest_X19; -+ ULong guest_X20; -+ ULong guest_X21; -+ ULong guest_X22; -+ ULong guest_X23; -+ ULong guest_X24; -+ ULong guest_X25; -+ ULong guest_X26; -+ ULong guest_X27; -+ ULong guest_X28; -+ ULong guest_X29; -+ ULong guest_X30; /* link register */ -+ ULong guest_SP; -+ ULong guest_PC; -+ -+ /* 4-word thunk used to calculate N(sign) Z(zero) C(carry, -+ unsigned overflow) and V(signed overflow) flags. */ -+ ULong guest_CC_OP; -+ ULong guest_CC_DEP1; -+ ULong guest_CC_DEP2; -+ ULong guest_CC_NDEP; -+ -+ /* User-space thread register? */ -+ ULong guest_TPIDR_EL0; -+ -+ /* FP/SIMD state */ -+ U128 guest_Q0; -+ U128 guest_Q1; -+ U128 guest_Q2; -+ U128 guest_Q3; -+ U128 guest_Q4; -+ U128 guest_Q5; -+ U128 guest_Q6; -+ U128 guest_Q7; -+ U128 guest_Q8; -+ U128 guest_Q9; -+ U128 guest_Q10; -+ U128 guest_Q11; -+ U128 guest_Q12; -+ U128 guest_Q13; -+ U128 guest_Q14; -+ U128 guest_Q15; -+ U128 guest_Q16; -+ U128 guest_Q17; -+ U128 guest_Q18; -+ U128 guest_Q19; -+ U128 guest_Q20; -+ U128 guest_Q21; -+ U128 guest_Q22; -+ U128 guest_Q23; -+ U128 guest_Q24; -+ U128 guest_Q25; -+ U128 guest_Q26; -+ U128 guest_Q27; -+ U128 guest_Q28; -+ U128 guest_Q29; -+ U128 guest_Q30; -+ U128 guest_Q31; -+ -+ /* Various pseudo-regs mandated by Vex or Valgrind. */ -+ /* Emulation notes */ -+ UInt guest_EMNOTE; -+ -+ /* For clflush: record start and length of area to invalidate */ -+ ULong guest_TISTART; -+ ULong guest_TILEN; -+ -+ /* Used to record the unredirected guest address at the start of -+ a translation whose start has been redirected. By reading -+ this pseudo-register shortly afterwards, the translation can -+ find out what the corresponding no-redirection address was. -+ Note, this is only set for wrap-style redirects, not for -+ replace-style ones. */ -+ ULong guest_NRADDR; -+ -+ /* Needed for Darwin (but mandated for all guest architectures): -+ program counter at the last syscall insn (int 0x80/81/82, -+ sysenter, syscall, svc). Used when backing up to restart a -+ syscall that has been interrupted by a signal. */ -+ ULong guest_IP_AT_SYSCALL; -+ -+ /* The complete FPCR. Default value seems to be zero. We -+ ignore all bits except 23 and 22, which are the rounding -+ mode. The guest is unconstrained in what values it can write -+ to and read from this register, but the emulation only takes -+ note of bits 23 and 22. */ -+ UInt guest_FPCR; -+ -+ /* The complete FPSR. As with FPCR, the guest may write and -+ read any values here, and the emulation ignores it, with the -+ exception of bit 27 (QC, the sticky saturation bit) which -+ does get set when required. */ -+ UInt guest_FPSR; -+ -+ /* Padding to make it have an 32-aligned size */ -+ UInt pad_end_0; -+ ULong pad_end_1; -+ } -+ VexGuestARM64State; -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- Utility functions for ARM64 guest stuff. ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */ -+ -+/* Initialise all guest ARM64 state. */ -+ -+extern -+void LibVEX_GuestARM64_initialise ( /*OUT*/VexGuestARM64State* vex_state ); -+ -+/* Calculate the ARM64 flag state from the saved data, in the format -+ 32x0:n:z:c:v:28x0. */ -+extern -+ULong LibVEX_GuestARM64_get_nzcv ( /*IN*/ -+ const VexGuestARM64State* vex_state ); -+ -+#endif /* ndef __LIBVEX_PUB_GUEST_ARM64_H */ -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- libvex_guest_arm64.h ---*/ -+/*---------------------------------------------------------------*/ -Index: VEX/pub/libvex_basictypes.h -=================================================================== ---- VEX/pub/libvex_basictypes.h.orig -+++ VEX/pub/libvex_basictypes.h -@@ -192,15 +192,11 @@ typedef unsigned long HWord; - # define VEX_HOST_WORDSIZE 4 - # define VEX_REGPARM(_n) /* */ - --#elif defined(__arm__) -+#elif defined(__arm__) && !defined(__aarch64__) - # define VEX_HOST_WORDSIZE 4 - # define VEX_REGPARM(_n) /* */ - --#elif defined(_AIX) && !defined(__64BIT__) --# define VEX_HOST_WORDSIZE 4 --# define VEX_REGPARM(_n) /* */ -- --#elif defined(_AIX) && defined(__64BIT__) -+#elif defined(__aarch64__) && !defined(__arm__) - # define VEX_HOST_WORDSIZE 8 - # define VEX_REGPARM(_n) /* */ - -@@ -208,12 +204,12 @@ typedef unsigned long HWord; - # define VEX_HOST_WORDSIZE 8 - # define VEX_REGPARM(_n) /* */ - --#elif defined(__mips__) --#if (__mips==64) -+#elif defined(__mips__) && (__mips == 64) - # define VEX_HOST_WORDSIZE 8 --#else -+# define VEX_REGPARM(_n) /* */ -+ -+#elif defined(__mips__) && (__mips != 64) - # define VEX_HOST_WORDSIZE 4 --#endif - # define VEX_REGPARM(_n) /* */ - - #else -Index: VEX/pub/libvex_ir.h -=================================================================== ---- VEX/pub/libvex_ir.h.orig -+++ VEX/pub/libvex_ir.h -@@ -1691,7 +1691,7 @@ typedef - Irrm_PosINF = 2, // Round to positive infinity - Irrm_ZERO = 3, // Round toward zero - Irrm_NEAREST_TIE_AWAY_0 = 4, // Round to nearest, ties away from 0 -- Irrm_PREPARE_SHORTER = 5, // Round to prepare for storter -+ Irrm_PREPARE_SHORTER = 5, // Round to prepare for shorter - // precision - Irrm_AWAY_FROM_ZERO = 6, // Round to away from 0 - Irrm_NEAREST_TIE_TOWARD_0 = 7 // Round to nearest, ties towards 0 -Index: VEX/pub/libvex_guest_s390x.h -=================================================================== ---- VEX/pub/libvex_guest_s390x.h.orig -+++ VEX/pub/libvex_guest_s390x.h -@@ -166,9 +166,9 @@ void LibVEX_GuestS390X_initialise(VexGue - /*--- Dedicated registers ---*/ - /*------------------------------------------------------------*/ - --#define guest_LR guest_r14 /* Link register */ --#define guest_SP guest_r15 /* Stack pointer */ --#define guest_FP guest_r11 /* Frame pointer */ -+#define guest_s390_LR guest_r14 /* Link register */ -+#define guest_s390_SP guest_r15 /* Stack pointer */ -+#define guest_s390_FP guest_r11 /* Frame pointer */ - - /*---------------------------------------------------------------*/ - /*--- end libvex_guest_s390x.h ---*/ diff --git a/VEX-r2808.diff b/VEX-r2808.diff deleted file mode 100644 index 41849a5..0000000 --- a/VEX-r2808.diff +++ /dev/null @@ -1,28 +0,0 @@ ---- VEX/priv/guest_ppc_toIR.c (Revision 2807) -+++ VEX/priv/guest_ppc_toIR.c (Revision 2808) -@@ -5233,6 +5233,7 @@ static Bool dis_int_ldst_mult ( UInt the - - Int simm16 = extend_s_16to32(uimm16); - IRType ty = mode64 ? Ity_I64 : Ity_I32; -+ IROp mkAdd = mode64 ? Iop_Add64 : Iop_Add32; - IRTemp EA = newTemp(ty); - UInt r = 0; - UInt ea_off = 0; -@@ -5248,7 +5249,7 @@ static Bool dis_int_ldst_mult ( UInt the - } - DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); - for (r = rD_addr; r <= 31; r++) { -- irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); -+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); - putIReg( r, mkWidenFrom32(ty, loadBE(Ity_I32, irx_addr ), - False) ); - ea_off += 4; -@@ -5258,7 +5259,7 @@ static Bool dis_int_ldst_mult ( UInt the - case 0x2F: // stmw (Store Multiple Word, PPC32 p527) - DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); - for (r = rS_addr; r <= 31; r++) { -- irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); -+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); - storeBE( irx_addr, mkNarrowTo32(ty, getIReg(r)) ); - ea_off += 4; - } diff --git a/VEX-r2816.diff b/VEX-r2816.diff deleted file mode 100644 index 900c896..0000000 --- a/VEX-r2816.diff +++ /dev/null @@ -1,44 +0,0 @@ ---- VEX/priv/guest_ppc_toIR.c (Revision 2815) -+++ VEX/priv/guest_ppc_toIR.c (Revision 2816) -@@ -78,9 +78,9 @@ - concerned) but have meaning for supporting Valgrind. A special - instruction is flagged by a 16-byte preamble: - -- 32-bit mode: 54001800 54006800 5400E800 54009800 -- (rlwinm 0,0,3,0,0; rlwinm 0,0,13,0,0; -- rlwinm 0,0,29,0,0; rlwinm 0,0,19,0,0) -+ 32-bit mode: 5400183E 5400683E 5400E83E 5400983E -+ (rlwinm 0,0,3,0,31; rlwinm 0,0,13,0,31; -+ rlwinm 0,0,29,0,31; rlwinm 0,0,19,0,31) - - 64-bit mode: 78001800 78006800 7800E802 78009802 - (rotldi 0,0,3; rotldi 0,0,13; -@@ -18523,20 +18523,20 @@ DisResult disInstr_PPC_WRK ( - UChar* code = (UChar*)(guest_code + delta); - /* Spot the 16-byte preamble: - 32-bit mode: -- 54001800 rlwinm 0,0,3,0,0 -- 54006800 rlwinm 0,0,13,0,0 -- 5400E800 rlwinm 0,0,29,0,0 -- 54009800 rlwinm 0,0,19,0,0 -+ 5400183E rlwinm 0,0,3,0,31 -+ 5400683E rlwinm 0,0,13,0,31 -+ 5400E83E rlwinm 0,0,29,0,31 -+ 5400983E rlwinm 0,0,19,0,31 - 64-bit mode: - 78001800 rotldi 0,0,3 - 78006800 rotldi 0,0,13 - 7800E802 rotldi 0,0,61 - 78009802 rotldi 0,0,51 - */ -- UInt word1 = mode64 ? 0x78001800 : 0x54001800; -- UInt word2 = mode64 ? 0x78006800 : 0x54006800; -- UInt word3 = mode64 ? 0x7800E802 : 0x5400E800; -- UInt word4 = mode64 ? 0x78009802 : 0x54009800; -+ UInt word1 = mode64 ? 0x78001800 : 0x5400183E; -+ UInt word2 = mode64 ? 0x78006800 : 0x5400683E; -+ UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E; -+ UInt word4 = mode64 ? 0x78009802 : 0x5400983E; - if (getUIntBigendianly(code+ 0) == word1 && - getUIntBigendianly(code+ 4) == word2 && - getUIntBigendianly(code+ 8) == word3 && diff --git a/VEX-r2858.diff b/VEX-r2858.diff deleted file mode 100644 index 0acb305..0000000 --- a/VEX-r2858.diff +++ /dev/null @@ -1,233 +0,0 @@ ------------------------------------------------------------------------- -r2858 | mjw | 2014-05-09 13:41:06 +0200 (Fr, 09 Mai 2014) | 6 lines - -Recognize MPX instructions and bnd prefix. Bug #333666. - -Recognize and parse operands of new MPX instructions BNDMK, BNDCL, -BNDCU, BNDCN, BNDMOV, BNDLDX and BNDSTX. Also recognize bnd (F2) prefix -for CALL (E8,FF/2), RET (C2,C3), JMP (EB,E9,FF/4) and Jcc (70-7F,0F 80-8F). -All new MPX instructions are currently NOPs and the bnd prefix is ignored. ------------------------------------------------------------------------- -Index: VEX/priv/guest_amd64_toIR.c -=================================================================== ---- VEX/priv/guest_amd64_toIR.c.orig -+++ VEX/priv/guest_amd64_toIR.c -@@ -771,10 +771,10 @@ static Bool have66orF2orF3 ( Prefix pfx - return toBool( ! haveNo66noF2noF3(pfx) ); - } - --/* Return True iff pfx has 66 or F2 set */ --static Bool have66orF2 ( Prefix pfx ) -+/* Return True iff pfx has 66 or F3 set */ -+static Bool have66orF3 ( Prefix pfx ) - { -- return toBool((pfx & (PFX_66|PFX_F2)) > 0); -+ return toBool((pfx & (PFX_66|PFX_F3)) > 0); - } - - /* Clear all the segment-override bits in a prefix. */ -@@ -4270,8 +4270,12 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, - - modrm = getUChar(delta); - if (epartIsReg(modrm)) { -- /* F2/XACQ and F3/XREL are always invalid in the non-mem case. */ -- if (haveF2orF3(pfx)) goto unhandledR; -+ /* F2/XACQ and F3/XREL are always invalid in the non-mem case. -+ F2/CALL and F2/JMP may have bnd prefix. */ -+ if (haveF2orF3(pfx) -+ && ! (haveF2(pfx) -+ && (gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4))) -+ goto unhandledR; - assign(t1, getIRegE(sz,pfx,modrm)); - switch (gregLO3ofRM(modrm)) { - case 0: /* INC */ -@@ -4291,6 +4295,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, - case 2: /* call Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledR; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, getIRegE(sz,pfx,modrm)); -@@ -4306,6 +4311,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, - case 4: /* jmp Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledR; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, getIRegE(sz,pfx,modrm)); -@@ -4338,11 +4344,14 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, - showSz ? nameISize(sz) : ' ', - nameIRegE(sz, pfx, modrm)); - } else { -- /* Decide if F2/XACQ or F3/XREL might be valid. */ -+ /* Decide if F2/XACQ, F3/XREL, F2/CALL or F2/JMP might be valid. */ - Bool validF2orF3 = haveF2orF3(pfx) ? False : True; - if ((gregLO3ofRM(modrm) == 0/*INC*/ || gregLO3ofRM(modrm) == 1/*DEC*/) - && haveF2orF3(pfx) && !haveF2andF3(pfx) && haveLOCK(pfx)) { - validF2orF3 = True; -+ } else if ((gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4) -+ && (haveF2(pfx) && !haveF3(pfx))) { -+ validF2orF3 = True; - } - if (!validF2orF3) goto unhandledM; - /* */ -@@ -4379,6 +4388,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, - case 2: /* call Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledM; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, loadLE(Ity_I64,mkexpr(addr))); -@@ -4394,6 +4404,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi, - case 4: /* JMP Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledM; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, loadLE(Ity_I64,mkexpr(addr))); -@@ -19550,7 +19561,8 @@ Long dis_ESC_NONE ( - case 0x7F: { /* JGb/JNLEb (jump greater) */ - Long jmpDelta; - const HChar* comment = ""; -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - jmpDelta = getSDisp8(delta); - vassert(-128 <= jmpDelta && jmpDelta < 128); - d64 = (guest_RIP_bbstart+delta+1) + jmpDelta; -@@ -20203,7 +20215,8 @@ Long dis_ESC_NONE ( - } - - case 0xC2: /* RET imm16 */ -- if (have66orF2orF3(pfx)) goto decode_failure; -+ if (have66orF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = getUDisp16(delta); - delta += 2; - dis_ret(dres, vbi, d64); -@@ -20211,8 +20224,9 @@ Long dis_ESC_NONE ( - return delta; - - case 0xC3: /* RET */ -- if (have66orF2(pfx)) goto decode_failure; -+ if (have66(pfx)) goto decode_failure; - /* F3 is acceptable on AMD. */ -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - dis_ret(dres, vbi, 0); - DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n"); - return delta; -@@ -20606,7 +20620,8 @@ Long dis_ESC_NONE ( - } - - case 0xE8: /* CALL J4 */ -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = getSDisp32(delta); delta += 4; - d64 += (guest_RIP_bbstart+delta); - /* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */ -@@ -20629,9 +20644,10 @@ Long dis_ESC_NONE ( - return delta; - - case 0xE9: /* Jv (jump, 16/32 offset) */ -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; - if (sz != 4) - goto decode_failure; /* JRS added 2004 July 11 */ -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta); - delta += sz; - if (resteerOkFn(callback_opaque,d64)) { -@@ -20645,9 +20661,10 @@ Long dis_ESC_NONE ( - return delta; - - case 0xEB: /* Jb (jump, byte offset) */ -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; - if (sz != 4) - goto decode_failure; /* JRS added 2004 July 11 */ -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta); - delta++; - if (resteerOkFn(callback_opaque,d64)) { -@@ -21065,7 +21082,8 @@ Long dis_ESC_0F ( - case 0x8F: { /* JGb/JNLEb (jump greater) */ - Long jmpDelta; - const HChar* comment = ""; -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - jmpDelta = getSDisp32(delta); - d64 = (guest_RIP_bbstart+delta+4) + jmpDelta; - delta += 4; -@@ -21156,6 +21174,66 @@ Long dis_ESC_0F ( - } - return delta; - -+ case 0x1A: -+ case 0x1B: { /* Future MPX instructions, currently NOPs. -+ BNDMK b, m F3 0F 1B -+ BNDCL b, r/m F3 0F 1A -+ BNDCU b, r/m F2 0F 1A -+ BNDCN b, r/m F2 0F 1B -+ BNDMOV b, b/m 66 0F 1A -+ BNDMOV b/m, b 66 0F 1B -+ BNDLDX b, mib 0F 1A -+ BNDSTX mib, b 0F 1B */ -+ -+ /* All instructions have two operands. One operand is always the -+ bnd register number (bnd0-bnd3, other register numbers are -+ ignored when MPX isn't enabled, but should generate an -+ exception if MPX is enabled) given by gregOfRexRM. The other -+ operand is either a ModRM:reg, ModRM:r/m or a SIB encoded -+ address, all of which can be decoded by using either -+ eregOfRexRM or disAMode. */ -+ -+ modrm = getUChar(delta); -+ int bnd = gregOfRexRM(pfx,modrm); -+ const HChar *oper; -+ if (epartIsReg(modrm)) { -+ oper = nameIReg64 (eregOfRexRM(pfx,modrm)); -+ delta += 1; -+ } else { -+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); -+ delta += alen; -+ oper = dis_buf; -+ } -+ -+ if (haveF3no66noF2 (pfx)) { -+ if (opc == 0x1B) { -+ DIP ("bndmk %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1A */ { -+ DIP ("bndcl %s, %%bnd%d\n", oper, bnd); -+ } -+ } else if (haveF2no66noF3 (pfx)) { -+ if (opc == 0x1A) { -+ DIP ("bndcu %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1B */ { -+ DIP ("bndcn %s, %%bnd%d\n", oper, bnd); -+ } -+ } else if (have66noF2noF3 (pfx)) { -+ if (opc == 0x1A) { -+ DIP ("bndmov %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1B */ { -+ DIP ("bndmov %%bnd%d, %s\n", bnd, oper); -+ } -+ } else if (haveNo66noF2noF3 (pfx)) { -+ if (opc == 0x1A) { -+ DIP ("bndldx %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1B */ { -+ DIP ("bndstx %%bnd%d, %s\n", bnd, oper); -+ } -+ } else goto decode_failure; -+ -+ return delta; -+ } -+ - case 0xA2: { /* CPUID */ - /* Uses dirty helper: - void amd64g_dirtyhelper_CPUID ( VexGuestAMD64State* ) diff --git a/VEX-r2904.diff b/VEX-r2904.diff deleted file mode 100644 index fc588a4..0000000 --- a/VEX-r2904.diff +++ /dev/null @@ -1,131 +0,0 @@ -Index: VEX/priv/host_ppc_isel.c -=================================================================== ---- VEX/priv/host_ppc_isel.c.orig -+++ VEX/priv/host_ppc_isel.c -@@ -704,12 +704,6 @@ void doHelperCall ( /*OUT*/UInt* stack - UInt nVECRETs = 0; - UInt nBBPTRs = 0; - -- /* Do we need to force use of an odd-even reg pair for 64-bit args? -- JRS 31-07-2013: is this still relevant, now that we are not -- generating code for 32-bit AIX ? */ -- Bool regalign_int64s -- = (!mode64) && env->vbi->host_ppc32_regalign_int64_args; -- - /* Marshal args for a call and do the call. - - This function only deals with a tiny set of possibilities, which -@@ -867,7 +861,7 @@ void doHelperCall ( /*OUT*/UInt* stack - iselWordExpr_R(env, arg) )); - } else { // Ity_I64 in 32-bit mode - HReg rHi, rLo; -- if (regalign_int64s && (argreg%2) == 1) -+ if ((argreg%2) == 1) - // ppc32 ELF abi spec for passing LONG_LONG - argreg++; // XXX: odd argreg => even rN - vassert(argreg < PPC_N_REGPARMS-1); -@@ -943,7 +937,7 @@ void doHelperCall ( /*OUT*/UInt* stack - tmpregs[argreg] = iselWordExpr_R(env, arg); - } else { // Ity_I64 in 32-bit mode - HReg rHi, rLo; -- if (regalign_int64s && (argreg%2) == 1) -+ if ((argreg%2) == 1) - // ppc32 ELF abi spec for passing LONG_LONG - argreg++; // XXX: odd argreg => even rN - vassert(argreg < PPC_N_REGPARMS-1); -Index: VEX/priv/guest_ppc_toIR.c -=================================================================== ---- VEX/priv/guest_ppc_toIR.c.orig -+++ VEX/priv/guest_ppc_toIR.c -@@ -6060,9 +6060,7 @@ static Bool dis_syslink ( UInt theInstr, - /* It's important that all ArchRegs carry their up-to-date value - at this point. So we declare an end-of-block here, which - forces any TempRegs caching ArchRegs to be flushed. */ -- putGST( PPC_GST_CIA, abiinfo->guest_ppc_sc_continues_at_LR -- ? getGST( PPC_GST_LR ) -- : mkSzImm( ty, nextInsnAddr() )); -+ putGST( PPC_GST_CIA, mkSzImm( ty, nextInsnAddr() )); - - dres->whatNext = Dis_StopHere; - dres->jk_StopHere = Ijk_Sys_syscall; -Index: VEX/priv/main_main.c -=================================================================== ---- VEX/priv/main_main.c.orig -+++ VEX/priv/main_main.c -@@ -1242,9 +1242,7 @@ void LibVEX_default_VexAbiInfo ( /*OUT*/ - vbi->guest_amd64_assume_gs_is_0x60 = False; - vbi->guest_ppc_zap_RZ_at_blr = False; - vbi->guest_ppc_zap_RZ_at_bl = NULL; -- vbi->guest_ppc_sc_continues_at_LR = False; - vbi->host_ppc_calls_use_fndescrs = False; -- vbi->host_ppc32_regalign_int64_args = False; - } - - -Index: VEX/pub/libvex.h -=================================================================== ---- VEX/pub/libvex.h.orig -+++ VEX/pub/libvex.h -@@ -291,8 +291,6 @@ void LibVEX_default_VexArchInfo ( /*OUT* - guest_stack_redzone_size - guest is ppc32-linux ==> 0 - guest is ppc64-linux ==> 288 -- guest is ppc32-aix5 ==> 220 -- guest is ppc64-aix5 ==> unknown - guest is amd64-linux ==> 128 - guest is other ==> inapplicable - -@@ -309,32 +307,16 @@ void LibVEX_default_VexArchInfo ( /*OUT* - guest_ppc_zap_RZ_at_blr - guest is ppc64-linux ==> True - guest is ppc32-linux ==> False -- guest is ppc64-aix5 ==> unknown -- guest is ppc32-aix5 ==> False - guest is other ==> inapplicable - - guest_ppc_zap_RZ_at_bl - guest is ppc64-linux ==> const True - guest is ppc32-linux ==> const False -- guest is ppc64-aix5 ==> unknown -- guest is ppc32-aix5 ==> True except for calls to -- millicode, $SAVEFn, $RESTFn -- guest is other ==> inapplicable -- -- guest_ppc_sc_continues_at_LR: -- guest is ppc32-aix5 or ppc64-aix5 ==> True -- guest is ppc32-linux or ppc64-linux ==> False - guest is other ==> inapplicable - - host_ppc_calls_use_fndescrs: - host is ppc32-linux ==> False - host is ppc64-linux ==> True -- host is ppc32-aix5 or ppc64-aix5 ==> True -- host is other ==> inapplicable -- -- host_ppc32_regalign_int64_args: -- host is ppc32-linux ==> True -- host is ppc32-aix5 ==> False - host is other ==> inapplicable - */ - -@@ -364,20 +346,10 @@ typedef - is assumed equivalent to a fn which always returns False. */ - Bool (*guest_ppc_zap_RZ_at_bl)(Addr64); - -- /* PPC32/PPC64 GUESTS only: where does the kernel resume after -- 'sc'? False => Linux style, at the next insn. True => AIX -- style, at the address stated in the link register. */ -- Bool guest_ppc_sc_continues_at_LR; -- - /* PPC32/PPC64 HOSTS only: does '&f' give us a pointer to a - function descriptor on the host, or to the function code - itself? True => descriptor, False => code. */ - Bool host_ppc_calls_use_fndescrs; -- -- /* PPC32 HOSTS only: when generating code to pass a 64-bit value -- (actual parameter) in a pair of regs, should we skip an arg -- reg if it is even-numbered? True => yes, False => no. */ -- Bool host_ppc32_regalign_int64_args; - } - VexAbiInfo; - diff --git a/VEX-r2910.diff b/VEX-r2910.diff deleted file mode 100644 index 4196806..0000000 --- a/VEX-r2910.diff +++ /dev/null @@ -1,2010 +0,0 @@ -Index: VEX/priv/host_x86_isel.c -=================================================================== ---- VEX/priv/host_x86_isel.c.orig -+++ VEX/priv/host_x86_isel.c -@@ -4397,6 +4397,9 @@ HInstrArray* iselSB_X86 ( IRSB* bb, - vassert(sizeof(max_ga) == 8); - vassert((max_ga >> 32) == 0); - -+ /* Check that the host's endianness is as expected. */ -+ vassert(archinfo_host->endness == VexEndnessLE); -+ - /* Make up an initial environment to use. */ - env = LibVEX_Alloc(sizeof(ISelEnv)); - env->vreg_ctr = 0; -Index: VEX/priv/guest_ppc_defs.h -=================================================================== ---- VEX/priv/guest_ppc_defs.h.orig -+++ VEX/priv/guest_ppc_defs.h -@@ -61,7 +61,7 @@ DisResult disInstr_PPC ( IRSB* ir - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian, -+ VexEndness host_endness, - Bool sigill_diag ); - - /* Used by the optimiser to specialise calls to helpers. */ -Index: VEX/priv/host_arm_defs.c -=================================================================== ---- VEX/priv/host_arm_defs.c.orig -+++ VEX/priv/host_arm_defs.c -@@ -2970,7 +2970,7 @@ static UInt* do_load_or_store32 ( UInt* - - Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, ARMInstr* i, -- Bool mode64, -+ Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -4643,7 +4643,7 @@ Int emit_ARMInstr ( /*MB_MOD*/Bool* is_p - /* nofail: */ - - /* Crosscheck */ -- vassert(evCheckSzB_ARM() == (UChar*)p - (UChar*)p0); -+ vassert(evCheckSzB_ARM(endness_host) == (UChar*)p - (UChar*)p0); - goto done; - } - -@@ -4694,7 +4694,7 @@ Int emit_ARMInstr ( /*MB_MOD*/Bool* is_p - /* How big is an event check? See case for ARMin_EvCheck in - emit_ARMInstr just above. That crosschecks what this returns, so - we can tell if we're inconsistent. */ --Int evCheckSzB_ARM ( void ) -+Int evCheckSzB_ARM ( VexEndness endness_host ) - { - return 24; - } -@@ -4702,10 +4702,13 @@ Int evCheckSzB_ARM ( void ) - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange chainXDirect_ARM ( void* place_to_chain, -+VexInvalRange chainXDirect_ARM ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ) - { -+ vassert(endness_host == VexEndnessLE); -+ - /* What we're expecting to see is: - movw r12, lo16(disp_cp_chain_me_to_EXPECTED) - movt r12, hi16(disp_cp_chain_me_to_EXPECTED) -@@ -4782,10 +4785,13 @@ VexInvalRange chainXDirect_ARM ( void* p - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange unchainXDirect_ARM ( void* place_to_unchain, -+VexInvalRange unchainXDirect_ARM ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me ) - { -+ vassert(endness_host == VexEndnessLE); -+ - /* What we're expecting to see is: - (general case) - movw r12, lo16(place_to_jump_to_EXPECTED) -@@ -4843,9 +4849,11 @@ VexInvalRange unchainXDirect_ARM ( void* - - /* Patch the counter address into a profile inc point, as previously - created by the ARMin_ProfInc case for emit_ARMInstr. */ --VexInvalRange patchProfInc_ARM ( void* place_to_patch, -+VexInvalRange patchProfInc_ARM ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter ) - { -+ vassert(endness_host == VexEndnessLE); - vassert(sizeof(ULong*) == 4); - UInt* p = (UInt*)place_to_patch; - vassert(0 == (3 & (HWord)p)); -Index: VEX/priv/host_arm_defs.h -=================================================================== ---- VEX/priv/host_arm_defs.h.orig -+++ VEX/priv/host_arm_defs.h -@@ -1026,6 +1026,7 @@ extern Bool isMove_ARMInstr ( ARMIn - extern Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, ARMInstr* i, - Bool mode64, -+ VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -1050,19 +1051,22 @@ extern HInstrArray* iselSB_ARM ( IRSB* - /* How big is an event check? This is kind of a kludge because it - depends on the offsets of host_EvC_FAILADDR and - host_EvC_COUNTER. */ --extern Int evCheckSzB_ARM ( void ); -+extern Int evCheckSzB_ARM ( VexEndness endness_host ); - - /* Perform a chaining and unchaining of an XDirect jump. */ --extern VexInvalRange chainXDirect_ARM ( void* place_to_chain, -+extern VexInvalRange chainXDirect_ARM ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ); - --extern VexInvalRange unchainXDirect_ARM ( void* place_to_unchain, -+extern VexInvalRange unchainXDirect_ARM ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me ); - - /* Patch the counter location into an existing ProfInc point. */ --extern VexInvalRange patchProfInc_ARM ( void* place_to_patch, -+extern VexInvalRange patchProfInc_ARM ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter ); - - -Index: VEX/priv/guest_arm_toIR.c -=================================================================== ---- VEX/priv/guest_arm_toIR.c.orig -+++ VEX/priv/guest_arm_toIR.c -@@ -123,10 +123,10 @@ - not change during translation of the instruction. - */ - --/* CONST: is the host bigendian? This has to do with float vs double -- register accesses on VFP, but it's complex and not properly thought -- out. */ --static Bool host_is_bigendian; -+/* CONST: what is the host's endianness? This has to do with float vs -+ double register accesses on VFP, but it's complex and not properly -+ thought out. */ -+static VexEndness host_endness; - - /* CONST: The guest address for the instruction currently being - translated. This is the real, "decoded" address (not subject -@@ -849,11 +849,11 @@ static Int floatGuestRegOffset ( UInt fr - Int off; - vassert(fregNo < 32); - off = doubleGuestRegOffset(fregNo >> 1); -- if (host_is_bigendian) { -- vassert(0); -- } else { -+ if (host_endness == VexEndnessLE) { - if (fregNo & 1) - off += 4; -+ } else { -+ vassert(0); - } - return off; - } -@@ -21899,7 +21899,7 @@ DisResult disInstr_ARM ( IRSB* ir - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian_IN, -+ VexEndness host_endness_IN, - Bool sigill_diag_IN ) - { - DisResult dres; -@@ -21908,9 +21908,9 @@ DisResult disInstr_ARM ( IRSB* ir - /* Set globals (see top of this file) */ - vassert(guest_arch == VexArchARM); - -- irsb = irsb_IN; -- host_is_bigendian = host_bigendian_IN; -- __curr_is_Thumb = isThumb; -+ irsb = irsb_IN; -+ host_endness = host_endness_IN; -+ __curr_is_Thumb = isThumb; - - if (isThumb) { - guest_R15_curr_instr_notENC = (Addr32)guest_IP_ENCODED - 1; -Index: VEX/priv/guest_amd64_defs.h -=================================================================== ---- VEX/priv/guest_amd64_defs.h.orig -+++ VEX/priv/guest_amd64_defs.h -@@ -60,7 +60,7 @@ DisResult disInstr_AMD64 ( IRSB* - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian, -+ VexEndness host_endness, - Bool sigill_diag ); - - /* Used by the optimiser to specialise calls to helpers. */ -Index: VEX/priv/host_arm_isel.c -=================================================================== ---- VEX/priv/host_arm_isel.c.orig -+++ VEX/priv/host_arm_isel.c -@@ -6356,6 +6356,9 @@ HInstrArray* iselSB_ARM ( IRSB* bb, - /* sanity ... */ - vassert(arch_host == VexArchARM); - -+ /* Check that the host's endianness is as expected. */ -+ vassert(archinfo_host->endness == VexEndnessLE); -+ - /* guard against unexpected space regressions */ - vassert(sizeof(ARMInstr) <= 28); - -Index: VEX/priv/guest_s390_toIR.c -=================================================================== ---- VEX/priv/guest_s390_toIR.c.orig -+++ VEX/priv/guest_s390_toIR.c -@@ -16564,13 +16564,13 @@ disInstr_S390(IRSB *irsb_IN, - VexArch guest_arch, - VexArchInfo *archinfo, - VexAbiInfo *abiinfo, -- Bool host_bigendian, -+ VexEndness host_endness, - Bool sigill_diag_IN) - { - vassert(guest_arch == VexArchS390X); - - /* The instruction decoder requires a big-endian machine. */ -- vassert(host_bigendian == True); -+ vassert(host_endness == VexEndnessBE); - - /* Set globals (see top of this file) */ - guest_IA_curr_instr = guest_IP; -Index: VEX/priv/guest_mips_toIR.c -=================================================================== ---- VEX/priv/guest_mips_toIR.c.orig -+++ VEX/priv/guest_mips_toIR.c -@@ -49,10 +49,10 @@ - that we don't have to pass them around endlessly. CONST means does - not change during translation of the instruction. */ - --/* CONST: is the host bigendian? This has to do with float vs double -- register accesses on VFP, but it's complex and not properly thought -- out. */ --static Bool host_is_bigendian; -+/* CONST: what is the host's endianness? This has to do with float vs -+ double register accesses on VFP, but it's complex and not properly -+ thought out. */ -+static VexEndness host_endness; - - /* Pointer to the guest code area. */ - static UChar *guest_code; -@@ -16433,7 +16433,7 @@ DisResult disInstr_MIPS( IRSB* ir - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian_IN, -+ VexEndness host_endness_IN, - Bool sigill_diag_IN ) - { - DisResult dres; -@@ -16444,7 +16444,7 @@ DisResult disInstr_MIPS( IRSB* ir - - guest_code = guest_code_IN; - irsb = irsb_IN; -- host_is_bigendian = host_bigendian_IN; -+ host_endness = host_endness_IN; - #if defined(VGP_mips32_linux) - guest_PC_curr_instr = (Addr32)guest_IP; - #elif defined(VGP_mips64_linux) -Index: VEX/priv/host_ppc_defs.c -=================================================================== ---- VEX/priv/host_ppc_defs.c.orig -+++ VEX/priv/host_ppc_defs.c -@@ -3720,7 +3720,7 @@ static UChar* mkFormVA ( UChar* p, UInt - */ - Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, PPCInstr* i, -- Bool mode64, -+ Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -5707,7 +5707,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* nofail: */ - - /* Crosscheck */ -- vassert(evCheckSzB_PPC() == (UChar*)p - (UChar*)p0); -+ vassert(evCheckSzB_PPC(endness_host) == (UChar*)p - (UChar*)p0); - goto done; - } - -@@ -5772,7 +5772,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* How big is an event check? See case for Pin_EvCheck in - emit_PPCInstr just above. That crosschecks what this returns, so - we can tell if we're inconsistent. */ --Int evCheckSzB_PPC ( void ) -+Int evCheckSzB_PPC ( VexEndness endness_host ) - { - return 28; - } -@@ -5780,11 +5780,18 @@ Int evCheckSzB_PPC ( void ) - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange chainXDirect_PPC ( void* place_to_chain, -+VexInvalRange chainXDirect_PPC ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to, - Bool mode64 ) - { -+ if (mode64) { -+ vassert(endness_host == VexEndnessBE); /* later: or LE */ -+ } else { -+ vassert(endness_host == VexEndnessBE); -+ } -+ - /* What we're expecting to see is: - imm32/64-fixed r30, disp_cp_chain_me_to_EXPECTED - mtctr r30 -@@ -5825,11 +5832,18 @@ VexInvalRange chainXDirect_PPC ( void* p - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange unchainXDirect_PPC ( void* place_to_unchain, -+VexInvalRange unchainXDirect_PPC ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me, - Bool mode64 ) - { -+ if (mode64) { -+ vassert(endness_host == VexEndnessBE); /* later: or LE */ -+ } else { -+ vassert(endness_host == VexEndnessBE); -+ } -+ - /* What we're expecting to see is: - imm32/64-fixed r30, place_to_jump_to_EXPECTED - mtctr r30 -@@ -5870,10 +5884,17 @@ VexInvalRange unchainXDirect_PPC ( void* - - /* Patch the counter address into a profile inc point, as previously - created by the Pin_ProfInc case for emit_PPCInstr. */ --VexInvalRange patchProfInc_PPC ( void* place_to_patch, -+VexInvalRange patchProfInc_PPC ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter, - Bool mode64 ) - { -+ if (mode64) { -+ vassert(endness_host == VexEndnessBE); /* later: or LE */ -+ } else { -+ vassert(endness_host == VexEndnessBE); -+ } -+ - UChar* p = (UChar*)place_to_patch; - vassert(0 == (3 & (HWord)p)); - -Index: VEX/priv/guest_generic_bb_to_IR.c -=================================================================== ---- VEX/priv/guest_generic_bb_to_IR.c.orig -+++ VEX/priv/guest_generic_bb_to_IR.c -@@ -186,7 +186,7 @@ IRSB* bb_to_IR ( - /*IN*/ UChar* guest_code, - /*IN*/ Addr64 guest_IP_bbstart, - /*IN*/ Bool (*chase_into_ok)(void*,Addr64), -- /*IN*/ Bool host_bigendian, -+ /*IN*/ VexEndness host_endness, - /*IN*/ Bool sigill_diag, - /*IN*/ VexArch arch_guest, - /*IN*/ VexArchInfo* archinfo_guest, -@@ -362,7 +362,7 @@ IRSB* bb_to_IR ( - arch_guest, - archinfo_guest, - abiinfo_both, -- host_bigendian, -+ host_endness, - sigill_diag ); - - /* stay sane ... */ -Index: VEX/priv/host_ppc_defs.h -=================================================================== ---- VEX/priv/host_ppc_defs.h.orig -+++ VEX/priv/host_ppc_defs.h -@@ -1138,6 +1138,7 @@ extern Bool isMove_PPCInstr - extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, PPCInstr* i, - Bool mode64, -+ VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -1162,21 +1163,24 @@ extern HInstrArray* iselSB_PPC - /* How big is an event check? This is kind of a kludge because it - depends on the offsets of host_EvC_FAILADDR and - host_EvC_COUNTER. */ --extern Int evCheckSzB_PPC ( void ); -+extern Int evCheckSzB_PPC ( VexEndness endness_host ); - - /* Perform a chaining and unchaining of an XDirect jump. */ --extern VexInvalRange chainXDirect_PPC ( void* place_to_chain, -+extern VexInvalRange chainXDirect_PPC ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to, - Bool mode64 ); - --extern VexInvalRange unchainXDirect_PPC ( void* place_to_unchain, -+extern VexInvalRange unchainXDirect_PPC ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me, - Bool mode64 ); - - /* Patch the counter location into an existing ProfInc point. */ --extern VexInvalRange patchProfInc_PPC ( void* place_to_patch, -+extern VexInvalRange patchProfInc_PPC ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter, - Bool mode64 ); - -Index: VEX/priv/guest_ppc_toIR.c -=================================================================== ---- VEX/priv/guest_ppc_toIR.c.orig -+++ VEX/priv/guest_ppc_toIR.c -@@ -148,7 +148,7 @@ - given insn. */ - - /* We need to know this to do sub-register accesses correctly. */ --static Bool host_is_bigendian; -+static VexEndness host_endness; - - /* Pointer to the guest code area. */ - static UChar* guest_code; -@@ -1033,7 +1033,7 @@ static Int integerGuestRegOffset ( UInt - // jrs: probably not necessary; only matters if we reference sub-parts - // of the ppc registers, but that isn't the case - // later: this might affect Altivec though? -- vassert(host_is_bigendian); -+ vassert(host_endness == VexEndnessBE); - - switch (archreg) { - case 0: return offsetofPPCGuestState(guest_GPR0); -@@ -19918,7 +19918,7 @@ DisResult disInstr_PPC ( IRSB* ir - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian_IN, -+ VexEndness host_endness_IN, - Bool sigill_diag_IN ) - { - IRType ty; -@@ -19950,7 +19950,7 @@ DisResult disInstr_PPC ( IRSB* ir - /* Set globals (see top of this file) */ - guest_code = guest_code_IN; - irsb = irsb_IN; -- host_is_bigendian = host_bigendian_IN; -+ host_endness = host_endness_IN; - - guest_CIA_curr_instr = mkSzAddr(ty, guest_IP); - guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta); -Index: VEX/priv/guest_generic_bb_to_IR.h -=================================================================== ---- VEX/priv/guest_generic_bb_to_IR.h.orig -+++ VEX/priv/guest_generic_bb_to_IR.h -@@ -152,8 +152,8 @@ typedef - /* ABI info for both guest and host */ - /*IN*/ VexAbiInfo* abiinfo, - -- /* Is the host bigendian? */ -- /*IN*/ Bool host_bigendian, -+ /* The endianness of the host */ -+ /*IN*/ VexEndness host_endness, - - /* Should diagnostics be printed for illegal instructions? */ - /*IN*/ Bool sigill_diag -@@ -176,7 +176,7 @@ IRSB* bb_to_IR ( - /*IN*/ UChar* guest_code, - /*IN*/ Addr64 guest_IP_bbstart, - /*IN*/ Bool (*chase_into_ok)(void*,Addr64), -- /*IN*/ Bool host_bigendian, -+ /*IN*/ VexEndness host_endness, - /*IN*/ Bool sigill_diag, - /*IN*/ VexArch arch_guest, - /*IN*/ VexArchInfo* archinfo_guest, -Index: VEX/priv/host_ppc_isel.c -=================================================================== ---- VEX/priv/host_ppc_isel.c.orig -+++ VEX/priv/host_ppc_isel.c -@@ -5904,6 +5904,9 @@ HInstrArray* iselSB_PPC ( IRSB* bb, - vassert((hwcaps_host & mask64) == 0); - } - -+ /* Check that the host's endianness is as expected. */ -+ vassert(archinfo_host->endness == VexEndnessBE); -+ - /* Make up an initial environment to use. */ - env = LibVEX_Alloc(sizeof(ISelEnv)); - env->vreg_ctr = 0; -Index: VEX/priv/host_amd64_defs.c -=================================================================== ---- VEX/priv/host_amd64_defs.c.orig -+++ VEX/priv/host_amd64_defs.c -@@ -2265,7 +2265,7 @@ static UChar* do_ffree_st ( UChar* p, In - - Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, AMD64Instr* i, -- Bool mode64, -+ Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -3483,7 +3483,7 @@ Int emit_AMD64Instr ( /*MB_MOD*/Bool* is - p = doAMode_M(p, fake(4), i->Ain.EvCheck.amFailAddr); - vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */ - /* And crosscheck .. */ -- vassert(evCheckSzB_AMD64() == 8); -+ vassert(evCheckSzB_AMD64(endness_host) == 8); - goto done; - } - -@@ -3526,7 +3526,7 @@ Int emit_AMD64Instr ( /*MB_MOD*/Bool* is - /* How big is an event check? See case for Ain_EvCheck in - emit_AMD64Instr just above. That crosschecks what this returns, so - we can tell if we're inconsistent. */ --Int evCheckSzB_AMD64 ( void ) -+Int evCheckSzB_AMD64 ( VexEndness endness_host ) - { - return 8; - } -@@ -3534,10 +3534,13 @@ Int evCheckSzB_AMD64 ( void ) - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange chainXDirect_AMD64 ( void* place_to_chain, -+VexInvalRange chainXDirect_AMD64 ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ) - { -+ vassert(endness_host == VexEndnessLE); -+ - /* What we're expecting to see is: - movabsq $disp_cp_chain_me_EXPECTED, %r11 - call *%r11 -@@ -3620,10 +3623,13 @@ VexInvalRange chainXDirect_AMD64 ( void* - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain, -+VexInvalRange unchainXDirect_AMD64 ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me ) - { -+ vassert(endness_host == VexEndnessLE); -+ - /* What we're expecting to see is either: - (general case) - movabsq $place_to_jump_to_EXPECTED, %r11 -@@ -3684,9 +3690,11 @@ VexInvalRange unchainXDirect_AMD64 ( voi - - /* Patch the counter address into a profile inc point, as previously - created by the Ain_ProfInc case for emit_AMD64Instr. */ --VexInvalRange patchProfInc_AMD64 ( void* place_to_patch, -+VexInvalRange patchProfInc_AMD64 ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter ) - { -+ vassert(endness_host == VexEndnessLE); - vassert(sizeof(ULong*) == 8); - UChar* p = (UChar*)place_to_patch; - vassert(p[0] == 0x49); -Index: VEX/priv/host_amd64_defs.h -=================================================================== ---- VEX/priv/host_amd64_defs.h.orig -+++ VEX/priv/host_amd64_defs.h -@@ -754,8 +754,10 @@ extern void getRegUsage_AMD64Ins - extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); - extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); - extern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, -- UChar* buf, Int nbuf, AMD64Instr* i, -+ UChar* buf, Int nbuf, -+ AMD64Instr* i, - Bool mode64, -+ VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -782,19 +784,22 @@ extern HInstrArray* iselSB_AMD64 - and so assumes that they are both <= 128, and so can use the short - offset encoding. This is all checked with assertions, so in the - worst case we will merely assert at startup. */ --extern Int evCheckSzB_AMD64 ( void ); -+extern Int evCheckSzB_AMD64 ( VexEndness endness_host ); - - /* Perform a chaining and unchaining of an XDirect jump. */ --extern VexInvalRange chainXDirect_AMD64 ( void* place_to_chain, -+extern VexInvalRange chainXDirect_AMD64 ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ); - --extern VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain, -+extern VexInvalRange unchainXDirect_AMD64 ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me ); - - /* Patch the counter location into an existing ProfInc point. */ --extern VexInvalRange patchProfInc_AMD64 ( void* place_to_patch, -+extern VexInvalRange patchProfInc_AMD64 ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter ); - - -Index: VEX/priv/guest_amd64_toIR.c -=================================================================== ---- VEX/priv/guest_amd64_toIR.c.orig -+++ VEX/priv/guest_amd64_toIR.c -@@ -189,7 +189,7 @@ - that we don't have to pass them around endlessly. */ - - /* We need to know this to do sub-register accesses correctly. */ --static Bool host_is_bigendian; -+static VexEndness host_endness; - - /* Pointer to the guest code area (points to start of BB, not to the - insn being processed). */ -@@ -979,7 +979,7 @@ Int offsetIReg ( Int sz, UInt reg, Bool - - static IRExpr* getIRegCL ( void ) - { -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - return IRExpr_Get( OFFB_RCX, Ity_I8 ); - } - -@@ -988,7 +988,7 @@ static IRExpr* getIRegCL ( void ) - - static void putIRegAH ( IRExpr* e ) - { -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8); - stmt( IRStmt_Put( OFFB_RAX+1, e ) ); - } -@@ -1010,7 +1010,7 @@ static const HChar* nameIRegRAX ( Int sz - - static IRExpr* getIRegRAX ( Int sz ) - { -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - switch (sz) { - case 1: return IRExpr_Get( OFFB_RAX, Ity_I8 ); - case 2: return IRExpr_Get( OFFB_RAX, Ity_I16 ); -@@ -1023,7 +1023,7 @@ static IRExpr* getIRegRAX ( Int sz ) - static void putIRegRAX ( Int sz, IRExpr* e ) - { - IRType ty = typeOfIRExpr(irsb->tyenv, e); -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - switch (sz) { - case 8: vassert(ty == Ity_I64); - stmt( IRStmt_Put( OFFB_RAX, e )); -@@ -1058,7 +1058,7 @@ static const HChar* nameIRegRDX ( Int sz - - static IRExpr* getIRegRDX ( Int sz ) - { -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - switch (sz) { - case 1: return IRExpr_Get( OFFB_RDX, Ity_I8 ); - case 2: return IRExpr_Get( OFFB_RDX, Ity_I16 ); -@@ -1070,7 +1070,7 @@ static IRExpr* getIRegRDX ( Int sz ) - - static void putIRegRDX ( Int sz, IRExpr* e ) - { -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(typeOfIRExpr(irsb->tyenv, e) == szToITy(sz)); - switch (sz) { - case 8: stmt( IRStmt_Put( OFFB_RDX, e )); -@@ -1112,7 +1112,7 @@ static const HChar* nameIReg64 ( UInt re - - static IRExpr* getIReg32 ( UInt regno ) - { -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - return unop(Iop_64to32, - IRExpr_Get( integerGuestReg64Offset(regno), - Ity_I64 )); -@@ -1136,7 +1136,7 @@ static const HChar* nameIReg32 ( UInt re - - static IRExpr* getIReg16 ( UInt regno ) - { -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - return IRExpr_Get( integerGuestReg64Offset(regno), - Ity_I16 ); - } -@@ -1257,7 +1257,7 @@ static UInt eregOfRexRM ( Prefix pfx, UC - static UInt offsetIRegG ( Int sz, Prefix pfx, UChar mod_reg_rm ) - { - UInt reg; -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(IS_VALID_PFX(pfx)); - vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1); - reg = gregOfRexRM( pfx, mod_reg_rm ); -@@ -1336,7 +1336,7 @@ const HChar* nameIRegV ( Int sz, Prefix - static UInt offsetIRegE ( Int sz, Prefix pfx, UChar mod_reg_rm ) - { - UInt reg; -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(IS_VALID_PFX(pfx)); - vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1); - reg = eregOfRexRM( pfx, mod_reg_rm ); -@@ -1405,7 +1405,7 @@ static Int ymmGuestRegOffset ( UInt ymmr - static Int xmmGuestRegOffset ( UInt xmmreg ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - return ymmGuestRegOffset( xmmreg ); - } - -@@ -1415,7 +1415,7 @@ static Int xmmGuestRegOffset ( UInt xmmr - static Int xmmGuestRegLane16offset ( UInt xmmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 8); - return xmmGuestRegOffset( xmmreg ) + 2 * laneno; - } -@@ -1423,7 +1423,7 @@ static Int xmmGuestRegLane16offset ( UIn - static Int xmmGuestRegLane32offset ( UInt xmmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 4); - return xmmGuestRegOffset( xmmreg ) + 4 * laneno; - } -@@ -1431,7 +1431,7 @@ static Int xmmGuestRegLane32offset ( UIn - static Int xmmGuestRegLane64offset ( UInt xmmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 2); - return xmmGuestRegOffset( xmmreg ) + 8 * laneno; - } -@@ -1439,7 +1439,7 @@ static Int xmmGuestRegLane64offset ( UIn - static Int ymmGuestRegLane128offset ( UInt ymmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 2); - return ymmGuestRegOffset( ymmreg ) + 16 * laneno; - } -@@ -1447,7 +1447,7 @@ static Int ymmGuestRegLane128offset ( UI - static Int ymmGuestRegLane64offset ( UInt ymmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 4); - return ymmGuestRegOffset( ymmreg ) + 8 * laneno; - } -@@ -1455,7 +1455,7 @@ static Int ymmGuestRegLane64offset ( UIn - static Int ymmGuestRegLane32offset ( UInt ymmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 8); - return ymmGuestRegOffset( ymmreg ) + 4 * laneno; - } -@@ -31549,7 +31549,7 @@ DisResult disInstr_AMD64 ( IRSB* - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian_IN, -+ VexEndness host_endness_IN, - Bool sigill_diag_IN ) - { - Int i, x1, x2; -@@ -31560,7 +31560,7 @@ DisResult disInstr_AMD64 ( IRSB* - vassert(guest_arch == VexArchAMD64); - guest_code = guest_code_IN; - irsb = irsb_IN; -- host_is_bigendian = host_bigendian_IN; -+ host_endness = host_endness_IN; - guest_RIP_curr_instr = guest_IP; - guest_RIP_bbstart = guest_IP - delta; - -Index: VEX/priv/host_amd64_isel.c -=================================================================== ---- VEX/priv/host_amd64_isel.c.orig -+++ VEX/priv/host_amd64_isel.c -@@ -4797,6 +4797,9 @@ HInstrArray* iselSB_AMD64 ( IRSB* bb, - | VEX_HWCAPS_AMD64_BMI - | VEX_HWCAPS_AMD64_AVX2))); - -+ /* Check that the host's endianness is as expected. */ -+ vassert(archinfo_host->endness == VexEndnessLE); -+ - /* Make up an initial environment to use. */ - env = LibVEX_Alloc(sizeof(ISelEnv)); - env->vreg_ctr = 0; -Index: VEX/priv/main_main.c -=================================================================== ---- VEX/priv/main_main.c.orig -+++ VEX/priv/main_main.c -@@ -223,7 +223,7 @@ VexTranslateResult LibVEX_Translate ( Ve - HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*, VexAbiInfo*, - Int, Int, Bool, Bool, Addr64 ); - Int (*emit) ( /*MB_MOD*/Bool*, -- UChar*, Int, HInstr*, Bool, -+ UChar*, Int, HInstr*, Bool, VexEndness, - void*, void*, void*, void* ); - IRExpr* (*specHelper) ( const HChar*, IRExpr**, IRStmt**, Int ); - Bool (*preciseMemExnsFn) ( Int, Int ); -@@ -231,7 +231,6 @@ VexTranslateResult LibVEX_Translate ( Ve - DisOneInstrFn disInstrFn; - - VexGuestLayout* guest_layout; -- Bool host_is_bigendian = False; - IRSB* irsb; - HInstrArray* vcode; - HInstrArray* rcode; -@@ -310,12 +309,12 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; - ppReg = (void(*)(HReg)) ppHRegX86; - iselSB = iselSB_X86; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_X86Instr; -- host_is_bigendian = False; - host_word_type = Ity_I32; - vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessLE); - break; - - case VexArchAMD64: -@@ -333,12 +332,12 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; - ppReg = (void(*)(HReg)) ppHRegAMD64; - iselSB = iselSB_AMD64; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_AMD64Instr; -- host_is_bigendian = False; - host_word_type = Ity_I64; - vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessLE); - break; - - case VexArchPPC32: -@@ -353,12 +352,12 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr; - ppReg = (void(*)(HReg)) ppHRegPPC; - iselSB = iselSB_PPC; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_PPCInstr; -- host_is_bigendian = True; - host_word_type = Ity_I32; - vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessBE); - break; - - case VexArchPPC64: -@@ -373,12 +372,13 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr; - ppReg = (void(*)(HReg)) ppHRegPPC; - iselSB = iselSB_PPC; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_PPCInstr; -- host_is_bigendian = True; - host_word_type = Ity_I64; - vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessBE -+ /* later: || vta->archinfo_host.endness == VexEndnessLE */); - break; - - case VexArchS390X: -@@ -393,11 +393,11 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppS390Instr; - ppReg = (void(*)(HReg)) ppHRegS390; - iselSB = iselSB_S390; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) emit_S390Instr; -- host_is_bigendian = True; - host_word_type = Ity_I64; - vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessBE); - break; - - case VexArchARM: -@@ -412,12 +412,12 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppARMInstr; - ppReg = (void(*)(HReg)) ppHRegARM; - iselSB = iselSB_ARM; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_ARMInstr; -- host_is_bigendian = False; - host_word_type = Ity_I32; - vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessLE); - break; - - case VexArchARM64: -@@ -436,12 +436,12 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppARM64Instr; - ppReg = (void(*)(HReg)) ppHRegARM64; - iselSB = iselSB_ARM64; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_ARM64Instr; -- host_is_bigendian = False; - host_word_type = Ity_I64; - vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessLE); - break; - - case VexArchMIPS32: -@@ -456,16 +456,13 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppMIPSInstr; - ppReg = (void(*)(HReg)) ppHRegMIPS; - iselSB = iselSB_MIPS; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_MIPSInstr; --# if defined(VKI_LITTLE_ENDIAN) -- host_is_bigendian = False; --# elif defined(VKI_BIG_ENDIAN) -- host_is_bigendian = True; --# endif - host_word_type = Ity_I32; - vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessLE -+ || vta->archinfo_host.endness == VexEndnessBE); - break; - - case VexArchMIPS64: -@@ -480,16 +477,13 @@ VexTranslateResult LibVEX_Translate ( Ve - ppInstr = (void(*)(HInstr*, Bool)) ppMIPSInstr; - ppReg = (void(*)(HReg)) ppHRegMIPS; - iselSB = iselSB_MIPS; -- emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,VexEndness, - void*,void*,void*,void*)) - emit_MIPSInstr; --# if defined(VKI_LITTLE_ENDIAN) -- host_is_bigendian = False; --# elif defined(VKI_BIG_ENDIAN) -- host_is_bigendian = True; --# endif - host_word_type = Ity_I64; - vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_host.hwcaps)); -+ vassert(vta->archinfo_host.endness == VexEndnessLE -+ || vta->archinfo_host.endness == VexEndnessBE); - break; - - default: -@@ -513,6 +507,7 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessLE); - vassert(0 == sizeof(VexGuestX86State) % 16); - vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); - vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); -@@ -533,6 +528,7 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessLE); - vassert(0 == sizeof(VexGuestAMD64State) % 16); - vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); - vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); -@@ -553,6 +549,7 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessBE); - vassert(0 == sizeof(VexGuestPPC32State) % 16); - vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); - vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); -@@ -573,6 +570,8 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessBE -+ /* later: || vta->archinfo_guest.endness == VexEndnessBE */); - vassert(0 == sizeof(VexGuestPPC64State) % 16); - vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); - vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); -@@ -594,6 +593,7 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessBE); - vassert(0 == sizeof(VexGuestS390XState) % 16); - vassert(sizeof( ((VexGuestS390XState*)0)->guest_TISTART ) == 8); - vassert(sizeof( ((VexGuestS390XState*)0)->guest_TILEN ) == 8); -@@ -614,6 +614,7 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessLE); - vassert(0 == sizeof(VexGuestARMState) % 16); - vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4); - vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4); -@@ -654,6 +655,8 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessLE -+ || vta->archinfo_guest.endness == VexEndnessBE); - vassert(0 == sizeof(VexGuestMIPS32State) % 16); - vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TISTART) == 4); - vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TILEN ) == 4); -@@ -674,6 +677,8 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_guest.hwcaps)); -+ vassert(vta->archinfo_guest.endness == VexEndnessLE -+ || vta->archinfo_guest.endness == VexEndnessBE); - vassert(0 == sizeof(VexGuestMIPS64State) % 16); - vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_TISTART) == 8); - vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_TILEN ) == 8); -@@ -697,6 +702,8 @@ VexTranslateResult LibVEX_Translate ( Ve - we are simulating one flavour of an architecture a different - flavour of the same architecture, which is pretty strange. */ - vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); -+ /* ditto */ -+ vassert(vta->archinfo_guest.endness == vta->archinfo_host.endness); - } - - vexAllocSanityCheck(); -@@ -714,7 +721,7 @@ VexTranslateResult LibVEX_Translate ( Ve - vta->guest_bytes, - vta->guest_bytes_addr, - vta->chase_into_ok, -- host_is_bigendian, -+ vta->archinfo_host.endness, - vta->sigill_diag, - vta->arch_guest, - &vta->archinfo_guest, -@@ -935,7 +942,8 @@ VexTranslateResult LibVEX_Translate ( Ve - vex_printf("\n"); - } - j = emit( &hi_isProfInc, -- insn_bytes, sizeof insn_bytes, hi, mode64, -+ insn_bytes, sizeof insn_bytes, hi, -+ mode64, vta->archinfo_host.endness, - vta->disp_cp_chain_me_to_slowEP, - vta->disp_cp_chain_me_to_fastEP, - vta->disp_cp_xindir, -@@ -992,12 +1000,13 @@ VexTranslateResult LibVEX_Translate ( Ve - - /* --------- Chain/Unchain XDirects. --------- */ - --VexInvalRange LibVEX_Chain ( VexArch arch_host, -- void* place_to_chain, -- void* disp_cp_chain_me_EXPECTED, -- void* place_to_jump_to ) -+VexInvalRange LibVEX_Chain ( VexArch arch_host, -+ VexEndness endness_host, -+ void* place_to_chain, -+ void* disp_cp_chain_me_EXPECTED, -+ void* place_to_jump_to ) - { -- VexInvalRange (*chainXDirect)(void*, void*, void*) = NULL; -+ VexInvalRange (*chainXDirect)(VexEndness, void*, void*, void*) = NULL; - switch (arch_host) { - case VexArchX86: - chainXDirect = chainXDirect_X86; break; -@@ -1010,19 +1019,23 @@ VexInvalRange LibVEX_Chain ( VexArch arc - case VexArchS390X: - chainXDirect = chainXDirect_S390; break; - case VexArchPPC32: -- return chainXDirect_PPC(place_to_chain, -+ return chainXDirect_PPC(endness_host, -+ place_to_chain, - disp_cp_chain_me_EXPECTED, - place_to_jump_to, False/*!mode64*/); - case VexArchPPC64: -- return chainXDirect_PPC(place_to_chain, -+ return chainXDirect_PPC(endness_host, -+ place_to_chain, - disp_cp_chain_me_EXPECTED, - place_to_jump_to, True/*mode64*/); - case VexArchMIPS32: -- return chainXDirect_MIPS(place_to_chain, -+ return chainXDirect_MIPS(endness_host, -+ place_to_chain, - disp_cp_chain_me_EXPECTED, - place_to_jump_to, False/*!mode64*/); - case VexArchMIPS64: -- return chainXDirect_MIPS(place_to_chain, -+ return chainXDirect_MIPS(endness_host, -+ place_to_chain, - disp_cp_chain_me_EXPECTED, - place_to_jump_to, True/*!mode64*/); - default: -@@ -1030,17 +1043,18 @@ VexInvalRange LibVEX_Chain ( VexArch arc - } - vassert(chainXDirect); - VexInvalRange vir -- = chainXDirect(place_to_chain, disp_cp_chain_me_EXPECTED, -- place_to_jump_to); -+ = chainXDirect(endness_host, place_to_chain, -+ disp_cp_chain_me_EXPECTED, place_to_jump_to); - return vir; - } - --VexInvalRange LibVEX_UnChain ( VexArch arch_host, -- void* place_to_unchain, -- void* place_to_jump_to_EXPECTED, -- void* disp_cp_chain_me ) -+VexInvalRange LibVEX_UnChain ( VexArch arch_host, -+ VexEndness endness_host, -+ void* place_to_unchain, -+ void* place_to_jump_to_EXPECTED, -+ void* disp_cp_chain_me ) - { -- VexInvalRange (*unchainXDirect)(void*, void*, void*) = NULL; -+ VexInvalRange (*unchainXDirect)(VexEndness, void*, void*, void*) = NULL; - switch (arch_host) { - case VexArchX86: - unchainXDirect = unchainXDirect_X86; break; -@@ -1051,19 +1065,23 @@ VexInvalRange LibVEX_UnChain ( VexArch a - case VexArchS390X: - unchainXDirect = unchainXDirect_S390; break; - case VexArchPPC32: -- return unchainXDirect_PPC(place_to_unchain, -+ return unchainXDirect_PPC(endness_host, -+ place_to_unchain, - place_to_jump_to_EXPECTED, - disp_cp_chain_me, False/*!mode64*/); - case VexArchPPC64: -- return unchainXDirect_PPC(place_to_unchain, -+ return unchainXDirect_PPC(endness_host, -+ place_to_unchain, - place_to_jump_to_EXPECTED, - disp_cp_chain_me, True/*mode64*/); - case VexArchMIPS32: -- return unchainXDirect_MIPS(place_to_unchain, -+ return unchainXDirect_MIPS(endness_host, -+ place_to_unchain, - place_to_jump_to_EXPECTED, - disp_cp_chain_me, False/*!mode64*/); - case VexArchMIPS64: -- return unchainXDirect_MIPS(place_to_unchain, -+ return unchainXDirect_MIPS(endness_host, -+ place_to_unchain, - place_to_jump_to_EXPECTED, - disp_cp_chain_me, True/*!mode64*/); - default: -@@ -1071,32 +1089,32 @@ VexInvalRange LibVEX_UnChain ( VexArch a - } - vassert(unchainXDirect); - VexInvalRange vir -- = unchainXDirect(place_to_unchain, place_to_jump_to_EXPECTED, -- disp_cp_chain_me); -+ = unchainXDirect(endness_host, place_to_unchain, -+ place_to_jump_to_EXPECTED, disp_cp_chain_me); - return vir; - } - --Int LibVEX_evCheckSzB ( VexArch arch_host ) -+Int LibVEX_evCheckSzB ( VexArch arch_host, VexEndness endness_host) - { - static Int cached = 0; /* DO NOT MAKE NON-STATIC */ - if (UNLIKELY(cached == 0)) { - switch (arch_host) { - case VexArchX86: -- cached = evCheckSzB_X86(); break; -+ cached = evCheckSzB_X86(endness_host); break; - case VexArchAMD64: -- cached = evCheckSzB_AMD64(); break; -+ cached = evCheckSzB_AMD64(endness_host); break; - case VexArchARM: -- cached = evCheckSzB_ARM(); break; -+ cached = evCheckSzB_ARM(endness_host); break; - case VexArchARM64: -- cached = evCheckSzB_ARM64(); break; -+ cached = evCheckSzB_ARM64(endness_host); break; - case VexArchS390X: -- cached = evCheckSzB_S390(); break; -+ cached = evCheckSzB_S390(endness_host); break; - case VexArchPPC32: - case VexArchPPC64: -- cached = evCheckSzB_PPC(); break; -+ cached = evCheckSzB_PPC(endness_host); break; - case VexArchMIPS32: - case VexArchMIPS64: -- cached = evCheckSzB_MIPS(); break; -+ cached = evCheckSzB_MIPS(endness_host); break; - default: - vassert(0); - } -@@ -1104,11 +1122,12 @@ Int LibVEX_evCheckSzB ( VexArch arch_hos - return cached; - } - --VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, -- void* place_to_patch, -- ULong* location_of_counter ) -+VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, -+ VexEndness endness_host, -+ void* place_to_patch, -+ ULong* location_of_counter ) - { -- VexInvalRange (*patchProfInc)(void*,ULong*) = NULL; -+ VexInvalRange (*patchProfInc)(VexEndness,void*,ULong*) = NULL; - switch (arch_host) { - case VexArchX86: - patchProfInc = patchProfInc_X86; break; -@@ -1119,23 +1138,23 @@ VexInvalRange LibVEX_PatchProfInc ( VexA - case VexArchS390X: - patchProfInc = patchProfInc_S390; break; - case VexArchPPC32: -- return patchProfInc_PPC(place_to_patch, -+ return patchProfInc_PPC(endness_host, place_to_patch, - location_of_counter, False/*!mode64*/); - case VexArchPPC64: -- return patchProfInc_PPC(place_to_patch, -+ return patchProfInc_PPC(endness_host, place_to_patch, - location_of_counter, True/*mode64*/); - case VexArchMIPS32: -- return patchProfInc_MIPS(place_to_patch, -+ return patchProfInc_MIPS(endness_host, place_to_patch, - location_of_counter, False/*!mode64*/); - case VexArchMIPS64: -- return patchProfInc_MIPS(place_to_patch, -+ return patchProfInc_MIPS(endness_host, place_to_patch, - location_of_counter, True/*!mode64*/); - default: - vassert(0); - } - vassert(patchProfInc); - VexInvalRange vir -- = patchProfInc(place_to_patch, location_of_counter); -+ = patchProfInc(endness_host, place_to_patch, location_of_counter); - return vir; - } - -@@ -1213,6 +1232,16 @@ const HChar* LibVEX_ppVexArch ( VexArch - } - } - -+const HChar* LibVEX_ppVexEndness ( VexEndness endness ) -+{ -+ switch (endness) { -+ case VexEndness_INVALID: return "INVALID"; -+ case VexEndnessLE: return "LittleEndian"; -+ case VexEndnessBE: return "BigEndian"; -+ default: return "VexEndness???"; -+ } -+} -+ - const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) - { - const HChar* str = show_hwcaps(arch,hwcaps); -@@ -1224,6 +1253,7 @@ const HChar* LibVEX_ppVexHwCaps ( VexArc - void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) - { - vai->hwcaps = 0; -+ vai->endness = VexEndness_INVALID; - vai->ppc_icache_line_szB = 0; - vai->ppc_dcbz_szB = 0; - vai->ppc_dcbzl_szB = 0; -Index: VEX/priv/guest_arm_defs.h -=================================================================== ---- VEX/priv/guest_arm_defs.h.orig -+++ VEX/priv/guest_arm_defs.h -@@ -52,7 +52,7 @@ DisResult disInstr_ARM ( IRSB* ir - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian, -+ VexEndness host_endness, - Bool sigill_diag ); - - /* Used by the optimiser to specialise calls to helpers. */ -Index: VEX/priv/host_s390_defs.c -=================================================================== ---- VEX/priv/host_s390_defs.c.orig -+++ VEX/priv/host_s390_defs.c -@@ -9828,7 +9828,8 @@ s390_insn_xassisted_emit(UChar *buf, con - - The dispatch counter is a 32-bit value. */ - static UChar * --s390_insn_evcheck_emit(UChar *buf, const s390_insn *insn) -+s390_insn_evcheck_emit(UChar *buf, const s390_insn *insn, -+ VexEndness endness_host) - { - s390_amode *amode; - UInt b, d; -@@ -9864,7 +9865,7 @@ s390_insn_evcheck_emit(UChar *buf, const - - /* Make sure the size of the generated code is identical to the size - returned by evCheckSzB_S390 */ -- vassert(evCheckSzB_S390() == code_end - code_begin); -+ vassert(evCheckSzB_S390(endness_host) == code_end - code_begin); - - return buf; - } -@@ -9893,7 +9894,8 @@ s390_insn_profinc_emit(UChar *buf, - - Int - emit_S390Instr(Bool *is_profinc, UChar *buf, Int nbuf, s390_insn *insn, -- Bool mode64, void *disp_cp_chain_me_to_slowEP, -+ Bool mode64, VexEndness endness_host, -+ void *disp_cp_chain_me_to_slowEP, - void *disp_cp_chain_me_to_fastEP, void *disp_cp_xindir, - void *disp_cp_xassisted) - { -@@ -10054,7 +10056,7 @@ emit_S390Instr(Bool *is_profinc, UChar * - break; - - case S390_INSN_EVCHECK: -- end = s390_insn_evcheck_emit(buf, insn); -+ end = s390_insn_evcheck_emit(buf, insn, endness_host); - break; - - case S390_INSN_XDIRECT: -@@ -10084,7 +10086,7 @@ emit_S390Instr(Bool *is_profinc, UChar * - /* Return the number of bytes emitted for an S390_INSN_EVCHECK. - See s390_insn_evcheck_emit */ - Int --evCheckSzB_S390(void) -+evCheckSzB_S390(VexEndness endness_host) - { - return s390_host_has_gie ? 18 : 24; - } -@@ -10093,7 +10095,8 @@ evCheckSzB_S390(void) - /* Patch the counter address into CODE_TO_PATCH as previously - generated by s390_insn_profinc_emit. */ - VexInvalRange --patchProfInc_S390(void *code_to_patch, ULong *location_of_counter) -+patchProfInc_S390(VexEndness endness_host, -+ void *code_to_patch, ULong *location_of_counter) - { - vassert(sizeof(ULong *) == 8); - -@@ -10111,10 +10114,13 @@ patchProfInc_S390(void *code_to_patch, U - /* NB: what goes on here has to be very closely coordinated with the - s390_insn_xdirect_emit code above. */ - VexInvalRange --chainXDirect_S390(void *place_to_chain, -+chainXDirect_S390(VexEndness endness_host, -+ void *place_to_chain, - void *disp_cp_chain_me_EXPECTED, - void *place_to_jump_to) - { -+ vassert(endness_host == VexEndnessBE); -+ - /* What we're expecting to see @ PLACE_TO_CHAIN is: - - load tchain_scratch, #disp_cp_chain_me_EXPECTED -@@ -10196,10 +10202,13 @@ chainXDirect_S390(void *place_to_chain, - /* NB: what goes on here has to be very closely coordinated with the - s390_insn_xdirect_emit code above. */ - VexInvalRange --unchainXDirect_S390(void *place_to_unchain, -+unchainXDirect_S390(VexEndness endness_host, -+ void *place_to_unchain, - void *place_to_jump_to_EXPECTED, - void *disp_cp_chain_me) - { -+ vassert(endness_host == VexEndnessBE); -+ - /* What we're expecting to see @ PLACE_TO_UNCHAIN: - - load tchain_scratch, #place_to_jump_to_EXPECTED -Index: VEX/priv/host_s390_defs.h -=================================================================== ---- VEX/priv/host_s390_defs.h.orig -+++ VEX/priv/host_s390_defs.h -@@ -736,7 +736,7 @@ void getRegUsage_S390Instr( HRegUsage * - void mapRegs_S390Instr ( HRegRemap *, s390_insn *, Bool ); - Bool isMove_S390Instr ( s390_insn *, HReg *, HReg * ); - Int emit_S390Instr ( Bool *, UChar *, Int, s390_insn *, Bool, -- void *, void *, void *, void *); -+ VexEndness, void *, void *, void *, void *); - void getAllocableRegs_S390( Int *, HReg **, Bool ); - void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool ); - void genReload_S390 ( HInstr **, HInstr **, HReg , Int , Bool ); -@@ -745,19 +745,22 @@ HInstrArray *iselSB_S390 ( IRSB *, Vex - Int, Int, Bool, Bool, Addr64); - - /* Return the number of bytes of code needed for an event check */ --Int evCheckSzB_S390(void); -+Int evCheckSzB_S390(VexEndness endness_host); - - /* Perform a chaining and unchaining of an XDirect jump. */ --VexInvalRange chainXDirect_S390(void *place_to_chain, -+VexInvalRange chainXDirect_S390(VexEndness endness_host, -+ void *place_to_chain, - void *disp_cp_chain_me_EXPECTED, - void *place_to_jump_to); - --VexInvalRange unchainXDirect_S390(void *place_to_unchain, -+VexInvalRange unchainXDirect_S390(VexEndness endness_host, -+ void *place_to_unchain, - void *place_to_jump_to_EXPECTED, - void *disp_cp_chain_me); - - /* Patch the counter location into an existing ProfInc point. */ --VexInvalRange patchProfInc_S390(void *code_to_patch, -+VexInvalRange patchProfInc_S390(VexEndness endness_host, -+ void *code_to_patch, - ULong *location_of_counter); - - /* KLUDGE: See detailled comment in host_s390_defs.c. */ -Index: VEX/priv/host_s390_isel.c -=================================================================== ---- VEX/priv/host_s390_isel.c.orig -+++ VEX/priv/host_s390_isel.c -@@ -4079,6 +4079,9 @@ iselSB_S390(IRSB *bb, VexArch arch_host, - /* Do some sanity checks */ - vassert((VEX_HWCAPS_S390X(hwcaps_host) & ~(VEX_HWCAPS_S390X_ALL)) == 0); - -+ /* Check that the host's endianness is as expected. */ -+ vassert(archinfo_host->endness == VexEndnessBE); -+ - /* Make up an initial environment to use. */ - env = LibVEX_Alloc(sizeof(ISelEnv)); - env->vreg_ctr = 0; -Index: VEX/priv/guest_s390_defs.h -=================================================================== ---- VEX/priv/guest_s390_defs.h.orig -+++ VEX/priv/guest_s390_defs.h -@@ -50,7 +50,7 @@ DisResult disInstr_S390 ( IRSB* i - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian, -+ VexEndness host_endness, - Bool sigill_diag ); - - /* Used by the optimiser to specialise calls to helpers. */ -Index: VEX/priv/host_mips_defs.h -=================================================================== ---- VEX/priv/host_mips_defs.h.orig -+++ VEX/priv/host_mips_defs.h -@@ -702,6 +702,7 @@ extern Bool isMove_MIPSInstr - extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, MIPSInstr* i, - Bool mode64, -+ VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -728,25 +729,28 @@ extern HInstrArray *iselSB_MIPS - and so assumes that they are both <= 128, and so can use the short - offset encoding. This is all checked with assertions, so in the - worst case we will merely assert at startup. */ --extern Int evCheckSzB_MIPS ( void ); -+extern Int evCheckSzB_MIPS ( VexEndness endness_host ); - - /* Perform a chaining and unchaining of an XDirect jump. */ --extern VexInvalRange chainXDirect_MIPS ( void* place_to_chain, -+extern VexInvalRange chainXDirect_MIPS ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to, - Bool mode64 ); - --extern VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain, -+extern VexInvalRange unchainXDirect_MIPS ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me, - Bool mode64 ); - - /* Patch the counter location into an existing ProfInc point. */ --extern VexInvalRange patchProfInc_MIPS ( void* place_to_patch, -+extern VexInvalRange patchProfInc_MIPS ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter, - Bool mode64 ); - --#endif /* ndef __LIBVEX_HOST_MIPS_HDEFS_H */ -+#endif /* ndef __VEX_HOST_MIPS_DEFS_H */ - - /*---------------------------------------------------------------*/ - /*--- end host-mips_defs.h ---*/ -Index: VEX/priv/host_x86_defs.c -=================================================================== ---- VEX/priv/host_x86_defs.c.orig -+++ VEX/priv/host_x86_defs.c -@@ -2088,7 +2088,7 @@ static UChar* push_word_from_tags ( UCha - - Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, X86Instr* i, -- Bool mode64, -+ Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -3277,7 +3277,7 @@ Int emit_X86Instr ( /*MB_MOD*/Bool* is_p - p = doAMode_M(p, fake(4), i->Xin.EvCheck.amFailAddr); - vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */ - /* And crosscheck .. */ -- vassert(evCheckSzB_X86() == 8); -+ vassert(evCheckSzB_X86(endness_host) == 8); - goto done; - } - -@@ -3322,7 +3322,7 @@ Int emit_X86Instr ( /*MB_MOD*/Bool* is_p - /* How big is an event check? See case for Xin_EvCheck in - emit_X86Instr just above. That crosschecks what this returns, so - we can tell if we're inconsistent. */ --Int evCheckSzB_X86 ( void ) -+Int evCheckSzB_X86 ( VexEndness endness_host ) - { - return 8; - } -@@ -3330,10 +3330,13 @@ Int evCheckSzB_X86 ( void ) - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange chainXDirect_X86 ( void* place_to_chain, -+VexInvalRange chainXDirect_X86 ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ) - { -+ vassert(endness_host == VexEndnessLE); -+ - /* What we're expecting to see is: - movl $disp_cp_chain_me_EXPECTED, %edx - call *%edx -@@ -3375,10 +3378,13 @@ VexInvalRange chainXDirect_X86 ( void* p - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange unchainXDirect_X86 ( void* place_to_unchain, -+VexInvalRange unchainXDirect_X86 ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me ) - { -+ vassert(endness_host == VexEndnessLE); -+ - /* What we're expecting to see is: - jmp d32 - ud2; -@@ -3418,9 +3424,11 @@ VexInvalRange unchainXDirect_X86 ( void* - - /* Patch the counter address into a profile inc point, as previously - created by the Xin_ProfInc case for emit_X86Instr. */ --VexInvalRange patchProfInc_X86 ( void* place_to_patch, -+VexInvalRange patchProfInc_X86 ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter ) - { -+ vassert(endness_host == VexEndnessLE); - vassert(sizeof(ULong*) == 4); - UChar* p = (UChar*)place_to_patch; - vassert(p[0] == 0x83); -Index: VEX/priv/guest_mips_defs.h -=================================================================== ---- VEX/priv/guest_mips_defs.h.orig -+++ VEX/priv/guest_mips_defs.h -@@ -51,7 +51,7 @@ extern DisResult disInstr_MIPS ( IRSB* - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian, -+ VexEndness host_endness, - Bool sigill_diag ); - - /* Used by the optimiser to specialise calls to helpers. */ -Index: VEX/priv/host_x86_defs.h -=================================================================== ---- VEX/priv/host_x86_defs.h.orig -+++ VEX/priv/host_x86_defs.h -@@ -717,6 +717,7 @@ extern Bool isMove_X86Instr - extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, X86Instr* i, - Bool mode64, -+ VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -745,19 +746,22 @@ extern HInstrArray* iselSB_X86 - and so assumes that they are both <= 128, and so can use the short - offset encoding. This is all checked with assertions, so in the - worst case we will merely assert at startup. */ --extern Int evCheckSzB_X86 ( void ); -+extern Int evCheckSzB_X86 ( VexEndness endness_host ); - - /* Perform a chaining and unchaining of an XDirect jump. */ --extern VexInvalRange chainXDirect_X86 ( void* place_to_chain, -+extern VexInvalRange chainXDirect_X86 ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ); - --extern VexInvalRange unchainXDirect_X86 ( void* place_to_unchain, -+extern VexInvalRange unchainXDirect_X86 ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me ); - - /* Patch the counter location into an existing ProfInc point. */ --extern VexInvalRange patchProfInc_X86 ( void* place_to_patch, -+extern VexInvalRange patchProfInc_X86 ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter ); - - -Index: VEX/priv/guest_x86_toIR.c -=================================================================== ---- VEX/priv/guest_x86_toIR.c.orig -+++ VEX/priv/guest_x86_toIR.c -@@ -199,7 +199,7 @@ - given insn. */ - - /* We need to know this to do sub-register accesses correctly. */ --static Bool host_is_bigendian; -+static VexEndness host_endness; - - /* Pointer to the guest code area (points to start of BB, not to the - insn being processed). */ -@@ -456,7 +456,7 @@ static Int integerGuestRegOffset ( Int s - vassert(archreg < 8); - - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - - if (sz == 4 || sz == 2 || (sz == 1 && archreg < 4)) { - switch (archreg) { -@@ -519,7 +519,7 @@ static Int xmmGuestRegOffset ( UInt xmmr - static Int xmmGuestRegLane16offset ( UInt xmmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 8); - return xmmGuestRegOffset( xmmreg ) + 2 * laneno; - } -@@ -527,7 +527,7 @@ static Int xmmGuestRegLane16offset ( UIn - static Int xmmGuestRegLane32offset ( UInt xmmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 4); - return xmmGuestRegOffset( xmmreg ) + 4 * laneno; - } -@@ -535,7 +535,7 @@ static Int xmmGuestRegLane32offset ( UIn - static Int xmmGuestRegLane64offset ( UInt xmmreg, Int laneno ) - { - /* Correct for little-endian host only. */ -- vassert(!host_is_bigendian); -+ vassert(host_endness == VexEndnessLE); - vassert(laneno >= 0 && laneno < 2); - return xmmGuestRegOffset( xmmreg ) + 8 * laneno; - } -@@ -15264,7 +15264,7 @@ DisResult disInstr_X86 ( IRSB* ir - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian_IN, -+ VexEndness host_endness_IN, - Bool sigill_diag_IN ) - { - Int i, x1, x2; -@@ -15275,7 +15275,7 @@ DisResult disInstr_X86 ( IRSB* ir - vassert(guest_arch == VexArchX86); - guest_code = guest_code_IN; - irsb = irsb_IN; -- host_is_bigendian = host_bigendian_IN; -+ host_endness = host_endness_IN; - guest_EIP_curr_instr = (Addr32)guest_IP; - guest_EIP_bbstart = (Addr32)toUInt(guest_IP - delta); - -Index: VEX/pub/libvex.h -=================================================================== ---- VEX/pub/libvex.h.orig -+++ VEX/pub/libvex.h -@@ -51,7 +51,7 @@ - - typedef - enum { -- VexArch_INVALID, -+ VexArch_INVALID=0x400, - VexArchX86, - VexArchAMD64, - VexArchARM, -@@ -65,6 +65,16 @@ typedef - VexArch; - - -+/* Information about endianness. */ -+typedef -+ enum { -+ VexEndness_INVALID=0x600, /* unknown endianness */ -+ VexEndnessLE, /* little endian */ -+ VexEndnessBE /* big endian */ -+ } -+ VexEndness; -+ -+ - /* For a given architecture, these specify extra capabilities beyond - the minimum supported (baseline) capabilities. They may be OR'd - together, although some combinations don't make sense. (eg, SSE2 -@@ -215,12 +225,13 @@ typedef - /* These return statically allocated strings. */ - - extern const HChar* LibVEX_ppVexArch ( VexArch ); -+extern const HChar* LibVEX_ppVexEndness ( VexEndness endness ); - extern const HChar* LibVEX_ppVexHwCaps ( VexArch, UInt ); - - - /* The various kinds of caches */ - typedef enum { -- DATA_CACHE, -+ DATA_CACHE=0x500, - INSN_CACHE, - UNIFIED_CACHE - } VexCacheKind; -@@ -265,8 +276,9 @@ typedef struct { - - typedef - struct { -- /* The following two fields are mandatory. */ -- UInt hwcaps; -+ /* The following three fields are mandatory. */ -+ UInt hwcaps; -+ VexEndness endness; - VexCacheInfo hwcache_info; - /* PPC32/PPC64 only: size of instruction cache line */ - Int ppc_icache_line_szB; -@@ -379,7 +391,7 @@ void LibVEX_default_VexAbiInfo ( /*OUT*/ - points. - - VexRegUpdAllregsAtEachInsn : all registers up to date at each instruction. */ --typedef enum { VexRegUpdSpAtMemAccess, -+typedef enum { VexRegUpdSpAtMemAccess=0x700, - VexRegUpdUnwindregsAtMemAccess, - VexRegUpdAllregsAtMemAccess, - VexRegUpdAllregsAtEachInsn } VexRegisterUpdates; -@@ -573,7 +585,7 @@ extern void LibVEX_Init ( - typedef - struct { - /* overall status */ -- enum { VexTransOK, -+ enum { VexTransOK=0x800, - VexTransAccessFail, VexTransOutputFull } status; - /* The number of extents that have a self-check (0 to 3) */ - UInt n_sc_extents; -@@ -768,35 +780,39 @@ typedef - currently contains a call to the dispatcher specified by - disp_cp_chain_me_EXPECTED. */ - extern --VexInvalRange LibVEX_Chain ( VexArch arch_host, -- void* place_to_chain, -- void* disp_cp_chain_me_EXPECTED, -- void* place_to_jump_to ); -+VexInvalRange LibVEX_Chain ( VexArch arch_host, -+ VexEndness endhess_host, -+ void* place_to_chain, -+ void* disp_cp_chain_me_EXPECTED, -+ void* place_to_jump_to ); - - /* Undo an XDirect jump located at place_to_unchain, so it is - converted back into a call to disp_cp_chain_me. It is expected - (and checked) that this site currently contains a jump directly to - the address specified by place_to_jump_to_EXPECTED. */ - extern --VexInvalRange LibVEX_UnChain ( VexArch arch_host, -- void* place_to_unchain, -- void* place_to_jump_to_EXPECTED, -- void* disp_cp_chain_me ); -+VexInvalRange LibVEX_UnChain ( VexArch arch_host, -+ VexEndness endness_host, -+ void* place_to_unchain, -+ void* place_to_jump_to_EXPECTED, -+ void* disp_cp_chain_me ); - - /* Returns a constant -- the size of the event check that is put at - the start of every translation. This makes it possible to - calculate the fast entry point address if the slow entry point - address is known (the usual case), or vice versa. */ - extern --Int LibVEX_evCheckSzB ( VexArch arch_host ); -+Int LibVEX_evCheckSzB ( VexArch arch_host, -+ VexEndness endness_host ); - - - /* Patch the counter location into an existing ProfInc point. The - specified point is checked to make sure it is plausible. */ - extern --VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, -- void* place_to_patch, -- ULong* location_of_counter ); -+VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, -+ VexEndness endness_host, -+ void* place_to_patch, -+ ULong* location_of_counter ); - - - /*-------------------------------------------------------*/ -Index: VEX/priv/host_arm64_defs.c -=================================================================== ---- VEX/priv/host_arm64_defs.c.orig -+++ VEX/priv/host_arm64_defs.c -@@ -3702,7 +3702,7 @@ static UInt* do_load_or_store64 ( UInt* - - Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, ARM64Instr* i, -- Bool mode64, -+ Bool mode64, VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -5718,7 +5718,7 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is - /* nofail: */ - - /* Crosscheck */ -- vassert(evCheckSzB_ARM64() == (UChar*)p - (UChar*)p0); -+ vassert(evCheckSzB_ARM64(endness_host) == (UChar*)p - (UChar*)p0); - goto done; - } - -@@ -5769,7 +5769,7 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is - /* How big is an event check? See case for ARM64in_EvCheck in - emit_ARM64Instr just above. That crosschecks what this returns, so - we can tell if we're inconsistent. */ --Int evCheckSzB_ARM64 ( void ) -+Int evCheckSzB_ARM64 ( VexEndness endness_host ) - { - return 24; - } -@@ -5777,10 +5777,13 @@ Int evCheckSzB_ARM64 ( void ) - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange chainXDirect_ARM64 ( void* place_to_chain, -+VexInvalRange chainXDirect_ARM64 ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ) - { -+ vassert(endness_host == VexEndnessLE); -+ - /* What we're expecting to see is: - movw x9, disp_cp_chain_me_to_EXPECTED[15:0] - movk x9, disp_cp_chain_me_to_EXPECTED[31:15], lsl 16 -@@ -5881,7 +5884,8 @@ VexInvalRange chainXDirect_ARM64 ( void* - //ZZ - //ZZ /* Patch the counter address into a profile inc point, as previously - //ZZ created by the ARMin_ProfInc case for emit_ARMInstr. */ --//ZZ VexInvalRange patchProfInc_ARM ( void* place_to_patch, -+//ZZ VexInvalRange patchProfInc_ARM ( VexEndness endness_host, -+//ZZ void* place_to_patch, - //ZZ ULong* location_of_counter ) - //ZZ { - //ZZ vassert(sizeof(ULong*) == 4); -Index: VEX/priv/host_arm64_defs.h -=================================================================== ---- VEX/priv/host_arm64_defs.h.orig -+++ VEX/priv/host_arm64_defs.h -@@ -989,6 +989,7 @@ extern Bool isMove_ARM64Instr ( ARM - extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, ARM64Instr* i, - Bool mode64, -+ VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -1013,10 +1014,11 @@ extern HInstrArray* iselSB_ARM64 ( IRSB* - /* How big is an event check? This is kind of a kludge because it - depends on the offsets of host_EvC_FAILADDR and - host_EvC_COUNTER. */ --extern Int evCheckSzB_ARM64 ( void ); -+extern Int evCheckSzB_ARM64 ( VexEndness endness_host ); - - /* Perform a chaining and unchaining of an XDirect jump. */ --extern VexInvalRange chainXDirect_ARM64 ( void* place_to_chain, -+extern VexInvalRange chainXDirect_ARM64 ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to ); - ---- VEX/priv/guest_x86_defs.h (Revision 2909) -+++ VEX/priv/guest_x86_defs.h (Revision 2910) -@@ -60,7 +60,7 @@ DisResult disInstr_X86 ( IRSB* ir - VexArch guest_arch, - VexArchInfo* archinfo, - VexAbiInfo* abiinfo, -- Bool host_bigendian, -+ VexEndness host_endness, - Bool sigill_diag ); - - /* Used by the optimiser to specialise calls to helpers. */ ---- VEX/priv/host_mips_defs.c (Revision 2909) -+++ VEX/priv/host_mips_defs.c (Revision 2910) -@@ -2920,6 +2920,7 @@ static UChar *mkMoveReg(UChar * p, UInt - Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc, - UChar* buf, Int nbuf, MIPSInstr* i, - Bool mode64, -+ VexEndness endness_host, - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -@@ -4229,7 +4230,7 @@ Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_ - /* nofail: */ - - /* Crosscheck */ -- vassert(evCheckSzB_MIPS() == (UChar*)p - (UChar*)p0); -+ vassert(evCheckSzB_MIPS(endness_host) == (UChar*)p - (UChar*)p0); - goto done; - } - -@@ -4315,7 +4316,7 @@ Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_ - /* How big is an event check? See case for Min_EvCheck in - emit_MIPSInstr just above. That crosschecks what this returns, so - we can tell if we're inconsistent. */ --Int evCheckSzB_MIPS ( void ) -+Int evCheckSzB_MIPS ( VexEndness endness_host ) - { - UInt kInstrSize = 4; - return 7*kInstrSize; -@@ -4323,11 +4324,13 @@ Int evCheckSzB_MIPS ( void ) - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange chainXDirect_MIPS ( void* place_to_chain, -+VexInvalRange chainXDirect_MIPS ( VexEndness endness_host, -+ void* place_to_chain, - void* disp_cp_chain_me_EXPECTED, - void* place_to_jump_to, - Bool mode64 ) - { -+ vassert(endness_host == VexEndnessLE || endness_host == VexEndnessBE); - /* What we're expecting to see is: - move r9, disp_cp_chain_me_to_EXPECTED - jalr r9 -@@ -4369,11 +4372,13 @@ VexInvalRange chainXDirect_MIPS ( void* - - /* NB: what goes on here has to be very closely coordinated with the - emitInstr case for XDirect, above. */ --VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain, -+VexInvalRange unchainXDirect_MIPS ( VexEndness endness_host, -+ void* place_to_unchain, - void* place_to_jump_to_EXPECTED, - void* disp_cp_chain_me, - Bool mode64 ) - { -+ vassert(endness_host == VexEndnessLE || endness_host == VexEndnessBE); - /* What we're expecting to see is: - move r9, place_to_jump_to_EXPECTED - jalr r9 -@@ -4413,13 +4418,16 @@ VexInvalRange unchainXDirect_MIPS ( void - - /* Patch the counter address into a profile inc point, as previously - created by the Min_ProfInc case for emit_MIPSInstr. */ --VexInvalRange patchProfInc_MIPS ( void* place_to_patch, -+VexInvalRange patchProfInc_MIPS ( VexEndness endness_host, -+ void* place_to_patch, - ULong* location_of_counter, Bool mode64 ) - { -- if (mode64) -+ vassert(endness_host == VexEndnessLE || endness_host == VexEndnessBE); -+ if (mode64) { - vassert(sizeof(ULong*) == 8); -- else -+ } else { - vassert(sizeof(ULong*) == 4); -+ } - UChar* p = (UChar*)place_to_patch; - vassert(0 == (3 & (HWord)p)); - vassert(isLoadImm_EXACTLY2or6((UChar *)p, /*r*/9, diff --git a/VEX-r2914.diff b/VEX-r2914.diff deleted file mode 100644 index ed85a80..0000000 --- a/VEX-r2914.diff +++ /dev/null @@ -1,7306 +0,0 @@ -Index: VEX/priv/host_ppc_defs.c -=================================================================== ---- VEX/priv/host_ppc_defs.c.orig -+++ VEX/priv/host_ppc_defs.c -@@ -3115,24 +3115,38 @@ static UInt vregNo ( HReg v ) - return n; - } - --/* Emit an instruction big-endianly */ --static UChar* emit32 ( UChar* p, UInt w32 ) -+/* Emit an instruction ppc-endianly */ -+static UChar* emit32 ( UChar* p, UInt w32, VexEndness endness_host ) - { -- *p++ = toUChar((w32 >> 24) & 0x000000FF); -- *p++ = toUChar((w32 >> 16) & 0x000000FF); -- *p++ = toUChar((w32 >> 8) & 0x000000FF); -- *p++ = toUChar((w32) & 0x000000FF); -+ if (endness_host == VexEndnessBE) { -+ *p++ = toUChar((w32 >> 24) & 0x000000FF); -+ *p++ = toUChar((w32 >> 16) & 0x000000FF); -+ *p++ = toUChar((w32 >> 8) & 0x000000FF); -+ *p++ = toUChar((w32) & 0x000000FF); -+ } else { -+ *p++ = toUChar((w32) & 0x000000FF); -+ *p++ = toUChar((w32 >> 8) & 0x000000FF); -+ *p++ = toUChar((w32 >> 16) & 0x000000FF); -+ *p++ = toUChar((w32 >> 24) & 0x000000FF); -+ } - return p; - } - --/* Fetch an instruction big-endianly */ --static UInt fetch32 ( UChar* p ) -+/* Fetch an instruction ppc-endianly */ -+static UInt fetch32 ( UChar* p, VexEndness endness_host ) - { - UInt w32 = 0; -- w32 |= ((0xFF & (UInt)p[0]) << 24); -- w32 |= ((0xFF & (UInt)p[1]) << 16); -- w32 |= ((0xFF & (UInt)p[2]) << 8); -- w32 |= ((0xFF & (UInt)p[3]) << 0); -+ if (endness_host == VexEndnessBE) { -+ w32 |= ((0xFF & (UInt)p[0]) << 24); -+ w32 |= ((0xFF & (UInt)p[1]) << 16); -+ w32 |= ((0xFF & (UInt)p[2]) << 8); -+ w32 |= ((0xFF & (UInt)p[3]) << 0); -+ } else { -+ w32 |= ((0xFF & (UInt)p[3]) << 24); -+ w32 |= ((0xFF & (UInt)p[2]) << 16); -+ w32 |= ((0xFF & (UInt)p[1]) << 8); -+ w32 |= ((0xFF & (UInt)p[0]) << 0); -+ } - return w32; - } - -@@ -3141,7 +3155,7 @@ static UInt fetch32 ( UChar* p ) - */ - - static UChar* mkFormD ( UChar* p, UInt opc1, -- UInt r1, UInt r2, UInt imm ) -+ UInt r1, UInt r2, UInt imm, VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3149,11 +3163,12 @@ static UChar* mkFormD ( UChar* p, UInt o - vassert(r2 < 0x20); - imm = imm & 0xFFFF; - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (imm)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormMD ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt imm1, UInt imm2, UInt opc2 ) -+ UInt imm1, UInt imm2, UInt opc2, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3166,11 +3181,11 @@ static UChar* mkFormMD ( UChar* p, UInt - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - ((imm1 & 0x1F)<<11) | (imm2<<5) | - (opc2<<2) | ((imm1 >> 5)<<1)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormX ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt r3, UInt opc2, UInt b0 ) -+ UInt r3, UInt opc2, UInt b0, VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3181,11 +3196,12 @@ static UChar* mkFormX ( UChar* p, UInt o - vassert(b0 < 0x2); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - (r3<<11) | (opc2<<1) | (b0)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormXO ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt r3, UInt b10, UInt opc2, UInt b0 ) -+ UInt r3, UInt b10, UInt opc2, UInt b0, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3197,11 +3213,11 @@ static UChar* mkFormXO ( UChar* p, UInt - vassert(b0 < 0x2); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - (r3<<11) | (b10 << 10) | (opc2<<1) | (b0)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormXL ( UChar* p, UInt opc1, UInt f1, UInt f2, -- UInt f3, UInt opc2, UInt b0 ) -+ UInt f3, UInt opc2, UInt b0, VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3212,11 +3228,12 @@ static UChar* mkFormXL ( UChar* p, UInt - vassert(b0 < 0x2); - theInstr = ((opc1<<26) | (f1<<21) | (f2<<16) | - (f3<<11) | (opc2<<1) | (b0)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - // Note: for split field ops, give mnemonic arg --static UChar* mkFormXFX ( UChar* p, UInt r1, UInt f2, UInt opc2 ) -+static UChar* mkFormXFX ( UChar* p, UInt r1, UInt f2, UInt opc2, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(r1 < 0x20); -@@ -3237,21 +3254,23 @@ static UChar* mkFormXFX ( UChar* p, UInt - default: vpanic("mkFormXFX(ppch)"); - } - theInstr = ((31<<26) | (r1<<21) | (f2<<11) | (opc2<<1)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - // Only used by mtfsf --static UChar* mkFormXFL ( UChar* p, UInt FM, UInt freg, UInt dfp_rm ) -+static UChar* mkFormXFL ( UChar* p, UInt FM, UInt freg, UInt dfp_rm, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(FM < 0x100); - vassert(freg < 0x20); - theInstr = ((63<<26) | (FM<<17) | (dfp_rm<<16) | (freg<<11) | (711<<1)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormXS ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt imm, UInt opc2, UInt b0 ) -+ UInt imm, UInt opc2, UInt b0, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3262,26 +3281,27 @@ static UChar* mkFormXS ( UChar* p, UInt - vassert(b0 < 0x2); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - ((imm & 0x1F)<<11) | (opc2<<2) | ((imm>>5)<<1) | (b0)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - - #if 0 - // 'b' --static UChar* mkFormI ( UChar* p, UInt LI, UInt AA, UInt LK ) -+static UChar* mkFormI ( UChar* p, UInt LI, UInt AA, UInt LK, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(LI < 0x1000000); - vassert(AA < 0x2); - vassert(LK < 0x2); - theInstr = ((18<<26) | (LI<<2) | (AA<<1) | (LK)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - #endif - - // 'bc' - static UChar* mkFormB ( UChar* p, UInt BO, UInt BI, -- UInt BD, UInt AA, UInt LK ) -+ UInt BD, UInt AA, UInt LK, VexEndness endness_host ) - { - UInt theInstr; - vassert(BO < 0x20); -@@ -3291,12 +3311,13 @@ static UChar* mkFormB ( UChar* p, UInt B - vassert(LK < 0x2); - theInstr = ((16<<26) | (BO<<21) | (BI<<16) | - (BD<<2) | (AA<<1) | (LK)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - // rotates - static UChar* mkFormM ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt f3, UInt MB, UInt ME, UInt Rc ) -+ UInt f3, UInt MB, UInt ME, UInt Rc, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3308,11 +3329,12 @@ static UChar* mkFormM ( UChar* p, UInt o - vassert(Rc < 0x2); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - (f3<<11) | (MB<<6) | (ME<<1) | (Rc)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormA ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt r3, UInt r4, UInt opc2, UInt b0 ) -+ UInt r3, UInt r4, UInt opc2, UInt b0, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3324,11 +3346,12 @@ static UChar* mkFormA ( UChar* p, UInt o - vassert(b0 < 0x2 ); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | - (r4<<6) | (opc2<<1) | (b0)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormZ22 ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt constant, UInt opc2, UInt b0 ) -+ UInt constant, UInt opc2, UInt b0, -+ VexEndness endness_host) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3339,11 +3362,12 @@ static UChar* mkFormZ22 ( UChar* p, UInt - vassert(b0 < 0x2); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - (constant<<10) | (opc2<<1) | (b0)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormZ23 ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt r3, UInt rmc, UInt opc2, UInt b0 ) -+ UInt r3, UInt rmc, UInt opc2, UInt b0, -+ VexEndness endness_host) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3355,11 +3379,11 @@ static UChar* mkFormZ23 ( UChar* p, UInt - vassert(b0 < 0x2); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - (r3<<11) | (rmc<<9) | (opc2<<1) | (b0)); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* doAMode_IR ( UChar* p, UInt opc1, UInt rSD, -- PPCAMode* am, Bool mode64 ) -+ PPCAMode* am, Bool mode64, VexEndness endness_host ) - { - UInt rA, idx; - vassert(am->tag == Pam_IR); -@@ -3374,12 +3398,13 @@ static UChar* doAMode_IR ( UChar* p, UIn - should be guaranteed to us by iselWordExpr_AMode. */ - vassert(0 == (idx & 3)); - } -- p = mkFormD(p, opc1, rSD, rA, idx); -+ p = mkFormD(p, opc1, rSD, rA, idx, endness_host); - return p; - } - - static UChar* doAMode_RR ( UChar* p, UInt opc1, UInt opc2, -- UInt rSD, PPCAMode* am, Bool mode64 ) -+ UInt rSD, PPCAMode* am, Bool mode64, -+ VexEndness endness_host ) - { - UInt rA, rB; - vassert(am->tag == Pam_RR); -@@ -3387,13 +3412,14 @@ static UChar* doAMode_RR ( UChar* p, UIn - rA = iregNo(am->Pam.RR.base, mode64); - rB = iregNo(am->Pam.RR.index, mode64); - -- p = mkFormX(p, opc1, rSD, rA, rB, opc2, 0); -+ p = mkFormX(p, opc1, rSD, rA, rB, opc2, 0, endness_host); - return p; - } - - - /* Load imm to r_dst */ --static UChar* mkLoadImm ( UChar* p, UInt r_dst, ULong imm, Bool mode64 ) -+static UChar* mkLoadImm ( UChar* p, UInt r_dst, ULong imm, Bool mode64, -+ VexEndness endness_host ) - { - vassert(r_dst < 0x20); - -@@ -3411,15 +3437,15 @@ static UChar* mkLoadImm ( UChar* p, UInt - // sign-extendable from 16 bits - - // addi r_dst,0,imm => li r_dst,imm -- p = mkFormD(p, 14, r_dst, 0, imm & 0xFFFF); -+ p = mkFormD(p, 14, r_dst, 0, imm & 0xFFFF, endness_host); - } else { - if (imm >= 0xFFFFFFFF80000000ULL || imm < 0x80000000ULL) { - // sign-extendable from 32 bits - - // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16) -- p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF); -+ p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF, endness_host); - // ori r_dst, r_dst, (imm & 0xFFFF) -- p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); - } else { - // full 64bit immediate load: 5 (five!) insns. - vassert(mode64); -@@ -3427,24 +3453,24 @@ static UChar* mkLoadImm ( UChar* p, UInt - // load high word - - // lis r_dst, (imm>>48) & 0xFFFF -- p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF); -+ p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF, endness_host); - - // ori r_dst, r_dst, (imm>>32) & 0xFFFF - if ((imm>>32) & 0xFFFF) -- p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF, endness_host); - - // shift r_dst low word to high word => rldicr -- p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1); -+ p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1, endness_host); - - // load low word - - // oris r_dst, r_dst, (imm>>16) & 0xFFFF - if ((imm>>16) & 0xFFFF) -- p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF); -+ p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF, endness_host); - - // ori r_dst, r_dst, (imm) & 0xFFFF - if (imm & 0xFFFF) -- p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); - } - } - return p; -@@ -3455,7 +3481,8 @@ static UChar* mkLoadImm ( UChar* p, UInt - fewer. This is needed for generating fixed sized patchable - sequences. */ - static UChar* mkLoadImm_EXACTLY2or5 ( UChar* p, -- UInt r_dst, ULong imm, Bool mode64 ) -+ UInt r_dst, ULong imm, Bool mode64, -+ VexEndness endness_host ) - { - vassert(r_dst < 0x20); - -@@ -3470,29 +3497,29 @@ static UChar* mkLoadImm_EXACTLY2or5 ( UC - - if (!mode64) { - // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16) -- p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF); -+ p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF, endness_host); - // ori r_dst, r_dst, (imm & 0xFFFF) -- p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); - - } else { - // full 64bit immediate load: 5 (five!) insns. - - // load high word - // lis r_dst, (imm>>48) & 0xFFFF -- p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF); -+ p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF, endness_host); - - // ori r_dst, r_dst, (imm>>32) & 0xFFFF -- p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF, endness_host); - - // shift r_dst low word to high word => rldicr -- p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1); -+ p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1, endness_host); - - // load low word - // oris r_dst, r_dst, (imm>>16) & 0xFFFF -- p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF); -+ p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF, endness_host); - - // ori r_dst, r_dst, (imm) & 0xFFFF -- p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); - } - return p; - } -@@ -3500,7 +3527,8 @@ static UChar* mkLoadImm_EXACTLY2or5 ( UC - /* Checks whether the sequence of bytes at p was indeed created - by mkLoadImm_EXACTLY2or5 with the given parameters. */ - static Bool isLoadImm_EXACTLY2or5 ( UChar* p_to_check, -- UInt r_dst, ULong imm, Bool mode64 ) -+ UInt r_dst, ULong imm, Bool mode64, -+ VexEndness endness_host ) - { - vassert(r_dst < 0x20); - -@@ -3517,13 +3545,13 @@ static Bool isLoadImm_EXACTLY2or5 ( UCha - UInt expect[2] = { 0, 0 }; - UChar* p = (UChar*)&expect[0]; - // addis r_dst,r0,(imm>>16) => lis r_dst, (imm>>16) -- p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF); -+ p = mkFormD(p, 15, r_dst, 0, (imm>>16) & 0xFFFF, endness_host); - // ori r_dst, r_dst, (imm & 0xFFFF) -- p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); - vassert(p == (UChar*)&expect[2]); - -- return fetch32(p_to_check + 0) == expect[0] -- && fetch32(p_to_check + 4) == expect[1]; -+ return fetch32(p_to_check + 0, endness_host) == expect[0] -+ && fetch32(p_to_check + 4, endness_host) == expect[1]; - - } else { - UInt expect[5] = { 0, 0, 0, 0, 0 }; -@@ -3532,28 +3560,28 @@ static Bool isLoadImm_EXACTLY2or5 ( UCha - - // load high word - // lis r_dst, (imm>>48) & 0xFFFF -- p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF); -+ p = mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF, endness_host); - - // ori r_dst, r_dst, (imm>>32) & 0xFFFF -- p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF, endness_host); - - // shift r_dst low word to high word => rldicr -- p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1); -+ p = mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1, endness_host); - - // load low word - // oris r_dst, r_dst, (imm>>16) & 0xFFFF -- p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF); -+ p = mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF, endness_host); - - // ori r_dst, r_dst, (imm) & 0xFFFF -- p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF); -+ p = mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF, endness_host); - - vassert(p == (UChar*)&expect[5]); - -- return fetch32(p_to_check + 0) == expect[0] -- && fetch32(p_to_check + 4) == expect[1] -- && fetch32(p_to_check + 8) == expect[2] -- && fetch32(p_to_check + 12) == expect[3] -- && fetch32(p_to_check + 16) == expect[4]; -+ return fetch32(p_to_check + 0, endness_host) == expect[0] -+ && fetch32(p_to_check + 4, endness_host) == expect[1] -+ && fetch32(p_to_check + 8, endness_host) == expect[2] -+ && fetch32(p_to_check + 12, endness_host) == expect[3] -+ && fetch32(p_to_check + 16, endness_host) == expect[4]; - } - } - -@@ -3562,7 +3590,7 @@ static Bool isLoadImm_EXACTLY2or5 ( UCha - the Pin_Load and Pin_Store cases below. */ - static UChar* do_load_or_store_machine_word ( - UChar* p, Bool isLoad, -- UInt reg, PPCAMode* am, Bool mode64 ) -+ UInt reg, PPCAMode* am, Bool mode64, VexEndness endness_host ) - { - if (isLoad) { - UInt opc1, sz = mode64 ? 8 : 4; -@@ -3576,7 +3604,7 @@ static UChar* do_load_or_store_machine_w - case 8: opc1 = 58; vassert(mode64); break; - default: vassert(0); - } -- p = doAMode_IR(p, opc1, reg, am, mode64); -+ p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); - break; - case Pam_RR: - /* we could handle this case, but we don't expect to ever -@@ -3597,7 +3625,7 @@ static UChar* do_load_or_store_machine_w - case 8: opc1 = 62; vassert(mode64); break; - default: vassert(0); - } -- p = doAMode_IR(p, opc1, reg, am, mode64); -+ p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); - break; - case Pam_RR: - /* we could handle this case, but we don't expect to ever -@@ -3614,7 +3642,7 @@ static UChar* do_load_or_store_machine_w - do_load_or_store_machine_word above. */ - static UChar* do_load_or_store_word32 ( - UChar* p, Bool isLoad, -- UInt reg, PPCAMode* am, Bool mode64 ) -+ UInt reg, PPCAMode* am, Bool mode64, VexEndness endness_host ) - { - if (isLoad) { - UInt opc1; -@@ -3624,7 +3652,7 @@ static UChar* do_load_or_store_word32 ( - vassert(0 == (am->Pam.IR.index & 3)); - } - opc1 = 32; -- p = doAMode_IR(p, opc1, reg, am, mode64); -+ p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); - break; - case Pam_RR: - /* we could handle this case, but we don't expect to ever -@@ -3641,7 +3669,7 @@ static UChar* do_load_or_store_word32 ( - vassert(0 == (am->Pam.IR.index & 3)); - } - opc1 = 36; -- p = doAMode_IR(p, opc1, reg, am, mode64); -+ p = doAMode_IR(p, opc1, reg, am, mode64, endness_host); - break; - case Pam_RR: - /* we could handle this case, but we don't expect to ever -@@ -3655,20 +3683,21 @@ static UChar* do_load_or_store_word32 ( - } - - /* Move r_dst to r_src */ --static UChar* mkMoveReg ( UChar* p, UInt r_dst, UInt r_src ) -+static UChar* mkMoveReg ( UChar* p, UInt r_dst, UInt r_src, -+ VexEndness endness_host ) - { - vassert(r_dst < 0x20); - vassert(r_src < 0x20); - - if (r_dst != r_src) { - /* or r_dst, r_src, r_src */ -- p = mkFormX(p, 31, r_src, r_dst, r_src, 444, 0 ); -+ p = mkFormX(p, 31, r_src, r_dst, r_src, 444, 0, endness_host ); - } - return p; - } - - static UChar* mkFormVX ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt r3, UInt opc2 ) -+ UInt r3, UInt opc2, VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3677,11 +3706,12 @@ static UChar* mkFormVX ( UChar* p, UInt - vassert(r3 < 0x20); - vassert(opc2 < 0x800); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | opc2); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormVXR ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt r3, UInt Rc, UInt opc2 ) -+ UInt r3, UInt Rc, UInt opc2, -+ VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3692,11 +3722,11 @@ static UChar* mkFormVXR ( UChar* p, UInt - vassert(opc2 < 0x400); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - (r3<<11) | (Rc<<10) | opc2); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - static UChar* mkFormVA ( UChar* p, UInt opc1, UInt r1, UInt r2, -- UInt r3, UInt r4, UInt opc2 ) -+ UInt r3, UInt r4, UInt opc2, VexEndness endness_host ) - { - UInt theInstr; - vassert(opc1 < 0x40); -@@ -3707,7 +3737,7 @@ static UChar* mkFormVA ( UChar* p, UInt - vassert(opc2 < 0x40); - theInstr = ((opc1<<26) | (r1<<21) | (r2<<16) | - (r3<<11) | (r4<<6) | opc2); -- return emit32(p, theInstr); -+ return emit32(p, theInstr, endness_host); - } - - -@@ -3724,7 +3754,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - void* disp_cp_chain_me_to_slowEP, - void* disp_cp_chain_me_to_fastEP, - void* disp_cp_xindir, -- void* disp_cp_xassisted ) -+ void* disp_cp_xassisted) - { - UChar* p = &buf[0]; - vassert(nbuf >= 32); -@@ -3737,7 +3767,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - case Pin_LI: - p = mkLoadImm(p, iregNo(i->Pin.LI.dst, mode64), -- i->Pin.LI.imm64, mode64); -+ i->Pin.LI.imm64, mode64, endness_host); - goto done; - - case Pin_Alu: { -@@ -3754,10 +3784,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* addi (PPC32 p350) */ - vassert(srcR->Prh.Imm.syned); - vassert(srcR->Prh.Imm.imm16 != 0x8000); -- p = mkFormD(p, 14, r_dst, r_srcL, srcR->Prh.Imm.imm16); -+ p = mkFormD(p, 14, r_dst, r_srcL, srcR->Prh.Imm.imm16, endness_host); - } else { - /* add (PPC32 p347) */ -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 266, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 266, 0, endness_host); - } - break; - -@@ -3766,10 +3796,11 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* addi (PPC32 p350), but with negated imm */ - vassert(srcR->Prh.Imm.syned); - vassert(srcR->Prh.Imm.imm16 != 0x8000); -- p = mkFormD(p, 14, r_dst, r_srcL, (- srcR->Prh.Imm.imm16)); -+ p = mkFormD(p, 14, r_dst, r_srcL, (- srcR->Prh.Imm.imm16), -+ endness_host); - } else { - /* subf (PPC32 p537), with args the "wrong" way round */ -- p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 40, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 40, 0, endness_host); - } - break; - -@@ -3777,10 +3808,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - if (immR) { - /* andi. (PPC32 p358) */ - vassert(!srcR->Prh.Imm.syned); -- p = mkFormD(p, 28, r_srcL, r_dst, srcR->Prh.Imm.imm16); -+ p = mkFormD(p, 28, r_srcL, r_dst, srcR->Prh.Imm.imm16, endness_host); - } else { - /* and (PPC32 p356) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 28, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 28, 0, endness_host); - } - break; - -@@ -3788,10 +3819,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - if (immR) { - /* ori (PPC32 p497) */ - vassert(!srcR->Prh.Imm.syned); -- p = mkFormD(p, 24, r_srcL, r_dst, srcR->Prh.Imm.imm16); -+ p = mkFormD(p, 24, r_srcL, r_dst, srcR->Prh.Imm.imm16, endness_host); - } else { - /* or (PPC32 p495) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 444, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 444, 0, endness_host); - } - break; - -@@ -3799,10 +3830,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - if (immR) { - /* xori (PPC32 p550) */ - vassert(!srcR->Prh.Imm.syned); -- p = mkFormD(p, 26, r_srcL, r_dst, srcR->Prh.Imm.imm16); -+ p = mkFormD(p, 26, r_srcL, r_dst, srcR->Prh.Imm.imm16, endness_host); - } else { - /* xor (PPC32 p549) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 316, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 316, 0, endness_host); - } - break; - -@@ -3834,10 +3865,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt n = srcR->Prh.Imm.imm16; - vassert(!srcR->Prh.Imm.syned); - vassert(n > 0 && n < 32); -- p = mkFormM(p, 21, r_srcL, r_dst, n, 0, 31-n, 0); -+ p = mkFormM(p, 21, r_srcL, r_dst, n, 0, 31-n, 0, endness_host); - } else { - /* slw (PPC32 p505) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 24, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 24, 0, endness_host); - } - } else { - if (immR) { -@@ -3848,10 +3879,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt n = srcR->Prh.Imm.imm16; - vassert(!srcR->Prh.Imm.syned); - vassert(n > 0 && n < 64); -- p = mkFormMD(p, 30, r_srcL, r_dst, n, 63-n, 1); -+ p = mkFormMD(p, 30, r_srcL, r_dst, n, 63-n, 1, endness_host); - } else { - /* sld (PPC64 p568) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 27, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 27, 0, endness_host); - } - } - break; -@@ -3866,10 +3897,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt n = srcR->Prh.Imm.imm16; - vassert(!srcR->Prh.Imm.syned); - vassert(n > 0 && n < 32); -- p = mkFormM(p, 21, r_srcL, r_dst, 32-n, n, 31, 0); -+ p = mkFormM(p, 21, r_srcL, r_dst, 32-n, n, 31, 0, endness_host); - } else { - /* srw (PPC32 p508) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 536, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 536, 0, endness_host); - } - } else { - if (immR) { -@@ -3880,10 +3911,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt n = srcR->Prh.Imm.imm16; - vassert(!srcR->Prh.Imm.syned); - vassert(n > 0 && n < 64); -- p = mkFormMD(p, 30, r_srcL, r_dst, 64-n, n, 0); -+ p = mkFormMD(p, 30, r_srcL, r_dst, 64-n, n, 0, endness_host); - } else { - /* srd (PPC64 p574) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 539, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 539, 0, endness_host); - } - } - break; -@@ -3901,10 +3932,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vassert(n >= 0 && n < 32); - else - vassert(n > 0 && n < 32); -- p = mkFormX(p, 31, r_srcL, r_dst, n, 824, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, n, 824, 0, endness_host); - } else { - /* sraw (PPC32 p506) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 792, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 792, 0, endness_host); - } - } else { - if (immR) { -@@ -3912,10 +3943,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt n = srcR->Prh.Imm.imm16; - vassert(!srcR->Prh.Imm.syned); - vassert(n > 0 && n < 64); -- p = mkFormXS(p, 31, r_srcL, r_dst, n, 413, 0); -+ p = mkFormXS(p, 31, r_srcL, r_dst, n, 413, 0, endness_host); - } else { - /* srad (PPC32 p570) */ -- p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 794, 0); -+ p = mkFormX(p, 31, r_srcL, r_dst, r_srcR, 794, 0, endness_host); - } - } - break; -@@ -3935,15 +3966,15 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - if (isAdd) { - if (setC) /* addc (PPC32 p348) */ -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 10, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 10, 0, endness_host); - else /* adde (PPC32 p349) */ -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 138, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 138, 0, endness_host); - } else { - /* subfX, with args the "wrong" way round */ - if (setC) /* subfc (PPC32 p538) */ -- p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 8, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 8, 0, endness_host); - else /* subfe (PPC32 p539) */ -- p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 136, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcR, r_srcL, 0, 136, 0, endness_host); - } - goto done; - } -@@ -3967,17 +3998,17 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - imm_srcR = srcR->Prh.Imm.imm16; - if (syned) { // cmpw/di (signed) (PPC32 p368) - vassert(imm_srcR != 0x8000); -- p = mkFormD(p, 11, fld1, r_srcL, imm_srcR); -+ p = mkFormD(p, 11, fld1, r_srcL, imm_srcR, endness_host); - } else { // cmplw/di (unsigned) (PPC32 p370) -- p = mkFormD(p, 10, fld1, r_srcL, imm_srcR); -+ p = mkFormD(p, 10, fld1, r_srcL, imm_srcR, endness_host); - } - break; - case Prh_Reg: - r_srcR = iregNo(srcR->Prh.Reg.reg, mode64); - if (syned) // cmpwi (signed) (PPC32 p367) -- p = mkFormX(p, 31, fld1, r_srcL, r_srcR, 0, 0); -+ p = mkFormX(p, 31, fld1, r_srcL, r_srcR, 0, 0, endness_host); - else // cmplwi (unsigned) (PPC32 p379) -- p = mkFormX(p, 31, fld1, r_srcL, r_srcR, 32, 0); -+ p = mkFormX(p, 31, fld1, r_srcL, r_srcR, 32, 0, endness_host); - break; - default: - goto bad; -@@ -3991,21 +4022,21 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - switch (i->Pin.Unary.op) { - case Pun_NOT: // nor r_dst,r_src,r_src -- p = mkFormX(p, 31, r_src, r_dst, r_src, 124, 0); -+ p = mkFormX(p, 31, r_src, r_dst, r_src, 124, 0, endness_host); - break; - case Pun_NEG: // neg r_dst,r_src -- p = mkFormXO(p, 31, r_dst, r_src, 0, 0, 104, 0); -+ p = mkFormXO(p, 31, r_dst, r_src, 0, 0, 104, 0, endness_host); - break; - case Pun_CLZ32: // cntlzw r_dst, r_src -- p = mkFormX(p, 31, r_src, r_dst, 0, 26, 0); -+ p = mkFormX(p, 31, r_src, r_dst, 0, 26, 0, endness_host); - break; - case Pun_CLZ64: // cntlzd r_dst, r_src - vassert(mode64); -- p = mkFormX(p, 31, r_src, r_dst, 0, 58, 0); -+ p = mkFormX(p, 31, r_src, r_dst, 0, 58, 0, endness_host); - break; - case Pun_EXTSW: // extsw r_dst, r_src - vassert(mode64); -- p = mkFormX(p, 31, r_src, r_dst, 0, 986, 0); -+ p = mkFormX(p, 31, r_src, r_dst, 0, 986, 0, endness_host); - break; - default: goto bad; - } -@@ -4026,22 +4057,25 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - // mul hi words, must consider sign - if (sz32) { - if (syned) // mulhw r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 75, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 75, 0, -+ endness_host); - else // mulhwu r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 11, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 11, 0, -+ endness_host); - } else { - if (syned) // mulhd r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 73, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 73, 0, -+ endness_host); - else // mulhdu r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 9, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 9, 0, endness_host); - } - } else { - // mul low word, sign is irrelevant - vassert(!i->Pin.MulL.syned); - if (sz32) // mullw r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 235, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 235, 0, endness_host); - else // mulld r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 233, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 233, 0, endness_host); - } - goto done; - } -@@ -4060,28 +4094,32 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - if (sz32) { - if (syned) - // divwe r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 427, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 427, 0, -+ endness_host); - else - // divweu r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 395, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 395, 0, -+ endness_host); - } else { - if (syned) - // divde r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 425, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 425, 0, -+ endness_host); - else - // divdeu r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 393, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 393, 0, -+ endness_host); - } - } else if (sz32) { - if (syned) // divw r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 491, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 491, 0, endness_host); - else // divwu r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 459, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 459, 0, endness_host); - } else { - if (syned) // divd r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 489, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 489, 0, endness_host); - else // divdu r_dst,r_srcL,r_srcR -- p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 457, 0); -+ p = mkFormXO(p, 31, r_dst, r_srcL, r_srcR, 0, 457, 0, endness_host); - } - goto done; - } -@@ -4113,13 +4151,13 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - } - - /* load target to r_dst */ // p += 4|8|20 -- p = mkLoadImm(p, r_dst, i->Pin.Call.target, mode64); -+ p = mkLoadImm(p, r_dst, i->Pin.Call.target, mode64, endness_host); - - /* mtspr 9,r_dst => move r_dst to count register */ -- p = mkFormXFX(p, r_dst, 9, 467); // p += 4 -+ p = mkFormXFX(p, r_dst, 9, 467, endness_host); // p += 4 - - /* bctrl => branch to count register (and save to lr) */ -- p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1); // p += 4 -+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1, endness_host); // p += 4 - - /* Fix up the conditional jump, if there was one. */ - if (cond.test != Pct_ALWAYS) { -@@ -4127,7 +4165,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vassert(delta >= 16 && delta <= 32); - /* bc !ct,cf,delta */ - mkFormB(ptmp, invertCondTest(cond.test), -- cond.flag, (delta>>2), 0, 0); -+ cond.flag, (delta>>2), 0, 0, endness_host); - } - goto done; - } -@@ -4156,11 +4194,12 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* Update the guest CIA. */ - /* imm32/64 r30, dstGA */ - if (!mode64) vassert(0 == (((ULong)i->Pin.XDirect.dstGA) >> 32)); -- p = mkLoadImm(p, /*r*/30, (ULong)i->Pin.XDirect.dstGA, mode64); -+ p = mkLoadImm(p, /*r*/30, (ULong)i->Pin.XDirect.dstGA, mode64, -+ endness_host); - /* stw/std r30, amCIA */ - p = do_load_or_store_machine_word( - p, False/*!isLoad*/, -- /*r*/30, i->Pin.XDirect.amCIA, mode64 -+ /*r*/30, i->Pin.XDirect.amCIA, mode64, endness_host - ); - - /* --- FIRST PATCHABLE BYTE follows --- */ -@@ -4173,11 +4212,11 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - = i->Pin.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP - : disp_cp_chain_me_to_slowEP; - p = mkLoadImm_EXACTLY2or5( -- p, /*r*/30, Ptr_to_ULong(disp_cp_chain_me), mode64); -+ p, /*r*/30, Ptr_to_ULong(disp_cp_chain_me), mode64, endness_host); - /* mtctr r30 */ -- p = mkFormXFX(p, /*r*/30, 9, 467); -+ p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); - /* bctrl */ -- p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1); -+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 1, endness_host); - /* --- END of PATCHABLE BYTES --- */ - - /* Fix up the conditional jump, if there was one. */ -@@ -4186,7 +4225,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vassert(delta >= 16 && delta <= 64 && 0 == (delta & 3)); - /* bc !ct,cf,delta */ - mkFormB(ptmp, invertCondTest(i->Pin.XDirect.cond.test), -- i->Pin.XDirect.cond.flag, (delta>>2), 0, 0); -+ i->Pin.XDirect.cond.flag, (delta>>2), 0, 0, endness_host); - } - goto done; - } -@@ -4217,15 +4256,16 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - p = do_load_or_store_machine_word( - p, False/*!isLoad*/, - iregNo(i->Pin.XIndir.dstGA, mode64), -- i->Pin.XIndir.amCIA, mode64 -+ i->Pin.XIndir.amCIA, mode64, endness_host - ); - - /* imm32/64 r30, VG_(disp_cp_xindir) */ -- p = mkLoadImm(p, /*r*/30, (ULong)Ptr_to_ULong(disp_cp_xindir), mode64); -+ p = mkLoadImm(p, /*r*/30, (ULong)Ptr_to_ULong(disp_cp_xindir), mode64, -+ endness_host); - /* mtctr r30 */ -- p = mkFormXFX(p, /*r*/30, 9, 467); -+ p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); - /* bctr */ -- p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0); -+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0, endness_host); - - /* Fix up the conditional jump, if there was one. */ - if (i->Pin.XIndir.cond.test != Pct_ALWAYS) { -@@ -4233,7 +4273,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vassert(delta >= 16 && delta <= 32 && 0 == (delta & 3)); - /* bc !ct,cf,delta */ - mkFormB(ptmp, invertCondTest(i->Pin.XIndir.cond.test), -- i->Pin.XIndir.cond.flag, (delta>>2), 0, 0); -+ i->Pin.XIndir.cond.flag, (delta>>2), 0, 0, endness_host); - } - goto done; - } -@@ -4256,7 +4296,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - p = do_load_or_store_machine_word( - p, False/*!isLoad*/, - iregNo(i->Pin.XIndir.dstGA, mode64), -- i->Pin.XIndir.amCIA, mode64 -+ i->Pin.XIndir.amCIA, mode64, endness_host - ); - - /* imm32/64 r31, $magic_number */ -@@ -4285,15 +4325,16 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vpanic("emit_ARMInstr.Pin_XAssisted: unexpected jump kind"); - } - vassert(trcval != 0); -- p = mkLoadImm(p, /*r*/31, trcval, mode64); -+ p = mkLoadImm(p, /*r*/31, trcval, mode64, endness_host); - - /* imm32/64 r30, VG_(disp_cp_xassisted) */ - p = mkLoadImm(p, /*r*/30, -- (ULong)Ptr_to_ULong(disp_cp_xassisted), mode64); -+ (ULong)Ptr_to_ULong(disp_cp_xassisted), mode64, -+ endness_host); - /* mtctr r30 */ -- p = mkFormXFX(p, /*r*/30, 9, 467); -+ p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); - /* bctr */ -- p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0); -+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0, endness_host); - - /* Fix up the conditional jump, if there was one. */ - if (i->Pin.XAssisted.cond.test != Pct_ALWAYS) { -@@ -4301,7 +4342,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vassert(delta >= 16 && delta <= 32 && 0 == (delta & 3)); - /* bc !ct,cf,delta */ - mkFormB(ptmp, invertCondTest(i->Pin.XAssisted.cond.test), -- i->Pin.XAssisted.cond.flag, (delta>>2), 0, 0); -+ i->Pin.XAssisted.cond.flag, (delta>>2), 0, 0, endness_host); - } - goto done; - } -@@ -4328,11 +4369,11 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - switch (i->Pin.CMov.src->tag) { - case Pri_Imm: - imm_src = i->Pin.CMov.src->Pri.Imm; -- p = mkLoadImm(p, r_dst, imm_src, mode64); // p += 4|8|20 -+ p = mkLoadImm(p, r_dst, imm_src, mode64, endness_host); // p += 4|8|20 - break; - case Pri_Reg: - r_src = iregNo(i->Pin.CMov.src->Pri.Reg, mode64); -- p = mkMoveReg(p, r_dst, r_src); // p += 4 -+ p = mkMoveReg(p, r_dst, r_src, endness_host); // p += 4 - break; - default: goto bad; - } -@@ -4343,7 +4384,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vassert(delta >= 8 && delta <= 24); - /* bc !ct,cf,delta */ - mkFormB(ptmp, invertCondTest(cond.test), -- cond.flag, (delta>>2), 0, 0); -+ cond.flag, (delta>>2), 0, 0, endness_host); - } - goto done; - } -@@ -4365,7 +4406,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - case 8: opc1 = 58; vassert(mode64); break; - default: goto bad; - } -- p = doAMode_IR(p, opc1, r_dst, am_addr, mode64); -+ p = doAMode_IR(p, opc1, r_dst, am_addr, mode64, endness_host); - goto done; - case Pam_RR: - switch(sz) { -@@ -4375,7 +4416,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - case 8: opc2 = 21; vassert(mode64); break; - default: goto bad; - } -- p = doAMode_RR(p, 31, opc2, r_dst, am_addr, mode64); -+ p = doAMode_RR(p, 31, opc2, r_dst, am_addr, mode64, endness_host); - goto done; - default: - goto bad; -@@ -4385,12 +4426,12 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - case Pin_LoadL: { - if (i->Pin.LoadL.sz == 4) { - p = mkFormX(p, 31, iregNo(i->Pin.LoadL.dst, mode64), -- 0, iregNo(i->Pin.LoadL.src, mode64), 20, 0); -+ 0, iregNo(i->Pin.LoadL.src, mode64), 20, 0, endness_host); - goto done; - } - if (i->Pin.LoadL.sz == 8 && mode64) { - p = mkFormX(p, 31, iregNo(i->Pin.LoadL.dst, mode64), -- 0, iregNo(i->Pin.LoadL.src, mode64), 84, 0); -+ 0, iregNo(i->Pin.LoadL.src, mode64), 84, 0, endness_host); - goto done; - } - goto bad; -@@ -4405,22 +4446,22 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - if (cond.test == Pct_ALWAYS) { - // Just load 1 to dst => li dst,1 -- p = mkFormD(p, 14, r_dst, 0, 1); -+ p = mkFormD(p, 14, r_dst, 0, 1, endness_host); - } else { - vassert(cond.flag != Pcf_NONE); - rot_imm = 1 + cond.flag; - r_tmp = 0; // Not set in getAllocable, so no need to declare. - - // r_tmp = CR => mfcr r_tmp -- p = mkFormX(p, 31, r_tmp, 0, 0, 19, 0); -+ p = mkFormX(p, 31, r_tmp, 0, 0, 19, 0, endness_host); - - // r_dst = flag (rotate left and mask) - // => rlwinm r_dst,r_tmp,rot_imm,31,31 -- p = mkFormM(p, 21, r_tmp, r_dst, rot_imm, 31, 31, 0); -+ p = mkFormM(p, 21, r_tmp, r_dst, rot_imm, 31, 31, 0, endness_host); - - if (cond.test == Pct_FALSE) { - // flip bit => xori r_dst,r_dst,1 -- p = mkFormD(p, 26, r_dst, r_dst, 1); -+ p = mkFormD(p, 26, r_dst, r_dst, 1, endness_host); - } - } - goto done; -@@ -4428,11 +4469,12 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - case Pin_MfCR: - // mfcr dst -- p = mkFormX(p, 31, iregNo(i->Pin.MfCR.dst, mode64), 0, 0, 19, 0); -+ p = mkFormX(p, 31, iregNo(i->Pin.MfCR.dst, mode64), 0, 0, 19, 0, -+ endness_host); - goto done; - - case Pin_MFence: { -- p = mkFormX(p, 31, 0, 0, 0, 598, 0); // sync, PPC32 p616 -+ p = mkFormX(p, 31, 0, 0, 0, 598, 0, endness_host); // sync, PPC32 p616 - // CAB: Should this be isync? - // p = mkFormXL(p, 19, 0, 0, 0, 150, 0); // isync, PPC32 p467 - goto done; -@@ -4457,7 +4499,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = doAMode_IR(p, opc1, r_src, am_addr, mode64); -+ p = doAMode_IR(p, opc1, r_src, am_addr, mode64, endness_host); - goto done; - case Pam_RR: - switch(sz) { -@@ -4469,7 +4511,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = doAMode_RR(p, 31, opc2, r_src, am_addr, mode64); -+ p = doAMode_RR(p, 31, opc2, r_src, am_addr, mode64, endness_host); - goto done; - default: - goto bad; -@@ -4480,12 +4522,12 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - case Pin_StoreC: { - if (i->Pin.StoreC.sz == 4) { - p = mkFormX(p, 31, iregNo(i->Pin.StoreC.src, mode64), -- 0, iregNo(i->Pin.StoreC.dst, mode64), 150, 1); -+ 0, iregNo(i->Pin.StoreC.dst, mode64), 150, 1, endness_host); - goto done; - } - if (i->Pin.StoreC.sz == 8 && mode64) { - p = mkFormX(p, 31, iregNo(i->Pin.StoreC.src, mode64), -- 0, iregNo(i->Pin.StoreC.dst, mode64), 214, 1); -+ 0, iregNo(i->Pin.StoreC.dst, mode64), 214, 1, endness_host); - goto done; - } - goto bad; -@@ -4496,34 +4538,34 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt fr_src = fregNo(i->Pin.FpUnary.src); - switch (i->Pin.FpUnary.op) { - case Pfp_RSQRTE: // frsqrtre, PPC32 p424 -- p = mkFormA( p, 63, fr_dst, 0, fr_src, 0, 26, 0 ); -+ p = mkFormA( p, 63, fr_dst, 0, fr_src, 0, 26, 0, endness_host ); - break; - case Pfp_RES: // fres, PPC32 p421 -- p = mkFormA( p, 59, fr_dst, 0, fr_src, 0, 24, 0 ); -+ p = mkFormA( p, 59, fr_dst, 0, fr_src, 0, 24, 0, endness_host ); - break; - case Pfp_SQRT: // fsqrt, PPC32 p427 -- p = mkFormA( p, 63, fr_dst, 0, fr_src, 0, 22, 0 ); -+ p = mkFormA( p, 63, fr_dst, 0, fr_src, 0, 22, 0, endness_host ); - break; - case Pfp_ABS: // fabs, PPC32 p399 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 264, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 264, 0, endness_host); - break; - case Pfp_NEG: // fneg, PPC32 p416 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 40, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 40, 0, endness_host); - break; - case Pfp_MOV: // fmr, PPC32 p410 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 72, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 72, 0, endness_host); - break; - case Pfp_FRIM: // frim, PPC ISA 2.05 p137 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 488, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 488, 0, endness_host); - break; - case Pfp_FRIP: // frip, PPC ISA 2.05 p137 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 456, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 456, 0, endness_host); - break; - case Pfp_FRIN: // frin, PPC ISA 2.05 p137 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 392, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 392, 0, endness_host); - break; - case Pfp_FRIZ: // friz, PPC ISA 2.05 p137 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 424, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 424, 0, endness_host); - break; - default: - goto bad; -@@ -4537,28 +4579,28 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt fr_srcR = fregNo(i->Pin.FpBinary.srcR); - switch (i->Pin.FpBinary.op) { - case Pfp_ADDD: // fadd, PPC32 p400 -- p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 21, 0 ); -+ p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 21, 0, endness_host ); - break; - case Pfp_ADDS: // fadds, PPC32 p401 -- p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 21, 0 ); -+ p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 21, 0, endness_host ); - break; - case Pfp_SUBD: // fsub, PPC32 p429 -- p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 20, 0 ); -+ p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 20, 0, endness_host ); - break; - case Pfp_SUBS: // fsubs, PPC32 p430 -- p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 20, 0 ); -+ p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 20, 0, endness_host ); - break; - case Pfp_MULD: // fmul, PPC32 p413 -- p = mkFormA( p, 63, fr_dst, fr_srcL, 0, fr_srcR, 25, 0 ); -+ p = mkFormA( p, 63, fr_dst, fr_srcL, 0, fr_srcR, 25, 0, endness_host ); - break; - case Pfp_MULS: // fmuls, PPC32 p414 -- p = mkFormA( p, 59, fr_dst, fr_srcL, 0, fr_srcR, 25, 0 ); -+ p = mkFormA( p, 59, fr_dst, fr_srcL, 0, fr_srcR, 25, 0, endness_host ); - break; - case Pfp_DIVD: // fdiv, PPC32 p406 -- p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 18, 0 ); -+ p = mkFormA( p, 63, fr_dst, fr_srcL, fr_srcR, 0, 18, 0, endness_host ); - break; - case Pfp_DIVS: // fdivs, PPC32 p407 -- p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 18, 0 ); -+ p = mkFormA( p, 59, fr_dst, fr_srcL, fr_srcR, 0, 18, 0, endness_host ); - break; - default: - goto bad; -@@ -4573,16 +4615,20 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt fr_srcAcc = fregNo(i->Pin.FpMulAcc.srcAcc); - switch (i->Pin.FpMulAcc.op) { - case Pfp_MADDD: // fmadd, PPC32 p408 -- p = mkFormA( p, 63, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 29, 0 ); -+ p = mkFormA( p, 63, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 29, 0, -+ endness_host ); - break; - case Pfp_MADDS: // fmadds, PPC32 p409 -- p = mkFormA( p, 59, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 29, 0 ); -+ p = mkFormA( p, 59, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 29, 0, -+ endness_host ); - break; - case Pfp_MSUBD: // fmsub, PPC32 p411 -- p = mkFormA( p, 63, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 28, 0 ); -+ p = mkFormA( p, 63, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 28, 0, -+ endness_host ); - break; - case Pfp_MSUBS: // fmsubs, PPC32 p412 -- p = mkFormA( p, 59, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 28, 0 ); -+ p = mkFormA( p, 59, fr_dst, fr_srcML, fr_srcAcc, fr_srcMR, 28, 0, -+ endness_host ); - break; - default: - goto bad; -@@ -4601,18 +4647,18 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - if (i->Pin.FpLdSt.isLoad) { // Load from memory - if (idxd) { // lf[s|d]x, PPC32 p444|440 - opc = (sz == 4) ? 535 : 599; -- p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64); -+ p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64, endness_host); - } else { // lf[s|d], PPC32 p441|437 - opc = (sz == 4) ? 48 : 50; -- p = doAMode_IR(p, opc, f_reg, am_addr, mode64); -+ p = doAMode_IR(p, opc, f_reg, am_addr, mode64, endness_host); - } - } else { // Store to memory - if (idxd) { // stf[s|d]x, PPC32 p521|516 - opc = (sz == 4) ? 663 : 727; -- p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64); -+ p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64, endness_host); - } else { // stf[s|d], PPC32 p518|513 - opc = (sz == 4) ? 52 : 54; -- p = doAMode_IR(p, opc, f_reg, am_addr, mode64); -+ p = doAMode_IR(p, opc, f_reg, am_addr, mode64, endness_host); - } - } - goto done; -@@ -4623,7 +4669,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt fr_data = fregNo(i->Pin.FpSTFIW.data); - // stfiwx (store fp64[lo32] as int32), PPC32 p517 - // Use rA==0, so that EA == rB == ir_addr -- p = mkFormX(p, 31, fr_data, 0/*rA=0*/, ir_addr, 983, 0); -+ p = mkFormX(p, 31, fr_data, 0/*rA=0*/, ir_addr, 983, 0, endness_host); - goto done; - } - -@@ -4631,7 +4677,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt fr_dst = fregNo(i->Pin.FpRSP.dst); - UInt fr_src = fregNo(i->Pin.FpRSP.src); - // frsp, PPC32 p423 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 12, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 12, 0, endness_host); - goto done; - } - -@@ -4641,37 +4687,37 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - if (i->Pin.FpCftI.fromI == False && i->Pin.FpCftI.int32 == True) { - if (i->Pin.FpCftI.syned == True) { - // fctiw (conv f64 to i32), PPC32 p404 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 14, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 14, 0, endness_host); - goto done; - } else { - // fctiwu (conv f64 to u32) -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 142, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 142, 0, endness_host); - goto done; - } - } - if (i->Pin.FpCftI.fromI == False && i->Pin.FpCftI.int32 == False) { - if (i->Pin.FpCftI.syned == True) { - // fctid (conv f64 to i64), PPC64 p437 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 814, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 814, 0, endness_host); - goto done; - } else { - // fctidu (conv f64 to u64) -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 942, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 942, 0, endness_host); - goto done; - } - } - if (i->Pin.FpCftI.fromI == True && i->Pin.FpCftI.int32 == False) { - if (i->Pin.FpCftI.syned == True) { - // fcfid (conv i64 to f64), PPC64 p434 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 846, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 846, 0, endness_host); - goto done; - } else if (i->Pin.FpCftI.flt64 == True) { - // fcfidu (conv u64 to f64) -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 974, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 974, 0, endness_host); - goto done; - } else { - // fcfidus (conv u64 to f32) -- p = mkFormX(p, 59, fr_dst, 0, fr_src, 974, 0); -+ p = mkFormX(p, 59, fr_dst, 0, fr_src, 974, 0, endness_host); - goto done; - } - } -@@ -4690,17 +4736,18 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* jmp fwds if !condition */ - if (cc.test != Pct_ALWAYS) { - /* bc !ct,cf,n_bytes>>2 */ -- p = mkFormB(p, invertCondTest(cc.test), cc.flag, 8>>2, 0, 0); -+ p = mkFormB(p, invertCondTest(cc.test), cc.flag, 8>>2, 0, 0, -+ endness_host); - } - - // fmr, PPC32 p410 -- p = mkFormX(p, 63, fr_dst, 0, fr_src, 72, 0); -+ p = mkFormX(p, 63, fr_dst, 0, fr_src, 72, 0, endness_host); - goto done; - } - - case Pin_FpLdFPSCR: { - UInt fr_src = fregNo(i->Pin.FpLdFPSCR.src); -- p = mkFormXFL(p, 0xFF, fr_src, i->Pin.FpLdFPSCR.dfp_rm); // mtfsf, PPC32 p480 -+ p = mkFormXFL(p, 0xFF, fr_src, i->Pin.FpLdFPSCR.dfp_rm, endness_host); // mtfsf, PPC32 p480 - goto done; - } - -@@ -4711,21 +4758,22 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt fr_srcR = fregNo(i->Pin.FpCmp.srcR); - vassert(crfD < 8); - // fcmpo, PPC32 p402 -- p = mkFormX(p, 63, crfD<<2, fr_srcL, fr_srcR, 32, 0); -+ p = mkFormX(p, 63, crfD<<2, fr_srcL, fr_srcR, 32, 0, endness_host); - - // mfcr (mv CR to r_dst), PPC32 p467 -- p = mkFormX(p, 31, r_dst, 0, 0, 19, 0); -+ p = mkFormX(p, 31, r_dst, 0, 0, 19, 0, endness_host); - - // rlwinm r_dst,r_dst,8,28,31, PPC32 p501 - // => rotate field 1 to bottomw of word, masking out upper 28 -- p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0); -+ p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0, endness_host); - goto done; - } - - case Pin_RdWrLR: { - UInt reg = iregNo(i->Pin.RdWrLR.gpr, mode64); - /* wrLR==True ? mtlr r4 : mflr r4 */ -- p = mkFormXFX(p, reg, 8, (i->Pin.RdWrLR.wrLR==True) ? 467 : 339); -+ p = mkFormXFX(p, reg, 8, (i->Pin.RdWrLR.wrLR==True) ? 467 : 339, -+ endness_host); - goto done; - } - -@@ -4744,17 +4792,17 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - if (!idxd) { - r_idx = 30; // XXX: Using r30 as temp - p = mkLoadImm(p, r_idx, -- i->Pin.AvLdSt.addr->Pam.IR.index, mode64); -+ i->Pin.AvLdSt.addr->Pam.IR.index, mode64, endness_host); - } else { - r_idx = iregNo(i->Pin.AvLdSt.addr->Pam.RR.index, mode64); - } - - if (i->Pin.FpLdSt.isLoad) { // Load from memory (1,2,4,16) - opc2 = (sz==1) ? 7 : (sz==2) ? 39 : (sz==4) ? 71 : 103; -- p = mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0); -+ p = mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0, endness_host); - } else { // Store to memory (1,2,4,16) - opc2 = (sz==1) ? 135 : (sz==2) ? 167 : (sz==4) ? 199 : 231; -- p = mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0); -+ p = mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0, endness_host); - } - goto done; - } -@@ -4784,10 +4832,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - switch (i->Pin.AvUnary.op) { - case Pav_MOV: - case Pav_NOT: -- p = mkFormVX( p, 4, v_dst, v_src, v_src, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_src, v_src, opc2, endness_host ); - break; - default: -- p = mkFormVX( p, 4, v_dst, 0, v_src, opc2 ); -+ p = mkFormVX( p, 4, v_dst, 0, v_src, opc2, endness_host ); - break; - } - goto done; -@@ -4799,13 +4847,13 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt v_srcR = vregNo(i->Pin.AvBinary.srcR); - UInt opc2; - if (i->Pin.AvBinary.op == Pav_SHL) { -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1036 ); // vslo -- p = mkFormVX( p, 4, v_dst, v_dst, v_srcR, 452 ); // vsl -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1036, endness_host ); // vslo -+ p = mkFormVX( p, 4, v_dst, v_dst, v_srcR, 452, endness_host ); // vsl - goto done; - } - if (i->Pin.AvBinary.op == Pav_SHR) { -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1100 ); // vsro -- p = mkFormVX( p, 4, v_dst, v_dst, v_srcR, 708 ); // vsr -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1100, endness_host ); // vsro -+ p = mkFormVX( p, 4, v_dst, v_dst, v_srcR, 708, endness_host ); // vsr - goto done; - } - switch (i->Pin.AvBinary.op) { -@@ -4816,7 +4864,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); - goto done; - } - -@@ -4864,7 +4912,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); - goto done; - } - -@@ -4918,7 +4966,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); - goto done; - } - -@@ -4977,7 +5025,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); - goto done; - } - -@@ -5009,7 +5057,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); - goto done; - } - case Pin_AvCipherV128Unary: { -@@ -5021,7 +5069,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_src, 0, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_src, 0, opc2, endness_host ); - goto done; - } - case Pin_AvCipherV128Binary: { -@@ -5037,7 +5085,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2, endness_host ); - goto done; - } - case Pin_AvHashV128Binary: { -@@ -5051,7 +5099,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, v_src, s_field->Pri.Imm, opc2 ); -+ p = mkFormVX( p, 4, v_dst, v_src, s_field->Pri.Imm, opc2, endness_host ); - goto done; - } - case Pin_AvBCDV128Trinary: { -@@ -5067,7 +5115,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - goto bad; - } - p = mkFormVXR( p, 4, v_dst, v_src1, v_src2, -- 0x1, (ps->Pri.Imm << 9) | opc2 ); -+ 0x1, (ps->Pri.Imm << 9) | opc2, endness_host ); - goto done; - } - case Pin_AvBin32Fx4: { -@@ -5077,16 +5125,16 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - switch (i->Pin.AvBin32Fx4.op) { - - case Pavfp_ADDF: -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 10 ); // vaddfp -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 10, endness_host ); // vaddfp - break; - case Pavfp_SUBF: -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 74 ); // vsubfp -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 74, endness_host ); // vsubfp - break; - case Pavfp_MAXF: -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1034 ); // vmaxfp -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1034, endness_host ); // vmaxfp - break; - case Pavfp_MINF: -- p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1098 ); // vminfp -+ p = mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1098, endness_host ); // vminfp - break; - - case Pavfp_MULF: { -@@ -5101,23 +5149,23 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - // Better way to load -0.0 (0x80000000) ? - // vspltisw vB,0x1F (0x1F => each word of vB) -- p = mkFormVX( p, 4, vB, konst, 0, 908 ); -+ p = mkFormVX( p, 4, vB, konst, 0, 908, endness_host ); - - // vslw vB,vB,vB (each word of vB = (0x1F << 0x1F) = 0x80000000 -- p = mkFormVX( p, 4, vB, vB, vB, 388 ); -+ p = mkFormVX( p, 4, vB, vB, vB, 388, endness_host ); - - // Finally, do the multiply: -- p = mkFormVA( p, 4, v_dst, v_srcL, vB, v_srcR, 46 ); -+ p = mkFormVA( p, 4, v_dst, v_srcL, vB, v_srcR, 46, endness_host ); - break; - } - case Pavfp_CMPEQF: // vcmpeqfp -- p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 198 ); -+ p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 198, endness_host); - break; - case Pavfp_CMPGTF: // vcmpgtfp -- p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 710 ); -+ p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 710, endness_host ); - break; - case Pavfp_CMPGEF: // vcmpgefp -- p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 454 ); -+ p = mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 454, endness_host ); - break; - - default: -@@ -5144,7 +5192,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - default: - goto bad; - } -- p = mkFormVX( p, 4, v_dst, 0, v_src, opc2 ); -+ p = mkFormVX( p, 4, v_dst, 0, v_src, opc2, endness_host ); - goto done; - } - -@@ -5153,7 +5201,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt v_srcL = vregNo(i->Pin.AvPerm.srcL); - UInt v_srcR = vregNo(i->Pin.AvPerm.srcR); - UInt v_ctl = vregNo(i->Pin.AvPerm.ctl); -- p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 43 ); -+ p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 43, endness_host ); - goto done; - } - -@@ -5162,7 +5210,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt v_dst = vregNo(i->Pin.AvSel.dst); - UInt v_srcL = vregNo(i->Pin.AvSel.srcL); - UInt v_srcR = vregNo(i->Pin.AvSel.srcR); -- p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 42 ); -+ p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 42, endness_host ); - goto done; - } - -@@ -5172,7 +5220,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt v_srcL = vregNo(i->Pin.AvShlDbl.srcL); - UInt v_srcR = vregNo(i->Pin.AvShlDbl.srcR); - vassert(shift <= 0xF); -- p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, shift, 44 ); -+ p = mkFormVA( p, 4, v_dst, v_srcL, v_srcR, shift, 44, endness_host ); - goto done; - } - -@@ -5189,7 +5237,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - simm5 = i->Pin.AvSplat.src->Pvi.Imm5s; - vassert(simm5 >= -16 && simm5 <= 15); - simm5 = simm5 & 0x1F; -- p = mkFormVX( p, 4, v_dst, (UInt)simm5, 0, opc2 ); -+ p = mkFormVX( p, 4, v_dst, (UInt)simm5, 0, opc2, endness_host ); - } - else { // Pri_Reg - UInt lowest_lane; -@@ -5197,7 +5245,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - vassert(hregClass(i->Pin.AvSplat.src->Pvi.Reg) == HRcVec128); - v_src = vregNo(i->Pin.AvSplat.src->Pvi.Reg); - lowest_lane = (128/sz)-1; -- p = mkFormVX( p, 4, v_dst, lowest_lane, v_src, opc2 ); -+ p = mkFormVX( p, 4, v_dst, lowest_lane, v_src, opc2, endness_host ); - } - goto done; - } -@@ -5214,16 +5262,17 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* jmp fwds 2 insns if !condition */ - if (cc.test != Pct_ALWAYS) { - /* bc !ct,cf,n_bytes>>2 */ -- p = mkFormB(p, invertCondTest(cc.test), cc.flag, 8>>2, 0, 0); -+ p = mkFormB(p, invertCondTest(cc.test), cc.flag, 8>>2, 0, 0, -+ endness_host); - } - /* vmr */ -- p = mkFormVX( p, 4, v_dst, v_src, v_src, 1156 ); -+ p = mkFormVX( p, 4, v_dst, v_src, v_src, 1156, endness_host ); - goto done; - } - - case Pin_AvLdVSCR: { // mtvscr - UInt v_src = vregNo(i->Pin.AvLdVSCR.src); -- p = mkFormVX( p, 4, 0, 0, v_src, 1604 ); -+ p = mkFormVX( p, 4, 0, 0, v_src, 1604, endness_host ); - goto done; - } - -@@ -5233,23 +5282,23 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - switch (i->Pin.Dfp64Unary.op) { - case Pfp_MOV: // fmr, PPC32 p410 -- p = mkFormX( p, 63, fr_dst, 0, fr_src, 72, 0 ); -+ p = mkFormX( p, 63, fr_dst, 0, fr_src, 72, 0, endness_host ); - break; - case Pfp_DCTDP: // D32 to D64 -- p = mkFormX( p, 59, fr_dst, 0, fr_src, 258, 0 ); -+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 258, 0, endness_host ); - break; - case Pfp_DRSP: // D64 to D32 -- p = mkFormX( p, 59, fr_dst, 0, fr_src, 770, 0 ); -+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 770, 0, endness_host ); - break; - case Pfp_DCFFIX: // I64 to D64 conversion - /* ONLY WORKS ON POWER7 */ -- p = mkFormX( p, 59, fr_dst, 0, fr_src, 802, 0); -+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 802, 0, endness_host ); - break; - case Pfp_DCTFIX: // D64 to I64 conversion -- p = mkFormX( p, 59, fr_dst, 0, fr_src, 290, 0); -+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 290, 0, endness_host ); - break; - case Pfp_DXEX: // Extract exponent -- p = mkFormX( p, 59, fr_dst, 0, fr_src, 354, 0 ); -+ p = mkFormX( p, 59, fr_dst, 0, fr_src, 354, 0, endness_host ); - break; - default: - goto bad; -@@ -5264,22 +5313,22 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - switch (i->Pin.Dfp64Binary.op) { - case Pfp_DFPADD: /* dadd, dfp add, use default RM from reg ignore mode - * from the Iop instruction. */ -- p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 2, 0 ); -+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 2, 0, endness_host ); - break; - case Pfp_DFPSUB: /* dsub, dfp subtract, use default RM from reg ignore - * mode from the Iop instruction. */ -- p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 514, 0 ); -+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 514, 0, endness_host ); - break; - case Pfp_DFPMUL: /* dmul, dfp multipy, use default RM from reg ignore - * mode from the Iop instruction. */ -- p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 34, 0 ); -+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 34, 0, endness_host ); - break; - case Pfp_DFPDIV: /* ddiv, dfp divide, use default RM from reg ignore - * mode from the Iop instruction. */ -- p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 546, 0 ); -+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 546, 0, endness_host ); - break; - case Pfp_DIEX: /* diex, insert exponent */ -- p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 866, 0 ); -+ p = mkFormX( p, 59, fr_dst, fr_srcL, fr_srcR, 866, 0, endness_host ); - break; - default: - goto bad; -@@ -5296,10 +5345,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - switch (i->Pin.DfpShift.op) { - case Pfp_DSCLI: /* dscli, DFP shift left by fr_srcR */ -- p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 66, 0 ); -+ p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 66, 0, endness_host ); - break; - case Pfp_DSCRI: /* dscri, DFP shift right by fr_srcR */ -- p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 98, 0 ); -+ p = mkFormZ22( p, 59, fr_dst, fr_src, shift, 98, 0, endness_host ); - break; - default: - vex_printf("ERROR: emit_PPCInstr default case\n"); -@@ -5318,14 +5367,14 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* Setup the upper and lower registers of the source operand - * register pair. - */ -- p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0); -- p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0); -- p = mkFormX( p, 63, 10, 0, 12, 354, 0 ); -+ p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0, endness_host ); -+ p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0, endness_host ); -+ p = mkFormX( p, 63, 10, 0, 12, 354, 0, endness_host ); - - /* The instruction will put the 64-bit result in - * register 10. - */ -- p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0); -+ p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0, endness_host); - break; - default: - vex_printf("Error: emit_PPCInstr case Pin_DfpExtractExp, case inst Default\n"); -@@ -5343,16 +5392,16 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - */ - switch (i->Pin.Dfp128Unary.op) { - case Pfp_DCTQPQ: // D64 to D128, srcLo holds 64 bit operand -- p = mkFormX( p, 63, 12, 0, fr_srcLo, 72, 0); -+ p = mkFormX( p, 63, 12, 0, fr_srcLo, 72, 0, endness_host ); - -- p = mkFormX( p, 63, 10, 0, 12, 258, 0 ); -+ p = mkFormX( p, 63, 10, 0, 12, 258, 0, endness_host ); - - /* The instruction will put the 128-bit result in - * registers (10,11). Note, the operand in the instruction only - * reference the first of the two registers in the pair. - */ -- p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0); -- p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0); -+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); -+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); - break; - default: - vex_printf("Error: emit_PPCInstr case Pin_Dfp128Unary, case inst Default\ -@@ -5374,26 +5423,26 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* Setup the upper and lower registers of the source operand - * register pair. - */ -- p = mkFormX( p, 63, 10, 0, fr_dstHi, 72, 0 ); -- p = mkFormX( p, 63, 11, 0, fr_dstLo, 72, 0 ); -- p = mkFormX( p, 63, 12, 0, fr_srcRHi, 72, 0 ); -- p = mkFormX( p, 63, 13, 0, fr_srcRLo, 72, 0 ); -+ p = mkFormX( p, 63, 10, 0, fr_dstHi, 72, 0, endness_host ); -+ p = mkFormX( p, 63, 11, 0, fr_dstLo, 72, 0, endness_host ); -+ p = mkFormX( p, 63, 12, 0, fr_srcRHi, 72, 0, endness_host ); -+ p = mkFormX( p, 63, 13, 0, fr_srcRLo, 72, 0, endness_host ); - - /* Do instruction with 128-bit source operands in registers (10,11) - * and (12,13). - */ - switch (i->Pin.Dfp128Binary.op) { - case Pfp_DFPADDQ: -- p = mkFormX( p, 63, 10, 10, 12, 2, 0 ); -+ p = mkFormX( p, 63, 10, 10, 12, 2, 0, endness_host ); - break; - case Pfp_DFPSUBQ: -- p = mkFormX( p, 63, 10, 10, 12, 514, 0 ); -+ p = mkFormX( p, 63, 10, 10, 12, 514, 0, endness_host ); - break; - case Pfp_DFPMULQ: -- p = mkFormX( p, 63, 10, 10, 12, 34, 0 ); -+ p = mkFormX( p, 63, 10, 10, 12, 34, 0, endness_host ); - break; - case Pfp_DFPDIVQ: -- p = mkFormX( p, 63, 10, 10, 12, 546, 0 ); -+ p = mkFormX( p, 63, 10, 10, 12, 546, 0, endness_host ); - break; - default: - goto bad; -@@ -5403,8 +5452,8 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - * registers (10,11). Note, the operand in the instruction only - * reference the first of the two registers in the pair. - */ -- p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0); -- p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0); -+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); -+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); - goto done; - } - -@@ -5418,20 +5467,20 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - shift = i->Pin.DfpShift128.shift->Pri.Imm; - - /* setup source operand in register 12, 13 pair */ -- p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0); -- p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0); -+ p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0, endness_host); -+ p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0, endness_host); - - /* execute instruction putting result in register 10, 11 pair */ - switch (i->Pin.DfpShift128.op) { - case Pfp_DSCLIQ: /* dscliq, DFP shift left, fr_srcR is the integer - * shift amount. - */ -- p = mkFormZ22( p, 63, 10, 12, shift, 66, 0 ); -+ p = mkFormZ22( p, 63, 10, 12, shift, 66, 0, endness_host ); - break; - case Pfp_DSCRIQ: /* dscriq, DFP shift right, fr_srcR is the integer - * shift amount. - */ -- p = mkFormZ22( p, 63, 10, 12, shift, 98, 0 ); -+ p = mkFormZ22( p, 63, 10, 12, shift, 98, 0, endness_host ); - break; - default: - vex_printf("ERROR: emit_PPCInstr quad default case %d \n", -@@ -5443,8 +5492,8 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - * Note, the operand in the instruction only reference the first of - * the two registers in the pair. - */ -- p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0); -- p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0); -+ p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0, endness_host); -+ p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0, endness_host); - goto done; - } - -@@ -5458,7 +5507,7 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - rmc = r_rmc & 0x3; - - // drintx -- p = mkFormZ23(p, 59, fr_dst, r, fr_src, rmc, 99, 0); -+ p = mkFormZ23(p, 59, fr_dst, r, fr_src, rmc, 99, 0, endness_host); - goto done; - } - -@@ -5476,20 +5525,20 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* Setup the upper and lower registers of the source operand - * register pair. - */ -- p = mkFormX(p, 63, 12, 0, fr_srcHi, 72, 0); -- p = mkFormX(p, 63, 13, 0, fr_srcLo, 72, 0); -+ p = mkFormX(p, 63, 12, 0, fr_srcHi, 72, 0, endness_host); -+ p = mkFormX(p, 63, 13, 0, fr_srcLo, 72, 0, endness_host); - - /* Do drintx instruction with 128-bit source operands in - * registers (12,13). - */ -- p = mkFormZ23(p, 63, 10, r, 12, rmc, 99, 0); -+ p = mkFormZ23(p, 63, 10, r, 12, rmc, 99, 0, endness_host); - - /* The instruction will put the 128-bit result in - * registers (10,11). Note, the operand in the instruction only - * reference the first of the two registers in the pair. - */ -- p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0); -- p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0); -+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); -+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); - goto done; - } - -@@ -5503,10 +5552,10 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - switch (i->Pin.DfpQuantize.op) { - case Pfp_DQUA: -- p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 3, 0); -+ p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 3, 0, endness_host); - break; - case Pfp_RRDTR: -- p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 35, 0); -+ p = mkFormZ23(p, 59, fr_dst, fr_srcL, fr_srcR, rmc, 35, 0, endness_host); - break; - default: - break; -@@ -5526,20 +5575,20 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - * register pairs. Note, left source operand passed in via the - * dst register pair. - */ -- p = mkFormX(p, 63, 10, 0, fr_dst_hi, 72, 0); -- p = mkFormX(p, 63, 11, 0, fr_dst_lo, 72, 0); -- p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0); -- p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0); -+ p = mkFormX(p, 63, 10, 0, fr_dst_hi, 72, 0, endness_host); -+ p = mkFormX(p, 63, 11, 0, fr_dst_lo, 72, 0, endness_host); -+ p = mkFormX(p, 63, 12, 0, fr_src_hi, 72, 0, endness_host); -+ p = mkFormX(p, 63, 13, 0, fr_src_lo, 72, 0, endness_host); - - /* Do dquaq instruction with 128-bit source operands in - * registers (12,13). - */ - switch (i->Pin.DfpQuantize128.op) { - case Pfp_DQUAQ: -- p = mkFormZ23(p, 63, 10, 10, 12, rmc, 3, 0); -+ p = mkFormZ23(p, 63, 10, 10, 12, rmc, 3, 0, endness_host); - break; - case Pfp_DRRNDQ: -- p = mkFormZ23(p, 63, 10, 10, 12, rmc, 35, 0); -+ p = mkFormZ23(p, 63, 10, 10, 12, rmc, 35, 0, endness_host); - break; - default: - vpanic("Pin_DfpQuantize128: default case, couldn't find inst to issue \n"); -@@ -5550,8 +5599,8 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - * registers (10,11). Note, the operand in the instruction only - * reference the first of the two registers in the pair. - */ -- p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0); -- p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0); -+ p = mkFormX(p, 63, fr_dst_hi, 0, 10, 72, 0, endness_host); -+ p = mkFormX(p, 63, fr_dst_lo, 0, 11, 72, 0, endness_host); - goto done; - } - -@@ -5563,24 +5612,24 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* Setup the upper and lower registers of the source operand - * register pair. - */ -- p = mkFormX( p, 63, 10, 0, fr_dst, 72, 0 ); -- p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0 ); -- p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0 ); -+ p = mkFormX( p, 63, 10, 0, fr_dst, 72, 0, endness_host ); -+ p = mkFormX( p, 63, 12, 0, fr_srcHi, 72, 0, endness_host ); -+ p = mkFormX( p, 63, 13, 0, fr_srcLo, 72, 0, endness_host ); - - /* Do instruction with 128-bit source operands in registers (10,11) */ - switch (i->Pin.Dfp128Binary.op) { - case Pfp_DRDPQ: -- p = mkFormX( p, 63, 10, 0, 12, 770, 0 ); -+ p = mkFormX( p, 63, 10, 0, 12, 770, 0, endness_host ); - break; - case Pfp_DCTFIXQ: -- p = mkFormX( p, 63, 10, 0, 12, 290, 0 ); -+ p = mkFormX( p, 63, 10, 0, 12, 290, 0, endness_host ); - break; - default: - goto bad; - } - - /* The instruction will put the 64-bit result in registers 10. */ -- p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0); -+ p = mkFormX(p, 63, fr_dst, 0, 10, 72, 0, endness_host); - goto done; - } - -@@ -5591,15 +5640,15 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - - switch (i->Pin.Dfp128Binary.op) { - case Pfp_DCFFIXQ: -- p = mkFormX( p, 63, 10, 11, fr_src, 802, 0 ); -+ p = mkFormX( p, 63, 10, 11, fr_src, 802, 0, endness_host ); - break; - default: - goto bad; - } - - /* The instruction will put the 64-bit result in registers 10, 11. */ -- p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0); -- p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0); -+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); -+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); - goto done; - } - -@@ -5613,17 +5662,17 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* The left operand is a single F64 value, the right is an F128 - * register pair. - */ -- p = mkFormX(p, 63, 10, 0, fr_srcL, 72, 0); -- p = mkFormX(p, 63, 12, 0, fr_srcRHi, 72, 0); -- p = mkFormX(p, 63, 13, 0, fr_srcRLo, 72, 0); -- p = mkFormX(p, 63, 10, 10, 12, 866, 0 ); -+ p = mkFormX(p, 63, 10, 0, fr_srcL, 72, 0, endness_host); -+ p = mkFormX(p, 63, 12, 0, fr_srcRHi, 72, 0, endness_host); -+ p = mkFormX(p, 63, 13, 0, fr_srcRLo, 72, 0, endness_host); -+ p = mkFormX(p, 63, 10, 10, 12, 866, 0, endness_host ); - - /* The instruction will put the 128-bit result into - * registers (10,11). Note, the operand in the instruction only - * reference the first of the two registers in the pair. - */ -- p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0); -- p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0); -+ p = mkFormX(p, 63, fr_dstHi, 0, 10, 72, 0, endness_host); -+ p = mkFormX(p, 63, fr_dstLo, 0, 11, 72, 0, endness_host); - goto done; - } - -@@ -5634,14 +5683,14 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UInt fr_srcR = fregNo(i->Pin.Dfp64Cmp.srcR); - vassert(crfD < 8); - // dcmpo, dcmpu -- p = mkFormX(p, 59, crfD<<2, fr_srcL, fr_srcR, 130, 0); -+ p = mkFormX(p, 59, crfD<<2, fr_srcL, fr_srcR, 130, 0, endness_host); - - // mfcr (mv CR to r_dst) -- p = mkFormX(p, 31, r_dst, 0, 0, 19, 0); -+ p = mkFormX(p, 31, r_dst, 0, 0, 19, 0, endness_host); - - // rlwinm r_dst,r_dst,8,28,31 - // => rotate field 1 to bottomw of word, masking out upper 28 -- p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0); -+ p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0, endness_host); - goto done; - } - -@@ -5657,19 +5706,19 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - /* Setup the upper and lower registers of the source operand - * register pair. - */ -- p = mkFormX(p, 63, 10, 0, fr_srcL_hi, 72, 0); -- p = mkFormX(p, 63, 11, 0, fr_srcL_lo, 72, 0); -- p = mkFormX(p, 63, 12, 0, fr_srcR_hi, 72, 0); -- p = mkFormX(p, 63, 13, 0, fr_srcR_lo, 72, 0); -+ p = mkFormX(p, 63, 10, 0, fr_srcL_hi, 72, 0, endness_host); -+ p = mkFormX(p, 63, 11, 0, fr_srcL_lo, 72, 0, endness_host); -+ p = mkFormX(p, 63, 12, 0, fr_srcR_hi, 72, 0, endness_host); -+ p = mkFormX(p, 63, 13, 0, fr_srcR_lo, 72, 0, endness_host); - -- p = mkFormX(p, 63, crfD<<2, 10, 12, 130, 0); -+ p = mkFormX(p, 63, crfD<<2, 10, 12, 130, 0, endness_host); - - // mfcr (mv CR to r_dst) -- p = mkFormX(p, 31, r_dst, 0, 0, 19, 0); -+ p = mkFormX(p, 31, r_dst, 0, 0, 19, 0, endness_host); - - // rlwinm r_dst,r_dst,8,28,31 - // => rotate field 1 to bottomw of word, masking out upper 28 -- p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0); -+ p = mkFormM(p, 21, r_dst, r_dst, 8, 28, 31, 0, endness_host); - goto done; - } - -@@ -5689,21 +5738,24 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - UChar* p0 = p; - /* lwz r30, amCounter */ - p = do_load_or_store_word32(p, True/*isLoad*/, /*r*/30, -- i->Pin.EvCheck.amCounter, mode64); -+ i->Pin.EvCheck.amCounter, mode64, -+ endness_host); - /* addic. r30,r30,-1 */ -- p = emit32(p, 0x37DEFFFF); -+ p = emit32(p, 0x37DEFFFF, endness_host); - /* stw r30, amCounter */ - p = do_load_or_store_word32(p, False/*!isLoad*/, /*r*/30, -- i->Pin.EvCheck.amCounter, mode64); -+ i->Pin.EvCheck.amCounter, mode64, -+ endness_host); - /* bge nofail */ -- p = emit32(p, 0x40800010); -+ p = emit32(p, 0x40800010, endness_host); - /* lwz/ld r30, amFailAddr */ - p = do_load_or_store_machine_word(p, True/*isLoad*/, /*r*/30, -- i->Pin.EvCheck.amFailAddr, mode64); -+ i->Pin.EvCheck.amFailAddr, mode64, -+ endness_host); - /* mtctr r30 */ -- p = mkFormXFX(p, /*r*/30, 9, 467); -+ p = mkFormXFX(p, /*r*/30, 9, 467, endness_host); - /* bctr */ -- p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0); -+ p = mkFormXL(p, 19, Pct_ALWAYS, 0, 0, 528, 0, endness_host); - /* nofail: */ - - /* Crosscheck */ -@@ -5733,19 +5785,19 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_p - */ - if (mode64) { - p = mkLoadImm_EXACTLY2or5( -- p, /*r*/30, 0x6555655565556555ULL, True/*mode64*/); -- p = emit32(p, 0xEBBE0000); -- p = emit32(p, 0x3BBD0001); -- p = emit32(p, 0xFBBE0000); -+ p, /*r*/30, 0x6555655565556555ULL, True/*mode64*/, endness_host); -+ p = emit32(p, 0xEBBE0000, endness_host); -+ p = emit32(p, 0x3BBD0001, endness_host); -+ p = emit32(p, 0xFBBE0000, endness_host); - } else { - p = mkLoadImm_EXACTLY2or5( -- p, /*r*/30, 0x65556555ULL, False/*!mode64*/); -- p = emit32(p, 0x83BE0004); -- p = emit32(p, 0x37BD0001); -- p = emit32(p, 0x93BE0004); -- p = emit32(p, 0x83BE0000); -- p = emit32(p, 0x7FBD0194); -- p = emit32(p, 0x93BE0000); -+ p, /*r*/30, 0x65556555ULL, False/*!mode64*/, endness_host); -+ p = emit32(p, 0x83BE0004, endness_host); -+ p = emit32(p, 0x37BD0001, endness_host); -+ p = emit32(p, 0x93BE0004, endness_host); -+ p = emit32(p, 0x83BE0000, endness_host); -+ p = emit32(p, 0x7FBD0194, endness_host); -+ p = emit32(p, 0x93BE0000, endness_host); - } - /* Tell the caller .. */ - vassert(!(*is_profInc)); -@@ -5787,7 +5839,8 @@ VexInvalRange chainXDirect_PPC ( VexEndn - Bool mode64 ) - { - if (mode64) { -- vassert(endness_host == VexEndnessBE); /* later: or LE */ -+ vassert((endness_host == VexEndnessBE) || -+ (endness_host == VexEndnessLE)); - } else { - vassert(endness_host == VexEndnessBE); - } -@@ -5805,9 +5858,9 @@ VexInvalRange chainXDirect_PPC ( VexEndn - vassert(0 == (3 & (HWord)p)); - vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, - Ptr_to_ULong(disp_cp_chain_me_EXPECTED), -- mode64)); -- vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x7FC903A6); -- vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x4E800421); -+ mode64, endness_host)); -+ vassert(fetch32(p + (mode64 ? 20 : 8) + 0, endness_host) == 0x7FC903A6); -+ vassert(fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800421); - /* And what we want to change it to is: - imm32/64-fixed r30, place_to_jump_to - mtctr r30 -@@ -5819,9 +5872,10 @@ VexInvalRange chainXDirect_PPC ( VexEndn - The replacement has the same length as the original. - */ - p = mkLoadImm_EXACTLY2or5(p, /*r*/30, -- Ptr_to_ULong(place_to_jump_to), mode64); -- p = emit32(p, 0x7FC903A6); -- p = emit32(p, 0x4E800420); -+ Ptr_to_ULong(place_to_jump_to), mode64, -+ endness_host); -+ p = emit32(p, 0x7FC903A6, endness_host); -+ p = emit32(p, 0x4E800420, endness_host); - - Int len = p - (UChar*)place_to_chain; - vassert(len == (mode64 ? 28 : 16)); /* stay sane */ -@@ -5839,7 +5893,8 @@ VexInvalRange unchainXDirect_PPC ( VexEn - Bool mode64 ) - { - if (mode64) { -- vassert(endness_host == VexEndnessBE); /* later: or LE */ -+ vassert((endness_host == VexEndnessBE) || -+ (endness_host == VexEndnessLE)); - } else { - vassert(endness_host == VexEndnessBE); - } -@@ -5857,9 +5912,9 @@ VexInvalRange unchainXDirect_PPC ( VexEn - vassert(0 == (3 & (HWord)p)); - vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, - Ptr_to_ULong(place_to_jump_to_EXPECTED), -- mode64)); -- vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x7FC903A6); -- vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x4E800420); -+ mode64, endness_host)); -+ vassert(fetch32(p + (mode64 ? 20 : 8) + 0, endness_host) == 0x7FC903A6); -+ vassert(fetch32(p + (mode64 ? 20 : 8) + 4, endness_host) == 0x4E800420); - /* And what we want to change it to is: - imm32/64-fixed r30, disp_cp_chain_me - mtctr r30 -@@ -5871,9 +5926,10 @@ VexInvalRange unchainXDirect_PPC ( VexEn - The replacement has the same length as the original. - */ - p = mkLoadImm_EXACTLY2or5(p, /*r*/30, -- Ptr_to_ULong(disp_cp_chain_me), mode64); -- p = emit32(p, 0x7FC903A6); -- p = emit32(p, 0x4E800421); -+ Ptr_to_ULong(disp_cp_chain_me), mode64, -+ endness_host); -+ p = emit32(p, 0x7FC903A6, endness_host); -+ p = emit32(p, 0x4E800421, endness_host); - - Int len = p - (UChar*)place_to_unchain; - vassert(len == (mode64 ? 28 : 16)); /* stay sane */ -@@ -5890,7 +5946,8 @@ VexInvalRange patchProfInc_PPC ( VexEndn - Bool mode64 ) - { - if (mode64) { -- vassert(endness_host == VexEndnessBE); /* later: or LE */ -+ vassert((endness_host == VexEndnessBE) || -+ (endness_host == VexEndnessLE)); - } else { - vassert(endness_host == VexEndnessBE); - } -@@ -5901,27 +5958,29 @@ VexInvalRange patchProfInc_PPC ( VexEndn - Int len = 0; - if (mode64) { - vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, -- 0x6555655565556555ULL, True/*mode64*/)); -- vassert(fetch32(p + 20) == 0xEBBE0000); -- vassert(fetch32(p + 24) == 0x3BBD0001); -- vassert(fetch32(p + 28) == 0xFBBE0000); -+ 0x6555655565556555ULL, True/*mode64*/, -+ endness_host)); -+ vassert(fetch32(p + 20, endness_host) == 0xEBBE0000); -+ vassert(fetch32(p + 24, endness_host) == 0x3BBD0001); -+ vassert(fetch32(p + 28, endness_host) == 0xFBBE0000); - p = mkLoadImm_EXACTLY2or5(p, /*r*/30, - Ptr_to_ULong(location_of_counter), -- True/*mode64*/); -+ True/*mode64*/, endness_host); - len = p - (UChar*)place_to_patch; - vassert(len == 20); - } else { - vassert(isLoadImm_EXACTLY2or5(p, /*r*/30, -- 0x65556555ULL, False/*!mode64*/)); -- vassert(fetch32(p + 8) == 0x83BE0004); -- vassert(fetch32(p + 12) == 0x37BD0001); -- vassert(fetch32(p + 16) == 0x93BE0004); -- vassert(fetch32(p + 20) == 0x83BE0000); -- vassert(fetch32(p + 24) == 0x7FBD0194); -- vassert(fetch32(p + 28) == 0x93BE0000); -+ 0x65556555ULL, False/*!mode64*/, -+ endness_host)); -+ vassert(fetch32(p + 8, endness_host) == 0x83BE0004); -+ vassert(fetch32(p + 12, endness_host) == 0x37BD0001); -+ vassert(fetch32(p + 16, endness_host) == 0x93BE0004); -+ vassert(fetch32(p + 20, endness_host) == 0x83BE0000); -+ vassert(fetch32(p + 24, endness_host) == 0x7FBD0194); -+ vassert(fetch32(p + 28, endness_host) == 0x93BE0000); - p = mkLoadImm_EXACTLY2or5(p, /*r*/30, - Ptr_to_ULong(location_of_counter), -- False/*!mode64*/); -+ False/*!mode64*/, endness_host); - len = p - (UChar*)place_to_patch; - vassert(len == 8); - } -Index: VEX/priv/host_ppc_isel.c -=================================================================== ---- VEX/priv/host_ppc_isel.c.orig -+++ VEX/priv/host_ppc_isel.c -@@ -379,8 +379,10 @@ static HReg newVRegV ( ISelEnv* env ) - */ - /* 32-bit mode: compute an I8/I16/I32 into a GPR. - 64-bit mode: compute an I8/I16/I32/I64 into a GPR. */ --static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e ); --static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e ); -+static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - /* 32-bit mode: Compute an I8/I16/I32 into a RH - (reg-or-halfword-immediate). -@@ -392,26 +394,34 @@ static HReg iselWordExpr_R - return can have their sign inverted if need be. - */ - static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, -- Bool syned, IRExpr* e ); -+ Bool syned, IRExpr* e, -+ IREndness IEndianess ); - static PPCRH* iselWordExpr_RH ( ISelEnv* env, -- Bool syned, IRExpr* e ); -+ Bool syned, IRExpr* e, -+ IREndness IEndianess ); - - /* 32-bit mode: compute an I32 into a RI (reg or 32-bit immediate). - 64-bit mode: compute an I64 into a RI (reg or 64-bit immediate). */ --static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e ); --static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e ); -+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - /* In 32 bit mode ONLY, compute an I8 into a - reg-or-5-bit-unsigned-immediate, the latter being an immediate in - the range 1 .. 31 inclusive. Used for doing shift amounts. */ --static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e ); --static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e ); -+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - /* In 64-bit mode ONLY, compute an I8 into a - reg-or-6-bit-unsigned-immediate, the latter being an immediate in - the range 1 .. 63 inclusive. Used for doing shift amounts. */ --static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e ); --static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e ); -+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - /* 32-bit mode: compute an I32 into an AMode. - 64-bit mode: compute an I64 into an AMode. -@@ -424,52 +434,75 @@ static PPCRH* iselWordExpr_RH6u - - Since there are no such restrictions on 32-bit insns, xferTy is - ignored for 32-bit code generation. */ --static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType xferTy ); --static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy ); -+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, -+ IRType xferTy, -+ IREndness IEndianess ); -+static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, -+ IRType xferTy, -+ IREndness IEndianess ); - - static void iselInt128Expr_to_32x4_wrk ( HReg* rHi, HReg* rMedHi, - HReg* rMedLo, HReg* rLo, -- ISelEnv* env, IRExpr* e ); -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - static void iselInt128Expr_to_32x4 ( HReg* rHi, HReg* rMedHi, - HReg* rMedLo, HReg* rLo, -- ISelEnv* env, IRExpr* e ); -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - - /* 32-bit mode ONLY: compute an I64 into a GPR pair. */ --static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ); --static void iselInt64Expr ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ); -+static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static void iselInt64Expr ( HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - /* 64-bit mode ONLY: compute an I128 into a GPR64 pair. */ - static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ); --static void iselInt128Expr ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ); -- --static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ); --static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e ); -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - --static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ); --static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ); -- --static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ); --static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ); -+static void iselInt128Expr ( HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - --static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ); --static HReg iselVecExpr ( ISelEnv* env, IRExpr* e ); -+static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+ -+static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static HReg iselDblExpr ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+ -+static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static HReg iselFltExpr ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+ -+static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static HReg iselVecExpr ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - /* 64-bit mode ONLY. */ --static HReg iselDfp32Expr_wrk ( ISelEnv* env, IRExpr* e ); --static HReg iselDfp32Expr ( ISelEnv* env, IRExpr* e ); --static HReg iselDfp64Expr_wrk ( ISelEnv* env, IRExpr* e ); --static HReg iselDfp64Expr ( ISelEnv* env, IRExpr* e ); -+static HReg iselDfp32Expr_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static HReg iselDfp32Expr ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static HReg iselDfp64Expr_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); -+static HReg iselDfp64Expr ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ); - - /* 64-bit mode ONLY: compute an D128 into a GPR64 pair. */ - static void iselDfp128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, -- IRExpr* e ); -+ IRExpr* e, IREndness IEndianess ); - static void iselDfp128Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, -- IRExpr* e ); -+ IRExpr* e, IREndness IEndianess ); - - /*---------------------------------------------------------*/ - /*--- ISEL: Misc helpers ---*/ -@@ -596,7 +629,7 @@ static PPCAMode* advance4 ( ISelEnv* env - guest state. */ - static - PPCAMode* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr, -- IRExpr* off, Int bias ) -+ IRExpr* off, Int bias, IREndness IEndianess ) - { - HReg rtmp, roff; - Int elemSz = sizeofIRType(descr->elemTy); -@@ -628,7 +661,7 @@ PPCAMode* genGuestArrayOffset ( ISelEnv* - addi %tmp, %tmp, base - ... Baseblockptr + %tmp ... - */ -- roff = iselWordExpr_R(env, off); -+ roff = iselWordExpr_R(env, off, IEndianess); - rtmp = newVRegI(env); - addInstr(env, PPCInstr_Alu( - Palu_ADD, -@@ -685,7 +718,8 @@ void doHelperCall ( /*OUT*/UInt* stack - /*OUT*/RetLoc* retloc, - ISelEnv* env, - IRExpr* guard, -- IRCallee* cee, IRType retTy, IRExpr** args ) -+ IRCallee* cee, IRType retTy, IRExpr** args, -+ IREndness IEndianess) - { - PPCCondCode cc; - HReg argregs[PPC_N_REGPARMS]; -@@ -858,14 +892,15 @@ void doHelperCall ( /*OUT*/UInt* stack - argiregs |= (1 << (argreg+3)); - addInstr(env, - mk_iMOVds_RR( argregs[argreg], -- iselWordExpr_R(env, arg) )); -+ iselWordExpr_R(env, arg, -+ IEndianess) )); - } else { // Ity_I64 in 32-bit mode - HReg rHi, rLo; - if ((argreg%2) == 1) - // ppc32 ELF abi spec for passing LONG_LONG - argreg++; // XXX: odd argreg => even rN - vassert(argreg < PPC_N_REGPARMS-1); -- iselInt64Expr(&rHi,&rLo, env, arg); -+ iselInt64Expr(&rHi,&rLo, env, arg, IEndianess); - argiregs |= (1 << (argreg+3)); - addInstr(env, mk_iMOVds_RR( argregs[argreg++], rHi )); - argiregs |= (1 << (argreg+3)); -@@ -874,7 +909,8 @@ void doHelperCall ( /*OUT*/UInt* stack - } else { // mode64 - argiregs |= (1 << (argreg+3)); - addInstr(env, mk_iMOVds_RR( argregs[argreg], -- iselWordExpr_R(env, arg) )); -+ iselWordExpr_R(env, arg, -+ IEndianess) )); - } - argreg++; - } /* if (arg == IRExprP__BBPR) */ -@@ -934,19 +970,19 @@ void doHelperCall ( /*OUT*/UInt* stack - vassert(ty == Ity_I32 || ty == Ity_I64); - if (!mode64) { - if (ty == Ity_I32) { -- tmpregs[argreg] = iselWordExpr_R(env, arg); -+ tmpregs[argreg] = iselWordExpr_R(env, arg, IEndianess); - } else { // Ity_I64 in 32-bit mode - HReg rHi, rLo; - if ((argreg%2) == 1) - // ppc32 ELF abi spec for passing LONG_LONG - argreg++; // XXX: odd argreg => even rN - vassert(argreg < PPC_N_REGPARMS-1); -- iselInt64Expr(&rHi,&rLo, env, arg); -+ iselInt64Expr(&rHi,&rLo, env, arg, IEndianess); - tmpregs[argreg++] = rHi; - tmpregs[argreg] = rLo; - } - } else { // mode64 -- tmpregs[argreg] = iselWordExpr_R(env, arg); -+ tmpregs[argreg] = iselWordExpr_R(env, arg, IEndianess); - } - } - argreg++; -@@ -963,7 +999,7 @@ void doHelperCall ( /*OUT*/UInt* stack - && guard->Iex.Const.con->Ico.U1 == True) { - /* unconditional -- do nothing */ - } else { -- cc = iselCondCode( env, guard ); -+ cc = iselCondCode( env, guard, IEndianess ); - } - } - -@@ -1125,7 +1161,8 @@ static HReg roundModeIRtoPPC ( ISelEnv* - on any block with any sign of floating point activity. - */ - static --void _set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode, Bool dfp_rm ) -+void _set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode, Bool dfp_rm, -+ IREndness IEndianess ) - { - HReg fr_src = newVRegF(env); - HReg r_src; -@@ -1149,7 +1186,7 @@ void _set_FPU_rounding_mode ( ISelEnv* e - 0x0 - so we can set the whole register at once (faster). */ - - // Resolve rounding mode and convert to PPC representation -- r_src = roundModeIRtoPPC( env, iselWordExpr_R(env, mode) ); -+ r_src = roundModeIRtoPPC( env, iselWordExpr_R(env, mode, IEndianess) ); - - // gpr -> fpr - if (env->mode64) { -@@ -1176,14 +1213,16 @@ void _set_FPU_rounding_mode ( ISelEnv* e - addInstr(env, PPCInstr_FpLdFPSCR( fr_src, dfp_rm )); - } - --static void set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode ) -+static void set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode, -+ IREndness IEndianess ) - { -- _set_FPU_rounding_mode(env, mode, False); -+ _set_FPU_rounding_mode(env, mode, False, IEndianess); - } - --static void set_FPU_DFP_rounding_mode ( ISelEnv* env, IRExpr* mode ) -+static void set_FPU_DFP_rounding_mode ( ISelEnv* env, IRExpr* mode, -+ IREndness IEndianess ) - { -- _set_FPU_rounding_mode(env, mode, True); -+ _set_FPU_rounding_mode(env, mode, True, IEndianess); - } - - -@@ -1218,11 +1257,11 @@ static HReg generate_ones_V128 ( ISelEnv - - uses AvSplat(imm) for imms up to simm6. - otherwise must use store reg & load vector - */ --static HReg mk_AvDuplicateRI( ISelEnv* env, IRExpr* e ) -+static HReg mk_AvDuplicateRI( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { - HReg r_src; - HReg dst = newVRegV(env); -- PPCRI* ri = iselWordExpr_RI(env, e); -+ PPCRI* ri = iselWordExpr_RI(env, e, IEndianess); - IRType ty = typeOfIRExpr(env->type_env,e); - UInt sz = (ty == Ity_I8) ? 8 : (ty == Ity_I16) ? 16 : 32; - vassert(ty == Ity_I8 || ty == Ity_I16 || ty == Ity_I32); -@@ -1269,44 +1308,43 @@ static HReg mk_AvDuplicateRI( ISelEnv* e - r_src = ri->Pri.Reg; - } - -- /* default case: store r_src in lowest lane of 16-aligned mem, -- load vector, splat lowest lane to dst */ - { -- /* CAB: Maybe faster to store r_src multiple times (sz dependent), -- and simply load the vector? */ -+ /* Store r_src multiple times (sz dependent); then load the dest vector. */ - HReg r_aligned16; -- HReg v_src = newVRegV(env); -- PPCAMode *am_off12; -+ PPCAMode *am_offset, *am_offset_zero; - - sub_from_sp( env, 32 ); // Move SP down - /* Get a 16-aligned address within our stack space */ - r_aligned16 = get_sp_aligned16( env ); -- am_off12 = PPCAMode_IR( 12, r_aligned16 ); - -- /* Store r_src in low word of 16-aligned mem */ -- addInstr(env, PPCInstr_Store( 4, am_off12, r_src, env->mode64 )); -+ Int i; -+ Int stride = (sz == 8) ? 1 : (sz == 16) ? 2 : 4; -+ UChar num_bytes_to_store = stride; -+ am_offset_zero = PPCAMode_IR( 0, r_aligned16 ); -+ am_offset = am_offset_zero; -+ for (i = 0; i < 16; i+=stride, am_offset = PPCAMode_IR( i, r_aligned16)) { -+ addInstr(env, PPCInstr_Store( num_bytes_to_store, am_offset, r_src, env->mode64 )); -+ } - -- /* Load src to vector[low lane] */ -- addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, v_src, am_off12 ) ); -+ /* Effectively splat the r_src value to dst */ -+ addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_offset_zero ) ); - add_to_sp( env, 32 ); // Reset SP - -- /* Finally, splat v_src[low_lane] to dst */ -- addInstr(env, PPCInstr_AvSplat(sz, dst, PPCVI5s_Reg(v_src))); - return dst; - } - } - - - /* for each lane of vSrc: lane == nan ? laneX = all 1's : all 0's */ --static HReg isNan ( ISelEnv* env, HReg vSrc ) -+static HReg isNan ( ISelEnv* env, HReg vSrc, IREndness IEndianess ) - { - HReg zeros, msk_exp, msk_mnt, expt, mnts, vIsNan; - - vassert(hregClass(vSrc) == HRcVec128); - -- zeros = mk_AvDuplicateRI(env, mkU32(0)); -- msk_exp = mk_AvDuplicateRI(env, mkU32(0x7F800000)); -- msk_mnt = mk_AvDuplicateRI(env, mkU32(0x7FFFFF)); -+ zeros = mk_AvDuplicateRI(env, mkU32(0), IEndianess); -+ msk_exp = mk_AvDuplicateRI(env, mkU32(0x7F800000), IEndianess); -+ msk_mnt = mk_AvDuplicateRI(env, mkU32(0x7FFFFF), IEndianess); - expt = newVRegV(env); - mnts = newVRegV(env); - vIsNan = newVRegV(env); -@@ -1342,9 +1380,9 @@ static HReg isNan ( ISelEnv* env, HReg v - if necessary. - */ - --static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e ) -+static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { -- HReg r = iselWordExpr_R_wrk(env, e); -+ HReg r = iselWordExpr_R_wrk(env, e, IEndianess); - /* sanity checks ... */ - # if 0 - vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -@@ -1356,7 +1394,8 @@ static HReg iselWordExpr_R ( ISelEnv* en - } - - /* DO NOT CALL THIS DIRECTLY ! */ --static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e ) -+static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - Bool mode64 = env->mode64; - MatchInfo mi; -@@ -1376,10 +1415,11 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iex_Load: { - HReg r_dst; - PPCAMode* am_addr; -- if (e->Iex.Load.end != Iend_BE) -+ if (e->Iex.Load.end != IEndianess) - goto irreducible; - r_dst = newVRegI(env); -- am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/ ); -+ am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/, -+ IEndianess ); - addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)), - r_dst, am_addr, mode64 )); - return r_dst; -@@ -1410,17 +1450,17 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - values are on the second operand. */ - if (aluOp != Palu_INVALID) { - HReg r_dst = newVRegI(env); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); - PPCRH* ri_srcR = NULL; - /* get right arg into an RH, in the appropriate way */ - switch (aluOp) { - case Palu_ADD: case Palu_SUB: - ri_srcR = iselWordExpr_RH(env, True/*signed*/, -- e->Iex.Binop.arg2); -+ e->Iex.Binop.arg2, IEndianess); - break; - case Palu_AND: case Palu_OR: case Palu_XOR: - ri_srcR = iselWordExpr_RH(env, False/*signed*/, -- e->Iex.Binop.arg2); -+ e->Iex.Binop.arg2, IEndianess); - break; - default: - vpanic("iselWordExpr_R_wrk-aluOp-arg2"); -@@ -1443,15 +1483,15 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - /* we assume any literal values are on the second operand. */ - if (shftOp != Pshft_INVALID) { - HReg r_dst = newVRegI(env); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); - PPCRH* ri_srcR = NULL; - /* get right arg into an RH, in the appropriate way */ - switch (shftOp) { - case Pshft_SHL: case Pshft_SHR: case Pshft_SAR: - if (!mode64) -- ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2); -+ ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2, IEndianess); - else -- ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); -+ ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2, IEndianess); - break; - default: - vpanic("iselIntExpr_R_wrk-shftOp-arg2"); -@@ -1492,8 +1532,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - e->Iex.Binop.op == Iop_DivU32E) { - Bool syned = toBool((e->Iex.Binop.op == Iop_DivS32) || (e->Iex.Binop.op == Iop_DivS32E)); - HReg r_dst = newVRegI(env); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - addInstr( env, - PPCInstr_Div( ( ( e->Iex.Binop.op == Iop_DivU32E ) - || ( e->Iex.Binop.op == Iop_DivS32E ) ) ? True -@@ -1510,8 +1550,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - || e->Iex.Binop.op == Iop_DivU64E ) { - Bool syned = toBool((e->Iex.Binop.op == Iop_DivS64) ||(e->Iex.Binop.op == Iop_DivS64E)); - HReg r_dst = newVRegI(env); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - vassert(mode64); - addInstr( env, - PPCInstr_Div( ( ( e->Iex.Binop.op == Iop_DivS64E ) -@@ -1532,8 +1572,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - Bool syned = False; - Bool sz32 = (e->Iex.Binop.op != Iop_Mul64); - HReg r_dst = newVRegI(env); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_MulL(syned, False/*lo32*/, sz32, - r_dst, r_srcL, r_srcR)); - return r_dst; -@@ -1547,8 +1587,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - HReg tHi = newVRegI(env); - HReg r_dst = newVRegI(env); - Bool syned = toBool(e->Iex.Binop.op == Iop_MullS32); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/, - False/*lo32*/, True/*32bit mul*/, - tLo, r_srcL, r_srcR)); -@@ -1567,8 +1607,9 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - || e->Iex.Binop.op == Iop_CmpORD32U) { - Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD32S); - HReg dst = newVRegI(env); -- HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2); -+ HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/, - 7/*cr*/, srcL, srcR)); - addInstr(env, PPCInstr_MfCR(dst)); -@@ -1581,8 +1622,9 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - || e->Iex.Binop.op == Iop_CmpORD64U) { - Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD64S); - HReg dst = newVRegI(env); -- HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2); -+ HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, -+ IEndianess); - vassert(mode64); - addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/, - 7/*cr*/, srcL, srcR)); -@@ -1593,8 +1635,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - } - - if (e->Iex.Binop.op == Iop_Max32U) { -- HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - HReg rdst = newVRegI(env); - PPCCondCode cc = mk_PPCCondCode( Pct_TRUE, Pcf_7LT ); - addInstr(env, mk_iMOVds_RR(rdst, r1)); -@@ -1605,8 +1647,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - } - - if (e->Iex.Binop.op == Iop_32HLto64) { -- HReg r_Hi = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_Lo = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_Hi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_Lo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - HReg r_Tmp = newVRegI(env); - HReg r_dst = newVRegI(env); - HReg msk = newVRegI(env); -@@ -1637,18 +1679,20 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - HReg r_ccIR_b6 = newVRegI(env); - - if (e->Iex.Binop.op == Iop_CmpF64) { -- fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1); -- fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2); -+ fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess); -+ fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_FpCmp(r_ccPPC, fr_srcL, fr_srcR)); - - } else if (e->Iex.Binop.op == Iop_CmpD64) { -- fr_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1); -- fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2); -+ fr_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess); -+ fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_Dfp64Cmp(r_ccPPC, fr_srcL, fr_srcR)); - - } else { // e->Iex.Binop.op == Iop_CmpD128 -- iselDfp128Expr(&fr_srcL, &fr_srcL_lo, env, e->Iex.Binop.arg1); -- iselDfp128Expr(&fr_srcR, &fr_srcR_lo, env, e->Iex.Binop.arg2); -+ iselDfp128Expr(&fr_srcL, &fr_srcL_lo, env, e->Iex.Binop.arg1, -+ IEndianess); -+ iselDfp128Expr(&fr_srcR, &fr_srcR_lo, env, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_Dfp128Cmp(r_ccPPC, fr_srcL, fr_srcL_lo, - fr_srcR, fr_srcR_lo)); - } -@@ -1705,12 +1749,12 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - /* This works in both mode64 and mode32. */ - HReg r1 = StackFramePtr(env->mode64); - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); -- HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg ftmp = newVRegF(env); - HReg idst = newVRegI(env); - - /* Set host rounding mode */ -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - - sub_from_sp( env, 16 ); - addInstr(env, PPCInstr_FpCftI(False/*F->I*/, True/*int32*/, -@@ -1736,12 +1780,13 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - if (mode64) { - HReg r1 = StackFramePtr(env->mode64); - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); -- HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2, -+ IEndianess); - HReg idst = newVRegI(env); - HReg ftmp = newVRegF(env); - - /* Set host rounding mode */ -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - - sub_from_sp( env, 16 ); - addInstr(env, PPCInstr_FpCftI(False/*F->I*/, False/*int64*/, -@@ -1761,12 +1806,12 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - if (e->Iex.Binop.op == Iop_D64toI64S ) { - HReg r1 = StackFramePtr(env->mode64); - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); -- HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess); - HReg idst = newVRegI(env); - HReg ftmp = newVRegF(env); - - /* Set host rounding mode */ -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - addInstr(env, PPCInstr_Dfp64Unary(Pfp_DCTFIX, ftmp, fr_src)); - sub_from_sp( env, 16 ); - addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_r1)); -@@ -1787,8 +1832,9 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - HReg ftmp = newVRegF(env); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_DfpD128toD64(fpop, ftmp, r_srcHi, r_srcLo)); - - // put the D64 result into an integer register -@@ -1811,7 +1857,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - if (matchIRExpr(&mi,p_32to1_then_1Uto8,e)) { - IRExpr* expr32 = mi.bindee[0]; - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, expr32); -+ HReg r_src = iselWordExpr_R(env, expr32, IEndianess); - addInstr(env, PPCInstr_Alu(Palu_AND, r_dst, - r_src, PPCRH_Imm(False,1))); - return r_dst; -@@ -1822,11 +1868,12 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - DECLARE_PATTERN(p_LDbe16_then_16Uto32); - DEFINE_PATTERN(p_LDbe16_then_16Uto32, - unop(Iop_16Uto32, -- IRExpr_Load(Iend_BE,Ity_I16,bind(0))) ); -+ IRExpr_Load(IEndianess,Ity_I16,bind(0))) ); - if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) { - HReg r_dst = newVRegI(env); - PPCAMode* amode -- = iselWordExpr_AMode( env, mi.bindee[0], Ity_I16/*xfer*/ ); -+ = iselWordExpr_AMode( env, mi.bindee[0], Ity_I16/*xfer*/, -+ IEndianess ); - addInstr(env, PPCInstr_Load(2,r_dst,amode, mode64)); - return r_dst; - } -@@ -1839,7 +1886,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_16Uto32: - case Iop_16Uto64: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - UShort mask = toUShort(op_unop==Iop_16Uto64 ? 0xFFFF : - op_unop==Iop_16Uto32 ? 0xFFFF : 0xFF); - addInstr(env, PPCInstr_Alu(Palu_AND,r_dst,r_src, -@@ -1848,7 +1895,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - } - case Iop_32Uto64: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - vassert(mode64); - addInstr(env, - PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/, -@@ -1862,7 +1909,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_8Sto32: - case Iop_16Sto32: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - UShort amt = toUShort(op_unop==Iop_16Sto32 ? 16 : 24); - addInstr(env, - PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/, -@@ -1875,7 +1922,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_8Sto64: - case Iop_16Sto64: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - UShort amt = toUShort(op_unop==Iop_8Sto64 ? 56 : 48); - vassert(mode64); - addInstr(env, -@@ -1888,7 +1935,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - } - case Iop_32Sto64: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - vassert(mode64); - /* According to the IBM docs, in 64 bit mode, srawi r,r,0 - sign extends the lower 32 bits into the upper 32 bits. */ -@@ -1903,18 +1950,18 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_Not64: { - if (op_unop == Iop_Not64) vassert(mode64); - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Unary(Pun_NOT,r_dst,r_src)); - return r_dst; - } - case Iop_64HIto32: { - if (!mode64) { - HReg rHi, rLo; -- iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess); - return rHi; /* and abandon rLo .. poor wee thing :-) */ - } else { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, - PPCInstr_Shft(Pshft_SHR, False/*64bit shift*/, - r_dst, r_src, PPCRH_Imm(False,32))); -@@ -1924,23 +1971,23 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_64to32: { - if (!mode64) { - HReg rHi, rLo; -- iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess); - return rLo; /* similar stupid comment to the above ... */ - } else { - /* This is a no-op. */ -- return iselWordExpr_R(env, e->Iex.Unop.arg); -+ return iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - } - } - case Iop_64to16: { - if (mode64) { /* This is a no-op. */ -- return iselWordExpr_R(env, e->Iex.Unop.arg); -+ return iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - } - break; /* evidently not used in 32-bit mode */ - } - case Iop_16HIto8: - case Iop_32HIto16: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - UShort shift = toUShort(op_unop == Iop_16HIto8 ? 8 : 16); - addInstr(env, - PPCInstr_Shft(Pshft_SHR, True/*32bit shift*/, -@@ -1950,14 +1997,14 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_128HIto64: - if (mode64) { - HReg rHi, rLo; -- iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess); - return rHi; /* and abandon rLo .. poor wee thing :-) */ - } - break; - case Iop_128to64: - if (mode64) { - HReg rHi, rLo; -- iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess); - return rLo; /* similar stupid comment to the above ... */ - } - break; -@@ -1966,7 +2013,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_1Uto8: - if ((op_unop != Iop_1Uto64) || mode64) { - HReg r_dst = newVRegI(env); -- PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+ PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Set(cond,r_dst)); - return r_dst; - } -@@ -1976,7 +2023,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_1Sto32: { - /* could do better than this, but for now ... */ - HReg r_dst = newVRegI(env); -- PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+ PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Set(cond,r_dst)); - addInstr(env, - PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/, -@@ -1990,7 +2037,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - if (mode64) { - /* could do better than this, but for now ... */ - HReg r_dst = newVRegI(env); -- PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+ PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Set(cond,r_dst)); - addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/, - r_dst, r_dst, PPCRH_Imm(False,63))); -@@ -2008,7 +2055,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - goto irreducible; - /* Count leading zeroes. */ - r_dst = newVRegI(env); -- r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src)); - return r_dst; - } -@@ -2021,7 +2068,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - if (op_unop == Iop_Left64 && !mode64) - goto irreducible; - r_dst = newVRegI(env); -- r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src)); - addInstr(env, PPCInstr_Alu(Palu_OR, r_dst, r_dst, PPCRH_Reg(r_src))); - return r_dst; -@@ -2029,7 +2076,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - - case Iop_CmpwNEZ32: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src)); - addInstr(env, PPCInstr_Alu(Palu_OR, r_dst, r_dst, PPCRH_Reg(r_src))); - addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/, -@@ -2039,7 +2086,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - - case Iop_CmpwNEZ64: { - HReg r_dst = newVRegI(env); -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - if (!mode64) goto irreducible; - addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src)); - addInstr(env, PPCInstr_Alu(Palu_OR, r_dst, r_dst, PPCRH_Reg(r_src))); -@@ -2051,20 +2098,31 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_V128to32: { - HReg r_aligned16; - HReg dst = newVRegI(env); -- HReg vec = iselVecExpr(env, e->Iex.Unop.arg); -- PPCAMode *am_off0, *am_off12; -+ HReg vec = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); -+ PPCAMode *am_off0, *am_off_word0; - sub_from_sp( env, 32 ); // Move SP down 32 bytes - - // get a quadword aligned address within our stack space - r_aligned16 = get_sp_aligned16( env ); - am_off0 = PPCAMode_IR( 0, r_aligned16 ); -- am_off12 = PPCAMode_IR( 12,r_aligned16 ); -+ -+ /* Note that the store below (done via PPCInstr_AvLdSt) uses -+ * stvx, which stores the vector in proper LE format, -+ * with byte zero (far right byte of the register in LE format) -+ * stored at the lowest memory address. Therefore, to obtain -+ * integer word zero, we need to use that lowest memory address -+ * as the base for the load. -+ */ -+ if (IEndianess == Iend_LE) -+ am_off_word0 = am_off0; -+ else -+ am_off_word0 = PPCAMode_IR( 12,r_aligned16 ); - - // store vec, load low word to dst - addInstr(env, - PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 )); - addInstr(env, -- PPCInstr_Load( 4, dst, am_off12, mode64 )); -+ PPCInstr_Load( 4, dst, am_off_word0, mode64 )); - - add_to_sp( env, 32 ); // Reset SP - return dst; -@@ -2075,8 +2133,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - if (mode64) { - HReg r_aligned16; - HReg dst = newVRegI(env); -- HReg vec = iselVecExpr(env, e->Iex.Unop.arg); -- PPCAMode *am_off0, *am_off8; -+ HReg vec = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); -+ PPCAMode *am_off0, *am_off8, *am_off_arg; - sub_from_sp( env, 32 ); // Move SP down 32 bytes - - // get a quadword aligned address within our stack space -@@ -2084,13 +2142,24 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - am_off0 = PPCAMode_IR( 0, r_aligned16 ); - am_off8 = PPCAMode_IR( 8 ,r_aligned16 ); - -- // store vec, load low word (+8) or high (+0) to dst -+ // store vec, load low word or high to dst - addInstr(env, - PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 )); -+ if (IEndianess == Iend_LE) { -+ if (op_unop == Iop_V128HIto64) -+ am_off_arg = am_off8; -+ else -+ am_off_arg = am_off0; -+ } else { -+ if (op_unop == Iop_V128HIto64) -+ am_off_arg = am_off0; -+ else -+ am_off_arg = am_off8; -+ } - addInstr(env, - PPCInstr_Load( - 8, dst, -- op_unop == Iop_V128HIto64 ? am_off0 : am_off8, -+ am_off_arg, - mode64 )); - - add_to_sp( env, 32 ); // Reset SP -@@ -2102,7 +2171,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_32to16: - case Iop_64to8: - /* These are no-ops. */ -- return iselWordExpr_R(env, e->Iex.Unop.arg); -+ return iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - - /* ReinterpF64asI64(e) */ - /* Given an IEEE754 double, produce an I64 with the same bit -@@ -2110,7 +2179,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_ReinterpF64asI64: - if (mode64) { - PPCAMode *am_addr; -- HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg, IEndianess); - HReg r_dst = newVRegI(env); - - sub_from_sp( env, 16 ); // Move SP down 16 bytes -@@ -2134,7 +2203,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - /* I believe this generates correct code for both 32- and - 64-bit hosts. */ - PPCAMode *am_addr; -- HReg fr_src = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselFltExpr(env, e->Iex.Unop.arg, IEndianess); - HReg r_dst = newVRegI(env); - - sub_from_sp( env, 16 ); // Move SP down 16 bytes -@@ -2154,7 +2223,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_ReinterpD64asI64: - if (mode64) { - PPCAMode *am_addr; -- HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess); - HReg r_dst = newVRegI(env); - - sub_from_sp( env, 16 ); // Move SP down 16 bytes -@@ -2179,7 +2248,6 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - HReg argregs[1]; - HReg r_dst = newVRegI(env); - Int argreg; -- HWord* fdescr; - - argiregs = 0; - argreg = 0; -@@ -2187,13 +2255,21 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - - argiregs |= (1 << (argreg+3)); - addInstr(env, mk_iMOVds_RR( argregs[argreg++], -- iselWordExpr_R(env, e->Iex.Unop.arg) ) ); -+ iselWordExpr_R(env, e->Iex.Unop.arg, -+ IEndianess) ) ); - - cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE ); -- -- fdescr = (HWord*)h_calc_BCDtoDPB; -- addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]), -- argiregs, mk_RetLoc_simple(RLPri_Int)) ); -+ if (IEndianess == Iend_LE) { -+ addInstr(env, PPCInstr_Call( cc, Ptr_to_ULong(h_calc_BCDtoDPB), -+ argiregs, -+ mk_RetLoc_simple(RLPri_Int)) ); -+ } else { -+ HWord* fdescr; -+ fdescr = (HWord*)h_calc_BCDtoDPB; -+ addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]), -+ argiregs, -+ mk_RetLoc_simple(RLPri_Int)) ); -+ } - - addInstr(env, mk_iMOVds_RR(r_dst, argregs[0])); - return r_dst; -@@ -2208,7 +2284,6 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - HReg argregs[1]; - HReg r_dst = newVRegI(env); - Int argreg; -- HWord* fdescr; - - argiregs = 0; - argreg = 0; -@@ -2216,13 +2291,22 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - - argiregs |= (1 << (argreg+3)); - addInstr(env, mk_iMOVds_RR( argregs[argreg++], -- iselWordExpr_R(env, e->Iex.Unop.arg) ) ); -+ iselWordExpr_R(env, e->Iex.Unop.arg, -+ IEndianess) ) ); - - cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE ); - -- fdescr = (HWord*)h_calc_DPBtoBCD; -- addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]), -- argiregs, mk_RetLoc_simple(RLPri_Int) ) ); -+ if (IEndianess == Iend_LE) { -+ addInstr(env, PPCInstr_Call( cc, Ptr_to_ULong(h_calc_DPBtoBCD), -+ argiregs, -+ mk_RetLoc_simple(RLPri_Int) ) ); -+ } else { -+ HWord* fdescr; -+ fdescr = (HWord*)h_calc_DPBtoBCD; -+ addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]), -+ argiregs, -+ mk_RetLoc_simple(RLPri_Int) ) ); -+ } - - addInstr(env, mk_iMOVds_RR(r_dst, argregs[0])); - return r_dst; -@@ -2236,7 +2320,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iop_ExtractExpD64: { - - HReg fr_dst = newVRegI(env); -- HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess); - HReg tmp = newVRegF(env); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - addInstr(env, PPCInstr_Dfp64Unary(Pfp_DXEX, tmp, fr_src)); -@@ -2255,7 +2339,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - HReg tmp = newVRegF(env); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Unop.arg); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Unop.arg, -+ IEndianess); - addInstr(env, PPCInstr_ExtractExpD128(Pfp_DXEXQ, tmp, - r_srcHi, r_srcLo)); - -@@ -2289,7 +2374,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - case Iex_GetI: { - PPCAMode* src_am - = genGuestArrayOffset( env, e->Iex.GetI.descr, -- e->Iex.GetI.ix, e->Iex.GetI.bias ); -+ e->Iex.GetI.ix, e->Iex.GetI.bias, -+ IEndianess ); - HReg r_dst = newVRegI(env); - if (mode64 && ty == Ity_I64) { - addInstr(env, PPCInstr_Load( toUChar(8), -@@ -2317,7 +2403,8 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - UInt addToSp = 0; - RetLoc rloc = mk_RetLoc_INVALID(); - doHelperCall( &addToSp, &rloc, env, NULL/*guard*/, -- e->Iex.CCall.cee, e->Iex.CCall.retty, e->Iex.CCall.args ); -+ e->Iex.CCall.cee, e->Iex.CCall.retty, e->Iex.CCall.args, -+ IEndianess ); - vassert(is_sane_RetLoc(rloc)); - vassert(rloc.pri == RLPri_Int); - vassert(addToSp == 0); -@@ -2351,11 +2438,11 @@ static HReg iselWordExpr_R_wrk ( ISelEnv - if ((ty == Ity_I8 || ty == Ity_I16 || - ty == Ity_I32 || ((ty == Ity_I64) && mode64)) && - typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) { -- PPCRI* r1 = iselWordExpr_RI(env, e->Iex.ITE.iftrue); -- HReg r0 = iselWordExpr_R(env, e->Iex.ITE.iffalse); -+ PPCRI* r1 = iselWordExpr_RI(env, e->Iex.ITE.iftrue, IEndianess); -+ HReg r0 = iselWordExpr_R(env, e->Iex.ITE.iffalse, IEndianess); - HReg r_dst = newVRegI(env); - addInstr(env, mk_iMOVds_RR(r_dst,r0)); -- PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond); -+ PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond, IEndianess); - addInstr(env, PPCInstr_CMov(cc, r_dst, r1)); - return r_dst; - } -@@ -2429,15 +2516,17 @@ static Bool sane_AMode ( ISelEnv* env, P - } - - static --PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy ) -+PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy, -+ IREndness IEndianess ) - { -- PPCAMode* am = iselWordExpr_AMode_wrk(env, e, xferTy); -+ PPCAMode* am = iselWordExpr_AMode_wrk(env, e, xferTy, IEndianess); - vassert(sane_AMode(env, am)); - return am; - } - - /* DO NOT CALL THIS DIRECTLY ! */ --static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType xferTy ) -+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, -+ IRType xferTy, IREndness IEndianess ) - { - IRType ty = typeOfIRExpr(env->type_env,e); - -@@ -2465,14 +2554,15 @@ static PPCAMode* iselWordExpr_AMode_wrk - && uLong_fits_in_16_bits(e->Iex.Binop.arg2 - ->Iex.Const.con->Ico.U64)) { - return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64, -- iselWordExpr_R(env, e->Iex.Binop.arg1) ); -+ iselWordExpr_R(env, e->Iex.Binop.arg1, -+ IEndianess) ); - } - - /* Add64(expr,expr) */ - if (e->tag == Iex_Binop - && e->Iex.Binop.op == Iop_Add64) { -- HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - return PPCAMode_RR( r_idx, r_base ); - } - -@@ -2488,14 +2578,15 @@ static PPCAMode* iselWordExpr_AMode_wrk - && uInt_fits_in_16_bits(e->Iex.Binop.arg2 - ->Iex.Const.con->Ico.U32)) { - return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32, -- iselWordExpr_R(env, e->Iex.Binop.arg1) ); -+ iselWordExpr_R(env, e->Iex.Binop.arg1, -+ IEndianess) ); - } - - /* Add32(expr,expr) */ - if (e->tag == Iex_Binop - && e->Iex.Binop.op == Iop_Add32) { -- HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - return PPCAMode_RR( r_idx, r_base ); - } - -@@ -2503,7 +2594,7 @@ static PPCAMode* iselWordExpr_AMode_wrk - - /* Doesn't match anything in particular. Generate it into - a register and use that. */ -- return PPCAMode_IR( 0, iselWordExpr_R(env,e) ); -+ return PPCAMode_IR( 0, iselWordExpr_R(env,e,IEndianess) ); - } - - -@@ -2516,9 +2607,10 @@ static PPCAMode* iselWordExpr_AMode_wrk - signed immediates that are return can have their sign inverted if - need be. */ - --static PPCRH* iselWordExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e ) -+static PPCRH* iselWordExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e, -+ IREndness IEndianess ) - { -- PPCRH* ri = iselWordExpr_RH_wrk(env, syned, e); -+ PPCRH* ri = iselWordExpr_RH_wrk(env, syned, e, IEndianess); - /* sanity checks ... */ - switch (ri->tag) { - case Prh_Imm: -@@ -2536,7 +2628,8 @@ static PPCRH* iselWordExpr_RH ( ISelEnv* - } - - /* DO NOT CALL THIS DIRECTLY ! */ --static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e ) -+static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e, -+ IREndness IEndianess ) - { - ULong u; - Long l; -@@ -2569,7 +2662,7 @@ static PPCRH* iselWordExpr_RH_wrk ( ISel - } - - /* default case: calculate into a register and return that */ -- return PPCRH_Reg( iselWordExpr_R ( env, e ) ); -+ return PPCRH_Reg( iselWordExpr_R ( env, e, IEndianess ) ); - } - - -@@ -2579,9 +2672,9 @@ static PPCRH* iselWordExpr_RH_wrk ( ISel - iselIntExpr_R, the expression can have type 32, 16 or 8 bits, or, - in 64-bit mode, 64 bits. */ - --static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e ) -+static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { -- PPCRI* ri = iselWordExpr_RI_wrk(env, e); -+ PPCRI* ri = iselWordExpr_RI_wrk(env, e, IEndianess); - /* sanity checks ... */ - switch (ri->tag) { - case Pri_Imm: -@@ -2596,7 +2689,8 @@ static PPCRI* iselWordExpr_RI ( ISelEnv* - } - - /* DO NOT CALL THIS DIRECTLY ! */ --static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e ) -+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - Long l; - IRType ty = typeOfIRExpr(env->type_env,e); -@@ -2618,7 +2712,7 @@ static PPCRI* iselWordExpr_RI_wrk ( ISel - } - - /* default case: calculate into a register and return that */ -- return PPCRI_Reg( iselWordExpr_R ( env, e ) ); -+ return PPCRI_Reg( iselWordExpr_R ( env, e, IEndianess ) ); - } - - -@@ -2628,11 +2722,12 @@ static PPCRI* iselWordExpr_RI_wrk ( ISel - being an immediate in the range 1 .. 31 inclusive. Used for doing - shift amounts. Only used in 32-bit mode. */ - --static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e ) -+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - PPCRH* ri; - vassert(!env->mode64); -- ri = iselWordExpr_RH5u_wrk(env, e); -+ ri = iselWordExpr_RH5u_wrk(env, e, IEndianess); - /* sanity checks ... */ - switch (ri->tag) { - case Prh_Imm: -@@ -2649,7 +2744,8 @@ static PPCRH* iselWordExpr_RH5u ( ISelEn - } - - /* DO NOT CALL THIS DIRECTLY ! */ --static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e ) -+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - IRType ty = typeOfIRExpr(env->type_env,e); - vassert(ty == Ity_I8); -@@ -2663,7 +2759,7 @@ static PPCRH* iselWordExpr_RH5u_wrk ( IS - } - - /* default case: calculate into a register and return that */ -- return PPCRH_Reg( iselWordExpr_R ( env, e ) ); -+ return PPCRH_Reg( iselWordExpr_R ( env, e, IEndianess ) ); - } - - -@@ -2673,11 +2769,12 @@ static PPCRH* iselWordExpr_RH5u_wrk ( IS - being an immediate in the range 1 .. 63 inclusive. Used for doing - shift amounts. Only used in 64-bit mode. */ - --static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e ) -+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - PPCRH* ri; - vassert(env->mode64); -- ri = iselWordExpr_RH6u_wrk(env, e); -+ ri = iselWordExpr_RH6u_wrk(env, e, IEndianess); - /* sanity checks ... */ - switch (ri->tag) { - case Prh_Imm: -@@ -2694,7 +2791,8 @@ static PPCRH* iselWordExpr_RH6u ( ISelEn - } - - /* DO NOT CALL THIS DIRECTLY ! */ --static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e ) -+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - IRType ty = typeOfIRExpr(env->type_env,e); - vassert(ty == Ity_I8); -@@ -2708,7 +2806,7 @@ static PPCRH* iselWordExpr_RH6u_wrk ( IS - } - - /* default case: calculate into a register and return that */ -- return PPCRH_Reg( iselWordExpr_R ( env, e ) ); -+ return PPCRH_Reg( iselWordExpr_R ( env, e, IEndianess ) ); - } - - -@@ -2718,14 +2816,16 @@ static PPCRH* iselWordExpr_RH6u_wrk ( IS - condition code which would correspond when the expression would - notionally have returned 1. */ - --static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e ) -+static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - /* Uh, there's nothing we can sanity check here, unfortunately. */ -- return iselCondCode_wrk(env,e); -+ return iselCondCode_wrk(env,e, IEndianess); - } - - /* DO NOT CALL THIS DIRECTLY ! */ --static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) -+static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - vassert(e); - vassert(typeOfIRExpr(env->type_env,e) == Ity_I1); -@@ -2743,7 +2843,7 @@ static PPCCondCode iselCondCode_wrk ( IS - /* Not1(...) */ - if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) { - /* Generate code for the arg, and negate the test condition */ -- PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+ PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess); - cond.test = invertCondTest(cond.test); - return cond; - } -@@ -2753,7 +2853,7 @@ static PPCCondCode iselCondCode_wrk ( IS - /* 32to1, 64to1 */ - if (e->tag == Iex_Unop && - (e->Iex.Unop.op == Iop_32to1 || e->Iex.Unop.op == Iop_64to1)) { -- HReg src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - HReg tmp = newVRegI(env); - /* could do better, probably -- andi. */ - addInstr(env, PPCInstr_Alu(Palu_AND, tmp, -@@ -2770,7 +2870,7 @@ static PPCCondCode iselCondCode_wrk ( IS - /* could do better -- andi. */ - if (e->tag == Iex_Unop - && e->Iex.Unop.op == Iop_CmpNEZ8) { -- HReg arg = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg arg = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - HReg tmp = newVRegI(env); - addInstr(env, PPCInstr_Alu(Palu_AND, tmp, arg, - PPCRH_Imm(False,0xFF))); -@@ -2784,7 +2884,7 @@ static PPCCondCode iselCondCode_wrk ( IS - /* CmpNEZ32(x) */ - if (e->tag == Iex_Unop - && e->Iex.Unop.op == Iop_CmpNEZ32) { -- HReg r1 = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r1 = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/, - 7/*cr*/, r1, PPCRH_Imm(False,0))); - return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ ); -@@ -2802,8 +2902,8 @@ static PPCCondCode iselCondCode_wrk ( IS - || e->Iex.Binop.op == Iop_CmpLE32U)) { - Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S || - e->Iex.Binop.op == Iop_CmpLE32S); -- HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1); -- PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2); -+ HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/, - 7/*cr*/, r1, ri2)); - -@@ -2826,13 +2926,13 @@ static PPCCondCode iselCondCode_wrk ( IS - if (!env->mode64) { - HReg hi, lo; - HReg tmp = newVRegI(env); -- iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg ); -+ iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg, IEndianess ); - addInstr(env, PPCInstr_Alu(Palu_OR, tmp, lo, PPCRH_Reg(hi))); - addInstr(env, PPCInstr_Cmp(False/*sign*/, True/*32bit cmp*/, - 7/*cr*/, tmp,PPCRH_Imm(False,0))); - return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ ); - } else { // mode64 -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Cmp(False/*sign*/, False/*64bit cmp*/, - 7/*cr*/, r_src,PPCRH_Imm(False,0))); - return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ ); -@@ -2851,8 +2951,8 @@ static PPCCondCode iselCondCode_wrk ( IS - || e->Iex.Binop.op == Iop_CmpLE64U)) { - Bool syned = (e->Iex.Binop.op == Iop_CmpLT64S || - e->Iex.Binop.op == Iop_CmpLE64S); -- HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1); -- PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2); -+ HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, IEndianess); - vassert(env->mode64); - addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/, - 7/*cr*/, r1, ri2)); -@@ -2874,7 +2974,7 @@ static PPCCondCode iselCondCode_wrk ( IS - if (e->tag == Iex_Binop - && e->Iex.Binop.op == Iop_CmpNE8 - && isZeroU8(e->Iex.Binop.arg2)) { -- HReg arg = iselWordExpr_R(env, e->Iex.Binop.arg1); -+ HReg arg = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); - HReg tmp = newVRegI(env); - addInstr(env, PPCInstr_Alu(Palu_AND, tmp, arg, - PPCRH_Imm(False,0xFF))); -@@ -2913,10 +3013,10 @@ static PPCCondCode iselCondCode_wrk ( IS - caller. */ - - static void iselInt128Expr ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ) -+ ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { - vassert(env->mode64); -- iselInt128Expr_wrk(rHi, rLo, env, e); -+ iselInt128Expr_wrk(rHi, rLo, env, e, IEndianess); - # if 0 - vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); - # endif -@@ -2928,7 +3028,7 @@ static void iselInt128Expr ( HReg* rHi, - - /* DO NOT CALL THIS DIRECTLY ! */ - static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ) -+ ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { - vassert(e); - vassert(typeOfIRExpr(env->type_env,e) == Ity_I128); -@@ -2948,8 +3048,8 @@ static void iselInt128Expr_wrk ( HReg* r - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); - Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/, - False/*lo64*/, False/*64bit mul*/, - tLo, r_srcL, r_srcR)); -@@ -2963,8 +3063,8 @@ static void iselInt128Expr_wrk ( HReg* r - - /* 64HLto128(e1,e2) */ - case Iop_64HLto128: -- *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1); -- *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - return; - default: - break; -@@ -2992,10 +3092,11 @@ static void iselInt128Expr_wrk ( HReg* r - - /* 32-bit mode ONLY: compute a 128-bit value into a register quad */ - static void iselInt128Expr_to_32x4 ( HReg* rHi, HReg* rMedHi, HReg* rMedLo, -- HReg* rLo, ISelEnv* env, IRExpr* e ) -+ HReg* rLo, ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - vassert(!env->mode64); -- iselInt128Expr_to_32x4_wrk(rHi, rMedHi, rMedLo, rLo, env, e); -+ iselInt128Expr_to_32x4_wrk(rHi, rMedHi, rMedLo, rLo, env, e, IEndianess); - # if 0 - vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); - # endif -@@ -3011,7 +3112,8 @@ static void iselInt128Expr_to_32x4 ( HRe - - static void iselInt128Expr_to_32x4_wrk ( HReg* rHi, HReg* rMedHi, - HReg* rMedLo, HReg* rLo, -- ISelEnv* env, IRExpr* e ) -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - vassert(e); - vassert(typeOfIRExpr(env->type_env,e) == Ity_I128); -@@ -3027,8 +3129,8 @@ static void iselInt128Expr_to_32x4_wrk ( - IROp op_binop = e->Iex.Binop.op; - switch (op_binop) { - case Iop_64HLto128: -- iselInt64Expr(rHi, rMedHi, env, e->Iex.Binop.arg1); -- iselInt64Expr(rMedLo, rLo, env, e->Iex.Binop.arg2); -+ iselInt64Expr(rHi, rMedHi, env, e->Iex.Binop.arg1, IEndianess); -+ iselInt64Expr(rMedLo, rLo, env, e->Iex.Binop.arg2, IEndianess); - return; - default: - vex_printf("iselInt128Expr_to_32x4_wrk: Binop case 0x%x not found\n", -@@ -3048,10 +3150,11 @@ static void iselInt128Expr_to_32x4_wrk ( - caller. */ - - static void iselInt64Expr ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ) -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - vassert(!env->mode64); -- iselInt64Expr_wrk(rHi, rLo, env, e); -+ iselInt64Expr_wrk(rHi, rLo, env, e, IEndianess); - # if 0 - vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); - # endif -@@ -3063,16 +3166,17 @@ static void iselInt64Expr ( HReg* rHi, H - - /* DO NOT CALL THIS DIRECTLY ! */ - static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, -- ISelEnv* env, IRExpr* e ) -+ ISelEnv* env, IRExpr* e, -+ IREndness IEndianess ) - { - vassert(e); - vassert(typeOfIRExpr(env->type_env,e) == Ity_I64); - - /* 64-bit load */ -- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { -+ if (e->tag == Iex_Load && e->Iex.Load.end == IEndianess) { - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); -- HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr); -+ HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr, IEndianess); - vassert(!env->mode64); - addInstr(env, PPCInstr_Load( 4/*byte-load*/, - tHi, PPCAMode_IR( 0, r_addr ), -@@ -3123,13 +3227,13 @@ static void iselInt64Expr_wrk ( HReg* rH - /* 64-bit ITE */ - if (e->tag == Iex_ITE) { // VFD - HReg e0Lo, e0Hi, eXLo, eXHi; -- iselInt64Expr(&eXHi, &eXLo, env, e->Iex.ITE.iftrue); -- iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.ITE.iffalse); -+ iselInt64Expr(&eXHi, &eXLo, env, e->Iex.ITE.iftrue, IEndianess); -+ iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.ITE.iffalse, IEndianess); - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); - addInstr(env, mk_iMOVds_RR(tHi,e0Hi)); - addInstr(env, mk_iMOVds_RR(tLo,e0Lo)); -- PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond); -+ PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond, IEndianess); - addInstr(env, PPCInstr_CMov(cc,tHi,PPCRI_Reg(eXHi))); - addInstr(env, PPCInstr_CMov(cc,tLo,PPCRI_Reg(eXLo))); - *rHi = tHi; -@@ -3147,8 +3251,10 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); - Bool syned = toBool(op_binop == Iop_MullS32); -- HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, -+ IEndianess); -+ HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/, - False/*lo32*/, True/*32bit mul*/, - tLo, r_srcL, r_srcR)); -@@ -3169,8 +3275,8 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg tHi = newVRegI(env); - PPCAluOp op = (op_binop == Iop_Or64) ? Palu_OR : - (op_binop == Iop_And64) ? Palu_AND : Palu_XOR; -- iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -- iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); -+ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess); -+ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_Alu(op, tHi, xHi, PPCRH_Reg(yHi))); - addInstr(env, PPCInstr_Alu(op, tLo, xLo, PPCRH_Reg(yLo))); - *rHi = tHi; -@@ -3183,8 +3289,8 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg xLo, xHi, yLo, yHi; - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); -- iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -- iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); -+ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess); -+ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_AddSubC( True/*add*/, True /*set carry*/, - tLo, xLo, yLo)); - addInstr(env, PPCInstr_AddSubC( True/*add*/, False/*read carry*/, -@@ -3196,8 +3302,8 @@ static void iselInt64Expr_wrk ( HReg* rH - - /* 32HLto64(e1,e2) */ - case Iop_32HLto64: -- *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1); -- *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - return; - - /* F64toI64[S|U] */ -@@ -3207,12 +3313,13 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg r1 = StackFramePtr(env->mode64); - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); - PPCAMode* four_r1 = PPCAMode_IR( 4, r1 ); -- HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2, -+ IEndianess); - HReg ftmp = newVRegF(env); - - vassert(!env->mode64); - /* Set host rounding mode */ -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - - sub_from_sp( env, 16 ); - addInstr(env, PPCInstr_FpCftI(False/*F->I*/, False/*int64*/, -@@ -3235,11 +3342,11 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg r1 = StackFramePtr(env->mode64); - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); - PPCAMode* four_r1 = PPCAMode_IR( 4, r1 ); -- HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess); - HReg tmp = newVRegF(env); - - vassert(!env->mode64); -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - addInstr(env, PPCInstr_Dfp64Unary(Pfp_DCTFIX, tmp, fr_src)); - - sub_from_sp( env, 16 ); -@@ -3261,8 +3368,9 @@ static void iselInt64Expr_wrk ( HReg* rH - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) ); - -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_DfpD128toD64(fpop, ftmp, r_srcHi, r_srcLo)); - - // put the D64 result into an integer register pair -@@ -3290,7 +3398,7 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg argHi, argLo; - HReg tmp1 = newVRegI(env); - HReg tmp2 = newVRegI(env); -- iselInt64Expr(&argHi, &argLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&argHi, &argLo, env, e->Iex.Unop.arg, IEndianess); - /* tmp1 = argHi | argLo */ - addInstr(env, PPCInstr_Alu(Palu_OR, tmp1, argHi, PPCRH_Reg(argLo))); - /* tmp2 = (tmp1 | -tmp1) >>s 31 */ -@@ -3309,7 +3417,7 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg zero32 = newVRegI(env); - HReg resHi = newVRegI(env); - HReg resLo = newVRegI(env); -- iselInt64Expr(&argHi, &argLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&argHi, &argLo, env, e->Iex.Unop.arg, IEndianess); - vassert(env->mode64 == False); - addInstr(env, PPCInstr_LI(zero32, 0, env->mode64)); - /* resHi:resLo = - argHi:argLo */ -@@ -3328,7 +3436,7 @@ static void iselInt64Expr_wrk ( HReg* rH - /* 32Sto64(e) */ - case Iop_32Sto64: { - HReg tHi = newVRegI(env); -- HReg src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/, - tHi, src, PPCRH_Imm(False,31))); - *rHi = tHi; -@@ -3337,7 +3445,7 @@ static void iselInt64Expr_wrk ( HReg* rH - } - case Iop_ExtractExpD64: { - HReg tmp = newVRegF(env); -- HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess); - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); -@@ -3364,7 +3472,7 @@ static void iselInt64Expr_wrk ( HReg* rH - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) ); - -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Unop.arg); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_ExtractExpD128(Pfp_DXEXQ, tmp, - r_srcHi, r_srcLo)); - -@@ -3382,7 +3490,7 @@ static void iselInt64Expr_wrk ( HReg* rH - /* 32Uto64(e) */ - case Iop_32Uto64: { - HReg tHi = newVRegI(env); -- HReg tLo = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg tLo = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_LI(tHi, 0, False/*mode32*/)); - *rHi = tHi; - *rLo = tLo; -@@ -3398,7 +3506,7 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg r_Lo = INVALID_HREG; - - iselInt128Expr_to_32x4(&r_Hi, &r_MedHi, &r_MedLo, &r_Lo, -- env, e->Iex.Unop.arg); -+ env, e->Iex.Unop.arg, IEndianess); - *rHi = r_MedLo; - *rLo = r_Lo; - return; -@@ -3413,7 +3521,7 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg r_Lo = INVALID_HREG; - - iselInt128Expr_to_32x4(&r_Hi, &r_MedHi, &r_MedLo, &r_Lo, -- env, e->Iex.Unop.arg); -+ env, e->Iex.Unop.arg, IEndianess); - *rHi = r_Hi; - *rLo = r_MedHi; - return; -@@ -3426,7 +3534,7 @@ static void iselInt64Expr_wrk ( HReg* rH - Int off = e->Iex.Unop.op==Iop_V128HIto64 ? 0 : 8; - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); -- HReg vec = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg vec = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - PPCAMode *am_off0, *am_offLO, *am_offHI; - sub_from_sp( env, 32 ); // Move SP down 32 bytes - -@@ -3456,7 +3564,7 @@ static void iselInt64Expr_wrk ( HReg* rH - case Iop_1Sto64: { - HReg tLo = newVRegI(env); - HReg tHi = newVRegI(env); -- PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+ PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Set(cond,tLo)); - addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/, - tLo, tLo, PPCRH_Imm(False,31))); -@@ -3472,7 +3580,7 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg xLo, xHi; - HReg tmpLo = newVRegI(env); - HReg tmpHi = newVRegI(env); -- iselInt64Expr(&xHi, &xLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&xHi, &xLo, env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Unary(Pun_NOT,tmpLo,xLo)); - addInstr(env, PPCInstr_Unary(Pun_NOT,tmpHi,xHi)); - *rHi = tmpHi; -@@ -3485,7 +3593,7 @@ static void iselInt64Expr_wrk ( HReg* rH - pattern. */ - case Iop_ReinterpF64asI64: { - PPCAMode *am_addr0, *am_addr1; -- HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg, IEndianess); - HReg r_dstLo = newVRegI(env); - HReg r_dstHi = newVRegI(env); - -@@ -3510,7 +3618,7 @@ static void iselInt64Expr_wrk ( HReg* rH - } - - case Iop_ReinterpD64asI64: { -- HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess); - PPCAMode *am_addr0, *am_addr1; - HReg r_dstLo = newVRegI(env); - HReg r_dstHi = newVRegI(env); -@@ -3546,7 +3654,6 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg tHi = newVRegI(env); - HReg tmpHi; - HReg tmpLo; -- ULong target; - Bool mode64 = env->mode64; - - argregs[0] = hregPPC_GPR3(mode64); -@@ -3555,7 +3662,7 @@ static void iselInt64Expr_wrk ( HReg* rH - argiregs = 0; - argreg = 0; - -- iselInt64Expr( &tmpHi, &tmpLo, env, e->Iex.Unop.arg ); -+ iselInt64Expr( &tmpHi, &tmpLo, env, e->Iex.Unop.arg, IEndianess ); - - argiregs |= ( 1 << (argreg+3 ) ); - addInstr( env, mk_iMOVds_RR( argregs[argreg++], tmpHi ) ); -@@ -3564,11 +3671,19 @@ static void iselInt64Expr_wrk ( HReg* rH - addInstr( env, mk_iMOVds_RR( argregs[argreg], tmpLo ) ); - - cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE ); -- target = toUInt( Ptr_to_ULong(h_calc_BCDtoDPB ) ); - -- addInstr( env, PPCInstr_Call( cc, (Addr64)target, -- argiregs, -- mk_RetLoc_simple(RLPri_2Int) ) ); -+ if (IEndianess == Iend_LE) { -+ addInstr( env, PPCInstr_Call( cc, Ptr_to_ULong(h_calc_BCDtoDPB), -+ argiregs, -+ mk_RetLoc_simple(RLPri_2Int) ) ); -+ } else { -+ ULong target; -+ target = toUInt( Ptr_to_ULong(h_calc_BCDtoDPB ) ); -+ addInstr( env, PPCInstr_Call( cc, (Addr64)target, -+ argiregs, -+ mk_RetLoc_simple(RLPri_2Int) ) ); -+ } -+ - addInstr( env, mk_iMOVds_RR( tHi, argregs[argreg-1] ) ); - addInstr( env, mk_iMOVds_RR( tLo, argregs[argreg] ) ); - -@@ -3586,7 +3701,6 @@ static void iselInt64Expr_wrk ( HReg* rH - HReg tHi = newVRegI(env); - HReg tmpHi; - HReg tmpLo; -- ULong target; - Bool mode64 = env->mode64; - - argregs[0] = hregPPC_GPR3(mode64); -@@ -3595,7 +3709,7 @@ static void iselInt64Expr_wrk ( HReg* rH - argiregs = 0; - argreg = 0; - -- iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg, IEndianess); - - argiregs |= (1 << (argreg+3)); - addInstr(env, mk_iMOVds_RR( argregs[argreg++], tmpHi )); -@@ -3605,10 +3719,17 @@ static void iselInt64Expr_wrk ( HReg* rH - - cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE ); - -- target = toUInt( Ptr_to_ULong( h_calc_DPBtoBCD ) ); -+ if (IEndianess == Iend_LE) { -+ addInstr(env, PPCInstr_Call( cc, Ptr_to_ULong(h_calc_DPBtoBCD), -+ argiregs, -+ mk_RetLoc_simple(RLPri_2Int) ) ); -+ } else { -+ ULong target; -+ target = toUInt( Ptr_to_ULong( h_calc_DPBtoBCD ) ); -+ addInstr(env, PPCInstr_Call( cc, (Addr64)target, argiregs, -+ mk_RetLoc_simple(RLPri_2Int) ) ); -+ } - -- addInstr(env, PPCInstr_Call( cc, (Addr64)target, argiregs, -- mk_RetLoc_simple(RLPri_2Int) ) ); - addInstr(env, mk_iMOVds_RR(tHi, argregs[argreg-1])); - addInstr(env, mk_iMOVds_RR(tLo, argregs[argreg])); - -@@ -3635,9 +3756,9 @@ static void iselInt64Expr_wrk ( HReg* rH - /* Nothing interesting here; really just wrappers for - 64-bit stuff. */ - --static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ) -+static HReg iselFltExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { -- HReg r = iselFltExpr_wrk( env, e ); -+ HReg r = iselFltExpr_wrk( env, e, IEndianess ); - # if 0 - vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); - # endif -@@ -3647,7 +3768,7 @@ static HReg iselFltExpr ( ISelEnv* env, - } - - /* DO NOT CALL THIS DIRECTLY */ --static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) -+static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { - Bool mode64 = env->mode64; - -@@ -3658,11 +3779,12 @@ static HReg iselFltExpr_wrk ( ISelEnv* e - return lookupIRTemp(env, e->Iex.RdTmp.tmp); - } - -- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { -+ if (e->tag == Iex_Load && e->Iex.Load.end == IEndianess) { - PPCAMode* am_addr; - HReg r_dst = newVRegF(env); - vassert(e->Iex.Load.ty == Ity_F32); -- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F32/*xfer*/); -+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F32/*xfer*/, -+ IEndianess); - addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, r_dst, am_addr)); - return r_dst; - } -@@ -3704,7 +3826,7 @@ static HReg iselFltExpr_wrk ( ISelEnv* e - part the latter optimisation will apply and hence this code - will not often be used. - */ -- HReg fsrc = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg fsrc = iselDblExpr(env, e->Iex.Unop.arg, IEndianess); - HReg fdst = newVRegF(env); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - -@@ -3722,12 +3844,12 @@ static HReg iselFltExpr_wrk ( ISelEnv* e - if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64UtoF32) { - if (mode64) { - HReg fdst = newVRegF(env); -- HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - HReg r1 = StackFramePtr(env->mode64); - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); - - /* Set host rounding mode */ -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - - sub_from_sp( env, 16 ); - -@@ -3750,10 +3872,10 @@ static HReg iselFltExpr_wrk ( ISelEnv* e - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); - PPCAMode* four_r1 = PPCAMode_IR( 4, r1 ); - -- iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2); -+ iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2, IEndianess); - - /* Set host rounding mode */ -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - - sub_from_sp( env, 16 ); - -@@ -3806,9 +3928,9 @@ static HReg iselFltExpr_wrk ( ISelEnv* e - positive zero 0 0 .000000---0 - */ - --static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ) -+static HReg iselDblExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { -- HReg r = iselDblExpr_wrk( env, e ); -+ HReg r = iselDblExpr_wrk( env, e, IEndianess ); - # if 0 - vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); - # endif -@@ -3818,7 +3940,7 @@ static HReg iselDblExpr ( ISelEnv* env, - } - - /* DO NOT CALL THIS DIRECTLY */ --static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) -+static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { - Bool mode64 = env->mode64; - IRType ty = typeOfIRExpr(env->type_env,e); -@@ -3860,11 +3982,12 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - } - - /* --------- LOAD --------- */ -- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { -+ if (e->tag == Iex_Load && e->Iex.Load.end == IEndianess) { - HReg r_dst = newVRegF(env); - PPCAMode* am_addr; - vassert(e->Iex.Load.ty == Ity_F64); -- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F64/*xfer*/); -+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F64/*xfer*/, -+ IEndianess); - addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dst, am_addr)); - return r_dst; - } -@@ -3890,10 +4013,13 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - } - if (fpop != Pfp_INVALID) { - HReg r_dst = newVRegF(env); -- HReg r_srcML = iselDblExpr(env, e->Iex.Qop.details->arg2); -- HReg r_srcMR = iselDblExpr(env, e->Iex.Qop.details->arg3); -- HReg r_srcAcc = iselDblExpr(env, e->Iex.Qop.details->arg4); -- set_FPU_rounding_mode( env, e->Iex.Qop.details->arg1 ); -+ HReg r_srcML = iselDblExpr(env, e->Iex.Qop.details->arg2, -+ IEndianess); -+ HReg r_srcMR = iselDblExpr(env, e->Iex.Qop.details->arg3, -+ IEndianess); -+ HReg r_srcAcc = iselDblExpr(env, e->Iex.Qop.details->arg4, -+ IEndianess); -+ set_FPU_rounding_mode( env, e->Iex.Qop.details->arg1, IEndianess ); - addInstr(env, PPCInstr_FpMulAcc(fpop, r_dst, - r_srcML, r_srcMR, r_srcAcc)); - return r_dst; -@@ -3916,9 +4042,9 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - } - if (fpop != Pfp_INVALID) { - HReg r_dst = newVRegF(env); -- HReg r_srcL = iselDblExpr(env, triop->arg2); -- HReg r_srcR = iselDblExpr(env, triop->arg3); -- set_FPU_rounding_mode( env, triop->arg1 ); -+ HReg r_srcL = iselDblExpr(env, triop->arg2, IEndianess); -+ HReg r_srcR = iselDblExpr(env, triop->arg3, IEndianess); -+ set_FPU_rounding_mode( env, triop->arg1, IEndianess ); - addInstr(env, PPCInstr_FpBinary(fpop, r_dst, r_srcL, r_srcR)); - return r_dst; - } -@@ -3932,8 +4058,8 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - } - if (fpop == Pfp_SQRT) { - HReg fr_dst = newVRegF(env); -- HReg fr_src = iselDblExpr(env, e->Iex.Binop.arg2); -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ HReg fr_src = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - addInstr(env, PPCInstr_FpUnary(fpop, fr_dst, fr_src)); - return fr_dst; - } -@@ -3943,8 +4069,8 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - - if (e->Iex.Binop.op == Iop_RoundF64toF32) { - HReg r_dst = newVRegF(env); -- HReg r_src = iselDblExpr(env, e->Iex.Binop.arg2); -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ HReg r_src = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - addInstr(env, PPCInstr_FpRSP(r_dst, r_src)); - //set_FPU_rounding_default( env ); - return r_dst; -@@ -3953,12 +4079,12 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - if (e->Iex.Binop.op == Iop_I64StoF64 || e->Iex.Binop.op == Iop_I64UtoF64) { - if (mode64) { - HReg fdst = newVRegF(env); -- HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - HReg r1 = StackFramePtr(env->mode64); - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); - - /* Set host rounding mode */ -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - - sub_from_sp( env, 16 ); - -@@ -3982,10 +4108,11 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - PPCAMode* zero_r1 = PPCAMode_IR( 0, r1 ); - PPCAMode* four_r1 = PPCAMode_IR( 4, r1 ); - -- iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2); -+ iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2, -+ IEndianess); - - /* Set host rounding mode */ -- set_FPU_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - - sub_from_sp( env, 16 ); - -@@ -4021,7 +4148,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - } - if (fpop != Pfp_INVALID) { - HReg fr_dst = newVRegF(env); -- HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_FpUnary(fpop, fr_dst, fr_src)); - return fr_dst; - } -@@ -4034,10 +4161,11 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - bit pattern. */ - if (!mode64) { - HReg r_srcHi, r_srcLo; -- iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg); -+ iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg, -+ IEndianess); - return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo ); - } else { -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - return mk_LoadR64toFPR( env, r_src ); - } - } -@@ -4047,7 +4175,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - e->Iex.Unop.arg->Iex.Unop.op == Iop_ReinterpI32asF32 ) { - e = e->Iex.Unop.arg; - -- HReg src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - HReg fr_dst = newVRegF(env); - PPCAMode *am_addr; - -@@ -4067,7 +4195,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - - - /* this is a no-op */ -- HReg res = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg res = iselFltExpr(env, e->Iex.Unop.arg, IEndianess); - return res; - } - default: -@@ -4079,11 +4207,11 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - if (e->tag == Iex_ITE) { // VFD - if (ty == Ity_F64 - && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) { -- HReg fr1 = iselDblExpr(env, e->Iex.ITE.iftrue); -- HReg fr0 = iselDblExpr(env, e->Iex.ITE.iffalse); -+ HReg fr1 = iselDblExpr(env, e->Iex.ITE.iftrue, IEndianess); -+ HReg fr0 = iselDblExpr(env, e->Iex.ITE.iffalse, IEndianess); - HReg fr_dst = newVRegF(env); - addInstr(env, PPCInstr_FpUnary( Pfp_MOV, fr_dst, fr0 )); -- PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond); -+ PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond, IEndianess); - addInstr(env, PPCInstr_FpCMov( cc, fr_dst, fr1 )); - return fr_dst; - } -@@ -4094,16 +4222,16 @@ static HReg iselDblExpr_wrk ( ISelEnv* e - vpanic("iselDblExpr_wrk(ppc)"); - } - --static HReg iselDfp32Expr(ISelEnv* env, IRExpr* e) -+static HReg iselDfp32Expr(ISelEnv* env, IRExpr* e, IREndness IEndianess) - { -- HReg r = iselDfp32Expr_wrk( env, e ); -+ HReg r = iselDfp32Expr_wrk( env, e, IEndianess ); - vassert(hregClass(r) == HRcFlt64); - vassert( hregIsVirtual(r) ); - return r; - } - - /* DO NOT CALL THIS DIRECTLY */ --static HReg iselDfp32Expr_wrk(ISelEnv* env, IRExpr* e) -+static HReg iselDfp32Expr_wrk(ISelEnv* env, IRExpr* e, IREndness IEndianess) - { - Bool mode64 = env->mode64; - IRType ty = typeOfIRExpr( env->type_env, e ); -@@ -4121,11 +4249,12 @@ static HReg iselDfp32Expr_wrk(ISelEnv* e - } - - /* --------- LOAD --------- */ -- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { -+ if (e->tag == Iex_Load && e->Iex.Load.end == IEndianess) { - PPCAMode* am_addr; - HReg r_dst = newVRegF(env); - vassert(e->Iex.Load.ty == Ity_D32); -- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_D32/*xfer*/); -+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_D32/*xfer*/, -+ IEndianess); - addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, r_dst, am_addr)); - return r_dst; - } -@@ -4134,8 +4263,8 @@ static HReg iselDfp32Expr_wrk(ISelEnv* e - if (e->tag == Iex_Binop) { - if (e->Iex.Binop.op == Iop_D64toD32) { - HReg fr_dst = newVRegF(env); -- HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2); -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - addInstr(env, PPCInstr_Dfp64Unary(Pfp_DRSP, fr_dst, fr_src)); - return fr_dst; - } -@@ -4145,16 +4274,16 @@ static HReg iselDfp32Expr_wrk(ISelEnv* e - vpanic( "iselDfp32Expr_wrk(ppc)" ); - } - --static HReg iselDfp64Expr(ISelEnv* env, IRExpr* e) -+static HReg iselDfp64Expr(ISelEnv* env, IRExpr* e, IREndness IEndianess) - { -- HReg r = iselDfp64Expr_wrk( env, e ); -+ HReg r = iselDfp64Expr_wrk( env, e, IEndianess ); - vassert(hregClass(r) == HRcFlt64); - vassert( hregIsVirtual(r) ); - return r; - } - - /* DO NOT CALL THIS DIRECTLY */ --static HReg iselDfp64Expr_wrk(ISelEnv* env, IRExpr* e) -+static HReg iselDfp64Expr_wrk(ISelEnv* env, IRExpr* e, IREndness IEndianess) - { - Bool mode64 = env->mode64; - IRType ty = typeOfIRExpr( env->type_env, e ); -@@ -4176,11 +4305,12 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - return r_dst; - } - -- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { -+ if (e->tag == Iex_Load && e->Iex.Load.end == IEndianess) { - PPCAMode* am_addr; - HReg r_dst = newVRegF(env); - vassert(e->Iex.Load.ty == Ity_D64); -- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_D64/*xfer*/); -+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_D64/*xfer*/, -+ IEndianess); - addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dst, am_addr)); - return r_dst; - } -@@ -4199,27 +4329,30 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - bit pattern. */ - if (!mode64) { - HReg r_srcHi, r_srcLo; -- iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg); -+ iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg, -+ IEndianess); - return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo ); - } else { -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - return mk_LoadR64toFPR( env, r_src ); - } - } - case Iop_D32toD64: { -- HReg fr_src = iselDfp32Expr(env, e->Iex.Unop.arg); -+ HReg fr_src = iselDfp32Expr(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Dfp64Unary(Pfp_DCTDP, fr_dst, fr_src)); - return fr_dst; - } - case Iop_D128HItoD64: -- iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg ); -+ iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg, -+ IEndianess ); - return r_dstHi; - case Iop_D128LOtoD64: -- iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg ); -+ iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg, -+ IEndianess ); - return r_dstLo; - case Iop_InsertExpD64: { -- HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1); -- HReg fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess); - - addInstr(env, PPCInstr_Dfp64Binary(Pfp_DIEX, fr_dst, fr_srcL, - fr_srcR)); -@@ -4246,27 +4379,28 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - HReg r_srcHi = newVRegF(env); - HReg r_srcLo = newVRegF(env); - -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo)); - return fr_dst; - - } else if (fpop == Pfp_DRINTN) { - HReg fr_src = newVRegF(env); -- PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1); -+ PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess); - - /* NOTE, this IOP takes a DFP value and rounds to the - * neares floating point integer value, i.e. fractional part - * is zero. The result is a decimal floating point number. - * the INT in the name is a bit misleading. - */ -- fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2); -+ fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_DfpRound(fr_dst, fr_src, r_rmc)); - return fr_dst; - - } else if (fpop == Pfp_DRSP) { -- HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2); -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - addInstr(env, PPCInstr_Dfp64Unary(fpop, fr_dst, fr_src)); - return fr_dst; - -@@ -4274,19 +4408,20 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - HReg fr_src = newVRegF(env); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); - sub_from_sp( env, 16 ); - - // put the I64 value into a floating point register - if (mode64) { -- HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - - addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/)); - } else { - HReg tmpHi, tmpLo; - PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) ); - -- iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg2); -+ iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*mode32*/)); - addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*mode32*/)); - } -@@ -4304,8 +4439,8 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - default: break; - } - if (fpop != Pfp_INVALID) { -- HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg1); -- PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2); -+ HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess); -+ PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess); - - /* shift value must be an immediate value */ - vassert(shift->tag == Pri_Imm); -@@ -4322,13 +4457,13 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - } - if (fpop != Pfp_INVALID) { - HReg fr_srcL = newVRegF(env); -- HReg fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2); -+ HReg fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - sub_from_sp( env, 16 ); - - if (env->mode64) { - // put the I64 value into a floating point reg -- HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1); -+ HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); - - addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/)); - } else { -@@ -4337,7 +4472,8 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - HReg tmpLo; - PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) ); - -- iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg1); -+ iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg1, -+ IEndianess); - addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*!mode64*/)); - addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*!mode64*/)); - } -@@ -4371,10 +4507,10 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - } - if (fpop != Pfp_INVALID) { - HReg r_dst = newVRegF( env ); -- HReg r_srcL = iselDfp64Expr( env, triop->arg2 ); -- HReg r_srcR = iselDfp64Expr( env, triop->arg3 ); -+ HReg r_srcL = iselDfp64Expr( env, triop->arg2, IEndianess ); -+ HReg r_srcR = iselDfp64Expr( env, triop->arg3, IEndianess ); - -- set_FPU_DFP_rounding_mode( env, triop->arg1 ); -+ set_FPU_DFP_rounding_mode( env, triop->arg1, IEndianess ); - addInstr( env, PPCInstr_Dfp64Binary( fpop, r_dst, r_srcL, r_srcR ) ); - return r_dst; - } -@@ -4386,9 +4522,9 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - } - if (fpop == Pfp_DQUA) { - HReg r_dst = newVRegF(env); -- HReg r_srcL = iselDfp64Expr(env, triop->arg2); -- HReg r_srcR = iselDfp64Expr(env, triop->arg3); -- PPCRI* rmc = iselWordExpr_RI(env, triop->arg1); -+ HReg r_srcL = iselDfp64Expr(env, triop->arg2, IEndianess); -+ HReg r_srcR = iselDfp64Expr(env, triop->arg3, IEndianess); -+ PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess); - addInstr(env, PPCInstr_DfpQuantize(fpop, r_dst, r_srcL, r_srcR, - rmc)); - return r_dst; -@@ -4396,10 +4532,10 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - } else if (fpop == Pfp_RRDTR) { - HReg r_dst = newVRegF(env); - HReg r_srcL = newVRegF(env); -- HReg r_srcR = iselDfp64Expr(env, triop->arg3); -- PPCRI* rmc = iselWordExpr_RI(env, triop->arg1); -+ HReg r_srcR = iselDfp64Expr(env, triop->arg3, IEndianess); -+ PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); -- HReg i8_val = iselWordExpr_R(env, triop->arg2); -+ HReg i8_val = iselWordExpr_R(env, triop->arg2, IEndianess); - - /* Move I8 to float register to issue instruction */ - sub_from_sp( env, 16 ); -@@ -4421,15 +4557,17 @@ static HReg iselDfp64Expr_wrk(ISelEnv* e - vpanic( "iselDfp64Expr_wrk(ppc)" ); - } - --static void iselDfp128Expr(HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e) -+static void iselDfp128Expr(HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e, -+ IREndness IEndianess) - { -- iselDfp128Expr_wrk( rHi, rLo, env, e ); -+ iselDfp128Expr_wrk( rHi, rLo, env, e, IEndianess ); - vassert( hregIsVirtual(*rHi) ); - vassert( hregIsVirtual(*rLo) ); - } - - /* DO NOT CALL THIS DIRECTLY */ --static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, IRExpr* e) -+static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, IRExpr* e, -+ IREndness IEndianess) - { - vassert( e ); - vassert( typeOfIRExpr(env->type_env,e) == Ity_D128 ); -@@ -4450,13 +4588,14 @@ static void iselDfp128Expr_wrk(HReg* rHi - - // put the I64 value into a floating point reg - if (env->mode64) { -- HReg tmp = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg tmp = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/)); - } else { - HReg tmpHi, tmpLo; - PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) ); - -- iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg, -+ IEndianess); - addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*mode32*/)); - addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*mode32*/)); - } -@@ -4467,7 +4606,7 @@ static void iselDfp128Expr_wrk(HReg* rHi - } - - if (e->Iex.Unop.op == Iop_D64toD128) { -- HReg r_src = iselDfp64Expr(env, e->Iex.Unop.arg); -+ HReg r_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess); - - /* Source is 64bit, result is 128 bit. High 64bit source arg, - * is ignored by the instruction. Set high arg to r_src just -@@ -4488,8 +4627,8 @@ static void iselDfp128Expr_wrk(HReg* rHi - - switch (e->Iex.Binop.op) { - case Iop_D64HLtoD128: -- r_srcHi = iselDfp64Expr( env, e->Iex.Binop.arg1 ); -- r_srcLo = iselDfp64Expr( env, e->Iex.Binop.arg2 ); -+ r_srcHi = iselDfp64Expr( env, e->Iex.Binop.arg1, IEndianess ); -+ r_srcLo = iselDfp64Expr( env, e->Iex.Binop.arg2, IEndianess ); - *rHi = r_srcHi; - *rLo = r_srcLo; - return; -@@ -4498,8 +4637,9 @@ static void iselDfp128Expr_wrk(HReg* rHi - PPCFpOp fpop = Pfp_DRDPQ; - HReg fr_dst = newVRegF(env); - -- set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1 ); -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2); -+ set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess ); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2, -+ IEndianess); - addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo)); - - /* Need to meet the interface spec but the result is -@@ -4513,10 +4653,11 @@ static void iselDfp128Expr_wrk(HReg* rHi - case Iop_ShrD128: { - HReg fr_dst_hi = newVRegF(env); - HReg fr_dst_lo = newVRegF(env); -- PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2); -+ PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess); - PPCFpOp fpop = Pfp_DSCLIQ; /* fix later if necessary */ - -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg1); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg1, -+ IEndianess); - - if (e->Iex.Binop.op == Iop_ShrD128) - fpop = Pfp_DSCRIQ; -@@ -4531,10 +4672,11 @@ static void iselDfp128Expr_wrk(HReg* rHi - case Iop_RoundD128toInt: { - HReg r_dstHi = newVRegF(env); - HReg r_dstLo = newVRegF(env); -- PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1); -+ PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess); - - // will set R and RMC when issuing instruction -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2, -+ IEndianess); - - addInstr(env, PPCInstr_DfpRound128(r_dstHi, r_dstLo, - r_srcHi, r_srcLo, r_rmc)); -@@ -4550,17 +4692,19 @@ static void iselDfp128Expr_wrk(HReg* rHi - r_srcHi = newVRegF(env); - r_srcLo = newVRegF(env); - -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2, -+ IEndianess); - - /* Move I64 to float register to issue instruction */ - if (env->mode64) { -- HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1); -+ HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); - addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/)); - } else { - HReg tmpHi, tmpLo; - PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) ); - -- iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg); -+ iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg, -+ IEndianess); - addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*mode32*/)); - addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*mode32*/)); - } -@@ -4608,9 +4752,9 @@ static void iselDfp128Expr_wrk(HReg* rHi - HReg r_srcRLo = newVRegV( env ); - - /* dst will be used to pass in the left operand and get the result. */ -- iselDfp128Expr( &r_dstHi, &r_dstLo, env, triop->arg2 ); -- iselDfp128Expr( &r_srcRHi, &r_srcRLo, env, triop->arg3 ); -- set_FPU_DFP_rounding_mode( env, triop->arg1 ); -+ iselDfp128Expr( &r_dstHi, &r_dstLo, env, triop->arg2, IEndianess ); -+ iselDfp128Expr( &r_srcRHi, &r_srcRLo, env, triop->arg3, IEndianess ); -+ set_FPU_DFP_rounding_mode( env, triop->arg1, IEndianess ); - addInstr( env, - PPCInstr_Dfp128Binary( fpop, r_dstHi, r_dstLo, - r_srcRHi, r_srcRLo ) ); -@@ -4626,11 +4770,11 @@ static void iselDfp128Expr_wrk(HReg* rHi - if (fpop == Pfp_DQUAQ) { - HReg r_srcHi = newVRegF(env); - HReg r_srcLo = newVRegF(env); -- PPCRI* rmc = iselWordExpr_RI(env, triop->arg1); -+ PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess); - - /* dst will be used to pass in the left operand and get the result */ -- iselDfp128Expr(&r_dstHi, &r_dstLo, env, triop->arg2); -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, triop->arg3); -+ iselDfp128Expr(&r_dstHi, &r_dstLo, env, triop->arg2, IEndianess); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, triop->arg3, IEndianess); - - // will set RMC when issuing instruction - addInstr(env, PPCInstr_DfpQuantize128(fpop, r_dstHi, r_dstLo, -@@ -4642,13 +4786,13 @@ static void iselDfp128Expr_wrk(HReg* rHi - } else if (fpop == Pfp_DRRNDQ) { - HReg r_srcHi = newVRegF(env); - HReg r_srcLo = newVRegF(env); -- PPCRI* rmc = iselWordExpr_RI(env, triop->arg1); -+ PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess); - PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) ); - PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) ); -- HReg i8_val = iselWordExpr_R(env, triop->arg2); -+ HReg i8_val = iselWordExpr_R(env, triop->arg2, IEndianess); - HReg r_zero = newVRegI( env ); - -- iselDfp128Expr(&r_srcHi, &r_srcLo, env, triop->arg3); -+ iselDfp128Expr(&r_srcHi, &r_srcLo, env, triop->arg3, IEndianess); - - /* dst will be used to pass in the left operand and get the result */ - /* Move I8 to float register to issue instruction. Note, the -@@ -4690,9 +4834,9 @@ static void iselDfp128Expr_wrk(HReg* rHi - /*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/ - /*---------------------------------------------------------*/ - --static HReg iselVecExpr ( ISelEnv* env, IRExpr* e ) -+static HReg iselVecExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { -- HReg r = iselVecExpr_wrk( env, e ); -+ HReg r = iselVecExpr_wrk( env, e, IEndianess ); - # if 0 - vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); - # endif -@@ -4702,7 +4846,7 @@ static HReg iselVecExpr ( ISelEnv* env, - } - - /* DO NOT CALL THIS DIRECTLY */ --static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e ) -+static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess ) - { - Bool mode64 = env->mode64; - PPCAvOp op = Pav_INVALID; -@@ -4726,11 +4870,12 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - return dst; - } - -- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) { -+ if (e->tag == Iex_Load && e->Iex.Load.end == IEndianess) { - PPCAMode* am_addr; - HReg v_dst = newVRegV(env); - vassert(e->Iex.Load.ty == Ity_V128); -- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_V128/*xfer*/); -+ am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_V128/*xfer*/, -+ IEndianess); - addInstr(env, PPCInstr_AvLdSt( True/*load*/, 16, v_dst, am_addr)); - return v_dst; - } -@@ -4739,14 +4884,14 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - switch (e->Iex.Unop.op) { - - case Iop_NotV128: { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvUnary(Pav_NOT, dst, arg)); - return dst; - } - - case Iop_CmpNEZ8x16: { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg zero = newVRegV(env); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero)); -@@ -4756,7 +4901,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - } - - case Iop_CmpNEZ16x8: { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg zero = newVRegV(env); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero)); -@@ -4766,7 +4911,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - } - - case Iop_CmpNEZ32x4: { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg zero = newVRegV(env); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero)); -@@ -4776,7 +4921,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - } - - case Iop_CmpNEZ64x2: { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg zero = newVRegV(env); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero)); -@@ -4797,7 +4942,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_RoundF32x4_RZ: fpop = Pavfp_ROUNDZ; goto do_32Fx4_unary; - do_32Fx4_unary: - { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvUn32Fx4(fpop, dst, arg)); - return dst; -@@ -4805,7 +4950,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - - case Iop_32UtoV128: { - HReg r_aligned16, r_zeros; -- HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess); - HReg dst = newVRegV(env); - PPCAMode *am_off0, *am_off4, *am_off8, *am_off12; - sub_from_sp( env, 32 ); // Move SP down -@@ -4820,15 +4965,24 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - /* Store zeros */ - r_zeros = newVRegI(env); - addInstr(env, PPCInstr_LI(r_zeros, 0x0, mode64)); -- addInstr(env, PPCInstr_Store( 4, am_off0, r_zeros, mode64 )); -+ if (IEndianess == Iend_LE) -+ addInstr(env, PPCInstr_Store( 4, am_off0, r_src, mode64 )); -+ else -+ addInstr(env, PPCInstr_Store( 4, am_off0, r_zeros, mode64 )); - addInstr(env, PPCInstr_Store( 4, am_off4, r_zeros, mode64 )); - addInstr(env, PPCInstr_Store( 4, am_off8, r_zeros, mode64 )); - - /* Store r_src in low word of quadword-aligned mem */ -- addInstr(env, PPCInstr_Store( 4, am_off12, r_src, mode64 )); -+ if (IEndianess == Iend_LE) -+ addInstr(env, PPCInstr_Store( 4, am_off12, r_zeros, mode64 )); -+ else -+ addInstr(env, PPCInstr_Store( 4, am_off12, r_src, mode64 )); - - /* Load word into low word of quadword vector reg */ -- addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off12 )); -+ if (IEndianess == Iend_LE) -+ addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off0 )); -+ else -+ addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off12 )); - - add_to_sp( env, 32 ); // Reset SP - return dst; -@@ -4837,11 +4991,11 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_Dup8x16: - case Iop_Dup16x8: - case Iop_Dup32x4: -- return mk_AvDuplicateRI(env, e->Iex.Unop.arg); -+ return mk_AvDuplicateRI(env, e->Iex.Unop.arg, IEndianess); - - case Iop_CipherSV128: op = Pav_CIPHERSUBV128; goto do_AvCipherV128Un; - do_AvCipherV128Un: { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvCipherV128Unary(op, dst, arg)); - return dst; -@@ -4854,7 +5008,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_PwBitMtxXpose64x2: fpop = Pav_BITMTXXPOSE; goto do_zerocnt; - do_zerocnt: - { -- HReg arg = iselVecExpr(env, e->Iex.Unop.arg); -+ HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvUnary(fpop, dst, arg)); - return dst; -@@ -4884,11 +5038,11 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - am_off12 = PPCAMode_IR( 12, r_aligned16 ); - - /* Do the less significant 64 bits */ -- iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2); -+ iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_Store( 4, am_off12, r0, mode64 )); - addInstr(env, PPCInstr_Store( 4, am_off8, r1, mode64 )); - /* Do the more significant 64 bits */ -- iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1); -+ iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1, IEndianess); - addInstr(env, PPCInstr_Store( 4, am_off4, r2, mode64 )); - addInstr(env, PPCInstr_Store( 4, am_off0, r3, mode64 )); - -@@ -4898,8 +5052,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - add_to_sp( env, 32 ); // Reset SP - return dst; - } else { -- HReg rHi = iselWordExpr_R(env, e->Iex.Binop.arg1); -- HReg rLo = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ HReg rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); -+ HReg rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - HReg r_aligned16; - PPCAMode *am_off0, *am_off8; -@@ -4912,9 +5066,13 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - am_off8 = PPCAMode_IR( 8, r_aligned16 ); - - /* Store 2*I64 to stack */ -- addInstr(env, PPCInstr_Store( 8, am_off0, rHi, mode64 )); -- addInstr(env, PPCInstr_Store( 8, am_off8, rLo, mode64 )); -- -+ if (IEndianess == Iend_LE) { -+ addInstr(env, PPCInstr_Store( 8, am_off0, rLo, mode64 )); -+ addInstr(env, PPCInstr_Store( 8, am_off8, rHi, mode64 )); -+ } else { -+ addInstr(env, PPCInstr_Store( 8, am_off0, rHi, mode64 )); -+ addInstr(env, PPCInstr_Store( 8, am_off8, rLo, mode64 )); -+ } - /* Fetch result back from stack. */ - addInstr(env, PPCInstr_AvLdSt(True/*ld*/, 16, dst, am_off0)); - -@@ -4933,16 +5091,16 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_CmpGE32Fx4: fpop = Pavfp_CMPGEF; goto do_32Fx4; - do_32Fx4: - { -- HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg argR = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBin32Fx4(fpop, dst, argL, argR)); - return dst; - } - - case Iop_CmpLE32Fx4: { -- HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg argR = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg argR = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - - /* stay consistent with native ppc compares: -@@ -4950,8 +5108,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - so: le == NOT(gt OR isNan) - */ - HReg isNanLR = newVRegV(env); -- HReg isNanL = isNan(env, argL); -- HReg isNanR = isNan(env, argR); -+ HReg isNanL = isNan(env, argL, IEndianess); -+ HReg isNanR = isNan(env, argR, IEndianess); - addInstr(env, PPCInstr_AvBinary(Pav_OR, isNanLR, - isNanL, isNanR)); - -@@ -4966,8 +5124,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_OrV128: op = Pav_OR; goto do_AvBin; - case Iop_XorV128: op = Pav_XOR; goto do_AvBin; - do_AvBin: { -- HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBinary(op, dst, arg1, arg2)); - return dst; -@@ -4998,8 +5156,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_CmpGT8Sx16: op = Pav_CMPGTS; goto do_AvBin8x16; - case Iop_PolynomialMulAdd8x16: op = Pav_POLYMULADD; goto do_AvBin8x16; - do_AvBin8x16: { -- HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBin8x16(op, dst, arg1, arg2)); - return dst; -@@ -5033,8 +5191,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_CmpGT16Sx8: op = Pav_CMPGTS; goto do_AvBin16x8; - case Iop_PolynomialMulAdd16x8: op = Pav_POLYMULADD; goto do_AvBin16x8; - do_AvBin16x8: { -- HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBin16x8(op, dst, arg1, arg2)); - return dst; -@@ -5071,8 +5229,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_CatEvenLanes32x4: op = Pav_CATEVEN; goto do_AvBin32x4; - case Iop_PolynomialMulAdd32x4: op = Pav_POLYMULADD; goto do_AvBin32x4; - do_AvBin32x4: { -- HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBin32x4(op, dst, arg1, arg2)); - return dst; -@@ -5098,8 +5256,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_CmpGT64Sx2: op = Pav_CMPGTS; goto do_AvBin64x2; - case Iop_PolynomialMulAdd64x2: op = Pav_POLYMULADD; goto do_AvBin64x2; - do_AvBin64x2: { -- HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvBin64x2(op, dst, arg1, arg2)); - return dst; -@@ -5108,9 +5266,9 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_ShlN8x16: op = Pav_SHL; goto do_AvShift8x16; - case Iop_SarN8x16: op = Pav_SAR; goto do_AvShift8x16; - do_AvShift8x16: { -- HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); -+ HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); - HReg dst = newVRegV(env); -- HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2); -+ HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_AvBin8x16(op, dst, r_src, v_shft)); - return dst; - } -@@ -5119,9 +5277,9 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_ShrN16x8: op = Pav_SHR; goto do_AvShift16x8; - case Iop_SarN16x8: op = Pav_SAR; goto do_AvShift16x8; - do_AvShift16x8: { -- HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); -+ HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); - HReg dst = newVRegV(env); -- HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2); -+ HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_AvBin16x8(op, dst, r_src, v_shft)); - return dst; - } -@@ -5130,9 +5288,9 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_ShrN32x4: op = Pav_SHR; goto do_AvShift32x4; - case Iop_SarN32x4: op = Pav_SAR; goto do_AvShift32x4; - do_AvShift32x4: { -- HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); -+ HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); - HReg dst = newVRegV(env); -- HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2); -+ HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_AvBin32x4(op, dst, r_src, v_shft)); - return dst; - } -@@ -5141,9 +5299,9 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_ShrN64x2: op = Pav_SHR; goto do_AvShift64x2; - case Iop_SarN64x2: op = Pav_SAR; goto do_AvShift64x2; - do_AvShift64x2: { -- HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); -+ HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); - HReg dst = newVRegV(env); -- HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2); -+ HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_AvBin64x2(op, dst, r_src, v_shft)); - return dst; - } -@@ -5152,8 +5310,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_ShlV128: op = Pav_SHL; goto do_AvShiftV128; - do_AvShiftV128: { - HReg dst = newVRegV(env); -- HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2); -+ HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess); - /* Note: shift value gets masked by 127 */ - addInstr(env, PPCInstr_AvBinary(op, dst, r_src, v_shft)); - return dst; -@@ -5161,8 +5319,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - - case Iop_Perm8x16: { - HReg dst = newVRegV(env); -- HReg v_src = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg v_ctl = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg v_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg v_ctl = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_AvPerm(dst, v_src, v_src, v_ctl)); - return dst; - } -@@ -5172,8 +5330,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_NCipherV128: op = Pav_NCIPHERV128; goto do_AvCipherV128; - case Iop_NCipherLV128:op = Pav_NCIPHERLV128; goto do_AvCipherV128; - do_AvCipherV128: { -- HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); -- HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2); -+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); -+ HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess); - HReg dst = newVRegV(env); - addInstr(env, PPCInstr_AvCipherV128Binary(op, dst, arg1, arg2)); - return dst; -@@ -5182,9 +5340,9 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_SHA256:op = Pav_SHA256; goto do_AvHashV128; - case Iop_SHA512:op = Pav_SHA512; goto do_AvHashV128; - do_AvHashV128: { -- HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1); -+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess); - HReg dst = newVRegV(env); -- PPCRI* s_field = iselWordExpr_RI(env, e->Iex.Binop.arg2); -+ PPCRI* s_field = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess); - addInstr(env, PPCInstr_AvHashV128Binary(op, dst, arg1, s_field)); - return dst; - } -@@ -5199,10 +5357,10 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - case Iop_BCDAdd:op = Pav_BCDAdd; goto do_AvBCDV128; - case Iop_BCDSub:op = Pav_BCDSub; goto do_AvBCDV128; - do_AvBCDV128: { -- HReg arg1 = iselVecExpr(env, triop->arg1); -- HReg arg2 = iselVecExpr(env, triop->arg2); -+ HReg arg1 = iselVecExpr(env, triop->arg1, IEndianess); -+ HReg arg2 = iselVecExpr(env, triop->arg2, IEndianess); - HReg dst = newVRegV(env); -- PPCRI* ps = iselWordExpr_RI(env, triop->arg3); -+ PPCRI* ps = iselWordExpr_RI(env, triop->arg3, IEndianess); - addInstr(env, PPCInstr_AvBCDV128Trinary(op, dst, arg1, arg2, ps)); - return dst; - } -@@ -5235,7 +5393,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* e - /*--- ISEL: Statements ---*/ - /*---------------------------------------------------------*/ - --static void iselStmt ( ISelEnv* env, IRStmt* stmt ) -+static void iselStmt ( ISelEnv* env, IRStmt* stmt, IREndness IEndianess ) - { - Bool mode64 = env->mode64; - if (vex_traceflags & VEX_TRACE_VCODE) { -@@ -5252,7 +5410,7 @@ static void iselStmt ( ISelEnv* env, IRS - IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); - IREndness end = stmt->Ist.Store.end; - -- if (end != Iend_BE) -+ if (end != IEndianess) - goto stmt_fail; - if (!mode64 && (tya != Ity_I32)) - goto stmt_fail; -@@ -5262,48 +5420,54 @@ static void iselStmt ( ISelEnv* env, IRS - if (tyd == Ity_I8 || tyd == Ity_I16 || tyd == Ity_I32 || - (mode64 && (tyd == Ity_I64))) { - PPCAMode* am_addr -- = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/); -- HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data); -+ = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/, -+ IEndianess); -+ HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data, IEndianess); - addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(tyd)), - am_addr, r_src, mode64 )); - return; - } - if (tyd == Ity_F64) { - PPCAMode* am_addr -- = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/); -- HReg fr_src = iselDblExpr(env, stmt->Ist.Store.data); -+ = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/, -+ IEndianess); -+ HReg fr_src = iselDblExpr(env, stmt->Ist.Store.data, IEndianess); - addInstr(env, - PPCInstr_FpLdSt(False/*store*/, 8, fr_src, am_addr)); - return; - } - if (tyd == Ity_F32) { - PPCAMode* am_addr -- = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/); -- HReg fr_src = iselFltExpr(env, stmt->Ist.Store.data); -+ = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/, -+ IEndianess); -+ HReg fr_src = iselFltExpr(env, stmt->Ist.Store.data, IEndianess); - addInstr(env, - PPCInstr_FpLdSt(False/*store*/, 4, fr_src, am_addr)); - return; - } - if (tyd == Ity_D64) { - PPCAMode* am_addr -- = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/); -- HReg fr_src = iselDfp64Expr(env, stmt->Ist.Store.data); -+ = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/, -+ IEndianess); -+ HReg fr_src = iselDfp64Expr(env, stmt->Ist.Store.data, IEndianess); - addInstr(env, - PPCInstr_FpLdSt(False/*store*/, 8, fr_src, am_addr)); - return; - } - if (tyd == Ity_D32) { - PPCAMode* am_addr -- = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/); -- HReg fr_src = iselDfp32Expr(env, stmt->Ist.Store.data); -+ = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/, -+ IEndianess); -+ HReg fr_src = iselDfp32Expr(env, stmt->Ist.Store.data, IEndianess); - addInstr(env, - PPCInstr_FpLdSt(False/*store*/, 4, fr_src, am_addr)); - return; - } - if (tyd == Ity_V128) { - PPCAMode* am_addr -- = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/); -- HReg v_src = iselVecExpr(env, stmt->Ist.Store.data); -+ = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/, -+ IEndianess); -+ HReg v_src = iselVecExpr(env, stmt->Ist.Store.data, IEndianess); - addInstr(env, - PPCInstr_AvLdSt(False/*store*/, 16, v_src, am_addr)); - return; -@@ -5313,8 +5477,9 @@ static void iselStmt ( ISelEnv* env, IRS - short to arse around trying and possibly failing to adjust - the offset in a 'reg+offset' style amode. */ - HReg rHi32, rLo32; -- HReg r_addr = iselWordExpr_R(env, stmt->Ist.Store.addr); -- iselInt64Expr( &rHi32, &rLo32, env, stmt->Ist.Store.data ); -+ HReg r_addr = iselWordExpr_R(env, stmt->Ist.Store.addr, IEndianess); -+ iselInt64Expr( &rHi32, &rLo32, env, stmt->Ist.Store.data, -+ IEndianess ); - addInstr(env, PPCInstr_Store( 4/*byte-store*/, - PPCAMode_IR( 0, r_addr ), - rHi32, -@@ -5333,7 +5498,7 @@ static void iselStmt ( ISelEnv* env, IRS - IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data); - if (ty == Ity_I8 || ty == Ity_I16 || - ty == Ity_I32 || ((ty == Ity_I64) && mode64)) { -- HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data); -+ HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data, IEndianess); - PPCAMode* am_addr = PPCAMode_IR( stmt->Ist.Put.offset, - GuestStatePtr(mode64) ); - addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(ty)), -@@ -5345,7 +5510,7 @@ static void iselStmt ( ISelEnv* env, IRS - PPCAMode* am_addr = PPCAMode_IR( stmt->Ist.Put.offset, - GuestStatePtr(mode64) ); - PPCAMode* am_addr4 = advance4(env, am_addr); -- iselInt64Expr(&rHi,&rLo, env, stmt->Ist.Put.data); -+ iselInt64Expr(&rHi,&rLo, env, stmt->Ist.Put.data, IEndianess); - addInstr(env, PPCInstr_Store( 4, am_addr, rHi, mode64 )); - addInstr(env, PPCInstr_Store( 4, am_addr4, rLo, mode64 )); - return; -@@ -5353,7 +5518,7 @@ static void iselStmt ( ISelEnv* env, IRS - if (ty == Ity_V128) { - /* Guest state vectors are 16byte aligned, - so don't need to worry here */ -- HReg v_src = iselVecExpr(env, stmt->Ist.Put.data); -+ HReg v_src = iselVecExpr(env, stmt->Ist.Put.data, IEndianess); - PPCAMode* am_addr = PPCAMode_IR( stmt->Ist.Put.offset, - GuestStatePtr(mode64) ); - addInstr(env, -@@ -5361,7 +5526,7 @@ static void iselStmt ( ISelEnv* env, IRS - return; - } - if (ty == Ity_F64) { -- HReg fr_src = iselDblExpr(env, stmt->Ist.Put.data); -+ HReg fr_src = iselDblExpr(env, stmt->Ist.Put.data, IEndianess); - PPCAMode* am_addr = PPCAMode_IR( stmt->Ist.Put.offset, - GuestStatePtr(mode64) ); - addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8, -@@ -5370,7 +5535,7 @@ static void iselStmt ( ISelEnv* env, IRS - } - if (ty == Ity_D32) { - /* The 32-bit value is stored in a 64-bit register */ -- HReg fr_src = iselDfp32Expr( env, stmt->Ist.Put.data ); -+ HReg fr_src = iselDfp32Expr( env, stmt->Ist.Put.data, IEndianess ); - PPCAMode* am_addr = PPCAMode_IR( stmt->Ist.Put.offset, - GuestStatePtr(mode64) ); - addInstr( env, PPCInstr_FpLdSt( False/*store*/, 8, -@@ -5378,7 +5543,7 @@ static void iselStmt ( ISelEnv* env, IRS - return; - } - if (ty == Ity_D64) { -- HReg fr_src = iselDfp64Expr( env, stmt->Ist.Put.data ); -+ HReg fr_src = iselDfp64Expr( env, stmt->Ist.Put.data, IEndianess ); - PPCAMode* am_addr = PPCAMode_IR( stmt->Ist.Put.offset, - GuestStatePtr(mode64) ); - addInstr( env, PPCInstr_FpLdSt( False/*store*/, 8, fr_src, am_addr ) ); -@@ -5394,16 +5559,17 @@ static void iselStmt ( ISelEnv* env, IRS - PPCAMode* dst_am - = genGuestArrayOffset( - env, puti->descr, -- puti->ix, puti->bias ); -+ puti->ix, puti->bias, -+ IEndianess ); - IRType ty = typeOfIRExpr(env->type_env, puti->data); - if (mode64 && ty == Ity_I64) { -- HReg r_src = iselWordExpr_R(env, puti->data); -+ HReg r_src = iselWordExpr_R(env, puti->data, IEndianess); - addInstr(env, PPCInstr_Store( toUChar(8), - dst_am, r_src, mode64 )); - return; - } - if ((!mode64) && ty == Ity_I32) { -- HReg r_src = iselWordExpr_R(env, puti->data); -+ HReg r_src = iselWordExpr_R(env, puti->data, IEndianess); - addInstr(env, PPCInstr_Store( toUChar(4), - dst_am, r_src, mode64 )); - return; -@@ -5418,14 +5584,15 @@ static void iselStmt ( ISelEnv* env, IRS - if (ty == Ity_I8 || ty == Ity_I16 || - ty == Ity_I32 || ((ty == Ity_I64) && mode64)) { - HReg r_dst = lookupIRTemp(env, tmp); -- HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data); -+ HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data, IEndianess); - addInstr(env, mk_iMOVds_RR( r_dst, r_src )); - return; - } - if (!mode64 && ty == Ity_I64) { - HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo; - -- iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data); -+ iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data, -+ IEndianess); - lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp); - addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) ); - addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) ); -@@ -5433,7 +5600,8 @@ static void iselStmt ( ISelEnv* env, IRS - } - if (mode64 && ty == Ity_I128) { - HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo; -- iselInt128Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data); -+ iselInt128Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data, -+ IEndianess); - lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp); - addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) ); - addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) ); -@@ -5445,7 +5613,7 @@ static void iselStmt ( ISelEnv* env, IRS - - iselInt128Expr_to_32x4(&r_srcHi, &r_srcMedHi, - &r_srcMedLo, &r_srcLo, -- env, stmt->Ist.WrTmp.data); -+ env, stmt->Ist.WrTmp.data, IEndianess); - - lookupIRTempQuad( &r_dstHi, &r_dstMedHi, &r_dstMedLo, - &r_dstLo, env, tmp); -@@ -5457,38 +5625,39 @@ static void iselStmt ( ISelEnv* env, IRS - return; - } - if (ty == Ity_I1) { -- PPCCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data); -+ PPCCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data, -+ IEndianess); - HReg r_dst = lookupIRTemp(env, tmp); - addInstr(env, PPCInstr_Set(cond, r_dst)); - return; - } - if (ty == Ity_F64) { - HReg fr_dst = lookupIRTemp(env, tmp); -- HReg fr_src = iselDblExpr(env, stmt->Ist.WrTmp.data); -+ HReg fr_src = iselDblExpr(env, stmt->Ist.WrTmp.data, IEndianess); - addInstr(env, PPCInstr_FpUnary(Pfp_MOV, fr_dst, fr_src)); - return; - } - if (ty == Ity_F32) { - HReg fr_dst = lookupIRTemp(env, tmp); -- HReg fr_src = iselFltExpr(env, stmt->Ist.WrTmp.data); -+ HReg fr_src = iselFltExpr(env, stmt->Ist.WrTmp.data, IEndianess); - addInstr(env, PPCInstr_FpUnary(Pfp_MOV, fr_dst, fr_src)); - return; - } - if (ty == Ity_D32) { - HReg fr_dst = lookupIRTemp(env, tmp); -- HReg fr_src = iselDfp32Expr(env, stmt->Ist.WrTmp.data); -+ HReg fr_src = iselDfp32Expr(env, stmt->Ist.WrTmp.data, IEndianess); - addInstr(env, PPCInstr_Dfp64Unary(Pfp_MOV, fr_dst, fr_src)); - return; - } - if (ty == Ity_V128) { - HReg v_dst = lookupIRTemp(env, tmp); -- HReg v_src = iselVecExpr(env, stmt->Ist.WrTmp.data); -+ HReg v_src = iselVecExpr(env, stmt->Ist.WrTmp.data, IEndianess); - addInstr(env, PPCInstr_AvUnary(Pav_MOV, v_dst, v_src)); - return; - } - if (ty == Ity_D64) { - HReg fr_dst = lookupIRTemp( env, tmp ); -- HReg fr_src = iselDfp64Expr( env, stmt->Ist.WrTmp.data ); -+ HReg fr_src = iselDfp64Expr( env, stmt->Ist.WrTmp.data, IEndianess ); - addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dst, fr_src ) ); - return; - } -@@ -5496,7 +5665,8 @@ static void iselStmt ( ISelEnv* env, IRS - HReg fr_srcHi, fr_srcLo, fr_dstHi, fr_dstLo; - // lookupDfp128IRTempPair( &fr_dstHi, &fr_dstLo, env, tmp ); - lookupIRTempPair( &fr_dstHi, &fr_dstLo, env, tmp ); -- iselDfp128Expr( &fr_srcHi, &fr_srcLo, env, stmt->Ist.WrTmp.data ); -+ iselDfp128Expr( &fr_srcHi, &fr_srcLo, env, stmt->Ist.WrTmp.data, -+ IEndianess ); - addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dstHi, fr_srcHi ) ); - addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dstLo, fr_srcLo ) ); - return; -@@ -5510,7 +5680,7 @@ static void iselStmt ( ISelEnv* env, IRS - IRType tyRes = typeOfIRTemp(env->type_env, res); - IRType tyAddr = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.addr); - -- if (stmt->Ist.LLSC.end != Iend_BE) -+ if (stmt->Ist.LLSC.end != IEndianess) - goto stmt_fail; - if (!mode64 && (tyAddr != Ity_I32)) - goto stmt_fail; -@@ -5519,7 +5689,7 @@ static void iselStmt ( ISelEnv* env, IRS - - if (stmt->Ist.LLSC.storedata == NULL) { - /* LL */ -- HReg r_addr = iselWordExpr_R( env, stmt->Ist.LLSC.addr ); -+ HReg r_addr = iselWordExpr_R( env, stmt->Ist.LLSC.addr, IEndianess ); - HReg r_dst = lookupIRTemp(env, res); - if (tyRes == Ity_I32) { - addInstr(env, PPCInstr_LoadL( 4, r_dst, r_addr, mode64 )); -@@ -5533,8 +5703,9 @@ static void iselStmt ( ISelEnv* env, IRS - } else { - /* SC */ - HReg r_res = lookupIRTemp(env, res); /* :: Ity_I1 */ -- HReg r_a = iselWordExpr_R(env, stmt->Ist.LLSC.addr); -- HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata); -+ HReg r_a = iselWordExpr_R(env, stmt->Ist.LLSC.addr, IEndianess); -+ HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata, -+ IEndianess); - HReg r_tmp = newVRegI(env); - IRType tyData = typeOfIRExpr(env->type_env, - stmt->Ist.LLSC.storedata); -@@ -5603,7 +5774,8 @@ static void iselStmt ( ISelEnv* env, IRS - value and the call is skipped. */ - UInt addToSp = 0; - RetLoc rloc = mk_RetLoc_INVALID(); -- doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args ); -+ doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args, -+ IEndianess ); - vassert(is_sane_RetLoc(rloc)); - - /* Now figure out what to do with the returned value, if any. */ -@@ -5698,7 +5870,7 @@ static void iselStmt ( ISelEnv* env, IRS - if (mode64 && dst->tag != Ico_U64) - vpanic("iselStmt(ppc64): Ist_Exit: dst is not a 64-bit value"); - -- PPCCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard); -+ PPCCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard, IEndianess); - PPCAMode* amCIA = PPCAMode_IR(stmt->Ist.Exit.offsIP, - hregPPC_GPR31(mode64)); - -@@ -5723,7 +5895,8 @@ static void iselStmt ( ISelEnv* env, IRS - /* .. very occasionally .. */ - /* We can't use chaining, so ask for an assisted transfer, - as that's the only alternative that is allowable. */ -- HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -+ HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst), -+ IEndianess); - addInstr(env, PPCInstr_XAssisted(r, amCIA, cc, Ijk_Boring)); - } - return; -@@ -5742,7 +5915,8 @@ static void iselStmt ( ISelEnv* env, IRS - case Ijk_Sys_syscall: - case Ijk_TInval: - { -- HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -+ HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst), -+ IEndianess); - addInstr(env, PPCInstr_XAssisted(r, amCIA, cc, - stmt->Ist.Exit.jk)); - return; -@@ -5768,7 +5942,8 @@ static void iselStmt ( ISelEnv* env, IRS - /*---------------------------------------------------------*/ - - static void iselNext ( ISelEnv* env, -- IRExpr* next, IRJumpKind jk, Int offsIP ) -+ IRExpr* next, IRJumpKind jk, Int offsIP, -+ IREndness IEndianess) - { - if (vex_traceflags & VEX_TRACE_VCODE) { - vex_printf( "\n-- PUT(%d) = ", offsIP); -@@ -5804,7 +5979,7 @@ static void iselNext ( ISelEnv* env, - /* .. very occasionally .. */ - /* We can't use chaining, so ask for an assisted transfer, - as that's the only alternative that is allowable. */ -- HReg r = iselWordExpr_R(env, next); -+ HReg r = iselWordExpr_R(env, next, IEndianess); - addInstr(env, PPCInstr_XAssisted(r, amCIA, always, - Ijk_Boring)); - } -@@ -5815,7 +5990,7 @@ static void iselNext ( ISelEnv* env, - /* Case: call/return (==boring) transfer to any address */ - switch (jk) { - case Ijk_Boring: case Ijk_Ret: case Ijk_Call: { -- HReg r = iselWordExpr_R(env, next); -+ HReg r = iselWordExpr_R(env, next, IEndianess); - PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64)); - if (env->chainingAllowed) { - addInstr(env, PPCInstr_XIndir(r, amCIA, always)); -@@ -5842,7 +6017,7 @@ static void iselNext ( ISelEnv* env, - case Ijk_Sys_syscall: - case Ijk_TInval: - { -- HReg r = iselWordExpr_R(env, next); -+ HReg r = iselWordExpr_R(env, next, IEndianess); - PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64)); - addInstr(env, PPCInstr_XAssisted(r, amCIA, always, jk)); - return; -@@ -5873,7 +6048,8 @@ HInstrArray* iselSB_PPC ( IRSB* bb, - Int offs_Host_EvC_FailAddr, - Bool chainingAllowed, - Bool addProfInc, -- Addr64 max_ga ) -+ Addr64 max_ga) -+ - { - Int i, j; - HReg hregLo, hregMedLo, hregMedHi, hregHi; -@@ -5882,7 +6058,7 @@ HInstrArray* iselSB_PPC ( IRSB* bb, - Bool mode64 = False; - UInt mask32, mask64; - PPCAMode *amCounter, *amFailAddr; -- -+ IREndness IEndianess; - - vassert(arch_host == VexArchPPC32 || arch_host == VexArchPPC64); - mode64 = arch_host == VexArchPPC64; -@@ -5905,7 +6081,13 @@ HInstrArray* iselSB_PPC ( IRSB* bb, - } - - /* Check that the host's endianness is as expected. */ -- vassert(archinfo_host->endness == VexEndnessBE); -+ vassert((archinfo_host->endness == VexEndnessBE) || -+ (archinfo_host->endness == VexEndnessLE)); -+ -+ if (archinfo_host->endness == VexEndnessBE) -+ IEndianess = Iend_BE; -+ else -+ IEndianess = Iend_LE; - - /* Make up an initial environment to use. */ - env = LibVEX_Alloc(sizeof(ISelEnv)); -@@ -6005,9 +6187,9 @@ HInstrArray* iselSB_PPC ( IRSB* bb, - - /* Ok, finally we can iterate over the statements. */ - for (i = 0; i < bb->stmts_used; i++) -- iselStmt(env, bb->stmts[i]); -+ iselStmt(env, bb->stmts[i], IEndianess); - -- iselNext(env, bb->next, bb->jumpkind, bb->offsIP); -+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP, IEndianess); - - /* record the number of vregs we used. */ - env->code->n_vregs = env->vreg_ctr; -Index: VEX/priv/guest_ppc_defs.h -=================================================================== ---- VEX/priv/guest_ppc_defs.h.orig -+++ VEX/priv/guest_ppc_defs.h -@@ -161,7 +161,8 @@ extern void ppc32g_dirtyhelper_LVS ( Vex - - extern void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst, - UInt vD_idx, UInt sh, -- UInt shift_right ); -+ UInt shift_right, -+ UInt endness ); - - #endif /* ndef __VEX_GUEST_PPC_DEFS_H */ - -Index: VEX/priv/guest_ppc_helpers.c -=================================================================== ---- VEX/priv/guest_ppc_helpers.c.orig -+++ VEX/priv/guest_ppc_helpers.c -@@ -153,10 +153,12 @@ void ppc32g_dirtyhelper_LVS ( VexGuestPP - /* CALLED FROM GENERATED CODE */ - /* DIRTY HELPER (reads guest state, writes guest mem) */ - void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst, -- UInt vD_off, UInt sh, UInt shift_right ) -+ UInt vD_off, UInt sh, UInt shift_right, -+ UInt endness ) - { - UChar ref[32]; - ULong i; -+ Int k; - /* ref[] used to be a static const array, but this doesn't work on - ppc64 because VEX doesn't load the TOC pointer for the call here, - and so we wind up picking up some totally random other data. -@@ -179,10 +181,19 @@ void ppc64g_dirtyhelper_LVS ( VexGuestPP - pU128_src = (U128*)&ref[sh]; - pU128_dst = (U128*)( ((UChar*)gst) + vD_off ); - -- (*pU128_dst)[0] = (*pU128_src)[0]; -- (*pU128_dst)[1] = (*pU128_src)[1]; -- (*pU128_dst)[2] = (*pU128_src)[2]; -- (*pU128_dst)[3] = (*pU128_src)[3]; -+ if ((0x1 & endness) == 0x0) { -+ /* Little endian */ -+ unsigned char *srcp, *dstp; -+ srcp = (unsigned char *)pU128_src; -+ dstp = (unsigned char *)pU128_dst; -+ for (k = 15; k >= 0; k--, srcp++) -+ dstp[k] = *srcp; -+ } else { -+ (*pU128_dst)[0] = (*pU128_src)[0]; -+ (*pU128_dst)[1] = (*pU128_src)[1]; -+ (*pU128_dst)[2] = (*pU128_src)[2]; -+ (*pU128_dst)[3] = (*pU128_src)[3]; -+ } - } - - -Index: VEX/priv/main_main.c -=================================================================== ---- VEX/priv/main_main.c.orig -+++ VEX/priv/main_main.c -@@ -1,6 +1,6 @@ - - /*---------------------------------------------------------------*/ --/*--- begin main_main.c ---*/ -+/*--- Begin main_main.c ---*/ - /*---------------------------------------------------------------*/ - - /* -@@ -374,8 +374,8 @@ VexTranslateResult LibVEX_Translate ( Ve - emit_PPCInstr; - host_word_type = Ity_I64; - vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); -- vassert(vta->archinfo_host.endness == VexEndnessBE -- /* later: || vta->archinfo_host.endness == VexEndnessLE */); -+ vassert(vta->archinfo_host.endness == VexEndnessBE || -+ vta->archinfo_host.endness == VexEndnessLE ); - break; - - case VexArchS390X: -@@ -543,8 +543,8 @@ VexTranslateResult LibVEX_Translate ( Ve - offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); -- vassert(vta->archinfo_guest.endness == VexEndnessBE -- /* later: || vta->archinfo_guest.endness == VexEndnessBE */); -+ vassert(vta->archinfo_guest.endness == VexEndnessBE || -+ vta->archinfo_guest.endness == VexEndnessLE ); - vassert(0 == sizeof(VexGuestPPC64State) % 16); - vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); - vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); -Index: VEX/priv/guest_ppc_toIR.c -=================================================================== ---- VEX/priv/guest_ppc_toIR.c.orig -+++ VEX/priv/guest_ppc_toIR.c -@@ -91,7 +91,8 @@ - - 7C210B78 (or 1,1,1) %R3 = client_request ( %R4 ) - 7C421378 (or 2,2,2) %R3 = guest_NRADDR -- 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11 -+ 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11 Big endian -+ 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R12 Little endian - 7C842378 (or 4,4,4) %R3 = guest_NRADDR_GPR2 - 7CA52B78 (or 5,5,5) IR injection - -@@ -101,7 +102,55 @@ - fragments designed for Valgrind to catch. - */ - -- -+/* Little Endian notes */ -+/* -+ * Vector operations in little Endian mode behave in non-obvious ways at times. -+ * Below is an attempt at explaining this. -+ * -+ * LE/BE vector example -+ * With a vector of unsigned ints declared as follows: -+ * vector unsigned int vec_inA = -+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }; -+ * The '0x11111111' word is word zero in both LE and BE format. But the -+ * loaded vector register will have word zero on the far left in BE mode and -+ * on the far right in LE mode. The lvx and stvx instructions work naturally -+ * for whatever endianness is in effect. For example, in LE mode, the stvx -+ * stores word zero (far right word) of the vector at the lowest memory -+ * address of the EA; in BE mode, stvx still stores word zero at the lowest -+ * memory address, but with word zero interpreted as the one at the far left -+ * of the register. -+ * -+ * The lxvd2x and stxvd2x instructions are not so well suited for LE mode. -+ * When the compiler generates an lxvd2x instruction to load the -+ * above-declared vector of unsigned integers, it loads the vector as two -+ * double words, but they are in BE word-wise format. To put the vector in -+ * the right order for LE, the compiler also generates an xxswapd after the -+ * load, which puts it in proper LE format. Similarly, the stxvd2x -+ * instruction has a BE bias, storing the vector in BE word-wise format. But -+ * the compiler also generates an xxswapd prior to the store, thus ensuring -+ * the vector is stored in memory in the correct LE order. -+ * -+ * Vector-flavored Iops, such Iop_V128Hito64, reference the hi and lo parts -+ * of a double words and words within a vector. Because of the reverse order -+ * of numbering for LE as described above, the high part refers to word 1 in -+ * LE format. When input data is saved to a guest state vector register -+ * (e.g., via Iop_64HLtoV128), it is first saved to memory and then the -+ * register is loaded via PPCInstr_AvLdSt, which does an lvx instruction. -+ * The saving of the data to memory must be done in proper LE order. For the -+ * inverse operation of extracting data from a vector register (e.g., -+ * Iop_V128Hito64), the register is first saved (by PPCInstr_AvLdSt resulting -+ * in stvx), and then integer registers are loaded from the memory location -+ * from where the vector register was saved. Again, this must be done in -+ * proper LE order. So for these various vector Iops, we have LE-specific -+ * code in host_ppc_isel.c -+ * -+ * Another unique behavior of vectors in LE mode is with the vector scalar -+ * (VSX) operations that operate on "double word 0" of the source register, -+ * storing the result in "double word 0" of the output vector register. For -+ * these operations, "double word 0" is interpreted as "high half of the -+ * register" (i.e, the part on the left side). -+ * -+ */ - /* Translates PPC32/64 code to IR. */ - - /* References -@@ -137,7 +186,6 @@ - #include "guest_generic_bb_to_IR.h" - #include "guest_ppc_defs.h" - -- - /*------------------------------------------------------------*/ - /*--- Globals ---*/ - /*------------------------------------------------------------*/ -@@ -497,15 +545,22 @@ static ULong extend_s_32to64 ( UInt x ) - return (ULong)((((Long)x) << 32) >> 32); - } - --/* Do a big-endian load of a 32-bit word, regardless of the endianness -+/* Do a proper-endian load of a 32-bit word, regardless of the endianness - of the underlying host. */ --static UInt getUIntBigendianly ( UChar* p ) -+static UInt getUIntPPCendianly ( UChar* p ) - { - UInt w = 0; -- w = (w << 8) | p[0]; -- w = (w << 8) | p[1]; -- w = (w << 8) | p[2]; -- w = (w << 8) | p[3]; -+ if (host_endness == VexEndnessBE) { -+ w = (w << 8) | p[0]; -+ w = (w << 8) | p[1]; -+ w = (w << 8) | p[2]; -+ w = (w << 8) | p[3]; -+ } else { -+ w = (w << 8) | p[3]; -+ w = (w << 8) | p[2]; -+ w = (w << 8) | p[1]; -+ w = (w << 8) | p[0]; -+ } - return w; - } - -@@ -520,11 +575,15 @@ static void assign ( IRTemp dst, IRExpr* - } - - /* This generates a normal (non store-conditional) store. */ --static void storeBE ( IRExpr* addr, IRExpr* data ) -+static void store ( IRExpr* addr, IRExpr* data ) - { - IRType tyA = typeOfIRExpr(irsb->tyenv, addr); - vassert(tyA == Ity_I32 || tyA == Ity_I64); -- stmt( IRStmt_Store(Iend_BE, addr, data) ); -+ -+ if (host_endness == VexEndnessBE) -+ stmt( IRStmt_Store(Iend_BE, addr, data) ); -+ else -+ stmt( IRStmt_Store(Iend_LE, addr, data) ); - } - - static IRExpr* unop ( IROp op, IRExpr* a ) -@@ -580,9 +639,21 @@ static IRExpr* mkV128 ( UShort i ) - } - - /* This generates a normal (non load-linked) load. */ --static IRExpr* loadBE ( IRType ty, IRExpr* addr ) -+static IRExpr* load ( IRType ty, IRExpr* addr ) - { -- return IRExpr_Load(Iend_BE, ty, addr); -+ if (host_endness == VexEndnessBE) -+ return IRExpr_Load(Iend_BE, ty, addr); -+ else -+ return IRExpr_Load(Iend_LE, ty, addr); -+} -+ -+static IRStmt* stmt_load ( IRTemp result, -+ IRExpr* addr, IRExpr* storedata ) -+{ -+ if (host_endness == VexEndnessBE) -+ return IRStmt_LLSC(Iend_BE, result, addr, storedata); -+ else -+ return IRStmt_LLSC(Iend_LE, result, addr, storedata); - } - - static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 ) -@@ -1033,7 +1104,6 @@ static Int integerGuestRegOffset ( UInt - // jrs: probably not necessary; only matters if we reference sub-parts - // of the ppc registers, but that isn't the case - // later: this might affect Altivec though? -- vassert(host_endness == VexEndnessBE); - - switch (archreg) { - case 0: return offsetofPPCGuestState(guest_GPR0); -@@ -1095,40 +1165,78 @@ static Int floatGuestRegOffset ( UInt ar - { - vassert(archreg < 32); - -- switch (archreg) { -- case 0: return offsetofPPCGuestState(guest_VSR0); -- case 1: return offsetofPPCGuestState(guest_VSR1); -- case 2: return offsetofPPCGuestState(guest_VSR2); -- case 3: return offsetofPPCGuestState(guest_VSR3); -- case 4: return offsetofPPCGuestState(guest_VSR4); -- case 5: return offsetofPPCGuestState(guest_VSR5); -- case 6: return offsetofPPCGuestState(guest_VSR6); -- case 7: return offsetofPPCGuestState(guest_VSR7); -- case 8: return offsetofPPCGuestState(guest_VSR8); -- case 9: return offsetofPPCGuestState(guest_VSR9); -- case 10: return offsetofPPCGuestState(guest_VSR10); -- case 11: return offsetofPPCGuestState(guest_VSR11); -- case 12: return offsetofPPCGuestState(guest_VSR12); -- case 13: return offsetofPPCGuestState(guest_VSR13); -- case 14: return offsetofPPCGuestState(guest_VSR14); -- case 15: return offsetofPPCGuestState(guest_VSR15); -- case 16: return offsetofPPCGuestState(guest_VSR16); -- case 17: return offsetofPPCGuestState(guest_VSR17); -- case 18: return offsetofPPCGuestState(guest_VSR18); -- case 19: return offsetofPPCGuestState(guest_VSR19); -- case 20: return offsetofPPCGuestState(guest_VSR20); -- case 21: return offsetofPPCGuestState(guest_VSR21); -- case 22: return offsetofPPCGuestState(guest_VSR22); -- case 23: return offsetofPPCGuestState(guest_VSR23); -- case 24: return offsetofPPCGuestState(guest_VSR24); -- case 25: return offsetofPPCGuestState(guest_VSR25); -- case 26: return offsetofPPCGuestState(guest_VSR26); -- case 27: return offsetofPPCGuestState(guest_VSR27); -- case 28: return offsetofPPCGuestState(guest_VSR28); -- case 29: return offsetofPPCGuestState(guest_VSR29); -- case 30: return offsetofPPCGuestState(guest_VSR30); -- case 31: return offsetofPPCGuestState(guest_VSR31); -- default: break; -+ if (host_endness == VexEndnessLE) { -+ switch (archreg) { -+ case 0: return offsetofPPCGuestState(guest_VSR0 + 8); -+ case 1: return offsetofPPCGuestState(guest_VSR1 + 8); -+ case 2: return offsetofPPCGuestState(guest_VSR2 + 8); -+ case 3: return offsetofPPCGuestState(guest_VSR3 + 8); -+ case 4: return offsetofPPCGuestState(guest_VSR4 + 8); -+ case 5: return offsetofPPCGuestState(guest_VSR5 + 8); -+ case 6: return offsetofPPCGuestState(guest_VSR6 + 8); -+ case 7: return offsetofPPCGuestState(guest_VSR7 + 8); -+ case 8: return offsetofPPCGuestState(guest_VSR8 + 8); -+ case 9: return offsetofPPCGuestState(guest_VSR9 + 8); -+ case 10: return offsetofPPCGuestState(guest_VSR10 + 8); -+ case 11: return offsetofPPCGuestState(guest_VSR11 + 8); -+ case 12: return offsetofPPCGuestState(guest_VSR12 + 8); -+ case 13: return offsetofPPCGuestState(guest_VSR13 + 8); -+ case 14: return offsetofPPCGuestState(guest_VSR14 + 8); -+ case 15: return offsetofPPCGuestState(guest_VSR15 + 8); -+ case 16: return offsetofPPCGuestState(guest_VSR16 + 8); -+ case 17: return offsetofPPCGuestState(guest_VSR17 + 8); -+ case 18: return offsetofPPCGuestState(guest_VSR18 + 8); -+ case 19: return offsetofPPCGuestState(guest_VSR19 + 8); -+ case 20: return offsetofPPCGuestState(guest_VSR20 + 8); -+ case 21: return offsetofPPCGuestState(guest_VSR21 + 8); -+ case 22: return offsetofPPCGuestState(guest_VSR22 + 8); -+ case 23: return offsetofPPCGuestState(guest_VSR23 + 8); -+ case 24: return offsetofPPCGuestState(guest_VSR24 + 8); -+ case 25: return offsetofPPCGuestState(guest_VSR25 + 8); -+ case 26: return offsetofPPCGuestState(guest_VSR26 + 8); -+ case 27: return offsetofPPCGuestState(guest_VSR27 + 8); -+ case 28: return offsetofPPCGuestState(guest_VSR28 + 8); -+ case 29: return offsetofPPCGuestState(guest_VSR29 + 8); -+ case 30: return offsetofPPCGuestState(guest_VSR30 + 8); -+ case 31: return offsetofPPCGuestState(guest_VSR31 + 8); -+ default: break; -+ } -+ } else { -+ switch (archreg) { -+ case 0: return offsetofPPCGuestState(guest_VSR0); -+ case 1: return offsetofPPCGuestState(guest_VSR1); -+ case 2: return offsetofPPCGuestState(guest_VSR2); -+ case 3: return offsetofPPCGuestState(guest_VSR3); -+ case 4: return offsetofPPCGuestState(guest_VSR4); -+ case 5: return offsetofPPCGuestState(guest_VSR5); -+ case 6: return offsetofPPCGuestState(guest_VSR6); -+ case 7: return offsetofPPCGuestState(guest_VSR7); -+ case 8: return offsetofPPCGuestState(guest_VSR8); -+ case 9: return offsetofPPCGuestState(guest_VSR9); -+ case 10: return offsetofPPCGuestState(guest_VSR10); -+ case 11: return offsetofPPCGuestState(guest_VSR11); -+ case 12: return offsetofPPCGuestState(guest_VSR12); -+ case 13: return offsetofPPCGuestState(guest_VSR13); -+ case 14: return offsetofPPCGuestState(guest_VSR14); -+ case 15: return offsetofPPCGuestState(guest_VSR15); -+ case 16: return offsetofPPCGuestState(guest_VSR16); -+ case 17: return offsetofPPCGuestState(guest_VSR17); -+ case 18: return offsetofPPCGuestState(guest_VSR18); -+ case 19: return offsetofPPCGuestState(guest_VSR19); -+ case 20: return offsetofPPCGuestState(guest_VSR20); -+ case 21: return offsetofPPCGuestState(guest_VSR21); -+ case 22: return offsetofPPCGuestState(guest_VSR22); -+ case 23: return offsetofPPCGuestState(guest_VSR23); -+ case 24: return offsetofPPCGuestState(guest_VSR24); -+ case 25: return offsetofPPCGuestState(guest_VSR25); -+ case 26: return offsetofPPCGuestState(guest_VSR26); -+ case 27: return offsetofPPCGuestState(guest_VSR27); -+ case 28: return offsetofPPCGuestState(guest_VSR28); -+ case 29: return offsetofPPCGuestState(guest_VSR29); -+ case 30: return offsetofPPCGuestState(guest_VSR30); -+ case 31: return offsetofPPCGuestState(guest_VSR31); -+ default: break; -+ } - } - vpanic("floatGuestRegOffset(ppc)"); /*notreached*/ - } -@@ -4752,7 +4860,7 @@ static Bool dis_int_load ( UInt theInstr - switch (opc1) { - case 0x22: // lbz (Load B & Zero, PPC32 p433) - DIP("lbz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I8, mkexpr(EA)); -+ val = load(Ity_I8, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); - break; - -@@ -4762,14 +4870,14 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("lbzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I8, mkexpr(EA)); -+ val = load(Ity_I8, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x2A: // lha (Load HW Alg, PPC32 p445) - DIP("lha r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); - break; - -@@ -4779,14 +4887,14 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("lhau r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x28: // lhz (Load HW & Zero, PPC32 p450) - DIP("lhz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); - break; - -@@ -4796,14 +4904,14 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("lhzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x20: // lwz (Load W & Zero, PPC32 p460) - DIP("lwz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I32, mkexpr(EA)); -+ val = load(Ity_I32, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); - break; - -@@ -4813,7 +4921,7 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("lwzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); -- val = loadBE(Ity_I32, mkexpr(EA)); -+ val = load(Ity_I32, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); - putIReg( rA_addr, mkexpr(EA) ); - break; -@@ -4832,14 +4940,14 @@ static Bool dis_int_load ( UInt theInstr - vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n"); - return False; - } -- val = loadBE(Ity_I8, mkexpr(EA)); -+ val = load(Ity_I8, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x057: // lbzx (Load B & Zero, Indexed, PPC32 p436) - DIP("lbzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- val = loadBE(Ity_I8, mkexpr(EA)); -+ val = load(Ity_I8, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom8(ty, val, False) ); - break; - -@@ -4849,14 +4957,14 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("lhaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x157: // lhax (Load HW Alg, Indexed, PPC32 p448) - DIP("lhax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, True) ); - break; - -@@ -4866,14 +4974,14 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("lhzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x117: // lhzx (Load HW & Zero, Indexed, PPC32 p453) - DIP("lhzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- val = loadBE(Ity_I16, mkexpr(EA)); -+ val = load(Ity_I16, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom16(ty, val, False) ); - break; - -@@ -4883,14 +4991,14 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("lwzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- val = loadBE(Ity_I32, mkexpr(EA)); -+ val = load(Ity_I32, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x017: // lwzx (Load W & Zero, Indexed, PPC32 p463) - DIP("lwzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- val = loadBE(Ity_I32, mkexpr(EA)); -+ val = load(Ity_I32, mkexpr(EA)); - putIReg( rD_addr, mkWidenFrom32(ty, val, False) ); - break; - -@@ -4902,13 +5010,13 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("ldux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); -+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x015: // ldx (Load DWord, Indexed, PPC64 p476) - DIP("ldx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); -+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); - break; - - case 0x175: // lwaux (Load W Alg, Update Indexed, PPC64 p501) -@@ -4918,14 +5026,14 @@ static Bool dis_int_load ( UInt theInstr - } - DIP("lwaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); - putIReg( rD_addr, -- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) ); -+ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x155: // lwax (Load W Alg, Indexed, PPC64 p502) - DIP("lwax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); - putIReg( rD_addr, -- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) ); -+ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) ); - break; - - default: -@@ -4940,7 +5048,7 @@ static Bool dis_int_load ( UInt theInstr - switch ((b1<<1) | b0) { - case 0x0: // ld (Load DWord, PPC64 p472) - DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); -- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); -+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); - break; - - case 0x1: // ldu (Load DWord, Update, PPC64 p474) -@@ -4949,14 +5057,14 @@ static Bool dis_int_load ( UInt theInstr - return False; - } - DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); -- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); -+ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x2: // lwa (Load Word Alg, PPC64 p499) - DIP("lwa r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); - putIReg( rD_addr, -- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) ); -+ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) ); - break; - - default: -@@ -4975,17 +5083,17 @@ static Bool dis_int_load ( UInt theInstr - */ - // trap if EA misaligned on 16 byte address - if (mode64) { -- assign(high, loadBE(ty, mkexpr( EA ) ) ); -- assign(low, loadBE(ty, binop( Iop_Add64, -- mkexpr( EA ), -- mkU64( 8 ) ) ) ); -+ assign(high, load(ty, mkexpr( EA ) ) ); -+ assign(low, load(ty, binop( Iop_Add64, -+ mkexpr( EA ), -+ mkU64( 8 ) ) ) ); - } else { -- assign(high, loadBE(ty, binop( Iop_Add32, -- mkexpr( EA ), -- mkU32( 4 ) ) ) ); -- assign(low, loadBE(ty, binop( Iop_Add32, -- mkexpr( EA ), -- mkU32( 12 ) ) ) ); -+ assign(high, load(ty, binop( Iop_Add32, -+ mkexpr( EA ), -+ mkU32( 4 ) ) ) ); -+ assign(low, load(ty, binop( Iop_Add32, -+ mkexpr( EA ), -+ mkU32( 12 ) ) ) ); - } - gen_SIGBUS_if_misaligned( EA, 16 ); - putIReg( rD_addr, mkexpr( high) ); -@@ -5040,7 +5148,7 @@ static Bool dis_int_store ( UInt theInst - switch (opc1) { - case 0x26: // stb (Store B, PPC32 p509) - DIP("stb r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); -- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); - break; - - case 0x27: // stbu (Store B, Update, PPC32 p510) -@@ -5050,12 +5158,12 @@ static Bool dis_int_store ( UInt theInst - } - DIP("stbu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); - break; - - case 0x2C: // sth (Store HW, PPC32 p522) - DIP("sth r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); -- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); - break; - - case 0x2D: // sthu (Store HW, Update, PPC32 p524) -@@ -5065,12 +5173,12 @@ static Bool dis_int_store ( UInt theInst - } - DIP("sthu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); - break; - - case 0x24: // stw (Store W, PPC32 p530) - DIP("stw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); -- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); - break; - - case 0x25: // stwu (Store W, Update, PPC32 p534) -@@ -5080,7 +5188,7 @@ static Bool dis_int_store ( UInt theInst - } - DIP("stwu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); - break; - - /* X Form : all these use EA_indexed */ -@@ -5098,12 +5206,12 @@ static Bool dis_int_store ( UInt theInst - } - DIP("stbux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); - break; - - case 0x0D7: // stbx (Store B Indexed, PPC32 p512) - DIP("stbx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); -- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) ); - break; - - case 0x1B7: // sthux (Store HW, Update Indexed, PPC32 p525) -@@ -5113,12 +5221,12 @@ static Bool dis_int_store ( UInt theInst - } - DIP("sthux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); - break; - - case 0x197: // sthx (Store HW Indexed, PPC32 p526) - DIP("sthx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); -- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) ); - break; - - case 0x0B7: // stwux (Store W, Update Indexed, PPC32 p535) -@@ -5128,12 +5236,12 @@ static Bool dis_int_store ( UInt theInst - } - DIP("stwux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); - break; - - case 0x097: // stwx (Store W Indexed, PPC32 p536) - DIP("stwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); -- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); -+ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) ); - break; - - -@@ -5145,12 +5253,12 @@ static Bool dis_int_store ( UInt theInst - } - DIP("stdux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkexpr(rS) ); -+ store( mkexpr(EA), mkexpr(rS) ); - break; - - case 0x095: // stdx (Store DWord Indexed, PPC64 p585) - DIP("stdx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); -- storeBE( mkexpr(EA), mkexpr(rS) ); -+ store( mkexpr(EA), mkexpr(rS) ); - break; - - default: -@@ -5168,7 +5276,7 @@ static Bool dis_int_store ( UInt theInst - return False; - - DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); -- storeBE( mkexpr(EA), mkexpr(rS) ); -+ store( mkexpr(EA), mkexpr(rS) ); - break; - - case 0x1: // stdu (Store DWord, Update, PPC64 p583) -@@ -5177,7 +5285,7 @@ static Bool dis_int_store ( UInt theInst - - DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); - putIReg( rA_addr, mkexpr(EA) ); -- storeBE( mkexpr(EA), mkexpr(rS) ); -+ store( mkexpr(EA), mkexpr(rS) ); - break; - - case 0x2: { // stq (Store QuadWord, Update, PPC64 p583) -@@ -5199,9 +5307,9 @@ static Bool dis_int_store ( UInt theInst - assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+12 ) ); - } - putIReg( rA_addr, mkexpr(EA_hi) ); -- storeBE( mkexpr(EA_hi), mkexpr(rS) ); -+ store( mkexpr(EA_hi), mkexpr(rS) ); - putIReg( rA_addr, mkexpr( EA_lo) ); -- storeBE( mkexpr(EA_lo), getIReg( rS_addr+1 ) ); -+ store( mkexpr(EA_lo), getIReg( rS_addr+1 ) ); - break; - } - default: -@@ -5250,7 +5358,7 @@ static Bool dis_int_ldst_mult ( UInt the - DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); - for (r = rD_addr; r <= 31; r++) { - irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); -- putIReg( r, mkWidenFrom32(ty, loadBE(Ity_I32, irx_addr ), -+ putIReg( r, mkWidenFrom32(ty, load(Ity_I32, irx_addr ), - False) ); - ea_off += 4; - } -@@ -5260,7 +5368,7 @@ static Bool dis_int_ldst_mult ( UInt the - DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); - for (r = rS_addr; r <= 31; r++) { - irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); -- storeBE( irx_addr, mkNarrowTo32(ty, getIReg(r)) ); -+ store( irx_addr, mkNarrowTo32(ty, getIReg(r)) ); - ea_off += 4; - } - break; -@@ -5315,8 +5423,9 @@ void generate_lsw_sequence ( IRTemp tNBy - Iop_Shl32, - unop( - Iop_8Uto32, -- loadBE(Ity_I8, -- binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i))) -+ load( Ity_I8, -+ binop( mkSzOp(ty,Iop_Add8), -+ e_EA, mkSzImm(ty,i))) - ), - mkU8(toUChar(shift)) - ) -@@ -5354,12 +5463,12 @@ void generate_stsw_sequence ( IRTemp tNB - } - /* *(EA+i) = 32to8(rS >> shift) */ - vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24); -- storeBE( -- binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)), -- unop(Iop_32to8, -- binop(Iop_Shr32, -- mkNarrowTo32(ty, getIReg(rS)), -- mkU8(toUChar(shift)))) -+ store( -+ binop( mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)), -+ unop( Iop_32to8, -+ binop( Iop_Shr32, -+ mkNarrowTo32( ty, getIReg(rS) ), -+ mkU8( toUChar(shift) ))) - ); - shift -= 8; - } -@@ -5398,10 +5507,10 @@ static Bool dis_int_ldst_str ( UInt theI - /* Special case hack */ - /* rD = Mem[EA]; (rD+1)%32 = Mem[EA+4] */ - putIReg( rD_addr, -- loadBE(Ity_I32, mkexpr(t_EA)) ); -+ load(Ity_I32, mkexpr(t_EA)) ); - putIReg( (rD_addr+1) % 32, -- loadBE(Ity_I32, -- binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) ); -+ load(Ity_I32, -+ binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) ); - } else { - t_nbytes = newTemp(Ity_I32); - assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) ); -@@ -5433,10 +5542,10 @@ static Bool dis_int_ldst_str ( UInt theI - if (NumBytes == 8 && !mode64) { - /* Special case hack */ - /* Mem[EA] = rD; Mem[EA+4] = (rD+1)%32 */ -- storeBE( mkexpr(t_EA), -- getIReg(rD_addr) ); -- storeBE( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)), -- getIReg((rD_addr+1) % 32) ); -+ store( mkexpr(t_EA), -+ getIReg(rD_addr) ); -+ store( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)), -+ getIReg((rD_addr+1) % 32) ); - } else { - t_nbytes = newTemp(Ity_I32); - assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) ); -@@ -6137,7 +6246,7 @@ static Bool dis_memsync ( UInt theInstr - - // and actually do the load - res = newTemp(Ity_I32); -- stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) ); -+ stmt( stmt_load(res, mkexpr(EA), NULL/*this is a load*/) ); - - putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(res), False) ); - break; -@@ -6163,7 +6272,7 @@ static Bool dis_memsync ( UInt theInstr - - // Do the store, and get success/failure bit into resSC - resSC = newTemp(Ity_I1); -- stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) ); -+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) ); - - // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure - // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success -@@ -6230,7 +6339,7 @@ static Bool dis_memsync ( UInt theInstr - - // and actually do the load - res = newTemp(Ity_I64); -- stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) ); -+ stmt( stmt_load( res, mkexpr(EA), NULL/*this is a load*/) ); - - putIReg( rD_addr, mkexpr(res) ); - break; -@@ -6256,7 +6365,7 @@ static Bool dis_memsync ( UInt theInstr - - // Do the store, and get success/failure bit into resSC - resSC = newTemp(Ity_I1); -- stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) ); -+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) ); - - // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure - // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success -@@ -6286,18 +6395,18 @@ static Bool dis_memsync ( UInt theInstr - - // and actually do the load - if (mode64) { -- stmt( IRStmt_LLSC( Iend_BE, res_hi, -- mkexpr(EA), NULL/*this is a load*/) ); -- stmt( IRStmt_LLSC( Iend_BE, res_lo, -- binop(Iop_Add64, mkexpr(EA), mkU64(8) ), -- NULL/*this is a load*/) ); -+ stmt( stmt_load( res_hi, -+ mkexpr(EA), NULL/*this is a load*/) ); -+ stmt( stmt_load( res_lo, -+ binop(Iop_Add64, mkexpr(EA), mkU64(8) ), -+ NULL/*this is a load*/) ); - } else { -- stmt( IRStmt_LLSC( Iend_BE, res_hi, -- binop( Iop_Add32, mkexpr(EA), mkU32(4) ), -- NULL/*this is a load*/) ); -- stmt( IRStmt_LLSC( Iend_BE, res_lo, -- binop( Iop_Add32, mkexpr(EA), mkU32(12) ), -- NULL/*this is a load*/) ); -+ stmt( stmt_load( res_hi, -+ binop( Iop_Add32, mkexpr(EA), mkU32(4) ), -+ NULL/*this is a load*/) ); -+ stmt( stmt_load( res_lo, -+ binop( Iop_Add32, mkexpr(EA), mkU32(12) ), -+ NULL/*this is a load*/) ); - } - putIReg( rD_addr, mkexpr(res_hi) ); - putIReg( rD_addr+1, mkexpr(res_lo) ); -@@ -6326,14 +6435,14 @@ static Bool dis_memsync ( UInt theInstr - resSC = newTemp(Ity_I1); - - if (mode64) { -- stmt( IRStmt_LLSC( Iend_BE, resSC, mkexpr(EA), mkexpr(rS_hi) ) ); -- storeBE(binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) ); -+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS_hi) ) ); -+ store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) ); - } else { -- stmt( IRStmt_LLSC( Iend_BE, resSC, binop( Iop_Add32, -- mkexpr(EA), -- mkU32(4) ), -- mkexpr(rS_hi) ) ); -- storeBE(binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) ); -+ stmt( stmt_load( resSC, binop( Iop_Add32, -+ mkexpr(EA), -+ mkU32(4) ), -+ mkexpr(rS_hi) ) ); -+ store( binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) ); - } - - // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure -@@ -6656,7 +6765,7 @@ static Bool dis_int_ldst_rev ( UInt theI - - case 0x316: // lhbrx (Load Halfword Byte-Reverse Indexed, PPC32 p449) - DIP("lhbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- assign( w1, unop(Iop_16Uto32, loadBE(Ity_I16, mkexpr(EA))) ); -+ assign( w1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(EA))) ); - assign( w2, gen_byterev16(w1) ); - putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2), - /* Signed */False) ); -@@ -6664,7 +6773,7 @@ static Bool dis_int_ldst_rev ( UInt theI - - case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459) - DIP("lwbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- assign( w1, loadBE(Ity_I32, mkexpr(EA)) ); -+ assign( w1, load(Ity_I32, mkexpr(EA)) ); - assign( w2, gen_byterev32(w1) ); - putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2), - /* Signed */False) ); -@@ -6676,26 +6785,29 @@ static Bool dis_int_ldst_rev ( UInt theI - IRTemp w3 = newTemp( Ity_I32 ); - IRTemp w4 = newTemp( Ity_I32 ); - DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); -- assign( w1, loadBE( Ity_I32, mkexpr( EA ) ) ); -+ assign( w1, load( Ity_I32, mkexpr( EA ) ) ); - assign( w2, gen_byterev32( w1 ) ); - nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) ); -- assign( w3, loadBE( Ity_I32, nextAddr ) ); -+ assign( w3, load( Ity_I32, nextAddr ) ); - assign( w4, gen_byterev32( w3 ) ); -- putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) ); -+ if (host_endness == VexEndnessLE) -+ putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) ); -+ else -+ putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) ); - break; - } - - case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC32 p523) - DIP("sthbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); - assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) ); -- storeBE( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) ); -+ store( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) ); - break; - - case 0x296: // stwbrx (Store Word Byte-Reverse Indxd, PPC32 p531) - DIP("stwbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); - assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) ); -- storeBE( mkexpr(EA), gen_byterev32(w1) ); -+ store( mkexpr(EA), gen_byterev32(w1) ); - break; - - case 0x294: // stdbrx (Store Doubleword Byte-Reverse Indexed) -@@ -6707,8 +6819,9 @@ static Bool dis_int_ldst_rev ( UInt theI - DIP("stdbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); - assign(lo, unop(Iop_64HIto32, mkexpr(rS))); - assign(hi, unop(Iop_64to32, mkexpr(rS))); -- storeBE( mkexpr( EA ), -- binop( Iop_32HLto64, gen_byterev32( hi ), gen_byterev32( lo ) ) ); -+ store( mkexpr( EA ), -+ binop( Iop_32HLto64, gen_byterev32( hi ), -+ gen_byterev32( lo ) ) ); - break; - } - -@@ -7226,7 +7339,7 @@ static Bool dis_cache_manage ( UInt - - for (i = 0; i < clearszB / 8; i++) { - irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) ); -- storeBE( irx_addr, mkU64(0) ); -+ store( irx_addr, mkU64(0) ); - } - } else { - /* Round EA down to the start of the containing block. */ -@@ -7236,7 +7349,7 @@ static Bool dis_cache_manage ( UInt - - for (i = 0; i < clearszB / 4; i++) { - irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) ); -- storeBE( irx_addr, mkU32(0) ); -+ store( irx_addr, mkU32(0) ); - } - } - break; -@@ -7456,7 +7569,7 @@ static Bool dis_fp_load ( UInt theInstr - DIP("lfs fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); - assign( EA, ea_rAor0_simm(rA_addr, simm16) ); - putFReg( frD_addr, -- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) ); -+ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) ); - break; - - case 0x31: // lfsu (Load Float Single, Update, PPC32 p442) -@@ -7465,14 +7578,14 @@ static Bool dis_fp_load ( UInt theInstr - DIP("lfsu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); - assign( EA, ea_rA_simm(rA_addr, simm16) ); - putFReg( frD_addr, -- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) ); -+ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x32: // lfd (Load Float Double, PPC32 p437) - DIP("lfd fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); - assign( EA, ea_rAor0_simm(rA_addr, simm16) ); -- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); -+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); - break; - - case 0x33: // lfdu (Load Float Double, Update, PPC32 p438) -@@ -7480,7 +7593,7 @@ static Bool dis_fp_load ( UInt theInstr - return False; - DIP("lfdu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); - assign( EA, ea_rA_simm(rA_addr, simm16) ); -- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); -+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - -@@ -7495,7 +7608,7 @@ static Bool dis_fp_load ( UInt theInstr - DIP("lfsx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); - assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); - putFReg( frD_addr, unop( Iop_F32toF64, -- loadBE(Ity_F32, mkexpr(EA))) ); -+ load(Ity_F32, mkexpr(EA))) ); - break; - - case 0x237: // lfsux (Load Float Single, Update Indxd, PPC32 p443) -@@ -7504,14 +7617,14 @@ static Bool dis_fp_load ( UInt theInstr - DIP("lfsux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); - assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); - putFReg( frD_addr, -- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) ); -+ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x257: // lfdx (Load Float Double Indexed, PPC32 p440) - DIP("lfdx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); - assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); -- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); -+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); - break; - - case 0x277: // lfdux (Load Float Double, Update Indxd, PPC32 p439) -@@ -7519,14 +7632,14 @@ static Bool dis_fp_load ( UInt theInstr - return False; - DIP("lfdux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); - assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); -- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); -+ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x357: // lfiwax (Load Float As Integer, Indxd, ISA 2.05 p120) - DIP("lfiwax fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); - assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); -- assign( iLo, loadBE(Ity_I32, mkexpr(EA)) ); -+ assign( iLo, load(Ity_I32, mkexpr(EA)) ); - assign( iHi, binop(Iop_Sub32, - mkU32(0), - binop(Iop_Shr32, mkexpr(iLo), mkU8(31))) ); -@@ -7539,7 +7652,7 @@ static Bool dis_fp_load ( UInt theInstr - IRTemp dw = newTemp( Ity_I64 ); - DIP("lfiwzx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); - assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); -- assign( iLo, loadBE(Ity_I32, mkexpr(EA)) ); -+ assign( iLo, load(Ity_I32, mkexpr(EA)) ); - assign( dw, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( iLo ) ) ); - putFReg( frD_addr, unop( Iop_ReinterpI64asF64, mkexpr( dw ) ) ); - break; -@@ -7598,8 +7711,7 @@ static Bool dis_fp_store ( UInt theInstr - /* Use Iop_TruncF64asF32 to truncate and possible denormalise - the value to be stored in the correct way, without any - rounding. */ -- storeBE( mkexpr(EA), -- unop(Iop_TruncF64asF32, mkexpr(frS)) ); -+ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) ); - break; - - case 0x35: // stfsu (Store Float Single, Update, PPC32 p519) -@@ -7608,15 +7720,14 @@ static Bool dis_fp_store ( UInt theInstr - DIP("stfsu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); - assign( EA, ea_rA_simm(rA_addr, simm16) ); - /* See comment for stfs */ -- storeBE( mkexpr(EA), -- unop(Iop_TruncF64asF32, mkexpr(frS)) ); -+ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x36: // stfd (Store Float Double, PPC32 p513) - DIP("stfd fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); - assign( EA, ea_rAor0_simm(rA_addr, simm16) ); -- storeBE( mkexpr(EA), mkexpr(frS) ); -+ store( mkexpr(EA), mkexpr(frS) ); - break; - - case 0x37: // stfdu (Store Float Double, Update, PPC32 p514) -@@ -7624,7 +7735,7 @@ static Bool dis_fp_store ( UInt theInstr - return False; - DIP("stfdu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); - assign( EA, ea_rA_simm(rA_addr, simm16) ); -- storeBE( mkexpr(EA), mkexpr(frS) ); -+ store( mkexpr(EA), mkexpr(frS) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - -@@ -7638,8 +7749,8 @@ static Bool dis_fp_store ( UInt theInstr - DIP("stfsx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); - assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); - /* See note for stfs */ -- storeBE( mkexpr(EA), -- unop(Iop_TruncF64asF32, mkexpr(frS)) ); -+ store( mkexpr(EA), -+ unop(Iop_TruncF64asF32, mkexpr(frS)) ); - break; - - case 0x2B7: // stfsux (Store Float Sgl, Update Indxd, PPC32 p520) -@@ -7648,15 +7759,14 @@ static Bool dis_fp_store ( UInt theInstr - DIP("stfsux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); - assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); - /* See note for stfs */ -- storeBE( mkexpr(EA), -- unop(Iop_TruncF64asF32, mkexpr(frS)) ); -+ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - - case 0x2D7: // stfdx (Store Float Double Indexed, PPC32 p516) - DIP("stfdx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); - assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); -- storeBE( mkexpr(EA), mkexpr(frS) ); -+ store( mkexpr(EA), mkexpr(frS) ); - break; - - case 0x2F7: // stfdux (Store Float Dbl, Update Indxd, PPC32 p515) -@@ -7664,7 +7774,7 @@ static Bool dis_fp_store ( UInt theInstr - return False; - DIP("stfdux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); - assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); -- storeBE( mkexpr(EA), mkexpr(frS) ); -+ store( mkexpr(EA), mkexpr(frS) ); - putIReg( rA_addr, mkexpr(EA) ); - break; - -@@ -7672,8 +7782,8 @@ static Bool dis_fp_store ( UInt theInstr - // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) - DIP("stfiwx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); - assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); -- storeBE( mkexpr(EA), -- unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) ); -+ store( mkexpr(EA), -+ unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) ); - break; - - default: -@@ -8859,11 +8969,11 @@ static Bool dis_fp_pair ( UInt theInstr - assign( frT_lo, getFReg(frT_lo_addr) ); - - if (is_load) { -- putFReg( frT_hi_addr, loadBE(Ity_F64, mkexpr(EA_hi)) ); -- putFReg( frT_lo_addr, loadBE(Ity_F64, mkexpr(EA_lo)) ); -+ putFReg( frT_hi_addr, load(Ity_F64, mkexpr(EA_hi)) ); -+ putFReg( frT_lo_addr, load(Ity_F64, mkexpr(EA_lo)) ); - } else { -- storeBE( mkexpr(EA_hi), mkexpr(frT_hi) ); -- storeBE( mkexpr(EA_lo), mkexpr(frT_lo) ); -+ store( mkexpr(EA_hi), mkexpr(frT_hi) ); -+ store( mkexpr(EA_lo), mkexpr(frT_lo) ); - } - - return True; -@@ -14755,6 +14865,7 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 ) - static Bool - dis_vxs_misc( UInt theInstr, UInt opc2 ) - { -+#define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL - /* XX3-Form and XX2-Form */ - UChar opc1 = ifieldOPC( theInstr ); - UChar XT = ifieldRegXT ( theInstr ); -@@ -14781,7 +14892,20 @@ dis_vxs_misc( UInt theInstr, UInt opc2 ) - { - /* Move abs val of dw 0 of VSX[XB] to dw 0 of VSX[XT]. */ - IRTemp absVal = newTemp(Ity_V128); -- assign(absVal, binop(Iop_ShrV128, binop(Iop_ShlV128, mkexpr(vB), mkU8(1)), mkU8(1))); -+ if (host_endness == VexEndnessLE) { -+ IRTemp hi64 = newTemp(Ity_I64); -+ IRTemp lo64 = newTemp(Ity_I64); -+ assign( hi64, unop( Iop_V128HIto64, mkexpr(vB) ) ); -+ assign( lo64, unop( Iop_V128to64, mkexpr(vB) ) ); -+ assign( absVal, binop( Iop_64HLtoV128, -+ binop( Iop_And64, mkexpr(hi64), -+ mkU64(VG_PPC_SIGN_MASK) ), -+ mkexpr(lo64) ) ); -+ } else { -+ assign(absVal, binop(Iop_ShrV128, -+ binop(Iop_ShlV128, mkexpr(vB), -+ mkU8(1)), mkU8(1))); -+ } - DIP("xsabsdp v%d,v%d\n", (UInt)XT, (UInt)XB); - putVSReg(XT, mkexpr(absVal)); - break; -@@ -14789,51 +14913,73 @@ dis_vxs_misc( UInt theInstr, UInt opc2 ) - case 0x2C0: // xscpsgndp - { - /* Scalar copy sign double-precision */ -- IRTemp vecA_signbit = newTemp(Ity_V128); -- IRTemp vecB_no_signbit = newTemp(Ity_V128); -+ IRTemp vecA_signed = newTemp(Ity_I64); -+ IRTemp vecB_unsigned = newTemp(Ity_I64); - IRTemp vec_result = newTemp(Ity_V128); - DIP("xscpsgndp v%d,v%d v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); -- assign( vecB_no_signbit, binop( Iop_ShrV128, binop( Iop_ShlV128, -- mkexpr( vB ), -- mkU8( 1 ) ), -- mkU8( 1 ) ) ); -- assign( vecA_signbit, binop( Iop_ShlV128, binop( Iop_ShrV128, -- mkexpr( vA ), -- mkU8( 127 ) ), -- mkU8( 127 ) ) ); -- assign( vec_result, binop( Iop_OrV128, mkexpr(vecA_signbit), mkexpr( vecB_no_signbit ) ) ); -+ assign( vecA_signed, binop( Iop_And64, -+ unop( Iop_V128HIto64, -+ mkexpr(vA)), -+ mkU64(~VG_PPC_SIGN_MASK) ) ); -+ assign( vecB_unsigned, binop( Iop_And64, -+ unop( Iop_V128HIto64, -+ mkexpr(vB) ), -+ mkU64(VG_PPC_SIGN_MASK) ) ); -+ assign( vec_result, binop( Iop_64HLtoV128, -+ binop( Iop_Or64, -+ mkexpr(vecA_signed), -+ mkexpr(vecB_unsigned) ), -+ mkU64(0x0ULL))); - putVSReg(XT, mkexpr(vec_result)); - break; - } - case 0x2D2: // xsnabsdp - { - /* Scalar negative absolute value double-precision */ -- IRTemp vec_neg_signbit = newTemp(Ity_V128); -+ IRTemp BHi_signed = newTemp(Ity_I64); - DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB); -- assign( vec_neg_signbit, unop( Iop_NotV128, binop( Iop_ShrV128, -- mkV128( 0xffff ), -- mkU8( 1 ) ) ) ); -- putVSReg(XT, binop(Iop_OrV128, mkexpr(vec_neg_signbit), mkexpr(vB))); -+ assign( BHi_signed, binop( Iop_Or64, -+ unop( Iop_V128HIto64, -+ mkexpr(vB) ), -+ mkU64(~VG_PPC_SIGN_MASK) ) ); -+ putVSReg(XT, binop( Iop_64HLtoV128, -+ mkexpr(BHi_signed), mkU64(0x0ULL) ) ); - break; - } - case 0x2F2: // xsnegdp - { - /* Scalar negate double-precision */ -- IRTemp vecB_no_signbit = newTemp(Ity_V128); -- IRTemp vecB_signbit_comp = newTemp(Ity_V128); -+ IRTemp BHi_signed = newTemp(Ity_I64); -+ IRTemp BHi_unsigned = newTemp(Ity_I64); -+ IRTemp BHi_negated = newTemp(Ity_I64); -+ IRTemp BHi_negated_signbit = newTemp(Ity_I1); -+ IRTemp vec_result = newTemp(Ity_V128); - DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB); -- assign( vecB_no_signbit, binop( Iop_ShrV128, binop( Iop_ShlV128, -- mkexpr( vB ), -- mkU8( 1 ) ), -- mkU8( 1 ) ) ); -- assign( vecB_signbit_comp, binop( Iop_ShlV128, -- unop( Iop_NotV128, -- binop( Iop_ShrV128, -- mkexpr( vB ), -- mkU8( 127 ) ) ), -- mkU8( 127 ) ) ); -- putVSReg( XT, binop( Iop_OrV128, mkexpr( vecB_no_signbit ), -- mkexpr( vecB_signbit_comp ) ) ); -+ assign( BHi_signed, unop( Iop_V128HIto64, mkexpr(vB) ) ); -+ assign( BHi_unsigned, binop( Iop_And64, mkexpr(BHi_signed), -+ mkU64(VG_PPC_SIGN_MASK) ) ); -+ assign( BHi_negated_signbit, -+ unop( Iop_Not1, -+ unop( Iop_32to1, -+ binop( Iop_Shr32, -+ unop( Iop_64HIto32, -+ binop( Iop_And64, -+ mkexpr(BHi_signed), -+ mkU64(~VG_PPC_SIGN_MASK) ) -+ ), -+ mkU8(31) ) ) ) ); -+ assign( BHi_negated, -+ binop( Iop_Or64, -+ binop( Iop_32HLto64, -+ binop( Iop_Shl32, -+ unop( Iop_1Uto32, -+ mkexpr(BHi_negated_signbit) ), -+ mkU8(31) ), -+ mkU32(0) ), -+ mkexpr(BHi_unsigned) ) ); -+ assign( vec_result, binop( Iop_64HLtoV128, mkexpr(BHi_negated), -+ mkU64(0x0ULL))); -+ putVSReg( XT, mkexpr(vec_result)); - break; - } - case 0x280: // xsmaxdp (VSX Scalar Maximum Double-Precision) -@@ -15058,7 +15204,7 @@ dis_vx_load ( UInt theInstr ) - { - IRExpr * exp; - DIP("lxsiwzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); -- exp = unop( Iop_64HIto32, loadBE( Ity_I64, mkexpr( EA ) ) ); -+ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) ); - putVSReg( XT, binop( Iop_64HLtoV128, - unop( Iop_32Uto64, exp), - mkU64(0) ) ); -@@ -15068,7 +15214,7 @@ dis_vx_load ( UInt theInstr ) - { - IRExpr * exp; - DIP("lxsiwax %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); -- exp = unop( Iop_64HIto32, loadBE( Ity_I64, mkexpr( EA ) ) ); -+ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) ); - putVSReg( XT, binop( Iop_64HLtoV128, - unop( Iop_32Sto64, exp), - mkU64(0) ) ); -@@ -15085,8 +15231,7 @@ dis_vx_load ( UInt theInstr ) - exp = unop( Iop_ReinterpF64asI64, - unop( Iop_F32toF64, - unop( Iop_ReinterpI32asF32, -- unop( Iop_64HIto32, -- loadBE( Ity_I64, mkexpr( EA ) ) ) ) ) ); -+ load( Ity_I32, mkexpr( EA ) ) ) ) ); - - putVSReg( XT, binop( Iop_64HLtoV128, exp, mkU64( 0 ) ) ); - break; -@@ -15095,7 +15240,7 @@ dis_vx_load ( UInt theInstr ) - { - IRExpr * exp; - DIP("lxsdx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); -- exp = loadBE( Ity_I64, mkexpr( EA ) ); -+ exp = load( Ity_I64, mkexpr( EA ) ); - // We need to pass an expression of type Ity_V128 with putVSReg, but the load - // we just performed is only a DW. But since the contents of VSR[XT] element 1 - // are undefined after this operation, we can just do a splat op. -@@ -15109,10 +15254,10 @@ dis_vx_load ( UInt theInstr ) - ULong ea_off = 8; - IRExpr* high_addr; - DIP("lxvd2x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); -- high = loadBE( Ity_I64, mkexpr( EA ) ); -+ high = load( Ity_I64, mkexpr( EA ) ); - high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off ) - : mkU32( ea_off ) ); -- low = loadBE( Ity_I64, high_addr ); -+ low = load( Ity_I64, high_addr ); - putVSReg( XT, binop( Iop_64HLtoV128, high, low ) ); - break; - } -@@ -15120,7 +15265,7 @@ dis_vx_load ( UInt theInstr ) - { - IRTemp data = newTemp(Ity_I64); - DIP("lxvdsx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); -- assign( data, loadBE( Ity_I64, mkexpr( EA ) ) ); -+ assign( data, load( Ity_I64, mkexpr( EA ) ) ); - putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( data ), mkexpr( data ) ) ); - break; - } -@@ -15131,19 +15276,19 @@ dis_vx_load ( UInt theInstr ) - IRExpr* irx_addr; - - DIP("lxvw4x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); -- t3 = loadBE( Ity_I32, mkexpr( EA ) ); -+ t3 = load( Ity_I32, mkexpr( EA ) ); - ea_off += 4; - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); -- t2 = loadBE( Ity_I32, irx_addr ); -+ t2 = load( Ity_I32, irx_addr ); - ea_off += 4; - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); -- t1 = loadBE( Ity_I32, irx_addr ); -+ t1 = load( Ity_I32, irx_addr ); - ea_off += 4; - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); -- t0 = loadBE( Ity_I32, irx_addr ); -+ t0 = load( Ity_I32, irx_addr ); - putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, t3, t2 ), - binop( Iop_32HLto64, t1, t0 ) ) ); - break; -@@ -15191,7 +15336,7 @@ dis_vx_store ( UInt theInstr ) - DIP("stxsiwx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); - high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); - low32 = unop( Iop_64to32, high64 ); -- storeBE( mkexpr( EA ), low32 ); -+ store( mkexpr( EA ), low32 ); - break; - } - case 0x28C: -@@ -15204,7 +15349,7 @@ dis_vx_store ( UInt theInstr ) - assign(val32, unop( Iop_ReinterpF32asI32, - unop( Iop_TruncF64asF32, - mkexpr(high64) ) ) ); -- storeBE( mkexpr( EA ), mkexpr( val32 ) ); -+ store( mkexpr( EA ), mkexpr( val32 ) ); - break; - } - case 0x2CC: -@@ -15212,7 +15357,7 @@ dis_vx_store ( UInt theInstr ) - IRExpr * high64; - DIP("stxsdx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); - high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); -- storeBE( mkexpr( EA ), high64 ); -+ store( mkexpr( EA ), high64 ); - break; - } - case 0x3CC: -@@ -15221,9 +15366,9 @@ dis_vx_store ( UInt theInstr ) - DIP("stxvd2x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); - high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); - low64 = unop( Iop_V128to64, mkexpr( vS ) ); -- storeBE( mkexpr( EA ), high64 ); -- storeBE( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), ty == Ity_I64 ? mkU64( 8 ) -- : mkU32( 8 ) ), low64 ); -+ store( mkexpr( EA ), high64 ); -+ store( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), -+ ty == Ity_I64 ? mkU64( 8 ) : mkU32( 8 ) ), low64 ); - break; - } - case 0x38C: -@@ -15239,20 +15384,19 @@ dis_vx_store ( UInt theInstr ) - // quad-word aligned. Therefore, do 4 individual word-size stores. - assign( hi64, unop( Iop_V128HIto64, mkexpr( vS ) ) ); - assign( lo64, unop( Iop_V128to64, mkexpr( vS ) ) ); -- -- storeBE( mkexpr( EA ), unop( Iop_64HIto32, mkexpr( hi64 ) ) ); -+ store( mkexpr( EA ), unop( Iop_64HIto32, mkexpr( hi64 ) ) ); - ea_off += 4; - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); -- storeBE( irx_addr, unop( Iop_64to32, mkexpr( hi64 ) ) ); -+ store( irx_addr, unop( Iop_64to32, mkexpr( hi64 ) ) ); - ea_off += 4; - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); -- storeBE( irx_addr, unop( Iop_64HIto32, mkexpr( lo64 ) ) ); -+ store( irx_addr, unop( Iop_64HIto32, mkexpr( lo64 ) ) ); - ea_off += 4; - irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), - ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) ); -- storeBE( irx_addr, unop( Iop_64to32, mkexpr( lo64 ) ) ); -+ store( irx_addr, unop( Iop_64to32, mkexpr( lo64 ) ) ); - - break; - } -@@ -15414,24 +15558,39 @@ static Bool dis_av_load ( VexAbiInfo* vb - case 0x006: { // lvsl (Load Vector for Shift Left, AV p123) - IRDirty* d; - UInt vD_off = vectorGuestRegOffset(vD_addr); -- IRExpr** args = mkIRExprVec_4( -+ IRExpr** args_be = mkIRExprVec_5( -+ IRExpr_BBPTR(), -+ mkU32(vD_off), -+ binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), -+ mkU32(0xF)), -+ mkU32(0)/*left*/, -+ mkU32(1)/*Big Endian*/); -+ IRExpr** args_le = mkIRExprVec_5( - IRExpr_BBPTR(), -- mkU32(vD_off), -+ mkU32(vD_off), - binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), - mkU32(0xF)), -- mkU32(0)/*left*/ ); -+ mkU32(0)/*left*/, -+ mkU32(0)/*Little Endian*/); - if (!mode64) { - d = unsafeIRDirty_0_N ( - 0/*regparms*/, - "ppc32g_dirtyhelper_LVS", - fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS), -- args ); -+ args_be ); - } else { -- d = unsafeIRDirty_0_N ( -- 0/*regparms*/, -- "ppc64g_dirtyhelper_LVS", -- fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS), -- args ); -+ if (host_endness == VexEndnessBE) -+ d = unsafeIRDirty_0_N ( -+ 0/*regparms*/, -+ "ppc64g_dirtyhelper_LVS", -+ fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS), -+ args_be ); -+ else -+ d = unsafeIRDirty_0_N ( -+ 0/*regparms*/, -+ "ppc64g_dirtyhelper_LVS", -+ &ppc64g_dirtyhelper_LVS, -+ args_le ); - } - DIP("lvsl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); - /* declare guest state effects */ -@@ -15448,24 +15607,40 @@ static Bool dis_av_load ( VexAbiInfo* vb - case 0x026: { // lvsr (Load Vector for Shift Right, AV p125) - IRDirty* d; - UInt vD_off = vectorGuestRegOffset(vD_addr); -- IRExpr** args = mkIRExprVec_4( -- IRExpr_BBPTR(), -- mkU32(vD_off), -- binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), -- mkU32(0xF)), -- mkU32(1)/*right*/ ); -+ IRExpr** args_be = mkIRExprVec_5( -+ IRExpr_BBPTR(), -+ mkU32(vD_off), -+ binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), -+ mkU32(0xF)), -+ mkU32(1)/*right*/, -+ mkU32(1)/*Big Endian*/); -+ IRExpr** args_le = mkIRExprVec_5( -+ IRExpr_BBPTR(), -+ mkU32(vD_off), -+ binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)), -+ mkU32(0xF)), -+ mkU32(1)/*right*/, -+ mkU32(0)/*Little Endian*/); -+ - if (!mode64) { - d = unsafeIRDirty_0_N ( -- 0/*regparms*/, -+ 0/*regparms*/, - "ppc32g_dirtyhelper_LVS", - fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS), -- args ); -+ args_be ); - } else { -- d = unsafeIRDirty_0_N ( -- 0/*regparms*/, -- "ppc64g_dirtyhelper_LVS", -- fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS), -- args ); -+ if (host_endness == VexEndnessBE) -+ d = unsafeIRDirty_0_N ( -+ 0/*regparms*/, -+ "ppc64g_dirtyhelper_LVS", -+ fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS), -+ args_be ); -+ else -+ d = unsafeIRDirty_0_N ( -+ 0/*regparms*/, -+ "ppc64g_dirtyhelper_LVS", -+ &ppc64g_dirtyhelper_LVS, -+ args_le ); - } - DIP("lvsr v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); - /* declare guest state effects */ -@@ -15484,29 +15659,29 @@ static Bool dis_av_load ( VexAbiInfo* vb - /* loads addressed byte into vector[EA[0:3] - since all other destination bytes are undefined, - can simply load entire vector from 16-aligned EA */ -- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); -+ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); - break; - - case 0x027: // lvehx (Load Vector Element Half Word Indexed, AV p121) - DIP("lvehx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); - /* see note for lvebx */ -- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); -+ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); - break; - - case 0x047: // lvewx (Load Vector Element Word Indexed, AV p122) - DIP("lvewx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); - /* see note for lvebx */ -- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); -+ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); - break; - - case 0x067: // lvx (Load Vector Indexed, AV p127) - DIP("lvx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); -- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); -+ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); - break; - - case 0x167: // lvxl (Load Vector Indexed LRU, AV p128) - DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); -- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); -+ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) ); - break; - - default: -@@ -15550,12 +15725,16 @@ static Bool dis_av_store ( UInt theInstr - assign( eb, binop(Iop_And8, mkU8(0xF), - unop(Iop_32to8, - mkNarrowTo32(ty, mkexpr(EA)) )) ); -- assign( idx, binop(Iop_Shl8, -- binop(Iop_Sub8, mkU8(15), mkexpr(eb)), -- mkU8(3)) ); -- storeBE( mkexpr(EA), -- unop(Iop_32to8, unop(Iop_V128to32, -- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); -+ if (host_endness == VexEndnessLE) { -+ assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) ); -+ } else { -+ assign( idx, binop(Iop_Shl8, -+ binop(Iop_Sub8, mkU8(15), mkexpr(eb)), -+ mkU8(3)) ); -+ } -+ store( mkexpr(EA), -+ unop( Iop_32to8, unop(Iop_V128to32, -+ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); - break; - } - case 0x0A7: { // stvehx (Store Vector Half Word Indexed, AV p132) -@@ -15563,12 +15742,16 @@ static Bool dis_av_store ( UInt theInstr - assign( addr_aligned, addr_align(mkexpr(EA), 2) ); - assign( eb, binop(Iop_And8, mkU8(0xF), - mkNarrowTo8(ty, mkexpr(addr_aligned) )) ); -- assign( idx, binop(Iop_Shl8, -- binop(Iop_Sub8, mkU8(14), mkexpr(eb)), -- mkU8(3)) ); -- storeBE( mkexpr(addr_aligned), -- unop(Iop_32to16, unop(Iop_V128to32, -- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); -+ if (host_endness == VexEndnessLE) { -+ assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) ); -+ } else { -+ assign( idx, binop(Iop_Shl8, -+ binop(Iop_Sub8, mkU8(14), mkexpr(eb)), -+ mkU8(3)) ); -+ } -+ store( mkexpr(addr_aligned), -+ unop( Iop_32to16, unop(Iop_V128to32, -+ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); - break; - } - case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133) -@@ -15576,23 +15759,27 @@ static Bool dis_av_store ( UInt theInstr - assign( addr_aligned, addr_align(mkexpr(EA), 4) ); - assign( eb, binop(Iop_And8, mkU8(0xF), - mkNarrowTo8(ty, mkexpr(addr_aligned) )) ); -- assign( idx, binop(Iop_Shl8, -- binop(Iop_Sub8, mkU8(12), mkexpr(eb)), -- mkU8(3)) ); -- storeBE( mkexpr(addr_aligned), -- unop(Iop_V128to32, -- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))) ); -+ if (host_endness == VexEndnessLE) { -+ assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) ); -+ } else { -+ assign( idx, binop(Iop_Shl8, -+ binop(Iop_Sub8, mkU8(12), mkexpr(eb)), -+ mkU8(3)) ); -+ } -+ store( mkexpr( addr_aligned), -+ unop( Iop_V128to32, -+ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))) ); - break; - } - - case 0x0E7: // stvx (Store Vector Indexed, AV p134) - DIP("stvx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); -- storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) ); -+ store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) ); - break; - - case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135) - DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); -- storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) ); -+ store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) ); - break; - - default: -@@ -18510,7 +18697,7 @@ DisResult disInstr_PPC_WRK ( - /* At least this is simple on PPC32: insns are all 4 bytes long, and - 4-aligned. So just fish the whole thing out of memory right now - and have done. */ -- theInstr = getUIntBigendianly( (UChar*)(&guest_code[delta]) ); -+ theInstr = getUIntPPCendianly( (UChar*)(&guest_code[delta]) ); - - if (0) vex_printf("insn: 0x%x\n", theInstr); - -@@ -18535,12 +18722,12 @@ DisResult disInstr_PPC_WRK ( - UInt word2 = mode64 ? 0x78006800 : 0x5400683E; - UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E; - UInt word4 = mode64 ? 0x78009802 : 0x5400983E; -- if (getUIntBigendianly(code+ 0) == word1 && -- getUIntBigendianly(code+ 4) == word2 && -- getUIntBigendianly(code+ 8) == word3 && -- getUIntBigendianly(code+12) == word4) { -+ if (getUIntPPCendianly(code+ 0) == word1 && -+ getUIntPPCendianly(code+ 4) == word2 && -+ getUIntPPCendianly(code+ 8) == word3 && -+ getUIntPPCendianly(code+12) == word4) { - /* Got a "Special" instruction preamble. Which one is it? */ -- if (getUIntBigendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) { -+ if (getUIntPPCendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) { - /* %R3 = client_request ( %R4 ) */ - DIP("r3 = client_request ( %%r4 )\n"); - delta += 20; -@@ -18550,7 +18737,7 @@ DisResult disInstr_PPC_WRK ( - goto decode_success; - } - else -- if (getUIntBigendianly(code+16) == 0x7C421378 /* or 2,2,2 */) { -+ if (getUIntPPCendianly(code+16) == 0x7C421378 /* or 2,2,2 */) { - /* %R3 = guest_NRADDR */ - DIP("r3 = guest_NRADDR\n"); - delta += 20; -@@ -18559,18 +18746,27 @@ DisResult disInstr_PPC_WRK ( - goto decode_success; - } - else -- if (getUIntBigendianly(code+16) == 0x7C631B78 /* or 3,3,3 */) { -- /* branch-and-link-to-noredir %R11 */ -- DIP("branch-and-link-to-noredir r11\n"); -+ if (getUIntPPCendianly(code+16) == 0x7C631B78 /* or 3,3,3 */) { - delta += 20; -- putGST( PPC_GST_LR, mkSzImm(ty, guest_CIA_bbstart + (Long)delta) ); -- putGST( PPC_GST_CIA, getIReg(11)); -+ if (host_endness == VexEndnessLE) { -+ /* branch-and-link-to-noredir %R12 */ -+ DIP("branch-and-link-to-noredir r12\n"); -+ putGST( PPC_GST_LR, -+ mkSzImm(ty, guest_CIA_bbstart + (Long)delta) ); -+ putGST( PPC_GST_CIA, getIReg(12)); -+ } else { -+ /* branch-and-link-to-noredir %R11 */ -+ DIP("branch-and-link-to-noredir r11\n"); -+ putGST( PPC_GST_LR, -+ mkSzImm(ty, guest_CIA_bbstart + (Long)delta) ); -+ putGST( PPC_GST_CIA, getIReg(11)); -+ } - dres.jk_StopHere = Ijk_NoRedir; - dres.whatNext = Dis_StopHere; - goto decode_success; - } - else -- if (getUIntBigendianly(code+16) == 0x7C842378 /* or 4,4,4 */) { -+ if (getUIntPPCendianly(code+16) == 0x7C842378 /* or 4,4,4 */) { - /* %R3 = guest_NRADDR_GPR2 */ - DIP("r3 = guest_NRADDR_GPR2\n"); - delta += 20; -@@ -18579,10 +18775,12 @@ DisResult disInstr_PPC_WRK ( - goto decode_success; - } - else -- if (getUIntBigendianly(code+16) == 0x7CA52B78 /* or 5,5,5 */) { -+ if (getUIntPPCendianly(code+16) == 0x7CA52B78 /* or 5,5,5 */) { - DIP("IR injection\n"); -- -- vex_inject_ir(irsb, Iend_BE); -+ if (host_endness == VexEndnessBE) -+ vex_inject_ir(irsb, Iend_BE); -+ else -+ vex_inject_ir(irsb, Iend_LE); - - delta += 20; - dres.len = 20; -@@ -18602,7 +18800,7 @@ DisResult disInstr_PPC_WRK ( - } - /* We don't know what it is. Set opc1/opc2 so decode_failure - can print the insn following the Special-insn preamble. */ -- theInstr = getUIntBigendianly(code+16); -+ theInstr = getUIntPPCendianly(code+16); - opc1 = ifieldOPC(theInstr); - opc2 = ifieldOPClo10(theInstr); - goto decode_failure; -@@ -19298,7 +19496,7 @@ DisResult disInstr_PPC_WRK ( - case 0x32E: case 0x34E: case 0x36E: // tabortdc., tabortwci., tabortdci. - case 0x38E: case 0x3AE: case 0x3EE: // tabort., treclaim., trechkpt. - if (dis_transactional_memory( theInstr, -- getUIntBigendianly( (UChar*)(&guest_code[delta + 4])), -+ getUIntPPCendianly( (UChar*)(&guest_code[delta + 4])), - abiinfo, &dres, - resteerOkFn, callback_opaque)) - goto decode_success; -@@ -19414,7 +19612,7 @@ DisResult disInstr_PPC_WRK ( - case 0x2F6: case 0x056: case 0x036: // dcba, dcbf, dcbst - case 0x116: case 0x0F6: case 0x3F6: // dcbt, dcbtst, dcbz - case 0x3D6: // icbi -- if (dis_cache_manage( theInstr, &dres, archinfo )) -+ if (dis_cache_manage( theInstr, &dres, archinfo )) - goto decode_success; - goto decode_failure; - -@@ -19504,7 +19702,7 @@ DisResult disInstr_PPC_WRK ( - // if allow_V is not set, we'll skip trying to decode. - if (!allow_V) goto decode_noV; - -- if (dis_vx_load( theInstr )) goto decode_success; -+ if (dis_vx_load( theInstr )) goto decode_success; - goto decode_failure; - - /* VSX Store */ -@@ -19517,14 +19715,14 @@ DisResult disInstr_PPC_WRK ( - // if allow_V is not set, we'll skip trying to decode. - if (!allow_V) goto decode_noV; - -- if (dis_vx_store( theInstr )) goto decode_success; -+ if (dis_vx_store( theInstr )) goto decode_success; - goto decode_failure; - - /* Miscellaneous ISA 2.06 instructions */ - case 0x1FA: // popcntd - case 0x17A: // popcntw - case 0x7A: // popcntb -- if (dis_int_logic( theInstr )) goto decode_success; -+ if (dis_int_logic( theInstr )) goto decode_success; - goto decode_failure; - - case 0x0FC: // bpermd -@@ -19931,6 +20129,13 @@ DisResult disInstr_PPC ( IRSB* ir - /* global -- ick */ - mode64 = guest_arch == VexArchPPC64; - ty = mode64 ? Ity_I64 : Ity_I32; -+ if (!mode64 && (host_endness_IN == VexEndnessLE)) { -+ vex_printf("disInstr(ppc): Little Endian 32-bit mode is not supported\n"); -+ dres.whatNext = Dis_StopHere; -+ dres.jk_StopHere = Ijk_NoDecode; -+ dres.len = 0; -+ return dres; -+ } - - /* do some sanity checks */ - mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V -@@ -19956,7 +20161,7 @@ DisResult disInstr_PPC ( IRSB* ir - guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta); - - dres = disInstr_PPC_WRK ( resteerOkFn, resteerCisOk, callback_opaque, -- delta, archinfo, abiinfo, sigill_diag_IN ); -+ delta, archinfo, abiinfo, sigill_diag_IN); - - return dres; - } diff --git a/VEX-r2915.diff b/VEX-r2915.diff deleted file mode 100644 index d8179df..0000000 --- a/VEX-r2915.diff +++ /dev/null @@ -1,12 +0,0 @@ -Index: VEX/priv/guest_ppc_toIR.c -=================================================================== ---- VEX/priv/guest_ppc_toIR.c.orig -+++ VEX/priv/guest_ppc_toIR.c -@@ -20134,6 +20134,7 @@ DisResult disInstr_PPC ( IRSB* ir - dres.whatNext = Dis_StopHere; - dres.jk_StopHere = Ijk_NoDecode; - dres.len = 0; -+ dis.continueAt = 0; - return dres; - } - diff --git a/VEX-r2916.diff b/VEX-r2916.diff deleted file mode 100644 index 9ff6090..0000000 --- a/VEX-r2916.diff +++ /dev/null @@ -1,13 +0,0 @@ -Index: VEX/priv/guest_ppc_toIR.c -=================================================================== ---- VEX/priv/guest_ppc_toIR.c.orig -+++ VEX/priv/guest_ppc_toIR.c -@@ -20134,7 +20134,7 @@ DisResult disInstr_PPC ( IRSB* ir - dres.whatNext = Dis_StopHere; - dres.jk_StopHere = Ijk_NoDecode; - dres.len = 0; -- dis.continueAt = 0; -+ dres.continueAt = 0; - return dres; - } - diff --git a/aarch64-VEX-support.diff b/aarch64-VEX-support.diff deleted file mode 100644 index 88e745d..0000000 --- a/aarch64-VEX-support.diff +++ /dev/null @@ -1,35641 +0,0 @@ -Index: auxprogs/genoffsets.c -=================================================================== ---- auxprogs/genoffsets.c (.../tags/VEX_3_9_0) (revision 2863) -+++ auxprogs/genoffsets.c (.../trunk) (revision 2863) -@@ -51,6 +51,7 @@ - #include "../pub/libvex_guest_ppc32.h" - #include "../pub/libvex_guest_ppc64.h" - #include "../pub/libvex_guest_arm.h" -+#include "../pub/libvex_guest_arm64.h" - #include "../pub/libvex_guest_s390x.h" - #include "../pub/libvex_guest_mips32.h" - #include "../pub/libvex_guest_mips64.h" -@@ -159,6 +160,19 @@ - GENOFFSET(ARM,arm,R14); - GENOFFSET(ARM,arm,R15T); - -+ // arm64 -+ GENOFFSET(ARM64,arm64,X0); -+ GENOFFSET(ARM64,arm64,X1); -+ GENOFFSET(ARM64,arm64,X2); -+ GENOFFSET(ARM64,arm64,X3); -+ GENOFFSET(ARM64,arm64,X4); -+ GENOFFSET(ARM64,arm64,X5); -+ GENOFFSET(ARM64,arm64,X6); -+ GENOFFSET(ARM64,arm64,X7); -+ GENOFFSET(ARM64,arm64,X8); -+ GENOFFSET(ARM64,arm64,XSP); -+ GENOFFSET(ARM64,arm64,PC); -+ - // s390x - GENOFFSET(S390X,s390x,r2); - GENOFFSET(S390X,s390x,r3); -Index: priv/guest_amd64_helpers.c -=================================================================== ---- priv/guest_amd64_helpers.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_amd64_helpers.c (.../trunk) (revision 2863) -@@ -3777,6 +3777,7 @@ - - vex_state->guest_DFLAG = 1; /* forwards */ - vex_state->guest_IDFLAG = 0; -+ vex_state->guest_ACFLAG = 0; - - /* HACK: represent the offset associated with %fs==0. This - assumes that %fs is only ever zero. */ -@@ -3817,8 +3818,8 @@ - - /* These should not ever be either read or written, but we - initialise them anyway. */ -- vex_state->guest_TISTART = 0; -- vex_state->guest_TILEN = 0; -+ vex_state->guest_CMSTART = 0; -+ vex_state->guest_CMLEN = 0; - - vex_state->guest_NRADDR = 0; - vex_state->guest_SC_CLASS = 0; -@@ -3923,8 +3924,8 @@ - // /* */ ALWAYSDEFD(guest_GDT), - /* 10 */ ALWAYSDEFD(guest_EMNOTE), - /* 11 */ ALWAYSDEFD(guest_SSEROUND), -- /* 12 */ ALWAYSDEFD(guest_TISTART), -- /* 13 */ ALWAYSDEFD(guest_TILEN), -+ /* 12 */ ALWAYSDEFD(guest_CMSTART), -+ /* 13 */ ALWAYSDEFD(guest_CMLEN), - /* 14 */ ALWAYSDEFD(guest_SC_CLASS), - /* 15 */ ALWAYSDEFD(guest_IP_AT_SYSCALL) - } -Index: priv/guest_amd64_toIR.c -=================================================================== ---- priv/guest_amd64_toIR.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_amd64_toIR.c (.../trunk) (revision 2863) -@@ -51,10 +51,6 @@ - float-to-float rounding. For all other operations, - round-to-nearest is used, regardless. - -- * FP sin/cos/tan/sincos: C2 flag is always cleared. IOW the -- simulation claims the argument is in-range (-2^63 <= arg <= 2^63) -- even when it isn't. -- - * some of the FCOM cases could do with testing -- not convinced - that the args are the right way round. - -@@ -436,8 +432,8 @@ - #define OFFB_YMM16 offsetof(VexGuestAMD64State,guest_YMM16) - - #define OFFB_EMNOTE offsetof(VexGuestAMD64State,guest_EMNOTE) --#define OFFB_TISTART offsetof(VexGuestAMD64State,guest_TISTART) --#define OFFB_TILEN offsetof(VexGuestAMD64State,guest_TILEN) -+#define OFFB_CMSTART offsetof(VexGuestAMD64State,guest_CMSTART) -+#define OFFB_CMLEN offsetof(VexGuestAMD64State,guest_CMLEN) - - #define OFFB_NRADDR offsetof(VexGuestAMD64State,guest_NRADDR) - -@@ -771,10 +767,10 @@ - return toBool( ! haveNo66noF2noF3(pfx) ); - } - --/* Return True iff pfx has 66 or F2 set */ --static Bool have66orF2 ( Prefix pfx ) -+/* Return True iff pfx has 66 or F3 set */ -+static Bool have66orF3 ( Prefix pfx ) - { -- return toBool((pfx & (PFX_66|PFX_F2)) > 0); -+ return toBool((pfx & (PFX_66|PFX_F3)) > 0); - } - - /* Clear all the segment-override bits in a prefix. */ -@@ -4270,8 +4266,12 @@ - - modrm = getUChar(delta); - if (epartIsReg(modrm)) { -- /* F2/XACQ and F3/XREL are always invalid in the non-mem case. */ -- if (haveF2orF3(pfx)) goto unhandledR; -+ /* F2/XACQ and F3/XREL are always invalid in the non-mem case. -+ F2/CALL and F2/JMP may have bnd prefix. */ -+ if (haveF2orF3(pfx) -+ && ! (haveF2(pfx) -+ && (gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4))) -+ goto unhandledR; - assign(t1, getIRegE(sz,pfx,modrm)); - switch (gregLO3ofRM(modrm)) { - case 0: /* INC */ -@@ -4291,6 +4291,7 @@ - case 2: /* call Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledR; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, getIRegE(sz,pfx,modrm)); -@@ -4306,6 +4307,7 @@ - case 4: /* jmp Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledR; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, getIRegE(sz,pfx,modrm)); -@@ -4338,11 +4340,14 @@ - showSz ? nameISize(sz) : ' ', - nameIRegE(sz, pfx, modrm)); - } else { -- /* Decide if F2/XACQ or F3/XREL might be valid. */ -+ /* Decide if F2/XACQ, F3/XREL, F2/CALL or F2/JMP might be valid. */ - Bool validF2orF3 = haveF2orF3(pfx) ? False : True; - if ((gregLO3ofRM(modrm) == 0/*INC*/ || gregLO3ofRM(modrm) == 1/*DEC*/) - && haveF2orF3(pfx) && !haveF2andF3(pfx) && haveLOCK(pfx)) { - validF2orF3 = True; -+ } else if ((gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4) -+ && (haveF2(pfx) && !haveF3(pfx))) { -+ validF2orF3 = True; - } - if (!validF2orF3) goto unhandledM; - /* */ -@@ -4379,6 +4384,7 @@ - case 2: /* call Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledM; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, loadLE(Ity_I64,mkexpr(addr))); -@@ -4394,6 +4400,7 @@ - case 4: /* JMP Ev */ - /* Ignore any sz value and operate as if sz==8. */ - if (!(sz == 4 || sz == 8)) goto unhandledM; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - sz = 8; - t3 = newTemp(Ity_I64); - assign(t3, loadLE(Ity_I64,mkexpr(addr))); -@@ -5066,6 +5073,42 @@ - } - - -+/* Given i, and some expression e, and a condition cond, generate IR -+ which has the same effect as put_ST(i,e) when cond is true and has -+ no effect when cond is false. Given the lack of proper -+ if-then-else in the IR, this is pretty tricky. -+*/ -+ -+static void maybe_put_ST ( IRTemp cond, Int i, IRExpr* value ) -+{ -+ // new_tag = if cond then FULL else old_tag -+ // new_val = if cond then (if old_tag==FULL then NaN else val) -+ // else old_val -+ -+ IRTemp old_tag = newTemp(Ity_I8); -+ assign(old_tag, get_ST_TAG(i)); -+ IRTemp new_tag = newTemp(Ity_I8); -+ assign(new_tag, -+ IRExpr_ITE(mkexpr(cond), mkU8(1)/*FULL*/, mkexpr(old_tag))); -+ -+ IRTemp old_val = newTemp(Ity_F64); -+ assign(old_val, get_ST_UNCHECKED(i)); -+ IRTemp new_val = newTemp(Ity_F64); -+ assign(new_val, -+ IRExpr_ITE(mkexpr(cond), -+ IRExpr_ITE(binop(Iop_CmpNE8, mkexpr(old_tag), mkU8(0)), -+ /* non-0 means full */ -+ mkQNaN64(), -+ /* 0 means empty */ -+ value), -+ mkexpr(old_val))); -+ -+ put_ST_UNCHECKED(i, mkexpr(new_val)); -+ // put_ST_UNCHECKED incorrectly sets tag(i) to always be FULL. So -+ // now set it to new_tag instead. -+ put_ST_TAG(i, mkexpr(new_tag)); -+} -+ - /* Adjust FTOP downwards by one register. */ - - static void fp_push ( void ) -@@ -5073,6 +5116,14 @@ - put_ftop( binop(Iop_Sub32, get_ftop(), mkU32(1)) ); - } - -+/* Adjust FTOP downwards by one register when COND is 1:I1. Else -+ don't change it. */ -+ -+static void maybe_fp_push ( IRTemp cond ) -+{ -+ put_ftop( binop(Iop_Sub32, get_ftop(), unop(Iop_1Uto32,mkexpr(cond))) ); -+} -+ - /* Adjust FTOP upwards by one register, and mark the vacated register - as empty. */ - -@@ -5082,12 +5133,49 @@ - put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) ); - } - --/* Clear the C2 bit of the FPU status register, for -- sin/cos/tan/sincos. */ -+/* Set the C2 bit of the FPU status register to e[0]. Assumes that -+ e[31:1] == 0. -+*/ -+static void set_C2 ( IRExpr* e ) -+{ -+ IRExpr* cleared = binop(Iop_And64, get_C3210(), mkU64(~AMD64G_FC_MASK_C2)); -+ put_C3210( binop(Iop_Or64, -+ cleared, -+ binop(Iop_Shl64, e, mkU8(AMD64G_FC_SHIFT_C2))) ); -+} - --static void clear_C2 ( void ) -+/* Generate code to check that abs(d64) < 2^63 and is finite. This is -+ used to do the range checks for FSIN, FCOS, FSINCOS and FPTAN. The -+ test is simple, but the derivation of it is not so simple. -+ -+ The exponent field for an IEEE754 double is 11 bits. That means it -+ can take values 0 through 0x7FF. If the exponent has value 0x7FF, -+ the number is either a NaN or an Infinity and so is not finite. -+ Furthermore, a finite value of exactly 2^63 is the smallest value -+ that has exponent value 0x43E. Hence, what we need to do is -+ extract the exponent, ignoring the sign bit and mantissa, and check -+ it is < 0x43E, or <= 0x43D. -+ -+ To make this easily applicable to 32- and 64-bit targets, a -+ roundabout approach is used. First the number is converted to I64, -+ then the top 32 bits are taken. Shifting them right by 20 bits -+ places the sign bit and exponent in the bottom 12 bits. Anding -+ with 0x7FF gets rid of the sign bit, leaving just the exponent -+ available for comparison. -+*/ -+static IRTemp math_IS_TRIG_ARG_FINITE_AND_IN_RANGE ( IRTemp d64 ) - { -- put_C3210( binop(Iop_And64, get_C3210(), mkU64(~AMD64G_FC_MASK_C2)) ); -+ IRTemp i64 = newTemp(Ity_I64); -+ assign(i64, unop(Iop_ReinterpF64asI64, mkexpr(d64)) ); -+ IRTemp exponent = newTemp(Ity_I32); -+ assign(exponent, -+ binop(Iop_And32, -+ binop(Iop_Shr32, unop(Iop_64HIto32, mkexpr(i64)), mkU8(20)), -+ mkU32(0x7FF))); -+ IRTemp in_range_and_finite = newTemp(Ity_I1); -+ assign(in_range_and_finite, -+ binop(Iop_CmpLE32U, mkexpr(exponent), mkU32(0x43D))); -+ return in_range_and_finite; - } - - /* Invent a plausible-looking FPU status word value: -@@ -5717,16 +5805,31 @@ - fp_pop(); - break; - -- case 0xF2: /* FPTAN */ -- DIP("ftan\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_TanF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- get_ST(0))); -- fp_push(); -- put_ST(0, IRExpr_Const(IRConst_F64(1.0))); -- clear_C2(); /* HACK */ -+ case 0xF2: { /* FPTAN */ -+ DIP("fptan\n"); -+ IRTemp argD = newTemp(Ity_F64); -+ assign(argD, get_ST(0)); -+ IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); -+ IRTemp resD = newTemp(Ity_F64); -+ assign(resD, -+ IRExpr_ITE( -+ mkexpr(argOK), -+ binop(Iop_TanF64, -+ get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ mkexpr(argD)), -+ mkexpr(argD)) -+ ); -+ put_ST_UNCHECKED(0, mkexpr(resD)); -+ /* Conditionally push 1.0 on the stack, if the arg is -+ in range */ -+ maybe_fp_push(argOK); -+ maybe_put_ST(argOK, 0, -+ IRExpr_Const(IRConst_F64(1.0))); -+ set_C2( binop(Iop_Xor64, -+ unop(Iop_1Uto64, mkexpr(argOK)), -+ mkU64(1)) ); - break; -+ } - - case 0xF3: /* FPATAN */ - DIP("fpatan\n"); -@@ -5842,19 +5945,30 @@ - break; - - case 0xFB: { /* FSINCOS */ -- IRTemp a1 = newTemp(Ity_F64); -- assign( a1, get_ST(0) ); - DIP("fsincos\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_SinF64, -+ IRTemp argD = newTemp(Ity_F64); -+ assign(argD, get_ST(0)); -+ IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); -+ IRTemp resD = newTemp(Ity_F64); -+ assign(resD, -+ IRExpr_ITE( -+ mkexpr(argOK), -+ binop(Iop_SinF64, -+ get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ mkexpr(argD)), -+ mkexpr(argD)) -+ ); -+ put_ST_UNCHECKED(0, mkexpr(resD)); -+ /* Conditionally push the cos value on the stack, if -+ the arg is in range */ -+ maybe_fp_push(argOK); -+ maybe_put_ST(argOK, 0, -+ binop(Iop_CosF64, - get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- mkexpr(a1))); -- fp_push(); -- put_ST(0, -- binop(Iop_CosF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- mkexpr(a1))); -- clear_C2(); /* HACK */ -+ mkexpr(argD))); -+ set_C2( binop(Iop_Xor64, -+ unop(Iop_1Uto64, mkexpr(argOK)), -+ mkU64(1)) ); - break; - } - -@@ -5873,24 +5987,29 @@ - get_ST(1))); - break; - -- case 0xFE: /* FSIN */ -- DIP("fsin\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_SinF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- get_ST(0))); -- clear_C2(); /* HACK */ -+ case 0xFE: /* FSIN */ -+ case 0xFF: { /* FCOS */ -+ Bool isSIN = modrm == 0xFE; -+ DIP("%s\n", isSIN ? "fsin" : "fcos"); -+ IRTemp argD = newTemp(Ity_F64); -+ assign(argD, get_ST(0)); -+ IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); -+ IRTemp resD = newTemp(Ity_F64); -+ assign(resD, -+ IRExpr_ITE( -+ mkexpr(argOK), -+ binop(isSIN ? Iop_SinF64 : Iop_CosF64, -+ get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ mkexpr(argD)), -+ mkexpr(argD)) -+ ); -+ put_ST_UNCHECKED(0, mkexpr(resD)); -+ set_C2( binop(Iop_Xor64, -+ unop(Iop_1Uto64, mkexpr(argOK)), -+ mkU64(1)) ); - break; -+ } - -- case 0xFF: /* FCOS */ -- DIP("fcos\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_CosF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- get_ST(0))); -- clear_C2(); /* HACK */ -- break; -- - default: - goto decode_fail; - } -@@ -8548,6 +8667,32 @@ - /*--- SSE/SSE2/SSE3 helpers ---*/ - /*------------------------------------------------------------*/ - -+/* Indicates whether the op requires a rounding-mode argument. Note -+ that this covers only vector floating point arithmetic ops, and -+ omits the scalar ones that need rounding modes. Note also that -+ inconsistencies here will get picked up later by the IR sanity -+ checker, so this isn't correctness-critical. */ -+static Bool requiresRMode ( IROp op ) -+{ -+ switch (op) { -+ /* 128 bit ops */ -+ case Iop_Add32Fx4: case Iop_Sub32Fx4: -+ case Iop_Mul32Fx4: case Iop_Div32Fx4: -+ case Iop_Add64Fx2: case Iop_Sub64Fx2: -+ case Iop_Mul64Fx2: case Iop_Div64Fx2: -+ /* 256 bit ops */ -+ case Iop_Add32Fx8: case Iop_Sub32Fx8: -+ case Iop_Mul32Fx8: case Iop_Div32Fx8: -+ case Iop_Add64Fx4: case Iop_Sub64Fx4: -+ case Iop_Mul64Fx4: case Iop_Div64Fx4: -+ return True; -+ default: -+ break; -+ } -+ return False; -+} -+ -+ - /* Worker function; do not call directly. - Handles full width G = G `op` E and G = (not G) `op` E. - */ -@@ -8563,13 +8708,20 @@ - Int alen; - IRTemp addr; - UChar rm = getUChar(delta); -+ Bool needsRMode = requiresRMode(op); - IRExpr* gpart - = invertG ? unop(Iop_NotV128, getXMMReg(gregOfRexRM(pfx,rm))) - : getXMMReg(gregOfRexRM(pfx,rm)); - if (epartIsReg(rm)) { -- putXMMReg( gregOfRexRM(pfx,rm), -- binop(op, gpart, -- getXMMReg(eregOfRexRM(pfx,rm))) ); -+ putXMMReg( -+ gregOfRexRM(pfx,rm), -+ needsRMode -+ ? triop(op, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ gpart, -+ getXMMReg(eregOfRexRM(pfx,rm))) -+ : binop(op, gpart, -+ getXMMReg(eregOfRexRM(pfx,rm))) -+ ); - DIP("%s %s,%s\n", opname, - nameXMMReg(eregOfRexRM(pfx,rm)), - nameXMMReg(gregOfRexRM(pfx,rm)) ); -@@ -8576,9 +8728,15 @@ - return delta+1; - } else { - addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); -- putXMMReg( gregOfRexRM(pfx,rm), -- binop(op, gpart, -- loadLE(Ity_V128, mkexpr(addr))) ); -+ putXMMReg( -+ gregOfRexRM(pfx,rm), -+ needsRMode -+ ? triop(op, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ gpart, -+ loadLE(Ity_V128, mkexpr(addr))) -+ : binop(op, gpart, -+ loadLE(Ity_V128, mkexpr(addr))) -+ ); - DIP("%s %s,%s\n", opname, - dis_buf, - nameXMMReg(gregOfRexRM(pfx,rm)) ); -@@ -10982,9 +11140,11 @@ - IRTemp subV = newTemp(Ity_V128); - IRTemp a1 = newTemp(Ity_I64); - IRTemp s0 = newTemp(Ity_I64); -+ IRTemp rm = newTemp(Ity_I32); - -- assign( addV, binop(Iop_Add64Fx2, mkexpr(dV), mkexpr(sV)) ); -- assign( subV, binop(Iop_Sub64Fx2, mkexpr(dV), mkexpr(sV)) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( addV, triop(Iop_Add64Fx2, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); -+ assign( subV, triop(Iop_Sub64Fx2, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); - - assign( a1, unop(Iop_V128HIto64, mkexpr(addV) )); - assign( s0, unop(Iop_V128to64, mkexpr(subV) )); -@@ -11000,10 +11160,12 @@ - IRTemp a3, a2, a1, a0, s3, s2, s1, s0; - IRTemp addV = newTemp(Ity_V256); - IRTemp subV = newTemp(Ity_V256); -+ IRTemp rm = newTemp(Ity_I32); - a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID; - -- assign( addV, binop(Iop_Add64Fx4, mkexpr(dV), mkexpr(sV)) ); -- assign( subV, binop(Iop_Sub64Fx4, mkexpr(dV), mkexpr(sV)) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( addV, triop(Iop_Add64Fx4, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); -+ assign( subV, triop(Iop_Sub64Fx4, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); - - breakupV256to64s( addV, &a3, &a2, &a1, &a0 ); - breakupV256to64s( subV, &s3, &s2, &s1, &s0 ); -@@ -11019,10 +11181,12 @@ - IRTemp a3, a2, a1, a0, s3, s2, s1, s0; - IRTemp addV = newTemp(Ity_V128); - IRTemp subV = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); - a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID; - -- assign( addV, binop(Iop_Add32Fx4, mkexpr(dV), mkexpr(sV)) ); -- assign( subV, binop(Iop_Sub32Fx4, mkexpr(dV), mkexpr(sV)) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( addV, triop(Iop_Add32Fx4, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); -+ assign( subV, triop(Iop_Sub32Fx4, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); - - breakupV128to32s( addV, &a3, &a2, &a1, &a0 ); - breakupV128to32s( subV, &s3, &s2, &s1, &s0 ); -@@ -11039,11 +11203,13 @@ - IRTemp s7, s6, s5, s4, s3, s2, s1, s0; - IRTemp addV = newTemp(Ity_V256); - IRTemp subV = newTemp(Ity_V256); -+ IRTemp rm = newTemp(Ity_I32); - a7 = a6 = a5 = a4 = a3 = a2 = a1 = a0 = IRTemp_INVALID; - s7 = s6 = s5 = s4 = s3 = s2 = s1 = s0 = IRTemp_INVALID; - -- assign( addV, binop(Iop_Add32Fx8, mkexpr(dV), mkexpr(sV)) ); -- assign( subV, binop(Iop_Sub32Fx8, mkexpr(dV), mkexpr(sV)) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( addV, triop(Iop_Add32Fx8, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); -+ assign( subV, triop(Iop_Sub32Fx8, mkexpr(rm), mkexpr(dV), mkexpr(sV)) ); - - breakupV256to32s( addV, &a7, &a6, &a5, &a4, &a3, &a2, &a1, &a0 ); - breakupV256to32s( subV, &s7, &s6, &s5, &s4, &s3, &s2, &s1, &s0 ); -@@ -13361,14 +13527,14 @@ - - /* Round addr down to the start of the containing block. */ - stmt( IRStmt_Put( -- OFFB_TISTART, -+ OFFB_CMSTART, - binop( Iop_And64, - mkexpr(addr), - mkU64( ~(lineszB-1) ))) ); - -- stmt( IRStmt_Put(OFFB_TILEN, mkU64(lineszB) ) ); -+ stmt( IRStmt_Put(OFFB_CMLEN, mkU64(lineszB) ) ); - -- jmp_lit(dres, Ijk_TInval, (Addr64)(guest_RIP_bbstart+delta)); -+ jmp_lit(dres, Ijk_InvalICache, (Addr64)(guest_RIP_bbstart+delta)); - - DIP("clflush %s\n", dis_buf); - goto decode_success; -@@ -14594,6 +14760,7 @@ - IRTemp s3, s2, s1, s0, d3, d2, d1, d0; - IRTemp leftV = newTemp(Ity_V128); - IRTemp rightV = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); - s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID; - - breakupV128to32s( sV, &s3, &s2, &s1, &s0 ); -@@ -14603,8 +14770,9 @@ - assign( rightV, mkV128from32s( s3, s1, d3, d1 ) ); - - IRTemp res = newTemp(Ity_V128); -- assign( res, binop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, -- mkexpr(leftV), mkexpr(rightV) ) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( res, triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, -+ mkexpr(rm), mkexpr(leftV), mkexpr(rightV) ) ); - return res; - } - -@@ -14614,6 +14782,7 @@ - IRTemp s1, s0, d1, d0; - IRTemp leftV = newTemp(Ity_V128); - IRTemp rightV = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); - s1 = s0 = d1 = d0 = IRTemp_INVALID; - - breakupV128to64s( sV, &s1, &s0 ); -@@ -14623,8 +14792,9 @@ - assign( rightV, binop(Iop_64HLtoV128, mkexpr(s1), mkexpr(d1)) ); - - IRTemp res = newTemp(Ity_V128); -- assign( res, binop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, -- mkexpr(leftV), mkexpr(rightV) ) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( res, triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, -+ mkexpr(rm), mkexpr(leftV), mkexpr(rightV) ) ); - return res; - } - -@@ -18271,8 +18441,11 @@ - UShort imm8_perms[4] = { 0x0000, 0x00FF, 0xFF00, 0xFFFF }; - IRTemp and_vec = newTemp(Ity_V128); - IRTemp sum_vec = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ - assign( and_vec, binop( Iop_AndV128, -- binop( Iop_Mul64Fx2, -+ triop( Iop_Mul64Fx2, -+ mkexpr(rm), - mkexpr(dst_vec), mkexpr(src_vec) ), - mkV128( imm8_perms[ ((imm8 >> 4) & 3) ] ) ) ); - -@@ -18296,6 +18469,7 @@ - IRTemp tmp_prod_vec = newTemp(Ity_V128); - IRTemp prod_vec = newTemp(Ity_V128); - IRTemp sum_vec = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); - IRTemp v3, v2, v1, v0; - v3 = v2 = v1 = v0 = IRTemp_INVALID; - UShort imm8_perms[16] = { 0x0000, 0x000F, 0x00F0, 0x00FF, 0x0F00, -@@ -18303,15 +18477,17 @@ - 0xF0F0, 0xF0FF, 0xFF00, 0xFF0F, 0xFFF0, - 0xFFFF }; - -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ - assign( tmp_prod_vec, - binop( Iop_AndV128, -- binop( Iop_Mul32Fx4, mkexpr(dst_vec), -- mkexpr(src_vec) ), -+ triop( Iop_Mul32Fx4, -+ mkexpr(rm), mkexpr(dst_vec), mkexpr(src_vec) ), - mkV128( imm8_perms[((imm8 >> 4)& 15)] ) ) ); - breakupV128to32s( tmp_prod_vec, &v3, &v2, &v1, &v0 ); - assign( prod_vec, mkV128from32s( v3, v1, v2, v0 ) ); - -- assign( sum_vec, binop( Iop_Add32Fx4, -+ assign( sum_vec, triop( Iop_Add32Fx4, -+ mkexpr(rm), - binop( Iop_InterleaveHI32x4, - mkexpr(prod_vec), mkexpr(prod_vec) ), - binop( Iop_InterleaveLO32x4, -@@ -18319,7 +18495,8 @@ - - IRTemp res = newTemp(Ity_V128); - assign( res, binop( Iop_AndV128, -- binop( Iop_Add32Fx4, -+ triop( Iop_Add32Fx4, -+ mkexpr(rm), - binop( Iop_InterleaveHI32x4, - mkexpr(sum_vec), mkexpr(sum_vec) ), - binop( Iop_InterleaveLO32x4, -@@ -19550,7 +19727,8 @@ - case 0x7F: { /* JGb/JNLEb (jump greater) */ - Long jmpDelta; - const HChar* comment = ""; -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - jmpDelta = getSDisp8(delta); - vassert(-128 <= jmpDelta && jmpDelta < 128); - d64 = (guest_RIP_bbstart+delta+1) + jmpDelta; -@@ -20203,7 +20381,8 @@ - } - - case 0xC2: /* RET imm16 */ -- if (have66orF2orF3(pfx)) goto decode_failure; -+ if (have66orF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = getUDisp16(delta); - delta += 2; - dis_ret(dres, vbi, d64); -@@ -20211,8 +20390,9 @@ - return delta; - - case 0xC3: /* RET */ -- if (have66orF2(pfx)) goto decode_failure; -+ if (have66(pfx)) goto decode_failure; - /* F3 is acceptable on AMD. */ -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - dis_ret(dres, vbi, 0); - DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n"); - return delta; -@@ -20251,7 +20431,7 @@ - return delta; - } - /* BEGIN HACKY SUPPORT FOR xbegin */ -- if (modrm == 0xF8 && !have66orF2orF3(pfx) && sz == 4 -+ if (opc == 0xC7 && modrm == 0xF8 && !have66orF2orF3(pfx) && sz == 4 - && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { - delta++; /* mod/rm byte */ - d64 = getSDisp(4,delta); -@@ -20270,6 +20450,16 @@ - return delta; - } - /* END HACKY SUPPORT FOR xbegin */ -+ /* BEGIN HACKY SUPPORT FOR xabort */ -+ if (opc == 0xC6 && modrm == 0xF8 && !have66orF2orF3(pfx) && sz == 1 -+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) { -+ delta++; /* mod/rm byte */ -+ abyte = getUChar(delta); delta++; -+ /* There is never a real transaction in progress, so do nothing. */ -+ DIP("xabort $%d", (Int)abyte); -+ return delta; -+ } -+ /* END HACKY SUPPORT FOR xabort */ - goto decode_failure; - - case 0xC8: /* ENTER */ -@@ -20606,7 +20796,8 @@ - } - - case 0xE8: /* CALL J4 */ -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = getSDisp32(delta); delta += 4; - d64 += (guest_RIP_bbstart+delta); - /* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */ -@@ -20629,9 +20820,10 @@ - return delta; - - case 0xE9: /* Jv (jump, 16/32 offset) */ -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; - if (sz != 4) - goto decode_failure; /* JRS added 2004 July 11 */ -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta); - delta += sz; - if (resteerOkFn(callback_opaque,d64)) { -@@ -20645,9 +20837,10 @@ - return delta; - - case 0xEB: /* Jb (jump, byte offset) */ -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; - if (sz != 4) - goto decode_failure; /* JRS added 2004 July 11 */ -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta); - delta++; - if (resteerOkFn(callback_opaque,d64)) { -@@ -21065,7 +21258,8 @@ - case 0x8F: { /* JGb/JNLEb (jump greater) */ - Long jmpDelta; - const HChar* comment = ""; -- if (haveF2orF3(pfx)) goto decode_failure; -+ if (haveF3(pfx)) goto decode_failure; -+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */ - jmpDelta = getSDisp32(delta); - d64 = (guest_RIP_bbstart+delta+4) + jmpDelta; - delta += 4; -@@ -21156,6 +21350,66 @@ - } - return delta; - -+ case 0x1A: -+ case 0x1B: { /* Future MPX instructions, currently NOPs. -+ BNDMK b, m F3 0F 1B -+ BNDCL b, r/m F3 0F 1A -+ BNDCU b, r/m F2 0F 1A -+ BNDCN b, r/m F2 0F 1B -+ BNDMOV b, b/m 66 0F 1A -+ BNDMOV b/m, b 66 0F 1B -+ BNDLDX b, mib 0F 1A -+ BNDSTX mib, b 0F 1B */ -+ -+ /* All instructions have two operands. One operand is always the -+ bnd register number (bnd0-bnd3, other register numbers are -+ ignored when MPX isn't enabled, but should generate an -+ exception if MPX is enabled) given by gregOfRexRM. The other -+ operand is either a ModRM:reg, ModRM:r/m or a SIB encoded -+ address, all of which can be decoded by using either -+ eregOfRexRM or disAMode. */ -+ -+ modrm = getUChar(delta); -+ int bnd = gregOfRexRM(pfx,modrm); -+ const HChar *oper; -+ if (epartIsReg(modrm)) { -+ oper = nameIReg64 (eregOfRexRM(pfx,modrm)); -+ delta += 1; -+ } else { -+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 ); -+ delta += alen; -+ oper = dis_buf; -+ } -+ -+ if (haveF3no66noF2 (pfx)) { -+ if (opc == 0x1B) { -+ DIP ("bndmk %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1A */ { -+ DIP ("bndcl %s, %%bnd%d\n", oper, bnd); -+ } -+ } else if (haveF2no66noF3 (pfx)) { -+ if (opc == 0x1A) { -+ DIP ("bndcu %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1B */ { -+ DIP ("bndcn %s, %%bnd%d\n", oper, bnd); -+ } -+ } else if (have66noF2noF3 (pfx)) { -+ if (opc == 0x1A) { -+ DIP ("bndmov %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1B */ { -+ DIP ("bndmov %%bnd%d, %s\n", bnd, oper); -+ } -+ } else if (haveNo66noF2noF3 (pfx)) { -+ if (opc == 0x1A) { -+ DIP ("bndldx %s, %%bnd%d\n", oper, bnd); -+ } else /* opc == 0x1B */ { -+ DIP ("bndstx %%bnd%d, %s\n", bnd, oper); -+ } -+ } else goto decode_failure; -+ -+ return delta; -+ } -+ - case 0xA2: { /* CPUID */ - /* Uses dirty helper: - void amd64g_dirtyhelper_CPUID ( VexGuestAMD64State* ) -@@ -21888,8 +22142,17 @@ - if (op != Iop_INVALID) { - vassert(opFn == NULL); - res = newTemp(Ity_V128); -- assign(res, swapArgs ? binop(op, mkexpr(tSR), mkexpr(tSL)) -- : binop(op, mkexpr(tSL), mkexpr(tSR))); -+ if (requiresRMode(op)) { -+ IRTemp rm = newTemp(Ity_I32); -+ assign(rm, get_FAKE_roundingmode()); /* XXXROUNDINGFIXME */ -+ assign(res, swapArgs -+ ? triop(op, mkexpr(rm), mkexpr(tSR), mkexpr(tSL)) -+ : triop(op, mkexpr(rm), mkexpr(tSL), mkexpr(tSR))); -+ } else { -+ assign(res, swapArgs -+ ? binop(op, mkexpr(tSR), mkexpr(tSL)) -+ : binop(op, mkexpr(tSL), mkexpr(tSR))); -+ } - } else { - vassert(opFn != NULL); - res = swapArgs ? opFn(tSR, tSL) : opFn(tSL, tSR); -@@ -22792,8 +23055,17 @@ - if (op != Iop_INVALID) { - vassert(opFn == NULL); - res = newTemp(Ity_V256); -- assign(res, swapArgs ? binop(op, mkexpr(tSR), mkexpr(tSL)) -- : binop(op, mkexpr(tSL), mkexpr(tSR))); -+ if (requiresRMode(op)) { -+ IRTemp rm = newTemp(Ity_I32); -+ assign(rm, get_FAKE_roundingmode()); /* XXXROUNDINGFIXME */ -+ assign(res, swapArgs -+ ? triop(op, mkexpr(rm), mkexpr(tSR), mkexpr(tSL)) -+ : triop(op, mkexpr(rm), mkexpr(tSL), mkexpr(tSR))); -+ } else { -+ assign(res, swapArgs -+ ? binop(op, mkexpr(tSR), mkexpr(tSL)) -+ : binop(op, mkexpr(tSL), mkexpr(tSR))); -+ } - } else { - vassert(opFn != NULL); - res = swapArgs ? opFn(tSR, tSL) : opFn(tSL, tSR); -@@ -30936,14 +31208,14 @@ - // injecting here can change. In which case the translation has to - // be redone. For ease of handling, we simply invalidate all the - // time. -- stmt(IRStmt_Put(OFFB_TISTART, mkU64(guest_RIP_curr_instr))); -- stmt(IRStmt_Put(OFFB_TILEN, mkU64(19))); -+ stmt(IRStmt_Put(OFFB_CMSTART, mkU64(guest_RIP_curr_instr))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(19))); - - delta += 19; - - stmt( IRStmt_Put( OFFB_RIP, mkU64(guest_RIP_bbstart + delta) ) ); - dres.whatNext = Dis_StopHere; -- dres.jk_StopHere = Ijk_TInval; -+ dres.jk_StopHere = Ijk_InvalICache; - goto decode_success; - } - /* We don't know what it is. */ -Index: priv/guest_arm64_defs.h -=================================================================== ---- priv/guest_arm64_defs.h (.../tags/VEX_3_9_0) (revision 0) -+++ priv/guest_arm64_defs.h (.../trunk) (revision 2863) -@@ -0,0 +1,244 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin guest_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VEX_GUEST_ARM64_DEFS_H -+#define __VEX_GUEST_ARM64_DEFS_H -+ -+#include "libvex_basictypes.h" -+#include "guest_generic_bb_to_IR.h" // DisResult -+ -+/*---------------------------------------------------------*/ -+/*--- arm64 to IR conversion ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Convert one ARM64 insn to IR. See the type DisOneInstrFn in -+ bb_to_IR.h. */ -+extern -+DisResult disInstr_ARM64 ( IRSB* irbb, -+ Bool (*resteerOkFn) ( void*, Addr64 ), -+ Bool resteerCisOk, -+ void* callback_opaque, -+ UChar* guest_code, -+ Long delta, -+ Addr64 guest_IP, -+ VexArch guest_arch, -+ VexArchInfo* archinfo, -+ VexAbiInfo* abiinfo, -+ Bool host_bigendian, -+ Bool sigill_diag ); -+ -+/* Used by the optimiser to specialise calls to helpers. */ -+extern -+IRExpr* guest_arm64_spechelper ( const HChar* function_name, -+ IRExpr** args, -+ IRStmt** precedingStmts, -+ Int n_precedingStmts ); -+ -+/* Describes to the optimser which part of the guest state require -+ precise memory exceptions. This is logically part of the guest -+ state description. */ -+extern -+Bool guest_arm64_state_requires_precise_mem_exns ( Int, Int ); -+ -+extern -+VexGuestLayout arm64Guest_layout; -+ -+ -+/*---------------------------------------------------------*/ -+/*--- arm64 guest helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* --- CLEAN HELPERS --- */ -+ -+/* Calculate NZCV from the supplied thunk components, in the positions -+ they appear in the CPSR, viz bits 31:28 for N Z C V respectively. -+ Returned bits 63:32 and 27:0 are zero. */ -+extern -+ULong arm64g_calculate_flags_nzcv ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ); -+ -+//ZZ /* Calculate the C flag from the thunk components, in the lowest bit -+//ZZ of the word (bit 0). */ -+//ZZ extern -+//ZZ UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1, -+//ZZ UInt cc_dep2, UInt cc_dep3 ); -+//ZZ -+//ZZ /* Calculate the V flag from the thunk components, in the lowest bit -+//ZZ of the word (bit 0). */ -+//ZZ extern -+//ZZ UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1, -+//ZZ UInt cc_dep2, UInt cc_dep3 ); -+//ZZ -+/* Calculate the specified condition from the thunk components, in the -+ lowest bit of the word (bit 0). */ -+extern -+ULong arm64g_calculate_condition ( /* ARM64Condcode << 4 | cc_op */ -+ ULong cond_n_op , -+ ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ); -+ -+//ZZ /* Calculate the QC flag from the thunk components, in the lowest bit -+//ZZ of the word (bit 0). */ -+//ZZ extern -+//ZZ UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2, -+//ZZ UInt resR1, UInt resR2 ); -+ -+ -+/*---------------------------------------------------------*/ -+/*--- Condition code stuff ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Flag masks. Defines positions of flag bits in the NZCV -+ register. */ -+#define ARM64G_CC_SHIFT_N 31 -+#define ARM64G_CC_SHIFT_Z 30 -+#define ARM64G_CC_SHIFT_C 29 -+#define ARM64G_CC_SHIFT_V 28 -+//ZZ #define ARMG_CC_SHIFT_Q 27 -+//ZZ -+//ZZ #define ARMG_CC_MASK_N (1 << ARMG_CC_SHIFT_N) -+//ZZ #define ARMG_CC_MASK_Z (1 << ARMG_CC_SHIFT_Z) -+//ZZ #define ARMG_CC_MASK_C (1 << ARMG_CC_SHIFT_C) -+//ZZ #define ARMG_CC_MASK_V (1 << ARMG_CC_SHIFT_V) -+//ZZ #define ARMG_CC_MASK_Q (1 << ARMG_CC_SHIFT_Q) -+ -+/* Flag thunk descriptors. A four-word thunk is used to record -+ details of the most recent flag-setting operation, so NZCV can -+ be computed later if needed. -+ -+ The four words are: -+ -+ CC_OP, which describes the operation. -+ -+ CC_DEP1, CC_DEP2, CC_NDEP. These are arguments to the -+ operation. We want set up the mcx_masks in flag helper calls -+ involving these fields so that Memcheck "believes" that the -+ resulting flags are data-dependent on both CC_DEP1 and -+ CC_DEP2. Hence the name DEP. -+ -+ When building the thunk, it is always necessary to write words into -+ CC_DEP1/2 and NDEP, even if those args are not used given the CC_OP -+ field. This is important because otherwise Memcheck could give -+ false positives as it does not understand the relationship between -+ the CC_OP field and CC_DEP1/2/NDEP, and so believes that the -+ definedness of the stored flags always depends on all 3 DEP values. -+ -+ A summary of the field usages is: -+ -+ OP DEP1 DEP2 DEP3 -+ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -+ -+ OP_COPY curr_NZCV:28x0 unused unused -+ OP_ADD32 argL argR unused -+ OP_ADD64 argL argR unused -+ OP_SUB32 argL argR unused -+ OP_SUB64 argL argR unused -+//ZZ OP_ADC argL argR 31x0:old_C -+//ZZ OP_SBB argL argR 31x0:old_C -+ OP_LOGIC32 result unused unused -+ OP_LOGIC64 result unused unused -+//ZZ OP_MUL result unused 30x0:old_C:old_V -+//ZZ OP_MULL resLO32 resHI32 30x0:old_C:old_V -+//ZZ */ -+ -+enum { -+ ARM64G_CC_OP_COPY=0, /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0 -+ just copy DEP1 to output */ -+ -+ ARM64G_CC_OP_ADD32, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+ ARM64G_CC_OP_ADD64, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+ ARM64G_CC_OP_SUB32, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+ ARM64G_CC_OP_SUB64, /* DEP1 = argL (Rn), DEP2 = argR (shifter_op), -+ DEP3 = 0 */ -+ -+//ZZ ARMG_CC_OP_ADC, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), -+//ZZ DEP3 = oldC (in LSB) */ -+//ZZ -+//ZZ ARMG_CC_OP_SBB, /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op), -+//ZZ DEP3 = oldC (in LSB) */ -+ -+ ARM64G_CC_OP_LOGIC32, /* DEP1 = result, DEP2 = 0, DEP3 = 0 */ -+ ARM64G_CC_OP_LOGIC64, /* DEP1 = result, DEP2 = 0, DEP3 = 0 */ -+ -+//ZZ ARMG_CC_OP_MUL, /* DEP1 = result, DEP2 = 0, DEP3 = oldC:old_V -+//ZZ (in bits 1:0) */ -+//ZZ -+//ZZ ARMG_CC_OP_MULL, /* DEP1 = resLO32, DEP2 = resHI32, DEP3 = oldC:old_V -+//ZZ (in bits 1:0) */ -+ -+ ARM64G_CC_OP_NUMBER -+}; -+ -+/* XXXX because of the calling conventions for -+ arm64g_calculate_condition, all these OP values MUST be in the range -+ 0 .. 15 only (viz, 4-bits). */ -+ -+ -+ -+/* Defines conditions which we can ask for */ -+ -+typedef -+ enum { -+ ARM64CondEQ = 0, /* equal : Z=1 */ -+ ARM64CondNE = 1, /* not equal : Z=0 */ -+ -+ ARM64CondCS = 2, /* >=u (higher or same) (aka HS) : C=1 */ -+ ARM64CondCC = 3, /* u (higher) : C=1 && Z=0 */ -+ ARM64CondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */ -+ -+ ARM64CondGE = 10, /* >=s (signed greater or equal) : N=V */ -+ ARM64CondLT = 11, /* s (signed greater) : Z=0 && N=V */ -+ ARM64CondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */ -+ -+ ARM64CondAL = 14, /* always (unconditional) : 1 */ -+ ARM64CondNV = 15 /* always (unconditional) : 1 */ -+ } -+ ARM64Condcode; -+ -+#endif /* ndef __VEX_GUEST_ARM64_DEFS_H */ -+ -+/*---------------------------------------------------------------*/ -+/*--- end guest_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -Index: priv/guest_arm64_helpers.c -=================================================================== ---- priv/guest_arm64_helpers.c (.../tags/VEX_3_9_0) (revision 0) -+++ priv/guest_arm64_helpers.c (.../trunk) (revision 2863) -@@ -0,0 +1,1292 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin guest_arm64_helpers.c ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "libvex_basictypes.h" -+#include "libvex_emnote.h" -+#include "libvex_guest_arm64.h" -+#include "libvex_ir.h" -+#include "libvex.h" -+ -+#include "main_util.h" -+#include "main_globals.h" -+#include "guest_generic_bb_to_IR.h" -+#include "guest_arm64_defs.h" -+ -+ -+/* This file contains helper functions for arm guest code. Calls to -+ these functions are generated by the back end. These calls are of -+ course in the host machine code and this file will be compiled to -+ host machine code, so that all makes sense. -+ -+ Only change the signatures of these helper functions very -+ carefully. If you change the signature here, you'll have to change -+ the parameters passed to it in the IR calls constructed by -+ guest_arm64_toIR.c. -+*/ -+ -+ -+/* Set to 1 to get detailed profiling info about individual N, Z, C -+ and V flag evaluation. */ -+#define PROFILE_NZCV_FLAGS 0 -+ -+#if PROFILE_NZCV_FLAGS -+ -+static UInt tab_eval[ARM64G_CC_OP_NUMBER][16]; -+static UInt initted = 0; -+static UInt tot_evals = 0; -+ -+static void initCounts ( void ) -+{ -+ UInt i, j; -+ for (i = 0; i < ARM64G_CC_OP_NUMBER; i++) { -+ for (j = 0; j < 16; j++) { -+ tab_eval[i][j] = 0; -+ } -+ } -+ initted = 1; -+} -+ -+static void showCounts ( void ) -+{ -+ const HChar* nameCC[16] -+ = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", -+ "HI", "LS", "GE", "LT", "GT", "LE", "AL", "NV" }; -+ UInt i, j; -+ ULong sum = 0; -+ vex_printf("\nCC_OP 0 1 2 3 " -+ " 4 5 6\n"); -+ vex_printf( "--------------------------------------------------" -+ "--------------------------\n"); -+ for (j = 0; j < 16; j++) { -+ vex_printf("%2d %s ", j, nameCC[j]); -+ for (i = 0; i < ARM64G_CC_OP_NUMBER; i++) { -+ vex_printf("%9d ", tab_eval[i][j]); -+ sum += tab_eval[i][j]; -+ } -+ vex_printf("\n"); -+ } -+ vex_printf("(In total %llu calls)\n", sum); -+} -+ -+#define NOTE_EVAL(_cc_op, _cond) \ -+ do { \ -+ if (!initted) initCounts(); \ -+ vassert( ((UInt)(_cc_op)) < ARM64G_CC_OP_NUMBER); \ -+ vassert( ((UInt)(_cond)) < 16); \ -+ tab_eval[(UInt)(_cc_op)][(UInt)(cond)]++; \ -+ tot_evals++; \ -+ if (0 == (tot_evals & 0x7FFF)) \ -+ showCounts(); \ -+ } while (0) -+ -+#endif /* PROFILE_NZCV_FLAGS */ -+ -+ -+/* Calculate the N flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_n ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong nf = (cc_dep1 >> ARM64G_CC_SHIFT_N) & 1; -+ return nf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong nf = (ULong)(res >> 31); -+ return nf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong nf = (ULong)(res >> 63); -+ return nf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL - argR; -+ ULong nf = (ULong)(res >> 31); -+ return nf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL - argR; -+ ULong nf = res >> 63; -+ return nf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt nf = res >> 31; -+//ZZ return nf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL - argR - (oldC ^ 1); -+//ZZ UInt nf = res >> 31; -+//ZZ return nf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: { -+ /* (res, unused, unused) */ -+ UInt res = (UInt)cc_dep1; -+ ULong nf = res >> 31; -+ return nf; -+ } -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ ULong res = cc_dep1; -+ ULong nf = res >> 63; -+ return nf; -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt res = cc_dep1; -+//ZZ UInt nf = res >> 31; -+//ZZ return nf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt resHi32 = cc_dep2; -+//ZZ UInt nf = resHi32 >> 31; -+//ZZ return nf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_n" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_n"); -+ } -+} -+ -+ -+/* Calculate the Z flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_z ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong zf = (cc_dep1 >> ARM64G_CC_SHIFT_Z) & 1; -+ return zf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL - argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL - argR; -+ ULong zf = res == 0; -+ return zf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt zf = res == 0; -+//ZZ return zf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL - argR - (oldC ^ 1); -+//ZZ UInt zf = res == 0; -+//ZZ return zf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: { -+ /* (res, unused, unused) */ -+ UInt res = (UInt)cc_dep1; -+ ULong zf = res == 0; -+ return zf; -+ } -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ ULong res = cc_dep1; -+ ULong zf = res == 0; -+ return zf; -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt res = cc_dep1; -+//ZZ UInt zf = res == 0; -+//ZZ return zf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt resLo32 = cc_dep1; -+//ZZ UInt resHi32 = cc_dep2; -+//ZZ UInt zf = (resHi32|resLo32) == 0; -+//ZZ return zf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_z" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_z"); -+ } -+} -+ -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate the C flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_c ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong cf = (cc_dep1 >> ARM64G_CC_SHIFT_C) & 1; -+ return cf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong cf = res < argL; -+ return cf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong cf = res < argL; -+ return cf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ ULong cf = argL >= argR; -+ return cf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong cf = argL >= argR; -+ return cf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt cf = oldC ? (res <= argL) : (res < argL); -+//ZZ return cf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt cf = oldC ? (argL >= argR) : (argL > argR); -+//ZZ return cf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ return 0; // C after logic is zero on arm64 -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt oldC = (cc_dep3 >> 1) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt cf = oldC; -+//ZZ return cf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt oldC = (cc_dep3 >> 1) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt cf = oldC; -+//ZZ return cf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_c" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_c"); -+ } -+} -+ -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate the V flag from the supplied thunk components, in the -+ least significant bit of the word. Returned bits 63:1 are zero. */ -+static -+ULong arm64g_calculate_flag_v ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ switch (cc_op) { -+ case ARM64G_CC_OP_COPY: { -+ /* (nzcv:28x0, unused, unused) */ -+ ULong vf = (cc_dep1 >> ARM64G_CC_SHIFT_V) & 1; -+ return vf; -+ } -+ case ARM64G_CC_OP_ADD32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL + argR; -+ ULong vf = (ULong)(((res ^ argL) & (res ^ argR)) >> 31); -+ return vf; -+ } -+ case ARM64G_CC_OP_ADD64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL + argR; -+ ULong vf = ((res ^ argL) & (res ^ argR)) >> 63; -+ return vf; -+ } -+ case ARM64G_CC_OP_SUB32: { -+ /* (argL, argR, unused) */ -+ UInt argL = (UInt)cc_dep1; -+ UInt argR = (UInt)cc_dep2; -+ UInt res = argL - argR; -+ ULong vf = (ULong)(((argL ^ argR) & (argL ^ res)) >> 31); -+ return vf; -+ } -+ case ARM64G_CC_OP_SUB64: { -+ /* (argL, argR, unused) */ -+ ULong argL = cc_dep1; -+ ULong argR = cc_dep2; -+ ULong res = argL - argR; -+ ULong vf = (((argL ^ argR) & (argL ^ res))) >> 63; -+ return vf; -+ } -+//ZZ case ARMG_CC_OP_ADC: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL + argR + oldC; -+//ZZ UInt vf = ((res ^ argL) & (res ^ argR)) >> 31; -+//ZZ return vf; -+//ZZ } -+//ZZ case ARMG_CC_OP_SBB: { -+//ZZ /* (argL, argR, oldC) */ -+//ZZ UInt argL = cc_dep1; -+//ZZ UInt argR = cc_dep2; -+//ZZ UInt oldC = cc_dep3; -+//ZZ vassert((oldC & ~1) == 0); -+//ZZ UInt res = argL - argR - (oldC ^ 1); -+//ZZ UInt vf = ((argL ^ argR) & (argL ^ res)) >> 31; -+//ZZ return vf; -+//ZZ } -+ case ARM64G_CC_OP_LOGIC32: -+ case ARM64G_CC_OP_LOGIC64: { -+ /* (res, unused, unused) */ -+ return 0; // V after logic is zero on arm64 -+ } -+//ZZ case ARMG_CC_OP_MUL: { -+//ZZ /* (res, unused, oldC:oldV) */ -+//ZZ UInt oldV = (cc_dep3 >> 0) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt vf = oldV; -+//ZZ return vf; -+//ZZ } -+//ZZ case ARMG_CC_OP_MULL: { -+//ZZ /* (resLo32, resHi32, oldC:oldV) */ -+//ZZ UInt oldV = (cc_dep3 >> 0) & 1; -+//ZZ vassert((cc_dep3 & ~3) == 0); -+//ZZ UInt vf = oldV; -+//ZZ return vf; -+//ZZ } -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_flag_v" -+ "( op=%llu, dep1=0x%llx, dep2=0x%llx, dep3=0x%llx )\n", -+ cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("arm64g_calculate_flag_v"); -+ } -+} -+ -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate NZCV from the supplied thunk components, in the positions -+ they appear in the CPSR, viz bits 31:28 for N Z C V respectively. -+ Returned bits 27:0 are zero. */ -+ULong arm64g_calculate_flags_nzcv ( ULong cc_op, ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ ULong f; -+ ULong res = 0; -+ f = 1 & arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_N); -+ f = 1 & arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_Z); -+ f = 1 & arm64g_calculate_flag_c(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_C); -+ f = 1 & arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ res |= (f << ARM64G_CC_SHIFT_V); -+ return res; -+} -+ -+//ZZ -+//ZZ /* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+//ZZ /* Calculate the QC flag from the arguments, in the lowest bit -+//ZZ of the word (bit 0). Urr, having this out of line is bizarre. -+//ZZ Push back inline. */ -+//ZZ UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2, -+//ZZ UInt resR1, UInt resR2 ) -+//ZZ { -+//ZZ if (resL1 != resR1 || resL2 != resR2) -+//ZZ return 1; -+//ZZ else -+//ZZ return 0; -+//ZZ } -+ -+/* CALLED FROM GENERATED CODE: CLEAN HELPER */ -+/* Calculate the specified condition from the thunk components, in the -+ lowest bit of the word (bit 0). Returned bits 63:1 are zero. */ -+ULong arm64g_calculate_condition ( /* ARM64Condcode << 4 | cc_op */ -+ ULong cond_n_op , -+ ULong cc_dep1, -+ ULong cc_dep2, ULong cc_dep3 ) -+{ -+ ULong cond = cond_n_op >> 4; -+ ULong cc_op = cond_n_op & 0xF; -+ ULong inv = cond & 1; -+ ULong nf, zf, vf, cf; -+ -+# if PROFILE_NZCV_FLAGS -+ NOTE_EVAL(cc_op, cond); -+# endif -+ -+ // vex_printf("XXXXXXXX %llx %llx %llx %llx\n", -+ // cond_n_op, cc_dep1, cc_dep2, cc_dep3); -+ -+ switch (cond) { -+ case ARM64CondEQ: // Z=1 => z -+ case ARM64CondNE: // Z=0 -+ zf = arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ zf; -+ -+ case ARM64CondCS: // C=1 => c -+ case ARM64CondCC: // C=0 -+ cf = arm64g_calculate_flag_c(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ cf; -+ -+ case ARM64CondMI: // N=1 => n -+ case ARM64CondPL: // N=0 -+ nf = arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ nf; -+ -+ case ARM64CondVS: // V=1 => v -+ case ARM64CondVC: // V=0 -+ vf = arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ vf; -+ -+ case ARM64CondHI: // C=1 && Z=0 => c & ~z -+ case ARM64CondLS: // C=0 || Z=1 -+ cf = arm64g_calculate_flag_c(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ zf = arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ (1 & (cf & ~zf)); -+ -+ case ARM64CondGE: // N=V => ~(n^v) -+ case ARM64CondLT: // N!=V -+ nf = arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ vf = arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ (1 & ~(nf ^ vf)); -+ -+ case ARM64CondGT: // Z=0 && N=V => ~z & ~(n^v) => ~(z | (n^v)) -+ case ARM64CondLE: // Z=1 || N!=V -+ nf = arm64g_calculate_flag_n(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ vf = arm64g_calculate_flag_v(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ zf = arm64g_calculate_flag_z(cc_op, cc_dep1, cc_dep2, cc_dep3); -+ return inv ^ (1 & ~(zf | (nf ^ vf))); -+ -+ case ARM64CondAL: // 1 -+ case ARM64CondNV: // 1 -+ return 1; -+ -+ default: -+ /* shouldn't really make these calls from generated code */ -+ vex_printf("arm64g_calculate_condition(ARM64)" -+ "( %llu, %llu, 0x%llx, 0x%llx, 0x%llx )\n", -+ cond, cc_op, cc_dep1, cc_dep2, cc_dep3 ); -+ vpanic("armg_calculate_condition(ARM64)"); -+ } -+} -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- Flag-helpers translation-time function specialisers. ---*/ -+/*--- These help iropt specialise calls the above run-time ---*/ -+/*--- flags functions. ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* Used by the optimiser to try specialisations. Returns an -+ equivalent expression, or NULL if none. */ -+ -+static Bool isU64 ( IRExpr* e, ULong n ) -+{ -+ return -+ toBool( e->tag == Iex_Const -+ && e->Iex.Const.con->tag == Ico_U64 -+ && e->Iex.Const.con->Ico.U64 == n ); -+} -+ -+IRExpr* guest_arm64_spechelper ( const HChar* function_name, -+ IRExpr** args, -+ IRStmt** precedingStmts, -+ Int n_precedingStmts ) -+{ -+# define unop(_op,_a1) IRExpr_Unop((_op),(_a1)) -+# define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2)) -+# define mkU64(_n) IRExpr_Const(IRConst_U64(_n)) -+# define mkU8(_n) IRExpr_Const(IRConst_U8(_n)) -+ -+ Int i, arity = 0; -+ for (i = 0; args[i]; i++) -+ arity++; -+//ZZ # if 0 -+//ZZ vex_printf("spec request:\n"); -+//ZZ vex_printf(" %s ", function_name); -+//ZZ for (i = 0; i < arity; i++) { -+//ZZ vex_printf(" "); -+//ZZ ppIRExpr(args[i]); -+//ZZ } -+//ZZ vex_printf("\n"); -+//ZZ # endif -+ -+ /* --------- specialising "arm64g_calculate_condition" --------- */ -+ -+ if (vex_streq(function_name, "arm64g_calculate_condition")) { -+ -+ /* specialise calls to the "arm64g_calculate_condition" function. -+ Not sure whether this is strictly necessary, but: the -+ replacement IR must produce only the values 0 or 1. Bits -+ 63:1 are required to be zero. */ -+ IRExpr *cond_n_op, *cc_dep1, *cc_dep2 ; //, *cc_ndep; -+ vassert(arity == 4); -+ cond_n_op = args[0]; /* (ARM64Condcode << 4) | ARM64G_CC_OP_* */ -+ cc_dep1 = args[1]; -+ cc_dep2 = args[2]; -+ //cc_ndep = args[3]; -+ -+ /*---------------- SUB64 ----------------*/ -+ -+ /* 0, 1 */ -+ if (isU64(cond_n_op, (ARM64CondEQ << 4) | ARM64G_CC_OP_SUB64)) { -+ /* EQ after SUB --> test argL == argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpEQ64, cc_dep1, cc_dep2)); -+ } -+ if (isU64(cond_n_op, (ARM64CondNE << 4) | ARM64G_CC_OP_SUB64)) { -+ /* NE after SUB --> test argL != argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpNE64, cc_dep1, cc_dep2)); -+ } -+ -+ /* 2, 3 */ -+ if (isU64(cond_n_op, (ARM64CondCS << 4) | ARM64G_CC_OP_SUB64)) { -+ /* CS after SUB --> test argL >=u argR -+ --> test argR <=u argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64U, cc_dep2, cc_dep1)); -+ } -+ if (isU64(cond_n_op, (ARM64CondCC << 4) | ARM64G_CC_OP_SUB64)) { -+ /* CC after SUB --> test argL test argL <=u argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64U, cc_dep1, cc_dep2)); -+ } -+ if (isU64(cond_n_op, (ARM64CondHI << 4) | ARM64G_CC_OP_SUB64)) { -+ /* HI after SUB --> test argL >u argR -+ --> test argR test argL test argL >=s argR -+ --> test argR <=s argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64S, cc_dep2, cc_dep1)); -+ } -+ -+ /* 12, 13 */ -+ if (isU64(cond_n_op, (ARM64CondGT << 4) | ARM64G_CC_OP_SUB64)) { -+ /* GT after SUB --> test argL >s argR -+ --> test argR test argL <=s argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE64S, cc_dep1, cc_dep2)); -+ } -+ -+ /*---------------- SUB32 ----------------*/ -+ -+ /* 0, 1 */ -+ if (isU64(cond_n_op, (ARM64CondEQ << 4) | ARM64G_CC_OP_SUB32)) { -+ /* EQ after SUB --> test argL == argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpEQ32, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ if (isU64(cond_n_op, (ARM64CondNE << 4) | ARM64G_CC_OP_SUB32)) { -+ /* NE after SUB --> test argL != argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpNE32, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ -+ /* 2, 3 */ -+ if (isU64(cond_n_op, (ARM64CondCS << 4) | ARM64G_CC_OP_SUB32)) { -+ /* CS after SUB --> test argL >=u argR -+ --> test argR <=u argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32U, unop(Iop_64to32, cc_dep2), -+ unop(Iop_64to32, cc_dep1))); -+ } -+ if (isU64(cond_n_op, (ARM64CondCC << 4) | ARM64G_CC_OP_SUB32)) { -+ /* CC after SUB --> test argL test argL <=u argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32U, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ if (isU64(cond_n_op, (ARM64CondHI << 4) | ARM64G_CC_OP_SUB32)) { -+ /* HI after SUB --> test argL >u argR -+ --> test argR test argL test argL >=s argR -+ --> test argR <=s argL */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32S, unop(Iop_64to32, cc_dep2), -+ unop(Iop_64to32, cc_dep1))); -+ } -+ -+ /* 12, 13 */ -+ if (isU64(cond_n_op, (ARM64CondGT << 4) | ARM64G_CC_OP_SUB32)) { -+ /* GT after SUB --> test argL >s argR -+ --> test argR test argL <=s argR */ -+ return unop(Iop_1Uto64, -+ binop(Iop_CmpLE32S, unop(Iop_64to32, cc_dep1), -+ unop(Iop_64to32, cc_dep2))); -+ } -+ -+//ZZ /*---------------- SBB ----------------*/ -+//ZZ -+//ZZ if (isU32(cond_n_op, (ARMCondHS << 4) | ARMG_CC_OP_SBB)) { -+//ZZ /* This seems to happen a lot in softfloat code, eg __divdf3+140 */ -+//ZZ /* thunk is: (dep1=argL, dep2=argR, ndep=oldC) */ -+//ZZ /* HS after SBB (same as C after SBB below) -+//ZZ --> oldC ? (argL >=u argR) : (argL >u argR) -+//ZZ --> oldC ? (argR <=u argL) : (argR test res == 0 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpEQ32, cc_dep1, mkU32(0))); -+//ZZ } -+//ZZ if (isU32(cond_n_op, (ARMCondNE << 4) | ARMG_CC_OP_LOGIC)) { -+//ZZ /* NE after LOGIC --> test res != 0 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpNE32, cc_dep1, mkU32(0))); -+//ZZ } -+//ZZ -+//ZZ if (isU32(cond_n_op, (ARMCondPL << 4) | ARMG_CC_OP_LOGIC)) { -+//ZZ /* PL after LOGIC --> test (res >> 31) == 0 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpEQ32, -+//ZZ binop(Iop_Shr32, cc_dep1, mkU8(31)), -+//ZZ mkU32(0))); -+//ZZ } -+//ZZ if (isU32(cond_n_op, (ARMCondMI << 4) | ARMG_CC_OP_LOGIC)) { -+//ZZ /* MI after LOGIC --> test (res >> 31) == 1 */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpEQ32, -+//ZZ binop(Iop_Shr32, cc_dep1, mkU8(31)), -+//ZZ mkU32(1))); -+//ZZ } -+ -+ /*---------------- COPY ----------------*/ -+ -+ if (isU64(cond_n_op, (ARM64CondEQ << 4) | ARM64G_CC_OP_COPY)) { -+ /* EQ after COPY --> (cc_dep1 >> ARM64G_CC_SHIFT_Z) & 1 */ -+ return binop(Iop_And64, -+ binop(Iop_Shr64, cc_dep1, -+ mkU8(ARM64G_CC_SHIFT_Z)), -+ mkU64(1)); -+ } -+ if (isU64(cond_n_op, (ARM64CondNE << 4) | ARM64G_CC_OP_COPY)) { -+ /* NE after COPY --> ((cc_dep1 >> ARM64G_CC_SHIFT_Z) ^ 1) & 1 */ -+ return binop(Iop_And64, -+ binop(Iop_Xor64, -+ binop(Iop_Shr64, cc_dep1, -+ mkU8(ARM64G_CC_SHIFT_Z)), -+ mkU64(1)), -+ mkU64(1)); -+ } -+ -+//ZZ /*----------------- AL -----------------*/ -+//ZZ -+//ZZ /* A critically important case for Thumb code. -+//ZZ -+//ZZ What we're trying to spot is the case where cond_n_op is an -+//ZZ expression of the form Or32(..., 0xE0) since that means the -+//ZZ caller is asking for CondAL and we can simply return 1 -+//ZZ without caring what the ... part is. This is a potentially -+//ZZ dodgy kludge in that it assumes that the ... part has zeroes -+//ZZ in bits 7:4, so that the result of the Or32 is guaranteed to -+//ZZ be 0xE in bits 7:4. Given that the places where this first -+//ZZ arg are constructed (in guest_arm_toIR.c) are very -+//ZZ constrained, we can get away with this. To make this -+//ZZ guaranteed safe would require to have a new primop, Slice44 -+//ZZ or some such, thusly -+//ZZ -+//ZZ Slice44(arg1, arg2) = 0--(24)--0 arg1[7:4] arg2[3:0] -+//ZZ -+//ZZ and we would then look for Slice44(0xE0, ...) -+//ZZ which would give the required safety property. -+//ZZ -+//ZZ It would be infeasibly expensive to scan backwards through -+//ZZ the entire block looking for an assignment to the temp, so -+//ZZ just look at the previous 16 statements. That should find it -+//ZZ if it is an interesting case, as a result of how the -+//ZZ boilerplate guff at the start of each Thumb insn translation -+//ZZ is made. -+//ZZ */ -+//ZZ if (cond_n_op->tag == Iex_RdTmp) { -+//ZZ Int j; -+//ZZ IRTemp look_for = cond_n_op->Iex.RdTmp.tmp; -+//ZZ Int limit = n_precedingStmts - 16; -+//ZZ if (limit < 0) limit = 0; -+//ZZ if (0) vex_printf("scanning %d .. %d\n", n_precedingStmts-1, limit); -+//ZZ for (j = n_precedingStmts - 1; j >= limit; j--) { -+//ZZ IRStmt* st = precedingStmts[j]; -+//ZZ if (st->tag == Ist_WrTmp -+//ZZ && st->Ist.WrTmp.tmp == look_for -+//ZZ && st->Ist.WrTmp.data->tag == Iex_Binop -+//ZZ && st->Ist.WrTmp.data->Iex.Binop.op == Iop_Or32 -+//ZZ && isU32(st->Ist.WrTmp.data->Iex.Binop.arg2, (ARMCondAL << 4))) -+//ZZ return mkU32(1); -+//ZZ } -+//ZZ /* Didn't find any useful binding to the first arg -+//ZZ in the previous 16 stmts. */ -+//ZZ } -+ } -+ -+//ZZ /* --------- specialising "armg_calculate_flag_c" --------- */ -+//ZZ -+//ZZ else -+//ZZ if (vex_streq(function_name, "armg_calculate_flag_c")) { -+//ZZ -+//ZZ /* specialise calls to the "armg_calculate_flag_c" function. -+//ZZ Note that the returned value must be either 0 or 1; nonzero -+//ZZ bits 31:1 are not allowed. In turn, incoming oldV and oldC -+//ZZ values (from the thunk) are assumed to have bits 31:1 -+//ZZ clear. */ -+//ZZ IRExpr *cc_op, *cc_dep1, *cc_dep2, *cc_ndep; -+//ZZ vassert(arity == 4); -+//ZZ cc_op = args[0]; /* ARMG_CC_OP_* */ -+//ZZ cc_dep1 = args[1]; -+//ZZ cc_dep2 = args[2]; -+//ZZ cc_ndep = args[3]; -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_LOGIC)) { -+//ZZ /* Thunk args are (result, shco, oldV) */ -+//ZZ /* C after LOGIC --> shco */ -+//ZZ return cc_dep2; -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SUB)) { -+//ZZ /* Thunk args are (argL, argR, unused) */ -+//ZZ /* C after SUB --> argL >=u argR -+//ZZ --> argR <=u argL */ -+//ZZ return unop(Iop_1Uto32, -+//ZZ binop(Iop_CmpLE32U, cc_dep2, cc_dep1)); -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SBB)) { -+//ZZ /* This happens occasionally in softfloat code, eg __divdf3+140 */ -+//ZZ /* thunk is: (dep1=argL, dep2=argR, ndep=oldC) */ -+//ZZ /* C after SBB (same as HS after SBB above) -+//ZZ --> oldC ? (argL >=u argR) : (argL >u argR) -+//ZZ --> oldC ? (argR <=u argL) : (argR oldV */ -+//ZZ return cc_ndep; -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SUB)) { -+//ZZ /* Thunk args are (argL, argR, unused) */ -+//ZZ /* V after SUB -+//ZZ --> let res = argL - argR -+//ZZ in ((argL ^ argR) & (argL ^ res)) >> 31 -+//ZZ --> ((argL ^ argR) & (argL ^ (argL - argR))) >> 31 -+//ZZ */ -+//ZZ IRExpr* argL = cc_dep1; -+//ZZ IRExpr* argR = cc_dep2; -+//ZZ return -+//ZZ binop(Iop_Shr32, -+//ZZ binop(Iop_And32, -+//ZZ binop(Iop_Xor32, argL, argR), -+//ZZ binop(Iop_Xor32, argL, binop(Iop_Sub32, argL, argR)) -+//ZZ ), -+//ZZ mkU8(31) -+//ZZ ); -+//ZZ } -+//ZZ -+//ZZ if (isU32(cc_op, ARMG_CC_OP_SBB)) { -+//ZZ /* This happens occasionally in softfloat code, eg __divdf3+140 */ -+//ZZ /* thunk is: (dep1=argL, dep2=argR, ndep=oldC) */ -+//ZZ /* V after SBB -+//ZZ --> let res = argL - argR - (oldC ^ 1) -+//ZZ in (argL ^ argR) & (argL ^ res) & 1 -+//ZZ */ -+//ZZ return -+//ZZ binop( -+//ZZ Iop_And32, -+//ZZ binop( -+//ZZ Iop_And32, -+//ZZ // argL ^ argR -+//ZZ binop(Iop_Xor32, cc_dep1, cc_dep2), -+//ZZ // argL ^ (argL - argR - (oldC ^ 1)) -+//ZZ binop(Iop_Xor32, -+//ZZ cc_dep1, -+//ZZ binop(Iop_Sub32, -+//ZZ binop(Iop_Sub32, cc_dep1, cc_dep2), -+//ZZ binop(Iop_Xor32, cc_ndep, mkU32(1))) -+//ZZ ) -+//ZZ ), -+//ZZ mkU32(1) -+//ZZ ); -+//ZZ } -+//ZZ -+//ZZ } -+ -+# undef unop -+# undef binop -+# undef mkU64 -+# undef mkU8 -+ -+ return NULL; -+} -+ -+ -+/*----------------------------------------------*/ -+/*--- The exported fns .. ---*/ -+/*----------------------------------------------*/ -+ -+//ZZ /* VISIBLE TO LIBVEX CLIENT */ -+//ZZ #if 0 -+//ZZ void LibVEX_GuestARM_put_flags ( UInt flags_native, -+//ZZ /*OUT*/VexGuestARMState* vex_state ) -+//ZZ { -+//ZZ vassert(0); // FIXME -+//ZZ -+//ZZ /* Mask out everything except N Z V C. */ -+//ZZ flags_native -+//ZZ &= (ARMG_CC_MASK_N | ARMG_CC_MASK_Z | ARMG_CC_MASK_V | ARMG_CC_MASK_C); -+//ZZ -+//ZZ vex_state->guest_CC_OP = ARMG_CC_OP_COPY; -+//ZZ vex_state->guest_CC_DEP1 = flags_native; -+//ZZ vex_state->guest_CC_DEP2 = 0; -+//ZZ vex_state->guest_CC_NDEP = 0; -+//ZZ } -+//ZZ #endif -+ -+/* VISIBLE TO LIBVEX CLIENT */ -+ULong LibVEX_GuestARM64_get_nzcv ( /*IN*/const VexGuestARM64State* vex_state ) -+{ -+ ULong nzcv = 0; -+ // NZCV -+ nzcv |= arm64g_calculate_flags_nzcv( -+ vex_state->guest_CC_OP, -+ vex_state->guest_CC_DEP1, -+ vex_state->guest_CC_DEP2, -+ vex_state->guest_CC_NDEP -+ ); -+ vassert(0 == (nzcv & 0xFFFFFFFF0FFFFFFFULL)); -+//ZZ // Q -+//ZZ if (vex_state->guest_QFLAG32 > 0) -+//ZZ cpsr |= (1 << 27); -+//ZZ // GE -+//ZZ if (vex_state->guest_GEFLAG0 > 0) -+//ZZ cpsr |= (1 << 16); -+//ZZ if (vex_state->guest_GEFLAG1 > 0) -+//ZZ cpsr |= (1 << 17); -+//ZZ if (vex_state->guest_GEFLAG2 > 0) -+//ZZ cpsr |= (1 << 18); -+//ZZ if (vex_state->guest_GEFLAG3 > 0) -+//ZZ cpsr |= (1 << 19); -+//ZZ // M -+//ZZ cpsr |= (1 << 4); // 0b10000 means user-mode -+//ZZ // J,T J (bit 24) is zero by initialisation above -+//ZZ // T we copy from R15T[0] -+//ZZ if (vex_state->guest_R15T & 1) -+//ZZ cpsr |= (1 << 5); -+//ZZ // ITSTATE we punt on for the time being. Could compute it -+//ZZ // if needed though. -+//ZZ // E, endianness, 0 (littleendian) from initialisation above -+//ZZ // A,I,F disable some async exceptions. Not sure about these. -+//ZZ // Leave as zero for the time being. -+ return nzcv; -+} -+ -+/* VISIBLE TO LIBVEX CLIENT */ -+void LibVEX_GuestARM64_initialise ( /*OUT*/VexGuestARM64State* vex_state ) -+{ -+ vex_bzero(vex_state, sizeof(*vex_state)); -+//ZZ vex_state->host_EvC_FAILADDR = 0; -+//ZZ vex_state->host_EvC_COUNTER = 0; -+//ZZ -+//ZZ vex_state->guest_R0 = 0; -+//ZZ vex_state->guest_R1 = 0; -+//ZZ vex_state->guest_R2 = 0; -+//ZZ vex_state->guest_R3 = 0; -+//ZZ vex_state->guest_R4 = 0; -+//ZZ vex_state->guest_R5 = 0; -+//ZZ vex_state->guest_R6 = 0; -+//ZZ vex_state->guest_R7 = 0; -+//ZZ vex_state->guest_R8 = 0; -+//ZZ vex_state->guest_R9 = 0; -+//ZZ vex_state->guest_R10 = 0; -+//ZZ vex_state->guest_R11 = 0; -+//ZZ vex_state->guest_R12 = 0; -+//ZZ vex_state->guest_R13 = 0; -+//ZZ vex_state->guest_R14 = 0; -+//ZZ vex_state->guest_R15T = 0; /* NB: implies ARM mode */ -+//ZZ -+ vex_state->guest_CC_OP = ARM64G_CC_OP_COPY; -+//ZZ vex_state->guest_CC_DEP1 = 0; -+//ZZ vex_state->guest_CC_DEP2 = 0; -+//ZZ vex_state->guest_CC_NDEP = 0; -+//ZZ vex_state->guest_QFLAG32 = 0; -+//ZZ vex_state->guest_GEFLAG0 = 0; -+//ZZ vex_state->guest_GEFLAG1 = 0; -+//ZZ vex_state->guest_GEFLAG2 = 0; -+//ZZ vex_state->guest_GEFLAG3 = 0; -+//ZZ -+//ZZ vex_state->guest_EMNOTE = EmNote_NONE; -+//ZZ vex_state->guest_CMSTART = 0; -+//ZZ vex_state->guest_CMLEN = 0; -+//ZZ vex_state->guest_NRADDR = 0; -+//ZZ vex_state->guest_IP_AT_SYSCALL = 0; -+//ZZ -+//ZZ vex_state->guest_D0 = 0; -+//ZZ vex_state->guest_D1 = 0; -+//ZZ vex_state->guest_D2 = 0; -+//ZZ vex_state->guest_D3 = 0; -+//ZZ vex_state->guest_D4 = 0; -+//ZZ vex_state->guest_D5 = 0; -+//ZZ vex_state->guest_D6 = 0; -+//ZZ vex_state->guest_D7 = 0; -+//ZZ vex_state->guest_D8 = 0; -+//ZZ vex_state->guest_D9 = 0; -+//ZZ vex_state->guest_D10 = 0; -+//ZZ vex_state->guest_D11 = 0; -+//ZZ vex_state->guest_D12 = 0; -+//ZZ vex_state->guest_D13 = 0; -+//ZZ vex_state->guest_D14 = 0; -+//ZZ vex_state->guest_D15 = 0; -+//ZZ vex_state->guest_D16 = 0; -+//ZZ vex_state->guest_D17 = 0; -+//ZZ vex_state->guest_D18 = 0; -+//ZZ vex_state->guest_D19 = 0; -+//ZZ vex_state->guest_D20 = 0; -+//ZZ vex_state->guest_D21 = 0; -+//ZZ vex_state->guest_D22 = 0; -+//ZZ vex_state->guest_D23 = 0; -+//ZZ vex_state->guest_D24 = 0; -+//ZZ vex_state->guest_D25 = 0; -+//ZZ vex_state->guest_D26 = 0; -+//ZZ vex_state->guest_D27 = 0; -+//ZZ vex_state->guest_D28 = 0; -+//ZZ vex_state->guest_D29 = 0; -+//ZZ vex_state->guest_D30 = 0; -+//ZZ vex_state->guest_D31 = 0; -+//ZZ -+//ZZ /* ARM encoded; zero is the default as it happens (result flags -+//ZZ (NZCV) cleared, FZ disabled, round to nearest, non-vector mode, -+//ZZ all exns masked, all exn sticky bits cleared). */ -+//ZZ vex_state->guest_FPSCR = 0; -+//ZZ -+//ZZ vex_state->guest_TPIDRURO = 0; -+//ZZ -+//ZZ /* Not in a Thumb IT block. */ -+//ZZ vex_state->guest_ITSTATE = 0; -+//ZZ -+//ZZ vex_state->padding1 = 0; -+//ZZ vex_state->padding2 = 0; -+//ZZ vex_state->padding3 = 0; -+//ZZ vex_state->padding4 = 0; -+//ZZ vex_state->padding5 = 0; -+} -+ -+ -+/*-----------------------------------------------------------*/ -+/*--- Describing the arm guest state, for the benefit ---*/ -+/*--- of iropt and instrumenters. ---*/ -+/*-----------------------------------------------------------*/ -+ -+/* Figure out if any part of the guest state contained in minoff -+ .. maxoff requires precise memory exceptions. If in doubt return -+ True (but this generates significantly slower code). -+ -+ We enforce precise exns for guest SP, PC, 29(FP), 30(LR). -+ That might be overkill (for 29 and 30); I don't know. -+*/ -+Bool guest_arm64_state_requires_precise_mem_exns ( Int minoff, -+ Int maxoff) -+{ -+ Int xsp_min = offsetof(VexGuestARM64State, guest_XSP); -+ Int xsp_max = xsp_min + 8 - 1; -+ Int pc_min = offsetof(VexGuestARM64State, guest_PC); -+ Int pc_max = pc_min + 8 - 1; -+ -+ if (maxoff < xsp_min || minoff > xsp_max) { -+ /* no overlap with xsp */ -+ if (vex_control.iropt_register_updates == VexRegUpdSpAtMemAccess) -+ return False; // We only need to check stack pointer. -+ } else { -+ return True; -+ } -+ -+ if (maxoff < pc_min || minoff > pc_max) { -+ /* no overlap with pc */ -+ } else { -+ return True; -+ } -+ -+ /* Guessing that we need PX for FP, but I don't really know. */ -+ Int x29_min = offsetof(VexGuestARM64State, guest_X29); -+ Int x29_max = x29_min + 8 - 1; -+ -+ if (maxoff < x29_min || minoff > x29_max) { -+ /* no overlap with x29 */ -+ } else { -+ return True; -+ } -+ -+ /* Guessing that we need PX for LR, but I don't really know. */ -+ Int x30_min = offsetof(VexGuestARM64State, guest_X30); -+ Int x30_max = x30_min + 8 - 1; -+ -+ if (maxoff < x30_min || minoff > x30_max) { -+ /* no overlap with r30 */ -+ } else { -+ return True; -+ } -+ -+ return False; -+} -+ -+ -+#define ALWAYSDEFD(field) \ -+ { offsetof(VexGuestARM64State, field), \ -+ (sizeof ((VexGuestARM64State*)0)->field) } -+VexGuestLayout -+ arm64Guest_layout -+ = { -+ /* Total size of the guest state, in bytes. */ -+ .total_sizeB = sizeof(VexGuestARM64State), -+ -+ /* Describe the stack pointer. */ -+ .offset_SP = offsetof(VexGuestARM64State,guest_XSP), -+ .sizeof_SP = 8, -+ -+ /* Describe the instruction pointer. */ -+ .offset_IP = offsetof(VexGuestARM64State,guest_PC), -+ .sizeof_IP = 8, -+ -+ /* Describe any sections to be regarded by Memcheck as -+ 'always-defined'. */ -+ .n_alwaysDefd = 10, -+ -+ /* flags thunk: OP is always defd, whereas DEP1 and DEP2 -+ have to be tracked. See detailed comment in gdefs.h on -+ meaning of thunk fields. */ -+ .alwaysDefd -+ = { /* 0 */ ALWAYSDEFD(guest_PC), -+ /* 1 */ ALWAYSDEFD(guest_CC_OP), -+ /* 2 */ ALWAYSDEFD(guest_CC_NDEP), -+ /* 3 */ ALWAYSDEFD(guest_EMNOTE), -+ /* 4 */ ALWAYSDEFD(guest_CMSTART), -+ /* 5 */ ALWAYSDEFD(guest_CMLEN), -+ /* 6 */ ALWAYSDEFD(guest_NRADDR), -+ /* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL), -+ /* 8 */ ALWAYSDEFD(guest_FPCR), -+ /* 9 */ ALWAYSDEFD(guest_FPSR) -+ } -+ }; -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- end guest_arm64_helpers.c ---*/ -+/*---------------------------------------------------------------*/ -Index: priv/guest_arm64_toIR.c -=================================================================== ---- priv/guest_arm64_toIR.c (.../tags/VEX_3_9_0) (revision 0) -+++ priv/guest_arm64_toIR.c (.../trunk) (revision 2863) -@@ -0,0 +1,7856 @@ -+/* -*- mode: C; c-basic-offset: 3; -*- */ -+ -+/*--------------------------------------------------------------------*/ -+/*--- begin guest_arm64_toIR.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+//ZZ /* XXXX thumb to check: -+//ZZ that all cases where putIRegT writes r15, we generate a jump. -+//ZZ -+//ZZ All uses of newTemp assign to an IRTemp and not a UInt -+//ZZ -+//ZZ For all thumb loads and stores, including VFP ones, new-ITSTATE is -+//ZZ backed out before the memory op, and restored afterwards. This -+//ZZ needs to happen even after we go uncond. (and for sure it doesn't -+//ZZ happen for VFP loads/stores right now). -+//ZZ -+//ZZ VFP on thumb: check that we exclude all r13/r15 cases that we -+//ZZ should. -+//ZZ -+//ZZ XXXX thumb to do: improve the ITSTATE-zeroing optimisation by -+//ZZ taking into account the number of insns guarded by an IT. -+//ZZ -+//ZZ remove the nasty hack, in the spechelper, of looking for Or32(..., -+//ZZ 0xE0) in as the first arg to armg_calculate_condition, and instead -+//ZZ use Slice44 as specified in comments in the spechelper. -+//ZZ -+//ZZ add specialisations for armg_calculate_flag_c and _v, as they -+//ZZ are moderately often needed in Thumb code. -+//ZZ -+//ZZ Correctness: ITSTATE handling in Thumb SVCs is wrong. -+//ZZ -+//ZZ Correctness (obscure): in m_transtab, when invalidating code -+//ZZ address ranges, invalidate up to 18 bytes after the end of the -+//ZZ range. This is because the ITSTATE optimisation at the top of -+//ZZ _THUMB_WRK below analyses up to 18 bytes before the start of any -+//ZZ given instruction, and so might depend on the invalidated area. -+//ZZ */ -+//ZZ -+//ZZ /* Limitations, etc -+//ZZ -+//ZZ - pretty dodgy exception semantics for {LD,ST}Mxx and {LD,ST}RD. -+//ZZ These instructions are non-restartable in the case where the -+//ZZ transfer(s) fault. -+//ZZ -+//ZZ - SWP: the restart jump back is Ijk_Boring; it should be -+//ZZ Ijk_NoRedir but that's expensive. See comments on casLE() in -+//ZZ guest_x86_toIR.c. -+//ZZ */ -+ -+/* "Special" instructions. -+ -+ This instruction decoder can decode four special instructions -+ which mean nothing natively (are no-ops as far as regs/mem are -+ concerned) but have meaning for supporting Valgrind. A special -+ instruction is flagged by a 16-byte preamble: -+ -+ 93CC0D8C 93CC358C 93CCCD8C 93CCF58C -+ (ror x12, x12, #3; ror x12, x12, #13 -+ ror x12, x12, #51; ror x12, x12, #61) -+ -+ Following that, one of the following 3 are allowed -+ (standard interpretation in parentheses): -+ -+ AA0A014A (orr x10,x10,x10) X3 = client_request ( X4 ) -+ AA0B016B (orr x11,x11,x11) X3 = guest_NRADDR -+ AA0C018C (orr x12,x12,x12) branch-and-link-to-noredir X8 -+ AA090129 (orr x9,x9,x9) IR injection -+ -+ Any other bytes following the 16-byte preamble are illegal and -+ constitute a failure in instruction decoding. This all assumes -+ that the preamble will never occur except in specific code -+ fragments designed for Valgrind to catch. -+*/ -+ -+/* Translates ARM64 code to IR. */ -+ -+#include "libvex_basictypes.h" -+#include "libvex_ir.h" -+#include "libvex.h" -+#include "libvex_guest_arm64.h" -+ -+#include "main_util.h" -+#include "main_globals.h" -+#include "guest_generic_bb_to_IR.h" -+#include "guest_arm64_defs.h" -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Globals ---*/ -+/*------------------------------------------------------------*/ -+ -+/* These are set at the start of the translation of a instruction, so -+ that we don't have to pass them around endlessly. CONST means does -+ not change during translation of the instruction. -+*/ -+ -+/* CONST: is the host bigendian? We need to know this in order to do -+ sub-register accesses to the SIMD/FP registers correctly. */ -+static Bool host_is_bigendian; -+ -+/* CONST: The guest address for the instruction currently being -+ translated. */ -+static Addr64 guest_PC_curr_instr; -+ -+/* MOD: The IRSB* into which we're generating code. */ -+static IRSB* irsb; -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Debugging output ---*/ -+/*------------------------------------------------------------*/ -+ -+#define DIP(format, args...) \ -+ if (vex_traceflags & VEX_TRACE_FE) \ -+ vex_printf(format, ## args) -+ -+#define DIS(buf, format, args...) \ -+ if (vex_traceflags & VEX_TRACE_FE) \ -+ vex_sprintf(buf, format, ## args) -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helper bits and pieces for deconstructing the ---*/ -+/*--- arm insn stream. ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Do a little-endian load of a 32-bit word, regardless of the -+ endianness of the underlying host. */ -+static inline UInt getUIntLittleEndianly ( UChar* p ) -+{ -+ UInt w = 0; -+ w = (w << 8) | p[3]; -+ w = (w << 8) | p[2]; -+ w = (w << 8) | p[1]; -+ w = (w << 8) | p[0]; -+ return w; -+} -+ -+/* Sign extend a N-bit value up to 64 bits, by copying -+ bit N-1 into all higher positions. */ -+static ULong sx_to_64 ( ULong x, UInt n ) -+{ -+ vassert(n > 1 && n < 64); -+ Long r = (Long)x; -+ r = (r << (64-n)) >> (64-n); -+ return (ULong)r; -+} -+ -+//ZZ /* Do a little-endian load of a 16-bit word, regardless of the -+//ZZ endianness of the underlying host. */ -+//ZZ static inline UShort getUShortLittleEndianly ( UChar* p ) -+//ZZ { -+//ZZ UShort w = 0; -+//ZZ w = (w << 8) | p[1]; -+//ZZ w = (w << 8) | p[0]; -+//ZZ return w; -+//ZZ } -+//ZZ -+//ZZ static UInt ROR32 ( UInt x, UInt sh ) { -+//ZZ vassert(sh >= 0 && sh < 32); -+//ZZ if (sh == 0) -+//ZZ return x; -+//ZZ else -+//ZZ return (x << (32-sh)) | (x >> sh); -+//ZZ } -+//ZZ -+//ZZ static Int popcount32 ( UInt x ) -+//ZZ { -+//ZZ Int res = 0, i; -+//ZZ for (i = 0; i < 32; i++) { -+//ZZ res += (x & 1); -+//ZZ x >>= 1; -+//ZZ } -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ static UInt setbit32 ( UInt x, Int ix, UInt b ) -+//ZZ { -+//ZZ UInt mask = 1 << ix; -+//ZZ x &= ~mask; -+//ZZ x |= ((b << ix) & mask); -+//ZZ return x; -+//ZZ } -+ -+#define BITS2(_b1,_b0) \ -+ (((_b1) << 1) | (_b0)) -+ -+#define BITS3(_b2,_b1,_b0) \ -+ (((_b2) << 2) | ((_b1) << 1) | (_b0)) -+ -+#define BITS4(_b3,_b2,_b1,_b0) \ -+ (((_b3) << 3) | ((_b2) << 2) | ((_b1) << 1) | (_b0)) -+ -+#define BITS8(_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \ -+ | BITS4((_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS5(_b4,_b3,_b2,_b1,_b0) \ -+ (BITS8(0,0,0,(_b4),(_b3),(_b2),(_b1),(_b0))) -+#define BITS6(_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (BITS8(0,0,(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+#define BITS7(_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (BITS8(0,(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS9(_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (((_b8) << 8) \ -+ | BITS8((_b7),(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS10(_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (((_b9) << 9) | ((_b8) << 8) \ -+ | BITS8((_b7),(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0))) -+ -+#define BITS11(_b10,_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (((_b10) << 10) \ -+ | BITS10(_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0)) -+ -+#define BITS12(_b11, _b10,_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ -+ (((_b11) << 11) \ -+ | BITS11(_b10,_b9,_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0)) -+ -+// produces _uint[_bMax:_bMin] -+#define SLICE_UInt(_uint,_bMax,_bMin) \ -+ (( ((UInt)(_uint)) >> (_bMin)) \ -+ & (UInt)((1ULL << ((_bMax) - (_bMin) + 1)) - 1ULL)) -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helper bits and pieces for creating IR fragments. ---*/ -+/*------------------------------------------------------------*/ -+ -+static IRExpr* mkV128 ( UShort w ) -+{ -+ return IRExpr_Const(IRConst_V128(w)); -+} -+ -+static IRExpr* mkU64 ( ULong i ) -+{ -+ return IRExpr_Const(IRConst_U64(i)); -+} -+ -+static IRExpr* mkU32 ( UInt i ) -+{ -+ return IRExpr_Const(IRConst_U32(i)); -+} -+ -+static IRExpr* mkU8 ( UInt i ) -+{ -+ vassert(i < 256); -+ return IRExpr_Const(IRConst_U8( (UChar)i )); -+} -+ -+static IRExpr* mkexpr ( IRTemp tmp ) -+{ -+ return IRExpr_RdTmp(tmp); -+} -+ -+static IRExpr* unop ( IROp op, IRExpr* a ) -+{ -+ return IRExpr_Unop(op, a); -+} -+ -+static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) -+{ -+ return IRExpr_Binop(op, a1, a2); -+} -+ -+static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) -+{ -+ return IRExpr_Triop(op, a1, a2, a3); -+} -+ -+static IRExpr* loadLE ( IRType ty, IRExpr* addr ) -+{ -+ return IRExpr_Load(Iend_LE, ty, addr); -+} -+ -+/* Add a statement to the list held by "irbb". */ -+static void stmt ( IRStmt* st ) -+{ -+ addStmtToIRSB( irsb, st ); -+} -+ -+static void assign ( IRTemp dst, IRExpr* e ) -+{ -+ stmt( IRStmt_WrTmp(dst, e) ); -+} -+ -+static void storeLE ( IRExpr* addr, IRExpr* data ) -+{ -+ stmt( IRStmt_Store(Iend_LE, addr, data) ); -+} -+ -+//ZZ static void storeGuardedLE ( IRExpr* addr, IRExpr* data, IRTemp guardT ) -+//ZZ { -+//ZZ if (guardT == IRTemp_INVALID) { -+//ZZ /* unconditional */ -+//ZZ storeLE(addr, data); -+//ZZ } else { -+//ZZ stmt( IRStmt_StoreG(Iend_LE, addr, data, -+//ZZ binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0))) ); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void loadGuardedLE ( IRTemp dst, IRLoadGOp cvt, -+//ZZ IRExpr* addr, IRExpr* alt, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ if (guardT == IRTemp_INVALID) { -+//ZZ /* unconditional */ -+//ZZ IRExpr* loaded = NULL; -+//ZZ switch (cvt) { -+//ZZ case ILGop_Ident32: -+//ZZ loaded = loadLE(Ity_I32, addr); break; -+//ZZ case ILGop_8Uto32: -+//ZZ loaded = unop(Iop_8Uto32, loadLE(Ity_I8, addr)); break; -+//ZZ case ILGop_8Sto32: -+//ZZ loaded = unop(Iop_8Sto32, loadLE(Ity_I8, addr)); break; -+//ZZ case ILGop_16Uto32: -+//ZZ loaded = unop(Iop_16Uto32, loadLE(Ity_I16, addr)); break; -+//ZZ case ILGop_16Sto32: -+//ZZ loaded = unop(Iop_16Sto32, loadLE(Ity_I16, addr)); break; -+//ZZ default: -+//ZZ vassert(0); -+//ZZ } -+//ZZ vassert(loaded != NULL); -+//ZZ assign(dst, loaded); -+//ZZ } else { -+//ZZ /* Generate a guarded load into 'dst', but apply 'cvt' to the -+//ZZ loaded data before putting the data in 'dst'. If the load -+//ZZ does not take place, 'alt' is placed directly in 'dst'. */ -+//ZZ stmt( IRStmt_LoadG(Iend_LE, cvt, dst, addr, alt, -+//ZZ binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0))) ); -+//ZZ } -+//ZZ } -+ -+/* Generate a new temporary of the given type. */ -+static IRTemp newTemp ( IRType ty ) -+{ -+ vassert(isPlausibleIRType(ty)); -+ return newIRTemp( irsb->tyenv, ty ); -+} -+ -+//ZZ /* Produces a value in 0 .. 3, which is encoded as per the type -+//ZZ IRRoundingMode. */ -+//ZZ static IRExpr* /* :: Ity_I32 */ get_FAKE_roundingmode ( void ) -+//ZZ { -+//ZZ return mkU32(Irrm_NEAREST); -+//ZZ } -+//ZZ -+//ZZ /* Generate an expression for SRC rotated right by ROT. */ -+//ZZ static IRExpr* genROR32( IRTemp src, Int rot ) -+//ZZ { -+//ZZ vassert(rot >= 0 && rot < 32); -+//ZZ if (rot == 0) -+//ZZ return mkexpr(src); -+//ZZ return -+//ZZ binop(Iop_Or32, -+//ZZ binop(Iop_Shl32, mkexpr(src), mkU8(32 - rot)), -+//ZZ binop(Iop_Shr32, mkexpr(src), mkU8(rot))); -+//ZZ } -+//ZZ -+//ZZ static IRExpr* mkU128 ( ULong i ) -+//ZZ { -+//ZZ return binop(Iop_64HLtoV128, mkU64(i), mkU64(i)); -+//ZZ } -+//ZZ -+//ZZ /* Generate a 4-aligned version of the given expression if -+//ZZ the given condition is true. Else return it unchanged. */ -+//ZZ static IRExpr* align4if ( IRExpr* e, Bool b ) -+//ZZ { -+//ZZ if (b) -+//ZZ return binop(Iop_And32, e, mkU32(~3)); -+//ZZ else -+//ZZ return e; -+//ZZ } -+ -+/* Other IR construction helpers. */ -+static IROp mkAND ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_And32; -+ case Ity_I64: return Iop_And64; -+ default: vpanic("mkAND"); -+ } -+} -+ -+static IROp mkOR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Or32; -+ case Ity_I64: return Iop_Or64; -+ default: vpanic("mkOR"); -+ } -+} -+ -+static IROp mkXOR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Xor32; -+ case Ity_I64: return Iop_Xor64; -+ default: vpanic("mkXOR"); -+ } -+} -+ -+static IROp mkSHL ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Shl32; -+ case Ity_I64: return Iop_Shl64; -+ default: vpanic("mkSHL"); -+ } -+} -+ -+static IROp mkSHR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Shr32; -+ case Ity_I64: return Iop_Shr64; -+ default: vpanic("mkSHR"); -+ } -+} -+ -+static IROp mkSAR ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Sar32; -+ case Ity_I64: return Iop_Sar64; -+ default: vpanic("mkSAR"); -+ } -+} -+ -+static IROp mkNOT ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Not32; -+ case Ity_I64: return Iop_Not64; -+ default: vpanic("mkNOT"); -+ } -+} -+ -+static IROp mkADD ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Add32; -+ case Ity_I64: return Iop_Add64; -+ default: vpanic("mkADD"); -+ } -+} -+ -+static IROp mkSUB ( IRType ty ) { -+ switch (ty) { -+ case Ity_I32: return Iop_Sub32; -+ case Ity_I64: return Iop_Sub64; -+ default: vpanic("mkSUB"); -+ } -+} -+ -+static IROp mkADDF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_AddF32; -+ case Ity_F64: return Iop_AddF64; -+ default: vpanic("mkADDF"); -+ } -+} -+ -+static IROp mkSUBF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_SubF32; -+ case Ity_F64: return Iop_SubF64; -+ default: vpanic("mkSUBF"); -+ } -+} -+ -+static IROp mkMULF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_MulF32; -+ case Ity_F64: return Iop_MulF64; -+ default: vpanic("mkMULF"); -+ } -+} -+ -+static IROp mkDIVF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_DivF32; -+ case Ity_F64: return Iop_DivF64; -+ default: vpanic("mkMULF"); -+ } -+} -+ -+static IROp mkNEGF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_NegF32; -+ case Ity_F64: return Iop_NegF64; -+ default: vpanic("mkNEGF"); -+ } -+} -+ -+static IROp mkABSF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_AbsF32; -+ case Ity_F64: return Iop_AbsF64; -+ default: vpanic("mkNEGF"); -+ } -+} -+ -+static IROp mkSQRTF ( IRType ty ) { -+ switch (ty) { -+ case Ity_F32: return Iop_SqrtF32; -+ case Ity_F64: return Iop_SqrtF64; -+ default: vpanic("mkNEGF"); -+ } -+} -+ -+static IRExpr* mkU ( IRType ty, ULong imm ) { -+ switch (ty) { -+ case Ity_I32: return mkU32((UInt)(imm & 0xFFFFFFFFULL)); -+ case Ity_I64: return mkU64(imm); -+ default: vpanic("mkU"); -+ } -+} -+ -+/* Generate IR to create 'arg rotated right by imm', for sane values -+ of 'ty' and 'imm'. */ -+static IRTemp mathROR ( IRType ty, IRTemp arg, UInt imm ) -+{ -+ UInt w = 0; -+ if (ty == Ity_I64) { -+ w = 64; -+ } else { -+ vassert(ty == Ity_I32); -+ w = 32; -+ } -+ vassert(w != 0); -+ vassert(imm < w); -+ if (imm == 0) { -+ return arg; -+ } -+ IRTemp res = newTemp(ty); -+ assign(res, binop(mkOR(ty), -+ binop(mkSHL(ty), mkexpr(arg), mkU8(w - imm)), -+ binop(mkSHR(ty), mkexpr(arg), mkU8(imm)) )); -+ return res; -+} -+ -+/* Generate IR to set the returned temp to either all-zeroes or -+ all ones, as a copy of arg. */ -+static IRTemp mathREPLICATE ( IRType ty, IRTemp arg, UInt imm ) -+{ -+ UInt w = 0; -+ if (ty == Ity_I64) { -+ w = 64; -+ } else { -+ vassert(ty == Ity_I32); -+ w = 32; -+ } -+ vassert(w != 0); -+ vassert(imm < w); -+ IRTemp res = newTemp(ty); -+ assign(res, binop(mkSAR(ty), -+ binop(mkSHL(ty), mkexpr(arg), mkU8(w - 1 - imm)), -+ mkU8(w - 1))); -+ return res; -+} -+ -+/* U-widen 8/16/32/64 bit int expr to 64. */ -+static IRExpr* widenUto64 ( IRType srcTy, IRExpr* e ) -+{ -+ switch (srcTy) { -+ case Ity_I64: return e; -+ case Ity_I32: return unop(Iop_32Uto64, e); -+ case Ity_I16: return unop(Iop_16Uto64, e); -+ case Ity_I8: return unop(Iop_8Uto64, e); -+ default: vpanic("widenUto64(arm64)"); -+ } -+} -+ -+/* Narrow 64 bit int expr to 8/16/32/64. Clearly only some -+ of these combinations make sense. */ -+static IRExpr* narrowFrom64 ( IRType dstTy, IRExpr* e ) -+{ -+ switch (dstTy) { -+ case Ity_I64: return e; -+ case Ity_I32: return unop(Iop_64to32, e); -+ case Ity_I16: return unop(Iop_64to16, e); -+ case Ity_I8: return unop(Iop_64to8, e); -+ default: vpanic("narrowFrom64(arm64)"); -+ } -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helpers for accessing guest registers. ---*/ -+/*------------------------------------------------------------*/ -+ -+#define OFFB_X0 offsetof(VexGuestARM64State,guest_X0) -+#define OFFB_X1 offsetof(VexGuestARM64State,guest_X1) -+#define OFFB_X2 offsetof(VexGuestARM64State,guest_X2) -+#define OFFB_X3 offsetof(VexGuestARM64State,guest_X3) -+#define OFFB_X4 offsetof(VexGuestARM64State,guest_X4) -+#define OFFB_X5 offsetof(VexGuestARM64State,guest_X5) -+#define OFFB_X6 offsetof(VexGuestARM64State,guest_X6) -+#define OFFB_X7 offsetof(VexGuestARM64State,guest_X7) -+#define OFFB_X8 offsetof(VexGuestARM64State,guest_X8) -+#define OFFB_X9 offsetof(VexGuestARM64State,guest_X9) -+#define OFFB_X10 offsetof(VexGuestARM64State,guest_X10) -+#define OFFB_X11 offsetof(VexGuestARM64State,guest_X11) -+#define OFFB_X12 offsetof(VexGuestARM64State,guest_X12) -+#define OFFB_X13 offsetof(VexGuestARM64State,guest_X13) -+#define OFFB_X14 offsetof(VexGuestARM64State,guest_X14) -+#define OFFB_X15 offsetof(VexGuestARM64State,guest_X15) -+#define OFFB_X16 offsetof(VexGuestARM64State,guest_X16) -+#define OFFB_X17 offsetof(VexGuestARM64State,guest_X17) -+#define OFFB_X18 offsetof(VexGuestARM64State,guest_X18) -+#define OFFB_X19 offsetof(VexGuestARM64State,guest_X19) -+#define OFFB_X20 offsetof(VexGuestARM64State,guest_X20) -+#define OFFB_X21 offsetof(VexGuestARM64State,guest_X21) -+#define OFFB_X22 offsetof(VexGuestARM64State,guest_X22) -+#define OFFB_X23 offsetof(VexGuestARM64State,guest_X23) -+#define OFFB_X24 offsetof(VexGuestARM64State,guest_X24) -+#define OFFB_X25 offsetof(VexGuestARM64State,guest_X25) -+#define OFFB_X26 offsetof(VexGuestARM64State,guest_X26) -+#define OFFB_X27 offsetof(VexGuestARM64State,guest_X27) -+#define OFFB_X28 offsetof(VexGuestARM64State,guest_X28) -+#define OFFB_X29 offsetof(VexGuestARM64State,guest_X29) -+#define OFFB_X30 offsetof(VexGuestARM64State,guest_X30) -+ -+#define OFFB_XSP offsetof(VexGuestARM64State,guest_XSP) -+#define OFFB_PC offsetof(VexGuestARM64State,guest_PC) -+ -+#define OFFB_CC_OP offsetof(VexGuestARM64State,guest_CC_OP) -+#define OFFB_CC_DEP1 offsetof(VexGuestARM64State,guest_CC_DEP1) -+#define OFFB_CC_DEP2 offsetof(VexGuestARM64State,guest_CC_DEP2) -+#define OFFB_CC_NDEP offsetof(VexGuestARM64State,guest_CC_NDEP) -+ -+#define OFFB_TPIDR_EL0 offsetof(VexGuestARM64State,guest_TPIDR_EL0) -+#define OFFB_NRADDR offsetof(VexGuestARM64State,guest_NRADDR) -+ -+#define OFFB_Q0 offsetof(VexGuestARM64State,guest_Q0) -+#define OFFB_Q1 offsetof(VexGuestARM64State,guest_Q1) -+#define OFFB_Q2 offsetof(VexGuestARM64State,guest_Q2) -+#define OFFB_Q3 offsetof(VexGuestARM64State,guest_Q3) -+#define OFFB_Q4 offsetof(VexGuestARM64State,guest_Q4) -+#define OFFB_Q5 offsetof(VexGuestARM64State,guest_Q5) -+#define OFFB_Q6 offsetof(VexGuestARM64State,guest_Q6) -+#define OFFB_Q7 offsetof(VexGuestARM64State,guest_Q7) -+#define OFFB_Q8 offsetof(VexGuestARM64State,guest_Q8) -+#define OFFB_Q9 offsetof(VexGuestARM64State,guest_Q9) -+#define OFFB_Q10 offsetof(VexGuestARM64State,guest_Q10) -+#define OFFB_Q11 offsetof(VexGuestARM64State,guest_Q11) -+#define OFFB_Q12 offsetof(VexGuestARM64State,guest_Q12) -+#define OFFB_Q13 offsetof(VexGuestARM64State,guest_Q13) -+#define OFFB_Q14 offsetof(VexGuestARM64State,guest_Q14) -+#define OFFB_Q15 offsetof(VexGuestARM64State,guest_Q15) -+#define OFFB_Q16 offsetof(VexGuestARM64State,guest_Q16) -+#define OFFB_Q17 offsetof(VexGuestARM64State,guest_Q17) -+#define OFFB_Q18 offsetof(VexGuestARM64State,guest_Q18) -+#define OFFB_Q19 offsetof(VexGuestARM64State,guest_Q19) -+#define OFFB_Q20 offsetof(VexGuestARM64State,guest_Q20) -+#define OFFB_Q21 offsetof(VexGuestARM64State,guest_Q21) -+#define OFFB_Q22 offsetof(VexGuestARM64State,guest_Q22) -+#define OFFB_Q23 offsetof(VexGuestARM64State,guest_Q23) -+#define OFFB_Q24 offsetof(VexGuestARM64State,guest_Q24) -+#define OFFB_Q25 offsetof(VexGuestARM64State,guest_Q25) -+#define OFFB_Q26 offsetof(VexGuestARM64State,guest_Q26) -+#define OFFB_Q27 offsetof(VexGuestARM64State,guest_Q27) -+#define OFFB_Q28 offsetof(VexGuestARM64State,guest_Q28) -+#define OFFB_Q29 offsetof(VexGuestARM64State,guest_Q29) -+#define OFFB_Q30 offsetof(VexGuestARM64State,guest_Q30) -+#define OFFB_Q31 offsetof(VexGuestARM64State,guest_Q31) -+ -+#define OFFB_FPCR offsetof(VexGuestARM64State,guest_FPCR) -+#define OFFB_FPSR offsetof(VexGuestARM64State,guest_FPSR) -+//ZZ #define OFFB_TPIDRURO offsetof(VexGuestARMState,guest_TPIDRURO) -+//ZZ #define OFFB_ITSTATE offsetof(VexGuestARMState,guest_ITSTATE) -+//ZZ #define OFFB_QFLAG32 offsetof(VexGuestARMState,guest_QFLAG32) -+//ZZ #define OFFB_GEFLAG0 offsetof(VexGuestARMState,guest_GEFLAG0) -+//ZZ #define OFFB_GEFLAG1 offsetof(VexGuestARMState,guest_GEFLAG1) -+//ZZ #define OFFB_GEFLAG2 offsetof(VexGuestARMState,guest_GEFLAG2) -+//ZZ #define OFFB_GEFLAG3 offsetof(VexGuestARMState,guest_GEFLAG3) -+ -+#define OFFB_CMSTART offsetof(VexGuestARM64State,guest_CMSTART) -+#define OFFB_CMLEN offsetof(VexGuestARM64State,guest_CMLEN) -+ -+ -+/* ---------------- Integer registers ---------------- */ -+ -+static Int offsetIReg64 ( UInt iregNo ) -+{ -+ /* Do we care about endianness here? We do if sub-parts of integer -+ registers are accessed. */ -+ switch (iregNo) { -+ case 0: return OFFB_X0; -+ case 1: return OFFB_X1; -+ case 2: return OFFB_X2; -+ case 3: return OFFB_X3; -+ case 4: return OFFB_X4; -+ case 5: return OFFB_X5; -+ case 6: return OFFB_X6; -+ case 7: return OFFB_X7; -+ case 8: return OFFB_X8; -+ case 9: return OFFB_X9; -+ case 10: return OFFB_X10; -+ case 11: return OFFB_X11; -+ case 12: return OFFB_X12; -+ case 13: return OFFB_X13; -+ case 14: return OFFB_X14; -+ case 15: return OFFB_X15; -+ case 16: return OFFB_X16; -+ case 17: return OFFB_X17; -+ case 18: return OFFB_X18; -+ case 19: return OFFB_X19; -+ case 20: return OFFB_X20; -+ case 21: return OFFB_X21; -+ case 22: return OFFB_X22; -+ case 23: return OFFB_X23; -+ case 24: return OFFB_X24; -+ case 25: return OFFB_X25; -+ case 26: return OFFB_X26; -+ case 27: return OFFB_X27; -+ case 28: return OFFB_X28; -+ case 29: return OFFB_X29; -+ case 30: return OFFB_X30; -+ /* but not 31 */ -+ default: vassert(0); -+ } -+} -+ -+static Int offsetIReg64orSP ( UInt iregNo ) -+{ -+ return iregNo == 31 ? OFFB_XSP : offsetIReg64(iregNo); -+} -+ -+static const HChar* nameIReg64orZR ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ static const HChar* names[32] -+ = { "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", -+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", -+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", -+ "x24", "x25", "x26", "x27", "x28", "x29", "x30", "xzr" }; -+ return names[iregNo]; -+} -+ -+static const HChar* nameIReg64orSP ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return "sp"; -+ } -+ vassert(iregNo < 31); -+ return nameIReg64orZR(iregNo); -+} -+ -+static IRExpr* getIReg64orSP ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ return IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 ); -+} -+ -+static IRExpr* getIReg64orZR ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return mkU64(0); -+ } -+ vassert(iregNo < 31); -+ return IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 ); -+} -+ -+static void putIReg64orSP ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), e) ); -+} -+ -+static void putIReg64orZR ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); -+ if (iregNo == 31) { -+ return; -+ } -+ vassert(iregNo < 31); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), e) ); -+} -+ -+static const HChar* nameIReg32orZR ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ static const HChar* names[32] -+ = { "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", -+ "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", -+ "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", -+ "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr" }; -+ return names[iregNo]; -+} -+ -+static const HChar* nameIReg32orSP ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return "wsp"; -+ } -+ vassert(iregNo < 31); -+ return nameIReg32orZR(iregNo); -+} -+ -+static IRExpr* getIReg32orSP ( UInt iregNo ) -+{ -+ vassert(iregNo < 32); -+ return unop(Iop_64to32, -+ IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 )); -+} -+ -+static IRExpr* getIReg32orZR ( UInt iregNo ) -+{ -+ if (iregNo == 31) { -+ return mkU32(0); -+ } -+ vassert(iregNo < 31); -+ return unop(Iop_64to32, -+ IRExpr_Get( offsetIReg64orSP(iregNo), Ity_I64 )); -+} -+ -+static void putIReg32orSP ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), unop(Iop_32Uto64, e)) ); -+} -+ -+static void putIReg32orZR ( UInt iregNo, IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); -+ if (iregNo == 31) { -+ return; -+ } -+ vassert(iregNo < 31); -+ stmt( IRStmt_Put(offsetIReg64orSP(iregNo), unop(Iop_32Uto64, e)) ); -+} -+ -+static const HChar* nameIRegOrSP ( Bool is64, UInt iregNo ) -+{ -+ vassert(is64 == True || is64 == False); -+ return is64 ? nameIReg64orSP(iregNo) : nameIReg32orSP(iregNo); -+} -+ -+static const HChar* nameIRegOrZR ( Bool is64, UInt iregNo ) -+{ -+ vassert(is64 == True || is64 == False); -+ return is64 ? nameIReg64orZR(iregNo) : nameIReg32orZR(iregNo); -+} -+ -+static IRExpr* getIRegOrZR ( Bool is64, UInt iregNo ) -+{ -+ vassert(is64 == True || is64 == False); -+ return is64 ? getIReg64orZR(iregNo) : getIReg32orZR(iregNo); -+} -+ -+static void putIRegOrZR ( Bool is64, UInt iregNo, IRExpr* e ) -+{ -+ vassert(is64 == True || is64 == False); -+ if (is64) putIReg64orZR(iregNo, e); else putIReg32orZR(iregNo, e); -+} -+ -+static void putPC ( IRExpr* e ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64); -+ stmt( IRStmt_Put(OFFB_PC, e) ); -+} -+ -+ -+/* ---------------- Vector (Q) registers ---------------- */ -+ -+static Int offsetQReg128 ( UInt qregNo ) -+{ -+ /* We don't care about endianness at this point. It only becomes -+ relevant when dealing with sections of these registers.*/ -+ switch (qregNo) { -+ case 0: return OFFB_Q0; -+ case 1: return OFFB_Q1; -+ case 2: return OFFB_Q2; -+ case 3: return OFFB_Q3; -+ case 4: return OFFB_Q4; -+ case 5: return OFFB_Q5; -+ case 6: return OFFB_Q6; -+ case 7: return OFFB_Q7; -+ case 8: return OFFB_Q8; -+ case 9: return OFFB_Q9; -+ case 10: return OFFB_Q10; -+ case 11: return OFFB_Q11; -+ case 12: return OFFB_Q12; -+ case 13: return OFFB_Q13; -+ case 14: return OFFB_Q14; -+ case 15: return OFFB_Q15; -+ case 16: return OFFB_Q16; -+ case 17: return OFFB_Q17; -+ case 18: return OFFB_Q18; -+ case 19: return OFFB_Q19; -+ case 20: return OFFB_Q20; -+ case 21: return OFFB_Q21; -+ case 22: return OFFB_Q22; -+ case 23: return OFFB_Q23; -+ case 24: return OFFB_Q24; -+ case 25: return OFFB_Q25; -+ case 26: return OFFB_Q26; -+ case 27: return OFFB_Q27; -+ case 28: return OFFB_Q28; -+ case 29: return OFFB_Q29; -+ case 30: return OFFB_Q30; -+ case 31: return OFFB_Q31; -+ default: vassert(0); -+ } -+} -+ -+/* Write to a complete Qreg. */ -+static void putQReg128 ( UInt qregNo, IRExpr* e ) -+{ -+ vassert(qregNo < 32); -+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128); -+ stmt( IRStmt_Put(offsetQReg128(qregNo), e) ); -+} -+ -+/* Read a complete Qreg. */ -+static IRExpr* getQReg128 ( UInt qregNo ) -+{ -+ vassert(qregNo < 32); -+ return IRExpr_Get(offsetQReg128(qregNo), Ity_V128); -+} -+ -+/* Produce the IR type for some sub-part of a vector. For 32- and 64- -+ bit sub-parts we can choose either integer or float types, and -+ choose float on the basis that that is the common use case and so -+ will give least interference with Put-to-Get forwarding later -+ on. */ -+static IRType preferredVectorSubTypeFromSize ( UInt szB ) -+{ -+ switch (szB) { -+ case 1: return Ity_I8; -+ case 2: return Ity_I16; -+ case 4: return Ity_I32; //Ity_F32; -+ case 8: return Ity_F64; -+ case 16: return Ity_V128; -+ default: vassert(0); -+ } -+} -+ -+/* Find the offset of the laneNo'th lane of type laneTy in the given -+ Qreg. Since the host is little-endian, the least significant lane -+ has the lowest offset. */ -+static Int offsetQRegLane ( UInt qregNo, IRType laneTy, UInt laneNo ) -+{ -+ vassert(!host_is_bigendian); -+ Int base = offsetQReg128(qregNo); -+ /* Since the host is little-endian, the least significant lane -+ will be at the lowest address. */ -+ /* Restrict this to known types, so as to avoid silently accepting -+ stupid types. */ -+ UInt laneSzB = 0; -+ switch (laneTy) { -+ case Ity_I8: laneSzB = 1; break; -+ case Ity_I16: laneSzB = 2; break; -+ case Ity_F32: case Ity_I32: laneSzB = 4; break; -+ case Ity_F64: case Ity_I64: laneSzB = 8; break; -+ case Ity_V128: laneSzB = 16; break; -+ default: break; -+ } -+ vassert(laneSzB > 0); -+ UInt minOff = laneNo * laneSzB; -+ UInt maxOff = minOff + laneSzB - 1; -+ vassert(maxOff < 16); -+ return base + minOff; -+} -+ -+/* Put to the least significant lane of a Qreg. */ -+static void putQRegLO ( UInt qregNo, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(irsb->tyenv, e); -+ Int off = offsetQRegLane(qregNo, ty, 0); -+ switch (ty) { -+ case Ity_I8: case Ity_I16: case Ity_I32: case Ity_I64: -+ case Ity_F32: case Ity_F64: case Ity_V128: -+ break; -+ default: -+ vassert(0); // Other cases are probably invalid -+ } -+ stmt(IRStmt_Put(off, e)); -+} -+ -+/* Get from the least significant lane of a Qreg. */ -+static IRExpr* getQRegLO ( UInt qregNo, IRType ty ) -+{ -+ Int off = offsetQRegLane(qregNo, ty, 0); -+ switch (ty) { -+ case Ity_I8: -+ case Ity_I16: -+ case Ity_I32: case Ity_I64: -+ case Ity_F32: case Ity_F64: case Ity_V128: -+ break; -+ default: -+ vassert(0); // Other cases are ATC -+ } -+ return IRExpr_Get(off, ty); -+} -+ -+static const HChar* nameQRegLO ( UInt qregNo, IRType laneTy ) -+{ -+ static const HChar* namesQ[32] -+ = { "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", -+ "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", -+ "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", -+ "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" }; -+ static const HChar* namesD[32] -+ = { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", -+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", -+ "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", -+ "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31" }; -+ static const HChar* namesS[32] -+ = { "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", -+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", -+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", -+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31" }; -+ static const HChar* namesH[32] -+ = { "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", -+ "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", -+ "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", -+ "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31" }; -+ static const HChar* namesB[32] -+ = { "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", -+ "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", -+ "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", -+ "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31" }; -+ vassert(qregNo < 32); -+ switch (sizeofIRType(laneTy)) { -+ case 1: return namesB[qregNo]; -+ case 2: return namesH[qregNo]; -+ case 4: return namesS[qregNo]; -+ case 8: return namesD[qregNo]; -+ case 16: return namesQ[qregNo]; -+ default: vassert(0); -+ } -+ /*NOTREACHED*/ -+} -+ -+static const HChar* nameQReg128 ( UInt qregNo ) -+{ -+ return nameQRegLO(qregNo, Ity_V128); -+} -+ -+/* Find the offset of the most significant half (8 bytes) of the given -+ Qreg. This requires knowing the endianness of the host. */ -+static Int offsetQRegHI64 ( UInt qregNo ) -+{ -+ return offsetQRegLane(qregNo, Ity_I64, 1); -+} -+ -+static IRExpr* getQRegHI64 ( UInt qregNo ) -+{ -+ return IRExpr_Get(offsetQRegHI64(qregNo), Ity_I64); -+} -+ -+static void putQRegHI64 ( UInt qregNo, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(irsb->tyenv, e); -+ Int off = offsetQRegHI64(qregNo); -+ switch (ty) { -+ case Ity_I64: case Ity_F64: -+ break; -+ default: -+ vassert(0); // Other cases are plain wrong -+ } -+ stmt(IRStmt_Put(off, e)); -+} -+ -+/* Put to a specified lane of a Qreg. */ -+static void putQRegLane ( UInt qregNo, UInt laneNo, IRExpr* e ) -+{ -+ IRType laneTy = typeOfIRExpr(irsb->tyenv, e); -+ Int off = offsetQRegLane(qregNo, laneTy, laneNo); -+ switch (laneTy) { -+ case Ity_F64: case Ity_I64: -+ case Ity_I32: case Ity_F32: -+ case Ity_I16: -+ case Ity_I8: -+ break; -+ default: -+ vassert(0); // Other cases are ATC -+ } -+ stmt(IRStmt_Put(off, e)); -+} -+ -+/* Get from a specified lane of a Qreg. */ -+static IRExpr* getQRegLane ( UInt qregNo, UInt laneNo, IRType laneTy ) -+{ -+ Int off = offsetQRegLane(qregNo, laneTy, laneNo); -+ switch (laneTy) { -+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: -+ case Ity_F64: -+ break; -+ default: -+ vassert(0); // Other cases are ATC -+ } -+ return IRExpr_Get(off, laneTy); -+} -+ -+ -+//ZZ /* ---------------- Misc registers ---------------- */ -+//ZZ -+//ZZ static void putMiscReg32 ( UInt gsoffset, -+//ZZ IRExpr* e, /* :: Ity_I32 */ -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */) -+//ZZ { -+//ZZ switch (gsoffset) { -+//ZZ case OFFB_FPSCR: break; -+//ZZ case OFFB_QFLAG32: break; -+//ZZ case OFFB_GEFLAG0: break; -+//ZZ case OFFB_GEFLAG1: break; -+//ZZ case OFFB_GEFLAG2: break; -+//ZZ case OFFB_GEFLAG3: break; -+//ZZ default: vassert(0); /* awaiting more cases */ -+//ZZ } -+//ZZ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32); -+//ZZ -+//ZZ if (guardT == IRTemp_INVALID) { -+//ZZ /* unconditional write */ -+//ZZ stmt(IRStmt_Put(gsoffset, e)); -+//ZZ } else { -+//ZZ stmt(IRStmt_Put( -+//ZZ gsoffset, -+//ZZ IRExpr_ITE( binop(Iop_CmpNE32, mkexpr(guardT), mkU32(0)), -+//ZZ e, IRExpr_Get(gsoffset, Ity_I32) ) -+//ZZ )); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static IRTemp get_ITSTATE ( void ) -+//ZZ { -+//ZZ ASSERT_IS_THUMB; -+//ZZ IRTemp t = newTemp(Ity_I32); -+//ZZ assign(t, IRExpr_Get( OFFB_ITSTATE, Ity_I32)); -+//ZZ return t; -+//ZZ } -+//ZZ -+//ZZ static void put_ITSTATE ( IRTemp t ) -+//ZZ { -+//ZZ ASSERT_IS_THUMB; -+//ZZ stmt( IRStmt_Put( OFFB_ITSTATE, mkexpr(t)) ); -+//ZZ } -+//ZZ -+//ZZ static IRTemp get_QFLAG32 ( void ) -+//ZZ { -+//ZZ IRTemp t = newTemp(Ity_I32); -+//ZZ assign(t, IRExpr_Get( OFFB_QFLAG32, Ity_I32)); -+//ZZ return t; -+//ZZ } -+//ZZ -+//ZZ static void put_QFLAG32 ( IRTemp t, IRTemp condT ) -+//ZZ { -+//ZZ putMiscReg32( OFFB_QFLAG32, mkexpr(t), condT ); -+//ZZ } -+//ZZ -+//ZZ /* Stickily set the 'Q' flag (APSR bit 27) of the APSR (Application Program -+//ZZ Status Register) to indicate that overflow or saturation occurred. -+//ZZ Nb: t must be zero to denote no saturation, and any nonzero -+//ZZ value to indicate saturation. */ -+//ZZ static void or_into_QFLAG32 ( IRExpr* e, IRTemp condT ) -+//ZZ { -+//ZZ IRTemp old = get_QFLAG32(); -+//ZZ IRTemp nyu = newTemp(Ity_I32); -+//ZZ assign(nyu, binop(Iop_Or32, mkexpr(old), e) ); -+//ZZ put_QFLAG32(nyu, condT); -+//ZZ } -+ -+ -+/* ---------------- FPCR stuff ---------------- */ -+ -+/* Generate IR to get hold of the rounding mode bits in FPCR, and -+ convert them to IR format. Bind the final result to the -+ returned temp. */ -+static IRTemp /* :: Ity_I32 */ mk_get_IR_rounding_mode ( void ) -+{ -+ /* The ARMvfp encoding for rounding mode bits is: -+ 00 to nearest -+ 01 to +infinity -+ 10 to -infinity -+ 11 to zero -+ We need to convert that to the IR encoding: -+ 00 to nearest (the default) -+ 10 to +infinity -+ 01 to -infinity -+ 11 to zero -+ Which can be done by swapping bits 0 and 1. -+ The rmode bits are at 23:22 in FPSCR. -+ */ -+ IRTemp armEncd = newTemp(Ity_I32); -+ IRTemp swapped = newTemp(Ity_I32); -+ /* Fish FPCR[23:22] out, and slide to bottom. Doesn't matter that -+ we don't zero out bits 24 and above, since the assignment to -+ 'swapped' will mask them out anyway. */ -+ assign(armEncd, -+ binop(Iop_Shr32, IRExpr_Get(OFFB_FPCR, Ity_I32), mkU8(22))); -+ /* Now swap them. */ -+ assign(swapped, -+ binop(Iop_Or32, -+ binop(Iop_And32, -+ binop(Iop_Shl32, mkexpr(armEncd), mkU8(1)), -+ mkU32(2)), -+ binop(Iop_And32, -+ binop(Iop_Shr32, mkexpr(armEncd), mkU8(1)), -+ mkU32(1)) -+ )); -+ return swapped; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Helpers for flag handling and conditional insns ---*/ -+/*------------------------------------------------------------*/ -+ -+static const HChar* nameARM64Condcode ( ARM64Condcode cond ) -+{ -+ switch (cond) { -+ case ARM64CondEQ: return "eq"; -+ case ARM64CondNE: return "ne"; -+ case ARM64CondCS: return "cs"; // or 'hs' -+ case ARM64CondCC: return "cc"; // or 'lo' -+ case ARM64CondMI: return "mi"; -+ case ARM64CondPL: return "pl"; -+ case ARM64CondVS: return "vs"; -+ case ARM64CondVC: return "vc"; -+ case ARM64CondHI: return "hi"; -+ case ARM64CondLS: return "ls"; -+ case ARM64CondGE: return "ge"; -+ case ARM64CondLT: return "lt"; -+ case ARM64CondGT: return "gt"; -+ case ARM64CondLE: return "le"; -+ case ARM64CondAL: return "al"; -+ case ARM64CondNV: return "nv"; -+ default: vpanic("name_ARM64Condcode"); -+ } -+} -+ -+/* and a handy shorthand for it */ -+static const HChar* nameCC ( ARM64Condcode cond ) { -+ return nameARM64Condcode(cond); -+} -+ -+ -+/* Build IR to calculate some particular condition from stored -+ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression of type -+ Ity_I64, suitable for narrowing. Although the return type is -+ Ity_I64, the returned value is either 0 or 1. 'cond' must be -+ :: Ity_I64 and must denote the condition to compute in -+ bits 7:4, and be zero everywhere else. -+*/ -+static IRExpr* mk_arm64g_calculate_condition_dyn ( IRExpr* cond ) -+{ -+ vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I64); -+ /* And 'cond' had better produce a value in which only bits 7:4 are -+ nonzero. However, obviously we can't assert for that. */ -+ -+ /* So what we're constructing for the first argument is -+ "(cond << 4) | stored-operation". -+ However, as per comments above, 'cond' must be supplied -+ pre-shifted to this function. -+ -+ This pairing scheme requires that the ARM64_CC_OP_ values all fit -+ in 4 bits. Hence we are passing a (COND, OP) pair in the lowest -+ 8 bits of the first argument. */ -+ IRExpr** args -+ = mkIRExprVec_4( -+ binop(Iop_Or64, IRExpr_Get(OFFB_CC_OP, Ity_I64), cond), -+ IRExpr_Get(OFFB_CC_DEP1, Ity_I64), -+ IRExpr_Get(OFFB_CC_DEP2, Ity_I64), -+ IRExpr_Get(OFFB_CC_NDEP, Ity_I64) -+ ); -+ IRExpr* call -+ = mkIRExprCCall( -+ Ity_I64, -+ 0/*regparm*/, -+ "arm64g_calculate_condition", &arm64g_calculate_condition, -+ args -+ ); -+ -+ /* Exclude the requested condition, OP and NDEP from definedness -+ checking. We're only interested in DEP1 and DEP2. */ -+ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+ return call; -+} -+ -+ -+/* Build IR to calculate some particular condition from stored -+ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression of type -+ Ity_I64, suitable for narrowing. Although the return type is -+ Ity_I64, the returned value is either 0 or 1. -+*/ -+static IRExpr* mk_arm64g_calculate_condition ( ARM64Condcode cond ) -+{ -+ /* First arg is "(cond << 4) | condition". This requires that the -+ ARM64_CC_OP_ values all fit in 4 bits. Hence we are passing a -+ (COND, OP) pair in the lowest 8 bits of the first argument. */ -+ vassert(cond >= 0 && cond <= 15); -+ return mk_arm64g_calculate_condition_dyn( mkU64(cond << 4) ); -+} -+ -+ -+//ZZ /* Build IR to calculate just the carry flag from stored -+//ZZ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: -+//ZZ Ity_I32. */ -+//ZZ static IRExpr* mk_armg_calculate_flag_c ( void ) -+//ZZ { -+//ZZ IRExpr** args -+//ZZ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP1, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP2, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); -+//ZZ IRExpr* call -+//ZZ = mkIRExprCCall( -+//ZZ Ity_I32, -+//ZZ 0/*regparm*/, -+//ZZ "armg_calculate_flag_c", &armg_calculate_flag_c, -+//ZZ args -+//ZZ ); -+//ZZ /* Exclude OP and NDEP from definedness checking. We're only -+//ZZ interested in DEP1 and DEP2. */ -+//ZZ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+//ZZ return call; -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* Build IR to calculate just the overflow flag from stored -+//ZZ CC_OP/CC_DEP1/CC_DEP2/CC_NDEP. Returns an expression :: -+//ZZ Ity_I32. */ -+//ZZ static IRExpr* mk_armg_calculate_flag_v ( void ) -+//ZZ { -+//ZZ IRExpr** args -+//ZZ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP1, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_DEP2, Ity_I32), -+//ZZ IRExpr_Get(OFFB_CC_NDEP, Ity_I32) ); -+//ZZ IRExpr* call -+//ZZ = mkIRExprCCall( -+//ZZ Ity_I32, -+//ZZ 0/*regparm*/, -+//ZZ "armg_calculate_flag_v", &armg_calculate_flag_v, -+//ZZ args -+//ZZ ); -+//ZZ /* Exclude OP and NDEP from definedness checking. We're only -+//ZZ interested in DEP1 and DEP2. */ -+//ZZ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+//ZZ return call; -+//ZZ } -+ -+ -+/* Build IR to calculate N Z C V in bits 31:28 of the -+ returned word. */ -+static IRExpr* mk_arm64g_calculate_flags_nzcv ( void ) -+{ -+ IRExpr** args -+ = mkIRExprVec_4( IRExpr_Get(OFFB_CC_OP, Ity_I64), -+ IRExpr_Get(OFFB_CC_DEP1, Ity_I64), -+ IRExpr_Get(OFFB_CC_DEP2, Ity_I64), -+ IRExpr_Get(OFFB_CC_NDEP, Ity_I64) ); -+ IRExpr* call -+ = mkIRExprCCall( -+ Ity_I64, -+ 0/*regparm*/, -+ "arm64g_calculate_flags_nzcv", &arm64g_calculate_flags_nzcv, -+ args -+ ); -+ /* Exclude OP and NDEP from definedness checking. We're only -+ interested in DEP1 and DEP2. */ -+ call->Iex.CCall.cee->mcx_mask = (1<<0) | (1<<3); -+ return call; -+} -+ -+ -+/* Build IR to set the flags thunk, in the most general case. */ -+static -+void setFlags_D1_D2_ND ( UInt cc_op, -+ IRTemp t_dep1, IRTemp t_dep2, IRTemp t_ndep ) -+{ -+ vassert(typeOfIRTemp(irsb->tyenv, t_dep1 == Ity_I64)); -+ vassert(typeOfIRTemp(irsb->tyenv, t_dep2 == Ity_I64)); -+ vassert(typeOfIRTemp(irsb->tyenv, t_ndep == Ity_I64)); -+ vassert(cc_op >= ARM64G_CC_OP_COPY && cc_op < ARM64G_CC_OP_NUMBER); -+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(cc_op) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(t_dep1) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkexpr(t_dep2) )); -+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(t_ndep) )); -+} -+ -+/* Build IR to set the flags thunk after ADD or SUB. */ -+static -+void setFlags_ADD_SUB ( Bool is64, Bool isSUB, IRTemp argL, IRTemp argR ) -+{ -+ IRTemp argL64 = IRTemp_INVALID; -+ IRTemp argR64 = IRTemp_INVALID; -+ IRTemp z64 = newTemp(Ity_I64); -+ if (is64) { -+ argL64 = argL; -+ argR64 = argR; -+ } else { -+ argL64 = newTemp(Ity_I64); -+ argR64 = newTemp(Ity_I64); -+ assign(argL64, unop(Iop_32Uto64, mkexpr(argL))); -+ assign(argR64, unop(Iop_32Uto64, mkexpr(argR))); -+ } -+ assign(z64, mkU64(0)); -+ UInt cc_op = ARM64G_CC_OP_NUMBER; -+ /**/ if ( isSUB && is64) { cc_op = ARM64G_CC_OP_SUB64; } -+ else if ( isSUB && !is64) { cc_op = ARM64G_CC_OP_SUB32; } -+ else if (!isSUB && is64) { cc_op = ARM64G_CC_OP_ADD64; } -+ else if (!isSUB && !is64) { cc_op = ARM64G_CC_OP_ADD32; } -+ else { vassert(0); } -+ setFlags_D1_D2_ND(cc_op, argL64, argR64, z64); -+} -+ -+/* Build IR to set the flags thunk after ADD or SUB, if the given -+ condition evaluates to True at run time. If not, the flags are set -+ to the specified NZCV value. */ -+static -+void setFlags_ADD_SUB_conditionally ( -+ Bool is64, Bool isSUB, -+ IRTemp cond, IRTemp argL, IRTemp argR, UInt nzcv -+ ) -+{ -+ /* Generate IR as follows: -+ CC_OP = ITE(cond, OP_{ADD,SUB}{32,64}, OP_COPY) -+ CC_DEP1 = ITE(cond, argL64, nzcv << 28) -+ CC_DEP2 = ITE(cond, argR64, 0) -+ CC_NDEP = 0 -+ */ -+ -+ IRTemp z64 = newTemp(Ity_I64); -+ assign(z64, mkU64(0)); -+ -+ /* Establish the operation and operands for the True case. */ -+ IRTemp t_dep1 = IRTemp_INVALID; -+ IRTemp t_dep2 = IRTemp_INVALID; -+ UInt t_op = ARM64G_CC_OP_NUMBER; -+ /**/ if ( isSUB && is64) { t_op = ARM64G_CC_OP_SUB64; } -+ else if ( isSUB && !is64) { t_op = ARM64G_CC_OP_SUB32; } -+ else if (!isSUB && is64) { t_op = ARM64G_CC_OP_ADD64; } -+ else if (!isSUB && !is64) { t_op = ARM64G_CC_OP_ADD32; } -+ else { vassert(0); } -+ /* */ -+ if (is64) { -+ t_dep1 = argL; -+ t_dep2 = argR; -+ } else { -+ t_dep1 = newTemp(Ity_I64); -+ t_dep2 = newTemp(Ity_I64); -+ assign(t_dep1, unop(Iop_32Uto64, mkexpr(argL))); -+ assign(t_dep2, unop(Iop_32Uto64, mkexpr(argR))); -+ } -+ -+ /* Establish the operation and operands for the False case. */ -+ IRTemp f_dep1 = newTemp(Ity_I64); -+ IRTemp f_dep2 = z64; -+ UInt f_op = ARM64G_CC_OP_COPY; -+ assign(f_dep1, mkU64(nzcv << 28)); -+ -+ /* Final thunk values */ -+ IRTemp dep1 = newTemp(Ity_I64); -+ IRTemp dep2 = newTemp(Ity_I64); -+ IRTemp op = newTemp(Ity_I64); -+ -+ assign(op, IRExpr_ITE(mkexpr(cond), mkU64(t_op), mkU64(f_op))); -+ assign(dep1, IRExpr_ITE(mkexpr(cond), mkexpr(t_dep1), mkexpr(f_dep1))); -+ assign(dep2, IRExpr_ITE(mkexpr(cond), mkexpr(t_dep2), mkexpr(f_dep2))); -+ -+ /* finally .. */ -+ stmt( IRStmt_Put( OFFB_CC_OP, mkexpr(op) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(dep1) )); -+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkexpr(dep2) )); -+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkexpr(z64) )); -+} -+ -+/* Build IR to set the flags thunk after AND/OR/XOR or variants thereof. */ -+static -+void setFlags_LOGIC ( Bool is64, IRTemp res ) -+{ -+ IRTemp res64 = IRTemp_INVALID; -+ IRTemp z64 = newTemp(Ity_I64); -+ UInt cc_op = ARM64G_CC_OP_NUMBER; -+ if (is64) { -+ res64 = res; -+ cc_op = ARM64G_CC_OP_LOGIC64; -+ } else { -+ res64 = newTemp(Ity_I64); -+ assign(res64, unop(Iop_32Uto64, mkexpr(res))); -+ cc_op = ARM64G_CC_OP_LOGIC32; -+ } -+ assign(z64, mkU64(0)); -+ setFlags_D1_D2_ND(cc_op, res64, z64, z64); -+} -+ -+/* Build IR to set the flags thunk to a given NZCV value. NZCV is -+ located in bits 31:28 of the supplied value. */ -+static -+void setFlags_COPY ( IRTemp nzcv_28x0 ) -+{ -+ IRTemp z64 = newTemp(Ity_I64); -+ assign(z64, mkU64(0)); -+ setFlags_D1_D2_ND(ARM64G_CC_OP_COPY, nzcv_28x0, z64, z64); -+} -+ -+ -+//ZZ /* Minor variant of the above that sets NDEP to zero (if it -+//ZZ sets it at all) */ -+//ZZ static void setFlags_D1_D2 ( UInt cc_op, IRTemp t_dep1, -+//ZZ IRTemp t_dep2, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ IRTemp z32 = newTemp(Ity_I32); -+//ZZ assign( z32, mkU32(0) ); -+//ZZ setFlags_D1_D2_ND( cc_op, t_dep1, t_dep2, z32, guardT ); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* Minor variant of the above that sets DEP2 to zero (if it -+//ZZ sets it at all) */ -+//ZZ static void setFlags_D1_ND ( UInt cc_op, IRTemp t_dep1, -+//ZZ IRTemp t_ndep, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ IRTemp z32 = newTemp(Ity_I32); -+//ZZ assign( z32, mkU32(0) ); -+//ZZ setFlags_D1_D2_ND( cc_op, t_dep1, z32, t_ndep, guardT ); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* Minor variant of the above that sets DEP2 and NDEP to zero (if it -+//ZZ sets them at all) */ -+//ZZ static void setFlags_D1 ( UInt cc_op, IRTemp t_dep1, -+//ZZ IRTemp guardT /* :: Ity_I32, 0 or 1 */ ) -+//ZZ { -+//ZZ IRTemp z32 = newTemp(Ity_I32); -+//ZZ assign( z32, mkU32(0) ); -+//ZZ setFlags_D1_D2_ND( cc_op, t_dep1, z32, z32, guardT ); -+//ZZ } -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Misc math helpers ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Generate IR for ((x & mask) >>u sh) | ((x << sh) & mask) */ -+static IRTemp math_SWAPHELPER ( IRTemp x, ULong mask, Int sh ) -+{ -+ IRTemp maskT = newTemp(Ity_I64); -+ IRTemp res = newTemp(Ity_I64); -+ vassert(sh >= 1 && sh <= 63); -+ assign(maskT, mkU64(mask)); -+ assign( res, -+ binop(Iop_Or64, -+ binop(Iop_Shr64, -+ binop(Iop_And64,mkexpr(x),mkexpr(maskT)), -+ mkU8(sh)), -+ binop(Iop_And64, -+ binop(Iop_Shl64,mkexpr(x),mkU8(sh)), -+ mkexpr(maskT)) -+ ) -+ ); -+ return res; -+} -+ -+/* Generates byte swaps within 32-bit lanes. */ -+static IRTemp math_UINTSWAP64 ( IRTemp src ) -+{ -+ IRTemp res; -+ res = math_SWAPHELPER(src, 0xFF00FF00FF00FF00ULL, 8); -+ res = math_SWAPHELPER(res, 0xFFFF0000FFFF0000ULL, 16); -+ return res; -+} -+ -+/* Generates byte swaps within 16-bit lanes. */ -+static IRTemp math_USHORTSWAP64 ( IRTemp src ) -+{ -+ IRTemp res; -+ res = math_SWAPHELPER(src, 0xFF00FF00FF00FF00ULL, 8); -+ return res; -+} -+ -+/* Generates a 64-bit byte swap. */ -+static IRTemp math_BYTESWAP64 ( IRTemp src ) -+{ -+ IRTemp res; -+ res = math_SWAPHELPER(src, 0xFF00FF00FF00FF00ULL, 8); -+ res = math_SWAPHELPER(res, 0xFFFF0000FFFF0000ULL, 16); -+ res = math_SWAPHELPER(res, 0xFFFFFFFF00000000ULL, 32); -+ return res; -+} -+ -+/* Generates a 64-bit bit swap. */ -+static IRTemp math_BITSWAP64 ( IRTemp src ) -+{ -+ IRTemp res; -+ res = math_SWAPHELPER(src, 0xAAAAAAAAAAAAAAAAULL, 1); -+ res = math_SWAPHELPER(res, 0xCCCCCCCCCCCCCCCCULL, 2); -+ res = math_SWAPHELPER(res, 0xF0F0F0F0F0F0F0F0ULL, 4); -+ return math_BYTESWAP64(res); -+} -+ -+/* Duplicates the bits at the bottom of the given word to fill the -+ whole word. src :: Ity_I64 is assumed to have zeroes everywhere -+ except for the bottom bits. */ -+static IRTemp math_DUP_TO_64 ( IRTemp src, IRType srcTy ) -+{ -+ if (srcTy == Ity_I8) { -+ IRTemp t16 = newTemp(Ity_I64); -+ assign(t16, binop(Iop_Or64, mkexpr(src), -+ binop(Iop_Shl64, mkexpr(src), mkU8(8)))); -+ IRTemp t32 = newTemp(Ity_I64); -+ assign(t32, binop(Iop_Or64, mkexpr(t16), -+ binop(Iop_Shl64, mkexpr(t16), mkU8(16)))); -+ IRTemp t64 = newTemp(Ity_I64); -+ assign(t64, binop(Iop_Or64, mkexpr(t32), -+ binop(Iop_Shl64, mkexpr(t32), mkU8(32)))); -+ return t64; -+ } -+ if (srcTy == Ity_I16) { -+ IRTemp t32 = newTemp(Ity_I64); -+ assign(t32, binop(Iop_Or64, mkexpr(src), -+ binop(Iop_Shl64, mkexpr(src), mkU8(16)))); -+ IRTemp t64 = newTemp(Ity_I64); -+ assign(t64, binop(Iop_Or64, mkexpr(t32), -+ binop(Iop_Shl64, mkexpr(t32), mkU8(32)))); -+ return t64; -+ } -+ if (srcTy == Ity_I32) { -+ IRTemp t64 = newTemp(Ity_I64); -+ assign(t64, binop(Iop_Or64, mkexpr(src), -+ binop(Iop_Shl64, mkexpr(src), mkU8(32)))); -+ return t64; -+ } -+ if (srcTy == Ity_I64) { -+ return src; -+ } -+ vassert(0); -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- FP comparison helpers ---*/ -+/*------------------------------------------------------------*/ -+ -+/* irRes :: Ity_I32 holds a floating point comparison result encoded -+ as an IRCmpF64Result. Generate code to convert it to an -+ ARM64-encoded (N,Z,C,V) group in the lowest 4 bits of an I64 value. -+ Assign a new temp to hold that value, and return the temp. */ -+static -+IRTemp mk_convert_IRCmpF64Result_to_NZCV ( IRTemp irRes32 ) -+{ -+ IRTemp ix = newTemp(Ity_I64); -+ IRTemp termL = newTemp(Ity_I64); -+ IRTemp termR = newTemp(Ity_I64); -+ IRTemp nzcv = newTemp(Ity_I64); -+ IRTemp irRes = newTemp(Ity_I64); -+ -+ /* This is where the fun starts. We have to convert 'irRes' from -+ an IR-convention return result (IRCmpF64Result) to an -+ ARM-encoded (N,Z,C,V) group. The final result is in the bottom -+ 4 bits of 'nzcv'. */ -+ /* Map compare result from IR to ARM(nzcv) */ -+ /* -+ FP cmp result | IR | ARM(nzcv) -+ -------------------------------- -+ UN 0x45 0011 -+ LT 0x01 1000 -+ GT 0x00 0010 -+ EQ 0x40 0110 -+ */ -+ /* Now since you're probably wondering WTF .. -+ -+ ix fishes the useful bits out of the IR value, bits 6 and 0, and -+ places them side by side, giving a number which is 0, 1, 2 or 3. -+ -+ termL is a sequence cooked up by GNU superopt. It converts ix -+ into an almost correct value NZCV value (incredibly), except -+ for the case of UN, where it produces 0100 instead of the -+ required 0011. -+ -+ termR is therefore a correction term, also computed from ix. It -+ is 1 in the UN case and 0 for LT, GT and UN. Hence, to get -+ the final correct value, we subtract termR from termL. -+ -+ Don't take my word for it. There's a test program at the bottom -+ of guest_arm_toIR.c, to try this out with. -+ */ -+ assign(irRes, unop(Iop_32Uto64, mkexpr(irRes32))); -+ -+ assign( -+ ix, -+ binop(Iop_Or64, -+ binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(irRes), mkU8(5)), -+ mkU64(3)), -+ binop(Iop_And64, mkexpr(irRes), mkU64(1)))); -+ -+ assign( -+ termL, -+ binop(Iop_Add64, -+ binop(Iop_Shr64, -+ binop(Iop_Sub64, -+ binop(Iop_Shl64, -+ binop(Iop_Xor64, mkexpr(ix), mkU64(1)), -+ mkU8(62)), -+ mkU64(1)), -+ mkU8(61)), -+ mkU64(1))); -+ -+ assign( -+ termR, -+ binop(Iop_And64, -+ binop(Iop_And64, -+ mkexpr(ix), -+ binop(Iop_Shr64, mkexpr(ix), mkU8(1))), -+ mkU64(1))); -+ -+ assign(nzcv, binop(Iop_Sub64, mkexpr(termL), mkexpr(termR))); -+ return nzcv; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Data processing (immediate) ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Helper functions for supporting "DecodeBitMasks" */ -+ -+static ULong dbm_ROR ( Int width, ULong x, Int rot ) -+{ -+ vassert(width > 0 && width <= 64); -+ vassert(rot >= 0 && rot < width); -+ if (rot == 0) return x; -+ ULong res = x >> rot; -+ res |= (x << (width - rot)); -+ if (width < 64) -+ res &= ((1ULL << width) - 1); -+ return res; -+} -+ -+static ULong dbm_RepTo64( Int esize, ULong x ) -+{ -+ switch (esize) { -+ case 64: -+ return x; -+ case 32: -+ x &= 0xFFFFFFFF; x |= (x << 32); -+ return x; -+ case 16: -+ x &= 0xFFFF; x |= (x << 16); x |= (x << 32); -+ return x; -+ case 8: -+ x &= 0xFF; x |= (x << 8); x |= (x << 16); x |= (x << 32); -+ return x; -+ case 4: -+ x &= 0xF; x |= (x << 4); x |= (x << 8); -+ x |= (x << 16); x |= (x << 32); -+ return x; -+ case 2: -+ x &= 0x3; x |= (x << 2); x |= (x << 4); x |= (x << 8); -+ x |= (x << 16); x |= (x << 32); -+ return x; -+ default: -+ break; -+ } -+ vpanic("dbm_RepTo64"); -+ /*NOTREACHED*/ -+ return 0; -+} -+ -+static Int dbm_highestSetBit ( ULong x ) -+{ -+ Int i; -+ for (i = 63; i >= 0; i--) { -+ if (x & (1ULL << i)) -+ return i; -+ } -+ vassert(x == 0); -+ return -1; -+} -+ -+static -+Bool dbm_DecodeBitMasks ( /*OUT*/ULong* wmask, /*OUT*/ULong* tmask, -+ ULong immN, ULong imms, ULong immr, Bool immediate, -+ UInt M /*32 or 64*/) -+{ -+ vassert(immN < (1ULL << 1)); -+ vassert(imms < (1ULL << 6)); -+ vassert(immr < (1ULL << 6)); -+ vassert(immediate == False || immediate == True); -+ vassert(M == 32 || M == 64); -+ -+ Int len = dbm_highestSetBit( ((immN << 6) & 64) | ((~imms) & 63) ); -+ if (len < 1) { /* printf("fail1\n"); */ return False; } -+ vassert(len <= 6); -+ vassert(M >= (1 << len)); -+ -+ vassert(len >= 1 && len <= 6); -+ ULong levels = // (zeroes(6 - len) << (6-len)) | ones(len); -+ (1 << len) - 1; -+ vassert(levels >= 1 && levels <= 63); -+ -+ if (immediate && ((imms & levels) == levels)) { -+ /* printf("fail2 imms %llu levels %llu len %d\n", imms, levels, len); */ -+ return False; -+ } -+ -+ ULong S = imms & levels; -+ ULong R = immr & levels; -+ Int diff = S - R; -+ diff &= 63; -+ Int esize = 1 << len; -+ vassert(2 <= esize && esize <= 64); -+ -+ /* Be careful of these (1ULL << (S+1)) - 1 expressions, and the -+ same below with d. S can be 63 in which case we have an out of -+ range and hence undefined shift. */ -+ vassert(S >= 0 && S <= 63); -+ vassert(esize >= (S+1)); -+ ULong elem_s = // Zeroes(esize-(S+1)):Ones(S+1) -+ //(1ULL << (S+1)) - 1; -+ ((1ULL << S) - 1) + (1ULL << S); -+ -+ Int d = // diff -+ diff & ((1 << len)-1); -+ vassert(esize >= (d+1)); -+ vassert(d >= 0 && d <= 63); -+ -+ ULong elem_d = // Zeroes(esize-(d+1)):Ones(d+1) -+ //(1ULL << (d+1)) - 1; -+ ((1ULL << d) - 1) + (1ULL << d); -+ -+ if (esize != 64) vassert(elem_s < (1ULL << esize)); -+ if (esize != 64) vassert(elem_d < (1ULL << esize)); -+ -+ if (wmask) *wmask = dbm_RepTo64(esize, dbm_ROR(esize, elem_s, R)); -+ if (tmask) *tmask = dbm_RepTo64(esize, elem_d); -+ -+ return True; -+} -+ -+ -+static -+Bool dis_ARM64_data_processing_immediate(/*MB_OUT*/DisResult* dres, -+ UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* insn[28:23] -+ 10000x PC-rel addressing -+ 10001x Add/subtract (immediate) -+ 100100 Logical (immediate) -+ 100101 Move Wide (immediate) -+ 100110 Bitfield -+ 100111 Extract -+ */ -+ -+ /* ------------------ ADD/SUB{,S} imm12 ------------------ */ -+ if (INSN(28,24) == BITS5(1,0,0,0,1)) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSub = INSN(30,30) == 1; -+ Bool setCC = INSN(29,29) == 1; -+ UInt sh = INSN(23,22); -+ UInt uimm12 = INSN(21,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ const HChar* nm = isSub ? "sub" : "add"; -+ if (sh >= 2) { -+ /* Invalid; fall through */ -+ } else { -+ vassert(sh <= 1); -+ uimm12 <<= (12 * sh); -+ if (is64) { -+ IRTemp argL = newTemp(Ity_I64); -+ IRTemp argR = newTemp(Ity_I64); -+ IRTemp res = newTemp(Ity_I64); -+ assign(argL, getIReg64orSP(nn)); -+ assign(argR, mkU64(uimm12)); -+ assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64, -+ mkexpr(argL), mkexpr(argR))); -+ if (setCC) { -+ putIReg64orZR(dd, mkexpr(res)); -+ setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR); -+ DIP("%ss %s, %s, 0x%x\n", -+ nm, nameIReg64orZR(dd), nameIReg64orSP(nn), uimm12); -+ } else { -+ putIReg64orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%x\n", -+ nm, nameIReg64orSP(dd), nameIReg64orSP(nn), uimm12); -+ } -+ } else { -+ IRTemp argL = newTemp(Ity_I32); -+ IRTemp argR = newTemp(Ity_I32); -+ IRTemp res = newTemp(Ity_I32); -+ assign(argL, getIReg32orSP(nn)); -+ assign(argR, mkU32(uimm12)); -+ assign(res, binop(isSub ? Iop_Sub32 : Iop_Add32, -+ mkexpr(argL), mkexpr(argR))); -+ if (setCC) { -+ putIReg32orZR(dd, mkexpr(res)); -+ setFlags_ADD_SUB(False/*!is64*/, isSub, argL, argR); -+ DIP("%ss %s, %s, 0x%x\n", -+ nm, nameIReg32orZR(dd), nameIReg32orSP(nn), uimm12); -+ } else { -+ putIReg32orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%x\n", -+ nm, nameIReg32orSP(dd), nameIReg32orSP(nn), uimm12); -+ } -+ } -+ return True; -+ } -+ } -+ -+ /* -------------------- ADR/ADRP -------------------- */ -+ if (INSN(28,24) == BITS5(1,0,0,0,0)) { -+ UInt bP = INSN(31,31); -+ UInt immLo = INSN(30,29); -+ UInt immHi = INSN(23,5); -+ UInt rD = INSN(4,0); -+ ULong uimm = (immHi << 2) | immLo; -+ ULong simm = sx_to_64(uimm, 21); -+ ULong val; -+ if (bP) { -+ val = (guest_PC_curr_instr & 0xFFFFFFFFFFFFF000ULL) + (simm << 12); -+ } else { -+ val = guest_PC_curr_instr + simm; -+ } -+ putIReg64orZR(rD, mkU64(val)); -+ DIP("adr%s %s, 0x%llx\n", bP ? "p" : "", nameIReg64orZR(rD), val); -+ return True; -+ } -+ -+ /* -------------------- LOGIC(imm) -------------------- */ -+ if (INSN(28,23) == BITS6(1,0,0,1,0,0)) { -+ /* 31 30 28 22 21 15 9 4 -+ sf op 100100 N immr imms Rn Rd -+ op=00: AND Rd|SP, Rn, #imm -+ op=01: ORR Rd|SP, Rn, #imm -+ op=10: EOR Rd|SP, Rn, #imm -+ op=11: ANDS Rd|ZR, Rn, #imm -+ */ -+ Bool is64 = INSN(31,31) == 1; -+ UInt op = INSN(30,29); -+ UInt N = INSN(22,22); -+ UInt immR = INSN(21,16); -+ UInt immS = INSN(15,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ ULong imm = 0; -+ Bool ok; -+ if (N == 1 && !is64) -+ goto after_logic_imm; /* not allowed; fall through */ -+ ok = dbm_DecodeBitMasks(&imm, NULL, -+ N, immS, immR, True, is64 ? 64 : 32); -+ if (!ok) -+ goto after_logic_imm; -+ -+ const HChar* names[4] = { "and", "orr", "eor", "ands" }; -+ const IROp ops64[4] = { Iop_And64, Iop_Or64, Iop_Xor64, Iop_And64 }; -+ const IROp ops32[4] = { Iop_And32, Iop_Or32, Iop_Xor32, Iop_And32 }; -+ -+ vassert(op < 4); -+ if (is64) { -+ IRExpr* argL = getIReg64orZR(nn); -+ IRExpr* argR = mkU64(imm); -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, binop(ops64[op], argL, argR)); -+ if (op < 3) { -+ putIReg64orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%llx\n", names[op], -+ nameIReg64orSP(dd), nameIReg64orZR(nn), imm); -+ } else { -+ putIReg64orZR(dd, mkexpr(res)); -+ setFlags_LOGIC(True/*is64*/, res); -+ DIP("%s %s, %s, 0x%llx\n", names[op], -+ nameIReg64orZR(dd), nameIReg64orZR(nn), imm); -+ } -+ } else { -+ IRExpr* argL = getIReg32orZR(nn); -+ IRExpr* argR = mkU32((UInt)imm); -+ IRTemp res = newTemp(Ity_I32); -+ assign(res, binop(ops32[op], argL, argR)); -+ if (op < 3) { -+ putIReg32orSP(dd, mkexpr(res)); -+ DIP("%s %s, %s, 0x%x\n", names[op], -+ nameIReg32orSP(dd), nameIReg32orZR(nn), (UInt)imm); -+ } else { -+ putIReg32orZR(dd, mkexpr(res)); -+ setFlags_LOGIC(False/*!is64*/, res); -+ DIP("%s %s, %s, 0x%x\n", names[op], -+ nameIReg32orZR(dd), nameIReg32orZR(nn), (UInt)imm); -+ } -+ } -+ return True; -+ } -+ after_logic_imm: -+ -+ /* -------------------- MOV{Z,N,K} -------------------- */ -+ if (INSN(28,23) == BITS6(1,0,0,1,0,1)) { -+ /* 31 30 28 22 20 4 -+ | | | | | | -+ sf 10 100 101 hw imm16 Rd MOV(Z) Rd, (imm16 << (16*hw)) -+ sf 00 100 101 hw imm16 Rd MOV(N) Rd, ~(imm16 << (16*hw)) -+ sf 11 100 101 hw imm16 Rd MOV(K) Rd, (imm16 << (16*hw)) -+ */ -+ Bool is64 = INSN(31,31) == 1; -+ UInt subopc = INSN(30,29); -+ UInt hw = INSN(22,21); -+ UInt imm16 = INSN(20,5); -+ UInt dd = INSN(4,0); -+ if (subopc == BITS2(0,1) || (!is64 && hw >= 2)) { -+ /* invalid; fall through */ -+ } else { -+ ULong imm64 = ((ULong)imm16) << (16 * hw); -+ if (!is64) -+ vassert(imm64 < 0x100000000ULL); -+ switch (subopc) { -+ case BITS2(1,0): // MOVZ -+ putIRegOrZR(is64, dd, is64 ? mkU64(imm64) : mkU32((UInt)imm64)); -+ DIP("movz %s, 0x%llx\n", nameIRegOrZR(is64, dd), imm64); -+ break; -+ case BITS2(0,0): // MOVN -+ imm64 = ~imm64; -+ if (!is64) -+ imm64 &= 0xFFFFFFFFULL; -+ putIRegOrZR(is64, dd, is64 ? mkU64(imm64) : mkU32((UInt)imm64)); -+ DIP("movn %s, 0x%llx\n", nameIRegOrZR(is64, dd), imm64); -+ break; -+ case BITS2(1,1): // MOVK -+ /* This is more complex. We are inserting a slice into -+ the destination register, so we need to have the old -+ value of it. */ -+ if (is64) { -+ IRTemp old = newTemp(Ity_I64); -+ assign(old, getIReg64orZR(dd)); -+ ULong mask = 0xFFFFULL << (16 * hw); -+ IRExpr* res -+ = binop(Iop_Or64, -+ binop(Iop_And64, mkexpr(old), mkU64(~mask)), -+ mkU64(imm64)); -+ putIReg64orZR(dd, res); -+ DIP("movk %s, 0x%x, lsl %u\n", -+ nameIReg64orZR(dd), imm16, 16*hw); -+ } else { -+ IRTemp old = newTemp(Ity_I32); -+ assign(old, getIReg32orZR(dd)); -+ vassert(hw <= 1); -+ UInt mask = 0xFFFF << (16 * hw); -+ IRExpr* res -+ = binop(Iop_Or32, -+ binop(Iop_And32, mkexpr(old), mkU32(~mask)), -+ mkU32((UInt)imm64)); -+ putIReg32orZR(dd, res); -+ DIP("movk %s, 0x%x, lsl %u\n", -+ nameIReg32orZR(dd), imm16, 16*hw); -+ } -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ } -+ -+ /* -------------------- {U,S,}BFM -------------------- */ -+ /* 30 28 22 21 15 9 4 -+ -+ sf 10 100110 N immr imms nn dd -+ UBFM Wd, Wn, #immr, #imms when sf=0, N=0, immr[5]=0, imms[5]=0 -+ UBFM Xd, Xn, #immr, #imms when sf=1, N=1 -+ -+ sf 00 100110 N immr imms nn dd -+ SBFM Wd, Wn, #immr, #imms when sf=0, N=0, immr[5]=0, imms[5]=0 -+ SBFM Xd, Xn, #immr, #imms when sf=1, N=1 -+ -+ sf 01 100110 N immr imms nn dd -+ BFM Wd, Wn, #immr, #imms when sf=0, N=0, immr[5]=0, imms[5]=0 -+ BFM Xd, Xn, #immr, #imms when sf=1, N=1 -+ */ -+ if (INSN(28,23) == BITS6(1,0,0,1,1,0)) { -+ UInt sf = INSN(31,31); -+ UInt opc = INSN(30,29); -+ UInt N = INSN(22,22); -+ UInt immR = INSN(21,16); -+ UInt immS = INSN(15,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool inZero = False; -+ Bool extend = False; -+ const HChar* nm = "???"; -+ /* skip invalid combinations */ -+ switch (opc) { -+ case BITS2(0,0): -+ inZero = True; extend = True; nm = "sbfm"; break; -+ case BITS2(0,1): -+ inZero = False; extend = False; nm = "bfm"; break; -+ case BITS2(1,0): -+ inZero = True; extend = False; nm = "ubfm"; break; -+ case BITS2(1,1): -+ goto after_bfm; /* invalid */ -+ default: -+ vassert(0); -+ } -+ if (sf == 1 && N != 1) goto after_bfm; -+ if (sf == 0 && (N != 0 || ((immR >> 5) & 1) != 0 -+ || ((immS >> 5) & 1) != 0)) goto after_bfm; -+ ULong wmask = 0, tmask = 0; -+ Bool ok = dbm_DecodeBitMasks(&wmask, &tmask, -+ N, immS, immR, False, sf == 1 ? 64 : 32); -+ if (!ok) goto after_bfm; /* hmmm */ -+ -+ Bool is64 = sf == 1; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ -+ IRTemp dst = newTemp(ty); -+ IRTemp src = newTemp(ty); -+ IRTemp bot = newTemp(ty); -+ IRTemp top = newTemp(ty); -+ IRTemp res = newTemp(ty); -+ assign(dst, inZero ? mkU(ty,0) : getIRegOrZR(is64, dd)); -+ assign(src, getIRegOrZR(is64, nn)); -+ /* perform bitfield move on low bits */ -+ assign(bot, binop(mkOR(ty), -+ binop(mkAND(ty), mkexpr(dst), mkU(ty, ~wmask)), -+ binop(mkAND(ty), mkexpr(mathROR(ty, src, immR)), -+ mkU(ty, wmask)))); -+ /* determine extension bits (sign, zero or dest register) */ -+ assign(top, mkexpr(extend ? mathREPLICATE(ty, src, immS) : dst)); -+ /* combine extension bits and result bits */ -+ assign(res, binop(mkOR(ty), -+ binop(mkAND(ty), mkexpr(top), mkU(ty, ~tmask)), -+ binop(mkAND(ty), mkexpr(bot), mkU(ty, tmask)))); -+ putIRegOrZR(is64, dd, mkexpr(res)); -+ DIP("%s %s, %s, immR=%u, immS=%u\n", -+ nm, nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), immR, immS); -+ return True; -+ } -+ after_bfm: -+ -+ /* ---------------------- EXTR ---------------------- */ -+ /* 30 28 22 20 15 9 4 -+ 1 00 100111 10 m imm6 n d EXTR Xd, Xn, Xm, #imm6 -+ 0 00 100111 00 m imm6 n d EXTR Wd, Wn, Wm, #imm6 when #imm6 < 32 -+ */ -+ if (INSN(30,23) == BITS8(0,0,1,0,0,1,1,1) && INSN(21,21) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ UInt imm6 = INSN(15,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool valid = True; -+ if (INSN(31,31) != INSN(22,22)) -+ valid = False; -+ if (!is64 && imm6 >= 32) -+ valid = False; -+ if (!valid) goto after_extr; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp srcHi = newTemp(ty); -+ IRTemp srcLo = newTemp(ty); -+ IRTemp res = newTemp(ty); -+ assign(srcHi, getIRegOrZR(is64, nn)); -+ assign(srcLo, getIRegOrZR(is64, mm)); -+ if (imm6 == 0) { -+ assign(res, mkexpr(srcLo)); -+ } else { -+ UInt szBits = 8 * sizeofIRType(ty); -+ vassert(imm6 > 0 && imm6 < szBits); -+ assign(res, binop(mkOR(ty), -+ binop(mkSHL(ty), mkexpr(srcHi), mkU8(szBits-imm6)), -+ binop(mkSHR(ty), mkexpr(srcLo), mkU8(imm6)))); -+ } -+ putIRegOrZR(is64, dd, mkexpr(res)); -+ DIP("extr %s, %s, %s, #%u\n", -+ nameIRegOrZR(is64,dd), -+ nameIRegOrZR(is64,nn), nameIRegOrZR(is64,mm), imm6); -+ return True; -+ } -+ after_extr: -+ -+ vex_printf("ARM64 front end: data_processing_immediate\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Data processing (register) instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+static const HChar* nameSH ( UInt sh ) { -+ switch (sh) { -+ case 0: return "lsl"; -+ case 1: return "lsr"; -+ case 2: return "asr"; -+ case 3: return "ror"; -+ default: vassert(0); -+ } -+} -+ -+/* Generate IR to get a register value, possibly shifted by an -+ immediate. Returns either a 32- or 64-bit temporary holding the -+ result. After the shift, the value can optionally be NOT-ed -+ too. -+ -+ sh_how coding: 00=SHL, 01=SHR, 10=SAR, 11=ROR. sh_amt may only be -+ in the range 0 to (is64 ? 64 : 32)-1. For some instructions, ROR -+ isn't allowed, but it's the job of the caller to check that. -+*/ -+static IRTemp getShiftedIRegOrZR ( Bool is64, -+ UInt sh_how, UInt sh_amt, UInt regNo, -+ Bool invert ) -+{ -+ vassert(sh_how < 4); -+ vassert(sh_amt < (is64 ? 64 : 32)); -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp t0 = newTemp(ty); -+ assign(t0, getIRegOrZR(is64, regNo)); -+ IRTemp t1 = newTemp(ty); -+ switch (sh_how) { -+ case BITS2(0,0): -+ assign(t1, binop(mkSHL(ty), mkexpr(t0), mkU8(sh_amt))); -+ break; -+ case BITS2(0,1): -+ assign(t1, binop(mkSHR(ty), mkexpr(t0), mkU8(sh_amt))); -+ break; -+ case BITS2(1,0): -+ assign(t1, binop(mkSAR(ty), mkexpr(t0), mkU8(sh_amt))); -+ break; -+ case BITS2(1,1): -+ assign(t1, mkexpr(mathROR(ty, t0, sh_amt))); -+ break; -+ default: -+ vassert(0); -+ } -+ if (invert) { -+ IRTemp t2 = newTemp(ty); -+ assign(t2, unop(mkNOT(ty), mkexpr(t1))); -+ return t2; -+ } else { -+ return t1; -+ } -+} -+ -+ -+static -+Bool dis_ARM64_data_processing_register(/*MB_OUT*/DisResult* dres, -+ UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ------------------- ADD/SUB(reg) ------------------- */ -+ /* x==0 => 32 bit op x==1 => 64 bit op -+ sh: 00=LSL, 01=LSR, 10=ASR, 11=ROR(NOT ALLOWED) -+ -+ 31 30 29 28 23 21 20 15 9 4 -+ | | | | | | | | | | -+ x 0 0 01011 sh 0 Rm imm6 Rn Rd ADD Rd,Rn, sh(Rm,imm6) -+ x 0 1 01011 sh 0 Rm imm6 Rn Rd ADDS Rd,Rn, sh(Rm,imm6) -+ x 1 0 01011 sh 0 Rm imm6 Rn Rd SUB Rd,Rn, sh(Rm,imm6) -+ x 1 1 01011 sh 0 Rm imm6 Rn Rd SUBS Rd,Rn, sh(Rm,imm6) -+ */ -+ if (INSN(28,24) == BITS5(0,1,0,1,1) && INSN(21,21) == 0) { -+ UInt bX = INSN(31,31); -+ UInt bOP = INSN(30,30); /* 0: ADD, 1: SUB */ -+ UInt bS = INSN(29, 29); /* set flags? */ -+ UInt sh = INSN(23,22); -+ UInt rM = INSN(20,16); -+ UInt imm6 = INSN(15,10); -+ UInt rN = INSN(9,5); -+ UInt rD = INSN(4,0); -+ Bool isSUB = bOP == 1; -+ Bool is64 = bX == 1; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ if ((!is64 && imm6 > 31) || sh == BITS2(1,1)) { -+ /* invalid; fall through */ -+ } else { -+ IRTemp argL = newTemp(ty); -+ assign(argL, getIRegOrZR(is64, rN)); -+ IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, False); -+ IROp op = isSUB ? mkSUB(ty) : mkADD(ty); -+ IRTemp res = newTemp(ty); -+ assign(res, binop(op, mkexpr(argL), mkexpr(argR))); -+ if (rD != 31) putIRegOrZR(is64, rD, mkexpr(res)); -+ if (bS) { -+ setFlags_ADD_SUB(is64, isSUB, argL, argR); -+ } -+ DIP("%s%s %s, %s, %s, %s #%u\n", -+ bOP ? "sub" : "add", bS ? "s" : "", -+ nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), -+ nameIRegOrZR(is64, rM), nameSH(sh), imm6); -+ return True; -+ } -+ } -+ -+ /* -------------------- LOGIC(reg) -------------------- */ -+ /* x==0 => 32 bit op x==1 => 64 bit op -+ N==0 => inv? is no-op (no inversion) -+ N==1 => inv? is NOT -+ sh: 00=LSL, 01=LSR, 10=ASR, 11=ROR -+ -+ 31 30 28 23 21 20 15 9 4 -+ | | | | | | | | | -+ x 00 01010 sh N Rm imm6 Rn Rd AND Rd,Rn, inv?(sh(Rm,imm6)) -+ x 01 01010 sh N Rm imm6 Rn Rd ORR Rd,Rn, inv?(sh(Rm,imm6)) -+ x 10 01010 sh N Rm imm6 Rn Rd EOR Rd,Rn, inv?(sh(Rm,imm6)) -+ x 11 01010 sh N Rm imm6 Rn Rd ANDS Rd,Rn, inv?(sh(Rm,imm6)) -+ With N=1, the names are: BIC ORN EON BICS -+ */ -+ if (INSN(28,24) == BITS5(0,1,0,1,0)) { -+ UInt bX = INSN(31,31); -+ UInt sh = INSN(23,22); -+ UInt bN = INSN(21,21); -+ UInt rM = INSN(20,16); -+ UInt imm6 = INSN(15,10); -+ UInt rN = INSN(9,5); -+ UInt rD = INSN(4,0); -+ Bool is64 = bX == 1; -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ if (!is64 && imm6 > 31) { -+ /* invalid; fall though */ -+ } else { -+ IRTemp argL = newTemp(ty); -+ assign(argL, getIRegOrZR(is64, rN)); -+ IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, bN == 1); -+ IROp op = Iop_INVALID; -+ switch (INSN(30,29)) { -+ case BITS2(0,0): case BITS2(1,1): op = mkAND(ty); break; -+ case BITS2(0,1): op = mkOR(ty); break; -+ case BITS2(1,0): op = mkXOR(ty); break; -+ default: vassert(0); -+ } -+ IRTemp res = newTemp(ty); -+ assign(res, binop(op, mkexpr(argL), mkexpr(argR))); -+ if (INSN(30,29) == BITS2(1,1)) { -+ setFlags_LOGIC(is64, res); -+ } -+ putIRegOrZR(is64, rD, mkexpr(res)); -+ -+ static const HChar* names_op[8] -+ = { "and", "orr", "eor", "ands", "bic", "orn", "eon", "bics" }; -+ vassert(((bN << 2) | INSN(30,29)) < 8); -+ const HChar* nm_op = names_op[(bN << 2) | INSN(30,29)]; -+ /* Special-case the printing of "MOV" */ -+ if (rN == 31/*zr*/ && sh == 0/*LSL*/ && imm6 == 0 && bN == 0) { -+ DIP("mov %s, %s\n", nameIRegOrZR(is64, rD), -+ nameIRegOrZR(is64, rM)); -+ } else { -+ DIP("%s %s, %s, %s, %s #%u\n", nm_op, -+ nameIRegOrZR(is64, rD), nameIRegOrZR(is64, rN), -+ nameIRegOrZR(is64, rM), nameSH(sh), imm6); -+ } -+ return True; -+ } -+ } -+ -+ /* -------------------- {U,S}MULH -------------------- */ -+ /* 31 23 22 20 15 9 4 -+ 10011011 1 10 Rm 011111 Rn Rd UMULH Xd,Xn,Xm -+ 10011011 0 10 Rm 011111 Rn Rd SMULH Xd,Xn,Xm -+ */ -+ if (INSN(31,24) == BITS8(1,0,0,1,1,0,1,1) -+ && INSN(22,21) == BITS2(1,0) && INSN(15,10) == BITS6(0,1,1,1,1,1)) { -+ Bool isU = INSN(23,23) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ putIReg64orZR(dd, unop(Iop_128HIto64, -+ binop(isU ? Iop_MullU64 : Iop_MullS64, -+ getIReg64orZR(nn), getIReg64orZR(mm)))); -+ DIP("%cmulh %s, %s, %s\n", -+ isU ? 'u' : 's', -+ nameIReg64orZR(dd), nameIReg64orZR(nn), nameIReg64orZR(mm)); -+ return True; -+ } -+ -+ /* -------------------- M{ADD,SUB} -------------------- */ -+ /* 31 30 20 15 14 9 4 -+ sf 00 11011 000 m 0 a n r MADD Rd,Rn,Rm,Ra d = a+m*n -+ sf 00 11011 000 m 1 a n r MADD Rd,Rn,Rm,Ra d = a-m*n -+ */ -+ if (INSN(30,21) == BITS10(0,0,1,1,0,1,1,0,0,0)) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ Bool isAdd = INSN(15,15) == 0; -+ UInt aa = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (is64) { -+ putIReg64orZR( -+ dd, -+ binop(isAdd ? Iop_Add64 : Iop_Sub64, -+ getIReg64orZR(aa), -+ binop(Iop_Mul64, getIReg64orZR(mm), getIReg64orZR(nn)))); -+ } else { -+ putIReg32orZR( -+ dd, -+ binop(isAdd ? Iop_Add32 : Iop_Sub32, -+ getIReg32orZR(aa), -+ binop(Iop_Mul32, getIReg32orZR(mm), getIReg32orZR(nn)))); -+ } -+ DIP("%s %s, %s, %s, %s\n", -+ isAdd ? "madd" : "msub", -+ nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), -+ nameIRegOrZR(is64, mm), nameIRegOrZR(is64, aa)); -+ return True; -+ } -+ -+ /* ---------------- CS{EL,INC,INV,NEG} ---------------- */ -+ /* 31 30 28 20 15 11 9 4 -+ sf 00 1101 0100 mm cond 00 nn dd CSEL Rd,Rn,Rm -+ sf 00 1101 0100 mm cond 01 nn dd CSINC Rd,Rn,Rm -+ sf 10 1101 0100 mm cond 00 nn dd CSINV Rd,Rn,Rm -+ sf 10 1101 0100 mm cond 01 nn dd CSNEG Rd,Rn,Rm -+ In all cases, the operation is: Rd = if cond then Rn else OP(Rm) -+ */ -+ if (INSN(29,21) == BITS9(0, 1,1,0,1, 0,1,0,0) && INSN(11,11) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt b30 = INSN(30,30); -+ UInt mm = INSN(20,16); -+ UInt cond = INSN(15,12); -+ UInt b10 = INSN(10,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt op = (b30 << 1) | b10; /* 00=id 01=inc 10=inv 11=neg */ -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRExpr* argL = getIRegOrZR(is64, nn); -+ IRExpr* argR = getIRegOrZR(is64, mm); -+ switch (op) { -+ case BITS2(0,0): -+ break; -+ case BITS2(0,1): -+ argR = binop(mkADD(ty), argR, mkU(ty,1)); -+ break; -+ case BITS2(1,0): -+ argR = unop(mkNOT(ty), argR); -+ break; -+ case BITS2(1,1): -+ argR = binop(mkSUB(ty), mkU(ty,0), argR); -+ break; -+ default: -+ vassert(0); -+ } -+ putIRegOrZR( -+ is64, dd, -+ IRExpr_ITE(unop(Iop_64to1, mk_arm64g_calculate_condition(cond)), -+ argL, argR) -+ ); -+ const HChar* op_nm[4] = { "csel", "csinc", "csinv", "csneg" }; -+ DIP("%s %s, %s, %s, %s\n", op_nm[op], -+ nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn), -+ nameIRegOrZR(is64, mm), nameCC(cond)); -+ return True; -+ } -+ -+ /* -------------- ADD/SUB(extended reg) -------------- */ -+ /* 28 20 15 12 9 4 -+ 000 01011 00 1 m opt imm3 n d ADD Wd|SP, Wn|SP, Wm ext&lsld -+ 100 01011 00 1 m opt imm3 n d ADD Xd|SP, Xn|SP, Rm ext&lsld -+ -+ 001 01011 00 1 m opt imm3 n d ADDS Wd, Wn|SP, Wm ext&lsld -+ 101 01011 00 1 m opt imm3 n d ADDS Xd, Xn|SP, Rm ext&lsld -+ -+ 010 01011 00 1 m opt imm3 n d SUB Wd|SP, Wn|SP, Wm ext&lsld -+ 110 01011 00 1 m opt imm3 n d SUB Xd|SP, Xn|SP, Rm ext&lsld -+ -+ 011 01011 00 1 m opt imm3 n d SUBS Wd, Wn|SP, Wm ext&lsld -+ 111 01011 00 1 m opt imm3 n d SUBS Xd, Xn|SP, Rm ext&lsld -+ -+ The 'm' operand is extended per opt, thusly: -+ -+ 000 Xm & 0xFF UXTB -+ 001 Xm & 0xFFFF UXTH -+ 010 Xm & (2^32)-1 UXTW -+ 011 Xm UXTX -+ -+ 100 Xm sx from bit 7 SXTB -+ 101 Xm sx from bit 15 SXTH -+ 110 Xm sx from bit 31 SXTW -+ 111 Xm SXTX -+ -+ In the 64 bit case (bit31 == 1), UXTX and SXTX are the identity -+ operation on Xm. In the 32 bit case, UXTW, UXTX, SXTW and SXTX -+ are the identity operation on Wm. -+ -+ After extension, the value is shifted left by imm3 bits, which -+ may only be in the range 0 .. 4 inclusive. -+ */ -+ if (INSN(28,21) == BITS8(0,1,0,1,1,0,0,1) && INSN(12,10) <= 4) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSub = INSN(30,30) == 1; -+ Bool setCC = INSN(29,29) == 1; -+ UInt mm = INSN(20,16); -+ UInt opt = INSN(15,13); -+ UInt imm3 = INSN(12,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ const HChar* nameExt[8] = { "uxtb", "uxth", "uxtw", "uxtx", -+ "sxtb", "sxth", "sxtw", "sxtx" }; -+ /* Do almost the same thing in the 32- and 64-bit cases. */ -+ IRTemp xN = newTemp(Ity_I64); -+ IRTemp xM = newTemp(Ity_I64); -+ assign(xN, getIReg64orSP(nn)); -+ assign(xM, getIReg64orZR(mm)); -+ IRExpr* xMw = mkexpr(xM); /* "xM widened" */ -+ Int shSX = 0; -+ /* widen Xm .. */ -+ switch (opt) { -+ case BITS3(0,0,0): // UXTB -+ xMw = binop(Iop_And64, xMw, mkU64(0xFF)); break; -+ case BITS3(0,0,1): // UXTH -+ xMw = binop(Iop_And64, xMw, mkU64(0xFFFF)); break; -+ case BITS3(0,1,0): // UXTW -- noop for the 32bit case -+ if (is64) { -+ xMw = unop(Iop_32Uto64, unop(Iop_64to32, xMw)); -+ } -+ break; -+ case BITS3(0,1,1): // UXTX -- always a noop -+ break; -+ case BITS3(1,0,0): // SXTB -+ shSX = 56; goto sxTo64; -+ case BITS3(1,0,1): // SXTH -+ shSX = 48; goto sxTo64; -+ case BITS3(1,1,0): // SXTW -- noop for the 32bit case -+ if (is64) { -+ shSX = 32; goto sxTo64; -+ } -+ break; -+ case BITS3(1,1,1): // SXTX -- always a noop -+ break; -+ sxTo64: -+ vassert(shSX >= 32); -+ xMw = binop(Iop_Sar64, binop(Iop_Shl64, xMw, mkU8(shSX)), -+ mkU8(shSX)); -+ break; -+ default: -+ vassert(0); -+ } -+ /* and now shift */ -+ IRTemp argL = xN; -+ IRTemp argR = newTemp(Ity_I64); -+ assign(argR, binop(Iop_Shl64, xMw, mkU8(imm3))); -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64, -+ mkexpr(argL), mkexpr(argR))); -+ if (is64) { -+ if (setCC) { -+ putIReg64orZR(dd, mkexpr(res)); -+ setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR); -+ } else { -+ putIReg64orSP(dd, mkexpr(res)); -+ } -+ } else { -+ if (setCC) { -+ IRTemp argL32 = newTemp(Ity_I32); -+ IRTemp argR32 = newTemp(Ity_I32); -+ putIReg32orZR(dd, unop(Iop_64to32, mkexpr(res))); -+ assign(argL32, unop(Iop_64to32, mkexpr(argL))); -+ assign(argR32, unop(Iop_64to32, mkexpr(argR))); -+ setFlags_ADD_SUB(False/*!is64*/, isSub, argL32, argR32); -+ } else { -+ putIReg32orSP(dd, unop(Iop_64to32, mkexpr(res))); -+ } -+ } -+ DIP("%s%s %s, %s, %s %s lsl %u\n", -+ isSub ? "sub" : "add", setCC ? "s" : "", -+ setCC ? nameIRegOrZR(is64, dd) : nameIRegOrSP(is64, dd), -+ nameIRegOrSP(is64, nn), nameIRegOrSP(is64, mm), -+ nameExt[opt], imm3); -+ return True; -+ } -+ -+ /* ---------------- CCMP/CCMN(imm) ---------------- */ -+ /* Bizarrely, these appear in the "data processing register" -+ category, even though they are operations against an -+ immediate. */ -+ /* 31 29 20 15 11 9 3 -+ sf 1 111010010 imm5 cond 10 Rn 0 nzcv CCMP Rn, #imm5, #nzcv, cond -+ sf 0 111010010 imm5 cond 10 Rn 0 nzcv CCMN Rn, #imm5, #nzcv, cond -+ -+ Operation is: -+ (CCMP) flags = if cond then flags-after-sub(Rn,imm5) else nzcv -+ (CCMN) flags = if cond then flags-after-add(Rn,imm5) else nzcv -+ */ -+ if (INSN(29,21) == BITS9(1,1,1,0,1,0,0,1,0) -+ && INSN(11,10) == BITS2(1,0) && INSN(4,4) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSUB = INSN(30,30) == 1; -+ UInt imm5 = INSN(20,16); -+ UInt cond = INSN(15,12); -+ UInt nn = INSN(9,5); -+ UInt nzcv = INSN(3,0); -+ -+ IRTemp condT = newTemp(Ity_I1); -+ assign(condT, unop(Iop_64to1, mk_arm64g_calculate_condition(cond))); -+ -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp argL = newTemp(ty); -+ IRTemp argR = newTemp(ty); -+ -+ if (is64) { -+ assign(argL, getIReg64orZR(nn)); -+ assign(argR, mkU64(imm5)); -+ } else { -+ assign(argL, getIReg32orZR(nn)); -+ assign(argR, mkU32(imm5)); -+ } -+ setFlags_ADD_SUB_conditionally(is64, isSUB, condT, argL, argR, nzcv); -+ -+ DIP("ccm%c %s, #%u, #%u, %s\n", -+ isSUB ? 'p' : 'n', nameIRegOrZR(is64, nn), -+ imm5, nzcv, nameCC(cond)); -+ return True; -+ } -+ -+ /* ---------------- CCMP/CCMN(reg) ---------------- */ -+ /* 31 29 20 15 11 9 3 -+ sf 1 111010010 Rm cond 00 Rn 0 nzcv CCMP Rn, Rm, #nzcv, cond -+ sf 0 111010010 Rm cond 00 Rn 0 nzcv CCMN Rn, Rm, #nzcv, cond -+ Operation is: -+ (CCMP) flags = if cond then flags-after-sub(Rn,Rm) else nzcv -+ (CCMN) flags = if cond then flags-after-add(Rn,Rm) else nzcv -+ */ -+ if (INSN(29,21) == BITS9(1,1,1,0,1,0,0,1,0) -+ && INSN(11,10) == BITS2(0,0) && INSN(4,4) == 0) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isSUB = INSN(30,30) == 1; -+ UInt mm = INSN(20,16); -+ UInt cond = INSN(15,12); -+ UInt nn = INSN(9,5); -+ UInt nzcv = INSN(3,0); -+ -+ IRTemp condT = newTemp(Ity_I1); -+ assign(condT, unop(Iop_64to1, mk_arm64g_calculate_condition(cond))); -+ -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp argL = newTemp(ty); -+ IRTemp argR = newTemp(ty); -+ -+ if (is64) { -+ assign(argL, getIReg64orZR(nn)); -+ assign(argR, getIReg64orZR(mm)); -+ } else { -+ assign(argL, getIReg32orZR(nn)); -+ assign(argR, getIReg32orZR(mm)); -+ } -+ setFlags_ADD_SUB_conditionally(is64, isSUB, condT, argL, argR, nzcv); -+ -+ DIP("ccm%c %s, %s, #%u, %s\n", -+ isSUB ? 'p' : 'n', nameIRegOrZR(is64, nn), -+ nameIRegOrZR(is64, mm), nzcv, nameCC(cond)); -+ return True; -+ } -+ -+ -+ /* -------------- REV/REV16/REV32/RBIT -------------- */ -+ /* 31 30 28 20 15 11 9 4 -+ -+ 1 10 11010110 00000 0000 11 n d (1) REV Xd, Xn -+ 0 10 11010110 00000 0000 10 n d (2) REV Wd, Wn -+ -+ 1 10 11010110 00000 0000 00 n d (3) RBIT Xd, Xn -+ 0 10 11010110 00000 0000 00 n d (4) RBIT Wd, Wn -+ -+ 1 10 11010110 00000 0000 01 n d (5) REV16 Xd, Xn -+ 0 10 11010110 00000 0000 01 n d (6) REV16 Wd, Wn -+ -+ 1 10 11010110 00000 0000 10 n d (7) REV32 Xd, Xn -+ */ -+ if (INSN(30,21) == BITS10(1,0,1,1,0,1,0,1,1,0) -+ && INSN(20,12) == BITS9(0,0,0,0,0,0,0,0,0)) { -+ UInt b31 = INSN(31,31); -+ UInt opc = INSN(11,10); -+ -+ UInt ix = 0; -+ /**/ if (b31 == 1 && opc == BITS2(1,1)) ix = 1; -+ else if (b31 == 0 && opc == BITS2(1,0)) ix = 2; -+ else if (b31 == 1 && opc == BITS2(0,0)) ix = 3; -+ else if (b31 == 0 && opc == BITS2(0,0)) ix = 4; -+ else if (b31 == 1 && opc == BITS2(0,1)) ix = 5; -+ else if (b31 == 0 && opc == BITS2(0,1)) ix = 6; -+ else if (b31 == 1 && opc == BITS2(1,0)) ix = 7; -+ if (ix >= 1 && ix <= 7) { -+ Bool is64 = ix == 1 || ix == 3 || ix == 5 || ix == 7; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp src = newTemp(Ity_I64); -+ IRTemp dst = IRTemp_INVALID; -+ IRTemp (*math)(IRTemp) = NULL; -+ switch (ix) { -+ case 1: case 2: math = math_BYTESWAP64; break; -+ case 3: case 4: math = math_BITSWAP64; break; -+ case 5: case 6: math = math_USHORTSWAP64; break; -+ case 7: math = math_UINTSWAP64; break; -+ default: vassert(0); -+ } -+ const HChar* names[7] -+ = { "rev", "rev", "rbit", "rbit", "rev16", "rev16", "rev32" }; -+ const HChar* nm = names[ix-1]; -+ vassert(math); -+ if (ix == 6) { -+ /* This has to be special cased, since the logic below doesn't -+ handle it correctly. */ -+ assign(src, getIReg64orZR(nn)); -+ dst = math(src); -+ putIReg64orZR(dd, -+ unop(Iop_32Uto64, unop(Iop_64to32, mkexpr(dst)))); -+ } else if (is64) { -+ assign(src, getIReg64orZR(nn)); -+ dst = math(src); -+ putIReg64orZR(dd, mkexpr(dst)); -+ } else { -+ assign(src, binop(Iop_Shl64, getIReg64orZR(nn), mkU8(32))); -+ dst = math(src); -+ putIReg32orZR(dd, unop(Iop_64to32, mkexpr(dst))); -+ } -+ DIP("%s %s, %s\n", nm, -+ nameIRegOrZR(is64,dd), nameIRegOrZR(is64,nn)); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------------- CLZ/CLS -------------------- */ -+ /* 30 28 24 20 15 9 4 -+ sf 10 1101 0110 00000 00010 0 n d CLZ Rd, Rn -+ sf 10 1101 0110 00000 00010 1 n d CLS Rd, Rn -+ */ -+ if (INSN(30,21) == BITS10(1,0,1,1,0,1,0,1,1,0) -+ && INSN(20,11) == BITS10(0,0,0,0,0,0,0,0,1,0)) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool isCLS = INSN(10,10) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp src = newTemp(Ity_I64); -+ IRTemp dst = newTemp(Ity_I64); -+ if (!isCLS) { // CLS not yet supported -+ if (is64) { -+ assign(src, getIReg64orZR(nn)); -+ assign(dst, IRExpr_ITE(binop(Iop_CmpEQ64, mkexpr(src), mkU64(0)), -+ mkU64(64), -+ unop(Iop_Clz64, mkexpr(src)))); -+ putIReg64orZR(dd, mkexpr(dst)); -+ } else { -+ assign(src, binop(Iop_Shl64, -+ unop(Iop_32Uto64, getIReg32orZR(nn)), mkU8(32))); -+ assign(dst, IRExpr_ITE(binop(Iop_CmpEQ64, mkexpr(src), mkU64(0)), -+ mkU64(32), -+ unop(Iop_Clz64, mkexpr(src)))); -+ putIReg32orZR(dd, unop(Iop_64to32, mkexpr(dst))); -+ } -+ DIP("cl%c %s, %s\n", -+ isCLS ? 's' : 'z', nameIRegOrZR(is64, dd), nameIRegOrZR(is64, nn)); -+ return True; -+ } -+ } -+ -+ /* -------------------- LSLV/LSRV/ASRV -------------------- */ -+ /* 30 28 20 15 11 9 4 -+ sf 00 1101 0110 m 0010 00 n d LSLV Rd,Rn,Rm -+ sf 00 1101 0110 m 0010 01 n d LSRV Rd,Rn,Rm -+ sf 00 1101 0110 m 0010 10 n d ASRV Rd,Rn,Rm -+ */ -+ if (INSN(30,21) == BITS10(0,0,1,1,0,1,0,1,1,0) -+ && INSN(15,12) == BITS4(0,0,1,0) && INSN(11,10) < BITS2(1,1)) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ UInt op = INSN(11,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = is64 ? Ity_I64 : Ity_I32; -+ IRTemp srcL = newTemp(ty); -+ IRTemp srcR = newTemp(Ity_I8); -+ IRTemp res = newTemp(ty); -+ IROp iop = Iop_INVALID; -+ assign(srcL, getIRegOrZR(is64, nn)); -+ assign(srcR, -+ unop(Iop_64to8, -+ binop(Iop_And64, -+ getIReg64orZR(mm), mkU64(is64 ? 63 : 31)))); -+ switch (op) { -+ case BITS2(0,0): iop = mkSHL(ty); break; -+ case BITS2(0,1): iop = mkSHR(ty); break; -+ case BITS2(1,0): iop = mkSAR(ty); break; -+ default: vassert(0); -+ } -+ assign(res, binop(iop, mkexpr(srcL), mkexpr(srcR))); -+ putIRegOrZR(is64, dd, mkexpr(res)); -+ vassert(op < 3); -+ const HChar* names[3] = { "lslv", "lsrv", "asrv" }; -+ DIP("%s %s, %s, %s\n", -+ names[op], nameIRegOrZR(is64,dd), -+ nameIRegOrZR(is64,nn), nameIRegOrZR(is64,mm)); -+ return True; -+ } -+ -+ /* -------------------- SDIV/UDIV -------------------- */ -+ /* 30 28 20 15 10 9 4 -+ sf 00 1101 0110 m 00001 1 n d SDIV Rd,Rn,Rm -+ sf 00 1101 0110 m 00001 0 n d UDIV Rd,Rn,Rm -+ */ -+ if (INSN(30,21) == BITS10(0,0,1,1,0,1,0,1,1,0) -+ && INSN(15,11) == BITS5(0,0,0,0,1)) { -+ Bool is64 = INSN(31,31) == 1; -+ UInt mm = INSN(20,16); -+ Bool isS = INSN(10,10) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (isS) { -+ putIRegOrZR(is64, dd, binop(is64 ? Iop_DivS64 : Iop_DivS32, -+ getIRegOrZR(is64, nn), -+ getIRegOrZR(is64, mm))); -+ } else { -+ putIRegOrZR(is64, dd, binop(is64 ? Iop_DivU64 : Iop_DivU32, -+ getIRegOrZR(is64, nn), -+ getIRegOrZR(is64, mm))); -+ } -+ DIP("%cdiv %s, %s, %s\n", isS ? 's' : 'u', -+ nameIRegOrZR(is64, dd), -+ nameIRegOrZR(is64, nn), nameIRegOrZR(is64, mm)); -+ return True; -+ } -+ -+ /* ------------------ {S,U}M{ADD,SUB}L ------------------ */ -+ /* 31 23 20 15 14 9 4 -+ 1001 1011 101 m 0 a n d UMADDL Xd,Wn,Wm,Xa -+ 1001 1011 001 m 0 a n d SMADDL Xd,Wn,Wm,Xa -+ 1001 1011 101 m 1 a n d UMSUBL Xd,Wn,Wm,Xa -+ 1001 1011 001 m 1 a n d SMSUBL Xd,Wn,Wm,Xa -+ with operation -+ Xd = Xa +/- (Wn *u/s Wm) -+ */ -+ if (INSN(31,24) == BITS8(1,0,0,1,1,0,1,1) && INSN(22,21) == BITS2(0,1)) { -+ Bool isU = INSN(23,23) == 1; -+ UInt mm = INSN(20,16); -+ Bool isAdd = INSN(15,15) == 0; -+ UInt aa = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp wN = newTemp(Ity_I32); -+ IRTemp wM = newTemp(Ity_I32); -+ IRTemp xA = newTemp(Ity_I64); -+ IRTemp muld = newTemp(Ity_I64); -+ IRTemp res = newTemp(Ity_I64); -+ assign(wN, getIReg32orZR(nn)); -+ assign(wM, getIReg32orZR(mm)); -+ assign(xA, getIReg64orZR(aa)); -+ assign(muld, binop(isU ? Iop_MullU32 : Iop_MullS32, -+ mkexpr(wN), mkexpr(wM))); -+ assign(res, binop(isAdd ? Iop_Add64 : Iop_Sub64, -+ mkexpr(xA), mkexpr(muld))); -+ putIReg64orZR(dd, mkexpr(res)); -+ DIP("%cm%sl %s, %s, %s, %s\n", isU ? 'u' : 's', isAdd ? "add" : "sub", -+ nameIReg64orZR(dd), nameIReg32orZR(nn), -+ nameIReg32orZR(mm), nameIReg64orZR(aa)); -+ return True; -+ } -+ vex_printf("ARM64 front end: data_processing_register\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Load and Store instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Generate the EA for a "reg + reg" style amode. This is done from -+ parts of the insn, but for sanity checking sake it takes the whole -+ insn. This appears to depend on insn[15:12], with opt=insn[15:13] -+ and S=insn[12]: -+ -+ The possible forms, along with their opt:S values, are: -+ 011:0 Xn|SP + Xm -+ 111:0 Xn|SP + Xm -+ 011:1 Xn|SP + Xm * transfer_szB -+ 111:1 Xn|SP + Xm * transfer_szB -+ 010:0 Xn|SP + 32Uto64(Wm) -+ 010:1 Xn|SP + 32Uto64(Wm) * transfer_szB -+ 110:0 Xn|SP + 32Sto64(Wm) -+ 110:1 Xn|SP + 32Sto64(Wm) * transfer_szB -+ -+ Rm is insn[20:16]. Rn is insn[9:5]. Rt is insn[4:0]. Log2 of -+ the transfer size is insn[23,31,30]. For integer loads/stores, -+ insn[23] is zero, hence szLg2 can be at most 3 in such cases. -+ -+ If the decoding fails, it returns IRTemp_INVALID. -+ -+ isInt is True iff this is decoding is for transfers to/from integer -+ registers. If False it is for transfers to/from vector registers. -+*/ -+static IRTemp gen_indexed_EA ( /*OUT*/HChar* buf, UInt insn, Bool isInt ) -+{ -+ UInt optS = SLICE_UInt(insn, 15, 12); -+ UInt mm = SLICE_UInt(insn, 20, 16); -+ UInt nn = SLICE_UInt(insn, 9, 5); -+ UInt szLg2 = (isInt ? 0 : (SLICE_UInt(insn, 23, 23) << 2)) -+ | SLICE_UInt(insn, 31, 30); // Log2 of the size -+ -+ buf[0] = 0; -+ -+ /* Sanity checks, that this really is a load/store insn. */ -+ if (SLICE_UInt(insn, 11, 10) != BITS2(1,0)) -+ goto fail; -+ -+ if (isInt -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,0,1,1)/*LDR*/ -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,0,0,1)/*STR*/ -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,1,0,1)/*LDRSbhw Xt*/ -+ && SLICE_UInt(insn, 29, 21) != BITS9(1,1,1,0,0,0,1,1,1))/*LDRSbhw Wt*/ -+ goto fail; -+ -+ if (!isInt -+ && SLICE_UInt(insn, 29, 24) != BITS6(1,1,1,1,0,0)) /*LDR/STR*/ -+ goto fail; -+ -+ /* Throw out non-verified but possibly valid cases. */ -+ switch (szLg2) { -+ case BITS3(0,0,0): break; // 8 bit, valid for both int and vec -+ case BITS3(0,0,1): break; // 16 bit, valid for both int and vec -+ case BITS3(0,1,0): break; // 32 bit, valid for both int and vec -+ case BITS3(0,1,1): break; // 64 bit, valid for both int and vec -+ case BITS3(1,0,0): // can only ever be valid for the vector case -+ if (isInt) goto fail; else goto fail; -+ case BITS3(1,0,1): // these sizes are never valid -+ case BITS3(1,1,0): -+ case BITS3(1,1,1): goto fail; -+ -+ default: vassert(0); -+ } -+ -+ IRExpr* rhs = NULL; -+ switch (optS) { -+ case BITS4(1,1,1,0): goto fail; //ATC -+ case BITS4(0,1,1,0): -+ rhs = getIReg64orZR(mm); -+ vex_sprintf(buf, "[%s, %s]", -+ nameIReg64orZR(nn), nameIReg64orZR(mm)); -+ break; -+ case BITS4(1,1,1,1): goto fail; //ATC -+ case BITS4(0,1,1,1): -+ rhs = binop(Iop_Shl64, getIReg64orZR(mm), mkU8(szLg2)); -+ vex_sprintf(buf, "[%s, %s lsl %u]", -+ nameIReg64orZR(nn), nameIReg64orZR(mm), szLg2); -+ break; -+ case BITS4(0,1,0,0): -+ rhs = unop(Iop_32Uto64, getIReg32orZR(mm)); -+ vex_sprintf(buf, "[%s, %s uxtx]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm)); -+ break; -+ case BITS4(0,1,0,1): -+ rhs = binop(Iop_Shl64, -+ unop(Iop_32Uto64, getIReg32orZR(mm)), mkU8(szLg2)); -+ vex_sprintf(buf, "[%s, %s uxtx, lsl %u]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm), szLg2); -+ break; -+ case BITS4(1,1,0,0): -+ rhs = unop(Iop_32Sto64, getIReg32orZR(mm)); -+ vex_sprintf(buf, "[%s, %s sxtx]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm)); -+ break; -+ case BITS4(1,1,0,1): -+ rhs = binop(Iop_Shl64, -+ unop(Iop_32Sto64, getIReg32orZR(mm)), mkU8(szLg2)); -+ vex_sprintf(buf, "[%s, %s sxtx, lsl %u]", -+ nameIReg64orZR(nn), nameIReg32orZR(mm), szLg2); -+ break; -+ default: -+ /* The rest appear to be genuinely invalid */ -+ goto fail; -+ } -+ -+ vassert(rhs); -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, binop(Iop_Add64, getIReg64orSP(nn), rhs)); -+ return res; -+ -+ fail: -+ vex_printf("gen_indexed_EA: unhandled case optS == 0x%x\n", optS); -+ return IRTemp_INVALID; -+} -+ -+ -+/* Generate an 8/16/32/64 bit integer store to ADDR for the lowest -+ bits of DATAE :: Ity_I64. */ -+static void gen_narrowing_store ( UInt szB, IRTemp addr, IRExpr* dataE ) -+{ -+ IRExpr* addrE = mkexpr(addr); -+ switch (szB) { -+ case 8: -+ storeLE(addrE, dataE); -+ break; -+ case 4: -+ storeLE(addrE, unop(Iop_64to32, dataE)); -+ break; -+ case 2: -+ storeLE(addrE, unop(Iop_64to16, dataE)); -+ break; -+ case 1: -+ storeLE(addrE, unop(Iop_64to8, dataE)); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+ -+/* Generate an 8/16/32/64 bit unsigned widening load from ADDR, -+ placing the result in an Ity_I64 temporary. */ -+static IRTemp gen_zwidening_load ( UInt szB, IRTemp addr ) -+{ -+ IRTemp res = newTemp(Ity_I64); -+ IRExpr* addrE = mkexpr(addr); -+ switch (szB) { -+ case 8: -+ assign(res, loadLE(Ity_I64,addrE)); -+ break; -+ case 4: -+ assign(res, unop(Iop_32Uto64, loadLE(Ity_I32,addrE))); -+ break; -+ case 2: -+ assign(res, unop(Iop_16Uto64, loadLE(Ity_I16,addrE))); -+ break; -+ case 1: -+ assign(res, unop(Iop_8Uto64, loadLE(Ity_I8,addrE))); -+ break; -+ default: -+ vassert(0); -+ } -+ return res; -+} -+ -+ -+static -+Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ------------ LDR,STR (immediate, uimm12) ----------- */ -+ /* uimm12 is scaled by the transfer size -+ -+ 31 29 26 21 9 4 -+ | | | | | | -+ 11 111 00100 imm12 nn tt STR Xt, [Xn|SP, #imm12 * 8] -+ 11 111 00101 imm12 nn tt LDR Xt, [Xn|SP, #imm12 * 8] -+ -+ 10 111 00100 imm12 nn tt STR Wt, [Xn|SP, #imm12 * 4] -+ 10 111 00101 imm12 nn tt LDR Wt, [Xn|SP, #imm12 * 4] -+ -+ 01 111 00100 imm12 nn tt STRH Wt, [Xn|SP, #imm12 * 2] -+ 01 111 00101 imm12 nn tt LDRH Wt, [Xn|SP, #imm12 * 2] -+ -+ 00 111 00100 imm12 nn tt STRB Wt, [Xn|SP, #imm12 * 1] -+ 00 111 00101 imm12 nn tt LDRB Wt, [Xn|SP, #imm12 * 1] -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,1,0)) { -+ UInt szLg2 = INSN(31,30); -+ UInt szB = 1 << szLg2; -+ Bool isLD = INSN(22,22) == 1; -+ UInt offs = INSN(21,10) * szB; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp ta = newTemp(Ity_I64); -+ assign(ta, binop(Iop_Add64, getIReg64orSP(nn), mkU64(offs))); -+ if (nn == 31) { /* FIXME generate stack alignment check */ } -+ vassert(szLg2 < 4); -+ if (isLD) { -+ putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, ta))); -+ } else { -+ gen_narrowing_store(szB, ta, getIReg64orZR(tt)); -+ } -+ const HChar* ld_name[4] = { "ldrb", "ldrh", "ldr", "ldr" }; -+ const HChar* st_name[4] = { "strb", "strh", "str", "str" }; -+ DIP("%s %s, [%s, #%u]\n", -+ (isLD ? ld_name : st_name)[szLg2], nameIRegOrZR(szB == 8, tt), -+ nameIReg64orSP(nn), offs); -+ return True; -+ } -+ -+ /* ------------ LDUR,STUR (immediate, simm9) ----------- */ -+ /* -+ 31 29 26 20 11 9 4 -+ | | | | | | | -+ (at-Rn-then-Rn=EA) | | | -+ sz 111 00000 0 imm9 01 Rn Rt STR Rt, [Xn|SP], #simm9 -+ sz 111 00001 0 imm9 01 Rn Rt LDR Rt, [Xn|SP], #simm9 -+ -+ (at-EA-then-Rn=EA) -+ sz 111 00000 0 imm9 11 Rn Rt STR Rt, [Xn|SP, #simm9]! -+ sz 111 00001 0 imm9 11 Rn Rt LDR Rt, [Xn|SP, #simm9]! -+ -+ (at-EA) -+ sz 111 00000 0 imm9 00 Rn Rt STR Rt, [Xn|SP, #simm9] -+ sz 111 00001 0 imm9 00 Rn Rt LDR Rt, [Xn|SP, #simm9] -+ -+ simm9 is unscaled. -+ -+ The case 'wback && Rn == Rt && Rt != 31' is disallowed. In the -+ load case this is because would create two competing values for -+ Rt. In the store case the reason is unclear, but the spec -+ disallows it anyway. -+ -+ Stores are narrowing, loads are unsigned widening. sz encodes -+ the transfer size in the normal way: 00=1, 01=2, 10=4, 11=8. -+ */ -+ if ((INSN(29,21) & BITS9(1,1,1, 1,1,1,1,0, 1)) -+ == BITS9(1,1,1, 0,0,0,0,0, 0)) { -+ UInt szLg2 = INSN(31,30); -+ UInt szB = 1 << szLg2; -+ Bool isLoad = INSN(22,22) == 1; -+ UInt imm9 = INSN(20,12); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ Bool wBack = INSN(10,10) == 1; -+ UInt how = INSN(11,10); -+ if (how == BITS2(1,0) || (wBack && nn == tt && tt != 31)) { -+ /* undecodable; fall through */ -+ } else { -+ if (nn == 31) { /* FIXME generate stack alignment check */ } -+ -+ // Compute the transfer address TA and the writeback address WA. -+ IRTemp tRN = newTemp(Ity_I64); -+ assign(tRN, getIReg64orSP(nn)); -+ IRTemp tEA = newTemp(Ity_I64); -+ Long simm9 = (Long)sx_to_64(imm9, 9); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ -+ IRTemp tTA = newTemp(Ity_I64); -+ IRTemp tWA = newTemp(Ity_I64); -+ switch (how) { -+ case BITS2(0,1): -+ assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,1): -+ assign(tTA, mkexpr(tEA)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(0,0): -+ assign(tTA, mkexpr(tEA)); /* tWA is unused */ break; -+ default: -+ vassert(0); /* NOTREACHED */ -+ } -+ -+ /* Normally rN would be updated after the transfer. However, in -+ the special case typifed by -+ str x30, [sp,#-16]! -+ it is necessary to update SP before the transfer, (1) -+ because Memcheck will otherwise complain about a write -+ below the stack pointer, and (2) because the segfault -+ stack extension mechanism will otherwise extend the stack -+ only down to SP before the instruction, which might not be -+ far enough, if the -16 bit takes the actual access -+ address to the next page. -+ */ -+ Bool earlyWBack -+ = wBack && simm9 < 0 && szB == 8 -+ && how == BITS2(1,1) && nn == 31 && !isLoad && tt != nn; -+ -+ if (wBack && earlyWBack) -+ putIReg64orSP(nn, mkexpr(tEA)); -+ -+ if (isLoad) { -+ putIReg64orZR(tt, mkexpr(gen_zwidening_load(szB, tTA))); -+ } else { -+ gen_narrowing_store(szB, tTA, getIReg64orZR(tt)); -+ } -+ -+ if (wBack && !earlyWBack) -+ putIReg64orSP(nn, mkexpr(tEA)); -+ -+ const HChar* ld_name[4] = { "ldurb", "ldurh", "ldur", "ldur" }; -+ const HChar* st_name[4] = { "sturb", "sturh", "stur", "stur" }; -+ const HChar* fmt_str = NULL; -+ switch (how) { -+ case BITS2(0,1): -+ fmt_str = "%s %s, [%s], #%lld (at-Rn-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,1): -+ fmt_str = "%s %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n"; -+ break; -+ case BITS2(0,0): -+ fmt_str = "%s %s, [%s, #%lld] (at-Rn)\n"; -+ break; -+ default: -+ vassert(0); -+ } -+ DIP(fmt_str, (isLoad ? ld_name : st_name)[szLg2], -+ nameIRegOrZR(szB == 8, tt), -+ nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ } -+ -+ /* -------- LDP,STP (immediate, simm7) (INT REGS) -------- */ -+ /* L==1 => mm==LD -+ L==0 => mm==ST -+ x==0 => 32 bit transfers, and zero extended loads -+ x==1 => 64 bit transfers -+ simm7 is scaled by the (single-register) transfer size -+ -+ (at-Rn-then-Rn=EA) -+ x0 101 0001 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP], #imm -+ -+ (at-EA-then-Rn=EA) -+ x0 101 0011 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm]! -+ -+ (at-EA) -+ x0 101 0010 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm] -+ */ -+ -+ UInt insn_30_23 = INSN(30,23); -+ if (insn_30_23 == BITS8(0,1,0,1,0,0,0,1) -+ || insn_30_23 == BITS8(0,1,0,1,0,0,1,1) -+ || insn_30_23 == BITS8(0,1,0,1,0,0,1,0)) { -+ UInt bL = INSN(22,22); -+ UInt bX = INSN(31,31); -+ UInt bWBack = INSN(23,23); -+ UInt rT1 = INSN(4,0); -+ UInt rN = INSN(9,5); -+ UInt rT2 = INSN(14,10); -+ Long simm7 = (Long)sx_to_64(INSN(21,15), 7); -+ if ((bWBack && (rT1 == rN || rT2 == rN) && rN != 31) -+ || (bL && rT1 == rT2)) { -+ /* undecodable; fall through */ -+ } else { -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ -+ // Compute the transfer address TA and the writeback address WA. -+ IRTemp tRN = newTemp(Ity_I64); -+ assign(tRN, getIReg64orSP(rN)); -+ IRTemp tEA = newTemp(Ity_I64); -+ simm7 = (bX ? 8 : 4) * simm7; -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm7))); -+ -+ IRTemp tTA = newTemp(Ity_I64); -+ IRTemp tWA = newTemp(Ity_I64); -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,1): -+ assign(tTA, mkexpr(tEA)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,0): -+ assign(tTA, mkexpr(tEA)); /* tWA is unused */ break; -+ default: -+ vassert(0); /* NOTREACHED */ -+ } -+ -+ /* Normally rN would be updated after the transfer. However, in -+ the special case typifed by -+ stp x29, x30, [sp,#-112]! -+ it is necessary to update SP before the transfer, (1) -+ because Memcheck will otherwise complain about a write -+ below the stack pointer, and (2) because the segfault -+ stack extension mechanism will otherwise extend the stack -+ only down to SP before the instruction, which might not be -+ far enough, if the -112 bit takes the actual access -+ address to the next page. -+ */ -+ Bool earlyWBack -+ = bWBack && simm7 < 0 -+ && INSN(24,23) == BITS2(1,1) && rN == 31 && bL == 0; -+ -+ if (bWBack && earlyWBack) -+ putIReg64orSP(rN, mkexpr(tEA)); -+ -+ /**/ if (bL == 1 && bX == 1) { -+ // 64 bit load -+ putIReg64orZR(rT1, loadLE(Ity_I64, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(0)))); -+ putIReg64orZR(rT2, loadLE(Ity_I64, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(8)))); -+ } else if (bL == 1 && bX == 0) { -+ // 32 bit load -+ putIReg32orZR(rT1, loadLE(Ity_I32, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(0)))); -+ putIReg32orZR(rT2, loadLE(Ity_I32, -+ binop(Iop_Add64,mkexpr(tTA),mkU64(4)))); -+ } else if (bL == 0 && bX == 1) { -+ // 64 bit store -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(0)), -+ getIReg64orZR(rT1)); -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(8)), -+ getIReg64orZR(rT2)); -+ } else { -+ vassert(bL == 0 && bX == 0); -+ // 32 bit store -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(0)), -+ getIReg32orZR(rT1)); -+ storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(4)), -+ getIReg32orZR(rT2)); -+ } -+ -+ if (bWBack && !earlyWBack) -+ putIReg64orSP(rN, mkexpr(tEA)); -+ -+ const HChar* fmt_str = NULL; -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,1): -+ fmt_str = "%sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,0): -+ fmt_str = "%sp %s, %s, [%s, #%lld] (at-Rn)\n"; -+ break; -+ default: -+ vassert(0); -+ } -+ DIP(fmt_str, bL == 0 ? "st" : "ld", -+ nameIRegOrZR(bX == 1, rT1), -+ nameIRegOrZR(bX == 1, rT2), -+ nameIReg64orSP(rN), simm7); -+ return True; -+ } -+ } -+ -+ /* ---------------- LDR (literal, int reg) ---------------- */ -+ /* 31 29 23 4 -+ 00 011 000 imm19 Rt LDR Wt, [PC + sxTo64(imm19 << 2)] -+ 01 011 000 imm19 Rt LDR Xt, [PC + sxTo64(imm19 << 2)] -+ 10 011 000 imm19 Rt LDRSW Xt, [PC + sxTo64(imm19 << 2)] -+ 11 011 000 imm19 Rt prefetch [PC + sxTo64(imm19 << 2)] -+ Just handles the first two cases for now. -+ */ -+ if (INSN(29,24) == BITS6(0,1,1,0,0,0) && INSN(31,31) == 0) { -+ UInt imm19 = INSN(23,5); -+ UInt rT = INSN(4,0); -+ UInt bX = INSN(30,30); -+ ULong ea = guest_PC_curr_instr + sx_to_64(imm19 << 2, 21); -+ if (bX) { -+ putIReg64orZR(rT, loadLE(Ity_I64, mkU64(ea))); -+ } else { -+ putIReg32orZR(rT, loadLE(Ity_I32, mkU64(ea))); -+ } -+ DIP("ldr %s, 0x%llx (literal)\n", nameIRegOrZR(bX == 1, rT), ea); -+ return True; -+ } -+ -+ /* -------------- {LD,ST}R (integer register) --------------- */ -+ /* 31 29 20 15 12 11 9 4 -+ | | | | | | | | -+ 11 111000011 Rm option S 10 Rn Rt LDR Xt, [Xn|SP, R{ext/sh}] -+ 10 111000011 Rm option S 10 Rn Rt LDR Wt, [Xn|SP, R{ext/sh}] -+ 01 111000011 Rm option S 10 Rn Rt LDRH Wt, [Xn|SP, R{ext/sh}] -+ 00 111000011 Rm option S 10 Rn Rt LDRB Wt, [Xn|SP, R{ext/sh}] -+ -+ 11 111000001 Rm option S 10 Rn Rt STR Xt, [Xn|SP, R{ext/sh}] -+ 10 111000001 Rm option S 10 Rn Rt STR Wt, [Xn|SP, R{ext/sh}] -+ 01 111000001 Rm option S 10 Rn Rt STRH Wt, [Xn|SP, R{ext/sh}] -+ 00 111000001 Rm option S 10 Rn Rt STRB Wt, [Xn|SP, R{ext/sh}] -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,0) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ HChar dis_buf[64]; -+ UInt szLg2 = INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt tt = INSN(4,0); -+ IRTemp ea = gen_indexed_EA(dis_buf, insn, True/*to/from int regs*/); -+ if (ea != IRTemp_INVALID) { -+ switch (szLg2) { -+ case 3: /* 64 bit */ -+ if (isLD) { -+ putIReg64orZR(tt, loadLE(Ity_I64, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getIReg64orZR(tt)); -+ DIP("str %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } -+ break; -+ case 2: /* 32 bit */ -+ if (isLD) { -+ putIReg32orZR(tt, loadLE(Ity_I32, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getIReg32orZR(tt)); -+ DIP("str %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ break; -+ case 1: /* 16 bit */ -+ if (isLD) { -+ putIReg64orZR(tt, unop(Iop_16Uto64, -+ loadLE(Ity_I16, mkexpr(ea)))); -+ DIP("ldruh %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), unop(Iop_64to16, getIReg64orZR(tt))); -+ DIP("strh %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ break; -+ case 0: /* 8 bit */ -+ if (isLD) { -+ putIReg64orZR(tt, unop(Iop_8Uto64, -+ loadLE(Ity_I8, mkexpr(ea)))); -+ DIP("ldrub %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), unop(Iop_64to8, getIReg64orZR(tt))); -+ DIP("strb %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ } -+ -+ /* -------------- LDRS{B,H,W} (uimm12) -------------- */ -+ /* 31 29 26 23 21 9 4 -+ 10 111 001 10 imm12 n t LDRSW Xt, [Xn|SP, #pimm12 * 4] -+ 01 111 001 1x imm12 n t LDRSH Rt, [Xn|SP, #pimm12 * 2] -+ 00 111 001 1x imm12 n t LDRSB Rt, [Xn|SP, #pimm12 * 1] -+ where -+ Rt is Wt when x==1, Xt when x==0 -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,1,1)) { -+ /* Further checks on bits 31:30 and 22 */ -+ Bool valid = False; -+ switch ((INSN(31,30) << 1) | INSN(22,22)) { -+ case BITS3(1,0,0): -+ case BITS3(0,1,0): case BITS3(0,1,1): -+ case BITS3(0,0,0): case BITS3(0,0,1): -+ valid = True; -+ break; -+ } -+ if (valid) { -+ UInt szLg2 = INSN(31,30); -+ UInt bitX = INSN(22,22); -+ UInt imm12 = INSN(21,10); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ UInt szB = 1 << szLg2; -+ IRExpr* ea = binop(Iop_Add64, -+ getIReg64orSP(nn), mkU64(imm12 * szB)); -+ switch (szB) { -+ case 4: -+ vassert(bitX == 0); -+ putIReg64orZR(tt, unop(Iop_32Sto64, loadLE(Ity_I32, ea))); -+ DIP("ldrsw %s, [%s, #%u]\n", nameIReg64orZR(tt), -+ nameIReg64orSP(nn), imm12 * szB); -+ break; -+ case 2: -+ if (bitX == 1) { -+ putIReg32orZR(tt, unop(Iop_16Sto32, loadLE(Ity_I16, ea))); -+ } else { -+ putIReg64orZR(tt, unop(Iop_16Sto64, loadLE(Ity_I16, ea))); -+ } -+ DIP("ldrsh %s, [%s, #%u]\n", -+ nameIRegOrZR(bitX == 0, tt), -+ nameIReg64orSP(nn), imm12 * szB); -+ break; -+ case 1: -+ if (bitX == 1) { -+ putIReg32orZR(tt, unop(Iop_8Sto32, loadLE(Ity_I8, ea))); -+ } else { -+ putIReg64orZR(tt, unop(Iop_8Sto64, loadLE(Ity_I8, ea))); -+ } -+ DIP("ldrsb %s, [%s, #%u]\n", -+ nameIRegOrZR(bitX == 0, tt), -+ nameIReg64orSP(nn), imm12 * szB); -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------- LDRS{B,H,W} (simm9, upd) -------------- */ -+ /* (at-Rn-then-Rn=EA) -+ 31 29 23 21 20 11 9 4 -+ 00 111 000 1x 0 imm9 01 n t LDRSB Rt, [Xn|SP], #simm9 -+ 01 111 000 1x 0 imm9 01 n t LDRSH Rt, [Xn|SP], #simm9 -+ 10 111 000 10 0 imm9 01 n t LDRSW Xt, [Xn|SP], #simm9 -+ -+ (at-EA-then-Rn=EA) -+ 00 111 000 1x 0 imm9 11 n t LDRSB Rt, [Xn|SP, #simm9]! -+ 01 111 000 1x 0 imm9 11 n t LDRSH Rt, [Xn|SP, #simm9]! -+ 10 111 000 10 0 imm9 11 n t LDRSW Xt, [Xn|SP, #simm9]! -+ where -+ Rt is Wt when x==1, Xt when x==0 -+ transfer-at-Rn when [11]==0, at EA when [11]==1 -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,1) -+ && INSN(21,21) == 0 && INSN(10,10) == 1) { -+ /* Further checks on bits 31:30 and 22 */ -+ Bool valid = False; -+ switch ((INSN(31,30) << 1) | INSN(22,22)) { -+ case BITS3(1,0,0): // LDRSW Xt -+ case BITS3(0,1,0): case BITS3(0,1,1): // LDRSH Xt, Wt -+ case BITS3(0,0,0): case BITS3(0,0,1): // LDRSB Xt, Wt -+ valid = True; -+ break; -+ } -+ if (valid) { -+ UInt szLg2 = INSN(31,30); -+ UInt imm9 = INSN(20,12); -+ Bool atRN = INSN(11,11) == 0; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tRN = newTemp(Ity_I64); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRTemp tTA = IRTemp_INVALID; -+ ULong simm9 = sx_to_64(imm9, 9); -+ Bool is64 = INSN(22,22) == 0; -+ assign(tRN, getIReg64orSP(nn)); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ tTA = atRN ? tRN : tEA; -+ HChar ch = '?'; -+ /* There are 5 cases: -+ byte load, SX to 64 -+ byte load, SX to 32, ZX to 64 -+ halfword load, SX to 64 -+ halfword load, SX to 32, ZX to 64 -+ word load, SX to 64 -+ The ifs below handle them in the listed order. -+ */ -+ if (szLg2 == 0) { -+ ch = 'b'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_8Sto64, -+ loadLE(Ity_I8, mkexpr(tTA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_8Sto32, -+ loadLE(Ity_I8, mkexpr(tTA)))); -+ } -+ } -+ else if (szLg2 == 1) { -+ ch = 'h'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_16Sto64, -+ loadLE(Ity_I16, mkexpr(tTA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_16Sto32, -+ loadLE(Ity_I16, mkexpr(tTA)))); -+ } -+ } -+ else if (szLg2 == 2 && is64) { -+ ch = 'w'; -+ putIReg64orZR(tt, unop(Iop_32Sto64, -+ loadLE(Ity_I32, mkexpr(tTA)))); -+ } -+ else { -+ vassert(0); -+ } -+ putIReg64orSP(nn, mkexpr(tEA)); -+ DIP(atRN ? "ldrs%c %s, [%s], #%lld\n" : "ldrs%c %s, [%s, #%lld]!", -+ ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------- LDRS{B,H,W} (simm9, noUpd) -------------- */ -+ /* 31 29 23 21 20 11 9 4 -+ 00 111 000 1x 0 imm9 00 n t LDURSB Rt, [Xn|SP, #simm9] -+ 01 111 000 1x 0 imm9 00 n t LDURSH Rt, [Xn|SP, #simm9] -+ 10 111 000 10 0 imm9 00 n t LDURSW Xt, [Xn|SP, #simm9] -+ where -+ Rt is Wt when x==1, Xt when x==0 -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,1) -+ && INSN(21,21) == 0 && INSN(11,10) == BITS2(0,0)) { -+ /* Further checks on bits 31:30 and 22 */ -+ Bool valid = False; -+ switch ((INSN(31,30) << 1) | INSN(22,22)) { -+ case BITS3(1,0,0): // LDURSW Xt -+ case BITS3(0,1,0): case BITS3(0,1,1): // LDURSH Xt, Wt -+ case BITS3(0,0,0): case BITS3(0,0,1): // LDURSB Xt, Wt -+ valid = True; -+ break; -+ } -+ if (valid) { -+ UInt szLg2 = INSN(31,30); -+ UInt imm9 = INSN(20,12); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tRN = newTemp(Ity_I64); -+ IRTemp tEA = newTemp(Ity_I64); -+ ULong simm9 = sx_to_64(imm9, 9); -+ Bool is64 = INSN(22,22) == 0; -+ assign(tRN, getIReg64orSP(nn)); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ HChar ch = '?'; -+ /* There are 5 cases: -+ byte load, SX to 64 -+ byte load, SX to 32, ZX to 64 -+ halfword load, SX to 64 -+ halfword load, SX to 32, ZX to 64 -+ word load, SX to 64 -+ The ifs below handle them in the listed order. -+ */ -+ if (szLg2 == 0) { -+ ch = 'b'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_8Sto64, -+ loadLE(Ity_I8, mkexpr(tEA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_8Sto32, -+ loadLE(Ity_I8, mkexpr(tEA)))); -+ } -+ } -+ else if (szLg2 == 1) { -+ ch = 'h'; -+ if (is64) { -+ putIReg64orZR(tt, unop(Iop_16Sto64, -+ loadLE(Ity_I16, mkexpr(tEA)))); -+ } else { -+ putIReg32orZR(tt, unop(Iop_16Sto32, -+ loadLE(Ity_I16, mkexpr(tEA)))); -+ } -+ } -+ else if (szLg2 == 2 && is64) { -+ ch = 'w'; -+ putIReg64orZR(tt, unop(Iop_32Sto64, -+ loadLE(Ity_I32, mkexpr(tEA)))); -+ } -+ else { -+ vassert(0); -+ } -+ DIP("ldurs%c %s, [%s, #%lld]", -+ ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------- LDP,STP (immediate, simm7) (FP&VEC) -------- */ -+ /* L==1 => mm==LD -+ L==0 => mm==ST -+ sz==00 => 32 bit (S) transfers -+ sz==01 => 64 bit (D) transfers -+ sz==10 => 128 bit (Q) transfers -+ sz==11 isn't allowed -+ simm7 is scaled by the (single-register) transfer size -+ -+ 31 29 22 21 14 9 4 -+ sz 101 1001 L imm7 t2 n t1 mmP SDQt1, SDQt2, [Xn|SP], #imm -+ (at-Rn-then-Rn=EA) -+ -+ sz 101 1011 L imm7 t2 n t1 mmP SDQt1, SDQt2, [Xn|SP, #imm]! -+ (at-EA-then-Rn=EA) -+ -+ sz 101 1010 L imm7 t2 n t1 mmP SDQt1, SDQt2, [Xn|SP, #imm] -+ (at-EA) -+ */ -+ -+ UInt insn_29_23 = INSN(29,23); -+ if (insn_29_23 == BITS7(1,0,1,1,0,0,1) -+ || insn_29_23 == BITS7(1,0,1,1,0,1,1) -+ || insn_29_23 == BITS7(1,0,1,1,0,1,0)) { -+ UInt szSlg2 = INSN(31,30); // log2 of the xfer size in 32-bit units -+ Bool isLD = INSN(22,22) == 1; -+ Bool wBack = INSN(23,23) == 1; -+ Long simm7 = (Long)sx_to_64(INSN(21,15), 7); -+ UInt tt2 = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt tt1 = INSN(4,0); -+ if (szSlg2 == BITS2(1,1) || (isLD && tt1 == tt2)) { -+ /* undecodable; fall through */ -+ } else { -+ if (nn == 31) { /* FIXME generate stack alignment check */ } -+ -+ // Compute the transfer address TA and the writeback address WA. -+ UInt szB = 4 << szSlg2; /* szB is the per-register size */ -+ IRTemp tRN = newTemp(Ity_I64); -+ assign(tRN, getIReg64orSP(nn)); -+ IRTemp tEA = newTemp(Ity_I64); -+ simm7 = szB * simm7; -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm7))); -+ -+ IRTemp tTA = newTemp(Ity_I64); -+ IRTemp tWA = newTemp(Ity_I64); -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,1): -+ assign(tTA, mkexpr(tEA)); assign(tWA, mkexpr(tEA)); break; -+ case BITS2(1,0): -+ assign(tTA, mkexpr(tEA)); /* tWA is unused */ break; -+ default: -+ vassert(0); /* NOTREACHED */ -+ } -+ -+ IRType ty = Ity_INVALID; -+ switch (szB) { -+ case 4: ty = Ity_F32; break; -+ case 8: ty = Ity_F64; break; -+ case 16: ty = Ity_V128; break; -+ default: vassert(0); -+ } -+ -+ /* Normally rN would be updated after the transfer. However, in -+ the special cases typifed by -+ stp q0, q1, [sp,#-512]! -+ stp d0, d1, [sp,#-512]! -+ stp s0, s1, [sp,#-512]! -+ it is necessary to update SP before the transfer, (1) -+ because Memcheck will otherwise complain about a write -+ below the stack pointer, and (2) because the segfault -+ stack extension mechanism will otherwise extend the stack -+ only down to SP before the instruction, which might not be -+ far enough, if the -512 bit takes the actual access -+ address to the next page. -+ */ -+ Bool earlyWBack -+ = wBack && simm7 < 0 -+ && INSN(24,23) == BITS2(1,1) && nn == 31 && !isLD; -+ -+ if (wBack && earlyWBack) -+ putIReg64orSP(nn, mkexpr(tEA)); -+ -+ if (isLD) { -+ if (szB < 16) { -+ putQReg128(tt1, mkV128(0x0000)); -+ } -+ putQRegLO(tt1, -+ loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(0)))); -+ if (szB < 16) { -+ putQReg128(tt2, mkV128(0x0000)); -+ } -+ putQRegLO(tt2, -+ loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(szB)))); -+ } else { -+ storeLE(binop(Iop_Add64, mkexpr(tTA), mkU64(0)), -+ getQRegLO(tt1, ty)); -+ storeLE(binop(Iop_Add64, mkexpr(tTA), mkU64(szB)), -+ getQRegLO(tt2, ty)); -+ } -+ -+ if (wBack && !earlyWBack) -+ putIReg64orSP(nn, mkexpr(tEA)); -+ -+ const HChar* fmt_str = NULL; -+ switch (INSN(24,23)) { -+ case BITS2(0,1): -+ fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,1): -+ fmt_str = "%sp %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n"; -+ break; -+ case BITS2(1,0): -+ fmt_str = "%sp %s, %s, [%s, #%lld] (at-Rn)\n"; -+ break; -+ default: -+ vassert(0); -+ } -+ DIP(fmt_str, isLD ? "ld" : "st", -+ nameQRegLO(tt1, ty), nameQRegLO(tt2, ty), -+ nameIReg64orSP(nn), simm7); -+ return True; -+ } -+ } -+ -+ /* -------------- {LD,ST}R (vector register) --------------- */ -+ /* 31 29 23 20 15 12 11 9 4 -+ | | | | | | | | | -+ 00 111100 011 Rm option S 10 Rn Rt LDR Bt, [Xn|SP, R{ext/sh}] -+ 01 111100 011 Rm option S 10 Rn Rt LDR Ht, [Xn|SP, R{ext/sh}] -+ 10 111100 011 Rm option S 10 Rn Rt LDR St, [Xn|SP, R{ext/sh}] -+ 11 111100 011 Rm option S 10 Rn Rt LDR Dt, [Xn|SP, R{ext/sh}] -+ 00 111100 111 Rm option S 10 Rn Rt LDR Qt, [Xn|SP, R{ext/sh}] -+ -+ 00 111100 001 Rm option S 10 Rn Rt STR Bt, [Xn|SP, R{ext/sh}] -+ 01 111100 001 Rm option S 10 Rn Rt STR Ht, [Xn|SP, R{ext/sh}] -+ 10 111100 001 Rm option S 10 Rn Rt STR St, [Xn|SP, R{ext/sh}] -+ 11 111100 001 Rm option S 10 Rn Rt STR Dt, [Xn|SP, R{ext/sh}] -+ 00 111100 101 Rm option S 10 Rn Rt STR Qt, [Xn|SP, R{ext/sh}] -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,0) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ HChar dis_buf[64]; -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt tt = INSN(4,0); -+ if (szLg2 >= 4) goto after_LDR_STR_vector_register; -+ IRTemp ea = gen_indexed_EA(dis_buf, insn, False/*to/from vec regs*/); -+ if (ea == IRTemp_INVALID) goto after_LDR_STR_vector_register; -+ switch (szLg2) { -+ case 0: /* 8 bit */ -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQRegLO(tt, loadLE(Ity_I8, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQRegLO(tt, Ity_I8), dis_buf); -+ } else { -+ vassert(0); //ATC -+ storeLE(mkexpr(ea), getQRegLO(tt, Ity_I8)); -+ DIP("str %s, %s\n", nameQRegLO(tt, Ity_I8), dis_buf); -+ } -+ break; -+ case 1: -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQRegLO(tt, loadLE(Ity_I16, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQRegLO(tt, Ity_I16), dis_buf); -+ } else { -+ vassert(0); //ATC -+ storeLE(mkexpr(ea), getQRegLO(tt, Ity_I16)); -+ DIP("str %s, %s\n", nameQRegLO(tt, Ity_I16), dis_buf); -+ } -+ break; -+ case 2: /* 32 bit */ -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQRegLO(tt, loadLE(Ity_I32, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQRegLO(tt, Ity_I32), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getQRegLO(tt, Ity_I32)); -+ DIP("str %s, %s\n", nameQRegLO(tt, Ity_I32), dis_buf); -+ } -+ break; -+ case 3: /* 64 bit */ -+ if (isLD) { -+ putQReg128(tt, mkV128(0x0000)); -+ putQRegLO(tt, loadLE(Ity_I64, mkexpr(ea))); -+ DIP("ldr %s, %s\n", nameQRegLO(tt, Ity_I64), dis_buf); -+ } else { -+ storeLE(mkexpr(ea), getQRegLO(tt, Ity_I64)); -+ DIP("str %s, %s\n", nameQRegLO(tt, Ity_I64), dis_buf); -+ } -+ break; -+ case 4: return False; //ATC -+ default: vassert(0); -+ } -+ return True; -+ } -+ after_LDR_STR_vector_register: -+ -+ /* ---------- LDRS{B,H,W} (integer register, SX) ---------- */ -+ /* 31 29 22 20 15 12 11 9 4 -+ | | | | | | | | | -+ 10 1110001 01 Rm opt S 10 Rn Rt LDRSW Xt, [Xn|SP, R{ext/sh}] -+ -+ 01 1110001 01 Rm opt S 10 Rn Rt LDRSH Xt, [Xn|SP, R{ext/sh}] -+ 01 1110001 11 Rm opt S 10 Rn Rt LDRSH Wt, [Xn|SP, R{ext/sh}] -+ -+ 00 1110001 01 Rm opt S 10 Rn Rt LDRSB Xt, [Xn|SP, R{ext/sh}] -+ 00 1110001 11 Rm opt S 10 Rn Rt LDRSB Wt, [Xn|SP, R{ext/sh}] -+ */ -+ if (INSN(29,23) == BITS7(1,1,1,0,0,0,1) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ HChar dis_buf[64]; -+ UInt szLg2 = INSN(31,30); -+ Bool sxTo64 = INSN(22,22) == 0; // else sx to 32 and zx to 64 -+ UInt tt = INSN(4,0); -+ if (szLg2 == 3) goto after_LDRS_integer_register; -+ IRTemp ea = gen_indexed_EA(dis_buf, insn, True/*to/from int regs*/); -+ if (ea == IRTemp_INVALID) goto after_LDRS_integer_register; -+ /* Enumerate the 5 variants explicitly. */ -+ if (szLg2 == 2/*32 bit*/ && sxTo64) { -+ putIReg64orZR(tt, unop(Iop_32Sto64, loadLE(Ity_I32, mkexpr(ea)))); -+ DIP("ldrsw %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ return True; -+ } -+ else -+ if (szLg2 == 1/*16 bit*/) { -+ if (sxTo64) { -+ putIReg64orZR(tt, unop(Iop_16Sto64, loadLE(Ity_I16, mkexpr(ea)))); -+ DIP("ldrsh %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } else { -+ putIReg32orZR(tt, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(ea)))); -+ DIP("ldrsh %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ return True; -+ } -+ else -+ if (szLg2 == 0/*8 bit*/) { -+ if (sxTo64) { -+ putIReg64orZR(tt, unop(Iop_8Sto64, loadLE(Ity_I8, mkexpr(ea)))); -+ DIP("ldrsb %s, %s\n", nameIReg64orZR(tt), dis_buf); -+ } else { -+ putIReg32orZR(tt, unop(Iop_8Sto32, loadLE(Ity_I8, mkexpr(ea)))); -+ DIP("ldrsb %s, %s\n", nameIReg32orZR(tt), dis_buf); -+ } -+ return True; -+ } -+ /* else it's an invalid combination */ -+ } -+ after_LDRS_integer_register: -+ -+ /* -------- LDR/STR (immediate, SIMD&FP, unsigned offset) -------- */ -+ /* This is the Unsigned offset variant only. The Post-Index and -+ Pre-Index variants are below. -+ -+ 31 29 23 21 9 4 -+ 00 111 101 01 imm12 n t LDR Bt, [Xn|SP + imm12 * 1] -+ 01 111 101 01 imm12 n t LDR Ht, [Xn|SP + imm12 * 2] -+ 10 111 101 01 imm12 n t LDR St, [Xn|SP + imm12 * 4] -+ 11 111 101 01 imm12 n t LDR Dt, [Xn|SP + imm12 * 8] -+ 00 111 101 11 imm12 n t LDR Qt, [Xn|SP + imm12 * 16] -+ -+ 00 111 101 00 imm12 n t STR Bt, [Xn|SP + imm12 * 1] -+ 01 111 101 00 imm12 n t STR Ht, [Xn|SP + imm12 * 2] -+ 10 111 101 00 imm12 n t STR St, [Xn|SP + imm12 * 4] -+ 11 111 101 00 imm12 n t STR Dt, [Xn|SP + imm12 * 8] -+ 00 111 101 10 imm12 n t STR Qt, [Xn|SP + imm12 * 16] -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,1) -+ && ((INSN(23,23) << 2) | INSN(31,30)) <= 4) { -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt pimm12 = INSN(21,10) << szLg2; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRType ty = preferredVectorSubTypeFromSize(1 << szLg2); -+ assign(tEA, binop(Iop_Add64, getIReg64orSP(nn), mkU64(pimm12))); -+ if (isLD) { -+ if (szLg2 < 4) { -+ putQReg128(tt, mkV128(0x0000)); -+ } -+ putQRegLO(tt, loadLE(ty, mkexpr(tEA))); -+ } else { -+ storeLE(mkexpr(tEA), getQRegLO(tt, ty)); -+ } -+ DIP("%s %s, [%s, #%u]\n", -+ isLD ? "ldr" : "str", -+ nameQRegLO(tt, ty), nameIReg64orSP(nn), pimm12); -+ return True; -+ } -+ -+ /* -------- LDR/STR (immediate, SIMD&FP, pre/post index) -------- */ -+ /* These are the Post-Index and Pre-Index variants. -+ -+ 31 29 23 20 11 9 4 -+ (at-Rn-then-Rn=EA) -+ 00 111 100 01 0 imm9 01 n t LDR Bt, [Xn|SP], #simm -+ 01 111 100 01 0 imm9 01 n t LDR Ht, [Xn|SP], #simm -+ 10 111 100 01 0 imm9 01 n t LDR St, [Xn|SP], #simm -+ 11 111 100 01 0 imm9 01 n t LDR Dt, [Xn|SP], #simm -+ 00 111 100 11 0 imm9 01 n t LDR Qt, [Xn|SP], #simm -+ -+ (at-EA-then-Rn=EA) -+ 00 111 100 01 0 imm9 11 n t LDR Bt, [Xn|SP, #simm]! -+ 01 111 100 01 0 imm9 11 n t LDR Ht, [Xn|SP, #simm]! -+ 10 111 100 01 0 imm9 11 n t LDR St, [Xn|SP, #simm]! -+ 11 111 100 01 0 imm9 11 n t LDR Dt, [Xn|SP, #simm]! -+ 00 111 100 11 0 imm9 11 n t LDR Qt, [Xn|SP, #simm]! -+ -+ Stores are the same except with bit 22 set to 0. -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,0) -+ && ((INSN(23,23) << 2) | INSN(31,30)) <= 4 -+ && INSN(21,21) == 0 && INSN(10,10) == 1) { -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt imm9 = INSN(20,12); -+ Bool atRN = INSN(11,11) == 0; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ IRTemp tRN = newTemp(Ity_I64); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRTemp tTA = IRTemp_INVALID; -+ IRType ty = preferredVectorSubTypeFromSize(1 << szLg2); -+ ULong simm9 = sx_to_64(imm9, 9); -+ assign(tRN, getIReg64orSP(nn)); -+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm9))); -+ tTA = atRN ? tRN : tEA; -+ if (isLD) { -+ if (szLg2 < 4) { -+ putQReg128(tt, mkV128(0x0000)); -+ } -+ putQRegLO(tt, loadLE(ty, mkexpr(tTA))); -+ } else { -+ storeLE(mkexpr(tTA), getQRegLO(tt, ty)); -+ } -+ putIReg64orSP(nn, mkexpr(tEA)); -+ DIP(atRN ? "%s %s, [%s], #%lld\n" : "%s %s, [%s, #%lld]!\n", -+ isLD ? "ldr" : "str", -+ nameQRegLO(tt, ty), nameIReg64orSP(nn), simm9); -+ return True; -+ } -+ -+ /* -------- LDUR/STUR (unscaled offset, SIMD&FP) -------- */ -+ /* 31 29 23 20 11 9 4 -+ 00 111 100 01 0 imm9 00 n t LDR Bt, [Xn|SP, #simm] -+ 01 111 100 01 0 imm9 00 n t LDR Ht, [Xn|SP, #simm] -+ 10 111 100 01 0 imm9 00 n t LDR St, [Xn|SP, #simm] -+ 11 111 100 01 0 imm9 00 n t LDR Dt, [Xn|SP, #simm] -+ 00 111 100 11 0 imm9 00 n t LDR Qt, [Xn|SP, #simm] -+ -+ 00 111 100 00 0 imm9 00 n t STR Bt, [Xn|SP, #simm] -+ 01 111 100 00 0 imm9 00 n t STR Ht, [Xn|SP, #simm] -+ 10 111 100 00 0 imm9 00 n t STR St, [Xn|SP, #simm] -+ 11 111 100 00 0 imm9 00 n t STR Dt, [Xn|SP, #simm] -+ 00 111 100 10 0 imm9 00 n t STR Qt, [Xn|SP, #simm] -+ */ -+ if (INSN(29,24) == BITS6(1,1,1,1,0,0) -+ && ((INSN(23,23) << 2) | INSN(31,30)) <= 4 -+ && INSN(21,21) == 0 && INSN(11,10) == BITS2(0,0)) { -+ UInt szLg2 = (INSN(23,23) << 2) | INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt imm9 = INSN(20,12); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ ULong simm9 = sx_to_64(imm9, 9); -+ IRTemp tEA = newTemp(Ity_I64); -+ IRType ty = preferredVectorSubTypeFromSize(1 << szLg2); -+ assign(tEA, binop(Iop_Add64, getIReg64orSP(nn), mkU64(simm9))); -+ if (isLD) { -+ if (szLg2 < 4) { -+ putQReg128(tt, mkV128(0x0000)); -+ } -+ putQRegLO(tt, loadLE(ty, mkexpr(tEA))); -+ } else { -+ storeLE(mkexpr(tEA), getQRegLO(tt, ty)); -+ } -+ DIP("%s %s, [%s, #%lld]\n", -+ isLD ? "ldur" : "stur", -+ nameQRegLO(tt, ty), nameIReg64orSP(nn), (Long)simm9); -+ return True; -+ } -+ -+ /* ---------------- LDR (literal, SIMD&FP) ---------------- */ -+ /* 31 29 23 4 -+ 00 011 100 imm19 t LDR St, [PC + sxTo64(imm19 << 2)] -+ 01 011 100 imm19 t LDR Dt, [PC + sxTo64(imm19 << 2)] -+ 10 011 100 imm19 t LDR Qt, [PC + sxTo64(imm19 << 2)] -+ */ -+ if (INSN(29,24) == BITS6(0,1,1,1,0,0) && INSN(31,30) < BITS2(1,1)) { -+ UInt szB = 4 << INSN(31,30); -+ UInt imm19 = INSN(23,5); -+ UInt tt = INSN(4,0); -+ ULong ea = guest_PC_curr_instr + sx_to_64(imm19 << 2, 21); -+ IRType ty = preferredVectorSubTypeFromSize(szB); -+ putQReg128(tt, mkV128(0x0000)); -+ putQRegLO(tt, loadLE(ty, mkU64(ea))); -+ DIP("ldr %s, 0x%llx (literal)\n", nameQRegLO(tt, ty), ea); -+ return True; -+ } -+ -+ /* ---------- LD1/ST1 (single structure, no offset) ---------- */ -+ /* 31 23 -+ 0100 1100 0100 0000 0111 11 N T LD1 {vT.2d}, [Xn|SP] -+ 0100 1100 0000 0000 0111 11 N T ST1 {vT.2d}, [Xn|SP] -+ 0100 1100 0100 0000 0111 10 N T LD1 {vT.4s}, [Xn|SP] -+ 0100 1100 0000 0000 0111 10 N T ST1 {vT.4s}, [Xn|SP] -+ 0100 1100 0100 0000 0111 01 N T LD1 {vT.8h}, [Xn|SP] -+ 0100 1100 0000 0000 0111 01 N T ST1 {vT.8h}, [Xn|SP] -+ 0100 1100 0100 0000 0111 00 N T LD1 {vT.16b}, [Xn|SP] -+ 0100 1100 0000 0000 0111 00 N T ST1 {vT.16b}, [Xn|SP] -+ FIXME does this assume that the host is little endian? -+ */ -+ if ( (insn & 0xFFFFF000) == 0x4C407000 // LD1 cases -+ || (insn & 0xFFFFF000) == 0x4C007000 // ST1 cases -+ ) { -+ Bool isLD = INSN(22,22) == 1; -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ const HChar* names[4] = { "2d", "4s", "8h", "16b" }; -+ const HChar* name = names[INSN(11,10)]; -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ if (isLD) { -+ putQReg128(vT, loadLE(Ity_V128, mkexpr(tEA))); -+ } else { -+ storeLE(mkexpr(tEA), getQReg128(vT)); -+ } -+ DIP("%s {v%u.%s}, [%s]\n", isLD ? "ld1" : "st1", -+ vT, name, nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* 31 23 -+ 0000 1100 0100 0000 0111 11 N T LD1 {vT.1d}, [Xn|SP] -+ 0000 1100 0000 0000 0111 11 N T ST1 {vT.1d}, [Xn|SP] -+ 0000 1100 0100 0000 0111 10 N T LD1 {vT.2s}, [Xn|SP] -+ 0000 1100 0000 0000 0111 10 N T ST1 {vT.2s}, [Xn|SP] -+ 0000 1100 0100 0000 0111 01 N T LD1 {vT.4h}, [Xn|SP] -+ 0000 1100 0000 0000 0111 01 N T ST1 {vT.4h}, [Xn|SP] -+ 0000 1100 0100 0000 0111 00 N T LD1 {vT.8b}, [Xn|SP] -+ 0000 1100 0000 0000 0111 00 N T ST1 {vT.8b}, [Xn|SP] -+ FIXME does this assume that the host is little endian? -+ */ -+ if ( (insn & 0xFFFFF000) == 0x0C407000 // LD1 cases -+ || (insn & 0xFFFFF000) == 0x0C007000 // ST1 cases -+ ) { -+ Bool isLD = INSN(22,22) == 1; -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ const HChar* names[4] = { "1d", "2s", "4h", "8b" }; -+ const HChar* name = names[INSN(11,10)]; -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ if (isLD) { -+ putQRegLane(vT, 0, loadLE(Ity_I64, mkexpr(tEA))); -+ putQRegLane(vT, 1, mkU64(0)); -+ } else { -+ storeLE(mkexpr(tEA), getQRegLane(vT, 0, Ity_I64)); -+ } -+ DIP("%s {v%u.%s}, [%s]\n", isLD ? "ld1" : "st1", -+ vT, name, nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* ---------- LD1/ST1 (single structure, post index) ---------- */ -+ /* 31 23 -+ 0100 1100 1001 1111 0111 11 N T ST1 {vT.2d}, [xN|SP], #16 -+ 0100 1100 1101 1111 0111 11 N T LD1 {vT.2d}, [xN|SP], #16 -+ 0100 1100 1001 1111 0111 10 N T ST1 {vT.4s}, [xN|SP], #16 -+ 0100 1100 1101 1111 0111 10 N T LD1 {vT.4s}, [xN|SP], #16 -+ 0100 1100 1001 1111 0111 01 N T ST1 {vT.8h}, [xN|SP], #16 -+ 0100 1100 1101 1111 0111 01 N T LD1 {vT.8h}, [xN|SP], #16 -+ 0100 1100 1001 1111 0111 00 N T ST1 {vT.16b}, [xN|SP], #16 -+ 0100 1100 1101 1111 0111 00 N T LD1 {vT.16b}, [xN|SP], #16 -+ Note that #16 is implied and cannot be any other value. -+ FIXME does this assume that the host is little endian? -+ */ -+ if ( (insn & 0xFFFFF000) == 0x4CDF7000 // LD1 cases -+ || (insn & 0xFFFFF000) == 0x4C9F7000 // ST1 cases -+ ) { -+ Bool isLD = INSN(22,22) == 1; -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ const HChar* names[4] = { "2d", "4s", "8h", "16b" }; -+ const HChar* name = names[INSN(11,10)]; -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ if (isLD) { -+ putQReg128(vT, loadLE(Ity_V128, mkexpr(tEA))); -+ } else { -+ storeLE(mkexpr(tEA), getQReg128(vT)); -+ } -+ putIReg64orSP(rN, binop(Iop_Add64, mkexpr(tEA), mkU64(16))); -+ DIP("%s {v%u.%s}, [%s], #16\n", isLD ? "ld1" : "st1", -+ vT, name, nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* 31 23 -+ 0000 1100 1001 1111 0111 11 N T ST1 {vT.1d}, [xN|SP], #8 -+ 0000 1100 1101 1111 0111 11 N T LD1 {vT.1d}, [xN|SP], #8 -+ 0000 1100 1001 1111 0111 10 N T ST1 {vT.2s}, [xN|SP], #8 -+ 0000 1100 1101 1111 0111 10 N T LD1 {vT.2s}, [xN|SP], #8 -+ 0000 1100 1001 1111 0111 01 N T ST1 {vT.4h}, [xN|SP], #8 -+ 0000 1100 1101 1111 0111 01 N T LD1 {vT.4h}, [xN|SP], #8 -+ 0000 1100 1001 1111 0111 00 N T ST1 {vT.8b}, [xN|SP], #8 -+ 0000 1100 1101 1111 0111 00 N T LD1 {vT.8b}, [xN|SP], #8 -+ Note that #8 is implied and cannot be any other value. -+ FIXME does this assume that the host is little endian? -+ */ -+ if ( (insn & 0xFFFFF000) == 0x0CDF7000 // LD1 cases -+ || (insn & 0xFFFFF000) == 0x0C9F7000 // ST1 cases -+ ) { -+ Bool isLD = INSN(22,22) == 1; -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ const HChar* names[4] = { "1d", "2s", "4h", "8b" }; -+ const HChar* name = names[INSN(11,10)]; -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ if (isLD) { -+ putQRegLane(vT, 0, loadLE(Ity_I64, mkexpr(tEA))); -+ putQRegLane(vT, 1, mkU64(0)); -+ } else { -+ storeLE(mkexpr(tEA), getQRegLane(vT, 0, Ity_I64)); -+ } -+ putIReg64orSP(rN, binop(Iop_Add64, mkexpr(tEA), mkU64(8))); -+ DIP("%s {v%u.%s}, [%s], #8\n", isLD ? "ld1" : "st1", -+ vT, name, nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* ---------- LD2/ST2 (multiple structures, post index) ---------- */ -+ /* Only a very few cases. */ -+ /* 31 23 11 9 4 -+ 0100 1100 1101 1111 1000 11 n t LD2 {Vt.2d, V(t+1)%32.2d}, [Xn|SP], #32 -+ 0100 1100 1001 1111 1000 11 n t ST2 {Vt.2d, V(t+1)%32.2d}, [Xn|SP], #32 -+ 0100 1100 1101 1111 1000 10 n t LD2 {Vt.4s, V(t+1)%32.4s}, [Xn|SP], #32 -+ 0100 1100 1001 1111 1000 10 n t ST2 {Vt.4s, V(t+1)%32.4s}, [Xn|SP], #32 -+ */ -+ if ( (insn & 0xFFFFFC00) == 0x4CDF8C00 // LD2 .2d -+ || (insn & 0xFFFFFC00) == 0x4C9F8C00 // ST2 .2d -+ || (insn & 0xFFFFFC00) == 0x4CDF8800 // LD2 .4s -+ || (insn & 0xFFFFFC00) == 0x4C9F8800 // ST2 .4s -+ ) { -+ Bool isLD = INSN(22,22) == 1; -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ UInt sz = INSN(11,10); -+ const HChar* name = "??"; -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ IRExpr* tEA_0 = binop(Iop_Add64, mkexpr(tEA), mkU64(0)); -+ IRExpr* tEA_8 = binop(Iop_Add64, mkexpr(tEA), mkU64(8)); -+ IRExpr* tEA_16 = binop(Iop_Add64, mkexpr(tEA), mkU64(16)); -+ IRExpr* tEA_24 = binop(Iop_Add64, mkexpr(tEA), mkU64(24)); -+ if (sz == BITS2(1,1)) { -+ name = "2d"; -+ if (isLD) { -+ putQRegLane((vT+0) % 32, 0, loadLE(Ity_I64, tEA_0)); -+ putQRegLane((vT+0) % 32, 1, loadLE(Ity_I64, tEA_16)); -+ putQRegLane((vT+1) % 32, 0, loadLE(Ity_I64, tEA_8)); -+ putQRegLane((vT+1) % 32, 1, loadLE(Ity_I64, tEA_24)); -+ } else { -+ storeLE(tEA_0, getQRegLane((vT+0) % 32, 0, Ity_I64)); -+ storeLE(tEA_16, getQRegLane((vT+0) % 32, 1, Ity_I64)); -+ storeLE(tEA_8, getQRegLane((vT+1) % 32, 0, Ity_I64)); -+ storeLE(tEA_24, getQRegLane((vT+1) % 32, 1, Ity_I64)); -+ } -+ } -+ else if (sz == BITS2(1,0)) { -+ /* Uh, this is ugly. TODO: better. */ -+ name = "4s"; -+ IRExpr* tEA_4 = binop(Iop_Add64, mkexpr(tEA), mkU64(4)); -+ IRExpr* tEA_12 = binop(Iop_Add64, mkexpr(tEA), mkU64(12)); -+ IRExpr* tEA_20 = binop(Iop_Add64, mkexpr(tEA), mkU64(20)); -+ IRExpr* tEA_28 = binop(Iop_Add64, mkexpr(tEA), mkU64(28)); -+ if (isLD) { -+ putQRegLane((vT+0) % 32, 0, loadLE(Ity_I32, tEA_0)); -+ putQRegLane((vT+0) % 32, 1, loadLE(Ity_I32, tEA_8)); -+ putQRegLane((vT+0) % 32, 2, loadLE(Ity_I32, tEA_16)); -+ putQRegLane((vT+0) % 32, 3, loadLE(Ity_I32, tEA_24)); -+ putQRegLane((vT+1) % 32, 0, loadLE(Ity_I32, tEA_4)); -+ putQRegLane((vT+1) % 32, 1, loadLE(Ity_I32, tEA_12)); -+ putQRegLane((vT+1) % 32, 2, loadLE(Ity_I32, tEA_20)); -+ putQRegLane((vT+1) % 32, 3, loadLE(Ity_I32, tEA_28)); -+ } else { -+ storeLE(tEA_0, getQRegLane((vT+0) % 32, 0, Ity_I32)); -+ storeLE(tEA_8, getQRegLane((vT+0) % 32, 1, Ity_I32)); -+ storeLE(tEA_16, getQRegLane((vT+0) % 32, 2, Ity_I32)); -+ storeLE(tEA_24, getQRegLane((vT+0) % 32, 3, Ity_I32)); -+ storeLE(tEA_4, getQRegLane((vT+1) % 32, 0, Ity_I32)); -+ storeLE(tEA_12, getQRegLane((vT+1) % 32, 1, Ity_I32)); -+ storeLE(tEA_20, getQRegLane((vT+1) % 32, 2, Ity_I32)); -+ storeLE(tEA_28, getQRegLane((vT+1) % 32, 3, Ity_I32)); -+ } -+ } -+ else { -+ vassert(0); // Can't happen. -+ } -+ putIReg64orSP(rN, binop(Iop_Add64, mkexpr(tEA), mkU64(32))); -+ DIP("%s {v%u.%s, v%u.%s}, [%s], #32\n", isLD ? "ld2" : "st2", -+ (vT+0) % 32, name, (vT+1) % 32, name, nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* ---------- LD1/ST1 (multiple structures, no offset) ---------- */ -+ /* Only a very few cases. */ -+ /* 31 23 -+ 0100 1100 0100 0000 1010 00 n t LD1 {Vt.16b, V(t+1)%32.16b}, [Xn|SP] -+ 0100 1100 0000 0000 1010 00 n t ST1 {Vt.16b, V(t+1)%32.16b}, [Xn|SP] -+ */ -+ if ( (insn & 0xFFFFFC00) == 0x4C40A000 // LD1 -+ || (insn & 0xFFFFFC00) == 0x4C00A000 // ST1 -+ ) { -+ Bool isLD = INSN(22,22) == 1; -+ UInt rN = INSN(9,5); -+ UInt vT = INSN(4,0); -+ IRTemp tEA = newTemp(Ity_I64); -+ const HChar* name = "16b"; -+ assign(tEA, getIReg64orSP(rN)); -+ if (rN == 31) { /* FIXME generate stack alignment check */ } -+ IRExpr* tEA_0 = binop(Iop_Add64, mkexpr(tEA), mkU64(0)); -+ IRExpr* tEA_16 = binop(Iop_Add64, mkexpr(tEA), mkU64(16)); -+ if (isLD) { -+ putQReg128((vT+0) % 32, loadLE(Ity_V128, tEA_0)); -+ putQReg128((vT+1) % 32, loadLE(Ity_V128, tEA_16)); -+ } else { -+ storeLE(tEA_0, getQReg128((vT+0) % 32)); -+ storeLE(tEA_16, getQReg128((vT+1) % 32)); -+ } -+ DIP("%s {v%u.%s, v%u.%s}, [%s], #32\n", isLD ? "ld1" : "st1", -+ (vT+0) % 32, name, (vT+1) % 32, name, nameIReg64orSP(rN)); -+ return True; -+ } -+ -+ /* ------------------ LD{,A}X{R,RH,RB} ------------------ */ -+ /* ------------------ ST{,L}X{R,RH,RB} ------------------ */ -+ /* 31 29 23 20 14 9 4 -+ sz 001000 010 11111 0 11111 n t LDX{R,RH,RB} Rt, [Xn|SP] -+ sz 001000 010 11111 1 11111 n t LDAX{R,RH,RB} Rt, [Xn|SP] -+ sz 001000 000 s 0 11111 n t STX{R,RH,RB} Ws, Rt, [Xn|SP] -+ sz 001000 000 s 1 11111 n t STLX{R,RH,RB} Ws, Rt, [Xn|SP] -+ */ -+ if (INSN(29,23) == BITS7(0,0,1,0,0,0,0) -+ && (INSN(23,21) & BITS3(1,0,1)) == BITS3(0,0,0) -+ && INSN(14,10) == BITS5(1,1,1,1,1)) { -+ UInt szBlg2 = INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ Bool isAcqOrRel = INSN(15,15) == 1; -+ UInt ss = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ -+ vassert(szBlg2 < 4); -+ UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ -+ IRType ty = integerIRTypeOfSize(szB); -+ const HChar* suffix[4] = { "rb", "rh", "r", "r" }; -+ -+ IRTemp ea = newTemp(Ity_I64); -+ assign(ea, getIReg64orSP(nn)); -+ /* FIXME generate check that ea is szB-aligned */ -+ -+ if (isLD && ss == BITS5(1,1,1,1,1)) { -+ IRTemp res = newTemp(ty); -+ stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), NULL/*LL*/)); -+ putIReg64orZR(tt, widenUto64(ty, mkexpr(res))); -+ if (isAcqOrRel) { -+ stmt(IRStmt_MBE(Imbe_Fence)); -+ } -+ DIP("ld%sx%s %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2], -+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn)); -+ return True; -+ } -+ if (!isLD) { -+ if (isAcqOrRel) { -+ stmt(IRStmt_MBE(Imbe_Fence)); -+ } -+ IRTemp res = newTemp(Ity_I1); -+ IRExpr* data = narrowFrom64(ty, getIReg64orZR(tt)); -+ stmt(IRStmt_LLSC(Iend_LE, res, mkexpr(ea), data)); -+ /* IR semantics: res is 1 if store succeeds, 0 if it fails. -+ Need to set rS to 1 on failure, 0 on success. */ -+ putIReg64orZR(ss, binop(Iop_Xor64, unop(Iop_1Uto64, mkexpr(res)), -+ mkU64(1))); -+ DIP("st%sx%s %s, %s, [%s]\n", isAcqOrRel ? "a" : "", suffix[szBlg2], -+ nameIRegOrZR(False, ss), -+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn)); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ------------------ LDA{R,RH,RB} ------------------ */ -+ /* ------------------ STL{R,RH,RB} ------------------ */ -+ /* 31 29 23 20 14 9 4 -+ sz 001000 110 11111 1 11111 n t LDAR Rt, [Xn|SP] -+ sz 001000 100 11111 1 11111 n t STLR Rt, [Xn|SP] -+ */ -+ if (INSN(29,23) == BITS7(0,0,1,0,0,0,1) -+ && INSN(21,10) == BITS12(0,1,1,1,1,1,1,1,1,1,1,1)) { -+ UInt szBlg2 = INSN(31,30); -+ Bool isLD = INSN(22,22) == 1; -+ UInt nn = INSN(9,5); -+ UInt tt = INSN(4,0); -+ -+ vassert(szBlg2 < 4); -+ UInt szB = 1 << szBlg2; /* 1, 2, 4 or 8 */ -+ IRType ty = integerIRTypeOfSize(szB); -+ const HChar* suffix[4] = { "rb", "rh", "r", "r" }; -+ -+ IRTemp ea = newTemp(Ity_I64); -+ assign(ea, getIReg64orSP(nn)); -+ /* FIXME generate check that ea is szB-aligned */ -+ -+ if (isLD) { -+ IRTemp res = newTemp(ty); -+ assign(res, loadLE(ty, mkexpr(ea))); -+ putIReg64orZR(tt, widenUto64(ty, mkexpr(res))); -+ stmt(IRStmt_MBE(Imbe_Fence)); -+ DIP("lda%s %s, [%s]\n", suffix[szBlg2], -+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn)); -+ } else { -+ stmt(IRStmt_MBE(Imbe_Fence)); -+ IRExpr* data = narrowFrom64(ty, getIReg64orZR(tt)); -+ storeLE(mkexpr(ea), data); -+ DIP("stl%s %s, [%s]\n", suffix[szBlg2], -+ nameIRegOrZR(szB == 8, tt), nameIReg64orSP(nn)); -+ } -+ return True; -+ } -+ -+ vex_printf("ARM64 front end: load_store\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Control flow and misc instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+static -+Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn, -+ VexArchInfo* archinfo) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ---------------------- B cond ----------------------- */ -+ /* 31 24 4 3 -+ 0101010 0 imm19 0 cond */ -+ if (INSN(31,24) == BITS8(0,1,0,1,0,1,0,0) && INSN(4,4) == 0) { -+ UInt cond = INSN(3,0); -+ ULong uimm64 = INSN(23,5) << 2; -+ Long simm64 = (Long)sx_to_64(uimm64, 21); -+ vassert(dres->whatNext == Dis_Continue); -+ vassert(dres->len == 4); -+ vassert(dres->continueAt == 0); -+ vassert(dres->jk_StopHere == Ijk_INVALID); -+ stmt( IRStmt_Exit(unop(Iop_64to1, mk_arm64g_calculate_condition(cond)), -+ Ijk_Boring, -+ IRConst_U64(guest_PC_curr_instr + simm64), -+ OFFB_PC) ); -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("b.%s 0x%llx\n", nameCC(cond), guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* -------------------- B{L} uncond -------------------- */ -+ if (INSN(30,26) == BITS5(0,0,1,0,1)) { -+ /* 000101 imm26 B (PC + sxTo64(imm26 << 2)) -+ 100101 imm26 B (PC + sxTo64(imm26 << 2)) -+ */ -+ UInt bLink = INSN(31,31); -+ ULong uimm64 = INSN(25,0) << 2; -+ Long simm64 = (Long)sx_to_64(uimm64, 28); -+ if (bLink) { -+ putIReg64orSP(30, mkU64(guest_PC_curr_instr + 4)); -+ } -+ putPC(mkU64(guest_PC_curr_instr + simm64)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Call; -+ DIP("b%s 0x%llx\n", bLink == 1 ? "l" : "", -+ guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* --------------------- B{L} reg --------------------- */ -+ /* 31 24 22 20 15 9 4 -+ 1101011 00 10 11111 000000 nn 00000 RET Rn -+ 1101011 00 01 11111 000000 nn 00000 CALL Rn -+ 1101011 00 00 11111 000000 nn 00000 JMP Rn -+ */ -+ if (INSN(31,23) == BITS9(1,1,0,1,0,1,1,0,0) -+ && INSN(20,16) == BITS5(1,1,1,1,1) -+ && INSN(15,10) == BITS6(0,0,0,0,0,0) -+ && INSN(4,0) == BITS5(0,0,0,0,0)) { -+ UInt branch_type = INSN(22,21); -+ UInt nn = INSN(9,5); -+ if (branch_type == BITS2(1,0) /* RET */) { -+ putPC(getIReg64orZR(nn)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Ret; -+ DIP("ret %s\n", nameIReg64orZR(nn)); -+ return True; -+ } -+ if (branch_type == BITS2(0,1) /* CALL */) { -+ IRTemp dst = newTemp(Ity_I64); -+ assign(dst, getIReg64orZR(nn)); -+ putIReg64orSP(30, mkU64(guest_PC_curr_instr + 4)); -+ putPC(mkexpr(dst)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Call; -+ DIP("blr %s\n", nameIReg64orZR(nn)); -+ return True; -+ } -+ if (branch_type == BITS2(0,0) /* JMP */) { -+ putPC(getIReg64orZR(nn)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("jmp %s\n", nameIReg64orZR(nn)); -+ return True; -+ } -+ } -+ -+ /* -------------------- CB{N}Z -------------------- */ -+ /* sf 011 010 1 imm19 Rt CBNZ Xt|Wt, (PC + sxTo64(imm19 << 2)) -+ sf 011 010 0 imm19 Rt CBZ Xt|Wt, (PC + sxTo64(imm19 << 2)) -+ */ -+ if (INSN(30,25) == BITS6(0,1,1,0,1,0)) { -+ Bool is64 = INSN(31,31) == 1; -+ Bool bIfZ = INSN(24,24) == 0; -+ ULong uimm64 = INSN(23,5) << 2; -+ UInt rT = INSN(4,0); -+ Long simm64 = (Long)sx_to_64(uimm64, 21); -+ IRExpr* cond = NULL; -+ if (is64) { -+ cond = binop(bIfZ ? Iop_CmpEQ64 : Iop_CmpNE64, -+ getIReg64orZR(rT), mkU64(0)); -+ } else { -+ cond = binop(bIfZ ? Iop_CmpEQ32 : Iop_CmpNE32, -+ getIReg32orZR(rT), mkU32(0)); -+ } -+ stmt( IRStmt_Exit(cond, -+ Ijk_Boring, -+ IRConst_U64(guest_PC_curr_instr + simm64), -+ OFFB_PC) ); -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("cb%sz %s, 0x%llx\n", -+ bIfZ ? "" : "n", nameIRegOrZR(is64, rT), -+ guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* -------------------- TB{N}Z -------------------- */ -+ /* 31 30 24 23 18 5 4 -+ b5 011 011 1 b40 imm14 t TBNZ Xt, #(b5:b40), (PC + sxTo64(imm14 << 2)) -+ b5 011 011 0 b40 imm14 t TBZ Xt, #(b5:b40), (PC + sxTo64(imm14 << 2)) -+ */ -+ if (INSN(30,25) == BITS6(0,1,1,0,1,1)) { -+ UInt b5 = INSN(31,31); -+ Bool bIfZ = INSN(24,24) == 0; -+ UInt b40 = INSN(23,19); -+ UInt imm14 = INSN(18,5); -+ UInt tt = INSN(4,0); -+ UInt bitNo = (b5 << 5) | b40; -+ ULong uimm64 = imm14 << 2; -+ Long simm64 = sx_to_64(uimm64, 16); -+ IRExpr* cond -+ = binop(bIfZ ? Iop_CmpEQ64 : Iop_CmpNE64, -+ binop(Iop_And64, -+ binop(Iop_Shr64, getIReg64orZR(tt), mkU8(bitNo)), -+ mkU64(1)), -+ mkU64(0)); -+ stmt( IRStmt_Exit(cond, -+ Ijk_Boring, -+ IRConst_U64(guest_PC_curr_instr + simm64), -+ OFFB_PC) ); -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Boring; -+ DIP("tb%sz %s, #%u, 0x%llx\n", -+ bIfZ ? "" : "n", nameIReg64orZR(tt), bitNo, -+ guest_PC_curr_instr + simm64); -+ return True; -+ } -+ -+ /* -------------------- SVC -------------------- */ -+ /* 11010100 000 imm16 000 01 -+ Don't bother with anything except the imm16==0 case. -+ */ -+ if (INSN(31,0) == 0xD4000001) { -+ putPC(mkU64(guest_PC_curr_instr + 4)); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_Sys_syscall; -+ DIP("svc #0\n"); -+ return True; -+ } -+ -+ /* ------------------ M{SR,RS} ------------------ */ -+ /* Only handles the case where the system register is TPIDR_EL0. -+ 0xD51BD0 010 Rt MSR tpidr_el0, rT -+ 0xD53BD0 010 Rt MRS rT, tpidr_el0 -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51BD040 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53BD040 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ stmt( IRStmt_Put( OFFB_TPIDR_EL0, getIReg64orZR(tt)) ); -+ DIP("msr tpidr_el0, %s\n", nameIReg64orZR(tt)); -+ } else { -+ putIReg64orZR(tt, IRExpr_Get( OFFB_TPIDR_EL0, Ity_I64 )); -+ DIP("mrs %s, tpidr_el0\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ /* Cases for FPCR -+ 0xD51B44 000 Rt MSR fpcr, rT -+ 0xD53B44 000 Rt MSR rT, fpcr -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4400 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4400 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ stmt( IRStmt_Put( OFFB_FPCR, getIReg32orZR(tt)) ); -+ DIP("msr fpcr, %s\n", nameIReg64orZR(tt)); -+ } else { -+ putIReg32orZR(tt, IRExpr_Get(OFFB_FPCR, Ity_I32)); -+ DIP("mrs %s, fpcr\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ /* Cases for FPSR -+ 0xD51B44 001 Rt MSR fpsr, rT -+ 0xD53B44 001 Rt MSR rT, fpsr -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4420 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4420 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ stmt( IRStmt_Put( OFFB_FPSR, getIReg32orZR(tt)) ); -+ DIP("msr fpsr, %s\n", nameIReg64orZR(tt)); -+ } else { -+ putIReg32orZR(tt, IRExpr_Get(OFFB_FPSR, Ity_I32)); -+ DIP("mrs %s, fpsr\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ /* Cases for NZCV -+ D51B42 000 Rt MSR nzcv, rT -+ D53B42 000 Rt MRS rT, nzcv -+ */ -+ if ( (INSN(31,0) & 0xFFFFFFE0) == 0xD51B4200 /*MSR*/ -+ || (INSN(31,0) & 0xFFFFFFE0) == 0xD53B4200 /*MRS*/) { -+ Bool toSys = INSN(21,21) == 0; -+ UInt tt = INSN(4,0); -+ if (toSys) { -+ IRTemp t = newTemp(Ity_I64); -+ assign(t, binop(Iop_And64, getIReg64orZR(tt), mkU64(0xF0000000ULL))); -+ setFlags_COPY(t); -+ DIP("msr %s, nzcv\n", nameIReg32orZR(tt)); -+ } else { -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, mk_arm64g_calculate_flags_nzcv()); -+ putIReg32orZR(tt, unop(Iop_64to32, mkexpr(res))); -+ DIP("mrs %s, nzcv\n", nameIReg64orZR(tt)); -+ } -+ return True; -+ } -+ /* Cases for DCZID_EL0 -+ Don't support arbitrary reads and writes to this register. Just -+ return the value 16, which indicates that the DC ZVA instruction -+ is not permitted, so we don't have to emulate it. -+ D5 3B 00 111 Rt MRS rT, dczid_el0 -+ */ -+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53B00E0) { -+ UInt tt = INSN(4,0); -+ putIReg64orZR(tt, mkU64(1<<4)); -+ DIP("mrs %s, dczid_el0 (FAKED)\n", nameIReg64orZR(tt)); -+ return True; -+ } -+ /* Cases for CTR_EL0 -+ We just handle reads, and make up a value from the D and I line -+ sizes in the VexArchInfo we are given, and patch in the following -+ fields that the Foundation model gives ("natively"): -+ CWG = 0b0100, ERG = 0b0100, L1Ip = 0b11 -+ D5 3B 00 001 Rt MRS rT, dczid_el0 -+ */ -+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53B0020) { -+ UInt tt = INSN(4,0); -+ /* Need to generate a value from dMinLine_lg2_szB and -+ dMinLine_lg2_szB. The value in the register is in 32-bit -+ units, so need to subtract 2 from the values in the -+ VexArchInfo. We can assume that the values here are valid -- -+ disInstr_ARM64 checks them -- so there's no need to deal with -+ out-of-range cases. */ -+ vassert(archinfo->arm64_dMinLine_lg2_szB >= 2 -+ && archinfo->arm64_dMinLine_lg2_szB <= 17 -+ && archinfo->arm64_iMinLine_lg2_szB >= 2 -+ && archinfo->arm64_iMinLine_lg2_szB <= 17); -+ UInt val -+ = 0x8440c000 | ((0xF & (archinfo->arm64_dMinLine_lg2_szB - 2)) << 16) -+ | ((0xF & (archinfo->arm64_iMinLine_lg2_szB - 2)) << 0); -+ putIReg64orZR(tt, mkU64(val)); -+ DIP("mrs %s, ctr_el0\n", nameIReg64orZR(tt)); -+ return True; -+ } -+ -+ /* ------------------ IC_IVAU ------------------ */ -+ /* D5 0B 75 001 Rt ic ivau, rT -+ */ -+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7520) { -+ /* We will always be provided with a valid iMinLine value. */ -+ vassert(archinfo->arm64_iMinLine_lg2_szB >= 2 -+ && archinfo->arm64_iMinLine_lg2_szB <= 17); -+ /* Round the requested address, in rT, down to the start of the -+ containing block. */ -+ UInt tt = INSN(4,0); -+ ULong lineszB = 1ULL << archinfo->arm64_iMinLine_lg2_szB; -+ IRTemp addr = newTemp(Ity_I64); -+ assign( addr, binop( Iop_And64, -+ getIReg64orZR(tt), -+ mkU64(~(lineszB - 1))) ); -+ /* Set the invalidation range, request exit-and-invalidate, with -+ continuation at the next instruction. */ -+ stmt(IRStmt_Put(OFFB_CMSTART, mkexpr(addr))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(lineszB))); -+ /* be paranoid ... */ -+ stmt( IRStmt_MBE(Imbe_Fence) ); -+ putPC(mkU64( guest_PC_curr_instr + 4 )); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_InvalICache; -+ DIP("ic ivau, %s\n", nameIReg64orZR(tt)); -+ return True; -+ } -+ -+ /* ------------------ DC_CVAU ------------------ */ -+ /* D5 0B 7B 001 Rt dc cvau, rT -+ */ -+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20) { -+ /* Exactly the same scheme as for IC IVAU, except we observe the -+ dMinLine size, and request an Ijk_FlushDCache instead of -+ Ijk_InvalICache. */ -+ /* We will always be provided with a valid dMinLine value. */ -+ vassert(archinfo->arm64_dMinLine_lg2_szB >= 2 -+ && archinfo->arm64_dMinLine_lg2_szB <= 17); -+ /* Round the requested address, in rT, down to the start of the -+ containing block. */ -+ UInt tt = INSN(4,0); -+ ULong lineszB = 1ULL << archinfo->arm64_dMinLine_lg2_szB; -+ IRTemp addr = newTemp(Ity_I64); -+ assign( addr, binop( Iop_And64, -+ getIReg64orZR(tt), -+ mkU64(~(lineszB - 1))) ); -+ /* Set the flush range, request exit-and-flush, with -+ continuation at the next instruction. */ -+ stmt(IRStmt_Put(OFFB_CMSTART, mkexpr(addr))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(lineszB))); -+ /* be paranoid ... */ -+ stmt( IRStmt_MBE(Imbe_Fence) ); -+ putPC(mkU64( guest_PC_curr_instr + 4 )); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_FlushDCache; -+ DIP("dc cvau, %s\n", nameIReg64orZR(tt)); -+ return True; -+ } -+ -+ /* ------------------ ISB, DMB, DSB ------------------ */ -+ if (INSN(31,0) == 0xD5033FDF) { -+ stmt(IRStmt_MBE(Imbe_Fence)); -+ DIP("isb\n"); -+ return True; -+ } -+ if (INSN(31,0) == 0xD5033BBF) { -+ stmt(IRStmt_MBE(Imbe_Fence)); -+ DIP("dmb ish\n"); -+ return True; -+ } -+ if (INSN(31,0) == 0xD5033B9F) { -+ stmt(IRStmt_MBE(Imbe_Fence)); -+ DIP("dsb ish\n"); -+ return True; -+ } -+ -+ /* -------------------- NOP -------------------- */ -+ if (INSN(31,0) == 0xD503201F) { -+ DIP("nop\n"); -+ return True; -+ } -+ -+ //fail: -+ vex_printf("ARM64 front end: branch_etc\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- SIMD and FP instructions ---*/ -+/*------------------------------------------------------------*/ -+ -+/* begin FIXME -- rm temp scaffolding */ -+static IRExpr* mk_CatEvenLanes64x2 ( IRTemp, IRTemp ); -+static IRExpr* mk_CatOddLanes64x2 ( IRTemp, IRTemp ); -+ -+static IRExpr* mk_CatEvenLanes32x4 ( IRTemp, IRTemp ); -+static IRExpr* mk_CatOddLanes32x4 ( IRTemp, IRTemp ); -+static IRExpr* mk_InterleaveLO32x4 ( IRTemp, IRTemp ); -+static IRExpr* mk_InterleaveHI32x4 ( IRTemp, IRTemp ); -+ -+static IRExpr* mk_CatEvenLanes16x8 ( IRTemp, IRTemp ); -+static IRExpr* mk_CatOddLanes16x8 ( IRTemp, IRTemp ); -+static IRExpr* mk_InterleaveLO16x8 ( IRTemp, IRTemp ); -+static IRExpr* mk_InterleaveHI16x8 ( IRTemp, IRTemp ); -+ -+static IRExpr* mk_CatEvenLanes8x16 ( IRTemp, IRTemp ); -+static IRExpr* mk_CatOddLanes8x16 ( IRTemp, IRTemp ); -+static IRExpr* mk_InterleaveLO8x16 ( IRTemp, IRTemp ); -+static IRExpr* mk_InterleaveHI8x16 ( IRTemp, IRTemp ); -+/* end FIXME -- rm temp scaffolding */ -+ -+/* Generate N copies of |bit| in the bottom of a ULong. */ -+static ULong Replicate ( ULong bit, Int N ) -+{ -+ vassert(bit <= 1 && N >= 1 && N < 64); -+ if (bit == 0) { -+ return 0; -+ } else { -+ /* Careful. This won't work for N == 64. */ -+ return (1ULL << N) - 1; -+ } -+} -+ -+static ULong Replicate32x2 ( ULong bits32 ) -+{ -+ vassert(0 == (bits32 & ~0xFFFFFFFFULL)); -+ return (bits32 << 32) | bits32; -+} -+ -+static ULong Replicate16x4 ( ULong bits16 ) -+{ -+ vassert(0 == (bits16 & ~0xFFFFULL)); -+ return Replicate32x2((bits16 << 16) | bits16); -+} -+ -+static ULong Replicate8x8 ( ULong bits8 ) -+{ -+ vassert(0 == (bits8 & ~0xFFULL)); -+ return Replicate16x4((bits8 << 8) | bits8); -+} -+ -+/* Expand the VFPExpandImm-style encoding in the bottom 8 bits of -+ |imm8| to either a 32-bit value if N is 32 or a 64 bit value if N -+ is 64. In the former case, the upper 32 bits of the returned value -+ are guaranteed to be zero. */ -+static ULong VFPExpandImm ( ULong imm8, Int N ) -+{ -+ vassert(imm8 <= 0xFF); -+ vassert(N == 32 || N == 64); -+ Int E = ((N == 32) ? 8 : 11) - 2; // The spec incorrectly omits the -2. -+ Int F = N - E - 1; -+ ULong imm8_6 = (imm8 >> 6) & 1; -+ /* sign: 1 bit */ -+ /* exp: E bits */ -+ /* frac: F bits */ -+ ULong sign = (imm8 >> 7) & 1; -+ ULong exp = ((imm8_6 ^ 1) << (E-1)) | Replicate(imm8_6, E-1); -+ ULong frac = ((imm8 & 63) << (F-6)) | Replicate(0, F-6); -+ vassert(sign < (1ULL << 1)); -+ vassert(exp < (1ULL << E)); -+ vassert(frac < (1ULL << F)); -+ vassert(1 + E + F == N); -+ ULong res = (sign << (E+F)) | (exp << F) | frac; -+ return res; -+} -+ -+/* Expand an AdvSIMDExpandImm-style encoding into a 64-bit value. -+ This might fail, as indicated by the returned Bool. Page 2530 of -+ the manual. */ -+static Bool AdvSIMDExpandImm ( /*OUT*/ULong* res, -+ UInt op, UInt cmode, UInt imm8 ) -+{ -+ vassert(op <= 1); -+ vassert(cmode <= 15); -+ vassert(imm8 <= 255); -+ -+ *res = 0; /* will overwrite iff returning True */ -+ -+ ULong imm64 = 0; -+ Bool testimm8 = False; -+ -+ switch (cmode >> 1) { -+ case 0: -+ testimm8 = False; imm64 = Replicate32x2(imm8); break; -+ case 1: -+ testimm8 = True; imm64 = Replicate32x2(imm8 << 8); break; -+ case 2: -+ testimm8 = True; imm64 = Replicate32x2(imm8 << 16); break; -+ case 3: -+ testimm8 = True; imm64 = Replicate32x2(imm8 << 24); break; -+ case 4: -+ testimm8 = False; imm64 = Replicate16x4(imm8); break; -+ case 5: -+ testimm8 = True; imm64 = Replicate16x4(imm8 << 8); break; -+ case 6: -+ testimm8 = True; -+ if ((cmode & 1) == 0) -+ imm64 = Replicate32x2((imm8 << 8) | 0xFF); -+ else -+ imm64 = Replicate32x2((imm8 << 16) | 0xFFFF); -+ break; -+ case 7: -+ testimm8 = False; -+ if ((cmode & 1) == 0 && op == 0) -+ imm64 = Replicate8x8(imm8); -+ if ((cmode & 1) == 0 && op == 1) { -+ imm64 = 0; imm64 |= (imm8 & 0x80) ? 0xFF : 0x00; -+ imm64 <<= 8; imm64 |= (imm8 & 0x40) ? 0xFF : 0x00; -+ imm64 <<= 8; imm64 |= (imm8 & 0x20) ? 0xFF : 0x00; -+ imm64 <<= 8; imm64 |= (imm8 & 0x10) ? 0xFF : 0x00; -+ imm64 <<= 8; imm64 |= (imm8 & 0x08) ? 0xFF : 0x00; -+ imm64 <<= 8; imm64 |= (imm8 & 0x04) ? 0xFF : 0x00; -+ imm64 <<= 8; imm64 |= (imm8 & 0x02) ? 0xFF : 0x00; -+ imm64 <<= 8; imm64 |= (imm8 & 0x01) ? 0xFF : 0x00; -+ } -+ if ((cmode & 1) == 1 && op == 0) { -+ ULong imm8_7 = (imm8 >> 7) & 1; -+ ULong imm8_6 = (imm8 >> 6) & 1; -+ ULong imm8_50 = imm8 & 63; -+ ULong imm32 = (imm8_7 << (1 + 5 + 6 + 19)) -+ | ((imm8_6 ^ 1) << (5 + 6 + 19)) -+ | (Replicate(imm8_6, 5) << (6 + 19)) -+ | (imm8_50 << 19); -+ imm64 = Replicate32x2(imm32); -+ } -+ if ((cmode & 1) == 1 && op == 1) { -+ // imm64 = imm8<7>:NOT(imm8<6>) -+ // :Replicate(imm8<6>,8):imm8<5:0>:Zeros(48); -+ ULong imm8_7 = (imm8 >> 7) & 1; -+ ULong imm8_6 = (imm8 >> 6) & 1; -+ ULong imm8_50 = imm8 & 63; -+ imm64 = (imm8_7 << 63) | ((imm8_6 ^ 1) << 62) -+ | (Replicate(imm8_6, 8) << 54) -+ | (imm8_50 << 48); -+ } -+ break; -+ default: -+ vassert(0); -+ } -+ -+ if (testimm8 && imm8 == 0) -+ return False; -+ -+ *res = imm64; -+ return True; -+} -+ -+ -+/* Help a bit for decoding laneage for vector operations that can be -+ of the form 4x32, 2x64 or 2x32-and-zero-upper-half, as encoded by Q -+ and SZ bits, typically for vector floating point. */ -+static Bool getLaneInfo_Q_SZ ( /*OUT*/IRType* tyI, /*OUT*/IRType* tyF, -+ /*OUT*/UInt* nLanes, /*OUT*/Bool* zeroUpper, -+ /*OUT*/const HChar** arrSpec, -+ Bool bitQ, Bool bitSZ ) -+{ -+ vassert(bitQ == True || bitQ == False); -+ vassert(bitSZ == True || bitSZ == False); -+ if (bitQ && bitSZ) { // 2x64 -+ if (tyI) *tyI = Ity_I64; -+ if (tyF) *tyF = Ity_F64; -+ if (nLanes) *nLanes = 2; -+ if (zeroUpper) *zeroUpper = False; -+ if (arrSpec) *arrSpec = "2d"; -+ return True; -+ } -+ if (bitQ && !bitSZ) { // 4x32 -+ if (tyI) *tyI = Ity_I32; -+ if (tyF) *tyF = Ity_F32; -+ if (nLanes) *nLanes = 4; -+ if (zeroUpper) *zeroUpper = False; -+ if (arrSpec) *arrSpec = "4s"; -+ return True; -+ } -+ if (!bitQ && !bitSZ) { // 2x32 -+ if (tyI) *tyI = Ity_I32; -+ if (tyF) *tyF = Ity_F32; -+ if (nLanes) *nLanes = 2; -+ if (zeroUpper) *zeroUpper = True; -+ if (arrSpec) *arrSpec = "2s"; -+ return True; -+ } -+ // Else impliedly 1x64, which isn't allowed. -+ return False; -+} -+ -+/* Helper for decoding laneage for simple vector operations, -+ eg integer add. */ -+static Bool getLaneInfo_SIMPLE ( /*OUT*/Bool* zeroUpper, -+ /*OUT*/const HChar** arrSpec, -+ Bool bitQ, UInt szBlg2 ) -+{ -+ vassert(bitQ == True || bitQ == False); -+ vassert(szBlg2 < 4); -+ Bool zu = False; -+ const HChar* as = NULL; -+ switch ((szBlg2 << 1) | (bitQ ? 1 : 0)) { -+ case 0: zu = True; as = "8b"; break; -+ case 1: zu = False; as = "16b"; break; -+ case 2: zu = True; as = "4h"; break; -+ case 3: zu = False; as = "8h"; break; -+ case 4: zu = True; as = "2s"; break; -+ case 5: zu = False; as = "4s"; break; -+ case 6: return False; // impliedly 1x64 -+ case 7: zu = False; as = "2d"; break; -+ default: vassert(0); -+ } -+ vassert(as); -+ if (arrSpec) *arrSpec = as; -+ if (zeroUpper) *zeroUpper = zu; -+ return True; -+} -+ -+ -+/* Helper for decoding laneage for shift-style vector operations -+ that involve an immediate shift amount. */ -+static Bool getLaneInfo_IMMH_IMMB ( /*OUT*/UInt* shift, /*OUT*/UInt* szBlg2, -+ UInt immh, UInt immb ) -+{ -+ vassert(immh < (1<<4)); -+ vassert(immb < (1<<3)); -+ UInt immhb = (immh << 3) | immb; -+ if (immh & 8) { -+ if (shift) *shift = 128 - immhb; -+ if (szBlg2) *szBlg2 = 3; -+ return True; -+ } -+ if (immh & 4) { -+ if (shift) *shift = 64 - immhb; -+ if (szBlg2) *szBlg2 = 2; -+ return True; -+ } -+ if (immh & 2) { -+ if (shift) *shift = 32 - immhb; -+ if (szBlg2) *szBlg2 = 1; -+ return True; -+ } -+ if (immh & 1) { -+ if (shift) *shift = 16 - immhb; -+ if (szBlg2) *szBlg2 = 0; -+ return True; -+ } -+ return False; -+} -+ -+ -+/* Generate IR to fold all lanes of the V128 value in 'src' as -+ characterised by the operator 'op', and return the result in the -+ bottom bits of a V128, with all other bits set to zero. */ -+static IRTemp math_MINMAXV ( IRTemp src, IROp op ) -+{ -+ /* The basic idea is to use repeated applications of Iop_CatEven* -+ and Iop_CatOdd* operators to 'src' so as to clone each lane into -+ a complete vector. Then fold all those vectors with 'op' and -+ zero out all but the least significant lane. */ -+ switch (op) { -+ case Iop_Min8Sx16: case Iop_Min8Ux16: -+ case Iop_Max8Sx16: case Iop_Max8Ux16: { -+ /* NB: temp naming here is misleading -- the naming is for 8 -+ lanes of 16 bit, whereas what is being operated on is 16 -+ lanes of 8 bits. */ -+ IRTemp x76543210 = src; -+ IRTemp x76547654 = newTemp(Ity_V128); -+ IRTemp x32103210 = newTemp(Ity_V128); -+ assign(x76547654, mk_CatOddLanes64x2 (x76543210, x76543210)); -+ assign(x32103210, mk_CatEvenLanes64x2(x76543210, x76543210)); -+ IRTemp x76767676 = newTemp(Ity_V128); -+ IRTemp x54545454 = newTemp(Ity_V128); -+ IRTemp x32323232 = newTemp(Ity_V128); -+ IRTemp x10101010 = newTemp(Ity_V128); -+ assign(x76767676, mk_CatOddLanes32x4 (x76547654, x76547654)); -+ assign(x54545454, mk_CatEvenLanes32x4(x76547654, x76547654)); -+ assign(x32323232, mk_CatOddLanes32x4 (x32103210, x32103210)); -+ assign(x10101010, mk_CatEvenLanes32x4(x32103210, x32103210)); -+ IRTemp x77777777 = newTemp(Ity_V128); -+ IRTemp x66666666 = newTemp(Ity_V128); -+ IRTemp x55555555 = newTemp(Ity_V128); -+ IRTemp x44444444 = newTemp(Ity_V128); -+ IRTemp x33333333 = newTemp(Ity_V128); -+ IRTemp x22222222 = newTemp(Ity_V128); -+ IRTemp x11111111 = newTemp(Ity_V128); -+ IRTemp x00000000 = newTemp(Ity_V128); -+ assign(x77777777, mk_CatOddLanes16x8 (x76767676, x76767676)); -+ assign(x66666666, mk_CatEvenLanes16x8(x76767676, x76767676)); -+ assign(x55555555, mk_CatOddLanes16x8 (x54545454, x54545454)); -+ assign(x44444444, mk_CatEvenLanes16x8(x54545454, x54545454)); -+ assign(x33333333, mk_CatOddLanes16x8 (x32323232, x32323232)); -+ assign(x22222222, mk_CatEvenLanes16x8(x32323232, x32323232)); -+ assign(x11111111, mk_CatOddLanes16x8 (x10101010, x10101010)); -+ assign(x00000000, mk_CatEvenLanes16x8(x10101010, x10101010)); -+ /* Naming not misleading after here. */ -+ IRTemp xAllF = newTemp(Ity_V128); -+ IRTemp xAllE = newTemp(Ity_V128); -+ IRTemp xAllD = newTemp(Ity_V128); -+ IRTemp xAllC = newTemp(Ity_V128); -+ IRTemp xAllB = newTemp(Ity_V128); -+ IRTemp xAllA = newTemp(Ity_V128); -+ IRTemp xAll9 = newTemp(Ity_V128); -+ IRTemp xAll8 = newTemp(Ity_V128); -+ IRTemp xAll7 = newTemp(Ity_V128); -+ IRTemp xAll6 = newTemp(Ity_V128); -+ IRTemp xAll5 = newTemp(Ity_V128); -+ IRTemp xAll4 = newTemp(Ity_V128); -+ IRTemp xAll3 = newTemp(Ity_V128); -+ IRTemp xAll2 = newTemp(Ity_V128); -+ IRTemp xAll1 = newTemp(Ity_V128); -+ IRTemp xAll0 = newTemp(Ity_V128); -+ assign(xAllF, mk_CatOddLanes8x16 (x77777777, x77777777)); -+ assign(xAllE, mk_CatEvenLanes8x16(x77777777, x77777777)); -+ assign(xAllD, mk_CatOddLanes8x16 (x66666666, x66666666)); -+ assign(xAllC, mk_CatEvenLanes8x16(x66666666, x66666666)); -+ assign(xAllB, mk_CatOddLanes8x16 (x55555555, x55555555)); -+ assign(xAllA, mk_CatEvenLanes8x16(x55555555, x55555555)); -+ assign(xAll9, mk_CatOddLanes8x16 (x44444444, x44444444)); -+ assign(xAll8, mk_CatEvenLanes8x16(x44444444, x44444444)); -+ assign(xAll7, mk_CatOddLanes8x16 (x33333333, x33333333)); -+ assign(xAll6, mk_CatEvenLanes8x16(x33333333, x33333333)); -+ assign(xAll5, mk_CatOddLanes8x16 (x22222222, x22222222)); -+ assign(xAll4, mk_CatEvenLanes8x16(x22222222, x22222222)); -+ assign(xAll3, mk_CatOddLanes8x16 (x11111111, x11111111)); -+ assign(xAll2, mk_CatEvenLanes8x16(x11111111, x11111111)); -+ assign(xAll1, mk_CatOddLanes8x16 (x00000000, x00000000)); -+ assign(xAll0, mk_CatEvenLanes8x16(x00000000, x00000000)); -+ IRTemp maxFE = newTemp(Ity_V128); -+ IRTemp maxDC = newTemp(Ity_V128); -+ IRTemp maxBA = newTemp(Ity_V128); -+ IRTemp max98 = newTemp(Ity_V128); -+ IRTemp max76 = newTemp(Ity_V128); -+ IRTemp max54 = newTemp(Ity_V128); -+ IRTemp max32 = newTemp(Ity_V128); -+ IRTemp max10 = newTemp(Ity_V128); -+ assign(maxFE, binop(op, mkexpr(xAllF), mkexpr(xAllE))); -+ assign(maxDC, binop(op, mkexpr(xAllD), mkexpr(xAllC))); -+ assign(maxBA, binop(op, mkexpr(xAllB), mkexpr(xAllA))); -+ assign(max98, binop(op, mkexpr(xAll9), mkexpr(xAll8))); -+ assign(max76, binop(op, mkexpr(xAll7), mkexpr(xAll6))); -+ assign(max54, binop(op, mkexpr(xAll5), mkexpr(xAll4))); -+ assign(max32, binop(op, mkexpr(xAll3), mkexpr(xAll2))); -+ assign(max10, binop(op, mkexpr(xAll1), mkexpr(xAll0))); -+ IRTemp maxFEDC = newTemp(Ity_V128); -+ IRTemp maxBA98 = newTemp(Ity_V128); -+ IRTemp max7654 = newTemp(Ity_V128); -+ IRTemp max3210 = newTemp(Ity_V128); -+ assign(maxFEDC, binop(op, mkexpr(maxFE), mkexpr(maxDC))); -+ assign(maxBA98, binop(op, mkexpr(maxBA), mkexpr(max98))); -+ assign(max7654, binop(op, mkexpr(max76), mkexpr(max54))); -+ assign(max3210, binop(op, mkexpr(max32), mkexpr(max10))); -+ IRTemp maxFEDCBA98 = newTemp(Ity_V128); -+ IRTemp max76543210 = newTemp(Ity_V128); -+ assign(maxFEDCBA98, binop(op, mkexpr(maxFEDC), mkexpr(maxBA98))); -+ assign(max76543210, binop(op, mkexpr(max7654), mkexpr(max3210))); -+ IRTemp maxAllLanes = newTemp(Ity_V128); -+ assign(maxAllLanes, binop(op, mkexpr(maxFEDCBA98), -+ mkexpr(max76543210))); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, unop(Iop_ZeroHI120ofV128, mkexpr(maxAllLanes))); -+ return res; -+ } -+ case Iop_Min16Sx8: case Iop_Min16Ux8: -+ case Iop_Max16Sx8: case Iop_Max16Ux8: { -+ IRTemp x76543210 = src; -+ IRTemp x76547654 = newTemp(Ity_V128); -+ IRTemp x32103210 = newTemp(Ity_V128); -+ assign(x76547654, mk_CatOddLanes64x2 (x76543210, x76543210)); -+ assign(x32103210, mk_CatEvenLanes64x2(x76543210, x76543210)); -+ IRTemp x76767676 = newTemp(Ity_V128); -+ IRTemp x54545454 = newTemp(Ity_V128); -+ IRTemp x32323232 = newTemp(Ity_V128); -+ IRTemp x10101010 = newTemp(Ity_V128); -+ assign(x76767676, mk_CatOddLanes32x4 (x76547654, x76547654)); -+ assign(x54545454, mk_CatEvenLanes32x4(x76547654, x76547654)); -+ assign(x32323232, mk_CatOddLanes32x4 (x32103210, x32103210)); -+ assign(x10101010, mk_CatEvenLanes32x4(x32103210, x32103210)); -+ IRTemp x77777777 = newTemp(Ity_V128); -+ IRTemp x66666666 = newTemp(Ity_V128); -+ IRTemp x55555555 = newTemp(Ity_V128); -+ IRTemp x44444444 = newTemp(Ity_V128); -+ IRTemp x33333333 = newTemp(Ity_V128); -+ IRTemp x22222222 = newTemp(Ity_V128); -+ IRTemp x11111111 = newTemp(Ity_V128); -+ IRTemp x00000000 = newTemp(Ity_V128); -+ assign(x77777777, mk_CatOddLanes16x8 (x76767676, x76767676)); -+ assign(x66666666, mk_CatEvenLanes16x8(x76767676, x76767676)); -+ assign(x55555555, mk_CatOddLanes16x8 (x54545454, x54545454)); -+ assign(x44444444, mk_CatEvenLanes16x8(x54545454, x54545454)); -+ assign(x33333333, mk_CatOddLanes16x8 (x32323232, x32323232)); -+ assign(x22222222, mk_CatEvenLanes16x8(x32323232, x32323232)); -+ assign(x11111111, mk_CatOddLanes16x8 (x10101010, x10101010)); -+ assign(x00000000, mk_CatEvenLanes16x8(x10101010, x10101010)); -+ IRTemp max76 = newTemp(Ity_V128); -+ IRTemp max54 = newTemp(Ity_V128); -+ IRTemp max32 = newTemp(Ity_V128); -+ IRTemp max10 = newTemp(Ity_V128); -+ assign(max76, binop(op, mkexpr(x77777777), mkexpr(x66666666))); -+ assign(max54, binop(op, mkexpr(x55555555), mkexpr(x44444444))); -+ assign(max32, binop(op, mkexpr(x33333333), mkexpr(x22222222))); -+ assign(max10, binop(op, mkexpr(x11111111), mkexpr(x00000000))); -+ IRTemp max7654 = newTemp(Ity_V128); -+ IRTemp max3210 = newTemp(Ity_V128); -+ assign(max7654, binop(op, mkexpr(max76), mkexpr(max54))); -+ assign(max3210, binop(op, mkexpr(max32), mkexpr(max10))); -+ IRTemp max76543210 = newTemp(Ity_V128); -+ assign(max76543210, binop(op, mkexpr(max7654), mkexpr(max3210))); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, unop(Iop_ZeroHI112ofV128, mkexpr(max76543210))); -+ return res; -+ } -+ case Iop_Min32Sx4: case Iop_Min32Ux4: -+ case Iop_Max32Sx4: case Iop_Max32Ux4: { -+ IRTemp x3210 = src; -+ IRTemp x3232 = newTemp(Ity_V128); -+ IRTemp x1010 = newTemp(Ity_V128); -+ assign(x3232, mk_CatOddLanes64x2 (x3210, x3210)); -+ assign(x1010, mk_CatEvenLanes64x2(x3210, x3210)); -+ IRTemp x3333 = newTemp(Ity_V128); -+ IRTemp x2222 = newTemp(Ity_V128); -+ IRTemp x1111 = newTemp(Ity_V128); -+ IRTemp x0000 = newTemp(Ity_V128); -+ assign(x3333, mk_CatOddLanes32x4 (x3232, x3232)); -+ assign(x2222, mk_CatEvenLanes32x4(x3232, x3232)); -+ assign(x1111, mk_CatOddLanes32x4 (x1010, x1010)); -+ assign(x0000, mk_CatEvenLanes32x4(x1010, x1010)); -+ IRTemp max32 = newTemp(Ity_V128); -+ IRTemp max10 = newTemp(Ity_V128); -+ assign(max32, binop(op, mkexpr(x3333), mkexpr(x2222))); -+ assign(max10, binop(op, mkexpr(x1111), mkexpr(x0000))); -+ IRTemp max3210 = newTemp(Ity_V128); -+ assign(max3210, binop(op, mkexpr(max32), mkexpr(max10))); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, unop(Iop_ZeroHI96ofV128, mkexpr(max3210))); -+ return res; -+ } -+ default: -+ vassert(0); -+ } -+} -+ -+ -+/* Generate IR for TBL and TBX. This deals with the 128 bit case -+ only. */ -+static IRTemp math_TBL_TBX ( IRTemp tab[4], UInt len, IRTemp src, -+ IRTemp oor_values ) -+{ -+ vassert(len >= 0 && len <= 3); -+ -+ /* Generate some useful constants as concisely as possible. */ -+ IRTemp half15 = newTemp(Ity_I64); -+ assign(half15, mkU64(0x0F0F0F0F0F0F0F0FULL)); -+ IRTemp half16 = newTemp(Ity_I64); -+ assign(half16, mkU64(0x1010101010101010ULL)); -+ -+ /* A zero vector */ -+ IRTemp allZero = newTemp(Ity_V128); -+ assign(allZero, mkV128(0x0000)); -+ /* A vector containing 15 in each 8-bit lane */ -+ IRTemp all15 = newTemp(Ity_V128); -+ assign(all15, binop(Iop_64HLtoV128, mkexpr(half15), mkexpr(half15))); -+ /* A vector containing 16 in each 8-bit lane */ -+ IRTemp all16 = newTemp(Ity_V128); -+ assign(all16, binop(Iop_64HLtoV128, mkexpr(half16), mkexpr(half16))); -+ /* A vector containing 32 in each 8-bit lane */ -+ IRTemp all32 = newTemp(Ity_V128); -+ assign(all32, binop(Iop_Add8x16, mkexpr(all16), mkexpr(all16))); -+ /* A vector containing 48 in each 8-bit lane */ -+ IRTemp all48 = newTemp(Ity_V128); -+ assign(all48, binop(Iop_Add8x16, mkexpr(all16), mkexpr(all32))); -+ /* A vector containing 64 in each 8-bit lane */ -+ IRTemp all64 = newTemp(Ity_V128); -+ assign(all64, binop(Iop_Add8x16, mkexpr(all32), mkexpr(all32))); -+ -+ /* Group the 16/32/48/64 vectors so as to be indexable. */ -+ IRTemp allXX[4] = { all16, all32, all48, all64 }; -+ -+ /* Compute the result for each table vector, with zeroes in places -+ where the index values are out of range, and OR them into the -+ running vector. */ -+ IRTemp running_result = newTemp(Ity_V128); -+ assign(running_result, mkV128(0)); -+ -+ UInt tabent; -+ for (tabent = 0; tabent <= len; tabent++) { -+ vassert(tabent >= 0 && tabent < 4); -+ IRTemp bias = newTemp(Ity_V128); -+ assign(bias, -+ mkexpr(tabent == 0 ? allZero : allXX[tabent-1])); -+ IRTemp biased_indices = newTemp(Ity_V128); -+ assign(biased_indices, -+ binop(Iop_Sub8x16, mkexpr(src), mkexpr(bias))); -+ IRTemp valid_mask = newTemp(Ity_V128); -+ assign(valid_mask, -+ binop(Iop_CmpGT8Ux16, mkexpr(all16), mkexpr(biased_indices))); -+ IRTemp safe_biased_indices = newTemp(Ity_V128); -+ assign(safe_biased_indices, -+ binop(Iop_AndV128, mkexpr(biased_indices), mkexpr(all15))); -+ IRTemp results_or_junk = newTemp(Ity_V128); -+ assign(results_or_junk, -+ binop(Iop_Perm8x16, mkexpr(tab[tabent]), -+ mkexpr(safe_biased_indices))); -+ IRTemp results_or_zero = newTemp(Ity_V128); -+ assign(results_or_zero, -+ binop(Iop_AndV128, mkexpr(results_or_junk), mkexpr(valid_mask))); -+ /* And OR that into the running result. */ -+ IRTemp tmp = newTemp(Ity_V128); -+ assign(tmp, binop(Iop_OrV128, mkexpr(results_or_zero), -+ mkexpr(running_result))); -+ running_result = tmp; -+ } -+ -+ /* So now running_result holds the overall result where the indices -+ are in range, and zero in out-of-range lanes. Now we need to -+ compute an overall validity mask and use this to copy in the -+ lanes in the oor_values for out of range indices. This is -+ unnecessary for TBL but will get folded out by iropt, so we lean -+ on that and generate the same code for TBL and TBX here. */ -+ IRTemp overall_valid_mask = newTemp(Ity_V128); -+ assign(overall_valid_mask, -+ binop(Iop_CmpGT8Ux16, mkexpr(allXX[len]), mkexpr(src))); -+ IRTemp result = newTemp(Ity_V128); -+ assign(result, -+ binop(Iop_OrV128, -+ mkexpr(running_result), -+ binop(Iop_AndV128, -+ mkexpr(oor_values), -+ unop(Iop_NotV128, mkexpr(overall_valid_mask))))); -+ return result; -+} -+ -+ -+static -+Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn) -+{ -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+ /* ---------------- FMOV (general) ---------------- */ -+ /* case 30 23 20 18 15 9 4 -+ (1) 0 00 11110 00 1 00 111 000000 n d FMOV Sd, Wn -+ (2) 1 00 11110 01 1 00 111 000000 n d FMOV Dd, Xn -+ (3) 1 00 11110 10 1 01 111 000000 n d FMOV Vd.D[1], Xn -+ -+ (4) 0 00 11110 00 1 00 110 000000 n d FMOV Wd, Sn -+ (5) 1 00 11110 01 1 00 110 000000 n d FMOV Xd, Dn -+ (6) 1 00 11110 10 1 01 110 000000 n d FMOV Xd, Vn.D[1] -+ */ -+ if (INSN(30,24) == BITS7(0,0,1,1,1,1,0) -+ && INSN(21,21) == 1 && INSN(15,10) == BITS6(0,0,0,0,0,0)) { -+ UInt sf = INSN(31,31); -+ UInt ty = INSN(23,22); // type -+ UInt rm = INSN(20,19); // rmode -+ UInt op = INSN(18,16); // opcode -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt ix = 0; // case -+ if (sf == 0) { -+ if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,1)) -+ ix = 1; -+ else -+ if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,0)) -+ ix = 4; -+ } else { -+ vassert(sf == 1); -+ if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,1)) -+ ix = 2; -+ else -+ if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,0)) -+ ix = 5; -+ else -+ if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,1)) -+ ix = 3; -+ else -+ if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,0)) -+ ix = 6; -+ } -+ if (ix > 0) { -+ switch (ix) { -+ case 1: -+ putQReg128(dd, mkV128(0)); -+ putQRegLO(dd, getIReg32orZR(nn)); -+ DIP("fmov s%u, w%u\n", dd, nn); -+ break; -+ case 2: -+ putQReg128(dd, mkV128(0)); -+ putQRegLO(dd, getIReg64orZR(nn)); -+ DIP("fmov d%u, x%u\n", dd, nn); -+ break; -+ case 3: -+ putQRegHI64(dd, getIReg64orZR(nn)); -+ DIP("fmov v%u.d[1], x%u\n", dd, nn); -+ break; -+ case 4: -+ putIReg32orZR(dd, getQRegLO(nn, Ity_I32)); -+ DIP("fmov w%u, s%u\n", dd, nn); -+ break; -+ case 5: -+ putIReg64orZR(dd, getQRegLO(nn, Ity_I64)); -+ DIP("fmov x%u, d%u\n", dd, nn); -+ break; -+ case 6: -+ putIReg64orZR(dd, getQRegHI64(nn)); -+ DIP("fmov x%u, v%u.d[1]\n", dd, nn); -+ break; -+ default: -+ vassert(0); -+ } -+ return True; -+ } -+ /* undecodable; fall through */ -+ } -+ -+ /* -------------- FMOV (scalar, immediate) -------------- */ -+ /* 31 28 23 20 12 9 4 -+ 000 11110 00 1 imm8 100 00000 d FMOV Sd, #imm -+ 000 11110 01 1 imm8 100 00000 d FMOV Dd, #imm -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,21) == 1 && INSN(12,5) == BITS8(1,0,0,0,0,0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt imm8 = INSN(20,13); -+ UInt dd = INSN(4,0); -+ ULong imm = VFPExpandImm(imm8, isD ? 64 : 32); -+ if (!isD) { -+ vassert(0 == (imm & 0xFFFFFFFF00000000ULL)); -+ } -+ putQReg128(dd, mkV128(0)); -+ putQRegLO(dd, isD ? mkU64(imm) : mkU32(imm & 0xFFFFFFFFULL)); -+ DIP("fmov %s, #0x%llx\n", -+ nameQRegLO(dd, isD ? Ity_F64 : Ity_F32), imm); -+ return True; -+ } -+ -+ /* -------------- {FMOV,MOVI} (vector, immediate) -------------- */ -+ /* 31 28 18 15 11 9 4 -+ 0q op 01111 00000 abc cmode 01 defgh d MOV Dd, #imm (q=0) -+ MOV Vd.2d #imm (q=1) -+ Allowable op:cmode -+ FMOV = 1:1111 -+ MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, 11110 -+ */ -+ if (INSN(31,31) == 0 -+ && INSN(28,19) == BITS10(0,1,1,1,1,0,0,0,0,0) -+ && INSN(11,10) == BITS2(0,1)) { -+ UInt bitQ = INSN(30,30); -+ UInt bitOP = INSN(29,29); -+ UInt cmode = INSN(15,12); -+ UInt imm8 = (INSN(18,16) << 5) | INSN(9,5); -+ UInt dd = INSN(4,0); -+ ULong imm64lo = 0; -+ UInt op_cmode = (bitOP << 4) | cmode; -+ Bool ok = False; -+ switch (op_cmode) { -+ case BITS5(1,1,1,1,1): // 1:1111 -+ case BITS5(0,0,0,0,0): case BITS5(0,0,1,0,0): -+ case BITS5(0,1,0,0,0): case BITS5(0,1,1,0,0): // 0:xx00 -+ case BITS5(1,0,0,0,0): case BITS5(1,0,1,0,0): // 1:0x00 -+ case BITS5(1,1,0,0,0): case BITS5(1,1,0,1,0): // 1:10x0 -+ case BITS5(1,1,1,0,0): case BITS5(1,1,1,0,1): // 1:110x -+ case BITS5(1,1,1,1,0): // 1:1110 -+ ok = True; break; -+ default: -+ break; -+ } -+ if (ok) { -+ ok = AdvSIMDExpandImm(&imm64lo, bitOP, cmode, imm8); -+ } -+ if (ok) { -+ ULong imm64hi = (bitQ == 0 && bitOP == 0) ? 0 : imm64lo; -+ putQReg128(dd, binop(Iop_64HLtoV128, mkU64(imm64hi), mkU64(imm64lo))); -+ DIP("mov %s, #0x%016llx'%016llx\n", nameQReg128(dd), imm64hi, imm64lo); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------- {S,U}CVTF (scalar, integer) -------------- */ -+ /* 31 28 23 21 20 18 15 9 4 ix -+ 000 11110 00 1 00 010 000000 n d SCVTF Sd, Wn 0 -+ 000 11110 01 1 00 010 000000 n d SCVTF Dd, Wn 1 -+ 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn 2 -+ 100 11110 01 1 00 010 000000 n d SCVTF Dd, Xn 3 -+ -+ 000 11110 00 1 00 011 000000 n d UCVTF Sd, Wn 4 -+ 000 11110 01 1 00 011 000000 n d UCVTF Dd, Wn 5 -+ 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn 6 -+ 100 11110 01 1 00 011 000000 n d UCVTF Dd, Xn 7 -+ -+ These are signed/unsigned conversion from integer registers to -+ FP registers, all 4 32/64-bit combinations, rounded per FPCR. -+ */ -+ if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) && INSN(21,17) == BITS5(1,0,0,0,1) -+ && INSN(15,10) == BITS6(0,0,0,0,0,0)) { -+ Bool isI64 = INSN(31,31) == 1; -+ Bool isF64 = INSN(22,22) == 1; -+ Bool isU = INSN(16,16) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0); -+ const IROp ops[8] -+ = { Iop_I32StoF32, Iop_I32StoF64, Iop_I64StoF32, Iop_I64StoF64, -+ Iop_I32UtoF32, Iop_I32UtoF64, Iop_I64UtoF32, Iop_I64UtoF64 }; -+ IRExpr* src = getIRegOrZR(isI64, nn); -+ IRExpr* res = (isF64 && !isI64) -+ ? unop(ops[ix], src) -+ : binop(ops[ix], mkexpr(mk_get_IR_rounding_mode()), src); -+ putQReg128(dd, mkV128(0)); -+ putQRegLO(dd, res); -+ DIP("%ccvtf %s, %s\n", -+ isU ? 'u' : 's', nameQRegLO(dd, isF64 ? Ity_F64 : Ity_F32), -+ nameIRegOrZR(isI64, nn)); -+ return True; -+ } -+ -+ /* ------------ F{ADD,SUB,MUL,DIV,NMUL} (scalar) ------------ */ -+ /* 31 23 20 15 11 9 4 -+ ---------------- 0000 ------ FMUL -------- -+ 000 11110 001 m 0001 10 n d FDIV Sd,Sn,Sm -+ 000 11110 011 m 0001 10 n d FDIV Dd,Dn,Dm -+ ---------------- 0010 ------ FADD -------- -+ ---------------- 0011 ------ FSUB -------- -+ ---------------- 1000 ------ FNMUL -------- -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,21) == 1 && INSN(11,10) == BITS2(1,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt op = INSN(15,12); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IROp iop = Iop_INVALID; -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ Bool neg = False; -+ const HChar* nm = "???"; -+ switch (op) { -+ case BITS4(0,0,0,0): nm = "fmul"; iop = mkMULF(ty); break; -+ case BITS4(0,0,0,1): nm = "fdiv"; iop = mkDIVF(ty); break; -+ case BITS4(0,0,1,0): nm = "fadd"; iop = mkADDF(ty); break; -+ case BITS4(0,0,1,1): nm = "fsub"; iop = mkSUBF(ty); break; -+ case BITS4(1,0,0,0): nm = "fnmul"; iop = mkMULF(ty); -+ neg = True; break; -+ default: return False; -+ } -+ vassert(iop != Iop_INVALID); -+ IRExpr* resE = triop(iop, mkexpr(mk_get_IR_rounding_mode()), -+ getQRegLO(nn, ty), getQRegLO(mm, ty)); -+ IRTemp res = newTemp(ty); -+ assign(res, neg ? unop(mkNEGF(ty),resE) : resE); -+ putQReg128(dd, mkV128(0)); -+ putQRegLO(dd, mkexpr(res)); -+ DIP("%s %s, %s, %s\n", -+ nm, nameQRegLO(dd, ty), nameQRegLO(nn, ty), nameQRegLO(mm, ty)); -+ return True; -+ } -+ -+ /* ------------ F{MOV,ABS,NEG,SQRT} D/D or S/S ------------ */ -+ /* 31 23 21 16 14 9 4 -+ 000 11110 00 10000 00 10000 n d FMOV Sd, Sn -+ 000 11110 01 10000 00 10000 n d FMOV Dd, Dn -+ ------------------ 01 --------- FABS ------ -+ ------------------ 10 --------- FNEG ------ -+ ------------------ 11 --------- FSQRT ----- -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,17) == BITS5(1,0,0,0,0) -+ && INSN(14,10) == BITS5(1,0,0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt opc = INSN(16,15); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ IRTemp res = newTemp(ty); -+ if (opc == BITS2(0,0)) { -+ assign(res, getQRegLO(nn, ty)); -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(res)); -+ DIP("fmov %s, %s\n", -+ nameQRegLO(dd, ty), nameQRegLO(nn, ty)); -+ return True; -+ } -+ if (opc == BITS2(1,0) || opc == BITS2(0,1)) { -+ Bool isAbs = opc == BITS2(0,1); -+ IROp op = isAbs ? mkABSF(ty) : mkNEGF(ty); -+ assign(res, unop(op, getQRegLO(nn, ty))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(res)); -+ DIP("%s %s, %s\n", isAbs ? "fabs" : "fneg", -+ nameQRegLO(dd, ty), nameQRegLO(nn, ty)); -+ return True; -+ } -+ if (opc == BITS2(1,1)) { -+ assign(res, -+ binop(mkSQRTF(ty), -+ mkexpr(mk_get_IR_rounding_mode()), getQRegLO(nn, ty))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(res)); -+ DIP("fsqrt %s, %s\n", nameQRegLO(dd, ty), nameQRegLO(nn, ty)); -+ return True; -+ } -+ /* else fall through; other cases are ATC */ -+ } -+ -+ /* ---------------- F{ABS,NEG} (vector) ---------------- */ -+ /* 31 28 22 21 16 9 4 -+ 0q0 01110 1 sz 10000 01111 10 n d FABS Vd.T, Vn.T -+ 0q1 01110 1 sz 10000 01111 10 n d FNEG Vd.T, Vn.T -+ */ -+ if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,0,1) -+ && INSN(21,17) == BITS5(1,0,0,0,0) -+ && INSN(16,10) == BITS7(0,1,1,1,1,1,0)) { -+ UInt bitQ = INSN(30,30); -+ UInt bitSZ = INSN(22,22); -+ Bool isFNEG = INSN(29,29) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ const HChar* ar = "??"; -+ IRType tyF = Ity_INVALID; -+ Bool zeroHI = False; -+ Bool ok = getLaneInfo_Q_SZ(NULL, &tyF, NULL, &zeroHI, &ar, -+ (Bool)bitQ, (Bool)bitSZ); -+ if (ok) { -+ vassert(tyF == Ity_F64 || tyF == Ity_F32); -+ IROp op = (tyF == Ity_F64) ? (isFNEG ? Iop_Neg64Fx2 : Iop_Abs64Fx2) -+ : (isFNEG ? Iop_Neg32Fx4 : Iop_Abs32Fx4); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, unop(op, getQReg128(nn))); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(res)) -+ : mkexpr(res)); -+ DIP("%s %s.%s, %s.%s\n", isFNEG ? "fneg" : "fabs", -+ nameQReg128(dd), ar, nameQReg128(nn), ar); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------------- FCMP,FCMPE -------------------- */ -+ /* 31 23 20 15 9 4 -+ 000 11110 01 1 m 00 1000 n 10 000 FCMPE Dn, Dm -+ 000 11110 01 1 00000 00 1000 n 11 000 FCMPE Dn, #0.0 -+ 000 11110 01 1 m 00 1000 n 00 000 FCMP Dn, Dm -+ 000 11110 01 1 00000 00 1000 n 01 000 FCMP Dn, #0.0 -+ -+ 000 11110 00 1 m 00 1000 n 10 000 FCMPE Sn, Sm -+ 000 11110 00 1 00000 00 1000 n 11 000 FCMPE Sn, #0.0 -+ 000 11110 00 1 m 00 1000 n 00 000 FCMP Sn, Sm -+ 000 11110 00 1 00000 00 1000 n 01 000 FCMP Sn, #0.0 -+ -+ FCMPE generates Invalid Operation exn if either arg is any kind -+ of NaN. FCMP generates Invalid Operation exn if either arg is a -+ signalling NaN. We ignore this detail here and produce the same -+ IR for both. -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) && INSN(21,21) == 1 -+ && INSN(15,10) == BITS6(0,0,1,0,0,0) && INSN(2,0) == BITS3(0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ Bool isCMPE = INSN(4,4) == 1; -+ Bool cmpZero = INSN(3,3) == 1; -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ Bool valid = True; -+ if (cmpZero && mm != 0) valid = False; -+ if (valid) { -+ IRTemp argL = newTemp(ty); -+ IRTemp argR = newTemp(ty); -+ IRTemp irRes = newTemp(Ity_I32); -+ assign(argL, getQRegLO(nn, ty)); -+ assign(argR, -+ cmpZero -+ ? (IRExpr_Const(isD ? IRConst_F64i(0) : IRConst_F32i(0))) -+ : getQRegLO(mm, ty)); -+ assign(irRes, binop(isD ? Iop_CmpF64 : Iop_CmpF32, -+ mkexpr(argL), mkexpr(argR))); -+ IRTemp nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes); -+ IRTemp nzcv_28x0 = newTemp(Ity_I64); -+ assign(nzcv_28x0, binop(Iop_Shl64, mkexpr(nzcv), mkU8(28))); -+ setFlags_COPY(nzcv_28x0); -+ DIP("fcmp%s %s, %s\n", isCMPE ? "e" : "", nameQRegLO(nn, ty), -+ cmpZero ? "#0.0" : nameQRegLO(mm, ty)); -+ return True; -+ } -+ } -+ -+ /* -------------------- F{N}M{ADD,SUB} -------------------- */ -+ /* 31 22 20 15 14 9 4 ix -+ 000 11111 0 sz 0 m 0 a n d 0 FMADD Fd,Fn,Fm,Fa -+ 000 11111 0 sz 0 m 1 a n d 1 FMSUB Fd,Fn,Fm,Fa -+ 000 11111 0 sz 1 m 0 a n d 2 FNMADD Fd,Fn,Fm,Fa -+ 000 11111 0 sz 1 m 1 a n d 3 FNMSUB Fd,Fn,Fm,Fa -+ where Fx=Dx when sz=1, Fx=Sx when sz=0 -+ -+ -----SPEC------ ----IMPL---- -+ fmadd a + n * m a + n * m -+ fmsub a + (-n) * m a - n * m -+ fnmadd (-a) + (-n) * m -(a + n * m) -+ fnmsub (-a) + n * m -(a - n * m) -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,1,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt aa = INSN(14,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt ix = (INSN(21,21) << 1) | INSN(15,15); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ IROp opADD = mkADDF(ty); -+ IROp opSUB = mkSUBF(ty); -+ IROp opMUL = mkMULF(ty); -+ IROp opNEG = mkNEGF(ty); -+ IRTemp res = newTemp(ty); -+ IRExpr* eA = getQRegLO(aa, ty); -+ IRExpr* eN = getQRegLO(nn, ty); -+ IRExpr* eM = getQRegLO(mm, ty); -+ IRExpr* rm = mkexpr(mk_get_IR_rounding_mode()); -+ IRExpr* eNxM = triop(opMUL, rm, eN, eM); -+ switch (ix) { -+ case 0: assign(res, triop(opADD, rm, eA, eNxM)); break; -+ case 1: assign(res, triop(opSUB, rm, eA, eNxM)); break; -+ case 2: assign(res, unop(opNEG, triop(opADD, rm, eA, eNxM))); break; -+ case 3: assign(res, unop(opNEG, triop(opSUB, rm, eA, eNxM))); break; -+ default: vassert(0); -+ } -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(res)); -+ const HChar* names[4] = { "fmadd", "fmsub", "fnmadd", "fnmsub" }; -+ DIP("%s %s, %s, %s, %s\n", -+ names[ix], nameQRegLO(dd, ty), nameQRegLO(nn, ty), -+ nameQRegLO(mm, ty), nameQRegLO(aa, ty)); -+ return True; -+ } -+ -+ /* -------- FCVT{N,P,M,Z}{S,U} (scalar, integer) -------- */ -+ /* 30 23 20 18 15 9 4 -+ sf 00 11110 0x 1 00 000 000000 n d FCVTNS Rd, Fn (round to -+ sf 00 11110 0x 1 00 001 000000 n d FCVTNU Rd, Fn nearest) -+ ---------------- 01 -------------- FCVTP-------- (round to +inf) -+ ---------------- 10 -------------- FCVTM-------- (round to -inf) -+ ---------------- 11 -------------- FCVTZ-------- (round to zero) -+ -+ Rd is Xd when sf==1, Wd when sf==0 -+ Fn is Dn when x==1, Sn when x==0 -+ 20:19 carry the rounding mode, using the same encoding as FPCR -+ */ -+ if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) && INSN(21,21) == 1 -+ && INSN(18,17) == BITS2(0,0) && INSN(15,10) == BITS6(0,0,0,0,0,0)) { -+ Bool isI64 = INSN(31,31) == 1; -+ Bool isF64 = INSN(22,22) == 1; -+ UInt rm = INSN(20,19); -+ Bool isU = INSN(16,16) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ /* Decide on the IR rounding mode to use. */ -+ IRRoundingMode irrm = 8; /*impossible*/ -+ HChar ch = '?'; -+ switch (rm) { -+ case BITS2(0,0): ch = 'n'; irrm = Irrm_NEAREST; break; -+ case BITS2(0,1): ch = 'p'; irrm = Irrm_PosINF; break; -+ case BITS2(1,0): ch = 'm'; irrm = Irrm_NegINF; break; -+ case BITS2(1,1): ch = 'z'; irrm = Irrm_ZERO; break; -+ default: vassert(0); -+ } -+ vassert(irrm != 8); -+ /* Decide on the conversion primop, based on the source size, -+ dest size and signedness (8 possibilities). Case coding: -+ F32 ->s I32 0 -+ F32 ->u I32 1 -+ F32 ->s I64 2 -+ F32 ->u I64 3 -+ F64 ->s I32 4 -+ F64 ->u I32 5 -+ F64 ->s I64 6 -+ F64 ->u I64 7 -+ */ -+ UInt ix = (isF64 ? 4 : 0) | (isI64 ? 2 : 0) | (isU ? 1 : 0); -+ vassert(ix < 8); -+ const IROp ops[8] -+ = { Iop_F32toI32S, Iop_F32toI32U, Iop_F32toI64S, Iop_F32toI64U, -+ Iop_F64toI32S, Iop_F64toI32U, Iop_F64toI64S, Iop_F64toI64U }; -+ IROp op = ops[ix]; -+ // A bit of ATCery: bounce all cases we haven't seen an example of. -+ if (/* F32toI32S */ -+ (op == Iop_F32toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Sn */ -+ || (op == Iop_F32toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Sn */ -+ || (op == Iop_F32toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Sn */ -+ /* F32toI32U */ -+ || (op == Iop_F32toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Sn */ -+ || (op == Iop_F32toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Sn */ -+ /* F32toI64S */ -+ || (op == Iop_F32toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Sn */ -+ /* F32toI64U */ -+ || (op == Iop_F32toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Sn */ -+ /* F64toI32S */ -+ || (op == Iop_F64toI32S && irrm == Irrm_ZERO) /* FCVTZS Wd,Dn */ -+ || (op == Iop_F64toI32S && irrm == Irrm_NegINF) /* FCVTMS Wd,Dn */ -+ || (op == Iop_F64toI32S && irrm == Irrm_PosINF) /* FCVTPS Wd,Dn */ -+ /* F64toI32U */ -+ || (op == Iop_F64toI32U && irrm == Irrm_ZERO) /* FCVTZU Wd,Dn */ -+ || (op == Iop_F64toI32U && irrm == Irrm_NegINF) /* FCVTMU Wd,Dn */ -+ || (op == Iop_F64toI32U && irrm == Irrm_PosINF) /* FCVTPU Wd,Dn */ -+ /* F64toI64S */ -+ || (op == Iop_F64toI64S && irrm == Irrm_ZERO) /* FCVTZS Xd,Dn */ -+ || (op == Iop_F64toI64S && irrm == Irrm_NegINF) /* FCVTMS Xd,Dn */ -+ || (op == Iop_F64toI64S && irrm == Irrm_PosINF) /* FCVTPS Xd,Dn */ -+ /* F64toI64U */ -+ || (op == Iop_F64toI64U && irrm == Irrm_ZERO) /* FCVTZU Xd,Dn */ -+ || (op == Iop_F64toI64U && irrm == Irrm_PosINF) /* FCVTPU Xd,Dn */ -+ ) { -+ /* validated */ -+ } else { -+ return False; -+ } -+ IRType srcTy = isF64 ? Ity_F64 : Ity_F32; -+ IRType dstTy = isI64 ? Ity_I64 : Ity_I32; -+ IRTemp src = newTemp(srcTy); -+ IRTemp dst = newTemp(dstTy); -+ assign(src, getQRegLO(nn, srcTy)); -+ assign(dst, binop(op, mkU32(irrm), mkexpr(src))); -+ putIRegOrZR(isI64, dd, mkexpr(dst)); -+ DIP("fcvt%c%c %s, %s\n", ch, isU ? 'u' : 's', -+ nameIRegOrZR(isI64, dd), nameQRegLO(nn, srcTy)); -+ return True; -+ } -+ -+ /* -------- FCVTAS (KLUDGED) (scalar, integer) -------- */ -+ /* 30 23 20 18 15 9 4 -+ 1 00 11110 0x 1 00 100 000000 n d FCVTAS Xd, Fn -+ 0 00 11110 0x 1 00 100 000000 n d FCVTAS Wd, Fn -+ Fn is Dn when x==1, Sn when x==0 -+ */ -+ if (INSN(30,23) == BITS8(0,0,1,1,1,1,0,0) -+ && INSN(21,16) == BITS6(1,0,0,1,0,0) -+ && INSN(15,10) == BITS6(0,0,0,0,0,0)) { -+ Bool isI64 = INSN(31,31) == 1; -+ Bool isF64 = INSN(22,22) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ /* Decide on the IR rounding mode to use. */ -+ /* KLUDGE: should be Irrm_NEAREST_TIE_AWAY_0 */ -+ IRRoundingMode irrm = Irrm_NEAREST; -+ /* Decide on the conversion primop. */ -+ IROp op = isI64 ? (isF64 ? Iop_F64toI64S : Iop_F32toI64S) -+ : (isF64 ? Iop_F64toI32S : Iop_F32toI32S); -+ IRType srcTy = isF64 ? Ity_F64 : Ity_F32; -+ IRType dstTy = isI64 ? Ity_I64 : Ity_I32; -+ IRTemp src = newTemp(srcTy); -+ IRTemp dst = newTemp(dstTy); -+ assign(src, getQRegLO(nn, srcTy)); -+ assign(dst, binop(op, mkU32(irrm), mkexpr(src))); -+ putIRegOrZR(isI64, dd, mkexpr(dst)); -+ DIP("fcvtas %s, %s (KLUDGED)\n", -+ nameIRegOrZR(isI64, dd), nameQRegLO(nn, srcTy)); -+ return True; -+ } -+ -+ /* ---------------- FRINT{I,M,P,Z} (scalar) ---------------- */ -+ /* 31 23 21 17 14 9 4 -+ 000 11110 0x 1001 111 10000 n d FRINTI Fd, Fm (round per FPCR) -+ rm -+ x==0 => S-registers, x==1 => D-registers -+ rm (17:15) encodings: -+ 111 per FPCR (FRINTI) -+ 001 +inf (FRINTP) -+ 010 -inf (FRINTM) -+ 011 zero (FRINTZ) -+ 000 tieeven -+ 100 tieaway (FRINTA) -- !! FIXME KLUDGED !! -+ 110 per FPCR + "exact = TRUE" -+ 101 unallocated -+ */ -+ if (INSN(31,23) == BITS9(0,0,0,1,1,1,1,0,0) -+ && INSN(21,18) == BITS4(1,0,0,1) && INSN(14,10) == BITS5(1,0,0,0,0)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt rm = INSN(17,15); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ IRExpr* irrmE = NULL; -+ UChar ch = '?'; -+ switch (rm) { -+ case BITS3(0,1,1): ch = 'z'; irrmE = mkU32(Irrm_ZERO); break; -+ case BITS3(0,1,0): ch = 'm'; irrmE = mkU32(Irrm_NegINF); break; -+ case BITS3(0,0,1): ch = 'p'; irrmE = mkU32(Irrm_PosINF); break; -+ // The following is a kludge. Should be: Irrm_NEAREST_TIE_AWAY_0 -+ case BITS3(1,0,0): ch = 'a'; irrmE = mkU32(Irrm_NEAREST); break; -+ default: break; -+ } -+ if (irrmE) { -+ IRTemp src = newTemp(ty); -+ IRTemp dst = newTemp(ty); -+ assign(src, getQRegLO(nn, ty)); -+ assign(dst, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt, -+ irrmE, mkexpr(src))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(dst)); -+ DIP("frint%c %s, %s\n", -+ ch, nameQRegLO(dd, ty), nameQRegLO(nn, ty)); -+ return True; -+ } -+ /* else unhandled rounding mode case -- fall through */ -+ } -+ -+ /* ------------------ FCVT (scalar) ------------------ */ -+ /* 31 23 21 16 14 9 4 -+ 000 11110 11 10001 00 10000 n d FCVT Sd, Hn (unimp) -+ --------- 11 ----- 01 --------- FCVT Dd, Hn (unimp) -+ --------- 00 ----- 11 --------- FCVT Hd, Sn (unimp) -+ --------- 00 ----- 01 --------- FCVT Dd, Sn -+ --------- 01 ----- 11 --------- FCVT Hd, Dn (unimp) -+ --------- 01 ----- 00 --------- FCVT Sd, Dn -+ Rounding, when dst is smaller than src, is per the FPCR. -+ */ -+ if (INSN(31,24) == BITS8(0,0,0,1,1,1,1,0) -+ && INSN(21,17) == BITS5(1,0,0,0,1) -+ && INSN(14,10) == BITS5(1,0,0,0,0)) { -+ UInt b2322 = INSN(23,22); -+ UInt b1615 = INSN(16,15); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (b2322 == BITS2(0,0) && b1615 == BITS2(0,1)) { -+ /* Convert S to D */ -+ IRTemp res = newTemp(Ity_F64); -+ assign(res, unop(Iop_F32toF64, getQRegLO(nn, Ity_F32))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(res)); -+ DIP("fcvt %s, %s\n", -+ nameQRegLO(dd, Ity_F64), nameQRegLO(nn, Ity_F32)); -+ return True; -+ } -+ if (b2322 == BITS2(0,1) && b1615 == BITS2(0,0)) { -+ /* Convert D to S */ -+ IRTemp res = newTemp(Ity_F32); -+ assign(res, binop(Iop_F64toF32, mkexpr(mk_get_IR_rounding_mode()), -+ getQRegLO(nn, Ity_F64))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(res)); -+ DIP("fcvt %s, %s\n", -+ nameQRegLO(dd, Ity_F32), nameQRegLO(nn, Ity_F64)); -+ return True; -+ } -+ /* else unhandled */ -+ } -+ -+ /* ------------------ FABD (scalar) ------------------ */ -+ /* 31 23 20 15 9 4 -+ 011 11110 111 m 110101 n d FABD Dd, Dn, Dm -+ 011 11110 101 m 110101 n d FABD Sd, Sn, Sm -+ */ -+ if (INSN(31,23) == BITS9(0,1,1,1,1,1,1,0,1) && INSN(21,21) == 1 -+ && INSN(15,10) == BITS6(1,1,0,1,0,1)) { -+ Bool isD = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRType ty = isD ? Ity_F64 : Ity_F32; -+ IRTemp res = newTemp(ty); -+ assign(res, unop(mkABSF(ty), -+ triop(mkSUBF(ty), -+ mkexpr(mk_get_IR_rounding_mode()), -+ getQRegLO(nn,ty), getQRegLO(mm,ty)))); -+ putQReg128(dd, mkV128(0x0000)); -+ putQRegLO(dd, mkexpr(res)); -+ DIP("fabd %s, %s, %s\n", -+ nameQRegLO(dd, ty), nameQRegLO(nn, ty), nameQRegLO(mm, ty)); -+ return True; -+ } -+ -+ /* -------------- {S,U}CVTF (vector, integer) -------------- */ -+ /* 31 28 22 21 15 9 4 -+ 0q0 01110 0 sz 1 00001 110110 n d SCVTF Vd, Vn -+ 0q1 01110 0 sz 1 00001 110110 n d UCVTF Vd, Vn -+ with laneage: -+ case sz:Q of 00 -> 2S, zero upper, 01 -> 4S, 10 -> illegal, 11 -> 2D -+ */ -+ if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,0,0) -+ && INSN(21,16) == BITS6(1,0,0,0,0,1) -+ && INSN(15,10) == BITS6(1,1,0,1,1,0)) { -+ Bool isQ = INSN(30,30) == 1; -+ Bool isU = INSN(29,29) == 1; -+ Bool isF64 = INSN(22,22) == 1; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (isQ || !isF64) { -+ IRType tyF = Ity_INVALID, tyI = Ity_INVALID; -+ UInt nLanes = 0; -+ Bool zeroHI = False; -+ const HChar* arrSpec = NULL; -+ Bool ok = getLaneInfo_Q_SZ(&tyI, &tyF, &nLanes, &zeroHI, &arrSpec, -+ isQ, isF64 ); -+ IROp op = isU ? (isF64 ? Iop_I64UtoF64 : Iop_I32UtoF32) -+ : (isF64 ? Iop_I64StoF64 : Iop_I32StoF32); -+ IRTemp rm = mk_get_IR_rounding_mode(); -+ UInt i; -+ vassert(ok); /* the 'if' above should ensure this */ -+ for (i = 0; i < nLanes; i++) { -+ putQRegLane(dd, i, -+ binop(op, mkexpr(rm), getQRegLane(nn, i, tyI))); -+ } -+ if (zeroHI) { -+ putQRegLane(dd, 1, mkU64(0)); -+ } -+ DIP("%ccvtf %s.%s, %s.%s\n", isU ? 'u' : 's', -+ nameQReg128(dd), arrSpec, nameQReg128(nn), arrSpec); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ---------- F{ADD,SUB,MUL,DIV,MLA,MLS} (vector) ---------- */ -+ /* 31 28 22 21 20 15 9 4 case -+ 0q0 01110 0 sz 1 m 110101 n d FADD Vd,Vn,Vm 1 -+ 0q0 01110 1 sz 1 m 110101 n d FSUB Vd,Vn,Vm 2 -+ 0q1 01110 0 sz 1 m 110111 n d FMUL Vd,Vn,Vm 3 -+ 0q1 01110 0 sz 1 m 111111 n d FDIV Vd,Vn,Vm 4 -+ 0q0 01110 0 sz 1 m 110011 n d FMLA Vd,Vn,Vm 5 -+ 0q0 01110 1 sz 1 m 110011 n d FMLS Vd,Vn,Vm 6 -+ 0q1 01110 1 sz 1 m 110101 n d FABD Vd,Vn,Vm 7 -+ */ -+ if (INSN(31,31) == 0 -+ && INSN(28,24) == BITS5(0,1,1,1,0) && INSN(21,21) == 1) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt b29 = INSN(29,29); -+ UInt b23 = INSN(23,23); -+ Bool isF64 = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt b1510 = INSN(15,10); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt ix = 0; -+ /**/ if (b29 == 0 && b23 == 0 && b1510 == BITS6(1,1,0,1,0,1)) ix = 1; -+ else if (b29 == 0 && b23 == 1 && b1510 == BITS6(1,1,0,1,0,1)) ix = 2; -+ else if (b29 == 1 && b23 == 0 && b1510 == BITS6(1,1,0,1,1,1)) ix = 3; -+ else if (b29 == 1 && b23 == 0 && b1510 == BITS6(1,1,1,1,1,1)) ix = 4; -+ else if (b29 == 0 && b23 == 0 && b1510 == BITS6(1,1,0,0,1,1)) ix = 5; -+ else if (b29 == 0 && b23 == 1 && b1510 == BITS6(1,1,0,0,1,1)) ix = 6; -+ else if (b29 == 1 && b23 == 1 && b1510 == BITS6(1,1,0,1,0,1)) ix = 7; -+ IRType laneTy = Ity_INVALID; -+ Bool zeroHI = False; -+ const HChar* arr = "??"; -+ Bool ok -+ = getLaneInfo_Q_SZ(NULL, &laneTy, NULL, &zeroHI, &arr, isQ, isF64); -+ /* Skip MLA/MLS for the time being */ -+ if (ok && ix >= 1 && ix <= 4) { -+ const IROp ops64[4] -+ = { Iop_Add64Fx2, Iop_Sub64Fx2, Iop_Mul64Fx2, Iop_Div64Fx2 }; -+ const IROp ops32[4] -+ = { Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4 }; -+ const HChar* names[4] -+ = { "fadd", "fsub", "fmul", "fdiv" }; -+ IROp op = laneTy==Ity_F64 ? ops64[ix-1] : ops32[ix-1]; -+ IRTemp rm = mk_get_IR_rounding_mode(); -+ IRTemp t1 = newTemp(Ity_V128); -+ IRTemp t2 = newTemp(Ity_V128); -+ assign(t1, triop(op, mkexpr(rm), getQReg128(nn), getQReg128(mm))); -+ assign(t2, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t1)) -+ : mkexpr(t1)); -+ putQReg128(dd, mkexpr(t2)); -+ DIP("%s %s.%s, %s.%s, %s.%s\n", names[ix-1], -+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr); -+ return True; -+ } -+ if (ok && ix >= 5 && ix <= 6) { -+ IROp opADD = laneTy==Ity_F64 ? Iop_Add64Fx2 : Iop_Add32Fx4; -+ IROp opSUB = laneTy==Ity_F64 ? Iop_Sub64Fx2 : Iop_Sub32Fx4; -+ IROp opMUL = laneTy==Ity_F64 ? Iop_Mul64Fx2 : Iop_Mul32Fx4; -+ IRTemp rm = mk_get_IR_rounding_mode(); -+ IRTemp t1 = newTemp(Ity_V128); -+ IRTemp t2 = newTemp(Ity_V128); -+ // FIXME: double rounding; use FMA primops instead -+ assign(t1, triop(opMUL, -+ mkexpr(rm), getQReg128(nn), getQReg128(mm))); -+ assign(t2, triop(ix == 5 ? opADD : opSUB, -+ mkexpr(rm), getQReg128(dd), mkexpr(t1))); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t2)) -+ : mkexpr(t2)); -+ DIP("%s %s.%s, %s.%s, %s.%s\n", ix == 5 ? "fmla" : "fmls", -+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr); -+ return True; -+ } -+ if (ok && ix == 7) { -+ IROp opSUB = laneTy==Ity_F64 ? Iop_Sub64Fx2 : Iop_Sub32Fx4; -+ IROp opABS = laneTy==Ity_F64 ? Iop_Abs64Fx2 : Iop_Abs32Fx4; -+ IRTemp rm = mk_get_IR_rounding_mode(); -+ IRTemp t1 = newTemp(Ity_V128); -+ IRTemp t2 = newTemp(Ity_V128); -+ // FIXME: use Abd primop instead? -+ assign(t1, triop(opSUB, -+ mkexpr(rm), getQReg128(nn), getQReg128(mm))); -+ assign(t2, unop(opABS, mkexpr(t1))); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t2)) -+ : mkexpr(t2)); -+ DIP("fabd %s.%s, %s.%s, %s.%s\n", -+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr); -+ return True; -+ } -+ } -+ -+ /* ------------ FCM{EQ,GE,GT}, FAC{GE,GT} (vector) ------------ */ -+ /* 31 28 22 20 15 9 4 case -+ 0q1 01110 0 sz 1 m 111011 n d FACGE Vd, Vn, Vm -+ 0q1 01110 1 sz 1 m 111011 n d FACGT Vd, Vn, Vm -+ 0q0 01110 0 sz 1 m 111001 n d FCMEQ Vd, Vn, Vm -+ 0q1 01110 0 sz 1 m 111001 n d FCMGE Vd, Vn, Vm -+ 0q1 01110 1 sz 1 m 111001 n d FCMGT Vd, Vn, Vm -+ */ -+ if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0) && INSN(21,21) == 1 -+ && INSN(15,12) == BITS4(1,1,1,0) && INSN(10,10) == 1) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt U = INSN(29,29); -+ UInt E = INSN(23,23); -+ Bool isF64 = INSN(22,22) == 1; -+ UInt ac = INSN(11,11); -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ /* */ -+ UInt EUac = (E << 2) | (U << 1) | ac; -+ IROp opABS = Iop_INVALID; -+ IROp opCMP = Iop_INVALID; -+ IRType laneTy = Ity_INVALID; -+ Bool zeroHI = False; -+ Bool swap = True; -+ const HChar* arr = "??"; -+ const HChar* nm = "??"; -+ Bool ok -+ = getLaneInfo_Q_SZ(NULL, &laneTy, NULL, &zeroHI, &arr, isQ, isF64); -+ if (ok) { -+ vassert((isF64 && laneTy == Ity_F64) || (!isF64 && laneTy == Ity_F32)); -+ switch (EUac) { -+ case BITS3(0,0,0): -+ nm = "fcmeq"; -+ opCMP = isF64 ? Iop_CmpEQ64Fx2 : Iop_CmpEQ32Fx4; -+ swap = False; -+ break; -+ case BITS3(0,1,0): -+ nm = "fcmge"; -+ opCMP = isF64 ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4; -+ break; -+ case BITS3(0,1,1): -+ nm = "facge"; -+ opCMP = isF64 ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4; -+ opABS = isF64 ? Iop_Abs64Fx2 : Iop_Abs32Fx4; -+ break; -+ case BITS3(1,1,0): -+ nm = "fcmgt"; -+ opCMP = isF64 ? Iop_CmpLT64Fx2 : Iop_CmpLT32Fx4; -+ break; -+ case BITS3(1,1,1): -+ nm = "fcagt"; -+ opCMP = isF64 ? Iop_CmpLE64Fx2 : Iop_CmpLE32Fx4; -+ opABS = isF64 ? Iop_Abs64Fx2 : Iop_Abs32Fx4; -+ break; -+ default: -+ break; -+ } -+ } -+ if (opCMP != Iop_INVALID) { -+ IRExpr* argN = getQReg128(nn); -+ IRExpr* argM = getQReg128(mm); -+ if (opABS != Iop_INVALID) { -+ argN = unop(opABS, argN); -+ argM = unop(opABS, argM); -+ } -+ IRExpr* res = swap ? binop(opCMP, argM, argN) -+ : binop(opCMP, argN, argM); -+ if (zeroHI) { -+ res = unop(Iop_ZeroHI64ofV128, res); -+ } -+ putQReg128(dd, res); -+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm, -+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------------- FCVTN -------------------- */ -+ /* 31 28 23 20 15 9 4 -+ 0q0 01110 0s1 00001 011010 n d FCVTN Vd, Vn -+ where case q:s of 00: 16Fx4(lo) <- 32Fx4 -+ 01: 32Fx2(lo) <- 64Fx2 -+ 10: 16Fx4(hi) <- 32Fx4 -+ 11: 32Fx2(hi) <- 64Fx2 -+ Only deals with the 32Fx2 <- 64Fx2 version (s==1) -+ */ -+ if (INSN(31,31) == 0 && INSN(29,23) == BITS7(0,0,1,1,1,0,0) -+ && INSN(21,10) == BITS12(1,0,0,0,0,1,0,1,1,0,1,0)) { -+ UInt bQ = INSN(30,30); -+ UInt bS = INSN(22,22); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (bS == 1) { -+ IRTemp rm = mk_get_IR_rounding_mode(); -+ IRExpr* srcLo = getQRegLane(nn, 0, Ity_F64); -+ IRExpr* srcHi = getQRegLane(nn, 1, Ity_F64); -+ putQRegLane(dd, 2 * bQ + 0, binop(Iop_F64toF32, mkexpr(rm), srcLo)); -+ putQRegLane(dd, 2 * bQ + 1, binop(Iop_F64toF32, mkexpr(rm), srcHi)); -+ if (bQ == 0) { -+ putQRegLane(dd, 1, mkU64(0)); -+ } -+ DIP("fcvtn%s %s.%s, %s.2d\n", bQ ? "2" : "", -+ nameQReg128(dd), bQ ? "4s" : "2s", nameQReg128(nn)); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ---------------- ADD/SUB (vector) ---------------- */ -+ /* 31 28 23 21 20 15 9 4 -+ 0q0 01110 size 1 m 100001 n d ADD Vd.T, Vn.T, Vm.T -+ 0q1 01110 size 1 m 100001 n d SUB Vd.T, Vn.T, Vm.T -+ */ -+ if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0) -+ && INSN(21,21) == 1 && INSN(15,10) == BITS6(1,0,0,0,0,1)) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt szBlg2 = INSN(23,22); -+ Bool isSUB = INSN(29,29) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool zeroHI = False; -+ const HChar* arrSpec = ""; -+ Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 ); -+ if (ok) { -+ const IROp opsADD[4] -+ = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2 }; -+ const IROp opsSUB[4] -+ = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 }; -+ vassert(szBlg2 < 4); -+ IROp op = isSUB ? opsSUB[szBlg2] : opsADD[szBlg2]; -+ IRTemp t = newTemp(Ity_V128); -+ assign(t, binop(op, getQReg128(nn), getQReg128(mm))); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t)) -+ : mkexpr(t)); -+ const HChar* nm = isSUB ? "sub" : "add"; -+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm, -+ nameQReg128(dd), arrSpec, -+ nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ---------------- ADD/SUB (scalar) ---------------- */ -+ /* 31 28 23 21 20 15 9 4 -+ 010 11110 11 1 m 100001 n d ADD Dd, Dn, Dm -+ 011 11110 11 1 m 100001 n d SUB Dd, Dn, Dm -+ */ -+ if (INSN(31,30) == BITS2(0,1) && INSN(28,21) == BITS8(1,1,1,1,0,1,1,1) -+ && INSN(15,10) == BITS6(1,0,0,0,0,1)) { -+ Bool isSUB = INSN(29,29) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp res = newTemp(Ity_I64); -+ assign(res, binop(isSUB ? Iop_Sub64 : Iop_Add64, -+ getQRegLane(nn, 0, Ity_I64), -+ getQRegLane(mm, 0, Ity_I64))); -+ putQRegLane(dd, 0, mkexpr(res)); -+ putQRegLane(dd, 1, mkU64(0)); -+ DIP("%s %s, %s, %s\n", isSUB ? "sub" : "add", -+ nameQRegLO(dd, Ity_I64), -+ nameQRegLO(nn, Ity_I64), nameQRegLO(mm, Ity_I64)); -+ return True; -+ } -+ -+ /* ------------ MUL/PMUL/MLA/MLS (vector) ------------ */ -+ /* 31 28 23 21 20 15 9 4 -+ 0q0 01110 size 1 m 100111 n d MUL Vd.T, Vn.T, Vm.T B/H/S only -+ 0q1 01110 size 1 m 100111 n d PMUL Vd.T, Vn.T, Vm.T B only -+ 0q0 01110 size 1 m 100101 n d MLA Vd.T, Vn.T, Vm.T B/H/S only -+ 0q1 01110 size 1 m 100101 n d MLS Vd.T, Vn.T, Vm.T B/H/S only -+ */ -+ if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0) -+ && INSN(21,21) == 1 -+ && (INSN(15,10) & BITS6(1,1,1,1,0,1)) == BITS6(1,0,0,1,0,1)) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt szBlg2 = INSN(23,22); -+ UInt bit29 = INSN(29,29); -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool isMLAS = INSN(11,11) == 0; -+ const IROp opsADD[4] -+ = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_INVALID }; -+ const IROp opsSUB[4] -+ = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_INVALID }; -+ const IROp opsMUL[4] -+ = { Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4, Iop_INVALID }; -+ const IROp opsPMUL[4] -+ = { Iop_PolynomialMul8x16, Iop_INVALID, Iop_INVALID, Iop_INVALID }; -+ /* Set opMUL and, if necessary, opACC. A result value of -+ Iop_INVALID for opMUL indicates that the instruction is -+ invalid. */ -+ Bool zeroHI = False; -+ const HChar* arrSpec = ""; -+ Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 ); -+ vassert(szBlg2 < 4); -+ IROp opACC = Iop_INVALID; -+ IROp opMUL = Iop_INVALID; -+ if (ok) { -+ opMUL = (bit29 == 1 && !isMLAS) ? opsPMUL[szBlg2] -+ : opsMUL[szBlg2]; -+ opACC = isMLAS ? (bit29 == 1 ? opsSUB[szBlg2] : opsADD[szBlg2]) -+ : Iop_INVALID; -+ } -+ if (ok && opMUL != Iop_INVALID) { -+ IRTemp t1 = newTemp(Ity_V128); -+ assign(t1, binop(opMUL, getQReg128(nn), getQReg128(mm))); -+ IRTemp t2 = newTemp(Ity_V128); -+ assign(t2, opACC == Iop_INVALID -+ ? mkexpr(t1) -+ : binop(opACC, getQReg128(dd), mkexpr(t1))); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t2)) -+ : mkexpr(t2)); -+ const HChar* nm = isMLAS ? (bit29 == 1 ? "mls" : "mla") -+ : (bit29 == 1 ? "pmul" : "mul"); -+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm, -+ nameQReg128(dd), arrSpec, -+ nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ---------------- {S,U}{MIN,MAX} (vector) ---------------- */ -+ /* 31 28 23 21 20 15 9 4 -+ 0q0 01110 size 1 m 011011 n d SMIN Vd.T, Vn.T, Vm.T -+ 0q1 01110 size 1 m 011011 n d UMIN Vd.T, Vn.T, Vm.T -+ 0q0 01110 size 1 m 011001 n d SMAX Vd.T, Vn.T, Vm.T -+ 0q1 01110 size 1 m 011001 n d UMAX Vd.T, Vn.T, Vm.T -+ */ -+ if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0) -+ && INSN(21,21) == 1 -+ && ((INSN(15,10) & BITS6(1,1,1,1,0,1)) == BITS6(0,1,1,0,0,1))) { -+ Bool isQ = INSN(30,30) == 1; -+ Bool isU = INSN(29,29) == 1; -+ UInt szBlg2 = INSN(23,22); -+ Bool isMAX = INSN(11,11) == 0; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool zeroHI = False; -+ const HChar* arrSpec = ""; -+ Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 ); -+ if (ok) { -+ const IROp opMINS[4] -+ = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4, Iop_Min64Sx2 }; -+ const IROp opMINU[4] -+ = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4, Iop_Min64Ux2 }; -+ const IROp opMAXS[4] -+ = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4, Iop_Max64Sx2 }; -+ const IROp opMAXU[4] -+ = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4, Iop_Max64Ux2 }; -+ vassert(szBlg2 < 4); -+ IROp op = isMAX ? (isU ? opMAXU[szBlg2] : opMAXS[szBlg2]) -+ : (isU ? opMINU[szBlg2] : opMINS[szBlg2]); -+ IRTemp t = newTemp(Ity_V128); -+ assign(t, binop(op, getQReg128(nn), getQReg128(mm))); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(t)) -+ : mkexpr(t)); -+ const HChar* nm = isMAX ? (isU ? "umax" : "smax") -+ : (isU ? "umin" : "smin"); -+ DIP("%s %s.%s, %s.%s, %s.%s\n", nm, -+ nameQReg128(dd), arrSpec, -+ nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------------- {S,U}{MIN,MAX}V -------------------- */ -+ /* 31 28 23 21 16 15 9 4 -+ 0q0 01110 size 11000 1 101010 n d SMINV Vd, Vn.T -+ 0q1 01110 size 11000 1 101010 n d UMINV Vd, Vn.T -+ 0q0 01110 size 11000 0 101010 n d SMAXV Vd, Vn.T -+ 0q1 01110 size 11000 0 101010 n d UMAXV Vd, Vn.T -+ */ -+ if (INSN(31,31) == 0 && INSN(28,24) == BITS5(0,1,1,1,0) -+ && INSN(21,17) == BITS5(1,1,0,0,0) -+ && INSN(15,10) == BITS6(1,0,1,0,1,0)) { -+ Bool isQ = INSN(30,30) == 1; -+ Bool isU = INSN(29,29) == 1; -+ UInt szBlg2 = INSN(23,22); -+ Bool isMAX = INSN(16,16) == 0; -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool zeroHI = False; -+ const HChar* arrSpec = ""; -+ Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2); -+ if (ok) { -+ if (szBlg2 == 3) ok = False; -+ if (szBlg2 == 2 && !isQ) ok = False; -+ } -+ if (ok) { -+ const IROp opMINS[3] -+ = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4 }; -+ const IROp opMINU[3] -+ = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4 }; -+ const IROp opMAXS[3] -+ = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4 }; -+ const IROp opMAXU[3] -+ = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4 }; -+ vassert(szBlg2 < 3); -+ IROp op = isMAX ? (isU ? opMAXU[szBlg2] : opMAXS[szBlg2]) -+ : (isU ? opMINU[szBlg2] : opMINS[szBlg2]); -+ IRTemp tN1 = newTemp(Ity_V128); -+ assign(tN1, getQReg128(nn)); -+ /* If Q == 0, we're just folding lanes in the lower half of -+ the value. In which case, copy the lower half of the -+ source into the upper half, so we can then treat it the -+ same as the full width case. */ -+ IRTemp tN2 = newTemp(Ity_V128); -+ assign(tN2, zeroHI ? mk_CatEvenLanes64x2(tN1,tN1) : mkexpr(tN1)); -+ IRTemp res = math_MINMAXV(tN2, op); -+ if (res == IRTemp_INVALID) -+ return False; /* means math_MINMAXV -+ doesn't handle this case yet */ -+ putQReg128(dd, mkexpr(res)); -+ const HChar* nm = isMAX ? (isU ? "umaxv" : "smaxv") -+ : (isU ? "uminv" : "sminv"); -+ const IRType tys[3] = { Ity_I8, Ity_I16, Ity_I32 }; -+ IRType laneTy = tys[szBlg2]; -+ DIP("%s %s, %s.%s\n", nm, -+ nameQRegLO(dd, laneTy), nameQReg128(nn), arrSpec); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ------------ {AND,BIC,ORR,ORN} (vector) ------------ */ -+ /* 31 28 23 20 15 9 4 -+ 0q0 01110 001 m 000111 n d AND Vd.T, Vn.T, Vm.T -+ 0q0 01110 011 m 000111 n d BIC Vd.T, Vn.T, Vm.T -+ 0q0 01110 101 m 000111 n d ORR Vd.T, Vn.T, Vm.T -+ 0q0 01110 111 m 000111 n d ORN Vd.T, Vn.T, Vm.T -+ T is 16b when q==1, 8b when q==0 -+ */ -+ if (INSN(31,31) == 0 && INSN(29,24) == BITS6(0,0,1,1,1,0) -+ && INSN(21,21) == 1 && INSN(15,10) == BITS6(0,0,0,1,1,1)) { -+ Bool isQ = INSN(30,30) == 1; -+ Bool isORR = INSN(23,23) == 1; -+ Bool invert = INSN(22,22) == 1; -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, binop(isORR ? Iop_OrV128 : Iop_AndV128, -+ getQReg128(nn), -+ invert ? unop(Iop_NotV128, getQReg128(mm)) -+ : getQReg128(mm))); -+ putQReg128(dd, isQ ? mkexpr(res) -+ : unop(Iop_ZeroHI64ofV128, mkexpr(res))); -+ const HChar* names[4] = { "and", "bic", "orr", "orn" }; -+ const HChar* ar = isQ ? "16b" : "8b"; -+ DIP("%s %s.%s, %s.%s, %s.%s\n", names[INSN(23,22)], -+ nameQReg128(dd), ar, nameQReg128(nn), ar, nameQReg128(mm), ar); -+ return True; -+ } -+ -+ /* ---------- CM{EQ,HI,HS,GE,GT,TST,LE,LT} (vector) ---------- */ -+ /* 31 28 23 21 15 9 4 ix -+ 0q1 01110 size 1 m 100011 n d CMEQ Vd.T, Vn.T, Vm.T (1) == -+ 0q0 01110 size 1 m 100011 n d CMTST Vd.T, Vn.T, Vm.T (2) &, != 0 -+ -+ 0q1 01110 size 1 m 001101 n d CMHI Vd.T, Vn.T, Vm.T (3) >u -+ 0q0 01110 size 1 m 001101 n d CMGT Vd.T, Vn.T, Vm.T (4) >s -+ -+ 0q1 01110 size 1 m 001111 n d CMHS Vd.T, Vn.T, Vm.T (5) >=u -+ 0q0 01110 size 1 m 001111 n d CMGE Vd.T, Vn.T, Vm.T (6) >=s -+ -+ 0q1 01110 size 100000 100010 n d CMGE Vd.T, Vn.T, #0 (7) >=s 0 -+ 0q0 01110 size 100000 100010 n d CMGT Vd.T, Vn.T, #0 (8) >s 0 -+ -+ 0q1 01110 size 100000 100110 n d CMLE Vd.T, Vn.T, #0 (9) <=s 0 -+ 0q0 01110 size 100000 100110 n d CMEQ Vd.T, Vn.T, #0 (10) == 0 -+ -+ 0q0 01110 size 100000 101010 n d CMLT Vd.T, Vn.T, #0 (11) y can be expressed directly -+ x < y == y > x -+ x <= y == not (x > y) -+ x >= y == not (y > x) -+ */ -+ switch (ix) { -+ case 1: res = binop(opsEQ[szBlg2], argL, argR); break; -+ case 2: res = unop(Iop_NotV128, binop(opsEQ[szBlg2], -+ binop(Iop_AndV128, argL, argR), -+ mkV128(0x0000))); -+ break; -+ case 3: res = binop(opsGTU[szBlg2], argL, argR); break; -+ case 4: res = binop(opsGTS[szBlg2], argL, argR); break; -+ case 5: res = unop(Iop_NotV128, binop(opsGTU[szBlg2], argR, argL)); -+ break; -+ case 6: res = unop(Iop_NotV128, binop(opsGTS[szBlg2], argR, argL)); -+ break; -+ case 7: res = unop(Iop_NotV128, binop(opsGTS[szBlg2], argR, argL)); -+ break; -+ case 8: res = binop(opsGTS[szBlg2], argL, argR); break; -+ case 9: res = unop(Iop_NotV128, -+ binop(opsGTS[szBlg2], argL, argR)); -+ break; -+ case 10: res = binop(opsEQ[szBlg2], argL, argR); break; -+ case 11: res = binop(opsGTS[szBlg2], argR, argL); break; -+ default: vassert(0); -+ } -+ vassert(res); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, res) : res); -+ const HChar* nms[11] = { "eq", "tst", "hi", "gt", "hs", "ge", -+ "ge", "gt", "le", "eq", "lt" }; -+ if (ix <= 6) { -+ DIP("cm%s %s.%s, %s.%s, %s.%s\n", nms[ix-1], -+ nameQReg128(dd), arrSpec, -+ nameQReg128(nn), arrSpec, nameQReg128(mm), arrSpec); -+ } else { -+ DIP("cm%s %s.%s, %s.%s, #0\n", nms[ix-1], -+ nameQReg128(dd), arrSpec, nameQReg128(nn), arrSpec); -+ } -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------- {EOR,BSL,BIT,BIF} (vector) -------------- */ -+ /* 31 28 23 20 15 9 4 -+ 0q1 01110 00 1 m 000111 n d EOR Vd.T, Vm.T, Vn.T -+ 0q1 01110 01 1 m 000111 n d BSL Vd.T, Vm.T, Vn.T -+ 0q1 01110 10 1 m 000111 n d BIT Vd.T, Vm.T, Vn.T -+ 0q1 01110 11 1 m 000111 n d BIF Vd.T, Vm.T, Vn.T -+ */ -+ if (INSN(31,31) == 0 && INSN(29,24) == BITS6(1,0,1,1,1,0) -+ && INSN(21,21) == 1 && INSN(15,10) == BITS6(0,0,0,1,1,1)) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt op = INSN(23,22); -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp argD = newTemp(Ity_V128); -+ IRTemp argN = newTemp(Ity_V128); -+ IRTemp argM = newTemp(Ity_V128); -+ assign(argD, getQReg128(dd)); -+ assign(argN, getQReg128(nn)); -+ assign(argM, getQReg128(mm)); -+ const IROp opXOR = Iop_XorV128; -+ const IROp opAND = Iop_AndV128; -+ const IROp opNOT = Iop_NotV128; -+ IRExpr* res = NULL; -+ switch (op) { -+ case BITS2(0,0): /* EOR */ -+ res = binop(opXOR, mkexpr(argM), mkexpr(argN)); -+ break; -+ case BITS2(0,1): /* BSL */ -+ res = binop(opXOR, mkexpr(argM), -+ binop(opAND, -+ binop(opXOR, mkexpr(argM), mkexpr(argN)), -+ mkexpr(argD))); -+ break; -+ case BITS2(1,0): /* BIT */ -+ res = binop(opXOR, mkexpr(argD), -+ binop(opAND, -+ binop(opXOR, mkexpr(argD), mkexpr(argN)), -+ mkexpr(argM))); -+ break; -+ case BITS2(1,1): /* BIF */ -+ res = binop(opXOR, mkexpr(argD), -+ binop(opAND, -+ binop(opXOR, mkexpr(argD), mkexpr(argN)), -+ unop(opNOT, mkexpr(argM)))); -+ break; -+ default: -+ vassert(0); -+ } -+ vassert(res); -+ putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res)); -+ const HChar* nms[4] = { "eor", "bsl", "bit", "bif" }; -+ const HChar* arr = isQ ? "16b" : "8b"; -+ vassert(op < 4); -+ DIP("%s %s.%s, %s.%s, %s.%s\n", nms[op], -+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr); -+ return True; -+ } -+ -+ /* ------------ {USHR,SSHR,SHL} (vector, immediate) ------------ */ -+ /* 31 28 22 18 15 9 4 -+ 0q1 011110 immh immb 000001 n d USHR Vd.T, Vn.T, #shift (1) -+ 0q0 011110 immh immb 000001 n d SSHR Vd.T, Vn.T, #shift (2) -+ 0q0 011110 immh immb 010101 n d SHL Vd.T, Vn.T, #shift (3) -+ laneTy, shift = case immh:immb of -+ 0001:xxx -> B, SHR:8-xxx, SHL:xxx -+ 001x:xxx -> H, SHR:16-xxxx SHL:xxxx -+ 01xx:xxx -> S, SHR:32-xxxxx SHL:xxxxx -+ 1xxx:xxx -> D, SHR:64-xxxxxx SHL:xxxxxx -+ other -> invalid -+ As usual the case laneTy==D && q==0 is not allowed. -+ */ -+ if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,1,0) -+ && INSN(10,10) == 1) { -+ UInt ix = 0; -+ /**/ if (INSN(29,29) == 1 && INSN(15,11) == BITS5(0,0,0,0,0)) ix = 1; -+ else if (INSN(29,29) == 0 && INSN(15,11) == BITS5(0,0,0,0,0)) ix = 2; -+ else if (INSN(29,29) == 0 && INSN(15,11) == BITS5(0,1,0,1,0)) ix = 3; -+ if (ix > 0) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt immh = INSN(22,19); -+ UInt immb = INSN(18,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ const IROp opsSHRN[4] -+ = { Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2 }; -+ const IROp opsSARN[4] -+ = { Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2 }; -+ const IROp opsSHLN[4] -+ = { Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2 }; -+ UInt szBlg2 = 0; -+ UInt shift = 0; -+ Bool ok = getLaneInfo_IMMH_IMMB(&shift, &szBlg2, immh, immb); -+ if (ix == 3) { -+ /* The shift encoding has opposite sign for the leftwards -+ case. Adjust shift to compensate. */ -+ shift = (8 << szBlg2) - shift; -+ } -+ if (ok && szBlg2 < 4 && shift > 0 && shift < (8 << szBlg2) -+ && !(szBlg2 == 3/*64bit*/ && !isQ)) { -+ IROp op = Iop_INVALID; -+ const HChar* nm = NULL; -+ switch (ix) { -+ case 1: op = opsSHRN[szBlg2]; nm = "ushr"; break; -+ case 2: op = opsSARN[szBlg2]; nm = "sshr"; break; -+ case 3: op = opsSHLN[szBlg2]; nm = "shl"; break; -+ default: vassert(0); -+ } -+ IRExpr* src = getQReg128(nn); -+ IRExpr* res = binop(op, src, mkU8(shift)); -+ putQReg128(dd, isQ ? res : unop(Iop_ZeroHI64ofV128, res)); -+ HChar laneCh = "bhsd"[szBlg2]; -+ UInt nLanes = (isQ ? 128 : 64) / (8 << szBlg2); -+ DIP("%s %s.%u%c, %s.%u%c, #%u\n", nm, -+ nameQReg128(dd), nLanes, laneCh, -+ nameQReg128(nn), nLanes, laneCh, shift); -+ return True; -+ } -+ /* else fall through */ -+ } -+ } -+ -+ /* -------------------- {U,S}SHLL{,2} -------------------- */ -+ /* 31 28 22 18 15 9 4 -+ 0q0 011110 immh immb 101001 n d SSHLL Vd.Ta, Vn.Tb, #sh -+ 0q1 011110 immh immb 101001 n d USHLL Vd.Ta, Vn.Tb, #sh -+ where Ta,Tb,sh -+ = case immh of 1xxx -> invalid -+ 01xx -> 2d, 2s(q0)/4s(q1), immh:immb - 32 (0..31) -+ 001x -> 4s, 4h(q0)/8h(q1), immh:immb - 16 (0..15) -+ 0001 -> 8h, 8b(q0)/16b(q1), immh:immb - 8 (0..7) -+ 0000 -> AdvSIMD modified immediate (???) -+ */ -+ if (INSN(31,31) == 0 && INSN(28,23) == BITS6(0,1,1,1,1,0) -+ && INSN(15,10) == BITS6(1,0,1,0,0,1)) { -+ Bool isQ = INSN(30,30) == 1; -+ Bool isU = INSN(29,29) == 1; -+ UInt immh = INSN(22,19); -+ UInt immb = INSN(18,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt immhb = (immh << 3) | immb; -+ IRTemp src = newTemp(Ity_V128); -+ IRTemp zero = newTemp(Ity_V128); -+ IRExpr* res = NULL; -+ UInt sh = 0; -+ const HChar* ta = "??"; -+ const HChar* tb = "??"; -+ assign(src, getQReg128(nn)); -+ assign(zero, mkV128(0x0000)); -+ if (immh & 8) { -+ /* invalid; don't assign to res */ -+ } -+ else if (immh & 4) { -+ sh = immhb - 32; -+ vassert(sh < 32); /* so 32-sh is 1..32 */ -+ ta = "2d"; -+ tb = isQ ? "4s" : "2s"; -+ IRExpr* tmp = isQ ? mk_InterleaveHI32x4(src, zero) -+ : mk_InterleaveLO32x4(src, zero); -+ res = binop(isU ? Iop_ShrN64x2 : Iop_SarN64x2, tmp, mkU8(32-sh)); -+ } -+ else if (immh & 2) { -+ sh = immhb - 16; -+ vassert(sh < 16); /* so 16-sh is 1..16 */ -+ ta = "4s"; -+ tb = isQ ? "8h" : "4h"; -+ IRExpr* tmp = isQ ? mk_InterleaveHI16x8(src, zero) -+ : mk_InterleaveLO16x8(src, zero); -+ res = binop(isU ? Iop_ShrN32x4 : Iop_SarN32x4, tmp, mkU8(16-sh)); -+ } -+ else if (immh & 1) { -+ sh = immhb - 8; -+ vassert(sh < 8); /* so 8-sh is 1..8 */ -+ ta = "8h"; -+ tb = isQ ? "16b" : "8b"; -+ IRExpr* tmp = isQ ? mk_InterleaveHI8x16(src, zero) -+ : mk_InterleaveLO8x16(src, zero); -+ res = binop(isU ? Iop_ShrN16x8 : Iop_SarN16x8, tmp, mkU8(8-sh)); -+ } else { -+ vassert(immh == 0); -+ /* invalid; don't assign to res */ -+ } -+ /* */ -+ if (res) { -+ putQReg128(dd, res); -+ DIP("%cshll%s %s.%s, %s.%s, #%d\n", -+ isU ? 'u' : 's', isQ ? "2" : "", -+ nameQReg128(dd), ta, nameQReg128(nn), tb, sh); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------------- XTN{,2} -------------------- */ -+ /* 31 28 23 21 15 9 4 XTN{,2} Vd.Tb, Vn.Ta -+ 0q0 01110 size 100001 001010 n d -+ */ -+ if (INSN(31,31) == 0 && INSN(29,24) == BITS6(0,0,1,1,1,0) -+ && INSN(21,16) == BITS6(1,0,0,0,0,1) -+ && INSN(15,10) == BITS6(0,0,1,0,1,0)) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt size = INSN(23,22); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IROp op = Iop_INVALID; -+ const HChar* tb = NULL; -+ const HChar* ta = NULL; -+ switch ((size << 1) | (isQ ? 1 : 0)) { -+ case 0: tb = "8b"; ta = "8h"; op = Iop_NarrowUn16to8x8; break; -+ case 1: tb = "16b"; ta = "8h"; op = Iop_NarrowUn16to8x8; break; -+ case 2: tb = "4h"; ta = "4s"; op = Iop_NarrowUn32to16x4; break; -+ case 3: tb = "8h"; ta = "4s"; op = Iop_NarrowUn32to16x4; break; -+ case 4: tb = "2s"; ta = "2d"; op = Iop_NarrowUn64to32x2; break; -+ case 5: tb = "4s"; ta = "2d"; op = Iop_NarrowUn64to32x2; break; -+ case 6: break; -+ case 7: break; -+ default: vassert(0); -+ } -+ if (op != Iop_INVALID) { -+ if (!isQ) { -+ putQRegLane(dd, 1, mkU64(0)); -+ } -+ putQRegLane(dd, isQ ? 1 : 0, unop(op, getQReg128(nn))); -+ DIP("xtn%s %s.%s, %s.%s\n", isQ ? "2" : "", -+ nameQReg128(dd), tb, nameQReg128(nn), ta); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ---------------- DUP (element, vector) ---------------- */ -+ /* 31 28 20 15 9 4 -+ 0q0 01110000 imm5 000001 n d DUP Vd.T, Vn.Ts[index] -+ */ -+ if (INSN(31,31) == 0 && INSN(29,21) == BITS9(0,0,1,1,1,0,0,0,0) -+ && INSN(15,10) == BITS6(0,0,0,0,0,1)) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt imm5 = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp w0 = newTemp(Ity_I64); -+ const HChar* arT = "??"; -+ const HChar* arTs = "??"; -+ IRType laneTy = Ity_INVALID; -+ UInt laneNo = 16; /* invalid */ -+ if (imm5 & 1) { -+ arT = isQ ? "16b" : "8b"; -+ arTs = "b"; -+ laneNo = (imm5 >> 1) & 15; -+ laneTy = Ity_I8; -+ assign(w0, unop(Iop_8Uto64, getQRegLane(nn, laneNo, laneTy))); -+ } -+ else if (imm5 & 2) { -+ arT = isQ ? "8h" : "4h"; -+ arTs = "h"; -+ laneNo = (imm5 >> 2) & 7; -+ laneTy = Ity_I16; -+ assign(w0, unop(Iop_16Uto64, getQRegLane(nn, laneNo, laneTy))); -+ } -+ else if (imm5 & 4) { -+ arT = isQ ? "4s" : "2s"; -+ arTs = "s"; -+ laneNo = (imm5 >> 3) & 3; -+ laneTy = Ity_I32; -+ assign(w0, unop(Iop_32Uto64, getQRegLane(nn, laneNo, laneTy))); -+ } -+ else if ((imm5 & 8) && isQ) { -+ arT = "2d"; -+ arTs = "d"; -+ laneNo = (imm5 >> 4) & 1; -+ laneTy = Ity_I64; -+ assign(w0, getQRegLane(nn, laneNo, laneTy)); -+ } -+ else { -+ /* invalid; leave laneTy unchanged. */ -+ } -+ /* */ -+ if (laneTy != Ity_INVALID) { -+ vassert(laneNo < 16); -+ IRTemp w1 = math_DUP_TO_64(w0, laneTy); -+ putQReg128(dd, binop(Iop_64HLtoV128, -+ isQ ? mkexpr(w1) : mkU64(0), mkexpr(w1))); -+ DIP("dup %s.%s, %s.%s[%u]\n", -+ nameQReg128(dd), arT, nameQReg128(nn), arTs, laneNo); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ---------------- DUP (general, vector) ---------------- */ -+ /* 31 28 23 20 15 9 4 -+ 0q0 01110 000 imm5 000011 n d DUP Vd.T, Rn -+ Q=0 writes 64, Q=1 writes 128 -+ imm5: xxxx1 8B(q=0) or 16b(q=1), R=W -+ xxx10 4H(q=0) or 8H(q=1), R=W -+ xx100 2S(q=0) or 4S(q=1), R=W -+ x1000 Invalid(q=0) or 2D(q=1), R=X -+ x0000 Invalid(q=0) or Invalid(q=1) -+ */ -+ if (INSN(31,31) == 0 && INSN(29,21) == BITS9(0,0,1,1,1,0,0,0,0) -+ && INSN(15,10) == BITS6(0,0,0,0,1,1)) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt imm5 = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ IRTemp w0 = newTemp(Ity_I64); -+ const HChar* arT = "??"; -+ IRType laneTy = Ity_INVALID; -+ if (imm5 & 1) { -+ arT = isQ ? "16b" : "8b"; -+ laneTy = Ity_I8; -+ assign(w0, unop(Iop_8Uto64, unop(Iop_64to8, getIReg64orZR(nn)))); -+ } -+ else if (imm5 & 2) { -+ arT = isQ ? "8h" : "4h"; -+ laneTy = Ity_I16; -+ assign(w0, unop(Iop_16Uto64, unop(Iop_64to16, getIReg64orZR(nn)))); -+ } -+ else if (imm5 & 4) { -+ arT = isQ ? "4s" : "2s"; -+ laneTy = Ity_I32; -+ assign(w0, unop(Iop_32Uto64, unop(Iop_64to32, getIReg64orZR(nn)))); -+ } -+ else if ((imm5 & 8) && isQ) { -+ arT = "2d"; -+ laneTy = Ity_I64; -+ assign(w0, getIReg64orZR(nn)); -+ } -+ else { -+ /* invalid; leave laneTy unchanged. */ -+ } -+ /* */ -+ if (laneTy != Ity_INVALID) { -+ IRTemp w1 = math_DUP_TO_64(w0, laneTy); -+ putQReg128(dd, binop(Iop_64HLtoV128, -+ isQ ? mkexpr(w1) : mkU64(0), mkexpr(w1))); -+ DIP("dup %s.%s, %s\n", -+ nameQReg128(dd), arT, nameIRegOrZR(laneTy == Ity_I64, nn)); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* ---------------------- {S,U}MOV ---------------------- */ -+ /* 31 28 20 15 9 4 -+ 0q0 01110 000 imm5 001111 n d UMOV Xd/Wd, Vn.Ts[index] -+ 0q0 01110 000 imm5 001011 n d SMOV Xd/Wd, Vn.Ts[index] -+ dest is Xd when q==1, Wd when q==0 -+ UMOV: -+ Ts,index,ops = case q:imm5 of -+ 0:xxxx1 -> B, xxxx, 8Uto64 -+ 1:xxxx1 -> invalid -+ 0:xxx10 -> H, xxx, 16Uto64 -+ 1:xxx10 -> invalid -+ 0:xx100 -> S, xx, 32Uto64 -+ 1:xx100 -> invalid -+ 1:x1000 -> D, x, copy64 -+ other -> invalid -+ SMOV: -+ Ts,index,ops = case q:imm5 of -+ 0:xxxx1 -> B, xxxx, (32Uto64 . 8Sto32) -+ 1:xxxx1 -> B, xxxx, 8Sto64 -+ 0:xxx10 -> H, xxx, (32Uto64 . 16Sto32) -+ 1:xxx10 -> H, xxx, 16Sto64 -+ 0:xx100 -> invalid -+ 1:xx100 -> S, xx, 32Sto64 -+ 1:x1000 -> invalid -+ other -> invalid -+ */ -+ if (INSN(31,31) == 0 && INSN(29,21) == BITS9(0,0,1,1,1,0,0,0,0) -+ && (INSN(15,10) & BITS6(1,1,1,0,1,1)) == BITS6(0,0,1,0,1,1)) { -+ UInt bitQ = INSN(30,30) == 1; -+ UInt imm5 = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool isU = INSN(12,12) == 1; -+ const HChar* arTs = "??"; -+ UInt laneNo = 16; /* invalid */ -+ // Setting 'res' to non-NULL determines valid/invalid -+ IRExpr* res = NULL; -+ if (!bitQ && (imm5 & 1)) { // 0:xxxx1 -+ laneNo = (imm5 >> 1) & 15; -+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); -+ res = isU ? unop(Iop_8Uto64, lane) -+ : unop(Iop_32Uto64, unop(Iop_8Sto32, lane)); -+ arTs = "b"; -+ } -+ else if (bitQ && (imm5 & 1)) { // 1:xxxx1 -+ laneNo = (imm5 >> 1) & 15; -+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); -+ res = isU ? NULL -+ : unop(Iop_8Sto64, lane); -+ arTs = "b"; -+ } -+ else if (!bitQ && (imm5 & 2)) { // 0:xxx10 -+ laneNo = (imm5 >> 2) & 7; -+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); -+ res = isU ? unop(Iop_16Uto64, lane) -+ : unop(Iop_32Uto64, unop(Iop_16Sto32, lane)); -+ arTs = "h"; -+ } -+ else if (bitQ && (imm5 & 2)) { // 1:xxx10 -+ laneNo = (imm5 >> 2) & 7; -+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); -+ res = isU ? NULL -+ : unop(Iop_16Sto64, lane); -+ arTs = "h"; -+ } -+ else if (!bitQ && (imm5 & 4)) { // 0:xx100 -+ laneNo = (imm5 >> 3) & 3; -+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); -+ res = isU ? unop(Iop_32Uto64, lane) -+ : NULL; -+ arTs = "s"; -+ } -+ else if (bitQ && (imm5 & 4)) { // 1:xxx10 -+ laneNo = (imm5 >> 3) & 3; -+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); -+ res = isU ? NULL -+ : unop(Iop_32Sto64, lane); -+ arTs = "s"; -+ } -+ else if (bitQ && (imm5 & 8)) { // 1:x1000 -+ laneNo = (imm5 >> 4) & 1; -+ IRExpr* lane = getQRegLane(nn, laneNo, Ity_I64); -+ res = isU ? lane -+ : NULL; -+ arTs = "d"; -+ } -+ /* */ -+ if (res) { -+ vassert(laneNo < 16); -+ putIReg64orZR(dd, res); -+ DIP("%cmov %s, %s.%s[%u]\n", isU ? 'u' : 's', -+ nameIRegOrZR(bitQ == 1, dd), -+ nameQReg128(nn), arTs, laneNo); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------------- INS (general) -------------------- */ -+ /* 31 28 20 15 9 4 -+ 010 01110000 imm5 000111 n d INS Vd.Ts[ix], Rn -+ where Ts,ix = case imm5 of xxxx1 -> B, xxxx -+ xxx10 -> H, xxx -+ xx100 -> S, xx -+ x1000 -> D, x -+ */ -+ if (INSN(31,21) == BITS11(0,1,0,0,1,1,1,0,0,0,0) -+ && INSN(15,10) == BITS6(0,0,0,1,1,1)) { -+ UInt imm5 = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ HChar ts = '?'; -+ UInt laneNo = 16; -+ IRExpr* src = NULL; -+ if (imm5 & 1) { -+ src = unop(Iop_64to8, getIReg64orZR(nn)); -+ laneNo = (imm5 >> 1) & 15; -+ ts = 'b'; -+ } -+ else if (imm5 & 2) { -+ src = unop(Iop_64to16, getIReg64orZR(nn)); -+ laneNo = (imm5 >> 2) & 7; -+ ts = 'h'; -+ } -+ else if (imm5 & 4) { -+ src = unop(Iop_64to32, getIReg64orZR(nn)); -+ laneNo = (imm5 >> 3) & 3; -+ ts = 's'; -+ } -+ else if (imm5 & 8) { -+ src = getIReg64orZR(nn); -+ laneNo = (imm5 >> 4) & 1; -+ ts = 'd'; -+ } -+ /* */ -+ if (src) { -+ vassert(laneNo < 16); -+ putQRegLane(dd, laneNo, src); -+ DIP("ins %s.%c[%u], %s\n", -+ nameQReg128(dd), ts, laneNo, nameIReg64orZR(nn)); -+ return True; -+ } -+ /* else invalid; fall through */ -+ } -+ -+ /* -------------------- NEG (vector) -------------------- */ -+ /* 31 28 23 21 16 9 4 -+ 0q1 01110 sz 10000 0101110 n d NEG Vd, Vn -+ sz is laneSz, q:sz == 011 is disallowed, as usual -+ */ -+ if (INSN(31,31) == 0 && INSN(29,24) == BITS6(1,0,1,1,1,0) -+ && INSN(21,10) == BITS12(1,0,0,0,0,0,1,0,1,1,1,0)) { -+ Bool isQ = INSN(30,30) == 1; -+ UInt szBlg2 = INSN(23,22); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ Bool zeroHI = False; -+ const HChar* arrSpec = ""; -+ Bool ok = getLaneInfo_SIMPLE(&zeroHI, &arrSpec, isQ, szBlg2 ); -+ if (ok) { -+ const IROp opSUB[4] -+ = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2 }; -+ IRTemp res = newTemp(Ity_V128); -+ vassert(szBlg2 < 4); -+ assign(res, binop(opSUB[szBlg2], mkV128(0x0000), getQReg128(nn))); -+ putQReg128(dd, zeroHI ? unop(Iop_ZeroHI64ofV128, mkexpr(res)) -+ : mkexpr(res)); -+ DIP("neg %s.%s, %s.%s\n", -+ nameQReg128(dd), arrSpec, nameQReg128(nn), arrSpec); -+ return True; -+ } -+ /* else fall through */ -+ } -+ -+ /* -------------------- TBL, TBX -------------------- */ -+ /* 31 28 20 15 14 12 9 4 -+ 0q0 01110 000 m 0 len 000 n d TBL Vd.Ta, {Vn .. V(n+len)%32}, Vm.Ta -+ 0q0 01110 000 m 0 len 100 n d TBX Vd.Ta, {Vn .. V(n+len)%32}, Vm.Ta -+ where Ta = 16b(q=1) or 8b(q=0) -+ */ -+ if (INSN(31,31) == 0 && INSN(29,21) == BITS9(0,0,1,1,1,0,0,0,0) -+ && INSN(15,15) == 0 && INSN(11,10) == BITS2(0,0)) { -+ Bool isQ = INSN(30,30) == 1; -+ Bool isTBX = INSN(12,12) == 1; -+ UInt mm = INSN(20,16); -+ UInt len = INSN(14,13); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ /* The out-of-range values to use. */ -+ IRTemp oor_values = newTemp(Ity_V128); -+ assign(oor_values, isTBX ? getQReg128(dd) : mkV128(0)); -+ /* src value */ -+ IRTemp src = newTemp(Ity_V128); -+ assign(src, getQReg128(mm)); -+ /* The table values */ -+ IRTemp tab[4]; -+ UInt i; -+ for (i = 0; i <= len; i++) { -+ vassert(i < 4); -+ tab[i] = newTemp(Ity_V128); -+ assign(tab[i], getQReg128((nn + i) % 32)); -+ } -+ IRTemp res = math_TBL_TBX(tab, len, src, oor_values); -+ putQReg128(dd, isQ ? mkexpr(res) -+ : unop(Iop_ZeroHI64ofV128, mkexpr(res)) ); -+ const HChar* Ta = isQ ? "16b" : "8b"; -+ const HChar* nm = isTBX ? "tbx" : "tbl"; -+ DIP("%s %s.%s, {v%d.16b .. v%d.16b}, %s.%s\n", -+ nm, nameQReg128(dd), Ta, nn, (nn + len) % 32, nameQReg128(mm), Ta); -+ return True; -+ } -+ /* FIXME Temporary hacks to get through ld.so FIXME */ -+ -+ /* ------------------ movi vD.4s, #0x0 ------------------ */ -+ /* 0x4F 0x00 0x04 000 vD */ -+ if ((insn & 0xFFFFFFE0) == 0x4F000400) { -+ UInt vD = INSN(4,0); -+ putQReg128(vD, mkV128(0x0000)); -+ DIP("movi v%u.4s, #0x0\n", vD); -+ return True; -+ } -+ -+ /* ---------------- MOV vD.16b, vN.16b ---------------- */ -+ /* 31 23 20 15 9 4 -+ 010 01110 101 m 000111 n d ORR vD.16b, vN.16b, vM.16b -+ This only handles the N == M case. -+ */ -+ if (INSN(31,24) == BITS8(0,1,0,0,1,1,1,0) -+ && INSN(23,21) == BITS3(1,0,1) && INSN(15,10) == BITS6(0,0,0,1,1,1)) { -+ UInt mm = INSN(20,16); -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ if (mm == nn) { -+ putQReg128(dd, getQReg128(nn)); -+ DIP("mov v%u.16b, v%u.16b\n", dd, nn); -+ return True; -+ } -+ /* else it's really an ORR; fall through. */ -+ } -+ -+ /* ---------------- CMEQ_d_d_#0 ---------------- */ -+ /* -+ 010 11110 11 10000 0100 110 n d CMEQ Dd, Dn, #0 -+ */ -+ if ((INSN(31,0) & 0xFFFFFC00) == 0x5EE09800) { -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ putQReg128(dd, unop(Iop_ZeroHI64ofV128, -+ binop(Iop_CmpEQ64x2, getQReg128(nn), -+ mkV128(0x0000)))); -+ DIP("cmeq d%u, d%u, #0\n", dd, nn); -+ return True; -+ } -+ -+ /* ---------------- SHL_d_d_#imm ---------------- */ -+ /* 31 22 21 18 15 9 4 -+ 010 111110 1 ih3 ib 010101 n d SHL Dd, Dn, #(ih3:ib) -+ */ -+ if (INSN(31,22) == BITS10(0,1,0,1,1,1,1,1,0,1) -+ && INSN(15,10) == BITS6(0,1,0,1,0,1)) { -+ UInt nn = INSN(9,5); -+ UInt dd = INSN(4,0); -+ UInt sh = INSN(21,16); -+ vassert(sh < 64); -+ putQReg128(dd, unop(Iop_ZeroHI64ofV128, -+ binop(Iop_ShlN64x2, getQReg128(nn), mkU8(sh)))); -+ DIP("shl d%u, d%u, #%u\n", dd, nn, sh); -+ return True; -+ } -+ -+ vex_printf("ARM64 front end: simd_and_fp\n"); -+ return False; -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Disassemble a single ARM64 instruction ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Disassemble a single ARM64 instruction into IR. The instruction -+ has is located at |guest_instr| and has guest IP of -+ |guest_PC_curr_instr|, which will have been set before the call -+ here. Returns True iff the instruction was decoded, in which case -+ *dres will be set accordingly, or False, in which case *dres should -+ be ignored by the caller. */ -+ -+static -+Bool disInstr_ARM64_WRK ( -+ /*MB_OUT*/DisResult* dres, -+ Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), -+ Bool resteerCisOk, -+ void* callback_opaque, -+ UChar* guest_instr, -+ VexArchInfo* archinfo, -+ VexAbiInfo* abiinfo -+ ) -+{ -+ // A macro to fish bits out of 'insn'. -+# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin)) -+ -+//ZZ DisResult dres; -+//ZZ UInt insn; -+//ZZ //Bool allow_VFP = False; -+//ZZ //UInt hwcaps = archinfo->hwcaps; -+//ZZ IRTemp condT; /* :: Ity_I32 */ -+//ZZ UInt summary; -+//ZZ HChar dis_buf[128]; // big enough to hold LDMIA etc text -+//ZZ -+//ZZ /* What insn variants are we supporting today? */ -+//ZZ //allow_VFP = (0 != (hwcaps & VEX_HWCAPS_ARM_VFP)); -+//ZZ // etc etc -+ -+ /* Set result defaults. */ -+ dres->whatNext = Dis_Continue; -+ dres->len = 4; -+ dres->continueAt = 0; -+ dres->jk_StopHere = Ijk_INVALID; -+ -+ /* At least this is simple on ARM64: insns are all 4 bytes long, and -+ 4-aligned. So just fish the whole thing out of memory right now -+ and have done. */ -+ UInt insn = getUIntLittleEndianly( guest_instr ); -+ -+ if (0) vex_printf("insn: 0x%x\n", insn); -+ -+ DIP("\t(arm64) 0x%llx: ", (ULong)guest_PC_curr_instr); -+ -+ vassert(0 == (guest_PC_curr_instr & 3ULL)); -+ -+ /* ----------------------------------------------------------- */ -+ -+ /* Spot "Special" instructions (see comment at top of file). */ -+ { -+ UChar* code = (UChar*)guest_instr; -+ /* Spot the 16-byte preamble: -+ 93CC0D8C ror x12, x12, #3 -+ 93CC358C ror x12, x12, #13 -+ 93CCCD8C ror x12, x12, #51 -+ 93CCF58C ror x12, x12, #61 -+ */ -+ UInt word1 = 0x93CC0D8C; -+ UInt word2 = 0x93CC358C; -+ UInt word3 = 0x93CCCD8C; -+ UInt word4 = 0x93CCF58C; -+ if (getUIntLittleEndianly(code+ 0) == word1 && -+ getUIntLittleEndianly(code+ 4) == word2 && -+ getUIntLittleEndianly(code+ 8) == word3 && -+ getUIntLittleEndianly(code+12) == word4) { -+ /* Got a "Special" instruction preamble. Which one is it? */ -+ if (getUIntLittleEndianly(code+16) == 0xAA0A014A -+ /* orr x10,x10,x10 */) { -+ /* X3 = client_request ( X4 ) */ -+ DIP("x3 = client_request ( x4 )\n"); -+ putPC(mkU64( guest_PC_curr_instr + 20 )); -+ dres->jk_StopHere = Ijk_ClientReq; -+ dres->whatNext = Dis_StopHere; -+ return True; -+ } -+ else -+ if (getUIntLittleEndianly(code+16) == 0xAA0B016B -+ /* orr x11,x11,x11 */) { -+ /* X3 = guest_NRADDR */ -+ DIP("x3 = guest_NRADDR\n"); -+ dres->len = 20; -+ putIReg64orZR(3, IRExpr_Get( OFFB_NRADDR, Ity_I64 )); -+ return True; -+ } -+ else -+ if (getUIntLittleEndianly(code+16) == 0xAA0C018C -+ /* orr x12,x12,x12 */) { -+ /* branch-and-link-to-noredir X8 */ -+ DIP("branch-and-link-to-noredir x8\n"); -+ putIReg64orZR(30, mkU64(guest_PC_curr_instr + 20)); -+ putPC(getIReg64orZR(8)); -+ dres->jk_StopHere = Ijk_NoRedir; -+ dres->whatNext = Dis_StopHere; -+ return True; -+ } -+ else -+ if (getUIntLittleEndianly(code+16) == 0xAA090129 -+ /* orr x9,x9,x9 */) { -+ /* IR injection */ -+ DIP("IR injection\n"); -+ vex_inject_ir(irsb, Iend_LE); -+ // Invalidate the current insn. The reason is that the IRop we're -+ // injecting here can change. In which case the translation has to -+ // be redone. For ease of handling, we simply invalidate all the -+ // time. -+ stmt(IRStmt_Put(OFFB_CMSTART, mkU64(guest_PC_curr_instr))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkU64(20))); -+ putPC(mkU64( guest_PC_curr_instr + 20 )); -+ dres->whatNext = Dis_StopHere; -+ dres->jk_StopHere = Ijk_InvalICache; -+ return True; -+ } -+ /* We don't know what it is. */ -+ return False; -+ /*NOTREACHED*/ -+ } -+ } -+ -+ /* ----------------------------------------------------------- */ -+ -+ /* Main ARM64 instruction decoder starts here. */ -+ -+ Bool ok = False; -+ -+ /* insn[28:25] determines the top-level grouping, so let's start -+ off with that. -+ -+ For all of these dis_ARM64_ functions, we pass *dres with the -+ normal default results "insn OK, 4 bytes long, keep decoding" so -+ they don't need to change it. However, decodes of control-flow -+ insns may cause *dres to change. -+ */ -+ switch (INSN(28,25)) { -+ case BITS4(1,0,0,0): case BITS4(1,0,0,1): -+ // Data processing - immediate -+ ok = dis_ARM64_data_processing_immediate(dres, insn); -+ break; -+ case BITS4(1,0,1,0): case BITS4(1,0,1,1): -+ // Branch, exception generation and system instructions -+ ok = dis_ARM64_branch_etc(dres, insn, archinfo); -+ break; -+ case BITS4(0,1,0,0): case BITS4(0,1,1,0): -+ case BITS4(1,1,0,0): case BITS4(1,1,1,0): -+ // Loads and stores -+ ok = dis_ARM64_load_store(dres, insn); -+ break; -+ case BITS4(0,1,0,1): case BITS4(1,1,0,1): -+ // Data processing - register -+ ok = dis_ARM64_data_processing_register(dres, insn); -+ break; -+ case BITS4(0,1,1,1): case BITS4(1,1,1,1): -+ // Data processing - SIMD and floating point -+ ok = dis_ARM64_simd_and_fp(dres, insn); -+ break; -+ case BITS4(0,0,0,0): case BITS4(0,0,0,1): -+ case BITS4(0,0,1,0): case BITS4(0,0,1,1): -+ // UNALLOCATED -+ break; -+ default: -+ vassert(0); /* Can't happen */ -+ } -+ -+ /* If the next-level down decoders failed, make sure |dres| didn't -+ get changed. */ -+ if (!ok) { -+ vassert(dres->whatNext == Dis_Continue); -+ vassert(dres->len == 4); -+ vassert(dres->continueAt == 0); -+ vassert(dres->jk_StopHere == Ijk_INVALID); -+ } -+ -+ return ok; -+ -+# undef INSN -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Top-level fn ---*/ -+/*------------------------------------------------------------*/ -+ -+/* Disassemble a single instruction into IR. The instruction -+ is located in host memory at &guest_code[delta]. */ -+ -+DisResult disInstr_ARM64 ( IRSB* irsb_IN, -+ Bool (*resteerOkFn) ( void*, Addr64 ), -+ Bool resteerCisOk, -+ void* callback_opaque, -+ UChar* guest_code_IN, -+ Long delta_IN, -+ Addr64 guest_IP, -+ VexArch guest_arch, -+ VexArchInfo* archinfo, -+ VexAbiInfo* abiinfo, -+ Bool host_bigendian_IN, -+ Bool sigill_diag_IN ) -+{ -+ DisResult dres; -+ vex_bzero(&dres, sizeof(dres)); -+ -+ /* Set globals (see top of this file) */ -+ vassert(guest_arch == VexArchARM64); -+ -+ irsb = irsb_IN; -+ host_is_bigendian = host_bigendian_IN; -+ guest_PC_curr_instr = (Addr64)guest_IP; -+ -+ /* Sanity checks */ -+ /* (x::UInt - 2) <= 15 === x >= 2 && x <= 17 (I hope) */ -+ vassert((archinfo->arm64_dMinLine_lg2_szB - 2) <= 15); -+ vassert((archinfo->arm64_iMinLine_lg2_szB - 2) <= 15); -+ -+ /* Try to decode */ -+ Bool ok = disInstr_ARM64_WRK( &dres, -+ resteerOkFn, resteerCisOk, callback_opaque, -+ (UChar*)&guest_code_IN[delta_IN], -+ archinfo, abiinfo ); -+ if (ok) { -+ /* All decode successes end up here. */ -+ vassert(dres.len == 4 || dres.len == 20); -+ switch (dres.whatNext) { -+ case Dis_Continue: -+ putPC( mkU64(dres.len + guest_PC_curr_instr) ); -+ break; -+ case Dis_ResteerU: -+ case Dis_ResteerC: -+ putPC(mkU64(dres.continueAt)); -+ break; -+ case Dis_StopHere: -+ break; -+ default: -+ vassert(0); -+ } -+ DIP("\n"); -+ } else { -+ /* All decode failures end up here. */ -+ if (sigill_diag_IN) { -+ Int i, j; -+ UChar buf[64]; -+ UInt insn -+ = getUIntLittleEndianly( (UChar*)&guest_code_IN[delta_IN] ); -+ vex_bzero(buf, sizeof(buf)); -+ for (i = j = 0; i < 32; i++) { -+ if (i > 0) { -+ if ((i & 7) == 0) buf[j++] = ' '; -+ else if ((i & 3) == 0) buf[j++] = '\''; -+ } -+ buf[j++] = (insn & (1<<(31-i))) ? '1' : '0'; -+ } -+ vex_printf("disInstr(arm64): unhandled instruction 0x%08x\n", insn); -+ vex_printf("disInstr(arm64): %s\n", buf); -+ } -+ -+ /* Tell the dispatcher that this insn cannot be decoded, and so -+ has not been executed, and (is currently) the next to be -+ executed. PC should be up-to-date since it is made so at the -+ start of each insn, but nevertheless be paranoid and update -+ it again right now. */ -+ putPC( mkU64(guest_PC_curr_instr) ); -+ dres.whatNext = Dis_StopHere; -+ dres.len = 0; -+ dres.continueAt = 0; -+ dres.jk_StopHere = Ijk_NoDecode; -+ } -+ return dres; -+} -+ -+//////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////// -+ -+/* Spare code for doing reference implementations of various 128-bit -+ SIMD interleaves/deinterleaves/concatenation ops. For 64-bit -+ equivalents see the end of guest_arm_toIR.c. */ -+ -+//////////////////////////////////////////////////////////////// -+// 64x2 operations -+// -+static IRExpr* mk_CatEvenLanes64x2 ( IRTemp a10, IRTemp b10 ) -+{ -+ // returns a0 b0 -+ return binop(Iop_64HLtoV128, unop(Iop_V128to64, mkexpr(a10)), -+ unop(Iop_V128to64, mkexpr(b10))); -+} -+ -+static IRExpr* mk_CatOddLanes64x2 ( IRTemp a10, IRTemp b10 ) -+{ -+ // returns a1 b1 -+ return binop(Iop_64HLtoV128, unop(Iop_V128HIto64, mkexpr(a10)), -+ unop(Iop_V128HIto64, mkexpr(b10))); -+} -+ -+ -+//////////////////////////////////////////////////////////////// -+// 32x4 operations -+// -+ -+// Split a 128 bit value into 4 32 bit ones, in 64-bit IRTemps with -+// the top halves guaranteed to be zero. -+static void breakV128to32s ( IRTemp* out3, IRTemp* out2, IRTemp* out1, -+ IRTemp* out0, IRTemp v128 ) -+{ -+ if (out3) *out3 = newTemp(Ity_I64); -+ if (out2) *out2 = newTemp(Ity_I64); -+ if (out1) *out1 = newTemp(Ity_I64); -+ if (out0) *out0 = newTemp(Ity_I64); -+ IRTemp hi64 = newTemp(Ity_I64); -+ IRTemp lo64 = newTemp(Ity_I64); -+ assign(hi64, unop(Iop_V128HIto64, mkexpr(v128)) ); -+ assign(lo64, unop(Iop_V128to64, mkexpr(v128)) ); -+ if (out3) assign(*out3, binop(Iop_Shr64, mkexpr(hi64), mkU8(32))); -+ if (out2) assign(*out2, binop(Iop_And64, mkexpr(hi64), mkU64(0xFFFFFFFF))); -+ if (out1) assign(*out1, binop(Iop_Shr64, mkexpr(lo64), mkU8(32))); -+ if (out0) assign(*out0, binop(Iop_And64, mkexpr(lo64), mkU64(0xFFFFFFFF))); -+} -+ -+// Make a V128 bit value from 4 32 bit ones, each of which is in a 64 bit -+// IRTemp. -+static IRTemp mkV128from32s ( IRTemp in3, IRTemp in2, IRTemp in1, IRTemp in0 ) -+{ -+ IRTemp hi64 = newTemp(Ity_I64); -+ IRTemp lo64 = newTemp(Ity_I64); -+ assign(hi64, -+ binop(Iop_Or64, -+ binop(Iop_Shl64, mkexpr(in3), mkU8(32)), -+ binop(Iop_And64, mkexpr(in2), mkU64(0xFFFFFFFF)))); -+ assign(lo64, -+ binop(Iop_Or64, -+ binop(Iop_Shl64, mkexpr(in1), mkU8(32)), -+ binop(Iop_And64, mkexpr(in0), mkU64(0xFFFFFFFF)))); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, binop(Iop_64HLtoV128, mkexpr(hi64), mkexpr(lo64))); -+ return res; -+} -+ -+static IRExpr* mk_CatEvenLanes32x4 ( IRTemp a3210, IRTemp b3210 ) -+{ -+ // returns a2 a0 b2 b0 -+ IRTemp a2, a0, b2, b0; -+ breakV128to32s(NULL, &a2, NULL, &a0, a3210); -+ breakV128to32s(NULL, &b2, NULL, &b0, b3210); -+ return mkexpr(mkV128from32s(a2, a0, b2, b0)); -+} -+ -+static IRExpr* mk_CatOddLanes32x4 ( IRTemp a3210, IRTemp b3210 ) -+{ -+ // returns a3 a1 b3 b1 -+ IRTemp a3, a1, b3, b1; -+ breakV128to32s(&a3, NULL, &a1, NULL, a3210); -+ breakV128to32s(&b3, NULL, &b1, NULL, b3210); -+ return mkexpr(mkV128from32s(a3, a1, b3, b1)); -+} -+ -+static IRExpr* mk_InterleaveLO32x4 ( IRTemp a3210, IRTemp b3210 ) -+{ -+ // returns a1 b1 a0 b0 -+ IRTemp a1, a0, b1, b0; -+ breakV128to32s(NULL, NULL, &a1, &a0, a3210); -+ breakV128to32s(NULL, NULL, &b1, &b0, b3210); -+ return mkexpr(mkV128from32s(a1, b1, a0, b0)); -+} -+ -+static IRExpr* mk_InterleaveHI32x4 ( IRTemp a3210, IRTemp b3210 ) -+{ -+ // returns a3 b3 a2 b2 -+ IRTemp a3, a2, b3, b2; -+ breakV128to32s(&a3, &a2, NULL, NULL, a3210); -+ breakV128to32s(&b3, &b2, NULL, NULL, b3210); -+ return mkexpr(mkV128from32s(a3, b3, a2, b2)); -+} -+ -+//////////////////////////////////////////////////////////////// -+// 16x8 operations -+// -+ -+static void breakV128to16s ( IRTemp* out7, IRTemp* out6, IRTemp* out5, -+ IRTemp* out4, IRTemp* out3, IRTemp* out2, -+ IRTemp* out1,IRTemp* out0, IRTemp v128 ) -+{ -+ if (out7) *out7 = newTemp(Ity_I64); -+ if (out6) *out6 = newTemp(Ity_I64); -+ if (out5) *out5 = newTemp(Ity_I64); -+ if (out4) *out4 = newTemp(Ity_I64); -+ if (out3) *out3 = newTemp(Ity_I64); -+ if (out2) *out2 = newTemp(Ity_I64); -+ if (out1) *out1 = newTemp(Ity_I64); -+ if (out0) *out0 = newTemp(Ity_I64); -+ IRTemp hi64 = newTemp(Ity_I64); -+ IRTemp lo64 = newTemp(Ity_I64); -+ assign(hi64, unop(Iop_V128HIto64, mkexpr(v128)) ); -+ assign(lo64, unop(Iop_V128to64, mkexpr(v128)) ); -+ if (out7) -+ assign(*out7, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(48)), -+ mkU64(0xFFFF))); -+ if (out6) -+ assign(*out6, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(32)), -+ mkU64(0xFFFF))); -+ if (out5) -+ assign(*out5, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(16)), -+ mkU64(0xFFFF))); -+ if (out4) -+ assign(*out4, binop(Iop_And64, mkexpr(hi64), mkU64(0xFFFF))); -+ if (out3) -+ assign(*out3, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(48)), -+ mkU64(0xFFFF))); -+ if (out2) -+ assign(*out2, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(32)), -+ mkU64(0xFFFF))); -+ if (out1) -+ assign(*out1, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(16)), -+ mkU64(0xFFFF))); -+ if (out0) -+ assign(*out0, binop(Iop_And64, mkexpr(lo64), mkU64(0xFFFF))); -+} -+ -+static IRTemp mkV128from16s ( IRTemp in7, IRTemp in6, IRTemp in5, IRTemp in4, -+ IRTemp in3, IRTemp in2, IRTemp in1, IRTemp in0 ) -+{ -+ IRTemp hi64 = newTemp(Ity_I64); -+ IRTemp lo64 = newTemp(Ity_I64); -+ assign(hi64, -+ binop(Iop_Or64, -+ binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in7), mkU64(0xFFFF)), -+ mkU8(48)), -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in6), mkU64(0xFFFF)), -+ mkU8(32))), -+ binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in5), mkU64(0xFFFF)), -+ mkU8(16)), -+ binop(Iop_And64, -+ mkexpr(in4), mkU64(0xFFFF))))); -+ assign(lo64, -+ binop(Iop_Or64, -+ binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in3), mkU64(0xFFFF)), -+ mkU8(48)), -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in2), mkU64(0xFFFF)), -+ mkU8(32))), -+ binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in1), mkU64(0xFFFF)), -+ mkU8(16)), -+ binop(Iop_And64, -+ mkexpr(in0), mkU64(0xFFFF))))); -+ IRTemp res = newTemp(Ity_V128); -+ assign(res, binop(Iop_64HLtoV128, mkexpr(hi64), mkexpr(lo64))); -+ return res; -+} -+ -+static IRExpr* mk_CatEvenLanes16x8 ( IRTemp a76543210, IRTemp b76543210 ) -+{ -+ // returns a6 a4 a2 a0 b6 b4 b2 b0 -+ IRTemp a6, a4, a2, a0, b6, b4, b2, b0; -+ breakV128to16s(NULL, &a6, NULL, &a4, NULL, &a2, NULL, &a0, a76543210); -+ breakV128to16s(NULL, &b6, NULL, &b4, NULL, &b2, NULL, &b0, b76543210); -+ return mkexpr(mkV128from16s(a6, a4, a2, a0, b6, b4, b2, b0)); -+} -+ -+static IRExpr* mk_CatOddLanes16x8 ( IRTemp a76543210, IRTemp b76543210 ) -+{ -+ // returns a7 a5 a3 a1 b7 b5 b3 b1 -+ IRTemp a7, a5, a3, a1, b7, b5, b3, b1; -+ breakV128to16s(&a7, NULL, &a5, NULL, &a3, NULL, &a1, NULL, a76543210); -+ breakV128to16s(&b7, NULL, &b5, NULL, &b3, NULL, &b1, NULL, b76543210); -+ return mkexpr(mkV128from16s(a7, a5, a3, a1, b7, b5, b3, b1)); -+} -+ -+static IRExpr* mk_InterleaveLO16x8 ( IRTemp a76543210, IRTemp b76543210 ) -+{ -+ // returns a3 b3 a2 b2 a1 b1 a0 b0 -+ IRTemp a3, b3, a2, b2, a1, a0, b1, b0; -+ breakV128to16s(NULL, NULL, NULL, NULL, &a3, &a2, &a1, &a0, a76543210); -+ breakV128to16s(NULL, NULL, NULL, NULL, &b3, &b2, &b1, &b0, b76543210); -+ return mkexpr(mkV128from16s(a3, b3, a2, b2, a1, b1, a0, b0)); -+} -+ -+static IRExpr* mk_InterleaveHI16x8 ( IRTemp a76543210, IRTemp b76543210 ) -+{ -+ // returns a7 b7 a6 b6 a5 b5 a4 b4 -+ IRTemp a7, b7, a6, b6, a5, b5, a4, b4; -+ breakV128to16s(&a7, &a6, &a5, &a4, NULL, NULL, NULL, NULL, a76543210); -+ breakV128to16s(&b7, &b6, &b5, &b4, NULL, NULL, NULL, NULL, b76543210); -+ return mkexpr(mkV128from16s(a7, b7, a6, b6, a5, b5, a4, b4)); -+} -+ -+//////////////////////////////////////////////////////////////// -+// 8x16 operations -+// -+ -+static void breakV128to8s ( IRTemp* outF, IRTemp* outE, IRTemp* outD, -+ IRTemp* outC, IRTemp* outB, IRTemp* outA, -+ IRTemp* out9, IRTemp* out8, -+ IRTemp* out7, IRTemp* out6, IRTemp* out5, -+ IRTemp* out4, IRTemp* out3, IRTemp* out2, -+ IRTemp* out1,IRTemp* out0, IRTemp v128 ) -+{ -+ if (outF) *outF = newTemp(Ity_I64); -+ if (outE) *outE = newTemp(Ity_I64); -+ if (outD) *outD = newTemp(Ity_I64); -+ if (outC) *outC = newTemp(Ity_I64); -+ if (outB) *outB = newTemp(Ity_I64); -+ if (outA) *outA = newTemp(Ity_I64); -+ if (out9) *out9 = newTemp(Ity_I64); -+ if (out8) *out8 = newTemp(Ity_I64); -+ if (out7) *out7 = newTemp(Ity_I64); -+ if (out6) *out6 = newTemp(Ity_I64); -+ if (out5) *out5 = newTemp(Ity_I64); -+ if (out4) *out4 = newTemp(Ity_I64); -+ if (out3) *out3 = newTemp(Ity_I64); -+ if (out2) *out2 = newTemp(Ity_I64); -+ if (out1) *out1 = newTemp(Ity_I64); -+ if (out0) *out0 = newTemp(Ity_I64); -+ IRTemp hi64 = newTemp(Ity_I64); -+ IRTemp lo64 = newTemp(Ity_I64); -+ assign(hi64, unop(Iop_V128HIto64, mkexpr(v128)) ); -+ assign(lo64, unop(Iop_V128to64, mkexpr(v128)) ); -+ if (outF) -+ assign(*outF, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(56)), -+ mkU64(0xFF))); -+ if (outE) -+ assign(*outE, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(48)), -+ mkU64(0xFF))); -+ if (outD) -+ assign(*outD, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(40)), -+ mkU64(0xFF))); -+ if (outC) -+ assign(*outC, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(32)), -+ mkU64(0xFF))); -+ if (outB) -+ assign(*outB, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(24)), -+ mkU64(0xFF))); -+ if (outA) -+ assign(*outA, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(16)), -+ mkU64(0xFF))); -+ if (out9) -+ assign(*out9, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(8)), -+ mkU64(0xFF))); -+ if (out8) -+ assign(*out8, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(hi64), mkU8(0)), -+ mkU64(0xFF))); -+ if (out7) -+ assign(*out7, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(56)), -+ mkU64(0xFF))); -+ if (out6) -+ assign(*out6, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(48)), -+ mkU64(0xFF))); -+ if (out5) -+ assign(*out5, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(40)), -+ mkU64(0xFF))); -+ if (out4) -+ assign(*out4, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(32)), -+ mkU64(0xFF))); -+ if (out3) -+ assign(*out3, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(24)), -+ mkU64(0xFF))); -+ if (out2) -+ assign(*out2, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(16)), -+ mkU64(0xFF))); -+ if (out1) -+ assign(*out1, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(8)), -+ mkU64(0xFF))); -+ if (out0) -+ assign(*out0, binop(Iop_And64, -+ binop(Iop_Shr64, mkexpr(lo64), mkU8(0)), -+ mkU64(0xFF))); -+} -+ -+static IRTemp mkV128from8s ( IRTemp inF, IRTemp inE, IRTemp inD, IRTemp inC, -+ IRTemp inB, IRTemp inA, IRTemp in9, IRTemp in8, -+ IRTemp in7, IRTemp in6, IRTemp in5, IRTemp in4, -+ IRTemp in3, IRTemp in2, IRTemp in1, IRTemp in0 ) -+{ -+ IRTemp vFE = newTemp(Ity_I64); -+ IRTemp vDC = newTemp(Ity_I64); -+ IRTemp vBA = newTemp(Ity_I64); -+ IRTemp v98 = newTemp(Ity_I64); -+ IRTemp v76 = newTemp(Ity_I64); -+ IRTemp v54 = newTemp(Ity_I64); -+ IRTemp v32 = newTemp(Ity_I64); -+ IRTemp v10 = newTemp(Ity_I64); -+ assign(vFE, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(inF), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(inE), mkU64(0xFF)))); -+ assign(vDC, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(inD), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(inC), mkU64(0xFF)))); -+ assign(vBA, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(inB), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(inA), mkU64(0xFF)))); -+ assign(v98, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in9), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(in8), mkU64(0xFF)))); -+ assign(v76, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in7), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(in6), mkU64(0xFF)))); -+ assign(v54, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in5), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(in4), mkU64(0xFF)))); -+ assign(v32, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in3), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(in2), mkU64(0xFF)))); -+ assign(v10, binop(Iop_Or64, -+ binop(Iop_Shl64, -+ binop(Iop_And64, mkexpr(in1), mkU64(0xFF)), mkU8(8)), -+ binop(Iop_And64, mkexpr(in0), mkU64(0xFF)))); -+ return mkV128from16s(vFE, vDC, vBA, v98, v76, v54, v32, v10); -+} -+ -+static IRExpr* mk_CatEvenLanes8x16 ( IRTemp aFEDCBA9876543210, -+ IRTemp bFEDCBA9876543210 ) -+{ -+ // returns aE aC aA a8 a6 a4 a2 a0 bE bC bA b8 b6 b4 b2 b0 -+ IRTemp aE, aC, aA, a8, a6, a4, a2, a0, bE, bC, bA, b8, b6, b4, b2, b0; -+ breakV128to8s(NULL, &aE, NULL, &aC, NULL, &aA, NULL, &a8, -+ NULL, &a6, NULL, &a4, NULL, &a2, NULL, &a0, -+ aFEDCBA9876543210); -+ breakV128to8s(NULL, &bE, NULL, &bC, NULL, &bA, NULL, &b8, -+ NULL, &b6, NULL, &b4, NULL, &b2, NULL, &b0, -+ bFEDCBA9876543210); -+ return mkexpr(mkV128from8s(aE, aC, aA, a8, a6, a4, a2, a0, -+ bE, bC, bA, b8, b6, b4, b2, b0)); -+} -+ -+static IRExpr* mk_CatOddLanes8x16 ( IRTemp aFEDCBA9876543210, -+ IRTemp bFEDCBA9876543210 ) -+{ -+ // returns aF aD aB a9 a7 a5 a3 a1 bF bD bB b9 b7 b5 b3 b1 -+ IRTemp aF, aD, aB, a9, a7, a5, a3, a1, bF, bD, bB, b9, b7, b5, b3, b1; -+ breakV128to8s(&aF, NULL, &aD, NULL, &aB, NULL, &a9, NULL, -+ &a7, NULL, &a5, NULL, &a3, NULL, &a1, NULL, -+ aFEDCBA9876543210); -+ -+ breakV128to8s(&bF, NULL, &bD, NULL, &bB, NULL, &b9, NULL, -+ &b7, NULL, &b5, NULL, &b3, NULL, &b1, NULL, -+ aFEDCBA9876543210); -+ -+ return mkexpr(mkV128from8s(aF, aD, aB, a9, a7, a5, a3, a1, -+ bF, bD, bB, b9, b7, b5, b3, b1)); -+} -+ -+static IRExpr* mk_InterleaveLO8x16 ( IRTemp aFEDCBA9876543210, -+ IRTemp bFEDCBA9876543210 ) -+{ -+ // returns a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 -+ IRTemp a7, b7, a6, b6, a5, b5, a4, b4, a3, b3, a2, b2, a1, b1, a0, b0; -+ breakV128to8s(NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, -+ &a7, &a6, &a5, &a4, &a3, &a2, &a1, &a0, -+ aFEDCBA9876543210); -+ breakV128to8s(NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, -+ &b7, &b6, &b5, &b4, &b3, &b2, &b1, &b0, -+ bFEDCBA9876543210); -+ return mkexpr(mkV128from8s(a7, b7, a6, b6, a5, b5, a4, b4, -+ a3, b3, a2, b2, a1, b1, a0, b0)); -+} -+ -+static IRExpr* mk_InterleaveHI8x16 ( IRTemp aFEDCBA9876543210, -+ IRTemp bFEDCBA9876543210 ) -+{ -+ // returns aF bF aE bE aD bD aC bC aB bB aA bA a9 b9 a8 b8 -+ IRTemp aF, bF, aE, bE, aD, bD, aC, bC, aB, bB, aA, bA, a9, b9, a8, b8; -+ breakV128to8s(&aF, &aE, &aD, &aC, &aB, &aA, &a9, &a8, -+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, -+ aFEDCBA9876543210); -+ breakV128to8s(&bF, &bE, &bD, &bC, &bB, &bA, &b9, &b8, -+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, -+ bFEDCBA9876543210); -+ return mkexpr(mkV128from8s(aF, bF, aE, bE, aD, bD, aC, bC, -+ aB, bB, aA, bA, a9, b9, a8, b8)); -+} -+ -+/*--------------------------------------------------------------------*/ -+/*--- end guest_arm64_toIR.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: priv/guest_arm_helpers.c -=================================================================== ---- priv/guest_arm_helpers.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_arm_helpers.c (.../trunk) (revision 2863) -@@ -981,8 +981,8 @@ - vex_state->guest_GEFLAG3 = 0; - - vex_state->guest_EMNOTE = EmNote_NONE; -- vex_state->guest_TISTART = 0; -- vex_state->guest_TILEN = 0; -+ vex_state->guest_CMSTART = 0; -+ vex_state->guest_CMLEN = 0; - vex_state->guest_NRADDR = 0; - vex_state->guest_IP_AT_SYSCALL = 0; - -@@ -1030,10 +1030,6 @@ - vex_state->guest_ITSTATE = 0; - - vex_state->padding1 = 0; -- vex_state->padding2 = 0; -- vex_state->padding3 = 0; -- vex_state->padding4 = 0; -- vex_state->padding5 = 0; - } - - -@@ -1130,8 +1126,8 @@ - /* 1 */ ALWAYSDEFD(guest_CC_OP), - /* 2 */ ALWAYSDEFD(guest_CC_NDEP), - /* 3 */ ALWAYSDEFD(guest_EMNOTE), -- /* 4 */ ALWAYSDEFD(guest_TISTART), -- /* 5 */ ALWAYSDEFD(guest_TILEN), -+ /* 4 */ ALWAYSDEFD(guest_CMSTART), -+ /* 5 */ ALWAYSDEFD(guest_CMLEN), - /* 6 */ ALWAYSDEFD(guest_NRADDR), - /* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL), - /* 8 */ ALWAYSDEFD(guest_TPIDRURO), -Index: priv/guest_arm_toIR.c -=================================================================== ---- priv/guest_arm_toIR.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_arm_toIR.c (.../trunk) (revision 2863) -@@ -485,8 +485,8 @@ - #define OFFB_GEFLAG2 offsetof(VexGuestARMState,guest_GEFLAG2) - #define OFFB_GEFLAG3 offsetof(VexGuestARMState,guest_GEFLAG3) - --#define OFFB_TISTART offsetof(VexGuestARMState,guest_TISTART) --#define OFFB_TILEN offsetof(VexGuestARMState,guest_TILEN) -+#define OFFB_CMSTART offsetof(VexGuestARMState,guest_CMSTART) -+#define OFFB_CMLEN offsetof(VexGuestARMState,guest_CMLEN) - - - /* ---------------- Integer registers ---------------- */ -@@ -2875,6 +2875,31 @@ - return True; - } - -+/* Generate specific vector FP binary ops, possibly with a fake -+ rounding mode as required by the primop. */ -+static -+IRExpr* binop_w_fake_RM ( IROp op, IRExpr* argL, IRExpr* argR ) -+{ -+ switch (op) { -+ case Iop_Add32Fx4: -+ case Iop_Sub32Fx4: -+ case Iop_Mul32Fx4: -+ return triop(op, get_FAKE_roundingmode(), argL, argR ); -+ case Iop_Add32x4: case Iop_Add16x8: -+ case Iop_Sub32x4: case Iop_Sub16x8: -+ case Iop_Mul32x4: case Iop_Mul16x8: -+ case Iop_Mul32x2: case Iop_Mul16x4: -+ case Iop_Add32Fx2: -+ case Iop_Sub32Fx2: -+ case Iop_Mul32Fx2: -+ case Iop_PwAdd32Fx2: -+ return binop(op, argL, argR); -+ default: -+ ppIROp(op); -+ vassert(0); -+ } -+} -+ - /* VTBL, VTBX */ - static - Bool dis_neon_vtb ( UInt theInstr, IRTemp condT ) -@@ -4601,7 +4626,8 @@ - /* VABD */ - if (Q) { - assign(res, unop(Iop_Abs32Fx4, -- binop(Iop_Sub32Fx4, -+ triop(Iop_Sub32Fx4, -+ get_FAKE_roundingmode(), - mkexpr(arg_n), - mkexpr(arg_m)))); - } else { -@@ -4616,7 +4642,7 @@ - break; - } - } -- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); -+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m))); - } else { - if (U == 0) { - /* VMLA, VMLS */ -@@ -4641,9 +4667,11 @@ - default: vassert(0); - } - } -- assign(res, binop(op2, -- Q ? getQReg(dreg) : getDRegI64(dreg), -- binop(op, mkexpr(arg_n), mkexpr(arg_m)))); -+ assign(res, binop_w_fake_RM( -+ op2, -+ Q ? getQReg(dreg) : getDRegI64(dreg), -+ binop_w_fake_RM(op, mkexpr(arg_n), -+ mkexpr(arg_m)))); - - DIP("vml%c.f32 %c%u, %c%u, %c%u\n", - P ? 's' : 'a', Q ? 'q' : 'd', -@@ -4654,7 +4682,7 @@ - if ((C >> 1) != 0) - return False; - op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2 ; -- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); -+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m))); - DIP("vmul.f32 %c%u, %c%u, %c%u\n", - Q ? 'q' : 'd', dreg, - Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg); -@@ -5318,10 +5346,10 @@ - } - } - op2 = INSN(10,10) ? sub : add; -- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); -+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m))); - if (Q) -- putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), -- condT); -+ putQReg(dreg, binop_w_fake_RM(op2, getQReg(dreg), mkexpr(res)), -+ condT); - else - putDRegI64(dreg, binop(op2, getDRegI64(dreg), mkexpr(res)), - condT); -@@ -5548,7 +5576,7 @@ - vassert(0); - } - } -- assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m))); -+ assign(res, binop_w_fake_RM(op, mkexpr(arg_n), mkexpr(arg_m))); - if (Q) - putQReg(dreg, mkexpr(res), condT); - else -@@ -13499,6 +13527,27 @@ - condT); - DIP("fdivd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); - goto decode_success_vfp; -+ case BITS4(1,1,0,0): /* VFMA: d + n * m (fused) */ -+ /* XXXROUNDINGFIXME look up ARM reference for fused -+ multiply-add rounding */ -+ putDReg(dD, triop(Iop_AddF64, rm, -+ getDReg(dD), -+ triop(Iop_MulF64, rm, getDReg(dN), -+ getDReg(dM))), -+ condT); -+ DIP("vfmad%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); -+ goto decode_success_vfp; -+ case BITS4(1,1,0,1): /* VFMS: d + (-n * m) (fused) */ -+ /* XXXROUNDINGFIXME look up ARM reference for fused -+ multiply-add rounding */ -+ putDReg(dD, triop(Iop_AddF64, rm, -+ getDReg(dD), -+ triop(Iop_MulF64, rm, -+ unop(Iop_NegF64, getDReg(dN)), -+ getDReg(dM))), -+ condT); -+ DIP("vfmsd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM); -+ goto decode_success_vfp; - default: - break; - } -@@ -13963,6 +14012,27 @@ - condT); - DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); - goto decode_success_vfp; -+ case BITS4(1,1,0,0): /* VFMA: d + n * m (fused) */ -+ /* XXXROUNDINGFIXME look up ARM reference for fused -+ multiply-add rounding */ -+ putFReg(fD, triop(Iop_AddF32, rm, -+ getFReg(fD), -+ triop(Iop_MulF32, rm, getFReg(fN), -+ getFReg(fM))), -+ condT); -+ DIP("vfmas%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); -+ goto decode_success_vfp; -+ case BITS4(1,1,0,1): /* VFMS: d + (-n * m) (fused) */ -+ /* XXXROUNDINGFIXME look up ARM reference for fused -+ multiply-add rounding */ -+ putFReg(fD, triop(Iop_AddF32, rm, -+ getFReg(fD), -+ triop(Iop_MulF32, rm, -+ unop(Iop_NegF32, getFReg(fN)), -+ getFReg(fM))), -+ condT); -+ DIP("vfmss%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM); -+ goto decode_success_vfp; - default: - break; - } -@@ -14577,11 +14647,11 @@ - // injecting here can change. In which case the translation has to - // be redone. For ease of handling, we simply invalidate all the - // time. -- stmt(IRStmt_Put(OFFB_TISTART, mkU32(guest_R15_curr_instr_notENC))); -- stmt(IRStmt_Put(OFFB_TILEN, mkU32(20))); -+ stmt(IRStmt_Put(OFFB_CMSTART, mkU32(guest_R15_curr_instr_notENC))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkU32(20))); - llPutIReg(15, mkU32( guest_R15_curr_instr_notENC + 20 )); - dres.whatNext = Dis_StopHere; -- dres.jk_StopHere = Ijk_TInval; -+ dres.jk_StopHere = Ijk_InvalICache; - goto decode_success; - } - /* We don't know what it is. Set opc1/opc2 so decode_failure -@@ -17422,11 +17492,11 @@ - // injecting here can change. In which case the translation has to - // be redone. For ease of handling, we simply invalidate all the - // time. -- stmt(IRStmt_Put(OFFB_TISTART, mkU32(guest_R15_curr_instr_notENC))); -- stmt(IRStmt_Put(OFFB_TILEN, mkU32(20))); -+ stmt(IRStmt_Put(OFFB_CMSTART, mkU32(guest_R15_curr_instr_notENC))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkU32(20))); - llPutIReg(15, mkU32( (guest_R15_curr_instr_notENC + 20) | 1 )); - dres.whatNext = Dis_StopHere; -- dres.jk_StopHere = Ijk_TInval; -+ dres.jk_StopHere = Ijk_InvalICache; - goto decode_success; - } - /* We don't know what it is. Set insn0 so decode_failure -@@ -18203,9 +18273,9 @@ - condT = IRTemp_INVALID; - // now uncond - /* non-interworking branch */ -- irsb->next = binop(Iop_Or32, mkexpr(res), mkU32(1)); -- irsb->jumpkind = Ijk_Boring; -- dres.whatNext = Dis_StopHere; -+ llPutIReg(15, binop(Iop_Or32, mkexpr(res), mkU32(1))); -+ dres.jk_StopHere = Ijk_Boring; -+ dres.whatNext = Dis_StopHere; - } - DIP("add(hi) r%u, r%u\n", rD, rM); - goto decode_success; -@@ -20250,7 +20320,7 @@ - - /* --------------- LD/ST reg+imm12 --------------- */ - /* Loads and stores of the form: -- op Rt, [Rn, +#imm12] -+ op Rt, [Rn, #+-imm12] - where op is one of - ldrb ldrh ldr ldrsb ldrsh - strb strh str -@@ -20257,27 +20327,25 @@ - */ - if (INSN0(15,9) == BITS7(1,1,1,1,1,0,0)) { - Bool valid = True; -- Bool syned = False; -+ Bool syned = INSN0(8,8) == 1; - Bool isST = False; - IRType ty = Ity_I8; -+ UInt bU = INSN0(7,7); // 1: +imm 0: -imm -+ // -imm is only supported by literal versions - const HChar* nm = "???"; - -- switch (INSN0(8,4)) { -- case BITS5(0,1,0,0,0): // strb -+ switch (INSN0(6,4)) { -+ case BITS3(0,0,0): // strb - nm = "strb"; isST = True; break; -- case BITS5(0,1,0,0,1): // ldrb -- nm = "ldrb"; break; -- case BITS5(1,1,0,0,1): // ldrsb -- nm = "ldrsb"; syned = True; break; -- case BITS5(0,1,0,1,0): // strh -+ case BITS3(0,0,1): // ldrb -+ nm = syned ? "ldrsb" : "ldrb"; break; -+ case BITS3(0,1,0): // strh - nm = "strh"; ty = Ity_I16; isST = True; break; -- case BITS5(0,1,0,1,1): // ldrh -- nm = "ldrh"; ty = Ity_I16; break; -- case BITS5(1,1,0,1,1): // ldrsh -- nm = "ldrsh"; ty = Ity_I16; syned = True; break; -- case BITS5(0,1,1,0,0): // str -+ case BITS3(0,1,1): // ldrh -+ nm = syned ? "ldrsh" : "ldrh"; ty = Ity_I16; break; -+ case BITS3(1,0,0): // str - nm = "str"; ty = Ity_I32; isST = True; break; -- case BITS5(0,1,1,0,1): -+ case BITS3(1,0,1): - nm = "ldr"; ty = Ity_I32; break; // ldr - default: - valid = False; break; -@@ -20288,25 +20356,27 @@ - UInt imm12 = INSN1(11,0); - Bool loadsPC = False; - -- if (ty == Ity_I8 || ty == Ity_I16) { -- /* all 8- and 16-bit load and store cases have the -- same exclusion set. */ -- if (rN == 15 || isBadRegT(rT)) -+ if (rN != 15 && bU == 0) { -+ // only pc supports #-imm12 -+ valid = False; -+ } -+ -+ if (isST) { -+ if (syned) valid = False; -+ if (rN == 15 || rT == 15) - valid = False; - } else { -- vassert(ty == Ity_I32); -- if (isST) { -- if (rN == 15 || rT == 15) -+ /* For a 32-bit load, rT == 15 is only allowable if we are not -+ in an IT block, or are the last in it. Need to insert -+ a dynamic check for that. Also, in this particular -+ case, rN == 15 is allowable. In this case however, the -+ value obtained for rN is (apparently) -+ "word-align(address of current insn + 4)". */ -+ if (rT == 15) { -+ if (ty == Ity_I32) -+ loadsPC = True; -+ else // Can't do it for B/H loads - valid = False; -- } else { -- /* For a 32-bit load, rT == 15 is only allowable if we not -- in an IT block, or are the last in it. Need to insert -- a dynamic check for that. Also, in this particular -- case, rN == 15 is allowable. In this case however, the -- value obtained for rN is (apparently) -- "word-align(address of current insn + 4)". */ -- if (rT == 15) -- loadsPC = True; - } - } - -@@ -20324,8 +20394,8 @@ - - IRTemp rNt = newTemp(Ity_I32); - if (rN == 15) { -- vassert(ty == Ity_I32 && !isST); -- assign(rNt, binop(Iop_And32, getIRegT(rN), mkU32(~3))); -+ vassert(!isST); -+ assign(rNt, binop(Iop_And32, getIRegT(15), mkU32(~3))); - } else { - assign(rNt, getIRegT(rN)); - } -@@ -20332,7 +20402,8 @@ - - IRTemp transAddr = newTemp(Ity_I32); - assign(transAddr, -- binop( Iop_Add32, mkexpr(rNt), mkU32(imm12) )); -+ binop(bU == 1 ? Iop_Add32 : Iop_Sub32, -+ mkexpr(rNt), mkU32(imm12))); - - IRTemp oldRt = newTemp(Ity_I32); - assign(oldRt, getIRegT(rT)); -@@ -20387,9 +20458,8 @@ - vassert(rT == 15); - vassert(condT == IRTemp_INVALID); /* due to check above */ - llPutIReg(15, mkexpr(newRt)); -- irsb->next = mkexpr(newRt); -- irsb->jumpkind = Ijk_Boring; /* or _Ret ? */ -- dres.whatNext = Dis_StopHere; -+ dres.jk_StopHere = Ijk_Boring; -+ dres.whatNext = Dis_StopHere; - } - } - -@@ -20401,7 +20471,7 @@ - - /* -------------- LDRD/STRD reg+/-#imm8 -------------- */ - /* Doubleword loads and stores of the form: -- ldrd/strd Rt, Rt2, [Rn, #-imm8] or -+ ldrd/strd Rt, Rt2, [Rn, #+/-imm8] or - ldrd/strd Rt, Rt2, [Rn], #+/-imm8 or - ldrd/strd Rt, Rt2, [Rn, #+/-imm8]! - */ -@@ -20419,12 +20489,17 @@ - if (bP == 0 && bW == 0) valid = False; - if (bW == 1 && (rN == rT || rN == rT2)) valid = False; - if (isBadRegT(rT) || isBadRegT(rT2)) valid = False; -- if (rN == 15) valid = False; - if (bL == 1 && rT == rT2) valid = False; -+ /* It's OK to use PC as the base register only in the -+ following case: ldrd Rt, Rt2, [PC, #+/-imm8] */ -+ if (rN == 15 && (bL == 0/*store*/ -+ || bW == 1/*wb*/)) valid = False; - - if (valid) { - IRTemp preAddr = newTemp(Ity_I32); -- assign(preAddr, getIRegT(rN)); -+ assign(preAddr, 15 == rN -+ ? binop(Iop_And32, getIRegT(15), mkU32(~3U)) -+ : getIRegT(rN)); - - IRTemp postAddr = newTemp(Ity_I32); - assign(postAddr, binop(bU == 1 ? Iop_Add32 : Iop_Sub32, -Index: priv/guest_generic_bb_to_IR.c -=================================================================== ---- priv/guest_generic_bb_to_IR.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_generic_bb_to_IR.c (.../trunk) (revision 2863) -@@ -131,8 +131,8 @@ - not to disassemble any instructions into it; this is indicated - by the callback returning True. - -- offB_TIADDR and offB_TILEN are the offsets of guest_TIADDR and -- guest_TILEN. Since this routine has to work for any guest state, -+ offB_CMADDR and offB_CMLEN are the offsets of guest_CMADDR and -+ guest_CMLEN. Since this routine has to work for any guest state, - without knowing what it is, those offsets have to passed in. - - callback_opaque is a caller-supplied pointer to data which the -@@ -194,8 +194,8 @@ - /*IN*/ IRType guest_word_type, - /*IN*/ UInt (*needs_self_check)(void*,VexGuestExtents*), - /*IN*/ Bool (*preamble_function)(void*,IRSB*), -- /*IN*/ Int offB_GUEST_TISTART, -- /*IN*/ Int offB_GUEST_TILEN, -+ /*IN*/ Int offB_GUEST_CMSTART, -+ /*IN*/ Int offB_GUEST_CMLEN, - /*IN*/ Int offB_GUEST_IP, - /*IN*/ Int szB_GUEST_IP - ) -@@ -663,7 +663,7 @@ - vassert(!nm_spec); - } - -- /* Set TISTART and TILEN. These will describe to the despatcher -+ /* Set CMSTART and CMLEN. These will describe to the despatcher - the area of guest code to invalidate should we exit with a - self-check failure. */ - -@@ -684,10 +684,10 @@ - = IRStmt_WrTmp(tilen_tmp, IRExpr_Const(len2check_IRConst) ); - - irsb->stmts[selfcheck_idx + i * 5 + 2] -- = IRStmt_Put( offB_GUEST_TISTART, IRExpr_RdTmp(tistart_tmp) ); -+ = IRStmt_Put( offB_GUEST_CMSTART, IRExpr_RdTmp(tistart_tmp) ); - - irsb->stmts[selfcheck_idx + i * 5 + 3] -- = IRStmt_Put( offB_GUEST_TILEN, IRExpr_RdTmp(tilen_tmp) ); -+ = IRStmt_Put( offB_GUEST_CMLEN, IRExpr_RdTmp(tilen_tmp) ); - - /* Generate the entry point descriptors */ - if (abiinfo_both->host_ppc_calls_use_fndescrs) { -@@ -737,7 +737,7 @@ - ? IRExpr_Const(IRConst_U64(expectedhW)) - : IRExpr_Const(IRConst_U32(expectedhW)) - ), -- Ijk_TInval, -+ Ijk_InvalICache, - /* Where we must restart if there's a failure: at the - first extent, regardless of which extent the - failure actually happened in. */ -Index: priv/guest_generic_bb_to_IR.h -=================================================================== ---- priv/guest_generic_bb_to_IR.h (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_generic_bb_to_IR.h (.../trunk) (revision 2863) -@@ -184,8 +184,8 @@ - /*IN*/ IRType guest_word_type, - /*IN*/ UInt (*needs_self_check)(void*,VexGuestExtents*), - /*IN*/ Bool (*preamble_function)(void*,IRSB*), -- /*IN*/ Int offB_GUEST_TISTART, -- /*IN*/ Int offB_GUEST_TILEN, -+ /*IN*/ Int offB_GUEST_CMSTART, -+ /*IN*/ Int offB_GUEST_CMLEN, - /*IN*/ Int offB_GUEST_IP, - /*IN*/ Int szB_GUEST_IP - ); -Index: priv/guest_mips_defs.h -=================================================================== ---- priv/guest_mips_defs.h (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_mips_defs.h (.../trunk) (revision 2863) -@@ -85,7 +85,8 @@ - TRUNCWS, TRUNCWD, TRUNCLS, TRUNCLD, - CVTDS, CVTDW, CVTSD, CVTSW, - CVTWS, CVTWD, CVTDL, CVTLS, -- CVTLD, CVTSL -+ CVTLD, CVTSL, ADDS, ADDD, -+ SUBS, SUBD, DIVS - } flt_op; - - extern UInt mips32_dirtyhelper_mfc0 ( UInt rd, UInt sel ); -@@ -98,8 +99,12 @@ - extern ULong mips64_dirtyhelper_rdhwr ( ULong rt, ULong rd ); - #endif - --extern UInt mips_dirtyhelper_calculate_FCSR ( void* guest_state, UInt fs, -- flt_op op ); -+/* Calculate FCSR in fp32 mode. */ -+extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* guest_state, UInt fs, -+ UInt ft, flt_op op ); -+/* Calculate FCSR in fp64 mode. */ -+extern UInt mips_dirtyhelper_calculate_FCSR_fp64 ( void* guest_state, UInt fs, -+ UInt ft, flt_op op ); - - /*---------------------------------------------------------*/ - /*--- Condition code stuff ---*/ -Index: priv/guest_mips_helpers.c -=================================================================== ---- priv/guest_mips_helpers.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_mips_helpers.c (.../trunk) (revision 2863) -@@ -44,7 +44,7 @@ - these functions are generated by the back end. - */ - --#define ALWAYSDEFD32(field) \ -+#define ALWAYSDEFD32(field) \ - { offsetof(VexGuestMIPS32State, field), \ - (sizeof ((VexGuestMIPS32State*)0)->field) } - -@@ -105,38 +105,38 @@ - vex_state->guest_LO = 0; /* Multiply and divide register lower result */ - - /* FPU Registers */ -- vex_state->guest_f0 = 0x7ff80000; /* Floting point general purpose registers */ -- vex_state->guest_f1 = 0x7ff80000; -- vex_state->guest_f2 = 0x7ff80000; -- vex_state->guest_f3 = 0x7ff80000; -- vex_state->guest_f4 = 0x7ff80000; -- vex_state->guest_f5 = 0x7ff80000; -- vex_state->guest_f6 = 0x7ff80000; -- vex_state->guest_f7 = 0x7ff80000; -- vex_state->guest_f8 = 0x7ff80000; -- vex_state->guest_f9 = 0x7ff80000; -- vex_state->guest_f10 = 0x7ff80000; -- vex_state->guest_f11 = 0x7ff80000; -- vex_state->guest_f12 = 0x7ff80000; -- vex_state->guest_f13 = 0x7ff80000; -- vex_state->guest_f14 = 0x7ff80000; -- vex_state->guest_f15 = 0x7ff80000; -- vex_state->guest_f16 = 0x7ff80000; -- vex_state->guest_f17 = 0x7ff80000; -- vex_state->guest_f18 = 0x7ff80000; -- vex_state->guest_f19 = 0x7ff80000; -- vex_state->guest_f20 = 0x7ff80000; -- vex_state->guest_f21 = 0x7ff80000; -- vex_state->guest_f22 = 0x7ff80000; -- vex_state->guest_f23 = 0x7ff80000; -- vex_state->guest_f24 = 0x7ff80000; -- vex_state->guest_f25 = 0x7ff80000; -- vex_state->guest_f26 = 0x7ff80000; -- vex_state->guest_f27 = 0x7ff80000; -- vex_state->guest_f28 = 0x7ff80000; -- vex_state->guest_f29 = 0x7ff80000; -- vex_state->guest_f30 = 0x7ff80000; -- vex_state->guest_f31 = 0x7ff80000; -+ vex_state->guest_f0 = 0x7ff800007ff80000ULL; /* Floting point GP registers */ -+ vex_state->guest_f1 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f2 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f3 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f4 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f5 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f6 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f7 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f8 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f9 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f10 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f11 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f12 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f13 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f14 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f15 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f16 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f17 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f18 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f19 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f20 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f21 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f22 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f23 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f24 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f25 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f26 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f27 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f28 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f29 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f30 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f31 = 0x7ff800007ff80000ULL; - - vex_state->guest_FIR = 0; /* FP implementation and revision register */ - vex_state->guest_FCCR = 0; /* FP condition codes register */ -@@ -150,8 +150,8 @@ - vex_state->guest_EMNOTE = 0; - - /* For clflush: record start and length of area to invalidate */ -- vex_state->guest_TISTART = 0; -- vex_state->guest_TILEN = 0; -+ vex_state->guest_CMSTART = 0; -+ vex_state->guest_CMLEN = 0; - vex_state->host_EvC_COUNTER = 0; - vex_state->host_EvC_FAILADDR = 0; - -@@ -212,38 +212,38 @@ - vex_state->guest_LO = 0; /* Multiply and divide register lower result */ - - /* FPU Registers */ -- vex_state->guest_f0 = 0xffffffffffffffffULL; /* Floting point registers */ -- vex_state->guest_f1 = 0xffffffffffffffffULL; -- vex_state->guest_f2 = 0xffffffffffffffffULL; -- vex_state->guest_f3 = 0xffffffffffffffffULL; -- vex_state->guest_f4 = 0xffffffffffffffffULL; -- vex_state->guest_f5 = 0xffffffffffffffffULL; -- vex_state->guest_f6 = 0xffffffffffffffffULL; -- vex_state->guest_f7 = 0xffffffffffffffffULL; -- vex_state->guest_f8 = 0xffffffffffffffffULL; -- vex_state->guest_f9 = 0xffffffffffffffffULL; -- vex_state->guest_f10 = 0xffffffffffffffffULL; -- vex_state->guest_f11 = 0xffffffffffffffffULL; -- vex_state->guest_f12 = 0xffffffffffffffffULL; -- vex_state->guest_f13 = 0xffffffffffffffffULL; -- vex_state->guest_f14 = 0xffffffffffffffffULL; -- vex_state->guest_f15 = 0xffffffffffffffffULL; -- vex_state->guest_f16 = 0xffffffffffffffffULL; -- vex_state->guest_f17 = 0xffffffffffffffffULL; -- vex_state->guest_f18 = 0xffffffffffffffffULL; -- vex_state->guest_f19 = 0xffffffffffffffffULL; -- vex_state->guest_f20 = 0xffffffffffffffffULL; -- vex_state->guest_f21 = 0xffffffffffffffffULL; -- vex_state->guest_f22 = 0xffffffffffffffffULL; -- vex_state->guest_f23 = 0xffffffffffffffffULL; -- vex_state->guest_f24 = 0xffffffffffffffffULL; -- vex_state->guest_f25 = 0xffffffffffffffffULL; -- vex_state->guest_f26 = 0xffffffffffffffffULL; -- vex_state->guest_f27 = 0xffffffffffffffffULL; -- vex_state->guest_f28 = 0xffffffffffffffffULL; -- vex_state->guest_f29 = 0xffffffffffffffffULL; -- vex_state->guest_f30 = 0xffffffffffffffffULL; -- vex_state->guest_f31 = 0xffffffffffffffffULL; -+ vex_state->guest_f0 = 0x7ff800007ff80000ULL; /* Floting point registers */ -+ vex_state->guest_f1 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f2 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f3 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f4 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f5 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f6 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f7 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f8 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f9 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f10 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f11 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f12 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f13 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f14 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f15 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f16 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f17 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f18 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f19 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f20 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f21 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f22 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f23 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f24 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f25 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f26 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f27 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f28 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f29 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f30 = 0x7ff800007ff80000ULL; -+ vex_state->guest_f31 = 0x7ff800007ff80000ULL; - - vex_state->guest_FIR = 0; /* FP implementation and revision register */ - vex_state->guest_FCCR = 0; /* FP condition codes register */ -@@ -258,8 +258,8 @@ - vex_state->guest_EMNOTE = 0; - - /* For clflush: record start and length of area to invalidate */ -- vex_state->guest_TISTART = 0; -- vex_state->guest_TILEN = 0; -+ vex_state->guest_CMSTART = 0; -+ vex_state->guest_CMLEN = 0; - vex_state->host_EvC_COUNTER = 0; - vex_state->host_EvC_FAILADDR = 0; - -@@ -375,8 +375,8 @@ - /* 0 */ ALWAYSDEFD32(guest_r0), - /* 1 */ ALWAYSDEFD32(guest_r1), - /* 2 */ ALWAYSDEFD32(guest_EMNOTE), -- /* 3 */ ALWAYSDEFD32(guest_TISTART), -- /* 4 */ ALWAYSDEFD32(guest_TILEN), -+ /* 3 */ ALWAYSDEFD32(guest_CMSTART), -+ /* 4 */ ALWAYSDEFD32(guest_CMLEN), - /* 5 */ ALWAYSDEFD32(guest_r29), - /* 6 */ ALWAYSDEFD32(guest_r31), - /* 7 */ ALWAYSDEFD32(guest_ULR) -@@ -402,8 +402,8 @@ - .alwaysDefd = { - /* 0 */ ALWAYSDEFD64 (guest_r0), - /* 1 */ ALWAYSDEFD64 (guest_EMNOTE), -- /* 2 */ ALWAYSDEFD64 (guest_TISTART), -- /* 3 */ ALWAYSDEFD64 (guest_TILEN), -+ /* 2 */ ALWAYSDEFD64 (guest_CMSTART), -+ /* 3 */ ALWAYSDEFD64 (guest_CMLEN), - /* 4 */ ALWAYSDEFD64 (guest_r29), - /* 5 */ ALWAYSDEFD64 (guest_r31), - /* 6 */ ALWAYSDEFD64 (guest_ULR) -@@ -1107,145 +1107,324 @@ - } - #endif - --#define ASM_VOLATILE_ROUND32(fs, inst) \ -- __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -- "ctc1 %2, $31" "\n\t" \ -- "mtc1 %1, $f0" "\n\t" \ -- ""#inst" $f0, $f0" "\n\t" \ -- "cfc1 %0, $31" "\n\t" \ -- "ctc1 $t0, $31" "\n\t" \ -+#define ASM_VOLATILE_UNARY32(inst) \ -+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -+ "ctc1 %2, $31" "\n\t" \ -+ "mtc1 %1, $f20" "\n\t" \ -+ #inst" $f20, $f20" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ "ctc1 $t0, $31" "\n\t" \ - : "=r" (ret) \ -- : "r" (loVal), "r" (fcsr) \ -- : "t0", "$f0", "$f1" \ -+ : "r" (loFsVal), "r" (fcsr) \ -+ : "t0", "$f20" \ - ); - --#define ASM_VOLATILE_ROUND32_DOUBLE(fs, inst) \ -- __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -- "ctc1 %3, $31" "\n\t" \ -- "mtc1 %1, $f0" "\n\t" \ -- "mtc1 %2, $f1" "\n\t" \ -- ""#inst" $f0, $f0" "\n\t" \ -- "cfc1 %0, $31" "\n\t" \ -- "ctc1 $t0, $31" "\n\t" \ -+#define ASM_VOLATILE_UNARY32_DOUBLE(inst) \ -+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -+ "ctc1 %3, $31" "\n\t" \ -+ "mtc1 %1, $f20" "\n\t" \ -+ "mtc1 %2, $f21" "\n\t" \ -+ #inst" $f20, $f20" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ "ctc1 $t0, $31" "\n\t" \ - : "=r" (ret) \ -- : "r" (loVal), "r" (hiVal), "r" (fcsr) \ -- : "t0", "$f0", "$f1" \ -+ : "r" (loFsVal), "r" (hiFsVal), "r" (fcsr) \ -+ : "t0", "$f20", "$f21" \ - ); - --#define ASM_VOLATILE_ROUND64(fs, inst) \ -- __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -- "ctc1 %2, $31" "\n\t" \ -- "dmtc1 %1, $f0" "\n\t" \ -- ""#inst" $f0, $f0" "\n\t" \ -- "cfc1 %0, $31" "\n\t" \ -- "ctc1 $t0, $31" "\n\t" \ -+#define ASM_VOLATILE_UNARY64(inst) \ -+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -+ "ctc1 %2, $31" "\n\t" \ -+ "ldc1 $f24, 0(%1)" "\n\t" \ -+ #inst" $f24, $f24" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ "ctc1 $t0, $31" "\n\t" \ - : "=r" (ret) \ -- : "r" (addr[fs]), "r" (fcsr) \ -- : "t0", "$f0" \ -+ : "r" (&(addr[fs])), "r" (fcsr) \ -+ : "t0", "$f24" \ - ); - -+#define ASM_VOLATILE_BINARY32(inst) \ -+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -+ "ctc1 %3, $31" "\n\t" \ -+ "mtc1 %1, $f20" "\n\t" \ -+ "mtc1 %2, $f22" "\n\t" \ -+ #inst" $f20, $f20, $f22" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ "ctc1 $t0, $31" "\n\t" \ -+ : "=r" (ret) \ -+ : "r" (loFsVal), "r" (loFtVal), "r" (fcsr) \ -+ : "t0", "$f20", "$f22" \ -+ ); -+ -+#define ASM_VOLATILE_BINARY32_DOUBLE(inst) \ -+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -+ "ctc1 %5, $31" "\n\t" \ -+ "mtc1 %1, $f20" "\n\t" \ -+ "mtc1 %2, $f21" "\n\t" \ -+ "mtc1 %3, $f22" "\n\t" \ -+ "mtc1 %4, $f23" "\n\t" \ -+ #inst" $f20, $f20, $f22" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ "ctc1 $t0, $31" "\n\t" \ -+ : "=r" (ret) \ -+ : "r" (loFsVal), "r" (hiFsVal), "r" (loFtVal), \ -+ "r" (hiFtVal), "r" (fcsr) \ -+ : "t0", "$f20", "$f21", "$f22", "$f23" \ -+ ); -+ -+#define ASM_VOLATILE_BINARY64(inst) \ -+ __asm__ volatile("cfc1 $t0, $31" "\n\t" \ -+ "ctc1 %3, $31" "\n\t" \ -+ "ldc1 $f24, 0(%1)" "\n\t" \ -+ "ldc1 $f26, 0(%2)" "\n\t" \ -+ #inst" $f24, $f24, $f26" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ "ctc1 $t0, $31" "\n\t" \ -+ : "=r" (ret) \ -+ : "r" (&(addr[fs])), "r" (&(addr[ft])), "r" (fcsr) \ -+ : "t0", "$f24", "$f26" \ -+ ); -+ - /* TODO: Add cases for all fpu instructions because all fpu instructions are - change the value of FCSR register. */ --extern UInt mips_dirtyhelper_calculate_FCSR ( void* gs, UInt fs, flt_op inst ) -+extern UInt mips_dirtyhelper_calculate_FCSR_fp32 ( void* gs, UInt fs, UInt ft, -+ flt_op inst ) - { - UInt ret = 0; - #if defined(__mips__) -+ VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs; -+ UInt loFsVal, hiFsVal, loFtVal, hiFtVal; -+#if defined (_MIPSEL) -+ ULong *addr = (ULong *)&guest_state->guest_f0; -+ loFsVal = (UInt)addr[fs]; -+ hiFsVal = (UInt)addr[fs+1]; -+ loFtVal = (UInt)addr[ft]; -+ hiFtVal = (UInt)addr[ft+1]; -+#elif defined (_MIPSEB) -+ UInt *addr = (UInt *)&guest_state->guest_f0; -+ loFsVal = (UInt)addr[fs*2]; -+ hiFsVal = (UInt)addr[fs*2+2]; -+ loFtVal = (UInt)addr[ft*2]; -+ hiFtVal = (UInt)addr[ft*2+2]; -+#endif -+ UInt fcsr = guest_state->guest_FCSR; -+ switch (inst) { -+ case ROUNDWD: -+ ASM_VOLATILE_UNARY32_DOUBLE(round.w.d) -+ break; -+ case FLOORWS: -+ ASM_VOLATILE_UNARY32(floor.w.s) -+ break; -+ case FLOORWD: -+ ASM_VOLATILE_UNARY32_DOUBLE(floor.w.d) -+ break; -+ case TRUNCWS: -+ ASM_VOLATILE_UNARY32(trunc.w.s) -+ break; -+ case TRUNCWD: -+ ASM_VOLATILE_UNARY32_DOUBLE(trunc.w.d) -+ break; -+ case CEILWS: -+ ASM_VOLATILE_UNARY32(ceil.w.s) -+ break; -+ case CEILWD: -+ ASM_VOLATILE_UNARY32_DOUBLE(ceil.w.d) -+ break; -+ case CVTDS: -+ ASM_VOLATILE_UNARY32(cvt.d.s) -+ break; -+ case CVTDW: -+ ASM_VOLATILE_UNARY32(cvt.d.w) -+ break; -+ case CVTSW: -+ ASM_VOLATILE_UNARY32(cvt.s.w) -+ break; -+ case CVTSD: -+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.s.d) -+ break; -+ case CVTWS: -+ ASM_VOLATILE_UNARY32(cvt.w.s) -+ break; -+ case CVTWD: -+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.w.d) -+ break; -+ case ROUNDWS: -+ ASM_VOLATILE_UNARY32(round.w.s) -+ break; -+#if ((__mips == 32) && defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \ -+ || (__mips == 64) -+ case CEILLS: -+ ASM_VOLATILE_UNARY32(ceil.l.s) -+ break; -+ case CEILLD: -+ ASM_VOLATILE_UNARY32_DOUBLE(ceil.l.d) -+ break; -+ case CVTDL: -+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.d.l) -+ break; -+ case CVTLS: -+ ASM_VOLATILE_UNARY32(cvt.l.s) -+ break; -+ case CVTLD: -+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.l.d) -+ break; -+ case CVTSL: -+ ASM_VOLATILE_UNARY32_DOUBLE(cvt.s.l) -+ break; -+ case FLOORLS: -+ ASM_VOLATILE_UNARY32(floor.l.s) -+ break; -+ case FLOORLD: -+ ASM_VOLATILE_UNARY32_DOUBLE(floor.l.d) -+ break; -+ case ROUNDLS: -+ ASM_VOLATILE_UNARY32(round.l.s) -+ break; -+ case ROUNDLD: -+ ASM_VOLATILE_UNARY32_DOUBLE(round.l.d) -+ break; -+ case TRUNCLS: -+ ASM_VOLATILE_UNARY32(trunc.l.s) -+ break; -+ case TRUNCLD: -+ ASM_VOLATILE_UNARY32_DOUBLE(trunc.l.d) -+ break; -+#endif -+ case ADDS: -+ ASM_VOLATILE_BINARY32(add.s) -+ break; -+ case ADDD: -+ ASM_VOLATILE_BINARY32_DOUBLE(add.d) -+ break; -+ case SUBS: -+ ASM_VOLATILE_BINARY32(sub.s) -+ break; -+ case SUBD: -+ ASM_VOLATILE_BINARY32_DOUBLE(sub.d) -+ break; -+ case DIVS: -+ ASM_VOLATILE_BINARY32(div.s) -+ break; -+ default: -+ vassert(0); -+ break; -+ } -+#endif -+ return ret; -+} -+ -+/* TODO: Add cases for all fpu instructions because all fpu instructions are -+ change the value of FCSR register. */ -+extern UInt mips_dirtyhelper_calculate_FCSR_fp64 ( void* gs, UInt fs, UInt ft, -+ flt_op inst ) -+{ -+ UInt ret = 0; -+#if defined(__mips__) - #if defined(VGA_mips32) - VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs; -- UInt *addr = (UInt *)&guest_state->guest_f0; -- UInt loVal = addr[fs]; -- UInt hiVal = addr[fs+1]; --#define ASM_VOLATILE_ROUND(fs, inst) ASM_VOLATILE_ROUND32(fs, inst) --#define ASM_VOLATILE_ROUND_DOUBLE(fs, inst) ASM_VOLATILE_ROUND32_DOUBLE(fs, inst) - #else - VexGuestMIPS64State* guest_state = (VexGuestMIPS64State*)gs; -+#endif - ULong *addr = (ULong *)&guest_state->guest_f0; --#define ASM_VOLATILE_ROUND(fs, inst) ASM_VOLATILE_ROUND64(fs, inst) --#define ASM_VOLATILE_ROUND_DOUBLE(fs, inst) ASM_VOLATILE_ROUND64(fs, inst) --#endif -- UInt fcsr = guest_state->guest_FCSR; -+ UInt fcsr = guest_state->guest_FCSR; - switch (inst) { - case ROUNDWD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, round.w.d) -+ ASM_VOLATILE_UNARY64(round.w.d) - break; - case FLOORWS: -- ASM_VOLATILE_ROUND(fs, floor.w.s) -+ ASM_VOLATILE_UNARY64(floor.w.s) - break; - case FLOORWD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, floor.w.d) -+ ASM_VOLATILE_UNARY64(floor.w.d) - break; - case TRUNCWS: -- ASM_VOLATILE_ROUND(fs, trunc.w.s) -+ ASM_VOLATILE_UNARY64(trunc.w.s) - break; - case TRUNCWD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, trunc.w.d) -+ ASM_VOLATILE_UNARY64(trunc.w.d) - break; - case CEILWS: -- ASM_VOLATILE_ROUND(fs, ceil.w.s) -+ ASM_VOLATILE_UNARY64(ceil.w.s) - break; - case CEILWD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, ceil.w.d) -+ ASM_VOLATILE_UNARY64(ceil.w.d) - break; - case CVTDS: -- ASM_VOLATILE_ROUND(fs, cvt.d.s) -+ ASM_VOLATILE_UNARY64(cvt.d.s) - break; - case CVTDW: -- ASM_VOLATILE_ROUND(fs, cvt.d.w) -+ ASM_VOLATILE_UNARY64(cvt.d.w) - break; - case CVTSW: -- ASM_VOLATILE_ROUND(fs, cvt.s.w) -+ ASM_VOLATILE_UNARY64(cvt.s.w) - break; - case CVTSD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, cvt.s.d) -+ ASM_VOLATILE_UNARY64(cvt.s.d) - break; - case CVTWS: -- ASM_VOLATILE_ROUND(fs, cvt.w.s) -+ ASM_VOLATILE_UNARY64(cvt.w.s) - break; - case CVTWD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, cvt.w.d) -+ ASM_VOLATILE_UNARY64(cvt.w.d) - break; - case ROUNDWS: -- ASM_VOLATILE_ROUND(fs, round.w.s) -+ ASM_VOLATILE_UNARY64(round.w.s) - break; - #if ((__mips == 32) && defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) \ - || (__mips == 64) - case CEILLS: -- ASM_VOLATILE_ROUND(fs, ceil.l.s) -+ ASM_VOLATILE_UNARY64(ceil.l.s) - break; - case CEILLD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, ceil.l.d) -+ ASM_VOLATILE_UNARY64(ceil.l.d) - break; - case CVTDL: -- ASM_VOLATILE_ROUND_DOUBLE(fs, cvt.d.l) -+ ASM_VOLATILE_UNARY64(cvt.d.l) - break; - case CVTLS: -- ASM_VOLATILE_ROUND(fs, cvt.l.s) -+ ASM_VOLATILE_UNARY64(cvt.l.s) - break; - case CVTLD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, cvt.l.d) -+ ASM_VOLATILE_UNARY64(cvt.l.d) - break; - case CVTSL: -- ASM_VOLATILE_ROUND_DOUBLE(fs, cvt.s.l) -+ ASM_VOLATILE_UNARY64(cvt.s.l) - break; - case FLOORLS: -- ASM_VOLATILE_ROUND(fs, floor.l.s) -+ ASM_VOLATILE_UNARY64(floor.l.s) - break; - case FLOORLD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, floor.l.d) -+ ASM_VOLATILE_UNARY64(floor.l.d) - break; - case ROUNDLS: -- ASM_VOLATILE_ROUND(fs, round.l.s) -+ ASM_VOLATILE_UNARY64(round.l.s) - break; - case ROUNDLD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, round.l.d) -+ ASM_VOLATILE_UNARY64(round.l.d) - break; - case TRUNCLS: -- ASM_VOLATILE_ROUND(fs, trunc.l.s) -+ ASM_VOLATILE_UNARY64(trunc.l.s) - break; - case TRUNCLD: -- ASM_VOLATILE_ROUND_DOUBLE(fs, trunc.l.d) -+ ASM_VOLATILE_UNARY64(trunc.l.d) - break; - #endif -+ case ADDS: -+ ASM_VOLATILE_BINARY64(add.s) -+ break; -+ case ADDD: -+ ASM_VOLATILE_BINARY64(add.d) -+ break; -+ case SUBS: -+ ASM_VOLATILE_BINARY64(sub.s) -+ break; -+ case SUBD: -+ ASM_VOLATILE_BINARY64(sub.d) -+ break; -+ case DIVS: -+ ASM_VOLATILE_BINARY64(div.s) -+ break; - default: - vassert(0); - break; -Index: priv/guest_mips_toIR.c -=================================================================== ---- priv/guest_mips_toIR.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_mips_toIR.c (.../trunk) (revision 2863) -@@ -72,6 +72,9 @@ - disInstr_MIPS below. */ - static Bool mode64 = False; - -+/* CPU has FPU and 32 dbl. prec. FP registers. */ -+static Bool fp_mode64 = False; -+ - /* Define 1.0 in single and double precision. */ - #define ONE_SINGLE 0x3F800000 - #define ONE_DOUBLE 0x3FF0000000000000ULL -@@ -466,6 +469,13 @@ - assign(t1, binop(Iop_Add64, getIReg(rs), \ - mkU64(extend_s_16to64(imm)))); \ - -+#define LOADX_STORE_PATTERN \ -+ t1 = newTemp(mode64 ? Ity_I64 : Ity_I32); \ -+ if(!mode64) \ -+ assign(t1, binop(Iop_Add32, getIReg(regRs), getIReg(regRt))); \ -+ else \ -+ assign(t1, binop(Iop_Add64, getIReg(regRs), getIReg(regRt))); -+ - #define LWX_SWX_PATTERN64 \ - t2 = newTemp(Ity_I64); \ - assign(t2, binop(Iop_And64, mkexpr(t1), mkU64(0xFFFFFFFFFFFFFFFCULL))); \ -@@ -534,6 +544,11 @@ - binop(Iop_Shr32, getFCSR(), mkU8(24+cc))), \ - mkU32(0x1))); - -+#define ILLEGAL_INSTRUCTON \ -+ putPC(mkU32(guest_PC_curr_instr + 4)); \ -+ dres.jk_StopHere = Ijk_SigILL; \ -+ dres.whatNext = Dis_StopHere; -+ - /*------------------------------------------------------------*/ - /*--- Field helpers ---*/ - /*------------------------------------------------------------*/ -@@ -1090,38 +1105,84 @@ - - /* fs - fpu source register number. - inst - fpu instruction that needs to be executed. -- sz32 - size of source register. */ --static void calculateFCSR(UInt fs, UInt inst, Bool sz32) -+ sz32 - size of source register. -+ opN - number of operads: -+ 1 - unary operation. -+ 2 - binary operation. */ -+static void calculateFCSR(UInt fs, UInt ft, UInt inst, Bool sz32, UInt opN) - { - IRDirty *d; - IRTemp fcsr = newTemp(Ity_I32); -- /* IRExpr_BBPTR() => Need to pass pointer to guest -- state to helper. */ -- d = unsafeIRDirty_1_N(fcsr, 0, -- "mips_dirtyhelper_calculate_FCSR", -- &mips_dirtyhelper_calculate_FCSR, -- mkIRExprVec_3(IRExpr_BBPTR(), -- mkU32(fs), -- mkU32(inst))); -- -- /* Declare we're reading guest state. */ -- if (!mode64 && !sz32) -- d->nFxState = 2; -+ /* IRExpr_BBPTR() => Need to pass pointer to guest state to helper. */ -+ if (fp_mode64) -+ d = unsafeIRDirty_1_N(fcsr, 0, -+ "mips_dirtyhelper_calculate_FCSR_fp64", -+ &mips_dirtyhelper_calculate_FCSR_fp64, -+ mkIRExprVec_4(IRExpr_BBPTR(), -+ mkU32(fs), -+ mkU32(ft), -+ mkU32(inst))); - else -- d->nFxState = 1; -- vex_bzero(&d->fxState, sizeof(d->fxState)); -+ d = unsafeIRDirty_1_N(fcsr, 0, -+ "mips_dirtyhelper_calculate_FCSR_fp32", -+ &mips_dirtyhelper_calculate_FCSR_fp32, -+ mkIRExprVec_4(IRExpr_BBPTR(), -+ mkU32(fs), -+ mkU32(ft), -+ mkU32(inst))); - -- d->fxState[0].fx = Ifx_Read; /* read */ -- d->fxState[0].offset = floatGuestRegOffset(fs); -- if (mode64) -- d->fxState[0].size = sizeof(ULong); -- else -+ if (opN == 1) { /* Unary operation. */ -+ /* Declare we're reading guest state. */ -+ if (sz32 || fp_mode64) -+ d->nFxState = 2; -+ else -+ d->nFxState = 3; -+ vex_bzero(&d->fxState, sizeof(d->fxState)); -+ -+ d->fxState[0].fx = Ifx_Read; /* read */ -+ if (mode64) -+ d->fxState[0].offset = offsetof(VexGuestMIPS64State, guest_FCSR); -+ else -+ d->fxState[0].offset = offsetof(VexGuestMIPS32State, guest_FCSR); - d->fxState[0].size = sizeof(UInt); -+ d->fxState[1].fx = Ifx_Read; /* read */ -+ d->fxState[1].offset = floatGuestRegOffset(fs); -+ d->fxState[1].size = sizeof(ULong); - -- if (!mode64 && !sz32) { -+ if (!(sz32 || fp_mode64)) { -+ d->fxState[2].fx = Ifx_Read; /* read */ -+ d->fxState[2].offset = floatGuestRegOffset(fs+1); -+ d->fxState[2].size = sizeof(ULong); -+ } -+ } else if (opN == 2) { /* Binary operation. */ -+ /* Declare we're reading guest state. */ -+ if (sz32 || fp_mode64) -+ d->nFxState = 3; -+ else -+ d->nFxState = 5; -+ vex_bzero(&d->fxState, sizeof(d->fxState)); -+ -+ d->fxState[0].fx = Ifx_Read; /* read */ -+ if (mode64) -+ d->fxState[0].offset = offsetof(VexGuestMIPS64State, guest_FCSR); -+ else -+ d->fxState[0].offset = offsetof(VexGuestMIPS32State, guest_FCSR); -+ d->fxState[0].size = sizeof(UInt); - d->fxState[1].fx = Ifx_Read; /* read */ -- d->fxState[1].offset = floatGuestRegOffset(fs+1); -- d->fxState[1].size = sizeof(UInt); -+ d->fxState[1].offset = floatGuestRegOffset(fs); -+ d->fxState[1].size = sizeof(ULong); -+ d->fxState[2].fx = Ifx_Read; /* read */ -+ d->fxState[2].offset = floatGuestRegOffset(ft); -+ d->fxState[2].size = sizeof(ULong); -+ -+ if (!(sz32 || fp_mode64)) { -+ d->fxState[3].fx = Ifx_Read; /* read */ -+ d->fxState[3].offset = floatGuestRegOffset(fs+1); -+ d->fxState[3].size = sizeof(ULong); -+ d->fxState[4].fx = Ifx_Read; /* read */ -+ d->fxState[4].offset = floatGuestRegOffset(ft+1); -+ d->fxState[4].size = sizeof(ULong); -+ } - } - - stmt(IRStmt_Dirty(d)); -@@ -1146,6 +1207,12 @@ - stmt(IRStmt_Put(integerGuestRegOffset(archreg), e)); - } - -+static IRExpr *mkNarrowTo32(IRType ty, IRExpr * src) -+{ -+ vassert(ty == Ity_I32 || ty == Ity_I64); -+ return ty == Ity_I64 ? unop(Iop_64to32, src) : src; -+} -+ - static void putLO(IRExpr * e) - { - if (mode64) { -@@ -1239,12 +1306,6 @@ - return 0; - } - --static IRExpr *mkNarrowTo32(IRType ty, IRExpr * src) --{ -- vassert(ty == Ity_I32 || ty == Ity_I64); -- return ty == Ity_I64 ? unop(Iop_64to32, src) : src; --} -- - static IRExpr *getLoFromF64(IRType ty, IRExpr * src) - { - vassert(ty == Ity_F32 || ty == Ity_F64); -@@ -1340,21 +1401,21 @@ - (UInt) branch_offset), OFFB_PC); - } - --static IRExpr *getFReg(UInt dregNo) -+static IRExpr *getFReg(UInt fregNo) - { -- vassert(dregNo < 32); -- IRType ty = mode64 ? Ity_F64 : Ity_F32; -- return IRExpr_Get(floatGuestRegOffset(dregNo), ty); -+ vassert(fregNo < 32); -+ IRType ty = fp_mode64 ? Ity_F64 : Ity_F32; -+ return IRExpr_Get(floatGuestRegOffset(fregNo), ty); - } - - static IRExpr *getDReg(UInt dregNo) - { -- if (mode64) { -- vassert(dregNo < 32); -- IRType ty = Ity_F64; -- return IRExpr_Get(floatGuestRegOffset(dregNo), ty); -+ vassert(dregNo < 32); -+ if (fp_mode64) { -+ return IRExpr_Get(floatGuestRegOffset(dregNo), Ity_F64); - } else { -- vassert(dregNo < 32); -+ /* Read a floating point register pair and combine their contents into a -+ 64-bit value */ - IRTemp t0 = newTemp(Ity_F32); - IRTemp t1 = newTemp(Ity_F32); - IRTemp t2 = newTemp(Ity_F64); -@@ -1377,7 +1438,7 @@ - static void putFReg(UInt dregNo, IRExpr * e) - { - vassert(dregNo < 32); -- IRType ty = mode64 ? Ity_F64 : Ity_F32; -+ IRType ty = fp_mode64 ? Ity_F64 : Ity_F32; - vassert(typeOfIRExpr(irsb->tyenv, e) == ty); - stmt(IRStmt_Put(floatGuestRegOffset(dregNo), e)); - } -@@ -1384,7 +1445,7 @@ - - static void putDReg(UInt dregNo, IRExpr * e) - { -- if (mode64) { -+ if (fp_mode64) { - vassert(dregNo < 32); - IRType ty = Ity_F64; - vassert(typeOfIRExpr(irsb->tyenv, e) == ty); -@@ -1642,22 +1703,22 @@ - static const HChar* showCondCode(UInt code) { - const HChar* ret; - switch (code) { -- case 0: ret = "F"; break; -- case 1: ret = "UN"; break; -- case 2: ret = "EQ"; break; -- case 3: ret = "UEQ"; break; -- case 4: ret = "OLT"; break; -- case 5: ret = "ULT"; break; -- case 6: ret = "OLE"; break; -- case 7: ret = "ULE"; break; -- case 8: ret = "SF"; break; -- case 9: ret = "NGLE"; break; -- case 10: ret = "SEQ"; break; -- case 11: ret = "NGL"; break; -- case 12: ret = "LT"; break; -- case 13: ret = "NGE"; break; -- case 14: ret = "LE"; break; -- case 15: ret = "NGT"; break; -+ case 0: ret = "f"; break; -+ case 1: ret = "un"; break; -+ case 2: ret = "eq"; break; -+ case 3: ret = "ueq"; break; -+ case 4: ret = "olt"; break; -+ case 5: ret = "ult"; break; -+ case 6: ret = "ole"; break; -+ case 7: ret = "ule"; break; -+ case 8: ret = "sf"; break; -+ case 9: ret = "ngle"; break; -+ case 10: ret = "seq"; break; -+ case 11: ret = "ngl"; break; -+ case 12: ret = "lt"; break; -+ case 13: ret = "nge"; break; -+ case 14: ret = "le"; break; -+ case 15: ret = "ngt"; break; - default: vpanic("showCondCode"); break; - } - return ret; -@@ -1678,8 +1739,8 @@ - UInt fpc_cc = get_fpc_cc(cins); - switch (fmt) { - case 0x10: { /* C.cond.S */ -- DIP("C.%s.S %d, f%d, f%d", showCondCode(cond), fpc_cc, fs, ft); -- if (mode64) { -+ DIP("c.%s.s %d, f%d, f%d", showCondCode(cond), fpc_cc, fs, ft); -+ if (fp_mode64) { - t0 = newTemp(Ity_I32); - t1 = newTemp(Ity_I32); - t2 = newTemp(Ity_I32); -@@ -1694,7 +1755,8 @@ - getFReg(ft)))); - - assign(ccIR, binop(Iop_CmpF64, mkexpr(tmp5), mkexpr(tmp6))); -- putHI(mkWidenFrom32(Ity_I64, mkexpr(ccIR), True)); -+ putHI(mkWidenFrom32(mode64 ? Ity_I64: Ity_I32, -+ mkexpr(ccIR), True)); - /* Map compare result from IR to MIPS - FP cmp result | MIPS | IR - -------------------------- -@@ -1711,7 +1773,8 @@ - binop(Iop_And32, binop(Iop_Xor32, mkexpr(ccIR), - binop(Iop_Shr32, mkexpr(ccIR), mkU8(6))), - mkU32(1)))))); -- putLO(mkWidenFrom32(Ity_I64, mkexpr(ccMIPS), True)); -+ putLO(mkWidenFrom32(mode64 ? Ity_I64: Ity_I32, -+ mkexpr(ccMIPS), True)); - - /* UN */ - assign(t0, binop(Iop_And32, mkexpr(ccMIPS), mkU32(0x1))); -@@ -1885,7 +1948,7 @@ - break; - - case 0x11: { /* C.cond.D */ -- DIP("C.%s.D %d, f%d, f%d", showCondCode(cond), fpc_cc, fs, ft); -+ DIP("c.%s.d %d, f%d, f%d", showCondCode(cond), fpc_cc, fs, ft); - t0 = newTemp(Ity_I32); - t1 = newTemp(Ity_I32); - t2 = newTemp(Ity_I32); -@@ -2110,6 +2173,7 @@ - static Bool dis_instr_CVM ( UInt theInstr ) - { - UChar opc2 = get_function(theInstr); -+ UChar opc1 = get_opcode(theInstr); - UChar regRs = get_rs(theInstr); - UChar regRt = get_rt(theInstr); - UChar regRd = get_rd(theInstr); -@@ -2120,99 +2184,184 @@ - IRTemp tmp = newTemp(ty); - IRTemp tmpRs = newTemp(ty); - IRTemp tmpRt = newTemp(ty); -+ IRTemp t1 = newTemp(ty); - UInt size; - assign(tmpRs, getIReg(regRs)); - -- switch(opc2) { -- case 0x03: { /* DMUL rd, rs, rt */ -- DIP("dmul r%d, r%d, r%d", regRd, regRs, regRt); -- IRType t0 = newTemp(Ity_I128); -- assign(t0, binop(Iop_MullU64, getIReg(regRs), getIReg(regRt))); -- putIReg(regRd, unop(Iop_128to64, mkexpr(t0))); -- break; -- } -- case 0x32: /* 5. CINS rd, rs, p, lenm1 */ -- DIP("cins r%u, r%u, %d, %d\n", regRt, regRs, p, lenM1); -- assign ( tmp , binop(Iop_Shl64, mkexpr(tmpRs), mkU8(64-( lenM1+1 )))); -- assign ( tmpRt, binop(Iop_Shr64, mkexpr( tmp ), mkU8(64-(p+lenM1+1)))); -- putIReg( regRt, mkexpr(tmpRt)); -- break; -+ switch(opc1){ -+ case 0x1C: { -+ switch(opc2) { -+ case 0x03: { /* DMUL rd, rs, rt */ -+ DIP("dmul r%d, r%d, r%d", regRd, regRs, regRt); -+ IRType t0 = newTemp(Ity_I128); -+ assign(t0, binop(Iop_MullU64, getIReg(regRs), getIReg(regRt))); -+ putIReg(regRd, unop(Iop_128to64, mkexpr(t0))); -+ break; -+ } - -- case 0x33: /* 6. CINS32 rd, rs, p+32, lenm1 */ -- DIP("cins32 r%u, r%u, %d, %d\n", regRt, regRs, p+32, lenM1); -- assign ( tmp , binop(Iop_Shl64, mkexpr(tmpRs), mkU8(64-( lenM1+1 )))); -- assign ( tmpRt, binop(Iop_Shr64, mkexpr( tmp ), mkU8(32-(p+lenM1+1)))); -- putIReg( regRt, mkexpr(tmpRt)); -- break; -+ case 0x32: /* 5. CINS rd, rs, p, lenm1 */ -+ DIP("cins r%u, r%u, %d, %d\n", regRt, regRs, p, lenM1); -+ assign ( tmp , binop(Iop_Shl64, mkexpr(tmpRs), -+ mkU8(64-( lenM1+1 )))); -+ assign ( tmpRt, binop(Iop_Shr64, mkexpr( tmp ), -+ mkU8(64-(p+lenM1+1)))); -+ putIReg( regRt, mkexpr(tmpRt)); -+ break; - -- case 0x3A: /* 3. EXTS rt, rs, p len */ -- DIP("exts r%u, r%u, %d, %d\n", regRt, regRs, p, lenM1); -- size = lenM1 + 1; /* lenm1+1 */ -- UChar lsAmt = 64 - (p + size); /* p+lenm1+1 */ -- UChar rsAmt = 64 - size; /* lenm1+1 */ -- tmp = newTemp(Ity_I64); -- assign(tmp, binop(Iop_Shl64, mkexpr(tmpRs), mkU8(lsAmt))); -- putIReg(regRt, binop(Iop_Sar64, mkexpr(tmp), mkU8(rsAmt))); -- break; -+ case 0x33: /* 6. CINS32 rd, rs, p+32, lenm1 */ -+ DIP("cins32 r%u, r%u, %d, %d\n", regRt, regRs, p+32, lenM1); -+ assign ( tmp , binop(Iop_Shl64, mkexpr(tmpRs), -+ mkU8(64-( lenM1+1 )))); -+ assign ( tmpRt, binop(Iop_Shr64, mkexpr( tmp ), -+ mkU8(32-(p+lenM1+1)))); -+ putIReg( regRt, mkexpr(tmpRt)); -+ break; - -- case 0x3B: /* 4. EXTS32 rt, rs, p len */ -- DIP("exts32 r%u, r%u, %d, %d\n", regRt, regRs, p, lenM1); -- assign ( tmp , binop(Iop_Shl64, mkexpr(tmpRs), mkU8(32-(p+lenM1+1)))); -- assign ( tmpRt, binop(Iop_Sar64, mkexpr(tmp) , mkU8(64-(lenM1+1))) ); -- putIReg( regRt, mkexpr(tmpRt)); -- break; -+ case 0x3A: /* 3. EXTS rt, rs, p len */ -+ DIP("exts r%u, r%u, %d, %d\n", regRt, regRs, p, lenM1); -+ size = lenM1 + 1; /* lenm1+1 */ -+ UChar lsAmt = 64 - (p + size); /* p+lenm1+1 */ -+ UChar rsAmt = 64 - size; /* lenm1+1 */ -+ tmp = newTemp(Ity_I64); -+ assign(tmp, binop(Iop_Shl64, mkexpr(tmpRs), mkU8(lsAmt))); -+ putIReg(regRt, binop(Iop_Sar64, mkexpr(tmp), mkU8(rsAmt))); -+ break; - -- case 0x2B: /* 20. SNE rd, rs, rt */ -- DIP("sne r%d, r%d, r%d", regRd,regRs, regRt); -- if (mode64) -- putIReg(regRd, unop(Iop_1Uto64, binop(Iop_CmpNE64, getIReg(regRs), -- getIReg(regRt)))); -- else -- putIReg(regRd,unop(Iop_1Uto32, binop(Iop_CmpNE32, getIReg(regRs), -- getIReg(regRt)))); -- break; -+ case 0x3B: /* 4. EXTS32 rt, rs, p len */ -+ DIP("exts32 r%u, r%u, %d, %d\n", regRt, regRs, p, lenM1); -+ assign ( tmp , binop(Iop_Shl64, mkexpr(tmpRs), -+ mkU8(32-(p+lenM1+1)))); -+ assign ( tmpRt, binop(Iop_Sar64, mkexpr(tmp), -+ mkU8(64-(lenM1+1))) ); -+ putIReg( regRt, mkexpr(tmpRt)); -+ break; - -- case 0x2A: /* Set Equals - SEQ; Cavium OCTEON */ -- DIP("seq r%d, r%d, %d", regRd, regRs, regRt); -- if (mode64) -- putIReg(regRd, unop(Iop_1Uto64, -- binop(Iop_CmpEQ64, getIReg(regRs), -- getIReg(regRt)))); -- else -- putIReg(regRd, unop(Iop_1Uto32, -- binop(Iop_CmpEQ32, getIReg(regRs), -- getIReg(regRt)))); -- break; -+ case 0x2B: /* 20. SNE rd, rs, rt */ -+ DIP("sne r%d, r%d, r%d", regRd,regRs, regRt); -+ if (mode64) -+ putIReg(regRd, unop(Iop_1Uto64, binop(Iop_CmpNE64, -+ getIReg(regRs), -+ getIReg(regRt)))); -+ else -+ putIReg(regRd,unop(Iop_1Uto32, binop(Iop_CmpNE32, -+ getIReg(regRs), -+ getIReg(regRt)))); -+ break; - -- case 0x2E: /* Set Equals Immediate - SEQI; Cavium OCTEON */ -- DIP("seqi r%d, r%d, %d", regRt, regRs, imm); -- if (mode64) -- putIReg(regRt, unop(Iop_1Uto64, -- binop(Iop_CmpEQ64, getIReg(regRs), -- mkU64(extend_s_10to64(imm))))); -- else -- putIReg(regRt, unop(Iop_1Uto32, -- binop(Iop_CmpEQ32, getIReg(regRs), -- mkU32(extend_s_10to32(imm))))); -- break; -+ case 0x2A: /* Set Equals - SEQ; Cavium OCTEON */ -+ DIP("seq r%d, r%d, %d", regRd, regRs, regRt); -+ if (mode64) -+ putIReg(regRd, unop(Iop_1Uto64, -+ binop(Iop_CmpEQ64, getIReg(regRs), -+ getIReg(regRt)))); -+ else -+ putIReg(regRd, unop(Iop_1Uto32, -+ binop(Iop_CmpEQ32, getIReg(regRs), -+ getIReg(regRt)))); -+ break; - -- case 0x2F: /* Set Not Equals Immediate - SNEI; Cavium OCTEON */ -- DIP("snei r%d, r%d, %d", regRt, regRs, imm); -- if (mode64) -- putIReg(regRt, unop(Iop_1Uto64, -- binop(Iop_CmpNE64, -- getIReg(regRs), -- mkU64(extend_s_10to64(imm))))); -- else -- putIReg(regRt, unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- getIReg(regRs), -- mkU32(extend_s_10to32(imm))))); -+ case 0x2E: /* Set Equals Immediate - SEQI; Cavium OCTEON */ -+ DIP("seqi r%d, r%d, %d", regRt, regRs, imm); -+ if (mode64) -+ putIReg(regRt, unop(Iop_1Uto64, -+ binop(Iop_CmpEQ64, getIReg(regRs), -+ mkU64(extend_s_10to64(imm))))); -+ else -+ putIReg(regRt, unop(Iop_1Uto32, -+ binop(Iop_CmpEQ32, getIReg(regRs), -+ mkU32(extend_s_10to32(imm))))); -+ break; -+ -+ case 0x2F: /* Set Not Equals Immediate - SNEI; Cavium OCTEON */ -+ DIP("snei r%d, r%d, %d", regRt, regRs, imm); -+ if (mode64) -+ putIReg(regRt, unop(Iop_1Uto64, -+ binop(Iop_CmpNE64, -+ getIReg(regRs), -+ mkU64(extend_s_10to64(imm))))); -+ else -+ putIReg(regRt, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ getIReg(regRs), -+ mkU32(extend_s_10to32(imm))))); -+ break; -+ -+ default: -+ return False; -+ } - break; -- -+ } /* opc1 0x1C ends here*/ -+ case 0x1F:{ -+ switch(opc2) { -+ case 0x0A: { // lx - Load indexed instructions -+ switch (get_sa(theInstr)) { -+ case 0x00: { // LWX rd, index(base) -+ DIP("lwx r%d, r%d(r%d)", regRd, regRt, regRs); -+ LOADX_STORE_PATTERN; -+ putIReg(regRd, mkWidenFrom32(ty, load(Ity_I32, mkexpr(t1)), -+ True)); -+ break; -+ } -+ case 0x08: { // LDX rd, index(base) -+ DIP("ldx r%d, r%d(r%d)", regRd, regRt, regRs); -+ vassert(mode64); /* Currently Implemented only for n64 */ -+ LOADX_STORE_PATTERN; -+ putIReg(regRd, load(Ity_I64, mkexpr(t1))); -+ break; -+ } -+ case 0x06: { // LBUX rd, index(base) -+ DIP("lbux r%d, r%d(r%d)", regRd, regRt, regRs); -+ LOADX_STORE_PATTERN; -+ if (mode64) -+ putIReg(regRd, unop(Iop_8Uto64, load(Ity_I8, -+ mkexpr(t1)))); -+ else -+ putIReg(regRd, unop(Iop_8Uto32, load(Ity_I8, -+ mkexpr(t1)))); -+ break; -+ } -+ case 0x10: { // LWUX rd, index(base) (Cavium OCTEON) -+ DIP("lwux r%d, r%d(r%d)", regRd, regRt, regRs); -+ LOADX_STORE_PATTERN; /* same for both 32 and 64 modes*/ -+ putIReg(regRd, mkWidenFrom32(ty, load(Ity_I32, mkexpr(t1)), -+ False)); -+ break; -+ } -+ case 0x14: { // LHUX rd, index(base) (Cavium OCTEON) -+ DIP("lhux r%d, r%d(r%d)", regRd, regRt, regRs); -+ LOADX_STORE_PATTERN; -+ if (mode64) -+ putIReg(regRd, -+ unop(Iop_16Uto64, load(Ity_I16, mkexpr(t1)))); -+ else -+ putIReg(regRd, -+ unop(Iop_16Uto32, load(Ity_I16, mkexpr(t1)))); -+ break; -+ } -+ case 0x16: { // LBX rd, index(base) (Cavium OCTEON) -+ DIP("lbx r%d, r%d(r%d)", regRd, regRs, regRt); -+ LOADX_STORE_PATTERN; -+ if (mode64) -+ putIReg(regRd, -+ unop(Iop_8Sto64, load(Ity_I8, mkexpr(t1)))); -+ else -+ putIReg(regRd, -+ unop(Iop_8Sto32, load(Ity_I8, mkexpr(t1)))); -+ break; -+ } -+ default: -+ vex_printf("\nUnhandled LX instruction opc3 = %x\n", -+ get_sa(theInstr)); -+ return False; -+ } -+ break; -+ } -+ } /* opc1 = 0x1F & opc2 = 0xA (LX) ends here*/ -+ break; -+ } /* opc1 = 0x1F ends here*/ - default: -- return False; -- } -+ return False; -+ } /* main opc1 switch ends here */ - return True; - } - -@@ -2223,7 +2372,7 @@ - static UInt disDSPInstr_MIPS_WRK ( UInt cins ) - { - IRTemp t0, t1 = 0, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, -- t15, t16, t17, t18; -+ t15, t16, t17; - UInt opcode, rs, rt, rd, sa, function, ac, ac_mfhilo, rddsp_mask, - wrdsp_mask, dsp_imm, shift; - -@@ -2875,40 +3024,123 @@ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I32); -- t3 = newTemp(Ity_I32); -- t4 = newTemp(Ity_I32); -+ t3 = newTemp(Ity_I1); -+ t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I1); -+ t7 = newTemp(Ity_I32); -+ t8 = newTemp(Ity_I64); -+ t9 = newTemp(Ity_I64); -+ t10 = newTemp(Ity_I1); -+ t11 = newTemp(Ity_I1); -+ t12 = newTemp(Ity_I1); -+ t13 = newTemp(Ity_I1); -+ t14 = newTemp(Ity_I32); - - assign(t0, getAcc(ac)); -- assign(t1, binop(Iop_Sar64, mkexpr(t0), mkU8(rs))); -- putIReg(rt, unop(Iop_64to32, mkexpr(t1))); -+ if (0 == rs) { -+ assign(t1, mkexpr(t0)); -+ } else { -+ assign(t1, binop(Iop_Sar64, mkexpr(t0), mkU8(rs))); -+ } -+ /* Check if bits 63..31 of the result in t1 aren't 0. */ -+ assign(t3, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0))); -+ assign(t4, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ /* Check if bits 63..31 of the result in t1 aren't -+ 0x1ffffffff. */ -+ assign(t5, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0xffffffff))); -+ assign(t6, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP -+ control register. */ -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t3)), -+ unop(Iop_1Sto32, mkexpr(t4))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t5)), -+ unop(Iop_1Sto32, mkexpr(t6))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t7), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - -- assign(t2, binop(Iop_Or32, -- getDSPControl(), mkU32(0x00800000))); -+ /* If the last discarded bit is 1, there would be carry -+ when rounding, otherwise there wouldn't. We use that -+ fact and just add the value of the last discarded bit -+ to the least sifgnificant bit of the shifted value -+ from acc. */ -+ if (0 == rs) { -+ assign(t8, mkU64(0x0ULL)); -+ } else { -+ assign(t8, binop(Iop_And64, -+ binop(Iop_Shr64, -+ mkexpr(t0), -+ mkU8(rs-1)), -+ mkU64(0x1ULL))); -+ } -+ assign(t9, binop(Iop_Add64, mkexpr(t1), mkexpr(t8))); - -- /* Check if signOut == signIn */ -- assign(t3, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t0)), -- mkU32(0x80000000)), -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x80000000))), -- getDSPControl(), -- mkexpr(t2))); -+ /* Repeat previous steps for the rounded value. */ -+ assign(t10, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0))); -+ assign(t11, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0))); - -- assign(t4, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0xffffffff)), -- mkexpr(t2), -- mkexpr(t3)), -- mkexpr(t3))); -- putDSPControl(mkexpr(t4)); -+ assign(t12, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0xffffffff))); -+ assign(t13, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ -+ assign(t14, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t10)), -+ unop(Iop_1Sto32, mkexpr(t11))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t12)), -+ unop(Iop_1Sto32, mkexpr(t13))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t14), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); -+ if (0 == rs) { -+ putIReg(rt, unop(Iop_64to32, mkexpr(t0))); -+ } else { -+ putIReg(rt, unop(Iop_64to32, mkexpr(t1))); -+ } - break; - } - case 0x1: { /* EXTRV.W */ -@@ -2917,43 +3149,133 @@ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I32); -- t3 = newTemp(Ity_I32); -+ t3 = newTemp(Ity_I1); - t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I1); -+ t7 = newTemp(Ity_I32); -+ t8 = newTemp(Ity_I64); -+ t9 = newTemp(Ity_I64); -+ t10 = newTemp(Ity_I1); -+ t11 = newTemp(Ity_I1); -+ t12 = newTemp(Ity_I1); -+ t13 = newTemp(Ity_I1); -+ t14 = newTemp(Ity_I32); -+ t15 = newTemp(Ity_I8); - -+ assign(t15, unop(Iop_32to8, -+ binop(Iop_And32, -+ getIReg(rs), -+ mkU32(0x1f)))); - assign(t0, getAcc(ac)); -- assign(t1, binop(Iop_Sar64, -- mkexpr(t0), -- unop(Iop_32to8, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f))))); -- putIReg(rt, unop(Iop_64to32, mkexpr(t1))); -+ assign(t1, binop(Iop_Sar64, mkexpr(t0), mkexpr(t15))); -+ putIReg(rt, IRExpr_ITE(binop(Iop_CmpEQ32, -+ unop(Iop_8Uto32, -+ mkexpr(t15)), -+ mkU32(0)), -+ unop(Iop_64to32, mkexpr(t0)), -+ unop(Iop_64to32, mkexpr(t1)))); - -- assign(t2, binop(Iop_Or32, -- getDSPControl(), mkU32(0x00800000))); -- -- /* Check if signOut == signIn */ -- assign(t3, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t0)), -- mkU32(0x80000000)), -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x80000000))), -- getDSPControl(), -- mkexpr(t2))); -+ /* Check if bits 63..31 of the result in t1 aren't 0. */ -+ assign(t3, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0))); - assign(t4, binop(Iop_CmpNE32, -- unop(Iop_64HIto32, mkexpr(t1)), -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ /* Check if bits 63..31 of the result in t1 aren't -+ 0x1ffffffff. */ -+ assign(t5, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), - mkU32(0xffffffff))); -+ assign(t6, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP -+ control register. */ -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t3)), -+ unop(Iop_1Sto32, mkexpr(t4))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t5)), -+ unop(Iop_1Sto32, mkexpr(t6))))); - putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0x0)), -- IRExpr_ITE(mkexpr(t4), -- mkexpr(t2), -- mkexpr(t3)), -- mkexpr(t3))); -+ mkexpr(t7), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); -+ -+ /* If the last discarded bit is 1, there would be carry -+ when rounding, otherwise there wouldn't. We use that -+ fact and just add the value of the last discarded bit -+ to the least sifgnificant bit of the shifted value -+ from acc. */ -+ assign(t8, -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ unop(Iop_8Uto32, -+ mkexpr(t15)), -+ mkU32(0)), -+ mkU64(0x0ULL), -+ binop(Iop_And64, -+ binop(Iop_Shr64, -+ mkexpr(t0), -+ unop(Iop_32to8, -+ binop(Iop_Sub32, -+ unop(Iop_8Uto32, -+ mkexpr(t15)), -+ mkU32(1)))), -+ mkU64(0x1ULL)))); -+ -+ assign(t9, binop(Iop_Add64, mkexpr(t1), mkexpr(t8))); -+ -+ /* Repeat previous steps for the rounded value. */ -+ assign(t10, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0))); -+ assign(t11, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ -+ assign(t12, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0xffffffff))); -+ assign(t13, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ -+ assign(t14, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t10)), -+ unop(Iop_1Sto32, mkexpr(t11))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t12)), -+ unop(Iop_1Sto32, mkexpr(t13))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t14), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - break; - } - case 0x2: { /* EXTP */ -@@ -3140,61 +3462,131 @@ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I32); -- t4 = newTemp(Ity_I32); -- t5 = newTemp(Ity_I64); -- t6 = newTemp(Ity_I64); -+ t3 = newTemp(Ity_I1); -+ t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I1); -+ t7 = newTemp(Ity_I32); -+ t8 = newTemp(Ity_I64); -+ t9 = newTemp(Ity_I64); -+ t10 = newTemp(Ity_I1); -+ t11 = newTemp(Ity_I1); -+ t12 = newTemp(Ity_I1); -+ t13 = newTemp(Ity_I1); -+ t14 = newTemp(Ity_I32); -+ t15 = newTemp(Ity_I64); -+ t16 = newTemp(Ity_I1); - - assign(t0, getAcc(ac)); -- if (0 == rs) { -- putIReg(rt, unop(Iop_64to32, mkexpr(t0))); -- } else { -- assign(t1, binop(Iop_Sar64, mkexpr(t0), mkU8(rs))); -+ assign(t16, binop(Iop_CmpEQ32, -+ mkU32(rs), -+ mkU32(0))); -+ assign(t1, IRExpr_ITE(mkexpr(t16), -+ mkexpr(t0), -+ binop(Iop_Sar64, -+ mkexpr(t0), -+ mkU8(rs)))); -+ /* If the last discarded bit is 1, there would be carry -+ when rounding, otherwise there wouldn't. We use that -+ fact and just add the value of the last discarded bit -+ to the least significant bit of the shifted value -+ from acc. */ -+ assign(t15, binop(Iop_Shr64, -+ mkexpr(t0), -+ unop(Iop_32to8, -+ binop(Iop_Sub32, -+ binop(Iop_And32, -+ mkU32(rs), -+ mkU32(0x1f)), -+ mkU32(1))))); - -- assign(t2, binop(Iop_Or32, -- getDSPControl(), mkU32(0x800000))); -+ assign(t8, -+ IRExpr_ITE(mkexpr(t16), -+ mkU64(0x0ULL), -+ binop(Iop_And64, -+ mkexpr(t15), -+ mkU64(0x0000000000000001ULL)))); -+ assign(t9, binop(Iop_Add64, mkexpr(t1), mkexpr(t8))); -+ putIReg(rt, unop(Iop_64to32, mkexpr(t9))); - -- putDSPControl(IRExpr_ITE( -- binop(Iop_CmpNE32, -- unop(Iop_64HIto32, mkexpr(t1)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0xffffffff)), -- mkexpr(t2), -- getDSPControl()), -- getDSPControl())); -+ /* Check if bits 63..31 of the result in t1 aren't 0. */ -+ assign(t3, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0))); -+ assign(t4, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0))); - -- assign(t4, binop(Iop_Or32, -- getDSPControl(), mkU32(0x800000))); -- /* If the last discarded bit is 1, there would be carry -- when rounding, otherwise there wouldn't. We use that -- fact and just add the value of the last discarded bit -- to the least sifgnificant bit of the shifted value -- from acc. */ -- assign(t5, binop(Iop_Shr64, -- binop(Iop_And64, -- mkexpr(t0), -- binop(Iop_Shl64, -- mkU64(0x1ULL), -- mkU8(rs-1))), -- mkU8(rs-1))); -+ /* Check if bits 63..31 of the result in t1 aren't -+ 0x1ffffffff. */ -+ assign(t5, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0xffffffff))); -+ assign(t6, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP -+ control register. */ -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t3)), -+ unop(Iop_1Sto32, mkexpr(t4))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t5)), -+ unop(Iop_1Sto32, mkexpr(t6))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t7), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - -- assign(t6, binop(Iop_Add64, mkexpr(t1), mkexpr(t5))); -+ /* Repeat previous steps for the rounded value. */ -+ assign(t10, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0))); -+ assign(t11, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0))); - -- putDSPControl(IRExpr_ITE( -- binop(Iop_CmpNE32, -- unop(Iop_64HIto32, mkexpr(t6)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0xffffffff)), -- mkexpr(t4), -- getDSPControl()), -- getDSPControl())); -- putIReg(rt, unop(Iop_64to32, mkexpr(t6))); -- } -+ assign(t12, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0xffffffff))); -+ assign(t13, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ -+ assign(t14, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t10)), -+ unop(Iop_1Sto32, mkexpr(t11))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t12)), -+ unop(Iop_1Sto32, mkexpr(t13))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t14), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - break; - } - case 0x5: { /* EXTRV_R.W */ -@@ -3203,79 +3595,129 @@ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I32); -- t4 = newTemp(Ity_I32); -- t5 = newTemp(Ity_I64); -- t6 = newTemp(Ity_I64); -+ t3 = newTemp(Ity_I1); -+ t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I1); -+ t7 = newTemp(Ity_I32); -+ t8 = newTemp(Ity_I64); -+ t9 = newTemp(Ity_I64); -+ t10 = newTemp(Ity_I1); -+ t11 = newTemp(Ity_I1); -+ t12 = newTemp(Ity_I1); -+ t13 = newTemp(Ity_I1); -+ t14 = newTemp(Ity_I32); -+ t15 = newTemp(Ity_I8); - -+ assign(t15, unop(Iop_32to8, -+ binop(Iop_And32, -+ getIReg(rs), -+ mkU32(0x1f)))); - assign(t0, getAcc(ac)); -+ assign(t1, binop(Iop_Sar64, mkexpr(t0), mkexpr(t15))); - -- assign(t1, binop(Iop_Sar64, -- mkexpr(t0), -- unop(Iop_32to8, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f))))); -+ /* Check if bits 63..31 of the result in t1 aren't 0. */ -+ assign(t3, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0))); -+ assign(t4, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ /* Check if bits 63..31 of the result in t1 aren't -+ 0x1ffffffff. */ -+ assign(t5, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0xffffffff))); -+ assign(t6, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP -+ control register. */ -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t3)), -+ unop(Iop_1Sto32, mkexpr(t4))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t5)), -+ unop(Iop_1Sto32, mkexpr(t6))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t7), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - -- assign(t2, binop(Iop_Or32, -- getDSPControl(), mkU32(0x00800000))); -- -- putDSPControl(IRExpr_ITE( -- binop(Iop_CmpNE32, -- unop(Iop_64HIto32, mkexpr(t1)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0xffffffff)), -- mkexpr(t2), -- getDSPControl()), -- getDSPControl())); -- -- assign(t4, binop(Iop_Or32, -- getDSPControl(), mkU32(0x00800000))); - /* If the last discarded bit is 1, there would be carry - when rounding, otherwise there wouldn't. We use that -- fact and just add the value of the last discarded bit to -- the least sifgnificant bit of the shifted value from -- acc. */ -- assign(t5, binop(Iop_Shr64, -- binop(Iop_And64, -- mkexpr(t0), -- binop(Iop_Shl64, -- mkU64(0x1ULL), -- unop(Iop_32to8, -- binop(Iop_Sub32, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f)), -- mkU32(0x1))))), -- unop(Iop_32to8, -- binop(Iop_Sub32, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f)), -- mkU32(0x1))))); -+ fact and just add the value of the last discarded bit -+ to the least sifgnificant bit of the shifted value -+ from acc. */ -+ assign(t8, -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ unop(Iop_8Uto32, -+ mkexpr(t15)), -+ mkU32(0)), -+ mkU64(0x0ULL), -+ binop(Iop_And64, -+ binop(Iop_Shr64, -+ mkexpr(t0), -+ unop(Iop_32to8, -+ binop(Iop_Sub32, -+ unop(Iop_8Uto32, -+ mkexpr(t15)), -+ mkU32(1)))), -+ mkU64(0x1ULL)))); - -- assign(t6, binop(Iop_Add64, mkexpr(t1), mkexpr(t5))); -+ assign(t9, binop(Iop_Add64, mkexpr(t1), mkexpr(t8))); -+ /* Put rounded value in destination register. */ -+ putIReg(rt, unop(Iop_64to32, mkexpr(t9))); - -- putDSPControl(IRExpr_ITE( -- binop(Iop_CmpNE32, -- unop(Iop_64HIto32, mkexpr(t6)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0xffffffff)), -- mkexpr(t4), -- getDSPControl()), -- getDSPControl())); -- putIReg(rt, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f)), -- mkU32(0x0)), -- unop(Iop_64to32, mkexpr(t0)), -- unop(Iop_64to32, mkexpr(t6)))); -+ /* Repeat previous steps for the rounded value. */ -+ assign(t10, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0))); -+ assign(t11, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ -+ assign(t12, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0xffffffff))); -+ assign(t13, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ -+ assign(t14, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t10)), -+ unop(Iop_1Sto32, mkexpr(t11))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t12)), -+ unop(Iop_1Sto32, mkexpr(t13))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t14), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - break; - } - case 0x6: { /* EXTR_RS.W */ -@@ -3283,81 +3725,136 @@ - vassert(!mode64); - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); -- t2 = newTemp(Ity_I64); -- t3 = newTemp(Ity_I32); -- t4 = newTemp(Ity_I32); -- t5 = newTemp(Ity_I32); -- t6 = newTemp(Ity_I32); -+ t2 = newTemp(Ity_I32); -+ t3 = newTemp(Ity_I1); -+ t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I1); -+ t7 = newTemp(Ity_I32); -+ t8 = newTemp(Ity_I64); -+ t9 = newTemp(Ity_I64); -+ t10 = newTemp(Ity_I1); -+ t11 = newTemp(Ity_I1); -+ t12 = newTemp(Ity_I1); -+ t13 = newTemp(Ity_I1); -+ t14 = newTemp(Ity_I32); -+ t16 = newTemp(Ity_I32); - -- if (0 != rs) { -- assign(t0, getAcc(ac)); -+ assign(t0, getAcc(ac)); -+ if (0 == rs) { -+ assign(t1, mkexpr(t0)); -+ } else { - assign(t1, binop(Iop_Sar64, mkexpr(t0), mkU8(rs))); -- putDSPControl(IRExpr_ITE( -- binop(Iop_CmpNE32, -- unop(Iop_64HIto32, mkexpr(t1)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0xffffffff)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x00800000)), -- getDSPControl()), -- getDSPControl())); -- /* If the last discarded bit is 1, there would be carry -- when rounding, otherwise there wouldn't. We use that -- fact and just add the value of the last discarded bit -- to the least sifgnificant bit of the shifted value -- from acc. */ -- assign(t2, binop(Iop_Add64, -- mkexpr(t1), -- binop(Iop_Shr64, -- binop(Iop_And64, -- mkexpr(t0), -- binop(Iop_Shl64, -- mkU64(0x1ULL), -- unop(Iop_32to8, -- mkU32(rs-1)))), -- unop(Iop_32to8, mkU32(rs-1))))); -- assign(t6, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t2)), -- mkU32(0xffffffff)), -+ } -+ -+ /* Check if bits 63..31 of the result in t1 aren't 0. */ -+ assign(t3, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0))); -+ assign(t4, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ /* Check if bits 63..31 of the result in t1 aren't -+ 0x1ffffffff. */ -+ assign(t5, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0xffffffff))); -+ assign(t6, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP -+ control register. */ -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t3)), -+ unop(Iop_1Sto32, mkexpr(t4))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t5)), -+ unop(Iop_1Sto32, mkexpr(t6))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t7), -+ mkU32(0)), - binop(Iop_Or32, - getDSPControl(), - mkU32(0x00800000)), - getDSPControl())); -- putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t2)), -- mkU32(0x0)), -- mkexpr(t6), -- getDSPControl())); -- assign(t3, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t2)), -- mkU32(0x80000000)), -- mkU32(0x0)), -- mkU32(0x7fffffff), -- mkU32(0x80000000))); -- assign(t4, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t2)), -- mkU32(0xffffffff)), -- mkexpr(t3), -- unop(Iop_64to32, mkexpr(t2)))); -- assign(t5, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t2)), -- mkU32(0x0)), -- mkexpr(t4), -- unop(Iop_64to32, mkexpr(t2)))); -- putIReg(rt, mkexpr(t5)); -+ -+ /* If the last discarded bit is 1, there would be carry -+ when rounding, otherwise there wouldn't. We use that -+ fact and just add the value of the last discarded bit -+ to the least sifgnificant bit of the shifted value -+ from acc. */ -+ if (0 == rs) { -+ assign(t8, mkU64(0x0ULL)); - } else { -- putIReg(rt, unop(Iop_64to32, getAcc(ac))); -+ assign(t8, binop(Iop_And64, -+ binop(Iop_Shr64, -+ mkexpr(t0), -+ mkU8(rs-1)), -+ mkU64(0x1ULL))); - } -+ -+ assign(t9, binop(Iop_Add64, mkexpr(t1), mkexpr(t8))); -+ -+ /* Repeat previous steps for the rounded value. */ -+ assign(t10, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0))); -+ assign(t11, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ -+ assign(t12, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0xffffffff))); -+ assign(t13, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ -+ assign(t14, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t10)), -+ unop(Iop_1Sto32, mkexpr(t11))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t12)), -+ unop(Iop_1Sto32, mkexpr(t13))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t14), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); -+ -+ assign(t16, binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0x80000000))); -+ putIReg(rt, IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t14), -+ mkU32(0)), -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t16), -+ mkU32(0)), -+ mkU32(0x7fffffff), -+ mkU32(0x80000000)), -+ unop(Iop_64to32, mkexpr(t9)))); - break; - } - case 0x7: { /* EXTRV_RS.W */ -@@ -3366,104 +3863,146 @@ - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I64); - t2 = newTemp(Ity_I32); -- t4 = newTemp(Ity_I32); -- t5 = newTemp(Ity_I64); -- t6 = newTemp(Ity_I64); -+ t3 = newTemp(Ity_I1); -+ t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I1); - t7 = newTemp(Ity_I32); -- t8 = newTemp(Ity_I32); -- t9 = newTemp(Ity_I32); -- t10 = newTemp(Ity_I32); -+ t8 = newTemp(Ity_I64); -+ t9 = newTemp(Ity_I64); -+ t10 = newTemp(Ity_I1); -+ t11 = newTemp(Ity_I1); -+ t12 = newTemp(Ity_I1); -+ t13 = newTemp(Ity_I1); -+ t14 = newTemp(Ity_I32); -+ t15 = newTemp(Ity_I32); -+ t16 = newTemp(Ity_I32); -+ t17 = newTemp(Ity_I1); - -+ assign(t15, binop(Iop_And32, -+ getIReg(rs), -+ mkU32(0x1f))); -+ assign(t17, binop(Iop_CmpEQ32, -+ mkexpr(t15), -+ mkU32(0))); - assign(t0, getAcc(ac)); -+ assign(t1, IRExpr_ITE(mkexpr(t17), -+ mkexpr(t0), -+ binop(Iop_Sar64, -+ mkexpr(t0), -+ unop(Iop_32to8, -+ mkexpr(t15))))); - -- assign(t1, binop(Iop_Sar64, -- mkexpr(t0), -- unop(Iop_32to8, binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f))))); -+ /* Check if bits 63..31 of the result in t1 aren't 0. */ -+ assign(t3, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0))); -+ assign(t4, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0))); -+ /* Check if bits 63..31 of the result in t1 aren't -+ 0x1ffffffff. */ -+ assign(t5, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t1)), -+ mkU32(0xffffffff))); -+ assign(t6, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); -+ /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP -+ control register. */ -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t3)), -+ unop(Iop_1Sto32, mkexpr(t4))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t5)), -+ unop(Iop_1Sto32, mkexpr(t6))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t7), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - -- assign(t2, binop(Iop_Or32, -- getDSPControl(), mkU32(0x00800000))); -+ /* If the last discarded bit is 1, there would be carry -+ when rounding, otherwise there wouldn't. We use that -+ fact and just add the value of the last discarded bit -+ to the least sifgnificant bit of the shifted value -+ from acc. */ -+ assign(t8, -+ IRExpr_ITE(mkexpr(t17), -+ mkU64(0x0ULL), -+ binop(Iop_And64, -+ binop(Iop_Shr64, -+ mkexpr(t0), -+ unop(Iop_32to8, -+ binop(Iop_Sub32, -+ mkexpr(t15), -+ mkU32(1)))), -+ mkU64(0x1ULL)))); - -- assign(t10, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t1)), -- mkU32(0xffffffff)), -- mkexpr(t2), -- getDSPControl()), -- getDSPControl())); -+ assign(t9, binop(Iop_Add64, mkexpr(t1), mkexpr(t8))); - -- putDSPControl(mkexpr(t10)); -+ /* Repeat previous steps for the rounded value. */ -+ assign(t10, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0))); -+ assign(t11, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0))); - -- assign(t4, binop(Iop_Or32, -- getDSPControl(), mkU32(0x00800000))); -- /* If the last discarded bit is 1, there would be carry -- when rounding, otherwise there wouldn't. We use that -- fact and just add the value of the last discarded bit to -- the least sifgnificant bit of the shifted value from -- acc. */ -- assign(t5, binop(Iop_Shr64, -- binop(Iop_And64, -- mkexpr(t0), -- binop(Iop_Shl64, -- mkU64(0x1ULL), -- unop(Iop_32to8, -- binop(Iop_Sub32, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f)), -- mkU32(0x1))))), -- unop(Iop_32to8, -- binop(Iop_Sub32, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f)), -- mkU32(0x1))))); -+ assign(t12, binop(Iop_CmpNE32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0xffffffff))); -+ assign(t13, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ mkU32(0x80000000)), -+ mkU32(0x80000000))); - -- assign(t6, binop(Iop_Add64, mkexpr(t1), mkexpr(t5))); -- -- assign(t8, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0xffffffff)), -- mkexpr(t4), -- getDSPControl())); -+ assign(t14, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t10)), -+ unop(Iop_1Sto32, mkexpr(t11))), -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, mkexpr(t12)), -+ unop(Iop_1Sto32, mkexpr(t13))))); - putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0x0)), -- mkexpr(t8), -+ mkexpr(t14), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), - getDSPControl())); -- assign(t9, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -+ -+ assign(t16, binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ mkU32(0x80000000))); -+ putIReg(rt, IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t14), -+ mkU32(0)), -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t16), -+ mkU32(0)), -+ mkU32(0x7fffffff), - mkU32(0x80000000)), -- mkU32(0x0)), -- mkU32(0x7fffffff), -- mkU32(0x80000000))); -- assign(t7, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, mkexpr(t6)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0xffffffff)), -- mkexpr(t9), -- unop(Iop_64to32, -- mkexpr(t6))), -- unop(Iop_64to32, mkexpr(t6)))); -- putIReg(rt, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x1f)), -- mkU32(0x0)), -- unop(Iop_64to32, mkexpr(t0)), -- mkexpr(t7))); -+ unop(Iop_64to32, mkexpr(t9)))); - break; - } - case 0xA: { /* EXTPDP */ -@@ -3678,9 +4217,7 @@ - t5 = newTemp(Ity_I32); - t6 = newTemp(Ity_I64); - t7 = newTemp(Ity_I32); -- t8 = newTemp(Ity_I32); - t9 = newTemp(Ity_I32); -- t10 = newTemp(Ity_I1); - - assign(t0, getAcc(ac)); - -@@ -3689,12 +4226,10 @@ - assign(t2, binop(Iop_Or32, - getDSPControl(), mkU32(0x00800000))); - -- assign(t9, binop(Iop_Shl32, -- binop(Iop_And32, -- unop(Iop_64to32, -- mkexpr(t1)), -- mkU32(0x00008000)), -- mkU8(16))); -+ assign(t9, binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000))); - putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, - mkexpr(t9), - binop(Iop_And32, -@@ -3711,120 +4246,79 @@ - assign(t3, binop(Iop_Sub64, - mkexpr(t1), - mkU64(0x0000000000007fffULL))); -- assign(t4, binop(Iop_Or32, -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t3)), -- mkU32(0x7fffffff)))), -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -+ assign(t4, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), -+ binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t3)), -+ mkU32(0x7fffffff)))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), - unop(Iop_64to32, -- mkexpr(t3)), -- mkU32(0xffffffff)))))); -- -- assign(t5, IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t3)), -- mkU32(0x80000000)), -- mkU8(31))), -- unop(Iop_64to32, mkexpr(t1)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t4), -- mkU32(0x0)), -- mkU32(0x7fff), -- unop(Iop_64to32, -- mkexpr(t1))))); -- -- assign(t10, unop(Iop_32to1, -- binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t3)), -- mkU32(0x80000000)), -- mkU8(31)))); -- putDSPControl(IRExpr_ITE(mkexpr(t10), -- getDSPControl(), -- IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t4), -- mkU32(0x0)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x00800000)), -- getDSPControl()))); -- -+ mkexpr(t3))))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t3)), -+ mkU32(0x80000000)), -+ mkU32(0))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t4)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); - /* Check if t1<0xffffffffffff8000 (0xffffffffffff8000-t1)>0 -- 1. subtract t1 from 0x7fff -+ 1. subtract t1 from 0xffffffffffff8000 - 2. if the resulting number is positive (sign bit = 0) - and any of the other bits is 1, the value is > 0 */ - assign(t6, binop(Iop_Sub64, - mkU64(0xffffffffffff8000ULL), - mkexpr(t1))); -- -- assign(t7, binop(Iop_Or32, -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0x7fffffff)))), -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -- unop(Iop_64to32, -- mkexpr(t6)), -- mkU32(0xffffffff)))))); -- -- assign(t8, IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0x80000000)), -- mkU8(31))), -- unop(Iop_64to32, mkexpr(t1)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t7), -- mkU32(0x0)), -- mkU32(0xffff8000), -- unop(Iop_64to32, -- mkexpr(t1))))); -- putDSPControl(IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0x80000000)), -- mkU8(31))), -- getDSPControl(), -- IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t7), -- mkU32(0x0)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x00800000)), -- getDSPControl()))); -- -- /* If the shifted value is positive, it can only be >0x7fff -- and the final result is the value stored in t5, -- otherwise, the final result is in t8. */ -- putIReg(rt, IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), - binop(Iop_And32, - unop(Iop_64HIto32, -- mkexpr(t1)), -+ mkexpr(t6)), -+ mkU32(0x7fffffff)))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), -+ unop(Iop_64to32, -+ mkexpr(t6))))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t6)), - mkU32(0x80000000)), -- mkU8(31))), -- mkexpr(t8), -- mkexpr(t5))); -+ mkU32(0))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t7)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); -+ putIReg(rt, IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t4)), -+ mkU32(0x00007fff), -+ IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t7)), -+ mkU32(0xffff8000), -+ unop(Iop_64to32, -+ mkexpr(t1))))); - break; - } - case 0xF: { /* EXTRV_S.H */ -@@ -3838,10 +4332,7 @@ - t5 = newTemp(Ity_I32); - t6 = newTemp(Ity_I64); - t7 = newTemp(Ity_I32); -- t8 = newTemp(Ity_I32); - t9 = newTemp(Ity_I32); -- t10 = newTemp(Ity_I32); -- t11 = newTemp(Ity_I32); - - assign(t0, getAcc(ac)); - -@@ -3855,12 +4346,10 @@ - assign(t2, binop(Iop_Or32, - getDSPControl(), mkU32(0x00800000))); - -- assign(t9, binop(Iop_Shl32, -- binop(Iop_And32, -- unop(Iop_64to32, -- mkexpr(t1)), -- mkU32(0x00008000)), -- mkU8(16))); -+ assign(t9, binop(Iop_And32, -+ unop(Iop_64to32, -+ mkexpr(t1)), -+ mkU32(0x80000000))); - putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, - mkexpr(t9), - binop(Iop_And32, -@@ -3873,127 +4362,83 @@ - /* Check if t1 > 0x7fff ((t1 - 0x7fff) > 0) - 1. subtract 0x7fff from t1 - 2. if the resulting number is positive (sign bit = 0) -- and any of the other bits is 1, the value is > 0 */ -+ and any of the other bits is 1, the value is > 0. */ - assign(t3, binop(Iop_Sub64, - mkexpr(t1), - mkU64(0x0000000000007fffULL))); -- assign(t4, binop(Iop_Or32, -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t3)), -- mkU32(0x7fffffff)))), -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -+ assign(t4, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), -+ binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t3)), -+ mkU32(0x7fffffff)))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), - unop(Iop_64to32, -- mkexpr(t3)), -- mkU32(0xffffffff)))))); -- -- assign(t5, IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t3)), -- mkU32(0x80000000)), -- mkU8(31))), -- unop(Iop_64to32, mkexpr(t1)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t4), -- mkU32(0x0)), -- mkU32(0x7fff), -- unop(Iop_64to32, -- mkexpr(t1))))); -- -- assign(t10, binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t3)), -- mkU32(0x80000000)), -- mkU8(31))); -- assign(t11, IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t4), -- mkU32(0x0)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x00800000)), -- getDSPControl())); -- putDSPControl(IRExpr_ITE(unop(Iop_32to1, -- mkexpr(t10)), -- getDSPControl(), -- mkexpr(t11))); -- -- /* Check if t1<0xffffffffffff8000 -- 1. subtract t1 from 0x7fff -- 2. if the resulting number is positive (sign bit == 0) -+ mkexpr(t3))))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t3)), -+ mkU32(0x80000000)), -+ mkU32(0))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t4)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); -+ /* Check if t1<0xffffffffffff8000 (0xffffffffffff8000-t1)>0 -+ 1. subtract t1 from 0xffffffffffff8000 -+ 2. if the resulting number is positive (sign bit = 0) - and any of the other bits is 1, the value is > 0 */ - assign(t6, binop(Iop_Sub64, -- mkU64(0xffffffffffff8000ULL), -- mkexpr(t1))); -- -- assign(t7, binop(Iop_Or32, -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0x7fffffff)))), -- unop(Iop_1Uto32, -- binop(Iop_CmpNE32, -- mkU32(0), -- binop(Iop_And32, -- unop(Iop_64to32, -- mkexpr(t6)), -- mkU32(0xffffffff)))))); -- -- assign(t8, IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0x80000000)), -- mkU8(31))), -- unop(Iop_64to32, mkexpr(t1)), -- IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t7), -- mkU32(0x0)), -- mkU32(0xffff8000), -- unop(Iop_64to32, -- mkexpr(t1))))); -- putDSPControl(IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t6)), -- mkU32(0x80000000) -- ), -- mkU8(31))), -- getDSPControl(), -- IRExpr_ITE(binop(Iop_CmpNE32, -- mkexpr(t7), -- mkU32(0x0)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x00800000) -- ), -- getDSPControl()))); -- -- /* If the shifted value is positive, it can only be >0x7fff -- and the final result is the value stored in t5, -- otherwise, the final result is in t8. */ -- putIReg(rt, IRExpr_ITE(unop(Iop_32to1, -- binop(Iop_Shr32, -+ mkU64(0xffffffffffff8000ULL), -+ mkexpr(t1))); -+ assign(t7, binop(Iop_And32, -+ binop(Iop_Or32, -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), - binop(Iop_And32, - unop(Iop_64HIto32, -- mkexpr(t1)), -+ mkexpr(t6)), -+ mkU32(0x7fffffff)))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpNE32, -+ mkU32(0), -+ unop(Iop_64to32, -+ mkexpr(t6))))), -+ unop(Iop_1Sto32, -+ binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ unop(Iop_64HIto32, -+ mkexpr(t6)), - mkU32(0x80000000)), -- mkU8(31))), -- mkexpr(t8), -- mkexpr(t5))); -+ mkU32(0))))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t7)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x00800000)), -+ getDSPControl())); -+ putIReg(rt, IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t4)), -+ mkU32(0x00007fff), -+ IRExpr_ITE(binop(Iop_CmpNE32, -+ mkU32(0), -+ mkexpr(t7)), -+ mkU32(0xffff8000), -+ unop(Iop_64to32, -+ mkexpr(t1))))); - break; - } - case 0x12: { /* RDDSP*/ -@@ -4192,38 +4637,38 @@ - DIP("shilov ac%d, r%d", ac, rs); - vassert(!mode64); - t0 = newTemp(Ity_I64); -- t1 = newTemp(Ity_I64); -- t2 = newTemp(Ity_I32); -- t3 = newTemp(Ity_I1); -+ t1 = newTemp(Ity_I32); -+ t2 = newTemp(Ity_I1); -+ t3 = newTemp(Ity_I64); - t4 = newTemp(Ity_I64); -- t5 = newTemp(Ity_I64); - - assign(t0, getAcc(ac)); -- assign(t2, binop(Iop_And32, getIReg(rs), mkU32(0x3f))); -- assign(t3, binop(Iop_CmpEQ32, mkexpr(t2), mkU32(0x20))); -- -- assign(t4, binop(Iop_Shl64, -+ assign(t1, binop(Iop_And32, getIReg(rs), mkU32(0x3f))); -+ assign(t2, binop(Iop_CmpEQ32, mkexpr(t1), mkU32(0x20))); -+ assign(t3, binop(Iop_Shl64, - mkexpr(t0), - unop(Iop_32to8, - binop(Iop_Add32, - unop(Iop_Not32, -- mkexpr(t2)), -+ mkexpr(t1)), - mkU32(0x1))))); -- assign(t5, binop(Iop_Shr64, -+ assign(t4, binop(Iop_Shr64, - mkexpr(t0), - unop(Iop_32to8, -- mkexpr(t2)))); -- putAcc(ac, IRExpr_ITE(mkexpr(t3), -- binop(Iop_32HLto64, -- unop(Iop_64to32, mkexpr(t0)), -- mkU32(0x0)), -- IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- mkexpr(t2), -- mkU32(0x20)), -- mkU32(0x20)), -- mkexpr(t4), -- mkexpr(t5)))); -+ mkexpr(t1)))); -+ -+ putAcc(ac, -+ IRExpr_ITE(mkexpr(t2), -+ binop(Iop_32HLto64, -+ unop(Iop_64to32, mkexpr(t0)), -+ mkU32(0x0)), -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ mkexpr(t1), -+ mkU32(0x20)), -+ mkU32(0x20)), -+ mkexpr(t3), -+ mkexpr(t4)))); - break; - } - case 0x1F: { /* MTHLIP */ -@@ -7201,160 +7646,113 @@ - t0 = newTemp(Ity_I32); - t1 = newTemp(Ity_I1); - t2 = newTemp(Ity_I1); -- t3 = newTemp(Ity_I1); -- t4 = newTemp(Ity_I32); -- t5 = newTemp(Ity_I32); -- t6 = newTemp(Ity_I1); -+ t3 = newTemp(Ity_I32); -+ t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I32); - t7 = newTemp(Ity_I1); - t8 = newTemp(Ity_I1); -- t9 = newTemp(Ity_I32); -- t10 = newTemp(Ity_I32); -- t11 = newTemp(Ity_I1); -- t12 = newTemp(Ity_I1); -- t13 = newTemp(Ity_I1); -- t14 = newTemp(Ity_I32); -- t15 = newTemp(Ity_I32); -- t16 = newTemp(Ity_I1); -- t17 = newTemp(Ity_I1); -- t18 = newTemp(Ity_I32); -+ t9 = newTemp(Ity_I1); -+ t10 = newTemp(Ity_I1); - - if (0 == rs) { - putIReg(rd, getIReg(rt)); - } else { -- /* Shift bits 7..0. */ -+ /* Shift bits 7..0 and 23..16. */ - assign(t0, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_32to8, getIReg(rt))), -- unop(Iop_32to8, -- binop(Iop_And32, -- mkU32(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x00ff00ff)), -+ mkU8(rs))); - assign(t1, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t0)))), -- mkU32(0x00000000))); -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0xff000000)), -+ mkU32(0x00000000))); - assign(t2, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t0)))), -- mkU32(0x000000ff))); -- assign(t4, binop(Iop_Or32, -- getDSPControl(), mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t1), -- IRExpr_ITE(mkexpr(t2), -- mkexpr(t4), -- getDSPControl()), -- getDSPControl())); -- -- /* Shift bits 15..8. */ -- assign(t5, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- getIReg(rt)))), -- unop(Iop_32to8, -- binop(Iop_And32, -- mkU32(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -- assign(t6, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t5)))), -- mkU32(0x00000000))); -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0xff000000)), -+ mkU32(0xff000000))); - assign(t7, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t5)))), -- mkU32(0x000000ff))); -- assign(t9, binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t6), -- IRExpr_ITE(mkexpr(t7), -- mkexpr(t9), -- getDSPControl()), -- getDSPControl())); -- -- /* Shift bits 23..16. */ -- assign(t10, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_16to8, -- unop(Iop_32HIto16, -- getIReg(rt)))), -- unop(Iop_32to8, -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0x0000ff00)), -+ mkU32(0x00000000))); -+ assign(t8, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0x0000ff00)), -+ mkU32(0x000ff00))); -+ /* Shift bits 15..8 and 31..24. */ -+ assign(t3, binop(Iop_Shl32, -+ binop(Iop_Shr32, - binop(Iop_And32, -- mkU32(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -- assign(t11, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t10)))), -- mkU32(0x00000000))); -- assign(t12, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t10)))), -- mkU32(0x000000ff))); -+ getIReg(rt), -+ mkU32(0xff00ff00)), -+ mkU8(8)), -+ mkU8(rs))); -+ assign(t4, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0xff000000)), -+ mkU32(0x00000000))); -+ assign(t5, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0xff000000)), -+ mkU32(0xff000000))); -+ assign(t9, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0x0000ff00)), -+ mkU32(0x00000000))); -+ assign(t10, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0x0000ff00)), -+ mkU32(0x0000ff00))); - -- assign(t14, binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t11), -- IRExpr_ITE(mkexpr(t12), -- mkexpr(t14), -- getDSPControl()), -- getDSPControl())); -- -- /* Shift bits 31..24. */ -- assign(t15, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32HIto16, -- getIReg(rt)))), -- unop(Iop_32to8, -+ assign(t6, binop(Iop_Or32, -+ binop(Iop_Or32, - binop(Iop_And32, -- mkU32(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -- assign(t16, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t15)))), -- mkU32(0x00000000))); -- assign(t17, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t15)))), -- mkU32(0x000000ff))); -+ unop(Iop_1Uto32, -+ mkexpr(t1)), -+ unop(Iop_1Uto32, -+ mkexpr(t2))), -+ binop(Iop_And32, -+ unop(Iop_1Uto32, -+ mkexpr(t7)), -+ unop(Iop_1Uto32, -+ mkexpr(t8)))), -+ binop(Iop_Or32, -+ binop(Iop_And32, -+ unop(Iop_1Uto32, -+ mkexpr(t4)), -+ unop(Iop_1Uto32, -+ mkexpr(t5))), -+ binop(Iop_And32, -+ unop(Iop_1Uto32, -+ mkexpr(t9)), -+ unop(Iop_1Uto32, -+ mkexpr(t10)))))); - -- assign(t18, binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t16), -- IRExpr_ITE(mkexpr(t17), -- mkexpr(t18), -- getDSPControl()), -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t6), -+ mkU32(0x0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), - getDSPControl())); -- -- putIReg(rd, binop(Iop_16HLto32, -- binop(Iop_8HLto16, -- unop(Iop_32to8, mkexpr(t15)), -- unop(Iop_32to8, mkexpr(t10))), -- binop(Iop_8HLto16, -- unop(Iop_32to8, mkexpr(t5)), -- unop(Iop_32to8, mkexpr(t0))))); -+ putIReg(rd, binop(Iop_Or32, -+ binop(Iop_Shl32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0x00ff00ff)), -+ mkU8(8)), -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0x00ff00ff)))); - } - break; - } -@@ -7422,165 +7820,119 @@ - t0 = newTemp(Ity_I32); - t1 = newTemp(Ity_I1); - t2 = newTemp(Ity_I1); -- t3 = newTemp(Ity_I1); -- t4 = newTemp(Ity_I32); -- t5 = newTemp(Ity_I32); -- t6 = newTemp(Ity_I1); -+ t3 = newTemp(Ity_I32); -+ t4 = newTemp(Ity_I1); -+ t5 = newTemp(Ity_I1); -+ t6 = newTemp(Ity_I32); - t7 = newTemp(Ity_I1); - t8 = newTemp(Ity_I1); -- t9 = newTemp(Ity_I32); -- t10 = newTemp(Ity_I32); -- t11 = newTemp(Ity_I1); -- t12 = newTemp(Ity_I1); -- t13 = newTemp(Ity_I1); -- t14 = newTemp(Ity_I32); -- t15 = newTemp(Ity_I32); -- t16 = newTemp(Ity_I1); -- t17 = newTemp(Ity_I1); -- t18 = newTemp(Ity_I32); -+ t9 = newTemp(Ity_I1); -+ t10 = newTemp(Ity_I1); -+ t11 = newTemp(Ity_I8); - -- /* Shift bits 7..0. */ -+ assign(t11, unop(Iop_32to8, -+ binop(Iop_And32, -+ getIReg(rs), -+ mkU32(0x7)))); -+ /* Shift bits 7..0 and 23..16. */ - assign(t0, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_32to8, getIReg(rt))), -- unop(Iop_32to8, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x00ff00ff)), -+ mkexpr(t11))); - assign(t1, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, mkexpr(t0)))), -- mkU32(0x00000000))); -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0xff000000)), -+ mkU32(0x00000000))); - assign(t2, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, mkexpr(t0)))), -- mkU32(0x000000ff))); -- -- assign(t4, binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t1), -- IRExpr_ITE(mkexpr(t2), -- mkexpr(t4), -- getDSPControl()), -- getDSPControl())); -- -- /* Shift bits 15..8. */ -- assign(t5, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, getIReg(rt)))), -- unop(Iop_32to8, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -- assign(t6, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, mkexpr(t5)))), -- mkU32(0x00000000))); -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0xff000000)), -+ mkU32(0xff000000))); - assign(t7, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, mkexpr(t5)))), -- mkU32(0x000000ff))); -- -- assign(t9, binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t6), -- IRExpr_ITE(mkexpr(t7), -- mkexpr(t9), -- getDSPControl()), -- getDSPControl())); -- -- /* Shift bits 23..16. */ -- assign(t10, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_16to8, -- unop(Iop_32HIto16, -- getIReg(rt)))), -- unop(Iop_32to8, -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0x0000ff00)), -+ mkU32(0x00000000))); -+ assign(t8, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0x0000ff00)), -+ mkU32(0x000ff00))); -+ /* Shift bits 15..8 and 31..24. */ -+ assign(t3, binop(Iop_Shl32, -+ binop(Iop_Shr32, - binop(Iop_And32, -- getIReg(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -- assign(t11, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t10)))), -- mkU32(0x00000000))); -- assign(t12, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t10)))), -- mkU32(0x000000ff))); -+ getIReg(rt), -+ mkU32(0xff00ff00)), -+ mkU8(8)), -+ mkexpr(t11))); -+ assign(t4, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0xff000000)), -+ mkU32(0x00000000))); -+ assign(t5, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0xff000000)), -+ mkU32(0xff000000))); -+ assign(t9, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0x0000ff00)), -+ mkU32(0x00000000))); -+ assign(t10, binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0x0000ff00)), -+ mkU32(0x0000ff00))); - -- assign(t14, binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t11), -- IRExpr_ITE(mkexpr(t12), -- mkexpr(t14), -- getDSPControl()), -- getDSPControl())); -- -- /* Shift bits 31..24. */ -- assign(t15, binop(Iop_Shl32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32HIto16, -- getIReg(rt)))), -- unop(Iop_32to8, -+ assign(t6, binop(Iop_Or32, -+ binop(Iop_Or32, - binop(Iop_And32, -- getIReg(rs), -- mkU32(0x7))))); -- /* Check if discard isn't 0x0 and 0xffffffff. */ -- assign(t16, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t15)))), -- mkU32(0x00000000))); -- assign(t17, binop(Iop_CmpNE32, -- unop(Iop_8Uto32, -- unop(Iop_16HIto8, -- unop(Iop_32to16, -- mkexpr(t15)))), -- mkU32(0x000000ff))); -+ unop(Iop_1Uto32, -+ mkexpr(t1)), -+ unop(Iop_1Uto32, -+ mkexpr(t2))), -+ binop(Iop_And32, -+ unop(Iop_1Uto32, -+ mkexpr(t7)), -+ unop(Iop_1Uto32, -+ mkexpr(t8)))), -+ binop(Iop_Or32, -+ binop(Iop_And32, -+ unop(Iop_1Uto32, -+ mkexpr(t4)), -+ unop(Iop_1Uto32, -+ mkexpr(t5))), -+ binop(Iop_And32, -+ unop(Iop_1Uto32, -+ mkexpr(t9)), -+ unop(Iop_1Uto32, -+ mkexpr(t10)))))); - -- assign(t18, binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000))); -- putDSPControl(IRExpr_ITE(mkexpr(t16), -- IRExpr_ITE(mkexpr(t17), -- mkexpr(t18), -- getDSPControl()), -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ mkexpr(t6), -+ mkU32(0x0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), - getDSPControl())); -- - putIReg(rd, IRExpr_ITE(binop(Iop_CmpEQ32, -+ unop(Iop_8Uto32, mkexpr(t11)), -+ mkU32(0)), -+ getIReg(rt), -+ binop(Iop_Or32, -+ binop(Iop_Shl32, -+ binop(Iop_And32, -+ mkexpr(t3), -+ mkU32(0xff00ff)), -+ mkU8(8)), - binop(Iop_And32, -- getIReg(rs), -- mkU32(0x7)), -- mkU32(0x0)), -- getIReg(rt), -- binop(Iop_16HLto32, -- binop(Iop_8HLto16, -- unop(Iop_32to8, -- mkexpr(t15)), -- unop(Iop_32to8, -- mkexpr(t10))), -- binop(Iop_8HLto16, -- unop(Iop_32to8, -- mkexpr(t5)), -- unop(Iop_32to8, -- mkexpr(t0)))))); -+ mkexpr(t0), -+ mkU32(0x00ff00ff))))); - break; - } - case 0x1: { /* SHRLV.QB */ -@@ -8075,7 +8427,10 @@ - t1 = newTemp(Ity_I32); - t2 = newTemp(Ity_I32); - t3 = newTemp(Ity_I32); -- t4 = newTemp(Ity_I1); -+ t4 = newTemp(Ity_I32); -+ t5 = newTemp(Ity_I32); -+ t6 = newTemp(Ity_I32); -+ t7 = newTemp(Ity_I32); - - if (0 == rs) { - putIReg(rd, getIReg(rt)); -@@ -8086,21 +8441,27 @@ - unop(Iop_32to16, getIReg(rt))), - mkU8(rs))); - -- assign(t2, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t0))), -- mkU32(0xffffffff)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000)), -- getDSPControl())); -- putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t0))), -- mkU32(0x00000000)), -- mkexpr(t2), -+ assign(t1, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t0), -+ mkU8(16)), -+ mkU32(0)))); -+ assign(t2, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t0), -+ mkU8(16)), -+ mkU32(0xffffffff)))); -+ assign(t3, binop(Iop_And32, -+ mkexpr(t1), -+ mkexpr(t2))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t3), -+ mkU32(0x1)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), - getDSPControl())); - putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, - binop(Iop_And32, -@@ -8115,46 +8476,56 @@ - getDSPControl(), - mkU32(0x400000)))); - /* Shift higher 16 bits. */ -- assign(t1, binop(Iop_Shl32, -+ assign(t4, binop(Iop_Shl32, - unop(Iop_16Sto32, - unop(Iop_32HIto16, getIReg(rt))), - mkU8(rs))); - -- assign(t3, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t1))), -- mkU32(0xffffffff)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000)), -- getDSPControl())); -- putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t1))), -- mkU32(0x00000000)), -- mkexpr(t3), -- getDSPControl())); -- assign(t4, binop(Iop_CmpEQ32, -- binop(Iop_Shr32, -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x80000000)), -- mkU8(31)), -- binop(Iop_Shr32, -- binop(Iop_And32, -- mkexpr(t1), -- mkU32(0x00008000)), -- mkU8(15)))); -- putDSPControl(IRExpr_ITE(mkexpr(t4), -+ assign(t5, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t4), -+ mkU8(16)), -+ mkU32(0)))); -+ assign(t6, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t4), -+ mkU8(16)), -+ mkU32(0xffffffff)))); -+ assign(t7, binop(Iop_And32, -+ mkexpr(t5), -+ mkexpr(t6))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t7), -+ mkU32(0x1)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), -+ getDSPControl())); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t7), -+ mkU32(0x1)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), -+ getDSPControl())); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x80000000)), -+ binop(Iop_Shl32, -+ binop(Iop_And32, -+ mkexpr(t4), -+ mkU32(0x00008000)), -+ mkU8(16)) -+ ), - getDSPControl(), - binop(Iop_Or32, - getDSPControl(), - mkU32(0x400000)))); -- - putIReg(rd, binop(Iop_16HLto32, -- unop(Iop_32to16, mkexpr(t1)), -+ unop(Iop_32to16, mkexpr(t4)), - unop(Iop_32to16, mkexpr(t0)))); - } - break; -@@ -8323,18 +8694,20 @@ - DIP("shll_s.ph r%d, r%d, %d", rd, rt, rs); - vassert(!mode64); - t0 = newTemp(Ity_I32); -- t1 = newTemp(Ity_I16); -- t2 = newTemp(Ity_I16); -- t3 = newTemp(Ity_I16); -+ t1 = newTemp(Ity_I32); -+ t2 = newTemp(Ity_I32); -+ t3 = newTemp(Ity_I32); - t4 = newTemp(Ity_I32); -- t5 = newTemp(Ity_I16); -- t6 = newTemp(Ity_I16); -- t7 = newTemp(Ity_I16); -+ t5 = newTemp(Ity_I32); -+ t6 = newTemp(Ity_I32); -+ t7 = newTemp(Ity_I32); - t8 = newTemp(Ity_I32); - t9 = newTemp(Ity_I32); -- t10 = newTemp(Ity_I1); -- t11 = newTemp(Ity_I16); -- t12 = newTemp(Ity_I16); -+ t10 = newTemp(Ity_I32); -+ t11 = newTemp(Ity_I32); -+ t12 = newTemp(Ity_I32); -+ t13 = newTemp(Ity_I32); -+ t14 = newTemp(Ity_I32); - - if (0 == rs) { - putIReg(rd, getIReg(rt)); -@@ -8345,69 +8718,70 @@ - unop(Iop_32to16, getIReg(rt))), - mkU8(rs))); - -- assign(t1, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x00008000)), -- mkU32(0x0)), -- mkU16(0x7fff), -- mkU16(0x8000))); -- assign(t2, -- IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_Shr32, -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x00008000)), -- mkU8(15)), -- binop(Iop_Shr32, -- binop(Iop_And32, -- mkexpr(t0), -- mkU32(0x00008000)), -- mkU8(15))), -- unop(Iop_32to16, mkexpr(t0)), -- mkexpr(t1))); -- assign(t11, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t0))), -- mkU32(0xffffffff)), -- mkexpr(t1), -- mkexpr(t2))); -- assign(t3, -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t0))), -- mkU32(0x00000000)), -- mkexpr(t11), -- mkexpr(t2))); -- assign(t8, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t0))), -- mkU32(0xffffffff)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000)), -- getDSPControl())); -- putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t0))), -- mkU32(0x00000000)), -- mkexpr(t8), -- getDSPControl())); -+ assign(t1, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t0), -+ mkU8(16)), -+ mkU32(0)))); -+ assign(t2, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t0), -+ mkU8(16)), -+ mkU32(0xffffffff)))); -+ assign(t3, binop(Iop_And32, -+ mkexpr(t1), -+ mkexpr(t2))); - putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t3), -+ mkU32(0x1)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), -+ getDSPControl())); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, - binop(Iop_And32, - getIReg(rt), - mkU32(0x00008000)), - binop(Iop_And32, -- mkexpr(t0), -- mkU32(0x00008000))), -+ mkexpr(t0), -+ mkU32(0x00008000)) -+ ), - getDSPControl(), - binop(Iop_Or32, - getDSPControl(), - mkU32(0x400000)))); -+ assign(t8, -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t3), -+ mkU32(0x1)), -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x8000)), -+ mkU32(0)), -+ mkU32(0x00007fff), -+ mkU32(0x00008000)), -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0x0000ffff)))); -+ assign(t10, -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x00008000)), -+ binop(Iop_And32, -+ mkexpr(t0), -+ mkU32(0x00008000))), -+ mkexpr(t8), -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x8000)), -+ mkU32(0)), -+ mkU32(0x00007fff), -+ mkU32(0x00008000)))); - /* Shift higher 16 bits. */ - assign(t4, binop(Iop_Shl32, - unop(Iop_16Sto32, -@@ -8414,77 +8788,88 @@ - unop(Iop_32HIto16, getIReg(rt))), - mkU8(rs))); - -- assign(t5, IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x80000000)), -- mkU32(0x0)), -- mkU16(0x7fff), -- mkU16(0x8000))); -- assign(t6, -- IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_Shr32, -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x80000000)), -- mkU8(31)), -- binop(Iop_Shr32, -- binop(Iop_And32, -- mkexpr(t4), -- mkU32(0x00008000)), -- mkU8(15))), -- unop(Iop_32to16, mkexpr(t4)), -- mkexpr(t5))); -- assign(t12, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t4))), -- mkU32(0xffffffff)), -- mkexpr(t5), -- mkexpr(t6))); -- assign(t7, -- IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t4))), -- mkU32(0x00000000)), -- mkexpr(t12), -- mkexpr(t6))); -- assign(t9, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t4))), -- mkU32(0xffffffff)), -- binop(Iop_Or32, -- getDSPControl(), -- mkU32(0x400000)), -- getDSPControl())); -- putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_16Sto32, -- unop(Iop_32HIto16, -- mkexpr(t4))), -- mkU32(0x00000000)), -- mkexpr(t9), -+ assign(t5, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t4), -+ mkU8(16)), -+ mkU32(0)))); -+ assign(t6, unop(Iop_1Uto32, -+ binop(Iop_CmpNE32, -+ binop(Iop_Sar32, -+ mkexpr(t4), -+ mkU8(16)), -+ mkU32(0xffffffff)))); -+ assign(t7, binop(Iop_And32, -+ mkexpr(t5), -+ mkexpr(t6))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t7), -+ mkU32(0x1)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), - getDSPControl())); -- assign(t10, binop(Iop_CmpEQ32, -- binop(Iop_Shr32, -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0x80000000)), -- mkU8(31)), -- binop(Iop_Shr32, -- binop(Iop_And32, -- mkexpr(t4), -- mkU32(0x00008000)), -- mkU8(15)))); -- putDSPControl(IRExpr_ITE(mkexpr(t10), -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t7), -+ mkU32(0x1)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ mkU32(0x400000)), -+ getDSPControl())); -+ assign(t12, binop(Iop_Shl32, -+ binop(Iop_And32, -+ mkexpr(t4), -+ mkU32(0x8000)), -+ mkU8(16))); -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x80000000)), -+ mkexpr(t12)), - getDSPControl(), - binop(Iop_Or32, - getDSPControl(), - mkU32(0x400000)))); -- -- putIReg(rd, binop(Iop_16HLto32, -- mkexpr(t7), mkexpr(t3))); -+ assign(t13, IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x80000000)), -+ mkU32(0)), -+ mkU32(0x7fff0000), -+ mkU32(0x80000000))); -+ assign(t9, -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ mkexpr(t7), -+ mkU32(0x1)), -+ mkexpr(t13), -+ binop(Iop_Shl32, -+ binop(Iop_And32, -+ mkexpr(t4), -+ mkU32(0x0000ffff)), -+ mkU8(16)))); -+ assign(t14, IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x80000000)), -+ mkU32(0)), -+ mkU32(0x7fff0000), -+ mkU32(0x80000000))); -+ assign(t11, -+ IRExpr_ITE(binop(Iop_CmpEQ32, -+ binop(Iop_And32, -+ getIReg(rt), -+ mkU32(0x80000000)), -+ binop(Iop_Shl32, -+ binop(Iop_And32, -+ mkexpr(t4), -+ mkU32(0x00008000)), -+ mkU8(16))), -+ mkexpr(t9), -+ mkexpr(t14))); -+ putIReg(rd, binop(Iop_Or32, -+ mkexpr(t10), -+ mkexpr(t11))); - } - break; - } -@@ -10831,10 +11216,9 @@ - t8 = newTemp(Ity_I64); - t9 = newTemp(Ity_I64); - t10 = newTemp(Ity_I32); -- t11 = newTemp(Ity_I32); - - assign(t0, getAcc(ac)); -- /* Calculate first cross dot product and saturate if -+ /* Calculate the first cross dot product and saturate if - needed. */ - assign(t1, unop(Iop_32Sto64, - binop(Iop_Shl32, -@@ -10859,23 +11243,28 @@ - unop(Iop_32to16, getIReg(rt))), - mkU32(0x00008000))); - -- assign(t4, -- IRExpr_ITE(mkexpr(t2), -- IRExpr_ITE(mkexpr(t3), -- mkU64(0x000000007fffffffULL), -- mkexpr(t1)), -- mkexpr(t1))); -+ assign(t4, IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t2)), -+ unop(Iop_1Sto32, -+ mkexpr(t3))), -+ mkU32(0)), -+ mkU64(0x000000007fffffffULL), -+ mkexpr(t1))); - -- putDSPControl(IRExpr_ITE(mkexpr(t2), -- IRExpr_ITE(mkexpr(t3), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16) -- ) -- ), -- getDSPControl()), -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t2)), -+ unop(Iop_1Sto32, -+ mkexpr(t3))), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))), - getDSPControl())); - /* Calculate second cross dot product and saturate if - needed. */ -@@ -10902,29 +11291,35 @@ - unop(Iop_32HIto16, getIReg(rt))), - mkU32(0x00008000))); - -- assign(t8, -- IRExpr_ITE(mkexpr(t6), -- IRExpr_ITE(mkexpr(t7), -- mkU64(0x000000007fffffffULL), -- mkexpr(t5)), -- mkexpr(t5))); -+ assign(t8, IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t6)), -+ unop(Iop_1Sto32, -+ mkexpr(t7))), -+ mkU32(0)), -+ mkU64(0x000000007fffffffULL), -+ mkexpr(t5))); - -- putDSPControl(IRExpr_ITE(mkexpr(t6), -- IRExpr_ITE(mkexpr(t7), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16) -- ) -- ), -- getDSPControl()), -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t6)), -+ unop(Iop_1Sto32, -+ mkexpr(t7))), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))), - getDSPControl())); -- /* Add intermediate products with value in the -+ /* Subtract intermediate products from value in the - accumulator. */ -- assign(t9, binop(Iop_Add64, -- mkexpr(t0), -- binop(Iop_Add64, mkexpr(t8), mkexpr(t4)))); -+ assign(t9, -+ binop(Iop_Add64, -+ mkexpr(t0), -+ binop(Iop_Add64, mkexpr(t8), mkexpr(t4)))); - - putAcc(ac, - IRExpr_ITE(binop(Iop_CmpEQ32, -@@ -10949,38 +11344,28 @@ - mkU32(0xffffffff)), - mkU64(0xffffffff80000000ULL), - mkexpr(t9)))); -- assign(t10, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- binop(Iop_Shl64, -- mkexpr(t9), -- mkU8(1))), -- mkU32(0x0)), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16))), -- getDSPControl())); -- assign(t11, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- binop(Iop_Shl64, -- mkexpr(t9), -- mkU8(1))), -- mkU32(0xffffffff)), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16))), -- getDSPControl())); -+ assign(t10, IRExpr_ITE(binop(Iop_CmpEQ32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ unop(Iop_64to32, -+ getAcc(ac))), -+ getDSPControl(), -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))))); - putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t9)), -- mkU32(0x80000000)), -- mkU32(0x0)), -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ unop(Iop_64HIto32, -+ getAcc(ac))), - mkexpr(t10), -- mkexpr(t11))); -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))))); - break; - } - case 0x1B: { /* DPSQX_SA.W.PH */ -@@ -10997,10 +11382,9 @@ - t8 = newTemp(Ity_I64); - t9 = newTemp(Ity_I64); - t10 = newTemp(Ity_I32); -- t11 = newTemp(Ity_I32); - - assign(t0, getAcc(ac)); -- /* Calculate first cross dot product and saturate if -+ /* Calculate the first cross dot product and saturate if - needed. */ - assign(t1, unop(Iop_32Sto64, - binop(Iop_Shl32, -@@ -11025,23 +11409,28 @@ - unop(Iop_32to16, getIReg(rt))), - mkU32(0x00008000))); - -- assign(t4, -- IRExpr_ITE(mkexpr(t2), -- IRExpr_ITE(mkexpr(t3), -- mkU64(0x000000007fffffffULL), -- mkexpr(t1)), -- mkexpr(t1))); -+ assign(t4, IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t2)), -+ unop(Iop_1Sto32, -+ mkexpr(t3))), -+ mkU32(0)), -+ mkU64(0x000000007fffffffULL), -+ mkexpr(t1))); - -- putDSPControl(IRExpr_ITE(mkexpr(t2), -- IRExpr_ITE(mkexpr(t3), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16) -- ) -- ), -- getDSPControl()), -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t2)), -+ unop(Iop_1Sto32, -+ mkexpr(t3))), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))), - getDSPControl())); - /* Calculate second cross dot product and saturate if - needed. */ -@@ -11060,31 +11449,36 @@ - intermediate product and write to DSPControl - register. */ - assign(t6, binop(Iop_CmpEQ32, -- binop(Iop_And32, -- getIReg(rs), -- mkU32(0x0000ffff)), -+ unop(Iop_16Uto32, -+ unop(Iop_32to16, getIReg(rs))), - mkU32(0x00008000))); - assign(t7, binop(Iop_CmpEQ32, -- binop(Iop_And32, -- getIReg(rt), -- mkU32(0xffff0000)), -- mkU32(0x80000000))); -+ unop(Iop_16Uto32, -+ unop(Iop_32HIto16, getIReg(rt))), -+ mkU32(0x00008000))); - -- assign(t8, -- IRExpr_ITE(mkexpr(t6), -- IRExpr_ITE(mkexpr(t7), -- mkU64(0x000000007fffffffULL), -- mkexpr(t5)), -- mkexpr(t5))); -+ assign(t8, IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t6)), -+ unop(Iop_1Sto32, -+ mkexpr(t7))), -+ mkU32(0)), -+ mkU64(0x000000007fffffffULL), -+ mkexpr(t5))); - -- putDSPControl(IRExpr_ITE(mkexpr(t6), -- IRExpr_ITE(mkexpr(t7), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16))), -- getDSPControl()), -+ putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32, -+ binop(Iop_And32, -+ unop(Iop_1Sto32, -+ mkexpr(t6)), -+ unop(Iop_1Sto32, -+ mkexpr(t7))), -+ mkU32(0)), -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))), - getDSPControl())); - /* Subtract intermediate products from value in the - accumulator. */ -@@ -11116,38 +11510,28 @@ - mkU32(0xffffffff)), - mkU64(0xffffffff80000000ULL), - mkexpr(t9)))); -- assign(t10, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- binop(Iop_Shl64, -- mkexpr(t9), -- mkU8(1))), -- mkU32(0x0)), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16))), -- getDSPControl())); -- assign(t11, IRExpr_ITE(binop(Iop_CmpNE32, -- unop(Iop_64HIto32, -- binop(Iop_Shl64, -- mkexpr(t9), -- mkU8(1))), -- mkU32(0xffffffff)), -- binop(Iop_Or32, -- getDSPControl(), -- binop(Iop_Shl32, -- mkU32(0x1), -- mkU8(ac+16))), -- getDSPControl())); -+ assign(t10, IRExpr_ITE(binop(Iop_CmpEQ32, -+ unop(Iop_64to32, -+ mkexpr(t9)), -+ unop(Iop_64to32, -+ getAcc(ac))), -+ getDSPControl(), -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))))); - putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32, -- binop(Iop_And32, -- unop(Iop_64HIto32, -- mkexpr(t9)), -- mkU32(0x80000000)), -- mkU32(0x0)), -+ unop(Iop_64HIto32, -+ mkexpr(t9)), -+ unop(Iop_64HIto32, -+ getAcc(ac))), - mkexpr(t10), -- mkexpr(t11))); -+ binop(Iop_Or32, -+ getDSPControl(), -+ binop(Iop_Shl32, -+ mkU32(0x1), -+ mkU8(ac+16))))); - break; - } - default: -@@ -11417,22 +11801,22 @@ - vex_inject_ir(irsb, Iend_BE); - #endif - if (mode64) { -- stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_TISTART), -+ stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_CMSTART), - mkU64(guest_PC_curr_instr))); -- stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_TILEN), -+ stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_CMLEN), - mkU64(20))); - - putPC(mkU64(guest_PC_curr_instr + 20)); - } else { -- stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_TISTART), -+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_CMSTART), - mkU32(guest_PC_curr_instr))); -- stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_TILEN), -+ stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_CMLEN), - mkU32(20))); - - putPC(mkU32(guest_PC_curr_instr + 20)); - } - dres.whatNext = Dis_StopHere; -- dres.jk_StopHere = Ijk_TInval; -+ dres.jk_StopHere = Ijk_InvalICache; - dres.len = 20; - delta += 20; - goto decode_success; -@@ -11462,7 +11846,7 @@ - trap_code = get_code(cins); - function = get_function(cins); - IRType ty = mode64 ? Ity_I64 : Ity_I32; -- IRType tyF = mode64 ? Ity_F64 : Ity_F32; -+ IRType tyF = fp_mode64 ? Ity_F64 : Ity_F32; - - ac = get_acNo(cins); - -@@ -11495,102 +11879,112 @@ - lastn = mkexpr(t0); - break; - -- case 0x11: /* COP1 */ -- { -+ case 0x11: { /* COP1 */ -+ if (fmt == 0x3 && fd == 0 && function == 0) { /* MFHC1 */ -+ DIP("mfhc1 r%d, f%d", rt, fs); -+ if (fp_mode64) { -+ t0 = newTemp(Ity_I64); -+ t1 = newTemp(Ity_I32); -+ assign(t0, unop(Iop_ReinterpF64asI64, getDReg(fs))); -+ assign(t1, unop(Iop_64HIto32, mkexpr(t0))); -+ putIReg(rt, mkWidenFrom32(ty, mkexpr(t1), True)); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } -+ break; -+ } else if (fmt == 0x7 && fd == 0 && function == 0) { /* MTHC1 */ -+ DIP("mthc1 r%d, f%d", rt, fs); -+ if (fp_mode64) { -+ t0 = newTemp(Ity_I64); -+ assign(t0, binop(Iop_32HLto64, getIReg(rt), -+ unop(Iop_ReinterpF32asI32, -+ getLoFromF64(Ity_F64 /* 32FPR mode. */, -+ getDReg(fs))))); -+ putDReg(fs, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } -+ break; -+ } else if (fmt == 0x8) { /* BC */ -+ /* FcConditionalCode(bc1_cc) */ - UInt bc1_cc = get_bc1_cc(cins); -- if (0x08 == fmt) { -- switch (fmt) { -- case 0x08: /* BC */ -- { -- DIP("tf: %d, nd: %d", tf, nd); -- /* FcConditionalCode(bc1_cc) */ -- t1 = newTemp(Ity_I1); -- t2 = newTemp(Ity_I32); -- t3 = newTemp(Ity_I1); -+ t1 = newTemp(Ity_I1); -+ t2 = newTemp(Ity_I32); -+ t3 = newTemp(Ity_I1); - -- assign(t1, binop(Iop_CmpEQ32, mkU32(0), mkU32(bc1_cc))); -- assign(t2, IRExpr_ITE(mkexpr(t1), -- binop(Iop_And32, -- binop(Iop_Shr32, getFCSR(), -- mkU8(23)), -- mkU32(0x1)), -- binop(Iop_And32, -- binop(Iop_Shr32, getFCSR(), -- mkU8(24 + bc1_cc)), -- mkU32(0x1)) -- )); -+ assign(t1, binop(Iop_CmpEQ32, mkU32(0), mkU32(bc1_cc))); -+ assign(t2, IRExpr_ITE(mkexpr(t1), -+ binop(Iop_And32, -+ binop(Iop_Shr32, getFCSR(), mkU8(23)), -+ mkU32(0x1)), -+ binop(Iop_And32, -+ binop(Iop_Shr32, getFCSR(), -+ mkU8(24 + bc1_cc)), -+ mkU32(0x1)))); - -- if (tf == 1 && nd == 0) { -- /* branch on true */ -- DIP("bc1t %d, %d", bc1_cc, imm); -- assign(t3, binop(Iop_CmpEQ32, mkU32(1), mkexpr(t2))); -- dis_branch(False, mkexpr(t3), imm, &bstmt); -+ if (tf == 1 && nd == 0) { -+ /* branch on true */ -+ DIP("bc1t %d, %d", bc1_cc, imm); -+ assign(t3, binop(Iop_CmpEQ32, mkU32(1), mkexpr(t2))); -+ dis_branch(False, mkexpr(t3), imm, &bstmt); -+ break; -+ } else if (tf == 0 && nd == 0) { -+ /* branch on false */ -+ DIP("bc1f %d, %d", bc1_cc, imm); -+ assign(t3, binop(Iop_CmpEQ32, mkU32(0), mkexpr(t2))); -+ dis_branch(False, mkexpr(t3), imm, &bstmt); -+ break; -+ } else if (nd == 1 && tf == 0) { -+ DIP("bc1fl %d, %d", bc1_cc, imm); -+ lastn = dis_branch_likely(binop(Iop_CmpNE32, mkexpr(t2), -+ mkU32(0x0)), imm); -+ break; -+ } else if (nd == 1 && tf == 1) { -+ DIP("bc1tl %d, %d", bc1_cc, imm); -+ lastn = dis_branch_likely(binop(Iop_CmpEQ32, mkexpr(t2), -+ mkU32(0x0)), imm); -+ break; -+ } else -+ goto decode_failure; -+ } else { -+ switch (function) { -+ case 0x4: { /* SQRT.fmt */ -+ switch (fmt) { -+ case 0x10: { /* S */ -+ IRExpr *rm = get_IR_roundingmode(); -+ putFReg(fd, mkWidenFromF32(tyF, binop(Iop_SqrtF32, rm, -+ getLoFromF64(tyF, getFReg(fs))))); - break; -- } else if (tf == 0 && nd == 0) { -- /* branch on false */ -- DIP("bc1f %d, %d", bc1_cc, imm); -- assign(t3, binop(Iop_CmpEQ32, mkU32(0), mkexpr(t2))); -- dis_branch(False, mkexpr(t3), imm, &bstmt); -+ } -+ case 0x11: { /* D */ -+ IRExpr *rm = get_IR_roundingmode(); -+ putDReg(fd, binop(Iop_SqrtF64, rm, getDReg(fs))); - break; -- } else if (nd == 1 && tf == 0) { -- DIP("bc1fl %d, %d", bc1_cc, imm); -- lastn = dis_branch_likely(binop(Iop_CmpNE32, mkexpr(t2), -- mkU32(0x0)), imm); -- break; -- } else if (nd == 1 && tf == 1) { -- DIP("bc1tl %d, %d", bc1_cc, imm); -- lastn = dis_branch_likely(binop(Iop_CmpEQ32, mkexpr(t2), -- mkU32(0x0)), imm); -- break; -- } else -+ } -+ default: - goto decode_failure; -- } -- -- default: -- goto decode_failure; -- } -- } else { -- switch (function) { -- -- case 0x4: /* SQRT.fmt */ -- { -- switch (fmt) { -- case 0x10: /* S */ -- { -- IRExpr *rm = get_IR_roundingmode(); -- putFReg(fd, mkWidenFromF32(tyF, binop(Iop_SqrtF32, rm, -- getLoFromF64(tyF, getFReg(fs))))); -- } -- break; -- case 0x11: /* D */ -- { -- IRExpr *rm = get_IR_roundingmode(); -- putDReg(fd, binop(Iop_SqrtF64, rm, getDReg(fs))); -- } -- break; - } - } - break; - case 0x5: /* abs.fmt */ - switch (fmt) { -- case 0x10: /* S */ -- DIP("abs.s f%d, f%d", fd, fs); -- putFReg(fd, mkWidenFromF32(tyF, unop(Iop_AbsF32, -- getLoFromF64(tyF, getFReg(fs))))); -- break; -- case 0x11: /* D */ -- DIP("abs.d f%d, f%d", fd, fs); -- putDReg(fd, unop(Iop_AbsF64, getDReg(fs))); -- break; -- default: -- goto decode_failure; -+ case 0x10: /* S */ -+ DIP("abs.s f%d, f%d", fd, fs); -+ putFReg(fd, mkWidenFromF32(tyF, unop(Iop_AbsF32, -+ getLoFromF64(tyF, getFReg(fs))))); -+ break; -+ case 0x11: /* D */ -+ DIP("abs.d f%d, f%d", fd, fs); -+ putDReg(fd, unop(Iop_AbsF64, getDReg(fs))); -+ break; -+ default: -+ goto decode_failure; - } - break; /* case 0x5 */ - - case 0x02: /* MUL.fmt */ - switch (fmt) { -- case 0x11: /* D */ -- { -+ case 0x11: { /* D */ - DIP("mul.d f%d, f%d, f%d", fd, fs, ft); - IRExpr *rm = get_IR_roundingmode(); - putDReg(fd, triop(Iop_MulF64, rm, getDReg(fs), -@@ -11597,8 +11991,7 @@ - getDReg(ft))); - break; - } -- case 0x10: /* S */ -- { -+ case 0x10: { /* S */ - DIP("mul.s f%d, f%d, f%d", fd, fs, ft); - IRExpr *rm = get_IR_roundingmode(); - putFReg(fd, mkWidenFromF32(tyF, triop(Iop_MulF32, rm, -@@ -11606,15 +11999,14 @@ - getLoFromF64(tyF, getFReg(ft))))); - break; - } -- default: -- goto decode_failure; -+ default: -+ goto decode_failure; - } - break; /* MUL.fmt */ - - case 0x03: /* DIV.fmt */ - switch (fmt) { -- case 0x11: /* D */ -- { -+ case 0x11: { /* D */ - DIP("div.d f%d, f%d, f%d", fd, fs, ft); - IRExpr *rm = get_IR_roundingmode(); - putDReg(fd, triop(Iop_DivF64, rm, getDReg(fs), -@@ -11621,9 +12013,9 @@ - getDReg(ft))); - break; - } -- case 0x10: /* S */ -- { -+ case 0x10: { /* S */ - DIP("div.s f%d, f%d, f%d", fd, fs, ft); -+ calculateFCSR(fs, ft, DIVS, False, 2); - IRExpr *rm = get_IR_roundingmode(); - putFReg(fd, mkWidenFromF32(tyF, triop(Iop_DivF32, rm, - getLoFromF64(tyF, getFReg(fs)), -@@ -11630,24 +12022,24 @@ - getLoFromF64(tyF, getFReg(ft))))); - break; - } -- default: -- goto decode_failure; -+ default: -+ goto decode_failure; - } - break; /* DIV.fmt */ - - case 0x01: /* SUB.fmt */ - switch (fmt) { -- case 0x11: /* D */ -- { -+ case 0x11: { /* D */ - DIP("sub.d f%d, f%d, f%d", fd, fs, ft); -+ calculateFCSR(fs, ft, SUBD, False, 2); - IRExpr *rm = get_IR_roundingmode(); - putDReg(fd, triop(Iop_SubF64, rm, getDReg(fs), - getDReg(ft))); - break; - } -- case 0x10: /* S */ -- { -+ case 0x10: { /* S */ - DIP("sub.s f%d, f%d, f%d", fd, fs, ft); -+ calculateFCSR(fs, ft, SUBS, True, 2); - IRExpr *rm = get_IR_roundingmode(); - putFReg(fd, mkWidenFromF32(tyF, triop(Iop_SubF32, rm, - getLoFromF64(tyF, getFReg(fs)), -@@ -11654,8 +12046,8 @@ - getLoFromF64(tyF, getFReg(ft))))); - break; - } -- default: -- goto decode_failure; -+ default: -+ goto decode_failure; - } - break; /* SUB.fmt */ - -@@ -11663,8 +12055,8 @@ - switch (fmt) { - case 0x11: /* D */ - DIP("mov.d f%d, f%d", fd, fs); -- if (mode64) { -- putFReg(fd, getFReg(fs)); -+ if (fp_mode64) { -+ putDReg(fd, getDReg(fs)); - } else { - putFReg(fd, getFReg(fs)); - putFReg(fd + 1, getFReg(fs + 1)); -@@ -11699,19 +12091,27 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("round.l.s f%d, f%d", fd, fs); -- calculateFCSR(fs, ROUNDLS, True); -- t0 = newTemp(Ity_I64); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, ROUNDLS, True, 1); -+ t0 = newTemp(Ity_I64); - -- assign(t0, binop(Iop_F32toI64S, mkU32(0x0), -- getLoFromF64(Ity_F64, getFReg(fs)))); -+ assign(t0, binop(Iop_F32toI64S, mkU32(0x0), -+ getLoFromF64(Ity_F64, getFReg(fs)))); - -- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -- break; -+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } -+ break; - case 0x11: /* D */ - DIP("round.l.d f%d, f%d", fd, fs); -- calculateFCSR(fs, ROUNDLD, False); -- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x0), -- getFReg(fs))); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, ROUNDLD, False, 1); -+ putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x0), -+ getDReg(fs))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - default: - goto decode_failure; -@@ -11723,18 +12123,26 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("trunc.l.s f%d, f%d", fd, fs); -- calculateFCSR(fs, TRUNCLS, True); -- t0 = newTemp(Ity_I64); -- assign(t0, binop(Iop_F32toI64S, mkU32(0x3), -- getLoFromF64(Ity_F64, getFReg(fs)))); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, TRUNCLS, True, 1); -+ t0 = newTemp(Ity_I64); -+ assign(t0, binop(Iop_F32toI64S, mkU32(0x3), -+ getLoFromF64(Ity_F64, getFReg(fs)))); - -- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - case 0x11: /* D */ - DIP("trunc.l.d f%d, f%d", fd, fs); -- calculateFCSR(fs, TRUNCLD, False); -- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x3), -- getFReg(fs))); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, TRUNCLD, False, 1); -+ putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x3), -+ getDReg(fs))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - default: - goto decode_failure; -@@ -11771,7 +12179,6 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("movn.s f%d, f%d, r%d", fd, fs, rt); -- - t1 = newTemp(Ity_F64); - t2 = newTemp(Ity_F64); - t3 = newTemp(Ity_I1); -@@ -11781,13 +12188,19 @@ - assign(t2, getFReg(fd)); - assign(t3, binop(Iop_CmpNE64, mkU64(0), getIReg(rt))); - } else { -- assign(t1, unop(Iop_F32toF64, getFReg(fs))); -- assign(t2, unop(Iop_F32toF64, getFReg(fd))); -- assign(t3, binop(Iop_CmpNE32, mkU32(0), getIReg(rt))); -+ if (fp_mode64) { -+ assign(t1, getFReg(fs)); -+ assign(t2, getFReg(fd)); -+ assign(t3, binop(Iop_CmpNE32, mkU32(0), getIReg(rt))); -+ } else { -+ assign(t1, unop(Iop_F32toF64, getFReg(fs))); -+ assign(t2, unop(Iop_F32toF64, getFReg(fd))); -+ assign(t3, binop(Iop_CmpNE32, mkU32(0), getIReg(rt))); -+ } - } - - assign(t4, IRExpr_ITE(mkexpr(t3), mkexpr(t1), mkexpr(t2))); -- if (mode64) { -+ if (fp_mode64) { - IRTemp f = newTemp(Ity_F64); - IRTemp fd_hi = newTemp(Ity_I32); - t5 = newTemp(Ity_I64); -@@ -11795,7 +12208,7 @@ - assign(fd_hi, unop(Iop_64HIto32, unop(Iop_ReinterpF64asI64, - mkexpr(f)))); - -- assign(t5, mkWidenFrom32(ty, unop(Iop_64to32, -+ assign(t5, mkWidenFrom32(Ity_I64, unop(Iop_64to32, - unop(Iop_ReinterpF64asI64, mkexpr(t4))), True)); - - putFReg(fd, unop (Iop_ReinterpI64asF64, mkexpr(t5))); -@@ -11830,10 +12243,13 @@ - t2 = newTemp(Ity_F64); - t3 = newTemp(Ity_I1); - t4 = newTemp(Ity_F64); -- if (mode64) { -+ if (fp_mode64) { - assign(t1, getFReg(fs)); - assign(t2, getFReg(fd)); -- assign(t3, binop(Iop_CmpEQ64, mkU64(0), getIReg(rt))); -+ if (mode64) -+ assign(t3, binop(Iop_CmpEQ64, mkU64(0), getIReg(rt))); -+ else -+ assign(t3, binop(Iop_CmpEQ32, mkU32(0), getIReg(rt))); - } else { - assign(t1, unop(Iop_F32toF64, getFReg(fs))); - assign(t2, unop(Iop_F32toF64, getFReg(fd))); -@@ -11841,7 +12257,7 @@ - } - assign(t4, IRExpr_ITE(mkexpr(t3), mkexpr(t1), mkexpr(t2))); - -- if (mode64) { -+ if (fp_mode64) { - IRTemp f = newTemp(Ity_F64); - IRTemp fd_hi = newTemp(Ity_I32); - t7 = newTemp(Ity_I64); -@@ -11848,7 +12264,7 @@ - assign(f, getFReg(fd)); - assign(fd_hi, unop(Iop_64HIto32, - unop(Iop_ReinterpF64asI64, mkexpr(f)))); -- assign(t7, mkWidenFrom32(ty, unop(Iop_64to32, -+ assign(t7, mkWidenFrom32(Ity_I64, unop(Iop_64to32, - unop(Iop_ReinterpF64asI64, mkexpr(t4))), True)); - - putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t7))); -@@ -11911,7 +12327,7 @@ - t6 = newTemp(Ity_F64); - t7 = newTemp(Ity_I64); - -- if (mode64) { -+ if (fp_mode64) { - assign(t5, getFReg(fs)); - assign(t6, getFReg(fd)); - } else { -@@ -11935,13 +12351,13 @@ - assign(t4, IRExpr_ITE(mkexpr(t3), - mkexpr(t5), mkexpr(t6))); - -- if (mode64) { -+ if (fp_mode64) { - IRTemp f = newTemp(Ity_F64); - IRTemp fd_hi = newTemp(Ity_I32); - assign(f, getFReg(fd)); - assign(fd_hi, unop(Iop_64HIto32, - unop(Iop_ReinterpF64asI64, mkexpr(f)))); -- assign(t7, mkWidenFrom32(ty, unop(Iop_64to32, -+ assign(t7, mkWidenFrom32(Ity_I64, unop(Iop_64to32, - unop(Iop_ReinterpF64asI64, mkexpr(t4))), - True)); - -@@ -11991,7 +12407,7 @@ - t5 = newTemp(Ity_F64); - t6 = newTemp(Ity_F64); - -- if (mode64) { -+ if (fp_mode64) { - assign(t5, getFReg(fs)); - assign(t6, getFReg(fd)); - } else { -@@ -12015,7 +12431,7 @@ - assign(t4, IRExpr_ITE(mkexpr(t3), - mkexpr(t5), mkexpr(t6))); - -- if (mode64) { -+ if (fp_mode64) { - IRTemp f = newTemp(Ity_F64); - IRTemp fd_hi = newTemp(Ity_I32); - t7 = newTemp(Ity_I64); -@@ -12022,7 +12438,7 @@ - assign(f, getFReg(fd)); - assign(fd_hi, unop(Iop_64HIto32, - unop(Iop_ReinterpF64asI64, mkexpr(f)))); -- assign(t7, mkWidenFrom32(ty, unop(Iop_64to32, -+ assign(t7, mkWidenFrom32(Ity_I64, unop(Iop_64to32, - unop(Iop_ReinterpF64asI64, mkexpr(t4))), - True)); - -@@ -12040,17 +12456,18 @@ - - case 0x0: /* add.fmt */ - switch (fmt) { -- case 0x10: /* S */ -- { -- DIP("add.s f%d, f%d, f%d", fd, fs, ft); -- IRExpr *rm = get_IR_roundingmode(); -- putFReg(fd, mkWidenFromF32(tyF, triop(Iop_AddF32, rm, -- getLoFromF64(tyF, getFReg(fs)), -- getLoFromF64(tyF, getFReg(ft))))); -- break; -- } -+ case 0x10: { /* S */ -+ DIP("add.s f%d, f%d, f%d", fd, fs, ft); -+ calculateFCSR(fs, ft, ADDS, True, 2); -+ IRExpr *rm = get_IR_roundingmode(); -+ putFReg(fd, mkWidenFromF32(tyF, triop(Iop_AddF32, rm, -+ getLoFromF64(tyF, getFReg(fs)), -+ getLoFromF64(tyF, getFReg(ft))))); -+ break; -+ } - case 0x11: { /* D */ - DIP("add.d f%d, f%d, f%d", fd, fs, ft); -+ calculateFCSR(fs, ft, ADDD, False, 2); - IRExpr *rm = get_IR_roundingmode(); - putDReg(fd, triop(Iop_AddF64, rm, getDReg(fs), getDReg(ft))); - break; -@@ -12058,10 +12475,10 @@ - - case 0x4: /* MTC1 (Move Word to Floating Point) */ - DIP("mtc1 r%d, f%d", rt, fs); -- if (mode64) { -+ if (fp_mode64) { - t0 = newTemp(Ity_I32); - t1 = newTemp(Ity_F32); -- assign(t0, unop(Iop_64to32, getIReg(rt))); -+ assign(t0, mkNarrowTo32(ty, getIReg(rt))); - assign(t1, unop(Iop_ReinterpI32asF32, mkexpr(t0))); - - putFReg(fs, mkWidenFromF32(tyF, mkexpr(t1))); -@@ -12077,7 +12494,7 @@ - - case 0x0: /* MFC1 */ - DIP("mfc1 r%d, f%d", rt, fs); -- if (mode64) { -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs))); -@@ -12200,8 +12617,8 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("cvt.d.s f%d, f%d", fd, fs); -- calculateFCSR(fs, CVTDS, True); -- if (mode64) { -+ calculateFCSR(fs, 0, CVTDS, True, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); -@@ -12220,8 +12637,8 @@ - - case 0x14: - DIP("cvt.d.w %d, %d", fd, fs); -- calculateFCSR(fs, CVTDW, True); -- if (mode64) { -+ calculateFCSR(fs, 0, CVTDW, True, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); -@@ -12240,9 +12657,9 @@ - } - - case 0x15: { /* L */ -- if (mode64) { -+ if (fp_mode64) { - DIP("cvt.d.l %d, %d", fd, fs); -- calculateFCSR(fs, CVTDL, False); -+ calculateFCSR(fs, 0, CVTDL, False, 1); - t0 = newTemp(Ity_I64); - assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs))); - -@@ -12261,8 +12678,8 @@ - switch (fmt) { - case 0x14: /* W */ - DIP("cvt.s.w %d, %d", fd, fs); -- calculateFCSR(fs, CVTSW, True); -- if (mode64) { -+ calculateFCSR(fs, 0, CVTSW, True, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); -@@ -12283,20 +12700,16 @@ - - case 0x11: /* D */ - DIP("cvt.s.d %d, %d", fd, fs); -- calculateFCSR(fs, CVTSD, False); -- if (mode64) { -- t0 = newTemp(Ity_F32); -- assign(t0, binop(Iop_F64toF32, get_IR_roundingmode(), -- getFReg(fs))); -- putFReg(fd, mkWidenFromF32(tyF, mkexpr(t0))); -- } else -- putFReg(fd, binop(Iop_F64toF32, get_IR_roundingmode(), -- getDReg(fs))); -+ calculateFCSR(fs, 0, CVTSD, False, 1); -+ t0 = newTemp(Ity_F32); -+ assign(t0, binop(Iop_F64toF32, get_IR_roundingmode(), -+ getDReg(fs))); -+ putFReg(fd, mkWidenFromF32(tyF, mkexpr(t0))); - break; - - case 0x15: /* L */ - DIP("cvt.s.l %d, %d", fd, fs); -- calculateFCSR(fs, CVTSL, False); -+ calculateFCSR(fs, 0, CVTSL, False, 1); - t0 = newTemp(Ity_I64); - assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs))); - -@@ -12313,34 +12726,24 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("cvt.w.s %d, %d", fd, fs); -- calculateFCSR(fs, CVTWS, True); -- if (mode64) { -- putFReg(fd, mkWidenFromF32(tyF, binop(Iop_RoundF32toInt, -- get_IR_roundingmode(), getLoFromF64(tyF, -- getFReg(fs))))); -- } else -- putFReg(fd, binop(Iop_RoundF32toInt, get_IR_roundingmode(), -- getFReg(fs))); -+ calculateFCSR(fs, 0, CVTWS, True, 1); -+ putFReg(fd, -+ mkWidenFromF32(tyF, -+ binop(Iop_RoundF32toInt, -+ get_IR_roundingmode(), -+ getLoFromF64(tyF, getFReg(fs)))) -+ ); - break; - - case 0x11: - DIP("cvt.w.d %d, %d", fd, fs); -- calculateFCSR(fs, CVTWD, False); -- if (mode64) { -- t0 = newTemp(Ity_I32); -- t1 = newTemp(Ity_F32); -- assign(t0, binop(Iop_F64toI32S, get_IR_roundingmode(), -- getFReg(fs))); -- assign(t1, unop(Iop_ReinterpI32asF32, mkexpr(t0))); -- putFReg(fd, mkWidenFromF32(tyF, mkexpr(t1))); -- } else { -- t0 = newTemp(Ity_I32); -- -- assign(t0, binop(Iop_F64toI32S, get_IR_roundingmode(), -- getDReg(fs))); -- -- putFReg(fd, unop(Iop_ReinterpI32asF32, mkexpr(t0))); -- } -+ calculateFCSR(fs, 0, CVTWD, False, 1); -+ t0 = newTemp(Ity_I32); -+ t1 = newTemp(Ity_F32); -+ assign(t0, binop(Iop_F64toI32S, get_IR_roundingmode(), -+ getDReg(fs))); -+ assign(t1, unop(Iop_ReinterpI32asF32, mkexpr(t0))); -+ putFReg(fd, mkWidenFromF32(tyF, mkexpr(t1))); - break; - - default: -@@ -12353,20 +12756,28 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("cvt.l.s %d, %d", fd, fs); -- calculateFCSR(fs, CVTLS, True); -- t0 = newTemp(Ity_I64); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, CVTLS, True, 1); -+ t0 = newTemp(Ity_I64); - -- assign(t0, binop(Iop_F32toI64S, get_IR_roundingmode(), -- getLoFromF64(Ity_F64, getFReg(fs)))); -+ assign(t0, binop(Iop_F32toI64S, get_IR_roundingmode(), -+ getLoFromF64(tyF, getFReg(fs)))); - -- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - - case 0x11: { /* D */ - DIP("cvt.l.d %d, %d", fd, fs); -- calculateFCSR(fs, CVTLD, False); -- putFReg(fd, binop(Iop_RoundF64toInt, -- get_IR_roundingmode(), getFReg(fs))); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, CVTLD, False, 1); -+ putDReg(fd, binop(Iop_RoundF64toInt, -+ get_IR_roundingmode(), getDReg(fs))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - } - -@@ -12379,20 +12790,28 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("floor.l.s %d, %d", fd, fs); -- calculateFCSR(fs, FLOORLS, True); -- t0 = newTemp(Ity_I64); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, FLOORLS, True, 1); -+ t0 = newTemp(Ity_I64); - -- assign(t0, binop(Iop_F32toI64S, mkU32(0x1), -- getLoFromF64(Ity_F64, getFReg(fs)))); -+ assign(t0, binop(Iop_F32toI64S, mkU32(0x1), -+ getLoFromF64(tyF, getFReg(fs)))); - -- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ putDReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - - case 0x11: /* D */ - DIP("floor.l.d %d, %d", fd, fs); -- calculateFCSR(fs, FLOORLD, False); -- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x1), -- getFReg(fs))); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, FLOORLD, False, 1); -+ putDReg(fd, binop(Iop_RoundF64toInt, mkU32(0x1), -+ getDReg(fs))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - default: - goto decode_failure; -@@ -12403,8 +12822,8 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("round.w.s f%d, f%d", fd, fs); -- calculateFCSR(fs, ROUNDWS, True); -- if (mode64) { -+ calculateFCSR(fs, 0, ROUNDWS, True, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); -@@ -12427,8 +12846,8 @@ - - case 0x11: /* D */ - DIP("round.w.d f%d, f%d", fd, fs); -- calculateFCSR(fs, ROUNDWD, False); -- if (mode64) { -+ calculateFCSR(fs, 0, ROUNDWD, False, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I32); - assign(t0, binop(Iop_F64toI32S, mkU32(0x0), - getDReg(fs))); -@@ -12453,8 +12872,8 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("floor.w.s f%d, f%d", fd, fs); -- calculateFCSR(fs, FLOORWS, True); -- if (mode64) { -+ calculateFCSR(fs, 0, FLOORWS, True, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); -@@ -12477,8 +12896,8 @@ - - case 0x11: /* D */ - DIP("floor.w.d f%d, f%d", fd, fs); -- calculateFCSR(fs, FLOORWD, False); -- if (mode64) { -+ calculateFCSR(fs, 0, FLOORWD, False, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I32); - assign(t0, binop(Iop_F64toI32S, mkU32(0x1), - getDReg(fs))); -@@ -12504,8 +12923,8 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("trunc.w.s %d, %d", fd, fs); -- calculateFCSR(fs, TRUNCWS, True); -- if (mode64) { -+ calculateFCSR(fs, 0, TRUNCWS, True, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); -@@ -12527,8 +12946,8 @@ - break; - case 0x11: /* D */ - DIP("trunc.w.d %d, %d", fd, fs); -- calculateFCSR(fs, TRUNCWD, False); -- if (mode64) { -+ calculateFCSR(fs, 0, TRUNCWD, False, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I32); - - assign(t0, binop(Iop_F64toI32S, mkU32(0x3), -@@ -12555,8 +12974,8 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("ceil.w.s %d, %d", fd, fs); -- calculateFCSR(fs, CEILWS, True); -- if (mode64) { -+ calculateFCSR(fs, 0, CEILWS, True, 1); -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); - t3 = newTemp(Ity_F32); -@@ -12579,8 +12998,8 @@ - - case 0x11: /* D */ - DIP("ceil.w.d %d, %d", fd, fs); -- calculateFCSR(fs, CEILWD, False); -- if (!mode64) { -+ calculateFCSR(fs, 0, CEILWD, False, 1); -+ if (!fp_mode64) { - t0 = newTemp(Ity_I32); - assign(t0, binop(Iop_F64toI32S, mkU32(0x2), - getDReg(fs))); -@@ -12603,20 +13022,28 @@ - switch (fmt) { - case 0x10: /* S */ - DIP("ceil.l.s %d, %d", fd, fs); -- calculateFCSR(fs, CEILLS, True); -- t0 = newTemp(Ity_I64); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, CEILLS, True, 1); -+ t0 = newTemp(Ity_I64); - -- assign(t0, binop(Iop_F32toI64S, mkU32(0x2), -- getLoFromF64(Ity_F64, getFReg(fs)))); -+ assign(t0, binop(Iop_F32toI64S, mkU32(0x2), -+ getLoFromF64(tyF, getFReg(fs)))); - -- putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t0))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - - case 0x11: /* D */ - DIP("ceil.l.d %d, %d", fd, fs); -- calculateFCSR(fs, CEILLD, False); -- putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x2), -- getFReg(fs))); -+ if (fp_mode64) { -+ calculateFCSR(fs, 0, CEILLD, False, 1); -+ putFReg(fd, binop(Iop_RoundF64toInt, mkU32(0x2), -+ getFReg(fs))); -+ } else { -+ ILLEGAL_INSTRUCTON; -+ } - break; - - default: -@@ -12692,17 +13119,24 @@ - case 0x31: /* LWC1 */ - /* Load Word to Floating Point - LWC1 (MIPS32) */ - DIP("lwc1 f%d, %d(r%d)", ft, imm, rs); -- if (mode64) { -- t0 = newTemp(Ity_I64); -+ if (fp_mode64) { - t1 = newTemp(Ity_F32); - t2 = newTemp(Ity_I64); -- /* new LO */ -- assign(t0, binop(Iop_Add64, getIReg(rs), -- mkU64(extend_s_16to64(imm)))); -+ if (mode64) { -+ t0 = newTemp(Ity_I64); -+ /* new LO */ -+ assign(t0, binop(Iop_Add64, getIReg(rs), -+ mkU64(extend_s_16to64(imm)))); -+ } else { -+ t0 = newTemp(Ity_I32); -+ /* new LO */ -+ assign(t0, binop(Iop_Add32, getIReg(rs), -+ mkU32(extend_s_16to32(imm)))); -+ } - assign(t1, load(Ity_F32, mkexpr(t0))); -- assign(t2, mkWidenFrom32(ty, unop(Iop_ReinterpF32asI32, -- mkexpr(t1)), True)); -- putFReg(ft, unop(Iop_ReinterpI64asF64, mkexpr(t2))); -+ assign(t2, mkWidenFrom32(Ity_I64, unop(Iop_ReinterpF32asI32, -+ mkexpr(t1)), True)); -+ putDReg(ft, unop(Iop_ReinterpI64asF64, mkexpr(t2))); - } else { - t0 = newTemp(Ity_I32); - assign(t0, binop(Iop_Add32, getIReg(rs), -@@ -12713,7 +13147,7 @@ - - case 0x39: /* SWC1 */ - DIP("swc1 f%d, %d(r%d)", ft, imm, rs); -- if (mode64) { -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t2 = newTemp(Ity_I32); - LOAD_STORE_PATTERN; -@@ -12732,22 +13166,16 @@ - - case 0x35: - /* Load Doubleword to Floating Point - LDC1 (MIPS32) */ -+ DIP("ldc1 f%d, %d(%d)", rt, imm, rs); - LOAD_STORE_PATTERN; -- if (mode64) -- putFReg(ft, load(Ity_F64, mkexpr(t1))); -- else -- putDReg(ft, load(Ity_F64, mkexpr(t1))); -- DIP("ldc1 f%d, %d(%d)", rt, imm, rs); -+ putDReg(ft, load(Ity_F64, mkexpr(t1))); - break; - - case 0x3D: - /* Store Doubleword from Floating Point - SDC1 */ -+ DIP("sdc1 f%d, %d(%d)", ft, imm, rs); - LOAD_STORE_PATTERN; -- if (mode64) -- store(mkexpr(t1), getFReg(ft)); -- else -- store(mkexpr(t1), getDReg(ft)); -- DIP("sdc1 f%d, %d(%d)", ft, imm, rs); -+ store(mkexpr(t1), getDReg(ft)); - break; - - case 0x23: /* LW */ -@@ -12806,19 +13234,20 @@ - case 0x0: { /* LWXC1 */ - /* Load Word Indexed to Floating Point - LWXC1 (MIPS32r2) */ - DIP("lwxc1 f%d, r%d(r%d)", fd, rt, rs); -- if (mode64) { -+ if (fp_mode64) { - t0 = newTemp(Ity_I64); - t1 = newTemp(Ity_I32); -- t2 = newTemp(Ity_I64); - t3 = newTemp(Ity_F32); - t4 = newTemp(Ity_I64); - -+ t2 = newTemp(ty); - /* new LO */ -- assign(t2, binop(Iop_Add64, getIReg(rs), getIReg(rt))); -+ assign(t2, binop(mode64 ? Iop_Add64 : Iop_Add32, getIReg(rs), -+ getIReg(rt))); - assign(t3, load(Ity_F32, mkexpr(t2))); - -- assign(t4, mkWidenFrom32(ty, unop(Iop_ReinterpF32asI32, -- mkexpr(t3)), True)); -+ assign(t4, mkWidenFrom32(Ity_I64, unop(Iop_ReinterpF32asI32, -+ mkexpr(t3)), True)); - - putFReg(fd, unop(Iop_ReinterpI64asF64, mkexpr(t4))); - } else { -@@ -12832,10 +13261,11 @@ - case 0x1: { /* LDXC1 */ - /* Load Doubleword Indexed to Floating Point - LDXC1 (MIPS32r2 and MIPS64) */ -- if (mode64) { -+ if (fp_mode64) { - DIP("ldxc1 f%d, r%d(r%d)", fd, rt, rs); -- t0 = newTemp(Ity_I64); -- assign(t0, binop(Iop_Add64, getIReg(rs), getIReg(rt))); -+ t0 = newTemp(ty); -+ assign(t0, binop(mode64 ? Iop_Add64 : Iop_Add32, getIReg(rs), -+ getIReg(rt))); - putFReg(fd, load(Ity_F64, mkexpr(t0))); - break; - } else { -@@ -12869,10 +13299,10 @@ - - case 0x8: { /* Store Word Indexed from Floating Point - SWXC1 */ - DIP("swxc1 f%d, r%d(r%d)", ft, rt, rs); -- if (mode64) { -- t0 = newTemp(Ity_I64); -- assign(t0, binop(Iop_Add64, getIReg(rs), getIReg(rt))); -- -+ if (fp_mode64) { -+ t0 = newTemp(ty); -+ assign(t0, binop(mode64 ? Iop_Add64 : Iop_Add32, getIReg(rs), -+ getIReg(rt))); - store(mkexpr(t0), getLoFromF64(tyF, getFReg(fs))); - - } else { -@@ -12885,9 +13315,10 @@ - } - case 0x9: { /* Store Doubleword Indexed from Floating Point - SDXC1 */ - DIP("sdc1 f%d, %d(%d)", ft, imm, rs); -- if (mode64) { -- t0 = newTemp(Ity_I64); -- assign(t0, binop(Iop_Add64, getIReg(rs), getIReg(rt))); -+ if (fp_mode64) { -+ t0 = newTemp(ty); -+ assign(t0, binop(mode64 ? Iop_Add64 : Iop_Add32, getIReg(rs), -+ getIReg(rt))); - store(mkexpr(t0), getFReg(fs)); - } else { - t0 = newTemp(Ity_I32); -@@ -13692,6 +14123,7 @@ - /* Cavium Specific instructions */ - case 0x03: case 0x32: case 0x33: /* DMUL, CINS , CINS32 */ - case 0x3A: case 0x3B: case 0x2B: /* EXT, EXT32, SNE */ -+ /* CVM Compare Instructions */ - case 0x2A: case 0x2E: case 0x2F: /* SEQ, SEQI, SNEI */ - if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) { - if (dis_instr_CVM(cins)) -@@ -14528,8 +14960,13 @@ - } - break; /* BSHFL */ - -- /* -------- MIPS32(r2) DSP ASE(r2) instructions -------- */ -+ /* --- MIPS32(r2) DSP ASE(r2) / Cavium Specfic (LX) instructions --- */ - case 0xA: /* LX */ -+ if (VEX_MIPS_COMP_ID(archinfo->hwcaps) == VEX_PRID_COMP_CAVIUM) { -+ if (dis_instr_CVM(cins)) -+ break; -+ goto decode_failure; -+ } - case 0xC: /* INSV */ - case 0x38: { /* EXTR.W */ - if (VEX_MIPS_PROC_DSP(archinfo->hwcaps)) { -@@ -16318,8 +16755,8 @@ - - decode_failure_dsp: - vex_printf("Error occured while trying to decode MIPS32 DSP " -- "instruction.\nYour platform probably doesn't support " -- "MIPS32 DSP ASE.\n"); -+ "instruction.\nYour platform probably doesn't support " -+ "MIPS32 DSP ASE.\n"); - decode_failure: - /* All decode failures end up here. */ - if (sigill_diag) -@@ -16422,7 +16859,6 @@ - - /* Disassemble a single instruction into IR. The instruction - is located in host memory at &guest_code[delta]. */ -- - DisResult disInstr_MIPS( IRSB* irsb_IN, - Bool (*resteerOkFn) ( void *, Addr64 ), - Bool resteerCisOk, -@@ -16441,6 +16877,10 @@ - vassert(guest_arch == VexArchMIPS32 || guest_arch == VexArchMIPS64); - - mode64 = guest_arch != VexArchMIPS32; -+#if (__mips_fpr==64) -+ fp_mode64 = ((VEX_MIPS_REV(archinfo->hwcaps) == VEX_PRID_CPU_32FPR) -+ || guest_arch == VexArchMIPS64); -+#endif - - guest_code = guest_code_IN; - irsb = irsb_IN; -Index: priv/guest_ppc_helpers.c -=================================================================== ---- priv/guest_ppc_helpers.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_ppc_helpers.c (.../trunk) (revision 2863) -@@ -498,8 +498,8 @@ - - vex_state->guest_EMNOTE = EmNote_NONE; - -- vex_state->guest_TISTART = 0; -- vex_state->guest_TILEN = 0; -+ vex_state->guest_CMSTART = 0; -+ vex_state->guest_CMLEN = 0; - - vex_state->guest_NRADDR = 0; - vex_state->guest_NRADDR_GPR2 = 0; -@@ -665,8 +665,8 @@ - - vex_state->padding = 0; - -- vex_state->guest_TISTART = 0; -- vex_state->guest_TILEN = 0; -+ vex_state->guest_CMSTART = 0; -+ vex_state->guest_CMLEN = 0; - - vex_state->guest_NRADDR = 0; - vex_state->guest_NRADDR_GPR2 = 0; -@@ -808,8 +808,8 @@ - .alwaysDefd - = { /* 0 */ ALWAYSDEFD32(guest_CIA), - /* 1 */ ALWAYSDEFD32(guest_EMNOTE), -- /* 2 */ ALWAYSDEFD32(guest_TISTART), -- /* 3 */ ALWAYSDEFD32(guest_TILEN), -+ /* 2 */ ALWAYSDEFD32(guest_CMSTART), -+ /* 3 */ ALWAYSDEFD32(guest_CMLEN), - /* 4 */ ALWAYSDEFD32(guest_VSCR), - /* 5 */ ALWAYSDEFD32(guest_FPROUND), - /* 6 */ ALWAYSDEFD32(guest_NRADDR), -@@ -849,8 +849,8 @@ - .alwaysDefd - = { /* 0 */ ALWAYSDEFD64(guest_CIA), - /* 1 */ ALWAYSDEFD64(guest_EMNOTE), -- /* 2 */ ALWAYSDEFD64(guest_TISTART), -- /* 3 */ ALWAYSDEFD64(guest_TILEN), -+ /* 2 */ ALWAYSDEFD64(guest_CMSTART), -+ /* 3 */ ALWAYSDEFD64(guest_CMLEN), - /* 4 */ ALWAYSDEFD64(guest_VSCR), - /* 5 */ ALWAYSDEFD64(guest_FPROUND), - /* 6 */ ALWAYSDEFD64(guest_NRADDR), -Index: priv/guest_ppc_toIR.c -=================================================================== ---- priv/guest_ppc_toIR.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_ppc_toIR.c (.../trunk) (revision 2863) -@@ -69,6 +69,12 @@ - unconditional calls and returns (bl, blr). They should also be - emitted for conditional calls and returns, but we don't have a - way to express that right now. Ah well. -+ -+ - Uses of Iop_{Add,Sub,Mul}32Fx4: the backend (host_ppc_isel.c) -+ ignores the rounding mode, and generates code that assumes -+ round-to-nearest. This means V will compute incorrect results -+ for uses of these IROps when the rounding mode (first) arg is -+ not mkU32(Irrm_NEAREST). - */ - - /* "Special" instructions. -@@ -78,9 +84,9 @@ - concerned) but have meaning for supporting Valgrind. A special - instruction is flagged by a 16-byte preamble: - -- 32-bit mode: 54001800 54006800 5400E800 54009800 -- (rlwinm 0,0,3,0,0; rlwinm 0,0,13,0,0; -- rlwinm 0,0,29,0,0; rlwinm 0,0,19,0,0) -+ 32-bit mode: 5400183E 5400683E 5400E83E 5400983E -+ (rlwinm 0,0,3,0,31; rlwinm 0,0,13,0,31; -+ rlwinm 0,0,29,0,31; rlwinm 0,0,19,0,31) - - 64-bit mode: 78001800 78006800 7800E802 78009802 - (rotldi 0,0,3; rotldi 0,0,13; -@@ -228,8 +234,8 @@ - #define OFFB_VRSAVE offsetofPPCGuestState(guest_VRSAVE) - #define OFFB_VSCR offsetofPPCGuestState(guest_VSCR) - #define OFFB_EMNOTE offsetofPPCGuestState(guest_EMNOTE) --#define OFFB_TISTART offsetofPPCGuestState(guest_TISTART) --#define OFFB_TILEN offsetofPPCGuestState(guest_TILEN) -+#define OFFB_CMSTART offsetofPPCGuestState(guest_CMSTART) -+#define OFFB_CMLEN offsetofPPCGuestState(guest_CMLEN) - #define OFFB_NRADDR offsetofPPCGuestState(guest_NRADDR) - #define OFFB_NRADDR_GPR2 offsetofPPCGuestState(guest_NRADDR_GPR2) - #define OFFB_TFHAR offsetofPPCGuestState(guest_TFHAR) -@@ -377,8 +383,8 @@ - PPC_GST_VRSAVE, // Vector Save/Restore Register - PPC_GST_VSCR, // Vector Status and Control Register - PPC_GST_EMWARN, // Emulation warnings -- PPC_GST_TISTART,// For icbi: start of area to invalidate -- PPC_GST_TILEN, // For icbi: length of area to invalidate -+ PPC_GST_CMSTART,// For icbi: start of area to invalidate -+ PPC_GST_CMLEN, // For icbi: length of area to invalidate - PPC_GST_IP_AT_SYSCALL, // the CIA of the most recently executed SC insn - PPC_GST_SPRG3_RO, // SPRG3 - PPC_GST_TFHAR, // Transactional Failure Handler Address Register -@@ -2781,14 +2787,14 @@ - stmt( IRStmt_Put( OFFB_EMNOTE,src) ); - break; - -- case PPC_GST_TISTART: -+ case PPC_GST_CMSTART: - vassert( ty_src == ty ); -- stmt( IRStmt_Put( OFFB_TISTART, src) ); -+ stmt( IRStmt_Put( OFFB_CMSTART, src) ); - break; - -- case PPC_GST_TILEN: -+ case PPC_GST_CMLEN: - vassert( ty_src == ty ); -- stmt( IRStmt_Put( OFFB_TILEN, src) ); -+ stmt( IRStmt_Put( OFFB_CMLEN, src) ); - break; - - case PPC_GST_TEXASR: -@@ -5233,6 +5239,7 @@ - - Int simm16 = extend_s_16to32(uimm16); - IRType ty = mode64 ? Ity_I64 : Ity_I32; -+ IROp mkAdd = mode64 ? Iop_Add64 : Iop_Add32; - IRTemp EA = newTemp(ty); - UInt r = 0; - UInt ea_off = 0; -@@ -5248,7 +5255,7 @@ - } - DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); - for (r = rD_addr; r <= 31; r++) { -- irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); -+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); - putIReg( r, mkWidenFrom32(ty, loadBE(Ity_I32, irx_addr ), - False) ); - ea_off += 4; -@@ -5258,7 +5265,7 @@ - case 0x2F: // stmw (Store Multiple Word, PPC32 p527) - DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); - for (r = rS_addr; r <= 31; r++) { -- irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); -+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off)); - storeBE( irx_addr, mkNarrowTo32(ty, getIReg(r)) ); - ea_off += 4; - } -@@ -7256,14 +7263,14 @@ - assign( addr, binop( mkSzOp(ty, Iop_And8), - mkexpr(EA), - mkSzImm(ty, ~(((ULong)lineszB)-1) )) ); -- putGST( PPC_GST_TISTART, mkexpr(addr) ); -- putGST( PPC_GST_TILEN, mkSzImm(ty, lineszB) ); -+ putGST( PPC_GST_CMSTART, mkexpr(addr) ); -+ putGST( PPC_GST_CMLEN, mkSzImm(ty, lineszB) ); - - /* be paranoid ... */ - stmt( IRStmt_MBE(Imbe_Fence) ); - - putGST( PPC_GST_CIA, mkSzImm(ty, nextInsnAddr())); -- dres->jk_StopHere = Ijk_TInval; -+ dres->jk_StopHere = Ijk_InvalICache; - dres->whatNext = Dis_StopHere; - break; - } -@@ -12980,17 +12987,23 @@ - switch (opc2) { - case 0x100: // xvaddsp (VSX Vector Add Single-Precision) - DIP("xvaddsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); -- putVSReg( XT, binop(Iop_Add32Fx4, getVSReg( XA ), getVSReg( XB )) ); -+ // WARNING: BOGUS! The backend ignores rm on Iop_Add32Fx4 -+ putVSReg( XT, triop(Iop_Add32Fx4, rm, -+ getVSReg( XA ), getVSReg( XB )) ); - break; - - case 0x140: // xvmulsp (VSX Vector Multiply Single-Precision) - DIP("xvmulsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); -- putVSReg( XT, binop(Iop_Mul32Fx4, getVSReg( XA ), getVSReg( XB )) ); -+ // WARNING: BOGUS! The backend ignores rm on Iop_Mul32Fx4 -+ putVSReg( XT, triop(Iop_Mul32Fx4, rm, -+ getVSReg( XA ), getVSReg( XB )) ); - break; - - case 0x120: // xvsubsp (VSX Vector Subtract Single-Precision) - DIP("xvsubsp v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); -- putVSReg( XT, binop(Iop_Sub32Fx4, getVSReg( XA ), getVSReg( XB )) ); -+ // WARNING: BOGUS! The backend ignores rm on Iop_Sub32Fx4 -+ putVSReg( XT, triop(Iop_Sub32Fx4, rm, -+ getVSReg( XA ), getVSReg( XB )) ); - break; - - case 0x160: // xvdivsp (VSX Vector Divide Single-Precision) -@@ -17774,6 +17787,9 @@ - return False; - } - -+ IRTemp rm = newTemp(Ity_I32); -+ assign(rm, get_IR_roundingmode()); -+ - opc2 = IFIELD( theInstr, 0, 6 ); - switch (opc2) { - case 0x2E: // vmaddfp (Multiply Add FP, AV p177) -@@ -17780,8 +17796,10 @@ - DIP("vmaddfp v%d,v%d,v%d,v%d\n", - vD_addr, vA_addr, vC_addr, vB_addr); - putVReg( vD_addr, -- binop(Iop_Add32Fx4, mkexpr(vB), -- binop(Iop_Mul32Fx4, mkexpr(vA), mkexpr(vC))) ); -+ triop(Iop_Add32Fx4, mkU32(Irrm_NEAREST), -+ mkexpr(vB), -+ triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), -+ mkexpr(vA), mkexpr(vC))) ); - return True; - - case 0x2F: { // vnmsubfp (Negative Multiply-Subtract FP, AV p215) -@@ -17788,9 +17806,10 @@ - DIP("vnmsubfp v%d,v%d,v%d,v%d\n", - vD_addr, vA_addr, vC_addr, vB_addr); - putVReg( vD_addr, -- binop(Iop_Sub32Fx4, -+ triop(Iop_Sub32Fx4, mkU32(Irrm_NEAREST), - mkexpr(vB), -- binop(Iop_Mul32Fx4, mkexpr(vA), mkexpr(vC))) ); -+ triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), -+ mkexpr(vA), mkexpr(vC))) ); - return True; - } - -@@ -17802,12 +17821,14 @@ - switch (opc2) { - case 0x00A: // vaddfp (Add FP, AV p137) - DIP("vaddfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); -- putVReg( vD_addr, binop(Iop_Add32Fx4, mkexpr(vA), mkexpr(vB)) ); -+ putVReg( vD_addr, triop(Iop_Add32Fx4, -+ mkU32(Irrm_NEAREST), mkexpr(vA), mkexpr(vB)) ); - return True; - - case 0x04A: // vsubfp (Subtract FP, AV p261) - DIP("vsubfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); -- putVReg( vD_addr, binop(Iop_Sub32Fx4, mkexpr(vA), mkexpr(vB)) ); -+ putVReg( vD_addr, triop(Iop_Sub32Fx4, -+ mkU32(Irrm_NEAREST), mkexpr(vA), mkexpr(vB)) ); - return True; - - case 0x40A: // vmaxfp (Maximum FP, AV p178) -@@ -17924,8 +17945,9 @@ - binop(Iop_CmpLE32Fx4, mkexpr(vA), mkexpr(vB))) ); - assign( lt, unop(Iop_NotV128, - binop(Iop_CmpGE32Fx4, mkexpr(vA), -- binop(Iop_Sub32Fx4, mkexpr(zeros), -- mkexpr(vB)))) ); -+ triop(Iop_Sub32Fx4, mkU32(Irrm_NEAREST), -+ mkexpr(zeros), -+ mkexpr(vB)))) ); - - // finally, just shift gt,lt to correct position - assign( vD, binop(Iop_ShlN32x4, -@@ -17986,7 +18008,7 @@ - switch (opc2) { - case 0x30A: // vcfux (Convert from Unsigned Fixed-Point W, AV p156) - DIP("vcfux v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); -- putVReg( vD_addr, binop(Iop_Mul32Fx4, -+ putVReg( vD_addr, triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), - unop(Iop_I32UtoFx4, mkexpr(vB)), - mkexpr(vInvScale)) ); - return True; -@@ -17994,7 +18016,7 @@ - case 0x34A: // vcfsx (Convert from Signed Fixed-Point W, AV p155) - DIP("vcfsx v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); - -- putVReg( vD_addr, binop(Iop_Mul32Fx4, -+ putVReg( vD_addr, triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), - unop(Iop_I32StoFx4, mkexpr(vB)), - mkexpr(vInvScale)) ); - return True; -@@ -18003,7 +18025,8 @@ - DIP("vctuxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); - putVReg( vD_addr, - unop(Iop_QFtoI32Ux4_RZ, -- binop(Iop_Mul32Fx4, mkexpr(vB), mkexpr(vScale))) ); -+ triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), -+ mkexpr(vB), mkexpr(vScale))) ); - return True; - - case 0x3CA: // vctsxs (Convert to Signed Fixed-Point W Saturate, AV p171) -@@ -18010,7 +18033,8 @@ - DIP("vctsxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); - putVReg( vD_addr, - unop(Iop_QFtoI32Sx4_RZ, -- binop(Iop_Mul32Fx4, mkexpr(vB), mkexpr(vScale))) ); -+ triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), -+ mkexpr(vB), mkexpr(vScale))) ); - return True; - - default: -@@ -18522,10 +18546,10 @@ - UChar* code = (UChar*)(guest_code + delta); - /* Spot the 16-byte preamble: - 32-bit mode: -- 54001800 rlwinm 0,0,3,0,0 -- 54006800 rlwinm 0,0,13,0,0 -- 5400E800 rlwinm 0,0,29,0,0 -- 54009800 rlwinm 0,0,19,0,0 -+ 5400183E rlwinm 0,0,3,0,31 -+ 5400683E rlwinm 0,0,13,0,31 -+ 5400E83E rlwinm 0,0,29,0,31 -+ 5400983E rlwinm 0,0,19,0,31 - 64-bit mode: - 78001800 rotldi 0,0,3 - 78006800 rotldi 0,0,13 -@@ -18532,10 +18556,10 @@ - 7800E802 rotldi 0,0,61 - 78009802 rotldi 0,0,51 - */ -- UInt word1 = mode64 ? 0x78001800 : 0x54001800; -- UInt word2 = mode64 ? 0x78006800 : 0x54006800; -- UInt word3 = mode64 ? 0x7800E802 : 0x5400E800; -- UInt word4 = mode64 ? 0x78009802 : 0x54009800; -+ UInt word1 = mode64 ? 0x78001800 : 0x5400183E; -+ UInt word2 = mode64 ? 0x78006800 : 0x5400683E; -+ UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E; -+ UInt word4 = mode64 ? 0x78009802 : 0x5400983E; - if (getUIntBigendianly(code+ 0) == word1 && - getUIntBigendianly(code+ 4) == word2 && - getUIntBigendianly(code+ 8) == word3 && -@@ -18593,12 +18617,12 @@ - // be redone. For ease of handling, we simply invalidate all the - // time. - -- stmt(IRStmt_Put(OFFB_TISTART, mkSzImm(ty, guest_CIA_curr_instr))); -- stmt(IRStmt_Put(OFFB_TILEN, mkSzImm(ty, 20))); -+ stmt(IRStmt_Put(OFFB_CMSTART, mkSzImm(ty, guest_CIA_curr_instr))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkSzImm(ty, 20))); - - putGST( PPC_GST_CIA, mkSzImm( ty, guest_CIA_bbstart + delta )); - dres.whatNext = Dis_StopHere; -- dres.jk_StopHere = Ijk_TInval; -+ dres.jk_StopHere = Ijk_InvalICache; - goto decode_success; - } - /* We don't know what it is. Set opc1/opc2 so decode_failure -Index: priv/guest_s390_helpers.c -=================================================================== ---- priv/guest_s390_helpers.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_s390_helpers.c (.../trunk) (revision 2863) -@@ -128,8 +128,8 @@ - /*------------------------------------------------------------*/ - - state->guest_NRADDR = 0; -- state->guest_TISTART = 0; -- state->guest_TILEN = 0; -+ state->guest_CMSTART = 0; -+ state->guest_CMLEN = 0; - state->guest_IP_AT_SYSCALL = 0; - state->guest_EMNOTE = EmNote_NONE; - state->host_EvC_COUNTER = 0; -@@ -225,8 +225,8 @@ - /* 0 */ ALWAYSDEFD(guest_CC_OP), /* generic */ - /* 1 */ ALWAYSDEFD(guest_CC_NDEP), /* generic */ - /* 2 */ ALWAYSDEFD(guest_EMNOTE), /* generic */ -- /* 3 */ ALWAYSDEFD(guest_TISTART), /* generic */ -- /* 4 */ ALWAYSDEFD(guest_TILEN), /* generic */ -+ /* 3 */ ALWAYSDEFD(guest_CMSTART), /* generic */ -+ /* 4 */ ALWAYSDEFD(guest_CMLEN), /* generic */ - /* 5 */ ALWAYSDEFD(guest_IP_AT_SYSCALL), /* generic */ - /* 6 */ ALWAYSDEFD(guest_IA), /* control reg */ - /* 7 */ ALWAYSDEFD(guest_fpc), /* control reg */ -Index: priv/guest_s390_toIR.c -=================================================================== ---- priv/guest_s390_toIR.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_s390_toIR.c (.../trunk) (revision 2863) -@@ -417,7 +417,8 @@ - { - vassert(typeOfIRExpr(irsb->tyenv, condition) == Ity_I1); - -- stmt(IRStmt_Exit(condition, Ijk_TInval, IRConst_U64(guest_IA_curr_instr), -+ stmt(IRStmt_Exit(condition, Ijk_InvalICache, -+ IRConst_U64(guest_IA_curr_instr), - S390X_GUEST_OFFSET(guest_IA))); - } - -@@ -7606,7 +7607,7 @@ - put_gpr_dw0(r1, binop(Iop_And64, mkexpr(op2), mkU64(mask))); - } - assign(result, get_gpr_dw0(r1)); -- s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); -+ s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result); - - return "risbg"; - } -@@ -10862,9 +10863,9 @@ - stmt(IRStmt_Dirty(d)); - - /* and restart */ -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART), -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART), - mkU64(guest_IA_curr_instr))); -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4))); -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN), mkU64(4))); - restart_if(mkexpr(cond)); - - ss.bytes = last_execute_target; -@@ -10893,15 +10894,15 @@ - mkIRExprVec_1(load(Ity_I64, mkexpr(addr2)))); - stmt(IRStmt_Dirty(d)); - /* and restart */ -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART), -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART), - mkU64(guest_IA_curr_instr))); -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4))); -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN), mkU64(4))); - restart_if(IRExpr_Const(IRConst_U1(True))); - - /* we know that this will be invalidated */ - put_IA(mkaddr_expr(guest_IA_next_instr)); - dis_res->whatNext = Dis_StopHere; -- dis_res->jk_StopHere = Ijk_TInval; -+ dis_res->jk_StopHere = Ijk_InvalICache; - break; - } - -@@ -10967,8 +10968,8 @@ - stmt(IRStmt_Dirty(d)); - - /* and restart */ -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART), mkU64(guest_IA_curr_instr))); -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), mkU64(4))); -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART), mkU64(guest_IA_curr_instr))); -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN), mkU64(4))); - restart_if(mkexpr(cond)); - - /* Now comes the actual translation */ -@@ -16362,9 +16363,9 @@ - injecting here can change. In which case the translation has to - be redone. For ease of handling, we simply invalidate all the - time. */ -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TISTART), -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMSTART), - mkU64(guest_IA_curr_instr))); -- stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_TILEN), -+ stmt(IRStmt_Put(S390X_GUEST_OFFSET(guest_CMLEN), - mkU64(guest_IA_next_instr - guest_IA_curr_instr))); - vassert(guest_IA_next_instr - guest_IA_curr_instr == - S390_SPECIAL_OP_PREAMBLE_SIZE + S390_SPECIAL_OP_SIZE); -@@ -16371,7 +16372,7 @@ - - put_IA(mkaddr_expr(guest_IA_next_instr)); - dis_res->whatNext = Dis_StopHere; -- dis_res->jk_StopHere = Ijk_TInval; -+ dis_res->jk_StopHere = Ijk_InvalICache; - } else { - /* We don't know what it is. */ - return S390_DECODE_UNKNOWN_SPECIAL_INSN; -Index: priv/guest_x86_helpers.c -=================================================================== ---- priv/guest_x86_helpers.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_x86_helpers.c (.../trunk) (revision 2863) -@@ -2757,18 +2757,14 @@ - vex_state->guest_EMNOTE = EmNote_NONE; - - /* SSE2 has a 'clflush' cache-line-invalidator which uses these. */ -- vex_state->guest_TISTART = 0; -- vex_state->guest_TILEN = 0; -+ vex_state->guest_CMSTART = 0; -+ vex_state->guest_CMLEN = 0; - - vex_state->guest_NRADDR = 0; - vex_state->guest_SC_CLASS = 0; - vex_state->guest_IP_AT_SYSCALL = 0; - -- Int i; -- for (i = 0; i < sizeof(vex_state->padding) -- / sizeof(vex_state->padding[0]); i++) { -- vex_state->padding[i] = 0; -- } -+ vex_state->padding1 = 0; - } - - -@@ -2866,8 +2862,8 @@ - /* 17 */ ALWAYSDEFD(guest_GDT), - /* 18 */ ALWAYSDEFD(guest_EMNOTE), - /* 19 */ ALWAYSDEFD(guest_SSEROUND), -- /* 20 */ ALWAYSDEFD(guest_TISTART), -- /* 21 */ ALWAYSDEFD(guest_TILEN), -+ /* 20 */ ALWAYSDEFD(guest_CMSTART), -+ /* 21 */ ALWAYSDEFD(guest_CMLEN), - /* 22 */ ALWAYSDEFD(guest_SC_CLASS), - /* 23 */ ALWAYSDEFD(guest_IP_AT_SYSCALL) - } -Index: priv/guest_x86_toIR.c -=================================================================== ---- priv/guest_x86_toIR.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/guest_x86_toIR.c (.../trunk) (revision 2863) -@@ -54,10 +54,6 @@ - for float-to-float rounding. For all other operations, - round-to-nearest is used, regardless. - -- * FP sin/cos/tan/sincos: C2 flag is always cleared. IOW the -- simulation claims the argument is in-range (-2^63 <= arg <= 2^63) -- even when it isn't. -- - * some of the FCOM cases could do with testing -- not convinced - that the args are the right way round. - -@@ -279,8 +275,8 @@ - - #define OFFB_EMNOTE offsetof(VexGuestX86State,guest_EMNOTE) - --#define OFFB_TISTART offsetof(VexGuestX86State,guest_TISTART) --#define OFFB_TILEN offsetof(VexGuestX86State,guest_TILEN) -+#define OFFB_CMSTART offsetof(VexGuestX86State,guest_CMSTART) -+#define OFFB_CMLEN offsetof(VexGuestX86State,guest_CMLEN) - #define OFFB_NRADDR offsetof(VexGuestX86State,guest_NRADDR) - - #define OFFB_IP_AT_SYSCALL offsetof(VexGuestX86State,guest_IP_AT_SYSCALL) -@@ -3603,6 +3599,42 @@ - } - - -+/* Given i, and some expression e, and a condition cond, generate IR -+ which has the same effect as put_ST(i,e) when cond is true and has -+ no effect when cond is false. Given the lack of proper -+ if-then-else in the IR, this is pretty tricky. -+*/ -+ -+static void maybe_put_ST ( IRTemp cond, Int i, IRExpr* value ) -+{ -+ // new_tag = if cond then FULL else old_tag -+ // new_val = if cond then (if old_tag==FULL then NaN else val) -+ // else old_val -+ -+ IRTemp old_tag = newTemp(Ity_I8); -+ assign(old_tag, get_ST_TAG(i)); -+ IRTemp new_tag = newTemp(Ity_I8); -+ assign(new_tag, -+ IRExpr_ITE(mkexpr(cond), mkU8(1)/*FULL*/, mkexpr(old_tag))); -+ -+ IRTemp old_val = newTemp(Ity_F64); -+ assign(old_val, get_ST_UNCHECKED(i)); -+ IRTemp new_val = newTemp(Ity_F64); -+ assign(new_val, -+ IRExpr_ITE(mkexpr(cond), -+ IRExpr_ITE(binop(Iop_CmpNE8, mkexpr(old_tag), mkU8(0)), -+ /* non-0 means full */ -+ mkQNaN64(), -+ /* 0 means empty */ -+ value), -+ mkexpr(old_val))); -+ -+ put_ST_UNCHECKED(i, mkexpr(new_val)); -+ // put_ST_UNCHECKED incorrectly sets tag(i) to always be FULL. So -+ // now set it to new_tag instead. -+ put_ST_TAG(i, mkexpr(new_tag)); -+} -+ - /* Adjust FTOP downwards by one register. */ - - static void fp_push ( void ) -@@ -3610,6 +3642,14 @@ - put_ftop( binop(Iop_Sub32, get_ftop(), mkU32(1)) ); - } - -+/* Adjust FTOP downwards by one register when COND is 1:I1. Else -+ don't change it. */ -+ -+static void maybe_fp_push ( IRTemp cond ) -+{ -+ put_ftop( binop(Iop_Sub32, get_ftop(), unop(Iop_1Uto32,mkexpr(cond))) ); -+} -+ - /* Adjust FTOP upwards by one register, and mark the vacated register - as empty. */ - -@@ -3619,12 +3659,49 @@ - put_ftop( binop(Iop_Add32, get_ftop(), mkU32(1)) ); - } - --/* Clear the C2 bit of the FPU status register, for -- sin/cos/tan/sincos. */ -+/* Set the C2 bit of the FPU status register to e[0]. Assumes that -+ e[31:1] == 0. -+*/ -+static void set_C2 ( IRExpr* e ) -+{ -+ IRExpr* cleared = binop(Iop_And32, get_C3210(), mkU32(~X86G_FC_MASK_C2)); -+ put_C3210( binop(Iop_Or32, -+ cleared, -+ binop(Iop_Shl32, e, mkU8(X86G_FC_SHIFT_C2))) ); -+} - --static void clear_C2 ( void ) -+/* Generate code to check that abs(d64) < 2^63 and is finite. This is -+ used to do the range checks for FSIN, FCOS, FSINCOS and FPTAN. The -+ test is simple, but the derivation of it is not so simple. -+ -+ The exponent field for an IEEE754 double is 11 bits. That means it -+ can take values 0 through 0x7FF. If the exponent has value 0x7FF, -+ the number is either a NaN or an Infinity and so is not finite. -+ Furthermore, a finite value of exactly 2^63 is the smallest value -+ that has exponent value 0x43E. Hence, what we need to do is -+ extract the exponent, ignoring the sign bit and mantissa, and check -+ it is < 0x43E, or <= 0x43D. -+ -+ To make this easily applicable to 32- and 64-bit targets, a -+ roundabout approach is used. First the number is converted to I64, -+ then the top 32 bits are taken. Shifting them right by 20 bits -+ places the sign bit and exponent in the bottom 12 bits. Anding -+ with 0x7FF gets rid of the sign bit, leaving just the exponent -+ available for comparison. -+*/ -+static IRTemp math_IS_TRIG_ARG_FINITE_AND_IN_RANGE ( IRTemp d64 ) - { -- put_C3210( binop(Iop_And32, get_C3210(), mkU32(~X86G_FC_MASK_C2)) ); -+ IRTemp i64 = newTemp(Ity_I64); -+ assign(i64, unop(Iop_ReinterpF64asI64, mkexpr(d64)) ); -+ IRTemp exponent = newTemp(Ity_I32); -+ assign(exponent, -+ binop(Iop_And32, -+ binop(Iop_Shr32, unop(Iop_64HIto32, mkexpr(i64)), mkU8(20)), -+ mkU32(0x7FF))); -+ IRTemp in_range_and_finite = newTemp(Ity_I1); -+ assign(in_range_and_finite, -+ binop(Iop_CmpLE32U, mkexpr(exponent), mkU32(0x43D))); -+ return in_range_and_finite; - } - - /* Invent a plausible-looking FPU status word value: -@@ -4245,16 +4322,31 @@ - fp_pop(); - break; - -- case 0xF2: /* FPTAN */ -- DIP("ftan\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_TanF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- get_ST(0))); -- fp_push(); -- put_ST(0, IRExpr_Const(IRConst_F64(1.0))); -- clear_C2(); /* HACK */ -+ case 0xF2: { /* FPTAN */ -+ DIP("fptan\n"); -+ IRTemp argD = newTemp(Ity_F64); -+ assign(argD, get_ST(0)); -+ IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); -+ IRTemp resD = newTemp(Ity_F64); -+ assign(resD, -+ IRExpr_ITE( -+ mkexpr(argOK), -+ binop(Iop_TanF64, -+ get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ mkexpr(argD)), -+ mkexpr(argD)) -+ ); -+ put_ST_UNCHECKED(0, mkexpr(resD)); -+ /* Conditionally push 1.0 on the stack, if the arg is -+ in range */ -+ maybe_fp_push(argOK); -+ maybe_put_ST(argOK, 0, -+ IRExpr_Const(IRConst_F64(1.0))); -+ set_C2( binop(Iop_Xor32, -+ unop(Iop_1Uto32, mkexpr(argOK)), -+ mkU32(1)) ); - break; -+ } - - case 0xF3: /* FPATAN */ - DIP("fpatan\n"); -@@ -4368,19 +4460,30 @@ - break; - - case 0xFB: { /* FSINCOS */ -- IRTemp a1 = newTemp(Ity_F64); -- assign( a1, get_ST(0) ); - DIP("fsincos\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_SinF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- mkexpr(a1))); -- fp_push(); -- put_ST(0, -+ IRTemp argD = newTemp(Ity_F64); -+ assign(argD, get_ST(0)); -+ IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); -+ IRTemp resD = newTemp(Ity_F64); -+ assign(resD, -+ IRExpr_ITE( -+ mkexpr(argOK), -+ binop(Iop_SinF64, -+ get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ mkexpr(argD)), -+ mkexpr(argD)) -+ ); -+ put_ST_UNCHECKED(0, mkexpr(resD)); -+ /* Conditionally push the cos value on the stack, if -+ the arg is in range */ -+ maybe_fp_push(argOK); -+ maybe_put_ST(argOK, 0, - binop(Iop_CosF64, - get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- mkexpr(a1))); -- clear_C2(); /* HACK */ -+ mkexpr(argD))); -+ set_C2( binop(Iop_Xor32, -+ unop(Iop_1Uto32, mkexpr(argOK)), -+ mkU32(1)) ); - break; - } - -@@ -4399,24 +4502,29 @@ - get_ST(1))); - break; - -- case 0xFE: /* FSIN */ -- DIP("fsin\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_SinF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- get_ST(0))); -- clear_C2(); /* HACK */ -+ case 0xFE: /* FSIN */ -+ case 0xFF: { /* FCOS */ -+ Bool isSIN = modrm == 0xFE; -+ DIP("%s\n", isSIN ? "fsin" : "fcos"); -+ IRTemp argD = newTemp(Ity_F64); -+ assign(argD, get_ST(0)); -+ IRTemp argOK = math_IS_TRIG_ARG_FINITE_AND_IN_RANGE(argD); -+ IRTemp resD = newTemp(Ity_F64); -+ assign(resD, -+ IRExpr_ITE( -+ mkexpr(argOK), -+ binop(isSIN ? Iop_SinF64 : Iop_CosF64, -+ get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ mkexpr(argD)), -+ mkexpr(argD)) -+ ); -+ put_ST_UNCHECKED(0, mkexpr(resD)); -+ set_C2( binop(Iop_Xor32, -+ unop(Iop_1Uto32, mkexpr(argOK)), -+ mkU32(1)) ); - break; -+ } - -- case 0xFF: /* FCOS */ -- DIP("fcos\n"); -- put_ST_UNCHECKED(0, -- binop(Iop_CosF64, -- get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -- get_ST(0))); -- clear_C2(); /* HACK */ -- break; -- - default: - goto decode_fail; - } -@@ -6856,6 +6964,27 @@ - /*--- SSE/SSE2/SSE3 helpers ---*/ - /*------------------------------------------------------------*/ - -+/* Indicates whether the op requires a rounding-mode argument. Note -+ that this covers only vector floating point arithmetic ops, and -+ omits the scalar ones that need rounding modes. Note also that -+ inconsistencies here will get picked up later by the IR sanity -+ checker, so this isn't correctness-critical. */ -+static Bool requiresRMode ( IROp op ) -+{ -+ switch (op) { -+ /* 128 bit ops */ -+ case Iop_Add32Fx4: case Iop_Sub32Fx4: -+ case Iop_Mul32Fx4: case Iop_Div32Fx4: -+ case Iop_Add64Fx2: case Iop_Sub64Fx2: -+ case Iop_Mul64Fx2: case Iop_Div64Fx2: -+ return True; -+ default: -+ break; -+ } -+ return False; -+} -+ -+ - /* Worker function; do not call directly. - Handles full width G = G `op` E and G = (not G) `op` E. - */ -@@ -6874,9 +7003,15 @@ - = invertG ? unop(Iop_NotV128, getXMMReg(gregOfRM(rm))) - : getXMMReg(gregOfRM(rm)); - if (epartIsReg(rm)) { -- putXMMReg( gregOfRM(rm), -- binop(op, gpart, -- getXMMReg(eregOfRM(rm))) ); -+ putXMMReg( -+ gregOfRM(rm), -+ requiresRMode(op) -+ ? triop(op, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ gpart, -+ getXMMReg(eregOfRM(rm))) -+ : binop(op, gpart, -+ getXMMReg(eregOfRM(rm))) -+ ); - DIP("%s %s,%s\n", opname, - nameXMMReg(eregOfRM(rm)), - nameXMMReg(gregOfRM(rm)) ); -@@ -6883,9 +7018,15 @@ - return delta+1; - } else { - addr = disAMode ( &alen, sorb, delta, dis_buf ); -- putXMMReg( gregOfRM(rm), -- binop(op, gpart, -- loadLE(Ity_V128, mkexpr(addr))) ); -+ putXMMReg( -+ gregOfRM(rm), -+ requiresRMode(op) -+ ? triop(op, get_FAKE_roundingmode(), /* XXXROUNDINGFIXME */ -+ gpart, -+ loadLE(Ity_V128, mkexpr(addr))) -+ : binop(op, gpart, -+ loadLE(Ity_V128, mkexpr(addr))) -+ ); - DIP("%s %s,%s\n", opname, - dis_buf, - nameXMMReg(gregOfRM(rm)) ); -@@ -8026,14 +8167,14 @@ - // injecting here can change. In which case the translation has to - // be redone. For ease of handling, we simply invalidate all the - // time. -- stmt(IRStmt_Put(OFFB_TISTART, mkU32(guest_EIP_curr_instr))); -- stmt(IRStmt_Put(OFFB_TILEN, mkU32(14))); -+ stmt(IRStmt_Put(OFFB_CMSTART, mkU32(guest_EIP_curr_instr))); -+ stmt(IRStmt_Put(OFFB_CMLEN, mkU32(14))); - - delta += 14; - - stmt( IRStmt_Put( OFFB_EIP, mkU32(guest_EIP_bbstart + delta) ) ); - dres.whatNext = Dis_StopHere; -- dres.jk_StopHere = Ijk_TInval; -+ dres.jk_StopHere = Ijk_InvalICache; - goto decode_success; - } - /* We don't know what it is. */ -@@ -11613,14 +11754,14 @@ - - /* Round addr down to the start of the containing block. */ - stmt( IRStmt_Put( -- OFFB_TISTART, -+ OFFB_CMSTART, - binop( Iop_And32, - mkexpr(addr), - mkU32( ~(lineszB-1) ))) ); - -- stmt( IRStmt_Put(OFFB_TILEN, mkU32(lineszB) ) ); -+ stmt( IRStmt_Put(OFFB_CMLEN, mkU32(lineszB) ) ); - -- jmp_lit(&dres, Ijk_TInval, (Addr32)(guest_EIP_bbstart+delta)); -+ jmp_lit(&dres, Ijk_InvalICache, (Addr32)(guest_EIP_bbstart+delta)); - - DIP("clflush %s\n", dis_buf); - goto decode_success; -@@ -11712,6 +11853,7 @@ - IRTemp gV = newTemp(Ity_V128); - IRTemp addV = newTemp(Ity_V128); - IRTemp subV = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); - a3 = a2 = a1 = a0 = s3 = s2 = s1 = s0 = IRTemp_INVALID; - - modrm = insn[3]; -@@ -11730,8 +11872,9 @@ - - assign( gV, getXMMReg(gregOfRM(modrm)) ); - -- assign( addV, binop(Iop_Add32Fx4, mkexpr(gV), mkexpr(eV)) ); -- assign( subV, binop(Iop_Sub32Fx4, mkexpr(gV), mkexpr(eV)) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( addV, triop(Iop_Add32Fx4, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); -+ assign( subV, triop(Iop_Sub32Fx4, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); - - breakup128to32s( addV, &a3, &a2, &a1, &a0 ); - breakup128to32s( subV, &s3, &s2, &s1, &s0 ); -@@ -11748,6 +11891,7 @@ - IRTemp subV = newTemp(Ity_V128); - IRTemp a1 = newTemp(Ity_I64); - IRTemp s0 = newTemp(Ity_I64); -+ IRTemp rm = newTemp(Ity_I32); - - modrm = insn[2]; - if (epartIsReg(modrm)) { -@@ -11765,8 +11909,9 @@ - - assign( gV, getXMMReg(gregOfRM(modrm)) ); - -- assign( addV, binop(Iop_Add64Fx2, mkexpr(gV), mkexpr(eV)) ); -- assign( subV, binop(Iop_Sub64Fx2, mkexpr(gV), mkexpr(eV)) ); -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ -+ assign( addV, triop(Iop_Add64Fx2, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); -+ assign( subV, triop(Iop_Sub64Fx2, mkexpr(rm), mkexpr(gV), mkexpr(eV)) ); - - assign( a1, unop(Iop_V128HIto64, mkexpr(addV) )); - assign( s0, unop(Iop_V128to64, mkexpr(subV) )); -@@ -11785,6 +11930,7 @@ - IRTemp gV = newTemp(Ity_V128); - IRTemp leftV = newTemp(Ity_V128); - IRTemp rightV = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); - Bool isAdd = insn[2] == 0x7C; - const HChar* str = isAdd ? "add" : "sub"; - e3 = e2 = e1 = e0 = g3 = g2 = g1 = g0 = IRTemp_INVALID; -@@ -11811,9 +11957,10 @@ - assign( leftV, mk128from32s( e2, e0, g2, g0 ) ); - assign( rightV, mk128from32s( e3, e1, g3, g1 ) ); - -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ - putXMMReg( gregOfRM(modrm), -- binop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, -- mkexpr(leftV), mkexpr(rightV) ) ); -+ triop(isAdd ? Iop_Add32Fx4 : Iop_Sub32Fx4, -+ mkexpr(rm), mkexpr(leftV), mkexpr(rightV) ) ); - goto decode_success; - } - -@@ -11828,6 +11975,7 @@ - IRTemp gV = newTemp(Ity_V128); - IRTemp leftV = newTemp(Ity_V128); - IRTemp rightV = newTemp(Ity_V128); -+ IRTemp rm = newTemp(Ity_I32); - Bool isAdd = insn[1] == 0x7C; - const HChar* str = isAdd ? "add" : "sub"; - -@@ -11855,9 +12003,10 @@ - assign( leftV, binop(Iop_64HLtoV128, mkexpr(e0),mkexpr(g0)) ); - assign( rightV, binop(Iop_64HLtoV128, mkexpr(e1),mkexpr(g1)) ); - -+ assign( rm, get_FAKE_roundingmode() ); /* XXXROUNDINGFIXME */ - putXMMReg( gregOfRM(modrm), -- binop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, -- mkexpr(leftV), mkexpr(rightV) ) ); -+ triop(isAdd ? Iop_Add64Fx2 : Iop_Sub64Fx2, -+ mkexpr(rm), mkexpr(leftV), mkexpr(rightV) ) ); - goto decode_success; - } - -@@ -15181,6 +15330,14 @@ - break; - } - -+ case 0x05: /* AMD's syscall */ -+ stmt( IRStmt_Put( OFFB_IP_AT_SYSCALL, -+ mkU32(guest_EIP_curr_instr) ) ); -+ jmp_lit(&dres, Ijk_Sys_syscall, ((Addr32)guest_EIP_bbstart)+delta); -+ vassert(dres.whatNext == Dis_StopHere); -+ DIP("syscall\n"); -+ break; -+ - /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */ - - default: -Index: priv/host_amd64_defs.c -=================================================================== ---- priv/host_amd64_defs.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_amd64_defs.c (.../trunk) (revision 2863) -@@ -2865,7 +2865,7 @@ - case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; - case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; - case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; -+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; - case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; - case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; - case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; -@@ -3069,7 +3069,6 @@ - case Afp_SQRT: *p++ = 0xD9; *p++ = 0xFA; break; - case Afp_SIN: *p++ = 0xD9; *p++ = 0xFE; break; - case Afp_COS: *p++ = 0xD9; *p++ = 0xFF; break; -- case Afp_TAN: *p++ = 0xD9; *p++ = 0xF2; break; - case Afp_ROUND: *p++ = 0xD9; *p++ = 0xFC; break; - case Afp_2XM1: *p++ = 0xD9; *p++ = 0xF0; break; - case Afp_SCALE: *p++ = 0xD9; *p++ = 0xFD; break; -@@ -3078,7 +3077,24 @@ - case Afp_YL2XP1: *p++ = 0xD9; *p++ = 0xF9; break; - case Afp_PREM: *p++ = 0xD9; *p++ = 0xF8; break; - case Afp_PREM1: *p++ = 0xD9; *p++ = 0xF5; break; -- default: goto bad; -+ case Afp_TAN: -+ /* fptan pushes 1.0 on the FP stack, except when the -+ argument is out of range. Hence we have to do the -+ instruction, then inspect C2 to see if there is an out -+ of range condition. If there is, we skip the fincstp -+ that is used by the in-range case to get rid of this -+ extra 1.0 value. */ -+ *p++ = 0xD9; *p++ = 0xF2; // fptan -+ *p++ = 0x50; // pushq %rax -+ *p++ = 0xDF; *p++ = 0xE0; // fnstsw %ax -+ *p++ = 0x66; *p++ = 0xA9; -+ *p++ = 0x00; *p++ = 0x04; // testw $0x400,%ax -+ *p++ = 0x75; *p++ = 0x02; // jnz after_fincstp -+ *p++ = 0xD9; *p++ = 0xF7; // fincstp -+ *p++ = 0x58; // after_fincstp: popq %rax -+ break; -+ default: -+ goto bad; - } - goto done; - -Index: priv/host_amd64_isel.c -=================================================================== ---- priv/host_amd64_isel.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_amd64_isel.c (.../trunk) (revision 2863) -@@ -3031,11 +3031,12 @@ - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8)); - /* XXXROUNDINGFIXME */ - /* set roundingmode here */ -+ /* Note that AMD64Instr_A87FpOp(Afp_TAN) sets the condition -+ codes. I don't think that matters, since this insn -+ selector never generates such an instruction intervening -+ between an flag-setting instruction and a flag-using -+ instruction. */ - addInstr(env, AMD64Instr_A87FpOp(fpop)); -- if (e->Iex.Binop.op==Iop_TanF64) { -- /* get rid of the extra 1.0 that fptan pushes */ -- addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8)); -- } - addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8)); - addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp)); - return dst; -@@ -3355,12 +3356,8 @@ - case Iop_CmpLT32Fx4: op = Asse_CMPLTF; goto do_32Fx4; - case Iop_CmpLE32Fx4: op = Asse_CMPLEF; goto do_32Fx4; - case Iop_CmpUN32Fx4: op = Asse_CMPUNF; goto do_32Fx4; -- case Iop_Add32Fx4: op = Asse_ADDF; goto do_32Fx4; -- case Iop_Div32Fx4: op = Asse_DIVF; goto do_32Fx4; - case Iop_Max32Fx4: op = Asse_MAXF; goto do_32Fx4; - case Iop_Min32Fx4: op = Asse_MINF; goto do_32Fx4; -- case Iop_Mul32Fx4: op = Asse_MULF; goto do_32Fx4; -- case Iop_Sub32Fx4: op = Asse_SUBF; goto do_32Fx4; - do_32Fx4: - { - HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); -@@ -3375,12 +3372,8 @@ - case Iop_CmpLT64Fx2: op = Asse_CMPLTF; goto do_64Fx2; - case Iop_CmpLE64Fx2: op = Asse_CMPLEF; goto do_64Fx2; - case Iop_CmpUN64Fx2: op = Asse_CMPUNF; goto do_64Fx2; -- case Iop_Add64Fx2: op = Asse_ADDF; goto do_64Fx2; -- case Iop_Div64Fx2: op = Asse_DIVF; goto do_64Fx2; - case Iop_Max64Fx2: op = Asse_MAXF; goto do_64Fx2; - case Iop_Min64Fx2: op = Asse_MINF; goto do_64Fx2; -- case Iop_Mul64Fx2: op = Asse_MULF; goto do_64Fx2; -- case Iop_Sub64Fx2: op = Asse_SUBF; goto do_64Fx2; - do_64Fx2: - { - HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); -@@ -3660,6 +3653,47 @@ - } /* switch (e->Iex.Binop.op) */ - } /* if (e->tag == Iex_Binop) */ - -+ if (e->tag == Iex_Triop) { -+ IRTriop *triop = e->Iex.Triop.details; -+ switch (triop->op) { -+ -+ case Iop_Add64Fx2: op = Asse_ADDF; goto do_64Fx2_w_rm; -+ case Iop_Sub64Fx2: op = Asse_SUBF; goto do_64Fx2_w_rm; -+ case Iop_Mul64Fx2: op = Asse_MULF; goto do_64Fx2_w_rm; -+ case Iop_Div64Fx2: op = Asse_DIVF; goto do_64Fx2_w_rm; -+ do_64Fx2_w_rm: -+ { -+ HReg argL = iselVecExpr(env, triop->arg2); -+ HReg argR = iselVecExpr(env, triop->arg3); -+ HReg dst = newVRegV(env); -+ addInstr(env, mk_vMOVsd_RR(argL, dst)); -+ /* XXXROUNDINGFIXME */ -+ /* set roundingmode here */ -+ addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst)); -+ return dst; -+ } -+ -+ case Iop_Add32Fx4: op = Asse_ADDF; goto do_32Fx4_w_rm; -+ case Iop_Sub32Fx4: op = Asse_SUBF; goto do_32Fx4_w_rm; -+ case Iop_Mul32Fx4: op = Asse_MULF; goto do_32Fx4_w_rm; -+ case Iop_Div32Fx4: op = Asse_DIVF; goto do_32Fx4_w_rm; -+ do_32Fx4_w_rm: -+ { -+ HReg argL = iselVecExpr(env, triop->arg2); -+ HReg argR = iselVecExpr(env, triop->arg3); -+ HReg dst = newVRegV(env); -+ addInstr(env, mk_vMOVsd_RR(argL, dst)); -+ /* XXXROUNDINGFIXME */ -+ /* set roundingmode here */ -+ addInstr(env, AMD64Instr_Sse32Fx4(op, argR, dst)); -+ return dst; -+ } -+ -+ default: -+ break; -+ } /* switch (triop->op) */ -+ } /* if (e->tag == Iex_Triop) */ -+ - if (e->tag == Iex_ITE) { // VFD - HReg r1 = iselVecExpr(env, e->Iex.ITE.iftrue); - HReg r0 = iselVecExpr(env, e->Iex.ITE.iffalse); -@@ -3851,10 +3885,6 @@ - if (e->tag == Iex_Binop) { - switch (e->Iex.Binop.op) { - -- case Iop_Add64Fx4: op = Asse_ADDF; goto do_64Fx4; -- case Iop_Sub64Fx4: op = Asse_SUBF; goto do_64Fx4; -- case Iop_Mul64Fx4: op = Asse_MULF; goto do_64Fx4; -- case Iop_Div64Fx4: op = Asse_DIVF; goto do_64Fx4; - case Iop_Max64Fx4: op = Asse_MAXF; goto do_64Fx4; - case Iop_Min64Fx4: op = Asse_MINF; goto do_64Fx4; - do_64Fx4: -@@ -3873,10 +3903,6 @@ - return; - } - -- case Iop_Add32Fx8: op = Asse_ADDF; goto do_32Fx8; -- case Iop_Sub32Fx8: op = Asse_SUBF; goto do_32Fx8; -- case Iop_Mul32Fx8: op = Asse_MULF; goto do_32Fx8; -- case Iop_Div32Fx8: op = Asse_DIVF; goto do_32Fx8; - case Iop_Max32Fx8: op = Asse_MAXF; goto do_32Fx8; - case Iop_Min32Fx8: op = Asse_MINF; goto do_32Fx8; - do_32Fx8: -@@ -4145,6 +4171,60 @@ - } /* switch (e->Iex.Binop.op) */ - } /* if (e->tag == Iex_Binop) */ - -+ if (e->tag == Iex_Triop) { -+ IRTriop *triop = e->Iex.Triop.details; -+ switch (triop->op) { -+ -+ case Iop_Add64Fx4: op = Asse_ADDF; goto do_64Fx4_w_rm; -+ case Iop_Sub64Fx4: op = Asse_SUBF; goto do_64Fx4_w_rm; -+ case Iop_Mul64Fx4: op = Asse_MULF; goto do_64Fx4_w_rm; -+ case Iop_Div64Fx4: op = Asse_DIVF; goto do_64Fx4_w_rm; -+ do_64Fx4_w_rm: -+ { -+ HReg argLhi, argLlo, argRhi, argRlo; -+ iselDVecExpr(&argLhi, &argLlo, env, triop->arg2); -+ iselDVecExpr(&argRhi, &argRlo, env, triop->arg3); -+ HReg dstHi = newVRegV(env); -+ HReg dstLo = newVRegV(env); -+ addInstr(env, mk_vMOVsd_RR(argLhi, dstHi)); -+ addInstr(env, mk_vMOVsd_RR(argLlo, dstLo)); -+ /* XXXROUNDINGFIXME */ -+ /* set roundingmode here */ -+ addInstr(env, AMD64Instr_Sse64Fx2(op, argRhi, dstHi)); -+ addInstr(env, AMD64Instr_Sse64Fx2(op, argRlo, dstLo)); -+ *rHi = dstHi; -+ *rLo = dstLo; -+ return; -+ } -+ -+ case Iop_Add32Fx8: op = Asse_ADDF; goto do_32Fx8_w_rm; -+ case Iop_Sub32Fx8: op = Asse_SUBF; goto do_32Fx8_w_rm; -+ case Iop_Mul32Fx8: op = Asse_MULF; goto do_32Fx8_w_rm; -+ case Iop_Div32Fx8: op = Asse_DIVF; goto do_32Fx8_w_rm; -+ do_32Fx8_w_rm: -+ { -+ HReg argLhi, argLlo, argRhi, argRlo; -+ iselDVecExpr(&argLhi, &argLlo, env, triop->arg2); -+ iselDVecExpr(&argRhi, &argRlo, env, triop->arg3); -+ HReg dstHi = newVRegV(env); -+ HReg dstLo = newVRegV(env); -+ addInstr(env, mk_vMOVsd_RR(argLhi, dstHi)); -+ addInstr(env, mk_vMOVsd_RR(argLlo, dstLo)); -+ /* XXXROUNDINGFIXME */ -+ /* set roundingmode here */ -+ addInstr(env, AMD64Instr_Sse32Fx4(op, argRhi, dstHi)); -+ addInstr(env, AMD64Instr_Sse32Fx4(op, argRlo, dstLo)); -+ *rHi = dstHi; -+ *rLo = dstLo; -+ return; -+ } -+ -+ default: -+ break; -+ } /* switch (triop->op) */ -+ } /* if (e->tag == Iex_Triop) */ -+ -+ - if (e->tag == Iex_Qop && e->Iex.Qop.details->op == Iop_64x4toV256) { - HReg rsp = hregAMD64_RSP(); - HReg vHi = newVRegV(env); -@@ -4649,7 +4729,7 @@ - case Ijk_SigSEGV: - case Ijk_SigTRAP: - case Ijk_Sys_syscall: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Yield: - { - HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -@@ -4744,7 +4824,7 @@ - case Ijk_SigSEGV: - case Ijk_SigTRAP: - case Ijk_Sys_syscall: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Yield: { - HReg r = iselIntExpr_R(env, next); - AMD64AMode* amRIP = AMD64AMode_IR(offsIP, hregAMD64_RBP()); -Index: priv/host_arm64_defs.c -=================================================================== ---- priv/host_arm64_defs.c (.../tags/VEX_3_9_0) (revision 0) -+++ priv/host_arm64_defs.c (.../trunk) (revision 2863) -@@ -0,0 +1,6609 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin host_arm64_defs.c ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "libvex_basictypes.h" -+#include "libvex.h" -+#include "libvex_trc_values.h" -+ -+#include "main_util.h" -+#include "host_generic_regs.h" -+#include "host_arm64_defs.h" -+ -+//ZZ UInt arm_hwcaps = 0; -+ -+ -+/* --------- Registers. --------- */ -+ -+/* The usual HReg abstraction. We use the following classes only: -+ X regs (64 bit int) -+ D regs (64 bit float, also used for 32 bit float) -+ Q regs (128 bit vector) -+*/ -+ -+void ppHRegARM64 ( HReg reg ) { -+ Int r; -+ /* Be generic for all virtual regs. */ -+ if (hregIsVirtual(reg)) { -+ ppHReg(reg); -+ return; -+ } -+ /* But specific for real regs. */ -+ switch (hregClass(reg)) { -+ case HRcInt64: -+ r = hregNumber(reg); -+ vassert(r >= 0 && r < 31); -+ vex_printf("x%d", r); -+ return; -+ case HRcFlt64: -+ r = hregNumber(reg); -+ vassert(r >= 0 && r < 32); -+ vex_printf("d%d", r); -+ return; -+ case HRcVec128: -+ r = hregNumber(reg); -+ vassert(r >= 0 && r < 32); -+ vex_printf("q%d", r); -+ return; -+ default: -+ vpanic("ppHRegARM64"); -+ } -+} -+ -+static void ppHRegARM64asSreg ( HReg reg ) { -+ ppHRegARM64(reg); -+ vex_printf("(S-reg)"); -+} -+ -+HReg hregARM64_X0 ( void ) { return mkHReg(0, HRcInt64, False); } -+HReg hregARM64_X1 ( void ) { return mkHReg(1, HRcInt64, False); } -+HReg hregARM64_X2 ( void ) { return mkHReg(2, HRcInt64, False); } -+HReg hregARM64_X3 ( void ) { return mkHReg(3, HRcInt64, False); } -+HReg hregARM64_X4 ( void ) { return mkHReg(4, HRcInt64, False); } -+HReg hregARM64_X5 ( void ) { return mkHReg(5, HRcInt64, False); } -+HReg hregARM64_X6 ( void ) { return mkHReg(6, HRcInt64, False); } -+HReg hregARM64_X7 ( void ) { return mkHReg(7, HRcInt64, False); } -+//ZZ HReg hregARM_R8 ( void ) { return mkHReg(8, HRcInt32, False); } -+HReg hregARM64_X9 ( void ) { return mkHReg(9, HRcInt64, False); } -+HReg hregARM64_X10 ( void ) { return mkHReg(10, HRcInt64, False); } -+HReg hregARM64_X11 ( void ) { return mkHReg(11, HRcInt64, False); } -+HReg hregARM64_X12 ( void ) { return mkHReg(12, HRcInt64, False); } -+HReg hregARM64_X13 ( void ) { return mkHReg(13, HRcInt64, False); } -+HReg hregARM64_X14 ( void ) { return mkHReg(14, HRcInt64, False); } -+HReg hregARM64_X15 ( void ) { return mkHReg(15, HRcInt64, False); } -+HReg hregARM64_X21 ( void ) { return mkHReg(21, HRcInt64, False); } -+HReg hregARM64_X22 ( void ) { return mkHReg(22, HRcInt64, False); } -+HReg hregARM64_X23 ( void ) { return mkHReg(23, HRcInt64, False); } -+HReg hregARM64_X24 ( void ) { return mkHReg(24, HRcInt64, False); } -+HReg hregARM64_X25 ( void ) { return mkHReg(25, HRcInt64, False); } -+HReg hregARM64_X26 ( void ) { return mkHReg(26, HRcInt64, False); } -+HReg hregARM64_X27 ( void ) { return mkHReg(27, HRcInt64, False); } -+HReg hregARM64_X28 ( void ) { return mkHReg(28, HRcInt64, False); } -+ -+// Should really use D8 .. D15 for class F64, since they are callee -+// save -+HReg hregARM64_D8 ( void ) { return mkHReg(8, HRcFlt64, False); } -+HReg hregARM64_D9 ( void ) { return mkHReg(9, HRcFlt64, False); } -+HReg hregARM64_D10 ( void ) { return mkHReg(10, HRcFlt64, False); } -+HReg hregARM64_D11 ( void ) { return mkHReg(11, HRcFlt64, False); } -+HReg hregARM64_D12 ( void ) { return mkHReg(12, HRcFlt64, False); } -+HReg hregARM64_D13 ( void ) { return mkHReg(13, HRcFlt64, False); } -+//ZZ HReg hregARM_S26 ( void ) { return mkHReg(26, HRcFlt32, False); } -+//ZZ HReg hregARM_S27 ( void ) { return mkHReg(27, HRcFlt32, False); } -+//ZZ HReg hregARM_S28 ( void ) { return mkHReg(28, HRcFlt32, False); } -+//ZZ HReg hregARM_S29 ( void ) { return mkHReg(29, HRcFlt32, False); } -+//ZZ HReg hregARM_S30 ( void ) { return mkHReg(30, HRcFlt32, False); } -+HReg hregARM64_Q16 ( void ) { return mkHReg(16, HRcVec128, False); } -+HReg hregARM64_Q17 ( void ) { return mkHReg(17, HRcVec128, False); } -+HReg hregARM64_Q18 ( void ) { return mkHReg(18, HRcVec128, False); } -+//ZZ HReg hregARM_Q11 ( void ) { return mkHReg(11, HRcVec128, False); } -+//ZZ HReg hregARM_Q12 ( void ) { return mkHReg(12, HRcVec128, False); } -+//ZZ HReg hregARM_Q13 ( void ) { return mkHReg(13, HRcVec128, False); } -+//ZZ HReg hregARM_Q14 ( void ) { return mkHReg(14, HRcVec128, False); } -+//ZZ HReg hregARM_Q15 ( void ) { return mkHReg(15, HRcVec128, False); } -+ -+void getAllocableRegs_ARM64 ( Int* nregs, HReg** arr ) -+{ -+ Int i = 0; -+ *nregs = 24; -+ *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); -+ -+ // callee saves ones (22 to 28) are listed first, since we prefer -+ // them if they're available -+ (*arr)[i++] = hregARM64_X22(); -+ (*arr)[i++] = hregARM64_X23(); -+ (*arr)[i++] = hregARM64_X24(); -+ (*arr)[i++] = hregARM64_X25(); -+ (*arr)[i++] = hregARM64_X26(); -+ (*arr)[i++] = hregARM64_X27(); -+ (*arr)[i++] = hregARM64_X28(); -+ -+ (*arr)[i++] = hregARM64_X0(); -+ (*arr)[i++] = hregARM64_X1(); -+ (*arr)[i++] = hregARM64_X2(); -+ (*arr)[i++] = hregARM64_X3(); -+ (*arr)[i++] = hregARM64_X4(); -+ (*arr)[i++] = hregARM64_X5(); -+ (*arr)[i++] = hregARM64_X6(); -+ (*arr)[i++] = hregARM64_X7(); -+ // X8 .. who knows. -+ // X9 is a chaining/spill temporary, not available to regalloc. -+ -+ // Do we really need all these? -+ //(*arr)[i++] = hregARM64_X10(); -+ //(*arr)[i++] = hregARM64_X11(); -+ //(*arr)[i++] = hregARM64_X12(); -+ //(*arr)[i++] = hregARM64_X13(); -+ //(*arr)[i++] = hregARM64_X14(); -+ //(*arr)[i++] = hregARM64_X15(); -+ // X21 is the guest state pointer, not available to regalloc. -+ -+ // vector regs. Unfortunately not callee-saved. -+ (*arr)[i++] = hregARM64_Q16(); -+ (*arr)[i++] = hregARM64_Q17(); -+ (*arr)[i++] = hregARM64_Q18(); -+ -+ // F64 regs, all of which are callee-saved -+ (*arr)[i++] = hregARM64_D8(); -+ (*arr)[i++] = hregARM64_D9(); -+ (*arr)[i++] = hregARM64_D10(); -+ (*arr)[i++] = hregARM64_D11(); -+ (*arr)[i++] = hregARM64_D12(); -+ (*arr)[i++] = hregARM64_D13(); -+ -+ // unavail: x21 as GSP -+ // x9 is used as a spill/reload/chaining/call temporary -+ // x8 is unassigned -+ // x30 as LR -+ // x31 because dealing with the SP-vs-ZR overloading is too -+ // confusing, and we don't need to do so, so let's just avoid -+ // the problem -+ // -+ // Currently, we have 15 allocatable integer registers: -+ // 0 1 2 3 4 5 6 7 22 23 24 25 26 27 28 -+ // -+ // Hence for the allocatable integer registers we have: -+ // -+ // callee-saved: 22 23 24 25 26 27 28 -+ // caller-saved: 0 1 2 3 4 5 6 7 -+ // -+ // If the set of available registers changes or if the e/r status -+ // changes, be sure to re-check/sync the definition of -+ // getHRegUsage for ARMInstr_Call too. -+ vassert(i == *nregs); -+} -+ -+ -+/* --------- Condition codes, ARM64 encoding. --------- */ -+ -+static const HChar* showARM64CondCode ( ARM64CondCode cond ) { -+ switch (cond) { -+ case ARM64cc_EQ: return "eq"; -+ case ARM64cc_NE: return "ne"; -+ case ARM64cc_CS: return "cs"; -+ case ARM64cc_CC: return "cc"; -+ case ARM64cc_MI: return "mi"; -+ case ARM64cc_PL: return "pl"; -+ case ARM64cc_VS: return "vs"; -+ case ARM64cc_VC: return "vc"; -+ case ARM64cc_HI: return "hi"; -+ case ARM64cc_LS: return "ls"; -+ case ARM64cc_GE: return "ge"; -+ case ARM64cc_LT: return "lt"; -+ case ARM64cc_GT: return "gt"; -+ case ARM64cc_LE: return "le"; -+ case ARM64cc_AL: return "al"; // default -+ case ARM64cc_NV: return "nv"; -+ default: vpanic("showARM64CondCode"); -+ } -+} -+ -+ -+/* --------- Memory address expressions (amodes). --------- */ -+ -+ARM64AMode* ARM64AMode_RI9 ( HReg reg, Int simm9 ) { -+ ARM64AMode* am = LibVEX_Alloc(sizeof(ARM64AMode)); -+ am->tag = ARM64am_RI9; -+ am->ARM64am.RI9.reg = reg; -+ am->ARM64am.RI9.simm9 = simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ return am; -+} -+ -+ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB ) { -+ ARM64AMode* am = LibVEX_Alloc(sizeof(ARM64AMode)); -+ am->tag = ARM64am_RI12; -+ am->ARM64am.RI12.reg = reg; -+ am->ARM64am.RI12.uimm12 = uimm12; -+ am->ARM64am.RI12.szB = szB; -+ vassert(uimm12 >= 0 && uimm12 <= 4095); -+ switch (szB) { -+ case 1: case 2: case 4: case 8: break; -+ default: vassert(0); -+ } -+ return am; -+} -+ -+ARM64AMode* ARM64AMode_RR ( HReg base, HReg index ) { -+ ARM64AMode* am = LibVEX_Alloc(sizeof(ARM64AMode)); -+ am->tag = ARM64am_RR; -+ am->ARM64am.RR.base = base; -+ am->ARM64am.RR.index = index; -+ return am; -+} -+ -+static void ppARM64AMode ( ARM64AMode* am ) { -+ switch (am->tag) { -+ case ARM64am_RI9: -+ vex_printf("%d(", am->ARM64am.RI9.simm9); -+ ppHRegARM64(am->ARM64am.RI9.reg); -+ vex_printf(")"); -+ break; -+ case ARM64am_RI12: -+ vex_printf("%u(", (UInt)am->ARM64am.RI12.szB -+ * (UInt)am->ARM64am.RI12.uimm12); -+ ppHRegARM64(am->ARM64am.RI12.reg); -+ vex_printf(")"); -+ break; -+ case ARM64am_RR: -+ vex_printf("("); -+ ppHRegARM64(am->ARM64am.RR.base); -+ vex_printf(","); -+ ppHRegARM64(am->ARM64am.RR.index); -+ vex_printf(")"); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64AMode ( HRegUsage* u, ARM64AMode* am ) { -+ switch (am->tag) { -+ case ARM64am_RI9: -+ addHRegUse(u, HRmRead, am->ARM64am.RI9.reg); -+ return; -+ case ARM64am_RI12: -+ addHRegUse(u, HRmRead, am->ARM64am.RI12.reg); -+ return; -+ case ARM64am_RR: -+ addHRegUse(u, HRmRead, am->ARM64am.RR.base); -+ addHRegUse(u, HRmRead, am->ARM64am.RR.index); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64Amode"); -+ } -+} -+ -+static void mapRegs_ARM64AMode ( HRegRemap* m, ARM64AMode* am ) { -+ switch (am->tag) { -+ case ARM64am_RI9: -+ am->ARM64am.RI9.reg = lookupHRegRemap(m, am->ARM64am.RI9.reg); -+ return; -+ case ARM64am_RI12: -+ am->ARM64am.RI12.reg = lookupHRegRemap(m, am->ARM64am.RI12.reg); -+ return; -+ case ARM64am_RR: -+ am->ARM64am.RR.base = lookupHRegRemap(m, am->ARM64am.RR.base); -+ am->ARM64am.RR.index = lookupHRegRemap(m, am->ARM64am.RR.index); -+ return; -+ default: -+ vpanic("mapRegs_ARM64Amode"); -+ } -+} -+ -+ -+//ZZ /* --------- Mem AModes: Addressing Mode 2 --------- */ -+//ZZ -+//ZZ ARMAMode2* ARMAMode2_RI ( HReg reg, Int simm9 ) { -+//ZZ ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); -+//ZZ am->tag = ARMam2_RI; -+//ZZ am->ARMam2.RI.reg = reg; -+//ZZ am->ARMam2.RI.simm9 = simm9; -+//ZZ vassert(-255 <= simm9 && simm9 <= 255); -+//ZZ return am; -+//ZZ } -+//ZZ ARMAMode2* ARMAMode2_RR ( HReg base, HReg index ) { -+//ZZ ARMAMode2* am = LibVEX_Alloc(sizeof(ARMAMode2)); -+//ZZ am->tag = ARMam2_RR; -+//ZZ am->ARMam2.RR.base = base; -+//ZZ am->ARMam2.RR.index = index; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ void ppARMAMode2 ( ARMAMode2* am ) { -+//ZZ switch (am->tag) { -+//ZZ case ARMam2_RI: -+//ZZ vex_printf("%d(", am->ARMam2.RI.simm9); -+//ZZ ppHRegARM(am->ARMam2.RI.reg); -+//ZZ vex_printf(")"); -+//ZZ break; -+//ZZ case ARMam2_RR: -+//ZZ vex_printf("("); -+//ZZ ppHRegARM(am->ARMam2.RR.base); -+//ZZ vex_printf(","); -+//ZZ ppHRegARM(am->ARMam2.RR.index); -+//ZZ vex_printf(")"); -+//ZZ break; -+//ZZ default: -+//ZZ vassert(0); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void addRegUsage_ARMAMode2 ( HRegUsage* u, ARMAMode2* am ) { -+//ZZ switch (am->tag) { -+//ZZ case ARMam2_RI: -+//ZZ addHRegUse(u, HRmRead, am->ARMam2.RI.reg); -+//ZZ return; -+//ZZ case ARMam2_RR: -+//ZZ // addHRegUse(u, HRmRead, am->ARMam2.RR.base); -+//ZZ // addHRegUse(u, HRmRead, am->ARMam2.RR.index); -+//ZZ // return; -+//ZZ default: -+//ZZ vpanic("addRegUsage_ARMAmode2"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void mapRegs_ARMAMode2 ( HRegRemap* m, ARMAMode2* am ) { -+//ZZ switch (am->tag) { -+//ZZ case ARMam2_RI: -+//ZZ am->ARMam2.RI.reg = lookupHRegRemap(m, am->ARMam2.RI.reg); -+//ZZ return; -+//ZZ case ARMam2_RR: -+//ZZ //am->ARMam2.RR.base =lookupHRegRemap(m, am->ARMam2.RR.base); -+//ZZ //am->ARMam2.RR.index = lookupHRegRemap(m, am->ARMam2.RR.index); -+//ZZ //return; -+//ZZ default: -+//ZZ vpanic("mapRegs_ARMAmode2"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* --------- Mem AModes: Addressing Mode VFP --------- */ -+//ZZ -+//ZZ ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 ) { -+//ZZ ARMAModeV* am = LibVEX_Alloc(sizeof(ARMAModeV)); -+//ZZ vassert(simm11 >= -1020 && simm11 <= 1020); -+//ZZ vassert(0 == (simm11 & 3)); -+//ZZ am->reg = reg; -+//ZZ am->simm11 = simm11; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ void ppARMAModeV ( ARMAModeV* am ) { -+//ZZ vex_printf("%d(", am->simm11); -+//ZZ ppHRegARM(am->reg); -+//ZZ vex_printf(")"); -+//ZZ } -+//ZZ -+//ZZ static void addRegUsage_ARMAModeV ( HRegUsage* u, ARMAModeV* am ) { -+//ZZ addHRegUse(u, HRmRead, am->reg); -+//ZZ } -+//ZZ -+//ZZ static void mapRegs_ARMAModeV ( HRegRemap* m, ARMAModeV* am ) { -+//ZZ am->reg = lookupHRegRemap(m, am->reg); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* --------- Mem AModes: Addressing Mode Neon ------- */ -+//ZZ -+//ZZ ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { -+//ZZ ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN)); -+//ZZ am->tag = ARMamN_RR; -+//ZZ am->ARMamN.RR.rN = rN; -+//ZZ am->ARMamN.RR.rM = rM; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ ARMAModeN *mkARMAModeN_R ( HReg rN ) { -+//ZZ ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN)); -+//ZZ am->tag = ARMamN_R; -+//ZZ am->ARMamN.R.rN = rN; -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ static void addRegUsage_ARMAModeN ( HRegUsage* u, ARMAModeN* am ) { -+//ZZ if (am->tag == ARMamN_R) { -+//ZZ addHRegUse(u, HRmRead, am->ARMamN.R.rN); -+//ZZ } else { -+//ZZ addHRegUse(u, HRmRead, am->ARMamN.RR.rN); -+//ZZ addHRegUse(u, HRmRead, am->ARMamN.RR.rM); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static void mapRegs_ARMAModeN ( HRegRemap* m, ARMAModeN* am ) { -+//ZZ if (am->tag == ARMamN_R) { -+//ZZ am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN); -+//ZZ } else { -+//ZZ am->ARMamN.RR.rN = lookupHRegRemap(m, am->ARMamN.RR.rN); -+//ZZ am->ARMamN.RR.rM = lookupHRegRemap(m, am->ARMamN.RR.rM); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ void ppARMAModeN ( ARMAModeN* am ) { -+//ZZ vex_printf("["); -+//ZZ if (am->tag == ARMamN_R) { -+//ZZ ppHRegARM(am->ARMamN.R.rN); -+//ZZ } else { -+//ZZ ppHRegARM(am->ARMamN.RR.rN); -+//ZZ } -+//ZZ vex_printf("]"); -+//ZZ if (am->tag == ARMamN_RR) { -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(am->ARMamN.RR.rM); -+//ZZ } -+//ZZ } -+ -+ -+/* --------- Reg or uimm12<<{0,12} operands --------- */ -+ -+ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ) { -+ ARM64RIA* riA = LibVEX_Alloc(sizeof(ARM64RIA)); -+ riA->tag = ARM64riA_I12; -+ riA->ARM64riA.I12.imm12 = imm12; -+ riA->ARM64riA.I12.shift = shift; -+ vassert(imm12 < 4096); -+ vassert(shift == 0 || shift == 12); -+ return riA; -+} -+ARM64RIA* ARM64RIA_R ( HReg reg ) { -+ ARM64RIA* riA = LibVEX_Alloc(sizeof(ARM64RIA)); -+ riA->tag = ARM64riA_R; -+ riA->ARM64riA.R.reg = reg; -+ return riA; -+} -+ -+static void ppARM64RIA ( ARM64RIA* riA ) { -+ switch (riA->tag) { -+ case ARM64riA_I12: -+ vex_printf("#%u",(UInt)(riA->ARM64riA.I12.imm12 -+ << riA->ARM64riA.I12.shift)); -+ break; -+ case ARM64riA_R: -+ ppHRegARM64(riA->ARM64riA.R.reg); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64RIA ( HRegUsage* u, ARM64RIA* riA ) { -+ switch (riA->tag) { -+ case ARM64riA_I12: -+ return; -+ case ARM64riA_R: -+ addHRegUse(u, HRmRead, riA->ARM64riA.R.reg); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64RIA"); -+ } -+} -+ -+static void mapRegs_ARM64RIA ( HRegRemap* m, ARM64RIA* riA ) { -+ switch (riA->tag) { -+ case ARM64riA_I12: -+ return; -+ case ARM64riA_R: -+ riA->ARM64riA.R.reg = lookupHRegRemap(m, riA->ARM64riA.R.reg); -+ return; -+ default: -+ vpanic("mapRegs_ARM64RIA"); -+ } -+} -+ -+ -+/* --------- Reg or "bitfield" (logic immediate) operands --------- */ -+ -+ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS ) { -+ ARM64RIL* riL = LibVEX_Alloc(sizeof(ARM64RIL)); -+ riL->tag = ARM64riL_I13; -+ riL->ARM64riL.I13.bitN = bitN; -+ riL->ARM64riL.I13.immR = immR; -+ riL->ARM64riL.I13.immS = immS; -+ vassert(bitN < 2); -+ vassert(immR < 64); -+ vassert(immS < 64); -+ return riL; -+} -+ARM64RIL* ARM64RIL_R ( HReg reg ) { -+ ARM64RIL* riL = LibVEX_Alloc(sizeof(ARM64RIL)); -+ riL->tag = ARM64riL_R; -+ riL->ARM64riL.R.reg = reg; -+ return riL; -+} -+ -+static void ppARM64RIL ( ARM64RIL* riL ) { -+ switch (riL->tag) { -+ case ARM64riL_I13: -+ vex_printf("#nrs(%u,%u,%u)", -+ (UInt)riL->ARM64riL.I13.bitN, -+ (UInt)riL->ARM64riL.I13.immR, -+ (UInt)riL->ARM64riL.I13.immS); -+ break; -+ case ARM64riL_R: -+ ppHRegARM64(riL->ARM64riL.R.reg); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64RIL ( HRegUsage* u, ARM64RIL* riL ) { -+ switch (riL->tag) { -+ case ARM64riL_I13: -+ return; -+ case ARM64riL_R: -+ addHRegUse(u, HRmRead, riL->ARM64riL.R.reg); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64RIL"); -+ } -+} -+ -+static void mapRegs_ARM64RIL ( HRegRemap* m, ARM64RIL* riL ) { -+ switch (riL->tag) { -+ case ARM64riL_I13: -+ return; -+ case ARM64riL_R: -+ riL->ARM64riL.R.reg = lookupHRegRemap(m, riL->ARM64riL.R.reg); -+ return; -+ default: -+ vpanic("mapRegs_ARM64RIL"); -+ } -+} -+ -+ -+/* --------------- Reg or uimm6 operands --------------- */ -+ -+ARM64RI6* ARM64RI6_I6 ( UInt imm6 ) { -+ ARM64RI6* ri6 = LibVEX_Alloc(sizeof(ARM64RI6)); -+ ri6->tag = ARM64ri6_I6; -+ ri6->ARM64ri6.I6.imm6 = imm6; -+ vassert(imm6 > 0 && imm6 < 64); -+ return ri6; -+} -+ARM64RI6* ARM64RI6_R ( HReg reg ) { -+ ARM64RI6* ri6 = LibVEX_Alloc(sizeof(ARM64RI6)); -+ ri6->tag = ARM64ri6_R; -+ ri6->ARM64ri6.R.reg = reg; -+ return ri6; -+} -+ -+static void ppARM64RI6 ( ARM64RI6* ri6 ) { -+ switch (ri6->tag) { -+ case ARM64ri6_I6: -+ vex_printf("#%u", ri6->ARM64ri6.I6.imm6); -+ break; -+ case ARM64ri6_R: -+ ppHRegARM64(ri6->ARM64ri6.R.reg); -+ break; -+ default: -+ vassert(0); -+ } -+} -+ -+static void addRegUsage_ARM64RI6 ( HRegUsage* u, ARM64RI6* ri6 ) { -+ switch (ri6->tag) { -+ case ARM64ri6_I6: -+ return; -+ case ARM64ri6_R: -+ addHRegUse(u, HRmRead, ri6->ARM64ri6.R.reg); -+ return; -+ default: -+ vpanic("addRegUsage_ARM64RI6"); -+ } -+} -+ -+static void mapRegs_ARM64RI6 ( HRegRemap* m, ARM64RI6* ri6 ) { -+ switch (ri6->tag) { -+ case ARM64ri6_I6: -+ return; -+ case ARM64ri6_R: -+ ri6->ARM64ri6.R.reg = lookupHRegRemap(m, ri6->ARM64ri6.R.reg); -+ return; -+ default: -+ vpanic("mapRegs_ARM64RI6"); -+ } -+} -+ -+ -+//ZZ /* -------- Neon Immediate operatnd --------- */ -+//ZZ -+//ZZ ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 ) { -+//ZZ ARMNImm* i = LibVEX_Alloc(sizeof(ARMNImm)); -+//ZZ i->type = type; -+//ZZ i->imm8 = imm8; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ULong ARMNImm_to_Imm64 ( ARMNImm* imm ) { -+//ZZ int i, j; -+//ZZ ULong y, x = imm->imm8; -+//ZZ switch (imm->type) { -+//ZZ case 3: -+//ZZ x = x << 8; /* fallthrough */ -+//ZZ case 2: -+//ZZ x = x << 8; /* fallthrough */ -+//ZZ case 1: -+//ZZ x = x << 8; /* fallthrough */ -+//ZZ case 0: -+//ZZ return (x << 32) | x; -+//ZZ case 5: -+//ZZ case 6: -+//ZZ if (imm->type == 5) -+//ZZ x = x << 8; -+//ZZ else -+//ZZ x = (x << 8) | x; -+//ZZ /* fallthrough */ -+//ZZ case 4: -+//ZZ x = (x << 16) | x; -+//ZZ return (x << 32) | x; -+//ZZ case 8: -+//ZZ x = (x << 8) | 0xFF; -+//ZZ /* fallthrough */ -+//ZZ case 7: -+//ZZ x = (x << 8) | 0xFF; -+//ZZ return (x << 32) | x; -+//ZZ case 9: -+//ZZ x = 0; -+//ZZ for (i = 7; i >= 0; i--) { -+//ZZ y = ((ULong)imm->imm8 >> i) & 1; -+//ZZ for (j = 0; j < 8; j++) { -+//ZZ x = (x << 1) | y; -+//ZZ } -+//ZZ } -+//ZZ return x; -+//ZZ case 10: -+//ZZ x |= (x & 0x80) << 5; -+//ZZ x |= (~x & 0x40) << 5; -+//ZZ x &= 0x187F; /* 0001 1000 0111 1111 */ -+//ZZ x |= (x & 0x40) << 4; -+//ZZ x |= (x & 0x40) << 3; -+//ZZ x |= (x & 0x40) << 2; -+//ZZ x |= (x & 0x40) << 1; -+//ZZ x = x << 19; -+//ZZ x = (x << 32) | x; -+//ZZ return x; -+//ZZ default: -+//ZZ vpanic("ARMNImm_to_Imm64"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ ARMNImm* Imm64_to_ARMNImm ( ULong x ) { -+//ZZ ARMNImm tmp; -+//ZZ if ((x & 0xFFFFFFFF) == (x >> 32)) { -+//ZZ if ((x & 0xFFFFFF00) == 0) -+//ZZ return ARMNImm_TI(0, x & 0xFF); -+//ZZ if ((x & 0xFFFF00FF) == 0) -+//ZZ return ARMNImm_TI(1, (x >> 8) & 0xFF); -+//ZZ if ((x & 0xFF00FFFF) == 0) -+//ZZ return ARMNImm_TI(2, (x >> 16) & 0xFF); -+//ZZ if ((x & 0x00FFFFFF) == 0) -+//ZZ return ARMNImm_TI(3, (x >> 24) & 0xFF); -+//ZZ if ((x & 0xFFFF00FF) == 0xFF) -+//ZZ return ARMNImm_TI(7, (x >> 8) & 0xFF); -+//ZZ if ((x & 0xFF00FFFF) == 0xFFFF) -+//ZZ return ARMNImm_TI(8, (x >> 16) & 0xFF); -+//ZZ if ((x & 0xFFFF) == ((x >> 16) & 0xFFFF)) { -+//ZZ if ((x & 0xFF00) == 0) -+//ZZ return ARMNImm_TI(4, x & 0xFF); -+//ZZ if ((x & 0x00FF) == 0) -+//ZZ return ARMNImm_TI(5, (x >> 8) & 0xFF); -+//ZZ if ((x & 0xFF) == ((x >> 8) & 0xFF)) -+//ZZ return ARMNImm_TI(6, x & 0xFF); -+//ZZ } -+//ZZ if ((x & 0x7FFFF) == 0) { -+//ZZ tmp.type = 10; -+//ZZ tmp.imm8 = ((x >> 19) & 0x7F) | ((x >> 24) & 0x80); -+//ZZ if (ARMNImm_to_Imm64(&tmp) == x) -+//ZZ return ARMNImm_TI(tmp.type, tmp.imm8); -+//ZZ } -+//ZZ } else { -+//ZZ /* This can only be type 9. */ -+//ZZ tmp.imm8 = (((x >> 56) & 1) << 7) -+//ZZ | (((x >> 48) & 1) << 6) -+//ZZ | (((x >> 40) & 1) << 5) -+//ZZ | (((x >> 32) & 1) << 4) -+//ZZ | (((x >> 24) & 1) << 3) -+//ZZ | (((x >> 16) & 1) << 2) -+//ZZ | (((x >> 8) & 1) << 1) -+//ZZ | (((x >> 0) & 1) << 0); -+//ZZ tmp.type = 9; -+//ZZ if (ARMNImm_to_Imm64 (&tmp) == x) -+//ZZ return ARMNImm_TI(tmp.type, tmp.imm8); -+//ZZ } -+//ZZ return NULL; -+//ZZ } -+//ZZ -+//ZZ void ppARMNImm (ARMNImm* i) { -+//ZZ ULong x = ARMNImm_to_Imm64(i); -+//ZZ vex_printf("0x%llX%llX", x, x); -+//ZZ } -+//ZZ -+//ZZ /* -- Register or scalar operand --- */ -+//ZZ -+//ZZ ARMNRS* mkARMNRS(ARMNRS_tag tag, HReg reg, UInt index) -+//ZZ { -+//ZZ ARMNRS *p = LibVEX_Alloc(sizeof(ARMNRS)); -+//ZZ p->tag = tag; -+//ZZ p->reg = reg; -+//ZZ p->index = index; -+//ZZ return p; -+//ZZ } -+//ZZ -+//ZZ void ppARMNRS(ARMNRS *p) -+//ZZ { -+//ZZ ppHRegARM(p->reg); -+//ZZ if (p->tag == ARMNRS_Scalar) { -+//ZZ vex_printf("[%d]", p->index); -+//ZZ } -+//ZZ } -+ -+/* --------- Instructions. --------- */ -+ -+static const HChar* showARM64LogicOp ( ARM64LogicOp op ) { -+ switch (op) { -+ case ARM64lo_AND: return "and"; -+ case ARM64lo_OR: return "orr"; -+ case ARM64lo_XOR: return "eor"; -+ default: vpanic("showARM64LogicOp"); -+ } -+} -+ -+static const HChar* showARM64ShiftOp ( ARM64ShiftOp op ) { -+ switch (op) { -+ case ARM64sh_SHL: return "lsl"; -+ case ARM64sh_SHR: return "lsr"; -+ case ARM64sh_SAR: return "asr"; -+ default: vpanic("showARM64ShiftOp"); -+ } -+} -+ -+static const HChar* showARM64UnaryOp ( ARM64UnaryOp op ) { -+ switch (op) { -+ case ARM64un_NEG: return "neg"; -+ case ARM64un_NOT: return "not"; -+ case ARM64un_CLZ: return "clz"; -+ default: vpanic("showARM64UnaryOp"); -+ } -+} -+ -+static const HChar* showARM64MulOp ( ARM64MulOp op ) { -+ switch (op) { -+ case ARM64mul_PLAIN: return "mul "; -+ case ARM64mul_ZX: return "umulh"; -+ case ARM64mul_SX: return "smulh"; -+ default: vpanic("showARM64MulOp"); -+ } -+} -+ -+static void characteriseARM64CvtOp ( /*OUT*/HChar* syn, -+ /*OUT*/UInt* fszB, /*OUT*/UInt* iszB, -+ ARM64CvtOp op ) { -+ switch (op) { -+ case ARM64cvt_F32_I32S: -+ *syn = 's'; *fszB = 4; *iszB = 4; break; -+ case ARM64cvt_F64_I32S: -+ *syn = 's'; *fszB = 8; *iszB = 4; break; -+ case ARM64cvt_F32_I64S: -+ *syn = 's'; *fszB = 4; *iszB = 8; break; -+ case ARM64cvt_F64_I64S: -+ *syn = 's'; *fszB = 8; *iszB = 8; break; -+ case ARM64cvt_F32_I32U: -+ *syn = 'u'; *fszB = 4; *iszB = 4; break; -+ case ARM64cvt_F64_I32U: -+ *syn = 'u'; *fszB = 8; *iszB = 4; break; -+ case ARM64cvt_F32_I64U: -+ *syn = 'u'; *fszB = 4; *iszB = 8; break; -+ case ARM64cvt_F64_I64U: -+ *syn = 'u'; *fszB = 8; *iszB = 8; break; -+ default: -+ vpanic("characteriseARM64CvtOp"); -+ } -+} -+ -+static const HChar* showARM64FpBinOp ( ARM64FpBinOp op ) { -+ switch (op) { -+ case ARM64fpb_ADD: return "add"; -+ case ARM64fpb_SUB: return "sub"; -+ case ARM64fpb_MUL: return "mul"; -+ case ARM64fpb_DIV: return "div"; -+ default: vpanic("showARM64FpBinOp"); -+ } -+} -+ -+static const HChar* showARM64FpUnaryOp ( ARM64FpUnaryOp op ) { -+ switch (op) { -+ case ARM64fpu_NEG: return "neg "; -+ case ARM64fpu_ABS: return "abs "; -+ case ARM64fpu_SQRT: return "sqrt "; -+ case ARM64fpu_RINT: return "rinti"; -+ default: vpanic("showARM64FpUnaryOp"); -+ } -+} -+ -+static void showARM64VecBinOp(/*OUT*/const HChar** nm, -+ /*OUT*/const HChar** ar, ARM64VecBinOp op ) { -+ switch (op) { -+ case ARM64vecb_ADD64x2: *nm = "add "; *ar = "2d"; return; -+ case ARM64vecb_ADD32x4: *nm = "add "; *ar = "4s"; return; -+ case ARM64vecb_ADD16x8: *nm = "add "; *ar = "8h"; return; -+ case ARM64vecb_ADD8x16: *nm = "add "; *ar = "16b"; return; -+ case ARM64vecb_SUB64x2: *nm = "sub "; *ar = "2d"; return; -+ case ARM64vecb_SUB32x4: *nm = "sub "; *ar = "4s"; return; -+ case ARM64vecb_SUB16x8: *nm = "sub "; *ar = "8h"; return; -+ case ARM64vecb_SUB8x16: *nm = "sub "; *ar = "16b"; return; -+ case ARM64vecb_MUL32x4: *nm = "mul "; *ar = "4s"; return; -+ case ARM64vecb_MUL16x8: *nm = "mul "; *ar = "8h"; return; -+ case ARM64vecb_MUL8x16: *nm = "mul "; *ar = "16b"; return; -+ case ARM64vecb_FADD64x2: *nm = "fadd"; *ar = "2d"; return; -+ case ARM64vecb_FSUB64x2: *nm = "fsub"; *ar = "2d"; return; -+ case ARM64vecb_FMUL64x2: *nm = "fmul"; *ar = "2d"; return; -+ case ARM64vecb_FDIV64x2: *nm = "fdiv"; *ar = "2d"; return; -+ case ARM64vecb_FADD32x4: *nm = "fadd"; *ar = "4s"; return; -+ case ARM64vecb_FSUB32x4: *nm = "fsub"; *ar = "4s"; return; -+ case ARM64vecb_FMUL32x4: *nm = "fmul"; *ar = "4s"; return; -+ case ARM64vecb_FDIV32x4: *nm = "fdiv"; *ar = "4s"; return; -+ case ARM64vecb_UMAX32x4: *nm = "umax"; *ar = "4s"; return; -+ case ARM64vecb_UMAX16x8: *nm = "umax"; *ar = "8h"; return; -+ case ARM64vecb_UMAX8x16: *nm = "umax"; *ar = "16b"; return; -+ case ARM64vecb_UMIN32x4: *nm = "umin"; *ar = "4s"; return; -+ case ARM64vecb_UMIN16x8: *nm = "umin"; *ar = "8h"; return; -+ case ARM64vecb_UMIN8x16: *nm = "umin"; *ar = "16b"; return; -+ case ARM64vecb_SMAX32x4: *nm = "smax"; *ar = "4s"; return; -+ case ARM64vecb_SMAX16x8: *nm = "smax"; *ar = "8h"; return; -+ case ARM64vecb_SMAX8x16: *nm = "smax"; *ar = "16b"; return; -+ case ARM64vecb_SMIN32x4: *nm = "smin"; *ar = "4s"; return; -+ case ARM64vecb_SMIN16x8: *nm = "smin"; *ar = "8h"; return; -+ case ARM64vecb_SMIN8x16: *nm = "smin"; *ar = "16b"; return; -+ case ARM64vecb_AND: *nm = "and "; *ar = "all"; return; -+ case ARM64vecb_ORR: *nm = "orr "; *ar = "all"; return; -+ case ARM64vecb_XOR: *nm = "eor "; *ar = "all"; return; -+ case ARM64vecb_CMEQ64x2: *nm = "cmeq"; *ar = "2d"; return; -+ case ARM64vecb_CMEQ32x4: *nm = "cmeq"; *ar = "4s"; return; -+ case ARM64vecb_CMEQ16x8: *nm = "cmeq"; *ar = "8h"; return; -+ case ARM64vecb_CMEQ8x16: *nm = "cmeq"; *ar = "16b"; return; -+ case ARM64vecb_CMHI64x2: *nm = "cmhi"; *ar = "2d"; return; -+ case ARM64vecb_CMHI32x4: *nm = "cmhi"; *ar = "4s"; return; -+ case ARM64vecb_CMHI16x8: *nm = "cmhi"; *ar = "8h"; return; -+ case ARM64vecb_CMHI8x16: *nm = "cmhi"; *ar = "16b"; return; -+ case ARM64vecb_CMGT64x2: *nm = "cmgt"; *ar = "2d"; return; -+ case ARM64vecb_CMGT32x4: *nm = "cmgt"; *ar = "4s"; return; -+ case ARM64vecb_CMGT16x8: *nm = "cmgt"; *ar = "8h"; return; -+ case ARM64vecb_CMGT8x16: *nm = "cmgt"; *ar = "16b"; return; -+ case ARM64vecb_FCMEQ64x2: *nm = "fcmeq"; *ar = "2d"; return; -+ case ARM64vecb_FCMEQ32x4: *nm = "fcmeq"; *ar = "4s"; return; -+ case ARM64vecb_FCMGE64x2: *nm = "fcmge"; *ar = "2d"; return; -+ case ARM64vecb_FCMGE32x4: *nm = "fcmge"; *ar = "4s"; return; -+ case ARM64vecb_FCMGT64x2: *nm = "fcmgt"; *ar = "2d"; return; -+ case ARM64vecb_FCMGT32x4: *nm = "fcmgt"; *ar = "4s"; return; -+ case ARM64vecb_TBL1: *nm = "tbl "; *ar = "16b"; return; -+ default: vpanic("showARM64VecBinOp"); -+ } -+} -+ -+static void showARM64VecUnaryOp(/*OUT*/const HChar** nm, -+ /*OUT*/const HChar** ar, ARM64VecUnaryOp op ) -+{ -+ switch (op) { -+ case ARM64vecu_FNEG64x2: *nm = "fneg "; *ar = "2d"; return; -+ case ARM64vecu_FNEG32x4: *nm = "fneg "; *ar = "4s"; return; -+ case ARM64vecu_FABS64x2: *nm = "fabs "; *ar = "2d"; return; -+ case ARM64vecu_FABS32x4: *nm = "fabs "; *ar = "4s"; return; -+ case ARM64vecu_NOT: *nm = "not "; *ar = "all"; return; -+ default: vpanic("showARM64VecUnaryOp"); -+ } -+} -+ -+static void showARM64VecShiftOp(/*OUT*/const HChar** nm, -+ /*OUT*/const HChar** ar, -+ ARM64VecShiftOp op ) -+{ -+ switch (op) { -+ case ARM64vecsh_USHR64x2: *nm = "ushr "; *ar = "2d"; return; -+ case ARM64vecsh_USHR32x4: *nm = "ushr "; *ar = "4s"; return; -+ case ARM64vecsh_USHR16x8: *nm = "ushr "; *ar = "8h"; return; -+ case ARM64vecsh_USHR8x16: *nm = "ushr "; *ar = "16b"; return; -+ case ARM64vecsh_SSHR64x2: *nm = "sshr "; *ar = "2d"; return; -+ case ARM64vecsh_SSHR32x4: *nm = "sshr "; *ar = "4s"; return; -+ case ARM64vecsh_SSHR16x8: *nm = "sshr "; *ar = "8h"; return; -+ case ARM64vecsh_SSHR8x16: *nm = "sshr "; *ar = "16b"; return; -+ case ARM64vecsh_SHL64x2: *nm = "shl "; *ar = "2d"; return; -+ case ARM64vecsh_SHL32x4: *nm = "shl "; *ar = "4s"; return; -+ case ARM64vecsh_SHL16x8: *nm = "shl "; *ar = "8h"; return; -+ case ARM64vecsh_SHL8x16: *nm = "shl "; *ar = "16b"; return; -+ default: vpanic("showARM64VecShiftImmOp"); -+ } -+} -+ -+//ZZ const HChar* showARMNeonBinOp ( ARMNeonBinOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VAND: return "vand"; -+//ZZ case ARMneon_VORR: return "vorr"; -+//ZZ case ARMneon_VXOR: return "veor"; -+//ZZ case ARMneon_VADD: return "vadd"; -+//ZZ case ARMneon_VRHADDS: return "vrhadd"; -+//ZZ case ARMneon_VRHADDU: return "vrhadd"; -+//ZZ case ARMneon_VADDFP: return "vadd"; -+//ZZ case ARMneon_VPADDFP: return "vpadd"; -+//ZZ case ARMneon_VABDFP: return "vabd"; -+//ZZ case ARMneon_VSUB: return "vsub"; -+//ZZ case ARMneon_VSUBFP: return "vsub"; -+//ZZ case ARMneon_VMINU: return "vmin"; -+//ZZ case ARMneon_VMINS: return "vmin"; -+//ZZ case ARMneon_VMINF: return "vmin"; -+//ZZ case ARMneon_VMAXU: return "vmax"; -+//ZZ case ARMneon_VMAXS: return "vmax"; -+//ZZ case ARMneon_VMAXF: return "vmax"; -+//ZZ case ARMneon_VQADDU: return "vqadd"; -+//ZZ case ARMneon_VQADDS: return "vqadd"; -+//ZZ case ARMneon_VQSUBU: return "vqsub"; -+//ZZ case ARMneon_VQSUBS: return "vqsub"; -+//ZZ case ARMneon_VCGTU: return "vcgt"; -+//ZZ case ARMneon_VCGTS: return "vcgt"; -+//ZZ case ARMneon_VCGTF: return "vcgt"; -+//ZZ case ARMneon_VCGEF: return "vcgt"; -+//ZZ case ARMneon_VCGEU: return "vcge"; -+//ZZ case ARMneon_VCGES: return "vcge"; -+//ZZ case ARMneon_VCEQ: return "vceq"; -+//ZZ case ARMneon_VCEQF: return "vceq"; -+//ZZ case ARMneon_VPADD: return "vpadd"; -+//ZZ case ARMneon_VPMINU: return "vpmin"; -+//ZZ case ARMneon_VPMINS: return "vpmin"; -+//ZZ case ARMneon_VPMINF: return "vpmin"; -+//ZZ case ARMneon_VPMAXU: return "vpmax"; -+//ZZ case ARMneon_VPMAXS: return "vpmax"; -+//ZZ case ARMneon_VPMAXF: return "vpmax"; -+//ZZ case ARMneon_VEXT: return "vext"; -+//ZZ case ARMneon_VMUL: return "vmuli"; -+//ZZ case ARMneon_VMULLU: return "vmull"; -+//ZZ case ARMneon_VMULLS: return "vmull"; -+//ZZ case ARMneon_VMULP: return "vmul"; -+//ZZ case ARMneon_VMULFP: return "vmul"; -+//ZZ case ARMneon_VMULLP: return "vmul"; -+//ZZ case ARMneon_VQDMULH: return "vqdmulh"; -+//ZZ case ARMneon_VQRDMULH: return "vqrdmulh"; -+//ZZ case ARMneon_VQDMULL: return "vqdmull"; -+//ZZ case ARMneon_VTBL: return "vtbl"; -+//ZZ case ARMneon_VRECPS: return "vrecps"; -+//ZZ case ARMneon_VRSQRTS: return "vrecps"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonBinOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VAND: -+//ZZ case ARMneon_VORR: -+//ZZ case ARMneon_VXOR: -+//ZZ return ""; -+//ZZ case ARMneon_VADD: -+//ZZ case ARMneon_VSUB: -+//ZZ case ARMneon_VEXT: -+//ZZ case ARMneon_VMUL: -+//ZZ case ARMneon_VPADD: -+//ZZ case ARMneon_VTBL: -+//ZZ case ARMneon_VCEQ: -+//ZZ return ".i"; -+//ZZ case ARMneon_VRHADDU: -+//ZZ case ARMneon_VMINU: -+//ZZ case ARMneon_VMAXU: -+//ZZ case ARMneon_VQADDU: -+//ZZ case ARMneon_VQSUBU: -+//ZZ case ARMneon_VCGTU: -+//ZZ case ARMneon_VCGEU: -+//ZZ case ARMneon_VMULLU: -+//ZZ case ARMneon_VPMINU: -+//ZZ case ARMneon_VPMAXU: -+//ZZ return ".u"; -+//ZZ case ARMneon_VRHADDS: -+//ZZ case ARMneon_VMINS: -+//ZZ case ARMneon_VMAXS: -+//ZZ case ARMneon_VQADDS: -+//ZZ case ARMneon_VQSUBS: -+//ZZ case ARMneon_VCGTS: -+//ZZ case ARMneon_VCGES: -+//ZZ case ARMneon_VQDMULL: -+//ZZ case ARMneon_VMULLS: -+//ZZ case ARMneon_VPMINS: -+//ZZ case ARMneon_VPMAXS: -+//ZZ case ARMneon_VQDMULH: -+//ZZ case ARMneon_VQRDMULH: -+//ZZ return ".s"; -+//ZZ case ARMneon_VMULP: -+//ZZ case ARMneon_VMULLP: -+//ZZ return ".p"; -+//ZZ case ARMneon_VADDFP: -+//ZZ case ARMneon_VABDFP: -+//ZZ case ARMneon_VPADDFP: -+//ZZ case ARMneon_VSUBFP: -+//ZZ case ARMneon_VMULFP: -+//ZZ case ARMneon_VMINF: -+//ZZ case ARMneon_VMAXF: -+//ZZ case ARMneon_VPMINF: -+//ZZ case ARMneon_VPMAXF: -+//ZZ case ARMneon_VCGTF: -+//ZZ case ARMneon_VCGEF: -+//ZZ case ARMneon_VCEQF: -+//ZZ case ARMneon_VRECPS: -+//ZZ case ARMneon_VRSQRTS: -+//ZZ return ".f"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonBinOpDataType"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOp ( ARMNeonUnOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_COPY: return "vmov"; -+//ZZ case ARMneon_COPYLS: return "vmov"; -+//ZZ case ARMneon_COPYLU: return "vmov"; -+//ZZ case ARMneon_COPYN: return "vmov"; -+//ZZ case ARMneon_COPYQNSS: return "vqmovn"; -+//ZZ case ARMneon_COPYQNUS: return "vqmovun"; -+//ZZ case ARMneon_COPYQNUU: return "vqmovn"; -+//ZZ case ARMneon_NOT: return "vmvn"; -+//ZZ case ARMneon_EQZ: return "vceq"; -+//ZZ case ARMneon_CNT: return "vcnt"; -+//ZZ case ARMneon_CLS: return "vcls"; -+//ZZ case ARMneon_CLZ: return "vclz"; -+//ZZ case ARMneon_DUP: return "vdup"; -+//ZZ case ARMneon_PADDLS: return "vpaddl"; -+//ZZ case ARMneon_PADDLU: return "vpaddl"; -+//ZZ case ARMneon_VQSHLNSS: return "vqshl"; -+//ZZ case ARMneon_VQSHLNUU: return "vqshl"; -+//ZZ case ARMneon_VQSHLNUS: return "vqshlu"; -+//ZZ case ARMneon_REV16: return "vrev16"; -+//ZZ case ARMneon_REV32: return "vrev32"; -+//ZZ case ARMneon_REV64: return "vrev64"; -+//ZZ case ARMneon_VCVTFtoU: return "vcvt"; -+//ZZ case ARMneon_VCVTFtoS: return "vcvt"; -+//ZZ case ARMneon_VCVTUtoF: return "vcvt"; -+//ZZ case ARMneon_VCVTStoF: return "vcvt"; -+//ZZ case ARMneon_VCVTFtoFixedU: return "vcvt"; -+//ZZ case ARMneon_VCVTFtoFixedS: return "vcvt"; -+//ZZ case ARMneon_VCVTFixedUtoF: return "vcvt"; -+//ZZ case ARMneon_VCVTFixedStoF: return "vcvt"; -+//ZZ case ARMneon_VCVTF32toF16: return "vcvt"; -+//ZZ case ARMneon_VCVTF16toF32: return "vcvt"; -+//ZZ case ARMneon_VRECIP: return "vrecip"; -+//ZZ case ARMneon_VRECIPF: return "vrecipf"; -+//ZZ case ARMneon_VNEGF: return "vneg"; -+//ZZ case ARMneon_ABS: return "vabs"; -+//ZZ case ARMneon_VABSFP: return "vabsfp"; -+//ZZ case ARMneon_VRSQRTEFP: return "vrsqrtefp"; -+//ZZ case ARMneon_VRSQRTE: return "vrsqrte"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_COPY: -+//ZZ case ARMneon_NOT: -+//ZZ return ""; -+//ZZ case ARMneon_COPYN: -+//ZZ case ARMneon_EQZ: -+//ZZ case ARMneon_CNT: -+//ZZ case ARMneon_DUP: -+//ZZ case ARMneon_REV16: -+//ZZ case ARMneon_REV32: -+//ZZ case ARMneon_REV64: -+//ZZ return ".i"; -+//ZZ case ARMneon_COPYLU: -+//ZZ case ARMneon_PADDLU: -+//ZZ case ARMneon_COPYQNUU: -+//ZZ case ARMneon_VQSHLNUU: -+//ZZ case ARMneon_VRECIP: -+//ZZ case ARMneon_VRSQRTE: -+//ZZ return ".u"; -+//ZZ case ARMneon_CLS: -+//ZZ case ARMneon_CLZ: -+//ZZ case ARMneon_COPYLS: -+//ZZ case ARMneon_PADDLS: -+//ZZ case ARMneon_COPYQNSS: -+//ZZ case ARMneon_COPYQNUS: -+//ZZ case ARMneon_VQSHLNSS: -+//ZZ case ARMneon_VQSHLNUS: -+//ZZ case ARMneon_ABS: -+//ZZ return ".s"; -+//ZZ case ARMneon_VRECIPF: -+//ZZ case ARMneon_VNEGF: -+//ZZ case ARMneon_VABSFP: -+//ZZ case ARMneon_VRSQRTEFP: -+//ZZ return ".f"; -+//ZZ case ARMneon_VCVTFtoU: return ".u32.f32"; -+//ZZ case ARMneon_VCVTFtoS: return ".s32.f32"; -+//ZZ case ARMneon_VCVTUtoF: return ".f32.u32"; -+//ZZ case ARMneon_VCVTStoF: return ".f32.s32"; -+//ZZ case ARMneon_VCVTF16toF32: return ".f32.f16"; -+//ZZ case ARMneon_VCVTF32toF16: return ".f16.f32"; -+//ZZ case ARMneon_VCVTFtoFixedU: return ".u32.f32"; -+//ZZ case ARMneon_VCVTFtoFixedS: return ".s32.f32"; -+//ZZ case ARMneon_VCVTFixedUtoF: return ".f32.u32"; -+//ZZ case ARMneon_VCVTFixedStoF: return ".f32.s32"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnOpDataType"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_SETELEM: return "vmov"; -+//ZZ case ARMneon_GETELEMU: return "vmov"; -+//ZZ case ARMneon_GETELEMS: return "vmov"; -+//ZZ case ARMneon_VDUP: return "vdup"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnarySOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_SETELEM: -+//ZZ case ARMneon_VDUP: -+//ZZ return ".i"; -+//ZZ case ARMneon_GETELEMS: -+//ZZ return ".s"; -+//ZZ case ARMneon_GETELEMU: -+//ZZ return ".u"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonUnarySOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VSHL: return "vshl"; -+//ZZ case ARMneon_VSAL: return "vshl"; -+//ZZ case ARMneon_VQSHL: return "vqshl"; -+//ZZ case ARMneon_VQSAL: return "vqshl"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonShiftOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_VSHL: -+//ZZ case ARMneon_VQSHL: -+//ZZ return ".u"; -+//ZZ case ARMneon_VSAL: -+//ZZ case ARMneon_VQSAL: -+//ZZ return ".s"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonShiftOpDataType"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonDualOp ( ARMNeonDualOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_TRN: return "vtrn"; -+//ZZ case ARMneon_ZIP: return "vzip"; -+//ZZ case ARMneon_UZP: return "vuzp"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonDualOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ const HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ) { -+//ZZ switch (op) { -+//ZZ case ARMneon_TRN: -+//ZZ case ARMneon_ZIP: -+//ZZ case ARMneon_UZP: -+//ZZ return "i"; -+//ZZ /* ... */ -+//ZZ default: vpanic("showARMNeonDualOp"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static const HChar* showARMNeonDataSize_wrk ( UInt size ) -+//ZZ { -+//ZZ switch (size) { -+//ZZ case 0: return "8"; -+//ZZ case 1: return "16"; -+//ZZ case 2: return "32"; -+//ZZ case 3: return "64"; -+//ZZ default: vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static const HChar* showARMNeonDataSize ( ARMInstr* i ) -+//ZZ { -+//ZZ switch (i->tag) { -+//ZZ case ARMin_NBinary: -+//ZZ if (i->ARMin.NBinary.op == ARMneon_VEXT) -+//ZZ return "8"; -+//ZZ if (i->ARMin.NBinary.op == ARMneon_VAND || -+//ZZ i->ARMin.NBinary.op == ARMneon_VORR || -+//ZZ i->ARMin.NBinary.op == ARMneon_VXOR) -+//ZZ return ""; -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NBinary.size); -+//ZZ case ARMin_NUnary: -+//ZZ if (i->ARMin.NUnary.op == ARMneon_COPY || -+//ZZ i->ARMin.NUnary.op == ARMneon_NOT || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTF32toF16|| -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTF16toF32|| -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTStoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTUtoF) -+//ZZ return ""; -+//ZZ if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUS) { -+//ZZ UInt size; -+//ZZ size = i->ARMin.NUnary.size; -+//ZZ if (size & 0x40) -+//ZZ return "64"; -+//ZZ if (size & 0x20) -+//ZZ return "32"; -+//ZZ if (size & 0x10) -+//ZZ return "16"; -+//ZZ if (size & 0x08) -+//ZZ return "8"; -+//ZZ vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NUnary.size); -+//ZZ case ARMin_NUnaryS: -+//ZZ if (i->ARMin.NUnaryS.op == ARMneon_VDUP) { -+//ZZ int size; -+//ZZ size = i->ARMin.NUnaryS.size; -+//ZZ if ((size & 1) == 1) -+//ZZ return "8"; -+//ZZ if ((size & 3) == 2) -+//ZZ return "16"; -+//ZZ if ((size & 7) == 4) -+//ZZ return "32"; -+//ZZ vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NUnaryS.size); -+//ZZ case ARMin_NShift: -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NShift.size); -+//ZZ case ARMin_NDual: -+//ZZ return showARMNeonDataSize_wrk(i->ARMin.NDual.size); -+//ZZ default: -+//ZZ vpanic("showARMNeonDataSize"); -+//ZZ } -+//ZZ } -+ -+ARM64Instr* ARM64Instr_Arith ( HReg dst, -+ HReg argL, ARM64RIA* argR, Bool isAdd ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Arith; -+ i->ARM64in.Arith.dst = dst; -+ i->ARM64in.Arith.argL = argL; -+ i->ARM64in.Arith.argR = argR; -+ i->ARM64in.Arith.isAdd = isAdd; -+ return i; -+} -+ARM64Instr* ARM64Instr_Cmp ( HReg argL, ARM64RIA* argR, Bool is64 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Cmp; -+ i->ARM64in.Cmp.argL = argL; -+ i->ARM64in.Cmp.argR = argR; -+ i->ARM64in.Cmp.is64 = is64; -+ return i; -+} -+ARM64Instr* ARM64Instr_Logic ( HReg dst, -+ HReg argL, ARM64RIL* argR, ARM64LogicOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Logic; -+ i->ARM64in.Logic.dst = dst; -+ i->ARM64in.Logic.argL = argL; -+ i->ARM64in.Logic.argR = argR; -+ i->ARM64in.Logic.op = op; -+ return i; -+} -+ARM64Instr* ARM64Instr_Test ( HReg argL, ARM64RIL* argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Test; -+ i->ARM64in.Test.argL = argL; -+ i->ARM64in.Test.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_Shift ( HReg dst, -+ HReg argL, ARM64RI6* argR, ARM64ShiftOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Shift; -+ i->ARM64in.Shift.dst = dst; -+ i->ARM64in.Shift.argL = argL; -+ i->ARM64in.Shift.argR = argR; -+ i->ARM64in.Shift.op = op; -+ return i; -+} -+ARM64Instr* ARM64Instr_Unary ( HReg dst, HReg src, ARM64UnaryOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Unary; -+ i->ARM64in.Unary.dst = dst; -+ i->ARM64in.Unary.src = src; -+ i->ARM64in.Unary.op = op; -+ return i; -+} -+ARM64Instr* ARM64Instr_MovI ( HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_MovI; -+ i->ARM64in.MovI.dst = dst; -+ i->ARM64in.MovI.src = src; -+ vassert(hregClass(src) == HRcInt64); -+ vassert(hregClass(dst) == HRcInt64); -+ return i; -+} -+ARM64Instr* ARM64Instr_Imm64 ( HReg dst, ULong imm64 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Imm64; -+ i->ARM64in.Imm64.dst = dst; -+ i->ARM64in.Imm64.imm64 = imm64; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt64; -+ i->ARM64in.LdSt64.isLoad = isLoad; -+ i->ARM64in.LdSt64.rD = rD; -+ i->ARM64in.LdSt64.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt32; -+ i->ARM64in.LdSt32.isLoad = isLoad; -+ i->ARM64in.LdSt32.rD = rD; -+ i->ARM64in.LdSt32.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt16; -+ i->ARM64in.LdSt16.isLoad = isLoad; -+ i->ARM64in.LdSt16.rD = rD; -+ i->ARM64in.LdSt16.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg rD, ARM64AMode* amode ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdSt8; -+ i->ARM64in.LdSt8.isLoad = isLoad; -+ i->ARM64in.LdSt8.rD = rD; -+ i->ARM64in.LdSt8.amode = amode; -+ return i; -+} -+ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, Bool toFastEP ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_XDirect; -+ i->ARM64in.XDirect.dstGA = dstGA; -+ i->ARM64in.XDirect.amPC = amPC; -+ i->ARM64in.XDirect.cond = cond; -+ i->ARM64in.XDirect.toFastEP = toFastEP; -+ return i; -+} -+ARM64Instr* ARM64Instr_XIndir ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_XIndir; -+ i->ARM64in.XIndir.dstGA = dstGA; -+ i->ARM64in.XIndir.amPC = amPC; -+ i->ARM64in.XIndir.cond = cond; -+ return i; -+} -+ARM64Instr* ARM64Instr_XAssisted ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, IRJumpKind jk ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_XAssisted; -+ i->ARM64in.XAssisted.dstGA = dstGA; -+ i->ARM64in.XAssisted.amPC = amPC; -+ i->ARM64in.XAssisted.cond = cond; -+ i->ARM64in.XAssisted.jk = jk; -+ return i; -+} -+ARM64Instr* ARM64Instr_CSel ( HReg dst, HReg argL, HReg argR, -+ ARM64CondCode cond ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_CSel; -+ i->ARM64in.CSel.dst = dst; -+ i->ARM64in.CSel.argL = argL; -+ i->ARM64in.CSel.argR = argR; -+ i->ARM64in.CSel.cond = cond; -+ return i; -+} -+ARM64Instr* ARM64Instr_Call ( ARM64CondCode cond, HWord target, Int nArgRegs, -+ RetLoc rloc ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Call; -+ i->ARM64in.Call.cond = cond; -+ i->ARM64in.Call.target = target; -+ i->ARM64in.Call.nArgRegs = nArgRegs; -+ i->ARM64in.Call.rloc = rloc; -+ vassert(is_sane_RetLoc(rloc)); -+ return i; -+} -+extern ARM64Instr* ARM64Instr_AddToSP ( Int simm ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_AddToSP; -+ i->ARM64in.AddToSP.simm = simm; -+ vassert(-4096 < simm && simm < 4096); -+ vassert(0 == (simm & 0xF)); -+ return i; -+} -+extern ARM64Instr* ARM64Instr_FromSP ( HReg dst ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_FromSP; -+ i->ARM64in.FromSP.dst = dst; -+ return i; -+} -+ARM64Instr* ARM64Instr_Mul ( HReg dst, HReg argL, HReg argR, -+ ARM64MulOp op ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_Mul; -+ i->ARM64in.Mul.dst = dst; -+ i->ARM64in.Mul.argL = argL; -+ i->ARM64in.Mul.argR = argR; -+ i->ARM64in.Mul.op = op; -+ return i; -+} -+ARM64Instr* ARM64Instr_LdrEX ( Int szB ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_LdrEX; -+ i->ARM64in.LdrEX.szB = szB; -+ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); -+ return i; -+} -+ARM64Instr* ARM64Instr_StrEX ( Int szB ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_StrEX; -+ i->ARM64in.StrEX.szB = szB; -+ vassert(szB == 8 || szB == 4 || szB == 2 || szB == 1); -+ return i; -+} -+ARM64Instr* ARM64Instr_MFence ( void ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_MFence; -+ return i; -+} -+//ZZ ARM64Instr* ARM64Instr_CLREX( void ) { -+//ZZ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+//ZZ i->tag = ARM64in_CLREX; -+//ZZ return i; -+//ZZ } -+ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VLdStS; -+ i->ARM64in.VLdStS.isLoad = isLoad; -+ i->ARM64in.VLdStS.sD = sD; -+ i->ARM64in.VLdStS.rN = rN; -+ i->ARM64in.VLdStS.uimm12 = uimm12; -+ vassert(uimm12 < 16384 && 0 == (uimm12 & 3)); -+ return i; -+} -+ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, UInt uimm12 ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VLdStD; -+ i->ARM64in.VLdStD.isLoad = isLoad; -+ i->ARM64in.VLdStD.dD = dD; -+ i->ARM64in.VLdStD.rN = rN; -+ i->ARM64in.VLdStD.uimm12 = uimm12; -+ vassert(uimm12 < 32768 && 0 == (uimm12 & 7)); -+ return i; -+} -+ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VLdStQ; -+ i->ARM64in.VLdStQ.isLoad = isLoad; -+ i->ARM64in.VLdStQ.rQ = rQ; -+ i->ARM64in.VLdStQ.rN = rN; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCvtI2F; -+ i->ARM64in.VCvtI2F.how = how; -+ i->ARM64in.VCvtI2F.rD = rD; -+ i->ARM64in.VCvtI2F.rS = rS; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS, -+ UChar armRM ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCvtF2I; -+ i->ARM64in.VCvtF2I.how = how; -+ i->ARM64in.VCvtF2I.rD = rD; -+ i->ARM64in.VCvtF2I.rS = rS; -+ i->ARM64in.VCvtF2I.armRM = armRM; -+ vassert(armRM <= 3); -+ return i; -+} -+ARM64Instr* ARM64Instr_VCvtSD ( Bool sToD, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCvtSD; -+ i->ARM64in.VCvtSD.sToD = sToD; -+ i->ARM64in.VCvtSD.dst = dst; -+ i->ARM64in.VCvtSD.src = src; -+ return i; -+} -+ARM64Instr* ARM64Instr_VUnaryD ( ARM64FpUnaryOp op, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VUnaryD; -+ i->ARM64in.VUnaryD.op = op; -+ i->ARM64in.VUnaryD.dst = dst; -+ i->ARM64in.VUnaryD.src = src; -+ return i; -+} -+ARM64Instr* ARM64Instr_VUnaryS ( ARM64FpUnaryOp op, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VUnaryS; -+ i->ARM64in.VUnaryS.op = op; -+ i->ARM64in.VUnaryS.dst = dst; -+ i->ARM64in.VUnaryS.src = src; -+ return i; -+} -+ARM64Instr* ARM64Instr_VBinD ( ARM64FpBinOp op, -+ HReg dst, HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VBinD; -+ i->ARM64in.VBinD.op = op; -+ i->ARM64in.VBinD.dst = dst; -+ i->ARM64in.VBinD.argL = argL; -+ i->ARM64in.VBinD.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_VBinS ( ARM64FpBinOp op, -+ HReg dst, HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VBinS; -+ i->ARM64in.VBinS.op = op; -+ i->ARM64in.VBinS.dst = dst; -+ i->ARM64in.VBinS.argL = argL; -+ i->ARM64in.VBinS.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCmpD ( HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCmpD; -+ i->ARM64in.VCmpD.argL = argL; -+ i->ARM64in.VCmpD.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_VCmpS ( HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VCmpS; -+ i->ARM64in.VCmpS.argL = argL; -+ i->ARM64in.VCmpS.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_FPCR ( Bool toFPCR, HReg iReg ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_FPCR; -+ i->ARM64in.FPCR.toFPCR = toFPCR; -+ i->ARM64in.FPCR.iReg = iReg; -+ return i; -+} -+ARM64Instr* ARM64Instr_VBinV ( ARM64VecBinOp op, -+ HReg dst, HReg argL, HReg argR ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VBinV; -+ i->ARM64in.VBinV.op = op; -+ i->ARM64in.VBinV.dst = dst; -+ i->ARM64in.VBinV.argL = argL; -+ i->ARM64in.VBinV.argR = argR; -+ return i; -+} -+ARM64Instr* ARM64Instr_VUnaryV ( ARM64VecUnaryOp op, HReg dst, HReg arg ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VUnaryV; -+ i->ARM64in.VUnaryV.op = op; -+ i->ARM64in.VUnaryV.dst = dst; -+ i->ARM64in.VUnaryV.arg = arg; -+ return i; -+} -+ARM64Instr* ARM64Instr_VNarrowV ( UInt dszBlg2, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VNarrowV; -+ i->ARM64in.VNarrowV.dszBlg2 = dszBlg2; -+ i->ARM64in.VNarrowV.dst = dst; -+ i->ARM64in.VNarrowV.src = src; -+ vassert(dszBlg2 == 0 || dszBlg2 == 1 || dszBlg2 == 2); -+ return i; -+} -+ARM64Instr* ARM64Instr_VShiftImmV ( ARM64VecShiftOp op, -+ HReg dst, HReg src, UInt amt ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VShiftImmV; -+ i->ARM64in.VShiftImmV.op = op; -+ i->ARM64in.VShiftImmV.dst = dst; -+ i->ARM64in.VShiftImmV.src = src; -+ i->ARM64in.VShiftImmV.amt = amt; -+ UInt maxSh = 0; -+ switch (op) { -+ case ARM64vecsh_USHR64x2: case ARM64vecsh_SSHR64x2: -+ case ARM64vecsh_SHL64x2: -+ maxSh = 63; break; -+ case ARM64vecsh_USHR32x4: case ARM64vecsh_SSHR32x4: -+ case ARM64vecsh_SHL32x4: -+ maxSh = 31; break; -+ case ARM64vecsh_USHR16x8: case ARM64vecsh_SSHR16x8: -+ case ARM64vecsh_SHL16x8: -+ maxSh = 15; break; -+ case ARM64vecsh_USHR8x16: case ARM64vecsh_SSHR8x16: -+ case ARM64vecsh_SHL8x16: -+ maxSh = 7; break; -+ default: -+ vassert(0); -+ } -+ vassert(maxSh > 0); -+ vassert(amt > 0 && amt <= maxSh); -+ return i; -+} -+//ZZ ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg dst, HReg argL, HReg argR ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VAluS; -+//ZZ i->ARMin.VAluS.op = op; -+//ZZ i->ARMin.VAluS.dst = dst; -+//ZZ i->ARMin.VAluS.argL = argL; -+//ZZ i->ARMin.VAluS.argR = argR; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VCMovD ( ARMCondCode cond, HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VCMovD; -+//ZZ i->ARMin.VCMovD.cond = cond; -+//ZZ i->ARMin.VCMovD.dst = dst; -+//ZZ i->ARMin.VCMovD.src = src; -+//ZZ vassert(cond != ARMcc_AL); -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VCMovS ( ARMCondCode cond, HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VCMovS; -+//ZZ i->ARMin.VCMovS.cond = cond; -+//ZZ i->ARMin.VCMovS.dst = dst; -+//ZZ i->ARMin.VCMovS.src = src; -+//ZZ vassert(cond != ARMcc_AL); -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VXferD; -+//ZZ i->ARMin.VXferD.toD = toD; -+//ZZ i->ARMin.VXferD.dD = dD; -+//ZZ i->ARMin.VXferD.rHi = rHi; -+//ZZ i->ARMin.VXferD.rLo = rLo; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VXferS; -+//ZZ i->ARMin.VXferS.toS = toS; -+//ZZ i->ARMin.VXferS.fD = fD; -+//ZZ i->ARMin.VXferS.rLo = rLo; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned, -+//ZZ HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_VCvtID; -+//ZZ i->ARMin.VCvtID.iToD = iToD; -+//ZZ i->ARMin.VCvtID.syned = syned; -+//ZZ i->ARMin.VCvtID.dst = dst; -+//ZZ i->ARMin.VCvtID.src = src; -+//ZZ return i; -+//ZZ } -+//ZZ ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg dD, ARMAModeN *amode ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NLdStD; -+//ZZ i->ARMin.NLdStD.isLoad = isLoad; -+//ZZ i->ARMin.NLdStD.dD = dD; -+//ZZ i->ARMin.NLdStD.amode = amode; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp op, HReg dQ, HReg nQ, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NUnary; -+//ZZ i->ARMin.NUnary.op = op; -+//ZZ i->ARMin.NUnary.src = nQ; -+//ZZ i->ARMin.NUnary.dst = dQ; -+//ZZ i->ARMin.NUnary.size = size; -+//ZZ i->ARMin.NUnary.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS op, ARMNRS* dst, ARMNRS* src, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NUnaryS; -+//ZZ i->ARMin.NUnaryS.op = op; -+//ZZ i->ARMin.NUnaryS.src = src; -+//ZZ i->ARMin.NUnaryS.dst = dst; -+//ZZ i->ARMin.NUnaryS.size = size; -+//ZZ i->ARMin.NUnaryS.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NDual ( ARMNeonDualOp op, HReg nQ, HReg mQ, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NDual; -+//ZZ i->ARMin.NDual.op = op; -+//ZZ i->ARMin.NDual.arg1 = nQ; -+//ZZ i->ARMin.NDual.arg2 = mQ; -+//ZZ i->ARMin.NDual.size = size; -+//ZZ i->ARMin.NDual.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp op, -+//ZZ HReg dst, HReg argL, HReg argR, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NBinary; -+//ZZ i->ARMin.NBinary.op = op; -+//ZZ i->ARMin.NBinary.argL = argL; -+//ZZ i->ARMin.NBinary.argR = argR; -+//ZZ i->ARMin.NBinary.dst = dst; -+//ZZ i->ARMin.NBinary.size = size; -+//ZZ i->ARMin.NBinary.Q = Q; -+//ZZ return i; -+//ZZ } -+ -+ARM64Instr* ARM64Instr_VImmQ (HReg rQ, UShort imm) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VImmQ; -+ i->ARM64in.VImmQ.rQ = rQ; -+ i->ARM64in.VImmQ.imm = imm; -+ return i; -+} -+ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VDfromX; -+ i->ARM64in.VDfromX.rD = rD; -+ i->ARM64in.VDfromX.rX = rX; -+ return i; -+} -+ARM64Instr* ARM64Instr_VQfromXX ( HReg rQ, HReg rXhi, HReg rXlo ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VQfromXX; -+ i->ARM64in.VQfromXX.rQ = rQ; -+ i->ARM64in.VQfromXX.rXhi = rXhi; -+ i->ARM64in.VQfromXX.rXlo = rXlo; -+ return i; -+} -+ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VXfromQ; -+ i->ARM64in.VXfromQ.rX = rX; -+ i->ARM64in.VXfromQ.rQ = rQ; -+ i->ARM64in.VXfromQ.laneNo = laneNo; -+ vassert(laneNo <= 1); -+ return i; -+} -+ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_VMov; -+ i->ARM64in.VMov.szB = szB; -+ i->ARM64in.VMov.dst = dst; -+ i->ARM64in.VMov.src = src; -+ switch (szB) { -+ case 16: -+ vassert(hregClass(src) == HRcVec128); -+ vassert(hregClass(dst) == HRcVec128); -+ break; -+ case 8: -+ vassert(hregClass(src) == HRcFlt64); -+ vassert(hregClass(dst) == HRcFlt64); -+ break; -+ default: -+ vpanic("ARM64Instr_VMov"); -+ } -+ return i; -+} -+ -+//ZZ ARMInstr* ARMInstr_NCMovQ ( ARMCondCode cond, HReg dst, HReg src ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NCMovQ; -+//ZZ i->ARMin.NCMovQ.cond = cond; -+//ZZ i->ARMin.NCMovQ.dst = dst; -+//ZZ i->ARMin.NCMovQ.src = src; -+//ZZ vassert(cond != ARMcc_AL); -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp op, -+//ZZ HReg dst, HReg argL, HReg argR, -+//ZZ UInt size, Bool Q ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NShift; -+//ZZ i->ARMin.NShift.op = op; -+//ZZ i->ARMin.NShift.argL = argL; -+//ZZ i->ARMin.NShift.argR = argR; -+//ZZ i->ARMin.NShift.dst = dst; -+//ZZ i->ARMin.NShift.size = size; -+//ZZ i->ARMin.NShift.Q = Q; -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_NShl64 ( HReg dst, HReg src, UInt amt ) -+//ZZ { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_NShl64; -+//ZZ i->ARMin.NShl64.dst = dst; -+//ZZ i->ARMin.NShl64.src = src; -+//ZZ i->ARMin.NShl64.amt = amt; -+//ZZ vassert(amt >= 1 && amt <= 63); -+//ZZ return i; -+//ZZ } -+//ZZ -+//ZZ /* Helper copy-pasted from isel.c */ -+//ZZ static Bool fitsIn8x4 ( UInt* u8, UInt* u4, UInt u ) -+//ZZ { -+//ZZ UInt i; -+//ZZ for (i = 0; i < 16; i++) { -+//ZZ if (0 == (u & 0xFFFFFF00)) { -+//ZZ *u8 = u; -+//ZZ *u4 = i; -+//ZZ return True; -+//ZZ } -+//ZZ u = ROR32(u, 30); -+//ZZ } -+//ZZ vassert(i == 16); -+//ZZ return False; -+//ZZ } -+//ZZ -+//ZZ ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) { -+//ZZ UInt u8, u4; -+//ZZ ARMInstr *i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ /* Try to generate single ADD if possible */ -+//ZZ if (fitsIn8x4(&u8, &u4, imm32)) { -+//ZZ i->tag = ARMin_Alu; -+//ZZ i->ARMin.Alu.op = ARMalu_ADD; -+//ZZ i->ARMin.Alu.dst = rD; -+//ZZ i->ARMin.Alu.argL = rN; -+//ZZ i->ARMin.Alu.argR = ARMRI84_I84(u8, u4); -+//ZZ } else { -+//ZZ i->tag = ARMin_Add32; -+//ZZ i->ARMin.Add32.rD = rD; -+//ZZ i->ARMin.Add32.rN = rN; -+//ZZ i->ARMin.Add32.imm32 = imm32; -+//ZZ } -+//ZZ return i; -+//ZZ } -+ -+ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter, -+ ARM64AMode* amFailAddr ) { -+ ARM64Instr* i = LibVEX_Alloc(sizeof(ARM64Instr)); -+ i->tag = ARM64in_EvCheck; -+ i->ARM64in.EvCheck.amCounter = amCounter; -+ i->ARM64in.EvCheck.amFailAddr = amFailAddr; -+ return i; -+} -+ -+//ZZ ARMInstr* ARMInstr_ProfInc ( void ) { -+//ZZ ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr)); -+//ZZ i->tag = ARMin_ProfInc; -+//ZZ return i; -+//ZZ } -+ -+/* ... */ -+ -+void ppARM64Instr ( ARM64Instr* i ) { -+ switch (i->tag) { -+ case ARM64in_Arith: -+ vex_printf("%s ", i->ARM64in.Arith.isAdd ? "add" : "sub"); -+ ppHRegARM64(i->ARM64in.Arith.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Arith.argL); -+ vex_printf(", "); -+ ppARM64RIA(i->ARM64in.Arith.argR); -+ return; -+ case ARM64in_Cmp: -+ vex_printf("cmp%s ", i->ARM64in.Cmp.is64 ? " " : "(w)" ); -+ ppHRegARM64(i->ARM64in.Cmp.argL); -+ vex_printf(", "); -+ ppARM64RIA(i->ARM64in.Cmp.argR); -+ return; -+ case ARM64in_Logic: -+ vex_printf("%s ", showARM64LogicOp(i->ARM64in.Logic.op)); -+ ppHRegARM64(i->ARM64in.Logic.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Logic.argL); -+ vex_printf(", "); -+ ppARM64RIL(i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Test: -+ vex_printf("tst "); -+ ppHRegARM64(i->ARM64in.Test.argL); -+ vex_printf(", "); -+ ppARM64RIL(i->ARM64in.Test.argR); -+ return; -+ case ARM64in_Shift: -+ vex_printf("%s ", showARM64ShiftOp(i->ARM64in.Shift.op)); -+ ppHRegARM64(i->ARM64in.Shift.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Shift.argL); -+ vex_printf(", "); -+ ppARM64RI6(i->ARM64in.Shift.argR); -+ return; -+ case ARM64in_Unary: -+ vex_printf("%s ", showARM64UnaryOp(i->ARM64in.Unary.op)); -+ ppHRegARM64(i->ARM64in.Unary.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Unary.src); -+ return; -+ case ARM64in_MovI: -+ vex_printf("mov "); -+ ppHRegARM64(i->ARM64in.MovI.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.MovI.src); -+ return; -+ case ARM64in_Imm64: -+ vex_printf("imm64 "); -+ ppHRegARM64(i->ARM64in.Imm64.dst); -+ vex_printf(", 0x%llx", i->ARM64in.Imm64.imm64); -+ return; -+ case ARM64in_LdSt64: -+ if (i->ARM64in.LdSt64.isLoad) { -+ vex_printf("ldr "); -+ ppHRegARM64(i->ARM64in.LdSt64.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt64.amode); -+ } else { -+ vex_printf("str "); -+ ppARM64AMode(i->ARM64in.LdSt64.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt64.rD); -+ } -+ return; -+ case ARM64in_LdSt32: -+ if (i->ARM64in.LdSt32.isLoad) { -+ vex_printf("ldruw "); -+ ppHRegARM64(i->ARM64in.LdSt32.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt32.amode); -+ } else { -+ vex_printf("strw "); -+ ppARM64AMode(i->ARM64in.LdSt32.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt32.rD); -+ } -+ return; -+ case ARM64in_LdSt16: -+ if (i->ARM64in.LdSt16.isLoad) { -+ vex_printf("ldruh "); -+ ppHRegARM64(i->ARM64in.LdSt16.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt16.amode); -+ } else { -+ vex_printf("strh "); -+ ppARM64AMode(i->ARM64in.LdSt16.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt16.rD); -+ } -+ return; -+ case ARM64in_LdSt8: -+ if (i->ARM64in.LdSt8.isLoad) { -+ vex_printf("ldrub "); -+ ppHRegARM64(i->ARM64in.LdSt8.rD); -+ vex_printf(", "); -+ ppARM64AMode(i->ARM64in.LdSt8.amode); -+ } else { -+ vex_printf("strb "); -+ ppARM64AMode(i->ARM64in.LdSt8.amode); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.LdSt8.rD); -+ } -+ return; -+ case ARM64in_XDirect: -+ vex_printf("(xDirect) "); -+ vex_printf("if (%%pstate.%s) { ", -+ showARM64CondCode(i->ARM64in.XDirect.cond)); -+ vex_printf("imm64 x9,0x%llx; ", i->ARM64in.XDirect.dstGA); -+ vex_printf("str x9,"); -+ ppARM64AMode(i->ARM64in.XDirect.amPC); -+ vex_printf("; imm64-exactly4 x9,$disp_cp_chain_me_to_%sEP; ", -+ i->ARM64in.XDirect.toFastEP ? "fast" : "slow"); -+ vex_printf("blr x9 }"); -+ return; -+ case ARM64in_XIndir: -+ vex_printf("(xIndir) "); -+ vex_printf("if (%%pstate.%s) { ", -+ showARM64CondCode(i->ARM64in.XIndir.cond)); -+ vex_printf("str "); -+ ppHRegARM64(i->ARM64in.XIndir.dstGA); -+ vex_printf(","); -+ ppARM64AMode(i->ARM64in.XIndir.amPC); -+ vex_printf("; imm64 x9,$disp_cp_xindir; "); -+ vex_printf("br x9 }"); -+ return; -+ case ARM64in_XAssisted: -+ vex_printf("(xAssisted) "); -+ vex_printf("if (%%pstate.%s) { ", -+ showARM64CondCode(i->ARM64in.XAssisted.cond)); -+ vex_printf("str "); -+ ppHRegARM64(i->ARM64in.XAssisted.dstGA); -+ vex_printf(","); -+ ppARM64AMode(i->ARM64in.XAssisted.amPC); -+ vex_printf("; movw x21,$IRJumpKind_to_TRCVAL(%d); ", -+ (Int)i->ARM64in.XAssisted.jk); -+ vex_printf("imm64 x9,$disp_cp_xassisted; "); -+ vex_printf("br x9 }"); -+ return; -+ case ARM64in_CSel: -+ vex_printf("csel "); -+ ppHRegARM64(i->ARM64in.CSel.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.CSel.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.CSel.argR); -+ vex_printf(", %s", showARM64CondCode(i->ARM64in.CSel.cond)); -+ return; -+ case ARM64in_Call: -+ vex_printf("call%s ", -+ i->ARM64in.Call.cond==ARM64cc_AL -+ ? " " : showARM64CondCode(i->ARM64in.Call.cond)); -+ vex_printf("0x%lx [nArgRegs=%d, ", -+ i->ARM64in.Call.target, i->ARM64in.Call.nArgRegs); -+ ppRetLoc(i->ARM64in.Call.rloc); -+ vex_printf("]"); -+ return; -+ case ARM64in_AddToSP: { -+ Int simm = i->ARM64in.AddToSP.simm; -+ vex_printf("%s xsp, xsp, #%d", simm < 0 ? "sub" : "add", -+ simm < 0 ? -simm : simm); -+ return; -+ } -+ case ARM64in_FromSP: -+ vex_printf("mov "); -+ ppHRegARM64(i->ARM64in.FromSP.dst); -+ vex_printf(", xsp"); -+ return; -+ case ARM64in_Mul: -+ vex_printf("%s ", showARM64MulOp(i->ARM64in.Mul.op)); -+ ppHRegARM64(i->ARM64in.Mul.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Mul.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.Mul.argR); -+ return; -+ -+ case ARM64in_LdrEX: { -+ const HChar* sz = " "; -+ switch (i->ARM64in.LdrEX.szB) { -+ case 1: sz = "b"; break; -+ case 2: sz = "h"; break; -+ case 4: case 8: break; -+ default: vassert(0); -+ } -+ vex_printf("ldxr%s %c2, [x4]", -+ sz, i->ARM64in.LdrEX.szB == 8 ? 'x' : 'w'); -+ return; -+ } -+ case ARM64in_StrEX: { -+ const HChar* sz = " "; -+ switch (i->ARM64in.StrEX.szB) { -+ case 1: sz = "b"; break; -+ case 2: sz = "h"; break; -+ case 4: case 8: break; -+ default: vassert(0); -+ } -+ vex_printf("stxr%s w0, %c2, [x4]", -+ sz, i->ARM64in.StrEX.szB == 8 ? 'x' : 'w'); -+ return; -+ } -+ case ARM64in_MFence: -+ vex_printf("(mfence) dsb sy; dmb sy; isb"); -+ return; -+//ZZ case ARM64in_CLREX: -+//ZZ vex_printf("clrex"); -+//ZZ return; -+ case ARM64in_VLdStS: -+ if (i->ARM64in.VLdStS.isLoad) { -+ vex_printf("ldr "); -+ ppHRegARM64asSreg(i->ARM64in.VLdStS.sD); -+ vex_printf(", %u(", i->ARM64in.VLdStS.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStS.rN); -+ vex_printf(")"); -+ } else { -+ vex_printf("str "); -+ vex_printf("%u(", i->ARM64in.VLdStS.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStS.rN); -+ vex_printf("), "); -+ ppHRegARM64asSreg(i->ARM64in.VLdStS.sD); -+ } -+ return; -+ case ARM64in_VLdStD: -+ if (i->ARM64in.VLdStD.isLoad) { -+ vex_printf("ldr "); -+ ppHRegARM64(i->ARM64in.VLdStD.dD); -+ vex_printf(", %u(", i->ARM64in.VLdStD.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStD.rN); -+ vex_printf(")"); -+ } else { -+ vex_printf("str "); -+ vex_printf("%u(", i->ARM64in.VLdStD.uimm12); -+ ppHRegARM64(i->ARM64in.VLdStD.rN); -+ vex_printf("), "); -+ ppHRegARM64(i->ARM64in.VLdStD.dD); -+ } -+ return; -+ case ARM64in_VLdStQ: -+ if (i->ARM64in.VLdStQ.isLoad) -+ vex_printf("ld1.2d {"); -+ else -+ vex_printf("st1.2d {"); -+ ppHRegARM64(i->ARM64in.VLdStQ.rQ); -+ vex_printf("}, ["); -+ ppHRegARM64(i->ARM64in.VLdStQ.rN); -+ vex_printf("]"); -+ return; -+ case ARM64in_VCvtI2F: { -+ HChar syn = '?'; -+ UInt fszB = 0; -+ UInt iszB = 0; -+ characteriseARM64CvtOp(&syn, &fszB, &iszB, i->ARM64in.VCvtI2F.how); -+ vex_printf("%ccvtf ", syn); -+ ppHRegARM64(i->ARM64in.VCvtI2F.rD); -+ vex_printf("(%c-reg), ", fszB == 4 ? 'S' : 'D'); -+ ppHRegARM64(i->ARM64in.VCvtI2F.rS); -+ vex_printf("(%c-reg)", iszB == 4 ? 'W' : 'X'); -+ return; -+ } -+ case ARM64in_VCvtF2I: { -+ HChar syn = '?'; -+ UInt fszB = 0; -+ UInt iszB = 0; -+ HChar rmo = '?'; -+ characteriseARM64CvtOp(&syn, &fszB, &iszB, i->ARM64in.VCvtF2I.how); -+ UChar armRM = i->ARM64in.VCvtF2I.armRM; -+ if (armRM < 4) rmo = "npmz"[armRM]; -+ vex_printf("fcvt%c%c ", rmo, syn); -+ ppHRegARM64(i->ARM64in.VCvtF2I.rD); -+ vex_printf("(%c-reg), ", iszB == 4 ? 'W' : 'X'); -+ ppHRegARM64(i->ARM64in.VCvtF2I.rS); -+ vex_printf("(%c-reg)", fszB == 4 ? 'S' : 'D'); -+ return; -+ } -+ case ARM64in_VCvtSD: -+ vex_printf("fcvt%s ", i->ARM64in.VCvtSD.sToD ? "s2d" : "d2s"); -+ if (i->ARM64in.VCvtSD.sToD) { -+ ppHRegARM64(i->ARM64in.VCvtSD.dst); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VCvtSD.src); -+ } else { -+ ppHRegARM64asSreg(i->ARM64in.VCvtSD.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VCvtSD.src); -+ } -+ return; -+ case ARM64in_VUnaryD: -+ vex_printf("f%s ", showARM64FpUnaryOp(i->ARM64in.VUnaryD.op)); -+ ppHRegARM64(i->ARM64in.VUnaryD.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VUnaryD.src); -+ return; -+ case ARM64in_VUnaryS: -+ vex_printf("f%s ", showARM64FpUnaryOp(i->ARM64in.VUnaryS.op)); -+ ppHRegARM64asSreg(i->ARM64in.VUnaryS.dst); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VUnaryS.src); -+ return; -+ case ARM64in_VBinD: -+ vex_printf("f%s ", showARM64FpBinOp(i->ARM64in.VBinD.op)); -+ ppHRegARM64(i->ARM64in.VBinD.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VBinD.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VBinD.argR); -+ return; -+ case ARM64in_VBinS: -+ vex_printf("f%s ", showARM64FpBinOp(i->ARM64in.VBinS.op)); -+ ppHRegARM64asSreg(i->ARM64in.VBinS.dst); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VBinS.argL); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VBinS.argR); -+ return; -+ case ARM64in_VCmpD: -+ vex_printf("fcmp "); -+ ppHRegARM64(i->ARM64in.VCmpD.argL); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VCmpD.argR); -+ return; -+ case ARM64in_VCmpS: -+ vex_printf("fcmp "); -+ ppHRegARM64asSreg(i->ARM64in.VCmpS.argL); -+ vex_printf(", "); -+ ppHRegARM64asSreg(i->ARM64in.VCmpS.argR); -+ return; -+ case ARM64in_FPCR: -+ if (i->ARM64in.FPCR.toFPCR) { -+ vex_printf("msr fpcr, "); -+ ppHRegARM64(i->ARM64in.FPCR.iReg); -+ } else { -+ vex_printf("mrs "); -+ ppHRegARM64(i->ARM64in.FPCR.iReg); -+ vex_printf(", fpcr"); -+ } -+ return; -+ case ARM64in_VBinV: { -+ const HChar* nm = "??"; -+ const HChar* ar = "??"; -+ showARM64VecBinOp(&nm, &ar, i->ARM64in.VBinV.op); -+ vex_printf("%s ", nm); -+ ppHRegARM64(i->ARM64in.VBinV.dst); -+ vex_printf(".%s, ", ar); -+ ppHRegARM64(i->ARM64in.VBinV.argL); -+ vex_printf(".%s, ", ar); -+ ppHRegARM64(i->ARM64in.VBinV.argR); -+ vex_printf(".%s", ar); -+ return; -+ } -+ case ARM64in_VUnaryV: { -+ const HChar* nm = "??"; -+ const HChar* ar = "??"; -+ showARM64VecUnaryOp(&nm, &ar, i->ARM64in.VUnaryV.op); -+ vex_printf("%s ", nm); -+ ppHRegARM64(i->ARM64in.VUnaryV.dst); -+ vex_printf(".%s, ", ar); -+ ppHRegARM64(i->ARM64in.VUnaryV.arg); -+ vex_printf(".%s", ar); -+ return; -+ } -+ case ARM64in_VNarrowV: { -+ UInt dszBlg2 = i->ARM64in.VNarrowV.dszBlg2; -+ const HChar* darr[3] = { "8b", "4h", "2s" }; -+ const HChar* sarr[3] = { "8h", "4s", "2d" }; -+ vex_printf("xtn "); -+ ppHRegARM64(i->ARM64in.VNarrowV.dst); -+ vex_printf(".%s, ", dszBlg2 < 3 ? darr[dszBlg2] : "??"); -+ ppHRegARM64(i->ARM64in.VNarrowV.src); -+ vex_printf(".%s", dszBlg2 < 3 ? sarr[dszBlg2] : "??"); -+ return; -+ } -+ case ARM64in_VShiftImmV: { -+ const HChar* nm = "??"; -+ const HChar* ar = "??"; -+ showARM64VecShiftOp(&nm, &ar, i->ARM64in.VShiftImmV.op); -+ vex_printf("%s ", nm); -+ ppHRegARM64(i->ARM64in.VShiftImmV.dst); -+ vex_printf(".%s, ", ar); -+ ppHRegARM64(i->ARM64in.VShiftImmV.src); -+ vex_printf(".%s, #%u", ar, i->ARM64in.VShiftImmV.amt); -+ return; -+ } -+//ZZ case ARMin_VAluS: -+//ZZ vex_printf("f%-3ss ", showARMVfpOp(i->ARMin.VAluS.op)); -+//ZZ ppHRegARM(i->ARMin.VAluS.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VAluS.argL); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VAluS.argR); -+//ZZ return; -+//ZZ case ARMin_VCMovD: -+//ZZ vex_printf("fcpyd%s ", showARMCondCode(i->ARMin.VCMovD.cond)); -+//ZZ ppHRegARM(i->ARMin.VCMovD.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VCMovD.src); -+//ZZ return; -+//ZZ case ARMin_VCMovS: -+//ZZ vex_printf("fcpys%s ", showARMCondCode(i->ARMin.VCMovS.cond)); -+//ZZ ppHRegARM(i->ARMin.VCMovS.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VCMovS.src); -+//ZZ return; -+//ZZ case ARMin_VXferD: -+//ZZ vex_printf("vmov "); -+//ZZ if (i->ARMin.VXferD.toD) { -+//ZZ ppHRegARM(i->ARMin.VXferD.dD); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.rLo); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.rHi); -+//ZZ } else { -+//ZZ ppHRegARM(i->ARMin.VXferD.rLo); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.rHi); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferD.dD); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VXferS: -+//ZZ vex_printf("vmov "); -+//ZZ if (i->ARMin.VXferS.toS) { -+//ZZ ppHRegARM(i->ARMin.VXferS.fD); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferS.rLo); -+//ZZ } else { -+//ZZ ppHRegARM(i->ARMin.VXferS.rLo); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VXferS.fD); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VCvtID: { -+//ZZ const HChar* nm = "?"; -+//ZZ if (i->ARMin.VCvtID.iToD) { -+//ZZ nm = i->ARMin.VCvtID.syned ? "fsitod" : "fuitod"; -+//ZZ } else { -+//ZZ nm = i->ARMin.VCvtID.syned ? "ftosid" : "ftouid"; -+//ZZ } -+//ZZ vex_printf("%s ", nm); -+//ZZ ppHRegARM(i->ARMin.VCvtID.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.VCvtID.src); -+//ZZ return; -+//ZZ } -+//ZZ case ARMin_NLdStD: -+//ZZ if (i->ARMin.NLdStD.isLoad) -+//ZZ vex_printf("vld1.32 {"); -+//ZZ else -+//ZZ vex_printf("vst1.32 {"); -+//ZZ ppHRegARM(i->ARMin.NLdStD.dD); -+//ZZ vex_printf("} "); -+//ZZ ppARMAModeN(i->ARMin.NLdStD.amode); -+//ZZ return; -+//ZZ case ARMin_NUnary: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonUnOp(i->ARMin.NUnary.op), -+//ZZ showARMNeonUnOpDataType(i->ARMin.NUnary.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppHRegARM(i->ARMin.NUnary.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NUnary.src); -+//ZZ if (i->ARMin.NUnary.op == ARMneon_EQZ) -+//ZZ vex_printf(", #0"); -+//ZZ if (i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF || -+//ZZ i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF) { -+//ZZ vex_printf(", #%d", i->ARMin.NUnary.size); -+//ZZ } -+//ZZ if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUU || -+//ZZ i->ARMin.NUnary.op == ARMneon_VQSHLNUS) { -+//ZZ UInt size; -+//ZZ size = i->ARMin.NUnary.size; -+//ZZ if (size & 0x40) { -+//ZZ vex_printf(", #%d", size - 64); -+//ZZ } else if (size & 0x20) { -+//ZZ vex_printf(", #%d", size - 32); -+//ZZ } else if (size & 0x10) { -+//ZZ vex_printf(", #%d", size - 16); -+//ZZ } else if (size & 0x08) { -+//ZZ vex_printf(", #%d", size - 8); -+//ZZ } -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_NUnaryS: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonUnOpS(i->ARMin.NUnaryS.op), -+//ZZ showARMNeonUnOpSDataType(i->ARMin.NUnaryS.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppARMNRS(i->ARMin.NUnaryS.dst); -+//ZZ vex_printf(", "); -+//ZZ ppARMNRS(i->ARMin.NUnaryS.src); -+//ZZ return; -+//ZZ case ARMin_NShift: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonShiftOp(i->ARMin.NShift.op), -+//ZZ showARMNeonShiftOpDataType(i->ARMin.NShift.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppHRegARM(i->ARMin.NShift.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NShift.argL); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NShift.argR); -+//ZZ return; -+//ZZ case ARMin_NShl64: -+//ZZ vex_printf("vshl.i64 "); -+//ZZ ppHRegARM(i->ARMin.NShl64.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NShl64.src); -+//ZZ vex_printf(", #%u", i->ARMin.NShl64.amt); -+//ZZ return; -+//ZZ case ARMin_NDual: -+//ZZ vex_printf("%s%s%s ", -+//ZZ showARMNeonDualOp(i->ARMin.NDual.op), -+//ZZ showARMNeonDualOpDataType(i->ARMin.NDual.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ ppHRegARM(i->ARMin.NDual.arg1); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NDual.arg2); -+//ZZ return; -+//ZZ case ARMin_NBinary: -+//ZZ vex_printf("%s%s%s", -+//ZZ showARMNeonBinOp(i->ARMin.NBinary.op), -+//ZZ showARMNeonBinOpDataType(i->ARMin.NBinary.op), -+//ZZ showARMNeonDataSize(i)); -+//ZZ vex_printf(" "); -+//ZZ ppHRegARM(i->ARMin.NBinary.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NBinary.argL); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NBinary.argR); -+//ZZ return; -+ case ARM64in_VImmQ: -+ vex_printf("qimm "); -+ ppHRegARM64(i->ARM64in.VImmQ.rQ); -+ vex_printf(", Bits16toBytes16(0x%x)", (UInt)i->ARM64in.VImmQ.imm); -+ return; -+ case ARM64in_VDfromX: -+ vex_printf("fmov "); -+ ppHRegARM64(i->ARM64in.VDfromX.rD); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VDfromX.rX); -+ return; -+ case ARM64in_VQfromXX: -+ vex_printf("qFromXX "); -+ ppHRegARM64(i->ARM64in.VQfromXX.rQ); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VQfromXX.rXhi); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VQfromXX.rXlo); -+ return; -+ case ARM64in_VXfromQ: -+ vex_printf("mov "); -+ ppHRegARM64(i->ARM64in.VXfromQ.rX); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VXfromQ.rQ); -+ vex_printf(".d[%u]", i->ARM64in.VXfromQ.laneNo); -+ return; -+ case ARM64in_VMov: { -+ UChar aux = '?'; -+ switch (i->ARM64in.VMov.szB) { -+ case 16: aux = 'q'; break; -+ case 8: aux = 'd'; break; -+ case 4: aux = 's'; break; -+ default: break; -+ } -+ vex_printf("mov(%c) ", aux); -+ ppHRegARM64(i->ARM64in.VMov.dst); -+ vex_printf(", "); -+ ppHRegARM64(i->ARM64in.VMov.src); -+ return; -+ } -+//ZZ case ARMin_NCMovQ: -+//ZZ vex_printf("vmov%s ", showARMCondCode(i->ARMin.NCMovQ.cond)); -+//ZZ ppHRegARM(i->ARMin.NCMovQ.dst); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.NCMovQ.src); -+//ZZ return; -+//ZZ case ARMin_Add32: -+//ZZ vex_printf("add32 "); -+//ZZ ppHRegARM(i->ARMin.Add32.rD); -+//ZZ vex_printf(", "); -+//ZZ ppHRegARM(i->ARMin.Add32.rN); -+//ZZ vex_printf(", "); -+//ZZ vex_printf("%d", i->ARMin.Add32.imm32); -+//ZZ return; -+ case ARM64in_EvCheck: -+ vex_printf("(evCheck) ldr w9,"); -+ ppARM64AMode(i->ARM64in.EvCheck.amCounter); -+ vex_printf("; subs w9,w9,$1; str w9,"); -+ ppARM64AMode(i->ARM64in.EvCheck.amCounter); -+ vex_printf("; bpl nofail; ldr x9,"); -+ ppARM64AMode(i->ARM64in.EvCheck.amFailAddr); -+ vex_printf("; br x9; nofail:"); -+ return; -+//ZZ case ARMin_ProfInc: -+//ZZ vex_printf("(profInc) movw r12,LO16($NotKnownYet); " -+//ZZ "movw r12,HI16($NotKnownYet); " -+//ZZ "ldr r11,[r12]; " -+//ZZ "adds r11,r11,$1; " -+//ZZ "str r11,[r12]; " -+//ZZ "ldr r11,[r12+4]; " -+//ZZ "adc r11,r11,$0; " -+//ZZ "str r11,[r12+4]"); -+//ZZ return; -+ default: -+ vex_printf("ppARM64Instr: unhandled case (tag %d)", (Int)i->tag); -+ vpanic("ppARM64Instr(1)"); -+ return; -+ } -+} -+ -+ -+/* --------- Helpers for register allocation. --------- */ -+ -+void getRegUsage_ARM64Instr ( HRegUsage* u, ARM64Instr* i, Bool mode64 ) -+{ -+ vassert(mode64 == True); -+ initHRegUsage(u); -+ switch (i->tag) { -+ case ARM64in_Arith: -+ addHRegUse(u, HRmWrite, i->ARM64in.Arith.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Arith.argL); -+ addRegUsage_ARM64RIA(u, i->ARM64in.Arith.argR); -+ return; -+ case ARM64in_Cmp: -+ addHRegUse(u, HRmRead, i->ARM64in.Cmp.argL); -+ addRegUsage_ARM64RIA(u, i->ARM64in.Cmp.argR); -+ return; -+ case ARM64in_Logic: -+ addHRegUse(u, HRmWrite, i->ARM64in.Logic.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Logic.argL); -+ addRegUsage_ARM64RIL(u, i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Test: -+ addHRegUse(u, HRmRead, i->ARM64in.Test.argL); -+ addRegUsage_ARM64RIL(u, i->ARM64in.Test.argR); -+ return; -+ case ARM64in_Shift: -+ addHRegUse(u, HRmWrite, i->ARM64in.Shift.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Shift.argL); -+ addRegUsage_ARM64RI6(u, i->ARM64in.Shift.argR); -+ return; -+ case ARM64in_Unary: -+ addHRegUse(u, HRmWrite, i->ARM64in.Unary.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Unary.src); -+ return; -+ case ARM64in_MovI: -+ addHRegUse(u, HRmWrite, i->ARM64in.MovI.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.MovI.src); -+ return; -+ case ARM64in_Imm64: -+ addHRegUse(u, HRmWrite, i->ARM64in.Imm64.dst); -+ return; -+ case ARM64in_LdSt64: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt64.amode); -+ if (i->ARM64in.LdSt64.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt64.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt64.rD); -+ } -+ return; -+ case ARM64in_LdSt32: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt32.amode); -+ if (i->ARM64in.LdSt32.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt32.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt32.rD); -+ } -+ return; -+ case ARM64in_LdSt16: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt16.amode); -+ if (i->ARM64in.LdSt16.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt16.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt16.rD); -+ } -+ return; -+ case ARM64in_LdSt8: -+ addRegUsage_ARM64AMode(u, i->ARM64in.LdSt8.amode); -+ if (i->ARM64in.LdSt8.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.LdSt8.rD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.LdSt8.rD); -+ } -+ return; -+ /* XDirect/XIndir/XAssisted are also a bit subtle. They -+ conditionally exit the block. Hence we only need to list (1) -+ the registers that they read, and (2) the registers that they -+ write in the case where the block is not exited. (2) is -+ empty, hence only (1) is relevant here. */ -+ case ARM64in_XDirect: -+ addRegUsage_ARM64AMode(u, i->ARM64in.XDirect.amPC); -+ return; -+ case ARM64in_XIndir: -+ addHRegUse(u, HRmRead, i->ARM64in.XIndir.dstGA); -+ addRegUsage_ARM64AMode(u, i->ARM64in.XIndir.amPC); -+ return; -+ case ARM64in_XAssisted: -+ addHRegUse(u, HRmRead, i->ARM64in.XAssisted.dstGA); -+ addRegUsage_ARM64AMode(u, i->ARM64in.XAssisted.amPC); -+ return; -+ case ARM64in_CSel: -+ addHRegUse(u, HRmWrite, i->ARM64in.CSel.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.CSel.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.CSel.argR); -+ return; -+ case ARM64in_Call: -+ /* logic and comments copied/modified from x86 back end */ -+ /* This is a bit subtle. */ -+ /* First off, claim it trashes all the caller-saved regs -+ which fall within the register allocator's jurisdiction. -+ These I believe to be x0 to x7. Also need to be -+ careful about vector regs. */ -+ addHRegUse(u, HRmWrite, hregARM64_X0()); -+ addHRegUse(u, HRmWrite, hregARM64_X1()); -+ addHRegUse(u, HRmWrite, hregARM64_X2()); -+ addHRegUse(u, HRmWrite, hregARM64_X3()); -+ addHRegUse(u, HRmWrite, hregARM64_X4()); -+ addHRegUse(u, HRmWrite, hregARM64_X5()); -+ addHRegUse(u, HRmWrite, hregARM64_X6()); -+ addHRegUse(u, HRmWrite, hregARM64_X7()); -+ addHRegUse(u, HRmWrite, hregARM64_Q16()); -+ addHRegUse(u, HRmWrite, hregARM64_Q17()); -+ addHRegUse(u, HRmWrite, hregARM64_Q18()); -+ /* Now we have to state any parameter-carrying registers -+ which might be read. This depends on nArgRegs. */ -+ switch (i->ARM64in.Call.nArgRegs) { -+ case 8: addHRegUse(u, HRmRead, hregARM64_X7()); /*fallthru*/ -+ case 7: addHRegUse(u, HRmRead, hregARM64_X6()); /*fallthru*/ -+ case 6: addHRegUse(u, HRmRead, hregARM64_X5()); /*fallthru*/ -+ case 5: addHRegUse(u, HRmRead, hregARM64_X4()); /*fallthru*/ -+ case 4: addHRegUse(u, HRmRead, hregARM64_X3()); /*fallthru*/ -+ case 3: addHRegUse(u, HRmRead, hregARM64_X2()); /*fallthru*/ -+ case 2: addHRegUse(u, HRmRead, hregARM64_X1()); /*fallthru*/ -+ case 1: addHRegUse(u, HRmRead, hregARM64_X0()); break; -+ case 0: break; -+ default: vpanic("getRegUsage_ARM64:Call:regparms"); -+ } -+ /* Finally, there is the issue that the insn trashes a -+ register because the literal target address has to be -+ loaded into a register. However, we reserve x9 for that -+ purpose so there's no further complexity here. Stating x9 -+ as trashed is pointless since it's not under the control -+ of the allocator, but what the hell. */ -+ addHRegUse(u, HRmWrite, hregARM64_X9()); -+ return; -+ case ARM64in_AddToSP: -+ /* Only changes SP, but regalloc doesn't control that, hence -+ we don't care. */ -+ return; -+ case ARM64in_FromSP: -+ addHRegUse(u, HRmWrite, i->ARM64in.FromSP.dst); -+ return; -+ case ARM64in_Mul: -+ addHRegUse(u, HRmWrite, i->ARM64in.Mul.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.Mul.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.Mul.argR); -+ return; -+ case ARM64in_LdrEX: -+ addHRegUse(u, HRmRead, hregARM64_X4()); -+ addHRegUse(u, HRmWrite, hregARM64_X2()); -+ return; -+ case ARM64in_StrEX: -+ addHRegUse(u, HRmRead, hregARM64_X4()); -+ addHRegUse(u, HRmWrite, hregARM64_X0()); -+ addHRegUse(u, HRmRead, hregARM64_X2()); -+ return; -+ case ARM64in_MFence: -+ return; -+//ZZ case ARMin_CLREX: -+//ZZ return; -+ case ARM64in_VLdStS: -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStS.rN); -+ if (i->ARM64in.VLdStS.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.VLdStS.sD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStS.sD); -+ } -+ return; -+ case ARM64in_VLdStD: -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStD.rN); -+ if (i->ARM64in.VLdStD.isLoad) { -+ addHRegUse(u, HRmWrite, i->ARM64in.VLdStD.dD); -+ } else { -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStD.dD); -+ } -+ return; -+ case ARM64in_VLdStQ: -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStQ.rN); -+ if (i->ARM64in.VLdStQ.isLoad) -+ addHRegUse(u, HRmWrite, i->ARM64in.VLdStQ.rQ); -+ else -+ addHRegUse(u, HRmRead, i->ARM64in.VLdStQ.rQ); -+ return; -+ case ARM64in_VCvtI2F: -+ addHRegUse(u, HRmRead, i->ARM64in.VCvtI2F.rS); -+ addHRegUse(u, HRmWrite, i->ARM64in.VCvtI2F.rD); -+ return; -+ case ARM64in_VCvtF2I: -+ addHRegUse(u, HRmRead, i->ARM64in.VCvtF2I.rS); -+ addHRegUse(u, HRmWrite, i->ARM64in.VCvtF2I.rD); -+ return; -+ case ARM64in_VCvtSD: -+ addHRegUse(u, HRmWrite, i->ARM64in.VCvtSD.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VCvtSD.src); -+ return; -+ case ARM64in_VUnaryD: -+ addHRegUse(u, HRmWrite, i->ARM64in.VUnaryD.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VUnaryD.src); -+ return; -+ case ARM64in_VUnaryS: -+ addHRegUse(u, HRmWrite, i->ARM64in.VUnaryS.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VUnaryS.src); -+ return; -+ case ARM64in_VBinD: -+ addHRegUse(u, HRmWrite, i->ARM64in.VBinD.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinD.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinD.argR); -+ return; -+ case ARM64in_VBinS: -+ addHRegUse(u, HRmWrite, i->ARM64in.VBinS.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinS.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinS.argR); -+ return; -+ case ARM64in_VCmpD: -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpD.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpD.argR); -+ return; -+ case ARM64in_VCmpS: -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpS.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VCmpS.argR); -+ return; -+ case ARM64in_FPCR: -+ if (i->ARM64in.FPCR.toFPCR) -+ addHRegUse(u, HRmRead, i->ARM64in.FPCR.iReg); -+ else -+ addHRegUse(u, HRmWrite, i->ARM64in.FPCR.iReg); -+ return; -+ case ARM64in_VBinV: -+ addHRegUse(u, HRmWrite, i->ARM64in.VBinV.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinV.argL); -+ addHRegUse(u, HRmRead, i->ARM64in.VBinV.argR); -+ return; -+ case ARM64in_VUnaryV: -+ addHRegUse(u, HRmWrite, i->ARM64in.VUnaryV.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VUnaryV.arg); -+ return; -+ case ARM64in_VNarrowV: -+ addHRegUse(u, HRmWrite, i->ARM64in.VNarrowV.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VNarrowV.src); -+ return; -+ case ARM64in_VShiftImmV: -+ addHRegUse(u, HRmWrite, i->ARM64in.VShiftImmV.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VShiftImmV.src); -+ return; -+//ZZ case ARMin_VAluS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VAluS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VAluS.argL); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VAluS.argR); -+//ZZ return; -+//ZZ case ARMin_VUnaryS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VUnaryS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VUnaryS.src); -+//ZZ return; -+//ZZ case ARMin_VCMovD: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VCMovD.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovD.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovD.src); -+//ZZ return; -+//ZZ case ARMin_VCMovS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VCMovS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovS.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCMovS.src); -+//ZZ return; -+//ZZ case ARMin_VXferD: -+//ZZ if (i->ARMin.VXferD.toD) { -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferD.dD); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferD.rHi); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferD.rLo); -+//ZZ } else { -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferD.dD); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferD.rHi); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferD.rLo); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VXferS: -+//ZZ if (i->ARMin.VXferS.toS) { -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferS.fD); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferS.rLo); -+//ZZ } else { -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VXferS.fD); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VXferS.rLo); -+//ZZ } -+//ZZ return; -+//ZZ case ARMin_VCvtID: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.VCvtID.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.VCvtID.src); -+//ZZ return; -+//ZZ case ARMin_NLdStD: -+//ZZ if (i->ARMin.NLdStD.isLoad) -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NLdStD.dD); -+//ZZ else -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NLdStD.dD); -+//ZZ addRegUsage_ARMAModeN(u, i->ARMin.NLdStD.amode); -+//ZZ return; -+//ZZ case ARMin_NUnary: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NUnary.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NUnary.src); -+//ZZ return; -+//ZZ case ARMin_NUnaryS: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NUnaryS.dst->reg); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NUnaryS.src->reg); -+//ZZ return; -+//ZZ case ARMin_NShift: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NShift.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NShift.argL); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NShift.argR); -+//ZZ return; -+//ZZ case ARMin_NShl64: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NShl64.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NShl64.src); -+//ZZ return; -+//ZZ case ARMin_NDual: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NDual.arg1); -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NDual.arg2); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NDual.arg1); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NDual.arg2); -+//ZZ return; -+ case ARM64in_VImmQ: -+ addHRegUse(u, HRmWrite, i->ARM64in.VImmQ.rQ); -+ return; -+ case ARM64in_VDfromX: -+ addHRegUse(u, HRmWrite, i->ARM64in.VDfromX.rD); -+ addHRegUse(u, HRmRead, i->ARM64in.VDfromX.rX); -+ return; -+ case ARM64in_VQfromXX: -+ addHRegUse(u, HRmWrite, i->ARM64in.VQfromXX.rQ); -+ addHRegUse(u, HRmRead, i->ARM64in.VQfromXX.rXhi); -+ addHRegUse(u, HRmRead, i->ARM64in.VQfromXX.rXlo); -+ return; -+ case ARM64in_VXfromQ: -+ addHRegUse(u, HRmWrite, i->ARM64in.VXfromQ.rX); -+ addHRegUse(u, HRmRead, i->ARM64in.VXfromQ.rQ); -+ return; -+ case ARM64in_VMov: -+ addHRegUse(u, HRmWrite, i->ARM64in.VMov.dst); -+ addHRegUse(u, HRmRead, i->ARM64in.VMov.src); -+ return; -+//ZZ case ARMin_NBinary: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NBinary.dst); -+//ZZ /* TODO: sometimes dst is also being read! */ -+//ZZ // XXX fix this -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NBinary.argL); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NBinary.argR); -+//ZZ return; -+//ZZ case ARMin_NCMovQ: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.NCMovQ.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NCMovQ.dst); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.NCMovQ.src); -+//ZZ return; -+//ZZ case ARMin_Add32: -+//ZZ addHRegUse(u, HRmWrite, i->ARMin.Add32.rD); -+//ZZ addHRegUse(u, HRmRead, i->ARMin.Add32.rN); -+//ZZ return; -+ case ARM64in_EvCheck: -+ /* We expect both amodes only to mention x21, so this is in -+ fact pointless, since x21 isn't allocatable, but -+ anyway.. */ -+ addRegUsage_ARM64AMode(u, i->ARM64in.EvCheck.amCounter); -+ addRegUsage_ARM64AMode(u, i->ARM64in.EvCheck.amFailAddr); -+ addHRegUse(u, HRmWrite, hregARM64_X9()); /* also unavail to RA */ -+ return; -+//ZZ case ARMin_ProfInc: -+//ZZ addHRegUse(u, HRmWrite, hregARM_R12()); -+//ZZ addHRegUse(u, HRmWrite, hregARM_R11()); -+//ZZ return; -+ default: -+ ppARM64Instr(i); -+ vpanic("getRegUsage_ARM64Instr"); -+ } -+} -+ -+ -+void mapRegs_ARM64Instr ( HRegRemap* m, ARM64Instr* i, Bool mode64 ) -+{ -+ vassert(mode64 == True); -+ switch (i->tag) { -+ case ARM64in_Arith: -+ i->ARM64in.Arith.dst = lookupHRegRemap(m, i->ARM64in.Arith.dst); -+ i->ARM64in.Arith.argL = lookupHRegRemap(m, i->ARM64in.Arith.argL); -+ mapRegs_ARM64RIA(m, i->ARM64in.Arith.argR); -+ return; -+ case ARM64in_Cmp: -+ i->ARM64in.Cmp.argL = lookupHRegRemap(m, i->ARM64in.Cmp.argL); -+ mapRegs_ARM64RIA(m, i->ARM64in.Cmp.argR); -+ return; -+ case ARM64in_Logic: -+ i->ARM64in.Logic.dst = lookupHRegRemap(m, i->ARM64in.Logic.dst); -+ i->ARM64in.Logic.argL = lookupHRegRemap(m, i->ARM64in.Logic.argL); -+ mapRegs_ARM64RIL(m, i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Test: -+ i->ARM64in.Test.argL = lookupHRegRemap(m, i->ARM64in.Test.argL); -+ mapRegs_ARM64RIL(m, i->ARM64in.Logic.argR); -+ return; -+ case ARM64in_Shift: -+ i->ARM64in.Shift.dst = lookupHRegRemap(m, i->ARM64in.Shift.dst); -+ i->ARM64in.Shift.argL = lookupHRegRemap(m, i->ARM64in.Shift.argL); -+ mapRegs_ARM64RI6(m, i->ARM64in.Shift.argR); -+ return; -+ case ARM64in_Unary: -+ i->ARM64in.Unary.dst = lookupHRegRemap(m, i->ARM64in.Unary.dst); -+ i->ARM64in.Unary.src = lookupHRegRemap(m, i->ARM64in.Unary.src); -+ return; -+ case ARM64in_MovI: -+ i->ARM64in.MovI.dst = lookupHRegRemap(m, i->ARM64in.MovI.dst); -+ i->ARM64in.MovI.src = lookupHRegRemap(m, i->ARM64in.MovI.src); -+ return; -+ case ARM64in_Imm64: -+ i->ARM64in.Imm64.dst = lookupHRegRemap(m, i->ARM64in.Imm64.dst); -+ return; -+ case ARM64in_LdSt64: -+ i->ARM64in.LdSt64.rD = lookupHRegRemap(m, i->ARM64in.LdSt64.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt64.amode); -+ return; -+ case ARM64in_LdSt32: -+ i->ARM64in.LdSt32.rD = lookupHRegRemap(m, i->ARM64in.LdSt32.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt32.amode); -+ return; -+ case ARM64in_LdSt16: -+ i->ARM64in.LdSt16.rD = lookupHRegRemap(m, i->ARM64in.LdSt16.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt16.amode); -+ return; -+ case ARM64in_LdSt8: -+ i->ARM64in.LdSt8.rD = lookupHRegRemap(m, i->ARM64in.LdSt8.rD); -+ mapRegs_ARM64AMode(m, i->ARM64in.LdSt8.amode); -+ return; -+ case ARM64in_XDirect: -+ mapRegs_ARM64AMode(m, i->ARM64in.XDirect.amPC); -+ return; -+ case ARM64in_XIndir: -+ i->ARM64in.XIndir.dstGA -+ = lookupHRegRemap(m, i->ARM64in.XIndir.dstGA); -+ mapRegs_ARM64AMode(m, i->ARM64in.XIndir.amPC); -+ return; -+ case ARM64in_XAssisted: -+ i->ARM64in.XAssisted.dstGA -+ = lookupHRegRemap(m, i->ARM64in.XAssisted.dstGA); -+ mapRegs_ARM64AMode(m, i->ARM64in.XAssisted.amPC); -+ return; -+ case ARM64in_CSel: -+ i->ARM64in.CSel.dst = lookupHRegRemap(m, i->ARM64in.CSel.dst); -+ i->ARM64in.CSel.argL = lookupHRegRemap(m, i->ARM64in.CSel.argL); -+ i->ARM64in.CSel.argR = lookupHRegRemap(m, i->ARM64in.CSel.argR); -+ return; -+ case ARM64in_Call: -+ return; -+ case ARM64in_AddToSP: -+ return; -+ case ARM64in_FromSP: -+ i->ARM64in.FromSP.dst = lookupHRegRemap(m, i->ARM64in.FromSP.dst); -+ return; -+ case ARM64in_Mul: -+ i->ARM64in.Mul.dst = lookupHRegRemap(m, i->ARM64in.Mul.dst); -+ i->ARM64in.Mul.argL = lookupHRegRemap(m, i->ARM64in.Mul.argL); -+ i->ARM64in.Mul.argR = lookupHRegRemap(m, i->ARM64in.Mul.argR); -+ break; -+ case ARM64in_LdrEX: -+ return; -+ case ARM64in_StrEX: -+ return; -+ case ARM64in_MFence: -+ return; -+//ZZ case ARMin_CLREX: -+//ZZ return; -+ case ARM64in_VLdStS: -+ i->ARM64in.VLdStS.sD = lookupHRegRemap(m, i->ARM64in.VLdStS.sD); -+ i->ARM64in.VLdStS.rN = lookupHRegRemap(m, i->ARM64in.VLdStS.rN); -+ return; -+ case ARM64in_VLdStD: -+ i->ARM64in.VLdStD.dD = lookupHRegRemap(m, i->ARM64in.VLdStD.dD); -+ i->ARM64in.VLdStD.rN = lookupHRegRemap(m, i->ARM64in.VLdStD.rN); -+ return; -+ case ARM64in_VLdStQ: -+ i->ARM64in.VLdStQ.rQ = lookupHRegRemap(m, i->ARM64in.VLdStQ.rQ); -+ i->ARM64in.VLdStQ.rN = lookupHRegRemap(m, i->ARM64in.VLdStQ.rN); -+ return; -+ case ARM64in_VCvtI2F: -+ i->ARM64in.VCvtI2F.rS = lookupHRegRemap(m, i->ARM64in.VCvtI2F.rS); -+ i->ARM64in.VCvtI2F.rD = lookupHRegRemap(m, i->ARM64in.VCvtI2F.rD); -+ return; -+ case ARM64in_VCvtF2I: -+ i->ARM64in.VCvtF2I.rS = lookupHRegRemap(m, i->ARM64in.VCvtF2I.rS); -+ i->ARM64in.VCvtF2I.rD = lookupHRegRemap(m, i->ARM64in.VCvtF2I.rD); -+ return; -+ case ARM64in_VCvtSD: -+ i->ARM64in.VCvtSD.dst = lookupHRegRemap(m, i->ARM64in.VCvtSD.dst); -+ i->ARM64in.VCvtSD.src = lookupHRegRemap(m, i->ARM64in.VCvtSD.src); -+ return; -+ case ARM64in_VUnaryD: -+ i->ARM64in.VUnaryD.dst = lookupHRegRemap(m, i->ARM64in.VUnaryD.dst); -+ i->ARM64in.VUnaryD.src = lookupHRegRemap(m, i->ARM64in.VUnaryD.src); -+ return; -+ case ARM64in_VUnaryS: -+ i->ARM64in.VUnaryS.dst = lookupHRegRemap(m, i->ARM64in.VUnaryS.dst); -+ i->ARM64in.VUnaryS.src = lookupHRegRemap(m, i->ARM64in.VUnaryS.src); -+ return; -+ case ARM64in_VBinD: -+ i->ARM64in.VBinD.dst = lookupHRegRemap(m, i->ARM64in.VBinD.dst); -+ i->ARM64in.VBinD.argL = lookupHRegRemap(m, i->ARM64in.VBinD.argL); -+ i->ARM64in.VBinD.argR = lookupHRegRemap(m, i->ARM64in.VBinD.argR); -+ return; -+ case ARM64in_VBinS: -+ i->ARM64in.VBinS.dst = lookupHRegRemap(m, i->ARM64in.VBinS.dst); -+ i->ARM64in.VBinS.argL = lookupHRegRemap(m, i->ARM64in.VBinS.argL); -+ i->ARM64in.VBinS.argR = lookupHRegRemap(m, i->ARM64in.VBinS.argR); -+ return; -+ case ARM64in_VCmpD: -+ i->ARM64in.VCmpD.argL = lookupHRegRemap(m, i->ARM64in.VCmpD.argL); -+ i->ARM64in.VCmpD.argR = lookupHRegRemap(m, i->ARM64in.VCmpD.argR); -+ return; -+ case ARM64in_VCmpS: -+ i->ARM64in.VCmpS.argL = lookupHRegRemap(m, i->ARM64in.VCmpS.argL); -+ i->ARM64in.VCmpS.argR = lookupHRegRemap(m, i->ARM64in.VCmpS.argR); -+ return; -+ case ARM64in_FPCR: -+ i->ARM64in.FPCR.iReg = lookupHRegRemap(m, i->ARM64in.FPCR.iReg); -+ return; -+ case ARM64in_VBinV: -+ i->ARM64in.VBinV.dst = lookupHRegRemap(m, i->ARM64in.VBinV.dst); -+ i->ARM64in.VBinV.argL = lookupHRegRemap(m, i->ARM64in.VBinV.argL); -+ i->ARM64in.VBinV.argR = lookupHRegRemap(m, i->ARM64in.VBinV.argR); -+ return; -+ case ARM64in_VUnaryV: -+ i->ARM64in.VUnaryV.dst = lookupHRegRemap(m, i->ARM64in.VUnaryV.dst); -+ i->ARM64in.VUnaryV.arg = lookupHRegRemap(m, i->ARM64in.VUnaryV.arg); -+ return; -+ case ARM64in_VNarrowV: -+ i->ARM64in.VNarrowV.dst = lookupHRegRemap(m, i->ARM64in.VNarrowV.dst); -+ i->ARM64in.VNarrowV.src = lookupHRegRemap(m, i->ARM64in.VNarrowV.src); -+ return; -+ case ARM64in_VShiftImmV: -+ i->ARM64in.VShiftImmV.dst -+ = lookupHRegRemap(m, i->ARM64in.VShiftImmV.dst); -+ i->ARM64in.VShiftImmV.src -+ = lookupHRegRemap(m, i->ARM64in.VShiftImmV.src); -+ return; -+//ZZ case ARMin_VAluS: -+//ZZ i->ARMin.VAluS.dst = lookupHRegRemap(m, i->ARMin.VAluS.dst); -+//ZZ i->ARMin.VAluS.argL = lookupHRegRemap(m, i->ARMin.VAluS.argL); -+//ZZ i->ARMin.VAluS.argR = lookupHRegRemap(m, i->ARMin.VAluS.argR); -+//ZZ return; -+//ZZ case ARMin_VCMovD: -+//ZZ i->ARMin.VCMovD.dst = lookupHRegRemap(m, i->ARMin.VCMovD.dst); -+//ZZ i->ARMin.VCMovD.src = lookupHRegRemap(m, i->ARMin.VCMovD.src); -+//ZZ return; -+//ZZ case ARMin_VCMovS: -+//ZZ i->ARMin.VCMovS.dst = lookupHRegRemap(m, i->ARMin.VCMovS.dst); -+//ZZ i->ARMin.VCMovS.src = lookupHRegRemap(m, i->ARMin.VCMovS.src); -+//ZZ return; -+//ZZ case ARMin_VXferD: -+//ZZ i->ARMin.VXferD.dD = lookupHRegRemap(m, i->ARMin.VXferD.dD); -+//ZZ i->ARMin.VXferD.rHi = lookupHRegRemap(m, i->ARMin.VXferD.rHi); -+//ZZ i->ARMin.VXferD.rLo = lookupHRegRemap(m, i->ARMin.VXferD.rLo); -+//ZZ return; -+//ZZ case ARMin_VXferS: -+//ZZ i->ARMin.VXferS.fD = lookupHRegRemap(m, i->ARMin.VXferS.fD); -+//ZZ i->ARMin.VXferS.rLo = lookupHRegRemap(m, i->ARMin.VXferS.rLo); -+//ZZ return; -+//ZZ case ARMin_VCvtID: -+//ZZ i->ARMin.VCvtID.dst = lookupHRegRemap(m, i->ARMin.VCvtID.dst); -+//ZZ i->ARMin.VCvtID.src = lookupHRegRemap(m, i->ARMin.VCvtID.src); -+//ZZ return; -+//ZZ case ARMin_NLdStD: -+//ZZ i->ARMin.NLdStD.dD = lookupHRegRemap(m, i->ARMin.NLdStD.dD); -+//ZZ mapRegs_ARMAModeN(m, i->ARMin.NLdStD.amode); -+//ZZ return; -+//ZZ case ARMin_NUnary: -+//ZZ i->ARMin.NUnary.src = lookupHRegRemap(m, i->ARMin.NUnary.src); -+//ZZ i->ARMin.NUnary.dst = lookupHRegRemap(m, i->ARMin.NUnary.dst); -+//ZZ return; -+//ZZ case ARMin_NUnaryS: -+//ZZ i->ARMin.NUnaryS.src->reg -+//ZZ = lookupHRegRemap(m, i->ARMin.NUnaryS.src->reg); -+//ZZ i->ARMin.NUnaryS.dst->reg -+//ZZ = lookupHRegRemap(m, i->ARMin.NUnaryS.dst->reg); -+//ZZ return; -+//ZZ case ARMin_NShift: -+//ZZ i->ARMin.NShift.dst = lookupHRegRemap(m, i->ARMin.NShift.dst); -+//ZZ i->ARMin.NShift.argL = lookupHRegRemap(m, i->ARMin.NShift.argL); -+//ZZ i->ARMin.NShift.argR = lookupHRegRemap(m, i->ARMin.NShift.argR); -+//ZZ return; -+//ZZ case ARMin_NShl64: -+//ZZ i->ARMin.NShl64.dst = lookupHRegRemap(m, i->ARMin.NShl64.dst); -+//ZZ i->ARMin.NShl64.src = lookupHRegRemap(m, i->ARMin.NShl64.src); -+//ZZ return; -+//ZZ case ARMin_NDual: -+//ZZ i->ARMin.NDual.arg1 = lookupHRegRemap(m, i->ARMin.NDual.arg1); -+//ZZ i->ARMin.NDual.arg2 = lookupHRegRemap(m, i->ARMin.NDual.arg2); -+//ZZ return; -+ case ARM64in_VImmQ: -+ i->ARM64in.VImmQ.rQ = lookupHRegRemap(m, i->ARM64in.VImmQ.rQ); -+ return; -+ case ARM64in_VDfromX: -+ i->ARM64in.VDfromX.rD -+ = lookupHRegRemap(m, i->ARM64in.VDfromX.rD); -+ i->ARM64in.VDfromX.rX -+ = lookupHRegRemap(m, i->ARM64in.VDfromX.rX); -+ return; -+ case ARM64in_VQfromXX: -+ i->ARM64in.VQfromXX.rQ -+ = lookupHRegRemap(m, i->ARM64in.VQfromXX.rQ); -+ i->ARM64in.VQfromXX.rXhi -+ = lookupHRegRemap(m, i->ARM64in.VQfromXX.rXhi); -+ i->ARM64in.VQfromXX.rXlo -+ = lookupHRegRemap(m, i->ARM64in.VQfromXX.rXlo); -+ return; -+ case ARM64in_VXfromQ: -+ i->ARM64in.VXfromQ.rX -+ = lookupHRegRemap(m, i->ARM64in.VXfromQ.rX); -+ i->ARM64in.VXfromQ.rQ -+ = lookupHRegRemap(m, i->ARM64in.VXfromQ.rQ); -+ return; -+ case ARM64in_VMov: -+ i->ARM64in.VMov.dst = lookupHRegRemap(m, i->ARM64in.VMov.dst); -+ i->ARM64in.VMov.src = lookupHRegRemap(m, i->ARM64in.VMov.src); -+ return; -+ -+//ZZ case ARMin_NBinary: -+//ZZ i->ARMin.NBinary.argL = lookupHRegRemap(m, i->ARMin.NBinary.argL); -+//ZZ i->ARMin.NBinary.argR = lookupHRegRemap(m, i->ARMin.NBinary.argR); -+//ZZ i->ARMin.NBinary.dst = lookupHRegRemap(m, i->ARMin.NBinary.dst); -+//ZZ return; -+//ZZ case ARMin_NCMovQ: -+//ZZ i->ARMin.NCMovQ.dst = lookupHRegRemap(m, i->ARMin.NCMovQ.dst); -+//ZZ i->ARMin.NCMovQ.src = lookupHRegRemap(m, i->ARMin.NCMovQ.src); -+//ZZ return; -+//ZZ case ARMin_Add32: -+//ZZ i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD); -+//ZZ i->ARMin.Add32.rN = lookupHRegRemap(m, i->ARMin.Add32.rN); -+//ZZ return; -+ case ARM64in_EvCheck: -+ /* We expect both amodes only to mention x21, so this is in -+ fact pointless, since x21 isn't allocatable, but -+ anyway.. */ -+ mapRegs_ARM64AMode(m, i->ARM64in.EvCheck.amCounter); -+ mapRegs_ARM64AMode(m, i->ARM64in.EvCheck.amFailAddr); -+ return; -+//ZZ case ARMin_ProfInc: -+//ZZ /* hardwires r11 and r12 -- nothing to modify. */ -+//ZZ return; -+ default: -+ ppARM64Instr(i); -+ vpanic("mapRegs_ARM64Instr"); -+ } -+} -+ -+/* Figure out if i represents a reg-reg move, and if so assign the -+ source and destination to *src and *dst. If in doubt say No. Used -+ by the register allocator to do move coalescing. -+*/ -+Bool isMove_ARM64Instr ( ARM64Instr* i, HReg* src, HReg* dst ) -+{ -+ switch (i->tag) { -+ case ARM64in_MovI: -+ *src = i->ARM64in.MovI.src; -+ *dst = i->ARM64in.MovI.dst; -+ return True; -+ case ARM64in_VMov: -+ *src = i->ARM64in.VMov.src; -+ *dst = i->ARM64in.VMov.dst; -+ return True; -+ default: -+ break; -+ } -+ -+ return False; -+} -+ -+ -+/* Generate arm spill/reload instructions under the direction of the -+ register allocator. Note it's critical these don't write the -+ condition codes. */ -+ -+void genSpill_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offsetB, Bool mode64 ) -+{ -+ HRegClass rclass; -+ vassert(offsetB >= 0); -+ vassert(!hregIsVirtual(rreg)); -+ vassert(mode64 == True); -+ *i1 = *i2 = NULL; -+ rclass = hregClass(rreg); -+ switch (rclass) { -+ case HRcInt64: -+ vassert(0 == (offsetB & 7)); -+ offsetB >>= 3; -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_LdSt64( -+ False/*!isLoad*/, -+ rreg, -+ ARM64AMode_RI12(hregARM64_X21(), offsetB, 8) -+ ); -+ return; -+ case HRcFlt64: -+ vassert(0 == (offsetB & 7)); -+ vassert(offsetB >= 0 && offsetB < 32768); -+ *i1 = ARM64Instr_VLdStD(False/*!isLoad*/, -+ rreg, hregARM64_X21(), offsetB); -+ return; -+ case HRcVec128: { -+ HReg x21 = hregARM64_X21(); // baseblock -+ HReg x9 = hregARM64_X9(); // spill temporary -+ vassert(0 == (offsetB & 15)); // check sane alignment -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_Arith(x9, x21, ARM64RIA_I12(offsetB, 0), True); -+ *i2 = ARM64Instr_VLdStQ(False/*!isLoad*/, rreg, x9); -+ return; -+ } -+ default: -+ ppHRegClass(rclass); -+ vpanic("genSpill_ARM: unimplemented regclass"); -+ } -+} -+ -+void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offsetB, Bool mode64 ) -+{ -+ HRegClass rclass; -+ vassert(offsetB >= 0); -+ vassert(!hregIsVirtual(rreg)); -+ vassert(mode64 == True); -+ *i1 = *i2 = NULL; -+ rclass = hregClass(rreg); -+ switch (rclass) { -+ case HRcInt64: -+ vassert(0 == (offsetB & 7)); -+ offsetB >>= 3; -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_LdSt64( -+ True/*isLoad*/, -+ rreg, -+ ARM64AMode_RI12(hregARM64_X21(), offsetB, 8) -+ ); -+ return; -+ case HRcFlt64: -+ vassert(0 == (offsetB & 7)); -+ vassert(offsetB >= 0 && offsetB < 32768); -+ *i1 = ARM64Instr_VLdStD(True/*isLoad*/, -+ rreg, hregARM64_X21(), offsetB); -+ return; -+ case HRcVec128: { -+ HReg x21 = hregARM64_X21(); // baseblock -+ HReg x9 = hregARM64_X9(); // spill temporary -+ vassert(0 == (offsetB & 15)); // check sane alignment -+ vassert(offsetB < 4096); -+ *i1 = ARM64Instr_Arith(x9, x21, ARM64RIA_I12(offsetB, 0), True); -+ *i2 = ARM64Instr_VLdStQ(True/*isLoad*/, rreg, x9); -+ return; -+ } -+ default: -+ ppHRegClass(rclass); -+ vpanic("genReload_ARM: unimplemented regclass"); -+ } -+} -+ -+ -+//ZZ /* Emit an instruction into buf and return the number of bytes used. -+//ZZ Note that buf is not the insn's final place, and therefore it is -+//ZZ imperative to emit position-independent code. */ -+ -+static inline UChar iregNo ( HReg r ) -+{ -+ UInt n; -+ vassert(hregClass(r) == HRcInt64); -+ vassert(!hregIsVirtual(r)); -+ n = hregNumber(r); -+ vassert(n <= 30); -+ return toUChar(n); -+} -+ -+static inline UChar dregNo ( HReg r ) -+{ -+ UInt n; -+ vassert(hregClass(r) == HRcFlt64); -+ vassert(!hregIsVirtual(r)); -+ n = hregNumber(r); -+ vassert(n <= 31); -+ return toUChar(n); -+} -+ -+static inline UChar qregNo ( HReg r ) -+{ -+ UInt n; -+ vassert(hregClass(r) == HRcVec128); -+ vassert(!hregIsVirtual(r)); -+ n = hregNumber(r); -+ vassert(n <= 31); -+ return toUChar(n); -+} -+ -+#define BITS4(zzb3,zzb2,zzb1,zzb0) \ -+ (((zzb3) << 3) | ((zzb2) << 2) | ((zzb1) << 1) | (zzb0)) -+ -+#define X00 BITS4(0,0, 0,0) -+#define X01 BITS4(0,0, 0,1) -+#define X10 BITS4(0,0, 1,0) -+#define X11 BITS4(0,0, 1,1) -+ -+#define X000 BITS4(0, 0,0,0) -+#define X001 BITS4(0, 0,0,1) -+#define X010 BITS4(0, 0,1,0) -+#define X011 BITS4(0, 0,1,1) -+#define X100 BITS4(0, 1,0,0) -+#define X101 BITS4(0, 1,0,1) -+#define X110 BITS4(0, 1,1,0) -+#define X111 BITS4(0, 1,1,1) -+ -+#define X0000 BITS4(0,0,0,0) -+#define X0001 BITS4(0,0,0,1) -+#define X0010 BITS4(0,0,1,0) -+#define X0011 BITS4(0,0,1,1) -+ -+#define BITS8(zzb7,zzb6,zzb5,zzb4,zzb3,zzb2,zzb1,zzb0) \ -+ ((BITS4(zzb7,zzb6,zzb5,zzb4) << 4) | BITS4(zzb3,zzb2,zzb1,zzb0)) -+ -+#define X00000 BITS8(0,0,0, 0,0,0,0,0) -+#define X00001 BITS8(0,0,0, 0,0,0,0,1) -+#define X00111 BITS8(0,0,0, 0,0,1,1,1) -+#define X01000 BITS8(0,0,0, 0,1,0,0,0) -+#define X10000 BITS8(0,0,0, 1,0,0,0,0) -+#define X11000 BITS8(0,0,0, 1,1,0,0,0) -+#define X11110 BITS8(0,0,0, 1,1,1,1,0) -+#define X11111 BITS8(0,0,0, 1,1,1,1,1) -+ -+#define X000000 BITS8(0,0, 0,0,0,0,0,0) -+#define X000001 BITS8(0,0, 0,0,0,0,0,1) -+#define X000100 BITS8(0,0, 0,0,0,1,0,0) -+#define X000111 BITS8(0,0, 0,0,0,1,1,1) -+#define X001000 BITS8(0,0, 0,0,1,0,0,0) -+#define X001001 BITS8(0,0, 0,0,1,0,0,1) -+#define X001010 BITS8(0,0, 0,0,1,0,1,0) -+#define X001101 BITS8(0,0, 0,0,1,1,0,1) -+#define X001111 BITS8(0,0, 0,0,1,1,1,1) -+#define X010000 BITS8(0,0, 0,1,0,0,0,0) -+#define X010001 BITS8(0,0, 0,1,0,0,0,1) -+#define X010101 BITS8(0,0, 0,1,0,1,0,1) -+#define X010110 BITS8(0,0, 0,1,0,1,1,0) -+#define X011001 BITS8(0,0, 0,1,1,0,0,1) -+#define X011010 BITS8(0,0, 0,1,1,0,1,0) -+#define X011011 BITS8(0,0, 0,1,1,0,1,1) -+#define X011110 BITS8(0,0, 0,1,1,1,1,0) -+#define X011111 BITS8(0,0, 0,1,1,1,1,1) -+#define X100001 BITS8(0,0, 1,0,0,0,0,1) -+#define X100011 BITS8(0,0, 1,0,0,0,1,1) -+#define X100100 BITS8(0,0, 1,0,0,1,0,0) -+#define X100101 BITS8(0,0, 1,0,0,1,0,1) -+#define X100110 BITS8(0,0, 1,0,0,1,1,0) -+#define X100111 BITS8(0,0, 1,0,0,1,1,1) -+#define X110000 BITS8(0,0, 1,1,0,0,0,0) -+#define X110001 BITS8(0,0, 1,1,0,0,0,1) -+#define X110101 BITS8(0,0, 1,1,0,1,0,1) -+#define X110111 BITS8(0,0, 1,1,0,1,1,1) -+#define X111000 BITS8(0,0, 1,1,1,0,0,0) -+#define X111001 BITS8(0,0, 1,1,1,0,0,1) -+#define X111101 BITS8(0,0, 1,1,1,1,0,1) -+#define X111110 BITS8(0,0, 1,1,1,1,1,0) -+#define X111111 BITS8(0,0, 1,1,1,1,1,1) -+ -+#define X0001000 BITS8(0, 0,0,0,1,0,0,0) -+#define X0010000 BITS8(0, 0,0,1,0,0,0,0) -+#define X0100000 BITS8(0, 0,1,0,0,0,0,0) -+#define X1000000 BITS8(0, 1,0,0,0,0,0,0) -+ -+#define X00100000 BITS8(0,0,1,0,0,0,0,0) -+#define X00100001 BITS8(0,0,1,0,0,0,0,1) -+#define X00100010 BITS8(0,0,1,0,0,0,1,0) -+#define X00100011 BITS8(0,0,1,0,0,0,1,1) -+#define X01010000 BITS8(0,1,0,1,0,0,0,0) -+#define X01010001 BITS8(0,1,0,1,0,0,0,1) -+#define X01010100 BITS8(0,1,0,1,0,1,0,0) -+#define X01011000 BITS8(0,1,0,1,1,0,0,0) -+#define X01100000 BITS8(0,1,1,0,0,0,0,0) -+#define X01100001 BITS8(0,1,1,0,0,0,0,1) -+#define X01100010 BITS8(0,1,1,0,0,0,1,0) -+#define X01100011 BITS8(0,1,1,0,0,0,1,1) -+#define X01110000 BITS8(0,1,1,1,0,0,0,0) -+#define X01110001 BITS8(0,1,1,1,0,0,0,1) -+#define X01110011 BITS8(0,1,1,1,0,0,1,1) -+#define X01110101 BITS8(0,1,1,1,0,1,0,1) -+#define X01110111 BITS8(0,1,1,1,0,1,1,1) -+#define X11000001 BITS8(1,1,0,0,0,0,0,1) -+#define X11000011 BITS8(1,1,0,0,0,0,1,1) -+#define X11010100 BITS8(1,1,0,1,0,1,0,0) -+#define X11010110 BITS8(1,1,0,1,0,1,1,0) -+#define X11011000 BITS8(1,1,0,1,1,0,0,0) -+#define X11011010 BITS8(1,1,0,1,1,0,1,0) -+#define X11011110 BITS8(1,1,0,1,1,1,1,0) -+#define X11110001 BITS8(1,1,1,1,0,0,0,1) -+#define X11110011 BITS8(1,1,1,1,0,0,1,1) -+ -+ -+/* --- 4 fields --- */ -+ -+static inline UInt X_8_19_1_4 ( UInt f1, UInt f2, UInt f3, UInt f4 ) { -+ vassert(8+19+1+4 == 32); -+ vassert(f1 < (1<<8)); -+ vassert(f2 < (1<<19)); -+ vassert(f3 < (1<<1)); -+ vassert(f4 < (1<<4)); -+ UInt w = 0; -+ w = (w << 8) | f1; -+ w = (w << 19) | f2; -+ w = (w << 1) | f3; -+ w = (w << 4) | f4; -+ return w; -+} -+ -+/* --- 5 fields --- */ -+ -+static inline UInt X_3_6_2_16_5 ( UInt f1, UInt f2, -+ UInt f3, UInt f4, UInt f5 ) { -+ vassert(3+6+2+16+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<2)); -+ vassert(f4 < (1<<16)); -+ vassert(f5 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 6) | f2; -+ w = (w << 2) | f3; -+ w = (w << 16) | f4; -+ w = (w << 5) | f5; -+ return w; -+} -+ -+/* --- 6 fields --- */ -+ -+static inline UInt X_2_6_2_12_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6 ) { -+ vassert(2+6+2+12+5+5 == 32); -+ vassert(f1 < (1<<2)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<2)); -+ vassert(f4 < (1<<12)); -+ vassert(f5 < (1<<5)); -+ vassert(f6 < (1<<5)); -+ UInt w = 0; -+ w = (w << 2) | f1; -+ w = (w << 6) | f2; -+ w = (w << 2) | f3; -+ w = (w << 12) | f4; -+ w = (w << 5) | f5; -+ w = (w << 5) | f6; -+ return w; -+} -+ -+static inline UInt X_3_8_5_6_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6 ) { -+ vassert(3+8+5+6+5+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<8)); -+ vassert(f3 < (1<<5)); -+ vassert(f4 < (1<<6)); -+ vassert(f5 < (1<<5)); -+ vassert(f6 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 8) | f2; -+ w = (w << 5) | f3; -+ w = (w << 6) | f4; -+ w = (w << 5) | f5; -+ w = (w << 5) | f6; -+ return w; -+} -+ -+static inline UInt X_3_5_8_6_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6 ) { -+ vassert(3+8+5+6+5+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<5)); -+ vassert(f3 < (1<<8)); -+ vassert(f4 < (1<<6)); -+ vassert(f5 < (1<<5)); -+ vassert(f6 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 5) | f2; -+ w = (w << 8) | f3; -+ w = (w << 6) | f4; -+ w = (w << 5) | f5; -+ w = (w << 5) | f6; -+ return w; -+} -+ -+static inline UInt X_3_6_7_6_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6 ) { -+ vassert(3+6+7+6+5+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<7)); -+ vassert(f4 < (1<<6)); -+ vassert(f5 < (1<<5)); -+ vassert(f6 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 6) | f2; -+ w = (w << 7) | f3; -+ w = (w << 6) | f4; -+ w = (w << 5) | f5; -+ w = (w << 5) | f6; -+ return w; -+} -+ -+/* --- 7 fields --- */ -+ -+static inline UInt X_2_6_3_9_2_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6, UInt f7 ) { -+ vassert(2+6+3+9+2+5+5 == 32); -+ vassert(f1 < (1<<2)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<3)); -+ vassert(f4 < (1<<9)); -+ vassert(f5 < (1<<2)); -+ vassert(f6 < (1<<5)); -+ vassert(f7 < (1<<5)); -+ UInt w = 0; -+ w = (w << 2) | f1; -+ w = (w << 6) | f2; -+ w = (w << 3) | f3; -+ w = (w << 9) | f4; -+ w = (w << 2) | f5; -+ w = (w << 5) | f6; -+ w = (w << 5) | f7; -+ return w; -+} -+ -+static inline UInt X_3_6_1_6_6_5_5 ( UInt f1, UInt f2, UInt f3, -+ UInt f4, UInt f5, UInt f6, UInt f7 ) { -+ vassert(3+6+1+6+6+5+5 == 32); -+ vassert(f1 < (1<<3)); -+ vassert(f2 < (1<<6)); -+ vassert(f3 < (1<<1)); -+ vassert(f4 < (1<<6)); -+ vassert(f5 < (1<<6)); -+ vassert(f6 < (1<<5)); -+ vassert(f7 < (1<<5)); -+ UInt w = 0; -+ w = (w << 3) | f1; -+ w = (w << 6) | f2; -+ w = (w << 1) | f3; -+ w = (w << 6) | f4; -+ w = (w << 6) | f5; -+ w = (w << 5) | f6; -+ w = (w << 5) | f7; -+ return w; -+} -+ -+ -+//ZZ #define X0000 BITS4(0,0,0,0) -+//ZZ #define X0001 BITS4(0,0,0,1) -+//ZZ #define X0010 BITS4(0,0,1,0) -+//ZZ #define X0011 BITS4(0,0,1,1) -+//ZZ #define X0100 BITS4(0,1,0,0) -+//ZZ #define X0101 BITS4(0,1,0,1) -+//ZZ #define X0110 BITS4(0,1,1,0) -+//ZZ #define X0111 BITS4(0,1,1,1) -+//ZZ #define X1000 BITS4(1,0,0,0) -+//ZZ #define X1001 BITS4(1,0,0,1) -+//ZZ #define X1010 BITS4(1,0,1,0) -+//ZZ #define X1011 BITS4(1,0,1,1) -+//ZZ #define X1100 BITS4(1,1,0,0) -+//ZZ #define X1101 BITS4(1,1,0,1) -+//ZZ #define X1110 BITS4(1,1,1,0) -+//ZZ #define X1111 BITS4(1,1,1,1) -+/* -+#define XXXXX___(zzx7,zzx6,zzx5,zzx4,zzx3) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12)) -+ -+#define XXXXXX__(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8)) -+ -+#define XXXXX__X(zzx7,zzx6,zzx5,zzx4,zzx3,zzx0) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12) | (((zzx0) & 0xF) << 0)) -+ -+#define XXX___XX(zzx7,zzx6,zzx5,zzx1,zzx0) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx1) & 0xF) << 4) | \ -+ (((zzx0) & 0xF) << 0)) -+ -+#define XXXXXXXX(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2,zzx1,zzx0) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \ -+ (((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \ -+ (((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8) | \ -+ (((zzx1) & 0xF) << 4) | (((zzx0) & 0xF) << 0)) -+ -+#define XX______(zzx7,zzx6) \ -+ ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24)) -+*/ -+//ZZ /* Generate a skeletal insn that involves an a RI84 shifter operand. -+//ZZ Returns a word which is all zeroes apart from bits 25 and 11..0, -+//ZZ since it is those that encode the shifter operand (at least to the -+//ZZ extent that we care about it.) */ -+//ZZ static UInt skeletal_RI84 ( ARMRI84* ri ) -+//ZZ { -+//ZZ UInt instr; -+//ZZ if (ri->tag == ARMri84_I84) { -+//ZZ vassert(0 == (ri->ARMri84.I84.imm4 & ~0x0F)); -+//ZZ vassert(0 == (ri->ARMri84.I84.imm8 & ~0xFF)); -+//ZZ instr = 1 << 25; -+//ZZ instr |= (ri->ARMri84.I84.imm4 << 8); -+//ZZ instr |= ri->ARMri84.I84.imm8; -+//ZZ } else { -+//ZZ instr = 0 << 25; -+//ZZ instr |= iregNo(ri->ARMri84.R.reg); -+//ZZ } -+//ZZ return instr; -+//ZZ } -+//ZZ -+//ZZ /* Ditto for RI5. Resulting word is zeroes apart from bit 4 and bits -+//ZZ 11..7. */ -+//ZZ static UInt skeletal_RI5 ( ARMRI5* ri ) -+//ZZ { -+//ZZ UInt instr; -+//ZZ if (ri->tag == ARMri5_I5) { -+//ZZ UInt imm5 = ri->ARMri5.I5.imm5; -+//ZZ vassert(imm5 >= 1 && imm5 <= 31); -+//ZZ instr = 0 << 4; -+//ZZ instr |= imm5 << 7; -+//ZZ } else { -+//ZZ instr = 1 << 4; -+//ZZ instr |= iregNo(ri->ARMri5.R.reg) << 8; -+//ZZ } -+//ZZ return instr; -+//ZZ } -+ -+ -+/* Get an immediate into a register, using only that register. */ -+static UInt* imm64_to_iregNo ( UInt* p, Int xD, ULong imm64 ) -+{ -+ if (imm64 == 0) { -+ // This has to be special-cased, since the logic below -+ // will leave the register unchanged in this case. -+ // MOVZ xD, #0, LSL #0 -+ *p++ = X_3_6_2_16_5(X110, X100101, X00, 0/*imm16*/, xD); -+ return p; -+ } -+ -+ // There must be at least one non-zero halfword. Find the -+ // lowest nonzero such, and use MOVZ to install it and zero -+ // out the rest of the register. -+ UShort h[4]; -+ h[3] = (UShort)((imm64 >> 48) & 0xFFFF); -+ h[2] = (UShort)((imm64 >> 32) & 0xFFFF); -+ h[1] = (UShort)((imm64 >> 16) & 0xFFFF); -+ h[0] = (UShort)((imm64 >> 0) & 0xFFFF); -+ -+ UInt i; -+ for (i = 0; i < 4; i++) { -+ if (h[i] != 0) -+ break; -+ } -+ vassert(i < 4); -+ -+ // MOVZ xD, h[i], LSL (16*i) -+ *p++ = X_3_6_2_16_5(X110, X100101, i, h[i], xD); -+ -+ // Work on upwards through h[i], using MOVK to stuff in any -+ // remaining nonzero elements. -+ i++; -+ for (; i < 4; i++) { -+ if (h[i] == 0) -+ continue; -+ // MOVK xD, h[i], LSL (16*i) -+ *p++ = X_3_6_2_16_5(X111, X100101, i, h[i], xD); -+ } -+ -+ return p; -+} -+ -+/* Get an immediate into a register, using only that register, and -+ generating exactly 4 instructions, regardless of the value of the -+ immediate. This is used when generating sections of code that need -+ to be patched later, so as to guarantee a specific size. */ -+static UInt* imm64_to_iregNo_EXACTLY4 ( UInt* p, Int xD, ULong imm64 ) -+{ -+ UShort h[4]; -+ h[3] = (UShort)((imm64 >> 48) & 0xFFFF); -+ h[2] = (UShort)((imm64 >> 32) & 0xFFFF); -+ h[1] = (UShort)((imm64 >> 16) & 0xFFFF); -+ h[0] = (UShort)((imm64 >> 0) & 0xFFFF); -+ // Work on upwards through h[i], using MOVK to stuff in the -+ // remaining elements. -+ UInt i; -+ for (i = 0; i < 4; i++) { -+ if (i == 0) { -+ // MOVZ xD, h[0], LSL (16*0) -+ *p++ = X_3_6_2_16_5(X110, X100101, i, h[i], xD); -+ } else { -+ // MOVK xD, h[i], LSL (16*i) -+ *p++ = X_3_6_2_16_5(X111, X100101, i, h[i], xD); -+ } -+ } -+ return p; -+} -+ -+/* Check whether p points at a 4-insn sequence cooked up by -+ imm64_to_iregNo_EXACTLY4(). */ -+static Bool is_imm64_to_iregNo_EXACTLY4 ( UInt* p, Int xD, ULong imm64 ) -+{ -+ UShort h[4]; -+ h[3] = (UShort)((imm64 >> 48) & 0xFFFF); -+ h[2] = (UShort)((imm64 >> 32) & 0xFFFF); -+ h[1] = (UShort)((imm64 >> 16) & 0xFFFF); -+ h[0] = (UShort)((imm64 >> 0) & 0xFFFF); -+ // Work on upwards through h[i], using MOVK to stuff in the -+ // remaining elements. -+ UInt i; -+ for (i = 0; i < 4; i++) { -+ UInt expected; -+ if (i == 0) { -+ // MOVZ xD, h[0], LSL (16*0) -+ expected = X_3_6_2_16_5(X110, X100101, i, h[i], xD); -+ } else { -+ // MOVK xD, h[i], LSL (16*i) -+ expected = X_3_6_2_16_5(X111, X100101, i, h[i], xD); -+ } -+ if (p[i] != expected) -+ return False; -+ } -+ return True; -+} -+ -+ -+/* Generate a 8 bit store or 8-to-64 unsigned widening load from/to -+ rD, using the given amode for the address. */ -+static UInt* do_load_or_store8 ( UInt* p, -+ Bool isLoad, UInt wD, ARM64AMode* am ) -+{ -+ vassert(wD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STURB Wd, [Xn|SP + simm9]: 00 111000 000 simm9 00 n d -+ LDURB Wd, [Xn|SP + simm9]: 00 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt instr = X_2_6_3_9_2_5_5(X00, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, -+ iregNo(am->ARM64am.RI9.reg), wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STRB Wd, [Xn|SP + uimm12 * 1]: 00 111 001 00 imm12 n d -+ LDRB Wd, [Xn|SP + uimm12 * 1]: 00 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 1); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X00, X111001, isLoad ? X01 : X00, -+ uimm12, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STRB Xd, [Xn|SP, Xm]: 00 111 000 001 m 011 0 10 n d -+ LDRB Xd, [Xn|SP, Xm]: 00 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X001, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store8"); -+ vassert(0); -+} -+ -+ -+/* Generate a 16 bit store or 16-to-64 unsigned widening load from/to -+ rD, using the given amode for the address. */ -+static UInt* do_load_or_store16 ( UInt* p, -+ Bool isLoad, UInt wD, ARM64AMode* am ) -+{ -+ vassert(wD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STURH Wd, [Xn|SP + simm9]: 01 111000 000 simm9 00 n d -+ LDURH Wd, [Xn|SP + simm9]: 01 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt instr = X_2_6_3_9_2_5_5(X01, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, -+ iregNo(am->ARM64am.RI9.reg), wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STRH Wd, [Xn|SP + uimm12 * 2]: 01 111 001 00 imm12 n d -+ LDRH Wd, [Xn|SP + uimm12 * 2]: 01 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 2); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X01, X111001, isLoad ? X01 : X00, -+ uimm12, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STRH Xd, [Xn|SP, Xm]: 01 111 000 001 m 011 0 10 n d -+ LDRH Xd, [Xn|SP, Xm]: 01 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X011, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store16"); -+ vassert(0); -+} -+ -+ -+/* Generate a 32 bit store or 32-to-64 unsigned widening load from/to -+ rD, using the given amode for the address. */ -+static UInt* do_load_or_store32 ( UInt* p, -+ Bool isLoad, UInt wD, ARM64AMode* am ) -+{ -+ vassert(wD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STUR Wd, [Xn|SP + simm9]: 10 111000 000 simm9 00 n d -+ LDUR Wd, [Xn|SP + simm9]: 10 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt instr = X_2_6_3_9_2_5_5(X10, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, -+ iregNo(am->ARM64am.RI9.reg), wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STR Wd, [Xn|SP + uimm12 * 4]: 10 111 001 00 imm12 n d -+ LDR Wd, [Xn|SP + uimm12 * 4]: 10 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 4); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X10, X111001, isLoad ? X01 : X00, -+ uimm12, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STR Wd, [Xn|SP, Xm]: 10 111 000 001 m 011 0 10 n d -+ LDR Wd, [Xn|SP, Xm]: 10 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X101, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, wD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store32"); -+ vassert(0); -+} -+ -+ -+/* Generate a 64 bit load or store to/from xD, using the given amode -+ for the address. */ -+static UInt* do_load_or_store64 ( UInt* p, -+ Bool isLoad, UInt xD, ARM64AMode* am ) -+{ -+ /* In all these cases, Rn can't be 31 since that means SP. */ -+ vassert(xD <= 30); -+ if (am->tag == ARM64am_RI9) { -+ /* STUR Xd, [Xn|SP + simm9]: 11 111000 000 simm9 00 n d -+ LDUR Xd, [Xn|SP + simm9]: 11 111000 010 simm9 00 n d -+ */ -+ Int simm9 = am->ARM64am.RI9.simm9; -+ vassert(-256 <= simm9 && simm9 <= 255); -+ UInt xN = iregNo(am->ARM64am.RI9.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_3_9_2_5_5(X11, X111000, isLoad ? X010 : X000, -+ simm9 & 0x1FF, X00, xN, xD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RI12) { -+ /* STR Xd, [Xn|SP + uimm12 * 8]: 11 111 001 00 imm12 n d -+ LDR Xd, [Xn|SP + uimm12 * 8]: 11 111 001 01 imm12 n d -+ */ -+ UInt uimm12 = am->ARM64am.RI12.uimm12; -+ UInt scale = am->ARM64am.RI12.szB; -+ vassert(scale == 8); /* failure of this is serious. Do not ignore. */ -+ UInt xN = iregNo(am->ARM64am.RI12.reg); -+ vassert(xN <= 30); -+ UInt instr = X_2_6_2_12_5_5(X11, X111001, isLoad ? X01 : X00, -+ uimm12, xN, xD); -+ *p++ = instr; -+ return p; -+ } -+ if (am->tag == ARM64am_RR) { -+ /* STR Xd, [Xn|SP, Xm]: 11 111 000 001 m 011 0 10 n d -+ LDR Xd, [Xn|SP, Xm]: 11 111 000 011 m 011 0 10 n d -+ */ -+ UInt xN = iregNo(am->ARM64am.RR.base); -+ UInt xM = iregNo(am->ARM64am.RR.index); -+ vassert(xN <= 30); -+ UInt instr = X_3_8_5_6_5_5(X111, isLoad ? X11000011 : X11000001, -+ xM, X011010, xN, xD); -+ *p++ = instr; -+ return p; -+ } -+ vpanic("do_load_or_store64"); -+ vassert(0); -+} -+ -+ -+/* Emit an instruction into buf and return the number of bytes used. -+ Note that buf is not the insn's final place, and therefore it is -+ imperative to emit position-independent code. If the emitted -+ instruction was a profiler inc, set *is_profInc to True, else -+ leave it unchanged. */ -+ -+Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, -+ UChar* buf, Int nbuf, ARM64Instr* i, -+ Bool mode64, -+ void* disp_cp_chain_me_to_slowEP, -+ void* disp_cp_chain_me_to_fastEP, -+ void* disp_cp_xindir, -+ void* disp_cp_xassisted ) -+{ -+ UInt* p = (UInt*)buf; -+ vassert(nbuf >= 32); -+ vassert(mode64 == True); -+ vassert(0 == (((HWord)buf) & 3)); -+ -+ switch (i->tag) { -+ case ARM64in_Arith: { -+ UInt rD = iregNo(i->ARM64in.Arith.dst); -+ UInt rN = iregNo(i->ARM64in.Arith.argL); -+ ARM64RIA* argR = i->ARM64in.Arith.argR; -+ switch (argR->tag) { -+ case ARM64riA_I12: -+ *p++ = X_2_6_2_12_5_5( -+ i->ARM64in.Arith.isAdd ? X10 : X11, -+ X010001, -+ argR->ARM64riA.I12.shift == 12 ? X01 : X00, -+ argR->ARM64riA.I12.imm12, rN, rD -+ ); -+ break; -+ case ARM64riA_R: { -+ UInt rM = iregNo(i->ARM64in.Arith.argR->ARM64riA.R.reg); -+ *p++ = X_3_8_5_6_5_5( -+ i->ARM64in.Arith.isAdd ? X100 : X110, -+ X01011000, rM, X000000, rN, rD -+ ); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Cmp: { -+ UInt rD = 31; /* XZR, we are going to dump the result */ -+ UInt rN = iregNo(i->ARM64in.Cmp.argL); -+ ARM64RIA* argR = i->ARM64in.Cmp.argR; -+ Bool is64 = i->ARM64in.Cmp.is64; -+ switch (argR->tag) { -+ case ARM64riA_I12: -+ /* 1 11 10001 sh imm12 Rn Rd = SUBS Xd, Xn, #imm */ -+ /* 0 11 10001 sh imm12 Rn Rd = SUBS Wd, Wn, #imm */ -+ *p++ = X_2_6_2_12_5_5( -+ is64 ? X11 : X01, X110001, -+ argR->ARM64riA.I12.shift == 12 ? X01 : X00, -+ argR->ARM64riA.I12.imm12, rN, rD); -+ break; -+ case ARM64riA_R: { -+ /* 1 11 01011 00 0 Rm 000000 Rn Rd = SUBS Xd, Xn, Xm */ -+ /* 0 11 01011 00 0 Rm 000000 Rn Rd = SUBS Wd, Wn, Wm */ -+ UInt rM = iregNo(i->ARM64in.Cmp.argR->ARM64riA.R.reg); -+ *p++ = X_3_8_5_6_5_5(is64 ? X111 : X011, -+ X01011000, rM, X000000, rN, rD); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Logic: { -+ UInt rD = iregNo(i->ARM64in.Logic.dst); -+ UInt rN = iregNo(i->ARM64in.Logic.argL); -+ ARM64RIL* argR = i->ARM64in.Logic.argR; -+ UInt opc = 0; /* invalid */ -+ vassert(rD < 31); -+ vassert(rN < 31); -+ switch (i->ARM64in.Logic.op) { -+ case ARM64lo_OR: opc = X101; break; -+ case ARM64lo_AND: opc = X100; break; -+ case ARM64lo_XOR: opc = X110; break; -+ default: break; -+ } -+ vassert(opc != 0); -+ switch (argR->tag) { -+ case ARM64riL_I13: { -+ /* 1 01 100100 N immR immS Rn Rd = ORR , Xn, #imm */ -+ /* 1 00 100100 N immR immS Rn Rd = AND , Xn, #imm */ -+ /* 1 10 100100 N immR immS Rn Rd = EOR , Xn, #imm */ -+ *p++ = X_3_6_1_6_6_5_5( -+ opc, X100100, argR->ARM64riL.I13.bitN, -+ argR->ARM64riL.I13.immR, argR->ARM64riL.I13.immS, -+ rN, rD -+ ); -+ break; -+ } -+ case ARM64riL_R: { -+ /* 1 01 01010 00 0 m 000000 n d = ORR Xd, Xn, Xm */ -+ /* 1 00 01010 00 0 m 000000 n d = AND Xd, Xn, Xm */ -+ /* 1 10 01010 00 0 m 000000 n d = EOR Xd, Xn, Xm */ -+ UInt rM = iregNo(argR->ARM64riL.R.reg); -+ vassert(rM < 31); -+ *p++ = X_3_8_5_6_5_5(opc, X01010000, rM, X000000, rN, rD); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Test: { -+ UInt rD = 31; /* XZR, we are going to dump the result */ -+ UInt rN = iregNo(i->ARM64in.Test.argL); -+ ARM64RIL* argR = i->ARM64in.Test.argR; -+ switch (argR->tag) { -+ case ARM64riL_I13: { -+ /* 1 11 100100 N immR immS Rn Rd = ANDS Xd, Xn, #imm */ -+ *p++ = X_3_6_1_6_6_5_5( -+ X111, X100100, argR->ARM64riL.I13.bitN, -+ argR->ARM64riL.I13.immR, argR->ARM64riL.I13.immS, -+ rN, rD -+ ); -+ break; -+ } -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_Shift: { -+ UInt rD = iregNo(i->ARM64in.Shift.dst); -+ UInt rN = iregNo(i->ARM64in.Shift.argL); -+ ARM64RI6* argR = i->ARM64in.Shift.argR; -+ vassert(rD < 31); -+ vassert(rN < 31); -+ switch (argR->tag) { -+ case ARM64ri6_I6: { -+ /* 110 1001101 (63-sh) (64-sh) nn dd LSL Xd, Xn, sh */ -+ /* 110 1001101 sh 63 nn dd LSR Xd, Xn, sh */ -+ /* 100 1001101 sh 63 nn dd ASR Xd, Xn, sh */ -+ UInt sh = argR->ARM64ri6.I6.imm6; -+ vassert(sh > 0 && sh < 64); -+ switch (i->ARM64in.Shift.op) { -+ case ARM64sh_SHL: -+ *p++ = X_3_6_1_6_6_5_5(X110, X100110, -+ 1, 64-sh, 63-sh, rN, rD); -+ break; -+ case ARM64sh_SHR: -+ *p++ = X_3_6_1_6_6_5_5(X110, X100110, 1, sh, 63, rN, rD); -+ break; -+ case ARM64sh_SAR: -+ *p++ = X_3_6_1_6_6_5_5(X100, X100110, 1, sh, 63, rN, rD); -+ break; -+ default: -+ vassert(0); -+ } -+ break; -+ } -+ case ARM64ri6_R: { -+ /* 100 1101 0110 mm 001000 nn dd LSL Xd, Xn, Xm */ -+ /* 100 1101 0110 mm 001001 nn dd LSR Xd, Xn, Xm */ -+ /* 100 1101 0110 mm 001010 nn dd ASR Xd, Xn, Xm */ -+ UInt rM = iregNo(argR->ARM64ri6.R.reg); -+ vassert(rM < 31); -+ UInt subOpc = 0; -+ switch (i->ARM64in.Shift.op) { -+ case ARM64sh_SHL: subOpc = X001000; break; -+ case ARM64sh_SHR: subOpc = X001001; break; -+ case ARM64sh_SAR: subOpc = X001010; break; -+ default: vassert(0); -+ } -+ *p++ = X_3_8_5_6_5_5(X100, X11010110, rM, subOpc, rN, rD); -+ break; -+ } -+ default: -+ vassert(0); -+ } -+ goto done; -+ } -+ case ARM64in_Unary: { -+ UInt rDst = iregNo(i->ARM64in.Unary.dst); -+ UInt rSrc = iregNo(i->ARM64in.Unary.src); -+ switch (i->ARM64in.Unary.op) { -+ case ARM64un_CLZ: -+ /* 1 10 1101 0110 00000 00010 0 nn dd CLZ Xd, Xn */ -+ /* 1 10 1101 0110 00000 00010 1 nn dd CLS Xd, Xn (unimp) */ -+ *p++ = X_3_8_5_6_5_5(X110, -+ X11010110, X00000, X000100, rSrc, rDst); -+ goto done; -+ case ARM64un_NEG: -+ /* 1 10 01011 000 m 000000 11111 d NEG Xd,Xm */ -+ /* 0 10 01011 000 m 000000 11111 d NEG Wd,Wm (unimp) */ -+ *p++ = X_3_8_5_6_5_5(X110, -+ X01011000, rSrc, X000000, X11111, rDst); -+ goto done; -+ case ARM64un_NOT: { -+ /* 1 01 01010 00 1 m 000000 11111 d MVN Xd,Xm */ -+ *p++ = X_3_8_5_6_5_5(X101, -+ X01010001, rSrc, X000000, X11111, rDst); -+ goto done; -+ } -+ default: -+ break; -+ } -+ goto bad; -+ } -+ case ARM64in_MovI: { -+ /* We generate the "preferred form", ORR Xd, XZR, Xm -+ 101 01010 00 0 m 000000 11111 d -+ */ -+ UInt instr = 0xAA0003E0; -+ UInt d = iregNo(i->ARM64in.MovI.dst); -+ UInt m = iregNo(i->ARM64in.MovI.src); -+ *p++ = instr | ((m & 31) << 16) | ((d & 31) << 0); -+ goto done; -+ } -+ case ARM64in_Imm64: { -+ p = imm64_to_iregNo( p, iregNo(i->ARM64in.Imm64.dst), -+ i->ARM64in.Imm64.imm64 ); -+ goto done; -+ } -+ case ARM64in_LdSt64: { -+ p = do_load_or_store64( p, i->ARM64in.LdSt64.isLoad, -+ iregNo(i->ARM64in.LdSt64.rD), -+ i->ARM64in.LdSt64.amode ); -+ goto done; -+ } -+ case ARM64in_LdSt32: { -+ p = do_load_or_store32( p, i->ARM64in.LdSt32.isLoad, -+ iregNo(i->ARM64in.LdSt32.rD), -+ i->ARM64in.LdSt32.amode ); -+ goto done; -+ } -+ case ARM64in_LdSt16: { -+ p = do_load_or_store16( p, i->ARM64in.LdSt16.isLoad, -+ iregNo(i->ARM64in.LdSt16.rD), -+ i->ARM64in.LdSt16.amode ); -+ goto done; -+ } -+ case ARM64in_LdSt8: { -+ p = do_load_or_store8( p, i->ARM64in.LdSt8.isLoad, -+ iregNo(i->ARM64in.LdSt8.rD), -+ i->ARM64in.LdSt8.amode ); -+ goto done; -+ } -+//ZZ case ARMin_LdSt32: -+//ZZ case ARMin_LdSt8U: { -+//ZZ UInt bL, bB; -+//ZZ HReg rD; -+//ZZ ARMAMode1* am; -+//ZZ ARMCondCode cc; -+//ZZ if (i->tag == ARMin_LdSt32) { -+//ZZ bB = 0; -+//ZZ bL = i->ARMin.LdSt32.isLoad ? 1 : 0; -+//ZZ am = i->ARMin.LdSt32.amode; -+//ZZ rD = i->ARMin.LdSt32.rD; -+//ZZ cc = i->ARMin.LdSt32.cc; -+//ZZ } else { -+//ZZ bB = 1; -+//ZZ bL = i->ARMin.LdSt8U.isLoad ? 1 : 0; -+//ZZ am = i->ARMin.LdSt8U.amode; -+//ZZ rD = i->ARMin.LdSt8U.rD; -+//ZZ cc = i->ARMin.LdSt8U.cc; -+//ZZ } -+//ZZ vassert(cc != ARMcc_NV); -+//ZZ if (am->tag == ARMam1_RI) { -+//ZZ Int simm12; -+//ZZ UInt instr, bP; -+//ZZ if (am->ARMam1.RI.simm13 < 0) { -+//ZZ bP = 0; -+//ZZ simm12 = -am->ARMam1.RI.simm13; -+//ZZ } else { -+//ZZ bP = 1; -+//ZZ simm12 = am->ARMam1.RI.simm13; -+//ZZ } -+//ZZ vassert(simm12 >= 0 && simm12 <= 4095); -+//ZZ instr = XXXXX___(cc,X0101,BITS4(bP,bB,0,bL), -+//ZZ iregNo(am->ARMam1.RI.reg), -+//ZZ iregNo(rD)); -+//ZZ instr |= simm12; -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } else { -+//ZZ // RR case -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+//ZZ case ARMin_LdSt16: { -+//ZZ HReg rD = i->ARMin.LdSt16.rD; -+//ZZ UInt bS = i->ARMin.LdSt16.signedLoad ? 1 : 0; -+//ZZ UInt bL = i->ARMin.LdSt16.isLoad ? 1 : 0; -+//ZZ ARMAMode2* am = i->ARMin.LdSt16.amode; -+//ZZ ARMCondCode cc = i->ARMin.LdSt16.cc; -+//ZZ vassert(cc != ARMcc_NV); -+//ZZ if (am->tag == ARMam2_RI) { -+//ZZ HReg rN = am->ARMam2.RI.reg; -+//ZZ Int simm8; -+//ZZ UInt bP, imm8hi, imm8lo, instr; -+//ZZ if (am->ARMam2.RI.simm9 < 0) { -+//ZZ bP = 0; -+//ZZ simm8 = -am->ARMam2.RI.simm9; -+//ZZ } else { -+//ZZ bP = 1; -+//ZZ simm8 = am->ARMam2.RI.simm9; -+//ZZ } -+//ZZ vassert(simm8 >= 0 && simm8 <= 255); -+//ZZ imm8hi = (simm8 >> 4) & 0xF; -+//ZZ imm8lo = simm8 & 0xF; -+//ZZ vassert(!(bL == 0 && bS == 1)); // "! signed store" -+//ZZ /**/ if (bL == 0 && bS == 0) { -+//ZZ // strh -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,0), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1011, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } -+//ZZ else if (bL == 1 && bS == 0) { -+//ZZ // ldrh -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1011, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } -+//ZZ else if (bL == 1 && bS == 1) { -+//ZZ // ldrsh -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1111, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } -+//ZZ else vassert(0); // ill-constructed insn -+//ZZ } else { -+//ZZ // RR case -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+//ZZ case ARMin_Ld8S: { -+//ZZ HReg rD = i->ARMin.Ld8S.rD; -+//ZZ ARMAMode2* am = i->ARMin.Ld8S.amode; -+//ZZ ARMCondCode cc = i->ARMin.Ld8S.cc; -+//ZZ vassert(cc != ARMcc_NV); -+//ZZ if (am->tag == ARMam2_RI) { -+//ZZ HReg rN = am->ARMam2.RI.reg; -+//ZZ Int simm8; -+//ZZ UInt bP, imm8hi, imm8lo, instr; -+//ZZ if (am->ARMam2.RI.simm9 < 0) { -+//ZZ bP = 0; -+//ZZ simm8 = -am->ARMam2.RI.simm9; -+//ZZ } else { -+//ZZ bP = 1; -+//ZZ simm8 = am->ARMam2.RI.simm9; -+//ZZ } -+//ZZ vassert(simm8 >= 0 && simm8 <= 255); -+//ZZ imm8hi = (simm8 >> 4) & 0xF; -+//ZZ imm8lo = simm8 & 0xF; -+//ZZ // ldrsb -+//ZZ instr = XXXXXXXX(cc,X0001, BITS4(bP,1,0,1), iregNo(rN), -+//ZZ iregNo(rD), imm8hi, X1101, imm8lo); -+//ZZ *p++ = instr; -+//ZZ goto done; -+//ZZ } else { -+//ZZ // RR case -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+ -+ case ARM64in_XDirect: { -+ /* NB: what goes on here has to be very closely coordinated -+ with chainXDirect_ARM64 and unchainXDirect_ARM64 below. */ -+ /* We're generating chain-me requests here, so we need to be -+ sure this is actually allowed -- no-redir translations -+ can't use chain-me's. Hence: */ -+ vassert(disp_cp_chain_me_to_slowEP != NULL); -+ vassert(disp_cp_chain_me_to_fastEP != NULL); -+ -+ /* Use ptmp for backpatching conditional jumps. */ -+ UInt* ptmp = NULL; -+ -+ /* First off, if this is conditional, create a conditional -+ jump over the rest of it. Or at least, leave a space for -+ it that we will shortly fill in. */ -+ if (i->ARM64in.XDirect.cond != ARM64cc_AL) { -+ vassert(i->ARM64in.XDirect.cond != ARM64cc_NV); -+ ptmp = p; -+ *p++ = 0; -+ } -+ -+ /* Update the guest PC. */ -+ /* imm64 x9, dstGA */ -+ /* str x9, amPC */ -+ p = imm64_to_iregNo(p, /*x*/9, i->ARM64in.XDirect.dstGA); -+ p = do_load_or_store64(p, False/*!isLoad*/, -+ /*x*/9, i->ARM64in.XDirect.amPC); -+ -+ /* --- FIRST PATCHABLE BYTE follows --- */ -+ /* VG_(disp_cp_chain_me_to_{slowEP,fastEP}) (where we're -+ calling to) backs up the return address, so as to find the -+ address of the first patchable byte. So: don't change the -+ number of instructions (5) below. */ -+ /* movw x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[15:0] */ -+ /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[31:15], lsl 16 */ -+ /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[47:32], lsl 32 */ -+ /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[63:48], lsl 48 */ -+ /* blr x9 */ -+ void* disp_cp_chain_me -+ = i->ARM64in.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP -+ : disp_cp_chain_me_to_slowEP; -+ p = imm64_to_iregNo_EXACTLY4(p, /*x*/9, -+ Ptr_to_ULong(disp_cp_chain_me)); -+ *p++ = 0xD63F0120; -+ /* --- END of PATCHABLE BYTES --- */ -+ -+ /* Fix up the conditional jump, if there was one. */ -+ if (i->ARM64in.XDirect.cond != ARM64cc_AL) { -+ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */ -+ vassert(delta > 0 && delta < 40); -+ vassert((delta & 3) == 0); -+ UInt notCond = 1 ^ (UInt)i->ARM64in.XDirect.cond; -+ vassert(notCond <= 13); /* Neither AL nor NV */ -+ vassert(ptmp != NULL); -+ delta = delta >> 2; -+ *ptmp = X_8_19_1_4(X01010100, delta & ((1<<19)-1), 0, notCond); -+ } -+ goto done; -+ } -+ -+ case ARM64in_XIndir: { -+ // XIndir is more or less the same as XAssisted, except -+ // we don't have a trc value to hand back, so there's no -+ // write to r21 -+ /* Use ptmp for backpatching conditional jumps. */ -+ //UInt* ptmp = NULL; -+ -+ /* First off, if this is conditional, create a conditional -+ jump over the rest of it. Or at least, leave a space for -+ it that we will shortly fill in. */ -+ if (i->ARM64in.XIndir.cond != ARM64cc_AL) { -+ vassert(0); //ATC -+//ZZ vassert(i->ARMin.XIndir.cond != ARMcc_NV); -+//ZZ ptmp = p; -+//ZZ *p++ = 0; -+ } -+ -+ /* Update the guest PC. */ -+ /* str r-dstGA, amPC */ -+ p = do_load_or_store64(p, False/*!isLoad*/, -+ iregNo(i->ARM64in.XIndir.dstGA), -+ i->ARM64in.XIndir.amPC); -+ -+ /* imm64 x9, VG_(disp_cp_xindir) */ -+ /* br x9 */ -+ p = imm64_to_iregNo(p, /*x*/9, Ptr_to_ULong(disp_cp_xindir)); -+ *p++ = 0xD61F0120; /* br x9 */ -+ -+ /* Fix up the conditional jump, if there was one. */ -+ if (i->ARM64in.XIndir.cond != ARM64cc_AL) { -+ vassert(0); //ATC -+//ZZ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */ -+//ZZ vassert(delta > 0 && delta < 40); -+//ZZ vassert((delta & 3) == 0); -+//ZZ UInt notCond = 1 ^ (UInt)i->ARMin.XIndir.cond; -+//ZZ vassert(notCond <= 13); /* Neither AL nor NV */ -+//ZZ delta = (delta >> 2) - 2; -+//ZZ *ptmp = XX______(notCond, X1010) | (delta & 0xFFFFFF); -+ } -+ goto done; -+ } -+ -+ case ARM64in_XAssisted: { -+ /* Use ptmp for backpatching conditional jumps. */ -+ UInt* ptmp = NULL; -+ -+ /* First off, if this is conditional, create a conditional -+ jump over the rest of it. Or at least, leave a space for -+ it that we will shortly fill in. I think this can only -+ ever happen when VEX is driven by the switchbacker. */ -+ if (i->ARM64in.XAssisted.cond != ARM64cc_AL) { -+ vassert(i->ARM64in.XDirect.cond != ARM64cc_NV); -+ ptmp = p; -+ *p++ = 0; -+ } -+ -+ /* Update the guest PC. */ -+ /* str r-dstGA, amPC */ -+ p = do_load_or_store64(p, False/*!isLoad*/, -+ iregNo(i->ARM64in.XAssisted.dstGA), -+ i->ARM64in.XAssisted.amPC); -+ -+ /* movw r21, $magic_number */ -+ UInt trcval = 0; -+ switch (i->ARM64in.XAssisted.jk) { -+ case Ijk_ClientReq: trcval = VEX_TRC_JMP_CLIENTREQ; break; -+ case Ijk_Sys_syscall: trcval = VEX_TRC_JMP_SYS_SYSCALL; break; -+ //case Ijk_Sys_int128: trcval = VEX_TRC_JMP_SYS_INT128; break; -+ //case Ijk_Yield: trcval = VEX_TRC_JMP_YIELD; break; -+ //case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; -+ //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; -+ case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; -+ case Ijk_FlushDCache: trcval = VEX_TRC_JMP_FLUSHDCACHE; break; -+ case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; -+ //case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; -+ //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; -+ case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break; -+ /* We don't expect to see the following being assisted. */ -+ //case Ijk_Ret: -+ //case Ijk_Call: -+ /* fallthrough */ -+ default: -+ ppIRJumpKind(i->ARM64in.XAssisted.jk); -+ vpanic("emit_ARM64Instr.ARM64in_XAssisted: " -+ "unexpected jump kind"); -+ } -+ vassert(trcval != 0); -+ p = imm64_to_iregNo(p, /*x*/21, (ULong)trcval); -+ -+ /* imm64 x9, VG_(disp_cp_xassisted) */ -+ /* br x9 */ -+ p = imm64_to_iregNo(p, /*x*/9, Ptr_to_ULong(disp_cp_xassisted)); -+ *p++ = 0xD61F0120; /* br x9 */ -+ -+ /* Fix up the conditional jump, if there was one. */ -+ if (i->ARM64in.XAssisted.cond != ARM64cc_AL) { -+ Int delta = (UChar*)p - (UChar*)ptmp; /* must be signed */ -+ vassert(delta > 0 && delta < 40); -+ vassert((delta & 3) == 0); -+ UInt notCond = 1 ^ (UInt)i->ARM64in.XDirect.cond; -+ vassert(notCond <= 13); /* Neither AL nor NV */ -+ vassert(ptmp != NULL); -+ delta = delta >> 2; -+ *ptmp = X_8_19_1_4(X01010100, delta & ((1<<19)-1), 0, notCond); -+ } -+ goto done; -+ } -+ -+ case ARM64in_CSel: { -+ /* 100 1101 0100 mm cond 00 nn dd = CSEL Xd, Xn, Xm, cond */ -+ UInt dd = iregNo(i->ARM64in.CSel.dst); -+ UInt nn = iregNo(i->ARM64in.CSel.argL); -+ UInt mm = iregNo(i->ARM64in.CSel.argR); -+ UInt cond = (UInt)i->ARM64in.CSel.cond; -+ vassert(dd < 31 && nn < 31 && mm < 31 && cond < 16); -+ *p++ = X_3_8_5_6_5_5(X100, X11010100, mm, cond << 2, nn, dd); -+ goto done; -+ } -+ -+ case ARM64in_Call: { -+ /* We'll use x9 as a scratch register to put the target -+ address in. */ -+ if (i->ARM64in.Call.cond != ARM64cc_AL -+ && i->ARM64in.Call.rloc.pri != RLPri_None) { -+ /* The call might not happen (it isn't unconditional) and -+ it returns a result. In this case we will need to -+ generate a control flow diamond to put 0x555..555 in -+ the return register(s) in the case where the call -+ doesn't happen. If this ever becomes necessary, maybe -+ copy code from the 32-bit ARM equivalent. Until that -+ day, just give up. */ -+ goto bad; -+ } -+ -+ UInt* ptmp = NULL; -+ if (i->ARM64in.Call.cond != ARM64cc_AL) { -+ /* Create a hole to put a conditional branch in. We'll -+ patch it once we know the branch length. */ -+ ptmp = p; -+ *p++ = 0; -+ } -+ -+ // x9 = &target -+ p = imm64_to_iregNo( (UInt*)p, -+ /*x*/9, (ULong)i->ARM64in.Call.target ); -+ // blr x9 -+ *p++ = 0xD63F0120; -+ -+ // Patch the hole if necessary -+ if (i->ARM64in.Call.cond != ARM64cc_AL) { -+ ULong dist = (ULong)(p - ptmp); -+ /* imm64_to_iregNo produces between 1 and 4 insns, and -+ then there's the BLR itself. Hence: */ -+ vassert(dist >= 2 && dist <= 5); -+ vassert(ptmp != NULL); -+ // 01010100 simm19 0 cond = B.cond (here + simm19 << 2) -+ *ptmp = X_8_19_1_4(X01010100, dist, 0, -+ 1 ^ (UInt)i->ARM64in.Call.cond); -+ } else { -+ vassert(ptmp == NULL); -+ } -+ -+ goto done; -+ } -+ -+ case ARM64in_AddToSP: { -+ /* 10,0 10001 00 imm12 11111 11111 ADD xsp, xsp, #imm12 -+ 11,0 10001 00 imm12 11111 11111 SUB xsp, xsp, #imm12 -+ */ -+ Int simm12 = i->ARM64in.AddToSP.simm; -+ vassert(-4096 < simm12 && simm12 < 4096); -+ vassert(0 == (simm12 & 0xF)); -+ if (simm12 >= 0) { -+ *p++ = X_2_6_2_12_5_5(X10, X010001, X00, simm12, X11111, X11111); -+ } else { -+ *p++ = X_2_6_2_12_5_5(X11, X010001, X00, -simm12, X11111, X11111); -+ } -+ goto done; -+ } -+ -+ case ARM64in_FromSP: { -+ /* 10,0 10001 00 0..(12)..0 11111 dd MOV Xd, xsp */ -+ UInt dd = iregNo(i->ARM64in.FromSP.dst); -+ vassert(dd < 31); -+ *p++ = X_2_6_2_12_5_5(X10, X010001, X00, 0, X11111, dd); -+ goto done; -+ } -+ -+ case ARM64in_Mul: { -+ /* 100 11011 110 mm 011111 nn dd UMULH Xd, Xn,Xm -+ 100 11011 010 mm 011111 nn dd SMULH Xd, Xn,Xm -+ 100 11011 000 mm 011111 nn dd MUL Xd, Xn,Xm -+ */ -+ UInt dd = iregNo(i->ARM64in.Mul.dst); -+ UInt nn = iregNo(i->ARM64in.Mul.argL); -+ UInt mm = iregNo(i->ARM64in.Mul.argR); -+ vassert(dd < 31 && nn < 31 && mm < 31); -+ switch (i->ARM64in.Mul.op) { -+ case ARM64mul_ZX: -+ *p++ = X_3_8_5_6_5_5(X100, X11011110, mm, X011111, nn, dd); -+ goto done; -+ case ARM64mul_SX: -+ *p++ = X_3_8_5_6_5_5(X100, X11011010, mm, X011111, nn, dd); -+ goto done; -+ case ARM64mul_PLAIN: -+ *p++ = X_3_8_5_6_5_5(X100, X11011000, mm, X011111, nn, dd); -+ goto done; -+ default: -+ vassert(0); -+ } -+ goto bad; -+ } -+ case ARM64in_LdrEX: { -+ /* 085F7C82 ldxrb w2, [x4] -+ 485F7C82 ldxrh w2, [x4] -+ 885F7C82 ldxr w2, [x4] -+ C85F7C82 ldxr x2, [x4] -+ */ -+ switch (i->ARM64in.LdrEX.szB) { -+ case 1: *p++ = 0x085F7C82; goto done; -+ case 2: *p++ = 0x485F7C82; goto done; -+ case 4: *p++ = 0x885F7C82; goto done; -+ case 8: *p++ = 0xC85F7C82; goto done; -+ default: break; -+ } -+ goto bad; -+ } -+ case ARM64in_StrEX: { -+ /* 08007C82 stxrb w0, w2, [x4] -+ 48007C82 stxrh w0, w2, [x4] -+ 88007C82 stxr w0, w2, [x4] -+ C8007C82 stxr w0, x2, [x4] -+ */ -+ switch (i->ARM64in.StrEX.szB) { -+ case 1: *p++ = 0x08007C82; goto done; -+ case 2: *p++ = 0x48007C82; goto done; -+ case 4: *p++ = 0x88007C82; goto done; -+ case 8: *p++ = 0xC8007C82; goto done; -+ default: break; -+ } -+ goto bad; -+ } -+ case ARM64in_MFence: { -+ *p++ = 0xD5033F9F; /* DSB sy */ -+ *p++ = 0xD5033FBF; /* DMB sy */ -+ *p++ = 0xD5033FDF; /* ISB */ -+ goto done; -+ } -+ //case ARM64in_CLREX: { -+ // //ATC, but believed to be correct -+ // goto bad; -+ // *p++ = 0xD5033F5F; /* clrex */ -+ // goto done; -+ //} -+ case ARM64in_VLdStS: { -+ /* 10 111101 01 imm12 n t LDR St, [Xn|SP, #imm12 * 4] -+ 10 111101 00 imm12 n t STR St, [Xn|SP, #imm12 * 4] -+ */ -+ UInt sD = dregNo(i->ARM64in.VLdStS.sD); -+ UInt rN = iregNo(i->ARM64in.VLdStS.rN); -+ UInt uimm12 = i->ARM64in.VLdStS.uimm12; -+ Bool isLD = i->ARM64in.VLdStS.isLoad; -+ vassert(uimm12 < 16384 && 0 == (uimm12 & 3)); -+ uimm12 >>= 2; -+ vassert(uimm12 < (1<<12)); -+ vassert(sD < 32); -+ vassert(rN < 31); -+ *p++ = X_2_6_2_12_5_5(X10, X111101, isLD ? X01 : X00, -+ uimm12, rN, sD); -+ goto done; -+ } -+ case ARM64in_VLdStD: { -+ /* 11 111101 01 imm12 n t LDR Dt, [Xn|SP, #imm12 * 8] -+ 11 111101 00 imm12 n t STR Dt, [Xn|SP, #imm12 * 8] -+ */ -+ UInt dD = dregNo(i->ARM64in.VLdStD.dD); -+ UInt rN = iregNo(i->ARM64in.VLdStD.rN); -+ UInt uimm12 = i->ARM64in.VLdStD.uimm12; -+ Bool isLD = i->ARM64in.VLdStD.isLoad; -+ vassert(uimm12 < 32768 && 0 == (uimm12 & 7)); -+ uimm12 >>= 3; -+ vassert(uimm12 < (1<<12)); -+ vassert(dD < 32); -+ vassert(rN < 31); -+ *p++ = X_2_6_2_12_5_5(X11, X111101, isLD ? X01 : X00, -+ uimm12, rN, dD); -+ goto done; -+ } -+ case ARM64in_VLdStQ: { -+ /* 0100 1100 0000 0000 0111 11 rN rQ st1 {vQ.2d}, [] -+ 0100 1100 0100 0000 0111 11 rN rQ ld1 {vQ.2d}, [] -+ */ -+ UInt rQ = qregNo(i->ARM64in.VLdStQ.rQ); -+ UInt rN = iregNo(i->ARM64in.VLdStQ.rN); -+ vassert(rQ < 32); -+ vassert(rN < 31); -+ if (i->ARM64in.VLdStQ.isLoad) { -+ *p++ = 0x4C407C00 | (rN << 5) | rQ; -+ } else { -+ *p++ = 0x4C007C00 | (rN << 5) | rQ; -+ } -+ goto done; -+ } -+ case ARM64in_VCvtI2F: { -+ /* 31 28 23 21 20 18 15 9 4 -+ 000 11110 00 1 00 010 000000 n d SCVTF Sd, Wn -+ 000 11110 01 1 00 010 000000 n d SCVTF Dd, Wn -+ 100 11110 00 1 00 010 000000 n d SCVTF Sd, Xn -+ 100 11110 01 1 00 010 000000 n d SCVTF Dd, Xn -+ 000 11110 00 1 00 011 000000 n d UCVTF Sd, Wn -+ 000 11110 01 1 00 011 000000 n d UCVTF Dd, Wn -+ 100 11110 00 1 00 011 000000 n d UCVTF Sd, Xn -+ 100 11110 01 1 00 011 000000 n d UCVTF Dd, Xn -+ */ -+ UInt rN = iregNo(i->ARM64in.VCvtI2F.rS); -+ UInt rD = dregNo(i->ARM64in.VCvtI2F.rD); -+ ARM64CvtOp how = i->ARM64in.VCvtI2F.how; -+ /* Just handle cases as they show up. */ -+ switch (how) { -+ case ARM64cvt_F32_I32S: /* SCVTF Sd, Wn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100010, X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I32S: /* SCVTF Dd, Wn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100010, X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I64S: /* SCVTF Sd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X00100010, X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64S: /* SCVTF Dd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100010, X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I32U: /* UCVTF Sd, Wn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100011, X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I32U: /* UCVTF Dd, Wn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100011, X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I64U: /* UCVTF Sd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X00100011, X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64U: /* UCVTF Dd, Xn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100011, X000000, rN, rD); -+ break; -+ default: -+ goto bad; //ATC -+ } -+ goto done; -+ } -+ case ARM64in_VCvtF2I: { -+ /* 30 23 20 18 15 9 4 -+ sf 00,11110,0x 1 00 000,000000 n d FCVTNS Rd, Fn (round to -+ sf 00,11110,0x 1 00 001,000000 n d FCVTNU Rd, Fn nearest) -+ ---------------- 01 -------------- FCVTP-------- (round to +inf) -+ ---------------- 10 -------------- FCVTM-------- (round to -inf) -+ ---------------- 11 -------------- FCVTZ-------- (round to zero) -+ -+ Rd is Xd when sf==1, Wd when sf==0 -+ Fn is Dn when x==1, Sn when x==0 -+ 20:19 carry the rounding mode, using the same encoding as FPCR -+ */ -+ UInt rD = iregNo(i->ARM64in.VCvtF2I.rD); -+ UInt rN = dregNo(i->ARM64in.VCvtF2I.rS); -+ ARM64CvtOp how = i->ARM64in.VCvtF2I.how; -+ UChar armRM = i->ARM64in.VCvtF2I.armRM; -+ /* Just handle cases as they show up. */ -+ switch (how) { -+ case ARM64cvt_F64_I32S: /* FCVTxS Wd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100000 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I32U: /* FCVTxU Wd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100001 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64S: /* FCVTxS Xd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100000 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F64_I64U: /* FCVTxU Xd, Dn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X01100001 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I32S: /* FCVTxS Wd, Sn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100000 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I32U: /* FCVTxU Wd, Sn */ -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100001 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I64S: /* FCVTxS Xd, Sn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X00100000 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ case ARM64cvt_F32_I64U: /* FCVTxU Xd, Sn */ -+ *p++ = X_3_5_8_6_5_5(X100, X11110, X00100001 | (armRM << 3), -+ X000000, rN, rD); -+ break; -+ default: -+ goto bad; //ATC -+ } -+ goto done; -+ } -+ case ARM64in_VCvtSD: { -+ /* 31 23 21 16 14 9 4 -+ 000,11110, 00 10001 0,1 10000 n d FCVT Dd, Sn (S->D) -+ ---------- 01 ----- 0,0 --------- FCVT Sd, Dn (D->S) -+ Rounding, when dst is smaller than src, is per the FPCR. -+ */ -+ UInt dd = dregNo(i->ARM64in.VCvtSD.dst); -+ UInt nn = dregNo(i->ARM64in.VCvtSD.src); -+ if (i->ARM64in.VCvtSD.sToD) { -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X00100010, X110000, nn, dd); -+ } else { -+ *p++ = X_3_5_8_6_5_5(X000, X11110, X01100010, X010000, nn, dd); -+ } -+ goto done; -+ } -+ case ARM64in_VUnaryD: { -+ /* 31 23 21 16 14 9 4 -+ 000,11110 01 1,0000 0,0 10000 n d FMOV Dd, Dn (not handled) -+ ------------------- 0,1 --------- FABS ------ -+ ------------------- 1,0 --------- FNEG ------ -+ ------------------- 1,1 --------- FQSRT ----- -+ */ -+ UInt dD = dregNo(i->ARM64in.VUnaryD.dst); -+ UInt dN = dregNo(i->ARM64in.VUnaryD.src); -+ UInt b16 = 2; /* impossible */ -+ UInt b15 = 2; /* impossible */ -+ switch (i->ARM64in.VUnaryD.op) { -+ case ARM64fpu_NEG: b16 = 1; b15 = 0; break; -+ case ARM64fpu_SQRT: b16 = 1; b15 = 1; break; -+ case ARM64fpu_ABS: b16 = 0; b15 = 1; break; -+ default: break; -+ } -+ if (b16 < 2 && b15 < 2) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, (X0000 << 1) | b16, -+ (b15 << 5) | X10000, dN, dD); -+ goto done; -+ } -+ /* -+ 000, 11110 01 1,001 11,1 10000 n d FRINTI Dd, Dm (round per FPCR) -+ */ -+ if (i->ARM64in.VUnaryD.op == ARM64fpu_RINT) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, X00111, X110000, dN, dD); -+ goto done; -+ } -+ goto bad; -+ } -+ case ARM64in_VUnaryS: { -+ /* 31 23 21 16 14 9 4 -+ 000,11110 00 1,0000 0,0 10000 n d FMOV Sd, Sn (not handled) -+ ------------------- 0,1 --------- FABS ------ -+ ------------------- 1,0 --------- FNEG ------ -+ ------------------- 1,1 --------- FQSRT ----- -+ */ -+ UInt sD = dregNo(i->ARM64in.VUnaryS.dst); -+ UInt sN = dregNo(i->ARM64in.VUnaryS.src); -+ UInt b16 = 2; /* impossible */ -+ UInt b15 = 2; /* impossible */ -+ switch (i->ARM64in.VUnaryS.op) { -+ case ARM64fpu_NEG: b16 = 1; b15 = 0; break; -+ case ARM64fpu_SQRT: b16 = 1; b15 = 1; break; -+ case ARM64fpu_ABS: b16 = 0; b15 = 1; break; -+ default: break; -+ } -+ if (b16 < 2 && b15 < 2) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110001, (X0000 << 1) | b16, -+ (b15 << 5) | X10000, sN, sD); -+ goto done; -+ } -+ /* -+ 000, 11110 00 1,001 11,1 10000 n d FRINTI Sd, Sm (round per FPCR) -+ */ -+ if (i->ARM64in.VUnaryS.op == ARM64fpu_RINT) { -+ *p++ = X_3_8_5_6_5_5(X000, X11110001, X00111, X110000, sN, sD); -+ goto done; -+ } -+ goto bad; -+ } -+ case ARM64in_VBinD: { -+ /* 31 23 20 15 11 9 4 -+ ---------------- 0000 ------ FMUL -------- -+ 000 11110 011 m 0001 10 n d FDIV Dd,Dn,Dm -+ ---------------- 0010 ------ FADD -------- -+ ---------------- 0011 ------ FSUB -------- -+ */ -+ UInt dD = dregNo(i->ARM64in.VBinD.dst); -+ UInt dN = dregNo(i->ARM64in.VBinD.argL); -+ UInt dM = dregNo(i->ARM64in.VBinD.argR); -+ UInt b1512 = 16; /* impossible */ -+ switch (i->ARM64in.VBinD.op) { -+ case ARM64fpb_DIV: b1512 = X0001; break; -+ case ARM64fpb_MUL: b1512 = X0000; break; -+ case ARM64fpb_SUB: b1512 = X0011; break; -+ case ARM64fpb_ADD: b1512 = X0010; break; -+ default: goto bad; -+ } -+ vassert(b1512 < 16); -+ *p++ -+ = X_3_8_5_6_5_5(X000, X11110011, dM, (b1512 << 2) | X10, dN, dD); -+ goto done; -+ } -+ case ARM64in_VBinS: { -+ /* 31 23 20 15 11 9 4 -+ ---------------- 0000 ------ FMUL -------- -+ 000 11110 001 m 0001 10 n d FDIV Dd,Dn,Dm -+ ---------------- 0010 ------ FADD -------- -+ ---------------- 0011 ------ FSUB -------- -+ */ -+ UInt sD = dregNo(i->ARM64in.VBinS.dst); -+ UInt sN = dregNo(i->ARM64in.VBinS.argL); -+ UInt sM = dregNo(i->ARM64in.VBinS.argR); -+ UInt b1512 = 16; /* impossible */ -+ switch (i->ARM64in.VBinS.op) { -+ case ARM64fpb_DIV: b1512 = X0001; break; -+ case ARM64fpb_MUL: b1512 = X0000; break; -+ case ARM64fpb_SUB: b1512 = X0011; break; -+ case ARM64fpb_ADD: b1512 = X0010; break; -+ default: goto bad; -+ } -+ vassert(b1512 < 16); -+ *p++ -+ = X_3_8_5_6_5_5(X000, X11110001, sM, (b1512 << 2) | X10, sN, sD); -+ goto done; -+ } -+ case ARM64in_VCmpD: { -+ /* 000 11110 01 1 m 00 1000 n 00 000 FCMP Dn, Dm */ -+ UInt dN = dregNo(i->ARM64in.VCmpD.argL); -+ UInt dM = dregNo(i->ARM64in.VCmpD.argR); -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, dM, X001000, dN, X00000); -+ goto done; -+ } -+ case ARM64in_VCmpS: { -+ /* 000 11110 00 1 m 00 1000 n 00 000 FCMP Sn, Sm */ -+ UInt sN = dregNo(i->ARM64in.VCmpS.argL); -+ UInt sM = dregNo(i->ARM64in.VCmpS.argR); -+ *p++ = X_3_8_5_6_5_5(X000, X11110001, sM, X001000, sN, X00000); -+ goto done; -+ } -+ case ARM64in_FPCR: { -+ Bool toFPCR = i->ARM64in.FPCR.toFPCR; -+ UInt iReg = iregNo(i->ARM64in.FPCR.iReg); -+ if (toFPCR) { -+ /* 0xD51B44 000 Rt MSR fpcr, rT */ -+ *p++ = 0xD51B4400 | (iReg & 0x1F); -+ goto done; -+ } -+ goto bad; // FPCR -> iReg case currently ATC -+ } -+ case ARM64in_VBinV: { -+ /* 31 23 20 15 9 4 -+ 010 01110 11 1 m 100001 n d ADD Vd.2d, Vn.2d, Vm.2d -+ 010 01110 10 1 m 100001 n d ADD Vd.4s, Vn.4s, Vm.4s -+ 010 01110 01 1 m 100001 n d ADD Vd.8h, Vn.8h, Vm.8h -+ 010 01110 00 1 m 100001 n d ADD Vd.16b, Vn.16b, Vm.16b -+ -+ 011 01110 11 1 m 100001 n d SUB Vd.2d, Vn.2d, Vm.2d -+ 011 01110 10 1 m 100001 n d SUB Vd.4s, Vn.4s, Vm.4s -+ 011 01110 01 1 m 100001 n d SUB Vd.8h, Vn.8h, Vm.8h -+ 011 01110 00 1 m 100001 n d SUB Vd.16b, Vn.16b, Vm.16b -+ -+ 010 01110 10 1 m 100111 n d MUL Vd.4s, Vn.4s, Vm.4s -+ 010 01110 01 1 m 100111 n d MUL Vd.8h, Vn.8h, Vm.8h -+ 010 01110 00 1 m 100111 n d MUL Vd.16b, Vn.16b, Vm.16b -+ -+ 010 01110 01 1 m 110101 n d FADD Vd.2d, Vn.2d, Vm.2d -+ 010 01110 00 1 m 110101 n d FADD Vd.4s, Vn.4s, Vm.4s -+ 010 01110 11 1 m 110101 n d FSUB Vd.2d, Vn.2d, Vm.2d -+ 010 01110 10 1 m 110101 n d FSUB Vd.4s, Vn.4s, Vm.4s -+ -+ 011 01110 01 1 m 110111 n d FMUL Vd.2d, Vn.2d, Vm.2d -+ 011 01110 00 1 m 110111 n d FMUL Vd.4s, Vn.4s, Vm.4s -+ 011 01110 01 1 m 111111 n d FDIV Vd.2d, Vn.2d, Vm.2d -+ 011 01110 00 1 m 111111 n d FDIV Vd.4s, Vn.4s, Vm.4s -+ -+ 011 01110 10 1 m 011001 n d UMAX Vd.4s, Vn.4s, Vm.4s -+ 011 01110 01 1 m 011001 n d UMAX Vd.8h, Vn.8h, Vm.8h -+ 011 01110 00 1 m 011001 n d UMAX Vd.16b, Vn.16b, Vm.16b -+ -+ 011 01110 10 1 m 011011 n d UMIN Vd.4s, Vn.4s, Vm.4s -+ 011 01110 01 1 m 011011 n d UMIN Vd.8h, Vn.8h, Vm.8h -+ 011 01110 00 1 m 011011 n d UMIN Vd.16b, Vn.16b, Vm.16b -+ -+ 010 01110 10 1 m 011001 n d SMAX Vd.4s, Vn.4s, Vm.4s -+ 010 01110 01 1 m 011001 n d SMAX Vd.8h, Vn.8h, Vm.8h -+ 010 01110 00 1 m 011001 n d SMAX Vd.16b, Vn.16b, Vm.16b -+ -+ 010 01110 10 1 m 011011 n d SMIN Vd.4s, Vn.4s, Vm.4s -+ 010 01110 01 1 m 011011 n d SMIN Vd.8h, Vn.8h, Vm.8h -+ 010 01110 00 1 m 011011 n d SMIN Vd.16b, Vn.16b, Vm.16b -+ -+ 010 01110 00 1 m 000111 n d AND Vd, Vn, Vm -+ 010 01110 10 1 m 000111 n d ORR Vd, Vn, Vm -+ 011 01110 00 1 m 000111 n d EOR Vd, Vn, Vm -+ -+ 011 01110 11 1 m 100011 n d CMEQ Vd.2d, Vn.2d, Vm.2d -+ 011 01110 10 1 m 100011 n d CMEQ Vd.4s, Vn.4s, Vm.4s -+ 011 01110 01 1 m 100011 n d CMEQ Vd.8h, Vn.8h, Vm.8h -+ 011 01110 00 1 m 100011 n d CMEQ Vd.16b, Vn.16b, Vm.16b -+ -+ 011 01110 11 1 m 001101 n d CMHI Vd.2d, Vn.2d, Vm.2d -+ 011 01110 10 1 m 001101 n d CMHI Vd.4s, Vn.4s, Vm.4s -+ 011 01110 01 1 m 001101 n d CMHI Vd.8h, Vn.8h, Vm.8h -+ 011 01110 00 1 m 001101 n d CMHI Vd.16b, Vn.16b, Vm.16b -+ -+ 010 01110 11 1 m 001101 n d CMGT Vd.2d, Vn.2d, Vm.2d -+ 010 01110 10 1 m 001101 n d CMGT Vd.4s, Vn.4s, Vm.4s -+ 010 01110 01 1 m 001101 n d CMGT Vd.8h, Vn.8h, Vm.8h -+ 010 01110 00 1 m 001101 n d CMGT Vd.16b, Vn.16b, Vm.16b -+ -+ 010 01110 01 1 m 111001 n d FCMEQ Vd.2d, Vn.2d, Vm.2d -+ 010 01110 00 1 m 111001 n d FCMEQ Vd.4s, Vn.4s, Vm.4s -+ -+ 011 01110 01 1 m 111001 n d FCMGE Vd.2d, Vn.2d, Vm.2d -+ 011 01110 00 1 m 111001 n d FCMGE Vd.4s, Vn.4s, Vm.4s -+ -+ 011 01110 11 1 m 111001 n d FCMGT Vd.2d, Vn.2d, Vm.2d -+ 011 01110 10 1 m 111001 n d FCMGT Vd.4s, Vn.4s, Vm.4s -+ -+ 010 01110 00 0 m 000000 n d TBL Vd.16b, {Vn.16b}, Vm.16b -+ -+ */ -+ UInt vD = qregNo(i->ARM64in.VBinV.dst); -+ UInt vN = qregNo(i->ARM64in.VBinV.argL); -+ UInt vM = qregNo(i->ARM64in.VBinV.argR); -+ switch (i->ARM64in.VBinV.op) { -+ case ARM64vecb_ADD64x2: -+ *p++ = X_3_8_5_6_5_5(X010, X01110111, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_ADD32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_ADD16x8: -+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_ADD8x16: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_SUB64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110111, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_SUB32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_SUB16x8: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_SUB8x16: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X100001, vN, vD); -+ break; -+ case ARM64vecb_MUL32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X100111, vN, vD); -+ break; -+ case ARM64vecb_MUL16x8: -+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X100111, vN, vD); -+ break; -+ case ARM64vecb_MUL8x16: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X100111, vN, vD); -+ break; -+ case ARM64vecb_FADD64x2: -+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X110101, vN, vD); -+ break; -+ case ARM64vecb_FADD32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X110101, vN, vD); -+ break; -+ case ARM64vecb_FSUB64x2: -+ *p++ = X_3_8_5_6_5_5(X010, X01110111, vM, X110101, vN, vD); -+ break; -+ case ARM64vecb_FSUB32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X110101, vN, vD); -+ break; -+ case ARM64vecb_FMUL64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X110111, vN, vD); -+ break; -+ case ARM64vecb_FMUL32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X110111, vN, vD); -+ break; -+ case ARM64vecb_FDIV64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X111111, vN, vD); -+ break; -+ case ARM64vecb_FDIV32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X111111, vN, vD); -+ break; -+ -+ case ARM64vecb_UMAX32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X011001, vN, vD); -+ break; -+ case ARM64vecb_UMAX16x8: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X011001, vN, vD); -+ break; -+ case ARM64vecb_UMAX8x16: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X011001, vN, vD); -+ break; -+ -+ case ARM64vecb_UMIN32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X011011, vN, vD); -+ break; -+ case ARM64vecb_UMIN16x8: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X011011, vN, vD); -+ break; -+ case ARM64vecb_UMIN8x16: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X011011, vN, vD); -+ break; -+ -+ case ARM64vecb_SMAX32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X011001, vN, vD); -+ break; -+ case ARM64vecb_SMAX16x8: -+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X011001, vN, vD); -+ break; -+ case ARM64vecb_SMAX8x16: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X011001, vN, vD); -+ break; -+ -+ case ARM64vecb_SMIN32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X011011, vN, vD); -+ break; -+ case ARM64vecb_SMIN16x8: -+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X011011, vN, vD); -+ break; -+ case ARM64vecb_SMIN8x16: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X011011, vN, vD); -+ break; -+ -+ case ARM64vecb_AND: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X000111, vN, vD); -+ break; -+ case ARM64vecb_ORR: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X000111, vN, vD); -+ break; -+ case ARM64vecb_XOR: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X000111, vN, vD); -+ break; -+ -+ case ARM64vecb_CMEQ64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110111, vM, X100011, vN, vD); -+ break; -+ case ARM64vecb_CMEQ32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X100011, vN, vD); -+ break; -+ case ARM64vecb_CMEQ16x8: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X100011, vN, vD); -+ break; -+ case ARM64vecb_CMEQ8x16: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X100011, vN, vD); -+ break; -+ -+ case ARM64vecb_CMHI64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110111, vM, X001101, vN, vD); -+ break; -+ case ARM64vecb_CMHI32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X001101, vN, vD); -+ break; -+ case ARM64vecb_CMHI16x8: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X001101, vN, vD); -+ break; -+ case ARM64vecb_CMHI8x16: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X001101, vN, vD); -+ break; -+ -+ case ARM64vecb_CMGT64x2: -+ *p++ = X_3_8_5_6_5_5(X010, X01110111, vM, X001101, vN, vD); -+ break; -+ case ARM64vecb_CMGT32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X001101, vN, vD); -+ break; -+ case ARM64vecb_CMGT16x8: -+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X001101, vN, vD); -+ break; -+ case ARM64vecb_CMGT8x16: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X001101, vN, vD); -+ break; -+ -+ case ARM64vecb_FCMEQ64x2: -+ *p++ = X_3_8_5_6_5_5(X010, X01110011, vM, X111001, vN, vD); -+ break; -+ case ARM64vecb_FCMEQ32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110001, vM, X111001, vN, vD); -+ break; -+ -+ case ARM64vecb_FCMGE64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X111001, vN, vD); -+ break; -+ case ARM64vecb_FCMGE32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X111001, vN, vD); -+ break; -+ -+ case ARM64vecb_FCMGT64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110111, vM, X111001, vN, vD); -+ break; -+ case ARM64vecb_FCMGT32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110101, vM, X111001, vN, vD); -+ break; -+ -+ case ARM64vecb_TBL1: -+ *p++ = X_3_8_5_6_5_5(X010, X01110000, vM, X000000, vN, vD); -+ break; -+ -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_VUnaryV: { -+ /* 31 23 20 15 9 4 -+ 010 01110 11 1 00000 111110 n d FABS Vd.2d, Vn.2d -+ 010 01110 10 1 00000 111110 n d FABS Vd.4s, Vn.4s -+ 011 01110 11 1 00000 111110 n d FNEG Vd.2d, Vn.2d -+ 011 01110 10 1 00000 111110 n d FNEG Vd.4s, Vn.4s -+ 011 01110 00 1 00000 010110 n d NOT Vd.16b, Vn.16b -+ */ -+ UInt vD = qregNo(i->ARM64in.VUnaryV.dst); -+ UInt vN = qregNo(i->ARM64in.VUnaryV.arg); -+ switch (i->ARM64in.VUnaryV.op) { -+ case ARM64vecu_FABS64x2: -+ *p++ = X_3_8_5_6_5_5(X010, X01110111, X00000, X111110, vN, vD); -+ break; -+ case ARM64vecu_FABS32x4: -+ *p++ = X_3_8_5_6_5_5(X010, X01110101, X00000, X111110, vN, vD); -+ break; -+ case ARM64vecu_FNEG64x2: -+ *p++ = X_3_8_5_6_5_5(X011, X01110111, X00000, X111110, vN, vD); -+ break; -+ case ARM64vecu_FNEG32x4: -+ *p++ = X_3_8_5_6_5_5(X011, X01110101, X00000, X111110, vN, vD); -+ break; -+ case ARM64vecu_NOT: -+ *p++ = X_3_8_5_6_5_5(X011, X01110001, X00000, X010110, vN, vD); -+ break; -+ default: -+ goto bad; -+ } -+ goto done; -+ } -+ case ARM64in_VNarrowV: { -+ /* 31 23 21 15 9 4 -+ 000 01110 00 1,00001 001010 n d XTN Vd.8b, Vn.8h -+ 000 01110 01 1,00001 001010 n d XTN Vd.4h, Vn.4s -+ 000 01110 10 1,00001 001010 n d XTN Vd.2s, Vn.2d -+ */ -+ UInt vD = qregNo(i->ARM64in.VNarrowV.dst); -+ UInt vN = qregNo(i->ARM64in.VNarrowV.src); -+ UInt dszBlg2 = i->ARM64in.VNarrowV.dszBlg2; -+ vassert(dszBlg2 >= 0 && dszBlg2 <= 2); -+ *p++ = X_3_8_5_6_5_5(X000, X01110001 | (dszBlg2 << 1), -+ X00001, X001010, vN, vD); -+ goto done; -+ } -+ case ARM64in_VShiftImmV: { -+ /* -+ 0q1 011110 immh immb 000001 n d USHR Vd.T, Vn.T, #sh -+ 0q0 011110 immh immb 000001 n d SSHR Vd.T, Vn.T, #sh -+ where immh:immb -+ = case T of -+ 2d | sh in 1..63 -> let xxxxxx = 64-sh in 1xxx:xxx -+ 4s | sh in 1..31 -> let xxxxx = 32-sh in 01xx:xxx -+ 8h | sh in 1..15 -> let xxxx = 16-sh in 001x:xxx -+ 16b | sh in 1..7 -> let xxx = 8-sh in 0001:xxx -+ -+ 0q0 011110 immh immb 010101 n d SHL Vd.T, Vn.T, #sh -+ where immh:immb -+ = case T of -+ 2d | sh in 1..63 -> let xxxxxx = sh in 1xxx:xxx -+ 4s | sh in 1..31 -> let xxxxx = sh in 01xx:xxx -+ 8h | sh in 1..15 -> let xxxx = sh in 001x:xxx -+ 16b | sh in 1..7 -> let xxx = sh in 0001:xxx -+ */ -+ UInt vD = qregNo(i->ARM64in.VShiftImmV.dst); -+ UInt vN = qregNo(i->ARM64in.VShiftImmV.src); -+ UInt sh = i->ARM64in.VShiftImmV.amt; -+ ARM64VecShiftOp op = i->ARM64in.VShiftImmV.op; -+ Bool syned = False; -+ switch (op) { -+ /* 64x2 cases */ -+ case ARM64vecsh_SSHR64x2: syned = True; -+ case ARM64vecsh_USHR64x2: /* fallthrough */ -+ if (sh >= 1 && sh <= 63) { -+ UInt xxxxxx = 64-sh; -+ *p++ = X_3_6_7_6_5_5(syned ? X010 : X011, X011110, -+ X1000000 | xxxxxx, X000001, vN, vD); -+ goto done; -+ } -+ break; -+ case ARM64vecsh_SHL64x2: -+ if (sh >= 1 && sh <= 63) { -+ UInt xxxxxx = sh; -+ *p++ = X_3_6_7_6_5_5(X010, X011110, -+ X1000000 | xxxxxx, X010101, vN, vD); -+ goto done; -+ } -+ break; -+ /* 32x4 cases */ -+ case ARM64vecsh_SSHR32x4: syned = True; -+ case ARM64vecsh_USHR32x4: /* fallthrough */ -+ if (sh >= 1 && sh <= 31) { -+ UInt xxxxx = 32-sh; -+ *p++ = X_3_6_7_6_5_5(syned ? X010 : X011, X011110, -+ X0100000 | xxxxx, X000001, vN, vD); -+ goto done; -+ } -+ break; -+ case ARM64vecsh_SHL32x4: -+ if (sh >= 1 && sh <= 31) { -+ UInt xxxxx = sh; -+ *p++ = X_3_6_7_6_5_5(X010, X011110, -+ X0100000 | xxxxx, X010101, vN, vD); -+ goto done; -+ } -+ break; -+ /* 16x8 cases */ -+ case ARM64vecsh_SSHR16x8: syned = True; -+ case ARM64vecsh_USHR16x8: /* fallthrough */ -+ if (sh >= 1 && sh <= 15) { -+ UInt xxxx = 16-sh; -+ *p++ = X_3_6_7_6_5_5(syned ? X010 : X011, X011110, -+ X0010000 | xxxx, X000001, vN, vD); -+ goto done; -+ } -+ break; -+ case ARM64vecsh_SHL16x8: -+ if (sh >= 1 && sh <= 15) { -+ UInt xxxx = sh; -+ *p++ = X_3_6_7_6_5_5(X010, X011110, -+ X0010000 | xxxx, X010101, vN, vD); -+ goto done; -+ } -+ break; -+ -+ -+ /* 8x16 cases */ -+ case ARM64vecsh_SSHR8x16: syned = True; -+ case ARM64vecsh_USHR8x16: /* fallthrough */ -+ if (sh >= 1 && sh <= 7) { -+ UInt xxx = 8-sh; -+ *p++ = X_3_6_7_6_5_5(syned ? X010 : X011, X011110, -+ X0001000 | xxx, X000001, vN, vD); -+ goto done; -+ } -+ break; -+ case ARM64vecsh_SHL8x16: -+ if (sh >= 1 && sh <= 7) { -+ UInt xxx = sh; -+ *p++ = X_3_6_7_6_5_5(X010, X011110, -+ X0001000 | xxx, X010101, vN, vD); -+ goto done; -+ } -+ break; -+ -+ default: -+ break; -+ } -+ goto bad; -+ } -+//ZZ case ARMin_VAluS: { -+//ZZ UInt dN = fregNo(i->ARMin.VAluS.argL); -+//ZZ UInt dD = fregNo(i->ARMin.VAluS.dst); -+//ZZ UInt dM = fregNo(i->ARMin.VAluS.argR); -+//ZZ UInt bN = dN & 1; -+//ZZ UInt bD = dD & 1; -+//ZZ UInt bM = dM & 1; -+//ZZ UInt pqrs = X1111; /* undefined */ -+//ZZ switch (i->ARMin.VAluS.op) { -+//ZZ case ARMvfp_ADD: pqrs = X0110; break; -+//ZZ case ARMvfp_SUB: pqrs = X0111; break; -+//ZZ case ARMvfp_MUL: pqrs = X0100; break; -+//ZZ case ARMvfp_DIV: pqrs = X1000; break; -+//ZZ default: goto bad; -+//ZZ } -+//ZZ vassert(pqrs != X1111); -+//ZZ UInt bP = (pqrs >> 3) & 1; -+//ZZ UInt bQ = (pqrs >> 2) & 1; -+//ZZ UInt bR = (pqrs >> 1) & 1; -+//ZZ UInt bS = (pqrs >> 0) & 1; -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, BITS4(bP,bD,bQ,bR), -+//ZZ (dN >> 1), (dD >> 1), -+//ZZ X1010, BITS4(bN,bS,bM,0), (dM >> 1)); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VUnaryS: { -+//ZZ UInt fD = fregNo(i->ARMin.VUnaryS.dst); -+//ZZ UInt fM = fregNo(i->ARMin.VUnaryS.src); -+//ZZ UInt insn = 0; -+//ZZ switch (i->ARMin.VUnaryS.op) { -+//ZZ case ARMvfpu_COPY: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000, -+//ZZ (fD >> 1), X1010, BITS4(0,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ case ARMvfpu_ABS: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0000, -+//ZZ (fD >> 1), X1010, BITS4(1,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ case ARMvfpu_NEG: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001, -+//ZZ (fD >> 1), X1010, BITS4(0,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ case ARMvfpu_SQRT: -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(fD & 1),1,1), X0001, -+//ZZ (fD >> 1), X1010, BITS4(1,1,(fM & 1),0), -+//ZZ (fM >> 1)); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VCMovD: { -+//ZZ UInt cc = (UInt)i->ARMin.VCMovD.cond; -+//ZZ UInt dD = dregNo(i->ARMin.VCMovD.dst); -+//ZZ UInt dM = dregNo(i->ARMin.VCMovD.src); -+//ZZ vassert(cc < 16 && cc != ARMcc_AL); -+//ZZ UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VCMovS: { -+//ZZ UInt cc = (UInt)i->ARMin.VCMovS.cond; -+//ZZ UInt fD = fregNo(i->ARMin.VCMovS.dst); -+//ZZ UInt fM = fregNo(i->ARMin.VCMovS.src); -+//ZZ vassert(cc < 16 && cc != ARMcc_AL); -+//ZZ UInt insn = XXXXXXXX(cc, X1110, BITS4(1,(fD & 1),1,1), -+//ZZ X0000,(fD >> 1),X1010, -+//ZZ BITS4(0,1,(fM & 1),0), (fM >> 1)); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VXferD: { -+//ZZ UInt dD = dregNo(i->ARMin.VXferD.dD); -+//ZZ UInt rHi = iregNo(i->ARMin.VXferD.rHi); -+//ZZ UInt rLo = iregNo(i->ARMin.VXferD.rLo); -+//ZZ /* vmov dD, rLo, rHi is -+//ZZ E C 4 rHi rLo B (0,0,dD[4],1) dD[3:0] -+//ZZ vmov rLo, rHi, dD is -+//ZZ E C 5 rHi rLo B (0,0,dD[4],1) dD[3:0] -+//ZZ */ -+//ZZ UInt insn -+//ZZ = XXXXXXXX(0xE, 0xC, i->ARMin.VXferD.toD ? 4 : 5, -+//ZZ rHi, rLo, 0xB, -+//ZZ BITS4(0,0, ((dD >> 4) & 1), 1), (dD & 0xF)); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VXferS: { -+//ZZ UInt fD = fregNo(i->ARMin.VXferS.fD); -+//ZZ UInt rLo = iregNo(i->ARMin.VXferS.rLo); -+//ZZ /* vmov fD, rLo is -+//ZZ E E 0 fD[4:1] rLo A (fD[0],0,0,1) 0 -+//ZZ vmov rLo, fD is -+//ZZ E E 1 fD[4:1] rLo A (fD[0],0,0,1) 0 -+//ZZ */ -+//ZZ UInt insn -+//ZZ = XXXXXXXX(0xE, 0xE, i->ARMin.VXferS.toS ? 0 : 1, -+//ZZ (fD >> 1) & 0xF, rLo, 0xA, -+//ZZ BITS4((fD & 1),0,0,1), 0); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_VCvtID: { -+//ZZ Bool iToD = i->ARMin.VCvtID.iToD; -+//ZZ Bool syned = i->ARMin.VCvtID.syned; -+//ZZ if (iToD && syned) { -+//ZZ // FSITOD: I32S-in-freg to F64-in-dreg -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, -+//ZZ X1011, BITS4(1,1,(regF & 1),0), -+//ZZ (regF >> 1) & 0xF); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ if (iToD && (!syned)) { -+//ZZ // FUITOD: I32U-in-freg to F64-in-dreg -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, X1011, X1000, regD, -+//ZZ X1011, BITS4(0,1,(regF & 1),0), -+//ZZ (regF >> 1) & 0xF); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ if ((!iToD) && syned) { -+//ZZ // FTOSID: F64-in-dreg to I32S-in-freg -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1), -+//ZZ X1101, (regF >> 1) & 0xF, -+//ZZ X1011, X0100, regD); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ if ((!iToD) && (!syned)) { -+//ZZ // FTOUID: F64-in-dreg to I32U-in-freg -+//ZZ UInt regD = dregNo(i->ARMin.VCvtID.src); -+//ZZ UInt regF = fregNo(i->ARMin.VCvtID.dst); -+//ZZ UInt insn = XXXXXXXX(0xE, X1110, BITS4(1,(regF & 1),1,1), -+//ZZ X1100, (regF >> 1) & 0xF, -+//ZZ X1011, X0100, regD); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ /*UNREACHED*/ -+//ZZ vassert(0); -+//ZZ } -+//ZZ case ARMin_NLdStD: { -+//ZZ UInt regD = dregNo(i->ARMin.NLdStD.dD); -+//ZZ UInt regN, regM; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt bL = i->ARMin.NLdStD.isLoad ? 1 : 0; -+//ZZ UInt insn; -+//ZZ vassert(hregClass(i->ARMin.NLdStD.dD) == HRcFlt64); -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NLdStD.amode->tag == ARMamN_RR) { -+//ZZ regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rN); -+//ZZ regM = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rM); -+//ZZ } else { -+//ZZ regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.R.rN); -+//ZZ regM = 15; -+//ZZ } -+//ZZ insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), -+//ZZ regN, regD, X0111, X1000, regM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NUnaryS: { -+//ZZ UInt Q = i->ARMin.NUnaryS.Q ? 1 : 0; -+//ZZ UInt regD, D; -+//ZZ UInt regM, M; -+//ZZ UInt size = i->ARMin.NUnaryS.size; -+//ZZ UInt insn; -+//ZZ UInt opc, opc1, opc2; -+//ZZ switch (i->ARMin.NUnaryS.op) { -+//ZZ case ARMneon_VDUP: -+//ZZ if (i->ARMin.NUnaryS.size >= 16) -+//ZZ goto bad; -+//ZZ if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Reg) -+//ZZ goto bad; -+//ZZ if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ regD = (hregClass(i->ARMin.NUnaryS.dst->reg) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) -+//ZZ : dregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ regM = (hregClass(i->ARMin.NUnaryS.src->reg) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) -+//ZZ : dregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ D = regD >> 4; -+//ZZ M = regM >> 4; -+//ZZ regD &= 0xf; -+//ZZ regM &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), -+//ZZ (i->ARMin.NUnaryS.size & 0xf), regD, -+//ZZ X1100, BITS4(0,Q,M,0), regM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ case ARMneon_SETELEM: -+//ZZ regD = Q ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) : -+//ZZ dregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ regM = iregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ M = regM >> 4; -+//ZZ D = regD >> 4; -+//ZZ regM &= 0xF; -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ switch (size) { -+//ZZ case 0: -+//ZZ if (i->ARMin.NUnaryS.dst->index > 7) -+//ZZ goto bad; -+//ZZ opc = X1000 | i->ARMin.NUnaryS.dst->index; -+//ZZ break; -+//ZZ case 1: -+//ZZ if (i->ARMin.NUnaryS.dst->index > 3) -+//ZZ goto bad; -+//ZZ opc = X0001 | (i->ARMin.NUnaryS.dst->index << 1); -+//ZZ break; -+//ZZ case 2: -+//ZZ if (i->ARMin.NUnaryS.dst->index > 1) -+//ZZ goto bad; -+//ZZ opc = X0000 | (i->ARMin.NUnaryS.dst->index << 2); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ opc1 = (opc >> 2) & 3; -+//ZZ opc2 = opc & 3; -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0), -+//ZZ regD, regM, X1011, -+//ZZ BITS4(D,(opc2 >> 1),(opc2 & 1),1), X0000); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ case ARMneon_GETELEMU: -+//ZZ regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) : -+//ZZ dregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ regD = iregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ M = regM >> 4; -+//ZZ D = regD >> 4; -+//ZZ regM &= 0xF; -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ switch (size) { -+//ZZ case 0: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 7) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 8; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 7) -+//ZZ goto bad; -+//ZZ opc = X1000 | i->ARMin.NUnaryS.src->index; -+//ZZ break; -+//ZZ case 1: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 3) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 4; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 3) -+//ZZ goto bad; -+//ZZ opc = X0001 | (i->ARMin.NUnaryS.src->index << 1); -+//ZZ break; -+//ZZ case 2: -+//ZZ goto bad; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ opc1 = (opc >> 2) & 3; -+//ZZ opc2 = opc & 3; -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1), -+//ZZ regM, regD, X1011, -+//ZZ BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ case ARMneon_GETELEMS: -+//ZZ regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) : -+//ZZ dregNo(i->ARMin.NUnaryS.src->reg); -+//ZZ regD = iregNo(i->ARMin.NUnaryS.dst->reg); -+//ZZ M = regM >> 4; -+//ZZ D = regD >> 4; -+//ZZ regM &= 0xF; -+//ZZ regD &= 0xF; -+//ZZ if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar) -+//ZZ goto bad; -+//ZZ switch (size) { -+//ZZ case 0: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 7) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 8; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 7) -+//ZZ goto bad; -+//ZZ opc = X1000 | i->ARMin.NUnaryS.src->index; -+//ZZ break; -+//ZZ case 1: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 3) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 4; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 3) -+//ZZ goto bad; -+//ZZ opc = X0001 | (i->ARMin.NUnaryS.src->index << 1); -+//ZZ break; -+//ZZ case 2: -+//ZZ if (Q && i->ARMin.NUnaryS.src->index > 1) { -+//ZZ regM++; -+//ZZ i->ARMin.NUnaryS.src->index -= 2; -+//ZZ } -+//ZZ if (i->ARMin.NUnaryS.src->index > 1) -+//ZZ goto bad; -+//ZZ opc = X0000 | (i->ARMin.NUnaryS.src->index << 2); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ opc1 = (opc >> 2) & 3; -+//ZZ opc2 = opc & 3; -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1), -+//ZZ regM, regD, X1011, -+//ZZ BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ } -+//ZZ case ARMin_NUnary: { -+//ZZ UInt Q = i->ARMin.NUnary.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NUnary.dst) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnary.dst) << 1) -+//ZZ : dregNo(i->ARMin.NUnary.dst); -+//ZZ UInt regM, M; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt sz1 = i->ARMin.NUnary.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NUnary.size & 1; -+//ZZ UInt sz = i->ARMin.NUnary.size; -+//ZZ UInt insn; -+//ZZ UInt F = 0; /* TODO: floating point EQZ ??? */ -+//ZZ if (i->ARMin.NUnary.op != ARMneon_DUP) { -+//ZZ regM = (hregClass(i->ARMin.NUnary.src) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NUnary.src) << 1) -+//ZZ : dregNo(i->ARMin.NUnary.src); -+//ZZ M = regM >> 4; -+//ZZ } else { -+//ZZ regM = iregNo(i->ARMin.NUnary.src); -+//ZZ M = regM >> 4; -+//ZZ } -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ switch (i->ARMin.NUnary.op) { -+//ZZ case ARMneon_COPY: /* VMOV reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regM, regD, X0001, -+//ZZ BITS4(M,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYN: /* VMOVN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(0,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYQNSS: /* VQMOVN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(1,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYQNUS: /* VQMOVUN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(0,1,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYQNUU: /* VQMOVN regD, regQ */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0010, BITS4(1,1,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYLS: /* VMOVL regQ, regD */ -+//ZZ if (sz >= 3) -+//ZZ goto bad; -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0), -+//ZZ BITS4((sz == 0) ? 1 : 0,0,0,0), -+//ZZ regD, X1010, BITS4(0,0,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_COPYLU: /* VMOVL regQ, regD */ -+//ZZ if (sz >= 3) -+//ZZ goto bad; -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0), -+//ZZ BITS4((sz == 0) ? 1 : 0,0,0,0), -+//ZZ regD, X1010, BITS4(0,0,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_NOT: /* VMVN reg, reg*/ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_EQZ: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1), -+//ZZ regD, BITS4(0,F,0,1), BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_CNT: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_CLZ: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0100, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_CLS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0100, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_ABS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1), -+//ZZ regD, X0011, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_DUP: -+//ZZ sz1 = i->ARMin.NUnary.size == 0 ? 1 : 0; -+//ZZ sz2 = i->ARMin.NUnary.size == 1 ? 1 : 0; -+//ZZ vassert(sz1 + sz2 < 2); -+//ZZ insn = XXXXXXXX(0xE, X1110, BITS4(1, sz1, Q, 0), regD, regM, -+//ZZ X1011, BITS4(D,0,sz2,1), X0000); -+//ZZ break; -+//ZZ case ARMneon_REV16: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, BITS4(0,0,0,1), BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_REV32: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, BITS4(0,0,0,0), BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_REV64: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, BITS4(0,0,0,0), BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_PADDLU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0010, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_PADDLS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0), -+//ZZ regD, X0010, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHLNUU: -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ (1 << 3) | (D << 2) | ((sz >> 4) & 3), -+//ZZ sz & 0xf, regD, X0111, -+//ZZ BITS4(sz >> 6,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHLNSS: -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ (1 << 3) | (D << 2) | ((sz >> 4) & 3), -+//ZZ sz & 0xf, regD, X0111, -+//ZZ BITS4(sz >> 6,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHLNUS: -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ (1 << 3) | (D << 2) | ((sz >> 4) & 3), -+//ZZ sz & 0xf, regD, X0110, -+//ZZ BITS4(sz >> 6,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoS: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTStoF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTUtoF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoFixedU: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1111, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFtoFixedS: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1111, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFixedUtoF: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0011, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1110, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTFixedStoF: -+//ZZ sz1 = (sz >> 5) & 1; -+//ZZ sz2 = (sz >> 4) & 1; -+//ZZ sz &= 0xf; -+//ZZ insn = XXXXXXXX(0xF, X0010, -+//ZZ BITS4(1,D,sz1,sz2), sz, regD, X1110, -+//ZZ BITS4(0,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTF32toF16: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0110, -+//ZZ BITS4(0,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCVTF16toF32: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0111, -+//ZZ BITS4(0,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRECIP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRECIPF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VABSFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111, -+//ZZ BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRSQRTEFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRSQRTE: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VNEGF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111, -+//ZZ BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NDual: { -+//ZZ UInt Q = i->ARMin.NDual.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NDual.arg1) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NDual.arg1) << 1) -+//ZZ : dregNo(i->ARMin.NDual.arg1); -+//ZZ UInt regM = (hregClass(i->ARMin.NDual.arg2) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NDual.arg2) << 1) -+//ZZ : dregNo(i->ARMin.NDual.arg2); -+//ZZ UInt D = regD >> 4; -+//ZZ UInt M = regM >> 4; -+//ZZ UInt sz1 = i->ARMin.NDual.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NDual.size & 1; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ switch (i->ARMin.NDual.op) { -+//ZZ case ARMneon_TRN: /* VTRN reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0000, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_ZIP: /* VZIP reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0001, BITS4(1,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_UZP: /* VUZP reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0), -+//ZZ regD, X0001, BITS4(0,Q,M,0), regM); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NBinary: { -+//ZZ UInt Q = i->ARMin.NBinary.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NBinary.dst) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NBinary.dst) << 1) -+//ZZ : dregNo(i->ARMin.NBinary.dst); -+//ZZ UInt regN = (hregClass(i->ARMin.NBinary.argL) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NBinary.argL) << 1) -+//ZZ : dregNo(i->ARMin.NBinary.argL); -+//ZZ UInt regM = (hregClass(i->ARMin.NBinary.argR) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NBinary.argR) << 1) -+//ZZ : dregNo(i->ARMin.NBinary.argR); -+//ZZ UInt sz1 = i->ARMin.NBinary.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NBinary.size & 1; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt N = regN >> 4; -+//ZZ UInt M = regM >> 4; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ regN &= 0xF; -+//ZZ switch (i->ARMin.NBinary.op) { -+//ZZ case ARMneon_VAND: /* VAND reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X0001, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VORR: /* VORR reg, reg, reg*/ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X0001, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VXOR: /* VEOR reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X0001, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VADD: /* VADD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1000, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VSUB: /* VSUB reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1000, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMINU: /* VMIN.Uxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMINS: /* VMIN.Sxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMAXU: /* VMAX.Uxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMAXS: /* VMAX.Sxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0110, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRHADDS: /* VRHADD.Sxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0001, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRHADDU: /* VRHADD.Uxx reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0001, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQADDU: /* VQADD unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0000, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQADDS: /* VQADD signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0000, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSUBU: /* VQSUB unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSUBS: /* VQSUB signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGTU: /* VCGT unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGTS: /* VCGT signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGEU: /* VCGE unsigned reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGES: /* VCGE signed reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0011, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCEQ: /* VCEQ reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1000, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VEXT: /* VEXT.8 reg, reg, #imm4*/ -+//ZZ if (i->ARMin.NBinary.size >= 16) -+//ZZ goto bad; -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,1,1), regN, regD, -+//ZZ i->ARMin.NBinary.size & 0xf, BITS4(N,Q,M,0), -+//ZZ regM); -+//ZZ break; -+//ZZ case ARMneon_VMUL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1001, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULLU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1100, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULLS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1100, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1001, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VMULLP: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1110, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQDMULH: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQRDMULH: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1011, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQDMULL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD, -+//ZZ X1101, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VTBL: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), regN, regD, -+//ZZ X1000, BITS4(N,0,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPADD: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1011, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VPADDFP: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMINU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMINS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMAXU: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMAXS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X1010, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VADDFP: /* VADD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VSUBFP: /* VADD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VABDFP: /* VABD reg, reg, reg */ -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, -+//ZZ X1101, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMINF: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VMAXF: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMINF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VPMAXF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, -+//ZZ X1111, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRECPS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1111, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGTF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, X1110, -+//ZZ BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCGEF: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X1110, -+//ZZ BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VCEQF: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1110, -+//ZZ BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VRSQRTS: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X1111, -+//ZZ BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NShift: { -+//ZZ UInt Q = i->ARMin.NShift.Q ? 1 : 0; -+//ZZ UInt regD = (hregClass(i->ARMin.NShift.dst) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NShift.dst) << 1) -+//ZZ : dregNo(i->ARMin.NShift.dst); -+//ZZ UInt regM = (hregClass(i->ARMin.NShift.argL) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NShift.argL) << 1) -+//ZZ : dregNo(i->ARMin.NShift.argL); -+//ZZ UInt regN = (hregClass(i->ARMin.NShift.argR) == HRcVec128) -+//ZZ ? (qregNo(i->ARMin.NShift.argR) << 1) -+//ZZ : dregNo(i->ARMin.NShift.argR); -+//ZZ UInt sz1 = i->ARMin.NShift.size >> 1; -+//ZZ UInt sz2 = i->ARMin.NShift.size & 1; -+//ZZ UInt D = regD >> 4; -+//ZZ UInt N = regN >> 4; -+//ZZ UInt M = regM >> 4; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ regM &= 0xF; -+//ZZ regN &= 0xF; -+//ZZ switch (i->ARMin.NShift.op) { -+//ZZ case ARMneon_VSHL: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VSAL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,0), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSHL: -+//ZZ insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ case ARMneon_VQSAL: -+//ZZ insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD, -+//ZZ X0100, BITS4(N,Q,M,1), regM); -+//ZZ break; -+//ZZ default: -+//ZZ goto bad; -+//ZZ } -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NShl64: { -+//ZZ HReg regDreg = i->ARMin.NShl64.dst; -+//ZZ HReg regMreg = i->ARMin.NShl64.src; -+//ZZ UInt amt = i->ARMin.NShl64.amt; -+//ZZ vassert(amt >= 1 && amt <= 63); -+//ZZ vassert(hregClass(regDreg) == HRcFlt64); -+//ZZ vassert(hregClass(regMreg) == HRcFlt64); -+//ZZ UInt regD = dregNo(regDreg); -+//ZZ UInt regM = dregNo(regMreg); -+//ZZ UInt D = (regD >> 4) & 1; -+//ZZ UInt Vd = regD & 0xF; -+//ZZ UInt L = 1; -+//ZZ UInt Q = 0; /* always 64-bit */ -+//ZZ UInt M = (regM >> 4) & 1; -+//ZZ UInt Vm = regM & 0xF; -+//ZZ UInt insn = XXXXXXXX(X1111,X0010, BITS4(1,D,(amt>>5)&1,(amt>>4)&1), -+//ZZ amt & 0xF, Vd, X0101, BITS4(L,Q,M,1), Vm); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+ case ARM64in_VImmQ: { -+ UInt rQ = qregNo(i->ARM64in.VImmQ.rQ); -+ UShort imm = i->ARM64in.VImmQ.imm; -+ if (imm == 0x0000) { -+ /* movi rQ.4s, #0x0 == 0x4F 0x00 0x04 000 rQ */ -+ vassert(rQ < 32); -+ *p++ = 0x4F000400 | rQ; -+ goto done; -+ } -+ if (imm == 0x0001) { -+ /* movi rD, #0xFF == 0x2F 0x00 0xE4 001 rD */ -+ vassert(rQ < 32); -+ *p++ = 0x2F00E420 | rQ; -+ goto done; -+ } -+ if (imm == 0x0003) { -+ /* movi rD, #0xFFFF == 0x2F 0x00 0xE4 011 rD */ -+ vassert(rQ < 32); -+ *p++ = 0x2F00E460 | rQ; -+ goto done; -+ } -+ if (imm == 0x000F) { -+ /* movi rD, #0xFFFFFFFF == 0x2F 0x00 0xE5 111 rD */ -+ vassert(rQ < 32); -+ *p++ = 0x2F00E5E0 | rQ; -+ goto done; -+ } -+ if (imm == 0x00FF) { -+ /* movi rD, #0xFFFFFFFFFFFFFFFF == 0x2F 0x07 0xE7 111 rD */ -+ vassert(rQ < 32); -+ *p++ = 0x2F07E7E0 | rQ; -+ goto done; -+ } -+ goto bad; /* no other handled cases right now */ -+ } -+ -+ case ARM64in_VDfromX: { -+ /* INS Vd.D[0], rX -+ 0100 1110 0000 1000 0001 11 nn dd INS Vd.D[0], Xn -+ This isn't wonderful, in the sense that the upper half of -+ the vector register stays unchanged and thus the insn is -+ data dependent on its output register. */ -+ UInt dd = dregNo(i->ARM64in.VDfromX.rD); -+ UInt xx = iregNo(i->ARM64in.VDfromX.rX); -+ vassert(xx < 31); -+ *p++ = 0x4E081C00 | X_2_6_2_12_5_5(0,0,0,0,xx,dd); -+ goto done; -+ } -+ -+ case ARM64in_VQfromXX: { -+ /* What we really generate is a two insn sequence: -+ INS Vd.D[0], Xlo; INS Vd.D[1], Xhi -+ 0100 1110 0000 1000 0001 11 nn dd INS Vd.D[0], Xn -+ 0100 1110 0001 1000 0001 11 nn dd INS Vd.D[1], Xn -+ */ -+ UInt qq = qregNo(i->ARM64in.VQfromXX.rQ); -+ UInt xhi = iregNo(i->ARM64in.VQfromXX.rXhi); -+ UInt xlo = iregNo(i->ARM64in.VQfromXX.rXlo); -+ vassert(xhi < 31 && xlo < 31); -+ *p++ = 0x4E081C00 | X_2_6_2_12_5_5(0,0,0,0,xlo,qq); -+ *p++ = 0x4E181C00 | X_2_6_2_12_5_5(0,0,0,0,xhi,qq); -+ goto done; -+ } -+ -+ case ARM64in_VXfromQ: { -+ /* 010 0111 0000 01000 001111 nn dd UMOV Xd, Vn.D[0] -+ 010 0111 0000 11000 001111 nn dd UMOV Xd, Vn.D[1] -+ */ -+ UInt dd = iregNo(i->ARM64in.VXfromQ.rX); -+ UInt nn = qregNo(i->ARM64in.VXfromQ.rQ); -+ UInt laneNo = i->ARM64in.VXfromQ.laneNo; -+ vassert(dd < 31); -+ vassert(laneNo < 2); -+ *p++ = X_3_8_5_6_5_5(X010, X01110000, -+ laneNo == 1 ? X11000 : X01000, X001111, nn, dd); -+ goto done; -+ } -+ -+ case ARM64in_VMov: { -+ /* 000 11110 00 10000 00 10000 n d FMOV Sd, Sn -+ 000 11110 01 10000 00 10000 n d FMOV Dd, Dn -+ 010 01110 10 1 n 0 00111 n d MOV Vd.16b, Vn.16b -+ */ -+ HReg rD = i->ARM64in.VMov.dst; -+ HReg rN = i->ARM64in.VMov.src; -+ switch (i->ARM64in.VMov.szB) { -+ case 8: { -+ UInt dd = dregNo(rD); -+ UInt nn = dregNo(rN); -+ *p++ = X_3_8_5_6_5_5(X000, X11110011, X00000, X010000, nn, dd); -+ goto done; -+ } -+ default: -+ break; -+ } -+ goto bad; -+ } -+//ZZ case ARMin_NeonImm: { -+//ZZ UInt Q = (hregClass(i->ARMin.NeonImm.dst) == HRcVec128) ? 1 : 0; -+//ZZ UInt regD = Q ? (qregNo(i->ARMin.NeonImm.dst) << 1) : -+//ZZ dregNo(i->ARMin.NeonImm.dst); -+//ZZ UInt D = regD >> 4; -+//ZZ UInt imm = i->ARMin.NeonImm.imm->imm8; -+//ZZ UInt tp = i->ARMin.NeonImm.imm->type; -+//ZZ UInt j = imm >> 7; -+//ZZ UInt imm3 = (imm >> 4) & 0x7; -+//ZZ UInt imm4 = imm & 0xF; -+//ZZ UInt cmode, op; -+//ZZ UInt insn; -+//ZZ regD &= 0xF; -+//ZZ if (tp == 9) -+//ZZ op = 1; -+//ZZ else -+//ZZ op = 0; -+//ZZ switch (tp) { -+//ZZ case 0: -+//ZZ case 1: -+//ZZ case 2: -+//ZZ case 3: -+//ZZ case 4: -+//ZZ case 5: -+//ZZ cmode = tp << 1; -+//ZZ break; -+//ZZ case 9: -+//ZZ case 6: -+//ZZ cmode = 14; -+//ZZ break; -+//ZZ case 7: -+//ZZ cmode = 12; -+//ZZ break; -+//ZZ case 8: -+//ZZ cmode = 13; -+//ZZ break; -+//ZZ case 10: -+//ZZ cmode = 15; -+//ZZ break; -+//ZZ default: -+//ZZ vpanic("ARMin_NeonImm"); -+//ZZ -+//ZZ } -+//ZZ insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD, -+//ZZ cmode, BITS4(0,Q,op,1), imm4); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_NCMovQ: { -+//ZZ UInt cc = (UInt)i->ARMin.NCMovQ.cond; -+//ZZ UInt qM = qregNo(i->ARMin.NCMovQ.src) << 1; -+//ZZ UInt qD = qregNo(i->ARMin.NCMovQ.dst) << 1; -+//ZZ UInt vM = qM & 0xF; -+//ZZ UInt vD = qD & 0xF; -+//ZZ UInt M = (qM >> 4) & 1; -+//ZZ UInt D = (qD >> 4) & 1; -+//ZZ vassert(cc < 16 && cc != ARMcc_AL && cc != ARMcc_NV); -+//ZZ /* b!cc here+8: !cc A00 0000 */ -+//ZZ UInt insn = XXXXXXXX(cc ^ 1, 0xA, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0); -+//ZZ *p++ = insn; -+//ZZ /* vmov qD, qM */ -+//ZZ insn = XXXXXXXX(0xF, 0x2, BITS4(0,D,1,0), -+//ZZ vM, vD, BITS4(0,0,0,1), BITS4(M,1,M,1), vM); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+//ZZ case ARMin_Add32: { -+//ZZ UInt regD = iregNo(i->ARMin.Add32.rD); -+//ZZ UInt regN = iregNo(i->ARMin.Add32.rN); -+//ZZ UInt imm32 = i->ARMin.Add32.imm32; -+//ZZ vassert(regD != regN); -+//ZZ /* MOV regD, imm32 */ -+//ZZ p = imm32_to_iregNo((UInt *)p, regD, imm32); -+//ZZ /* ADD regD, regN, regD */ -+//ZZ UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD); -+//ZZ *p++ = insn; -+//ZZ goto done; -+//ZZ } -+ -+ case ARM64in_EvCheck: { -+ /* The sequence is fixed (canned) except for the two amodes -+ supplied by the insn. These don't change the length, though. -+ We generate: -+ ldr w9, [x21 + #8] 8 == offsetof(host_EvC_COUNTER) -+ subs w9, w9, #1 -+ str w9, [x21 + #8] 8 == offsetof(host_EvC_COUNTER) -+ bpl nofail -+ ldr x9, [x21 + #0] 0 == offsetof(host_EvC_FAILADDR) -+ br x9 -+ nofail: -+ */ -+ UInt* p0 = p; -+ p = do_load_or_store32(p, True/*isLoad*/, /*w*/9, -+ i->ARM64in.EvCheck.amCounter); -+ *p++ = 0x71000529; /* subs w9, w9, #1 */ -+ p = do_load_or_store32(p, False/*!isLoad*/, /*w*/9, -+ i->ARM64in.EvCheck.amCounter); -+ *p++ = 0x54000065; /* bpl nofail */ -+ p = do_load_or_store64(p, True/*isLoad*/, /*x*/9, -+ i->ARM64in.EvCheck.amFailAddr); -+ *p++ = 0xD61F0120; /* br x9 */ -+ /* nofail: */ -+ -+ /* Crosscheck */ -+ vassert(evCheckSzB_ARM64() == (UChar*)p - (UChar*)p0); -+ goto done; -+ } -+ -+//ZZ case ARMin_ProfInc: { -+//ZZ /* We generate: -+//ZZ (ctrP is unknown now, so use 0x65556555 in the -+//ZZ expectation that a later call to LibVEX_patchProfCtr -+//ZZ will be used to fill in the immediate fields once the -+//ZZ right value is known.) -+//ZZ movw r12, lo16(0x65556555) -+//ZZ movt r12, lo16(0x65556555) -+//ZZ ldr r11, [r12] -+//ZZ adds r11, r11, #1 -+//ZZ str r11, [r12] -+//ZZ ldr r11, [r12+4] -+//ZZ adc r11, r11, #0 -+//ZZ str r11, [r12+4] -+//ZZ */ -+//ZZ p = imm32_to_iregNo_EXACTLY2(p, /*r*/12, 0x65556555); -+//ZZ *p++ = 0xE59CB000; -+//ZZ *p++ = 0xE29BB001; -+//ZZ *p++ = 0xE58CB000; -+//ZZ *p++ = 0xE59CB004; -+//ZZ *p++ = 0xE2ABB000; -+//ZZ *p++ = 0xE58CB004; -+//ZZ /* Tell the caller .. */ -+//ZZ vassert(!(*is_profInc)); -+//ZZ *is_profInc = True; -+//ZZ goto done; -+//ZZ } -+ -+ /* ... */ -+ default: -+ goto bad; -+ } -+ -+ bad: -+ ppARM64Instr(i); -+ vpanic("emit_ARM64Instr"); -+ /*NOTREACHED*/ -+ -+ done: -+ vassert(((UChar*)p) - &buf[0] <= 36); -+ return ((UChar*)p) - &buf[0]; -+} -+ -+ -+/* How big is an event check? See case for ARM64in_EvCheck in -+ emit_ARM64Instr just above. That crosschecks what this returns, so -+ we can tell if we're inconsistent. */ -+Int evCheckSzB_ARM64 ( void ) -+{ -+ return 24; -+} -+ -+ -+/* NB: what goes on here has to be very closely coordinated with the -+ emitInstr case for XDirect, above. */ -+VexInvalRange chainXDirect_ARM64 ( void* place_to_chain, -+ void* disp_cp_chain_me_EXPECTED, -+ void* place_to_jump_to ) -+{ -+ /* What we're expecting to see is: -+ movw x9, disp_cp_chain_me_to_EXPECTED[15:0] -+ movk x9, disp_cp_chain_me_to_EXPECTED[31:15], lsl 16 -+ movk x9, disp_cp_chain_me_to_EXPECTED[47:32], lsl 32 -+ movk x9, disp_cp_chain_me_to_EXPECTED[63:48], lsl 48 -+ blr x9 -+ viz -+ <16 bytes generated by imm64_to_iregNo_EXACTLY4> -+ D6 3F 01 20 -+ */ -+ UInt* p = (UInt*)place_to_chain; -+ vassert(0 == (3 & (HWord)p)); -+ vassert(is_imm64_to_iregNo_EXACTLY4( -+ p, /*x*/9, Ptr_to_ULong(disp_cp_chain_me_EXPECTED))); -+ vassert(p[4] == 0xD63F0120); -+ -+ /* And what we want to change it to is: -+ movw x9, place_to_jump_to[15:0] -+ movk x9, place_to_jump_to[31:15], lsl 16 -+ movk x9, place_to_jump_to[47:32], lsl 32 -+ movk x9, place_to_jump_to[63:48], lsl 48 -+ br x9 -+ viz -+ <16 bytes generated by imm64_to_iregNo_EXACTLY4> -+ D6 1F 01 20 -+ -+ The replacement has the same length as the original. -+ */ -+ (void)imm64_to_iregNo_EXACTLY4( -+ p, /*x*/9, Ptr_to_ULong(place_to_jump_to)); -+ p[4] = 0xD61F0120; -+ -+ VexInvalRange vir = {(HWord)p, 20}; -+ return vir; -+} -+ -+ -+/* NB: what goes on here has to be very closely coordinated with the -+ emitInstr case for XDirect, above. */ -+VexInvalRange unchainXDirect_ARM64 ( void* place_to_unchain, -+ void* place_to_jump_to_EXPECTED, -+ void* disp_cp_chain_me ) -+{ -+ /* What we're expecting to see is: -+ movw x9, place_to_jump_to_EXPECTED[15:0] -+ movk x9, place_to_jump_to_EXPECTED[31:15], lsl 16 -+ movk x9, place_to_jump_to_EXPECTED[47:32], lsl 32 -+ movk x9, place_to_jump_to_EXPECTED[63:48], lsl 48 -+ br x9 -+ viz -+ <16 bytes generated by imm64_to_iregNo_EXACTLY4> -+ D6 1F 01 20 -+ */ -+ UInt* p = (UInt*)place_to_unchain; -+ vassert(0 == (3 & (HWord)p)); -+ vassert(is_imm64_to_iregNo_EXACTLY4( -+ p, /*x*/9, Ptr_to_ULong(place_to_jump_to_EXPECTED))); -+ vassert(p[4] == 0xD61F0120); -+ -+ /* And what we want to change it to is: -+ movw x9, disp_cp_chain_me_to[15:0] -+ movk x9, disp_cp_chain_me_to[31:15], lsl 16 -+ movk x9, disp_cp_chain_me_to[47:32], lsl 32 -+ movk x9, disp_cp_chain_me_to[63:48], lsl 48 -+ blr x9 -+ viz -+ <16 bytes generated by imm64_to_iregNo_EXACTLY4> -+ D6 3F 01 20 -+ */ -+ (void)imm64_to_iregNo_EXACTLY4( -+ p, /*x*/9, Ptr_to_ULong(disp_cp_chain_me)); -+ p[4] = 0xD63F0120; -+ -+ VexInvalRange vir = {(HWord)p, 20}; -+ return vir; -+} -+ -+ -+//ZZ /* Patch the counter address into a profile inc point, as previously -+//ZZ created by the ARMin_ProfInc case for emit_ARMInstr. */ -+//ZZ VexInvalRange patchProfInc_ARM ( void* place_to_patch, -+//ZZ ULong* location_of_counter ) -+//ZZ { -+//ZZ vassert(sizeof(ULong*) == 4); -+//ZZ UInt* p = (UInt*)place_to_patch; -+//ZZ vassert(0 == (3 & (HWord)p)); -+//ZZ vassert(is_imm32_to_iregNo_EXACTLY2(p, /*r*/12, 0x65556555)); -+//ZZ vassert(p[2] == 0xE59CB000); -+//ZZ vassert(p[3] == 0xE29BB001); -+//ZZ vassert(p[4] == 0xE58CB000); -+//ZZ vassert(p[5] == 0xE59CB004); -+//ZZ vassert(p[6] == 0xE2ABB000); -+//ZZ vassert(p[7] == 0xE58CB004); -+//ZZ imm32_to_iregNo_EXACTLY2(p, /*r*/12, -+//ZZ (UInt)Ptr_to_ULong(location_of_counter)); -+//ZZ VexInvalRange vir = {(HWord)p, 8}; -+//ZZ return vir; -+//ZZ } -+//ZZ -+//ZZ -+//ZZ #undef BITS4 -+//ZZ #undef X0000 -+//ZZ #undef X0001 -+//ZZ #undef X0010 -+//ZZ #undef X0011 -+//ZZ #undef X0100 -+//ZZ #undef X0101 -+//ZZ #undef X0110 -+//ZZ #undef X0111 -+//ZZ #undef X1000 -+//ZZ #undef X1001 -+//ZZ #undef X1010 -+//ZZ #undef X1011 -+//ZZ #undef X1100 -+//ZZ #undef X1101 -+//ZZ #undef X1110 -+//ZZ #undef X1111 -+//ZZ #undef XXXXX___ -+//ZZ #undef XXXXXX__ -+//ZZ #undef XXX___XX -+//ZZ #undef XXXXX__X -+//ZZ #undef XXXXXXXX -+//ZZ #undef XX______ -+ -+/*---------------------------------------------------------------*/ -+/*--- end host_arm64_defs.c ---*/ -+/*---------------------------------------------------------------*/ -Index: priv/host_arm64_defs.h -=================================================================== ---- priv/host_arm64_defs.h (.../tags/VEX_3_9_0) (revision 0) -+++ priv/host_arm64_defs.h (.../trunk) (revision 2863) -@@ -0,0 +1,1148 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin host_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VEX_HOST_ARM64_DEFS_H -+#define __VEX_HOST_ARM64_DEFS_H -+ -+#include "libvex_basictypes.h" -+#include "libvex.h" // VexArch -+#include "host_generic_regs.h" // HReg -+ -+//ZZ extern UInt arm_hwcaps; -+ -+ -+/* --------- Registers. --------- */ -+ -+//ZZ /* The usual HReg abstraction. -+//ZZ There are 16 general purpose regs. -+//ZZ */ -+ -+extern void ppHRegARM64 ( HReg ); -+ -+extern HReg hregARM64_X0 ( void ); -+extern HReg hregARM64_X1 ( void ); -+extern HReg hregARM64_X2 ( void ); -+extern HReg hregARM64_X3 ( void ); -+extern HReg hregARM64_X4 ( void ); -+extern HReg hregARM64_X5 ( void ); -+extern HReg hregARM64_X6 ( void ); -+extern HReg hregARM64_X7 ( void ); -+//ZZ extern HReg hregARM_R8 ( void ); -+extern HReg hregARM64_X9 ( void ); -+extern HReg hregARM64_X10 ( void ); -+extern HReg hregARM64_X11 ( void ); -+extern HReg hregARM64_X12 ( void ); -+extern HReg hregARM64_X13 ( void ); -+extern HReg hregARM64_X14 ( void ); -+extern HReg hregARM64_X15 ( void ); -+extern HReg hregARM64_X21 ( void ); -+extern HReg hregARM64_X22 ( void ); -+extern HReg hregARM64_X23 ( void ); -+extern HReg hregARM64_X24 ( void ); -+extern HReg hregARM64_X25 ( void ); -+extern HReg hregARM64_X26 ( void ); -+extern HReg hregARM64_X27 ( void ); -+extern HReg hregARM64_X28 ( void ); -+extern HReg hregARM64_D8 ( void ); -+extern HReg hregARM64_D9 ( void ); -+extern HReg hregARM64_D10 ( void ); -+extern HReg hregARM64_D11 ( void ); -+extern HReg hregARM64_D12 ( void ); -+extern HReg hregARM64_D13 ( void ); -+extern HReg hregARM64_Q16 ( void ); -+extern HReg hregARM64_Q17 ( void ); -+extern HReg hregARM64_Q18 ( void ); -+ -+/* Number of registers used arg passing in function calls */ -+#define ARM64_N_ARGREGS 8 /* x0 .. x7 */ -+ -+ -+/* --------- Condition codes. --------- */ -+ -+typedef -+ enum { -+ ARM64cc_EQ = 0, /* equal : Z=1 */ -+ ARM64cc_NE = 1, /* not equal : Z=0 */ -+ -+ ARM64cc_CS = 2, /* >=u (higher or same) : C=1 */ -+ ARM64cc_CC = 3, /* u (higher) : C=1 && Z=0 */ -+ ARM64cc_LS = 9, /* <=u (lower or same) : !(C=1 && Z=0) */ -+ -+ ARM64cc_GE = 10, /* >=s (signed greater or equal) : N=V */ -+ ARM64cc_LT = 11, /* s (signed greater) : Z=0 && N=V */ -+ ARM64cc_LE = 13, /* <=s (signed less or equal) : !(Z=0 && N=V) */ -+ -+ ARM64cc_AL = 14, /* always (unconditional) */ -+ ARM64cc_NV = 15 /* in 64-bit mode also means "always" */ -+ } -+ ARM64CondCode; -+ -+ -+/* --------- Memory address expressions (amodes). --------- */ -+ -+typedef -+ enum { -+ ARM64am_RI9=10, /* reg + simm9 */ -+ ARM64am_RI12, /* reg + uimm12 * szB (iow, scaled by access size) */ -+ ARM64am_RR /* reg1 + reg2 */ -+ } -+ ARM64AModeTag; -+ -+typedef -+ struct { -+ ARM64AModeTag tag; -+ union { -+ struct { -+ HReg reg; -+ Int simm9; /* -256 .. +255 */ -+ } RI9; -+ struct { -+ HReg reg; -+ UInt uimm12; /* 0 .. 4095 */ -+ UChar szB; /* 1, 2, 4, 8 (16 ?) */ -+ } RI12; -+ struct { -+ HReg base; -+ HReg index; -+ } RR; -+ } ARM64am; -+ } -+ ARM64AMode; -+ -+extern ARM64AMode* ARM64AMode_RI9 ( HReg reg, Int simm9 ); -+extern ARM64AMode* ARM64AMode_RI12 ( HReg reg, Int uimm12, UChar szB ); -+extern ARM64AMode* ARM64AMode_RR ( HReg base, HReg index ); -+ -+ -+/* --------- Reg or uimm12 or (uimm12 << 12) operands --------- */ -+ -+typedef -+ enum { -+ ARM64riA_I12=20, /* uimm12 << 0 or 12 only */ -+ ARM64riA_R /* reg */ -+ } -+ ARM64RIATag; -+ -+typedef -+ struct { -+ ARM64RIATag tag; -+ union { -+ struct { -+ UShort imm12; /* 0 .. 4095 */ -+ UChar shift; /* 0 or 12 only */ -+ } I12; -+ struct { -+ HReg reg; -+ } R; -+ } ARM64riA; -+ } -+ ARM64RIA; -+ -+extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ); -+extern ARM64RIA* ARM64RIA_R ( HReg ); -+ -+ -+/* --------- Reg or "bitfield" (logic immediate) operands --------- */ -+ -+typedef -+ enum { -+ ARM64riL_I13=6, /* wierd-o bitfield immediate, 13 bits in total */ -+ ARM64riL_R /* reg */ -+ } -+ ARM64RILTag; -+ -+typedef -+ struct { -+ ARM64RILTag tag; -+ union { -+ struct { -+ UChar bitN; /* 0 .. 1 */ -+ UChar immR; /* 0 .. 63 */ -+ UChar immS; /* 0 .. 63 */ -+ } I13; -+ struct { -+ HReg reg; -+ } R; -+ } ARM64riL; -+ } -+ ARM64RIL; -+ -+extern ARM64RIL* ARM64RIL_I13 ( UChar bitN, UChar immR, UChar immS ); -+extern ARM64RIL* ARM64RIL_R ( HReg ); -+ -+ -+/* --------------- Reg or uimm6 operands --------------- */ -+ -+typedef -+ enum { -+ ARM64ri6_I6=30, /* uimm6, 1 .. 63 only */ -+ ARM64ri6_R /* reg */ -+ } -+ ARM64RI6Tag; -+ -+typedef -+ struct { -+ ARM64RI6Tag tag; -+ union { -+ struct { -+ UInt imm6; /* 1 .. 63 */ -+ } I6; -+ struct { -+ HReg reg; -+ } R; -+ } ARM64ri6; -+ } -+ ARM64RI6; -+ -+extern ARM64RI6* ARM64RI6_I6 ( UInt imm6 ); -+extern ARM64RI6* ARM64RI6_R ( HReg ); -+ -+ -+/* --------------------- Instructions --------------------- */ -+ -+typedef -+ enum { -+ ARM64lo_AND=40, -+ ARM64lo_OR, -+ ARM64lo_XOR -+ } -+ ARM64LogicOp; -+ -+typedef -+ enum { -+ ARM64sh_SHL=50, -+ ARM64sh_SHR, -+ ARM64sh_SAR -+ } -+ ARM64ShiftOp; -+ -+typedef -+ enum { -+ ARM64un_NEG=60, -+ ARM64un_NOT, -+ ARM64un_CLZ, -+ } -+ ARM64UnaryOp; -+ -+typedef -+ enum { -+ ARM64mul_PLAIN=70, /* lo64(64 * 64) */ -+ ARM64mul_ZX, /* hi64(64 *u 64) */ -+ ARM64mul_SX /* hi64(64 *s 64) */ -+ } -+ ARM64MulOp; -+ -+typedef -+ /* These characterise an integer-FP conversion, but don't imply any -+ particular direction. */ -+ enum { -+ ARM64cvt_F32_I32S=80, -+ ARM64cvt_F64_I32S, -+ ARM64cvt_F32_I64S, -+ ARM64cvt_F64_I64S, -+ ARM64cvt_F32_I32U, -+ ARM64cvt_F64_I32U, -+ ARM64cvt_F32_I64U, -+ ARM64cvt_F64_I64U, -+ ARM64cvt_INVALID -+ } -+ ARM64CvtOp; -+ -+typedef -+ enum { -+ ARM64fpb_ADD=100, -+ ARM64fpb_SUB, -+ ARM64fpb_MUL, -+ ARM64fpb_DIV, -+ ARM64fpb_INVALID -+ } -+ ARM64FpBinOp; -+ -+typedef -+ enum { -+ ARM64fpu_NEG=110, -+ ARM64fpu_ABS, -+ ARM64fpu_SQRT, -+ ARM64fpu_RINT, -+ ARM64fpu_INVALID -+ } -+ ARM64FpUnaryOp; -+ -+typedef -+ enum { -+ ARM64vecb_ADD64x2=120, -+ ARM64vecb_ADD32x4, -+ ARM64vecb_ADD16x8, -+ ARM64vecb_ADD8x16, -+ ARM64vecb_SUB64x2, -+ ARM64vecb_SUB32x4, -+ ARM64vecb_SUB16x8, -+ ARM64vecb_SUB8x16, -+ ARM64vecb_MUL32x4, -+ ARM64vecb_MUL16x8, -+ ARM64vecb_MUL8x16, -+ ARM64vecb_FADD64x2, -+ ARM64vecb_FSUB64x2, -+ ARM64vecb_FMUL64x2, -+ ARM64vecb_FDIV64x2, -+ ARM64vecb_FADD32x4, -+ ARM64vecb_FSUB32x4, -+ ARM64vecb_FMUL32x4, -+ ARM64vecb_FDIV32x4, -+ ARM64vecb_UMAX32x4, -+ ARM64vecb_UMAX16x8, -+ ARM64vecb_UMAX8x16, -+ ARM64vecb_UMIN32x4, -+ ARM64vecb_UMIN16x8, -+ ARM64vecb_UMIN8x16, -+ ARM64vecb_SMAX32x4, -+ ARM64vecb_SMAX16x8, -+ ARM64vecb_SMAX8x16, -+ ARM64vecb_SMIN32x4, -+ ARM64vecb_SMIN16x8, -+ ARM64vecb_SMIN8x16, -+ ARM64vecb_AND, -+ ARM64vecb_ORR, -+ ARM64vecb_XOR, -+ ARM64vecb_CMEQ64x2, -+ ARM64vecb_CMEQ32x4, -+ ARM64vecb_CMEQ16x8, -+ ARM64vecb_CMEQ8x16, -+ ARM64vecb_CMHI64x2, /* >u */ -+ ARM64vecb_CMHI32x4, -+ ARM64vecb_CMHI16x8, -+ ARM64vecb_CMHI8x16, -+ ARM64vecb_CMGT64x2, /* >s */ -+ ARM64vecb_CMGT32x4, -+ ARM64vecb_CMGT16x8, -+ ARM64vecb_CMGT8x16, -+ ARM64vecb_FCMEQ64x2, -+ ARM64vecb_FCMEQ32x4, -+ ARM64vecb_FCMGE64x2, -+ ARM64vecb_FCMGE32x4, -+ ARM64vecb_FCMGT64x2, -+ ARM64vecb_FCMGT32x4, -+ ARM64vecb_TBL1, -+ ARM64vecb_INVALID -+ } -+ ARM64VecBinOp; -+ -+typedef -+ enum { -+ ARM64vecu_FNEG64x2=300, -+ ARM64vecu_FNEG32x4, -+ ARM64vecu_FABS64x2, -+ ARM64vecu_FABS32x4, -+ ARM64vecu_NOT, -+ ARM64vecu_INVALID -+ } -+ ARM64VecUnaryOp; -+ -+typedef -+ enum { -+ ARM64vecsh_USHR64x2=350, -+ ARM64vecsh_USHR32x4, -+ ARM64vecsh_USHR16x8, -+ ARM64vecsh_USHR8x16, -+ ARM64vecsh_SSHR64x2, -+ ARM64vecsh_SSHR32x4, -+ ARM64vecsh_SSHR16x8, -+ ARM64vecsh_SSHR8x16, -+ ARM64vecsh_SHL64x2, -+ ARM64vecsh_SHL32x4, -+ ARM64vecsh_SHL16x8, -+ ARM64vecsh_SHL8x16, -+ ARM64vecsh_INVALID -+ } -+ ARM64VecShiftOp; -+ -+//ZZ extern const HChar* showARMVfpUnaryOp ( ARMVfpUnaryOp op ); -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_VAND=90, -+//ZZ ARMneon_VORR, -+//ZZ ARMneon_VXOR, -+//ZZ ARMneon_VADD, -+//ZZ ARMneon_VADDFP, -+//ZZ ARMneon_VRHADDS, -+//ZZ ARMneon_VRHADDU, -+//ZZ ARMneon_VPADDFP, -+//ZZ ARMneon_VABDFP, -+//ZZ ARMneon_VSUB, -+//ZZ ARMneon_VSUBFP, -+//ZZ ARMneon_VMAXU, -+//ZZ ARMneon_VMAXS, -+//ZZ ARMneon_VMAXF, -+//ZZ ARMneon_VMINU, -+//ZZ ARMneon_VMINS, -+//ZZ ARMneon_VMINF, -+//ZZ ARMneon_VQADDU, -+//ZZ ARMneon_VQADDS, -+//ZZ ARMneon_VQSUBU, -+//ZZ ARMneon_VQSUBS, -+//ZZ ARMneon_VCGTU, -+//ZZ ARMneon_VCGTS, -+//ZZ ARMneon_VCGEU, -+//ZZ ARMneon_VCGES, -+//ZZ ARMneon_VCGTF, -+//ZZ ARMneon_VCGEF, -+//ZZ ARMneon_VCEQ, -+//ZZ ARMneon_VCEQF, -+//ZZ ARMneon_VEXT, -+//ZZ ARMneon_VMUL, -+//ZZ ARMneon_VMULFP, -+//ZZ ARMneon_VMULLU, -+//ZZ ARMneon_VMULLS, -+//ZZ ARMneon_VMULP, -+//ZZ ARMneon_VMULLP, -+//ZZ ARMneon_VQDMULH, -+//ZZ ARMneon_VQRDMULH, -+//ZZ ARMneon_VPADD, -+//ZZ ARMneon_VPMINU, -+//ZZ ARMneon_VPMINS, -+//ZZ ARMneon_VPMINF, -+//ZZ ARMneon_VPMAXU, -+//ZZ ARMneon_VPMAXS, -+//ZZ ARMneon_VPMAXF, -+//ZZ ARMneon_VTBL, -+//ZZ ARMneon_VQDMULL, -+//ZZ ARMneon_VRECPS, -+//ZZ ARMneon_VRSQRTS, -+//ZZ /* ... */ -+//ZZ } -+//ZZ ARMNeonBinOp; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_VSHL=150, -+//ZZ ARMneon_VSAL, /* Yah, not SAR but SAL */ -+//ZZ ARMneon_VQSHL, -+//ZZ ARMneon_VQSAL -+//ZZ } -+//ZZ ARMNeonShiftOp; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_COPY=160, -+//ZZ ARMneon_COPYLU, -+//ZZ ARMneon_COPYLS, -+//ZZ ARMneon_COPYN, -+//ZZ ARMneon_COPYQNSS, -+//ZZ ARMneon_COPYQNUS, -+//ZZ ARMneon_COPYQNUU, -+//ZZ ARMneon_NOT, -+//ZZ ARMneon_EQZ, -+//ZZ ARMneon_DUP, -+//ZZ ARMneon_PADDLS, -+//ZZ ARMneon_PADDLU, -+//ZZ ARMneon_CNT, -+//ZZ ARMneon_CLZ, -+//ZZ ARMneon_CLS, -+//ZZ ARMneon_VCVTxFPxINT, -+//ZZ ARMneon_VQSHLNSS, -+//ZZ ARMneon_VQSHLNUU, -+//ZZ ARMneon_VQSHLNUS, -+//ZZ ARMneon_VCVTFtoU, -+//ZZ ARMneon_VCVTFtoS, -+//ZZ ARMneon_VCVTUtoF, -+//ZZ ARMneon_VCVTStoF, -+//ZZ ARMneon_VCVTFtoFixedU, -+//ZZ ARMneon_VCVTFtoFixedS, -+//ZZ ARMneon_VCVTFixedUtoF, -+//ZZ ARMneon_VCVTFixedStoF, -+//ZZ ARMneon_VCVTF16toF32, -+//ZZ ARMneon_VCVTF32toF16, -+//ZZ ARMneon_REV16, -+//ZZ ARMneon_REV32, -+//ZZ ARMneon_REV64, -+//ZZ ARMneon_ABS, -+//ZZ ARMneon_VNEGF, -+//ZZ ARMneon_VRECIP, -+//ZZ ARMneon_VRECIPF, -+//ZZ ARMneon_VABSFP, -+//ZZ ARMneon_VRSQRTEFP, -+//ZZ ARMneon_VRSQRTE -+//ZZ /* ... */ -+//ZZ } -+//ZZ ARMNeonUnOp; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_SETELEM=200, -+//ZZ ARMneon_GETELEMU, -+//ZZ ARMneon_GETELEMS, -+//ZZ ARMneon_VDUP, -+//ZZ } -+//ZZ ARMNeonUnOpS; -+//ZZ -+//ZZ typedef -+//ZZ enum { -+//ZZ ARMneon_TRN=210, -+//ZZ ARMneon_ZIP, -+//ZZ ARMneon_UZP -+//ZZ /* ... */ -+//ZZ } -+//ZZ ARMNeonDualOp; -+//ZZ -+//ZZ extern const HChar* showARMNeonBinOp ( ARMNeonBinOp op ); -+//ZZ extern const HChar* showARMNeonUnOp ( ARMNeonUnOp op ); -+//ZZ extern const HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ); -+//ZZ extern const HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ); -+//ZZ extern const HChar* showARMNeonDualOp ( ARMNeonDualOp op ); -+//ZZ extern const HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ); -+//ZZ extern const HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ); -+//ZZ extern const HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ); -+//ZZ extern const HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ); -+//ZZ extern const HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ); -+ -+typedef -+ enum { -+ /* baseline */ -+ ARM64in_Arith=1220, -+ ARM64in_Cmp, -+ ARM64in_Logic, -+ ARM64in_Test, -+ ARM64in_Shift, -+ ARM64in_Unary, -+ ARM64in_MovI, /* int reg-reg move */ -+ ARM64in_Imm64, -+ ARM64in_LdSt64, -+ ARM64in_LdSt32, /* w/ ZX loads */ -+ ARM64in_LdSt16, /* w/ ZX loads */ -+ ARM64in_LdSt8, /* w/ ZX loads */ -+ ARM64in_XDirect, /* direct transfer to GA */ -+ ARM64in_XIndir, /* indirect transfer to GA */ -+ ARM64in_XAssisted, /* assisted transfer to GA */ -+ ARM64in_CSel, -+ ARM64in_Call, -+ ARM64in_AddToSP, /* move SP by small, signed constant */ -+ ARM64in_FromSP, /* move SP to integer register */ -+ ARM64in_Mul, -+ ARM64in_LdrEX, -+ ARM64in_StrEX, -+ ARM64in_MFence, -+//ZZ ARMin_CLREX, -+ /* ARM64in_V*: scalar ops involving vector registers */ -+ ARM64in_VLdStS, /* 32-bit FP load/store, with imm offset */ -+ ARM64in_VLdStD, /* 64-bit FP load/store, with imm offset */ -+ ARM64in_VLdStQ, -+ ARM64in_VCvtI2F, -+ ARM64in_VCvtF2I, -+ ARM64in_VCvtSD, -+ ARM64in_VUnaryD, -+ ARM64in_VUnaryS, -+ ARM64in_VBinD, -+ ARM64in_VBinS, -+ ARM64in_VCmpD, -+ ARM64in_VCmpS, -+ ARM64in_FPCR, -+ /* ARM64in_V*V: vector ops on vector registers */ -+ ARM64in_VBinV, -+ ARM64in_VUnaryV, -+ ARM64in_VNarrowV, -+ ARM64in_VShiftImmV, -+//ZZ ARMin_VAluS, -+//ZZ ARMin_VCMovD, -+//ZZ ARMin_VCMovS, -+//ZZ ARMin_VXferD, -+//ZZ ARMin_VXferS, -+//ZZ ARMin_VCvtID, -+//ZZ /* Neon */ -+//ZZ ARMin_NLdStD, -+//ZZ ARMin_NUnary, -+//ZZ ARMin_NUnaryS, -+//ZZ ARMin_NDual, -+//ZZ ARMin_NBinary, -+//ZZ ARMin_NBinaryS, -+//ZZ ARMin_NShift, -+//ZZ ARMin_NShl64, // special case 64-bit shift of Dreg by immediate -+ ARM64in_VImmQ, -+ ARM64in_VDfromX, /* Move an Xreg to a Dreg */ -+ ARM64in_VQfromXX, /* Move 2 Xregs to a Qreg */ -+ ARM64in_VXfromQ, /* Move half a Qreg to an Xreg */ -+ ARM64in_VMov, /* vector reg-reg move, 16, 8 or 4 bytes */ -+ /* infrastructure */ -+ ARM64in_EvCheck, /* Event check */ -+//ZZ ARMin_ProfInc /* 64-bit profile counter increment */ -+ } -+ ARM64InstrTag; -+ -+/* Destinations are on the LEFT (first operand) */ -+ -+typedef -+ struct { -+ ARM64InstrTag tag; -+ union { -+ /* --- INTEGER INSTRUCTIONS --- */ -+ /* 64 bit ADD/SUB reg, reg or uimm12<<{0,12} */ -+ struct { -+ HReg dst; -+ HReg argL; -+ ARM64RIA* argR; -+ Bool isAdd; -+ } Arith; -+ /* 64 or 32 bit CMP reg, reg or aimm (SUB and set flags) */ -+ struct { -+ HReg argL; -+ ARM64RIA* argR; -+ Bool is64; -+ } Cmp; -+ /* 64 bit AND/OR/XOR reg, reg or bitfield-immediate */ -+ struct { -+ HReg dst; -+ HReg argL; -+ ARM64RIL* argR; -+ ARM64LogicOp op; -+ } Logic; -+ /* 64 bit TST reg, reg or bimm (AND and set flags) */ -+ struct { -+ HReg argL; -+ ARM64RIL* argR; -+ } Test; -+ /* 64 bit SHL/SHR/SAR, 2nd arg is reg or imm */ -+ struct { -+ HReg dst; -+ HReg argL; -+ ARM64RI6* argR; -+ ARM64ShiftOp op; -+ } Shift; -+ /* NOT/NEG/CLZ, 64 bit only */ -+ struct { -+ HReg dst; -+ HReg src; -+ ARM64UnaryOp op; -+ } Unary; -+ /* MOV dst, src -- reg-reg move for integer registers */ -+ struct { -+ HReg dst; -+ HReg src; -+ } MovI; -+ /* Pseudo-insn; make a 64-bit immediate */ -+ struct { -+ HReg dst; -+ ULong imm64; -+ } Imm64; -+ /* 64-bit load or store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt64; -+ /* zx-32-to-64-bit load, or 32-bit store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt32; -+ /* zx-16-to-64-bit load, or 16-bit store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt16; -+ /* zx-8-to-64-bit load, or 8-bit store */ -+ struct { -+ Bool isLoad; -+ HReg rD; -+ ARM64AMode* amode; -+ } LdSt8; -+ /* Update the guest PC value, then exit requesting to chain -+ to it. May be conditional. Urr, use of Addr64 implicitly -+ assumes that wordsize(guest) == wordsize(host). */ -+ struct { -+ Addr64 dstGA; /* next guest address */ -+ ARM64AMode* amPC; /* amode in guest state for PC */ -+ ARM64CondCode cond; /* can be ARM64cc_AL */ -+ Bool toFastEP; /* chain to the slow or fast point? */ -+ } XDirect; -+ /* Boring transfer to a guest address not known at JIT time. -+ Not chainable. May be conditional. */ -+ struct { -+ HReg dstGA; -+ ARM64AMode* amPC; -+ ARM64CondCode cond; /* can be ARM64cc_AL */ -+ } XIndir; -+ /* Assisted transfer to a guest address, most general case. -+ Not chainable. May be conditional. */ -+ struct { -+ HReg dstGA; -+ ARM64AMode* amPC; -+ ARM64CondCode cond; /* can be ARM64cc_AL */ -+ IRJumpKind jk; -+ } XAssisted; -+ /* CSEL: dst = if cond then argL else argR. cond may be anything. */ -+ struct { -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ ARM64CondCode cond; -+ } CSel; -+ /* Pseudo-insn. Call target (an absolute address), on given -+ condition (which could be ARM64cc_AL). */ -+ struct { -+ RetLoc rloc; /* where the return value will be */ -+ HWord target; -+ ARM64CondCode cond; -+ Int nArgRegs; /* # regs carrying args: 0 .. 8 */ -+ } Call; -+ /* move SP by small, signed constant */ -+ struct { -+ Int simm; /* needs to be 0 % 16 and in the range -4095 -+ .. 4095 inclusive */ -+ } AddToSP; -+ /* move SP to integer register */ -+ struct { -+ HReg dst; -+ } FromSP; -+ /* Integer multiply, with 3 variants: -+ (PLAIN) lo64(64 * 64) -+ (ZX) hi64(64 *u 64) -+ (SX) hi64(64 *s 64) -+ */ -+ struct { -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ ARM64MulOp op; -+ } Mul; -+ /* LDXR{,H,B} x2, [x4] */ -+ struct { -+ Int szB; /* 1, 2, 4 or 8 */ -+ } LdrEX; -+ /* STXR{,H,B} w0, x2, [x4] */ -+ struct { -+ Int szB; /* 1, 2, 4 or 8 */ -+ } StrEX; -+ /* Mem fence. An insn which fences all loads and stores as -+ much as possible before continuing. On ARM64 we emit the -+ sequence "dsb sy ; dmb sy ; isb sy", which is probably -+ total nuclear overkill, but better safe than sorry. */ -+ struct { -+ } MFence; -+//ZZ /* A CLREX instruction. */ -+//ZZ struct { -+//ZZ } CLREX; -+ /* --- INSTRUCTIONS INVOLVING VECTOR REGISTERS --- */ -+ /* 32-bit Fp load/store */ -+ struct { -+ Bool isLoad; -+ HReg sD; -+ HReg rN; -+ UInt uimm12; /* 0 .. 16380 inclusive, 0 % 4 */ -+ } VLdStS; -+ /* 64-bit Fp load/store */ -+ struct { -+ Bool isLoad; -+ HReg dD; -+ HReg rN; -+ UInt uimm12; /* 0 .. 32760 inclusive, 0 % 8 */ -+ } VLdStD; -+ /* 128-bit Vector load/store. */ -+ struct { -+ Bool isLoad; -+ HReg rQ; // data -+ HReg rN; // address -+ } VLdStQ; -+ /* Scalar conversion of int to float. */ -+ struct { -+ ARM64CvtOp how; -+ HReg rD; // dst, a D or S register -+ HReg rS; // src, a W or X register -+ } VCvtI2F; -+ /* Scalar conversion of float to int, w/ specified RM. */ -+ struct { -+ ARM64CvtOp how; -+ HReg rD; // dst, a W or X register -+ HReg rS; // src, a D or S register -+ UChar armRM; // ARM encoded RM: -+ // 00=nearest, 01=+inf, 10=-inf, 11=zero -+ } VCvtF2I; -+ /* Convert between 32-bit and 64-bit FP values (both -+ ways). (FCVT) */ -+ struct { -+ Bool sToD; /* True: F32->F64. False: F64->F32 */ -+ HReg dst; -+ HReg src; -+ } VCvtSD; -+ /* 64-bit FP unary */ -+ struct { -+ ARM64FpUnaryOp op; -+ HReg dst; -+ HReg src; -+ } VUnaryD; -+ /* 32-bit FP unary */ -+ struct { -+ ARM64FpUnaryOp op; -+ HReg dst; -+ HReg src; -+ } VUnaryS; -+ /* 64-bit FP binary arithmetic */ -+ struct { -+ ARM64FpBinOp op; -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ } VBinD; -+ /* 32-bit FP binary arithmetic */ -+ struct { -+ ARM64FpBinOp op; -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ } VBinS; -+ /* 64-bit FP compare */ -+ struct { -+ HReg argL; -+ HReg argR; -+ } VCmpD; -+ /* 32-bit FP compare */ -+ struct { -+ HReg argL; -+ HReg argR; -+ } VCmpS; -+ /* Move a 32-bit value to/from the FPCR */ -+ struct { -+ Bool toFPCR; -+ HReg iReg; -+ } FPCR; -+ /* binary vector operation on vector registers */ -+ struct { -+ ARM64VecBinOp op; -+ HReg dst; -+ HReg argL; -+ HReg argR; -+ } VBinV; -+ /* unary vector operation on vector registers */ -+ struct { -+ ARM64VecUnaryOp op; -+ HReg dst; -+ HReg arg; -+ } VUnaryV; -+ /* vector narrowing, Q -> Q. Result goes in the bottom half -+ of dst and the top half is zeroed out. Iow is XTN. */ -+ struct { -+ UInt dszBlg2; // 0: 16to8_x8 1: 32to16_x4 2: 64to32_x2 -+ HReg dst; // Q reg -+ HReg src; // Q reg -+ } VNarrowV; -+ /* Vector shift by immediate. |amt| needs to be > 0 and < -+ implied lane size of |op|. Zero shifts and out of range -+ shifts are not allowed. */ -+ struct { -+ ARM64VecShiftOp op; -+ HReg dst; -+ HReg src; -+ UInt amt; -+ } VShiftImmV; -+//ZZ /* 32-bit FP binary arithmetic */ -+//ZZ struct { -+//ZZ ARMVfpOp op; -+//ZZ HReg dst; -+//ZZ HReg argL; -+//ZZ HReg argR; -+//ZZ } VAluS; -+//ZZ /* 64-bit FP mov src to dst on the given condition, which may -+//ZZ not be ARMcc_AL. */ -+//ZZ struct { -+//ZZ ARMCondCode cond; -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ } VCMovD; -+//ZZ /* 32-bit FP mov src to dst on the given condition, which may -+//ZZ not be ARMcc_AL. */ -+//ZZ struct { -+//ZZ ARMCondCode cond; -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ } VCMovS; -+//ZZ /* Transfer a VFP D reg to/from two integer registers (VMOV) */ -+//ZZ struct { -+//ZZ Bool toD; -+//ZZ HReg dD; -+//ZZ HReg rHi; -+//ZZ HReg rLo; -+//ZZ } VXferD; -+//ZZ /* Transfer a VFP S reg to/from an integer register (VMOV) */ -+//ZZ struct { -+//ZZ Bool toS; -+//ZZ HReg fD; -+//ZZ HReg rLo; -+//ZZ } VXferS; -+//ZZ /* Convert between 32-bit ints and 64-bit FP values (both ways -+//ZZ and both signednesses). (FSITOD, FUITOD, FTOSID, FTOUID) */ -+//ZZ struct { -+//ZZ Bool iToD; /* True: I32->F64. False: F64->I32 */ -+//ZZ Bool syned; /* True: I32 is signed. False: I32 is unsigned */ -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ } VCvtID; -+//ZZ /* Neon data processing instruction: 3 registers of the same -+//ZZ length */ -+//ZZ struct { -+//ZZ ARMNeonBinOp op; -+//ZZ HReg dst; -+//ZZ HReg argL; -+//ZZ HReg argR; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NBinary; -+//ZZ struct { -+//ZZ ARMNeonBinOp op; -+//ZZ ARMNRS* dst; -+//ZZ ARMNRS* argL; -+//ZZ ARMNRS* argR; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NBinaryS; -+//ZZ struct { -+//ZZ ARMNeonShiftOp op; -+//ZZ HReg dst; -+//ZZ HReg argL; -+//ZZ HReg argR; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NShift; -+//ZZ struct { -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ UInt amt; /* 1..63 only */ -+//ZZ } NShl64; -+//ZZ struct { -+//ZZ Bool isLoad; -+//ZZ HReg dD; -+//ZZ ARMAModeN *amode; -+//ZZ } NLdStD -+//ZZ struct { -+//ZZ ARMNeonUnOpS op; -+//ZZ ARMNRS* dst; -+//ZZ ARMNRS* src; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NUnaryS; -+//ZZ struct { -+//ZZ ARMNeonUnOp op; -+//ZZ HReg dst; -+//ZZ HReg src; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NUnary; -+//ZZ /* Takes two arguments and modifies them both. */ -+//ZZ struct { -+//ZZ ARMNeonDualOp op; -+//ZZ HReg arg1; -+//ZZ HReg arg2; -+//ZZ UInt size; -+//ZZ Bool Q; -+//ZZ } NDual; -+ struct { -+ HReg rQ; -+ UShort imm; /* Same 1-bit-per-byte encoding as IR */ -+ } VImmQ; -+ struct { -+ HReg rD; -+ HReg rX; -+ } VDfromX; -+ struct { -+ HReg rQ; -+ HReg rXhi; -+ HReg rXlo; -+ } VQfromXX; -+ struct { -+ HReg rX; -+ HReg rQ; -+ UInt laneNo; /* either 0 or 1 */ -+ } VXfromQ; -+ /* MOV dst, src -- reg-reg move for vector registers */ -+ struct { -+ UInt szB; // 16=mov qD,qS; 8=mov dD,dS; 4=mov sD,sS -+ HReg dst; -+ HReg src; -+ } VMov; -+ struct { -+ ARM64AMode* amCounter; -+ ARM64AMode* amFailAddr; -+ } EvCheck; -+//ZZ struct { -+//ZZ /* No fields. The address of the counter to inc is -+//ZZ installed later, post-translation, by patching it in, -+//ZZ as it is not known at translation time. */ -+//ZZ } ProfInc; -+ } ARM64in; -+ } -+ ARM64Instr; -+ -+//ZZ -+extern ARM64Instr* ARM64Instr_Arith ( HReg, HReg, ARM64RIA*, Bool isAdd ); -+extern ARM64Instr* ARM64Instr_Cmp ( HReg, ARM64RIA*, Bool is64 ); -+extern ARM64Instr* ARM64Instr_Logic ( HReg, HReg, ARM64RIL*, ARM64LogicOp ); -+extern ARM64Instr* ARM64Instr_Test ( HReg, ARM64RIL* ); -+extern ARM64Instr* ARM64Instr_Shift ( HReg, HReg, ARM64RI6*, ARM64ShiftOp ); -+extern ARM64Instr* ARM64Instr_Unary ( HReg, HReg, ARM64UnaryOp ); -+//ZZ extern ARMInstr* ARMInstr_CmpOrTst ( Bool isCmp, HReg, ARMRI84* ); -+extern ARM64Instr* ARM64Instr_MovI ( HReg, HReg ); -+extern ARM64Instr* ARM64Instr_Imm64 ( HReg, ULong ); -+extern ARM64Instr* ARM64Instr_LdSt64 ( Bool isLoad, HReg, ARM64AMode* ); -+extern ARM64Instr* ARM64Instr_LdSt32 ( Bool isLoad, HReg, ARM64AMode* ); -+extern ARM64Instr* ARM64Instr_LdSt16 ( Bool isLoad, HReg, ARM64AMode* ); -+extern ARM64Instr* ARM64Instr_LdSt8 ( Bool isLoad, HReg, ARM64AMode* ); -+//ZZ extern ARMInstr* ARMInstr_Ld8S ( ARMCondCode, HReg, ARMAMode2* ); -+extern ARM64Instr* ARM64Instr_XDirect ( Addr64 dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, Bool toFastEP ); -+extern ARM64Instr* ARM64Instr_XIndir ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond ); -+extern ARM64Instr* ARM64Instr_XAssisted ( HReg dstGA, ARM64AMode* amPC, -+ ARM64CondCode cond, IRJumpKind jk ); -+extern ARM64Instr* ARM64Instr_CSel ( HReg dst, HReg argL, HReg argR, -+ ARM64CondCode cond ); -+extern ARM64Instr* ARM64Instr_Call ( ARM64CondCode, HWord, Int nArgRegs, -+ RetLoc rloc ); -+extern ARM64Instr* ARM64Instr_AddToSP ( Int simm ); -+extern ARM64Instr* ARM64Instr_FromSP ( HReg dst ); -+extern ARM64Instr* ARM64Instr_Mul ( HReg dst, HReg argL, HReg argR, -+ ARM64MulOp op ); -+extern ARM64Instr* ARM64Instr_LdrEX ( Int szB ); -+extern ARM64Instr* ARM64Instr_StrEX ( Int szB ); -+extern ARM64Instr* ARM64Instr_MFence ( void ); -+//ZZ extern ARMInstr* ARMInstr_CLREX ( void ); -+extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, -+ UInt uimm12 /* 0 .. 16380, 0 % 4 */ ); -+extern ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, -+ UInt uimm12 /* 0 .. 32760, 0 % 8 */ ); -+extern ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ); -+extern ARM64Instr* ARM64Instr_VCvtI2F ( ARM64CvtOp how, HReg rD, HReg rS ); -+extern ARM64Instr* ARM64Instr_VCvtF2I ( ARM64CvtOp how, HReg rD, HReg rS, -+ UChar armRM ); -+extern ARM64Instr* ARM64Instr_VCvtSD ( Bool sToD, HReg dst, HReg src ); -+extern ARM64Instr* ARM64Instr_VUnaryD ( ARM64FpUnaryOp op, HReg dst, HReg src ); -+extern ARM64Instr* ARM64Instr_VUnaryS ( ARM64FpUnaryOp op, HReg dst, HReg src ); -+extern ARM64Instr* ARM64Instr_VBinD ( ARM64FpBinOp op, HReg, HReg, HReg ); -+extern ARM64Instr* ARM64Instr_VBinS ( ARM64FpBinOp op, HReg, HReg, HReg ); -+extern ARM64Instr* ARM64Instr_VCmpD ( HReg argL, HReg argR ); -+extern ARM64Instr* ARM64Instr_VCmpS ( HReg argL, HReg argR ); -+extern ARM64Instr* ARM64Instr_FPCR ( Bool toFPCR, HReg iReg ); -+extern ARM64Instr* ARM64Instr_VBinV ( ARM64VecBinOp op, HReg, HReg, HReg ); -+extern ARM64Instr* ARM64Instr_VUnaryV ( ARM64VecUnaryOp op, HReg, HReg ); -+extern ARM64Instr* ARM64Instr_VNarrowV ( UInt dszBlg2, HReg dst, HReg src ); -+extern ARM64Instr* ARM64Instr_VShiftImmV ( ARM64VecShiftOp op, -+ HReg dst, HReg src, UInt amt ); -+//ZZ extern ARMInstr* ARMInstr_VAluS ( ARMVfpOp op, HReg, HReg, HReg ); -+//ZZ extern ARMInstr* ARMInstr_VCMovD ( ARMCondCode, HReg dst, HReg src ); -+//ZZ extern ARMInstr* ARMInstr_VCMovS ( ARMCondCode, HReg dst, HReg src ); -+//ZZ extern ARMInstr* ARMInstr_VXferD ( Bool toD, HReg dD, HReg rHi, HReg rLo ); -+//ZZ extern ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo ); -+//ZZ extern ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned, -+//ZZ HReg dst, HReg src ); -+//ZZ extern ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg, ARMAModeN* ); -+//ZZ extern ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp, HReg, HReg, UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOpS, ARMNRS*, ARMNRS*, -+//ZZ UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NDual ( ARMNeonDualOp, HReg, HReg, UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp, HReg, HReg, HReg, -+//ZZ UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp, HReg, HReg, HReg, -+//ZZ UInt, Bool ); -+//ZZ extern ARMInstr* ARMInstr_NShl64 ( HReg, HReg, UInt ); -+extern ARM64Instr* ARM64Instr_VImmQ ( HReg, UShort ); -+extern ARM64Instr* ARM64Instr_VDfromX ( HReg rD, HReg rX ); -+extern ARM64Instr* ARM64Instr_VQfromXX( HReg rQ, HReg rXhi, HReg rXlo ); -+extern ARM64Instr* ARM64Instr_VXfromQ ( HReg rX, HReg rQ, UInt laneNo ); -+extern ARM64Instr* ARM64Instr_VMov ( UInt szB, HReg dst, HReg src ); -+ -+extern ARM64Instr* ARM64Instr_EvCheck ( ARM64AMode* amCounter, -+ ARM64AMode* amFailAddr ); -+//ZZ extern ARMInstr* ARMInstr_ProfInc ( void ); -+ -+extern void ppARM64Instr ( ARM64Instr* ); -+ -+ -+/* Some functions that insulate the register allocator from details -+ of the underlying instruction set. */ -+extern void getRegUsage_ARM64Instr ( HRegUsage*, ARM64Instr*, Bool ); -+extern void mapRegs_ARM64Instr ( HRegRemap*, ARM64Instr*, Bool ); -+extern Bool isMove_ARM64Instr ( ARM64Instr*, HReg*, HReg* ); -+extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, -+ UChar* buf, Int nbuf, ARM64Instr* i, -+ Bool mode64, -+ void* disp_cp_chain_me_to_slowEP, -+ void* disp_cp_chain_me_to_fastEP, -+ void* disp_cp_xindir, -+ void* disp_cp_xassisted ); -+ -+extern void genSpill_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offset, Bool ); -+extern void genReload_ARM64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, -+ HReg rreg, Int offset, Bool ); -+ -+extern void getAllocableRegs_ARM64 ( Int*, HReg** ); -+extern HInstrArray* iselSB_ARM64 ( IRSB*, -+ VexArch, -+ VexArchInfo*, -+ VexAbiInfo*, -+ Int offs_Host_EvC_Counter, -+ Int offs_Host_EvC_FailAddr, -+ Bool chainingAllowed, -+ Bool addProfInc, -+ Addr64 max_ga ); -+ -+/* How big is an event check? This is kind of a kludge because it -+ depends on the offsets of host_EvC_FAILADDR and -+ host_EvC_COUNTER. */ -+extern Int evCheckSzB_ARM64 ( void ); -+ -+/* Perform a chaining and unchaining of an XDirect jump. */ -+extern VexInvalRange chainXDirect_ARM64 ( void* place_to_chain, -+ void* disp_cp_chain_me_EXPECTED, -+ void* place_to_jump_to ); -+ -+extern VexInvalRange unchainXDirect_ARM64 ( void* place_to_unchain, -+ void* place_to_jump_to_EXPECTED, -+ void* disp_cp_chain_me ); -+ -+//ZZ /* Patch the counter location into an existing ProfInc point. */ -+//ZZ extern VexInvalRange patchProfInc_ARM ( void* place_to_patch, -+//ZZ ULong* location_of_counter ); -+ -+ -+#endif /* ndef __VEX_HOST_ARM64_DEFS_H */ -+ -+/*---------------------------------------------------------------*/ -+/*--- end host_arm64_defs.h ---*/ -+/*---------------------------------------------------------------*/ -Index: priv/host_arm64_isel.c -=================================================================== ---- priv/host_arm64_isel.c (.../tags/VEX_3_9_0) (revision 0) -+++ priv/host_arm64_isel.c (.../trunk) (revision 2863) -@@ -0,0 +1,7058 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin host_arm64_isel.c ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "libvex_basictypes.h" -+#include "libvex_ir.h" -+#include "libvex.h" -+#include "ir_match.h" -+ -+#include "main_util.h" -+#include "main_globals.h" -+#include "host_generic_regs.h" -+#include "host_generic_simd64.h" // for 32-bit SIMD helpers -+#include "host_arm64_defs.h" -+ -+ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ /*--- ARMvfp control word stuff ---*/ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ -+//ZZ /* Vex-generated code expects to run with the FPU set as follows: all -+//ZZ exceptions masked, round-to-nearest, non-vector mode, with the NZCV -+//ZZ flags cleared, and FZ (flush to zero) disabled. Curiously enough, -+//ZZ this corresponds to a FPSCR value of zero. -+//ZZ -+//ZZ fpscr should therefore be zero on entry to Vex-generated code, and -+//ZZ should be unchanged at exit. (Or at least the bottom 28 bits -+//ZZ should be zero). -+//ZZ */ -+//ZZ -+//ZZ #define DEFAULT_FPSCR 0 -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISelEnv ---*/ -+/*---------------------------------------------------------*/ -+ -+/* This carries around: -+ -+ - A mapping from IRTemp to IRType, giving the type of any IRTemp we -+ might encounter. This is computed before insn selection starts, -+ and does not change. -+ -+ - A mapping from IRTemp to HReg. This tells the insn selector -+ which virtual register is associated with each IRTemp temporary. -+ This is computed before insn selection starts, and does not -+ change. We expect this mapping to map precisely the same set of -+ IRTemps as the type mapping does. -+ -+ |vregmap| holds the primary register for the IRTemp. -+ |vregmapHI| is only used for 128-bit integer-typed -+ IRTemps. It holds the identity of a second -+ 64-bit virtual HReg, which holds the high half -+ of the value. -+ -+ - The code array, that is, the insns selected so far. -+ -+ - A counter, for generating new virtual registers. -+ -+ - The host hardware capabilities word. This is set at the start -+ and does not change. -+ -+ - A Bool for indicating whether we may generate chain-me -+ instructions for control flow transfers, or whether we must use -+ XAssisted. -+ -+ - The maximum guest address of any guest insn in this block. -+ Actually, the address of the highest-addressed byte from any insn -+ in this block. Is set at the start and does not change. This is -+ used for detecting jumps which are definitely forward-edges from -+ this block, and therefore can be made (chained) to the fast entry -+ point of the destination, thereby avoiding the destination's -+ event check. -+ -+ - An IRExpr*, which may be NULL, holding the IR expression (an -+ IRRoundingMode-encoded value) to which the FPU's rounding mode -+ was most recently set. Setting to NULL is always safe. Used to -+ avoid redundant settings of the FPU's rounding mode, as -+ described in set_FPCR_rounding_mode below. -+ -+ Note, this is all (well, mostly) host-independent. -+*/ -+ -+typedef -+ struct { -+ /* Constant -- are set at the start and do not change. */ -+ IRTypeEnv* type_env; -+ -+ HReg* vregmap; -+ HReg* vregmapHI; -+ Int n_vregmap; -+ -+ UInt hwcaps; -+ -+ Bool chainingAllowed; -+ Addr64 max_ga; -+ -+ /* These are modified as we go along. */ -+ HInstrArray* code; -+ Int vreg_ctr; -+ -+ IRExpr* previous_rm; -+ } -+ ISelEnv; -+ -+static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp ) -+{ -+ vassert(tmp >= 0); -+ vassert(tmp < env->n_vregmap); -+ return env->vregmap[tmp]; -+} -+ -+static void addInstr ( ISelEnv* env, ARM64Instr* instr ) -+{ -+ addHInstr(env->code, instr); -+ if (vex_traceflags & VEX_TRACE_VCODE) { -+ ppARM64Instr(instr); -+ vex_printf("\n"); -+ } -+} -+ -+static HReg newVRegI ( ISelEnv* env ) -+{ -+ HReg reg = mkHReg(env->vreg_ctr, HRcInt64, True/*virtual reg*/); -+ env->vreg_ctr++; -+ return reg; -+} -+ -+static HReg newVRegD ( ISelEnv* env ) -+{ -+ HReg reg = mkHReg(env->vreg_ctr, HRcFlt64, True/*virtual reg*/); -+ env->vreg_ctr++; -+ return reg; -+} -+ -+//ZZ static HReg newVRegF ( ISelEnv* env ) -+//ZZ { -+//ZZ HReg reg = mkHReg(env->vreg_ctr, HRcFlt32, True/*virtual reg*/); -+//ZZ env->vreg_ctr++; -+//ZZ return reg; -+//ZZ } -+ -+static HReg newVRegV ( ISelEnv* env ) -+{ -+ HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); -+ env->vreg_ctr++; -+ return reg; -+} -+ -+//ZZ /* These are duplicated in guest_arm_toIR.c */ -+//ZZ static IRExpr* unop ( IROp op, IRExpr* a ) -+//ZZ { -+//ZZ return IRExpr_Unop(op, a); -+//ZZ } -+//ZZ -+//ZZ static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) -+//ZZ { -+//ZZ return IRExpr_Binop(op, a1, a2); -+//ZZ } -+//ZZ -+//ZZ static IRExpr* bind ( Int binder ) -+//ZZ { -+//ZZ return IRExpr_Binder(binder); -+//ZZ } -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Forward declarations ---*/ -+/*---------------------------------------------------------*/ -+ -+/* These are organised as iselXXX and iselXXX_wrk pairs. The -+ iselXXX_wrk do the real work, but are not to be called directly. -+ For each XXX, iselXXX calls its iselXXX_wrk counterpart, then -+ checks that all returned registers are virtual. You should not -+ call the _wrk version directly. -+ -+ Because some forms of ARM64 memory amodes are implicitly scaled by -+ the access size, iselIntExpr_AMode takes an IRType which tells it -+ the type of the access for which the amode is to be used. This -+ type needs to be correct, else you'll get incorrect code. -+*/ -+static ARM64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, -+ IRExpr* e, IRType dty ); -+static ARM64AMode* iselIntExpr_AMode ( ISelEnv* env, -+ IRExpr* e, IRType dty ); -+ -+static ARM64RIA* iselIntExpr_RIA_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64RIA* iselIntExpr_RIA ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64RIL* iselIntExpr_RIL_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64RIL* iselIntExpr_RIL ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64RI6* iselIntExpr_RI6_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64RI6* iselIntExpr_RI6 ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ); -+static ARM64CondCode iselCondCode ( ISelEnv* env, IRExpr* e ); -+ -+static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ); -+ -+static void iselInt128Expr_wrk ( /*OUT*/HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ); -+static void iselInt128Expr ( /*OUT*/HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ); -+ -+ -+//ZZ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, -+//ZZ ISelEnv* env, IRExpr* e ); -+//ZZ static void iselInt64Expr ( HReg* rHi, HReg* rLo, -+//ZZ ISelEnv* env, IRExpr* e ); -+ -+static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ); -+ -+static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ); -+ -+//ZZ static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ); -+//ZZ static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e ); -+ -+static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ); -+static HReg iselV128Expr ( ISelEnv* env, IRExpr* e ); -+ -+static ARM64RIL* mb_mkARM64RIL_I ( ULong imm64 ); -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Misc helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Generate an amode suitable for a 64-bit sized access relative to -+ the baseblock register (X21). This generates an RI12 amode, which -+ means its scaled by the access size, which is why the access size -+ -- 64 bit -- is stated explicitly here. Consequently |off| needs -+ to be divisible by 8. */ -+static ARM64AMode* mk_baseblock_64bit_access_amode ( UInt off ) -+{ -+ vassert(off < (8 << 12)); /* otherwise it's unrepresentable */ -+ vassert((off & 7) == 0); /* ditto */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 3, 8/*scale*/); -+} -+ -+/* Ditto, for 32 bit accesses. */ -+static ARM64AMode* mk_baseblock_32bit_access_amode ( UInt off ) -+{ -+ vassert(off < (4 << 12)); /* otherwise it's unrepresentable */ -+ vassert((off & 3) == 0); /* ditto */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 2, 4/*scale*/); -+} -+ -+/* Ditto, for 16 bit accesses. */ -+static ARM64AMode* mk_baseblock_16bit_access_amode ( UInt off ) -+{ -+ vassert(off < (2 << 12)); /* otherwise it's unrepresentable */ -+ vassert((off & 1) == 0); /* ditto */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 1, 2/*scale*/); -+} -+ -+/* Ditto, for 8 bit accesses. */ -+static ARM64AMode* mk_baseblock_8bit_access_amode ( UInt off ) -+{ -+ vassert(off < (1 << 12)); /* otherwise it's unrepresentable */ -+ return ARM64AMode_RI12(hregARM64_X21(), off >> 0, 1/*scale*/); -+} -+ -+static HReg mk_baseblock_128bit_access_addr ( ISelEnv* env, UInt off ) -+{ -+ vassert(off < (1<<12)); -+ HReg r = newVRegI(env); -+ addInstr(env, ARM64Instr_Arith(r, hregARM64_X21(), -+ ARM64RIA_I12(off,0), True/*isAdd*/)); -+ return r; -+} -+ -+static HReg get_baseblock_register ( void ) -+{ -+ return hregARM64_X21(); -+} -+ -+/* Generate code to zero extend a 32 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_z_32_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RIL* mask = ARM64RIL_I13(1, 0, 31); /* encodes 0xFFFFFFFF */ -+ addInstr(env, ARM64Instr_Logic(dst, src, mask, ARM64lo_AND)); -+ return dst; -+} -+ -+/* Generate code to sign extend a 16 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_s_16_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n48 = ARM64RI6_I6(48); -+ addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SAR)); -+ return dst; -+} -+ -+/* Generate code to zero extend a 16 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_z_16_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n48 = ARM64RI6_I6(48); -+ addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SHR)); -+ return dst; -+} -+ -+/* Generate code to sign extend a 32 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_s_32_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n32 = ARM64RI6_I6(32); -+ addInstr(env, ARM64Instr_Shift(dst, src, n32, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n32, ARM64sh_SAR)); -+ return dst; -+} -+ -+/* Generate code to sign extend a 8 bit value in 'src' to 64 bits, in -+ a new register, and return the new register. */ -+static HReg widen_s_8_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n56 = ARM64RI6_I6(56); -+ addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n56, ARM64sh_SAR)); -+ return dst; -+} -+ -+static HReg widen_z_8_to_64 ( ISelEnv* env, HReg src ) -+{ -+ HReg dst = newVRegI(env); -+ ARM64RI6* n56 = ARM64RI6_I6(56); -+ addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, n56, ARM64sh_SHR)); -+ return dst; -+} -+ -+/* Is this IRExpr_Const(IRConst_U64(0)) ? */ -+static Bool isZeroU64 ( IRExpr* e ) { -+ if (e->tag != Iex_Const) return False; -+ IRConst* con = e->Iex.Const.con; -+ vassert(con->tag == Ico_U64); -+ return con->Ico.U64 == 0; -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: FP rounding mode helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Set the FP rounding mode: 'mode' is an I32-typed expression -+ denoting a value in the range 0 .. 3, indicating a round mode -+ encoded as per type IRRoundingMode -- the first four values only -+ (Irrm_NEAREST, Irrm_NegINF, Irrm_PosINF, Irrm_ZERO). Set the PPC -+ FSCR to have the same rounding. -+ -+ For speed & simplicity, we're setting the *entire* FPCR here. -+ -+ Setting the rounding mode is expensive. So this function tries to -+ avoid repeatedly setting the rounding mode to the same thing by -+ first comparing 'mode' to the 'mode' tree supplied in the previous -+ call to this function, if any. (The previous value is stored in -+ env->previous_rm.) If 'mode' is a single IR temporary 't' and -+ env->previous_rm is also just 't', then the setting is skipped. -+ -+ This is safe because of the SSA property of IR: an IR temporary can -+ only be defined once and so will have the same value regardless of -+ where it appears in the block. Cool stuff, SSA. -+ -+ A safety condition: all attempts to set the RM must be aware of -+ this mechanism - by being routed through the functions here. -+ -+ Of course this only helps if blocks where the RM is set more than -+ once and it is set to the same value each time, *and* that value is -+ held in the same IR temporary each time. In order to assure the -+ latter as much as possible, the IR optimiser takes care to do CSE -+ on any block with any sign of floating point activity. -+*/ -+static -+void set_FPCR_rounding_mode ( ISelEnv* env, IRExpr* mode ) -+{ -+ vassert(typeOfIRExpr(env->type_env,mode) == Ity_I32); -+ -+ /* Do we need to do anything? */ -+ if (env->previous_rm -+ && env->previous_rm->tag == Iex_RdTmp -+ && mode->tag == Iex_RdTmp -+ && env->previous_rm->Iex.RdTmp.tmp == mode->Iex.RdTmp.tmp) { -+ /* no - setting it to what it was before. */ -+ vassert(typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32); -+ return; -+ } -+ -+ /* No luck - we better set it, and remember what we set it to. */ -+ env->previous_rm = mode; -+ -+ /* Only supporting the rounding-mode bits - the rest of FPCR is set -+ to zero - so we can set the whole register at once (faster). */ -+ -+ /* This isn't simple, because 'mode' carries an IR rounding -+ encoding, and we need to translate that to an ARM64 FP one: -+ The IR encoding: -+ 00 to nearest (the default) -+ 10 to +infinity -+ 01 to -infinity -+ 11 to zero -+ The ARM64 FP encoding: -+ 00 to nearest -+ 01 to +infinity -+ 10 to -infinity -+ 11 to zero -+ Easy enough to do; just swap the two bits. -+ */ -+ HReg irrm = iselIntExpr_R(env, mode); -+ HReg tL = newVRegI(env); -+ HReg tR = newVRegI(env); -+ HReg t3 = newVRegI(env); -+ /* tL = irrm << 1; -+ tR = irrm >> 1; if we're lucky, these will issue together -+ tL &= 2; -+ tR &= 1; ditto -+ t3 = tL | tR; -+ t3 <<= 22; -+ fmxr fpscr, t3 -+ */ -+ ARM64RIL* ril_one = mb_mkARM64RIL_I(1); -+ ARM64RIL* ril_two = mb_mkARM64RIL_I(2); -+ vassert(ril_one && ril_two); -+ addInstr(env, ARM64Instr_Shift(tL, irrm, ARM64RI6_I6(1), ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(tR, irrm, ARM64RI6_I6(1), ARM64sh_SHR)); -+ addInstr(env, ARM64Instr_Logic(tL, tL, ril_two, ARM64lo_AND)); -+ addInstr(env, ARM64Instr_Logic(tR, tR, ril_one, ARM64lo_AND)); -+ addInstr(env, ARM64Instr_Logic(t3, tL, ARM64RIL_R(tR), ARM64lo_OR)); -+ addInstr(env, ARM64Instr_Shift(t3, t3, ARM64RI6_I6(22), ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_FPCR(True/*toFPCR*/, t3)); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Function call helpers ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Used only in doHelperCall. See big comment in doHelperCall re -+ handling of register-parameter args. This function figures out -+ whether evaluation of an expression might require use of a fixed -+ register. If in doubt return True (safe but suboptimal). -+*/ -+static -+Bool mightRequireFixedRegs ( IRExpr* e ) -+{ -+ if (UNLIKELY(is_IRExpr_VECRET_or_BBPTR(e))) { -+ // These are always "safe" -- either a copy of SP in some -+ // arbitrary vreg, or a copy of x21, respectively. -+ return False; -+ } -+ /* Else it's a "normal" expression. */ -+ switch (e->tag) { -+ case Iex_RdTmp: case Iex_Const: case Iex_Get: -+ return False; -+ default: -+ return True; -+ } -+} -+ -+ -+/* Do a complete function call. |guard| is a Ity_Bit expression -+ indicating whether or not the call happens. If guard==NULL, the -+ call is unconditional. |retloc| is set to indicate where the -+ return value is after the call. The caller (of this fn) must -+ generate code to add |stackAdjustAfterCall| to the stack pointer -+ after the call is done. Returns True iff it managed to handle this -+ combination of arg/return types, else returns False. */ -+ -+static -+Bool doHelperCall ( /*OUT*/UInt* stackAdjustAfterCall, -+ /*OUT*/RetLoc* retloc, -+ ISelEnv* env, -+ IRExpr* guard, -+ IRCallee* cee, IRType retTy, IRExpr** args ) -+{ -+ ARM64CondCode cc; -+ HReg argregs[ARM64_N_ARGREGS]; -+ HReg tmpregs[ARM64_N_ARGREGS]; -+ Bool go_fast; -+ Int n_args, i, nextArgReg; -+ ULong target; -+ -+ vassert(ARM64_N_ARGREGS == 8); -+ -+ /* Set default returns. We'll update them later if needed. */ -+ *stackAdjustAfterCall = 0; -+ *retloc = mk_RetLoc_INVALID(); -+ -+ /* These are used for cross-checking that IR-level constraints on -+ the use of IRExpr_VECRET() and IRExpr_BBPTR() are observed. */ -+ UInt nVECRETs = 0; -+ UInt nBBPTRs = 0; -+ -+ /* Marshal args for a call and do the call. -+ -+ This function only deals with a tiny set of possibilities, which -+ cover all helpers in practice. The restrictions are that only -+ arguments in registers are supported, hence only -+ ARM64_N_REGPARMS x 64 integer bits in total can be passed. In -+ fact the only supported arg type is I64. -+ -+ The return type can be I{64,32} or V128. In the V128 case, it -+ is expected that |args| will contain the special node -+ IRExpr_VECRET(), in which case this routine generates code to -+ allocate space on the stack for the vector return value. Since -+ we are not passing any scalars on the stack, it is enough to -+ preallocate the return space before marshalling any arguments, -+ in this case. -+ -+ |args| may also contain IRExpr_BBPTR(), in which case the -+ value in x21 is passed as the corresponding argument. -+ -+ Generating code which is both efficient and correct when -+ parameters are to be passed in registers is difficult, for the -+ reasons elaborated in detail in comments attached to -+ doHelperCall() in priv/host-x86/isel.c. Here, we use a variant -+ of the method described in those comments. -+ -+ The problem is split into two cases: the fast scheme and the -+ slow scheme. In the fast scheme, arguments are computed -+ directly into the target (real) registers. This is only safe -+ when we can be sure that computation of each argument will not -+ trash any real registers set by computation of any other -+ argument. -+ -+ In the slow scheme, all args are first computed into vregs, and -+ once they are all done, they are moved to the relevant real -+ regs. This always gives correct code, but it also gives a bunch -+ of vreg-to-rreg moves which are usually redundant but are hard -+ for the register allocator to get rid of. -+ -+ To decide which scheme to use, all argument expressions are -+ first examined. If they are all so simple that it is clear they -+ will be evaluated without use of any fixed registers, use the -+ fast scheme, else use the slow scheme. Note also that only -+ unconditional calls may use the fast scheme, since having to -+ compute a condition expression could itself trash real -+ registers. -+ -+ Note this requires being able to examine an expression and -+ determine whether or not evaluation of it might use a fixed -+ register. That requires knowledge of how the rest of this insn -+ selector works. Currently just the following 3 are regarded as -+ safe -- hopefully they cover the majority of arguments in -+ practice: IRExpr_Tmp IRExpr_Const IRExpr_Get. -+ */ -+ -+ /* Note that the cee->regparms field is meaningless on ARM64 hosts -+ (since there is only one calling convention) and so we always -+ ignore it. */ -+ -+ n_args = 0; -+ for (i = 0; args[i]; i++) { -+ IRExpr* arg = args[i]; -+ if (UNLIKELY(arg->tag == Iex_VECRET)) { -+ nVECRETs++; -+ } else if (UNLIKELY(arg->tag == Iex_BBPTR)) { -+ nBBPTRs++; -+ } -+ n_args++; -+ } -+ -+ /* If this fails, the IR is ill-formed */ -+ vassert(nBBPTRs == 0 || nBBPTRs == 1); -+ -+ /* If we have a VECRET, allocate space on the stack for the return -+ value, and record the stack pointer after that. */ -+ HReg r_vecRetAddr = INVALID_HREG; -+ if (nVECRETs == 1) { -+ vassert(retTy == Ity_V128 || retTy == Ity_V256); -+ vassert(retTy != Ity_V256); // we don't handle that yet (if ever) -+ r_vecRetAddr = newVRegI(env); -+ addInstr(env, ARM64Instr_AddToSP(-16)); -+ addInstr(env, ARM64Instr_FromSP(r_vecRetAddr)); -+ } else { -+ // If either of these fail, the IR is ill-formed -+ vassert(retTy != Ity_V128 && retTy != Ity_V256); -+ vassert(nVECRETs == 0); -+ } -+ -+ argregs[0] = hregARM64_X0(); -+ argregs[1] = hregARM64_X1(); -+ argregs[2] = hregARM64_X2(); -+ argregs[3] = hregARM64_X3(); -+ argregs[4] = hregARM64_X4(); -+ argregs[5] = hregARM64_X5(); -+ argregs[6] = hregARM64_X6(); -+ argregs[7] = hregARM64_X7(); -+ -+ tmpregs[0] = tmpregs[1] = tmpregs[2] = tmpregs[3] = INVALID_HREG; -+ tmpregs[4] = tmpregs[5] = tmpregs[6] = tmpregs[7] = INVALID_HREG; -+ -+ /* First decide which scheme (slow or fast) is to be used. First -+ assume the fast scheme, and select slow if any contraindications -+ (wow) appear. */ -+ -+ go_fast = True; -+ -+ if (guard) { -+ if (guard->tag == Iex_Const -+ && guard->Iex.Const.con->tag == Ico_U1 -+ && guard->Iex.Const.con->Ico.U1 == True) { -+ /* unconditional */ -+ } else { -+ /* Not manifestly unconditional -- be conservative. */ -+ go_fast = False; -+ } -+ } -+ -+ if (go_fast) { -+ for (i = 0; i < n_args; i++) { -+ if (mightRequireFixedRegs(args[i])) { -+ go_fast = False; -+ break; -+ } -+ } -+ } -+ -+ if (go_fast) { -+ if (retTy == Ity_V128 || retTy == Ity_V256) -+ go_fast = False; -+ } -+ -+ /* At this point the scheme to use has been established. Generate -+ code to get the arg values into the argument rregs. If we run -+ out of arg regs, give up. */ -+ -+ if (go_fast) { -+ -+ /* FAST SCHEME */ -+ nextArgReg = 0; -+ -+ for (i = 0; i < n_args; i++) { -+ IRExpr* arg = args[i]; -+ -+ IRType aTy = Ity_INVALID; -+ if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg))) -+ aTy = typeOfIRExpr(env->type_env, args[i]); -+ -+ if (nextArgReg >= ARM64_N_ARGREGS) -+ return False; /* out of argregs */ -+ -+ if (aTy == Ity_I64) { -+ addInstr(env, ARM64Instr_MovI( argregs[nextArgReg], -+ iselIntExpr_R(env, args[i]) )); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_BBPTR) { -+ vassert(0); //ATC -+ addInstr(env, ARM64Instr_MovI( argregs[nextArgReg], -+ hregARM64_X21() )); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_VECRET) { -+ // because of the go_fast logic above, we can't get here, -+ // since vector return values makes us use the slow path -+ // instead. -+ vassert(0); -+ } -+ else -+ return False; /* unhandled arg type */ -+ } -+ -+ /* Fast scheme only applies for unconditional calls. Hence: */ -+ cc = ARM64cc_AL; -+ -+ } else { -+ -+ /* SLOW SCHEME; move via temporaries */ -+ nextArgReg = 0; -+ -+ for (i = 0; i < n_args; i++) { -+ IRExpr* arg = args[i]; -+ -+ IRType aTy = Ity_INVALID; -+ if (LIKELY(!is_IRExpr_VECRET_or_BBPTR(arg))) -+ aTy = typeOfIRExpr(env->type_env, args[i]); -+ -+ if (nextArgReg >= ARM64_N_ARGREGS) -+ return False; /* out of argregs */ -+ -+ if (aTy == Ity_I64) { -+ tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_BBPTR) { -+ vassert(0); //ATC -+ tmpregs[nextArgReg] = hregARM64_X21(); -+ nextArgReg++; -+ } -+ else if (arg->tag == Iex_VECRET) { -+ vassert(!hregIsInvalid(r_vecRetAddr)); -+ tmpregs[nextArgReg] = r_vecRetAddr; -+ nextArgReg++; -+ } -+ else -+ return False; /* unhandled arg type */ -+ } -+ -+ /* Now we can compute the condition. We can't do it earlier -+ because the argument computations could trash the condition -+ codes. Be a bit clever to handle the common case where the -+ guard is 1:Bit. */ -+ cc = ARM64cc_AL; -+ if (guard) { -+ if (guard->tag == Iex_Const -+ && guard->Iex.Const.con->tag == Ico_U1 -+ && guard->Iex.Const.con->Ico.U1 == True) { -+ /* unconditional -- do nothing */ -+ } else { -+ cc = iselCondCode( env, guard ); -+ } -+ } -+ -+ /* Move the args to their final destinations. */ -+ for (i = 0; i < nextArgReg; i++) { -+ vassert(!(hregIsInvalid(tmpregs[i]))); -+ /* None of these insns, including any spill code that might -+ be generated, may alter the condition codes. */ -+ addInstr( env, ARM64Instr_MovI( argregs[i], tmpregs[i] ) ); -+ } -+ -+ } -+ -+ /* Should be assured by checks above */ -+ vassert(nextArgReg <= ARM64_N_ARGREGS); -+ -+ /* Do final checks, set the return values, and generate the call -+ instruction proper. */ -+ vassert(nBBPTRs == 0 || nBBPTRs == 1); -+ vassert(nVECRETs == (retTy == Ity_V128 || retTy == Ity_V256) ? 1 : 0); -+ vassert(*stackAdjustAfterCall == 0); -+ vassert(is_RetLoc_INVALID(*retloc)); -+ switch (retTy) { -+ case Ity_INVALID: -+ /* Function doesn't return a value. */ -+ *retloc = mk_RetLoc_simple(RLPri_None); -+ break; -+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: -+ *retloc = mk_RetLoc_simple(RLPri_Int); -+ break; -+ case Ity_V128: -+ *retloc = mk_RetLoc_spRel(RLPri_V128SpRel, 0); -+ *stackAdjustAfterCall = 16; -+ break; -+ case Ity_V256: -+ vassert(0); // ATC -+ *retloc = mk_RetLoc_spRel(RLPri_V256SpRel, 0); -+ *stackAdjustAfterCall = 32; -+ break; -+ default: -+ /* IR can denote other possible return types, but we don't -+ handle those here. */ -+ vassert(0); -+ } -+ -+ /* Finally, generate the call itself. This needs the *retloc value -+ set in the switch above, which is why it's at the end. */ -+ -+ /* nextArgReg doles out argument registers. Since these are -+ assigned in the order x0 .. x7, its numeric value at this point, -+ which must be between 0 and 8 inclusive, is going to be equal to -+ the number of arg regs in use for the call. Hence bake that -+ number into the call (we'll need to know it when doing register -+ allocation, to know what regs the call reads.) */ -+ -+ target = (HWord)Ptr_to_ULong(cee->addr); -+ addInstr(env, ARM64Instr_Call( cc, target, nextArgReg, *retloc )); -+ -+ return True; /* success */ -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Integer expressions (64/32 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Select insns for an integer-typed expression, and add them to the -+ code list. Return a reg holding the result. This reg will be a -+ virtual register. THE RETURNED REG MUST NOT BE MODIFIED. If you -+ want to modify it, ask for a new vreg, copy it in there, and modify -+ the copy. The register allocator will do its best to map both -+ vregs to the same real register, so the copies will often disappear -+ later in the game. -+ -+ This should handle expressions of 64- and 32-bit type. All results -+ are returned in a 64-bit register. For 32-bit expressions, the -+ upper 32 bits are arbitrary, so you should mask or sign extend -+ partial values if necessary. -+*/ -+ -+/* --------------------- AMode --------------------- */ -+ -+/* Return an AMode which computes the value of the specified -+ expression, possibly also adding insns to the code list as a -+ result. The expression may only be a 64-bit one. -+*/ -+ -+static Bool isValidScale ( UChar scale ) -+{ -+ switch (scale) { -+ case 1: case 2: case 4: case 8: /* case 16: ??*/ return True; -+ default: return False; -+ } -+} -+ -+static Bool sane_AMode ( ARM64AMode* am ) -+{ -+ switch (am->tag) { -+ case ARM64am_RI9: -+ return -+ toBool( hregClass(am->ARM64am.RI9.reg) == HRcInt64 -+ && (hregIsVirtual(am->ARM64am.RI9.reg) -+ /* || sameHReg(am->ARM64am.RI9.reg, -+ hregARM64_X21()) */ ) -+ && am->ARM64am.RI9.simm9 >= -256 -+ && am->ARM64am.RI9.simm9 <= 255 ); -+ case ARM64am_RI12: -+ return -+ toBool( hregClass(am->ARM64am.RI12.reg) == HRcInt64 -+ && (hregIsVirtual(am->ARM64am.RI12.reg) -+ /* || sameHReg(am->ARM64am.RI12.reg, -+ hregARM64_X21()) */ ) -+ && am->ARM64am.RI12.uimm12 < 4096 -+ && isValidScale(am->ARM64am.RI12.szB) ); -+ case ARM64am_RR: -+ return -+ toBool( hregClass(am->ARM64am.RR.base) == HRcInt64 -+ && hregIsVirtual(am->ARM64am.RR.base) -+ && hregClass(am->ARM64am.RR.index) == HRcInt64 -+ && hregIsVirtual(am->ARM64am.RR.index) ); -+ default: -+ vpanic("sane_AMode: unknown ARM64 AMode1 tag"); -+ } -+} -+ -+static -+ARM64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e, IRType dty ) -+{ -+ ARM64AMode* am = iselIntExpr_AMode_wrk(env, e, dty); -+ vassert(sane_AMode(am)); -+ return am; -+} -+ -+static -+ARM64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType dty ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64); -+ -+ ULong szBbits = 0; -+ switch (dty) { -+ case Ity_I64: szBbits = 3; break; -+ case Ity_I32: szBbits = 2; break; -+ case Ity_I16: szBbits = 1; break; -+ case Ity_I8: szBbits = 0; break; -+ default: vassert(0); -+ } -+ -+ /* {Add64,Sub64}(expr,simm9). We don't care about |dty| here since -+ we're going to create an amode suitable for LDU* or STU* -+ instructions, which use unscaled immediate offsets. */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_Add64 || e->Iex.Binop.op == Iop_Sub64) -+ && e->Iex.Binop.arg2->tag == Iex_Const -+ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64) { -+ Long simm = (Long)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; -+ if (simm >= -255 && simm <= 255) { -+ /* Although the gating condition might seem to be -+ simm >= -256 && simm <= 255 -+ we will need to negate simm in the case where the op is Sub64. -+ Hence limit the lower value to -255 in order that its negation -+ is representable. */ -+ HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ if (e->Iex.Binop.op == Iop_Sub64) simm = -simm; -+ return ARM64AMode_RI9(reg, (Int)simm); -+ } -+ } -+ -+ /* Add64(expr, uimm12 * transfer-size) */ -+ if (e->tag == Iex_Binop -+ && e->Iex.Binop.op == Iop_Add64 -+ && e->Iex.Binop.arg2->tag == Iex_Const -+ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64) { -+ ULong uimm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U64; -+ ULong szB = 1 << szBbits; -+ if (0 == (uimm & (szB-1)) /* "uimm is szB-aligned" */ -+ && (uimm >> szBbits) < 4096) { -+ HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ return ARM64AMode_RI12(reg, (UInt)(uimm >> szBbits), (UChar)szB); -+ } -+ } -+ -+ /* Add64(expr1, expr2) */ -+ if (e->tag == Iex_Binop -+ && e->Iex.Binop.op == Iop_Add64) { -+ HReg reg1 = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg reg2 = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ return ARM64AMode_RR(reg1, reg2); -+ } -+ -+ /* Doesn't match anything in particular. Generate it into -+ a register and use that. */ -+ HReg reg = iselIntExpr_R(env, e); -+ return ARM64AMode_RI9(reg, 0); -+} -+ -+//ZZ /* --------------------- AModeV --------------------- */ -+//ZZ -+//ZZ /* Return an AModeV which computes the value of the specified -+//ZZ expression, possibly also adding insns to the code list as a -+//ZZ result. The expression may only be a 32-bit one. -+//ZZ */ -+//ZZ -+//ZZ static Bool sane_AModeV ( ARMAModeV* am ) -+//ZZ { -+//ZZ return toBool( hregClass(am->reg) == HRcInt32 -+//ZZ && hregIsVirtual(am->reg) -+//ZZ && am->simm11 >= -1020 && am->simm11 <= 1020 -+//ZZ && 0 == (am->simm11 & 3) ); -+//ZZ } -+//ZZ -+//ZZ static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ ARMAModeV* am = iselIntExpr_AModeV_wrk(env, e); -+//ZZ vassert(sane_AModeV(am)); -+//ZZ return am; -+//ZZ } -+//ZZ -+//ZZ static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ IRType ty = typeOfIRExpr(env->type_env,e); -+//ZZ vassert(ty == Ity_I32); -+//ZZ -+//ZZ /* {Add32,Sub32}(expr, simm8 << 2) */ -+//ZZ if (e->tag == Iex_Binop -+//ZZ && (e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Sub32) -+//ZZ && e->Iex.Binop.arg2->tag == Iex_Const -+//ZZ && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32) { -+//ZZ Int simm = (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32; -+//ZZ if (simm >= -1020 && simm <= 1020 && 0 == (simm & 3)) { -+//ZZ HReg reg; -+//ZZ if (e->Iex.Binop.op == Iop_Sub32) -+//ZZ simm = -simm; -+//ZZ reg = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ return mkARMAModeV(reg, simm); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* Doesn't match anything in particular. Generate it into -+//ZZ a register and use that. */ -+//ZZ { -+//ZZ HReg reg = iselIntExpr_R(env, e); -+//ZZ return mkARMAModeV(reg, 0); -+//ZZ } -+//ZZ -+//ZZ } -+//ZZ -+//ZZ /* -------------------- AModeN -------------------- */ -+//ZZ -+//ZZ static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ return iselIntExpr_AModeN_wrk(env, e); -+//ZZ } -+//ZZ -+//ZZ static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ HReg reg = iselIntExpr_R(env, e); -+//ZZ return mkARMAModeN_R(reg); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /* --------------------- RI84 --------------------- */ -+//ZZ -+//ZZ /* Select instructions to generate 'e' into a RI84. If mayInv is -+//ZZ true, then the caller will also accept an I84 form that denotes -+//ZZ 'not e'. In this case didInv may not be NULL, and *didInv is set -+//ZZ to True. This complication is so as to allow generation of an RI84 -+//ZZ which is suitable for use in either an AND or BIC instruction, -+//ZZ without knowing (before this call) which one. -+//ZZ */ -+//ZZ static ARMRI84* iselIntExpr_RI84 ( /*OUT*/Bool* didInv, Bool mayInv, -+//ZZ ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ ARMRI84* ri; -+//ZZ if (mayInv) -+//ZZ vassert(didInv != NULL); -+//ZZ ri = iselIntExpr_RI84_wrk(didInv, mayInv, env, e); -+//ZZ /* sanity checks ... */ -+//ZZ switch (ri->tag) { -+//ZZ case ARMri84_I84: -+//ZZ return ri; -+//ZZ case ARMri84_R: -+//ZZ vassert(hregClass(ri->ARMri84.R.reg) == HRcInt32); -+//ZZ vassert(hregIsVirtual(ri->ARMri84.R.reg)); -+//ZZ return ri; -+//ZZ default: -+//ZZ vpanic("iselIntExpr_RI84: unknown arm RI84 tag"); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* DO NOT CALL THIS DIRECTLY ! */ -+//ZZ static ARMRI84* iselIntExpr_RI84_wrk ( /*OUT*/Bool* didInv, Bool mayInv, -+//ZZ ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ IRType ty = typeOfIRExpr(env->type_env,e); -+//ZZ vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8); -+//ZZ -+//ZZ if (didInv) *didInv = False; -+//ZZ -+//ZZ /* special case: immediate */ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ UInt u, u8 = 0x100, u4 = 0x10; /* both invalid */ -+//ZZ switch (e->Iex.Const.con->tag) { -+//ZZ case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; -+//ZZ case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break; -+//ZZ case Ico_U8: u = 0xFF & (e->Iex.Const.con->Ico.U8); break; -+//ZZ default: vpanic("iselIntExpr_RI84.Iex_Const(armh)"); -+//ZZ } -+//ZZ if (fitsIn8x4(&u8, &u4, u)) { -+//ZZ return ARMRI84_I84( (UShort)u8, (UShort)u4 ); -+//ZZ } -+//ZZ if (mayInv && fitsIn8x4(&u8, &u4, ~u)) { -+//ZZ vassert(didInv); -+//ZZ *didInv = True; -+//ZZ return ARMRI84_I84( (UShort)u8, (UShort)u4 ); -+//ZZ } -+//ZZ /* else fail, fall through to default case */ -+//ZZ } -+//ZZ -+//ZZ /* default case: calculate into a register and return that */ -+//ZZ { -+//ZZ HReg r = iselIntExpr_R ( env, e ); -+//ZZ return ARMRI84_R(r); -+//ZZ } -+//ZZ } -+ -+ -+/* --------------------- RIA --------------------- */ -+ -+/* Select instructions to generate 'e' into a RIA. */ -+ -+static ARM64RIA* iselIntExpr_RIA ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64RIA* ri = iselIntExpr_RIA_wrk(env, e); -+ /* sanity checks ... */ -+ switch (ri->tag) { -+ case ARM64riA_I12: -+ vassert(ri->ARM64riA.I12.imm12 < 4096); -+ vassert(ri->ARM64riA.I12.shift == 0 || ri->ARM64riA.I12.shift == 12); -+ return ri; -+ case ARM64riA_R: -+ vassert(hregClass(ri->ARM64riA.R.reg) == HRcInt64); -+ vassert(hregIsVirtual(ri->ARM64riA.R.reg)); -+ return ri; -+ default: -+ vpanic("iselIntExpr_RIA: unknown arm RIA tag"); -+ } -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static ARM64RIA* iselIntExpr_RIA_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I32); -+ -+ /* special case: immediate */ -+ if (e->tag == Iex_Const) { -+ ULong u = 0xF000000ULL; /* invalid */ -+ switch (e->Iex.Const.con->tag) { -+ case Ico_U64: u = e->Iex.Const.con->Ico.U64; break; -+ case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; -+ default: vpanic("iselIntExpr_RIA.Iex_Const(arm64)"); -+ } -+ if (0 == (u & ~(0xFFFULL << 0))) -+ return ARM64RIA_I12((UShort)((u >> 0) & 0xFFFULL), 0); -+ if (0 == (u & ~(0xFFFULL << 12))) -+ return ARM64RIA_I12((UShort)((u >> 12) & 0xFFFULL), 12); -+ /* else fail, fall through to default case */ -+ } -+ -+ /* default case: calculate into a register and return that */ -+ { -+ HReg r = iselIntExpr_R ( env, e ); -+ return ARM64RIA_R(r); -+ } -+} -+ -+ -+/* --------------------- RIL --------------------- */ -+ -+/* Select instructions to generate 'e' into a RIL. At this point we -+ have to deal with the strange bitfield-immediate encoding for logic -+ instructions. */ -+ -+ -+// The following four functions -+// CountLeadingZeros CountTrailingZeros CountSetBits isImmLogical -+// are copied, with modifications, from -+// https://github.com/armvixl/vixl/blob/master/src/a64/assembler-a64.cc -+// which has the following copyright notice: -+/* -+ Copyright 2013, ARM Limited -+ All rights reserved. -+ -+ Redistribution and use in source and binary forms, with or without -+ modification, are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright notice, -+ this list of conditions and the following disclaimer in the documentation -+ and/or other materials provided with the distribution. -+ * Neither the name of ARM Limited nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND -+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+static Int CountLeadingZeros(ULong value, Int width) -+{ -+ vassert(width == 32 || width == 64); -+ Int count = 0; -+ ULong bit_test = 1ULL << (width - 1); -+ while ((count < width) && ((bit_test & value) == 0)) { -+ count++; -+ bit_test >>= 1; -+ } -+ return count; -+} -+ -+static Int CountTrailingZeros(ULong value, Int width) -+{ -+ vassert(width == 32 || width == 64); -+ Int count = 0; -+ while ((count < width) && (((value >> count) & 1) == 0)) { -+ count++; -+ } -+ return count; -+} -+ -+static Int CountSetBits(ULong value, Int width) -+{ -+ // TODO: Other widths could be added here, as the implementation already -+ // supports them. -+ vassert(width == 32 || width == 64); -+ -+ // Mask out unused bits to ensure that they are not counted. -+ value &= (0xffffffffffffffffULL >> (64-width)); -+ -+ // Add up the set bits. -+ // The algorithm works by adding pairs of bit fields together iteratively, -+ // where the size of each bit field doubles each time. -+ // An example for an 8-bit value: -+ // Bits: h g f e d c b a -+ // \ | \ | \ | \ | -+ // value = h+g f+e d+c b+a -+ // \ | \ | -+ // value = h+g+f+e d+c+b+a -+ // \ | -+ // value = h+g+f+e+d+c+b+a -+ value = ((value >> 1) & 0x5555555555555555ULL) -+ + (value & 0x5555555555555555ULL); -+ value = ((value >> 2) & 0x3333333333333333ULL) -+ + (value & 0x3333333333333333ULL); -+ value = ((value >> 4) & 0x0f0f0f0f0f0f0f0fULL) -+ + (value & 0x0f0f0f0f0f0f0f0fULL); -+ value = ((value >> 8) & 0x00ff00ff00ff00ffULL) -+ + (value & 0x00ff00ff00ff00ffULL); -+ value = ((value >> 16) & 0x0000ffff0000ffffULL) -+ + (value & 0x0000ffff0000ffffULL); -+ value = ((value >> 32) & 0x00000000ffffffffULL) -+ + (value & 0x00000000ffffffffULL); -+ -+ return value; -+} -+ -+static Bool isImmLogical ( /*OUT*/UInt* n, -+ /*OUT*/UInt* imm_s, /*OUT*/UInt* imm_r, -+ ULong value, UInt width ) -+{ -+ // Test if a given value can be encoded in the immediate field of a -+ // logical instruction. -+ -+ // If it can be encoded, the function returns true, and values -+ // pointed to by n, imm_s and imm_r are updated with immediates -+ // encoded in the format required by the corresponding fields in the -+ // logical instruction. If it can not be encoded, the function -+ // returns false, and the values pointed to by n, imm_s and imm_r -+ // are undefined. -+ vassert(n != NULL && imm_s != NULL && imm_r != NULL); -+ vassert(width == 32 || width == 64); -+ -+ // Logical immediates are encoded using parameters n, imm_s and imm_r using -+ // the following table: -+ // -+ // N imms immr size S R -+ // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) -+ // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) -+ // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) -+ // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) -+ // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) -+ // 0 11110s xxxxxr 2 UInt(s) UInt(r) -+ // (s bits must not be all set) -+ // -+ // A pattern is constructed of size bits, where the least significant S+1 -+ // bits are set. The pattern is rotated right by R, and repeated across a -+ // 32 or 64-bit value, depending on destination register width. -+ // -+ // To test if an arbitrary immediate can be encoded using this scheme, an -+ // iterative algorithm is used. -+ // -+ // TODO: This code does not consider using X/W register overlap to support -+ // 64-bit immediates where the top 32-bits are zero, and the bottom 32-bits -+ // are an encodable logical immediate. -+ -+ // 1. If the value has all set or all clear bits, it can't be encoded. -+ if ((value == 0) || (value == 0xffffffffffffffffULL) || -+ ((width == 32) && (value == 0xffffffff))) { -+ return False; -+ } -+ -+ UInt lead_zero = CountLeadingZeros(value, width); -+ UInt lead_one = CountLeadingZeros(~value, width); -+ UInt trail_zero = CountTrailingZeros(value, width); -+ UInt trail_one = CountTrailingZeros(~value, width); -+ UInt set_bits = CountSetBits(value, width); -+ -+ // The fixed bits in the immediate s field. -+ // If width == 64 (X reg), start at 0xFFFFFF80. -+ // If width == 32 (W reg), start at 0xFFFFFFC0, as the iteration for 64-bit -+ // widths won't be executed. -+ Int imm_s_fixed = (width == 64) ? -128 : -64; -+ Int imm_s_mask = 0x3F; -+ -+ for (;;) { -+ // 2. If the value is two bits wide, it can be encoded. -+ if (width == 2) { -+ *n = 0; -+ *imm_s = 0x3C; -+ *imm_r = (value & 3) - 1; -+ return True; -+ } -+ -+ *n = (width == 64) ? 1 : 0; -+ *imm_s = ((imm_s_fixed | (set_bits - 1)) & imm_s_mask); -+ if ((lead_zero + set_bits) == width) { -+ *imm_r = 0; -+ } else { -+ *imm_r = (lead_zero > 0) ? (width - trail_zero) : lead_one; -+ } -+ -+ // 3. If the sum of leading zeros, trailing zeros and set bits is equal to -+ // the bit width of the value, it can be encoded. -+ if (lead_zero + trail_zero + set_bits == width) { -+ return True; -+ } -+ -+ // 4. If the sum of leading ones, trailing ones and unset bits in the -+ // value is equal to the bit width of the value, it can be encoded. -+ if (lead_one + trail_one + (width - set_bits) == width) { -+ return True; -+ } -+ -+ // 5. If the most-significant half of the bitwise value is equal to the -+ // least-significant half, return to step 2 using the least-significant -+ // half of the value. -+ ULong mask = (1ULL << (width >> 1)) - 1; -+ if ((value & mask) == ((value >> (width >> 1)) & mask)) { -+ width >>= 1; -+ set_bits >>= 1; -+ imm_s_fixed >>= 1; -+ continue; -+ } -+ -+ // 6. Otherwise, the value can't be encoded. -+ return False; -+ } -+} -+ -+ -+/* Create a RIL for the given immediate, if it is representable, or -+ return NULL if not. */ -+ -+static ARM64RIL* mb_mkARM64RIL_I ( ULong imm64 ) -+{ -+ UInt n = 0, imm_s = 0, imm_r = 0; -+ Bool ok = isImmLogical(&n, &imm_s, &imm_r, imm64, 64); -+ if (!ok) return NULL; -+ vassert(n < 2 && imm_s < 64 && imm_r < 64); -+ return ARM64RIL_I13(n, imm_r, imm_s); -+} -+ -+/* So, finally .. */ -+ -+static ARM64RIL* iselIntExpr_RIL ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64RIL* ri = iselIntExpr_RIL_wrk(env, e); -+ /* sanity checks ... */ -+ switch (ri->tag) { -+ case ARM64riL_I13: -+ vassert(ri->ARM64riL.I13.bitN < 2); -+ vassert(ri->ARM64riL.I13.immR < 64); -+ vassert(ri->ARM64riL.I13.immS < 64); -+ return ri; -+ case ARM64riL_R: -+ vassert(hregClass(ri->ARM64riL.R.reg) == HRcInt64); -+ vassert(hregIsVirtual(ri->ARM64riL.R.reg)); -+ return ri; -+ default: -+ vpanic("iselIntExpr_RIL: unknown arm RIL tag"); -+ } -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static ARM64RIL* iselIntExpr_RIL_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I32); -+ -+ /* special case: immediate */ -+ if (e->tag == Iex_Const) { -+ ARM64RIL* maybe = NULL; -+ if (ty == Ity_I64) { -+ vassert(e->Iex.Const.con->tag == Ico_U64); -+ maybe = mb_mkARM64RIL_I(e->Iex.Const.con->Ico.U64); -+ } else { -+ vassert(ty == Ity_I32); -+ vassert(e->Iex.Const.con->tag == Ico_U32); -+ UInt u32 = e->Iex.Const.con->Ico.U32; -+ ULong u64 = (ULong)u32; -+ /* First try with 32 leading zeroes. */ -+ maybe = mb_mkARM64RIL_I(u64); -+ /* If that doesn't work, try with 2 copies, since it doesn't -+ matter what winds up in the upper 32 bits. */ -+ if (!maybe) { -+ maybe = mb_mkARM64RIL_I((u64 << 32) | u64); -+ } -+ } -+ if (maybe) return maybe; -+ /* else fail, fall through to default case */ -+ } -+ -+ /* default case: calculate into a register and return that */ -+ { -+ HReg r = iselIntExpr_R ( env, e ); -+ return ARM64RIL_R(r); -+ } -+} -+ -+ -+/* --------------------- RI6 --------------------- */ -+ -+/* Select instructions to generate 'e' into a RI6. */ -+ -+static ARM64RI6* iselIntExpr_RI6 ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64RI6* ri = iselIntExpr_RI6_wrk(env, e); -+ /* sanity checks ... */ -+ switch (ri->tag) { -+ case ARM64ri6_I6: -+ vassert(ri->ARM64ri6.I6.imm6 < 64); -+ vassert(ri->ARM64ri6.I6.imm6 > 0); -+ return ri; -+ case ARM64ri6_R: -+ vassert(hregClass(ri->ARM64ri6.R.reg) == HRcInt64); -+ vassert(hregIsVirtual(ri->ARM64ri6.R.reg)); -+ return ri; -+ default: -+ vpanic("iselIntExpr_RI6: unknown arm RI6 tag"); -+ } -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static ARM64RI6* iselIntExpr_RI6_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I8); -+ -+ /* special case: immediate */ -+ if (e->tag == Iex_Const) { -+ switch (e->Iex.Const.con->tag) { -+ case Ico_U8: { -+ UInt u = e->Iex.Const.con->Ico.U8; -+ if (u > 0 && u < 64) -+ return ARM64RI6_I6(u); -+ break; -+ default: -+ break; -+ } -+ } -+ /* else fail, fall through to default case */ -+ } -+ -+ /* default case: calculate into a register and return that */ -+ { -+ HReg r = iselIntExpr_R ( env, e ); -+ return ARM64RI6_R(r); -+ } -+} -+ -+ -+/* ------------------- CondCode ------------------- */ -+ -+/* Generate code to evaluated a bit-typed expression, returning the -+ condition code which would correspond when the expression would -+ notionally have returned 1. */ -+ -+static ARM64CondCode iselCondCode ( ISelEnv* env, IRExpr* e ) -+{ -+ ARM64CondCode cc = iselCondCode_wrk(env,e); -+ vassert(cc != ARM64cc_NV); -+ return cc; -+} -+ -+static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ vassert(e); -+ vassert(typeOfIRExpr(env->type_env,e) == Ity_I1); -+ -+ /* var */ -+ if (e->tag == Iex_RdTmp) { -+ HReg rTmp = lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ /* Cmp doesn't modify rTmp; so this is OK. */ -+ ARM64RIL* one = mb_mkARM64RIL_I(1); -+ vassert(one); -+ addInstr(env, ARM64Instr_Test(rTmp, one)); -+ return ARM64cc_NE; -+ } -+ -+ /* Not1(e) */ -+ if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) { -+ /* Generate code for the arg, and negate the test condition */ -+ ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg); -+ if (cc == ARM64cc_AL || cc == ARM64cc_NV) { -+ return ARM64cc_AL; -+ } else { -+ return 1 ^ cc; -+ } -+ } -+ -+ /* --- patterns rooted at: 64to1 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_64to1) { -+ HReg rTmp = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIL* one = mb_mkARM64RIL_I(1); -+ vassert(one); /* '1' must be representable */ -+ addInstr(env, ARM64Instr_Test(rTmp, one)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- patterns rooted at: CmpNEZ8 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_CmpNEZ8) { -+ HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIL* xFF = mb_mkARM64RIL_I(0xFF); -+ addInstr(env, ARM64Instr_Test(r1, xFF)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- patterns rooted at: CmpNEZ64 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_CmpNEZ64) { -+ HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIA* zero = ARM64RIA_I12(0,0); -+ addInstr(env, ARM64Instr_Cmp(r1, zero, True/*is64*/)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- patterns rooted at: CmpNEZ32 --- */ -+ -+ if (e->tag == Iex_Unop -+ && e->Iex.Unop.op == Iop_CmpNEZ32) { -+ HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg); -+ ARM64RIA* zero = ARM64RIA_I12(0,0); -+ addInstr(env, ARM64Instr_Cmp(r1, zero, False/*!is64*/)); -+ return ARM64cc_NE; -+ } -+ -+ /* --- Cmp*64*(x,y) --- */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_CmpEQ64 -+ || e->Iex.Binop.op == Iop_CmpNE64 -+ || e->Iex.Binop.op == Iop_CmpLT64S -+ || e->Iex.Binop.op == Iop_CmpLT64U -+ || e->Iex.Binop.op == Iop_CmpLE64S -+ || e->Iex.Binop.op == Iop_CmpLE64U)) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Cmp(argL, argR, True/*is64*/)); -+ switch (e->Iex.Binop.op) { -+ case Iop_CmpEQ64: return ARM64cc_EQ; -+ case Iop_CmpNE64: return ARM64cc_NE; -+ case Iop_CmpLT64S: return ARM64cc_LT; -+ case Iop_CmpLT64U: return ARM64cc_CC; -+ case Iop_CmpLE64S: return ARM64cc_LE; -+ case Iop_CmpLE64U: return ARM64cc_LS; -+ default: vpanic("iselCondCode(arm64): CmpXX64"); -+ } -+ } -+ -+ /* --- Cmp*32*(x,y) --- */ -+ if (e->tag == Iex_Binop -+ && (e->Iex.Binop.op == Iop_CmpEQ32 -+ || e->Iex.Binop.op == Iop_CmpNE32 -+ || e->Iex.Binop.op == Iop_CmpLT32S -+ || e->Iex.Binop.op == Iop_CmpLT32U -+ || e->Iex.Binop.op == Iop_CmpLE32S -+ || e->Iex.Binop.op == Iop_CmpLE32U)) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Cmp(argL, argR, False/*!is64*/)); -+ switch (e->Iex.Binop.op) { -+ case Iop_CmpEQ32: return ARM64cc_EQ; -+ case Iop_CmpNE32: return ARM64cc_NE; -+ case Iop_CmpLT32S: return ARM64cc_LT; -+ case Iop_CmpLT32U: return ARM64cc_CC; -+ case Iop_CmpLE32S: return ARM64cc_LE; -+ case Iop_CmpLE32U: return ARM64cc_LS; -+ default: vpanic("iselCondCode(arm64): CmpXX32"); -+ } -+ } -+ -+//ZZ /* const */ -+//ZZ /* Constant 1:Bit */ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ HReg r; -+//ZZ vassert(e->Iex.Const.con->tag == Ico_U1); -+//ZZ vassert(e->Iex.Const.con->Ico.U1 == True -+//ZZ || e->Iex.Const.con->Ico.U1 == False); -+//ZZ r = newVRegI(env); -+//ZZ addInstr(env, ARMInstr_Imm32(r, 0)); -+//ZZ addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, r, ARMRI84_R(r))); -+//ZZ return e->Iex.Const.con->Ico.U1 ? ARMcc_EQ : ARMcc_NE; -+//ZZ } -+//ZZ -+//ZZ // JRS 2013-Jan-03: this seems completely nonsensical -+//ZZ /* --- CasCmpEQ* --- */ -+//ZZ /* Ist_Cas has a dummy argument to compare with, so comparison is -+//ZZ always true. */ -+//ZZ //if (e->tag == Iex_Binop -+//ZZ // && (e->Iex.Binop.op == Iop_CasCmpEQ32 -+//ZZ // || e->Iex.Binop.op == Iop_CasCmpEQ16 -+//ZZ // || e->Iex.Binop.op == Iop_CasCmpEQ8)) { -+//ZZ // return ARMcc_AL; -+//ZZ //} -+ -+ ppIRExpr(e); -+ vpanic("iselCondCode"); -+} -+ -+ -+/* --------------------- Reg --------------------- */ -+ -+static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselIntExpr_R_wrk(env, e); -+ /* sanity checks ... */ -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(r) == HRcInt64); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8); -+ -+ switch (e->tag) { -+ -+ /* --------- TEMP --------- */ -+ case Iex_RdTmp: { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ /* --------- LOAD --------- */ -+ case Iex_Load: { -+ HReg dst = newVRegI(env); -+ -+ if (e->Iex.Load.end != Iend_LE) -+ goto irreducible; -+ -+ if (ty == Ity_I64) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt64(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ if (ty == Ity_I32) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ if (ty == Ity_I16) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt16(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ if (ty == Ity_I8) { -+ ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty ); -+ addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, amode)); -+ return dst; -+ } -+ break; -+ } -+ -+ /* --------- BINARY OP --------- */ -+ case Iex_Binop: { -+ -+ ARM64LogicOp lop = 0; /* invalid */ -+ ARM64ShiftOp sop = 0; /* invalid */ -+ -+ /* Special-case 0-x into a Neg instruction. Not because it's -+ particularly useful but more so as to give value flow using -+ this instruction, so as to check its assembly correctness for -+ implementation of Left32/Left64. */ -+ switch (e->Iex.Binop.op) { -+ case Iop_Sub64: -+ if (isZeroU64(e->Iex.Binop.arg1)) { -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Unary(dst, argR, ARM64un_NEG)); -+ return dst; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ /* ADD/SUB */ -+ switch (e->Iex.Binop.op) { -+ case Iop_Add64: case Iop_Add32: -+ case Iop_Sub64: case Iop_Sub32: { -+ Bool isAdd = e->Iex.Binop.op == Iop_Add64 -+ || e->Iex.Binop.op == Iop_Add32; -+ HReg dst = newVRegI(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Arith(dst, argL, argR, isAdd)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ -+ /* AND/OR/XOR */ -+ switch (e->Iex.Binop.op) { -+ case Iop_And64: case Iop_And32: lop = ARM64lo_AND; goto log_binop; -+ case Iop_Or64: case Iop_Or32: lop = ARM64lo_OR; goto log_binop; -+ case Iop_Xor64: case Iop_Xor32: lop = ARM64lo_XOR; goto log_binop; -+ log_binop: { -+ HReg dst = newVRegI(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RIL* argR = iselIntExpr_RIL(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Logic(dst, argL, argR, lop)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ -+ /* SHL/SHR/SAR */ -+ switch (e->Iex.Binop.op) { -+ case Iop_Shr64: sop = ARM64sh_SHR; goto sh_binop; -+ case Iop_Sar64: sop = ARM64sh_SAR; goto sh_binop; -+ case Iop_Shl64: case Iop_Shl32: sop = ARM64sh_SHL; goto sh_binop; -+ sh_binop: { -+ HReg dst = newVRegI(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RI6* argR = iselIntExpr_RI6(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_Shift(dst, argL, argR, sop)); -+ return dst; -+ } -+ case Iop_Shr32: -+ case Iop_Sar32: { -+ Bool zx = e->Iex.Binop.op == Iop_Shr32; -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ ARM64RI6* argR = iselIntExpr_RI6(env, e->Iex.Binop.arg2); -+ HReg dst = zx ? widen_z_32_to_64(env, argL) -+ : widen_s_32_to_64(env, argL); -+ addInstr(env, ARM64Instr_Shift(dst, dst, argR, ARM64sh_SHR)); -+ return dst; -+ } -+ default: break; -+ } -+ -+ /* MUL */ -+ if (e->Iex.Binop.op == Iop_Mul64 || e->Iex.Binop.op == Iop_Mul32) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Mul(dst, argL, argR, ARM64mul_PLAIN)); -+ return dst; -+ } -+ -+ /* MULL */ -+ if (e->Iex.Binop.op == Iop_MullU32 || e->Iex.Binop.op == Iop_MullS32) { -+ Bool isS = e->Iex.Binop.op == Iop_MullS32; -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg extL = (isS ? widen_s_32_to_64 : widen_z_32_to_64)(env, argL); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg extR = (isS ? widen_s_32_to_64 : widen_z_32_to_64)(env, argR); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Mul(dst, extL, extR, ARM64mul_PLAIN)); -+ return dst; -+ } -+ -+ /* Handle misc other ops. */ -+ -+ if (e->Iex.Binop.op == Iop_Max32U) { -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Cmp(argL, ARM64RIA_R(argR), False/*!is64*/)); -+ addInstr(env, ARM64Instr_CSel(dst, argL, argR, ARM64cc_CS)); -+ return dst; -+ } -+ -+ if (e->Iex.Binop.op == Iop_32HLto64) { -+ HReg hi32s = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg lo32s = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg lo32 = widen_z_32_to_64(env, lo32s); -+ HReg hi32 = newVRegI(env); -+ addInstr(env, ARM64Instr_Shift(hi32, hi32s, ARM64RI6_I6(32), -+ ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Logic(hi32, hi32, ARM64RIL_R(lo32), -+ ARM64lo_OR)); -+ return hi32; -+ } -+ -+ if (e->Iex.Binop.op == Iop_CmpF64 || e->Iex.Binop.op == Iop_CmpF32) { -+ Bool isD = e->Iex.Binop.op == Iop_CmpF64; -+ HReg dL = (isD ? iselDblExpr : iselFltExpr)(env, e->Iex.Binop.arg1); -+ HReg dR = (isD ? iselDblExpr : iselFltExpr)(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ HReg imm = newVRegI(env); -+ /* Do the compare (FCMP), which sets NZCV in PSTATE. Then -+ create in dst, the IRCmpF64Result encoded result. */ -+ addInstr(env, (isD ? ARM64Instr_VCmpD : ARM64Instr_VCmpS)(dL, dR)); -+ addInstr(env, ARM64Instr_Imm64(dst, 0)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x40)); // 0x40 = Ircr_EQ -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_EQ)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x01)); // 0x01 = Ircr_LT -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_MI)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x00)); // 0x00 = Ircr_GT -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_GT)); -+ addInstr(env, ARM64Instr_Imm64(imm, 0x45)); // 0x45 = Ircr_UN -+ addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_VS)); -+ return dst; -+ } -+ -+ { /* local scope */ -+ ARM64CvtOp cvt_op = ARM64cvt_INVALID; -+ Bool srcIsD = False; -+ switch (e->Iex.Binop.op) { -+ case Iop_F64toI64S: -+ cvt_op = ARM64cvt_F64_I64S; srcIsD = True; break; -+ case Iop_F64toI64U: -+ cvt_op = ARM64cvt_F64_I64U; srcIsD = True; break; -+ case Iop_F64toI32S: -+ cvt_op = ARM64cvt_F64_I32S; srcIsD = True; break; -+ case Iop_F64toI32U: -+ cvt_op = ARM64cvt_F64_I32U; srcIsD = True; break; -+ case Iop_F32toI32S: -+ cvt_op = ARM64cvt_F32_I32S; srcIsD = False; break; -+ case Iop_F32toI32U: -+ cvt_op = ARM64cvt_F32_I32U; srcIsD = False; break; -+ case Iop_F32toI64S: -+ cvt_op = ARM64cvt_F32_I64S; srcIsD = False; break; -+ case Iop_F32toI64U: -+ cvt_op = ARM64cvt_F32_I64U; srcIsD = False; break; -+ default: -+ break; -+ } -+ if (cvt_op != ARM64cvt_INVALID) { -+ /* This is all a bit dodgy, because we can't handle a -+ non-constant (not-known-at-JIT-time) rounding mode -+ indication. That's because there's no instruction -+ AFAICS that does this conversion but rounds according to -+ FPCR.RM, so we have to bake the rounding mode into the -+ instruction right now. But that should be OK because -+ (1) the front end attaches a literal Irrm_ value to the -+ conversion binop, and (2) iropt will never float that -+ off via CSE, into a literal. Hence we should always -+ have an Irrm_ value as the first arg. */ -+ IRExpr* arg1 = e->Iex.Binop.arg1; -+ if (arg1->tag != Iex_Const) goto irreducible; -+ IRConst* arg1con = arg1->Iex.Const.con; -+ vassert(arg1con->tag == Ico_U32); // else ill-typed IR -+ UInt irrm = arg1con->Ico.U32; -+ /* Find the ARM-encoded equivalent for |irrm|. */ -+ UInt armrm = 4; /* impossible */ -+ switch (irrm) { -+ case Irrm_NEAREST: armrm = 0; break; -+ case Irrm_NegINF: armrm = 2; break; -+ case Irrm_PosINF: armrm = 1; break; -+ case Irrm_ZERO: armrm = 3; break; -+ default: goto irreducible; -+ } -+ HReg src = (srcIsD ? iselDblExpr : iselFltExpr) -+ (env, e->Iex.Binop.arg2); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_VCvtF2I(cvt_op, dst, src, armrm)); -+ return dst; -+ } -+ } /* local scope */ -+ -+//ZZ if (e->Iex.Binop.op == Iop_GetElem8x8 -+//ZZ || e->Iex.Binop.op == Iop_GetElem16x4 -+//ZZ || e->Iex.Binop.op == Iop_GetElem32x2) { -+//ZZ HReg res = newVRegI(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt index, size; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM target supports GetElem with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_GetElem8x8: vassert(index < 8); size = 0; break; -+//ZZ case Iop_GetElem16x4: vassert(index < 4); size = 1; break; -+//ZZ case Iop_GetElem32x2: vassert(index < 2); size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ if (e->Iex.Binop.op == Iop_GetElem8x16 -+//ZZ || e->Iex.Binop.op == Iop_GetElem16x8 -+//ZZ || e->Iex.Binop.op == Iop_GetElem32x4) { -+//ZZ HReg res = newVRegI(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt index, size; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM target supports GetElem with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_GetElem8x16: vassert(index < 16); size = 0; break; -+//ZZ case Iop_GetElem16x8: vassert(index < 8); size = 1; break; -+//ZZ case Iop_GetElem32x4: vassert(index < 4); size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ size, True)); -+//ZZ return res; -+//ZZ } -+ -+ /* All cases involving host-side helper calls. */ -+ void* fn = NULL; -+ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Add16x2: -+//ZZ fn = &h_generic_calc_Add16x2; break; -+//ZZ case Iop_Sub16x2: -+//ZZ fn = &h_generic_calc_Sub16x2; break; -+//ZZ case Iop_HAdd16Ux2: -+//ZZ fn = &h_generic_calc_HAdd16Ux2; break; -+//ZZ case Iop_HAdd16Sx2: -+//ZZ fn = &h_generic_calc_HAdd16Sx2; break; -+//ZZ case Iop_HSub16Ux2: -+//ZZ fn = &h_generic_calc_HSub16Ux2; break; -+//ZZ case Iop_HSub16Sx2: -+//ZZ fn = &h_generic_calc_HSub16Sx2; break; -+//ZZ case Iop_QAdd16Sx2: -+//ZZ fn = &h_generic_calc_QAdd16Sx2; break; -+//ZZ case Iop_QAdd16Ux2: -+//ZZ fn = &h_generic_calc_QAdd16Ux2; break; -+//ZZ case Iop_QSub16Sx2: -+//ZZ fn = &h_generic_calc_QSub16Sx2; break; -+//ZZ case Iop_Add8x4: -+//ZZ fn = &h_generic_calc_Add8x4; break; -+//ZZ case Iop_Sub8x4: -+//ZZ fn = &h_generic_calc_Sub8x4; break; -+//ZZ case Iop_HAdd8Ux4: -+//ZZ fn = &h_generic_calc_HAdd8Ux4; break; -+//ZZ case Iop_HAdd8Sx4: -+//ZZ fn = &h_generic_calc_HAdd8Sx4; break; -+//ZZ case Iop_HSub8Ux4: -+//ZZ fn = &h_generic_calc_HSub8Ux4; break; -+//ZZ case Iop_HSub8Sx4: -+//ZZ fn = &h_generic_calc_HSub8Sx4; break; -+//ZZ case Iop_QAdd8Sx4: -+//ZZ fn = &h_generic_calc_QAdd8Sx4; break; -+//ZZ case Iop_QAdd8Ux4: -+//ZZ fn = &h_generic_calc_QAdd8Ux4; break; -+//ZZ case Iop_QSub8Sx4: -+//ZZ fn = &h_generic_calc_QSub8Sx4; break; -+//ZZ case Iop_QSub8Ux4: -+//ZZ fn = &h_generic_calc_QSub8Ux4; break; -+//ZZ case Iop_Sad8Ux4: -+//ZZ fn = &h_generic_calc_Sad8Ux4; break; -+//ZZ case Iop_QAdd32S: -+//ZZ fn = &h_generic_calc_QAdd32S; break; -+//ZZ case Iop_QSub32S: -+//ZZ fn = &h_generic_calc_QSub32S; break; -+//ZZ case Iop_QSub16Ux2: -+//ZZ fn = &h_generic_calc_QSub16Ux2; break; -+ case Iop_DivU32: -+ fn = &h_calc_udiv32_w_arm_semantics; break; -+ case Iop_DivS32: -+ fn = &h_calc_sdiv32_w_arm_semantics; break; -+ case Iop_DivU64: -+ fn = &h_calc_udiv64_w_arm_semantics; break; -+ case Iop_DivS64: -+ fn = &h_calc_sdiv64_w_arm_semantics; break; -+ default: -+ break; -+ } -+ -+ if (fn) { -+ HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg res = newVRegI(env); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X0(), regL)); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X1(), regR)); -+ addInstr(env, ARM64Instr_Call( ARM64cc_AL, (HWord)Ptr_to_ULong(fn), -+ 2, mk_RetLoc_simple(RLPri_Int) )); -+ addInstr(env, ARM64Instr_MovI(res, hregARM64_X0())); -+ return res; -+ } -+ -+ break; -+ } -+ -+ /* --------- UNARY OP --------- */ -+ case Iex_Unop: { -+ -+ switch (e->Iex.Unop.op) { -+ case Iop_16Uto64: { -+ /* This probably doesn't occur often enough to be worth -+ rolling the extension into the load. */ -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_z_16_to_64(env, src); -+ return dst; -+ } -+ case Iop_32Uto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ if (arg->tag == Iex_Load) { -+ /* This correctly zero extends because _LdSt32 is -+ defined to do a zero extending load. */ -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I32); -+ addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ /* else be lame and mask it */ -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_z_32_to_64(env, src); -+ return dst; -+ } -+ case Iop_8Uto32: /* Just freeload on the 8Uto64 case */ -+ case Iop_8Uto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ if (arg->tag == Iex_Load) { -+ /* This correctly zero extends because _LdSt8 is -+ defined to do a zero extending load. */ -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I8); -+ addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ /* else be lame and mask it */ -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_z_8_to_64(env, src); -+ return dst; -+ } -+ case Iop_128HIto64: { -+ HReg rHi, rLo; -+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+ return rHi; /* and abandon rLo */ -+ } -+ case Iop_8Sto32: case Iop_8Sto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_s_8_to_64(env, src); -+ return dst; -+ } -+ case Iop_16Sto32: case Iop_16Sto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_s_16_to_64(env, src); -+ return dst; -+ } -+ case Iop_32Sto64: { -+ IRExpr* arg = e->Iex.Unop.arg; -+ HReg src = iselIntExpr_R(env, arg); -+ HReg dst = widen_s_32_to_64(env, src); -+ return dst; -+ } -+ case Iop_Not32: -+ case Iop_Not64: { -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NOT)); -+ return dst; -+ } -+ case Iop_Clz64: { -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_CLZ)); -+ return dst; -+ } -+ case Iop_Left32: -+ case Iop_Left64: { -+ /* Left64(src) = src | -src. Left32 can use the same -+ implementation since in that case we don't care what -+ the upper 32 bits become. */ -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG)); -+ addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src), -+ ARM64lo_OR)); -+ return dst; -+ } -+ case Iop_CmpwNEZ64: { -+ /* CmpwNEZ64(src) = (src == 0) ? 0...0 : 1...1 -+ = Left64(src) >>s 63 */ -+ HReg dst = newVRegI(env); -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG)); -+ addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src), -+ ARM64lo_OR)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SAR)); -+ return dst; -+ } -+ case Iop_CmpwNEZ32: { -+ /* CmpwNEZ32(src) = CmpwNEZ64(src & 0xFFFFFFFF) -+ = Left64(src & 0xFFFFFFFF) >>s 63 */ -+ HReg dst = newVRegI(env); -+ HReg pre = iselIntExpr_R(env, e->Iex.Unop.arg); -+ HReg src = widen_z_32_to_64(env, pre); -+ addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG)); -+ addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src), -+ ARM64lo_OR)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SAR)); -+ return dst; -+ } -+ case Iop_V128to64: case Iop_V128HIto64: { -+ HReg dst = newVRegI(env); -+ HReg src = iselV128Expr(env, e->Iex.Unop.arg); -+ UInt laneNo = (e->Iex.Unop.op == Iop_V128HIto64) ? 1 : 0; -+ addInstr(env, ARM64Instr_VXfromQ(dst, src, laneNo)); -+ return dst; -+ } -+ case Iop_1Sto32: -+ case Iop_1Sto64: { -+ /* As with the iselStmt case for 'tmp:I1 = expr', we could -+ do a lot better here if it ever became necessary. */ -+ HReg zero = newVRegI(env); -+ HReg one = newVRegI(env); -+ HReg dst = newVRegI(env); -+ addInstr(env, ARM64Instr_Imm64(zero, 0)); -+ addInstr(env, ARM64Instr_Imm64(one, 1)); -+ ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_CSel(dst, one, zero, cc)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SHL)); -+ addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63), -+ ARM64sh_SAR)); -+ return dst; -+ } -+ case Iop_NarrowUn16to8x8: -+ case Iop_NarrowUn32to16x4: -+ case Iop_NarrowUn64to32x2: { -+ HReg src = iselV128Expr(env, e->Iex.Unop.arg); -+ HReg tmp = newVRegV(env); -+ HReg dst = newVRegI(env); -+ UInt dszBlg2 = 3; /* illegal */ -+ switch (e->Iex.Unop.op) { -+ case Iop_NarrowUn16to8x8: dszBlg2 = 0; break; // 16to8_x8 -+ case Iop_NarrowUn32to16x4: dszBlg2 = 1; break; // 32to16_x4 -+ case Iop_NarrowUn64to32x2: dszBlg2 = 2; break; // 64to32_x2 -+ default: vassert(0); -+ } -+ addInstr(env, ARM64Instr_VNarrowV(dszBlg2, tmp, src)); -+ addInstr(env, ARM64Instr_VXfromQ(dst, tmp, 0/*laneNo*/)); -+ return dst; -+ } -+//ZZ case Iop_64HIto32: { -+//ZZ HReg rHi, rLo; -+//ZZ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+//ZZ return rHi; /* and abandon rLo .. poor wee thing :-) */ -+//ZZ } -+//ZZ case Iop_64to32: { -+//ZZ HReg rHi, rLo; -+//ZZ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+//ZZ return rLo; /* similar stupid comment to the above ... */ -+//ZZ } -+//ZZ case Iop_64to8: { -+//ZZ HReg rHi, rLo; -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); -+//ZZ rHi = tHi; -+//ZZ rLo = tLo; -+//ZZ } else { -+//ZZ iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg); -+//ZZ } -+//ZZ return rLo; -+//ZZ } -+ -+ case Iop_1Uto64: { -+ /* 1Uto64(tmp). */ -+ HReg dst = newVRegI(env); -+ if (e->Iex.Unop.arg->tag == Iex_RdTmp) { -+ ARM64RIL* one = mb_mkARM64RIL_I(1); -+ HReg src = lookupIRTemp(env, e->Iex.Unop.arg->Iex.RdTmp.tmp); -+ vassert(one); -+ addInstr(env, ARM64Instr_Logic(dst, src, one, ARM64lo_AND)); -+ } else { -+ /* CLONE-01 */ -+ HReg zero = newVRegI(env); -+ HReg one = newVRegI(env); -+ addInstr(env, ARM64Instr_Imm64(zero, 0)); -+ addInstr(env, ARM64Instr_Imm64(one, 1)); -+ ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg); -+ addInstr(env, ARM64Instr_CSel(dst, one, zero, cc)); -+ } -+ return dst; -+ } -+//ZZ case Iop_1Uto8: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); -+//ZZ addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_1Sto32: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+//ZZ ARMRI5* amt = ARMRI5_I5(31); -+//ZZ /* This is really rough. We could do much better here; -+//ZZ perhaps mvn{cond} dst, #0 as the second insn? -+//ZZ (same applies to 1Sto64) */ -+//ZZ addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); -+//ZZ addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt)); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt)); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_Clz32: { -+//ZZ /* Count leading zeroes; easy on ARM. */ -+//ZZ HReg dst = newVRegI(env); -+//ZZ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_CLZ, dst, src)); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_CmpwNEZ32: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src)); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, ARMRI5_I5(31))); -+//ZZ return dst; -+//ZZ } -+//ZZ -+//ZZ case Iop_ReinterpF32asI32: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferS(False/*!toS*/, src, dst)); -+//ZZ return dst; -+//ZZ } -+ -+ case Iop_64to32: -+ case Iop_64to16: -+ case Iop_64to8: -+ /* These are no-ops. */ -+ return iselIntExpr_R(env, e->Iex.Unop.arg); -+ -+ default: -+ break; -+ } -+ -+//ZZ /* All Unop cases involving host-side helper calls. */ -+//ZZ void* fn = NULL; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_CmpNEZ16x2: -+//ZZ fn = &h_generic_calc_CmpNEZ16x2; break; -+//ZZ case Iop_CmpNEZ8x4: -+//ZZ fn = &h_generic_calc_CmpNEZ8x4; break; -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ -+//ZZ if (fn) { -+//ZZ HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ HReg res = newVRegI(env); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R0(), arg)); -+//ZZ addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), -+//ZZ 1, RetLocInt )); -+//ZZ addInstr(env, mk_iMOVds_RR(res, hregARM_R0())); -+//ZZ return res; -+//ZZ } -+ -+ break; -+ } -+ -+ /* --------- GET --------- */ -+ case Iex_Get: { -+ if (ty == Ity_I64 -+ && 0 == (e->Iex.Get.offset & 7) && e->Iex.Get.offset < (8<<12)-8) { -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = mk_baseblock_64bit_access_amode(e->Iex.Get.offset); -+ addInstr(env, ARM64Instr_LdSt64(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ if (ty == Ity_I32 -+ && 0 == (e->Iex.Get.offset & 3) && e->Iex.Get.offset < (4<<12)-4) { -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = mk_baseblock_32bit_access_amode(e->Iex.Get.offset); -+ addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ if (ty == Ity_I16 -+ && 0 == (e->Iex.Get.offset & 1) && e->Iex.Get.offset < (2<<12)-2) { -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = mk_baseblock_16bit_access_amode(e->Iex.Get.offset); -+ addInstr(env, ARM64Instr_LdSt16(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ if (ty == Ity_I8 -+ /* && no alignment check */ && e->Iex.Get.offset < (1<<12)-1) { -+ HReg dst = newVRegI(env); -+ ARM64AMode* am -+ = mk_baseblock_8bit_access_amode(e->Iex.Get.offset); -+ addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, am)); -+ return dst; -+ } -+ break; -+ } -+ -+ /* --------- CCALL --------- */ -+ case Iex_CCall: { -+ HReg dst = newVRegI(env); -+ vassert(ty == e->Iex.CCall.retty); -+ -+ /* be very restrictive for now. Only 64-bit ints allowed for -+ args, and 64 bits for return type. Don't forget to change -+ the RetLoc if more types are allowed in future. */ -+ if (e->Iex.CCall.retty != Ity_I64) -+ goto irreducible; -+ -+ /* Marshal args, do the call, clear stack. */ -+ UInt addToSp = 0; -+ RetLoc rloc = mk_RetLoc_INVALID(); -+ Bool ok = doHelperCall( &addToSp, &rloc, env, NULL/*guard*/, -+ e->Iex.CCall.cee, e->Iex.CCall.retty, -+ e->Iex.CCall.args ); -+ /* */ -+ if (ok) { -+ vassert(is_sane_RetLoc(rloc)); -+ vassert(rloc.pri == RLPri_Int); -+ vassert(addToSp == 0); -+ addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0())); -+ return dst; -+ } -+ /* else fall through; will hit the irreducible: label */ -+ } -+ -+ /* --------- LITERAL --------- */ -+ /* 64-bit literals */ -+ case Iex_Const: { -+ ULong u = 0; -+ HReg dst = newVRegI(env); -+ switch (e->Iex.Const.con->tag) { -+ case Ico_U64: u = e->Iex.Const.con->Ico.U64; break; -+ case Ico_U32: u = e->Iex.Const.con->Ico.U32; break; -+ case Ico_U16: u = e->Iex.Const.con->Ico.U16; break; -+ case Ico_U8: u = e->Iex.Const.con->Ico.U8; break; -+ default: ppIRExpr(e); vpanic("iselIntExpr_R.Iex_Const(arm64)"); -+ } -+ addInstr(env, ARM64Instr_Imm64(dst, u)); -+ return dst; -+ } -+ -+ /* --------- MULTIPLEX --------- */ -+ case Iex_ITE: { -+ /* ITE(ccexpr, iftrue, iffalse) */ -+ if (ty == Ity_I64 || ty == Ity_I32) { -+ ARM64CondCode cc; -+ HReg r1 = iselIntExpr_R(env, e->Iex.ITE.iftrue); -+ HReg r0 = iselIntExpr_R(env, e->Iex.ITE.iffalse); -+ HReg dst = newVRegI(env); -+ cc = iselCondCode(env, e->Iex.ITE.cond); -+ addInstr(env, ARM64Instr_CSel(dst, r1, r0, cc)); -+ return dst; -+ } -+ break; -+ } -+ -+ default: -+ break; -+ } /* switch (e->tag) */ -+ -+ /* We get here if no pattern matched. */ -+ irreducible: -+ ppIRExpr(e); -+ vpanic("iselIntExpr_R: cannot reduce tree"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Integer expressions (128 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Compute a 128-bit value into a register pair, which is returned as -+ the first two parameters. As with iselIntExpr_R, these may be -+ either real or virtual regs; in any case they must not be changed -+ by subsequent code emitted by the caller. */ -+ -+static void iselInt128Expr ( HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ) -+{ -+ iselInt128Expr_wrk(rHi, rLo, env, e); -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(*rHi) == HRcInt64); -+ vassert(hregIsVirtual(*rHi)); -+ vassert(hregClass(*rLo) == HRcInt64); -+ vassert(hregIsVirtual(*rLo)); -+} -+ -+/* DO NOT CALL THIS DIRECTLY ! */ -+static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo, -+ ISelEnv* env, IRExpr* e ) -+{ -+ vassert(e); -+ vassert(typeOfIRExpr(env->type_env,e) == Ity_I128); -+ -+ /* --------- BINARY ops --------- */ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ /* 64 x 64 -> 128 multiply */ -+ case Iop_MullU64: -+ case Iop_MullS64: { -+ Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ HReg dstLo = newVRegI(env); -+ HReg dstHi = newVRegI(env); -+ addInstr(env, ARM64Instr_Mul(dstLo, argL, argR, -+ ARM64mul_PLAIN)); -+ addInstr(env, ARM64Instr_Mul(dstHi, argL, argR, -+ syned ? ARM64mul_SX : ARM64mul_ZX)); -+ *rHi = dstHi; -+ *rLo = dstLo; -+ return; -+ } -+ /* 64HLto128(e1,e2) */ -+ case Iop_64HLto128: -+ *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ return; -+ default: -+ break; -+ } -+ } /* if (e->tag == Iex_Binop) */ -+ -+ ppIRExpr(e); -+ vpanic("iselInt128Expr(arm64)"); -+} -+ -+ -+//ZZ /* -------------------- 64-bit -------------------- */ -+//ZZ -+//ZZ /* Compute a 64-bit value into a register pair, which is returned as -+//ZZ the first two parameters. As with iselIntExpr_R, these may be -+//ZZ either real or virtual regs; in any case they must not be changed -+//ZZ by subsequent code emitted by the caller. */ -+//ZZ -+//ZZ static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ iselInt64Expr_wrk(rHi, rLo, env, e); -+//ZZ # if 0 -+//ZZ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+//ZZ # endif -+//ZZ vassert(hregClass(*rHi) == HRcInt32); -+//ZZ vassert(hregIsVirtual(*rHi)); -+//ZZ vassert(hregClass(*rLo) == HRcInt32); -+//ZZ vassert(hregIsVirtual(*rLo)); -+//ZZ } -+//ZZ -+//ZZ /* DO NOT CALL THIS DIRECTLY ! */ -+//ZZ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ vassert(e); -+//ZZ vassert(typeOfIRExpr(env->type_env,e) == Ity_I64); -+//ZZ -+//ZZ /* 64-bit literal */ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ ULong w64 = e->Iex.Const.con->Ico.U64; -+//ZZ UInt wHi = toUInt(w64 >> 32); -+//ZZ UInt wLo = toUInt(w64); -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ vassert(e->Iex.Const.con->tag == Ico_U64); -+//ZZ addInstr(env, ARMInstr_Imm32(tHi, wHi)); -+//ZZ addInstr(env, ARMInstr_Imm32(tLo, wLo)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* read 64-bit IRTemp */ -+//ZZ if (e->tag == Iex_RdTmp) { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg tmp = iselNeon64Expr(env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ } else { -+//ZZ lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit load */ -+//ZZ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+//ZZ HReg tLo, tHi, rA; -+//ZZ vassert(e->Iex.Load.ty == Ity_I64); -+//ZZ rA = iselIntExpr_R(env, e->Iex.Load.addr); -+//ZZ tHi = newVRegI(env); -+//ZZ tLo = newVRegI(env); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, -+//ZZ tHi, ARMAMode1_RI(rA, 4))); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, -+//ZZ tLo, ARMAMode1_RI(rA, 0))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit GET */ -+//ZZ if (e->tag == Iex_Get) { -+//ZZ ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 0); -+//ZZ ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), e->Iex.Get.offset + 4); -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tHi, am4)); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tLo, am0)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* --------- BINARY ops --------- */ -+//ZZ if (e->tag == Iex_Binop) { -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ -+//ZZ /* 32 x 32 -> 64 multiply */ -+//ZZ case Iop_MullS32: -+//ZZ case Iop_MullU32: { -+//ZZ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ ARMMulOp mop = e->Iex.Binop.op == Iop_MullS32 -+//ZZ ? ARMmul_SX : ARMmul_ZX; -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL)); -+//ZZ addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR)); -+//ZZ addInstr(env, ARMInstr_Mul(mop)); -+//ZZ addInstr(env, mk_iMOVds_RR(tHi, hregARM_R1())); -+//ZZ addInstr(env, mk_iMOVds_RR(tLo, hregARM_R0())); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ case Iop_Or64: { -+//ZZ HReg xLo, xHi, yLo, yHi; -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -+//ZZ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, xHi, ARMRI84_R(yHi))); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, xLo, ARMRI84_R(yLo))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ case Iop_Add64: { -+//ZZ HReg xLo, xHi, yLo, yHi; -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -+//ZZ iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_ADDS, tLo, xLo, ARMRI84_R(yLo))); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_ADC, tHi, xHi, ARMRI84_R(yHi))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* 32HLto64(e1,e2) */ -+//ZZ case Iop_32HLto64: { -+//ZZ *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* --------- UNARY ops --------- */ -+//ZZ if (e->tag == Iex_Unop) { -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ -+//ZZ /* ReinterpF64asI64 */ -+//ZZ case Iop_ReinterpF64asI64: { -+//ZZ HReg dstHi = newVRegI(env); -+//ZZ HReg dstLo = newVRegI(env); -+//ZZ HReg src = iselDblExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferD(False/*!toD*/, src, dstHi, dstLo)); -+//ZZ *rHi = dstHi; -+//ZZ *rLo = dstLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* Left64(e) */ -+//ZZ case Iop_Left64: { -+//ZZ HReg yLo, yHi; -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg zero = newVRegI(env); -+//ZZ /* yHi:yLo = arg */ -+//ZZ iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg); -+//ZZ /* zero = 0 */ -+//ZZ addInstr(env, ARMInstr_Imm32(zero, 0)); -+//ZZ /* tLo = 0 - yLo, and set carry */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_SUBS, -+//ZZ tLo, zero, ARMRI84_R(yLo))); -+//ZZ /* tHi = 0 - yHi - carry */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_SBC, -+//ZZ tHi, zero, ARMRI84_R(yHi))); -+//ZZ /* So now we have tHi:tLo = -arg. To finish off, or 'arg' -+//ZZ back in, so as to give the final result -+//ZZ tHi:tLo = arg | -arg. */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, tHi, ARMRI84_R(yHi))); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, tLo, ARMRI84_R(yLo))); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* CmpwNEZ64(e) */ -+//ZZ case Iop_CmpwNEZ64: { -+//ZZ HReg srcLo, srcHi; -+//ZZ HReg tmp1 = newVRegI(env); -+//ZZ HReg tmp2 = newVRegI(env); -+//ZZ /* srcHi:srcLo = arg */ -+//ZZ iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg); -+//ZZ /* tmp1 = srcHi | srcLo */ -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, -+//ZZ tmp1, srcHi, ARMRI84_R(srcLo))); -+//ZZ /* tmp2 = (tmp1 | -tmp1) >>s 31 */ -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, tmp2, tmp1)); -+//ZZ addInstr(env, ARMInstr_Alu(ARMalu_OR, -+//ZZ tmp2, tmp2, ARMRI84_R(tmp1))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, -+//ZZ tmp2, tmp2, ARMRI5_I5(31))); -+//ZZ *rHi = tmp2; -+//ZZ *rLo = tmp2; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ case Iop_1Sto64: { -+//ZZ HReg dst = newVRegI(env); -+//ZZ ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg); -+//ZZ ARMRI5* amt = ARMRI5_I5(31); -+//ZZ /* This is really rough. We could do much better here; -+//ZZ perhaps mvn{cond} dst, #0 as the second insn? -+//ZZ (same applies to 1Sto32) */ -+//ZZ addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0))); -+//ZZ addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0))); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt)); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt)); -+//ZZ *rHi = dst; -+//ZZ *rLo = dst; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } /* if (e->tag == Iex_Unop) */ -+//ZZ -+//ZZ /* --------- MULTIPLEX --------- */ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ IRType tyC; -+//ZZ HReg r1hi, r1lo, r0hi, r0lo, dstHi, dstLo; -+//ZZ ARMCondCode cc; -+//ZZ tyC = typeOfIRExpr(env->type_env,e->Iex.ITE.cond); -+//ZZ vassert(tyC == Ity_I1); -+//ZZ iselInt64Expr(&r1hi, &r1lo, env, e->Iex.ITE.iftrue); -+//ZZ iselInt64Expr(&r0hi, &r0lo, env, e->Iex.ITE.iffalse); -+//ZZ dstHi = newVRegI(env); -+//ZZ dstLo = newVRegI(env); -+//ZZ addInstr(env, mk_iMOVds_RR(dstHi, r1hi)); -+//ZZ addInstr(env, mk_iMOVds_RR(dstLo, r1lo)); -+//ZZ cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_CMov(cc ^ 1, dstHi, ARMRI84_R(r0hi))); -+//ZZ addInstr(env, ARMInstr_CMov(cc ^ 1, dstLo, ARMRI84_R(r0lo))); -+//ZZ *rHi = dstHi; -+//ZZ *rLo = dstLo; -+//ZZ return; -+//ZZ } -+//ZZ -+//ZZ /* It is convenient sometimes to call iselInt64Expr even when we -+//ZZ have NEON support (e.g. in do_helper_call we need 64-bit -+//ZZ arguments as 2 x 32 regs). */ -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg tHi = newVRegI(env); -+//ZZ HReg tLo = newVRegI(env); -+//ZZ HReg tmp = iselNeon64Expr(env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo)); -+//ZZ *rHi = tHi; -+//ZZ *rLo = tLo; -+//ZZ return ; -+//ZZ } -+//ZZ -+//ZZ ppIRExpr(e); -+//ZZ vpanic("iselInt64Expr"); -+//ZZ } -+//ZZ -+//ZZ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ /*--- ISEL: Vector (NEON) expressions (64 bit) ---*/ -+//ZZ /*---------------------------------------------------------*/ -+//ZZ -+//ZZ static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ HReg r = iselNeon64Expr_wrk( env, e ); -+//ZZ vassert(hregClass(r) == HRcFlt64); -+//ZZ vassert(hregIsVirtual(r)); -+//ZZ return r; -+//ZZ } -+//ZZ -+//ZZ /* DO NOT CALL THIS DIRECTLY */ -+//ZZ static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e ) -+//ZZ { -+//ZZ IRType ty = typeOfIRExpr(env->type_env, e); -+//ZZ MatchInfo mi; -+//ZZ vassert(e); -+//ZZ vassert(ty == Ity_I64); -+//ZZ -+//ZZ if (e->tag == Iex_RdTmp) { -+//ZZ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+//ZZ } -+//ZZ -+//ZZ if (e->tag == Iex_Const) { -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit load */ -+//ZZ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+//ZZ HReg res = newVRegD(env); -+//ZZ ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr); -+//ZZ vassert(ty == Ity_I64); -+//ZZ addInstr(env, ARMInstr_NLdStD(True, res, am)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 64-bit GET */ -+//ZZ if (e->tag == Iex_Get) { -+//ZZ HReg addr = newVRegI(env); -+//ZZ HReg res = newVRegD(env); -+//ZZ vassert(ty == Ity_I64); -+//ZZ addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset)); -+//ZZ addInstr(env, ARMInstr_NLdStD(True, res, mkARMAModeN_R(addr))); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* --------- BINARY ops --------- */ -+//ZZ if (e->tag == Iex_Binop) { -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ -+//ZZ /* 32 x 32 -> 64 multiply */ -+//ZZ case Iop_MullS32: -+//ZZ case Iop_MullU32: { -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_And64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VAND, -+//ZZ res, argL, argR, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Or64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, argL, argR, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Xor64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VXOR, -+//ZZ res, argL, argR, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 32HLto64(e1,e2) */ -+//ZZ case Iop_32HLto64: { -+//ZZ HReg rHi = iselIntExpr_R(env, e->Iex.Binop.arg1); -+//ZZ HReg rLo = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg res = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_Add8x8: -+//ZZ case Iop_Add16x4: -+//ZZ case Iop_Add32x2: -+//ZZ case Iop_Add64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Add8x8: size = 0; break; -+//ZZ case Iop_Add16x4: size = 1; break; -+//ZZ case Iop_Add32x2: size = 2; break; -+//ZZ case Iop_Add64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VADD, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Add32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recps32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrts32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveHI32x2: -+//ZZ case Iop_InterleaveLO32x2: -+//ZZ case Iop_InterleaveOddLanes8x8: -+//ZZ case Iop_InterleaveEvenLanes8x8: -+//ZZ case Iop_InterleaveOddLanes16x4: -+//ZZ case Iop_InterleaveEvenLanes16x4: { -+//ZZ HReg rD = newVRegD(env); -+//ZZ HReg rM = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveOddLanes8x8: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveEvenLanes8x8: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveOddLanes16x4: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveEvenLanes16x4: resRd = True; size = 1; break; -+//ZZ case Iop_InterleaveHI32x2: resRd = False; size = 2; break; -+//ZZ case Iop_InterleaveLO32x2: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, False)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 4 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveHI8x8: -+//ZZ case Iop_InterleaveLO8x8: -+//ZZ case Iop_InterleaveHI16x4: -+//ZZ case Iop_InterleaveLO16x4: { -+//ZZ HReg rD = newVRegD(env); -+//ZZ HReg rM = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveHI8x8: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveLO8x8: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveHI16x4: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveLO16x4: resRd = True; size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, False)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 4 verified 18 Apr 2013 -+//ZZ case Iop_CatOddLanes8x8: -+//ZZ case Iop_CatEvenLanes8x8: -+//ZZ case Iop_CatOddLanes16x4: -+//ZZ case Iop_CatEvenLanes16x4: { -+//ZZ HReg rD = newVRegD(env); -+//ZZ HReg rM = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CatOddLanes8x8: resRd = False; size = 0; break; -+//ZZ case Iop_CatEvenLanes8x8: resRd = True; size = 0; break; -+//ZZ case Iop_CatOddLanes16x4: resRd = False; size = 1; break; -+//ZZ case Iop_CatEvenLanes16x4: resRd = True; size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, False)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ case Iop_QAdd8Ux8: -+//ZZ case Iop_QAdd16Ux4: -+//ZZ case Iop_QAdd32Ux2: -+//ZZ case Iop_QAdd64Ux1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Ux8: size = 0; break; -+//ZZ case Iop_QAdd16Ux4: size = 1; break; -+//ZZ case Iop_QAdd32Ux2: size = 2; break; -+//ZZ case Iop_QAdd64Ux1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QAdd8Sx8: -+//ZZ case Iop_QAdd16Sx4: -+//ZZ case Iop_QAdd32Sx2: -+//ZZ case Iop_QAdd64Sx1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Sx8: size = 0; break; -+//ZZ case Iop_QAdd16Sx4: size = 1; break; -+//ZZ case Iop_QAdd32Sx2: size = 2; break; -+//ZZ case Iop_QAdd64Sx1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub8x8: -+//ZZ case Iop_Sub16x4: -+//ZZ case Iop_Sub32x2: -+//ZZ case Iop_Sub64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sub8x8: size = 0; break; -+//ZZ case Iop_Sub16x4: size = 1; break; -+//ZZ case Iop_Sub32x2: size = 2; break; -+//ZZ case Iop_Sub64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Ux8: -+//ZZ case Iop_QSub16Ux4: -+//ZZ case Iop_QSub32Ux2: -+//ZZ case Iop_QSub64Ux1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Ux8: size = 0; break; -+//ZZ case Iop_QSub16Ux4: size = 1; break; -+//ZZ case Iop_QSub32Ux2: size = 2; break; -+//ZZ case Iop_QSub64Ux1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Sx8: -+//ZZ case Iop_QSub16Sx4: -+//ZZ case Iop_QSub32Sx2: -+//ZZ case Iop_QSub64Sx1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Sx8: size = 0; break; -+//ZZ case Iop_QSub16Sx4: size = 1; break; -+//ZZ case Iop_QSub32Sx2: size = 2; break; -+//ZZ case Iop_QSub64Sx1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Ux8: -+//ZZ case Iop_Max16Ux4: -+//ZZ case Iop_Max32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Ux8: size = 0; break; -+//ZZ case Iop_Max16Ux4: size = 1; break; -+//ZZ case Iop_Max32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Sx8: -+//ZZ case Iop_Max16Sx4: -+//ZZ case Iop_Max32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Sx8: size = 0; break; -+//ZZ case Iop_Max16Sx4: size = 1; break; -+//ZZ case Iop_Max32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Ux8: -+//ZZ case Iop_Min16Ux4: -+//ZZ case Iop_Min32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Ux8: size = 0; break; -+//ZZ case Iop_Min16Ux4: size = 1; break; -+//ZZ case Iop_Min32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Sx8: -+//ZZ case Iop_Min16Sx4: -+//ZZ case Iop_Min32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Sx8: size = 0; break; -+//ZZ case Iop_Min16Sx4: size = 1; break; -+//ZZ case Iop_Min32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sar8x8: -+//ZZ case Iop_Sar16x4: -+//ZZ case Iop_Sar32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegD(env); -+//ZZ HReg zero = newVRegD(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sar8x8: size = 0; break; -+//ZZ case Iop_Sar16x4: size = 1; break; -+//ZZ case Iop_Sar32x2: size = 2; break; -+//ZZ case Iop_Sar64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR2, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sal8x8: -+//ZZ case Iop_Sal16x4: -+//ZZ case Iop_Sal32x2: -+//ZZ case Iop_Sal64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sal8x8: size = 0; break; -+//ZZ case Iop_Sal16x4: size = 1; break; -+//ZZ case Iop_Sal32x2: size = 2; break; -+//ZZ case Iop_Sal64x1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shr8x8: -+//ZZ case Iop_Shr16x4: -+//ZZ case Iop_Shr32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegD(env); -+//ZZ HReg zero = newVRegD(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shr8x8: size = 0; break; -+//ZZ case Iop_Shr16x4: size = 1; break; -+//ZZ case Iop_Shr32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR2, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shl8x8: -+//ZZ case Iop_Shl16x4: -+//ZZ case Iop_Shl32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shl8x8: size = 0; break; -+//ZZ case Iop_Shl16x4: size = 1; break; -+//ZZ case Iop_Shl32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShl8x8: -+//ZZ case Iop_QShl16x4: -+//ZZ case Iop_QShl32x2: -+//ZZ case Iop_QShl64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShl8x8: size = 0; break; -+//ZZ case Iop_QShl16x4: size = 1; break; -+//ZZ case Iop_QShl32x2: size = 2; break; -+//ZZ case Iop_QShl64x1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSHL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSal8x8: -+//ZZ case Iop_QSal16x4: -+//ZZ case Iop_QSal32x2: -+//ZZ case Iop_QSal64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSal8x8: size = 0; break; -+//ZZ case Iop_QSal16x4: size = 1; break; -+//ZZ case Iop_QSal32x2: size = 2; break; -+//ZZ case Iop_QSal64x1: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSAL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8x8: -+//ZZ case Iop_QShlN16x4: -+//ZZ case Iop_QShlN32x2: -+//ZZ case Iop_QShlN64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8x8: size = 8 | imm; break; -+//ZZ case Iop_QShlN16x4: size = 16 | imm; break; -+//ZZ case Iop_QShlN32x2: size = 32 | imm; break; -+//ZZ case Iop_QShlN64x1: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, -+//ZZ res, argL, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8Sx8: -+//ZZ case Iop_QShlN16Sx4: -+//ZZ case Iop_QShlN32Sx2: -+//ZZ case Iop_QShlN64Sx1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8Sx8: size = 8 | imm; break; -+//ZZ case Iop_QShlN16Sx4: size = 16 | imm; break; -+//ZZ case Iop_QShlN32Sx2: size = 32 | imm; break; -+//ZZ case Iop_QShlN64Sx1: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, -+//ZZ res, argL, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSalN8x8: -+//ZZ case Iop_QSalN16x4: -+//ZZ case Iop_QSalN32x2: -+//ZZ case Iop_QSalN64x1: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSalN8x8: size = 8 | imm; break; -+//ZZ case Iop_QSalN16x4: size = 16 | imm; break; -+//ZZ case Iop_QSalN32x2: size = 32 | imm; break; -+//ZZ case Iop_QSalN64x1: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, -+//ZZ res, argL, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_ShrN8x8: -+//ZZ case Iop_ShrN16x4: -+//ZZ case Iop_ShrN32x2: -+//ZZ case Iop_Shr64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegI(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_ShrN8x8: size = 0; break; -+//ZZ case Iop_ShrN16x4: size = 1; break; -+//ZZ case Iop_ShrN32x2: size = 2; break; -+//ZZ case Iop_Shr64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, tmp, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_ShlN8x8: -+//ZZ case Iop_ShlN16x4: -+//ZZ case Iop_ShlN32x2: -+//ZZ case Iop_Shl64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ /* special-case Shl64(x, imm8) since the Neon front -+//ZZ end produces a lot of those for V{LD,ST}{1,2,3,4}. */ -+//ZZ if (e->Iex.Binop.op == Iop_Shl64 -+//ZZ && e->Iex.Binop.arg2->tag == Iex_Const) { -+//ZZ vassert(e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U8); -+//ZZ Int nshift = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ if (nshift >= 1 && nshift <= 63) { -+//ZZ addInstr(env, ARMInstr_NShl64(res, argL, nshift)); -+//ZZ return res; -+//ZZ } -+//ZZ /* else fall through to general case */ -+//ZZ } -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_ShlN8x8: size = 0; break; -+//ZZ case Iop_ShlN16x4: size = 1; break; -+//ZZ case Iop_ShlN32x2: size = 2; break; -+//ZZ case Iop_Shl64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, -+//ZZ tmp, argR, 0, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, tmp, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_SarN8x8: -+//ZZ case Iop_SarN16x4: -+//ZZ case Iop_SarN32x2: -+//ZZ case Iop_Sar64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegI(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_SarN8x8: size = 0; break; -+//ZZ case Iop_SarN16x4: size = 1; break; -+//ZZ case Iop_SarN32x2: size = 2; break; -+//ZZ case Iop_Sar64: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, tmp, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT8Ux8: -+//ZZ case Iop_CmpGT16Ux4: -+//ZZ case Iop_CmpGT32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Ux8: size = 0; break; -+//ZZ case Iop_CmpGT16Ux4: size = 1; break; -+//ZZ case Iop_CmpGT32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT8Sx8: -+//ZZ case Iop_CmpGT16Sx4: -+//ZZ case Iop_CmpGT32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Sx8: size = 0; break; -+//ZZ case Iop_CmpGT16Sx4: size = 1; break; -+//ZZ case Iop_CmpGT32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ8x8: -+//ZZ case Iop_CmpEQ16x4: -+//ZZ case Iop_CmpEQ32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpEQ8x8: size = 0; break; -+//ZZ case Iop_CmpEQ16x4: size = 1; break; -+//ZZ case Iop_CmpEQ32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul8x8: -+//ZZ case Iop_Mul16x4: -+//ZZ case Iop_Mul32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mul8x8: size = 0; break; -+//ZZ case Iop_Mul16x4: size = 1; break; -+//ZZ case Iop_Mul32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMUL, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QDMulHi16Sx4: -+//ZZ case Iop_QDMulHi32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QDMulHi16Sx4: size = 1; break; -+//ZZ case Iop_QDMulHi32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QRDMulHi16Sx4: -+//ZZ case Iop_QRDMulHi32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QRDMulHi16Sx4: size = 1; break; -+//ZZ case Iop_QRDMulHi32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_PwAdd8x8: -+//ZZ case Iop_PwAdd16x4: -+//ZZ case Iop_PwAdd32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAdd8x8: size = 0; break; -+//ZZ case Iop_PwAdd16x4: size = 1; break; -+//ZZ case Iop_PwAdd32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPADD, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAdd32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPADDFP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin8Ux8: -+//ZZ case Iop_PwMin16Ux4: -+//ZZ case Iop_PwMin32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMin8Ux8: size = 0; break; -+//ZZ case Iop_PwMin16Ux4: size = 1; break; -+//ZZ case Iop_PwMin32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin8Sx8: -+//ZZ case Iop_PwMin16Sx4: -+//ZZ case Iop_PwMin32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMin8Sx8: size = 0; break; -+//ZZ case Iop_PwMin16Sx4: size = 1; break; -+//ZZ case Iop_PwMin32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax8Ux8: -+//ZZ case Iop_PwMax16Ux4: -+//ZZ case Iop_PwMax32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMax8Ux8: size = 0; break; -+//ZZ case Iop_PwMax16Ux4: size = 1; break; -+//ZZ case Iop_PwMax32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXU, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax8Sx8: -+//ZZ case Iop_PwMax16Sx4: -+//ZZ case Iop_PwMax32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwMax8Sx8: size = 0; break; -+//ZZ case Iop_PwMax16Sx4: size = 1; break; -+//ZZ case Iop_PwMax32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXS, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Perm8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VTBL, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PolynomialMul8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULP, -+//ZZ res, argL, argR, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGE32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F32ToFixed32Ux2_RZ: -+//ZZ case Iop_F32ToFixed32Sx2_RZ: -+//ZZ case Iop_Fixed32UToF32x2_RN: -+//ZZ case Iop_Fixed32SToF32x2_RN: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ ARMNeonUnOp op; -+//ZZ UInt imm6; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports FP <-> Fixed conversion with constant " -+//ZZ "second argument less than 33 only\n"); -+//ZZ } -+//ZZ imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ vassert(imm6 <= 32 && imm6 > 0); -+//ZZ imm6 = 64 - imm6; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_F32ToFixed32Ux2_RZ: op = ARMneon_VCVTFtoFixedU; break; -+//ZZ case Iop_F32ToFixed32Sx2_RZ: op = ARMneon_VCVTFtoFixedS; break; -+//ZZ case Iop_Fixed32UToF32x2_RN: op = ARMneon_VCVTFixedUtoF; break; -+//ZZ case Iop_Fixed32SToF32x2_RN: op = ARMneon_VCVTFixedStoF; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False)); -+//ZZ return res; -+//ZZ } -+//ZZ /* -+//ZZ FIXME: is this here or not? -+//ZZ case Iop_VDup8x8: -+//ZZ case Iop_VDup16x4: -+//ZZ case Iop_VDup32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ UInt size = 0; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_VDup8x8: imm4 = (index << 1) + 1; break; -+//ZZ case Iop_VDup16x4: imm4 = (index << 2) + 2; break; -+//ZZ case Iop_VDup32x2: imm4 = (index << 3) + 4; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ if (imm4 >= 16) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VDUP, -+//ZZ res, argL, imm4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ */ -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* --------- UNARY ops --------- */ -+//ZZ if (e->tag == Iex_Unop) { -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ -+//ZZ /* 32Uto64 */ -+//ZZ case Iop_32Uto64: { -+//ZZ HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ HReg rHi = newVRegI(env); -+//ZZ HReg res = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_Imm32(rHi, 0)); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* 32Sto64 */ -+//ZZ case Iop_32Sto64: { -+//ZZ HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ HReg rHi = newVRegI(env); -+//ZZ addInstr(env, mk_iMOVds_RR(rHi, rLo)); -+//ZZ addInstr(env, ARMInstr_Shift(ARMsh_SAR, rHi, rHi, ARMRI5_I5(31))); -+//ZZ HReg res = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ /* The next 3 are pass-throughs */ -+//ZZ /* ReinterpF64asI64 */ -+//ZZ case Iop_ReinterpF64asI64: -+//ZZ /* Left64(e) */ -+//ZZ case Iop_Left64: -+//ZZ /* CmpwNEZ64(e) */ -+//ZZ case Iop_1Sto64: { -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_Not64: { -+//ZZ DECLARE_PATTERN(p_veqz_8x8); -+//ZZ DECLARE_PATTERN(p_veqz_16x4); -+//ZZ DECLARE_PATTERN(p_veqz_32x2); -+//ZZ DECLARE_PATTERN(p_vcge_8sx8); -+//ZZ DECLARE_PATTERN(p_vcge_16sx4); -+//ZZ DECLARE_PATTERN(p_vcge_32sx2); -+//ZZ DECLARE_PATTERN(p_vcge_8ux8); -+//ZZ DECLARE_PATTERN(p_vcge_16ux4); -+//ZZ DECLARE_PATTERN(p_vcge_32ux2); -+//ZZ DEFINE_PATTERN(p_veqz_8x8, -+//ZZ unop(Iop_Not64, unop(Iop_CmpNEZ8x8, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_16x4, -+//ZZ unop(Iop_Not64, unop(Iop_CmpNEZ16x4, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_32x2, -+//ZZ unop(Iop_Not64, unop(Iop_CmpNEZ32x2, bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8sx8, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT8Sx8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16sx4, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT16Sx4, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32sx2, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT32Sx2, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8ux8, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT8Ux8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16ux4, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT16Ux4, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32ux2, -+//ZZ unop(Iop_Not64, binop(Iop_CmpGT32Ux2, bind(1), bind(0)))); -+//ZZ if (matchIRExpr(&mi, p_veqz_8x8, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_16x4, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_32x2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8sx8, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16sx4, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 1, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32sx2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8ux8, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16ux4, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 1, False)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32ux2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 2, False)); -+//ZZ return res; -+//ZZ } else { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ case Iop_Dup8x8: -+//ZZ case Iop_Dup16x4: -+//ZZ case Iop_Dup32x2: { -+//ZZ HReg res, arg; -+//ZZ UInt size; -+//ZZ DECLARE_PATTERN(p_vdup_8x8); -+//ZZ DECLARE_PATTERN(p_vdup_16x4); -+//ZZ DECLARE_PATTERN(p_vdup_32x2); -+//ZZ DEFINE_PATTERN(p_vdup_8x8, -+//ZZ unop(Iop_Dup8x8, binop(Iop_GetElem8x8, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_16x4, -+//ZZ unop(Iop_Dup16x4, binop(Iop_GetElem16x4, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_32x2, -+//ZZ unop(Iop_Dup32x2, binop(Iop_GetElem32x2, bind(0), bind(1)))); -+//ZZ if (matchIRExpr(&mi, p_vdup_8x8, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 1) + 1; -+//ZZ if (index < 8) { -+//ZZ res = newVRegD(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, False -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_16x4, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 2) + 2; -+//ZZ if (index < 4) { -+//ZZ res = newVRegD(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, False -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_32x2, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 3) + 4; -+//ZZ if (index < 2) { -+//ZZ res = newVRegD(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, False -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } -+//ZZ arg = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ res = newVRegD(env); -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Dup8x8: size = 0; break; -+//ZZ case Iop_Dup16x4: size = 1; break; -+//ZZ case Iop_Dup32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Abs8x8: -+//ZZ case Iop_Abs16x4: -+//ZZ case Iop_Abs32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Abs8x8: size = 0; break; -+//ZZ case Iop_Abs16x4: size = 1; break; -+//ZZ case Iop_Abs32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse64_8x8: -+//ZZ case Iop_Reverse64_16x4: -+//ZZ case Iop_Reverse64_32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse64_8x8: size = 0; break; -+//ZZ case Iop_Reverse64_16x4: size = 1; break; -+//ZZ case Iop_Reverse64_32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV64, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse32_8x8: -+//ZZ case Iop_Reverse32_16x4: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse32_8x8: size = 0; break; -+//ZZ case Iop_Reverse32_16x4: size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV32, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse16_8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV16, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpwNEZ64: { -+//ZZ HReg x_lsh = newVRegD(env); -+//ZZ HReg x_rsh = newVRegD(env); -+//ZZ HReg lsh_amt = newVRegD(env); -+//ZZ HReg rsh_amt = newVRegD(env); -+//ZZ HReg zero = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg tmp2 = newVRegD(env); -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg x = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, False)); -+//ZZ addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32))); -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ rsh_amt, zero, lsh_amt, 2, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_lsh, x, lsh_amt, 3, False)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_rsh, x, rsh_amt, 3, False)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ tmp, x_lsh, x_rsh, 0, False)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, tmp, x, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpNEZ8x8: -+//ZZ case Iop_CmpNEZ16x4: -+//ZZ case Iop_CmpNEZ32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg tmp = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_CmpNEZ8x8: size = 0; break; -+//ZZ case Iop_CmpNEZ16x4: size = 1; break; -+//ZZ case Iop_CmpNEZ32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, False)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_NarrowUn16to8x8: -+//ZZ case Iop_NarrowUn32to16x4: -+//ZZ case Iop_NarrowUn64to32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_NarrowUn16to8x8: size = 0; break; -+//ZZ case Iop_NarrowUn32to16x4: size = 1; break; -+//ZZ case Iop_NarrowUn64to32x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYN, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QNarrowUn16Sto8Sx8: -+//ZZ case Iop_QNarrowUn32Sto16Sx4: -+//ZZ case Iop_QNarrowUn64Sto32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QNarrowUn16Sto8Sx8: size = 0; break; -+//ZZ case Iop_QNarrowUn32Sto16Sx4: size = 1; break; -+//ZZ case Iop_QNarrowUn64Sto32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QNarrowUn16Sto8Ux8: -+//ZZ case Iop_QNarrowUn32Sto16Ux4: -+//ZZ case Iop_QNarrowUn64Sto32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QNarrowUn16Sto8Ux8: size = 0; break; -+//ZZ case Iop_QNarrowUn32Sto16Ux4: size = 1; break; -+//ZZ case Iop_QNarrowUn64Sto32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QNarrowUn16Uto8Ux8: -+//ZZ case Iop_QNarrowUn32Uto16Ux4: -+//ZZ case Iop_QNarrowUn64Uto32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QNarrowUn16Uto8Ux8: size = 0; break; -+//ZZ case Iop_QNarrowUn32Uto16Ux4: size = 1; break; -+//ZZ case Iop_QNarrowUn64Uto32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Sx8: -+//ZZ case Iop_PwAddL16Sx4: -+//ZZ case Iop_PwAddL32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Sx8: size = 0; break; -+//ZZ case Iop_PwAddL16Sx4: size = 1; break; -+//ZZ case Iop_PwAddL32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Ux8: -+//ZZ case Iop_PwAddL16Ux4: -+//ZZ case Iop_PwAddL32Ux2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Ux8: size = 0; break; -+//ZZ case Iop_PwAddL16Ux4: size = 1; break; -+//ZZ case Iop_PwAddL32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cnt8x8: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CNT, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Clz8Sx8: -+//ZZ case Iop_Clz16Sx4: -+//ZZ case Iop_Clz32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Clz8Sx8: size = 0; break; -+//ZZ case Iop_Clz16Sx4: size = 1; break; -+//ZZ case Iop_Clz32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cls8Sx8: -+//ZZ case Iop_Cls16Sx4: -+//ZZ case Iop_Cls32Sx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Cls8Sx8: size = 0; break; -+//ZZ case Iop_Cls16Sx4: size = 1; break; -+//ZZ case Iop_Cls32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLS, -+//ZZ res, arg, size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Sx2_RZ: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Ux2_RZ: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32StoFx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32UtoFx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F32toF16x4: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16, -+//ZZ res, arg, 2, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF, -+//ZZ res, argL, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP, -+//ZZ res, argL, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Abs32Fx2: { -+//ZZ DECLARE_PATTERN(p_vabd_32fx2); -+//ZZ DEFINE_PATTERN(p_vabd_32fx2, -+//ZZ unop(Iop_Abs32Fx2, -+//ZZ binop(Iop_Sub32Fx2, -+//ZZ bind(0), -+//ZZ bind(1)))); -+//ZZ if (matchIRExpr(&mi, p_vabd_32fx2, e)) { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeon64Expr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP, -+//ZZ res, argL, argR, 0, False)); -+//ZZ return res; -+//ZZ } else { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ case Iop_Rsqrte32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrte32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Neg32Fx2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF, -+//ZZ res, arg, 0, False)); -+//ZZ return res; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } /* if (e->tag == Iex_Unop) */ -+//ZZ -+//ZZ if (e->tag == Iex_Triop) { -+//ZZ IRTriop *triop = e->Iex.Triop.details; -+//ZZ -+//ZZ switch (triop->op) { -+//ZZ case Iop_Extract64: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg argL = iselNeon64Expr(env, triop->arg1); -+//ZZ HReg argR = iselNeon64Expr(env, triop->arg2); -+//ZZ UInt imm4; -+//ZZ if (triop->arg3->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) { -+//ZZ vpanic("ARM target supports Iop_Extract64 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ imm4 = triop->arg3->Iex.Const.con->Ico.U8; -+//ZZ if (imm4 >= 8) { -+//ZZ vpanic("ARM target supports Iop_Extract64 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VEXT, -+//ZZ res, argL, argR, imm4, False)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_SetElem8x8: -+//ZZ case Iop_SetElem16x4: -+//ZZ case Iop_SetElem32x2: { -+//ZZ HReg res = newVRegD(env); -+//ZZ HReg dreg = iselNeon64Expr(env, triop->arg1); -+//ZZ HReg arg = iselIntExpr_R(env, triop->arg3); -+//ZZ UInt index, size; -+//ZZ if (triop->arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, triop->arg2) != Ity_I8) { -+//ZZ vpanic("ARM target supports SetElem with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ index = triop->arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (triop->op) { -+//ZZ case Iop_SetElem8x8: vassert(index < 8); size = 0; break; -+//ZZ case Iop_SetElem16x4: vassert(index < 4); size = 1; break; -+//ZZ case Iop_SetElem32x2: vassert(index < 2); size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False)); -+//ZZ addInstr(env, ARMInstr_NUnaryS(ARMneon_SETELEM, -+//ZZ mkARMNRS(ARMNRS_Scalar, res, index), -+//ZZ mkARMNRS(ARMNRS_Reg, arg, 0), -+//ZZ size, False)); -+//ZZ return res; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* --------- MULTIPLEX --------- */ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ HReg rLo, rHi; -+//ZZ HReg res = newVRegD(env); -+//ZZ iselInt64Expr(&rHi, &rLo, env, e); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ ppIRExpr(e); -+//ZZ vpanic("iselNeon64Expr"); -+//ZZ } -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Vector (NEON) expressions (128 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+static HReg iselV128Expr ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselV128Expr_wrk( env, e ); -+ vassert(hregClass(r) == HRcVec128); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY */ -+static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env, e); -+ vassert(e); -+ vassert(ty == Ity_V128); -+ -+ if (e->tag == Iex_RdTmp) { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ if (e->tag == Iex_Const) { -+ /* Only a very limited range of constants is handled. */ -+ vassert(e->Iex.Const.con->tag == Ico_V128); -+ UShort con = e->Iex.Const.con->Ico.V128; -+ if (con == 0x0000) { -+ HReg res = newVRegV(env); -+ addInstr(env, ARM64Instr_VImmQ(res, con)); -+ return res; -+ } -+ /* Unhandled */ -+ goto v128_expr_bad; -+ } -+ -+ if (e->tag == Iex_Load) { -+ HReg res = newVRegV(env); -+ HReg rN = iselIntExpr_R(env, e->Iex.Load.addr); -+ vassert(ty == Ity_V128); -+ addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, rN)); -+ return res; -+ } -+ -+ if (e->tag == Iex_Get) { -+ UInt offs = (UInt)e->Iex.Get.offset; -+ if (offs < (1<<12)) { -+ HReg addr = mk_baseblock_128bit_access_addr(env, offs); -+ HReg res = newVRegV(env); -+ vassert(ty == Ity_V128); -+ addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, addr)); -+ return res; -+ } -+ goto v128_expr_bad; -+ } -+ -+ if (e->tag == Iex_Unop) { -+ -+ /* Iop_ZeroHIXXofV128 cases */ -+ UShort imm16 = 0; -+ switch (e->Iex.Unop.op) { -+ case Iop_ZeroHI64ofV128: imm16 = 0x00FF; break; -+ case Iop_ZeroHI96ofV128: imm16 = 0x000F; break; -+ case Iop_ZeroHI112ofV128: imm16 = 0x0003; break; -+ case Iop_ZeroHI120ofV128: imm16 = 0x0001; break; -+ default: break; -+ } -+ if (imm16 != 0) { -+ HReg src = iselV128Expr(env, e->Iex.Unop.arg); -+ HReg imm = newVRegV(env); -+ HReg res = newVRegV(env); -+ addInstr(env, ARM64Instr_VImmQ(imm, imm16)); -+ addInstr(env, ARM64Instr_VBinV(ARM64vecb_AND, res, src, imm)); -+ return res; -+ } -+ -+ /* Other cases */ -+ switch (e->Iex.Unop.op) { -+ case Iop_NotV128: -+ case Iop_Abs64Fx2: -+ case Iop_Abs32Fx4: -+ case Iop_Neg64Fx2: -+ case Iop_Neg32Fx4: { -+ HReg res = newVRegV(env); -+ HReg arg = iselV128Expr(env, e->Iex.Unop.arg); -+ ARM64VecUnaryOp op = ARM64vecu_INVALID; -+ switch (e->Iex.Unop.op) { -+ case Iop_NotV128: op = ARM64vecu_NOT; break; -+ case Iop_Abs64Fx2: op = ARM64vecu_FABS64x2; break; -+ case Iop_Abs32Fx4: op = ARM64vecu_FABS32x4; break; -+ case Iop_Neg64Fx2: op = ARM64vecu_FNEG64x2; break; -+ case Iop_Neg32Fx4: op = ARM64vecu_FNEG32x4; break; -+ default: vassert(0); -+ } -+ addInstr(env, ARM64Instr_VUnaryV(op, res, arg)); -+ return res; -+ } -+ case Iop_CmpNEZ8x16: -+ case Iop_CmpNEZ16x8: -+ case Iop_CmpNEZ32x4: -+ case Iop_CmpNEZ64x2: { -+ HReg arg = iselV128Expr(env, e->Iex.Unop.arg); -+ HReg zero = newVRegV(env); -+ HReg res = newVRegV(env); -+ ARM64VecBinOp cmp = ARM64vecb_INVALID; -+ switch (e->Iex.Unop.op) { -+ case Iop_CmpNEZ64x2: cmp = ARM64vecb_CMEQ64x2; break; -+ case Iop_CmpNEZ32x4: cmp = ARM64vecb_CMEQ32x4; break; -+ case Iop_CmpNEZ16x8: cmp = ARM64vecb_CMEQ16x8; break; -+ case Iop_CmpNEZ8x16: cmp = ARM64vecb_CMEQ8x16; break; -+ default: vassert(0); -+ } -+ // This is pretty feeble. Better: use CMP against zero -+ // and avoid the extra instruction and extra register. -+ addInstr(env, ARM64Instr_VImmQ(zero, 0x0000)); -+ addInstr(env, ARM64Instr_VBinV(cmp, res, arg, zero)); -+ addInstr(env, ARM64Instr_VUnaryV(ARM64vecu_NOT, res, res)); -+ return res; -+ } -+ -+//ZZ case Iop_NotV128: { -+//ZZ DECLARE_PATTERN(p_veqz_8x16); -+//ZZ DECLARE_PATTERN(p_veqz_16x8); -+//ZZ DECLARE_PATTERN(p_veqz_32x4); -+//ZZ DECLARE_PATTERN(p_vcge_8sx16); -+//ZZ DECLARE_PATTERN(p_vcge_16sx8); -+//ZZ DECLARE_PATTERN(p_vcge_32sx4); -+//ZZ DECLARE_PATTERN(p_vcge_8ux16); -+//ZZ DECLARE_PATTERN(p_vcge_16ux8); -+//ZZ DECLARE_PATTERN(p_vcge_32ux4); -+//ZZ DEFINE_PATTERN(p_veqz_8x16, -+//ZZ unop(Iop_NotV128, unop(Iop_CmpNEZ8x16, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_16x8, -+//ZZ unop(Iop_NotV128, unop(Iop_CmpNEZ16x8, bind(0)))); -+//ZZ DEFINE_PATTERN(p_veqz_32x4, -+//ZZ unop(Iop_NotV128, unop(Iop_CmpNEZ32x4, bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8sx16, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT8Sx16, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16sx8, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT16Sx8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32sx4, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT32Sx4, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_8ux16, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT8Ux16, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_16ux8, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT16Ux8, bind(1), bind(0)))); -+//ZZ DEFINE_PATTERN(p_vcge_32ux4, -+//ZZ unop(Iop_NotV128, binop(Iop_CmpGT32Ux4, bind(1), bind(0)))); -+//ZZ if (matchIRExpr(&mi, p_veqz_8x16, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_16x8, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_veqz_32x4, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8sx16, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 0, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16sx8, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 1, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32sx4, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGES, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_8ux16, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 0, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_16ux8, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 1, True)); -+//ZZ return res; -+//ZZ } else if (matchIRExpr(&mi, p_vcge_32ux4, e)) { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, mi.bindee[0]); -+//ZZ HReg argR = iselNeonExpr(env, mi.bindee[1]); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } else { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ case Iop_Dup8x16: -+//ZZ case Iop_Dup16x8: -+//ZZ case Iop_Dup32x4: { -+//ZZ HReg res, arg; -+//ZZ UInt size; -+//ZZ DECLARE_PATTERN(p_vdup_8x16); -+//ZZ DECLARE_PATTERN(p_vdup_16x8); -+//ZZ DECLARE_PATTERN(p_vdup_32x4); -+//ZZ DEFINE_PATTERN(p_vdup_8x16, -+//ZZ unop(Iop_Dup8x16, binop(Iop_GetElem8x8, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_16x8, -+//ZZ unop(Iop_Dup16x8, binop(Iop_GetElem16x4, bind(0), bind(1)))); -+//ZZ DEFINE_PATTERN(p_vdup_32x4, -+//ZZ unop(Iop_Dup32x4, binop(Iop_GetElem32x2, bind(0), bind(1)))); -+//ZZ if (matchIRExpr(&mi, p_vdup_8x16, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 1) + 1; -+//ZZ if (index < 8) { -+//ZZ res = newVRegV(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, True -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_16x8, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 2) + 2; -+//ZZ if (index < 4) { -+//ZZ res = newVRegV(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, True -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } else if (matchIRExpr(&mi, p_vdup_32x4, e)) { -+//ZZ UInt index; -+//ZZ UInt imm4; -+//ZZ if (mi.bindee[1]->tag == Iex_Const && -+//ZZ typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) { -+//ZZ index = mi.bindee[1]->Iex.Const.con->Ico.U8; -+//ZZ imm4 = (index << 3) + 4; -+//ZZ if (index < 2) { -+//ZZ res = newVRegV(env); -+//ZZ arg = iselNeon64Expr(env, mi.bindee[0]); -+//ZZ addInstr(env, ARMInstr_NUnaryS( -+//ZZ ARMneon_VDUP, -+//ZZ mkARMNRS(ARMNRS_Reg, res, 0), -+//ZZ mkARMNRS(ARMNRS_Scalar, arg, index), -+//ZZ imm4, True -+//ZZ )); -+//ZZ return res; -+//ZZ } -+//ZZ } -+//ZZ } -+//ZZ arg = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ res = newVRegV(env); -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Dup8x16: size = 0; break; -+//ZZ case Iop_Dup16x8: size = 1; break; -+//ZZ case Iop_Dup32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Abs8x16: -+//ZZ case Iop_Abs16x8: -+//ZZ case Iop_Abs32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Abs8x16: size = 0; break; -+//ZZ case Iop_Abs16x8: size = 1; break; -+//ZZ case Iop_Abs32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse64_8x16: -+//ZZ case Iop_Reverse64_16x8: -+//ZZ case Iop_Reverse64_32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse64_8x16: size = 0; break; -+//ZZ case Iop_Reverse64_16x8: size = 1; break; -+//ZZ case Iop_Reverse64_32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV64, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse32_8x16: -+//ZZ case Iop_Reverse32_16x8: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Reverse32_8x16: size = 0; break; -+//ZZ case Iop_Reverse32_16x8: size = 1; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV32, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Reverse16_8x16: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_REV16, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpNEZ64x2: { -+//ZZ HReg x_lsh = newVRegV(env); -+//ZZ HReg x_rsh = newVRegV(env); -+//ZZ HReg lsh_amt = newVRegV(env); -+//ZZ HReg rsh_amt = newVRegV(env); -+//ZZ HReg zero = newVRegV(env); -+//ZZ HReg tmp = newVRegV(env); -+//ZZ HReg tmp2 = newVRegV(env); -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg x = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, True)); -+//ZZ addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32))); -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ rsh_amt, zero, lsh_amt, 2, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_lsh, x, lsh_amt, 3, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ x_rsh, x, rsh_amt, 3, True)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ tmp, x_lsh, x_rsh, 0, True)); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, tmp, x, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Widen8Uto16x8: -+//ZZ case Iop_Widen16Uto32x4: -+//ZZ case Iop_Widen32Uto64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Widen8Uto16x8: size = 0; break; -+//ZZ case Iop_Widen16Uto32x4: size = 1; break; -+//ZZ case Iop_Widen32Uto64x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Widen8Sto16x8: -+//ZZ case Iop_Widen16Sto32x4: -+//ZZ case Iop_Widen32Sto64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Unop.op) { -+//ZZ case Iop_Widen8Sto16x8: size = 0; break; -+//ZZ case Iop_Widen16Sto32x4: size = 1; break; -+//ZZ case Iop_Widen32Sto64x2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Sx16: -+//ZZ case Iop_PwAddL16Sx8: -+//ZZ case Iop_PwAddL32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Sx16: size = 0; break; -+//ZZ case Iop_PwAddL16Sx8: size = 1; break; -+//ZZ case Iop_PwAddL32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwAddL8Ux16: -+//ZZ case Iop_PwAddL16Ux8: -+//ZZ case Iop_PwAddL32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAddL8Ux16: size = 0; break; -+//ZZ case Iop_PwAddL16Ux8: size = 1; break; -+//ZZ case Iop_PwAddL32Ux4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU, -+//ZZ res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cnt8x16: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Clz8Sx16: -+//ZZ case Iop_Clz16Sx8: -+//ZZ case Iop_Clz32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Clz8Sx16: size = 0; break; -+//ZZ case Iop_Clz16Sx8: size = 1; break; -+//ZZ case Iop_Clz32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Cls8Sx16: -+//ZZ case Iop_Cls16Sx8: -+//ZZ case Iop_Cls32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Cls8Sx16: size = 0; break; -+//ZZ case Iop_Cls16Sx8: size = 1; break; -+//ZZ case Iop_Cls32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Sx4_RZ: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_FtoI32Ux4_RZ: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32StoFx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_I32UtoFx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F16toF32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF16toF32, -+//ZZ res, arg, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recip32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrte32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrte32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE, -+//ZZ res, argL, 0, True)); -+//ZZ return res; -+//ZZ } -+ /* ... */ -+ default: -+ break; -+ } /* switch on the unop */ -+ } /* if (e->tag == Iex_Unop) */ -+ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ case Iop_64HLtoV128: { -+ HReg res = newVRegV(env); -+ HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1); -+ HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ addInstr(env, ARM64Instr_VQfromXX(res, argL, argR)); -+ return res; -+ } -+//ZZ case Iop_AndV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VAND, -+//ZZ res, argL, argR, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_OrV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VORR, -+//ZZ res, argL, argR, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_XorV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VXOR, -+//ZZ res, argL, argR, 4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Add8x16: -+//ZZ case Iop_Add16x8: -+//ZZ case Iop_Add32x4: -+ case Iop_AndV128: -+ case Iop_OrV128: -+ case Iop_XorV128: -+ case Iop_Max32Ux4: -+ case Iop_Max16Ux8: -+ case Iop_Max8Ux16: -+ case Iop_Min32Ux4: -+ case Iop_Min16Ux8: -+ case Iop_Min8Ux16: -+ case Iop_Max32Sx4: -+ case Iop_Max16Sx8: -+ case Iop_Max8Sx16: -+ case Iop_Min32Sx4: -+ case Iop_Min16Sx8: -+ case Iop_Min8Sx16: -+ case Iop_Add64x2: -+ case Iop_Add32x4: -+ case Iop_Add16x8: -+ case Iop_Add8x16: -+ case Iop_Sub64x2: -+ case Iop_Sub32x4: -+ case Iop_Sub16x8: -+ case Iop_Sub8x16: -+ case Iop_Mul32x4: -+ case Iop_Mul16x8: -+ case Iop_Mul8x16: -+ case Iop_CmpEQ64x2: -+ case Iop_CmpEQ32x4: -+ case Iop_CmpEQ16x8: -+ case Iop_CmpEQ8x16: -+ case Iop_CmpGT64Ux2: -+ case Iop_CmpGT32Ux4: -+ case Iop_CmpGT16Ux8: -+ case Iop_CmpGT8Ux16: -+ case Iop_CmpGT64Sx2: -+ case Iop_CmpGT32Sx4: -+ case Iop_CmpGT16Sx8: -+ case Iop_CmpGT8Sx16: -+ case Iop_CmpEQ64Fx2: -+ case Iop_CmpEQ32Fx4: -+ case Iop_CmpLE64Fx2: -+ case Iop_CmpLE32Fx4: -+ case Iop_CmpLT64Fx2: -+ case Iop_CmpLT32Fx4: -+ case Iop_Perm8x16: -+ { -+ HReg res = newVRegV(env); -+ HReg argL = iselV128Expr(env, e->Iex.Binop.arg1); -+ HReg argR = iselV128Expr(env, e->Iex.Binop.arg2); -+ Bool sw = False; -+ ARM64VecBinOp op = ARM64vecb_INVALID; -+ switch (e->Iex.Binop.op) { -+ case Iop_AndV128: op = ARM64vecb_AND; break; -+ case Iop_OrV128: op = ARM64vecb_ORR; break; -+ case Iop_XorV128: op = ARM64vecb_XOR; break; -+ case Iop_Max32Ux4: op = ARM64vecb_UMAX32x4; break; -+ case Iop_Max16Ux8: op = ARM64vecb_UMAX16x8; break; -+ case Iop_Max8Ux16: op = ARM64vecb_UMAX8x16; break; -+ case Iop_Min32Ux4: op = ARM64vecb_UMIN32x4; break; -+ case Iop_Min16Ux8: op = ARM64vecb_UMIN16x8; break; -+ case Iop_Min8Ux16: op = ARM64vecb_UMIN8x16; break; -+ case Iop_Max32Sx4: op = ARM64vecb_SMAX32x4; break; -+ case Iop_Max16Sx8: op = ARM64vecb_SMAX16x8; break; -+ case Iop_Max8Sx16: op = ARM64vecb_SMAX8x16; break; -+ case Iop_Min32Sx4: op = ARM64vecb_SMIN32x4; break; -+ case Iop_Min16Sx8: op = ARM64vecb_SMIN16x8; break; -+ case Iop_Min8Sx16: op = ARM64vecb_SMIN8x16; break; -+ case Iop_Add64x2: op = ARM64vecb_ADD64x2; break; -+ case Iop_Add32x4: op = ARM64vecb_ADD32x4; break; -+ case Iop_Add16x8: op = ARM64vecb_ADD16x8; break; -+ case Iop_Add8x16: op = ARM64vecb_ADD8x16; break; -+ case Iop_Sub64x2: op = ARM64vecb_SUB64x2; break; -+ case Iop_Sub32x4: op = ARM64vecb_SUB32x4; break; -+ case Iop_Sub16x8: op = ARM64vecb_SUB16x8; break; -+ case Iop_Sub8x16: op = ARM64vecb_SUB8x16; break; -+ case Iop_Mul32x4: op = ARM64vecb_MUL32x4; break; -+ case Iop_Mul16x8: op = ARM64vecb_MUL16x8; break; -+ case Iop_Mul8x16: op = ARM64vecb_MUL8x16; break; -+ case Iop_CmpEQ64x2: op = ARM64vecb_CMEQ64x2; break; -+ case Iop_CmpEQ32x4: op = ARM64vecb_CMEQ32x4; break; -+ case Iop_CmpEQ16x8: op = ARM64vecb_CMEQ16x8; break; -+ case Iop_CmpEQ8x16: op = ARM64vecb_CMEQ8x16; break; -+ case Iop_CmpGT64Ux2: op = ARM64vecb_CMHI64x2; break; -+ case Iop_CmpGT32Ux4: op = ARM64vecb_CMHI32x4; break; -+ case Iop_CmpGT16Ux8: op = ARM64vecb_CMHI16x8; break; -+ case Iop_CmpGT8Ux16: op = ARM64vecb_CMHI8x16; break; -+ case Iop_CmpGT64Sx2: op = ARM64vecb_CMGT64x2; break; -+ case Iop_CmpGT32Sx4: op = ARM64vecb_CMGT32x4; break; -+ case Iop_CmpGT16Sx8: op = ARM64vecb_CMGT16x8; break; -+ case Iop_CmpGT8Sx16: op = ARM64vecb_CMGT8x16; break; -+ case Iop_CmpEQ64Fx2: op = ARM64vecb_FCMEQ64x2; break; -+ case Iop_CmpEQ32Fx4: op = ARM64vecb_FCMEQ32x4; break; -+ case Iop_CmpLE64Fx2: op = ARM64vecb_FCMGE64x2; sw = True; break; -+ case Iop_CmpLE32Fx4: op = ARM64vecb_FCMGE32x4; sw = True; break; -+ case Iop_CmpLT64Fx2: op = ARM64vecb_FCMGT64x2; sw = True; break; -+ case Iop_CmpLT32Fx4: op = ARM64vecb_FCMGT32x4; sw = True; break; -+ case Iop_Perm8x16: op = ARM64vecb_TBL1; break; -+ default: vassert(0); -+ } -+ if (sw) { -+ addInstr(env, ARM64Instr_VBinV(op, res, argR, argL)); -+ } else { -+ addInstr(env, ARM64Instr_VBinV(op, res, argL, argR)); -+ } -+ return res; -+ } -+//ZZ case Iop_Add32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Recps32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Rsqrts32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveEvenLanes8x16: -+//ZZ case Iop_InterleaveOddLanes8x16: -+//ZZ case Iop_InterleaveEvenLanes16x8: -+//ZZ case Iop_InterleaveOddLanes16x8: -+//ZZ case Iop_InterleaveEvenLanes32x4: -+//ZZ case Iop_InterleaveOddLanes32x4: { -+//ZZ HReg rD = newVRegV(env); -+//ZZ HReg rM = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveOddLanes8x16: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveEvenLanes8x16: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveOddLanes16x8: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveEvenLanes16x8: resRd = True; size = 1; break; -+//ZZ case Iop_InterleaveOddLanes32x4: resRd = False; size = 2; break; -+//ZZ case Iop_InterleaveEvenLanes32x4: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, True)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_InterleaveHI8x16: -+//ZZ case Iop_InterleaveLO8x16: -+//ZZ case Iop_InterleaveHI16x8: -+//ZZ case Iop_InterleaveLO16x8: -+//ZZ case Iop_InterleaveHI32x4: -+//ZZ case Iop_InterleaveLO32x4: { -+//ZZ HReg rD = newVRegV(env); -+//ZZ HReg rM = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_InterleaveHI8x16: resRd = False; size = 0; break; -+//ZZ case Iop_InterleaveLO8x16: resRd = True; size = 0; break; -+//ZZ case Iop_InterleaveHI16x8: resRd = False; size = 1; break; -+//ZZ case Iop_InterleaveLO16x8: resRd = True; size = 1; break; -+//ZZ case Iop_InterleaveHI32x4: resRd = False; size = 2; break; -+//ZZ case Iop_InterleaveLO32x4: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, True)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ // These 6 verified 18 Apr 2013 -+//ZZ case Iop_CatOddLanes8x16: -+//ZZ case Iop_CatEvenLanes8x16: -+//ZZ case Iop_CatOddLanes16x8: -+//ZZ case Iop_CatEvenLanes16x8: -+//ZZ case Iop_CatOddLanes32x4: -+//ZZ case Iop_CatEvenLanes32x4: { -+//ZZ HReg rD = newVRegV(env); -+//ZZ HReg rM = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ Bool resRd; // is the result in rD or rM ? -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CatOddLanes8x16: resRd = False; size = 0; break; -+//ZZ case Iop_CatEvenLanes8x16: resRd = True; size = 0; break; -+//ZZ case Iop_CatOddLanes16x8: resRd = False; size = 1; break; -+//ZZ case Iop_CatEvenLanes16x8: resRd = True; size = 1; break; -+//ZZ case Iop_CatOddLanes32x4: resRd = False; size = 2; break; -+//ZZ case Iop_CatEvenLanes32x4: resRd = True; size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True)); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True)); -+//ZZ addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, True)); -+//ZZ return resRd ? rD : rM; -+//ZZ } -+//ZZ -+//ZZ case Iop_QAdd8Ux16: -+//ZZ case Iop_QAdd16Ux8: -+//ZZ case Iop_QAdd32Ux4: -+//ZZ case Iop_QAdd64Ux2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Ux16: size = 0; break; -+//ZZ case Iop_QAdd16Ux8: size = 1; break; -+//ZZ case Iop_QAdd32Ux4: size = 2; break; -+//ZZ case Iop_QAdd64Ux2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQADDU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QAdd8Sx16: -+//ZZ case Iop_QAdd16Sx8: -+//ZZ case Iop_QAdd32Sx4: -+//ZZ case Iop_QAdd64Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QAdd8Sx16: size = 0; break; -+//ZZ case Iop_QAdd16Sx8: size = 1; break; -+//ZZ case Iop_QAdd32Sx4: size = 2; break; -+//ZZ case Iop_QAdd64Sx2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQADDS"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub8x16: -+//ZZ case Iop_Sub16x8: -+//ZZ case Iop_Sub32x4: -+//ZZ case Iop_Sub64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sub8x16: size = 0; break; -+//ZZ case Iop_Sub16x8: size = 1; break; -+//ZZ case Iop_Sub32x4: size = 2; break; -+//ZZ case Iop_Sub64x2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VSUB"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sub32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Ux16: -+//ZZ case Iop_QSub16Ux8: -+//ZZ case Iop_QSub32Ux4: -+//ZZ case Iop_QSub64Ux2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Ux16: size = 0; break; -+//ZZ case Iop_QSub16Ux8: size = 1; break; -+//ZZ case Iop_QSub32Ux4: size = 2; break; -+//ZZ case Iop_QSub64Ux2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQSUBU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSub8Sx16: -+//ZZ case Iop_QSub16Sx8: -+//ZZ case Iop_QSub32Sx4: -+//ZZ case Iop_QSub64Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSub8Sx16: size = 0; break; -+//ZZ case Iop_QSub16Sx8: size = 1; break; -+//ZZ case Iop_QSub32Sx4: size = 2; break; -+//ZZ case Iop_QSub64Sx2: size = 3; break; -+//ZZ default: -+//ZZ ppIROp(e->Iex.Binop.op); -+//ZZ vpanic("Illegal element size in VQSUBS"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Ux16: -+//ZZ case Iop_Max16Ux8: -+//ZZ case Iop_Max32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Ux16: size = 0; break; -+//ZZ case Iop_Max16Ux8: size = 1; break; -+//ZZ case Iop_Max32Ux4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max8Sx16: -+//ZZ case Iop_Max16Sx8: -+//ZZ case Iop_Max32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Max8Sx16: size = 0; break; -+//ZZ case Iop_Max16Sx8: size = 1; break; -+//ZZ case Iop_Max32Sx4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Ux16: -+//ZZ case Iop_Min16Ux8: -+//ZZ case Iop_Min32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Ux16: size = 0; break; -+//ZZ case Iop_Min16Ux8: size = 1; break; -+//ZZ case Iop_Min32Ux4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min8Sx16: -+//ZZ case Iop_Min16Sx8: -+//ZZ case Iop_Min32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Min8Sx16: size = 0; break; -+//ZZ case Iop_Min16Sx8: size = 1; break; -+//ZZ case Iop_Min32Sx4: size = 2; break; -+//ZZ default: vpanic("Illegal element size in VMAXU"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sar8x16: -+//ZZ case Iop_Sar16x8: -+//ZZ case Iop_Sar32x4: -+//ZZ case Iop_Sar64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegV(env); -+//ZZ HReg zero = newVRegV(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sar8x16: size = 0; break; -+//ZZ case Iop_Sar16x8: size = 1; break; -+//ZZ case Iop_Sar32x4: size = 2; break; -+//ZZ case Iop_Sar64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR2, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Sal8x16: -+//ZZ case Iop_Sal16x8: -+//ZZ case Iop_Sal32x4: -+//ZZ case Iop_Sal64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Sal8x16: size = 0; break; -+//ZZ case Iop_Sal16x8: size = 1; break; -+//ZZ case Iop_Sal32x4: size = 2; break; -+//ZZ case Iop_Sal64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSAL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shr8x16: -+//ZZ case Iop_Shr16x8: -+//ZZ case Iop_Shr32x4: -+//ZZ case Iop_Shr64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ HReg argR2 = newVRegV(env); -+//ZZ HReg zero = newVRegV(env); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shr8x16: size = 0; break; -+//ZZ case Iop_Shr16x8: size = 1; break; -+//ZZ case Iop_Shr32x4: size = 2; break; -+//ZZ case Iop_Shr64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0))); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VSUB, -+//ZZ argR2, zero, argR, size, True)); -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR2, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Shl8x16: -+//ZZ case Iop_Shl16x8: -+//ZZ case Iop_Shl32x4: -+//ZZ case Iop_Shl64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_Shl8x16: size = 0; break; -+//ZZ case Iop_Shl16x8: size = 1; break; -+//ZZ case Iop_Shl32x4: size = 2; break; -+//ZZ case Iop_Shl64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VSHL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShl8x16: -+//ZZ case Iop_QShl16x8: -+//ZZ case Iop_QShl32x4: -+//ZZ case Iop_QShl64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShl8x16: size = 0; break; -+//ZZ case Iop_QShl16x8: size = 1; break; -+//ZZ case Iop_QShl32x4: size = 2; break; -+//ZZ case Iop_QShl64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSHL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSal8x16: -+//ZZ case Iop_QSal16x8: -+//ZZ case Iop_QSal32x4: -+//ZZ case Iop_QSal64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSal8x16: size = 0; break; -+//ZZ case Iop_QSal16x8: size = 1; break; -+//ZZ case Iop_QSal32x4: size = 2; break; -+//ZZ case Iop_QSal64x2: size = 3; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NShift(ARMneon_VQSAL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8x16: -+//ZZ case Iop_QShlN16x8: -+//ZZ case Iop_QShlN32x4: -+//ZZ case Iop_QShlN64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8x16: size = 8 | imm; break; -+//ZZ case Iop_QShlN16x8: size = 16 | imm; break; -+//ZZ case Iop_QShlN32x4: size = 32 | imm; break; -+//ZZ case Iop_QShlN64x2: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU, -+//ZZ res, argL, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QShlN8Sx16: -+//ZZ case Iop_QShlN16Sx8: -+//ZZ case Iop_QShlN32Sx4: -+//ZZ case Iop_QShlN64Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNASxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QShlN8Sx16: size = 8 | imm; break; -+//ZZ case Iop_QShlN16Sx8: size = 16 | imm; break; -+//ZZ case Iop_QShlN32Sx4: size = 32 | imm; break; -+//ZZ case Iop_QShlN64Sx2: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS, -+//ZZ res, argL, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_QSalN8x16: -+//ZZ case Iop_QSalN16x8: -+//ZZ case Iop_QSalN32x4: -+//ZZ case Iop_QSalN64x2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ UInt size, imm; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM taget supports Iop_QShlNAxB with constant " -+//ZZ "second argument only\n"); -+//ZZ } -+//ZZ imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_QSalN8x16: size = 8 | imm; break; -+//ZZ case Iop_QSalN16x8: size = 16 | imm; break; -+//ZZ case Iop_QSalN32x4: size = 32 | imm; break; -+//ZZ case Iop_QSalN64x2: size = 64 | imm; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS, -+//ZZ res, argL, size, True)); -+//ZZ return res; -+//ZZ } -+ case Iop_ShrN64x2: -+ case Iop_ShrN32x4: -+ case Iop_ShrN16x8: -+ case Iop_ShrN8x16: -+ case Iop_SarN64x2: -+ case Iop_SarN32x4: -+ case Iop_SarN16x8: -+ case Iop_SarN8x16: -+ case Iop_ShlN64x2: -+ case Iop_ShlN32x4: -+ case Iop_ShlN16x8: -+ case Iop_ShlN8x16: -+ { -+ IRExpr* argL = e->Iex.Binop.arg1; -+ IRExpr* argR = e->Iex.Binop.arg2; -+ if (argR->tag == Iex_Const && argR->Iex.Const.con->tag == Ico_U8) { -+ UInt amt = argR->Iex.Const.con->Ico.U8; -+ UInt limit = 0; -+ ARM64VecShiftOp op = ARM64vecsh_INVALID; -+ switch (e->Iex.Binop.op) { -+ case Iop_ShrN64x2: -+ op = ARM64vecsh_USHR64x2; limit = 63; break; -+ case Iop_ShrN32x4: -+ op = ARM64vecsh_USHR32x4; limit = 31; break; -+ case Iop_ShrN16x8: -+ op = ARM64vecsh_USHR16x8; limit = 15; break; -+ case Iop_ShrN8x16: -+ op = ARM64vecsh_USHR8x16; limit = 7; break; -+ case Iop_SarN64x2: -+ op = ARM64vecsh_SSHR64x2; limit = 63; break; -+ case Iop_SarN32x4: -+ op = ARM64vecsh_SSHR32x4; limit = 31; break; -+ case Iop_SarN16x8: -+ op = ARM64vecsh_SSHR16x8; limit = 15; break; -+ case Iop_SarN8x16: -+ op = ARM64vecsh_SSHR8x16; limit = 7; break; -+ case Iop_ShlN64x2: -+ op = ARM64vecsh_SHL64x2; limit = 63; break; -+ case Iop_ShlN32x4: -+ op = ARM64vecsh_SHL32x4; limit = 31; break; -+ case Iop_ShlN16x8: -+ op = ARM64vecsh_SHL16x8; limit = 15; break; -+ case Iop_ShlN8x16: -+ op = ARM64vecsh_SHL8x16; limit = 7; break; -+ default: -+ vassert(0); -+ } -+ if (op != ARM64vecsh_INVALID && amt >= 0 && amt <= limit) { -+ HReg src = iselV128Expr(env, argL); -+ HReg dst = newVRegV(env); -+ if (amt > 0) { -+ addInstr(env, ARM64Instr_VShiftImmV(op, dst, src, amt)); -+ } else { -+ dst = src; -+ } -+ return dst; -+ } -+ } -+ /* else fall out; this is unhandled */ -+ break; -+ } -+//ZZ case Iop_CmpGT8Ux16: -+//ZZ case Iop_CmpGT16Ux8: -+//ZZ case Iop_CmpGT32Ux4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Ux16: size = 0; break; -+//ZZ case Iop_CmpGT16Ux8: size = 1; break; -+//ZZ case Iop_CmpGT32Ux4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT8Sx16: -+//ZZ case Iop_CmpGT16Sx8: -+//ZZ case Iop_CmpGT32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpGT8Sx16: size = 0; break; -+//ZZ case Iop_CmpGT16Sx8: size = 1; break; -+//ZZ case Iop_CmpGT32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ8x16: -+//ZZ case Iop_CmpEQ16x8: -+//ZZ case Iop_CmpEQ32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size; -+//ZZ switch (e->Iex.Binop.op) { -+//ZZ case Iop_CmpEQ8x16: size = 0; break; -+//ZZ case Iop_CmpEQ16x8: size = 1; break; -+//ZZ case Iop_CmpEQ32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul8x16: -+//ZZ case Iop_Mul16x8: -+//ZZ case Iop_Mul32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mul8x16: size = 0; break; -+//ZZ case Iop_Mul16x8: size = 1; break; -+//ZZ case Iop_Mul32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMUL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mul32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Mull8Ux8: -+//ZZ case Iop_Mull16Ux4: -+//ZZ case Iop_Mull32Ux2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mull8Ux8: size = 0; break; -+//ZZ case Iop_Mull16Ux4: size = 1; break; -+//ZZ case Iop_Mull32Ux2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULLU, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_Mull8Sx8: -+//ZZ case Iop_Mull16Sx4: -+//ZZ case Iop_Mull32Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_Mull8Sx8: size = 0; break; -+//ZZ case Iop_Mull16Sx4: size = 1; break; -+//ZZ case Iop_Mull32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULLS, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QDMulHi16Sx8: -+//ZZ case Iop_QDMulHi32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QDMulHi16Sx8: size = 1; break; -+//ZZ case Iop_QDMulHi32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QRDMulHi16Sx8: -+//ZZ case Iop_QRDMulHi32Sx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QRDMulHi16Sx8: size = 1; break; -+//ZZ case Iop_QRDMulHi32Sx4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_QDMulLong16Sx4: -+//ZZ case Iop_QDMulLong32Sx2: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_QDMulLong16Sx4: size = 1; break; -+//ZZ case Iop_QDMulLong32Sx2: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PolynomialMul8x16: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Max32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_Min32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMINF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMax32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_PwMin32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGT32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpGE32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_CmpEQ32Fx4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF, -+//ZZ res, argL, argR, 2, True)); -+//ZZ return res; -+//ZZ } -+//ZZ -+//ZZ case Iop_PolynomialMull8x8: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VMULLP, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+//ZZ case Iop_F32ToFixed32Ux4_RZ: -+//ZZ case Iop_F32ToFixed32Sx4_RZ: -+//ZZ case Iop_Fixed32UToF32x4_RN: -+//ZZ case Iop_Fixed32SToF32x4_RN: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ ARMNeonUnOp op; -+//ZZ UInt imm6; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports FP <-> Fixed conversion with constant " -+//ZZ "second argument less than 33 only\n"); -+//ZZ } -+//ZZ imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ vassert(imm6 <= 32 && imm6 > 0); -+//ZZ imm6 = 64 - imm6; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_F32ToFixed32Ux4_RZ: op = ARMneon_VCVTFtoFixedU; break; -+//ZZ case Iop_F32ToFixed32Sx4_RZ: op = ARMneon_VCVTFtoFixedS; break; -+//ZZ case Iop_Fixed32UToF32x4_RN: op = ARMneon_VCVTFixedUtoF; break; -+//ZZ case Iop_Fixed32SToF32x4_RN: op = ARMneon_VCVTFixedStoF; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True)); -+//ZZ return res; -+//ZZ } -+//ZZ /* -+//ZZ FIXME remove if not used -+//ZZ case Iop_VDup8x16: -+//ZZ case Iop_VDup16x8: -+//ZZ case Iop_VDup32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1); -+//ZZ UInt imm4; -+//ZZ UInt index; -+//ZZ if (e->Iex.Binop.arg2->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_VDup8x16: imm4 = (index << 1) + 1; break; -+//ZZ case Iop_VDup16x8: imm4 = (index << 2) + 2; break; -+//ZZ case Iop_VDup32x4: imm4 = (index << 3) + 4; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ if (imm4 >= 16) { -+//ZZ vpanic("ARM supports Iop_VDup with constant " -+//ZZ "second argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_VDUP, -+//ZZ res, argL, imm4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ */ -+//ZZ case Iop_PwAdd8x16: -+//ZZ case Iop_PwAdd16x8: -+//ZZ case Iop_PwAdd32x4: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -+//ZZ HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -+//ZZ UInt size = 0; -+//ZZ switch(e->Iex.Binop.op) { -+//ZZ case Iop_PwAdd8x16: size = 0; break; -+//ZZ case Iop_PwAdd16x8: size = 1; break; -+//ZZ case Iop_PwAdd32x4: size = 2; break; -+//ZZ default: vassert(0); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VPADD, -+//ZZ res, argL, argR, size, True)); -+//ZZ return res; -+//ZZ } -+ /* ... */ -+ default: -+ break; -+ } /* switch on the binop */ -+ } /* if (e->tag == Iex_Binop) */ -+ -+ if (e->tag == Iex_Triop) { -+ IRTriop* triop = e->Iex.Triop.details; -+ ARM64VecBinOp vecbop = ARM64vecb_INVALID; -+ switch (triop->op) { -+ case Iop_Add64Fx2: vecbop = ARM64vecb_FADD64x2; break; -+ case Iop_Sub64Fx2: vecbop = ARM64vecb_FSUB64x2; break; -+ case Iop_Mul64Fx2: vecbop = ARM64vecb_FMUL64x2; break; -+ case Iop_Div64Fx2: vecbop = ARM64vecb_FDIV64x2; break; -+ case Iop_Add32Fx4: vecbop = ARM64vecb_FADD32x4; break; -+ case Iop_Sub32Fx4: vecbop = ARM64vecb_FSUB32x4; break; -+ case Iop_Mul32Fx4: vecbop = ARM64vecb_FMUL32x4; break; -+ case Iop_Div32Fx4: vecbop = ARM64vecb_FDIV32x4; break; -+ default: break; -+ } -+ if (vecbop != ARM64vecb_INVALID) { -+ HReg argL = iselV128Expr(env, triop->arg2); -+ HReg argR = iselV128Expr(env, triop->arg3); -+ HReg dst = newVRegV(env); -+ set_FPCR_rounding_mode(env, triop->arg1); -+ addInstr(env, ARM64Instr_VBinV(vecbop, dst, argL, argR)); -+ return dst; -+ } -+ -+//ZZ switch (triop->op) { -+//ZZ case Iop_ExtractV128: { -+//ZZ HReg res = newVRegV(env); -+//ZZ HReg argL = iselNeonExpr(env, triop->arg1); -+//ZZ HReg argR = iselNeonExpr(env, triop->arg2); -+//ZZ UInt imm4; -+//ZZ if (triop->arg3->tag != Iex_Const || -+//ZZ typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) { -+//ZZ vpanic("ARM target supports Iop_ExtractV128 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ imm4 = triop->arg3->Iex.Const.con->Ico.U8; -+//ZZ if (imm4 >= 16) { -+//ZZ vpanic("ARM target supports Iop_ExtractV128 with constant " -+//ZZ "third argument less than 16 only\n"); -+//ZZ } -+//ZZ addInstr(env, ARMInstr_NBinary(ARMneon_VEXT, -+//ZZ res, argL, argR, imm4, True)); -+//ZZ return res; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+ } -+ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ ARMCondCode cc; -+//ZZ HReg r1 = iselNeonExpr(env, e->Iex.ITE.iftrue); -+//ZZ HReg r0 = iselNeonExpr(env, e->Iex.ITE.iffalse); -+//ZZ HReg dst = newVRegV(env); -+//ZZ addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, r1, 4, True)); -+//ZZ cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_NCMovQ(cc ^ 1, dst, r0)); -+//ZZ return dst; -+//ZZ } -+ -+ v128_expr_bad: -+ ppIRExpr(e); -+ vpanic("iselV128Expr_wrk"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Floating point expressions (64 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Compute a 64-bit floating point value into a register, the identity -+ of which is returned. As with iselIntExpr_R, the reg may be either -+ real or virtual; in any case it must not be changed by subsequent -+ code emitted by the caller. */ -+ -+static HReg iselDblExpr ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselDblExpr_wrk( env, e ); -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(r) == HRcFlt64); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY */ -+static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(e); -+ vassert(ty == Ity_F64); -+ -+ if (e->tag == Iex_RdTmp) { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ if (e->tag == Iex_Const) { -+ IRConst* con = e->Iex.Const.con; -+ if (con->tag == Ico_F64i) { -+ HReg src = newVRegI(env); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_Imm64(src, con->Ico.F64i)); -+ addInstr(env, ARM64Instr_VDfromX(dst, src)); -+ return dst; -+ } -+ } -+ -+ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+ vassert(e->Iex.Load.ty == Ity_F64); -+ HReg addr = iselIntExpr_R(env, e->Iex.Load.addr); -+ HReg res = newVRegD(env); -+ addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, res, addr, 0)); -+ return res; -+ } -+ -+ if (e->tag == Iex_Get) { -+ Int offs = e->Iex.Get.offset; -+ if (offs >= 0 && offs < 32768 && 0 == (offs & 7)) { -+ HReg rD = newVRegD(env); -+ HReg rN = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, rD, rN, offs)); -+ return rD; -+ } -+ } -+ -+ if (e->tag == Iex_Unop) { -+ switch (e->Iex.Unop.op) { -+//ZZ case Iop_ReinterpI64asF64: { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ return iselNeon64Expr(env, e->Iex.Unop.arg); -+//ZZ } else { -+//ZZ HReg srcHi, srcLo; -+//ZZ HReg dst = newVRegD(env); -+//ZZ iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo)); -+//ZZ return dst; -+//ZZ } -+//ZZ } -+ case Iop_NegF64: { -+ HReg src = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_NEG, dst, src)); -+ return dst; -+ } -+ case Iop_AbsF64: { -+ HReg src = iselDblExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_ABS, dst, src)); -+ return dst; -+ } -+ case Iop_F32toF64: { -+ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtSD(True/*sToD*/, dst, src)); -+ return dst; -+ } -+ case Iop_I32UtoF64: -+ case Iop_I32StoF64: { -+ /* Rounding mode is not involved here, since the -+ conversion can always be done without loss of -+ precision. */ -+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ Bool syned = e->Iex.Unop.op == Iop_I32StoF64; -+ ARM64CvtOp cvt_op = syned ? ARM64cvt_F64_I32S : ARM64cvt_F64_I32U; -+ addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dst, src)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ case Iop_RoundF64toInt: { -+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_RINT, dst, src)); -+ return dst; -+ } -+ case Iop_SqrtF64: { -+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_SQRT, dst, src)); -+ return dst; -+ } -+ case Iop_I64StoF64: -+ case Iop_I64UtoF64: { -+ ARM64CvtOp cvt_op = e->Iex.Binop.op == Iop_I64StoF64 -+ ? ARM64cvt_F64_I64S : ARM64cvt_F64_I64U; -+ HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ HReg dstS = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dstS, srcI)); -+ return dstS; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Triop) { -+ IRTriop* triop = e->Iex.Triop.details; -+ ARM64FpBinOp dblop = ARM64fpb_INVALID; -+ switch (triop->op) { -+ case Iop_DivF64: dblop = ARM64fpb_DIV; break; -+ case Iop_MulF64: dblop = ARM64fpb_MUL; break; -+ case Iop_SubF64: dblop = ARM64fpb_SUB; break; -+ case Iop_AddF64: dblop = ARM64fpb_ADD; break; -+ default: break; -+ } -+ if (dblop != ARM64fpb_INVALID) { -+ HReg argL = iselDblExpr(env, triop->arg2); -+ HReg argR = iselDblExpr(env, triop->arg3); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, triop->arg1); -+ addInstr(env, ARM64Instr_VBinD(dblop, dst, argL, argR)); -+ return dst; -+ } -+ } -+ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ if (ty == Ity_F64 -+//ZZ && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) { -+//ZZ HReg r1 = iselDblExpr(env, e->Iex.ITE.iftrue); -+//ZZ HReg r0 = iselDblExpr(env, e->Iex.ITE.iffalse); -+//ZZ HReg dst = newVRegD(env); -+//ZZ addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, r1)); -+//ZZ ARMCondCode cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_VCMovD(cc ^ 1, dst, r0)); -+//ZZ return dst; -+//ZZ } -+//ZZ } -+ -+ ppIRExpr(e); -+ vpanic("iselDblExpr_wrk"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Floating point expressions (32 bit) ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Compute a 32-bit floating point value into a register, the identity -+ of which is returned. As with iselIntExpr_R, the reg may be either -+ real or virtual; in any case it must not be changed by subsequent -+ code emitted by the caller. Values are generated into HRcFlt64 -+ registers despite the values themselves being Ity_F32s. */ -+ -+static HReg iselFltExpr ( ISelEnv* env, IRExpr* e ) -+{ -+ HReg r = iselFltExpr_wrk( env, e ); -+# if 0 -+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n"); -+# endif -+ vassert(hregClass(r) == HRcFlt64); -+ vassert(hregIsVirtual(r)); -+ return r; -+} -+ -+/* DO NOT CALL THIS DIRECTLY */ -+static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e ) -+{ -+ IRType ty = typeOfIRExpr(env->type_env,e); -+ vassert(e); -+ vassert(ty == Ity_F32); -+ -+ if (e->tag == Iex_RdTmp) { -+ return lookupIRTemp(env, e->Iex.RdTmp.tmp); -+ } -+ -+ if (e->tag == Iex_Const) { -+ /* This is something of a kludge. Since a 32 bit floating point -+ zero is just .. all zeroes, just create a 64 bit zero word -+ and transfer it. This avoids having to create a SfromW -+ instruction for this specific case. */ -+ IRConst* con = e->Iex.Const.con; -+ if (con->tag == Ico_F32i && con->Ico.F32i == 0) { -+ HReg src = newVRegI(env); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_Imm64(src, 0)); -+ addInstr(env, ARM64Instr_VDfromX(dst, src)); -+ return dst; -+ } -+ } -+ -+//ZZ if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) { -+//ZZ ARMAModeV* am; -+//ZZ HReg res = newVRegF(env); -+//ZZ vassert(e->Iex.Load.ty == Ity_F32); -+//ZZ am = iselIntExpr_AModeV(env, e->Iex.Load.addr); -+//ZZ addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am)); -+//ZZ return res; -+//ZZ } -+ -+ if (e->tag == Iex_Get) { -+ Int offs = e->Iex.Get.offset; -+ if (offs >= 0 && offs < 16384 && 0 == (offs & 3)) { -+ HReg rD = newVRegD(env); -+ HReg rN = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStS(True/*isLoad*/, rD, rN, offs)); -+ return rD; -+ } -+ } -+ -+ if (e->tag == Iex_Unop) { -+ switch (e->Iex.Unop.op) { -+//ZZ case Iop_ReinterpI32asF32: { -+//ZZ HReg dst = newVRegF(env); -+//ZZ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg); -+//ZZ addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src)); -+//ZZ return dst; -+//ZZ } -+ case Iop_NegF32: { -+ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_NEG, dst, src)); -+ return dst; -+ } -+ case Iop_AbsF32: { -+ HReg src = iselFltExpr(env, e->Iex.Unop.arg); -+ HReg dst = newVRegD(env); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_ABS, dst, src)); -+ return dst; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Binop) { -+ switch (e->Iex.Binop.op) { -+ case Iop_RoundF32toInt: { -+ HReg src = iselFltExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_RINT, dst, src)); -+ return dst; -+ } -+ case Iop_SqrtF32: { -+ HReg src = iselFltExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_SQRT, dst, src)); -+ return dst; -+ } -+ case Iop_F64toF32: { -+ HReg srcD = iselDblExpr(env, e->Iex.Binop.arg2); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ HReg dstS = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtSD(False/*dToS*/, dstS, srcD)); -+ return dstS; -+ } -+ case Iop_I32UtoF32: -+ case Iop_I32StoF32: -+ case Iop_I64UtoF32: -+ case Iop_I64StoF32: { -+ ARM64CvtOp cvt_op = ARM64cvt_INVALID; -+ switch (e->Iex.Binop.op) { -+ case Iop_I32UtoF32: cvt_op = ARM64cvt_F32_I32U; break; -+ case Iop_I32StoF32: cvt_op = ARM64cvt_F32_I32S; break; -+ case Iop_I64UtoF32: cvt_op = ARM64cvt_F32_I64U; break; -+ case Iop_I64StoF32: cvt_op = ARM64cvt_F32_I64S; break; -+ default: vassert(0); -+ } -+ HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2); -+ set_FPCR_rounding_mode(env, e->Iex.Binop.arg1); -+ HReg dstS = newVRegD(env); -+ addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dstS, srcI)); -+ return dstS; -+ } -+ default: -+ break; -+ } -+ } -+ -+ if (e->tag == Iex_Triop) { -+ IRTriop* triop = e->Iex.Triop.details; -+ ARM64FpBinOp sglop = ARM64fpb_INVALID; -+ switch (triop->op) { -+ case Iop_DivF32: sglop = ARM64fpb_DIV; break; -+ case Iop_MulF32: sglop = ARM64fpb_MUL; break; -+ case Iop_SubF32: sglop = ARM64fpb_SUB; break; -+ case Iop_AddF32: sglop = ARM64fpb_ADD; break; -+ default: break; -+ } -+ if (sglop != ARM64fpb_INVALID) { -+ HReg argL = iselFltExpr(env, triop->arg2); -+ HReg argR = iselFltExpr(env, triop->arg3); -+ HReg dst = newVRegD(env); -+ set_FPCR_rounding_mode(env, triop->arg1); -+ addInstr(env, ARM64Instr_VBinS(sglop, dst, argL, argR)); -+ return dst; -+ } -+ } -+ -+//ZZ -+//ZZ if (e->tag == Iex_ITE) { // VFD -+//ZZ if (ty == Ity_F32 -+//ZZ && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) { -+//ZZ ARMCondCode cc; -+//ZZ HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue); -+//ZZ HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse); -+//ZZ HReg dst = newVRegF(env); -+//ZZ addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, r1)); -+//ZZ cc = iselCondCode(env, e->Iex.ITE.cond); -+//ZZ addInstr(env, ARMInstr_VCMovS(cc ^ 1, dst, r0)); -+//ZZ return dst; -+//ZZ } -+//ZZ } -+ -+ ppIRExpr(e); -+ vpanic("iselFltExpr_wrk"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Statements ---*/ -+/*---------------------------------------------------------*/ -+ -+static void iselStmt ( ISelEnv* env, IRStmt* stmt ) -+{ -+ if (vex_traceflags & VEX_TRACE_VCODE) { -+ vex_printf("\n-- "); -+ ppIRStmt(stmt); -+ vex_printf("\n"); -+ } -+ switch (stmt->tag) { -+ -+ /* --------- STORE --------- */ -+ /* little-endian write to memory */ -+ case Ist_Store: { -+ IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr); -+ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data); -+ IREndness end = stmt->Ist.Store.end; -+ -+ if (tya != Ity_I64 || end != Iend_LE) -+ goto stmt_fail; -+ -+ if (tyd == Ity_I64) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt64(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I32) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt32(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I16) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt16(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I8) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+ ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd); -+ addInstr(env, ARM64Instr_LdSt8(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_V128) { -+ HReg qD = iselV128Expr(env, stmt->Ist.Store.data); -+ HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr); -+ addInstr(env, ARM64Instr_VLdStQ(False/*!isLoad*/, qD, addr)); -+ return; -+ } -+ if (tyd == Ity_F64) { -+ HReg dD = iselDblExpr(env, stmt->Ist.Store.data); -+ HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr); -+ addInstr(env, ARM64Instr_VLdStD(False/*!isLoad*/, dD, addr, 0)); -+ return; -+ } -+ if (tyd == Ity_F32) { -+ HReg sD = iselFltExpr(env, stmt->Ist.Store.data); -+ HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr); -+ addInstr(env, ARM64Instr_VLdStS(False/*!isLoad*/, sD, addr, 0)); -+ return; -+ } -+ -+//ZZ if (tyd == Ity_I16) { -+//ZZ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+//ZZ ARMAMode2* am = iselIntExpr_AMode2(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_LdSt16(ARMcc_AL, -+//ZZ False/*!isLoad*/, -+//ZZ False/*!isSignedLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_I8) { -+//ZZ HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data); -+//ZZ ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_LdSt8U(ARMcc_AL, False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_I64) { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_NLdStD(False, dD, am)); -+//ZZ } else { -+//ZZ HReg rDhi, rDlo, rA; -+//ZZ iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data); -+//ZZ rA = iselIntExpr_R(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDhi, -+//ZZ ARMAMode1_RI(rA,4))); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDlo, -+//ZZ ARMAMode1_RI(rA,0))); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F64) { -+//ZZ HReg dD = iselDblExpr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, dD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F32) { -+//ZZ HReg fD = iselFltExpr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_V128) { -+//ZZ HReg qD = iselNeonExpr(env, stmt->Ist.Store.data); -+//ZZ ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr); -+//ZZ addInstr(env, ARMInstr_NLdStQ(False, qD, am)); -+//ZZ return; -+//ZZ } -+ -+ break; -+ } -+ -+//ZZ /* --------- CONDITIONAL STORE --------- */ -+//ZZ /* conditional little-endian write to memory */ -+//ZZ case Ist_StoreG: { -+//ZZ IRStoreG* sg = stmt->Ist.StoreG.details; -+//ZZ IRType tya = typeOfIRExpr(env->type_env, sg->addr); -+//ZZ IRType tyd = typeOfIRExpr(env->type_env, sg->data); -+//ZZ IREndness end = sg->end; -+//ZZ -+//ZZ if (tya != Ity_I32 || end != Iend_LE) -+//ZZ goto stmt_fail; -+//ZZ -+//ZZ switch (tyd) { -+//ZZ case Ity_I8: -+//ZZ case Ity_I32: { -+//ZZ HReg rD = iselIntExpr_R(env, sg->data); -+//ZZ ARMAMode1* am = iselIntExpr_AMode1(env, sg->addr); -+//ZZ ARMCondCode cc = iselCondCode(env, sg->guard); -+//ZZ addInstr(env, (tyd == Ity_I32 ? ARMInstr_LdSt32 : ARMInstr_LdSt8U) -+//ZZ (cc, False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ case Ity_I16: { -+//ZZ HReg rD = iselIntExpr_R(env, sg->data); -+//ZZ ARMAMode2* am = iselIntExpr_AMode2(env, sg->addr); -+//ZZ ARMCondCode cc = iselCondCode(env, sg->guard); -+//ZZ addInstr(env, ARMInstr_LdSt16(cc, -+//ZZ False/*!isLoad*/, -+//ZZ False/*!isSignedLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ break; -+//ZZ } -+//ZZ -+//ZZ /* --------- CONDITIONAL LOAD --------- */ -+//ZZ /* conditional little-endian load from memory */ -+//ZZ case Ist_LoadG: { -+//ZZ IRLoadG* lg = stmt->Ist.LoadG.details; -+//ZZ IRType tya = typeOfIRExpr(env->type_env, lg->addr); -+//ZZ IREndness end = lg->end; -+//ZZ -+//ZZ if (tya != Ity_I32 || end != Iend_LE) -+//ZZ goto stmt_fail; -+//ZZ -+//ZZ switch (lg->cvt) { -+//ZZ case ILGop_8Uto32: -+//ZZ case ILGop_Ident32: { -+//ZZ HReg rAlt = iselIntExpr_R(env, lg->alt); -+//ZZ ARMAMode1* am = iselIntExpr_AMode1(env, lg->addr); -+//ZZ HReg rD = lookupIRTemp(env, lg->dst); -+//ZZ addInstr(env, mk_iMOVds_RR(rD, rAlt)); -+//ZZ ARMCondCode cc = iselCondCode(env, lg->guard); -+//ZZ addInstr(env, (lg->cvt == ILGop_Ident32 ? ARMInstr_LdSt32 -+//ZZ : ARMInstr_LdSt8U) -+//ZZ (cc, True/*isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ case ILGop_16Sto32: -+//ZZ case ILGop_16Uto32: -+//ZZ case ILGop_8Sto32: { -+//ZZ HReg rAlt = iselIntExpr_R(env, lg->alt); -+//ZZ ARMAMode2* am = iselIntExpr_AMode2(env, lg->addr); -+//ZZ HReg rD = lookupIRTemp(env, lg->dst); -+//ZZ addInstr(env, mk_iMOVds_RR(rD, rAlt)); -+//ZZ ARMCondCode cc = iselCondCode(env, lg->guard); -+//ZZ if (lg->cvt == ILGop_8Sto32) { -+//ZZ addInstr(env, ARMInstr_Ld8S(cc, rD, am)); -+//ZZ } else { -+//ZZ vassert(lg->cvt == ILGop_16Sto32 || lg->cvt == ILGop_16Uto32); -+//ZZ Bool sx = lg->cvt == ILGop_16Sto32; -+//ZZ addInstr(env, ARMInstr_LdSt16(cc, True/*isLoad*/, sx, rD, am)); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ break; -+//ZZ } -+ -+ /* --------- PUT --------- */ -+ /* write guest state, fixed offset */ -+ case Ist_Put: { -+ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Put.data); -+ UInt offs = (UInt)stmt->Ist.Put.offset; -+ if (tyd == Ity_I64 && 0 == (offs & 7) && offs < (8<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_64bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt64(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I32 && 0 == (offs & 3) && offs < (4<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_32bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt32(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I16 && 0 == (offs & 1) && offs < (2<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_16bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt16(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_I8 && offs < (1<<12)) { -+ HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data); -+ ARM64AMode* am = mk_baseblock_8bit_access_amode(offs); -+ addInstr(env, ARM64Instr_LdSt8(False/*!isLoad*/, rD, am)); -+ return; -+ } -+ if (tyd == Ity_V128 && offs < (1<<12)) { -+ HReg qD = iselV128Expr(env, stmt->Ist.Put.data); -+ HReg addr = mk_baseblock_128bit_access_addr(env, offs); -+ addInstr(env, ARM64Instr_VLdStQ(False/*!isLoad*/, qD, addr)); -+ return; -+ } -+ if (tyd == Ity_F64 && 0 == (offs & 7) && offs < (8<<12)) { -+ HReg dD = iselDblExpr(env, stmt->Ist.Put.data); -+ HReg bbp = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStD(False/*!isLoad*/, dD, bbp, offs)); -+ return; -+ } -+ if (tyd == Ity_F32 && 0 == (offs & 3) && offs < (4<<12)) { -+ HReg dD = iselFltExpr(env, stmt->Ist.Put.data); -+ HReg bbp = get_baseblock_register(); -+ addInstr(env, ARM64Instr_VLdStS(False/*!isLoad*/, dD, bbp, offs)); -+ return; -+ } -+ -+//ZZ if (tyd == Ity_I64) { -+//ZZ if (env->hwcaps & VEX_HWCAPS_ARM_NEON) { -+//ZZ HReg addr = newVRegI(env); -+//ZZ HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), -+//ZZ stmt->Ist.Put.offset)); -+//ZZ addInstr(env, ARMInstr_NLdStD(False, qD, mkARMAModeN_R(addr))); -+//ZZ } else { -+//ZZ HReg rDhi, rDlo; -+//ZZ ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), -+//ZZ stmt->Ist.Put.offset + 0); -+//ZZ ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), -+//ZZ stmt->Ist.Put.offset + 4); -+//ZZ iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, -+//ZZ rDhi, am4)); -+//ZZ addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, -+//ZZ rDlo, am0)); -+//ZZ } -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F64) { -+//ZZ // XXX This won't work if offset > 1020 or is not 0 % 4. -+//ZZ // In which case we'll have to generate more longwinded code. -+//ZZ ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset); -+//ZZ HReg rD = iselDblExpr(env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+//ZZ if (tyd == Ity_F32) { -+//ZZ // XXX This won't work if offset > 1020 or is not 0 % 4. -+//ZZ // In which case we'll have to generate more longwinded code. -+//ZZ ARMAModeV* am = mkARMAModeV(hregARM_R8(), stmt->Ist.Put.offset); -+//ZZ HReg rD = iselFltExpr(env, stmt->Ist.Put.data); -+//ZZ addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am)); -+//ZZ return; -+//ZZ } -+ break; -+ } -+ -+ /* --------- TMP --------- */ -+ /* assign value to temporary */ -+ case Ist_WrTmp: { -+ IRTemp tmp = stmt->Ist.WrTmp.tmp; -+ IRType ty = typeOfIRTemp(env->type_env, tmp); -+ -+ if (ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8) { -+ /* We could do a lot better here. But for the time being: */ -+ HReg dst = lookupIRTemp(env, tmp); -+ HReg rD = iselIntExpr_R(env, stmt->Ist.WrTmp.data); -+ addInstr(env, ARM64Instr_MovI(dst, rD)); -+ return; -+ } -+ if (ty == Ity_I1) { -+ /* Here, we are generating a I1 value into a 64 bit register. -+ Make sure the value in the register is only zero or one, -+ but no other. This allows optimisation of the -+ 1Uto64(tmp:I1) case, by making it simply a copy of the -+ register holding 'tmp'. The point being that the value in -+ the register holding 'tmp' can only have been created -+ here. LATER: that seems dangerous; safer to do 'tmp & 1' -+ in that case. Also, could do this just with a single CINC -+ insn. */ -+ /* CLONE-01 */ -+ HReg zero = newVRegI(env); -+ HReg one = newVRegI(env); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_Imm64(zero, 0)); -+ addInstr(env, ARM64Instr_Imm64(one, 1)); -+ ARM64CondCode cc = iselCondCode(env, stmt->Ist.WrTmp.data); -+ addInstr(env, ARM64Instr_CSel(dst, one, zero, cc)); -+ return; -+ } -+ if (ty == Ity_F64) { -+ HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_VMov(8, dst, src)); -+ return; -+ } -+ if (ty == Ity_F32) { -+ HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_VMov(8/*yes, really*/, dst, src)); -+ return; -+ } -+ if (ty == Ity_V128) { -+ HReg src = iselV128Expr(env, stmt->Ist.WrTmp.data); -+ HReg dst = lookupIRTemp(env, tmp); -+ addInstr(env, ARM64Instr_VMov(16, dst, src)); -+ return; -+ } -+ break; -+ } -+ -+ /* --------- Call to DIRTY helper --------- */ -+ /* call complex ("dirty") helper function */ -+ case Ist_Dirty: { -+ IRDirty* d = stmt->Ist.Dirty.details; -+ -+ /* Figure out the return type, if any. */ -+ IRType retty = Ity_INVALID; -+ if (d->tmp != IRTemp_INVALID) -+ retty = typeOfIRTemp(env->type_env, d->tmp); -+ -+ Bool retty_ok = False; -+ switch (retty) { -+ case Ity_INVALID: /* function doesn't return anything */ -+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: -+ case Ity_V128: -+ retty_ok = True; break; -+ default: -+ break; -+ } -+ if (!retty_ok) -+ break; /* will go to stmt_fail: */ -+ -+ /* Marshal args, do the call, and set the return value to 0x555..555 -+ if this is a conditional call that returns a value and the -+ call is skipped. */ -+ UInt addToSp = 0; -+ RetLoc rloc = mk_RetLoc_INVALID(); -+ doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args ); -+ vassert(is_sane_RetLoc(rloc)); -+ -+ /* Now figure out what to do with the returned value, if any. */ -+ switch (retty) { -+ case Ity_INVALID: { -+ /* No return value. Nothing to do. */ -+ vassert(d->tmp == IRTemp_INVALID); -+ vassert(rloc.pri == RLPri_None); -+ vassert(addToSp == 0); -+ return; -+ } -+ case Ity_I64: case Ity_I32: case Ity_I16: case Ity_I8: { -+ vassert(rloc.pri == RLPri_Int); -+ vassert(addToSp == 0); -+ /* The returned value is in x0. Park it in the register -+ associated with tmp. */ -+ HReg dst = lookupIRTemp(env, d->tmp); -+ addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0()) ); -+ return; -+ } -+ case Ity_V128: { -+ /* The returned value is on the stack, and *retloc tells -+ us where. Fish it off the stack and then move the -+ stack pointer upwards to clear it, as directed by -+ doHelperCall. */ -+ vassert(rloc.pri == RLPri_V128SpRel); -+ vassert(rloc.spOff < 256); // stay sane -+ vassert(addToSp >= 16); // ditto -+ vassert(addToSp < 256); // ditto -+ HReg dst = lookupIRTemp(env, d->tmp); -+ HReg tmp = newVRegI(env); // the address of the returned value -+ addInstr(env, ARM64Instr_FromSP(tmp)); // tmp = SP -+ addInstr(env, ARM64Instr_Arith(tmp, tmp, -+ ARM64RIA_I12((UShort)rloc.spOff, 0), -+ True/*isAdd*/ )); -+ addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, dst, tmp)); -+ addInstr(env, ARM64Instr_AddToSP(addToSp)); -+ return; -+ } -+ default: -+ /*NOTREACHED*/ -+ vassert(0); -+ } -+ break; -+ } -+ -+ /* --------- Load Linked and Store Conditional --------- */ -+ case Ist_LLSC: { -+ if (stmt->Ist.LLSC.storedata == NULL) { -+ /* LL */ -+ IRTemp res = stmt->Ist.LLSC.result; -+ IRType ty = typeOfIRTemp(env->type_env, res); -+ if (ty == Ity_I64 || ty == Ity_I32 -+ || ty == Ity_I16 || ty == Ity_I8) { -+ Int szB = 0; -+ HReg r_dst = lookupIRTemp(env, res); -+ HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr); -+ switch (ty) { -+ case Ity_I8: szB = 1; break; -+ case Ity_I16: szB = 2; break; -+ case Ity_I32: szB = 4; break; -+ case Ity_I64: szB = 8; break; -+ default: vassert(0); -+ } -+ addInstr(env, ARM64Instr_MovI(hregARM64_X4(), raddr)); -+ addInstr(env, ARM64Instr_LdrEX(szB)); -+ addInstr(env, ARM64Instr_MovI(r_dst, hregARM64_X2())); -+ return; -+ } -+ goto stmt_fail; -+ } else { -+ /* SC */ -+ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.storedata); -+ if (tyd == Ity_I64 || tyd == Ity_I32 -+ || tyd == Ity_I16 || tyd == Ity_I8) { -+ Int szB = 0; -+ HReg rD = iselIntExpr_R(env, stmt->Ist.LLSC.storedata); -+ HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr); -+ switch (tyd) { -+ case Ity_I8: szB = 1; break; -+ case Ity_I16: szB = 2; break; -+ case Ity_I32: szB = 4; break; -+ case Ity_I64: szB = 8; break; -+ default: vassert(0); -+ } -+ addInstr(env, ARM64Instr_MovI(hregARM64_X2(), rD)); -+ addInstr(env, ARM64Instr_MovI(hregARM64_X4(), rA)); -+ addInstr(env, ARM64Instr_StrEX(szB)); -+ } else { -+ goto stmt_fail; -+ } -+ /* now r0 is 1 if failed, 0 if success. Change to IR -+ conventions (0 is fail, 1 is success). Also transfer -+ result to r_res. */ -+ IRTemp res = stmt->Ist.LLSC.result; -+ IRType ty = typeOfIRTemp(env->type_env, res); -+ HReg r_res = lookupIRTemp(env, res); -+ ARM64RIL* one = mb_mkARM64RIL_I(1); -+ vassert(ty == Ity_I1); -+ vassert(one); -+ addInstr(env, ARM64Instr_Logic(r_res, hregARM64_X0(), one, -+ ARM64lo_XOR)); -+ /* And be conservative -- mask off all but the lowest bit. */ -+ addInstr(env, ARM64Instr_Logic(r_res, r_res, one, -+ ARM64lo_AND)); -+ return; -+ } -+ break; -+ } -+ -+ /* --------- MEM FENCE --------- */ -+ case Ist_MBE: -+ switch (stmt->Ist.MBE.event) { -+ case Imbe_Fence: -+ addInstr(env, ARM64Instr_MFence()); -+ return; -+//ZZ case Imbe_CancelReservation: -+//ZZ addInstr(env, ARMInstr_CLREX()); -+//ZZ return; -+ default: -+ break; -+ } -+ break; -+ -+ /* --------- INSTR MARK --------- */ -+ /* Doesn't generate any executable code ... */ -+ case Ist_IMark: -+ return; -+ -+ /* --------- NO-OP --------- */ -+ case Ist_NoOp: -+ return; -+ -+ /* --------- EXIT --------- */ -+ case Ist_Exit: { -+ if (stmt->Ist.Exit.dst->tag != Ico_U64) -+ vpanic("isel_arm: Ist_Exit: dst is not a 64-bit value"); -+ -+ ARM64CondCode cc -+ = iselCondCode(env, stmt->Ist.Exit.guard); -+ ARM64AMode* amPC -+ = mk_baseblock_64bit_access_amode(stmt->Ist.Exit.offsIP); -+ -+ /* Case: boring transfer to known address */ -+ if (stmt->Ist.Exit.jk == Ijk_Boring -+ /*ATC || stmt->Ist.Exit.jk == Ijk_Call */ -+ /*ATC || stmt->Ist.Exit.jk == Ijk_Ret */ ) { -+ if (env->chainingAllowed) { -+ /* .. almost always true .. */ -+ /* Skip the event check at the dst if this is a forwards -+ edge. */ -+ Bool toFastEP -+ = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga; -+ if (0) vex_printf("%s", toFastEP ? "Y" : ","); -+ addInstr(env, ARM64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64, -+ amPC, cc, toFastEP)); -+ } else { -+ /* .. very occasionally .. */ -+ /* We can't use chaining, so ask for an assisted transfer, -+ as that's the only alternative that is allowable. */ -+ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, cc, Ijk_Boring)); -+ } -+ return; -+ } -+ -+//ZZ /* Case: assisted transfer to arbitrary address */ -+//ZZ switch (stmt->Ist.Exit.jk) { -+//ZZ /* Keep this list in sync with that in iselNext below */ -+//ZZ case Ijk_ClientReq: -+//ZZ case Ijk_NoDecode: -+//ZZ case Ijk_NoRedir: -+//ZZ case Ijk_Sys_syscall: -+//ZZ case Ijk_InvalICache: -+//ZZ case Ijk_Yield: -+//ZZ { -+//ZZ HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -+//ZZ addInstr(env, ARMInstr_XAssisted(r, amR15T, cc, -+//ZZ stmt->Ist.Exit.jk)); -+//ZZ return; -+//ZZ } -+//ZZ default: -+//ZZ break; -+//ZZ } -+ -+ /* Do we ever expect to see any other kind? */ -+ goto stmt_fail; -+ } -+ -+ default: break; -+ } -+ stmt_fail: -+ ppIRStmt(stmt); -+ vpanic("iselStmt"); -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- ISEL: Basic block terminators (Nexts) ---*/ -+/*---------------------------------------------------------*/ -+ -+static void iselNext ( ISelEnv* env, -+ IRExpr* next, IRJumpKind jk, Int offsIP ) -+{ -+ if (vex_traceflags & VEX_TRACE_VCODE) { -+ vex_printf( "\n-- PUT(%d) = ", offsIP); -+ ppIRExpr( next ); -+ vex_printf( "; exit-"); -+ ppIRJumpKind(jk); -+ vex_printf( "\n"); -+ } -+ -+ /* Case: boring transfer to known address */ -+ if (next->tag == Iex_Const) { -+ IRConst* cdst = next->Iex.Const.con; -+ vassert(cdst->tag == Ico_U64); -+ if (jk == Ijk_Boring || jk == Ijk_Call) { -+ /* Boring transfer to known address */ -+ ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP); -+ if (env->chainingAllowed) { -+ /* .. almost always true .. */ -+ /* Skip the event check at the dst if this is a forwards -+ edge. */ -+ Bool toFastEP -+ = ((Addr64)cdst->Ico.U64) > env->max_ga; -+ if (0) vex_printf("%s", toFastEP ? "X" : "."); -+ addInstr(env, ARM64Instr_XDirect(cdst->Ico.U64, -+ amPC, ARM64cc_AL, -+ toFastEP)); -+ } else { -+ /* .. very occasionally .. */ -+ /* We can't use chaining, so ask for an assisted transfer, -+ as that's the only alternative that is allowable. */ -+ HReg r = iselIntExpr_R(env, next); -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, -+ Ijk_Boring)); -+ } -+ return; -+ } -+ } -+ -+ /* Case: call/return (==boring) transfer to any address */ -+ switch (jk) { -+ case Ijk_Boring: case Ijk_Ret: case Ijk_Call: { -+ HReg r = iselIntExpr_R(env, next); -+ ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP); -+ if (env->chainingAllowed) { -+ addInstr(env, ARM64Instr_XIndir(r, amPC, ARM64cc_AL)); -+ } else { -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, -+ Ijk_Boring)); -+ } -+ return; -+ } -+ default: -+ break; -+ } -+ -+ /* Case: assisted transfer to arbitrary address */ -+ switch (jk) { -+ /* Keep this list in sync with that for Ist_Exit above */ -+ case Ijk_ClientReq: -+ case Ijk_NoDecode: -+ case Ijk_NoRedir: -+ case Ijk_Sys_syscall: -+ case Ijk_InvalICache: -+ case Ijk_FlushDCache: -+//ZZ case Ijk_Yield: -+ { -+ HReg r = iselIntExpr_R(env, next); -+ ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP); -+ addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, jk)); -+ return; -+ } -+ default: -+ break; -+ } -+ -+ vex_printf( "\n-- PUT(%d) = ", offsIP); -+ ppIRExpr( next ); -+ vex_printf( "; exit-"); -+ ppIRJumpKind(jk); -+ vex_printf( "\n"); -+ vassert(0); // are we expecting any other kind? -+} -+ -+ -+/*---------------------------------------------------------*/ -+/*--- Insn selector top-level ---*/ -+/*---------------------------------------------------------*/ -+ -+/* Translate an entire SB to arm64 code. */ -+ -+HInstrArray* iselSB_ARM64 ( IRSB* bb, -+ VexArch arch_host, -+ VexArchInfo* archinfo_host, -+ VexAbiInfo* vbi/*UNUSED*/, -+ Int offs_Host_EvC_Counter, -+ Int offs_Host_EvC_FailAddr, -+ Bool chainingAllowed, -+ Bool addProfInc, -+ Addr64 max_ga ) -+{ -+ Int i, j; -+ HReg hreg, hregHI; -+ ISelEnv* env; -+ UInt hwcaps_host = archinfo_host->hwcaps; -+ ARM64AMode *amCounter, *amFailAddr; -+ -+ /* sanity ... */ -+ vassert(arch_host == VexArchARM64); -+ -+ /* guard against unexpected space regressions */ -+ vassert(sizeof(ARM64Instr) <= 32); -+ -+ /* Make up an initial environment to use. */ -+ env = LibVEX_Alloc(sizeof(ISelEnv)); -+ env->vreg_ctr = 0; -+ -+ /* Set up output code array. */ -+ env->code = newHInstrArray(); -+ -+ /* Copy BB's type env. */ -+ env->type_env = bb->tyenv; -+ -+ /* Make up an IRTemp -> virtual HReg mapping. This doesn't -+ change as we go along. */ -+ env->n_vregmap = bb->tyenv->types_used; -+ env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); -+ env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg)); -+ -+ /* and finally ... */ -+ env->chainingAllowed = chainingAllowed; -+ env->hwcaps = hwcaps_host; -+ env->previous_rm = NULL; -+ env->max_ga = max_ga; -+ -+ /* For each IR temporary, allocate a suitably-kinded virtual -+ register. */ -+ j = 0; -+ for (i = 0; i < env->n_vregmap; i++) { -+ hregHI = hreg = INVALID_HREG; -+ switch (bb->tyenv->types[i]) { -+ case Ity_I1: -+ case Ity_I8: case Ity_I16: case Ity_I32: case Ity_I64: -+ hreg = mkHReg(j++, HRcInt64, True); -+ break; -+ case Ity_I128: -+ hreg = mkHReg(j++, HRcInt64, True); -+ hregHI = mkHReg(j++, HRcInt64, True); -+ break; -+ case Ity_F32: // we'll use HRcFlt64 regs for F32 too -+ case Ity_F64: -+ hreg = mkHReg(j++, HRcFlt64, True); -+ break; -+ case Ity_V128: -+ hreg = mkHReg(j++, HRcVec128, True); -+ break; -+ default: -+ ppIRType(bb->tyenv->types[i]); -+ vpanic("iselBB(arm64): IRTemp type"); -+ } -+ env->vregmap[i] = hreg; -+ env->vregmapHI[i] = hregHI; -+ } -+ env->vreg_ctr = j; -+ -+ /* The very first instruction must be an event check. */ -+ amCounter = ARM64AMode_RI9(hregARM64_X21(), offs_Host_EvC_Counter); -+ amFailAddr = ARM64AMode_RI9(hregARM64_X21(), offs_Host_EvC_FailAddr); -+ addInstr(env, ARM64Instr_EvCheck(amCounter, amFailAddr)); -+ -+ /* Possibly a block counter increment (for profiling). At this -+ point we don't know the address of the counter, so just pretend -+ it is zero. It will have to be patched later, but before this -+ translation is used, by a call to LibVEX_patchProfCtr. */ -+ if (addProfInc) { -+ vassert(0); -+ //addInstr(env, ARM64Instr_ProfInc()); -+ } -+ -+ /* Ok, finally we can iterate over the statements. */ -+ for (i = 0; i < bb->stmts_used; i++) -+ iselStmt(env, bb->stmts[i]); -+ -+ iselNext(env, bb->next, bb->jumpkind, bb->offsIP); -+ -+ /* record the number of vregs we used. */ -+ env->code->n_vregs = env->vreg_ctr; -+ return env->code; -+} -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- end host_arm64_isel.c ---*/ -+/*---------------------------------------------------------------*/ -Index: priv/host_arm_defs.c -=================================================================== ---- priv/host_arm_defs.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_arm_defs.c (.../trunk) (revision 2863) -@@ -790,6 +790,7 @@ - case ARMneon_VTBL: return "vtbl"; - case ARMneon_VRECPS: return "vrecps"; - case ARMneon_VRSQRTS: return "vrecps"; -+ case ARMneon_INVALID: return "??invalid??"; - /* ... */ - default: vpanic("showARMNeonBinOp"); - } -@@ -3334,7 +3335,7 @@ - //case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; - //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; - case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; -+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; - case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; - //case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; - //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; -Index: priv/host_arm_defs.h -=================================================================== ---- priv/host_arm_defs.h (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_arm_defs.h (.../trunk) (revision 2863) -@@ -468,6 +468,7 @@ - ARMneon_VQDMULL, - ARMneon_VRECPS, - ARMneon_VRSQRTS, -+ ARMneon_INVALID - /* ... */ - } - ARMNeonBinOp; -Index: priv/host_arm_isel.c -=================================================================== ---- priv/host_arm_isel.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_arm_isel.c (.../trunk) (revision 2863) -@@ -4254,26 +4254,11 @@ - return res; - } - case Iop_Abs32Fx4: { -- DECLARE_PATTERN(p_vabd_32fx4); -- DEFINE_PATTERN(p_vabd_32fx4, -- unop(Iop_Abs32Fx4, -- binop(Iop_Sub32Fx4, -- bind(0), -- bind(1)))); -- if (matchIRExpr(&mi, p_vabd_32fx4, e)) { -- HReg res = newVRegV(env); -- HReg argL = iselNeonExpr(env, mi.bindee[0]); -- HReg argR = iselNeonExpr(env, mi.bindee[1]); -- addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP, -- res, argL, argR, 0, True)); -- return res; -- } else { -- HReg res = newVRegV(env); -- HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -- addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP, -- res, argL, 0, True)); -- return res; -- } -+ HReg res = newVRegV(env); -+ HReg argL = iselNeonExpr(env, e->Iex.Unop.arg); -+ addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP, -+ res, argL, 0, True)); -+ return res; - } - case Iop_Rsqrte32Fx4: { - HReg res = newVRegV(env); -@@ -4457,15 +4442,6 @@ - res, argL, argR, size, True)); - return res; - } -- case Iop_Add32Fx4: { -- HReg res = newVRegV(env); -- HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -- HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -- UInt size = 0; -- addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP, -- res, argL, argR, size, True)); -- return res; -- } - case Iop_Recps32Fx4: { - HReg res = newVRegV(env); - HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -@@ -4632,15 +4608,6 @@ - res, argL, argR, size, True)); - return res; - } -- case Iop_Sub32Fx4: { -- HReg res = newVRegV(env); -- HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -- HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -- UInt size = 0; -- addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP, -- res, argL, argR, size, True)); -- return res; -- } - case Iop_QSub8Ux16: - case Iop_QSub16Ux8: - case Iop_QSub32Ux4: -@@ -5083,15 +5050,6 @@ - res, argL, argR, size, True)); - return res; - } -- case Iop_Mul32Fx4: { -- HReg res = newVRegV(env); -- HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1); -- HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2); -- UInt size = 0; -- addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP, -- res, argL, argR, size, True)); -- return res; -- } - case Iop_Mull8Ux8: - case Iop_Mull16Ux4: - case Iop_Mull32Ux2: { -@@ -5352,6 +5310,23 @@ - res, argL, argR, imm4, True)); - return res; - } -+ case Iop_Mul32Fx4: -+ case Iop_Sub32Fx4: -+ case Iop_Add32Fx4: { -+ HReg res = newVRegV(env); -+ HReg argL = iselNeonExpr(env, triop->arg2); -+ HReg argR = iselNeonExpr(env, triop->arg3); -+ UInt size = 0; -+ ARMNeonBinOp op = ARMneon_INVALID; -+ switch (triop->op) { -+ case Iop_Mul32Fx4: op = ARMneon_VMULFP; break; -+ case Iop_Sub32Fx4: op = ARMneon_VSUBFP; break; -+ case Iop_Add32Fx4: op = ARMneon_VADDFP; break; -+ default: vassert(0); -+ } -+ addInstr(env, ARMInstr_NBinary(op, res, argL, argR, size, True)); -+ return res; -+ } - default: - break; - } -@@ -6218,7 +6193,7 @@ - case Ijk_NoDecode: - case Ijk_NoRedir: - case Ijk_Sys_syscall: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Yield: - { - HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -@@ -6310,7 +6285,7 @@ - case Ijk_NoDecode: - case Ijk_NoRedir: - case Ijk_Sys_syscall: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Yield: - { - HReg r = iselIntExpr_R(env, next); -Index: priv/host_generic_reg_alloc2.c -=================================================================== ---- priv/host_generic_reg_alloc2.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_generic_reg_alloc2.c (.../trunk) (revision 2863) -@@ -399,9 +399,9 @@ - not at each insn processed. */ - Bool do_sanity_check; - -- vassert(0 == (guest_sizeB % 32)); -- vassert(0 == (LibVEX_N_SPILL_BYTES % 32)); -- vassert(0 == (N_SPILL64S % 4)); -+ vassert(0 == (guest_sizeB % 16)); -+ vassert(0 == (LibVEX_N_SPILL_BYTES % 16)); -+ vassert(0 == (N_SPILL64S % 2)); - - /* The live range numbers are signed shorts, and so limiting the - number of insns to 15000 comfortably guards against them -Index: priv/host_generic_simd64.c -=================================================================== ---- priv/host_generic_simd64.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_generic_simd64.c (.../trunk) (revision 2863) -@@ -1553,7 +1553,11 @@ - - /* ----------------------------------------------------- */ - /* Signed and unsigned integer division, that behave like -- the ARMv7 UDIV ansd SDIV instructions. */ -+ the ARMv7 UDIV ansd SDIV instructions. -+ -+ sdiv32 also behaves like 64-bit v8 SDIV on w-regs. -+ udiv32 also behaves like 64-bit v8 UDIV on w-regs. -+*/ - /* ----------------------------------------------------- */ - - UInt h_calc_udiv32_w_arm_semantics ( UInt x, UInt y ) -@@ -1564,11 +1568,19 @@ - return x / y; - } - -+ULong h_calc_udiv64_w_arm_semantics ( ULong x, ULong y ) -+{ -+ // Division by zero --> zero -+ if (UNLIKELY(y == 0)) return 0; -+ // C requires rounding towards zero, which is also what we need. -+ return x / y; -+} -+ - Int h_calc_sdiv32_w_arm_semantics ( Int x, Int y ) - { - // Division by zero --> zero - if (UNLIKELY(y == 0)) return 0; -- // The single case that produces an unpresentable result -+ // The single case that produces an unrepresentable result - if (UNLIKELY( ((UInt)x) == ((UInt)0x80000000) - && ((UInt)y) == ((UInt)0xFFFFFFFF) )) - return (Int)(UInt)0x80000000; -@@ -1579,7 +1591,22 @@ - return x / y; - } - -+Long h_calc_sdiv64_w_arm_semantics ( Long x, Long y ) -+{ -+ // Division by zero --> zero -+ if (UNLIKELY(y == 0)) return 0; -+ // The single case that produces an unrepresentable result -+ if (UNLIKELY( ((ULong)x) == ((ULong)0x8000000000000000ULL ) -+ && ((ULong)y) == ((ULong)0xFFFFFFFFFFFFFFFFULL ) )) -+ return (Long)(ULong)0x8000000000000000ULL; -+ // Else return the result rounded towards zero. C89 says -+ // this is implementation defined (in the signed case), but gcc -+ // promises to round towards zero. Nevertheless, at startup, -+ // in main_main.c, do a check for that. -+ return x / y; -+} - -+ - /*---------------------------------------------------------------*/ - /*--- end host_generic_simd64.c ---*/ - /*---------------------------------------------------------------*/ -Index: priv/host_generic_simd64.h -=================================================================== ---- priv/host_generic_simd64.h (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_generic_simd64.h (.../trunk) (revision 2863) -@@ -166,9 +166,12 @@ - - // Signed and unsigned integer division, that behave like - // the ARMv7 UDIV and SDIV instructions. --extern UInt h_calc_udiv32_w_arm_semantics ( UInt, UInt ); --extern Int h_calc_sdiv32_w_arm_semantics ( Int, Int ); -+extern UInt h_calc_udiv32_w_arm_semantics ( UInt, UInt ); -+extern ULong h_calc_udiv64_w_arm_semantics ( ULong, ULong ); -+extern Int h_calc_sdiv32_w_arm_semantics ( Int, Int ); -+extern Long h_calc_sdiv64_w_arm_semantics ( Long, Long ); - -+ - #endif /* ndef __VEX_HOST_GENERIC_SIMD64_H */ - - /*---------------------------------------------------------------*/ -Index: priv/host_mips_defs.c -=================================================================== ---- priv/host_mips_defs.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_mips_defs.c (.../trunk) (revision 2863) -@@ -37,7 +37,7 @@ - #include "host_mips_defs.h" - - /* guest_COND offset. */ --#define COND_OFFSET(__mode64) (__mode64 ? 612 : 316) -+#define COND_OFFSET(__mode64) (__mode64 ? 612 : 448) - - /* Register number for guest state pointer in host code. */ - #define GuestSP 23 -@@ -81,7 +81,7 @@ - - /* But specific for real regs. */ - vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || -- hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64); -+ hregClass(reg) == HRcFlt32 || hregClass(reg) == HRcFlt64); - - /* But specific for real regs. */ - switch (hregClass(reg)) { -@@ -91,7 +91,6 @@ - vex_printf("%s", ireg32_names[r]); - return; - case HRcInt64: -- vassert(mode64); - r = hregNumber (reg); - vassert (r >= 0 && r < 32); - vex_printf ("%s", ireg32_names[r]); -@@ -773,6 +772,12 @@ - case Mfp_CVTWD: - ret = "cvt.w.d"; - break; -+ case Mfp_CVTLD: -+ ret = "cvt.l.d"; -+ break; -+ case Mfp_CVTLS: -+ ret = "cvt.l.s"; -+ break; - case Mfp_TRUWD: - ret = "trunc.w.d"; - break; -@@ -797,10 +802,20 @@ - case Mfp_CEILLD: - ret = "ceil.l.d"; - break; -- case Mfp_CMP: -- ret = "C.cond.d"; -+ case Mfp_CMP_UN: -+ ret = "c.un.d"; - break; -+ case Mfp_CMP_EQ: -+ ret = "c.eq.d"; -+ break; -+ case Mfp_CMP_LT: -+ ret = "c.lt.d"; -+ break; -+ case Mfp_CMP_NGT: -+ ret = "c.ngt.d"; -+ break; - default: -+ vex_printf("Unknown op: %d", op); - vpanic("showMIPSFpOp"); - break; - } -@@ -1497,8 +1512,7 @@ - - } - --MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL, HReg srcR, -- UChar cond1) -+MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL, HReg srcR) - { - MIPSInstr *i = LibVEX_Alloc(sizeof(MIPSInstr)); - i->tag = Min_FpCompare; -@@ -1506,7 +1520,6 @@ - i->Min.FpCompare.dst = dst; - i->Min.FpCompare.srcL = srcL; - i->Min.FpCompare.srcR = srcR; -- i->Min.FpCompare.cond1 = cond1; - return i; - } - -@@ -1811,7 +1824,6 @@ - ppHRegMIPS(i->Min.FpCompare.srcL, mode64); - vex_printf(","); - ppHRegMIPS(i->Min.FpCompare.srcR, mode64); -- vex_printf(" cond: %c", i->Min.FpCompare.cond1); - return; - case Min_FpMulAcc: - vex_printf("%s ", showMIPSFpOp(i->Min.FpMulAcc.op)); -@@ -1864,7 +1876,7 @@ - return; - } - case Min_FpGpMove: { -- vex_printf("%s", showMIPSFpGpMoveOp(i->Min.FpGpMove.op)); -+ vex_printf("%s ", showMIPSFpGpMoveOp(i->Min.FpGpMove.op)); - ppHRegMIPS(i->Min.FpGpMove.dst, mode64); - vex_printf(", "); - ppHRegMIPS(i->Min.FpGpMove.src, mode64); -@@ -2101,7 +2113,7 @@ - addHRegUse(u, HRmRead, i->Min.FpGpMove.src); - return; - case Min_MoveCond: -- addHRegUse(u, HRmWrite, i->Min.MoveCond.dst); -+ addHRegUse(u, HRmModify, i->Min.MoveCond.dst); - addHRegUse(u, HRmRead, i->Min.MoveCond.src); - addHRegUse(u, HRmRead, i->Min.MoveCond.cond); - return; -@@ -2380,7 +2392,6 @@ - static UChar fregNo(HReg r, Bool mode64) - { - UInt n; -- vassert(hregClass(r) == (mode64 ? HRcFlt64 : HRcFlt32)); - vassert(!hregIsVirtual(r)); - n = hregNumber(r); - vassert(n <= 31); -@@ -2390,7 +2401,6 @@ - static UChar dregNo(HReg r) - { - UInt n; -- vassert(hregClass(r) == HRcFlt64); - vassert(!hregIsVirtual(r)); - n = hregNumber(r); - vassert(n <= 31); -@@ -3455,8 +3465,9 @@ - case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break; - /* case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; */ - case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; -+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; - case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; -+ case Ijk_SigILL: trcval = VEX_TRC_JMP_SIGILL; break; - case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; - /* case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; */ - case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break; -@@ -3886,8 +3897,13 @@ - p = mkFormR(p, 0x11, 0x15, 0, fr_src, fr_dst, 0x20); - break; - case Mfp_CVTLS: -- fr_dst = fregNo(i->Min.FpConvert.dst, mode64); -- fr_src = dregNo(i->Min.FpConvert.src); -+ if (mode64) { -+ fr_dst = fregNo(i->Min.FpConvert.dst, mode64); -+ fr_src = dregNo(i->Min.FpConvert.src); -+ } else { -+ fr_dst = dregNo(i->Min.FpConvert.dst); -+ fr_src = fregNo(i->Min.FpConvert.src, mode64); -+ } - p = mkFormR(p, 0x11, 0x10, 0, fr_src, fr_dst, 0x25); - break; - case Mfp_CVTLD: -@@ -3973,19 +3989,35 @@ - } - - case Min_FpCompare: { -- UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64); -+ UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64); - UInt fr_srcL = dregNo(i->Min.FpCompare.srcL); - UInt fr_srcR = dregNo(i->Min.FpCompare.srcR); - -+ UInt op; - switch (i->Min.FpConvert.op) { -- case Mfp_CMP: -- p = mkFormR(p, 0x11, 0x11, fr_srcL, fr_srcR, 0, -- (i->Min.FpCompare.cond1 + 48)); -- p = mkFormR(p, 0x11, 0x2, r_dst, 31, 0, 0); -+ case Mfp_CMP_UN: -+ op = 1; - break; -+ case Mfp_CMP_EQ: -+ op = 2; -+ break; -+ case Mfp_CMP_LT: -+ op = 12; -+ break; -+ case Mfp_CMP_NGT: -+ op = 15; -+ break; - default: - goto bad; - } -+ /* c.cond.d fr_srcL, fr_srcR -+ cfc1 r_dst, $31 -+ srl r_dst, r_dst, 23 -+ andi r_dst, r_dst, 1 */ -+ p = mkFormR(p, 0x11, 0x11, fr_srcL, fr_srcR, 0, op + 48); -+ p = mkFormR(p, 0x11, 0x2, r_dst, 31, 0, 0); -+ p = mkFormS(p, 0, r_dst, 0, r_dst, 23, 2); -+ p = mkFormI(p, 12, r_dst, r_dst, 1); - goto done; - } - -Index: priv/host_mips_defs.h -=================================================================== ---- priv/host_mips_defs.h (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_mips_defs.h (.../trunk) (revision 2863) -@@ -366,9 +366,12 @@ - Mfp_CVTSD, Mfp_CVTSW, Mfp_CVTWD, - Mfp_CVTWS, Mfp_CVTDL, Mfp_CVTSL, Mfp_CVTLS, Mfp_CVTLD, Mfp_TRULS, Mfp_TRULD, - Mfp_TRUWS, Mfp_TRUWD, Mfp_FLOORWS, Mfp_FLOORWD, Mfp_ROUNDWS, Mfp_ROUNDWD, -- Mfp_CVTDW, Mfp_CMP, Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD, -- Mfp_CVTDS, Mfp_ROUNDLD, Mfp_FLOORLD -+ Mfp_CVTDW, Mfp_CEILWS, Mfp_CEILWD, Mfp_CEILLS, Mfp_CEILLD, Mfp_CVTDS, -+ Mfp_ROUNDLD, Mfp_FLOORLD, - -+ /* FP compare */ -+ Mfp_CMP_UN, Mfp_CMP_EQ, Mfp_CMP_LT, Mfp_CMP_NGT -+ - } MIPSFpOp; - - extern const HChar *showMIPSFpOp(MIPSFpOp); -@@ -664,7 +667,7 @@ - HReg src2, HReg src3 ); - extern MIPSInstr *MIPSInstr_FpConvert(MIPSFpOp op, HReg dst, HReg src); - extern MIPSInstr *MIPSInstr_FpCompare(MIPSFpOp op, HReg dst, HReg srcL, -- HReg srcR, UChar cond1); -+ HReg srcR); - extern MIPSInstr *MIPSInstr_FpMulAcc(MIPSFpOp op, HReg dst, HReg srcML, - HReg srcMR, HReg srcAcc); - extern MIPSInstr *MIPSInstr_FpLdSt(Bool isLoad, UChar sz, HReg, MIPSAMode *); -Index: priv/host_mips_isel.c -=================================================================== ---- priv/host_mips_isel.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_mips_isel.c (.../trunk) (revision 2863) -@@ -47,12 +47,14 @@ - ZERO0 Reserved - GPR12:22 Allocateable - 23 GuestStatePointer -- 23 Allocateable - SP StackFramePointer - RA LinkRegister */ - - static Bool mode64 = False; - -+/* Host CPU has FPU and 32 dbl. prec. FP registers. */ -+static Bool fp_mode64 = False; -+ - /* GPR register class for mips32/64 */ - #define HRcGPR(__mode64) (__mode64 ? HRcInt64 : HRcInt32) - -@@ -60,7 +62,7 @@ - #define HRcFPR(__mode64) (__mode64 ? HRcFlt64 : HRcFlt32) - - /* guest_COND offset */ --#define COND_OFFSET(__mode64) (__mode64 ? 612 : 316) -+#define COND_OFFSET(__mode64) (__mode64 ? 612 : 448) - - /*---------------------------------------------------------*/ - /*--- ISelEnv ---*/ -@@ -117,6 +119,7 @@ - - UInt hwcaps; - Bool mode64; -+ Bool fp_mode64; - - Bool chainingAllowed; - Addr64 max_ga; -@@ -180,7 +183,7 @@ - - static HReg newVRegF(ISelEnv * env) - { -- HReg reg = mkHReg(env->vreg_ctr, HRcFPR(env->mode64), -+ HReg reg = mkHReg(env->vreg_ctr, HRcFPR(env->fp_mode64), - True /*virtual reg */ ); - env->vreg_ctr++; - return reg; -@@ -230,12 +233,13 @@ - static MIPSRH *iselWordExpr_RH_wrk(ISelEnv * env, Bool syned, IRExpr * e); - static MIPSRH *iselWordExpr_RH(ISelEnv * env, Bool syned, IRExpr * e); - --/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter being an immediate in -- the range 1 .. 31 inclusive. Used for doing shift amounts. */ -+/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter being an -+ immediate in the range 1 .. 31 inclusive. Used for doing shift amounts. */ - static MIPSRH *iselWordExpr_RH5u_wrk(ISelEnv * env, IRExpr * e); - static MIPSRH *iselWordExpr_RH5u(ISelEnv * env, IRExpr * e); - --/* In 64-bit mode ONLY */ -+/* Compute an I8 into a reg-or-6-bit-unsigned-immediate, the latter being an -+ immediate in the range 1 .. 63 inclusive. Used for doing shift amounts. */ - static MIPSRH *iselWordExpr_RH6u_wrk(ISelEnv * env, IRExpr * e); - static MIPSRH *iselWordExpr_RH6u(ISelEnv * env, IRExpr * e); - -@@ -1119,29 +1123,24 @@ - - /* Create in dst, the IRCmpF64Result encoded result. */ - /* chech for EQ */ -- addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR, -- toUChar(2))); -- addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, r_ccMIPS, tmp, -- MIPSRH_Imm(False, 22))); -+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_EQ, tmp, r_srcL, r_srcR)); -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_ccMIPS, tmp, -+ MIPSRH_Imm(False, 1))); - /* chech for UN */ -- addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR, -- toUChar(1))); -- addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, tmp, -- MIPSRH_Imm(False, 23))); -+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_UN, tmp, r_srcL, r_srcR)); - addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS, - MIPSRH_Reg(tmp))); - /* chech for LT */ -- addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR, -- toUChar(12))); -- addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, -- tmp, MIPSRH_Imm(False, 21))); -+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_LT, tmp, r_srcL, r_srcR)); -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, -+ tmp, MIPSRH_Imm(False, 2))); - addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS, - MIPSRH_Reg(tmp))); - /* chech for GT */ -- addInstr(env, MIPSInstr_FpCompare(Mfp_CMP, tmp, r_srcL, r_srcR, -- toUChar(15))); -- addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, tmp, -- MIPSRH_Imm(False, 20))); -+ addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_NGT, -+ tmp, r_srcL, r_srcR)); -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, tmp, -+ MIPSRH_Imm(False, 3))); - - addInstr(env, MIPSInstr_Alu(Malu_NOR, tmp, tmp, MIPSRH_Reg(tmp))); - addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, tmp, -@@ -1789,34 +1788,14 @@ - if ((ty == Ity_I8 || ty == Ity_I16 || - ty == Ity_I32 || ((ty == Ity_I64))) && - typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1) { -+ HReg r_dst = iselWordExpr_R(env, e->Iex.ITE.iffalse); -+ HReg r1 = iselWordExpr_R(env, e->Iex.ITE.iftrue); -+ HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond); - /* -- * r_dst = cond && r1 -- * cond = not(cond) -- * tmp = cond && r0 -- * r_dst = tmp + r_dst -+ * r_dst = r0 -+ * movn r_dst, r1, r_cond - */ -- HReg r0 = iselWordExpr_R(env, e->Iex.ITE.iffalse); -- HReg r1 = iselWordExpr_R(env, e->Iex.ITE.iftrue); -- HReg r_cond_1 = iselWordExpr_R(env, e->Iex.ITE.cond); -- HReg r_cond = newVRegI(env); -- HReg mask = newVRegI(env); -- HReg r_dst = newVRegI(env); -- HReg r_tmp = newVRegI(env); -- HReg r_tmp1 = newVRegI(env); -- HReg r_cond_neg = newVRegI(env); -- /* r_cond = 0 - r_cond_1 */ -- addInstr(env, MIPSInstr_LI(mask, 0x0)); -- addInstr(env, MIPSInstr_Alu(Malu_SUB, r_cond, -- mask, MIPSRH_Reg(r_cond_1))); -- -- addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp, r_cond, MIPSRH_Reg(r1))); -- addInstr(env, MIPSInstr_Alu(Malu_NOR, r_cond_neg, r_cond, -- MIPSRH_Reg(r_cond))); -- addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp1, r_cond_neg, -- MIPSRH_Reg(r0))); -- addInstr(env, MIPSInstr_Alu(Malu_ADD, r_dst, r_tmp, -- MIPSRH_Reg(r_tmp1))); -- -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, r_dst, r1, r_cond)); - return r_dst; - } - break; -@@ -2009,7 +1988,6 @@ - static MIPSRH *iselWordExpr_RH6u ( ISelEnv * env, IRExpr * e ) - { - MIPSRH *ri; -- vassert(env->mode64); - ri = iselWordExpr_RH6u_wrk(env, e); - /* sanity checks ... */ - switch (ri->tag) { -@@ -2436,7 +2414,8 @@ - /* Check if borrow is nedded. */ - addInstr(env, MIPSInstr_Cmp(False, size32, borrow, xLo, yLo, cc)); - -- addInstr(env, MIPSInstr_Alu(Malu_ADD, yHi, yHi, MIPSRH_Reg(borrow))); -+ addInstr(env, MIPSInstr_Alu(Malu_ADD, yHi, yHi, -+ MIPSRH_Reg(borrow))); - addInstr(env, MIPSInstr_Alu(Malu_SUB, tHi, xHi, MIPSRH_Reg(yHi))); - - *rHi = tHi; -@@ -2505,177 +2484,309 @@ - } - - case Iop_Shr64: { -- HReg xLo, xHi; -- HReg tLo = newVRegI(env); -- HReg tLo1 = newVRegI(env); -- HReg tHi = newVRegI(env); -- HReg tmp = newVRegI(env); -- HReg tmp2 = newVRegI(env); -- HReg tmp3 = newVRegI(env); -- HReg mask = newVRegI(env); -- HReg tMask = newVRegI(env); -- HReg discard = newVRegI(env); -- HReg discard1 = newVRegI(env); -+#if defined (_MIPSEL) -+ /* 64-bit logical shift right based on what gcc generates: -+ : -+ nor v0, zero, a2 -+ sll a3, a1, 0x1 -+ sllv a3, a3, v0 -+ srlv v0, a0, a2 -+ srlv v1, a1, a2 -+ andi a0, a2, 0x20 -+ or v0, a3, v0 -+ movn v0, v1, a0 -+ jr ra -+ movn v1, zero, a0 -+ */ -+ HReg a0, a1; -+ HReg a0tmp = newVRegI(env); -+ HReg a2 = newVRegI(env); -+ HReg a3 = newVRegI(env); -+ HReg v0 = newVRegI(env); -+ HReg v1 = newVRegI(env); -+ HReg zero = newVRegI(env); -+ MIPSRH *sa = NULL; - -- /* We assume any literal values are on the second operand. */ -- iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -- MIPSRH *ri_srcR = NULL; -- MIPSRH *ri_srcR_sub = NULL; -+ iselInt64Expr(&a1, &a0, env, e->Iex.Binop.arg1); -+ sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); - -- ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2); -- ri_srcR_sub = iselWordExpr_RH(env, True /*signed */ , -- e->Iex.Binop.arg2); -+ if (sa->tag == Mrh_Imm) { -+ addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16)); -+ } -+ else { -+ addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg, -+ MIPSRH_Imm(False, 0x3f))); -+ } - -- /* Steps: -- 1. Take shift-amount (arg2) least significant bits from upper -- half of 64bit input value (arg1) -- 2. Shift upper half -- 3. Shift lower half -- 4. Put discarded bits (those from step 1) to most significant -- bit positions of lower half */ -+ addInstr(env, MIPSInstr_LI(zero, 0x00000000)); -+ /* nor v0, zero, a2 */ -+ addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2))); -+ /* sll a3, a1, 0x1 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ a3, a1, MIPSRH_Imm(False, 0x1))); -+ /* sllv a3, a3, v0 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ a3, a3, MIPSRH_Reg(v0))); -+ /* srlv v0, a0, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */, -+ v0, a0, MIPSRH_Reg(a2))); -+ /* srlv v1, a1, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */, -+ v1, a1, MIPSRH_Reg(a2))); -+ /* andi a0, a2, 0x20 */ -+ addInstr(env, MIPSInstr_Alu(Malu_AND, a0tmp, a2, -+ MIPSRH_Imm(False, 0x20))); -+ /* or v0, a3, v0 */ -+ addInstr(env, MIPSInstr_Alu(Malu_OR, v0, a3, MIPSRH_Reg(v0))); - -- /* Mask for extraction of bits that will be discarded. */ -- addInstr(env, MIPSInstr_LI(tmp, 0xffffffff)); -- addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /*32bit shift */, -- tMask, tmp, ri_srcR)); -- addInstr(env, MIPSInstr_Alu(Malu_NOR, mask, -- tMask, MIPSRH_Reg(tMask))); -+ /* movn v0, v1, a0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v0, v1, a0tmp)); -+ /* movn v1, zero, a0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, zero, a0tmp)); - -- /* Extraction of bits that will be discarded. */ -- addInstr(env, MIPSInstr_Alu(Malu_AND, discard, xHi, -- MIPSRH_Reg(mask))); -- /* Position discarded bits to most significant bit positions. */ -- addInstr(env, MIPSInstr_LI(tmp3, 32)); -- addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, -- tmp3, ri_srcR_sub)); -- addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /*32bit shift */, -- discard1, discard, MIPSRH_Reg(tmp2))); -+ *rHi = v1; -+ *rLo = v0; -+ return; -+#elif defined (_MIPSEB) -+ /* 64-bit logical shift right based on what gcc generates: -+ : -+ nor v0, zero, a2 -+ sll a3, a0, 0x1 -+ sllv a3, a3, v0 -+ srlv v1, a1, a2 -+ andi v0, a2, 0x20 -+ or v1, a3, v1 -+ srlv a2, a0, a2 -+ movn v1, a2, v0 -+ movn a2, zero, v0 -+ jr ra -+ move v0, a2 -+ */ -+ HReg a0, a1; -+ HReg a2 = newVRegI(env); -+ HReg a2tmp = newVRegI(env); -+ HReg a3 = newVRegI(env); -+ HReg v0 = newVRegI(env); -+ HReg v1 = newVRegI(env); -+ HReg zero = newVRegI(env); -+ MIPSRH *sa = NULL; - -- addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /*32bit shift */, -- tHi, xHi, ri_srcR)); -- addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /*32bit shift */, -- tLo1, xLo, ri_srcR)); -+ iselInt64Expr(&a0, &a1, env, e->Iex.Binop.arg1); -+ sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); - -- addInstr(env, MIPSInstr_Alu(Malu_OR, tLo, -- tLo1, MIPSRH_Reg(discard1))); -- *rHi = tHi; -- *rLo = tLo; -+ if (sa->tag == Mrh_Imm) { -+ addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16)); -+ } -+ else { -+ addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg, -+ MIPSRH_Imm(False, 0x3f))); -+ } -+ -+ addInstr(env, MIPSInstr_LI(zero, 0x00000000)); -+ /* nor v0, zero, a2 */ -+ addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2))); -+ /* sll a3, a0, 0x1 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ a3, a0, MIPSRH_Imm(False, 0x1))); -+ /* sllv a3, a3, v0 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ a3, a3, MIPSRH_Reg(v0))); -+ /* srlv v1, a1, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */, -+ v1, a1, MIPSRH_Reg(a2))); -+ /* andi v0, a2, 0x20 */ -+ addInstr(env, MIPSInstr_Alu(Malu_AND, v0, a2, -+ MIPSRH_Imm(False, 0x20))); -+ /* or v1, a3, v1 */ -+ addInstr(env, MIPSInstr_Alu(Malu_OR, v1, a3, MIPSRH_Reg(v1))); -+ /* srlv a2, a0, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */, -+ a2tmp, a0, MIPSRH_Reg(a2))); -+ -+ /* movn v1, a2, v0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, a2tmp, v0)); -+ /* movn a2, zero, v0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, a2tmp, zero, v0)); -+ /* move v0, a2 */ -+ addInstr(env, mk_iMOVds_RR(v0, a2tmp)); -+ -+ *rHi = v0; -+ *rLo = v1; - return; -+#endif - } -+ - case Iop_Shl64: { -- HReg xLo, xHi; -- HReg tLo = newVRegI(env); -- HReg tHi1 = newVRegI(env); -- HReg tHi = newVRegI(env); -- HReg tmp = newVRegI(env); -- HReg tmp2 = newVRegI(env); -- HReg tmp3 = newVRegI(env); -- HReg mask = newVRegI(env); -- HReg tMask = newVRegI(env); -- HReg discard = newVRegI(env); -- HReg discard1 = newVRegI(env); -+ /* 64-bit shift left based on what gcc generates: -+ : -+ nor v0,zero,a2 -+ srl a3,a0,0x1 -+ srlv a3,a3,v0 -+ sllv v1,a1,a2 -+ andi v0,a2,0x20 -+ or v1,a3,v1 -+ sllv a2,a0,a2 -+ movn v1,a2,v0 -+ movn a2,zero,v0 -+ jr ra -+ move v0,a2 -+ */ -+ HReg a0, a1; -+ HReg a2 = newVRegI(env); -+ HReg a3 = newVRegI(env); -+ HReg v0 = newVRegI(env); -+ HReg v1 = newVRegI(env); -+ HReg zero = newVRegI(env); -+ MIPSRH *sa = NULL; - -- /* We assume any literal values are on the second operand. */ -- iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -- MIPSRH *ri_srcR = NULL; -- MIPSRH *ri_srcR_sub = NULL; -+ iselInt64Expr(&a1, &a0, env, e->Iex.Binop.arg1); -+ sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); - -- ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2); -- ri_srcR_sub = iselWordExpr_RH(env, True /*signed */ , -- e->Iex.Binop.arg2); -+ if (sa->tag == Mrh_Imm) { -+ addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16)); -+ } -+ else { -+ addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg, -+ MIPSRH_Imm(False, 0x3f))); -+ } - -- /* Steps: -- 1. Take shift-amount (arg2) most significant bits from lower -- half of 64bit input value (arg1) -- 2. Shift lower half -- 3. Shift upper half -- 4. Put discarded bits (those from step 1) to least significant -- bit positions of upper half */ -+ addInstr(env, MIPSInstr_LI(zero, 0x00000000)); -+ /* nor v0, zero, a2 */ -+ addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2))); -+ /* srl a3, a0, 0x1 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */, -+ a3, a0, MIPSRH_Imm(False, 0x1))); -+ /* srlv a3, a3, v0 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */, -+ a3, a3, MIPSRH_Reg(v0))); -+ /* sllv v1, a1, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ v1, a1, MIPSRH_Reg(a2))); -+ /* andi v0, a2, 0x20 */ -+ addInstr(env, MIPSInstr_Alu(Malu_AND, v0, a2, -+ MIPSRH_Imm(False, 0x20))); -+ /* or v1, a3, v1 */ -+ addInstr(env, MIPSInstr_Alu(Malu_OR, v1, a3, MIPSRH_Reg(v1))); -+ /* sllv a2, a0, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ a2, a0, MIPSRH_Reg(a2))); - -- /* Mask for extraction of bits that will be discarded. */ -- addInstr(env, MIPSInstr_LI(tmp, 0xffffffff)); -- addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /*32bit shift */, -- tMask, tmp, ri_srcR)); -- addInstr(env, MIPSInstr_Alu(Malu_NOR, mask, -- tMask, MIPSRH_Reg(tMask))); -+ /* movn v1, a2, v0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, a2, v0)); -+ /* movn a2, zero, v0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, a2, zero, v0)); -+ addInstr(env, mk_iMOVds_RR(v0, a2)); - -- /* Extraction of bits that will be discarded. */ -- addInstr(env, MIPSInstr_Alu(Malu_AND, discard, xLo, -- MIPSRH_Reg(mask))); -- /* Position discarded bits to least significant bit positions. */ -- addInstr(env, MIPSInstr_LI(tmp3, 32)); -- addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, -- tmp3, ri_srcR_sub)); -- addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /*32bit shift */, -- discard1, discard, MIPSRH_Reg(tmp2))); -+ *rHi = v1; -+ *rLo = v0; -+ return; -+ } - -- addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /*32bit shift */, -- tHi1, xHi, ri_srcR)); -- addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /*32bit shift */, -- tLo, xLo, ri_srcR)); -+ case Iop_Sar64: { -+ /* 64-bit arithmetic shift right based on what gcc generates: -+ : -+ nor v0, zero, a2 -+ sll a3, a1, 0x1 -+ sllv a3, a3, v0 -+ srlv v0, a0, a2 -+ srav v1, a1, a2 -+ andi a0, a2, 0x20 -+ sra a1, a1, 0x1f -+ or v0, a3, v0 -+ movn v0, v1, a0 -+ jr ra -+ movn v1, a1, a0 -+ */ -+ HReg a0, a1; -+ HReg a0tmp = newVRegI(env); -+ HReg a1tmp = newVRegI(env); -+ HReg a2 = newVRegI(env); -+ HReg a3 = newVRegI(env); -+ HReg v0 = newVRegI(env); -+ HReg v1 = newVRegI(env); -+ HReg zero = newVRegI(env); -+ MIPSRH *sa = NULL; - -- addInstr(env, MIPSInstr_Alu(Malu_OR, tHi, -- tHi1, MIPSRH_Reg(discard1))); -- *rHi = tHi; -- *rLo = tLo; -+ iselInt64Expr(&a1, &a0, env, e->Iex.Binop.arg1); -+ sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2); -+ -+ if (sa->tag == Mrh_Imm) { -+ addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16)); -+ } -+ else { -+ addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg, -+ MIPSRH_Imm(False, 0x3f))); -+ } -+ -+ addInstr(env, MIPSInstr_LI(zero, 0x00000000)); -+ /* nor v0, zero, a2 */ -+ addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2))); -+ /* sll a3, a1, 0x1 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ a3, a1, MIPSRH_Imm(False, 0x1))); -+ /* sllv a3, a3, v0 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */, -+ a3, a3, MIPSRH_Reg(v0))); -+ /* srlv v0, a0, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */, -+ v0, a0, MIPSRH_Reg(a2))); -+ /* srav v1, a1, a2 */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True /* 32bit shift */, -+ v1, a1, MIPSRH_Reg(a2))); -+ /* andi a0, a2, 0x20 */ -+ addInstr(env, MIPSInstr_Alu(Malu_AND, a0tmp, a2, -+ MIPSRH_Imm(False, 0x20))); -+ /* sra a1, a1, 0x1f */ -+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True /* 32bit shift */, -+ a1tmp, a1, MIPSRH_Imm(False, 0x1f))); -+ /* or v0, a3, v0 */ -+ addInstr(env, MIPSInstr_Alu(Malu_OR, v0, a3, MIPSRH_Reg(v0))); -+ -+ /* movn v0, v1, a0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v0, v1, a0tmp)); -+ /* movn v1, a1, a0 */ -+ addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, a1tmp, a0tmp)); -+ -+ *rHi = v1; -+ *rLo = v0; - return; - } -- case Iop_Sar64: { -- HReg xLo, xHi; -- HReg tLo = newVRegI(env); -- HReg tLo1 = newVRegI(env); -- HReg tHi = newVRegI(env); -- HReg tmp = newVRegI(env); -- HReg tmp2 = newVRegI(env); -- HReg tmp3 = newVRegI(env); -- HReg mask = newVRegI(env); -- HReg tMask = newVRegI(env); -- HReg discard = newVRegI(env); -- HReg discard1 = newVRegI(env); - -- /* We assume any literal values are on the second operand. */ -- iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1); -- MIPSRH *ri_srcR = NULL; -- MIPSRH *ri_srcR_sub = NULL; -+ case Iop_F32toI64S: { -+ HReg tmpD = newVRegD(env); -+ HReg valF = iselFltExpr(env, e->Iex.Binop.arg2); -+ HReg tLo = newVRegI(env); -+ HReg tHi = newVRegI(env); -+ MIPSAMode *am_addr; - -- ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2); -- ri_srcR_sub = iselWordExpr_RH(env, True /*signed */ , -- e->Iex.Binop.arg2); -+ /* CVTLS tmpD, valF */ -+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, MIPSInstr_FpConvert(Mfp_CVTLS, tmpD, valF)); -+ set_MIPS_rounding_default(env); - -- /* Steps: -- 1. Take shift-amount (arg2) least significant bits from upper -- half of 64bit input value (arg1) -- 2. Shift upper half -- 3. Shift lower half -- 4. Put discarded bits (those from step 1) to most significant -- bit positions of lower half */ -+ sub_from_sp(env, 16); /* Move SP down 16 bytes */ -+ am_addr = MIPSAMode_IR(0, StackPointer(mode64)); - -- /* Mask for extraction of bits that will be discarded. */ -- addInstr(env, MIPSInstr_LI(tmp, 0xffffffff)); -- addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /*32bit shift */, -- tMask, tmp, ri_srcR)); -- addInstr(env, MIPSInstr_Alu(Malu_NOR, mask, -- tMask, MIPSRH_Reg(tMask))); -+ /* store as F64 */ -+ addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, tmpD, -+ am_addr)); -+ /* load as 2xI32 */ -+#if defined (_MIPSEL) -+ addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64)); -+ addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeFloat(am_addr), -+ mode64)); -+#elif defined (_MIPSEB) -+ addInstr(env, MIPSInstr_Load(4, tHi, am_addr, mode64)); -+ addInstr(env, MIPSInstr_Load(4, tLo, nextMIPSAModeFloat(am_addr), -+ mode64)); -+#endif - -- /* Extraction of bits that will be discarded. */ -- addInstr(env, MIPSInstr_Alu(Malu_AND, discard, xHi, -- MIPSRH_Reg(mask))); -- /* Position discarded bits to most significant bit positions. */ -- addInstr(env, MIPSInstr_LI(tmp3, 32)); -- addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, -- tmp3, ri_srcR_sub)); -- addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /*32bit shift */, -- discard1, discard, MIPSRH_Reg(tmp2))); -+ /* Reset SP */ -+ add_to_sp(env, 16); - -- addInstr(env, MIPSInstr_Shft(Mshft_SRA, True /*32bit shift */, -- tHi, xHi, ri_srcR)); -- addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /*32bit shift */, -- tLo1, xLo, ri_srcR)); -- -- addInstr(env, MIPSInstr_Alu(Malu_OR, tLo, -- tLo1, MIPSRH_Reg(discard1))); - *rHi = tHi; - *rLo = tLo; -+ - return; - } - -@@ -2695,7 +2806,7 @@ - - addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, src, - MIPSRH_Imm(False, 31))); -- addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, src, -+ addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, tmp, - MIPSRH_Imm(False, 31))); - - addInstr(env, mk_iMOVds_RR(tHi, tmp)); -@@ -2748,35 +2859,31 @@ - } - - case Iop_Left64: { -- HReg yLo, yHi, borrow; -+ HReg yHi, yLo; - HReg tHi = newVRegI(env); - HReg tLo = newVRegI(env); -+ HReg tmp = newVRegI(env); -+ HReg tmp1 = newVRegI(env); -+ HReg tmp2 = newVRegI(env); - HReg zero = newVRegI(env); -- Bool size32 = True; - MIPSCondCode cc = MIPScc_LO; - -- borrow = newVRegI(env); -- - /* yHi:yLo = arg */ - iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg); - /* zero = 0 */ - addInstr(env, MIPSInstr_LI(zero, 0x00000000)); - -- /* tLo = 0 - yLo */ -- addInstr(env, MIPSInstr_Alu(Malu_SUB, tLo, zero, MIPSRH_Reg(yLo))); -+ /* tmp2:tmp1 = 0 - (yHi:yLo)*/ -+ addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, zero, MIPSRH_Reg(yLo))); -+ addInstr(env, MIPSInstr_Cmp(False, True, tmp1, zero, tmp2, cc)); -+ addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp, zero, MIPSRH_Reg(yHi))); -+ addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp1, tmp, MIPSRH_Reg(tmp1))); - -- /* Check if borrow is needed. */ -- addInstr(env, MIPSInstr_Cmp(False, size32, borrow, zero, yLo, cc)); -- -- /* tHi = 0 - (yHi + borrow) */ -- addInstr(env, MIPSInstr_Alu(Malu_ADD, -- yHi, yHi, MIPSRH_Reg(borrow))); -- addInstr(env, MIPSInstr_Alu(Malu_SUB, tHi, zero, MIPSRH_Reg(yHi))); -- /* So now we have tHi:tLo = -arg. To finish off, or 'arg' -+ /* So now we have tmp2:tmp1 = -arg. To finish off, or 'arg' - back in, so as to give the final result - tHi:tLo = arg | -arg. */ -- addInstr(env, MIPSInstr_Alu(Malu_OR, tHi, tHi, MIPSRH_Reg(yHi))); -- addInstr(env, MIPSInstr_Alu(Malu_OR, tLo, tLo, MIPSRH_Reg(yLo))); -+ addInstr(env, MIPSInstr_Alu(Malu_OR, tHi, yHi, MIPSRH_Reg(tmp1))); -+ addInstr(env, MIPSInstr_Alu(Malu_OR, tLo, yLo, MIPSRH_Reg(tmp2))); - *rHi = tHi; - *rLo = tLo; - return; -@@ -2865,7 +2972,7 @@ - static HReg iselFltExpr_wrk(ISelEnv * env, IRExpr * e) - { - IRType ty = typeOfIRExpr(env->type_env, e); -- vassert(ty == Ity_F32 || (ty == Ity_F64 && mode64)); -+ vassert(ty == Ity_F32 || (ty == Ity_F64 && fp_mode64)); - - if (e->tag == Iex_RdTmp) { - return lookupIRTemp(env, e->Iex.RdTmp.tmp); -@@ -2872,26 +2979,31 @@ - } - - if (e->tag == Iex_Load) { -- MIPSAMode *am_addr; -- HReg r_dst = newVRegF(env); - vassert(e->Iex.Load.ty == Ity_F32 -- || (e->Iex.Load.ty == Ity_F64 && mode64)); -- am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty); -- if (mode64 && e->Iex.Load.ty == Ity_F64) -+ || (e->Iex.Load.ty == Ity_F64 && fp_mode64)); -+ HReg r_dst; -+ MIPSAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty); -+ if (e->Iex.Load.ty == Ity_F64) { -+ r_dst = newVRegD(env); - addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, r_dst, am_addr)); -- else -+ } else { -+ r_dst = newVRegF(env); - addInstr(env, MIPSInstr_FpLdSt(True /*load */, 4, r_dst, am_addr)); -+ } - return r_dst; - } - - if (e->tag == Iex_Get) { -- HReg r_dst = newVRegF(env); - MIPSAMode *am_addr = MIPSAMode_IR(e->Iex.Get.offset, - GuestStatePointer(mode64)); -- if (mode64) -+ HReg r_dst; -+ if (e->Iex.Load.ty == Ity_F64) { -+ r_dst = newVRegD(env); - addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, r_dst, am_addr)); -- else -+ } else { -+ r_dst = newVRegF(env); - addInstr(env, MIPSInstr_FpLdSt(True /*load */, 4, r_dst, am_addr)); -+ } - return r_dst; - } - -@@ -2908,7 +3020,7 @@ - return r_dst; - } - case Iop_F32toF64: { -- vassert(mode64); -+ vassert(fp_mode64); - HReg src = iselFltExpr(env, e->Iex.Unop.arg); - HReg dst = newVRegD(env); - -@@ -2916,24 +3028,29 @@ - return dst; - } - case Iop_ReinterpI64asF64: { -- vassert(mode64); -- HReg fr_src = iselWordExpr_R(env, e->Iex.Unop.arg); -- HReg r_dst = newVRegF(env); -- -- /* Move Doubleword to Floating Point -- dmtc1 r_dst, fr_src */ -- addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_dmtc1, r_dst, fr_src)); -- -+ HReg r_dst; -+ if (mode64) { -+ HReg fr_src = iselWordExpr_R(env, e->Iex.Unop.arg); -+ r_dst = newVRegF(env); -+ /* Move Doubleword to Floating Point -+ dmtc1 r_dst, fr_src */ -+ addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_dmtc1, r_dst, fr_src)); -+ } else { -+ HReg Hi, Lo; -+ r_dst = newVRegD(env); -+ iselInt64Expr(&Hi, &Lo, env, e->Iex.Unop.arg); -+ r_dst = mk_LoadRR32toFPR(env, Hi, Lo); /* 2*I32 -> F64 */ -+ } - return r_dst; - } - case Iop_I32StoF64: { -- vassert(mode64); -+ vassert(fp_mode64); - HReg dst = newVRegF(env); - HReg tmp = newVRegF(env); - HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); - - /* Move Word to Floating Point -- mtc1 tmp1, r_src */ -+ mtc1 tmp, r_src */ - addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mtc1, tmp, r_src)); - - /* and do convert */ -@@ -3010,7 +3127,7 @@ - op = Mfp_DIVS; - break; - case Iop_DivF64: -- vassert(mode64); -+ vassert(fp_mode64); - op = Mfp_DIVD; - break; - case Iop_MulF32: -@@ -3017,7 +3134,7 @@ - op = Mfp_MULS; - break; - case Iop_MulF64: -- vassert(mode64); -+ vassert(fp_mode64); - op = Mfp_MULD; - break; - case Iop_AddF32: -@@ -3024,7 +3141,7 @@ - op = Mfp_ADDS; - break; - case Iop_AddF64: -- vassert(mode64); -+ vassert(fp_mode64); - op = Mfp_ADDD; - break; - case Iop_SubF32: -@@ -3031,7 +3148,7 @@ - op = Mfp_SUBS; - break; - case Iop_SubF64: -- vassert(mode64); -+ vassert(fp_mode64); - op = Mfp_SUBD; - break; - default: -@@ -3101,24 +3218,30 @@ - - case Iop_I64StoF64: { - HReg r_dst = newVRegF(env); -- - MIPSAMode *am_addr; -- HReg fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2); -- HReg tmp = newVRegF(env); -+ HReg tmp, fr_src; -+ if (mode64) { -+ tmp = newVRegF(env); -+ fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ /* Move SP down 8 bytes */ -+ sub_from_sp(env, 8); -+ am_addr = MIPSAMode_IR(0, StackPointer(mode64)); - -- /* Move SP down 8 bytes */ -- sub_from_sp(env, 8); -- am_addr = MIPSAMode_IR(0, StackPointer(mode64)); -+ /* store as I64 */ -+ addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64)); - -- /* store as I64 */ -- addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64)); -+ /* load as Ity_F64 */ -+ addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, tmp, am_addr)); - -- /* load as Ity_F64 */ -- addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, tmp, am_addr)); -+ /* Reset SP */ -+ add_to_sp(env, 8); -+ } else { -+ HReg Hi, Lo; -+ tmp = newVRegD(env); -+ iselInt64Expr(&Hi, &Lo, env, e->Iex.Binop.arg2); -+ tmp = mk_LoadRR32toFPR(env, Hi, Lo); /* 2*I32 -> F64 */ -+ } - -- /* Reset SP */ -- add_to_sp(env, 8); -- - set_MIPS_rounding_mode(env, e->Iex.Binop.arg1); - addInstr(env, MIPSInstr_FpConvert(Mfp_CVTDL, r_dst, tmp)); - set_MIPS_rounding_default(env); -@@ -3128,24 +3251,30 @@ - - case Iop_I64StoF32: { - HReg r_dst = newVRegF(env); -- - MIPSAMode *am_addr; -- HReg fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2); -- HReg tmp = newVRegF(env); -+ HReg fr_src, tmp; -+ if (mode64) { -+ tmp = newVRegF(env); -+ fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2); -+ /* Move SP down 8 bytes */ -+ sub_from_sp(env, 8); -+ am_addr = MIPSAMode_IR(0, StackPointer(mode64)); - -- /* Move SP down 8 bytes */ -- sub_from_sp(env, 8); -- am_addr = MIPSAMode_IR(0, StackPointer(mode64)); -+ /* store as I64 */ -+ addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64)); - -- /* store as I64 */ -- addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64)); -+ /* load as Ity_F64 */ -+ addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, tmp, am_addr)); - -- /* load as Ity_F64 */ -- addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, tmp, am_addr)); -+ /* Reset SP */ -+ add_to_sp(env, 8); -+ } else { -+ HReg Hi, Lo; -+ tmp = newVRegD(env); -+ iselInt64Expr(&Hi, &Lo, env, e->Iex.Binop.arg2); -+ tmp = mk_LoadRR32toFPR(env, Hi, Lo); /* 2*I32 -> F64 */ -+ } - -- /* Reset SP */ -- add_to_sp(env, 8); -- - set_MIPS_rounding_mode(env, e->Iex.Binop.arg1); - addInstr(env, MIPSInstr_FpConvert(Mfp_CVTSL, r_dst, tmp)); - set_MIPS_rounding_default(env); -@@ -3155,7 +3284,6 @@ - - case Iop_SqrtF32: - case Iop_SqrtF64: { -- /* first arg is rounding mode; we ignore it. */ - Bool sz32 = e->Iex.Binop.op == Iop_SqrtF32; - HReg src = iselFltExpr(env, e->Iex.Binop.arg2); - HReg dst = newVRegF(env); -@@ -3368,26 +3496,22 @@ - if (e->tag == Iex_Binop) { - switch (e->Iex.Binop.op) { - case Iop_RoundF64toInt: { -- HReg valD = iselDblExpr(env, e->Iex.Binop.arg2); -- MIPSRH *fmt = iselWordExpr_RH(env, False, e->Iex.Binop.arg1); -- HReg valD1 = newVRegD(env); -+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2); -+ HReg dst = newVRegD(env); - -- if (fmt->Mrh.Imm.imm16 == 0x3) -- addInstr(env, MIPSInstr_FpConvert(Mfp_TRULD, valD1, valD)); -- else if (fmt->Mrh.Imm.imm16 == 0x2) -- addInstr(env, MIPSInstr_FpConvert(Mfp_CEILLD, valD1, valD)); -- else if (fmt->Mrh.Imm.imm16 == 0x0) -- addInstr(env, MIPSInstr_FpConvert(Mfp_ROUNDLD, valD1, valD)); -- else -- vassert(0); -- return valD1; -+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1); -+ addInstr(env, MIPSInstr_FpConvert(Mfp_CVTLD, dst, src)); -+ set_MIPS_rounding_default(env); -+ -+ return dst; - } - - case Iop_SqrtF64: { -- /* first arg is rounding mode; we ignore it. */ - HReg src = iselDblExpr(env, e->Iex.Binop.arg2); - HReg dst = newVRegD(env); -+ set_MIPS_rounding_mode(env, e->Iex.Binop.arg1); - addInstr(env, MIPSInstr_FpUnary(Mfp_SQRTD, dst, src)); -+ set_MIPS_rounding_default(env); - return dst; - } - -@@ -3412,6 +3536,9 @@ - case Iop_DivF64: - op = Mfp_DIVD; - break; -+ case Iop_DivF32: -+ op = Mfp_DIVS; -+ break; - case Iop_MulF64: - op = Mfp_MULD; - break; -@@ -3424,7 +3551,9 @@ - default: - vassert(0); - } -+ set_MIPS_rounding_mode(env, e->Iex.Triop.details->arg1); - addInstr(env, MIPSInstr_FpBinary(op, dst, argL, argR)); -+ set_MIPS_rounding_default(env); - return dst; - } - default: -@@ -3872,7 +4001,7 @@ - case Ijk_SigFPE_IntDiv: - case Ijk_SigFPE_IntOvf: - case Ijk_Sys_syscall: -- case Ijk_TInval: -+ case Ijk_InvalICache: - { - HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); - addInstr(env, MIPSInstr_XAssisted(r, amPC, cc, -@@ -3971,11 +4100,12 @@ - case Ijk_NoDecode: - case Ijk_NoRedir: - case Ijk_SigBUS: -+ case Ijk_SigILL: - case Ijk_SigTRAP: - case Ijk_SigFPE_IntDiv: - case Ijk_SigFPE_IntOvf: - case Ijk_Sys_syscall: -- case Ijk_TInval: { -+ case Ijk_InvalICache: { - HReg r = iselWordExpr_R(env, next); - MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64)); - addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL, jk)); -@@ -4021,11 +4151,16 @@ - || VEX_PRID_COMP_NETLOGIC); - - mode64 = arch_host != VexArchMIPS32; -+#if (__mips_fpr==64) -+ fp_mode64 = ((VEX_MIPS_REV(hwcaps_host) == VEX_PRID_CPU_32FPR) -+ || arch_host == VexArchMIPS64); -+#endif - - /* Make up an initial environment to use. */ - env = LibVEX_Alloc(sizeof(ISelEnv)); - env->vreg_ctr = 0; - env->mode64 = mode64; -+ env->fp_mode64 = fp_mode64; - - /* Set up output code array. */ - env->code = newHInstrArray(); -@@ -4090,6 +4225,7 @@ - default: - ppIRType(bb->tyenv->types[i]); - vpanic("iselBB(mips): IRTemp type"); -+ break; - } - env->vregmap[i] = hreg; - env->vregmapHI[i] = hregHI; -Index: priv/host_ppc_defs.c -=================================================================== ---- priv/host_ppc_defs.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_ppc_defs.c (.../trunk) (revision 2863) -@@ -4270,7 +4270,7 @@ - case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break; - //case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; - case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; -+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; - case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; - case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; - //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; -Index: priv/host_ppc_isel.c -=================================================================== ---- priv/host_ppc_isel.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_ppc_isel.c (.../trunk) (revision 2863) -@@ -4929,11 +4929,8 @@ - } - } - -- case Iop_Add32Fx4: fpop = Pavfp_ADDF; goto do_32Fx4; -- case Iop_Sub32Fx4: fpop = Pavfp_SUBF; goto do_32Fx4; - case Iop_Max32Fx4: fpop = Pavfp_MAXF; goto do_32Fx4; - case Iop_Min32Fx4: fpop = Pavfp_MINF; goto do_32Fx4; -- case Iop_Mul32Fx4: fpop = Pavfp_MULF; goto do_32Fx4; - case Iop_CmpEQ32Fx4: fpop = Pavfp_CMPEQF; goto do_32Fx4; - case Iop_CmpGT32Fx4: fpop = Pavfp_CMPGTF; goto do_32Fx4; - case Iop_CmpGE32Fx4: fpop = Pavfp_CMPGEF; goto do_32Fx4; -@@ -5213,6 +5210,25 @@ - return dst; - } - -+ case Iop_Add32Fx4: fpop = Pavfp_ADDF; goto do_32Fx4_with_rm; -+ case Iop_Sub32Fx4: fpop = Pavfp_SUBF; goto do_32Fx4_with_rm; -+ case Iop_Mul32Fx4: fpop = Pavfp_MULF; goto do_32Fx4_with_rm; -+ do_32Fx4_with_rm: -+ { -+ HReg argL = iselVecExpr(env, triop->arg2); -+ HReg argR = iselVecExpr(env, triop->arg3); -+ HReg dst = newVRegV(env); -+ /* FIXME: this is bogus, in the sense that Altivec ignores -+ FPSCR.RM, at least for some FP operations. So setting the -+ RM is pointless. This is only really correct in the case -+ where the RM is known, at JIT time, to be Irrm_NEAREST, -+ since -- at least for Altivec FP add/sub/mul -- the -+ emitted insn is hardwired to round to nearest. */ -+ set_FPU_rounding_mode(env, triop->arg1); -+ addInstr(env, PPCInstr_AvBin32Fx4(fpop, dst, argL, argR)); -+ return dst; -+ } -+ - default: - break; - } /* switch (e->Iex.Triop.op) */ -@@ -5746,7 +5762,7 @@ - case Ijk_SigBUS: - case Ijk_SigTRAP: - case Ijk_Sys_syscall: -- case Ijk_TInval: -+ case Ijk_InvalICache: - { - HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); - addInstr(env, PPCInstr_XAssisted(r, amCIA, cc, -@@ -5846,7 +5862,7 @@ - case Ijk_SigBUS: - case Ijk_SigTRAP: - case Ijk_Sys_syscall: -- case Ijk_TInval: -+ case Ijk_InvalICache: - { - HReg r = iselWordExpr_R(env, next); - PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64)); -Index: priv/host_s390_defs.c -=================================================================== ---- priv/host_s390_defs.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_s390_defs.c (.../trunk) (revision 2863) -@@ -273,7 +273,11 @@ - } - - --/* Construct an AMODE for accessing the guest state at OFFSET */ -+/* Construct an AMODE for accessing the guest state at OFFSET. -+ OFFSET can be at most 3 * sizeof(VexGuestS390XState) + LibVEX_N_SPILL_BYTES -+ which may be too large for a B12 addressing mode. -+ Use a B20 amode as a fallback which will be safe for any offset. -+*/ - s390_amode * - s390_amode_for_guest_state(Int offset) - { -@@ -280,6 +284,9 @@ - if (fits_unsigned_12bit(offset)) - return s390_amode_b12(offset, s390_hreg_guest_state_pointer()); - -+ if (fits_signed_20bit(offset)) -+ return s390_amode_b20(offset, s390_hreg_guest_state_pointer()); -+ - vpanic("invalid guest state offset"); - } - -@@ -458,7 +465,6 @@ - s390_amode *am; - - vassert(offsetB >= 0); -- vassert(offsetB <= (1 << 12)); /* because we use b12 amode */ - vassert(!hregIsVirtual(rreg)); - - *i1 = *i2 = NULL; -@@ -485,7 +491,6 @@ - s390_amode *am; - - vassert(offsetB >= 0); -- vassert(offsetB <= (1 << 12)); /* because we use b12 amode */ - vassert(!hregIsVirtual(rreg)); - - *i1 = *i2 = NULL; -@@ -5861,7 +5866,6 @@ - } else { - /* From 16 bytes to smaller size */ - vassert(is_valid_fp128_regpair(op_hi, op_lo)); -- vassert(hregIsInvalid(dst_lo)); - } - - insn->tag = S390_INSN_BFP_CONVERT; -@@ -5891,11 +5895,11 @@ - - - s390_insn * --s390_insn_bfp128_convert_from(UChar size, s390_bfp_conv_t tag, HReg dst, -- HReg op_hi, HReg op_lo, -+s390_insn_bfp128_convert_from(UChar size, s390_bfp_conv_t tag, HReg dst_hi, -+ HReg dst_lo, HReg op_hi, HReg op_lo, - s390_bfp_round_t rounding_mode) - { -- return s390_insn_bfp128_convert(size, tag, dst, INVALID_HREG, op_hi, op_lo, -+ return s390_insn_bfp128_convert(size, tag, dst_hi, dst_lo, op_hi, op_lo, - rounding_mode); - } - -@@ -6192,7 +6196,6 @@ - } else { - /* From 16 bytes to smaller size */ - vassert(is_valid_fp128_regpair(op_hi, op_lo)); -- vassert(hregIsInvalid(dst_lo)); - } - - insn->tag = S390_INSN_DFP_CONVERT; -@@ -6222,11 +6225,11 @@ - - - s390_insn * --s390_insn_dfp128_convert_from(UChar size, s390_dfp_conv_t tag, HReg dst, -- HReg op_hi, HReg op_lo, -+s390_insn_dfp128_convert_from(UChar size, s390_dfp_conv_t tag, HReg dst_hi, -+ HReg dst_lo, HReg op_hi, HReg op_lo, - s390_dfp_round_t rounding_mode) - { -- return s390_insn_dfp128_convert(size, tag, dst, INVALID_HREG, op_hi, op_lo, -+ return s390_insn_dfp128_convert(size, tag, dst_hi, dst_lo, op_hi, op_lo, - rounding_mode); - } - -@@ -6461,7 +6464,7 @@ - case Ijk_EmFail: return "EmFail"; - case Ijk_NoDecode: return "NoDecode"; - case Ijk_MapFail: return "MapFail"; -- case Ijk_TInval: return "Invalidate"; -+ case Ijk_InvalICache: return "Invalidate"; - case Ijk_NoRedir: return "NoRedir"; - case Ijk_SigTRAP: return "SigTRAP"; - case Ijk_SigSEGV: return "SigSEGV"; -@@ -9780,7 +9783,7 @@ - case Ijk_EmFail: trcval = VEX_TRC_JMP_EMFAIL; break; - case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; - case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; -+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; - case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; - case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; - case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; -Index: priv/host_s390_defs.h -=================================================================== ---- priv/host_s390_defs.h (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_s390_defs.h (.../trunk) (revision 2863) -@@ -665,8 +665,8 @@ - s390_insn *s390_insn_bfp128_convert_to(UChar size, s390_bfp_conv_t, - HReg dst_hi, HReg dst_lo, HReg op); - s390_insn *s390_insn_bfp128_convert_from(UChar size, s390_bfp_conv_t, -- HReg dst, HReg op_hi, HReg op_lo, -- s390_bfp_round_t); -+ HReg dst_hi, HReg dst_lo, HReg op_hi, -+ HReg op_lo, s390_bfp_round_t); - s390_insn *s390_insn_dfp_binop(UChar size, s390_dfp_binop_t, HReg dst, - HReg op2, HReg op3, - s390_dfp_round_t rounding_mode); -@@ -699,8 +699,8 @@ - s390_insn *s390_insn_dfp128_convert_to(UChar size, s390_dfp_conv_t, - HReg dst_hi, HReg dst_lo, HReg op); - s390_insn *s390_insn_dfp128_convert_from(UChar size, s390_dfp_conv_t, -- HReg dst, HReg op_hi, HReg op_lo, -- s390_dfp_round_t); -+ HReg dst_hi, HReg dst_lo, HReg op_hi, -+ HReg op_lo, s390_dfp_round_t); - s390_insn *s390_insn_dfp128_reround(UChar size, HReg dst_hi, HReg dst_lo, - HReg op2, HReg op3_hi, HReg op3_lo, - s390_dfp_round_t); -Index: priv/host_s390_isel.c -=================================================================== ---- priv/host_s390_isel.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_s390_isel.c (.../trunk) (revision 2863) -@@ -1257,7 +1257,8 @@ - addInstr(env, s390_insn_move(8, f15, op_lo)); - - rounding_mode = get_bfp_rounding_mode(env, arg1); -- addInstr(env, s390_insn_bfp128_convert_from(size, conv, res, f13, f15, -+ addInstr(env, s390_insn_bfp128_convert_from(size, conv, res, -+ INVALID_HREG, f13, f15, - rounding_mode)); - return res; - } -@@ -1290,7 +1291,8 @@ - addInstr(env, s390_insn_move(8, f15, op_lo)); - - rounding_mode = get_dfp_rounding_mode(env, arg1); -- addInstr(env, s390_insn_dfp128_convert_from(size, dconv, res, f13, -+ addInstr(env, s390_insn_dfp128_convert_from(size, dconv, res, -+ INVALID_HREG, f13, - f15, rounding_mode)); - return res; - } -@@ -2455,7 +2457,7 @@ - - case Iop_F128toF64: - case Iop_F128toF32: { -- HReg op_hi, op_lo, f13, f15; -+ HReg op_hi, op_lo, f12, f13, f14, f15; - s390_bfp_round_t rounding_mode; - - conv = op == Iop_F128toF32 ? S390_BFP_F128_TO_F32 -@@ -2463,8 +2465,10 @@ - - s390_isel_float128_expr(&op_hi, &op_lo, env, left); - -- /* We use non-virtual registers as pairs (f13, f15) */ -+ /* We use non-virtual registers as pairs (f13, f15) and (f12, f14)) */ -+ f12 = make_fpr(12); - f13 = make_fpr(13); -+ f14 = make_fpr(14); - f15 = make_fpr(15); - - /* operand --> (f13, f15) */ -@@ -2471,7 +2475,8 @@ - addInstr(env, s390_insn_move(8, f13, op_hi)); - addInstr(env, s390_insn_move(8, f15, op_lo)); - -- dst = newVRegF(env); -+ /* result --> (f12, f14) */ -+ - /* load-rounded has a rounding mode field when the floating point - extension facility is installed. */ - if (s390_host_has_fpext) { -@@ -2480,8 +2485,12 @@ - set_bfp_rounding_mode_in_fpc(env, irrm); - rounding_mode = S390_BFP_ROUND_PER_FPC; - } -- addInstr(env, s390_insn_bfp128_convert_from(size, conv, dst, f13, f15, -- rounding_mode)); -+ -+ addInstr(env, s390_insn_bfp128_convert_from(size, conv, f12, f14, -+ f13, f15, rounding_mode)); -+ dst = newVRegF(env); -+ addInstr(env, s390_insn_move(8, dst, f12)); -+ - return dst; - } - } -@@ -3044,7 +3053,7 @@ - } - - case Iop_D128toD64: { -- HReg op_hi, op_lo, f13, f15; -+ HReg op_hi, op_lo, f12, f13, f14, f15; - s390_dfp_round_t rounding_mode; - - conv = S390_DFP_D128_TO_D64; -@@ -3051,8 +3060,10 @@ - - s390_isel_dfp128_expr(&op_hi, &op_lo, env, left); - -- /* We use non-virtual registers as pairs (f13, f15) */ -+ /* We use non-virtual registers as pairs (f13, f15) and (f12, f14) */ -+ f12 = make_fpr(12); - f13 = make_fpr(13); -+ f14 = make_fpr(14); - f15 = make_fpr(15); - - /* operand --> (f13, f15) */ -@@ -3059,7 +3070,8 @@ - addInstr(env, s390_insn_move(8, f13, op_hi)); - addInstr(env, s390_insn_move(8, f15, op_lo)); - -- dst = newVRegF(env); -+ /* result --> (f12, f14) */ -+ - /* load-rounded has a rounding mode field when the floating point - extension facility is installed. */ - if (s390_host_has_fpext) { -@@ -3068,8 +3080,11 @@ - set_dfp_rounding_mode_in_fpc(env, irrm); - rounding_mode = S390_DFP_ROUND_PER_FPC_0; - } -- addInstr(env, s390_insn_dfp128_convert_from(size, conv, dst, f13, f15, -- rounding_mode)); -+ addInstr(env, s390_insn_dfp128_convert_from(size, conv, f12, f14, -+ f13, f15, rounding_mode)); -+ dst = newVRegF(env); -+ addInstr(env, s390_insn_move(8, dst, f12)); -+ - return dst; - } - -@@ -3921,7 +3936,7 @@ - case Ijk_EmFail: - case Ijk_EmWarn: - case Ijk_NoDecode: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Sys_syscall: - case Ijk_ClientReq: - case Ijk_NoRedir: -@@ -4036,7 +4051,7 @@ - case Ijk_EmFail: - case Ijk_EmWarn: - case Ijk_NoDecode: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Sys_syscall: - case Ijk_ClientReq: - case Ijk_NoRedir: -Index: priv/host_x86_defs.c -=================================================================== ---- priv/host_x86_defs.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_x86_defs.c (.../trunk) (revision 2863) -@@ -2023,11 +2023,25 @@ - case Xfp_COS: *p++ = 0xD9; *p++ = 0xFF; break; - case Xfp_2XM1: *p++ = 0xD9; *p++ = 0xF0; break; - case Xfp_MOV: break; -- case Xfp_TAN: p = do_ffree_st7(p); /* since fptan pushes 1.0 */ -- *p++ = 0xD9; *p++ = 0xF2; /* fptan */ -- *p++ = 0xD9; *p++ = 0xF7; /* fincstp */ -- break; -- default: vpanic("do_fop1_st: unknown op"); -+ case Xfp_TAN: -+ /* fptan pushes 1.0 on the FP stack, except when the argument -+ is out of range. Hence we have to do the instruction, -+ then inspect C2 to see if there is an out of range -+ condition. If there is, we skip the fincstp that is used -+ by the in-range case to get rid of this extra 1.0 -+ value. */ -+ p = do_ffree_st7(p); /* since fptan sometimes pushes 1.0 */ -+ *p++ = 0xD9; *p++ = 0xF2; // fptan -+ *p++ = 0x50; // pushl %eax -+ *p++ = 0xDF; *p++ = 0xE0; // fnstsw %ax -+ *p++ = 0x66; *p++ = 0xA9; -+ *p++ = 0x00; *p++ = 0x04; // testw $0x400,%ax -+ *p++ = 0x75; *p++ = 0x02; // jnz after_fincstp -+ *p++ = 0xD9; *p++ = 0xF7; // fincstp -+ *p++ = 0x58; // after_fincstp: popl %eax -+ break; -+ default: -+ vpanic("do_fop1_st: unknown op"); - } - return p; - } -@@ -2539,7 +2553,7 @@ - case Ijk_EmWarn: trcval = VEX_TRC_JMP_EMWARN; break; - case Ijk_MapFail: trcval = VEX_TRC_JMP_MAPFAIL; break; - case Ijk_NoDecode: trcval = VEX_TRC_JMP_NODECODE; break; -- case Ijk_TInval: trcval = VEX_TRC_JMP_TINVAL; break; -+ case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break; - case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; - case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; - case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; -Index: priv/host_x86_isel.c -=================================================================== ---- priv/host_x86_isel.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/host_x86_isel.c (.../trunk) (revision 2863) -@@ -3147,6 +3147,11 @@ - HReg src = iselDblExpr(env, e->Iex.Binop.arg2); - /* XXXROUNDINGFIXME */ - /* set roundingmode here */ -+ /* Note that X86Instr_FpUnary(Xfp_TAN,..) sets the condition -+ codes. I don't think that matters, since this insn -+ selector never generates such an instruction intervening -+ between an flag-setting instruction and a flag-using -+ instruction. */ - addInstr(env, X86Instr_FpUnary(fpop,src,res)); - if (fpop != Xfp_SQRT - && fpop != Xfp_NEG && fpop != Xfp_ABS) -@@ -3554,12 +3559,8 @@ - case Iop_CmpLT32Fx4: op = Xsse_CMPLTF; goto do_32Fx4; - case Iop_CmpLE32Fx4: op = Xsse_CMPLEF; goto do_32Fx4; - case Iop_CmpUN32Fx4: op = Xsse_CMPUNF; goto do_32Fx4; -- case Iop_Add32Fx4: op = Xsse_ADDF; goto do_32Fx4; -- case Iop_Div32Fx4: op = Xsse_DIVF; goto do_32Fx4; - case Iop_Max32Fx4: op = Xsse_MAXF; goto do_32Fx4; - case Iop_Min32Fx4: op = Xsse_MINF; goto do_32Fx4; -- case Iop_Mul32Fx4: op = Xsse_MULF; goto do_32Fx4; -- case Iop_Sub32Fx4: op = Xsse_SUBF; goto do_32Fx4; - do_32Fx4: - { - HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); -@@ -3574,12 +3575,8 @@ - case Iop_CmpLT64Fx2: op = Xsse_CMPLTF; goto do_64Fx2; - case Iop_CmpLE64Fx2: op = Xsse_CMPLEF; goto do_64Fx2; - case Iop_CmpUN64Fx2: op = Xsse_CMPUNF; goto do_64Fx2; -- case Iop_Add64Fx2: op = Xsse_ADDF; goto do_64Fx2; -- case Iop_Div64Fx2: op = Xsse_DIVF; goto do_64Fx2; - case Iop_Max64Fx2: op = Xsse_MAXF; goto do_64Fx2; - case Iop_Min64Fx2: op = Xsse_MINF; goto do_64Fx2; -- case Iop_Mul64Fx2: op = Xsse_MULF; goto do_64Fx2; -- case Iop_Sub64Fx2: op = Xsse_SUBF; goto do_64Fx2; - do_64Fx2: - { - HReg argL = iselVecExpr(env, e->Iex.Binop.arg1); -@@ -3790,6 +3787,50 @@ - } /* switch (e->Iex.Binop.op) */ - } /* if (e->tag == Iex_Binop) */ - -+ -+ if (e->tag == Iex_Triop) { -+ IRTriop *triop = e->Iex.Triop.details; -+ switch (triop->op) { -+ -+ case Iop_Add32Fx4: op = Xsse_ADDF; goto do_32Fx4_w_rm; -+ case Iop_Sub32Fx4: op = Xsse_SUBF; goto do_32Fx4_w_rm; -+ case Iop_Mul32Fx4: op = Xsse_MULF; goto do_32Fx4_w_rm; -+ case Iop_Div32Fx4: op = Xsse_DIVF; goto do_32Fx4_w_rm; -+ do_32Fx4_w_rm: -+ { -+ HReg argL = iselVecExpr(env, triop->arg2); -+ HReg argR = iselVecExpr(env, triop->arg3); -+ HReg dst = newVRegV(env); -+ addInstr(env, mk_vMOVsd_RR(argL, dst)); -+ /* XXXROUNDINGFIXME */ -+ /* set roundingmode here */ -+ addInstr(env, X86Instr_Sse32Fx4(op, argR, dst)); -+ return dst; -+ } -+ -+ case Iop_Add64Fx2: op = Xsse_ADDF; goto do_64Fx2_w_rm; -+ case Iop_Sub64Fx2: op = Xsse_SUBF; goto do_64Fx2_w_rm; -+ case Iop_Mul64Fx2: op = Xsse_MULF; goto do_64Fx2_w_rm; -+ case Iop_Div64Fx2: op = Xsse_DIVF; goto do_64Fx2_w_rm; -+ do_64Fx2_w_rm: -+ { -+ HReg argL = iselVecExpr(env, triop->arg2); -+ HReg argR = iselVecExpr(env, triop->arg3); -+ HReg dst = newVRegV(env); -+ REQUIRE_SSE2; -+ addInstr(env, mk_vMOVsd_RR(argL, dst)); -+ /* XXXROUNDINGFIXME */ -+ /* set roundingmode here */ -+ addInstr(env, X86Instr_Sse64Fx2(op, argR, dst)); -+ return dst; -+ } -+ -+ default: -+ break; -+ } /* switch (triop->op) */ -+ } /* if (e->tag == Iex_Triop) */ -+ -+ - if (e->tag == Iex_ITE) { // VFD - HReg r1 = iselVecExpr(env, e->Iex.ITE.iftrue); - HReg r0 = iselVecExpr(env, e->Iex.ITE.iffalse); -@@ -4244,8 +4285,9 @@ - case Ijk_Sys_int128: - case Ijk_Sys_int129: - case Ijk_Sys_int130: -+ case Ijk_Sys_syscall: - case Ijk_Sys_sysenter: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Yield: - { - HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); -@@ -4342,8 +4384,9 @@ - case Ijk_Sys_int128: - case Ijk_Sys_int129: - case Ijk_Sys_int130: -+ case Ijk_Sys_syscall: - case Ijk_Sys_sysenter: -- case Ijk_TInval: -+ case Ijk_InvalICache: - case Ijk_Yield: - { - HReg r = iselIntExpr_R(env, next); -Index: priv/ir_defs.c -=================================================================== ---- priv/ir_defs.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/ir_defs.c (.../trunk) (revision 2863) -@@ -640,6 +640,7 @@ - case Iop_Recps32Fx2: vex_printf("VRecps32Fx2"); return; - case Iop_Recps32Fx4: vex_printf("VRecps32Fx4"); return; - case Iop_Abs32Fx4: vex_printf("Abs32Fx4"); return; -+ case Iop_Abs64Fx2: vex_printf("Abs64Fx2"); return; - case Iop_Rsqrts32Fx4: vex_printf("VRsqrts32Fx4"); return; - case Iop_Rsqrts32Fx2: vex_printf("VRsqrts32Fx2"); return; - -@@ -685,6 +686,7 @@ - case Iop_CmpLE64F0x2: vex_printf("CmpLE64F0x2"); return; - case Iop_CmpUN64F0x2: vex_printf("CmpUN64F0x2"); return; - -+ case Iop_Neg64Fx2: vex_printf("Neg64Fx2"); return; - case Iop_Neg32Fx4: vex_printf("Neg32Fx4"); return; - case Iop_Neg32Fx2: vex_printf("Neg32Fx2"); return; - -@@ -695,6 +697,11 @@ - case Iop_64UtoV128: vex_printf("64UtoV128"); return; - case Iop_SetV128lo64: vex_printf("SetV128lo64"); return; - -+ case Iop_ZeroHI64ofV128: vex_printf("ZeroHI64ofV128"); return; -+ case Iop_ZeroHI96ofV128: vex_printf("ZeroHI96ofV128"); return; -+ case Iop_ZeroHI112ofV128: vex_printf("ZeroHI112ofV128"); return; -+ case Iop_ZeroHI120ofV128: vex_printf("ZeroHI120ofV128"); return; -+ - case Iop_32UtoV128: vex_printf("32UtoV128"); return; - case Iop_V128to32: vex_printf("V128to32"); return; - case Iop_SetV128lo32: vex_printf("SetV128lo32"); return; -@@ -1405,8 +1412,10 @@ - case Ijk_EmFail: vex_printf("EmFail"); break; - case Ijk_NoDecode: vex_printf("NoDecode"); break; - case Ijk_MapFail: vex_printf("MapFail"); break; -- case Ijk_TInval: vex_printf("Invalidate"); break; -+ case Ijk_InvalICache: vex_printf("InvalICache"); break; -+ case Ijk_FlushDCache: vex_printf("FlushDCache"); break; - case Ijk_NoRedir: vex_printf("NoRedir"); break; -+ case Ijk_SigILL: vex_printf("SigILL"); break; - case Ijk_SigTRAP: vex_printf("SigTRAP"); break; - case Ijk_SigSEGV: vex_printf("SigSEGV"); break; - case Ijk_SigBUS: vex_printf("SigBUS"); break; -@@ -2734,7 +2743,7 @@ - case Iop_RoundF32x4_RP: - case Iop_RoundF32x4_RN: - case Iop_RoundF32x4_RZ: -- case Iop_Abs32Fx4: -+ case Iop_Abs64Fx2: case Iop_Abs32Fx4: - case Iop_Rsqrte32Fx4: - case Iop_Rsqrte32x4: - UNARY(Ity_V128, Ity_V128); -@@ -2789,19 +2798,19 @@ - case Iop_CmpEQ64F0x2: case Iop_CmpLT64F0x2: - case Iop_CmpLE32F0x4: case Iop_CmpUN32F0x4: - case Iop_CmpLE64F0x2: case Iop_CmpUN64F0x2: -- case Iop_Add32Fx4: case Iop_Add32F0x4: -- case Iop_Add64Fx2: case Iop_Add64F0x2: -- case Iop_Div32Fx4: case Iop_Div32F0x4: -- case Iop_Div64Fx2: case Iop_Div64F0x2: -+ case Iop_Add32F0x4: -+ case Iop_Add64F0x2: -+ case Iop_Div32F0x4: -+ case Iop_Div64F0x2: - case Iop_Max32Fx4: case Iop_Max32F0x4: - case Iop_PwMax32Fx4: case Iop_PwMin32Fx4: - case Iop_Max64Fx2: case Iop_Max64F0x2: - case Iop_Min32Fx4: case Iop_Min32F0x4: - case Iop_Min64Fx2: case Iop_Min64F0x2: -- case Iop_Mul32Fx4: case Iop_Mul32F0x4: -- case Iop_Mul64Fx2: case Iop_Mul64F0x2: -- case Iop_Sub32Fx4: case Iop_Sub32F0x4: -- case Iop_Sub64Fx2: case Iop_Sub64F0x2: -+ case Iop_Mul32F0x4: -+ case Iop_Mul64F0x2: -+ case Iop_Sub32F0x4: -+ case Iop_Sub64F0x2: - case Iop_AndV128: case Iop_OrV128: case Iop_XorV128: - case Iop_Add8x16: case Iop_Add16x8: - case Iop_Add32x4: case Iop_Add64x2: -@@ -2900,10 +2909,12 @@ - case Iop_Reverse64_8x16: case Iop_Reverse64_16x8: case Iop_Reverse64_32x4: - case Iop_Reverse32_8x16: case Iop_Reverse32_16x8: - case Iop_Reverse16_8x16: -- case Iop_Neg32Fx4: -+ case Iop_Neg64Fx2: case Iop_Neg32Fx4: - case Iop_Abs8x16: case Iop_Abs16x8: case Iop_Abs32x4: - case Iop_CipherSV128: - case Iop_PwBitMtxXpose64x2: -+ case Iop_ZeroHI64ofV128: case Iop_ZeroHI96ofV128: -+ case Iop_ZeroHI112ofV128: case Iop_ZeroHI120ofV128: - UNARY(Ity_V128, Ity_V128); - - case Iop_ShlV128: case Iop_ShrV128: -@@ -2966,7 +2977,7 @@ - case Iop_QDMulLong16Sx4: case Iop_QDMulLong32Sx2: - BINARY(Ity_I64, Ity_I64, Ity_V128); - -- /* s390 specific */ -+ /* s390 specific */ - case Iop_MAddF32: - case Iop_MSubF32: - QUATERNARY(ity_RMode,Ity_F32,Ity_F32,Ity_F32, Ity_F32); -@@ -2984,6 +2995,18 @@ - case Iop_DivF128: - TERNARY(ity_RMode,Ity_F128,Ity_F128, Ity_F128); - -+ case Iop_Add64Fx2: case Iop_Sub64Fx2: -+ case Iop_Mul64Fx2: case Iop_Div64Fx2: -+ case Iop_Add32Fx4: case Iop_Sub32Fx4: -+ case Iop_Mul32Fx4: case Iop_Div32Fx4: -+ TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128); -+ -+ case Iop_Add64Fx4: case Iop_Sub64Fx4: -+ case Iop_Mul64Fx4: case Iop_Div64Fx4: -+ case Iop_Add32Fx8: case Iop_Sub32Fx8: -+ case Iop_Mul32Fx8: case Iop_Div32Fx8: -+ TERNARY(ity_RMode,Ity_V256,Ity_V256, Ity_V256); -+ - case Iop_NegF128: - case Iop_AbsF128: - UNARY(Ity_F128, Ity_F128); -@@ -3203,10 +3226,6 @@ - case Iop_64x4toV256: - QUATERNARY(Ity_I64, Ity_I64, Ity_I64, Ity_I64, Ity_V256); - -- case Iop_Add64Fx4: case Iop_Sub64Fx4: -- case Iop_Mul64Fx4: case Iop_Div64Fx4: -- case Iop_Add32Fx8: case Iop_Sub32Fx8: -- case Iop_Mul32Fx8: case Iop_Div32Fx8: - case Iop_AndV256: case Iop_OrV256: - case Iop_XorV256: - case Iop_Max32Fx8: case Iop_Min32Fx8: -@@ -4465,6 +4484,17 @@ - } - } - -+IRType integerIRTypeOfSize ( Int szB ) -+{ -+ switch (szB) { -+ case 8: return Ity_I64; -+ case 4: return Ity_I32; -+ case 2: return Ity_I16; -+ case 1: return Ity_I8; -+ default: vpanic("integerIRTypeOfSize"); -+ } -+} -+ - IRExpr* mkIRExpr_HWord ( HWord hw ) - { - vassert(sizeof(void*) == sizeof(HWord)); -Index: priv/ir_opt.c -=================================================================== ---- priv/ir_opt.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/ir_opt.c (.../trunk) (revision 2863) -@@ -1178,6 +1178,30 @@ - && e->Iex.Const.con->Ico.U32 == 0); - } - -+/* Is this literally IRExpr_Const(IRConst_U64(0)) ? */ -+static Bool isZeroU64 ( IRExpr* e ) -+{ -+ return toBool( e->tag == Iex_Const -+ && e->Iex.Const.con->tag == Ico_U64 -+ && e->Iex.Const.con->Ico.U64 == 0); -+} -+ -+/* Is this literally IRExpr_Const(IRConst_V128(0)) ? */ -+static Bool isZeroV128 ( IRExpr* e ) -+{ -+ return toBool( e->tag == Iex_Const -+ && e->Iex.Const.con->tag == Ico_V128 -+ && e->Iex.Const.con->Ico.V128 == 0x0000); -+} -+ -+/* Is this literally IRExpr_Const(IRConst_V256(0)) ? */ -+static Bool isZeroV256 ( IRExpr* e ) -+{ -+ return toBool( e->tag == Iex_Const -+ && e->Iex.Const.con->tag == Ico_V256 -+ && e->Iex.Const.con->Ico.V256 == 0x00000000); -+} -+ - /* Is this an integer constant with value 0 ? */ - static Bool isZeroU ( IRExpr* e ) - { -@@ -1224,9 +1248,11 @@ - case Iop_Xor16: return IRExpr_Const(IRConst_U16(0)); - case Iop_Sub32: - case Iop_Xor32: return IRExpr_Const(IRConst_U32(0)); -+ case Iop_And64: - case Iop_Sub64: - case Iop_Xor64: return IRExpr_Const(IRConst_U64(0)); -- case Iop_XorV128: return IRExpr_Const(IRConst_V128(0)); -+ case Iop_XorV128: -+ case Iop_AndV128: return IRExpr_Const(IRConst_V128(0)); - default: vpanic("mkZeroOfPrimopResultType: bad primop"); - } - } -@@ -1990,6 +2016,17 @@ - } - break; - } -+ /* Same reasoning for the 256-bit version. */ -+ case Iop_V128HLtoV256: { -+ IRExpr* argHi = e->Iex.Binop.arg1; -+ IRExpr* argLo = e->Iex.Binop.arg2; -+ if (isZeroV128(argHi) && isZeroV128(argLo)) { -+ e2 = IRExpr_Const(IRConst_V256(0)); -+ } else { -+ goto unhandled; -+ } -+ break; -+ } - - /* -- V128 stuff -- */ - case Iop_InterleaveLO8x16: { -@@ -2114,6 +2151,13 @@ - break; - } - break; -+ case Iop_Sub8x16: -+ /* Sub8x16(x,0) ==> x */ -+ if (isZeroV128(e->Iex.Binop.arg2)) { -+ e2 = e->Iex.Binop.arg1; -+ break; -+ } -+ break; - - case Iop_And64: - case Iop_And32: -@@ -2149,6 +2193,19 @@ - e2 = e->Iex.Binop.arg1; - break; - } -+ /* Deal with either arg zero. Could handle other And -+ cases here too. */ -+ if (e->Iex.Binop.op == Iop_And64 -+ && (isZeroU64(e->Iex.Binop.arg1) -+ || isZeroU64(e->Iex.Binop.arg2))) { -+ e2 = mkZeroOfPrimopResultType(e->Iex.Binop.op); -+ break; -+ } else if (e->Iex.Binop.op == Iop_AndV128 -+ && (isZeroV128(e->Iex.Binop.arg1) -+ || isZeroV128(e->Iex.Binop.arg2))) { -+ e2 = mkZeroOfPrimopResultType(e->Iex.Binop.op); -+ break; -+ } - break; - - case Iop_OrV128: -@@ -2158,6 +2215,29 @@ - e2 = e->Iex.Binop.arg1; - break; - } -+ /* OrV128(t,0) ==> t */ -+ if (e->Iex.Binop.op == Iop_OrV128) { -+ if (isZeroV128(e->Iex.Binop.arg2)) { -+ e2 = e->Iex.Binop.arg1; -+ break; -+ } -+ if (isZeroV128(e->Iex.Binop.arg1)) { -+ e2 = e->Iex.Binop.arg2; -+ break; -+ } -+ } -+ /* OrV256(t,0) ==> t */ -+ if (e->Iex.Binop.op == Iop_OrV256) { -+ if (isZeroV256(e->Iex.Binop.arg2)) { -+ e2 = e->Iex.Binop.arg1; -+ break; -+ } -+ //Disabled because there's no known test case right now. -+ //if (isZeroV256(e->Iex.Binop.arg1)) { -+ // e2 = e->Iex.Binop.arg2; -+ // break; -+ //} -+ } - break; - - case Iop_Xor8: -Index: priv/main_main.c -=================================================================== ---- priv/main_main.c (.../tags/VEX_3_9_0) (revision 2863) -+++ priv/main_main.c (.../trunk) (revision 2863) -@@ -38,6 +38,7 @@ - #include "libvex_guest_x86.h" - #include "libvex_guest_amd64.h" - #include "libvex_guest_arm.h" -+#include "libvex_guest_arm64.h" - #include "libvex_guest_ppc32.h" - #include "libvex_guest_ppc64.h" - #include "libvex_guest_s390x.h" -@@ -53,6 +54,7 @@ - #include "host_amd64_defs.h" - #include "host_ppc_defs.h" - #include "host_arm_defs.h" -+#include "host_arm64_defs.h" - #include "host_s390_defs.h" - #include "host_mips_defs.h" - -@@ -60,6 +62,7 @@ - #include "guest_x86_defs.h" - #include "guest_amd64_defs.h" - #include "guest_arm_defs.h" -+#include "guest_arm64_defs.h" - #include "guest_ppc_defs.h" - #include "guest_s390_defs.h" - #include "guest_mips_defs.h" -@@ -89,6 +92,7 @@ - - void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) - { -+ vex_bzero(vcon, sizeof(*vcon)); - vcon->iropt_verbosity = 0; - vcon->iropt_level = 2; - vcon->iropt_register_updates = VexRegUpdUnwindregsAtMemAccess; -@@ -233,7 +237,7 @@ - HInstrArray* vcode; - HInstrArray* rcode; - Int i, j, k, out_used, guest_sizeB; -- Int offB_TISTART, offB_TILEN, offB_GUEST_IP, szB_GUEST_IP; -+ Int offB_CMSTART, offB_CMLEN, offB_GUEST_IP, szB_GUEST_IP; - Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR; - UChar insn_bytes[128]; - IRType guest_word_type; -@@ -259,8 +263,8 @@ - disInstrFn = NULL; - guest_word_type = Ity_INVALID; - host_word_type = Ity_INVALID; -- offB_TISTART = 0; -- offB_TILEN = 0; -+ offB_CMSTART = 0; -+ offB_CMLEN = 0; - offB_GUEST_IP = 0; - szB_GUEST_IP = 0; - offB_HOST_EvC_COUNTER = 0; -@@ -417,6 +421,30 @@ - vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); - break; - -+ case VexArchARM64: -+ mode64 = True; -+ getAllocableRegs_ARM64 ( &n_available_real_regs, -+ &available_real_regs ); -+ isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_ARM64Instr; -+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) -+ getRegUsage_ARM64Instr; -+ mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) -+ mapRegs_ARM64Instr; -+ genSpill = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) -+ genSpill_ARM64; -+ genReload = (void(*)(HInstr**,HInstr**,HReg,Int,Bool)) -+ genReload_ARM64; -+ ppInstr = (void(*)(HInstr*, Bool)) ppARM64Instr; -+ ppReg = (void(*)(HReg)) ppHRegARM64; -+ iselSB = iselSB_ARM64; -+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool, -+ void*,void*,void*,void*)) -+ emit_ARM64Instr; -+ host_is_bigendian = False; -+ host_word_type = Ity_I64; -+ vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_host.hwcaps)); -+ break; -+ - case VexArchMIPS32: - mode64 = False; - getAllocableRegs_MIPS ( &n_available_real_regs, -@@ -479,8 +507,8 @@ - guest_sizeB = sizeof(VexGuestX86State); - guest_word_type = Ity_I32; - guest_layout = &x86guest_layout; -- offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); -- offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestX86State,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestX86State,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP); - szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP ); - offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); -@@ -487,8 +515,8 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestX86State) % 16); -- vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART) == 4); -- vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); -+ vassert(sizeof( ((VexGuestX86State*)0)->guest_CMSTART) == 4); -+ vassert(sizeof( ((VexGuestX86State*)0)->guest_CMLEN ) == 4); - vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); - break; - -@@ -499,8 +527,8 @@ - guest_sizeB = sizeof(VexGuestAMD64State); - guest_word_type = Ity_I64; - guest_layout = &amd64guest_layout; -- offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); -- offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestAMD64State,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestAMD64State,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP); - szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP ); - offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); -@@ -507,8 +535,8 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestAMD64State) % 16); -- vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); -- vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); -+ vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMSTART ) == 8); -+ vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMLEN ) == 8); - vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); - break; - -@@ -519,8 +547,8 @@ - guest_sizeB = sizeof(VexGuestPPC32State); - guest_word_type = Ity_I32; - guest_layout = &ppc32Guest_layout; -- offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); -- offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestPPC32State,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestPPC32State,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA); - szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA ); - offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); -@@ -527,8 +555,8 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestPPC32State) % 16); -- vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); -- vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); -+ vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMSTART ) == 4); -+ vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMLEN ) == 4); - vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); - break; - -@@ -539,8 +567,8 @@ - guest_sizeB = sizeof(VexGuestPPC64State); - guest_word_type = Ity_I64; - guest_layout = &ppc64Guest_layout; -- offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART); -- offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestPPC64State,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestPPC64State,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA); - szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA ); - offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); -@@ -547,8 +575,8 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestPPC64State) % 16); -- vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); -- vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); -+ vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMSTART ) == 8); -+ vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMLEN ) == 8); - vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); - vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); - break; -@@ -560,8 +588,8 @@ - guest_sizeB = sizeof(VexGuestS390XState); - guest_word_type = Ity_I64; - guest_layout = &s390xGuest_layout; -- offB_TISTART = offsetof(VexGuestS390XState,guest_TISTART); -- offB_TILEN = offsetof(VexGuestS390XState,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestS390XState,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestS390XState,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA); - szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA); - offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); -@@ -568,8 +596,8 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestS390XState) % 16); -- vassert(sizeof( ((VexGuestS390XState*)0)->guest_TISTART ) == 8); -- vassert(sizeof( ((VexGuestS390XState*)0)->guest_TILEN ) == 8); -+ vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMSTART ) == 8); -+ vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMLEN ) == 8); - vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8); - break; - -@@ -580,8 +608,8 @@ - guest_sizeB = sizeof(VexGuestARMState); - guest_word_type = Ity_I32; - guest_layout = &armGuest_layout; -- offB_TISTART = offsetof(VexGuestARMState,guest_TISTART); -- offB_TILEN = offsetof(VexGuestARMState,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestARMState,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestARMState,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T); - szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T ); - offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); -@@ -588,11 +616,31 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestARMState) % 16); -- vassert(sizeof( ((VexGuestARMState*)0)->guest_TISTART) == 4); -- vassert(sizeof( ((VexGuestARMState*)0)->guest_TILEN ) == 4); -+ vassert(sizeof( ((VexGuestARMState*)0)->guest_CMSTART) == 4); -+ vassert(sizeof( ((VexGuestARMState*)0)->guest_CMLEN ) == 4); - vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); - break; - -+ case VexArchARM64: -+ preciseMemExnsFn = guest_arm64_state_requires_precise_mem_exns; -+ disInstrFn = disInstr_ARM64; -+ specHelper = guest_arm64_spechelper; -+ guest_sizeB = sizeof(VexGuestARM64State); -+ guest_word_type = Ity_I64; -+ guest_layout = &arm64Guest_layout; -+ offB_CMSTART = offsetof(VexGuestARM64State,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestARM64State,guest_CMLEN); -+ offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC); -+ szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC ); -+ offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER); -+ offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR); -+ vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_guest.hwcaps)); -+ vassert(0 == sizeof(VexGuestARM64State) % 16); -+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMSTART) == 8); -+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMLEN ) == 8); -+ vassert(sizeof( ((VexGuestARM64State*)0)->guest_NRADDR ) == 8); -+ break; -+ - case VexArchMIPS32: - preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns; - disInstrFn = disInstr_MIPS; -@@ -600,8 +648,8 @@ - guest_sizeB = sizeof(VexGuestMIPS32State); - guest_word_type = Ity_I32; - guest_layout = &mips32Guest_layout; -- offB_TISTART = offsetof(VexGuestMIPS32State,guest_TISTART); -- offB_TILEN = offsetof(VexGuestMIPS32State,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestMIPS32State,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestMIPS32State,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC); - szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC ); - offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); -@@ -608,8 +656,8 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestMIPS32State) % 16); -- vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TISTART) == 4); -- vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_TILEN ) == 4); -+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMSTART) == 4); -+ vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMLEN ) == 4); - vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); - break; - -@@ -620,8 +668,8 @@ - guest_sizeB = sizeof(VexGuestMIPS64State); - guest_word_type = Ity_I64; - guest_layout = &mips64Guest_layout; -- offB_TISTART = offsetof(VexGuestMIPS64State,guest_TISTART); -- offB_TILEN = offsetof(VexGuestMIPS64State,guest_TILEN); -+ offB_CMSTART = offsetof(VexGuestMIPS64State,guest_CMSTART); -+ offB_CMLEN = offsetof(VexGuestMIPS64State,guest_CMLEN); - offB_GUEST_IP = offsetof(VexGuestMIPS64State,guest_PC); - szB_GUEST_IP = sizeof( ((VexGuestMIPS64State*)0)->guest_PC ); - offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER); -@@ -628,8 +676,8 @@ - offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); - vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_guest.hwcaps)); - vassert(0 == sizeof(VexGuestMIPS64State) % 16); -- vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_TISTART) == 8); -- vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_TILEN ) == 8); -+ vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMSTART) == 8); -+ vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMLEN ) == 8); - vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8); - break; - -@@ -675,8 +723,8 @@ - guest_word_type, - vta->needs_self_check, - vta->preamble_function, -- offB_TISTART, -- offB_TILEN, -+ offB_CMSTART, -+ offB_CMLEN, - offB_GUEST_IP, - szB_GUEST_IP ); - -@@ -958,6 +1006,8 @@ - chainXDirect = chainXDirect_AMD64; break; - case VexArchARM: - chainXDirect = chainXDirect_ARM; break; -+ case VexArchARM64: -+ chainXDirect = chainXDirect_ARM64; break; - case VexArchS390X: - chainXDirect = chainXDirect_S390; break; - case VexArchPPC32: -@@ -999,6 +1049,8 @@ - unchainXDirect = unchainXDirect_AMD64; break; - case VexArchARM: - unchainXDirect = unchainXDirect_ARM; break; -+ case VexArchARM64: -+ unchainXDirect = unchainXDirect_ARM64; break; - case VexArchS390X: - unchainXDirect = unchainXDirect_S390; break; - case VexArchPPC32: -@@ -1038,6 +1090,8 @@ - cached = evCheckSzB_AMD64(); break; - case VexArchARM: - cached = evCheckSzB_ARM(); break; -+ case VexArchARM64: -+ cached = evCheckSzB_ARM64(); break; - case VexArchS390X: - cached = evCheckSzB_S390(); break; - case VexArchPPC32: -@@ -1152,6 +1206,7 @@ - case VexArchX86: return "X86"; - case VexArchAMD64: return "AMD64"; - case VexArchARM: return "ARM"; -+ case VexArchARM64: return "ARM64"; - case VexArchPPC32: return "PPC32"; - case VexArchPPC64: return "PPC64"; - case VexArchS390X: return "S390X"; -@@ -1171,14 +1226,16 @@ - /* Write default settings info *vai. */ - void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) - { -+ vex_bzero(vai, sizeof(*vai)); - vai->hwcaps = 0; - vai->ppc_icache_line_szB = 0; - vai->ppc_dcbz_szB = 0; - vai->ppc_dcbzl_szB = 0; -- -+ vai->arm64_dMinLine_lg2_szB = 0; -+ vai->arm64_iMinLine_lg2_szB = 0; - vai->hwcache_info.num_levels = 0; - vai->hwcache_info.num_caches = 0; -- vai->hwcache_info.caches = NULL; -+ vai->hwcache_info.caches = NULL; - vai->hwcache_info.icaches_maintain_coherence = True; // whatever - } - -@@ -1185,6 +1242,7 @@ - /* Write default settings info *vbi. */ - void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) - { -+ vex_bzero(vbi, sizeof(*vbi)); - vbi->guest_stack_redzone_size = 0; - vbi->guest_amd64_assume_fs_is_zero = False; - vbi->guest_amd64_assume_gs_is_0x60 = False; -@@ -1381,6 +1439,15 @@ - return NULL; - } - -+static const HChar* show_hwcaps_arm64 ( UInt hwcaps ) -+{ -+ /* Since there are no variants, just insist that hwcaps is zero, -+ and declare it invalid otherwise. */ -+ if (hwcaps == 0) -+ return "baseline"; -+ return NULL; -+} -+ - static const HChar* show_hwcaps_s390x ( UInt hwcaps ) - { - static const HChar prefix[] = "s390x"; -@@ -1472,6 +1539,7 @@ - case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); - case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); - case VexArchARM: return show_hwcaps_arm(hwcaps); -+ case VexArchARM64: return show_hwcaps_arm64(hwcaps); - case VexArchS390X: return show_hwcaps_s390x(hwcaps); - case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); - case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); -Index: pub/libvex.h -=================================================================== ---- pub/libvex.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex.h (.../trunk) (revision 2863) -@@ -55,6 +55,7 @@ - VexArchX86, - VexArchAMD64, - VexArchARM, -+ VexArchARM64, - VexArchPPC32, - VexArchPPC64, - VexArchS390X, -@@ -172,6 +173,9 @@ - /* Get an ARM architecure level from HWCAPS */ - #define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f) - -+/* ARM64: baseline capability is AArch64 v8. */ -+/* (no definitions since no variants so far) */ -+ - /* MIPS baseline capability */ - /* Assigned Company values for bits 23:16 of the PRId Register - (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from -@@ -196,10 +200,15 @@ - #define VEX_PRID_IMP_34K 0x9500 - #define VEX_PRID_IMP_74K 0x9700 - -+/* CPU has FPU and 32 dbl. prec. FP registers */ -+#define VEX_PRID_CPU_32FPR 0x00000040 -+ - /* Get MIPS Company ID from HWCAPS */ - #define VEX_MIPS_COMP_ID(x) ((x) & 0x00FF0000) - /* Get MIPS Processor ID from HWCAPS */ --#define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FFFF) -+#define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00) -+/* Get MIPS Revision from HWCAPS */ -+#define VEX_MIPS_REV(x) ((x) & 0x000000FF) - /* Check if the processor supports DSP ASE Rev 2. */ - #define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \ - (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_74K)) -@@ -213,6 +222,7 @@ - extern const HChar* LibVEX_ppVexArch ( VexArch ); - extern const HChar* LibVEX_ppVexHwCaps ( VexArch, UInt ); - -+ - /* The various kinds of caches */ - typedef enum { - DATA_CACHE, -@@ -266,9 +276,14 @@ - /* PPC32/PPC64 only: size of instruction cache line */ - Int ppc_icache_line_szB; - /* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions -- * (bug#135264) */ -+ (bug#135264) */ - UInt ppc_dcbz_szB; - UInt ppc_dcbzl_szB; /* 0 means unsupported (SIGILL) */ -+ /* ARM64: I- and D- minimum line sizes in log2(bytes), as -+ obtained from ctr_el0.DminLine and .IminLine. For example, a -+ line size of 64 bytes would be encoded here as 6. */ -+ UInt arm64_dMinLine_lg2_szB; -+ UInt arm64_iMinLine_lg2_szB; - } - VexArchInfo; - -@@ -516,7 +531,7 @@ - typedef - struct { - /* Total size of the guest state, in bytes. Must be -- 8-aligned. */ -+ 16-aligned. */ - Int total_sizeB; - /* Whereabouts is the stack pointer? */ - Int offset_SP; -@@ -907,13 +922,25 @@ - ~~~~~ - Same as ppc32. - -+ arm32 -+ ~~~~~ -+ r8 is GSP. -+ -+ arm64 -+ ~~~~~ -+ r21 is GSP. -+ - ALL GUEST ARCHITECTURES - ~~~~~~~~~~~~~~~~~~~~~~~ -- The guest state must contain two pseudo-registers, guest_TISTART -- and guest_TILEN. These are used to pass the address of areas of -- guest code, translations of which are to be invalidated, back to -- the despatcher. Both pseudo-regs must have size equal to the guest -- word size. -+ The guest state must contain two pseudo-registers, guest_CMSTART -+ and guest_CMLEN. These are used to specify guest address ranges, -+ either of code to be invalidated, when used in conjunction with -+ Ijk_InvalICache, or of d-cache ranges to be flushed, when used in -+ conjunction with Ijk_FlushDCache. In such cases, the two _CM -+ pseudo-regs should be filled in by the IR, and then an exit with -+ one of the two abovementioned Ijk_ kinds should happen, so that the -+ dispatcher can action them. Both pseudo-regs must have size equal -+ to the guest word size. - - The architecture must a third pseudo-register, guest_NRADDR, also - guest-word-sized. This is used to record the unredirected guest -Index: pub/libvex_basictypes.h -=================================================================== ---- pub/libvex_basictypes.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_basictypes.h (.../trunk) (revision 2863) -@@ -192,28 +192,24 @@ - # define VEX_HOST_WORDSIZE 4 - # define VEX_REGPARM(_n) /* */ - --#elif defined(__arm__) -+#elif defined(__arm__) && !defined(__aarch64__) - # define VEX_HOST_WORDSIZE 4 - # define VEX_REGPARM(_n) /* */ - --#elif defined(_AIX) && !defined(__64BIT__) --# define VEX_HOST_WORDSIZE 4 -+#elif defined(__aarch64__) && !defined(__arm__) -+# define VEX_HOST_WORDSIZE 8 - # define VEX_REGPARM(_n) /* */ - --#elif defined(_AIX) && defined(__64BIT__) -+#elif defined(__s390x__) - # define VEX_HOST_WORDSIZE 8 - # define VEX_REGPARM(_n) /* */ - --#elif defined(__s390x__) -+#elif defined(__mips__) && (__mips == 64) - # define VEX_HOST_WORDSIZE 8 - # define VEX_REGPARM(_n) /* */ - --#elif defined(__mips__) --#if (__mips==64) --# define VEX_HOST_WORDSIZE 8 --#else -+#elif defined(__mips__) && (__mips != 64) - # define VEX_HOST_WORDSIZE 4 --#endif - # define VEX_REGPARM(_n) /* */ - - #else -Index: pub/libvex_guest_amd64.h -=================================================================== ---- pub/libvex_guest_amd64.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_amd64.h (.../trunk) (revision 2863) -@@ -138,8 +138,8 @@ - compilation breakage. On amd64, these two fields are set to - zero by LibVEX_GuestAMD64_initialise and then should be - ignored forever thereafter. */ -- ULong guest_TISTART; -- ULong guest_TILEN; -+ ULong guest_CMSTART; -+ ULong guest_CMLEN; - - /* Used to record the unredirected guest address at the start of - a translation whose start has been redirected. By reading -Index: pub/libvex_guest_arm.h -=================================================================== ---- pub/libvex_guest_arm.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_arm.h (.../trunk) (revision 2863) -@@ -94,9 +94,9 @@ - /* Emulation notes */ - UInt guest_EMNOTE; - -- /* For clflush: record start and length of area to invalidate */ -- UInt guest_TISTART; -- UInt guest_TILEN; -+ /* For clinval/clflush: record start and length of area */ -+ UInt guest_CMSTART; -+ UInt guest_CMLEN; - - /* Used to record the unredirected guest address at the start of - a translation whose start has been redirected. By reading -@@ -193,12 +193,8 @@ - */ - UInt guest_ITSTATE; - -- /* Padding to make it have an 32-aligned size */ -+ /* Padding to make it have an 16-aligned size */ - UInt padding1; -- UInt padding2; -- UInt padding3; -- UInt padding4; -- UInt padding5; - } - VexGuestARMState; - -Index: pub/libvex_guest_arm64.h -=================================================================== ---- pub/libvex_guest_arm64.h (.../tags/VEX_3_9_0) (revision 0) -+++ pub/libvex_guest_arm64.h (.../trunk) (revision 2863) -@@ -0,0 +1,190 @@ -+ -+/*---------------------------------------------------------------*/ -+/*--- begin libvex_guest_arm64.h ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ 02110-1301, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __LIBVEX_PUB_GUEST_ARM64_H -+#define __LIBVEX_PUB_GUEST_ARM64_H -+ -+#include "libvex_basictypes.h" -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- Vex's representation of the ARM64 CPU state. ---*/ -+/*---------------------------------------------------------------*/ -+ -+typedef -+ struct { -+ /* Event check fail addr and counter. */ -+ /* 0 */ ULong host_EvC_FAILADDR; -+ /* 8 */ UInt host_EvC_COUNTER; -+ /* 12 */ UInt pad0; -+ /* 16 */ -+ ULong guest_X0; -+ ULong guest_X1; -+ ULong guest_X2; -+ ULong guest_X3; -+ ULong guest_X4; -+ ULong guest_X5; -+ ULong guest_X6; -+ ULong guest_X7; -+ ULong guest_X8; -+ ULong guest_X9; -+ ULong guest_X10; -+ ULong guest_X11; -+ ULong guest_X12; -+ ULong guest_X13; -+ ULong guest_X14; -+ ULong guest_X15; -+ ULong guest_X16; -+ ULong guest_X17; -+ ULong guest_X18; -+ ULong guest_X19; -+ ULong guest_X20; -+ ULong guest_X21; -+ ULong guest_X22; -+ ULong guest_X23; -+ ULong guest_X24; -+ ULong guest_X25; -+ ULong guest_X26; -+ ULong guest_X27; -+ ULong guest_X28; -+ ULong guest_X29; -+ ULong guest_X30; /* link register */ -+ ULong guest_XSP; -+ ULong guest_PC; -+ -+ /* 4-word thunk used to calculate N(sign) Z(zero) C(carry, -+ unsigned overflow) and V(signed overflow) flags. */ -+ ULong guest_CC_OP; -+ ULong guest_CC_DEP1; -+ ULong guest_CC_DEP2; -+ ULong guest_CC_NDEP; -+ -+ /* User-space thread register? */ -+ ULong guest_TPIDR_EL0; -+ -+ /* FP/SIMD state */ -+ U128 guest_Q0; -+ U128 guest_Q1; -+ U128 guest_Q2; -+ U128 guest_Q3; -+ U128 guest_Q4; -+ U128 guest_Q5; -+ U128 guest_Q6; -+ U128 guest_Q7; -+ U128 guest_Q8; -+ U128 guest_Q9; -+ U128 guest_Q10; -+ U128 guest_Q11; -+ U128 guest_Q12; -+ U128 guest_Q13; -+ U128 guest_Q14; -+ U128 guest_Q15; -+ U128 guest_Q16; -+ U128 guest_Q17; -+ U128 guest_Q18; -+ U128 guest_Q19; -+ U128 guest_Q20; -+ U128 guest_Q21; -+ U128 guest_Q22; -+ U128 guest_Q23; -+ U128 guest_Q24; -+ U128 guest_Q25; -+ U128 guest_Q26; -+ U128 guest_Q27; -+ U128 guest_Q28; -+ U128 guest_Q29; -+ U128 guest_Q30; -+ U128 guest_Q31; -+ -+ /* Various pseudo-regs mandated by Vex or Valgrind. */ -+ /* Emulation notes */ -+ UInt guest_EMNOTE; -+ -+ /* For clflush/clinval: record start and length of area */ -+ ULong guest_CMSTART; -+ ULong guest_CMLEN; -+ -+ /* Used to record the unredirected guest address at the start of -+ a translation whose start has been redirected. By reading -+ this pseudo-register shortly afterwards, the translation can -+ find out what the corresponding no-redirection address was. -+ Note, this is only set for wrap-style redirects, not for -+ replace-style ones. */ -+ ULong guest_NRADDR; -+ -+ /* Needed for Darwin (but mandated for all guest architectures): -+ program counter at the last syscall insn (int 0x80/81/82, -+ sysenter, syscall, svc). Used when backing up to restart a -+ syscall that has been interrupted by a signal. */ -+ ULong guest_IP_AT_SYSCALL; -+ -+ /* The complete FPCR. Default value seems to be zero. We -+ ignore all bits except 23 and 22, which are the rounding -+ mode. The guest is unconstrained in what values it can write -+ to and read from this register, but the emulation only takes -+ note of bits 23 and 22. */ -+ UInt guest_FPCR; -+ -+ /* The complete FPSR. As with FPCR, the guest may write and -+ read any values here, and the emulation ignores it, with the -+ exception of bit 27 (QC, the sticky saturation bit) which -+ does get set when required. */ -+ UInt guest_FPSR; -+ -+ /* Padding to make it have an 16-aligned size */ -+ UInt pad_end_0; -+ ULong pad_end_1; -+ } -+ VexGuestARM64State; -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- Utility functions for ARM64 guest stuff. ---*/ -+/*---------------------------------------------------------------*/ -+ -+/* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */ -+ -+/* Initialise all guest ARM64 state. */ -+ -+extern -+void LibVEX_GuestARM64_initialise ( /*OUT*/VexGuestARM64State* vex_state ); -+ -+/* Calculate the ARM64 flag state from the saved data, in the format -+ 32x0:n:z:c:v:28x0. */ -+extern -+ULong LibVEX_GuestARM64_get_nzcv ( /*IN*/ -+ const VexGuestARM64State* vex_state ); -+ -+#endif /* ndef __LIBVEX_PUB_GUEST_ARM64_H */ -+ -+ -+/*---------------------------------------------------------------*/ -+/*--- libvex_guest_arm64.h ---*/ -+/*---------------------------------------------------------------*/ -Index: pub/libvex_guest_mips32.h -=================================================================== ---- pub/libvex_guest_mips32.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_mips32.h (.../trunk) (revision 2863) -@@ -41,82 +41,82 @@ - typedef - struct { - /* CPU Registers */ -- /* 0 */ UInt guest_r0; /* Hardwired to 0 */ -- /* 4 */ UInt guest_r1; /* Assembler temporary */ -- /* 8 */ UInt guest_r2; /* Values for function returns ...*/ -- /* 12 */ UInt guest_r3; /* ...and expression evaluation */ -- /* 16 */ UInt guest_r4; /* Function arguments */ -- /* 20 */ UInt guest_r5; -- /* 24 */ UInt guest_r6; -- /* 28 */ UInt guest_r7; -- /* 32 */ UInt guest_r8; /* Temporaries */ -- /* 36 */ UInt guest_r9; -- /* 40 */ UInt guest_r10; -- /* 44 */ UInt guest_r11; -- /* 48 */ UInt guest_r12; -- /* 52 */ UInt guest_r13; -- /* 56 */ UInt guest_r14; -- /* 60 */ UInt guest_r15; -- /* 64 */ UInt guest_r16; /* Saved temporaries */ -- /* 68 */ UInt guest_r17; -- /* 72 */ UInt guest_r18; -- /* 76 */ UInt guest_r19; -- /* 80 */ UInt guest_r20; -- /* 84 */ UInt guest_r21; -- /* 88 */ UInt guest_r22; -- /* 92 */ UInt guest_r23; -- /* 96 */ UInt guest_r24; /* Temporaries */ -- /* 100 */ UInt guest_r25; -- /* 104 */ UInt guest_r26; /* Reserved for OS kernel */ -- /* 108 */ UInt guest_r27; -- /* 112 */ UInt guest_r28; /* Global pointer */ -- /* 116 */ UInt guest_r29; /* Stack pointer */ -- /* 120 */ UInt guest_r30; /* Frame pointer */ -- /* 124 */ UInt guest_r31; /* Return address */ -- /* 128 */ UInt guest_PC; /* Program counter */ -- /* 132 */ UInt guest_HI;/* Multiply and divide register higher result */ -- /* 136 */ UInt guest_LO;/* Multiply and divide register lower result */ -+ /* 0 */ UInt guest_r0; /* Hardwired to 0 */ -+ /* 4 */ UInt guest_r1; /* Assembler temporary */ -+ /* 8 */ UInt guest_r2; /* Values for function returns ...*/ -+ /* 12 */ UInt guest_r3; /* ...and expression evaluation */ -+ /* 16 */ UInt guest_r4; /* Function arguments */ -+ /* 20 */ UInt guest_r5; -+ /* 24 */ UInt guest_r6; -+ /* 28 */ UInt guest_r7; -+ /* 32 */ UInt guest_r8; /* Temporaries */ -+ /* 36 */ UInt guest_r9; -+ /* 40 */ UInt guest_r10; -+ /* 44 */ UInt guest_r11; -+ /* 48 */ UInt guest_r12; -+ /* 52 */ UInt guest_r13; -+ /* 56 */ UInt guest_r14; -+ /* 60 */ UInt guest_r15; -+ /* 64 */ UInt guest_r16; /* Saved temporaries */ -+ /* 68 */ UInt guest_r17; -+ /* 72 */ UInt guest_r18; -+ /* 76 */ UInt guest_r19; -+ /* 80 */ UInt guest_r20; -+ /* 84 */ UInt guest_r21; -+ /* 88 */ UInt guest_r22; -+ /* 92 */ UInt guest_r23; -+ /* 96 */ UInt guest_r24; /* Temporaries */ -+ /* 100 */ UInt guest_r25; -+ /* 104 */ UInt guest_r26; /* Reserved for OS kernel */ -+ /* 108 */ UInt guest_r27; -+ /* 112 */ UInt guest_r28; /* Global pointer */ -+ /* 116 */ UInt guest_r29; /* Stack pointer */ -+ /* 120 */ UInt guest_r30; /* Frame pointer */ -+ /* 124 */ UInt guest_r31; /* Return address */ -+ /* 128 */ UInt guest_PC; /* Program counter */ -+ /* 132 */ UInt guest_HI; /* Multiply and divide register higher result */ -+ /* 136 */ UInt guest_LO; /* Multiply and divide register lower result */ - - /* FPU Registers */ -- /* 140 */ UInt guest_f0; /* Floting point general purpose registers */ -- /* 144 */ UInt guest_f1; -- /* 148 */ UInt guest_f2; -- /* 152 */ UInt guest_f3; -- /* 156 */ UInt guest_f4; -- /* 160 */ UInt guest_f5; -- /* 164 */ UInt guest_f6; -- /* 168 */ UInt guest_f7; -- /* 172 */ UInt guest_f8; -- /* 176 */ UInt guest_f9; -- /* 180 */ UInt guest_f10; -- /* 184 */ UInt guest_f11; -- /* 188 */ UInt guest_f12; -- /* 192 */ UInt guest_f13; -- /* 196 */ UInt guest_f14; -- /* 200 */ UInt guest_f15; -- /* 204 */ UInt guest_f16; -- /* 208 */ UInt guest_f17; -- /* 212 */ UInt guest_f18; -- /* 216 */ UInt guest_f19; -- /* 220 */ UInt guest_f20; -- /* 224 */ UInt guest_f21; -- /* 228 */ UInt guest_f22; -- /* 232 */ UInt guest_f23; -- /* 236 */ UInt guest_f24; -- /* 240 */ UInt guest_f25; -- /* 244 */ UInt guest_f26; -- /* 248 */ UInt guest_f27; -- /* 252 */ UInt guest_f28; -- /* 256 */ UInt guest_f29; -- /* 260 */ UInt guest_f30; -- /* 264 */ UInt guest_f31; -- -- /* 268 */ UInt guest_FIR; -- /* 272 */ UInt guest_FCCR; -- /* 276 */ UInt guest_FEXR; -- /* 280 */ UInt guest_FENR; -- /* 284 */ UInt guest_FCSR; -+ /* 144 */ ULong guest_f0; /* Floating point general purpose registers */ -+ /* 152 */ ULong guest_f1; -+ /* 160 */ ULong guest_f2; -+ /* 168 */ ULong guest_f3; -+ /* 176 */ ULong guest_f4; -+ /* 184 */ ULong guest_f5; -+ /* 192 */ ULong guest_f6; -+ /* 200 */ ULong guest_f7; -+ /* 208 */ ULong guest_f8; -+ /* 216 */ ULong guest_f9; -+ /* 224 */ ULong guest_f10; -+ /* 232 */ ULong guest_f11; -+ /* 240 */ ULong guest_f12; -+ /* 248 */ ULong guest_f13; -+ /* 256 */ ULong guest_f14; -+ /* 264 */ ULong guest_f15; -+ /* 272 */ ULong guest_f16; -+ /* 280 */ ULong guest_f17; -+ /* 288 */ ULong guest_f18; -+ /* 296 */ ULong guest_f19; -+ /* 304 */ ULong guest_f20; -+ /* 312 */ ULong guest_f21; -+ /* 320 */ ULong guest_f22; -+ /* 328 */ ULong guest_f23; -+ /* 336 */ ULong guest_f24; -+ /* 344 */ ULong guest_f25; -+ /* 352 */ ULong guest_f26; -+ /* 360 */ ULong guest_f27; -+ /* 368 */ ULong guest_f28; -+ /* 376 */ ULong guest_f29; -+ /* 384 */ ULong guest_f30; -+ /* 392 */ ULong guest_f31; - -+ /* 400 */ UInt guest_FIR; -+ /* 404 */ UInt guest_FCCR; -+ /* 408 */ UInt guest_FEXR; -+ /* 412 */ UInt guest_FENR; -+ /* 416 */ UInt guest_FCSR; -+ - /* TLS pointer for the thread. It's read-only in user space. - On Linux it is set in user space by various thread-related - syscalls. -@@ -126,29 +126,28 @@ - environments, the UserLocal register is a pointer to a - thread-specific storage block. - */ -- /* 288 */ UInt guest_ULR; -+ /* 420 */ UInt guest_ULR; - - /* Emulation notes */ -- UInt guest_EMNOTE; /* 292 */ -+ /* 424 */ UInt guest_EMNOTE; - - /* For clflush: record start and length of area to invalidate */ -- UInt guest_TISTART; /* 296 */ -- UInt guest_TILEN; /* 300 */ -- UInt guest_NRADDR; /* 304 */ -+ /* 428 */ UInt guest_CMSTART; -+ /* 432 */ UInt guest_CMLEN; -+ /* 436 */ UInt guest_NRADDR; - -- UInt host_EvC_FAILADDR; /* 308 */ -- UInt host_EvC_COUNTER; /* 312 */ -- UInt guest_COND; /* 316 */ -+ /* 440 */ UInt host_EvC_FAILADDR; -+ /* 444 */ UInt host_EvC_COUNTER; -+ /* 448 */ UInt guest_COND; - -- UInt padding1; - /* MIPS32 DSP ASE(r2) specific registers. */ -- UInt guest_DSPControl; /* 324 */ -- ULong guest_ac0; /* 328 */ -- ULong guest_ac1; /* 336 */ -- ULong guest_ac2; /* 344 */ -- ULong guest_ac3; /* 352 */ -- -- UInt padding[6]; -+ /* 452 */ UInt guest_DSPControl; -+ /* 456 */ ULong guest_ac0; -+ /* 464 */ ULong guest_ac1; -+ /* 472 */ ULong guest_ac2; -+ /* 480 */ ULong guest_ac3; -+ -+ UInt padding; - } VexGuestMIPS32State; - /*---------------------------------------------------------------*/ - /*--- Utility functions for MIPS32 guest stuff. ---*/ -Index: pub/libvex_guest_mips64.h -=================================================================== ---- pub/libvex_guest_mips64.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_mips64.h (.../trunk) (revision 2863) -@@ -137,8 +137,8 @@ - UInt guest_EMNOTE; /* 568 */ - - /* For clflush: record start and length of area to invalidate */ -- ULong guest_TISTART; /* 576 */ -- ULong guest_TILEN; /* 584 */ -+ ULong guest_CMSTART; /* 576 */ -+ ULong guest_CMLEN; /* 584 */ - - ULong guest_NRADDR; /* 592 */ - -@@ -145,7 +145,7 @@ - ULong host_EvC_FAILADDR; /* 600 */ - UInt host_EvC_COUNTER; /* 608 */ - UInt guest_COND; /* 612 */ -- UInt padding[6]; -+ UInt padding[2]; - } VexGuestMIPS64State; - - /*---------------------------------------------------------------*/ -Index: pub/libvex_guest_ppc32.h -=================================================================== ---- pub/libvex_guest_ppc32.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_ppc32.h (.../trunk) (revision 2863) -@@ -210,8 +210,8 @@ - /* 1196 */ UInt guest_EMNOTE; - - /* For icbi: record start and length of area to invalidate */ -- /* 1200 */ UInt guest_TISTART; -- /* 1204 */ UInt guest_TILEN; -+ /* 1200 */ UInt guest_CMSTART; -+ /* 1204 */ UInt guest_CMLEN; - - /* Used to record the unredirected guest address at the start of - a translation whose start has been redirected. By reading -@@ -242,7 +242,7 @@ - /* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register - /* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register - -- /* Padding to make it have an 8-aligned size */ -+ /* Padding to make it have an 16-aligned size */ - /* 1384 */ UInt padding2; - - } -Index: pub/libvex_guest_ppc64.h -=================================================================== ---- pub/libvex_guest_ppc64.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_ppc64.h (.../trunk) (revision 2863) -@@ -252,8 +252,8 @@ - /* 1340 */ UInt padding; - - /* For icbi: record start and length of area to invalidate */ -- /* 1344 */ ULong guest_TISTART; -- /* 1352 */ ULong guest_TILEN; -+ /* 1344 */ ULong guest_CMSTART; -+ /* 1352 */ ULong guest_CMLEN; - - /* Used to record the unredirected guest address at the start of - a translation whose start has been redirected. By reading -Index: pub/libvex_guest_s390x.h -=================================================================== ---- pub/libvex_guest_s390x.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_s390x.h (.../trunk) (revision 2863) -@@ -132,8 +132,8 @@ - - /* See comments at bottom of libvex.h */ - /* 384 */ ULong guest_NRADDR; -- /* 392 */ ULong guest_TISTART; -- /* 400 */ ULong guest_TILEN; -+ /* 392 */ ULong guest_CMSTART; -+ /* 400 */ ULong guest_CMLEN; - - /* Used when backing up to restart a syscall that has - been interrupted by a signal. See also comment in -@@ -148,11 +148,11 @@ - /* 424 */ ULong host_EvC_FAILADDR; - - /*------------------------------------------------------------*/ --/*--- Force alignment to 32 bytes ---*/ -+/*--- Force alignment to 16 bytes ---*/ - /*------------------------------------------------------------*/ -- /* 432 */ UChar padding[16]; -+ /* 432 */ UChar padding[0]; - -- /* 448 */ /* This is the size of the guest state */ -+ /* 432 */ /* This is the size of the guest state */ - } VexGuestS390XState; - - -Index: pub/libvex_guest_x86.h -=================================================================== ---- pub/libvex_guest_x86.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_guest_x86.h (.../trunk) (revision 2863) -@@ -199,9 +199,9 @@ - /* Emulation notes */ - UInt guest_EMNOTE; - -- /* For clflush: record start and length of area to invalidate */ -- UInt guest_TISTART; -- UInt guest_TILEN; -+ /* For clflush/clinval: record start and length of area */ -+ UInt guest_CMSTART; -+ UInt guest_CMLEN; - - /* Used to record the unredirected guest address at the start of - a translation whose start has been redirected. By reading -@@ -220,8 +220,8 @@ - been interrupted by a signal. */ - UInt guest_IP_AT_SYSCALL; - -- /* Padding to make it have an 32-aligned size */ -- UInt padding[5]; -+ /* Padding to make it have an 16-aligned size */ -+ UInt padding1; - } - VexGuestX86State; - -Index: pub/libvex_ir.h -=================================================================== ---- pub/libvex_ir.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_ir.h (.../trunk) (revision 2863) -@@ -242,7 +242,11 @@ - /* Get the size (in bytes) of an IRType */ - extern Int sizeofIRType ( IRType ); - -+/* Translate 1/2/4/8 into Ity_I{8,16,32,64} respectively. Asserts on -+ any other input. */ -+extern IRType integerIRTypeOfSize ( Int szB ); - -+ - /* ------------------ Endianness ------------------ */ - - /* IREndness is used in load IRExprs and store IRStmts. */ -@@ -481,9 +485,11 @@ - Iop_DivS32, // ditto, signed - Iop_DivU64, // :: I64,I64 -> I64 (simple div, no mod) - Iop_DivS64, // ditto, signed -- Iop_DivU64E, // :: I64,I64 -> I64 (dividend is 64-bit arg (hi) concat with 64 0's (low)) -+ Iop_DivU64E, // :: I64,I64 -> I64 (dividend is 64-bit arg (hi) -+ // concat with 64 0's (low)) - Iop_DivS64E, // ditto, signed -- Iop_DivU32E, // :: I32,I32 -> I32 (dividend is 32-bit arg (hi) concat with 32 0's (low)) -+ Iop_DivU32E, // :: I32,I32 -> I32 (dividend is 32-bit arg (hi) -+ // concat with 32 0's (low)) - Iop_DivS32E, // ditto, signed - - Iop_DivModU64to32, // :: I64,I32 -> I64 -@@ -1240,8 +1246,8 @@ - - /* BCD arithmetic instructions, (V128, V128) -> V128 - * The BCD format is the same as that used in the BCD<->DPB conversion -- * routines, except using 124 digits (vs 60) plus the trailing 4-bit signed code. -- * */ -+ * routines, except using 124 digits (vs 60) plus the trailing 4-bit -+ * signed code. */ - Iop_BCDAdd, Iop_BCDSub, - - /* Conversion I64 -> D64 */ -@@ -1254,8 +1260,10 @@ - - /* --- 32x4 vector FP --- */ - -+ /* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */ -+ Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4, -+ - /* binary */ -- Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4, - Iop_Max32Fx4, Iop_Min32Fx4, - Iop_Add32Fx2, Iop_Sub32Fx2, - /* Note: For the following compares, the ppc and arm front-ends assume a -@@ -1263,13 +1271,11 @@ - Iop_CmpEQ32Fx4, Iop_CmpLT32Fx4, Iop_CmpLE32Fx4, Iop_CmpUN32Fx4, - Iop_CmpGT32Fx4, Iop_CmpGE32Fx4, - -- /* Vector Absolute */ -- Iop_Abs32Fx4, -- - /* Pairwise Max and Min. See integer pairwise operations for details. */ - Iop_PwMax32Fx4, Iop_PwMin32Fx4, - - /* unary */ -+ Iop_Abs32Fx4, - Iop_Sqrt32Fx4, Iop_RSqrt32Fx4, - Iop_Neg32Fx4, - -@@ -1296,9 +1302,9 @@ - /* Unlike the standard fp conversions, these irops take no - rounding mode argument. Instead the irop trailers _R{M,P,N,Z} - indicate the mode: {-inf, +inf, nearest, zero} respectively. */ -- Iop_I32UtoFx4, Iop_I32StoFx4, /* I32x4 -> F32x4 */ -+ Iop_I32UtoFx4, Iop_I32StoFx4, /* I32x4 -> F32x4 */ - Iop_FtoI32Ux4_RZ, Iop_FtoI32Sx4_RZ, /* F32x4 -> I32x4 */ -- Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ, /* F32x4 -> I32x4 (with saturation) */ -+ Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ, /* F32x4 -> I32x4 (saturating) */ - Iop_RoundF32x4_RM, Iop_RoundF32x4_RP, /* round to fp integer */ - Iop_RoundF32x4_RN, Iop_RoundF32x4_RZ, /* round to fp integer */ - /* Fixed32 format is floating-point number with fixed number of fraction -@@ -1326,14 +1332,21 @@ - - /* --- 64x2 vector FP --- */ - -+ /* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */ -+ Iop_Add64Fx2, Iop_Sub64Fx2, Iop_Mul64Fx2, Iop_Div64Fx2, -+ - /* binary */ -- Iop_Add64Fx2, Iop_Sub64Fx2, Iop_Mul64Fx2, Iop_Div64Fx2, - Iop_Max64Fx2, Iop_Min64Fx2, - Iop_CmpEQ64Fx2, Iop_CmpLT64Fx2, Iop_CmpLE64Fx2, Iop_CmpUN64Fx2, - - /* unary */ -- Iop_Recip64Fx2, Iop_Sqrt64Fx2, Iop_RSqrt64Fx2, -+ Iop_Abs64Fx2, -+ Iop_Sqrt64Fx2, Iop_RSqrt64Fx2, -+ Iop_Neg64Fx2, - -+ /* Vector Reciprocal Estimate */ -+ Iop_Recip64Fx2, -+ - /* --- 64x2 lowest-lane-only scalar FP --- */ - - /* In binary cases, upper half is copied from first operand. In -@@ -1357,6 +1370,12 @@ - Iop_64UtoV128, - Iop_SetV128lo64, - -+ /* Copies lower 64/32/16/8 bits, zeroes out the rest. */ -+ Iop_ZeroHI64ofV128, // :: V128 -> V128 -+ Iop_ZeroHI96ofV128, // :: V128 -> V128 -+ Iop_ZeroHI112ofV128, // :: V128 -> V128 -+ Iop_ZeroHI120ofV128, // :: V128 -> V128 -+ - /* 32 <-> 128 bit vector */ - Iop_32UtoV128, - Iop_V128to32, // :: V128 -> I32, lowest lane -@@ -1405,8 +1424,8 @@ - Iop_QRDMulHi16Sx8, Iop_QRDMulHi32Sx4, - /* Doubling saturating multiplication (long) (I64, I64) -> V128 */ - Iop_QDMulLong16Sx4, Iop_QDMulLong32Sx2, -- /* Plynomial multiplication treats it's arguments as coefficients of -- polynoms over {0, 1}. */ -+ /* Polynomial multiplication treats its arguments as -+ coefficients of polynomials over {0, 1}. */ - Iop_PolynomialMul8x16, /* (V128, V128) -> V128 */ - Iop_PolynomialMull8x8, /* (I64, I64) -> V128 */ - -@@ -1519,7 +1538,8 @@ - - /* NARROWING (unary) -- narrow V128 into I64 */ - Iop_NarrowUn16to8x8, Iop_NarrowUn32to16x4, Iop_NarrowUn64to32x2, -- /* Saturating narrowing from signed source to signed/unsigned destination */ -+ /* Saturating narrowing from signed source to signed/unsigned -+ destination */ - Iop_QNarrowUn16Sto8Sx8, Iop_QNarrowUn32Sto16Sx4, Iop_QNarrowUn64Sto32Sx2, - Iop_QNarrowUn16Sto8Ux8, Iop_QNarrowUn32Sto16Ux4, Iop_QNarrowUn64Sto32Ux2, - /* Saturating narrowing from unsigned source to unsigned destination */ -@@ -1657,15 +1677,11 @@ - Iop_SHA512, Iop_SHA256, - - /* ------------------ 256-bit SIMD FP. ------------------ */ -- Iop_Add64Fx4, -- Iop_Sub64Fx4, -- Iop_Mul64Fx4, -- Iop_Div64Fx4, -- Iop_Add32Fx8, -- Iop_Sub32Fx8, -- Iop_Mul32Fx8, -- Iop_Div32Fx8, - -+ /* ternary :: IRRoundingMode(I32) x V256 x V256 -> V256 */ -+ Iop_Add64Fx4, Iop_Sub64Fx4, Iop_Mul64Fx4, Iop_Div64Fx4, -+ Iop_Add32Fx8, Iop_Sub32Fx8, Iop_Mul32Fx8, Iop_Div32Fx8, -+ - Iop_Sqrt32Fx8, - Iop_Sqrt64Fx4, - Iop_RSqrt32Fx8, -@@ -1691,7 +1707,7 @@ - Irrm_PosINF = 2, // Round to positive infinity - Irrm_ZERO = 3, // Round toward zero - Irrm_NEAREST_TIE_AWAY_0 = 4, // Round to nearest, ties away from 0 -- Irrm_PREPARE_SHORTER = 5, // Round to prepare for storter -+ Irrm_PREPARE_SHORTER = 5, // Round to prepare for shorter - // precision - Irrm_AWAY_FROM_ZERO = 6, // Round to away from 0 - Irrm_NEAREST_TIE_TOWARD_0 = 7 // Round to nearest, ties towards 0 -@@ -2059,13 +2075,18 @@ - /* This describes hints which can be passed to the dispatcher at guest - control-flow transfer points. - -- Re Ijk_TInval: the guest state _must_ have two pseudo-registers, -- guest_TISTART and guest_TILEN, which specify the start and length -- of the region to be invalidated. These are both the size of a -- guest word. It is the responsibility of the relevant toIR.c to -- ensure that these are filled in with suitable values before issuing -- a jump of kind Ijk_TInval. -+ Re Ijk_InvalICache and Ijk_FlushDCache: the guest state _must_ have -+ two pseudo-registers, guest_CMSTART and guest_CMLEN, which specify -+ the start and length of the region to be invalidated. CM stands -+ for "Cache Management". These are both the size of a guest word. -+ It is the responsibility of the relevant toIR.c to ensure that -+ these are filled in with suitable values before issuing a jump of -+ kind Ijk_InvalICache or Ijk_FlushDCache. - -+ Ijk_InvalICache requests invalidation of translations taken from -+ the requested range. Ijk_FlushDCache requests flushing of the D -+ cache for the specified range. -+ - Re Ijk_EmWarn and Ijk_EmFail: the guest state must have a - pseudo-register guest_EMNOTE, which is 32-bits regardless of the - host or guest word size. That register should be made to hold a -@@ -2093,8 +2114,10 @@ - Ijk_EmFail, /* emulation critical (FATAL) error; give up */ - Ijk_NoDecode, /* current instruction cannot be decoded */ - Ijk_MapFail, /* Vex-provided address translation failed */ -- Ijk_TInval, /* Invalidate translations before continuing. */ -+ Ijk_InvalICache, /* Inval icache for range [CMSTART, +CMLEN) */ -+ Ijk_FlushDCache, /* Flush dcache for range [CMSTART, +CMLEN) */ - Ijk_NoRedir, /* Jump to un-redirected guest addr */ -+ Ijk_SigILL, /* current instruction synths SIGILL */ - Ijk_SigTRAP, /* current instruction synths SIGTRAP */ - Ijk_SigSEGV, /* current instruction synths SIGSEGV */ - Ijk_SigBUS, /* current instruction synths SIGBUS */ -@@ -2102,7 +2125,7 @@ - Ijk_SigFPE_IntOvf, /* current instruction synths SIGFPE - IntOvf */ - /* Unfortunately, various guest-dependent syscall kinds. They - all mean: do a syscall before continuing. */ -- Ijk_Sys_syscall, /* amd64 'syscall', ppc 'sc', arm 'svc #0' */ -+ Ijk_Sys_syscall, /* amd64/x86 'syscall', ppc 'sc', arm 'svc #0' */ - Ijk_Sys_int32, /* amd64/x86 'int $0x20' */ - Ijk_Sys_int128, /* amd64/x86 'int $0x80' */ - Ijk_Sys_int129, /* amd64/x86 'int $0x81' */ -@@ -2849,12 +2872,12 @@ - /*---------------------------------------------------------------*/ - /*--- IR injection ---*/ - /*---------------------------------------------------------------*/ -+ - void vex_inject_ir(IRSB *, IREndness); - - - #endif /* ndef __LIBVEX_IR_H */ - -- - /*---------------------------------------------------------------*/ - /*--- libvex_ir.h ---*/ - /*---------------------------------------------------------------*/ -Index: pub/libvex_trc_values.h -=================================================================== ---- pub/libvex_trc_values.h (.../tags/VEX_3_9_0) (revision 2863) -+++ pub/libvex_trc_values.h (.../trunk) (revision 2863) -@@ -46,15 +46,12 @@ - - These values should be 61 or above so as not to conflict - with Valgrind's VG_TRC_ values, which are 60 or below. -- -- These values *must* be odd (have bit 0 set) because the dispatchers -- (coregrind/m_dispatch/dispatch-*-*.S) use this fact to distinguish -- a TRC value from the unchanged baseblock pointer -- which has 0 as -- its lowest bit. - */ - --#define VEX_TRC_JMP_TINVAL 61 /* invalidate translations before -- continuing */ -+#define VEX_TRC_JMP_INVALICACHE 61 /* invalidate icache (translations) -+ before continuing */ -+#define VEX_TRC_JMP_FLUSHDCACHE 103 /* flush dcache before continuing */ -+ - #define VEX_TRC_JMP_NOREDIR 81 /* jump to undirected guest addr */ - #define VEX_TRC_JMP_SIGTRAP 85 /* deliver trap (SIGTRAP) before - continuing */ -@@ -68,6 +65,9 @@ - #define VEX_TRC_JMP_SIGFPE_INTOVF 99 /* deliver SIGFPE (integer overflow) - before continuing */ - -+#define VEX_TRC_JMP_SIGILL 101 /* deliver SIGILL (Illegal instruction) -+ before continuing */ -+ - #define VEX_TRC_JMP_EMWARN 63 /* deliver emulation warning before - continuing */ - #define VEX_TRC_JMP_EMFAIL 83 /* emulation fatal error; abort system */ diff --git a/aarch64-support.diff b/aarch64-support.diff deleted file mode 100644 index d76c7a4..0000000 --- a/aarch64-support.diff +++ /dev/null @@ -1,87673 +0,0 @@ -Index: Makefile.all.am -=================================================================== ---- Makefile.all.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ Makefile.all.am (.../trunk) (revision 13981) -@@ -58,6 +58,14 @@ - $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \ - done - -+# This is used by coregrind/Makefile.am and by /Makefile.am for doing -+# "make uninstall". It removes $(noinst_PROGRAMS) from $prefix/lib/valgrind/. -+# It needs to be depended on by an 'uninstall-local' rule. -+uninstall-noinst_PROGRAMS: -+ for f in $(noinst_PROGRAMS); do \ -+ rm -f $(DESTDIR)$(pkglibdir)/$$f; \ -+ done -+ - # Similar to install-noinst_PROGRAMS. - # Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with - # directories. XXX: not sure whether the resulting permissions will be -@@ -68,6 +76,12 @@ - cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \ - done - -+# Similar to uninstall-noinst_PROGRAMS. -+uninstall-noinst_DSYMS: -+ for f in $(noinst_DSYMS); do \ -+ rm -f $(DESTDIR)$(pkglibdir)/$$f.dSYM; \ -+ done -+ - # This needs to be depended on by a 'clean-local' rule. - clean-noinst_DSYMS: - for f in $(noinst_DSYMS); do \ -@@ -117,6 +131,7 @@ - -I$(top_srcdir) \ - -I$(top_srcdir)/include \ - -I$(top_srcdir)/VEX/pub \ -+ -I$(top_builddir)/VEX/pub \ - -DVGA_@VGCONF_ARCH_PRI@=1 \ - -DVGO_@VGCONF_OS@=1 \ - -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \ -@@ -126,6 +141,7 @@ - -I$(top_srcdir) \ - -I$(top_srcdir)/include \ - -I$(top_srcdir)/VEX/pub \ -+ -I$(top_builddir)/VEX/pub \ - -DVGA_@VGCONF_ARCH_SEC@=1 \ - -DVGO_@VGCONF_OS@=1 \ - -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1 \ -@@ -156,6 +172,10 @@ - AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \ - -marm -mcpu=cortex-a8 -g - -+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@ -+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g -+ - AM_FLAG_M3264_X86_DARWIN = -arch i386 - AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \ - -mmacosx-version-min=10.5 \ -@@ -173,12 +193,12 @@ - AM_CCASFLAGS_S390X_LINUX = @FLAG_M64@ -g -mzarch -march=z900 - - AM_FLAG_M3264_MIPS32_LINUX = @FLAG_M32@ --AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) -mips32 --AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -mips32 -g -+AM_CFLAGS_MIPS32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) @FLAG_MIPS32@ -+AM_CCASFLAGS_MIPS32_LINUX = @FLAG_M32@ -g @FLAG_MIPS32@ - - AM_FLAG_M3264_MIPS64_LINUX = @FLAG_M64@ --AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -mips64 --AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -mips64 -g -+AM_CFLAGS_MIPS64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) @FLAG_MIPS64@ -+AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@ - - # Flags for the primary target. These must be used to build the - # regtests and performance tests. In fact, these must be used to -@@ -213,6 +233,7 @@ - PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ - PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ -+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386 - PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64 - PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -Index: Makefile.am -=================================================================== ---- Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ Makefile.am (.../trunk) (revision 13981) -@@ -25,6 +25,7 @@ - . \ - $(TOOLS) \ - $(EXP_TOOLS) \ -+ shared \ - tests \ - perf \ - gdbserver_tests \ -@@ -64,12 +65,12 @@ - default.supp: $(DEFAULT_SUPP_FILES) - echo "# This is a generated file, composed of the following suppression rules:" > default.supp - echo "# " $(DEFAULT_SUPP_FILES) >> default.supp -- cat $(DEFAULT_SUPP_FILES) >> default.supp -+ cat $^ >> default.supp - - ## Preprend @PERL@ because tests/vg_regtest isn't executable - ## Ensure make exits with error if PERL fails or post_regtest_checks fails. - regtest: check -- gdbserver_tests/make_local_links $(GDB) -+ $(top_srcdir)/gdbserver_tests/make_local_links $(GDB) - if @PERL@ tests/vg_regtest gdbserver_tests $(TOOLS) $(EXP_TOOLS) ; then \ - tests/post_regtest_checks $(abs_top_srcdir) gdbserver_tests $(TOOLS) $(EXP_TOOLS); \ - else \ -@@ -104,6 +105,7 @@ - README.android \ - README.android_emulator \ - README.mips \ -+ README.aarch64 \ - NEWS.old \ - valgrind.pc.in \ - valgrind.spec.in \ -Index: Makefile.tool-tests.am -=================================================================== ---- Makefile.tool-tests.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ Makefile.tool-tests.am (.../trunk) (revision 13981) -@@ -5,6 +5,7 @@ - AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \ - -I$(top_srcdir)/coregrind -I$(top_builddir)/include \ - -I$(top_srcdir)/VEX/pub \ -+ -I$(top_builddir)/VEX/pub \ - -DVGA_@VGCONF_ARCH_PRI@=1 \ - -DVGO_@VGCONF_OS@=1 \ - -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1 \ -Index: Makefile.tool.am -=================================================================== ---- Makefile.tool.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ Makefile.tool.am (.../trunk) (revision 13981) -@@ -52,6 +52,9 @@ - TOOL_LDFLAGS_ARM_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ - -+TOOL_LDFLAGS_ARM64_LINUX = \ -+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+ - TOOL_LDFLAGS_S390X_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - -@@ -105,6 +108,9 @@ - LIBREPLACEMALLOC_ARM_LINUX = \ - $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a - -+LIBREPLACEMALLOC_ARM64_LINUX = \ -+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm64-linux.a -+ - LIBREPLACEMALLOC_X86_DARWIN = \ - $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a - -@@ -145,6 +151,11 @@ - $(LIBREPLACEMALLOC_ARM_LINUX) \ - -Wl,--no-whole-archive - -+LIBREPLACEMALLOC_LDFLAGS_ARM64_LINUX = \ -+ -Wl,--whole-archive \ -+ $(LIBREPLACEMALLOC_ARM64_LINUX) \ -+ -Wl,--no-whole-archive -+ - LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \ - $(LIBREPLACEMALLOC_X86_DARWIN) - -@@ -176,3 +187,5 @@ - - install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS - -+uninstall-local: uninstall-noinst_PROGRAMS uninstall-noinst_DSYMS -+ -Index: Makefile.vex.am -=================================================================== ---- Makefile.vex.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ Makefile.vex.am (.../trunk) (revision 13981) -@@ -24,6 +24,7 @@ - pub/libvex_guest_ppc32.h \ - pub/libvex_guest_ppc64.h \ - pub/libvex_guest_arm.h \ -+ pub/libvex_guest_arm64.h \ - pub/libvex_guest_s390x.h \ - pub/libvex_guest_mips32.h \ - pub/libvex_guest_mips64.h \ -@@ -42,6 +43,7 @@ - priv/guest_amd64_defs.h \ - priv/guest_ppc_defs.h \ - priv/guest_arm_defs.h \ -+ priv/guest_arm64_defs.h \ - priv/guest_s390_defs.h \ - priv/guest_mips_defs.h \ - priv/host_generic_regs.h \ -@@ -53,6 +55,7 @@ - priv/host_amd64_defs.h \ - priv/host_ppc_defs.h \ - priv/host_arm_defs.h \ -+ priv/host_arm64_defs.h \ - priv/host_s390_defs.h \ - priv/s390_disasm.h \ - priv/s390_defs.h \ -@@ -71,15 +74,17 @@ - pub/libvex_guest_ppc32.h \ - pub/libvex_guest_ppc64.h \ - pub/libvex_guest_arm.h \ -+ pub/libvex_guest_arm64.h \ - pub/libvex_guest_s390x.h \ - pub/libvex_guest_mips32.h \ - pub/libvex_guest_mips64.h - rm -f auxprogs/genoffsets.s -+ $(mkdir_p) auxprogs pub - $(CC) $(CFLAGS) \ - $(LIBVEX_CFLAGS) \ - $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ - -O -S -o auxprogs/genoffsets.s \ -- auxprogs/genoffsets.c -+ $(srcdir)/auxprogs/genoffsets.c - grep xyzzy auxprogs/genoffsets.s | grep "^#define" \ - | sed "s/xyzzy\\$$//g" \ - | sed "s/xyzzy#//g" \ -@@ -114,6 +119,8 @@ - priv/guest_ppc_toIR.c \ - priv/guest_arm_helpers.c \ - priv/guest_arm_toIR.c \ -+ priv/guest_arm64_helpers.c \ -+ priv/guest_arm64_toIR.c \ - priv/guest_s390_helpers.c \ - priv/guest_s390_toIR.c \ - priv/guest_mips_helpers.c \ -@@ -132,6 +139,8 @@ - priv/host_ppc_isel.c \ - priv/host_arm_defs.c \ - priv/host_arm_isel.c \ -+ priv/host_arm64_defs.c \ -+ priv/host_arm64_isel.c \ - priv/host_s390_defs.c \ - priv/host_s390_isel.c \ - priv/s390_disasm.c \ -Index: NEWS -=================================================================== ---- NEWS (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ NEWS (.../trunk) (revision 13981) -@@ -1,4 +1,141 @@ -+Release 3.10.0 (?? ?????? 201?) -+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -+3.10.0 is not yet released. - -+* ================== PLATFORM CHANGES ================= -+ -+* Support for Android on MIPS32. -+* Support for 64bit FPU on MIPS32 platforms. -+ -+* ==================== TOOL CHANGES ==================== -+ -+* Memcheck: -+ - new client requests -+ VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE and -+ VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE -+ -+* Helgrind: -+ - Helgrind GDB server monitor command 'info locks' giving -+ the list of locks, their location, and their status. -+ -+* Callgrind: -+ - callgrind_control now supports the --vgdb-prefix argument, -+ which is needed if valgrind was started with this same argument. -+ -+* ==================== OTHER CHANGES ==================== -+ -+* New and modified GDB server monitor features: -+ -+ - The GDB server monitor command 'v.info location
' -+ outputs information about an address. The information produced depends -+ on the tool and on the options given to valgrind. -+ Possibly, the following are described: global variables, local (stack) -+ variables, allocated or freed blocks, ... -+ -+ - The option "--vgdb-stop-at=event1,event2,..." allows the user -+ to ask GDB server to stop before program execution, at the end -+ of the program execution and on Valgrind internal errors. -+ -+ - A new monitor command "v.info stats" that shows various valgrind core and -+ tool statistics. -+ -+ - A new monitor command "v.set hostvisibility" that allows GDB server -+ to provide access to Valgrind internal host status/memory. -+ -+* New option --aspace-minaddr=
allows to (possibly) make -+ use of some more memory by decreasing the default value above which -+ Valgrind maps memory or solve some conflicts with system libraries -+ by increasing the value. -+ See user manual for details. -+ -+* Minor improvements in dwarf handling with --read-var-info=yes -+ - Ada and C struct containing VLA do not cause a bad DIE error anymore -+ - Code compiled with -ffunction-sections -fdata-sections -Wl,--gc-sections -+ does not cause assert errors anymore. -+ -+* ==================== FIXED BUGS ==================== -+ -+The following bugs have been fixed or resolved. Note that "n-i-bz" -+stands for "not in bugzilla" -- that is, a bug that was reported to us -+but never got a bugzilla entry. We encourage you to file bugs in -+bugzilla (https://bugs.kde.org/enter_bug.cgi?product=valgrind) rather -+than mailing the developers (or mailing lists) directly -- bugs that -+are not entered into bugzilla tend to get forgotten about or ignored. -+ -+To see details of a given bug, visit -+ https://bugs.kde.org/show_bug.cgi?id=XXXXXX -+where XXXXXX is the bug number as listed below. -+ -+175819 Support for ipv6 socket reporting with --track-fds -+232510 make distcheck fails -+308729 vex x86->IR: unhandled instruction bytes 0xf 0x5 (syscall) -+325110 Add test-cases for Power ISA 2.06 insns: divdo/divdo. and divduo/divduo. -+325124 [MIPSEL] Compilation error -+325477 Phase 4 support for IBM Power ISA 2.07 -+325628 Phase 5 support for IBM Power ISA 2.07 -+325714 Empty vgcore but RLIMIT_CORE is big enough (too big) -+325751 Missing the two privileged Power PC Transactional Memory Instructions -+325816 Phase 6 support for IBM Power ISA 2.07 -+325856 Make SGCheck fail gracefully on unsupported platforms -+326436 DRD: False positive in libstdc++ std::list::push_back -+326444 Cavium MIPS Octeon Specific Load Indexed Instructions -+326462 Refactor vgdb to isolate invoker stuff into separate module -+326623 DRD: false positive conflict report in a field assignment -+326816 Intercept for __strncpy_sse2_unaligned missing? -+326921 coregrind fails to compile m_trampoline.S with MIPS/Linux port of V -+326983 Clear direction flag after tests on amd64. -+327212 Do not prepend the current directory to absolute path names. -+327238 Callgrind Assertion 'passed <= last_bb->cjmp_count' failed -+327284 s390x: Fix translation of the risbg instruction -+327837 dwz compressed alternate .debug_info and .debug_str not read correctly -+327916 DW_TAG_typedef may have no name -+328100 XABORT not implemented -+328205 Implement additional Xen hypercalls -+328455 s390x: SIGILL after emitting wrong register pair for ldxbr -+328711 valgrind.1 manpage "memcheck options" section is badly generated -+329612 Incorrect handling of AT_BASE for image execution -+329956 valgrind crashes when lmw/stmw instructions are used on ppc64 -+330228 mmap must align to VKI_SHMLBA on mips32 -+330459 --track-fds=yes doesn't track eventfds -+330469 Add clock_adjtime syscall support -+330622 Add test to regression suite for POWER instruction: dcbzl -+330939 Support for AMD's syscall instruction on x86 -+ == 308729 -+330941 Typo in PRE(poll) syscall wrapper -+331057 unhandled instruction: 0xEEE01B20 (vfma.f64) (has patch) -+331254 Fix expected output for memcheck/tests/dw4 -+331255 Fix race condition in test none/tests/coolo_sigaction -+331257 Fix type of jump buffer in test none/tests/faultstatus -+331305 configure uses bash specific syntax -+331337 s390x WARNING: unhandled syscall: 326 (dup3) -+331380 Syscall param timer_create(evp) points to uninitialised byte(s) -+331830 ppc64: WARNING: unhandled syscall: 96/97 -+331839 drd/tests/sem_open specifies invalid semaphore name -+331847 outcome of drd/tests/thread_name is nondeterministic -+332037 Valgrind cannot handle Thumb "add pc, reg" -+332055 drd asserts on platforms with VG_STACK_REDZONE_SZB == 0 and -+ consistency checks enabled -+332263 intercepts for pthread_rwlock_timedrdlock and -+ pthread_rwlock_timedwrlock are incorrect -+332265 drd could do with post-rwlock_init and pre-rwlock_destroy -+ client requests -+332276 Implement additional Xen hypercalls -+332658 ldrd.w r1, r2, [PC, #imm] does not adjust for 32bit alignment -+333145 Tests for missaligned PC+#imm access for arm -+333228 AAarch64 Missing instruction encoding: mrs %[reg], ctr_el0 -+333230 AAarch64 missing instruction encodings: dc, ic, dsb. -+333428 ldr.w pc [rD, #imm] instruction leads to assertion -+333666 Recognize MPX instructions and bnd prefix. -+334049 lzcnt fails silently (x86_32) -+334705 sendmsg and recvmsg should guard against bogus msghdr fields. -+334727 Build fails with -Werror=format-security -+334788 clarify doc about --log-file initial program directory -+n-i-bz Fix KVM_CREATE_IRQCHIP ioctl handling -+n-i-bz s390x: Fix memory corruption for multithreaded applications -+n-i-bz vex arm->IR: allow PC as basereg in some LDRD cases -+n-i-bz internal error in Valgrind if vgdb transmit signals when ptrace invoked -+n-i-bz Fix mingw64 support in valgrind.h (dev@, 9 May 2014) -+ - Release 3.9.0 (31 October 2013) - ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - 3.9.0 is a feature release with many improvements and the usual -Index: README.aarch64 -=================================================================== ---- README.aarch64 (.../tags/VALGRIND_3_9_0) (revision 0) -+++ README.aarch64 (.../trunk) (revision 13981) -@@ -0,0 +1,240 @@ -+ -+Status -+~~~~~~ -+ -+As of Jan 2014 the trunk contains a port to AArch64 ARMv8 -- loosely, -+the 64-bit ARM architecture. Currently it supports integer and FP -+instructions and can run anything generated by gcc-4.8.2 -O3. The -+port is under active development. -+ -+Current limitations, as of mid-May 2014. -+ -+* limited support of vector (SIMD) instructions. Initial target is -+ support for instructions created by gcc-4.8.2 -O3 -+ (via autovectorisation). This is complete. -+ -+* Integration with the built in GDB server: -+ - works ok (breakpoint, attach to a process blocked in a syscall, ...) -+ - still to do: -+ arm64 xml register description files (allowing shadow registers -+ to be looked at). -+ cpsr transfer to/from gdb to be looked at (see also arm equivalent code) -+ -+* limited syscall support -+ -+There has been extensive testing of the baseline simulation of integer -+and FP instructions. Memcheck is also believed to work, at least for -+small examples. Other tools appear to at least not crash when running -+/bin/date. -+ -+Enough syscalls and instructions are supported for substantial -+programs to work. Firefox 26 is able to start up and quit. The noise -+level from Memcheck is low enough to make it practical to use for real -+debugging. -+ -+ -+Building -+~~~~~~~~ -+ -+You could probably build it directly on a target OS, using the normal -+non-cross scheme -+ -+ ./autogen.sh ; ./configure --prefix=.. ; make ; make install -+ -+Development so far was however done by cross compiling, viz: -+ -+ export CC=aarch64-linux-gnu-gcc -+ export LD=aarch64-linux-gnu-ld -+ export AR=aarch64-linux-gnu-ar -+ -+ ./autogen.sh -+ ./configure --prefix=`pwd`/Inst --host=aarch64-unknown-linux \ -+ --enable-only64bit -+ make -j4 -+ make -j4 install -+ -+Doing this assumes that the install path (`pwd`/Inst) is valid on -+both host and target, which isn't normally the case. To avoid -+this limitation, do instead: -+ -+ ./configure --prefix=/install/path/on/target \ -+ --host=aarch64-unknown-linux \ -+ --enable-only64bit -+ make -j4 -+ make -j4 install DESTDIR=/a/temp/dir/on/host -+ # and then copy the contents of DESTDIR to the target. -+ -+See README.android for more examples of cross-compile building. -+ -+ -+Implementation tidying-up/TODO notes -+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -+ -+UnwindStartRegs -- what should that contain? -+ -+ -+vki-arm64-linux.h: vki_sigaction_base -+I really don't think that __vki_sigrestore_t sa_restorer -+should be present. Adding it surely puts sa_mask at a wrong -+offset compared to (kernel) reality. But not having it causes -+compilation of m_signals.c to fail in hard to understand ways, -+so adding it temporarily. -+ -+ -+m_trampoline.S: what's the unexecutable-insn value? 0xFFFFFFFF -+is there at the moment, but 0x00000000 is probably what it should be. -+Also, fix indentation/tab-vs-space stuff -+ -+ -+./include/vki/vki-arm64-linux.h: uses __uint128_t. Should change -+it to __vki_uint128_t, but what's the defn of that? -+ -+ -+m_debuginfo/priv_storage.h: need proper defn of DiCfSI -+ -+ -+readdwarf.c: is this correct? -+#elif defined(VGP_arm64_linux) -+# define FP_REG 29 //??? -+# define SP_REG 31 //??? -+# define RA_REG_DEFAULT 30 //??? -+ -+ -+vki-arm64-linux.h: -+re linux-3.10.5/include/uapi/asm-generic/sembuf.h -+I'd say the amd64 version has padding it shouldn't have. Check? -+ -+ -+syswrap-linux.c run_a_thread_NORETURN assembly sections -+seems like tst->os_state.exitcode has word type -+in which case the ppc64_linux use of lwz to read it, is wrong -+ -+ -+syswrap-linux.c ML_(do_fork_clone) -+assuming that VGP_arm64_linux is the same as VGP_arm_linux here -+ -+ -+dispatch-arm64-linux.S: FIXME: set up FP control state before -+entering generated code. Also fix screwy indentation. -+ -+ -+dispatcher-ery general: what's a good (predictor-friendly) way to -+branch to a register? -+ -+ -+in vki-arm64-scnums.h -+//#if __BITS_PER_LONG == 64 && !defined(__SYSCALL_COMPAT) -+Probably want to reenable that and clean up accordingly -+ -+ -+putIRegXXorZR: figure out a way that the computed value is actually -+used, so as to keep any memory reads that might generate it, alive. -+(else the simulation can lose exceptions). At least, for writes to -+the zero register generated by loads .. or .. can anything other -+integer instructions, that write to a register, cause exceptions? -+ -+ -+loads/stores: generate stack alignment checks as necessary -+ -+ -+fix barrier insns: ISB, DMB -+ -+ -+fix atomic loads/stores -+ -+ -+FMADD/FMSUB/FNMADD/FNMSUB: generate and use the relevant fused -+IROps so as to avoid double rounding -+ -+ -+ARM64Instr_Call getRegUsage: re-check relative to what -+getAllocableRegs_ARM64 makes available -+ -+ -+Make dispatch-arm64-linux.S save any callee-saved Q regs -+I think what is required is to save D8-D15 and nothing more than that. -+ -+ -+wrapper for __NR3264_fstat -- correct? -+ -+ -+PRE(sys_clone): get rid of references to vki_modify_ldt_t and the -+definition of it in vki-arm64-linux.h. Ditto for 32 bit arm. -+ -+ -+sigframe-arm64-linux.c: build_sigframe: references to nonexistent -+siguc->uc_mcontext.trap_no, siguc->uc_mcontext.error_code have been -+replaced by zero. Also in synth_ucontext. -+ -+ -+m_debugger.c: -+uregs.pstate = LibVEX_GuestARM64_get_nzcv(vex); /* is this correct? */ -+Is that remotely correct? -+ -+ -+host_arm64_defs.c: emit_ARM64INstr: -+ARM64in_VDfromX and ARM64in_VQfromXX: use simple top-half zeroing -+MOVs to vector registers instead of INS Vd.D[0], Xreg, to avoid false -+dependencies on the top half of the register. (Or at least check -+the semantics of INS Vd.D[0] to see if it zeroes out the top.) -+ -+ -+preferredVectorSubTypeFromSize: review perf effects and decide -+on a types-for-subparts policy -+ -+ -+fold_IRExpr_Unop: add a reduction rule for this -+1Sto64(CmpNEZ64( Or64(GET:I64(1192),GET:I64(1184)) )) -+vis 1Sto64(CmpNEZ64(x)) --> CmpwNEZ64(x) -+ -+ -+check insn selection for memcheck-only primops: -+Left64 CmpwNEZ64 V128to64 V128HIto64 1Sto64 CmpNEZ64 CmpNEZ32 -+widen_z_8_to_64 1Sto32 Left32 32HLto64 CmpwNEZ32 CmpNEZ8 -+ -+ -+isel: get rid of various cases where zero is put into a register -+and just use xzr instead. Especially for CmpNEZ64/32. And for -+writing zeroes into the CC thunk fields. -+ -+ -+/* Keep this list in sync with that in iselNext below */ -+/* Keep this list in sync with that for Ist_Exit above */ -+uh .. they are not in sync -+ -+ -+very stupid: -+imm64 x23, 0xFFFFFFFFFFFFFFA0 -+17 F4 9F D2 F7 FF BF F2 F7 FF DF F2 F7 FF FF F2 -+ -+ -+valgrind.h: fix VALGRIND_ALIGN_STACK/VALGRIND_RESTORE_STACK, -+also add CFI annotations -+ -+ -+could possibly bring r29 into use, which be useful as it is -+callee saved -+ -+ -+ubfm/sbfm etc: special case cases that are simple shifts, as iropt -+can't always simplify the general-case IR to a shift in such cases. -+ -+ -+LDP,STP (immediate, simm7) (FP&VEC) -+should zero out hi parts of dst registers in the LDP case -+ -+ -+DUP insns: use Iop_Dup8x16, Iop_Dup16x8, Iop_Dup32x4 -+rather than doing it "by hand" -+ -+ -+Any place where ZeroHI64ofV128 is used in conjunction with -+FP vector IROps: find a way to make sure that arithmetic on -+the upper half of the values is "harmless." -+ -+ -+math_MINMAXV: use real Iop_Cat{Odd,Even}Lanes ops rather than -+inline scalar code -+ -+ -+chainXDirect_ARM64: use direct jump forms when possible -Index: README.android -=================================================================== ---- README.android (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ README.android (.../trunk) (revision 13981) -@@ -13,6 +13,12 @@ - x86: - Android 4.0.3 running on android x86 emulator. - -+mips32: -+ Android 4.1.2 running on android mips emulator. -+ Android 4.2.2 running on android mips emulator. -+ Android 4.3 running on android mips emulator. -+ Android 4.0.4 running on BROADCOM bcm7425 -+ - On android-arm, GDBserver might insert breaks at wrong addresses. - Feedback on this welcome. - -@@ -26,6 +32,8 @@ - For the android emulator, the versions needed and how to - install them are described in README.android_emulator. - -+You can get android-ndk-r6 from -+http://dl.google.com/android/ndk/android-ndk-r6-linux-x86.tar.bz2 - Install it somewhere. Doesn't matter where. Then do this: - - -@@ -70,6 +78,10 @@ - export LD=$NDKROOT/toolchains/x86-4.4.3/prebuilt/linux-x86/bin/i686-android-linux-ld - export CC=$NDKROOT/toolchains/x86-4.4.3/prebuilt/linux-x86/bin/i686-android-linux-gcc - -+# For MIPS32 -+export AR=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-ar -+export LD=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-ld -+export CC=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-gcc - - # Do configuration stuff. Don't mess with the --prefix in the - # configure command below, even if you think it's wrong. -@@ -97,6 +109,13 @@ - --host=i686-android-linux --target=i686-android-linux \ - --with-tmpdir=/sdcard - -+# for MIPS32 -+CPPFLAGS="--sysroot=$NDKROOT/platforms/android-18/arch-mips -DANDROID_HARDWARE_$HWKIND" \ -+ CFLAGS="--sysroot=$NDKROOT/platforms/android-18/arch-mips" \ -+ ./configure --prefix=/data/local/Inst \ -+ --host=mipsel-linux-android --target=mipsel-linux-android \ -+ --with-tmpdir=/sdcard -+ - # At the end of the configure run, a few lines of details - # are printed. Make sure that you see these two lines: - # -@@ -108,6 +127,10 @@ - # Platform variant: android - # Primary -DVGPV string: -DVGPV_x86_linux_android=1 - # -+# For mips32: -+# Platform variant: android -+# Primary -DVGPV string: -DVGPV_mips32_linux_android=1 -+# - # If you see anything else at this point, something is wrong, and - # either the build will fail, or will succeed but you'll get something - # which won't work. -Index: README_DEVELOPERS_processes -=================================================================== ---- README_DEVELOPERS_processes (.../tags/VALGRIND_3_9_0) (revision 0) -+++ README_DEVELOPERS_processes (.../trunk) (revision 13981) -@@ -0,0 +1,94 @@ -+This file documents various "processes" that are used by Valgrind -+developers for development and release activities. -+This file contains one section for each process. -+A summary of each process is given here. Each process is described -+more in details afterwards. -+ -+ -+* Update of the NEWS file: NEWS describes fixed bugs and new features. -+ It is updated and committed together with the code fixing the bug/implementing -+ the feature. -+ -+* Major release production: -+ See docs/internals/release-HOWTO.txt (currently a bit out of date) -+ -+* Minor/correction release production: TBD -+ -+ -+Processes detailed descriptions: -+ -+Update of the NEWS file. -+======================== -+ The NEWS file gives for each release: -+ - the list of fixed bugs, -+ - a short description of each functional change, -+ - a short description of each technical change impacting the users. -+ -+ The update of the NEWS file should be committed together with the -+ code change (or as part of the last committed change) that fixes the -+ bug or implements the new feature/technical change. -+ The documentation (e.g. user manual) should also be committed as part of -+ the code change. -+ -+ Fixing a bug -+ ------------ -+ When fixing a bug, add a line in the 'FIXED BUGS' section of -+ the NEWS file. Keep the list of bugs sorted by bugzilla entry number. -+ -+ Once you have commit the change, update the bug status in bugzilla, -+ adding in the comment the revision number of the commit fixing the bug. -+ -+ If a bug is not entered in bugzilla (not encouraged), use "n-i-bz" -+ and add the bug line at the end of the bug list. -+ -+ The file docs/internals/X_Y_BUGSTATUS.txt (where X_Y is the last -+ major release e.g. 3_9) contains information/statuses for some bugs. -+ If a bug is fixed, remove the (possible) bug info from this file. -+ -+ Implementing a change -+ --------------------- -+ When implementing a functional or 'user impacting' technical change, -+ add a short description of the change in the relevant sub-section -+ (e.g. TOOL CHANGES, PLATFORM CHANGES, ...). -+ -+ -+ Some special cases: -+ ------------------- -+ Some bugs or changes only touch the VEX SVN repository, so it is not -+ possible to commit the NEWS change together with the code changes. -+ In such a case, first commit the VEX change. Then just after, commit -+ the NEWS change. In the bugzilla status, reference (at least) the Valgrind -+ revision number. -+ -+ Some changes or bug fixes are very big and might be implemented over -+ a significant period. In such a case, update the NEWS as part of the -+ final commit. -+ If relevant, you might already update the NEWS file as part of -+ earlier commits, using the word 'PARTIAL' to indicate that the change or -+ bug fix is not complete yet. -+ -+ Some bugs are reported more than once in bugzilla. -+ Also document in NEWS that such duplicated bugs have been fixed, using a line -+ such as: -+ 308333 == 307106 -+ to indicate that the bug 308333 is a duplicate of 307106, and was thus -+ fixed in the commit that fixed 307106. -+ Change also the status of the duplicated bug in bugzilla, -+ indicating in the comment the commit revision that fixed the 'master bug'. -+ -+ -+ -+Minor/correction release: -+========================= -+Describe here how to do changes and bug fixed in a minor (correction) release -+and how/when to merge the branch to the trunk. -+ -+Proposal to be discussed: -+When a bug is fixed on the branch, the NEWS file is updated on the branch -+(i.e. a 3.9.1 section is created if needed). -+ -+When often to merge the branch to trunk ? -+ after each fix ? -+ just after the correction release is produced ? -+ -+How is the branch merged to the trunk ? -Index: auxprogs/valgrind-di-server.c -=================================================================== ---- auxprogs/valgrind-di-server.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ auxprogs/valgrind-di-server.c (.../trunk) (revision 13981) -@@ -743,6 +743,8 @@ - fd = open((char*)filename, O_RDONLY); - if (fd == -1) { - res = mk_Frame_asciiz("FAIL", "OPEN: cannot open file"); -+ printf("(%d) SessionID %llu: open failed for \"%s\"\n", -+ conn_count, conn_state[conn_no].session_id, filename ); - ok = False; - } else { - assert(fd > 2); -Index: cachegrind/cg_arch.c -=================================================================== ---- cachegrind/cg_arch.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ cachegrind/cg_arch.c (.../trunk) (revision 13981) -@@ -367,6 +367,14 @@ - *D1c = (cache_t) { 16384, 4, 64 }; - *LLc = (cache_t) { 262144, 8, 64 }; - -+#elif defined(VGA_arm64) -+ -+ // Copy the 32-bit ARM version until such time as we have -+ // some real hardware to run on -+ *I1c = (cache_t) { 16384, 4, 64 }; -+ *D1c = (cache_t) { 16384, 4, 64 }; -+ *LLc = (cache_t) { 262144, 8, 64 }; -+ - #elif defined(VGA_s390x) - // - // Here is the cache data from older machine models: -Index: cachegrind/cg_branchpred.c -=================================================================== ---- cachegrind/cg_branchpred.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ cachegrind/cg_branchpred.c (.../trunk) (revision 13981) -@@ -44,12 +44,12 @@ - - /* How many bits at the bottom of an instruction address are - guaranteed to be zero? */ --#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm) \ -- || defined(VGA_mips32) || defined(VGA_mips64) -+#if defined(VGA_ppc32) || defined(VGA_ppc64) \ -+ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) - # define N_IADDR_LO_ZERO_BITS 2 - #elif defined(VGA_x86) || defined(VGA_amd64) - # define N_IADDR_LO_ZERO_BITS 0 --#elif defined(VGA_s390x) -+#elif defined(VGA_s390x) || defined(VGA_arm) - # define N_IADDR_LO_ZERO_BITS 1 - #else - # error "Unsupported architecture" -Index: callgrind/bbcc.c -=================================================================== ---- callgrind/bbcc.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ callgrind/bbcc.c (.../trunk) (revision 13981) -@@ -885,6 +885,10 @@ - } - - CLG_(current_state).bbcc = bbcc; -+ /* Even though this will be set in instrumented code directly before -+ * side exits, it needs to be set to 0 here in case an exception -+ * happens in first instructions of the BB */ -+ CLG_(current_state).jmps_passed = 0; - // needed for log_* handlers called in this BB - CLG_(bb_base) = bb->obj->offset + bb->offset; - CLG_(cost_base) = bbcc->cost; -Index: callgrind/callgrind_control.in -=================================================================== ---- callgrind/callgrind_control.in (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ callgrind/callgrind_control.in (.../trunk) (revision 13981) -@@ -27,7 +27,7 @@ - sub getCallgrindPids { - - @pids = (); -- open LIST, "vgdb -l|"; -+ open LIST, "vgdb $vgdbPrefixOption -l|"; - while() { - if (/^use --pid=(\d+) for \S*?valgrind\s+(.*?)\s*$/) { - $pid = $1; -@@ -78,6 +78,8 @@ - print " -z --zero Zero all event counters\n"; - print " -k --kill Kill\n"; - print " -i --instr=on|off Switch instrumentation state on/off\n"; -+ print "Uncommon options:\n"; -+ print " --vgdb-prefix= Only provide this if the same was given to Valgrind\n"; - print "\n"; - exit; - } -@@ -185,6 +187,16 @@ - # Main - # - -+# To find the list of active pids, we need to have -+# the --vgdb-prefix option if given. -+$vgdbPrefixOption = ""; -+foreach $arg (@ARGV) { -+ if ($arg =~ /^--vgdb-prefix=.*$/) { -+ $vgdbPrefixOption=$arg; -+ } -+ next; -+} -+ - getCallgrindPids; - - $requestEvents = 0; -@@ -192,6 +204,7 @@ - $switchInstr = 0; - $headerPrinted = 0; - $dumpHint = ""; -+ - $verbose = 0; - - %spids = (); -@@ -206,6 +219,10 @@ - elsif ($arg =~ /^--version$/) { - printVersion; - } -+ elsif ($arg =~ /^--vgdb-prefix=.*$/) { -+ # handled during the initial parsing. -+ next; -+ } - elsif ($arg =~ /^-v$/) { - $verbose++; - next; -@@ -346,7 +363,7 @@ - } else { - print "\n"; - } -- open RESULT, "vgdb --pid=$pid $vgdbCommand|"; -+ open RESULT, "vgdb $vgdbPrefixOption --pid=$pid $vgdbCommand|"; - - @tids = (); - $ctid = 0; -Index: callgrind/docs/cl-manual.xml -=================================================================== ---- callgrind/docs/cl-manual.xml (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ callgrind/docs/cl-manual.xml (.../trunk) (revision 13981) -@@ -1400,12 +1400,13 @@ - - - -- -+ - -- Specify the startup directory of an active Callgrind run. On some -- systems, active Callgrind runs can not be detected. To be able to -- control these, the failed auto-detection can be worked around by -- specifying the directory where a Callgrind run was started. -+ Specify the vgdb prefix to use by callgrind_control. -+ callgrind_control internally uses vgdb to find and control the active -+ Callgrind runs. If the option was used -+ for launching valgrind, then the same option must be given to -+ callgrind_control. - - - -Index: callgrind/global.h -=================================================================== ---- callgrind/global.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ callgrind/global.h (.../trunk) (revision 13981) -@@ -523,7 +523,8 @@ - Bool collect; - Context* cxt; - -- Int jmps_passed; /* number of conditional jumps passed in last BB */ -+ /* number of conditional jumps passed in last BB */ -+ Int jmps_passed; - BBCC* bbcc; /* last BB executed */ - BBCC* nonskipped; - -Index: callgrind/main.c -=================================================================== ---- callgrind/main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ callgrind/main.c (.../trunk) (revision 13981) -@@ -1243,9 +1243,10 @@ - /* Update global variable jmps_passed before the jump - * A correction is needed if VEX inverted the last jump condition - */ -+ UInt val = inverted ? cJumps+1 : cJumps; - addConstMemStoreStmt( clgs.sbOut, - (UWord) &CLG_(current_state).jmps_passed, -- inverted ? cJumps+1 : cJumps, hWordTy); -+ val, hWordTy); - cJumps++; - - break; -@@ -1289,10 +1290,12 @@ - /* At the end of the bb. Flush outstandings. */ - flushEvents( &clgs ); - -- /* Always update global variable jmps_passed at end of bb. -+ /* Update global variable jmps_passed at end of SB. -+ * As CLG_(current_state).jmps_passed is reset to 0 in setup_bbcc, -+ * this can be omitted if there is no conditional jump in this SB. - * A correction is needed if VEX inverted the last jump condition - */ -- { -+ if (cJumps>0) { - UInt jmps_passed = cJumps; - if (clgs.bb->cjmp_inverted) jmps_passed--; - addConstMemStoreStmt( clgs.sbOut, -@@ -1576,7 +1579,7 @@ - static Bool handle_gdb_monitor_command (ThreadId tid, const HChar *req) - { - HChar* wcmd; -- HChar s[VG_(strlen(req))]; /* copy for strtok_r */ -+ HChar s[VG_(strlen(req)) + 1]; /* copy for strtok_r */ - HChar *ssaveptr; - - VG_(strcpy) (s, req); -@@ -1807,7 +1810,79 @@ - VG_(umsg)("Mispred rate: %s (%s + %s )\n", buf1, buf2,buf3); - } - -+static -+void clg_print_stats(void) -+{ -+ int BB_lookups = -+ CLG_(stat).full_debug_BBs + -+ CLG_(stat).fn_name_debug_BBs + -+ CLG_(stat).file_line_debug_BBs + -+ CLG_(stat).no_debug_BBs; - -+ /* Hash table stats */ -+ VG_(message)(Vg_DebugMsg, "Distinct objects: %d\n", -+ CLG_(stat).distinct_objs); -+ VG_(message)(Vg_DebugMsg, "Distinct files: %d\n", -+ CLG_(stat).distinct_files); -+ VG_(message)(Vg_DebugMsg, "Distinct fns: %d\n", -+ CLG_(stat).distinct_fns); -+ VG_(message)(Vg_DebugMsg, "Distinct contexts:%d\n", -+ CLG_(stat).distinct_contexts); -+ VG_(message)(Vg_DebugMsg, "Distinct BBs: %d\n", -+ CLG_(stat).distinct_bbs); -+ VG_(message)(Vg_DebugMsg, "Cost entries: %d (Chunks %d)\n", -+ CLG_(costarray_entries), CLG_(costarray_chunks)); -+ VG_(message)(Vg_DebugMsg, "Distinct BBCCs: %d\n", -+ CLG_(stat).distinct_bbccs); -+ VG_(message)(Vg_DebugMsg, "Distinct JCCs: %d\n", -+ CLG_(stat).distinct_jccs); -+ VG_(message)(Vg_DebugMsg, "Distinct skips: %d\n", -+ CLG_(stat).distinct_skips); -+ VG_(message)(Vg_DebugMsg, "BB lookups: %d\n", -+ BB_lookups); -+ if (BB_lookups>0) { -+ VG_(message)(Vg_DebugMsg, "With full debug info:%3d%% (%d)\n", -+ CLG_(stat).full_debug_BBs * 100 / BB_lookups, -+ CLG_(stat).full_debug_BBs); -+ VG_(message)(Vg_DebugMsg, "With file/line debug info:%3d%% (%d)\n", -+ CLG_(stat).file_line_debug_BBs * 100 / BB_lookups, -+ CLG_(stat).file_line_debug_BBs); -+ VG_(message)(Vg_DebugMsg, "With fn name debug info:%3d%% (%d)\n", -+ CLG_(stat).fn_name_debug_BBs * 100 / BB_lookups, -+ CLG_(stat).fn_name_debug_BBs); -+ VG_(message)(Vg_DebugMsg, "With no debug info:%3d%% (%d)\n", -+ CLG_(stat).no_debug_BBs * 100 / BB_lookups, -+ CLG_(stat).no_debug_BBs); -+ } -+ VG_(message)(Vg_DebugMsg, "BBCC Clones: %d\n", -+ CLG_(stat).bbcc_clones); -+ VG_(message)(Vg_DebugMsg, "BBs Retranslated: %d\n", -+ CLG_(stat).bb_retranslations); -+ VG_(message)(Vg_DebugMsg, "Distinct instrs: %d\n", -+ CLG_(stat).distinct_instrs); -+ VG_(message)(Vg_DebugMsg, ""); -+ -+ VG_(message)(Vg_DebugMsg, "LRU Contxt Misses: %d\n", -+ CLG_(stat).cxt_lru_misses); -+ VG_(message)(Vg_DebugMsg, "LRU BBCC Misses: %d\n", -+ CLG_(stat).bbcc_lru_misses); -+ VG_(message)(Vg_DebugMsg, "LRU JCC Misses: %d\n", -+ CLG_(stat).jcc_lru_misses); -+ VG_(message)(Vg_DebugMsg, "BBs Executed: %llu\n", -+ CLG_(stat).bb_executions); -+ VG_(message)(Vg_DebugMsg, "Calls: %llu\n", -+ CLG_(stat).call_counter); -+ VG_(message)(Vg_DebugMsg, "CondJMP followed: %llu\n", -+ CLG_(stat).jcnd_counter); -+ VG_(message)(Vg_DebugMsg, "Boring JMPs: %llu\n", -+ CLG_(stat).jump_counter); -+ VG_(message)(Vg_DebugMsg, "Recursive calls: %llu\n", -+ CLG_(stat).rec_call_counter); -+ VG_(message)(Vg_DebugMsg, "Returns: %llu\n", -+ CLG_(stat).ret_counter); -+} -+ -+ - static - void finish(void) - { -@@ -1828,77 +1903,10 @@ - - if (VG_(clo_verbosity) == 0) return; - -- /* Hash table stats */ - if (VG_(clo_stats)) { -- int BB_lookups = -- CLG_(stat).full_debug_BBs + -- CLG_(stat).fn_name_debug_BBs + -- CLG_(stat).file_line_debug_BBs + -- CLG_(stat).no_debug_BBs; -- - VG_(message)(Vg_DebugMsg, "\n"); -- VG_(message)(Vg_DebugMsg, "Distinct objects: %d\n", -- CLG_(stat).distinct_objs); -- VG_(message)(Vg_DebugMsg, "Distinct files: %d\n", -- CLG_(stat).distinct_files); -- VG_(message)(Vg_DebugMsg, "Distinct fns: %d\n", -- CLG_(stat).distinct_fns); -- VG_(message)(Vg_DebugMsg, "Distinct contexts:%d\n", -- CLG_(stat).distinct_contexts); -- VG_(message)(Vg_DebugMsg, "Distinct BBs: %d\n", -- CLG_(stat).distinct_bbs); -- VG_(message)(Vg_DebugMsg, "Cost entries: %d (Chunks %d)\n", -- CLG_(costarray_entries), CLG_(costarray_chunks)); -- VG_(message)(Vg_DebugMsg, "Distinct BBCCs: %d\n", -- CLG_(stat).distinct_bbccs); -- VG_(message)(Vg_DebugMsg, "Distinct JCCs: %d\n", -- CLG_(stat).distinct_jccs); -- VG_(message)(Vg_DebugMsg, "Distinct skips: %d\n", -- CLG_(stat).distinct_skips); -- VG_(message)(Vg_DebugMsg, "BB lookups: %d\n", -- BB_lookups); -- if (BB_lookups>0) { -- VG_(message)(Vg_DebugMsg, "With full debug info:%3d%% (%d)\n", -- CLG_(stat).full_debug_BBs * 100 / BB_lookups, -- CLG_(stat).full_debug_BBs); -- VG_(message)(Vg_DebugMsg, "With file/line debug info:%3d%% (%d)\n", -- CLG_(stat).file_line_debug_BBs * 100 / BB_lookups, -- CLG_(stat).file_line_debug_BBs); -- VG_(message)(Vg_DebugMsg, "With fn name debug info:%3d%% (%d)\n", -- CLG_(stat).fn_name_debug_BBs * 100 / BB_lookups, -- CLG_(stat).fn_name_debug_BBs); -- VG_(message)(Vg_DebugMsg, "With no debug info:%3d%% (%d)\n", -- CLG_(stat).no_debug_BBs * 100 / BB_lookups, -- CLG_(stat).no_debug_BBs); -- } -- VG_(message)(Vg_DebugMsg, "BBCC Clones: %d\n", -- CLG_(stat).bbcc_clones); -- VG_(message)(Vg_DebugMsg, "BBs Retranslated: %d\n", -- CLG_(stat).bb_retranslations); -- VG_(message)(Vg_DebugMsg, "Distinct instrs: %d\n", -- CLG_(stat).distinct_instrs); -- VG_(message)(Vg_DebugMsg, ""); -- -- VG_(message)(Vg_DebugMsg, "LRU Contxt Misses: %d\n", -- CLG_(stat).cxt_lru_misses); -- VG_(message)(Vg_DebugMsg, "LRU BBCC Misses: %d\n", -- CLG_(stat).bbcc_lru_misses); -- VG_(message)(Vg_DebugMsg, "LRU JCC Misses: %d\n", -- CLG_(stat).jcc_lru_misses); -- VG_(message)(Vg_DebugMsg, "BBs Executed: %llu\n", -- CLG_(stat).bb_executions); -- VG_(message)(Vg_DebugMsg, "Calls: %llu\n", -- CLG_(stat).call_counter); -- VG_(message)(Vg_DebugMsg, "CondJMP followed: %llu\n", -- CLG_(stat).jcnd_counter); -- VG_(message)(Vg_DebugMsg, "Boring JMPs: %llu\n", -- CLG_(stat).jump_counter); -- VG_(message)(Vg_DebugMsg, "Recursive calls: %llu\n", -- CLG_(stat).rec_call_counter); -- VG_(message)(Vg_DebugMsg, "Returns: %llu\n", -- CLG_(stat).ret_counter); -- -- VG_(message)(Vg_DebugMsg, ""); -+ clg_print_stats(); -+ VG_(message)(Vg_DebugMsg, "\n"); - } - - CLG_(sprint_eventmapping)(buf, CLG_(dumpmap)); -@@ -2016,7 +2024,9 @@ - - if (VG_(clo_verbosity > 0)) { - VG_(message)(Vg_UserMsg, -- "For interactive control, run 'callgrind_control -h'.\n"); -+ "For interactive control, run 'callgrind_control%s%s -h'.\n", -+ (VG_(arg_vgdb_prefix) ? " " : ""), -+ (VG_(arg_vgdb_prefix) ? VG_(arg_vgdb_prefix) : "")); - } - } - -@@ -2048,6 +2058,7 @@ - CLG_(print_debug_usage)); - - VG_(needs_client_requests)(CLG_(handle_client_request)); -+ VG_(needs_print_stats) (clg_print_stats); - VG_(needs_syscall_wrapper)(CLG_(pre_syscalltime), - CLG_(post_syscalltime)); - -Index: configure.ac -=================================================================== ---- configure.ac (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ configure.ac (.../trunk) (revision 13981) -@@ -8,7 +8,7 @@ - ##------------------------------------------------------------## - - # Process this file with autoconf to produce a configure script. --AC_INIT([Valgrind],[3.9.0],[valgrind-users@lists.sourceforge.net]) -+AC_INIT([Valgrind],[3.10.0.SVN],[valgrind-users@lists.sourceforge.net]) - AC_CONFIG_SRCDIR(coregrind/m_main.c) - AC_CONFIG_HEADERS([config.h]) - AM_INIT_AUTOMAKE([foreign subdir-objects]) -@@ -195,6 +195,11 @@ - ARCH_MAX="arm" - ;; - -+ aarch64*) -+ AC_MSG_RESULT([ok (${host_cpu})]) -+ ARCH_MAX="arm64" -+ ;; -+ - mips) - AC_MSG_RESULT([ok (${host_cpu})]) - ARCH_MAX="mips32" -@@ -559,6 +564,35 @@ - valt_load_address_sec_inner="0xUNSET" - AC_MSG_RESULT([ok (${host_cpu}-${host_os})]) - ;; -+ arm64-linux) -+ valt_load_address_sec_norml="0xUNSET" -+ valt_load_address_sec_inner="0xUNSET" -+ if test x$vg_cv_only64bit = xyes; then -+ VGCONF_ARCH_PRI="arm64" -+ VGCONF_ARCH_SEC="" -+ VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX" -+ VGCONF_PLATFORM_SEC_CAPS="" -+ valt_load_address_pri_norml="0x38000000" -+ valt_load_address_pri_inner="0x28000000" -+ elif test x$vg_cv_only32bit = xyes; then -+ VGCONF_ARCH_PRI="arm" -+ VGCONF_ARCH_SEC="" -+ VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX" -+ VGCONF_PLATFORM_SEC_CAPS="" -+ valt_load_address_pri_norml="0x38000000" -+ valt_load_address_pri_inner="0x28000000" -+ else -+ VGCONF_ARCH_PRI="arm64" -+ VGCONF_ARCH_SEC="arm" -+ VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX" -+ VGCONF_PLATFORM_SEC_CAPS="ARM_LINUX" -+ valt_load_address_pri_norml="0x38000000" -+ valt_load_address_pri_inner="0x28000000" -+ valt_load_address_sec_norml="0x38000000" -+ valt_load_address_sec_inner="0x28000000" -+ fi -+ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) -+ ;; - s390x-linux) - VGCONF_ARCH_PRI="s390x" - VGCONF_ARCH_SEC="" -@@ -624,7 +658,10 @@ - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC64, - test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM, -- test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX ) -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ -+ -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX ) -+AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM64, -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_S390X, - test x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_MIPS32, -@@ -645,7 +682,10 @@ - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX) - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM_LINUX, -- test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX) -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ -+ -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX) -+AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM64_LINUX, -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX) - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_S390X_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xS390X_LINUX) -@@ -653,7 +693,6 @@ - test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX) - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX) -- - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_DARWIN, - test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xX86_DARWIN) -@@ -670,6 +709,7 @@ - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ -+ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX) -@@ -731,7 +771,7 @@ - - if test "$psize" = "0"; then - psizer=`getconf PAGESIZE` -- let "psize=${psizer}/1024" -+ psize=$((${psizer}/1024)) - fi - - if test "$psize" = "4"; then -@@ -918,6 +958,13 @@ - DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}" - DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}" - ;; -+ 2.19) -+ AC_MSG_RESULT(2.19 family) -+ AC_DEFINE([GLIBC_2_19], 1, [Define to 1 if you're using glibc 2.19.x]) -+ DEFAULT_SUPP="glibc-2.X.supp ${DEFAULT_SUPP}" -+ DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}" -+ DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}" -+ ;; - darwin) - AC_MSG_RESULT(Darwin) - AC_DEFINE([DARWIN_LIBC], 1, [Define to 1 if you're using Darwin]) -@@ -931,8 +978,8 @@ - - *) - AC_MSG_RESULT([unsupported version ${GLIBC_VERSION}]) -- AC_MSG_ERROR([Valgrind requires glibc version 2.2 - 2.17]) -- AC_MSG_ERROR([or Darwin libc]) -+ AC_MSG_ERROR([Valgrind requires glibc version 2.2 - 2.19]) -+ AC_MSG_ERROR([or Darwin or Bionic libc]) - ;; - esac - -@@ -957,9 +1004,9 @@ - # Normally the PLAT = (ARCH, OS) characterisation of the platform is enough. - # But there are times where we need a bit more control. The motivating - # and currently only case is Android: this is almost identical to --# {x86,arm}-linux, but not quite. So this introduces the concept of platform --# variant tags, which get passed in the compile as -DVGPV___ --# along with the main -DVGP__ definition. -+# {x86,arm,mips}-linux, but not quite. So this introduces the concept of -+# platform variant tags, which get passed in the compile as -+# -DVGPV___ along with the main -DVGP__ definition. - # - # In almost all cases, the bit is "vanilla". But for Android - # it is "android" instead. -@@ -1450,6 +1497,86 @@ - AC_SUBST(FLAG_M64) - - -+# does this compiler support -march=mips32 (mips32 default) ? -+AC_MSG_CHECKING([if gcc accepts -march=mips32]) -+ -+safe_CFLAGS=$CFLAGS -+CFLAGS="$CFLAGS -march=mips32" -+ -+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ -+ return 0; -+]])], [ -+FLAG_MIPS32="-march=mips32" -+AC_MSG_RESULT([yes]) -+], [ -+FLAG_MIPS32="" -+AC_MSG_RESULT([no]) -+]) -+CFLAGS=$safe_CFLAGS -+ -+AC_SUBST(FLAG_MIPS32) -+ -+ -+# does this compiler support -march=mips64 (mips64 default) ? -+AC_MSG_CHECKING([if gcc accepts -march=mips64]) -+ -+safe_CFLAGS=$CFLAGS -+CFLAGS="$CFLAGS -march=mips64" -+ -+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ -+ return 0; -+]])], [ -+FLAG_MIPS64="-march=mips64" -+AC_MSG_RESULT([yes]) -+], [ -+FLAG_MIPS64="" -+AC_MSG_RESULT([no]) -+]) -+CFLAGS=$safe_CFLAGS -+ -+AC_SUBST(FLAG_MIPS64) -+ -+ -+# does this compiler support -march=octeon (Cavium OCTEON I Specific) ? -+AC_MSG_CHECKING([if gcc accepts -march=octeon]) -+ -+safe_CFLAGS=$CFLAGS -+CFLAGS="$CFLAGS -march=octeon" -+ -+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ -+ return 0; -+]])], [ -+FLAG_OCTEON="-march=octeon" -+AC_MSG_RESULT([yes]) -+], [ -+FLAG_OCTEON="" -+AC_MSG_RESULT([no]) -+]) -+CFLAGS=$safe_CFLAGS -+ -+AC_SUBST(FLAG_OCTEON) -+ -+ -+# does this compiler support -march=octeon2 (Cavium OCTEON II Specific) ? -+AC_MSG_CHECKING([if gcc accepts -march=octeon2]) -+ -+safe_CFLAGS=$CFLAGS -+CFLAGS="$CFLAGS -march=octeon2" -+ -+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ -+ return 0; -+]])], [ -+FLAG_OCTEON2="-march=octeon2" -+AC_MSG_RESULT([yes]) -+], [ -+FLAG_OCTEON2="" -+AC_MSG_RESULT([no]) -+]) -+CFLAGS=$safe_CFLAGS -+ -+AC_SUBST(FLAG_OCTEON2) -+ -+ - # does this compiler support -mmmx ? - AC_MSG_CHECKING([if gcc accepts -mmmx]) - -@@ -1834,7 +1961,7 @@ - # (Pedantically if the linker is gold then -Ttext is fine, but newer - # gold versions also support -Ttext-segment. So just assume that unless - # we can use -Ttext-segment we need to strip the build-id NOTEs. --if test "x${linker_using_t_text}" == "xyes"; then -+if test "x${linker_using_t_text}" = "xyes"; then - AC_MSG_NOTICE([ld -Ttext used, need to strip build-id NOTEs.]) - # does the linker support -Wl,--build-id=none ? Note, it's - # important that we test indirectly via whichever C compiler -@@ -2195,6 +2322,27 @@ - AM_CONDITIONAL(BUILD_FMA_TESTS, test x$ac_have_as_fma = xyes) - - -+# does the amd64 assembler understand MPX instructions? -+# Note, this doesn't generate a C-level symbol. It generates a -+# automake-level symbol (BUILD_MPX_TESTS), used in test Makefile.am's -+AC_MSG_CHECKING([if amd64 assembler knows the MPX instructions]) -+ -+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ -+ asm ("bndmov %bnd0,(%rsp)") -+]])], [ -+ac_have_as_mpx=yes -+AC_MSG_RESULT([yes]) -+], [ -+ac_have_as_mpx=no -+AC_MSG_RESULT([no]) -+]) -+ -+AM_CONDITIONAL(BUILD_MPX_TESTS, test x$ac_have_as_mpx = xyes) -+ -+ -+# Does the C compiler support the "ifunc" attribute -+# Note, this doesn't generate a C-level symbol. It generates a -+# automake-level symbol (BUILD_IFUNC_TESTS), used in test Makefile.am's - # does the x86/amd64 assembler understand MOVBE? - # Note, this doesn't generate a C-level symbol. It generates a - # automake-level symbol (BUILD_MOVBE_TESTS), used in test Makefile.am's -@@ -2406,6 +2554,7 @@ - mflag_primary=$FLAG_M32 - elif test x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ -+ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX ; then - mflag_primary=$FLAG_M64 - elif test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN ; then -@@ -2868,6 +3017,7 @@ - exp-bbv/tests/arm-linux/Makefile - exp-dhat/Makefile - exp-dhat/tests/Makefile -+ shared/Makefile - ]) - AC_CONFIG_FILES([coregrind/link_tool_exe_linux], - [chmod +x coregrind/link_tool_exe_linux]) -Index: coregrind/Makefile.am -=================================================================== ---- coregrind/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/Makefile.am (.../trunk) (revision 13981) -@@ -59,7 +59,22 @@ - valgrind_LDFLAGS += -Wl,-z,noexecstack - endif - -+ - vgdb_SOURCES = vgdb.c -+if VGCONF_OS_IS_LINUX -+if VGCONF_PLATVARIANT_IS_ANDROID -+vgdb_SOURCES += vgdb-invoker-none.c -+else -+vgdb_SOURCES += vgdb-invoker-ptrace.c -+endif -+endif -+if VGCONF_OS_IS_DARWIN -+# Some darwin specific stuff is needed as ptrace is not -+# fully supported on MacOS. Till we find someone courageous -+# having access to Darwin, 'none' implementation is used. -+vgdb_SOURCES += vgdb-invoker-none.c -+endif -+ - vgdb_CPPFLAGS = $(AM_CPPFLAGS_PRI) - vgdb_CFLAGS = $(AM_CFLAGS_PRI) - vgdb_CCASFLAGS = $(AM_CCASFLAGS_PRI) -@@ -136,6 +151,7 @@ - #---------------------------------------------------------------------------- - - noinst_HEADERS = \ -+ pub_core_addrinfo.h \ - pub_core_aspacehl.h \ - pub_core_aspacemgr.h \ - pub_core_basics.h \ -@@ -169,6 +185,7 @@ - pub_core_mallocfree.h \ - pub_core_options.h \ - pub_core_oset.h \ -+ pub_core_rangemap.h \ - pub_core_redir.h \ - pub_core_poolalloc.h \ - pub_core_replacemalloc.h\ -@@ -231,8 +248,9 @@ - m_syswrap/priv_syswrap-linux-variants.h \ - m_syswrap/priv_syswrap-darwin.h \ - m_syswrap/priv_syswrap-main.h \ -- m_syswrap/priv_syswrap-xen.h \ -- m_ume/priv_ume.h -+ m_syswrap/priv_syswrap-xen.h \ -+ m_ume/priv_ume.h \ -+ vgdb.h - - #---------------------------------------------------------------------------- - # libcoregrind-.a -@@ -247,6 +265,7 @@ - endif - - COREGRIND_SOURCES_COMMON = \ -+ m_addrinfo.c \ - m_cache.c \ - m_commandline.c \ - m_clientstate.c \ -@@ -269,6 +288,7 @@ - m_mallocfree.c \ - m_options.c \ - m_oset.c \ -+ m_rangemap.c \ - m_redir.c \ - m_sbprofile.c \ - m_seqmatch.c \ -@@ -314,6 +334,7 @@ - m_dispatch/dispatch-ppc32-linux.S \ - m_dispatch/dispatch-ppc64-linux.S \ - m_dispatch/dispatch-arm-linux.S \ -+ m_dispatch/dispatch-arm64-linux.S \ - m_dispatch/dispatch-s390x-linux.S \ - m_dispatch/dispatch-mips32-linux.S \ - m_dispatch/dispatch-mips64-linux.S \ -@@ -330,6 +351,7 @@ - m_gdbserver/valgrind-low-x86.c \ - m_gdbserver/valgrind-low-amd64.c \ - m_gdbserver/valgrind-low-arm.c \ -+ m_gdbserver/valgrind-low-arm64.c \ - m_gdbserver/valgrind-low-ppc32.c \ - m_gdbserver/valgrind-low-ppc64.c \ - m_gdbserver/valgrind-low-s390x.c \ -@@ -353,6 +375,7 @@ - m_sigframe/sigframe-ppc32-linux.c \ - m_sigframe/sigframe-ppc64-linux.c \ - m_sigframe/sigframe-arm-linux.c \ -+ m_sigframe/sigframe-arm64-linux.c \ - m_sigframe/sigframe-s390x-linux.c \ - m_sigframe/sigframe-mips32-linux.c \ - m_sigframe/sigframe-mips64-linux.c \ -@@ -363,6 +386,7 @@ - m_syswrap/syscall-ppc32-linux.S \ - m_syswrap/syscall-ppc64-linux.S \ - m_syswrap/syscall-arm-linux.S \ -+ m_syswrap/syscall-arm64-linux.S \ - m_syswrap/syscall-s390x-linux.S \ - m_syswrap/syscall-mips32-linux.S \ - m_syswrap/syscall-mips64-linux.S \ -@@ -378,6 +402,7 @@ - m_syswrap/syswrap-ppc32-linux.c \ - m_syswrap/syswrap-ppc64-linux.c \ - m_syswrap/syswrap-arm-linux.c \ -+ m_syswrap/syswrap-arm64-linux.c \ - m_syswrap/syswrap-s390x-linux.c \ - m_syswrap/syswrap-mips32-linux.c \ - m_syswrap/syswrap-mips64-linux.c \ -@@ -602,6 +627,8 @@ - - install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS - -+uninstall-local: uninstall-noinst_PROGRAMS uninstall-noinst_DSYMS -+ - #---------------------------------------------------------------------------- - # Darwin linker kludges - #---------------------------------------------------------------------------- -@@ -610,7 +637,7 @@ - - BUILT_SOURCES += fixup_macho_loadcmds - fixup_macho_loadcmds: fixup_macho_loadcmds.c -- $(CC) -g -Wall -o fixup_macho_loadcmds fixup_macho_loadcmds.c -+ $(CC) -g -Wall -o $@ $< - - CLEANFILES += fixup_macho_loadcmds - -Index: coregrind/launcher-linux.c -=================================================================== ---- coregrind/launcher-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/launcher-linux.c (.../trunk) (revision 13981) -@@ -57,6 +57,10 @@ - #define EM_X86_64 62 // elf.h doesn't define this on some older systems - #endif - -+#ifndef EM_AARCH64 -+#define EM_AARCH64 183 // ditto -+#endif -+ - /* Report fatal errors */ - __attribute__((noreturn)) - static void barf ( const char *format, ... ) -@@ -220,9 +224,15 @@ - (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || - ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { - platform = "mips64-linux"; -+ } else if (ehdr->e_machine == EM_AARCH64 && -+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || -+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { -+ platform = "arm64-linux"; - } - } else if (header[EI_DATA] == ELFDATA2MSB) { --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) \ -+ && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - if (ehdr->e_machine == EM_PPC64 && - (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || - ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { -@@ -307,12 +317,13 @@ - target, because on most ppc64-linux setups, the basic /bin, - /usr/bin, etc, stuff is built in 32-bit mode, not 64-bit - mode. */ -- if ((0==strcmp(VG_PLATFORM,"x86-linux")) || -- (0==strcmp(VG_PLATFORM,"amd64-linux")) || -- (0==strcmp(VG_PLATFORM,"ppc32-linux")) || -- (0==strcmp(VG_PLATFORM,"ppc64-linux")) || -- (0==strcmp(VG_PLATFORM,"arm-linux")) || -- (0==strcmp(VG_PLATFORM,"s390x-linux")) || -+ if ((0==strcmp(VG_PLATFORM,"x86-linux")) || -+ (0==strcmp(VG_PLATFORM,"amd64-linux")) || -+ (0==strcmp(VG_PLATFORM,"ppc32-linux")) || -+ (0==strcmp(VG_PLATFORM,"ppc64-linux")) || -+ (0==strcmp(VG_PLATFORM,"arm-linux")) || -+ (0==strcmp(VG_PLATFORM,"arm64-linux")) || -+ (0==strcmp(VG_PLATFORM,"s390x-linux")) || - (0==strcmp(VG_PLATFORM,"mips32-linux")) || - (0==strcmp(VG_PLATFORM,"mips64-linux"))) - default_platform = VG_PLATFORM; -Index: coregrind/m_addrinfo.c -=================================================================== ---- coregrind/m_addrinfo.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/m_addrinfo.c (.../trunk) (revision 13981) -@@ -0,0 +1,354 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Obtaining information about an address. ---*/ -+/*--- m_addrinfo.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2008-2013 OpenWorks Ltd -+ info@open-works.co.uk -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "pub_core_basics.h" -+#include "pub_core_libcassert.h" -+#include "pub_core_libcbase.h" -+#include "pub_core_libcprint.h" -+#include "pub_core_xarray.h" -+#include "pub_core_debuginfo.h" -+#include "pub_core_execontext.h" -+#include "pub_core_addrinfo.h" -+#include "pub_core_mallocfree.h" -+#include "pub_core_machine.h" -+#include "pub_core_options.h" -+ -+void VG_(describe_addr) ( Addr a, /*OUT*/AddrInfo* ai ) -+{ -+ ThreadId tid; -+ Addr stack_min, stack_max; -+ VgSectKind sect; -+ -+ /* -- Perhaps the variable type/location data describes it? -- */ -+ ai->Addr.Variable.descr1 -+ = VG_(newXA)( VG_(malloc), "mc.da.descr1", -+ VG_(free), sizeof(HChar) ); -+ ai->Addr.Variable.descr2 -+ = VG_(newXA)( VG_(malloc), "mc.da.descr2", -+ VG_(free), sizeof(HChar) ); -+ -+ (void) VG_(get_data_description)( ai->Addr.Variable.descr1, -+ ai->Addr.Variable.descr2, a ); -+ /* If there's nothing in descr1/2, free them. Why is it safe to to -+ VG_(indexXA) at zero here? Because VG_(get_data_description) -+ guarantees to zero terminate descr1/2 regardless of the outcome -+ of the call. So there's always at least one element in each XA -+ after the call. -+ */ -+ if (0 == VG_(strlen)( VG_(indexXA)( ai->Addr.Variable.descr1, 0 ))) { -+ VG_(deleteXA)( ai->Addr.Variable.descr1 ); -+ ai->Addr.Variable.descr1 = NULL; -+ } -+ if (0 == VG_(strlen)( VG_(indexXA)( ai->Addr.Variable.descr2, 0 ))) { -+ VG_(deleteXA)( ai->Addr.Variable.descr2 ); -+ ai->Addr.Variable.descr2 = NULL; -+ } -+ /* Assume (assert) that VG_(get_data_description) fills in descr1 -+ before it fills in descr2 */ -+ if (ai->Addr.Variable.descr1 == NULL) -+ vg_assert(ai->Addr.Variable.descr2 == NULL); -+ /* So did we get lucky? */ -+ if (ai->Addr.Variable.descr1 != NULL) { -+ ai->tag = Addr_Variable; -+ return; -+ } -+ /* -- Have a look at the low level data symbols - perhaps it's in -+ there. -- */ -+ VG_(memset)( &ai->Addr.DataSym.name, -+ 0, sizeof(ai->Addr.DataSym.name)); -+ if (VG_(get_datasym_and_offset)( -+ a, &ai->Addr.DataSym.name[0], -+ sizeof(ai->Addr.DataSym.name)-1, -+ &ai->Addr.DataSym.offset )) { -+ ai->tag = Addr_DataSym; -+ vg_assert( ai->Addr.DataSym.name -+ [ sizeof(ai->Addr.DataSym.name)-1 ] == 0); -+ return; -+ } -+ /* -- Perhaps it's on a thread's stack? -- */ -+ VG_(thread_stack_reset_iter)(&tid); -+ while ( VG_(thread_stack_next)(&tid, &stack_min, &stack_max) ) { -+ if (stack_min - VG_STACK_REDZONE_SZB <= a && a <= stack_max) { -+ ai->tag = Addr_Stack; -+ ai->Addr.Stack.tid = tid; -+ return; -+ } -+ } -+ -+ /* -- Maybe it is in one of the m_mallocfree.c arenas. -- */ -+ { -+ AddrArenaInfo aai; -+ VG_(describe_arena_addr) ( a, &aai ); -+ if (aai.name != NULL) { -+ ai->tag = Addr_Block; -+ if (aai.aid == VG_AR_CLIENT) -+ ai->Addr.Block.block_kind -+ = aai.free ? Block_ClientArenaFree : Block_ClientArenaMallocd; -+ else -+ ai->Addr.Block.block_kind -+ = aai.free -+ ? Block_ValgrindArenaFree : Block_ValgrindArenaMallocd; -+ ai->Addr.Block.block_desc = aai.name; -+ ai->Addr.Block.block_szB = aai.block_szB; -+ ai->Addr.Block.rwoffset = aai.rwoffset; -+ ai->Addr.Block.allocated_at = VG_(null_ExeContext)(); -+ ai->Addr.Block.freed_at = VG_(null_ExeContext)(); -+ return; -+ } -+ } -+ -+ /* -- last ditch attempt at classification -- */ -+ vg_assert( sizeof(ai->Addr.SectKind.objname) > 4 ); -+ VG_(memset)( &ai->Addr.SectKind.objname, -+ 0, sizeof(ai->Addr.SectKind.objname)); -+ VG_(strcpy)( ai->Addr.SectKind.objname, "???" ); -+ sect = VG_(DebugInfo_sect_kind)( &ai->Addr.SectKind.objname[0], -+ sizeof(ai->Addr.SectKind.objname)-1, a); -+ if (sect != Vg_SectUnknown) { -+ ai->tag = Addr_SectKind; -+ ai->Addr.SectKind.kind = sect; -+ vg_assert( ai->Addr.SectKind.objname -+ [ sizeof(ai->Addr.SectKind.objname)-1 ] == 0); -+ return; -+ } -+ /* -- Clueless ... -- */ -+ ai->tag = Addr_Unknown; -+ return; -+} -+ -+void VG_(clear_addrinfo) ( AddrInfo* ai) -+{ -+ switch (ai->tag) { -+ case Addr_Unknown: -+ break; -+ -+ case Addr_Stack: -+ break; -+ -+ case Addr_Block: -+ break; -+ -+ case Addr_DataSym: -+ break; -+ -+ case Addr_Variable: -+ if (ai->Addr.Variable.descr1 != NULL) { -+ VG_(deleteXA)( ai->Addr.Variable.descr1 ); -+ ai->Addr.Variable.descr1 = NULL; -+ } -+ if (ai->Addr.Variable.descr2 != NULL) { -+ VG_(deleteXA)( ai->Addr.Variable.descr2 ); -+ ai->Addr.Variable.descr2 = NULL; -+ } -+ break; -+ -+ case Addr_SectKind: -+ break; -+ -+ default: -+ VG_(core_panic)("VG_(clear_addrinfo)"); -+ } -+ -+ ai->tag = Addr_Undescribed; -+} -+ -+static Bool is_arena_BlockKind(BlockKind bk) -+{ -+ switch (bk) { -+ case Block_Mallocd: -+ case Block_Freed: -+ case Block_MempoolChunk: -+ case Block_UserG: return False; -+ -+ case Block_ClientArenaMallocd: -+ case Block_ClientArenaFree: -+ case Block_ValgrindArenaMallocd: -+ case Block_ValgrindArenaFree: return True; -+ -+ default: vg_assert (0); -+ } -+} -+ -+static void pp_addrinfo_WRK ( Addr a, AddrInfo* ai, Bool mc, Bool maybe_gcc ) -+{ -+ const HChar* xpre = VG_(clo_xml) ? " " : " "; -+ const HChar* xpost = VG_(clo_xml) ? "" : ""; -+ -+ vg_assert (!maybe_gcc || mc); // maybe_gcc can only be given in mc mode. -+ -+ switch (ai->tag) { -+ case Addr_Unknown: -+ if (maybe_gcc) { -+ VG_(emit)( "%sAddress 0x%llx is just below the stack ptr. " -+ "To suppress, use: --workaround-gcc296-bugs=yes%s\n", -+ xpre, (ULong)a, xpost ); -+ } else { -+ VG_(emit)( "%sAddress 0x%llx " -+ "is not stack'd, malloc'd or %s%s\n", -+ xpre, -+ (ULong)a, -+ mc ? "(recently) free'd" : "on a free list", -+ xpost ); -+ } -+ break; -+ -+ case Addr_Stack: -+ VG_(emit)( "%sAddress 0x%llx is on thread %d's stack%s\n", -+ xpre, (ULong)a, ai->Addr.Stack.tid, xpost ); -+ break; -+ -+ case Addr_Block: { -+ SizeT block_szB = ai->Addr.Block.block_szB; -+ PtrdiffT rwoffset = ai->Addr.Block.rwoffset; -+ SizeT delta; -+ const HChar* relative; -+ -+ if (rwoffset < 0) { -+ delta = (SizeT)(-rwoffset); -+ relative = "before"; -+ } else if (rwoffset >= block_szB) { -+ delta = rwoffset - block_szB; -+ relative = "after"; -+ } else { -+ delta = rwoffset; -+ relative = "inside"; -+ } -+ if (is_arena_BlockKind (ai->Addr.Block.block_kind)) -+ VG_(emit)( -+ "%sAddress 0x%lx is %'lu bytes %s a%s block of size %'lu" -+ " in arena \"%s\"%s\n", -+ xpre, -+ a, delta, -+ relative, -+ ai->Addr.Block.block_kind==Block_ClientArenaMallocd -+ || ai->Addr.Block.block_kind==Block_ValgrindArenaMallocd -+ ? "" : "n unallocated", -+ block_szB, -+ ai->Addr.Block.block_desc, // arena name -+ xpost -+ ); -+ else -+ VG_(emit)( -+ "%sAddress 0x%lx is %'lu bytes %s a %s of size %'lu %s%s\n", -+ xpre, -+ a, delta, -+ relative, -+ ai->Addr.Block.block_desc, -+ block_szB, -+ ai->Addr.Block.block_kind==Block_Mallocd ? "alloc'd" -+ : ai->Addr.Block.block_kind==Block_Freed ? "free'd" -+ : "client-defined", -+ xpost -+ ); -+ if (ai->Addr.Block.block_kind==Block_Mallocd) { -+ VG_(pp_ExeContext)(ai->Addr.Block.allocated_at); -+ tl_assert (ai->Addr.Block.freed_at == VG_(null_ExeContext)()); -+ } -+ else if (ai->Addr.Block.block_kind==Block_Freed) { -+ VG_(pp_ExeContext)(ai->Addr.Block.freed_at); -+ if (ai->Addr.Block.allocated_at != VG_(null_ExeContext)()) { -+ VG_(emit)( -+ "%s block was alloc'd at%s\n", -+ xpre, -+ xpost -+ ); -+ VG_(pp_ExeContext)(ai->Addr.Block.allocated_at); -+ } -+ } -+ else if (ai->Addr.Block.block_kind==Block_MempoolChunk -+ || ai->Addr.Block.block_kind==Block_UserG) { -+ // client-defined -+ VG_(pp_ExeContext)(ai->Addr.Block.allocated_at); -+ tl_assert (ai->Addr.Block.freed_at == VG_(null_ExeContext)()); -+ /* Nb: cannot have a freed_at, as a freed client-defined block -+ has a Block_Freed block_kind. */ -+ } else { -+ // Client or Valgrind arena. At least currently, we never -+ // have stacktraces for these. -+ tl_assert (ai->Addr.Block.allocated_at == VG_(null_ExeContext)()); -+ tl_assert (ai->Addr.Block.freed_at == VG_(null_ExeContext)()); -+ } -+ -+ break; -+ } -+ -+ case Addr_DataSym: -+ VG_(emit)( "%sAddress 0x%llx is %llu bytes " -+ "inside data symbol \"%pS\"%s\n", -+ xpre, -+ (ULong)a, -+ (ULong)ai->Addr.DataSym.offset, -+ ai->Addr.DataSym.name, -+ xpost ); -+ break; -+ -+ case Addr_Variable: -+ /* Note, no need for XML tags here, because descr1/2 will -+ already have or s on them, in XML -+ mode. */ -+ if (ai->Addr.Variable.descr1) -+ VG_(emit)( "%s%s\n", -+ VG_(clo_xml) ? " " : " ", -+ (HChar*)VG_(indexXA)(ai->Addr.Variable.descr1, 0) ); -+ if (ai->Addr.Variable.descr2) -+ VG_(emit)( "%s%s\n", -+ VG_(clo_xml) ? " " : " ", -+ (HChar*)VG_(indexXA)(ai->Addr.Variable.descr2, 0) ); -+ break; -+ -+ case Addr_SectKind: -+ VG_(emit)( "%sAddress 0x%llx is in the %pS segment of %pS%s\n", -+ xpre, -+ (ULong)a, -+ VG_(pp_SectKind)(ai->Addr.SectKind.kind), -+ ai->Addr.SectKind.objname, -+ xpost ); -+ break; -+ -+ default: -+ VG_(tool_panic)("mc_pp_AddrInfo"); -+ } -+} -+ -+void VG_(pp_addrinfo) ( Addr a, AddrInfo* ai ) -+{ -+ pp_addrinfo_WRK (a, ai, False /*mc*/, False /*maybe_gcc*/); -+} -+ -+void VG_(pp_addrinfo_mc) ( Addr a, AddrInfo* ai, Bool maybe_gcc ) -+{ -+ pp_addrinfo_WRK (a, ai, True /*mc*/, maybe_gcc); -+} -+ -+ -+/*--------------------------------------------------------------------*/ -+/*--- end m_addrinfo.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_aspacemgr/aspacemgr-common.c -=================================================================== ---- coregrind/m_aspacemgr/aspacemgr-common.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_aspacemgr/aspacemgr-common.c (.../trunk) (revision 13981) -@@ -152,8 +152,12 @@ - { - SysRes res; - aspacem_assert(VG_IS_PAGE_ALIGNED(offset)); --# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_arm_linux) -+ -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall6)(__NR3264_mmap, (UWord)start, length, -+ prot, flags, fd, offset); -+# elif defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -+ || defined(VGP_arm_linux) - /* mmap2 uses 4096 chunks even if actual page size is bigger. */ - aspacem_assert((offset % 4096) == 0); - res = VG_(do_syscall6)(__NR_mmap2, (UWord)start, length, -@@ -160,7 +164,7 @@ - prot, flags, fd, offset / 4096); - # elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length, - prot, flags, fd, offset); - # elif defined(VGP_x86_darwin) -@@ -242,8 +246,14 @@ - /* --- Pertaining to files --- */ - - SysRes ML_(am_open) ( const HChar* pathname, Int flags, Int mode ) --{ -+{ -+# if defined(VGP_arm64_linux) -+ /* ARM64 wants to use __NR_openat rather than __NR_open. */ -+ SysRes res = VG_(do_syscall4)(__NR_openat, -+ VKI_AT_FDCWD, (UWord)pathname, flags, mode); -+# else - SysRes res = VG_(do_syscall3)(__NR_open, (UWord)pathname, flags, mode); -+# endif - return res; - } - -@@ -261,7 +271,12 @@ - Int ML_(am_readlink)(HChar* path, HChar* buf, UInt bufsiz) - { - SysRes res; -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, -+ (UWord)path, (UWord)buf, bufsiz); -+# else - res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz); -+# endif - return sr_isError(res) ? -1 : sr_Res(res); - } - -Index: coregrind/m_aspacemgr/aspacemgr-linux.c -=================================================================== ---- coregrind/m_aspacemgr/aspacemgr-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_aspacemgr/aspacemgr-linux.c (.../trunk) (revision 13981) -@@ -105,6 +105,9 @@ - to some low-ish value at startup (64M) and aspacem_maxAddr is - derived from the stack pointer at system startup. This seems a - reliable way to establish the initial boundaries. -+ A command line option allows to change the value of aspacem_minAddr, -+ so as to allow memory hungry applications to use the lowest -+ part of the memory. - - 64-bit Linux is similar except for the important detail that the - upper boundary is set to 64G. The reason is so that all -@@ -316,6 +319,19 @@ - - /* Limits etc */ - -+ -+Addr VG_(clo_aspacem_minAddr) -+#if defined(VGO_darwin) -+# if VG_WORDSIZE == 4 -+ = (Addr) 0x00001000; -+# else -+ = (Addr) 0x100000000; // 4GB page zero -+# endif -+#else -+ = (Addr) 0x04000000; // 64M -+#endif -+ -+ - // The smallest address that aspacem will try to allocate - static Addr aspacem_minAddr = 0; - -@@ -1278,12 +1294,12 @@ - } - - --/* Test if a piece of memory is addressable by the client with at -+/* Test if a piece of memory is addressable by client or by valgrind with at - least the "prot" protection permissions by examining the underlying -- segments. If freeOk is True then SkFree areas are also allowed. -+ segments. If client && freeOk is True then SkFree areas are also allowed. - */ - static --Bool is_valid_for_client( Addr start, SizeT len, UInt prot, Bool freeOk ) -+Bool is_valid_for( Bool client, Addr start, SizeT len, UInt prot, Bool freeOk ) - { - Int i, iLo, iHi; - Bool needR, needW, needX; -@@ -1311,19 +1327,33 @@ - iHi = find_nsegment_idx(start + len - 1); - } - -- for (i = iLo; i <= iHi; i++) { -- if ( (nsegments[i].kind == SkFileC -- || nsegments[i].kind == SkAnonC -- || nsegments[i].kind == SkShmC -- || (nsegments[i].kind == SkFree && freeOk) -- || (nsegments[i].kind == SkResvn && freeOk)) -- && (needR ? nsegments[i].hasR : True) -- && (needW ? nsegments[i].hasW : True) -- && (needX ? nsegments[i].hasX : True) ) { -- /* ok */ -- } else { -- return False; -+ if (client) { -+ for (i = iLo; i <= iHi; i++) { -+ if ( (nsegments[i].kind == SkFileC -+ || nsegments[i].kind == SkAnonC -+ || nsegments[i].kind == SkShmC -+ || (nsegments[i].kind == SkFree && freeOk) -+ || (nsegments[i].kind == SkResvn && freeOk)) -+ && (needR ? nsegments[i].hasR : True) -+ && (needW ? nsegments[i].hasW : True) -+ && (needX ? nsegments[i].hasX : True) ) { -+ /* ok */ -+ } else { -+ return False; -+ } - } -+ } else { -+ for (i = iLo; i <= iHi; i++) { -+ if ( (nsegments[i].kind == SkFileV -+ || nsegments[i].kind == SkAnonV) -+ && (needR ? nsegments[i].hasR : True) -+ && (needW ? nsegments[i].hasW : True) -+ && (needX ? nsegments[i].hasX : True) ) { -+ /* ok */ -+ } else { -+ return False; -+ } -+ } - } - return True; - } -@@ -1334,7 +1364,8 @@ - Bool VG_(am_is_valid_for_client)( Addr start, SizeT len, - UInt prot ) - { -- return is_valid_for_client( start, len, prot, False/*free not OK*/ ); -+ return is_valid_for(/* client */ True, -+ start, len, prot, False/*free not OK*/ ); - } - - /* Variant of VG_(am_is_valid_for_client) which allows free areas to -@@ -1344,32 +1375,15 @@ - Bool VG_(am_is_valid_for_client_or_free_or_resvn) - ( Addr start, SizeT len, UInt prot ) - { -- return is_valid_for_client( start, len, prot, True/*free is OK*/ ); -+ return is_valid_for(/* client */ True, -+ start, len, prot, True/*free is OK*/ ); - } - - --/* Test if a piece of memory is addressable by valgrind with at least -- PROT_NONE protection permissions by examining the underlying -- segments. */ --static Bool is_valid_for_valgrind( Addr start, SizeT len ) -+Bool VG_(am_is_valid_for_valgrind) ( Addr start, SizeT len, UInt prot ) - { -- Int i, iLo, iHi; -- -- if (len == 0) -- return True; /* somewhat dubious case */ -- if (start + len < start) -- return False; /* reject wraparounds */ -- -- iLo = find_nsegment_idx(start); -- iHi = find_nsegment_idx(start + len - 1); -- for (i = iLo; i <= iHi; i++) { -- if (nsegments[i].kind == SkFileV || nsegments[i].kind == SkAnonV) { -- /* ok */ -- } else { -- return False; -- } -- } -- return True; -+ return is_valid_for(/* client */ False, -+ start, len, prot, False/*irrelevant*/ ); - } - - -@@ -1629,16 +1643,16 @@ - nsegments[0] = seg; - nsegments_used = 1; - -+ aspacem_minAddr = VG_(clo_aspacem_minAddr); -+ - #if defined(VGO_darwin) - - # if VG_WORDSIZE == 4 -- aspacem_minAddr = (Addr) 0x00001000; - aspacem_maxAddr = (Addr) 0xffffffff; - - aspacem_cStart = aspacem_minAddr; - aspacem_vStart = 0xf0000000; // 0xc0000000..0xf0000000 available - # else -- aspacem_minAddr = (Addr) 0x100000000; // 4GB page zero - aspacem_maxAddr = (Addr) 0x7fffffffffff; - - aspacem_cStart = aspacem_minAddr; -@@ -1657,8 +1671,6 @@ - " sp_at_startup = 0x%010llx (supplied)\n", - (ULong)sp_at_startup ); - -- aspacem_minAddr = (Addr) 0x04000000; // 64M -- - # if VG_WORDSIZE == 8 - aspacem_maxAddr = (Addr)0x1000000000ULL - 1; // 64G - # ifdef ENABLE_INNER -@@ -1671,7 +1683,7 @@ - aspacem_maxAddr = VG_PGROUNDDN( sp_at_startup ) - 1; - # endif - -- aspacem_cStart = aspacem_minAddr; // 64M -+ aspacem_cStart = aspacem_minAddr; - aspacem_vStart = VG_PGROUNDUP(aspacem_minAddr - + (aspacem_maxAddr - aspacem_minAddr + 1) / 2); - # ifdef ENABLE_INNER -@@ -2407,21 +2419,6 @@ - } - - --/* Similarly, acquire new address space for the client but with -- considerable restrictions on what can be done with it: (1) the -- actual protections may exceed those stated in 'prot', (2) the -- area's protections cannot be later changed using any form of -- mprotect, and (3) the area cannot be freed using any form of -- munmap. On Linux this behaves the same as -- VG_(am_mmap_anon_float_client). On AIX5 this *may* allocate memory -- by using sbrk, so as to make use of large pages on AIX. */ -- --SysRes VG_(am_sbrk_anon_float_client) ( SizeT length, Int prot ) --{ -- return VG_(am_mmap_anon_float_client) ( length, prot ); --} -- -- - /* Map anonymously at an unconstrained address for V, and update the - segment array accordingly. This is fundamentally how V allocates - itself more address space when needed. */ -@@ -2527,15 +2524,6 @@ - return sr_isError(sres) ? NULL : (void*)sr_Res(sres); - } - --/* Same comments apply as per VG_(am_sbrk_anon_float_client). On -- Linux this behaves the same as VG_(am_mmap_anon_float_valgrind). */ -- --SysRes VG_(am_sbrk_anon_float_valgrind)( SizeT cszB ) --{ -- return VG_(am_mmap_anon_float_valgrind)( cszB ); --} -- -- - /* Map a file at an unconstrained address for V, and update the - segment array accordingly. Use the provided flags */ - -@@ -2559,7 +2547,8 @@ - /* Ask for an advisory. If it's negative, fail immediately. */ - req.rkind = MAny; - req.start = 0; -- #if defined(VGA_arm) || defined(VGA_mips32) || defined(VGA_mips64) -+ #if defined(VGA_arm) || defined(VGA_arm64) \ -+ || defined(VGA_mips32) || defined(VGA_mips64) - aspacem_assert(VKI_SHMLBA >= VKI_PAGE_SIZE); - #else - aspacem_assert(VKI_SHMLBA == VKI_PAGE_SIZE); -@@ -2666,7 +2655,8 @@ - ( start, len, VKI_PROT_NONE )) - goto eINVAL; - } else { -- if (!is_valid_for_valgrind( start, len )) -+ if (!VG_(am_is_valid_for_valgrind) -+ ( start, len, VKI_PROT_NONE )) - goto eINVAL; - } - -Index: coregrind/m_cache.c -=================================================================== ---- coregrind/m_cache.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_cache.c (.../trunk) (revision 13981) -@@ -539,7 +539,7 @@ - } - - #elif defined(VGA_arm) || defined(VGA_ppc32) || defined(VGA_ppc64) || \ -- defined(VGA_mips32) || defined(VGA_mips64) -+ defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) - - static Bool - get_cache_info(VexArchInfo *vai) -Index: coregrind/m_coredump/coredump-elf.c -=================================================================== ---- coregrind/m_coredump/coredump-elf.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_coredump/coredump-elf.c (.../trunk) (revision 13981) -@@ -136,7 +136,8 @@ - phdr->p_align = VKI_PAGE_SIZE; - } - --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* Android's libc doesn't provide a definition for this. Hence: */ - typedef - struct { -@@ -159,7 +160,8 @@ - + VG_ROUNDUP(n->note.n_descsz, 4); - } - --#if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+#if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - static void add_note(struct note **list, const HChar *name, UInt type, - const void *data, UInt datasz) - { -@@ -231,7 +233,7 @@ - } - - static void fill_prstatus(const ThreadState *tst, -- struct vki_elf_prstatus *prs, -+ /*OUT*/struct vki_elf_prstatus *prs, - const vki_siginfo_t *si) - { - struct vki_user_regs_struct *regs; -@@ -250,12 +252,11 @@ - prs->pr_pgrp = VG_(getpgrp)(); - prs->pr_sid = VG_(getpgrp)(); - --#ifdef VGP_s390x_linux -+#if defined(VGP_s390x_linux) - /* prs->pr_reg has struct type. Need to take address. */ - regs = (struct vki_user_regs_struct *)&(prs->pr_reg); - #else - regs = (struct vki_user_regs_struct *)prs->pr_reg; -- - vg_assert(sizeof(*regs) == sizeof(prs->pr_reg)); - #endif - -@@ -300,10 +301,6 @@ - regs->r14 = arch->vex.guest_R14; - regs->r15 = arch->vex.guest_R15; - --//:: regs->cs = arch->vex.guest_CS; --//:: regs->fs = arch->vex.guest_FS; --//:: regs->gs = arch->vex.guest_GS; -- - #elif defined(VGP_ppc32_linux) - # define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -365,6 +362,10 @@ - regs->ARM_pc = arch->vex.guest_R15T; - regs->ARM_cpsr = LibVEX_GuestARM_get_cpsr( &arch->vex ); - -+#elif defined(VGP_arm64_linux) -+ (void)arch; -+ I_die_here; -+ - #elif defined(VGP_s390x_linux) - # define DO(n) regs->gprs[n] = arch->vex.guest_r##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -375,6 +376,7 @@ - DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); - # undef DO - regs->orig_gpr2 = arch->vex.guest_r2; -+ - #elif defined(VGP_mips32_linux) - # define DO(n) regs->MIPS_r##n = arch->vex.guest_r##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -384,6 +386,7 @@ - # undef DO - regs->MIPS_hi = arch->vex.guest_HI; - regs->MIPS_lo = arch->vex.guest_LO; -+ - #elif defined(VGP_mips64_linux) - # define DO(n) regs->MIPS_r##n = arch->vex.guest_r##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -393,6 +396,7 @@ - # undef DO - regs->MIPS_hi = arch->vex.guest_HI; - regs->MIPS_lo = arch->vex.guest_LO; -+ - #else - # error Unknown ELF platform - #endif -@@ -468,6 +472,9 @@ - #elif defined(VGP_arm_linux) - // umm ... - -+#elif defined(VGP_arm64_linux) -+ I_die_here; -+ - #elif defined(VGP_s390x_linux) - # define DO(n) fpu->fprs[n].ui = arch->vex.guest_f##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -518,7 +525,7 @@ - #endif - - static --void make_elf_coredump(ThreadId tid, const vki_siginfo_t *si, UInt max_size) -+void make_elf_coredump(ThreadId tid, const vki_siginfo_t *si, ULong max_size) - { - HChar* buf = NULL; - const HChar *basename = "vgcore"; -@@ -604,8 +611,7 @@ - if (VG_(threads)[i].status == VgTs_Empty) - continue; - --# if defined(VGP_x86_linux) --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if defined(VGP_x86_linux) && !defined(VGPV_x86_linux_android) - { - vki_elf_fpxregset_t xfpu; - fill_xfpu(&VG_(threads)[i], &xfpu); -@@ -612,21 +618,23 @@ - add_note(¬elist, "LINUX", NT_PRXFPREG, &xfpu, sizeof(xfpu)); - } - # endif --# endif - - fill_fpu(&VG_(threads)[i], &fpu); --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - add_note(¬elist, "CORE", NT_FPREGSET, &fpu, sizeof(fpu)); - # endif - - fill_prstatus(&VG_(threads)[i], &prstatus, si); --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - add_note(¬elist, "CORE", NT_PRSTATUS, &prstatus, sizeof(prstatus)); - # endif - } - - fill_prpsinfo(&VG_(threads)[tid], &prpsinfo); --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - add_note(¬elist, "CORE", NT_PRPSINFO, &prpsinfo, sizeof(prpsinfo)); - # endif - -@@ -692,7 +700,7 @@ - VG_(close)(core_fd); - } - --void VG_(make_coredump)(ThreadId tid, const vki_siginfo_t *si, UInt max_size) -+void VG_(make_coredump)(ThreadId tid, const vki_siginfo_t *si, ULong max_size) - { - make_elf_coredump(tid, si, max_size); - } -Index: coregrind/m_coredump/coredump-macho.c -=================================================================== ---- coregrind/m_coredump/coredump-macho.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_coredump/coredump-macho.c (.../trunk) (revision 13981) -@@ -36,7 +36,7 @@ - #include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy - #include "pub_core_threadstate.h" - --void VG_(make_coredump)(ThreadId tid, const vki_siginfo_t *si, UInt max_size) -+void VG_(make_coredump)(ThreadId tid, const vki_siginfo_t *si, ULong max_size) - { - // DDD: #warning GrP fixme coredump - } -Index: coregrind/m_debugger.c -=================================================================== ---- coregrind/m_debugger.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debugger.c (.../trunk) (revision 13981) -@@ -232,6 +232,47 @@ - uregs.ARM_cpsr = LibVEX_GuestARM_get_cpsr(vex); - return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs); - -+#elif defined(VGP_arm64_linux) -+ I_die_here; -+ //ATC -+ struct vki_user_pt_regs uregs; -+ VG_(memset)(&uregs, 0, sizeof(uregs)); -+ uregs.regs[0] = vex->guest_X0; -+ uregs.regs[1] = vex->guest_X1; -+ uregs.regs[2] = vex->guest_X2; -+ uregs.regs[3] = vex->guest_X3; -+ uregs.regs[4] = vex->guest_X4; -+ uregs.regs[5] = vex->guest_X5; -+ uregs.regs[6] = vex->guest_X6; -+ uregs.regs[7] = vex->guest_X7; -+ uregs.regs[8] = vex->guest_X8; -+ uregs.regs[9] = vex->guest_X9; -+ uregs.regs[10] = vex->guest_X10; -+ uregs.regs[11] = vex->guest_X11; -+ uregs.regs[12] = vex->guest_X12; -+ uregs.regs[13] = vex->guest_X13; -+ uregs.regs[14] = vex->guest_X14; -+ uregs.regs[15] = vex->guest_X15; -+ uregs.regs[16] = vex->guest_X16; -+ uregs.regs[17] = vex->guest_X17; -+ uregs.regs[18] = vex->guest_X18; -+ uregs.regs[19] = vex->guest_X19; -+ uregs.regs[20] = vex->guest_X20; -+ uregs.regs[21] = vex->guest_X21; -+ uregs.regs[22] = vex->guest_X22; -+ uregs.regs[23] = vex->guest_X23; -+ uregs.regs[24] = vex->guest_X24; -+ uregs.regs[25] = vex->guest_X25; -+ uregs.regs[26] = vex->guest_X26; -+ uregs.regs[27] = vex->guest_X27; -+ uregs.regs[28] = vex->guest_X28; -+ uregs.regs[29] = vex->guest_X29; -+ uregs.regs[30] = vex->guest_X30; -+ uregs.sp = vex->guest_XSP; -+ uregs.pc = vex->guest_PC; -+ uregs.pstate = LibVEX_GuestARM64_get_nzcv(vex); /* is this correct? */ -+ return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs); -+ - #elif defined(VGP_x86_darwin) - I_die_here; - -Index: coregrind/m_debuginfo/d3basics.c -=================================================================== ---- coregrind/m_debuginfo/d3basics.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/d3basics.c (.../trunk) (revision 13981) -@@ -420,6 +420,8 @@ - # elif defined(VGP_mips64_linux) - if (regno == 29) { *a = regs->sp; return True; } - if (regno == 30) { *a = regs->fp; return True; } -+# elif defined(VGP_arm64_linux) -+ I_die_here; - # else - # error "Unknown platform" - # endif -Index: coregrind/m_debuginfo/debuginfo.c -=================================================================== ---- coregrind/m_debuginfo/debuginfo.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/debuginfo.c (.../trunk) (revision 13981) -@@ -824,7 +824,8 @@ - || defined(VGA_mips64) - is_rx_map = seg->hasR && seg->hasX; - is_rw_map = seg->hasR && seg->hasW; --# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) -+# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) \ -+ || defined(VGA_arm64) - is_rx_map = seg->hasR && seg->hasX && !seg->hasW; - is_rw_map = seg->hasR && seg->hasW && !seg->hasX; - # elif defined(VGP_s390x_linux) -@@ -2113,6 +2114,8 @@ - case Creg_IA_BP: return eec->uregs->fp; - case Creg_MIPS_RA: return eec->uregs->ra; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ case Creg_ARM64_X30: return eec->uregs->x30; - # else - # error "Unsupported arch" - # endif -@@ -2357,6 +2360,13 @@ - cfa = cfsi->cfa_off + uregs->fp; - break; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ case CFIC_ARM64_SPREL: -+ cfa = cfsi->cfa_off + uregs->sp; -+ break; -+ case CFIC_ARM64_X29REL: -+ cfa = cfsi->cfa_off + uregs->x29; -+ break; - # else - # error "Unsupported arch" - # endif -@@ -2416,6 +2426,14 @@ - return compute_cfa(&uregs, - min_accessible, max_accessible, di, cfsi); - } -+#elif defined(VGA_mips32) || defined(VGA_mips64) -+ { D3UnwindRegs uregs; -+ uregs.pc = ip; -+ uregs.sp = sp; -+ uregs.fp = fp; -+ return compute_cfa(&uregs, -+ min_accessible, max_accessible, di, cfsi); -+ } - - # else - return 0; /* indicates failure */ -@@ -2432,6 +2450,8 @@ - {E,R}SP, {E,R}BP. - - For arm, the unwound registers are: R7 R11 R12 R13 R14 R15. -+ -+ For arm64, the unwound registers are: X29(FP) X30(LR) SP PC. - */ - Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere, - Addr min_accessible, -@@ -2453,6 +2473,8 @@ - # elif defined(VGA_mips32) || defined(VGA_mips64) - ipHere = uregsHere->pc; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ ipHere = uregsHere->pc; - # else - # error "Unknown arch" - # endif -@@ -2533,6 +2555,11 @@ - COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi->sp_how, cfsi->sp_off); - COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi->fp_how, cfsi->fp_off); - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi->ra_how, cfsi->ra_off); -+ COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi->sp_how, cfsi->sp_off); -+ COMPUTE(uregsPrev.x30, uregsHere->x30, cfsi->x30_how, cfsi->x30_off); -+ COMPUTE(uregsPrev.x29, uregsHere->x29, cfsi->x29_how, cfsi->x29_off); - # else - # error "Unknown arch" - # endif -Index: coregrind/m_debuginfo/priv_storage.h -=================================================================== ---- coregrind/m_debuginfo/priv_storage.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/priv_storage.h (.../trunk) (revision 13981) -@@ -133,7 +133,7 @@ - cfa = case cfa_how of - CFIC_IA_SPREL -> {e,r}sp + cfa_off - CFIC_IA_BPREL -> {e,r}bp + cfa_off -- CFIR_IA_EXPR -> expr whose index is in cfa_off -+ CFIC_EXPR -> expr whose index is in cfa_off - - Once that is done, the previous frame's {e,r}sp/{e,r}bp values and - this frame's {e,r}ra value can be calculated like this: -@@ -150,11 +150,11 @@ - keep track of: - - cfa = case cfa_how of -- CFIC_R13REL -> r13 + cfa_off -- CFIC_R12REL -> r12 + cfa_off -- CFIC_R11REL -> r11 + cfa_off -- CFIC_R7REL -> r7 + cfa_off -- CFIR_EXPR -> expr whose index is in cfa_off -+ CFIC_ARM_R13REL -> r13 + cfa_off -+ CFIC_ARM_R12REL -> r12 + cfa_off -+ CFIC_ARM_R11REL -> r11 + cfa_off -+ CFIC_ARM_R7REL -> r7 + cfa_off -+ CFIR_EXPR -> expr whose index is in cfa_off - - old_r14/r13/r12/r11/r7/ra - = case r14/r13/r12/r11/r7/ra_how of -@@ -164,6 +164,21 @@ - CFIR_MEMCFAREL -> *( cfa + r14/r13/r12/r11/r7/ra_off ) - CFIR_EXPR -> expr whose index is in r14/r13/r12/r11/r7/ra_off - -+ On ARM64: -+ -+ cfa = case cfa_how of -+ CFIC_ARM64_SPREL -> sp + cfa_off -+ CFIC_ARM64_X29REL -> x29 + cfa_off -+ CFIC_EXPR -> expr whose index is in cfa_off -+ -+ old_sp/x30/x29/ra -+ = case sp/x30/x29/ra_how of -+ CFIR_UNKNOWN -> we don't know, sorry -+ CFIR_SAME -> same as it was before -+ CFIR_CFAREL -> cfa + sp/x30/x29/ra_how -+ CFIR_MEMCFAREL -> *( cfa + sp/x30/x29/ra_how ) -+ CFIR_EXPR -> expr whose index is in sp/x30/x29/ra_off -+ - On s390x we have a similar logic as x86 or amd64. We need the stack pointer - (r15), the frame pointer r11 (like BP) and together with the instruction - address in the PSW we can calculate the previous values: -@@ -170,7 +185,7 @@ - cfa = case cfa_how of - CFIC_IA_SPREL -> r15 + cfa_off - CFIC_IA_BPREL -> r11 + cfa_off -- CFIR_IA_EXPR -> expr whose index is in cfa_off -+ CFIC_EXPR -> expr whose index is in cfa_off - - old_sp/fp/ra - = case sp/fp/ra_how of -@@ -183,12 +198,13 @@ - - #define CFIC_IA_SPREL ((UChar)1) - #define CFIC_IA_BPREL ((UChar)2) --#define CFIC_IA_EXPR ((UChar)3) --#define CFIC_ARM_R13REL ((UChar)4) --#define CFIC_ARM_R12REL ((UChar)5) --#define CFIC_ARM_R11REL ((UChar)6) --#define CFIC_ARM_R7REL ((UChar)7) --#define CFIC_EXPR ((UChar)8) /* all targets */ -+#define CFIC_ARM_R13REL ((UChar)3) -+#define CFIC_ARM_R12REL ((UChar)4) -+#define CFIC_ARM_R11REL ((UChar)5) -+#define CFIC_ARM_R7REL ((UChar)6) -+#define CFIC_ARM64_SPREL ((UChar)7) -+#define CFIC_ARM64_X29REL ((UChar)8) -+#define CFIC_EXPR ((UChar)9) /* all targets */ - - #define CFIR_UNKNOWN ((UChar)64) - #define CFIR_SAME ((UChar)65) -@@ -232,6 +248,23 @@ - Int r7_off; - } - DiCfSI; -+#elif defined(VGA_arm64) -+typedef -+ struct { -+ Addr base; -+ UInt len; -+ UChar cfa_how; /* a CFIC_ value */ -+ UChar ra_how; /* a CFIR_ value */ -+ UChar sp_how; /* a CFIR_ value */ /*dw31=SP*/ -+ UChar x30_how; /* a CFIR_ value */ /*dw30=LR*/ -+ UChar x29_how; /* a CFIR_ value */ /*dw29=FP*/ -+ Int cfa_off; -+ Int ra_off; -+ Int sp_off; -+ Int x30_off; -+ Int x29_off; -+ } -+ DiCfSI; - #elif defined(VGA_ppc32) || defined(VGA_ppc64) - /* Just have a struct with the common fields in, so that code that - processes the common fields doesn't have to be ifdef'd against -@@ -316,6 +349,7 @@ - Creg_ARM_R12, - Creg_ARM_R15, - Creg_ARM_R14, -+ Creg_ARM64_X30, - Creg_S390_R14, - Creg_MIPS_RA - } -Index: coregrind/m_debuginfo/priv_tytypes.h -=================================================================== ---- coregrind/m_debuginfo/priv_tytypes.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/priv_tytypes.h (.../trunk) (revision 13981) -@@ -116,6 +116,7 @@ - struct { - HChar* name; /* in mallocville */ - UWord szB; -+ UWord typeR; - XArray* /* of UWord */ fieldRs; - Bool complete; - Bool isStruct; -Index: coregrind/m_debuginfo/readdwarf.c -=================================================================== ---- coregrind/m_debuginfo/readdwarf.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/readdwarf.c (.../trunk) (revision 13981) -@@ -1840,7 +1840,11 @@ - #elif defined(VGP_arm_linux) - # define FP_REG 12 - # define SP_REG 13 --# define RA_REG_DEFAULT 14 //??? -+# define RA_REG_DEFAULT 14 -+#elif defined(VGP_arm64_linux) -+# define FP_REG 29 -+# define SP_REG 31 -+# define RA_REG_DEFAULT 30 - #elif defined(VGP_x86_darwin) - # define FP_REG 5 - # define SP_REG 4 -@@ -1874,6 +1878,8 @@ - # define N_CFI_REGS 72 - #elif defined(VGP_arm_linux) - # define N_CFI_REGS 320 -+#elif defined(VGP_arm64_linux) -+# define N_CFI_REGS 128 - #else - # define N_CFI_REGS 20 - #endif -@@ -2096,6 +2102,11 @@ - ctx->state[j].reg[12].tag = RR_Same; - ctx->state[j].reg[7].tag = RR_Same; - /* this can't be right though: R12 (IP) isn't callee saved. */ -+# elif defined(VGA_arm64) -+ /* Callee-saved registers (that we are interested in) should -+ start out as RR_Same. */ -+ ctx->state[j].reg[29/*FP*/].tag = RR_Same; -+ ctx->state[j].reg[30/*LR*/].tag = RR_Same; - # endif - } - } -@@ -2117,7 +2128,7 @@ - - static void initCfiSI ( DiCfSI* si ) - { -- VG_(memset)(si, 0, sizeof(*si)); -+ VG_(bzero_inline)(si, sizeof(*si)); - } - - -@@ -2179,6 +2190,8 @@ - si->cfa_how = CFIC_IA_SPREL; - # elif defined(VGA_arm) - si->cfa_how = CFIC_ARM_R13REL; -+# elif defined(VGA_arm64) -+ si->cfa_how = CFIC_ARM64_SPREL; - # else - si->cfa_how = 0; /* invalid */ - # endif -@@ -2191,6 +2204,8 @@ - si->cfa_how = CFIC_IA_BPREL; - # elif defined(VGA_arm) - si->cfa_how = CFIC_ARM_R12REL; -+# elif defined(VGA_arm64) -+ si->cfa_how = CFIC_ARM64_X29REL; - # else - si->cfa_how = 0; /* invalid */ - # endif -@@ -2206,6 +2221,8 @@ - si->cfa_how = CFIC_ARM_R7REL; - si->cfa_off = ctxs->cfa_off; - } -+# elif defined(VGA_arm64) -+ // do we need any arm64 specifics here? - # endif - else { - why = 1; -@@ -2249,6 +2266,7 @@ - why = 2; goto failed; /* otherwise give up */ \ - } - -+ - # if defined(VGA_x86) || defined(VGA_amd64) - - /* --- entire tail of this fn specialised for x86/amd64 --- */ -@@ -2339,9 +2357,52 @@ - - return True; - -+# elif defined(VGA_arm64) - -+ /* --- entire tail of this fn specialised for arm64 --- */ -+ -+ SUMMARISE_HOW(si->x30_how, si->x30_off, ctxs->reg[30/*LR*/]); -+ SUMMARISE_HOW(si->x29_how, si->x29_off, ctxs->reg[29/*FP*/]); -+ -+ if (ctxs->reg[30/*LR*/].tag == RR_Same -+ && ctx->ra_reg == 30/*as we expect it always to be*/) { -+ /* Generate a trivial CfiExpr, which merely says "x30". First -+ ensure this DebugInfo has a cfsi_expr array in which to park -+ it. */ -+ if (!debuginfo->cfsi_exprs) -+ debuginfo->cfsi_exprs = VG_(newXA)( ML_(dinfo_zalloc), -+ "di.ccCt.2a-arm64", -+ ML_(dinfo_free), -+ sizeof(CfiExpr) ); -+ si->ra_off = ML_(CfiExpr_CfiReg)( debuginfo->cfsi_exprs, -+ Creg_ARM64_X30); -+ si->ra_how = CFIR_EXPR; -+ } else { -+ /* Just summarise it in the normal way */ -+ SUMMARISE_HOW(si->ra_how, si->ra_off, ctxs->reg[ctx->ra_reg]); -+ } -+ -+ /* on arm64, it seems the old SP value before the call is always -+ the same as the CFA. Therefore ... */ -+ si->sp_how = CFIR_CFAREL; -+ si->sp_off = 0; -+ -+ /* bogus looking range? Note, we require that the difference is -+ representable in 32 bits. */ -+ if (loc_start >= ctx->loc) -+ { why = 4; goto failed; } -+ if (ctx->loc - loc_start > 10000000 /* let's say */) -+ { why = 5; goto failed; } -+ -+ si->base = loc_start + ctx->initloc; -+ si->len = (UInt)(ctx->loc - loc_start); -+ -+ return True; -+ - # elif defined(VGA_s390x) - -+ /* --- entire tail of this fn specialised for s390 --- */ -+ - SUMMARISE_HOW(si->ra_how, si->ra_off, - ctxs->reg[ctx->ra_reg] ); - SUMMARISE_HOW(si->fp_how, si->fp_off, -@@ -2387,7 +2448,6 @@ - - return True; - -- - # elif defined(VGA_mips32) || defined(VGA_mips64) - - /* --- entire tail of this fn specialised for mips --- */ -@@ -2431,13 +2491,15 @@ - - return True; - -+# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+ /* These don't use CFI based unwinding (is that really true?) */ - -- --# elif defined(VGA_ppc32) || defined(VGA_ppc64) - # else - # error "Unknown arch" - # endif - -+ /* --- non-specialised code after this point --- */ -+ - # undef SUMMARISE_HOW - - failed: -@@ -2521,6 +2583,8 @@ - return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_BP ); - if (dwreg == srcuc->ra_reg) - return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP ); -+# elif defined(VGA_arm64) -+ I_die_here; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) - # else - # error "Unknown arch" -Index: coregrind/m_debuginfo/readdwarf3.c -=================================================================== ---- coregrind/m_debuginfo/readdwarf3.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/readdwarf3.c (.../trunk) (revision 13981) -@@ -1638,6 +1638,12 @@ - /* We're done! The rest of it is not interesting. */ - } - -+__attribute__((noinline)) -+static void bad_DIE_confusion(int linenr) -+{ -+ VG_(printf)("\nparse_var_DIE(%d): confused by:\n", linenr); -+} -+#define goto_bad_DIE do {bad_DIE_confusion(__LINE__); goto bad_DIE;} while (0) - - __attribute__((noinline)) - static void parse_var_DIE ( -@@ -1743,6 +1749,18 @@ - unitary_range_list(ip_lo, ip_hi1 - 1), - level, - False/*isFunc*/, NULL/*fbGX*/ ); -+ else if (ip_lo == 0 && ip_hi1 == 0) -+ /* CU has no code, presumably? -+ Such situations have been encountered for code -+ compiled with -ffunction-sections -fdata-sections -+ and linked with --gc-sections. Completely -+ eliminated CU gives such 0 lo/hi pc. Similarly -+ to a CU which has no lo/hi/range pc, we push -+ an empty range list. */ -+ varstack_push( cc, parser, td3, -+ empty_range_list(), -+ level, -+ False/*isFunc*/, NULL/*fbGX*/ ); - } else - if ((!have_lo) && (!have_hi1) && have_range) { - varstack_push( cc, parser, td3, -@@ -1770,7 +1788,7 @@ - } else { - if (0) VG_(printf)("I got hlo %d hhi1 %d hrange %d\n", - (Int)have_lo, (Int)have_hi1, (Int)have_range); -- goto bad_DIE; -+ goto_bad_DIE; - } - } - -@@ -1856,7 +1874,7 @@ - */ - /* Ignore (seems safe than pushing a single byte range) */ - } else -- goto bad_DIE; -+ goto_bad_DIE; - } - - if (dtag == DW_TAG_variable || dtag == DW_TAG_formal_parameter) { -@@ -1969,7 +1987,7 @@ - "warning: parse_var_DIE: non-global variable " - "outside DW_TAG_subprogram\n"); - } -- /* goto bad_DIE; */ -+ /* goto_bad_DIE; */ - /* This seems to happen a lot. Just ignore it -- if, - when we come to evaluation of the location (guarded) - expression, it requires a frame base value, and -@@ -2123,7 +2141,6 @@ - bad_DIE: - set_position_of_Cursor( c_die, saved_die_c_offset ); - set_position_of_Cursor( c_abbv, saved_abbv_c_offset ); -- VG_(printf)("\nparse_var_DIE: confused by:\n"); - posn = uncook_die( cc, posn, &debug_types_flag, &alt_flag ); - VG_(printf)(" <%d><%lx>: %s", level, posn, ML_(pp_DW_TAG)( dtag ) ); - if (debug_types_flag) { -@@ -2339,7 +2356,7 @@ - if (attr != DW_AT_language) - continue; - if (cts.szB <= 0) -- goto bad_DIE; -+ goto_bad_DIE; - switch (cts.u.val) { - case DW_LANG_C89: case DW_LANG_C: - case DW_LANG_C_plus_plus: case DW_LANG_ObjC: -@@ -2359,7 +2376,7 @@ - case DW_LANG_Mips_Assembler: - parser->language = '?'; break; - default: -- goto bad_DIE; -+ goto_bad_DIE; - } - } - } -@@ -2397,7 +2414,7 @@ - case DW_ATE_complex_float: - typeE.Te.TyBase.enc = 'C'; break; - default: -- goto bad_DIE; -+ goto_bad_DIE; - } - } - } -@@ -2420,7 +2437,7 @@ - && typeE.Te.TyBase.enc != 'S' - && typeE.Te.TyBase.enc != 'F' - && typeE.Te.TyBase.enc != 'C')) -- goto bad_DIE; -+ goto_bad_DIE; - /* Last minute hack: if we see this - <1><515>: DW_TAG_base_type - DW_AT_byte_size : 0 -@@ -2493,7 +2510,7 @@ - } - /* Do we have something that looks sane? */ - if (typeE.Te.TyPorR.szB != sizeof(UWord)) -- goto bad_DIE; -+ goto_bad_DIE; - else - goto acquire_Type; - } -@@ -2545,7 +2562,7 @@ - that will put such an enumeration_type into a .debug_types - unit which should only contain complete types.) */ - && (parser->language != 'A' && !is_decl)) { -- goto bad_DIE; -+ goto_bad_DIE; - } - - /* On't stack! */ -@@ -2604,13 +2621,13 @@ - } - /* Do we have something that looks sane? */ - if (atomE.Te.Atom.name == NULL) -- goto bad_DIE; -+ goto_bad_DIE; - /* Do we have a plausible parent? */ -- if (typestack_is_empty(parser)) goto bad_DIE; -+ if (typestack_is_empty(parser)) goto_bad_DIE; - vg_assert(ML_(TyEnt__is_type)(&parser->qparentE[parser->sp])); - vg_assert(parser->qparentE[parser->sp].cuOff != D3_INVALID_CUOFF); -- if (level != parser->qlevel[parser->sp]+1) goto bad_DIE; -- if (parser->qparentE[parser->sp].tag != Te_TyEnum) goto bad_DIE; -+ if (level != parser->qlevel[parser->sp]+1) goto_bad_DIE; -+ if (parser->qparentE[parser->sp].tag != Te_TyEnum) goto_bad_DIE; - /* Record this child in the parent */ - vg_assert(parser->qparentE[parser->sp].Te.TyEnum.atomRs); - VG_(addToXA)( parser->qparentE[parser->sp].Te.TyEnum.atomRs, -@@ -2632,6 +2649,7 @@ - typeE.cuOff = posn; - typeE.tag = Te_TyStOrUn; - typeE.Te.TyStOrUn.name = NULL; -+ typeE.Te.TyStOrUn.typeR = D3_INVALID_CUOFF; - typeE.Te.TyStOrUn.fieldRs - = VG_(newXA)( ML_(dinfo_zalloc), "di.readdwarf3.pTD.struct_type.1", - ML_(dinfo_free), -@@ -2659,6 +2677,13 @@ - if (attr == DW_AT_specification && cts.szB > 0 && cts.u.val > 0) { - is_spec = True; - } -+ if (attr == DW_AT_signature && form == DW_FORM_ref_sig8 -+ && cts.szB > 0) { -+ have_szB = True; -+ typeE.Te.TyStOrUn.szB = 8; -+ typeE.Te.TyStOrUn.typeR -+ = cook_die_using_form( cc, (UWord)cts.u.val, form ); -+ } - } - /* Do we have something that looks sane? */ - if (is_decl && (!is_spec)) { -@@ -2685,9 +2710,18 @@ - } - if ((!is_decl) /* && (!is_spec) */) { - /* this is the common, ordinary case */ -- if ((!have_szB) /* we must know the size */ -- /* But the name can be present, or not */) -- goto bad_DIE; -+ /* The name can be present, or not */ -+ if (!have_szB) { -+ /* We must know the size. -+ But in Ada, record with discriminants might have no size. -+ But in C, VLA in the middle of a struct (gcc extension) -+ might have no size. -+ Instead, some GNAT dwarf extensions and/or dwarf entries -+ allow to calculate the struct size at runtime. -+ We cannot do that (yet?) so, the temporary kludge is to use -+ a small size. */ -+ typeE.Te.TyStOrUn.szB = 1; -+ } - /* On't stack! */ - typestack_push( cc, parser, td3, &typeE, level ); - goto acquire_Type; -@@ -2694,7 +2728,7 @@ - } - else { - /* don't know how to handle any other variants just now */ -- goto bad_DIE; -+ goto_bad_DIE; - } - } - -@@ -2739,11 +2773,11 @@ - } - } - /* Do we have a plausible parent? */ -- if (typestack_is_empty(parser)) goto bad_DIE; -+ if (typestack_is_empty(parser)) goto_bad_DIE; - vg_assert(ML_(TyEnt__is_type)(&parser->qparentE[parser->sp])); - vg_assert(parser->qparentE[parser->sp].cuOff != D3_INVALID_CUOFF); -- if (level != parser->qlevel[parser->sp]+1) goto bad_DIE; -- if (parser->qparentE[parser->sp].tag != Te_TyStOrUn) goto bad_DIE; -+ if (level != parser->qlevel[parser->sp]+1) goto_bad_DIE; -+ if (parser->qparentE[parser->sp].tag != Te_TyStOrUn) goto_bad_DIE; - /* Do we have something that looks sane? If this a member of a - struct, we must have a location expression; but if a member - of a union that is irrelevant (D3 spec sec 5.6.6). We ought -@@ -2758,7 +2792,7 @@ - "" ); - vg_assert(fieldE.Te.Field.name); - if (fieldE.Te.Field.typeR == D3_INVALID_CUOFF) -- goto bad_DIE; -+ goto_bad_DIE; - if (fieldE.Te.Field.nLoc) { - if (!parent_is_struct) { - /* If this is a union type, pretend we haven't seen the data -@@ -2805,7 +2839,7 @@ - } - } - if (typeE.Te.TyArray.typeR == D3_INVALID_CUOFF) -- goto bad_DIE; -+ goto_bad_DIE; - /* On't stack! */ - typestack_push( cc, parser, td3, &typeE, level ); - goto acquire_Type; -@@ -2855,11 +2889,11 @@ - (not being used to describe the bounds of a containing array - type) */ - /* Do we have a plausible parent? */ -- if (typestack_is_empty(parser)) goto bad_DIE; -+ if (typestack_is_empty(parser)) goto_bad_DIE; - vg_assert(ML_(TyEnt__is_type)(&parser->qparentE[parser->sp])); - vg_assert(parser->qparentE[parser->sp].cuOff != D3_INVALID_CUOFF); -- if (level != parser->qlevel[parser->sp]+1) goto bad_DIE; -- if (parser->qparentE[parser->sp].tag != Te_TyArray) goto bad_DIE; -+ if (level != parser->qlevel[parser->sp]+1) goto_bad_DIE; -+ if (parser->qparentE[parser->sp].tag != Te_TyArray) goto_bad_DIE; - - /* Figure out if we have a definite range or not */ - if (have_lower && have_upper && (!have_count)) { -@@ -2887,7 +2921,7 @@ - boundE.Te.Bound.boundU = 0; - } else { - /* FIXME: handle more cases */ -- goto bad_DIE; -+ goto_bad_DIE; - } - - /* Record this bound in the parent */ -@@ -2926,19 +2960,17 @@ - = cook_die_using_form( cc, (UWord)cts.u.val, form ); - } - } -- /* Do we have something that looks sane? */ -- if (/* must have a name */ -- typeE.Te.TyTyDef.name == NULL -- /* However gcc gnat Ada generates minimal typedef -- such as the below => accept no name for Ada. -- <6><91cc>: DW_TAG_typedef -- DW_AT_abstract_ori: <9066> -- */ -- && parser->language != 'A' -- /* but the referred-to type can be absent */) -- goto bad_DIE; -- else -- goto acquire_Type; -+ /* Do we have something that looks sane? -+ gcc gnat Ada generates minimal typedef -+ such as the below -+ <6><91cc>: DW_TAG_typedef -+ DW_AT_abstract_ori: <9066> -+ g++ for OMP can generate artificial functions that have -+ parameters that refer to pointers to unnamed typedefs. -+ See https://bugs.kde.org/show_bug.cgi?id=273475 -+ So we cannot require a name for a DW_TAG_typedef. -+ */ -+ goto acquire_Type; - } - - if (dtag == DW_TAG_subroutine_type) { -@@ -2976,7 +3008,7 @@ - if (have_ty == 1 || have_ty == 0) - goto acquire_Type; - else -- goto bad_DIE; -+ goto_bad_DIE; - } - - /* -@@ -3045,7 +3077,6 @@ - bad_DIE: - set_position_of_Cursor( c_die, saved_die_c_offset ); - set_position_of_Cursor( c_abbv, saved_abbv_c_offset ); -- VG_(printf)("\nparse_type_DIE: confused by:\n"); - posn = uncook_die( cc, posn, &debug_types_flag, &alt_flag ); - VG_(printf)(" <%d><%lx>: %s", level, posn, ML_(pp_DW_TAG)( dtag ) ); - if (debug_types_flag) { -Index: coregrind/m_debuginfo/readelf.c -=================================================================== ---- coregrind/m_debuginfo/readelf.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/readelf.c (.../trunk) (revision 13981) -@@ -2088,7 +2088,8 @@ - /* PLT is different on different platforms, it seems. */ - # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ - || defined(VGP_arm_linux) || defined (VGP_s390x_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - /* Accept .plt where mapped as rx (code) */ - if (0 == VG_(strcmp)(name, ".plt")) { - if (inrx && !di->plt_present) { -@@ -2609,7 +2610,8 @@ - vg_assert(aimg == NULL); - - if (debugaltlink_escn.img != NULL) { -- UInt buildid_offset = ML_(img_strlen)(debugaltlink_escn.img, 0)+1; -+ UInt buildid_offset = ML_(img_strlen)(debugaltlink_escn.img, -+ debugaltlink_escn.ioff)+1; - - vg_assert(buildid_offset < debugaltlink_escn.szB); - -Index: coregrind/m_debuginfo/readstabs.c -=================================================================== ---- coregrind/m_debuginfo/readstabs.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/readstabs.c (.../trunk) (revision 13981) -@@ -36,7 +36,8 @@ - - /* "on Linux (except android), or on Darwin" */ - #if (defined(VGO_linux) && \ -- !(defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)) \ -+ !(defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android)) \ - || defined(VGO_darwin)) - - #include "pub_core_basics.h" -Index: coregrind/m_debuginfo/storage.c -=================================================================== ---- coregrind/m_debuginfo/storage.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/storage.c (.../trunk) (revision 13981) -@@ -162,6 +162,12 @@ - case CFIC_ARM_R7REL: - VG_(printf)("let cfa=oldR7+%d", si->cfa_off); - break; -+ case CFIC_ARM64_SPREL: -+ VG_(printf)("let cfa=oldSP+%d", si->cfa_off); -+ break; -+ case CFIC_ARM64_X29REL: -+ VG_(printf)("let cfa=oldX29+%d", si->cfa_off); -+ break; - case CFIC_EXPR: - VG_(printf)("let cfa={"); - ML_(ppCfiExpr)(exprs, si->cfa_off); -@@ -195,6 +201,13 @@ - SHOW_HOW(si->sp_how, si->sp_off); - VG_(printf)(" FP="); - SHOW_HOW(si->fp_how, si->fp_off); -+# elif defined(VGA_arm64) -+ VG_(printf)(" SP="); -+ SHOW_HOW(si->sp_how, si->sp_off); -+ VG_(printf)(" X30="); -+ SHOW_HOW(si->x30_how, si->x30_off); -+ VG_(printf)(" X29="); -+ SHOW_HOW(si->x29_how, si->x29_off); - # else - # error "Unknown arch" - # endif -@@ -669,15 +682,16 @@ - static void ppCfiReg ( CfiReg reg ) - { - switch (reg) { -- case Creg_IA_SP: VG_(printf)("xSP"); break; -- case Creg_IA_BP: VG_(printf)("xBP"); break; -- case Creg_IA_IP: VG_(printf)("xIP"); break; -- case Creg_ARM_R13: VG_(printf)("R13"); break; -- case Creg_ARM_R12: VG_(printf)("R12"); break; -- case Creg_ARM_R15: VG_(printf)("R15"); break; -- case Creg_ARM_R14: VG_(printf)("R14"); break; -- case Creg_MIPS_RA: VG_(printf)("RA"); break; -- case Creg_S390_R14: VG_(printf)("R14"); break; -+ case Creg_IA_SP: VG_(printf)("xSP"); break; -+ case Creg_IA_BP: VG_(printf)("xBP"); break; -+ case Creg_IA_IP: VG_(printf)("xIP"); break; -+ case Creg_ARM_R13: VG_(printf)("R13"); break; -+ case Creg_ARM_R12: VG_(printf)("R12"); break; -+ case Creg_ARM_R15: VG_(printf)("R15"); break; -+ case Creg_ARM_R14: VG_(printf)("R14"); break; -+ case Creg_ARM64_X30: VG_(printf)("X30"); break; -+ case Creg_MIPS_RA: VG_(printf)("RA"); break; -+ case Creg_S390_R14: VG_(printf)("R14"); break; - default: vg_assert(0); - } - } -Index: coregrind/m_debuginfo/tytypes.c -=================================================================== ---- coregrind/m_debuginfo/tytypes.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuginfo/tytypes.c (.../trunk) (revision 13981) -@@ -265,8 +265,8 @@ - VG_(printf)("&&"); - break; - case Te_TyEnum: -- if (!ent->Te.TyEnum.name) goto unhandled; -- VG_(printf)("enum %s", ent->Te.TyEnum.name); -+ VG_(printf)("enum %s", ent->Te.TyEnum.name ? ent->Te.TyEnum.name -+ : "" ); - break; - case Te_TyStOrUn: - VG_(printf)("%s %s", -@@ -287,8 +287,8 @@ - } - break; - case Te_TyTyDef: -- if (!ent->Te.TyTyDef.name) goto unhandled; -- VG_(printf)("%s", ent->Te.TyTyDef.name); -+ VG_(printf)("%s", ent->Te.TyTyDef.name ? ent->Te.TyTyDef.name -+ : "" ); - break; - case Te_TyFn: - VG_(printf)("%s", ""); -@@ -785,7 +785,8 @@ - PtrdiffT offMin = 0, offMax1 = 0; - if (!ty->Te.TyStOrUn.isStruct) goto done; - fieldRs = ty->Te.TyStOrUn.fieldRs; -- if ((!fieldRs) || VG_(sizeXA)(fieldRs) == 0) goto done; -+ if (((!fieldRs) || VG_(sizeXA)(fieldRs) == 0) -+ && (ty->Te.TyStOrUn.typeR == 0)) goto done; - for (i = 0; i < VG_(sizeXA)( fieldRs ); i++ ) { - fieldR = *(UWord*)VG_(indexXA)( fieldRs, i ); - field = ML_(TyEnts__index_by_cuOff)(tyents, NULL, fieldR); -@@ -831,8 +832,14 @@ - } - /* Did we find a suitable field? */ - vg_assert(i >= 0 && i <= VG_(sizeXA)( fieldRs )); -- if (i == VG_(sizeXA)( fieldRs )) -- goto done; /* No. Give up. */ -+ if (i == VG_(sizeXA)( fieldRs )) { -+ ty = ML_(TyEnts__index_by_cuOff)(tyents, NULL, -+ ty->Te.TyStOrUn.typeR); -+ vg_assert(ty); -+ if (ty->tag == Te_UNKNOWN) goto done; -+ vg_assert(ML_(TyEnt__is_type)(ty)); -+ continue; -+ } - /* Yes. 'field' is it. */ - vg_assert(field); - if (!field->Te.Field.name) goto done; -Index: coregrind/m_debuglog.c -=================================================================== ---- coregrind/m_debuglog.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_debuglog.c (.../trunk) (revision 13981) -@@ -103,6 +103,7 @@ - } - - #elif defined(VGP_amd64_linux) -+ - __attribute__((noinline)) - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { -@@ -267,6 +268,42 @@ - return __res; - } - -+#elif defined(VGP_arm64_linux) -+ -+static UInt local_sys_write_stderr ( const HChar* buf, Int n ) -+{ -+ volatile ULong block[2]; -+ block[0] = (ULong)buf; -+ block[1] = (ULong)n; -+ __asm__ volatile ( -+ "mov x0, #2\n\t" /* stderr */ -+ "ldr x1, [%0]\n\t" /* buf */ -+ "ldr x2, [%0, #8]\n\t" /* n */ -+ "mov x8, #"VG_STRINGIFY(__NR_write)"\n\t" -+ "svc 0x0\n" /* write() */ -+ "str x0, [%0]\n\t" -+ : -+ : "r" (block) -+ : "x0","x1","x2","x7" -+ ); -+ if (block[0] < 0) -+ block[0] = -1; -+ return (UInt)block[0]; -+} -+ -+static UInt local_sys_getpid ( void ) -+{ -+ UInt __res; -+ __asm__ volatile ( -+ "mov x8, #"VG_STRINGIFY(__NR_getpid)"\n" -+ "svc 0x0\n" /* getpid() */ -+ "mov %0, x0\n" -+ : "=r" (__res) -+ : -+ : "x0", "x8" ); -+ return (UInt)__res; -+} -+ - #elif defined(VGP_x86_darwin) - - /* We would use VG_DARWIN_SYSNO_TO_KERNEL instead of VG_DARWIN_SYSNO_INDEX -@@ -350,6 +387,7 @@ - } - - #elif defined(VGP_s390x_linux) -+ - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { - register Int r2 asm("2") = 2; /* file descriptor STDERR */ -@@ -391,6 +429,7 @@ - } - - #elif defined(VGP_mips32_linux) -+ - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { - volatile Int block[2]; -@@ -428,6 +467,7 @@ - } - - #elif defined(VGP_mips64_linux) -+ - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { - volatile Long block[2]; -Index: coregrind/m_dispatch/dispatch-arm64-linux.S -=================================================================== ---- coregrind/m_dispatch/dispatch-arm64-linux.S (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/m_dispatch/dispatch-arm64-linux.S (.../trunk) (revision 13981) -@@ -0,0 +1,241 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- The core dispatch loop, for jumping to a code address. ---*/ -+/*--- dispatch-arm64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_dispatch_asm.h" -+#include "pub_core_transtab_asm.h" -+#include "libvex_guest_offsets.h" /* for OFFSET_arm_R* */ -+ -+ -+/*------------------------------------------------------------*/ -+/*--- ---*/ -+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/ -+/*--- used to run all translations, ---*/ -+/*--- including no-redir ones. ---*/ -+/*--- ---*/ -+/*------------------------------------------------------------*/ -+ -+/*----------------------------------------------------*/ -+/*--- Entry and preamble (set everything up) ---*/ -+/*----------------------------------------------------*/ -+ -+/* signature: -+void VG_(disp_run_translations)( UWord* two_words, -+ void* guest_state, -+ Addr host_addr ); -+*/ -+.text -+.global VG_(disp_run_translations) -+VG_(disp_run_translations): -+ /* x0 holds two_words -+ x1 holds guest_state -+ x2 holds host_addr -+ */ -+ /* Push the callee-saved registers. Unclear if x19/x20 are -+ callee-saved, but be on the safe side. Note this sequence -+ maintains 16-alignment of sp. Also save x0 since it will -+ be needed in the postamble. */ -+ stp x29, x30, [sp, #-16]! -+ stp x27, x28, [sp, #-16]! -+ stp x25, x26, [sp, #-16]! -+ stp x23, x24, [sp, #-16]! -+ stp x21, x22, [sp, #-16]! -+ stp x19, x20, [sp, #-16]! -+ stp x0, xzr, [sp, #-16]! -+ -+ /* set FPSCR to vex-required default value */ -+ // FIXME -+ // mov r4, #0 -+ // fmxr fpscr, r4 -+ -+ /* Set up the guest state pointer */ -+ mov x21, x1 -+ -+ /* and jump into the code cache. Chained translations in -+ the code cache run, until for whatever reason, they can't -+ continue. When that happens, the translation in question -+ will jump (or call) to one of the continuation points -+ VG_(cp_...) below. */ -+ br x2 -+ /* NOTREACHED */ -+ -+/*----------------------------------------------------*/ -+/*--- Postamble and exit. ---*/ -+/*----------------------------------------------------*/ -+ -+postamble: -+ /* At this point, r1 and r2 contain two -+ words to be returned to the caller. r1 -+ holds a TRC value, and r2 optionally may -+ hold another word (for CHAIN_ME exits, the -+ address of the place to patch.) */ -+ -+ /* We're leaving. Check that nobody messed with -+ FPSCR in ways we don't expect. */ -+ // FIXME -+ // fmrx r4, fpscr -+ // bic r4, #0xF8000000 /* mask out NZCV and QC */ -+ // bic r4, #0x0000009F /* mask out IDC,IXC,UFC,OFC,DZC,IOC */ -+ // cmp r4, #0 -+ // beq remove_frame /* we're OK */ -+ /* otherwise we have an invariant violation */ -+ // movw r1, #VG_TRC_INVARIANT_FAILED -+ // movw r2, #0 -+ /* fall through */ -+ -+remove_frame: -+ /* Restore int regs, including importantly x0 (two_words), -+ but not x1 */ -+ ldp x0, xzr, [sp], #16 -+ ldp x19, x20, [sp], #16 -+ ldp x21, x22, [sp], #16 -+ ldp x23, x24, [sp], #16 -+ ldp x25, x26, [sp], #16 -+ ldp x27, x28, [sp], #16 -+ ldp x29, x30, [sp], #16 -+ -+ /* Stash return values */ -+ str x1, [x0, #0] -+ str x2, [x0, #8] -+ ret -+ -+/*----------------------------------------------------*/ -+/*--- Continuation points ---*/ -+/*----------------------------------------------------*/ -+ -+/* ------ Chain me to slow entry point ------ */ -+.global VG_(disp_cp_chain_me_to_slowEP) -+VG_(disp_cp_chain_me_to_slowEP): -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_S, RA) */ -+ mov x1, #VG_TRC_CHAIN_ME_TO_SLOW_EP -+ mov x2, x30 // 30 == LR -+ /* 4 = movw x9, disp_cp_chain_me_to_slowEP[15:0] -+ 4 = movk x9, disp_cp_chain_me_to_slowEP[31:16], lsl 16 -+ 4 = movk x9, disp_cp_chain_me_to_slowEP[47:32], lsl 32 -+ 4 = movk x9, disp_cp_chain_me_to_slowEP[63:48], lsl 48 -+ 4 = blr x9 -+ */ -+ sub x2, x2, #4+4+4+4+4 -+ b postamble -+ -+/* ------ Chain me to fast entry point ------ */ -+.global VG_(disp_cp_chain_me_to_fastEP) -+VG_(disp_cp_chain_me_to_fastEP): -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_F, RA) */ -+ mov x1, #VG_TRC_CHAIN_ME_TO_FAST_EP -+ mov x2, x30 // 30 == LR -+ /* 4 = movw x9, disp_cp_chain_me_to_fastEP[15:0] -+ 4 = movk x9, disp_cp_chain_me_to_fastEP[31:16], lsl 16 -+ 4 = movk x9, disp_cp_chain_me_to_fastEP[47:32], lsl 32 -+ 4 = movk x9, disp_cp_chain_me_to_fastEP[63:48], lsl 48 -+ 4 = blr x9 -+ */ -+ sub x2, x2, #4+4+4+4+4 -+ b postamble -+ -+/* ------ Indirect but boring jump ------ */ -+.global VG_(disp_cp_xindir) -+VG_(disp_cp_xindir): -+ /* Where are we going? */ -+ ldr x0, [x21, #OFFSET_arm64_PC] -+ -+ /* stats only */ -+ adrp x1, VG_(stats__n_xindirs_32) -+ add x1, x1, :lo12:VG_(stats__n_xindirs_32) -+ ldr w2, [x1, #0] -+ add w2, w2, #1 -+ str w2, [x1, #0] -+ -+ /* try a fast lookup in the translation cache */ -+ // x0 = next guest, x1,x2,x3,x4 scratch -+ mov x1, #VG_TT_FAST_MASK // x1 = VG_TT_FAST_MASK -+ and x2, x1, x0, LSR #2 // x2 = entry # = (x1 & (x0 >> 2)) -+ -+ adrp x4, VG_(tt_fast) -+ add x4, x4, :lo12:VG_(tt_fast) // x4 = &VG_(tt_fast) -+ -+ add x1, x4, x2, LSL #4 // r1 = &tt_fast[entry#] -+ -+ ldp x4, x5, [x1, #0] // x4 = .guest, x5 = .host -+ -+ cmp x4, x0 -+ -+ // jump to host if lookup succeeded -+ bne fast_lookup_failed -+ br x5 -+ /*NOTREACHED*/ -+ -+fast_lookup_failed: -+ /* RM ME -- stats only */ -+ adrp x1, VG_(stats__n_xindir_misses_32) -+ add x1, x1, :lo12:VG_(stats__n_xindir_misses_32) -+ ldr w2, [x1, #0] -+ add w2, w2, #1 -+ str w2, [x1, #0] -+ -+ mov x1, #VG_TRC_INNER_FASTMISS -+ mov x2, #0 -+ b postamble -+ -+/* ------ Assisted jump ------ */ -+.global VG_(disp_cp_xassisted) -+VG_(disp_cp_xassisted): -+ /* x21 contains the TRC */ -+ mov x1, x21 -+ mov x2, #0 -+ b postamble -+ -+/* ------ Event check failed ------ */ -+.global VG_(disp_cp_evcheck_fail) -+VG_(disp_cp_evcheck_fail): -+ mov x1, #VG_TRC_INNER_COUNTERZERO -+ mov x2, #0 -+ b postamble -+ -+ -+.size VG_(disp_run_translations), .-VG_(disp_run_translations) -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",%progbits -+ -+#endif // defined(VGP_arm64_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end dispatch-arm64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_gdbserver/README_DEVELOPERS -=================================================================== ---- coregrind/m_gdbserver/README_DEVELOPERS (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_gdbserver/README_DEVELOPERS (.../trunk) (revision 13981) -@@ -165,7 +165,7 @@ - by valgrind. If not, vgdb will force the invocation of the gdbserver - code inside the valgrind process. - --This forced invocation is implemented using the ptrace system call: -+On Linux, this forced invocation is implemented using the ptrace system call: - using ptrace, vgdb will cause the valgrind process to call the - gdbserver code. - -@@ -260,7 +260,7 @@ - and 'const char *expedite_regs' are build from files - in the gdb sources, e.g. for an new arch hal9000 - cd gdb/regformats -- ./regdat.sh reg-hal9000.dat hal9000 -+ sh ./regdat.sh reg-hal9000.dat hal9000 - - From the generated file hal9000, you copy/paste in - valgrind-low-hal9000.c the two needed data structures and change their -@@ -272,10 +272,12 @@ - Optional but heavily recommended: - To have a proper wake up of a Valgrind process with all threads - blocked in a system call, some architecture specific code --has to be done in vgdb.c : search for PTRACEINVOKER processor symbol --to see what has to be completed. -+has to be done in vgdb-invoker-*.c. -+Typically, for a linux system supporting ptrace, you have to modify -+vgdb-invoker-ptrace.c. - --For Linux based platforms, all the ptrace calls should be ok. -+For Linux based platforms, all the ptrace calls in vgdb-invoker-ptrace.c -+should be ok. - The only thing needed is the code needed to "push a dummy call" on the stack, - i.e. assign the relevant registers in the struct user_regs_struct, and push - values on the stack according to the ABI. -@@ -337,7 +339,6 @@ - (such as search leaks)? - - -- - * currently jump(s) and inferior call(s) are somewhat dangerous - when called from a block not yet instrumented : instead - of continuing till the next Imark, where there will be a -Index: coregrind/m_gdbserver/m_gdbserver.c -=================================================================== ---- coregrind/m_gdbserver/m_gdbserver.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_gdbserver/m_gdbserver.c (.../trunk) (revision 13981) -@@ -219,15 +219,19 @@ - VG_(HT_add_node)(gs_addresses, p); - /* It should be sufficient to discard a range of 1. - We use 2 to ensure the below is not sensitive to the presence -- of thumb bit in the range of addresses to discard. */ -- VG_(discard_translations) (addr, 2, from); -+ of thumb bit in the range of addresses to discard. -+ No need to discard translations for Vg_VgdbFull as all -+ instructions are in any case vgdb-instrumented. */ -+ if (VG_(clo_vgdb) != Vg_VgdbFull) -+ VG_(discard_translations) (addr, 2, from); - } - - static void remove_gs_address (GS_Address* g, const HChar* from) - { - VG_(HT_remove) (gs_addresses, g->addr); -- // See add_gs_address for the explanation for the range 2 below. -- VG_(discard_translations) (g->addr, 2, from); -+ // See add_gs_address for the explanation for condition and the range 2 below. -+ if (VG_(clo_vgdb) != Vg_VgdbFull) -+ VG_(discard_translations) (g->addr, 2, from); - VG_(arena_free) (VG_AR_CORE, g); - } - -@@ -584,11 +588,22 @@ - invalidate_if_jump_not_yet_gdbserved (VG_(get_IP) (tid), who); - } - -+Bool VG_(gdbserver_init_done) (void) -+{ -+ return gdbserver_called > 0; -+} -+ -+Bool VG_(gdbserver_stop_at) (VgdbStopAt stopat) -+{ -+ return gdbserver_called > 0 && VgdbStopAtiS(stopat, VG_(clo_vgdb_stop_at)); -+} -+ - void VG_(gdbserver_prerun_action) (ThreadId tid) - { - // Using VG_(dyn_vgdb_error) allows the user to control if gdbserver - // stops after a fork. -- if (VG_(dyn_vgdb_error) == 0) { -+ if (VG_(dyn_vgdb_error) == 0 -+ || VgdbStopAtiS(VgdbStopAt_Startup, VG_(clo_vgdb_stop_at))) { - /* The below call allows gdb to attach at startup - before the first guest instruction is executed. */ - VG_(umsg)("(action at startup) vgdb me ... \n"); -@@ -908,7 +923,11 @@ - switch (remote_desc_activity("VG_(gdbserver_activity)")) { - case 0: ret = False; break; - case 1: ret = True; break; -- case 2: call_gdbserver (tid, init_reason); ret = False; break; -+ case 2: -+ remote_finish(reset_after_error); -+ call_gdbserver (tid, init_reason); -+ ret = False; -+ break; - default: vg_assert (0); - } - busy--; -@@ -1385,7 +1404,7 @@ - return False; - } - --void VG_(strtok_get_address_and_size) (Addr* address, -+Bool VG_(strtok_get_address_and_size) (Addr* address, - SizeT* szB, - HChar **ssaveptr) - { -@@ -1400,7 +1419,7 @@ - VG_(gdb_printf) ("missing or malformed address\n"); - *address = (Addr) 0; - *szB = 0; -- return; -+ return False; - } - ws = VG_(strtok_r) (NULL, " ", ssaveptr); - if (ws == NULL) { -@@ -1432,8 +1451,9 @@ - "hex 0x..... or dec ...... or binary .....b\n"); - *address = (Addr) 0; - *szB = 0; -- return; -+ return False; - } -+ return True; - } - - void VG_(gdbserver_status_output)(void) -@@ -1449,7 +1469,8 @@ - "interrupts intr_tid %d gs_non_busy %d gs_busy %d tid_non_intr %d\n" - "gdbserved addresses %d (-1 = not initialized)\n" - "watchpoints %d (-1 = not initialized)\n" -- "vgdb-error %d\n", -+ "vgdb-error %d\n" -+ "hostvisibility %s\n", - gdbserver_called, - valgrind_single_stepping(), - -@@ -1460,5 +1481,6 @@ - - nr_gdbserved_addresses, - nr_watchpoints, -- VG_(dyn_vgdb_error)); -+ VG_(dyn_vgdb_error), -+ hostvisibility ? "yes" : "no"); - } -Index: coregrind/m_gdbserver/remote-utils.c -=================================================================== ---- coregrind/m_gdbserver/remote-utils.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_gdbserver/remote-utils.c (.../trunk) (revision 13981) -@@ -33,6 +33,66 @@ - #include - # endif - -+/* Calls sr_perror with msg. -+ Outputs more information about Valgrind state if verbosity > 0 -+ or debuglog_getlevel > 0. */ -+static -+void sr_extended_perror (SysRes sr, const HChar *msg) -+{ -+ sr_perror (sr, "%s", msg); -+ if (VG_(clo_verbosity) > 0 || VG_(debugLog_getLevel)() >= 1) { -+ Int i; -+ vki_sigset_t cursigset; -+ VG_(show_sched_status) (True, // host_stacktrace -+ True, // valgrind_stack_usage -+ True); // exited_threads -+ VG_(sigprocmask) (0, // dummy how. -+ NULL, // do not change the sigmask -+ &cursigset); // -+ VG_(dmsg)("current sigmask value { "); -+ for (i = 1; i <= _VKI_NSIG; i++) { -+ if (VG_(sigismember)(&cursigset, i)) -+ VG_(dmsg)("%u ", i); -+ } -+ VG_(dmsg)("}\n"); -+ } -+} -+ -+/* Calls VG_(poll) with given arguments. If VG_(poll) fails due to EINTR, -+ restarts the syscall. -+ Normally, VG_(poll) gdbsrv syscalls are not supposed to be interrupted : -+ either gdbsrv has been called by the scheduler (so all async signals -+ are masked) -+ or gdbsrv has been forced invoked by vgdb+ptrace, and vgdb is queuing -+ the signals. -+ -+ However, on old kernels (such as on RHEL5.5 2.6.18), when vgdb+ptrace -+ intercepts and queues an async signal, the poll syscall is not properly -+ restarted. Instead, it returns EINTR even if no signal was effectively -+ received by the ptraced process. -+ See red-hat "Bug 679129 - Change in behaviour between RH5.5 and RH6 -+ with ptrace and syscalls bugzilla" -+ e.g. "Why rhel5 differs? Because unlike in rhel6, sys_poll() returns -+ -EINTR if interrupted, that is all. This old implementation does -+ not support the restart-if-eintr-is-spurious." -+ -+ So in case VG_(poll) fails with EINTR, we retry. */ -+static SysRes VG_(poll_no_eintr) (struct vki_pollfd *fds, Int nfds, Int timeout) -+{ -+ const HChar* msg = "VG_(poll) failed (old kernel ?) retrying ... \n"; -+ SysRes sr; -+ do { -+ sr = VG_(poll) (fds, nfds, timeout); -+ if (!sr_isError(sr) || sr_Err(sr) != VKI_EINTR) -+ return sr; -+ sr_perror (sr, "%s", msg); -+ if (VG_(debugLog_getLevel)() >= 1) { -+ sr_extended_perror (sr, msg); -+ } -+ } while (1); -+ /*NOTREACHED*/ -+} -+ - Bool noack_mode; - - static int readchar (int single); -@@ -39,12 +99,12 @@ - - void remote_utils_output_status(void); - --static int remote_desc; -+#define INVALID_DESCRIPTOR -1 -+static int remote_desc = INVALID_DESCRIPTOR; - - static VgdbShared *shared; - static int last_looked_cntr = -1; - static struct vki_pollfd remote_desc_pollfdread_activity; --#define INVALID_DESCRIPTOR -1 - - /* for a gdbserver embedded in valgrind, we read from a FIFO and write - to another FIFO So, we need two descriptors */ -@@ -157,22 +217,27 @@ - - /* Ensures we have a valid write file descriptor. - Returns 1 if we have a valid write file descriptor, -- 0 if the write fd could not be opened. */ -+ 0 if the write fd is not valid/cannot be opened. */ - static - int ensure_write_remote_desc(void) - { - struct vki_pollfd write_remote_desc_ok; -- int ret; -+ SysRes ret; - if (write_remote_desc != INVALID_DESCRIPTOR) { - write_remote_desc_ok.fd = write_remote_desc; - write_remote_desc_ok.events = VKI_POLLOUT; - write_remote_desc_ok.revents = 0; -- ret = VG_(poll)(&write_remote_desc_ok, 1, 0); -- if (ret && poll_cond(write_remote_desc_ok.revents)) { -- dlog(1, "POLLcond %d closing write_remote_desc %d\n", -- write_remote_desc_ok.revents, write_remote_desc); -- VG_(close) (write_remote_desc); -- write_remote_desc = INVALID_DESCRIPTOR; -+ ret = VG_(poll_no_eintr)(&write_remote_desc_ok, 1, 0); -+ if (sr_isError(ret) -+ || (sr_Res(ret) > 0 && poll_cond(write_remote_desc_ok.revents))) { -+ if (sr_isError(ret)) { -+ sr_extended_perror(ret, "ensure_write_remote_desc: poll error\n"); -+ } else { -+ dlog(0, "POLLcond %d closing write_remote_desc %d\n", -+ write_remote_desc_ok.revents, write_remote_desc); -+ } -+ VG_(close) (write_remote_desc); -+ write_remote_desc = INVALID_DESCRIPTOR; - } - } - if (write_remote_desc == INVALID_DESCRIPTOR) { -@@ -229,7 +294,6 @@ - offsetof(ThreadState, os_state) + offsetof(ThreadOSstate, lwpid), - 0}; - const int pid = VG_(getpid)(); -- const int name_default = strcmp(name, VG_(vgdb_prefix_default)()) == 0; - Addr addr_shared; - SysRes o; - int shared_mem_fd = INVALID_DESCRIPTOR; -@@ -268,23 +332,26 @@ - VG_(umsg)("TO CONTROL THIS PROCESS USING vgdb (which you probably\n" - "don't want to do, unless you know exactly what you're doing,\n" - "or are doing some strange experiment):\n" -- " %s/../../bin/vgdb --pid=%d%s%s ...command...\n", -+ " %s/../../bin/vgdb%s%s --pid=%d ...command...\n", - VG_(libdir), -- pid, (name_default ? "" : " --vgdb-prefix="), -- (name_default ? "" : name)); -+ (VG_(arg_vgdb_prefix) ? " " : ""), -+ (VG_(arg_vgdb_prefix) ? VG_(arg_vgdb_prefix) : ""), -+ pid); - } - if (VG_(clo_verbosity) > 1 -- || VG_(clo_vgdb_error) < 999999999) { -+ || VG_(clo_vgdb_error) < 999999999 -+ || VG_(clo_vgdb_stop_at) != 0) { - VG_(umsg)("\n"); - VG_(umsg)( - "TO DEBUG THIS PROCESS USING GDB: start GDB like this\n" - " /path/to/gdb %s\n" - "and then give GDB the following command\n" -- " target remote | %s/../../bin/vgdb --pid=%d%s%s\n", -+ " target remote | %s/../../bin/vgdb%s%s --pid=%d\n", - VG_(args_the_exename), - VG_(libdir), -- pid, (name_default ? "" : " --vgdb-prefix="), -- (name_default ? "" : name) -+ (VG_(arg_vgdb_prefix) ? " " : ""), -+ (VG_(arg_vgdb_prefix) ? VG_(arg_vgdb_prefix) : ""), -+ pid - ); - VG_(umsg)("--pid is optional if only one valgrind process is running\n"); - VG_(umsg)("\n"); -@@ -334,15 +401,17 @@ - VG_(close) (shared_mem_fd); - } - -- /* we open the read side FIFO in non blocking mode -- We then set the fd in blocking mode. -- Opening in non-blocking read mode always succeeds while opening -- in non-blocking write mode succeeds only if the fifo is already -- opened in read mode. So, we wait till we have read the first -- character from the read side before opening the write side. */ -- remote_desc = open_fifo ("read", from_gdb, VKI_O_RDONLY|VKI_O_NONBLOCK); -- save_fcntl_flags = VG_(fcntl) (remote_desc, VKI_F_GETFL, 0); -- VG_(fcntl) (remote_desc, VKI_F_SETFL, save_fcntl_flags & ~VKI_O_NONBLOCK); -+ if (remote_desc == INVALID_DESCRIPTOR) { -+ /* we open the read side FIFO in non blocking mode -+ We then set the fd in blocking mode. -+ Opening in non-blocking read mode always succeeds while opening -+ in non-blocking write mode succeeds only if the fifo is already -+ opened in read mode. So, we wait till we have read the first -+ character from the read side before opening the write side. */ -+ remote_desc = open_fifo ("read", from_gdb, VKI_O_RDONLY|VKI_O_NONBLOCK); -+ save_fcntl_flags = VG_(fcntl) (remote_desc, VKI_F_GETFL, 0); -+ VG_(fcntl) (remote_desc, VKI_F_SETFL, save_fcntl_flags & ~VKI_O_NONBLOCK); -+ } - remote_desc_pollfdread_activity.fd = remote_desc; - remote_desc_pollfdread_activity.events = VKI_POLLIN; - remote_desc_pollfdread_activity.revents = 0; -@@ -357,7 +426,10 @@ - time to let a proper cleanup to be donex */ - void sync_gdb_connection(void) - { -- VG_(poll)(0, 0, 100); -+ SysRes ret; -+ ret = VG_(poll_no_eintr)(0, 0, 100); -+ if (sr_isError(ret)) -+ sr_extended_perror(ret, "sync_gdb_connection: poll error\n"); - } - - static -@@ -379,13 +451,19 @@ - if (write_remote_desc != INVALID_DESCRIPTOR) - VG_(close) (write_remote_desc); - write_remote_desc = INVALID_DESCRIPTOR; -- if (remote_desc != INVALID_DESCRIPTOR) { -+ -+ if (remote_desc != INVALID_DESCRIPTOR && reason != reset_after_error) { -+ /* Fully close the connection, either due to orderly_finish or -+ to reset_after_fork. -+ For reset_after_error, keep the reading side opened, to always be -+ ready to accept new vgdb connection. */ -+ vg_assert (reason == reset_after_fork || reason == orderly_finish); - remote_desc_pollfdread_activity.fd = INVALID_DESCRIPTOR; - remote_desc_pollfdread_activity.events = 0; - remote_desc_pollfdread_activity.revents = 0; - VG_(close) (remote_desc); -+ remote_desc = INVALID_DESCRIPTOR; - } -- remote_desc = INVALID_DESCRIPTOR; - noack_mode = False; - - /* ensure the child will create its own FIFOs */ -@@ -401,21 +479,23 @@ - { - const int pid = VG_(getpid)(); - remote_finish(orderly_finish); -- if (pid == pid_from_to_creator) { -- dlog(1, "unlinking\n %s\n %s\n %s\n", -- from_gdb, to_gdb, shared_mem); -- if (VG_(unlink) (from_gdb) == -1) -- warning ("could not unlink %s\n", from_gdb); -- if (VG_(unlink) (to_gdb) == -1) -- warning ("could not unlink %s\n", to_gdb); -- if (VG_(unlink) (shared_mem) == -1) -- warning ("could not unlink %s\n", shared_mem); -- } -- else { -- dlog(1, "not creator => not unlinking %s and %s\n", from_gdb, to_gdb); -- } -+ dlog(1, "%d (creator %d) maybe unlinking \n %s\n %s\n %s\n", -+ pid, pid_from_to_creator, -+ from_gdb ? from_gdb : "NULL", -+ to_gdb ? to_gdb : "NULL", -+ shared_mem ? shared_mem : "NULL"); -+ if (pid == pid_from_to_creator && from_gdb && VG_(unlink) (from_gdb) == -1) -+ warning ("could not unlink %s\n", from_gdb); -+ if (pid == pid_from_to_creator && to_gdb && VG_(unlink) (to_gdb) == -1) -+ warning ("could not unlink %s\n", to_gdb); -+ if (pid == pid_from_to_creator && shared_mem && VG_(unlink) (shared_mem) == -1) -+ warning ("could not unlink %s\n", shared_mem); - free (from_gdb); -+ from_gdb = NULL; - free (to_gdb); -+ to_gdb = NULL; -+ free (shared_mem); -+ shared_mem = NULL; - } - - Bool remote_connected(void) -@@ -439,10 +519,10 @@ - counter values maintained in shared memory by vgdb. */ - int remote_desc_activity(const char *msg) - { -- int ret; -+ int retval; -+ SysRes ret; - const int looking_at = shared->written_by_vgdb; - if (shared->seen_by_valgrind == looking_at) -- // if (last_looked_cntr == looking_at) - return 0; - if (remote_desc == INVALID_DESCRIPTOR) - return 0; -@@ -449,24 +529,31 @@ - - /* poll the remote desc */ - remote_desc_pollfdread_activity.revents = 0; -- ret = VG_(poll) (&remote_desc_pollfdread_activity, 1, 0); -- if (ret && poll_cond(remote_desc_pollfdread_activity.revents)) { -- dlog(1, "POLLcond %d remote_desc_pollfdread %d\n", -- remote_desc_pollfdread_activity.revents, remote_desc); -- error_poll_cond(); -- ret = 2; -+ ret = VG_(poll_no_eintr) (&remote_desc_pollfdread_activity, 1, 0); -+ if (sr_isError(ret) -+ || (sr_Res(ret) && poll_cond(remote_desc_pollfdread_activity.revents))) { -+ if (sr_isError(ret)) { -+ sr_extended_perror(ret, "remote_desc_activity: poll error\n"); -+ } else { -+ dlog(0, "POLLcond %d remote_desc_pollfdread %d\n", -+ remote_desc_pollfdread_activity.revents, remote_desc); -+ error_poll_cond(); -+ } -+ retval = 2; -+ } else { -+ retval = sr_Res(ret); - } - dlog(1, - "remote_desc_activity %s %d last_looked_cntr %d looking_at %d" - " shared->written_by_vgdb %d shared->seen_by_valgrind %d" -- " ret %d\n", -+ " retval %d\n", - msg, remote_desc, last_looked_cntr, looking_at, - shared->written_by_vgdb, shared->seen_by_valgrind, -- ret); -+ retval); - /* if no error from poll, indicate we have "seen" up to looking_at */ -- if (ret != 2) -+ if (retval == 1) - last_looked_cntr = looking_at; -- return ret; -+ return retval; - } - - /* Convert hex digit A to a number. */ -@@ -803,7 +890,7 @@ - static unsigned char buf[PBUFSIZ]; - static int bufcnt = 0; - static unsigned char *bufp; -- int ret; -+ SysRes ret; - - if (bufcnt-- > 0) - return *bufp++; -@@ -814,10 +901,14 @@ - /* No characters available in buf => - wait for some characters to arrive */ - remote_desc_pollfdread_activity.revents = 0; -- ret = VG_(poll)(&remote_desc_pollfdread_activity, 1, -1); -- if (ret != 1) { -- dlog(0, "readchar: poll got %d\n", ret); -- return -1; -+ ret = VG_(poll_no_eintr)(&remote_desc_pollfdread_activity, 1, -1); -+ if (sr_isError(ret) || sr_Res(ret) != 1) { -+ if (sr_isError(ret)) { -+ sr_extended_perror(ret, "readchar: poll error\n"); -+ } else { -+ dlog(0, "readchar: poll got %d, expecting 1\n", (int)sr_Res(ret)); -+ } -+ return -1; - } - if (single) - bufcnt = VG_(read) (remote_desc, buf, 1); -@@ -1103,7 +1194,7 @@ - } - - --/* Return the path prefix for the named pipes (FIFOs) used by vgdb/gdb -+/* Return the default path prefix for the named pipes (FIFOs) used by vgdb/gdb - to communicate with valgrind */ - HChar * - VG_(vgdb_prefix_default)(void) -Index: coregrind/m_gdbserver/server.c -=================================================================== ---- coregrind/m_gdbserver/server.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_gdbserver/server.c (.../trunk) (revision 13981) -@@ -30,6 +30,9 @@ - #include "pub_core_execontext.h" - #include "pub_core_syswrap.h" // VG_(show_open_fds) - #include "pub_core_scheduler.h" -+#include "pub_core_transtab.h" -+#include "pub_core_debuginfo.h" -+#include "pub_core_addrinfo.h" - - unsigned long cont_thread; - unsigned long general_thread; -@@ -118,7 +121,6 @@ - void kill_request (const char *msg) - { - VG_(umsg) ("%s", msg); -- remote_close(); - VG_(exit) (0); - } - -@@ -147,6 +149,30 @@ - return s; - } - -+void VG_(print_all_stats) (Bool memory_stats, Bool tool_stats) -+{ -+ if (memory_stats) { -+ VG_(message)(Vg_DebugMsg, "\n"); -+ VG_(message)(Vg_DebugMsg, -+ "------ Valgrind's internal memory use stats follow ------\n" ); -+ VG_(sanity_check_malloc_all)(); -+ VG_(message)(Vg_DebugMsg, "------\n" ); -+ VG_(print_all_arena_stats)(); -+ if (VG_(clo_profile_heap)) -+ VG_(print_arena_cc_analysis) (); -+ VG_(message)(Vg_DebugMsg, "\n"); -+ } -+ -+ VG_(print_translation_stats)(); -+ VG_(print_tt_tc_stats)(); -+ VG_(print_scheduler_stats)(); -+ VG_(print_ExeContext_stats)( False /* with_stacktraces */ ); -+ VG_(print_errormgr_stats)(); -+ if (tool_stats && VG_(needs).print_stats) { -+ VG_TDICT_CALL(tool_print_stats); -+ } -+} -+ - /* handle_gdb_valgrind_command handles the provided mon string command. - If command is recognised, return 1 else return 0. - Note that in case of ambiguous command, 1 is returned. -@@ -200,6 +226,7 @@ - " v.wait [] : sleep (default 0) then continue\n" - " v.info all_errors : show all errors found so far\n" - " v.info last_error : show last error found\n" -+" v.info location : show information about location \n" - " v.info n_errs_found [msg] : show the nr of errors found so far and the given msg\n" - " v.info open_fds : show open file descriptors (only if --track-fds=yes)\n" - " v.kill : kill the Valgrind process\n" -@@ -216,7 +243,10 @@ - " (with aspacemgr arg, also shows valgrind segments on log ouput)\n" - " v.info exectxt : show stacktraces and stats of all execontexts\n" - " v.info scheduler : show valgrind thread state and stacktrace\n" -+" v.info stats : show various valgrind and tool stats\n" - " v.set debuglog : set valgrind debug log level to \n" -+" v.set hostvisibility [yes*|no] : (en/dis)ables access by gdb/gdbserver to\n" -+" Valgrind internal host status/memory\n" - " v.translate [] : debug translation of with \n" - " (default traceflags 0b00100000 : show after instrumentation)\n" - " An additional flag 0b100000000 allows to show gdbserver instrumentation\n"); -@@ -227,7 +257,7 @@ - wcmd = strtok_r (NULL, " ", &ssaveptr); - switch (kwdid = VG_(keyword_id) - ("vgdb-error debuglog merge-recursive-frames" -- " gdb_output log_output mixed_output", -+ " gdb_output log_output mixed_output hostvisibility ", - wcmd, kwd_report_all)) { - case -2: - case -1: -@@ -279,6 +309,32 @@ - VG_(gdb_printf) - ("valgrind output will go to log, interactive output will go to gdb\n"); - break; -+ case 6: /* hostvisibility */ -+ wcmd = strtok_r (NULL, " ", &ssaveptr); -+ if (wcmd != NULL) { -+ switch (VG_(keyword_id) ("yes no", wcmd, kwd_report_all)) { -+ case -2: -+ case -1: break; -+ case 0: -+ hostvisibility = True; -+ break; -+ case 1: -+ hostvisibility = False; -+ break; -+ default: tl_assert (0); -+ } -+ } else { -+ hostvisibility = True; -+ } -+ if (hostvisibility) -+ VG_(gdb_printf) -+ ("Enabled access to Valgrind memory/status by GDB\n" -+ "If not yet done, tell GDB which valgrind file(s) to use:\n" -+ "add-symbol-file \n"); -+ else -+ VG_(gdb_printf) -+ ("Disabled access to Valgrind memory/status by GDB\n"); -+ break; - default: - vg_assert (0); - } -@@ -288,7 +344,7 @@ - wcmd = strtok_r (NULL, " ", &ssaveptr); - switch (kwdid = VG_(keyword_id) - ("all_errors n_errs_found last_error gdbserver_status memory" -- " scheduler open_fds exectxt", -+ " scheduler stats open_fds exectxt location", - wcmd, kwd_report_all)) { - case -2: - case -1: -@@ -311,6 +367,8 @@ - VG_(gdbserver_status_output)(); - break; - case 4: /* memory */ -+ VG_(printf) ("%llu bytes have already been allocated.\n", -+ VG_(am_get_anonsize_total)()); - VG_(print_all_arena_stats) (); - if (VG_(clo_profile_heap)) - VG_(print_arena_cc_analysis) (); -@@ -329,10 +387,17 @@ - ret = 1; - break; - case 5: /* scheduler */ -- VG_(show_sched_status) (); -+ VG_(show_sched_status) (True, // host_stacktrace -+ True, // valgrind_stack_usage -+ True); // exited_threads - ret = 1; - break; -- case 6: /* open_fds */ -+ case 6: /* stats */ -+ VG_(print_all_stats)(False, /* Memory stats */ -+ True /* Tool stats */); -+ ret = 1; -+ break; -+ case 7: /* open_fds */ - if (VG_(clo_track_fds)) - VG_(show_open_fds) (""); - else -@@ -341,10 +406,35 @@ - " to show open fds\n"); - ret = 1; - break; -- case 7: /* exectxt */ -+ case 8: /* exectxt */ - VG_(print_ExeContext_stats) (True /* with_stacktraces */); - ret = 1; - break; -+ case 9: { /* location */ -+ /* Note: we prefer 'v.info location' and not 'v.info address' as -+ v.info address is inconsistent with the GDB (native) -+ command 'info address' which gives the address for a symbol. -+ GDB equivalent command of 'v.info location' is 'info symbol'. */ -+ Addr address; -+ SizeT dummy_sz = 0x1234; -+ if (VG_(strtok_get_address_and_size) (&address, &dummy_sz, &ssaveptr)) { -+ // If tool provides location information, use that. -+ if (VG_(needs).info_location) { -+ VG_TDICT_CALL(tool_info_location, address); -+ } -+ // If tool does not provide location information, use the common one. -+ // Also use the common to compare with tool when debug log is set. -+ if (!VG_(needs).info_location || VG_(debugLog_getLevel)() > 0 ) { -+ AddrInfo ai; -+ ai.tag = Addr_Undescribed; -+ VG_(describe_addr) (address, &ai); -+ VG_(pp_addrinfo) (address, &ai); -+ VG_(clear_addrinfo) (&ai); -+ } -+ } -+ ret = 1; -+ break; -+ } - default: - vg_assert(0); - } -@@ -369,8 +459,7 @@ - - ret = 1; - -- VG_(strtok_get_address_and_size) (&address, &verbosity, &ssaveptr); -- if (address != (Addr) 0 || verbosity != 0) { -+ if (VG_(strtok_get_address_and_size) (&address, &verbosity, &ssaveptr)) { - /* we need to force the output to log for the translation trace, - as low level VEX tracing cannot be redirected to gdb. */ - int saved_command_output_to_log = command_output_to_log; -Index: coregrind/m_gdbserver/target.c -=================================================================== ---- coregrind/m_gdbserver/target.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_gdbserver/target.c (.../trunk) (revision 13981) -@@ -446,46 +446,58 @@ - usr_store_inferior_registers (regno); - } - -+Bool hostvisibility = False; -+ - int valgrind_read_memory (CORE_ADDR memaddr, unsigned char *myaddr, int len) - { - const void *sourceaddr = C2v (memaddr); - dlog(2, "reading memory %p size %d\n", sourceaddr, len); -- if (!VG_(am_is_valid_for_client_or_free_or_resvn) ((Addr) sourceaddr, -- len, VKI_PROT_READ)) { -+ if (VG_(am_is_valid_for_client) ((Addr) sourceaddr, -+ len, VKI_PROT_READ) -+ || (hostvisibility -+ && VG_(am_is_valid_for_valgrind) ((Addr) sourceaddr, -+ len, VKI_PROT_READ))) { -+ VG_(memcpy) (myaddr, sourceaddr, len); -+ return 0; -+ } else { - dlog(1, "error reading memory %p size %d\n", sourceaddr, len); - return -1; - } -- VG_(memcpy) (myaddr, sourceaddr, len); -- return 0; - } - - int valgrind_write_memory (CORE_ADDR memaddr, const unsigned char *myaddr, int len) - { -+ Bool is_valid_client_memory; - void *targetaddr = C2v (memaddr); - dlog(2, "writing memory %p size %d\n", targetaddr, len); -- if (!VG_(am_is_valid_for_client_or_free_or_resvn) ((Addr)targetaddr, -- len, VKI_PROT_WRITE)) { -+ is_valid_client_memory -+ = VG_(am_is_valid_for_client) ((Addr)targetaddr, len, VKI_PROT_WRITE); -+ if (is_valid_client_memory -+ || (hostvisibility -+ && VG_(am_is_valid_for_valgrind) ((Addr) targetaddr, -+ len, VKI_PROT_READ))) { -+ if (len > 0) { -+ VG_(memcpy) (targetaddr, myaddr, len); -+ if (is_valid_client_memory && VG_(tdict).track_post_mem_write) { -+ /* Inform the tool of the post memwrite. Note that we do the -+ minimum necessary to avoid complains from e.g. -+ memcheck. The idea is that the debugger is as least -+ intrusive as possible. So, we do not inform of the pre -+ mem write (and in any case, this would cause problems with -+ memcheck that does not like our CorePart in -+ pre_mem_write. */ -+ ThreadState *tst = -+ (ThreadState *) inferior_target_data (current_inferior); -+ ThreadId tid = tst->tid; -+ VG_(tdict).track_post_mem_write( Vg_CoreClientReq, tid, -+ (Addr) targetaddr, len ); -+ } -+ } -+ return 0; -+ } else { - dlog(1, "error writing memory %p size %d\n", targetaddr, len); - return -1; - } -- if (len > 0) { -- VG_(memcpy) (targetaddr, myaddr, len); -- if (VG_(tdict).track_post_mem_write) { -- /* Inform the tool of the post memwrite. Note that we do the -- minimum necessary to avoid complains from e.g. -- memcheck. The idea is that the debugger is as least -- intrusive as possible. So, we do not inform of the pre -- mem write (and in any case, this would cause problems with -- memcheck that does not like our CorePart in -- pre_mem_write. */ -- ThreadState *tst = -- (ThreadState *) inferior_target_data (current_inferior); -- ThreadId tid = tst->tid; -- VG_(tdict).track_post_mem_write( Vg_CoreClientReq, tid, -- (Addr) targetaddr, len ); -- } -- } -- return 0; - } - - /* insert or remove a breakpoint */ -@@ -641,6 +653,8 @@ - amd64_init_architecture(&the_low_target); - #elif defined(VGA_arm) - arm_init_architecture(&the_low_target); -+#elif defined(VGA_arm64) -+ arm64_init_architecture(&the_low_target); - #elif defined(VGA_ppc32) - ppc32_init_architecture(&the_low_target); - #elif defined(VGA_ppc64) -@@ -652,6 +666,6 @@ - #elif defined(VGA_mips64) - mips64_init_architecture(&the_low_target); - #else -- architecture missing in target.c valgrind_initialize_target -+ #error "architecture missing in target.c valgrind_initialize_target" - #endif - } -Index: coregrind/m_gdbserver/target.h -=================================================================== ---- coregrind/m_gdbserver/target.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_gdbserver/target.h (.../trunk) (revision 13981) -@@ -233,5 +233,8 @@ - Bool *mod); - - -+// True means gdbserver can access (internal) Valgrind memory. -+// Otherwise, only the client memory can be accessed. -+extern Bool hostvisibility; - - #endif /* TARGET_H */ -Index: coregrind/m_gdbserver/valgrind-low-arm64.c -=================================================================== ---- coregrind/m_gdbserver/valgrind-low-arm64.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/m_gdbserver/valgrind-low-arm64.c (.../trunk) (revision 13981) -@@ -0,0 +1,256 @@ -+/* Low level interface to valgrind, for the remote server for GDB integrated -+ in valgrind. -+ Copyright (C) 2014 -+ Free Software Foundation, Inc. -+ -+ This file is part of VALGRIND. -+ It has been inspired from a file from gdbserver in gdb 6.6. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, -+ Boston, MA 02110-1301, USA. */ -+ -+#include "server.h" -+#include "target.h" -+#include "regdef.h" -+#include "regcache.h" -+ -+#include "pub_core_aspacemgr.h" -+#include "pub_core_machine.h" -+#include "pub_core_threadstate.h" -+#include "pub_core_transtab.h" -+#include "pub_core_gdbserver.h" -+#include "pub_core_debuginfo.h" -+ -+#include "valgrind_low.h" -+ -+#include "libvex_guest_arm64.h" -+ -+static struct reg regs[] = { -+ { "x0", 0, 64 }, -+ { "x1", 64, 64 }, -+ { "x2", 128, 64 }, -+ { "x3", 192, 64 }, -+ { "x4", 256, 64 }, -+ { "x5", 320, 64 }, -+ { "x6", 384, 64 }, -+ { "x7", 448, 64 }, -+ { "x8", 512, 64 }, -+ { "x9", 576, 64 }, -+ { "x10", 640, 64 }, -+ { "x11", 704, 64 }, -+ { "x12", 768, 64 }, -+ { "x13", 832, 64 }, -+ { "x14", 896, 64 }, -+ { "x15", 960, 64 }, -+ { "x16", 1024, 64 }, -+ { "x17", 1088, 64 }, -+ { "x18", 1152, 64 }, -+ { "x19", 1216, 64 }, -+ { "x20", 1280, 64 }, -+ { "x21", 1344, 64 }, -+ { "x22", 1408, 64 }, -+ { "x23", 1472, 64 }, -+ { "x24", 1536, 64 }, -+ { "x25", 1600, 64 }, -+ { "x26", 1664, 64 }, -+ { "x27", 1728, 64 }, -+ { "x28", 1792, 64 }, -+ { "x29", 1856, 64 }, -+ { "x30", 1920, 64 }, -+ { "sp", 1984, 64 }, -+ { "pc", 2048, 64 }, -+ { "cpsr", 2112, 32 }, -+ { "v0", 2144, 128 }, -+ { "v1", 2272, 128 }, -+ { "v2", 2400, 128 }, -+ { "v3", 2528, 128 }, -+ { "v4", 2656, 128 }, -+ { "v5", 2784, 128 }, -+ { "v6", 2912, 128 }, -+ { "v7", 3040, 128 }, -+ { "v8", 3168, 128 }, -+ { "v9", 3296, 128 }, -+ { "v10", 3424, 128 }, -+ { "v11", 3552, 128 }, -+ { "v12", 3680, 128 }, -+ { "v13", 3808, 128 }, -+ { "v14", 3936, 128 }, -+ { "v15", 4064, 128 }, -+ { "v16", 4192, 128 }, -+ { "v17", 4320, 128 }, -+ { "v18", 4448, 128 }, -+ { "v19", 4576, 128 }, -+ { "v20", 4704, 128 }, -+ { "v21", 4832, 128 }, -+ { "v22", 4960, 128 }, -+ { "v23", 5088, 128 }, -+ { "v24", 5216, 128 }, -+ { "v25", 5344, 128 }, -+ { "v26", 5472, 128 }, -+ { "v27", 5600, 128 }, -+ { "v28", 5728, 128 }, -+ { "v29", 5856, 128 }, -+ { "v30", 5984, 128 }, -+ { "v31", 6112, 128 }, -+ { "fpsr", 6240, 32 }, -+ { "fpcr", 6272, 32 }, -+}; -+ -+static const char *expedite_regs[] = { "x29", "sp", "pc", 0 }; -+ -+#define num_regs (sizeof (regs) / sizeof (regs[0])) -+ -+static -+CORE_ADDR get_pc (void) -+{ -+ unsigned long pc; -+ -+ collect_register_by_name ("pc", &pc); -+ -+ dlog(1, "stop pc is %p\n", (void *) pc); -+ return pc; -+} -+ -+static -+void set_pc (CORE_ADDR newpc) -+{ -+ Bool mod; -+ supply_register_by_name ("pc", &newpc, &mod); -+ if (mod) -+ dlog(1, "set pc to %p\n", C2v (newpc)); -+ else -+ dlog(1, "set pc not changed %p\n", C2v (newpc)); -+} -+ -+/* store registers in the guest state (gdbserver_to_valgrind) -+ or fetch register from the guest state (valgrind_to_gdbserver). */ -+static -+void transfer_register (ThreadId tid, int abs_regno, void * buf, -+ transfer_direction dir, int size, Bool *mod) -+{ -+ ThreadState* tst = VG_(get_ThreadState)(tid); -+ int set = abs_regno / num_regs; -+ int regno = abs_regno % num_regs; -+ *mod = False; -+ -+ VexGuestARM64State* arm = (VexGuestARM64State*) get_arch (set, tst); -+ -+ switch (regno) { -+ // numbers here have to match the order of regs above -+ // Attention: gdb order does not match valgrind order. -+ case 0: VG_(transfer) (&arm->guest_X0, buf, dir, size, mod); break; -+ case 1: VG_(transfer) (&arm->guest_X1, buf, dir, size, mod); break; -+ case 2: VG_(transfer) (&arm->guest_X2, buf, dir, size, mod); break; -+ case 3: VG_(transfer) (&arm->guest_X3, buf, dir, size, mod); break; -+ case 4: VG_(transfer) (&arm->guest_X4, buf, dir, size, mod); break; -+ case 5: VG_(transfer) (&arm->guest_X5, buf, dir, size, mod); break; -+ case 6: VG_(transfer) (&arm->guest_X6, buf, dir, size, mod); break; -+ case 7: VG_(transfer) (&arm->guest_X7, buf, dir, size, mod); break; -+ case 8: VG_(transfer) (&arm->guest_X8, buf, dir, size, mod); break; -+ case 9: VG_(transfer) (&arm->guest_X9, buf, dir, size, mod); break; -+ case 10: VG_(transfer) (&arm->guest_X10, buf, dir, size, mod); break; -+ case 11: VG_(transfer) (&arm->guest_X11, buf, dir, size, mod); break; -+ case 12: VG_(transfer) (&arm->guest_X12, buf, dir, size, mod); break; -+ case 13: VG_(transfer) (&arm->guest_X13, buf, dir, size, mod); break; -+ case 14: VG_(transfer) (&arm->guest_X14, buf, dir, size, mod); break; -+ case 15: VG_(transfer) (&arm->guest_X15, buf, dir, size, mod); break; -+ case 16: VG_(transfer) (&arm->guest_X16, buf, dir, size, mod); break; -+ case 17: VG_(transfer) (&arm->guest_X17, buf, dir, size, mod); break; -+ case 18: VG_(transfer) (&arm->guest_X18, buf, dir, size, mod); break; -+ case 19: VG_(transfer) (&arm->guest_X19, buf, dir, size, mod); break; -+ case 20: VG_(transfer) (&arm->guest_X20, buf, dir, size, mod); break; -+ case 21: VG_(transfer) (&arm->guest_X21, buf, dir, size, mod); break; -+ case 22: VG_(transfer) (&arm->guest_X22, buf, dir, size, mod); break; -+ case 23: VG_(transfer) (&arm->guest_X23, buf, dir, size, mod); break; -+ case 24: VG_(transfer) (&arm->guest_X24, buf, dir, size, mod); break; -+ case 25: VG_(transfer) (&arm->guest_X25, buf, dir, size, mod); break; -+ case 26: VG_(transfer) (&arm->guest_X26, buf, dir, size, mod); break; -+ case 27: VG_(transfer) (&arm->guest_X27, buf, dir, size, mod); break; -+ case 28: VG_(transfer) (&arm->guest_X28, buf, dir, size, mod); break; -+ case 29: VG_(transfer) (&arm->guest_X29, buf, dir, size, mod); break; -+ case 30: VG_(transfer) (&arm->guest_X30, buf, dir, size, mod); break; -+ case 31: VG_(transfer) (&arm->guest_XSP, buf, dir, size, mod); break; -+ case 32: VG_(transfer) (&arm->guest_PC, buf, dir, size, mod); break; -+ case 33: *mod = False; // GDBTD cpsr what to do for arm64 ??? -+ -+ case 34: VG_(transfer) (&arm->guest_Q0, buf, dir, size, mod); break; -+ case 35: VG_(transfer) (&arm->guest_Q1, buf, dir, size, mod); break; -+ case 36: VG_(transfer) (&arm->guest_Q2, buf, dir, size, mod); break; -+ case 37: VG_(transfer) (&arm->guest_Q3, buf, dir, size, mod); break; -+ case 38: VG_(transfer) (&arm->guest_Q4, buf, dir, size, mod); break; -+ case 39: VG_(transfer) (&arm->guest_Q5, buf, dir, size, mod); break; -+ case 40: VG_(transfer) (&arm->guest_Q6, buf, dir, size, mod); break; -+ case 41: VG_(transfer) (&arm->guest_Q7, buf, dir, size, mod); break; -+ case 42: VG_(transfer) (&arm->guest_Q8, buf, dir, size, mod); break; -+ case 43: VG_(transfer) (&arm->guest_Q9, buf, dir, size, mod); break; -+ case 44: VG_(transfer) (&arm->guest_Q10, buf, dir, size, mod); break; -+ case 45: VG_(transfer) (&arm->guest_Q11, buf, dir, size, mod); break; -+ case 46: VG_(transfer) (&arm->guest_Q12, buf, dir, size, mod); break; -+ case 47: VG_(transfer) (&arm->guest_Q13, buf, dir, size, mod); break; -+ case 48: VG_(transfer) (&arm->guest_Q14, buf, dir, size, mod); break; -+ case 49: VG_(transfer) (&arm->guest_Q15, buf, dir, size, mod); break; -+ case 50: VG_(transfer) (&arm->guest_Q16, buf, dir, size, mod); break; -+ case 51: VG_(transfer) (&arm->guest_Q17, buf, dir, size, mod); break; -+ case 52: VG_(transfer) (&arm->guest_Q18, buf, dir, size, mod); break; -+ case 53: VG_(transfer) (&arm->guest_Q19, buf, dir, size, mod); break; -+ case 54: VG_(transfer) (&arm->guest_Q20, buf, dir, size, mod); break; -+ case 55: VG_(transfer) (&arm->guest_Q21, buf, dir, size, mod); break; -+ case 56: VG_(transfer) (&arm->guest_Q22, buf, dir, size, mod); break; -+ case 57: VG_(transfer) (&arm->guest_Q23, buf, dir, size, mod); break; -+ case 58: VG_(transfer) (&arm->guest_Q24, buf, dir, size, mod); break; -+ case 59: VG_(transfer) (&arm->guest_Q25, buf, dir, size, mod); break; -+ case 60: VG_(transfer) (&arm->guest_Q26, buf, dir, size, mod); break; -+ case 61: VG_(transfer) (&arm->guest_Q27, buf, dir, size, mod); break; -+ case 62: VG_(transfer) (&arm->guest_Q28, buf, dir, size, mod); break; -+ case 63: VG_(transfer) (&arm->guest_Q29, buf, dir, size, mod); break; -+ case 64: VG_(transfer) (&arm->guest_Q30, buf, dir, size, mod); break; -+ case 65: VG_(transfer) (&arm->guest_Q31, buf, dir, size, mod); break; -+ case 66: VG_(transfer) (&arm->guest_FPSR, buf, dir, size, mod); break; -+ case 67: VG_(transfer) (&arm->guest_FPCR, buf, dir, size, mod); break; -+ default: vg_assert(0); -+ } -+} -+ -+static -+const char* target_xml (Bool shadow_mode) -+{ -+ return NULL; -+#if 0 -+ GDBTD -+ if (shadow_mode) { -+ return "arm-with-vfpv3-valgrind.xml"; -+ } else { -+ return "arm-with-vfpv3.xml"; -+ } -+#endif -+} -+ -+static struct valgrind_target_ops low_target = { -+ num_regs, -+ regs, -+ 31, //SP -+ transfer_register, -+ get_pc, -+ set_pc, -+ "arm64", -+ target_xml -+}; -+ -+void arm64_init_architecture (struct valgrind_target_ops *target) -+{ -+ *target = low_target; -+ set_register_cache (regs, num_regs); -+ gdbserver_expedite_regs = expedite_regs; -+} -Index: coregrind/m_gdbserver/valgrind_low.h -=================================================================== ---- coregrind/m_gdbserver/valgrind_low.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_gdbserver/valgrind_low.h (.../trunk) (revision 13981) -@@ -73,6 +73,7 @@ - extern void x86_init_architecture (struct valgrind_target_ops *target); - extern void amd64_init_architecture (struct valgrind_target_ops *target); - extern void arm_init_architecture (struct valgrind_target_ops *target); -+extern void arm64_init_architecture (struct valgrind_target_ops *target); - extern void ppc32_init_architecture (struct valgrind_target_ops *target); - extern void ppc64_init_architecture (struct valgrind_target_ops *target); - extern void s390x_init_architecture (struct valgrind_target_ops *target); -Index: coregrind/m_initimg/initimg-linux.c -=================================================================== ---- coregrind/m_initimg/initimg-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_initimg/initimg-linux.c (.../trunk) (revision 13981) -@@ -640,7 +640,9 @@ - case AT_GID: - case AT_EGID: - case AT_CLKTCK: --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) \ -+ && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - case AT_FPUCW: /* missing on android */ - # endif - /* All these are pointerless, so we don't need to do -@@ -662,18 +664,7 @@ - break; - - case AT_BASE: -- /* When gdbserver sends the auxv to gdb, the AT_BASE has -- to be ignored, as otherwise gdb adds this offset -- to loaded shared libs, causing wrong address -- relocation e.g. when inserting breaks. -- However, ignoring AT_BASE makes V crash on Android 4.1. -- So, keep the AT_BASE on android for now. -- ??? Need to dig in depth about AT_BASE/GDB interaction */ --# if !defined(VGPV_arm_linux_android) \ -- && !defined(VGPV_x86_linux_android) -- auxv->a_type = AT_IGNORE; --# endif -- auxv->u.a_val = info->interp_base; -+ auxv->u.a_val = info->interp_offset; - break; - - case AT_PLATFORM: -@@ -1049,7 +1040,7 @@ - arch->vex.guest_GPR2 = iifii.initial_client_TOC; - arch->vex.guest_CIA = iifii.initial_client_IP; - --# elif defined(VGP_arm_linux) -+# elif defined(VGP_arm_linux) - /* Zero out the initial state, and set up the simulated FPU in a - sane way. */ - LibVEX_GuestARM_initialise(&arch->vex); -@@ -1065,6 +1056,17 @@ - // FIXME jrs: what's this for? - arch->vex.guest_R1 = iifii.initial_client_SP; - -+# elif defined(VGP_arm64_linux) -+ /* Zero out the initial state. */ -+ LibVEX_GuestARM64_initialise(&arch->vex); -+ -+ /* Zero out the shadow areas. */ -+ VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestARM64State)); -+ VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestARM64State)); -+ -+ arch->vex.guest_XSP = iifii.initial_client_SP; -+ arch->vex.guest_PC = iifii.initial_client_IP; -+ - # elif defined(VGP_s390x_linux) - vg_assert(0 == sizeof(VexGuestS390XState) % 16); - -@@ -1076,9 +1078,9 @@ - VG_(memset)(&arch->vex_shadow1, 0xFF, sizeof(VexGuestS390XState)); - VG_(memset)(&arch->vex_shadow2, 0x00, sizeof(VexGuestS390XState)); - /* ... except SP, FPC, and IA */ -- VG_(memset)(&arch->vex_shadow1 + VG_O_STACK_PTR, 0x00, 8); -- VG_(memset)(&arch->vex_shadow1 + VG_O_FPC_REG, 0x00, 4); -- VG_(memset)(&arch->vex_shadow1 + VG_O_INSTR_PTR, 0x00, 8); -+ arch->vex_shadow1.guest_SP = 0; -+ arch->vex_shadow1.guest_fpc = 0; -+ arch->vex_shadow1.guest_IA = 0; - - /* Put essential stuff into the new state. */ - arch->vex.guest_SP = iifii.initial_client_SP; -Index: coregrind/m_libcassert.c -=================================================================== ---- coregrind/m_libcassert.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_libcassert.c (.../trunk) (revision 13981) -@@ -33,6 +33,8 @@ - #include "pub_core_vkiscnums.h" - #include "pub_core_libcsetjmp.h" // to keep threadstate.h happy - #include "pub_core_threadstate.h" -+#include "pub_core_gdbserver.h" -+#include "pub_core_aspacemgr.h" - #include "pub_core_libcbase.h" - #include "pub_core_libcassert.h" - #include "pub_core_libcprint.h" -@@ -136,6 +138,25 @@ - (srP)->misc.ARM.r11 = block[4]; \ - (srP)->misc.ARM.r7 = block[5]; \ - } -+#elif defined(VGP_arm64_linux) -+# define GET_STARTREGS(srP) \ -+ { ULong block[4]; \ -+ __asm__ __volatile__( \ -+ "adr x19, 0;" \ -+ "str x19, [%0, #+0];" /* pc */ \ -+ "mov x19, sp;" \ -+ "str x19, [%0, #+8];" /* sp */ \ -+ "str x29, [%0, #+16];" /* fp */ \ -+ "str x30, [%0, #+24];" /* lr */ \ -+ : /* out */ \ -+ : /* in */ "r"(&block[0]) \ -+ : /* trash */ "memory","x19" \ -+ ); \ -+ (srP)->r_pc = block[0]; \ -+ (srP)->r_sp = block[1]; \ -+ (srP)->misc.ARM64.x29 = block[2]; \ -+ (srP)->misc.ARM64.x30 = block[3]; \ -+ } - #elif defined(VGP_s390x_linux) - # define GET_STARTREGS(srP) \ - { ULong ia, sp, fp, lr; \ -@@ -208,9 +229,33 @@ - - #define BACKTRACE_DEPTH 100 // nice and deep! - --/* Pull down the entire world */ --void VG_(exit)( Int status ) -+__attribute__ ((__noreturn__)) -+static void exit_wrk( Int status, Bool gdbserver_call_allowed) - { -+ static Bool exit_called = False; -+ // avoid recursive exit during gdbserver call. -+ -+ if (gdbserver_call_allowed && !exit_called) { -+ const ThreadId atid = 1; // Arbitrary tid used to call/terminate gdbsrv. -+ exit_called = True; -+ if (status != 0 && VG_(gdbserver_stop_at) (VgdbStopAt_ValgrindAbExit)) { -+ if (VG_(gdbserver_init_done)()) { -+ VG_(umsg)("(action at valgrind abnormal exit) vgdb me ... \n"); -+ VG_(gdbserver) (atid); -+ } else { -+ VG_(umsg)("(action at valgrind abnormal exit) " -+ "Early valgrind exit : vgdb not yet usable\n"); -+ } -+ } -+ if (VG_(gdbserver_init_done)()) { -+ // Always terminate the gdbserver when Valgrind exits, so as -+ // to e.g. cleanup the FIFOs. -+ VG_(gdbserver_exit) (atid, -+ status == 0 ? VgSrc_ExitProcess : VgSrc_FatalSig); -+ } -+ } -+ exit_called = True; -+ - #if defined(VGO_linux) - (void)VG_(do_syscall1)(__NR_exit_group, status ); - #elif defined(VGO_darwin) -@@ -225,57 +270,104 @@ - *(volatile Int*)0 = 'x'; - } - -+/* Pull down the entire world */ -+void VG_(exit)( Int status ) -+{ -+ exit_wrk (status, True); -+} -+ -+/* Pull down the entire world */ -+void VG_(client_exit)( Int status ) -+{ -+ exit_wrk (status, False); -+} -+ -+ - // Print the scheduler status. --void VG_(show_sched_status) ( void ) -+static void show_sched_status_wrk ( Bool host_stacktrace, -+ Bool valgrind_stack_usage, -+ Bool exited_threads, -+ UnwindStartRegs* startRegsIN) - { - Int i; -+ if (host_stacktrace) { -+ const Bool save_clo_xml = VG_(clo_xml); -+ Addr stacktop; -+ Addr ips[BACKTRACE_DEPTH]; -+ Int n_ips; -+ ThreadState *tst -+ = VG_(get_ThreadState)( VG_(lwpid_to_vgtid)( VG_(gettid)() ) ); -+ -+ // If necessary, fake up an ExeContext which is of our actual real CPU -+ // state. Could cause problems if we got the panic/exception within the -+ // execontext/stack dump/symtab code. But it's better than nothing. -+ UnwindStartRegs startRegs; -+ VG_(memset)(&startRegs, 0, sizeof(startRegs)); -+ -+ if (startRegsIN == NULL) { -+ GET_STARTREGS(&startRegs); -+ } else { -+ startRegs = *startRegsIN; -+ } -+ -+ stacktop = tst->os_state.valgrind_stack_init_SP; -+ -+ n_ips = -+ VG_(get_StackTrace_wrk)( -+ 0/*tid is unknown*/, -+ ips, BACKTRACE_DEPTH, -+ NULL/*array to dump SP values in*/, -+ NULL/*array to dump FP values in*/, -+ &startRegs, stacktop -+ ); -+ VG_(printf)("\nhost stacktrace:\n"); -+ VG_(clo_xml) = False; -+ VG_(pp_StackTrace) (ips, n_ips); -+ VG_(clo_xml) = save_clo_xml; -+ } -+ - VG_(printf)("\nsched status:\n"); - VG_(printf)(" running_tid=%d\n", VG_(get_running_tid)()); - for (i = 1; i < VG_N_THREADS; i++) { -- if (VG_(threads)[i].status == VgTs_Empty) continue; -- VG_(printf)( "\nThread %d: status = %s\n", i, -- VG_(name_of_ThreadStatus)(VG_(threads)[i].status) ); -- VG_(get_and_pp_StackTrace)( i, BACKTRACE_DEPTH ); -+ VgStack* stack -+ = (VgStack*)VG_(threads)[i].os_state.valgrind_stack_base; -+ /* If a thread slot was never used (yet), valgrind_stack_base is 0. -+ If a thread slot is used by a thread or was used by a thread which -+ has exited, then valgrind_stack_base points to the stack base. */ -+ if (VG_(threads)[i].status == VgTs_Empty -+ && (!exited_threads || stack == 0)) continue; -+ VG_(printf)("\nThread %d: status = %s\n", i, -+ VG_(name_of_ThreadStatus)(VG_(threads)[i].status) ); -+ if (VG_(threads)[i].status != VgTs_Empty) -+ VG_(get_and_pp_StackTrace)( i, BACKTRACE_DEPTH ); -+ if (valgrind_stack_usage && stack != 0) -+ VG_(printf)("valgrind stack top usage: %ld of %ld\n", -+ VG_STACK_ACTIVE_SZB -+ - VG_(am_get_VgStack_unused_szB)(stack, -+ VG_STACK_ACTIVE_SZB), -+ (SizeT) VG_STACK_ACTIVE_SZB); - } - VG_(printf)("\n"); - } - -+void VG_(show_sched_status) ( Bool host_stacktrace, -+ Bool valgrind_stack_usage, -+ Bool exited_threads) -+{ -+ show_sched_status_wrk (host_stacktrace, -+ valgrind_stack_usage, -+ exited_threads, -+ NULL); -+} -+ - __attribute__ ((noreturn)) - static void report_and_quit ( const HChar* report, - UnwindStartRegs* startRegsIN ) - { -- Addr stacktop; -- Addr ips[BACKTRACE_DEPTH]; -- Int n_ips; -- ThreadState *tst -- = VG_(get_ThreadState)( VG_(lwpid_to_vgtid)( VG_(gettid)() ) ); -- -- // If necessary, fake up an ExeContext which is of our actual real CPU -- // state. Could cause problems if we got the panic/exception within the -- // execontext/stack dump/symtab code. But it's better than nothing. -- UnwindStartRegs startRegs; -- VG_(memset)(&startRegs, 0, sizeof(startRegs)); -- -- if (startRegsIN == NULL) { -- GET_STARTREGS(&startRegs); -- } else { -- startRegs = *startRegsIN; -- } -- -- stacktop = tst->os_state.valgrind_stack_init_SP; -- -- n_ips = -- VG_(get_StackTrace_wrk)( -- 0/*tid is unknown*/, -- ips, BACKTRACE_DEPTH, -- NULL/*array to dump SP values in*/, -- NULL/*array to dump FP values in*/, -- &startRegs, stacktop -- ); -- VG_(clo_xml) = False; -- VG_(pp_StackTrace) (ips, n_ips); -- -- VG_(show_sched_status)(); -+ show_sched_status_wrk (True, // host_stacktrace -+ False, // valgrind_stack_usage -+ False, // exited_threads -+ startRegsIN); - VG_(printf)( - "\n" - "Note: see also the FAQ in the source distribution.\n" -@@ -383,7 +475,9 @@ - VG_(umsg)("\n"); - VG_(umsg)("Valgrind has to exit now. Sorry. Bye!\n"); - VG_(umsg)("\n"); -- VG_(show_sched_status)(); -+ VG_(show_sched_status)(False, // host_stacktrace -+ False, // valgrind_stack_usage -+ False); // exited_threads - VG_(exit)(1); - } - -Index: coregrind/m_libcbase.c -=================================================================== ---- coregrind/m_libcbase.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_libcbase.c (.../trunk) (revision 13981) -@@ -492,6 +492,82 @@ - return True; - } - -+Bool VG_(parse_enum_set) ( const HChar *tokens, -+ const HChar *input, -+ UInt *enum_set) -+{ -+ const SizeT tokens_len = VG_(strlen)(tokens); -+ if (tokens_len > 1000) return False; /* "obviously invalid" */ -+ HChar tok_tokens[tokens_len+1]; -+ HChar *tokens_saveptr; -+ HChar *token; -+ UInt token_nr = 0; -+ UInt all_set = 0; -+ -+ const SizeT input_len = VG_(strlen)(input); -+ if (input_len > 1000) return False; /* "obviously invalid" */ -+ HChar tok_input[input_len+1]; -+ HChar *input_saveptr; -+ HChar *input_word; -+ UInt word_nr = 0; -+ UInt known_words = 0; -+ Bool seen_all_kw = False; -+ Bool seen_none_kw = False; -+ -+ *enum_set = 0; -+ -+ VG_(strcpy) (tok_input, input); -+ for (input_word = VG_(strtok_r)(tok_input, ",", &input_saveptr); -+ input_word; -+ input_word = VG_(strtok_r)(NULL, ",", &input_saveptr)) { -+ word_nr++; -+ if (0 == VG_(strcmp)(input_word, "all")) { -+ seen_all_kw = True; -+ known_words++; -+ } else if (0 == VG_(strcmp)(input_word, "none")) { -+ seen_none_kw = True; -+ known_words++; -+ } -+ -+ // Scan tokens + compute all_set. Do that even if all or none was -+ // recognised to have a correct value for all_set when exiting -+ // of the 'input' loop. -+ all_set = 0; -+ token_nr = 0; -+ VG_(strcpy) (tok_tokens, tokens); -+ for (token = VG_(strtok_r)(tok_tokens, ",", &tokens_saveptr); -+ token; -+ token = VG_(strtok_r)(NULL, ",", &tokens_saveptr)) { -+ if (0 != VG_(strcmp)(token, "-")) { -+ if (0 == VG_(strcmp)(input_word, token)) { -+ *enum_set |= 1 << token_nr; -+ known_words++; -+ } -+ all_set |= 1 << token_nr; -+ } -+ token_nr++; -+ } -+ } -+ -+ if (known_words != word_nr) -+ return False; // One or more input_words not recognised. -+ if (seen_all_kw) { -+ if (seen_none_kw || *enum_set) -+ return False; // mixing all with either none or a specific value. -+ *enum_set = all_set; -+ } else if (seen_none_kw) { -+ if (seen_all_kw || *enum_set) -+ return False; // mixing none with either all or a specific value. -+ *enum_set = 0; -+ } else { -+ // seen neither all or none, we must see at least one value -+ if (*enum_set == 0) -+ return False; -+ } -+ -+ return True; -+} -+ - SizeT VG_(strspn) ( const HChar* s, const HChar* accpt ) - { - const HChar *p, *a; -Index: coregrind/m_libcfile.c -=================================================================== ---- coregrind/m_libcfile.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_libcfile.c (.../trunk) (revision 13981) -@@ -106,7 +106,11 @@ - - SysRes VG_(mknod) ( const HChar* pathname, Int mode, UWord dev ) - { --# if defined(VGO_linux) || defined(VGO_darwin) -+# if defined(VGP_arm64_linux) -+ /* ARM64 wants to use __NR_mknodat rather than __NR_mknod. */ -+ SysRes res = VG_(do_syscall4)(__NR_mknodat, -+ VKI_AT_FDCWD, (UWord)pathname, mode, dev); -+# elif defined(VGO_linux) || defined(VGO_darwin) - SysRes res = VG_(do_syscall3)(__NR_mknod, - (UWord)pathname, mode, dev); - # else -@@ -116,8 +120,12 @@ - } - - SysRes VG_(open) ( const HChar* pathname, Int flags, Int mode ) --{ --# if defined(VGO_linux) -+{ -+# if defined(VGP_arm64_linux) -+ /* ARM64 wants to use __NR_openat rather than __NR_open. */ -+ SysRes res = VG_(do_syscall4)(__NR_openat, -+ VKI_AT_FDCWD, (UWord)pathname, flags, mode); -+# elif defined(VGO_linux) - SysRes res = VG_(do_syscall3)(__NR_open, - (UWord)pathname, flags, mode); - # elif defined(VGO_darwin) -@@ -204,6 +212,9 @@ - } else { - return -1; - } -+# elif defined(VGP_arm64_linux) -+ SysRes res = VG_(do_syscall2)(__NR_pipe2, (UWord)fd, 0); -+ return sr_isError(res) ? -1 : 0; - # elif defined(VGO_linux) - SysRes res = VG_(do_syscall1)(__NR_pipe, (UWord)fd); - return sr_isError(res) ? -1 : 0; -@@ -289,8 +300,14 @@ - } - } - # endif /* defined(__NR_stat64) */ -+ /* This is the fallback ("vanilla version"). */ - { struct vki_stat buf; -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall3)(__NR3264_fstatat, VKI_AT_FDCWD, -+ (UWord)file_name, (UWord)&buf); -+# else - res = VG_(do_syscall2)(__NR_stat, (UWord)file_name, (UWord)&buf); -+# endif - if (!sr_isError(res)) - TRANSLATE_TO_vg_stat(vgbuf, &buf); - return res; -@@ -385,7 +402,12 @@ - - Int VG_(unlink) ( const HChar* file_name ) - { -+# if defined(VGP_arm64_linux) -+ SysRes res = VG_(do_syscall2)(__NR_unlinkat, VKI_AT_FDCWD, -+ (UWord)file_name); -+# else - SysRes res = VG_(do_syscall1)(__NR_unlink, (UWord)file_name); -+# endif - return sr_isError(res) ? (-1) : 0; - } - -@@ -456,10 +478,21 @@ - return True; - } - --Int VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout) -+SysRes VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout) - { - SysRes res; --# if defined(VGO_linux) -+# if defined(VGP_arm64_linux) -+ /* ARM64 wants to use __NR_ppoll rather than __NR_poll. */ -+ struct vki_timespec timeout_ts; -+ if (timeout >= 0) { -+ timeout_ts.tv_sec = timeout / 1000; -+ timeout_ts.tv_nsec = ((long)timeout % 1000) * 1000000; -+ } -+ res = VG_(do_syscall4)(__NR_ppoll, -+ (UWord)fds, nfds, -+ (UWord)(timeout >= 0 ? &timeout_ts : NULL), -+ (UWord)NULL); -+# elif defined(VGO_linux) - res = VG_(do_syscall3)(__NR_poll, (UWord)fds, nfds, timeout); - # elif defined(VGO_darwin) - res = VG_(do_syscall3)(__NR_poll_nocancel, (UWord)fds, nfds, timeout); -@@ -466,7 +499,7 @@ - # else - # error "Unknown OS" - # endif -- return sr_isError(res) ? -1 : sr_Res(res); -+ return res; - } - - -@@ -474,7 +507,12 @@ - { - SysRes res; - /* res = readlink( path, buf, bufsiz ); */ -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, -+ (UWord)path, (UWord)buf, bufsiz); -+# else - res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz); -+# endif - return sr_isError(res) ? -1 : sr_Res(res); - } - -@@ -509,7 +547,11 @@ - UWord w = (irusr ? VKI_R_OK : 0) - | (iwusr ? VKI_W_OK : 0) - | (ixusr ? VKI_X_OK : 0); -+# if defined(VGP_arm64_linux) -+ SysRes res = VG_(do_syscall3)(__NR_faccessat, VKI_AT_FDCWD, (UWord)path, w); -+# else - SysRes res = VG_(do_syscall2)(__NR_access, (UWord)path, w); -+# endif - return sr_isError(res) ? 1 : 0; - - # if defined(VGO_linux) -@@ -624,7 +666,8 @@ - return res; - # elif defined(VGP_amd64_linux) \ - || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset); - return res; - # elif defined(VGP_amd64_darwin) -@@ -877,7 +920,8 @@ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)(__NR_socket, domain, type, protocol ); - return sr_isError(res) ? -1 : sr_Res(res); -@@ -916,7 +960,8 @@ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)(__NR_connect, sockfd, (UWord)serv_addr, addrlen); - return sr_isError(res) ? -1 : sr_Res(res); -@@ -955,7 +1000,8 @@ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall6)(__NR_sendto, sd, (UWord)msg, - count, VKI_MSG_NOSIGNAL, 0,0); -@@ -985,7 +1031,7 @@ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)( __NR_getsockname, - (UWord)sd, (UWord)name, (UWord)namelen ); -@@ -1016,7 +1062,7 @@ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)( __NR_getpeername, - (UWord)sd, (UWord)name, (UWord)namelen ); -@@ -1049,7 +1095,8 @@ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall5)( __NR_getsockopt, - (UWord)sd, (UWord)level, (UWord)optname, -@@ -1085,7 +1132,8 @@ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall5)( __NR_setsockopt, - (UWord)sd, (UWord)level, (UWord)optname, -Index: coregrind/m_libcprint.c -=================================================================== ---- coregrind/m_libcprint.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_libcprint.c (.../trunk) (revision 13981) -@@ -168,6 +168,25 @@ - return ret; - } - -+static UInt emit_WRK ( const HChar* format, va_list vargs ) -+{ -+ if (VG_(clo_xml)) { -+ return VG_(vprintf_xml)(format, vargs); -+ } else if (VG_(log_output_sink).fd == -2) { -+ return VG_(vprintf) (format, vargs); -+ } else { -+ return VG_(vmessage)(Vg_UserMsg, format, vargs); -+ } -+} -+UInt VG_(emit) ( const HChar* format, ... ) -+{ -+ UInt ret; -+ va_list vargs; -+ va_start(vargs, format); -+ ret = emit_WRK(format, vargs); -+ va_end(vargs); -+ return ret; -+} - - /* --------- sprintf --------- */ - -Index: coregrind/m_libcproc.c -=================================================================== ---- coregrind/m_libcproc.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_libcproc.c (.../trunk) (revision 13981) -@@ -458,8 +458,14 @@ - * the /proc/self link is pointing... - */ - -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, -+ (UWord)"/proc/self", -+ (UWord)pid, sizeof(pid)); -+# else - res = VG_(do_syscall3)(__NR_readlink, (UWord)"/proc/self", - (UWord)pid, sizeof(pid)); -+# endif - if (!sr_isError(res) && sr_Res(res) > 0) { - HChar* s; - pid[sr_Res(res)] = '\0'; -@@ -552,7 +558,7 @@ - # elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_arm_linux) \ - || defined(VGO_darwin) || defined(VGP_s390x_linux) \ -- || defined(VGP_mips32_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_arm64_linux) - SysRes sres; - sres = VG_(do_syscall2)(__NR_getgroups, size, (Addr)list); - if (sr_isError(sres)) -@@ -763,6 +769,121 @@ - Addr endaddr = startaddr + nbytes; - VG_(do_syscall2)(__NR_ARM_cacheflush, startaddr, endaddr); - -+# elif defined(VGP_arm64_linux) -+ // This arm64_linux section of this function VG_(invalidate_icache) -+ // is copied from -+ // https://github.com/armvixl/vixl/blob/master/src/a64/cpu-a64.cc -+ // which has the following copyright notice: -+ /* -+ Copyright 2013, ARM Limited -+ All rights reserved. -+ -+ Redistribution and use in source and binary forms, with or without -+ modification, are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright notice, -+ this list of conditions and the following disclaimer in the documentation -+ and/or other materials provided with the distribution. -+ * Neither the name of ARM Limited nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND -+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ // Ask what the I and D line sizes are -+ UInt cache_type_register; -+ // Copy the content of the cache type register to a core register. -+ __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT -+ : [ctr] "=r" (cache_type_register)); -+ -+ const Int kDCacheLineSizeShift = 16; -+ const Int kICacheLineSizeShift = 0; -+ const UInt kDCacheLineSizeMask = 0xf << kDCacheLineSizeShift; -+ const UInt kICacheLineSizeMask = 0xf << kICacheLineSizeShift; -+ -+ // The cache type register holds the size of the I and D caches as a power of -+ // two. -+ const UInt dcache_line_size_power_of_two = -+ (cache_type_register & kDCacheLineSizeMask) >> kDCacheLineSizeShift; -+ const UInt icache_line_size_power_of_two = -+ (cache_type_register & kICacheLineSizeMask) >> kICacheLineSizeShift; -+ -+ const UInt dcache_line_size_ = 4 * (1 << dcache_line_size_power_of_two); -+ const UInt icache_line_size_ = 4 * (1 << icache_line_size_power_of_two); -+ -+ Addr start = (Addr)ptr; -+ // Sizes will be used to generate a mask big enough to cover a pointer. -+ Addr dsize = (Addr)dcache_line_size_; -+ Addr isize = (Addr)icache_line_size_; -+ -+ // Cache line sizes are always a power of 2. -+ Addr dstart = start & ~(dsize - 1); -+ Addr istart = start & ~(isize - 1); -+ Addr end = start + nbytes; -+ -+ __asm__ __volatile__ ( -+ // Clean every line of the D cache containing the target data. -+ "0: \n\t" -+ // dc : Data Cache maintenance -+ // c : Clean -+ // va : by (Virtual) Address -+ // u : to the point of Unification -+ // The point of unification for a processor is the point by which the -+ // instruction and data caches are guaranteed to see the same copy of a -+ // memory location. See ARM DDI 0406B page B2-12 for more information. -+ "dc cvau, %[dline] \n\t" -+ "add %[dline], %[dline], %[dsize] \n\t" -+ "cmp %[dline], %[end] \n\t" -+ "b.lt 0b \n\t" -+ // Barrier to make sure the effect of the code above is visible to the rest -+ // of the world. -+ // dsb : Data Synchronisation Barrier -+ // ish : Inner SHareable domain -+ // The point of unification for an Inner Shareable shareability domain is -+ // the point by which the instruction and data caches of all the processors -+ // in that Inner Shareable shareability domain are guaranteed to see the -+ // same copy of a memory location. See ARM DDI 0406B page B2-12 for more -+ // information. -+ "dsb ish \n\t" -+ // Invalidate every line of the I cache containing the target data. -+ "1: \n\t" -+ // ic : instruction cache maintenance -+ // i : invalidate -+ // va : by address -+ // u : to the point of unification -+ "ic ivau, %[iline] \n\t" -+ "add %[iline], %[iline], %[isize] \n\t" -+ "cmp %[iline], %[end] \n\t" -+ "b.lt 1b \n\t" -+ // Barrier to make sure the effect of the code above is visible to the rest -+ // of the world. -+ "dsb ish \n\t" -+ // Barrier to ensure any prefetching which happened before this code is -+ // discarded. -+ // isb : Instruction Synchronisation Barrier -+ "isb \n\t" -+ : [dline] "+r" (dstart), -+ [iline] "+r" (istart) -+ : [dsize] "r" (dsize), -+ [isize] "r" (isize), -+ [end] "r" (end) -+ // This code does not write to memory but without the dependency gcc might -+ // move this code before the code is generated. -+ : "cc", "memory" -+ ); -+ - # elif defined(VGA_mips32) || defined(VGA_mips64) - SysRes sres = VG_(do_syscall3)(__NR_cacheflush, (UWord) ptr, - (UWord) nbytes, (UWord) 3); -@@ -772,6 +893,34 @@ - } - - -+/* --------------------------------------------------------------------- -+ dcache flushing -+ ------------------------------------------------------------------ */ -+ -+void VG_(flush_dcache) ( void *ptr, SizeT nbytes ) -+{ -+ /* Currently this is only required on ARM64. */ -+# if defined(VGA_arm64) -+ Addr startaddr = (Addr) ptr; -+ Addr endaddr = startaddr + nbytes; -+ Addr cls; -+ Addr addr; -+ -+ ULong ctr_el0; -+ __asm__ __volatile__ ("mrs %0, ctr_el0" : "=r"(ctr_el0)); -+ cls = 4 * (1ULL << (0xF & (ctr_el0 >> 16))); -+ -+ /* Stay sane .. */ -+ vg_assert(cls == 64); -+ -+ startaddr &= ~(cls - 1); -+ for (addr = startaddr; addr < endaddr; addr += cls) { -+ __asm__ __volatile__("dc cvau, %0" : : "r" (addr)); -+ } -+ __asm__ __volatile__("dsb ish"); -+# endif -+} -+ - /*--------------------------------------------------------------------*/ - /*--- end ---*/ - /*--------------------------------------------------------------------*/ -Index: coregrind/m_machine.c -=================================================================== ---- coregrind/m_machine.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_machine.c (.../trunk) (revision 13981) -@@ -97,6 +97,11 @@ - = VG_(threads)[tid].arch.vex.guest_R11; - regs->misc.ARM.r7 - = VG_(threads)[tid].arch.vex.guest_R7; -+# elif defined(VGA_arm64) -+ regs->r_pc = VG_(threads)[tid].arch.vex.guest_PC; -+ regs->r_sp = VG_(threads)[tid].arch.vex.guest_XSP; -+ regs->misc.ARM64.x29 = VG_(threads)[tid].arch.vex.guest_X29; -+ regs->misc.ARM64.x30 = VG_(threads)[tid].arch.vex.guest_X30; - # elif defined(VGA_s390x) - regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_IA; - regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_SP; -@@ -127,38 +132,6 @@ - # endif - } - -- --void VG_(set_syscall_return_shadows) ( ThreadId tid, -- /* shadow vals for the result */ -- UWord s1res, UWord s2res, -- /* shadow vals for the error val */ -- UWord s1err, UWord s2err ) --{ --# if defined(VGP_x86_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_EAX = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_EAX = s2res; --# elif defined(VGP_amd64_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_RAX = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_RAX = s2res; --# elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_GPR3 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_GPR3 = s2res; --# elif defined(VGP_arm_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_R0 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_R0 = s2res; --# elif defined(VGO_darwin) -- // GrP fixme darwin syscalls may return more values (2 registers plus error) --# elif defined(VGP_s390x_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_r2 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_r2 = s2res; --# elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_r2 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_r2 = s2res; --# else --# error "Unknown plat" --# endif --} -- - void - VG_(get_shadow_regs_area) ( ThreadId tid, - /*DST*/UChar* dst, -@@ -339,6 +312,38 @@ - (*f)(tid, "r29", vex->guest_r29); - (*f)(tid, "r30", vex->guest_r30); - (*f)(tid, "r31", vex->guest_r31); -+#elif defined(VGA_arm64) -+ (*f)(tid, "x0" , vex->guest_X0 ); -+ (*f)(tid, "x1" , vex->guest_X1 ); -+ (*f)(tid, "x2" , vex->guest_X2 ); -+ (*f)(tid, "x3" , vex->guest_X3 ); -+ (*f)(tid, "x4" , vex->guest_X4 ); -+ (*f)(tid, "x5" , vex->guest_X5 ); -+ (*f)(tid, "x6" , vex->guest_X6 ); -+ (*f)(tid, "x7" , vex->guest_X7 ); -+ (*f)(tid, "x8" , vex->guest_X8 ); -+ (*f)(tid, "x9" , vex->guest_X9 ); -+ (*f)(tid, "x10", vex->guest_X10); -+ (*f)(tid, "x11", vex->guest_X11); -+ (*f)(tid, "x12", vex->guest_X12); -+ (*f)(tid, "x13", vex->guest_X13); -+ (*f)(tid, "x14", vex->guest_X14); -+ (*f)(tid, "x15", vex->guest_X15); -+ (*f)(tid, "x16", vex->guest_X16); -+ (*f)(tid, "x17", vex->guest_X17); -+ (*f)(tid, "x18", vex->guest_X18); -+ (*f)(tid, "x19", vex->guest_X19); -+ (*f)(tid, "x20", vex->guest_X20); -+ (*f)(tid, "x21", vex->guest_X21); -+ (*f)(tid, "x22", vex->guest_X22); -+ (*f)(tid, "x23", vex->guest_X23); -+ (*f)(tid, "x24", vex->guest_X24); -+ (*f)(tid, "x25", vex->guest_X25); -+ (*f)(tid, "x26", vex->guest_X26); -+ (*f)(tid, "x27", vex->guest_X27); -+ (*f)(tid, "x28", vex->guest_X28); -+ (*f)(tid, "x29", vex->guest_X29); -+ (*f)(tid, "x30", vex->guest_X30); - #else - # error Unknown arch - #endif -@@ -745,18 +750,24 @@ - if (!have_cx8) - return False; - -- /* Figure out if this is an AMD that can do mmxext and/or LZCNT. */ -+ /* Figure out if this is an AMD that can do MMXEXT. */ - have_mmxext = False; -- have_lzcnt = False; - if (0 == VG_(strcmp)(vstr, "AuthenticAMD") - && max_extended >= 0x80000001) { - VG_(cpuid)(0x80000001, 0, &eax, &ebx, &ecx, &edx); -- have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */ -- - /* Some older AMD processors support a sse1 subset (Integer SSE). */ - have_mmxext = !have_sse1 && ((edx & (1<<22)) != 0); - } - -+ /* Figure out if this is an AMD or Intel that can do LZCNT. */ -+ have_lzcnt = False; -+ if ((0 == VG_(strcmp)(vstr, "AuthenticAMD") -+ || 0 == VG_(strcmp)(vstr, "GenuineIntel")) -+ && max_extended >= 0x80000001) { -+ VG_(cpuid)(0x80000001, 0, &eax, &ebx, &ecx, &edx); -+ have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */ -+ } -+ - /* Intel processors don't define the mmxext extension, but since it - is just a sse1 subset always define it when we have sse1. */ - if (have_sse1) -@@ -847,7 +858,6 @@ - } - } - -- - /* cmpxchg8b is a minimum requirement now; if we don't have it we - must simply give up. But all CPUs since Pentium-I have it, so - that doesn't seem like much of a restriction. */ -@@ -1193,7 +1203,7 @@ - - #elif defined(VGA_s390x) - --#include "libvex_s390x_common.h" -+# include "libvex_s390x_common.h" - - { - /* Instruction set detection code borrowed from ppc above. */ -@@ -1440,8 +1450,35 @@ - return True; - } - -+#elif defined(VGA_arm64) -+ { -+ va = VexArchARM64; -+ -+ /* So far there are no variants. */ -+ vai.hwcaps = 0; -+ -+ VG_(machine_get_cache_info)(&vai); -+ -+ /* 0 denotes 'not set'. The range of legitimate values here, -+ after being set that is, is 2 though 17 inclusive. */ -+ vg_assert(vai.arm64_dMinLine_lg2_szB == 0); -+ vg_assert(vai.arm64_iMinLine_lg2_szB == 0); -+ ULong ctr_el0; -+ __asm__ __volatile__("mrs %0, ctr_el0" : "=r"(ctr_el0)); -+ vai.arm64_dMinLine_lg2_szB = ((ctr_el0 >> 16) & 0xF) + 2; -+ vai.arm64_iMinLine_lg2_szB = ((ctr_el0 >> 0) & 0xF) + 2; -+ VG_(debugLog)(1, "machine", "ARM64: ctr_el0.dMinLine_szB = %d, " -+ "ctr_el0.iMinLine_szB = %d\n", -+ 1 << vai.arm64_dMinLine_lg2_szB, -+ 1 << vai.arm64_iMinLine_lg2_szB); -+ -+ return True; -+ } -+ - #elif defined(VGA_mips32) - { -+ /* Define the position of F64 bit in FIR register. */ -+# define FP64 22 - va = VexArchMIPS32; - UInt model = VG_(get_machine_model)(); - if (model == -1) -@@ -1504,6 +1541,16 @@ - } - } - -+ /* Check if CPU has FPU and 32 dbl. prec. FP registers */ -+ int FIR = 0; -+ __asm__ __volatile__( -+ "cfc1 %0, $0" "\n\t" -+ : "=r" (FIR) -+ ); -+ if (FIR & (1 << FP64)) { -+ vai.hwcaps |= VEX_PRID_CPU_32FPR; -+ } -+ - VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act); - VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL); - VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); -@@ -1649,6 +1696,10 @@ - assume we always do. */ - return 16; - -+# elif defined(VGA_arm64) -+ /* ARM64 always has Neon, AFAICS. */ -+ return 16; -+ - # elif defined(VGA_mips32) - /* The guest state implies 4, but that can't really be true, can - it? */ -@@ -1671,7 +1722,7 @@ - || defined(VGP_arm_linux) \ - || defined(VGP_ppc32_linux) || defined(VGO_darwin) \ - || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - return f; - # elif defined(VGP_ppc64_linux) - /* ppc64-linux uses the AIX scheme, in which f is a pointer to a -Index: coregrind/m_main.c -=================================================================== ---- coregrind/m_main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_main.c (.../trunk) (revision 13981) -@@ -73,31 +73,6 @@ - - - /*====================================================================*/ --/*=== Counters, for profiling purposes only ===*/ --/*====================================================================*/ -- --static void print_all_stats ( void ) --{ -- VG_(print_translation_stats)(); -- VG_(print_tt_tc_stats)(); -- VG_(print_scheduler_stats)(); -- VG_(print_ExeContext_stats)( False /* with_stacktraces */ ); -- VG_(print_errormgr_stats)(); -- -- // Memory stats -- if (VG_(clo_verbosity) > 2) { -- VG_(message)(Vg_DebugMsg, "\n"); -- VG_(message)(Vg_DebugMsg, -- "------ Valgrind's internal memory use stats follow ------\n" ); -- VG_(sanity_check_malloc_all)(); -- VG_(message)(Vg_DebugMsg, "------\n" ); -- VG_(print_all_arena_stats)(); -- VG_(message)(Vg_DebugMsg, "\n"); -- } --} -- -- --/*====================================================================*/ - /*=== Command-line: variables, processing, etc ===*/ - /*====================================================================*/ - -@@ -133,6 +108,8 @@ - " --vgdb-error= invoke gdbserver after errors [%d]\n" - " to get started quickly, use --vgdb-error=0\n" - " and follow the on-screen directions\n" -+" --vgdb-stop-at=event1,event2,... invoke gdbserver for given events [none]\n" -+" where event is one of startup exit valgrindabexit all none\n" - " --track-fds=no|yes track open file descriptors? [no]\n" - " --time-stamp=no|yes add timestamps to log messages? [no]\n" - " --log-fd= log messages to file descriptor [2=stderr]\n" -@@ -202,6 +179,7 @@ - " program counters in max frames) [0]\n" - " --num-transtab-sectors= size of translated code cache [%d]\n" - " more sectors may increase performance, but use more memory.\n" -+" --aspace-minaddr=0xPP avoid mapping memory below 0xPP [guessed]\n" - " --show-emwarns=no|yes show warnings about emulation limits? [no]\n" - " --require-text-symbol=:sonamepattern:symbolpattern abort run if the\n" - " stated shared object doesn't have the stated\n" -@@ -516,10 +494,11 @@ - else if VG_STREQ( arg, "-d") {} - else if VG_STREQN(17, arg, "--max-stackframe=") {} - else if VG_STREQN(17, arg, "--main-stacksize=") {} -- else if VG_STREQN(12, arg, "--sim-hints=") {} -+ else if VG_STREQN(12, arg, "--sim-hints=") {} - else if VG_STREQN(15, arg, "--profile-heap=") {} - else if VG_STREQN(20, arg, "--core-redzone-size=") {} - else if VG_STREQN(15, arg, "--redzone-size=") {} -+ else if VG_STREQN(17, arg, "--aspace-minaddr=") {} - - /* Obsolete options. Report an error and exit */ - else if VG_STREQN(34, arg, "--vex-iropt-precise-memory-exns=no") { -@@ -562,7 +541,14 @@ - } - else if VG_INT_CLO (arg, "--vgdb-poll", VG_(clo_vgdb_poll)) {} - else if VG_INT_CLO (arg, "--vgdb-error", VG_(clo_vgdb_error)) {} -- else if VG_STR_CLO (arg, "--vgdb-prefix", VG_(clo_vgdb_prefix)) {} -+ else if VG_STR_CLO (arg, "--vgdb-stop-at", tmp_str) { -+ if (!VG_(parse_enum_set)("startup,exit,valgrindabexit", tmp_str, -+ &VG_(clo_vgdb_stop_at))) -+ VG_(fmsg_bad_option)(arg, ""); -+ } -+ else if VG_STR_CLO (arg, "--vgdb-prefix", VG_(clo_vgdb_prefix)) { -+ VG_(arg_vgdb_prefix) = arg; -+ } - else if VG_BOOL_CLO(arg, "--vgdb-shadow-registers", - VG_(clo_vgdb_shadow_registers)) {} - else if VG_BOOL_CLO(arg, "--db-attach", VG_(clo_db_attach)) {} -@@ -1558,10 +1544,12 @@ - //-------------------------------------------------------------- - /* Start the debugging-log system ASAP. First find out how many - "-d"s were specified. This is a pre-scan of the command line. Also -- get --profile-heap=yes, --core-redzone-size, --redzone-size which are -- needed by the time we start up dynamic memory management. */ -+ get --profile-heap=yes, --core-redzone-size, --redzone-size -+ --aspace-minaddr which are needed by the time we start up dynamic -+ memory management. */ - loglevel = 0; - for (i = 1; i < argc; i++) { -+ const HChar* tmp_str; - if (argv[i][0] != '-') break; - if VG_STREQ(argv[i], "--") break; - if VG_STREQ(argv[i], "-d") loglevel++; -@@ -1570,6 +1558,23 @@ - 0, MAX_CLO_REDZONE_SZB) {} - if VG_BINT_CLO(argv[i], "--redzone-size", VG_(clo_redzone_size), - 0, MAX_CLO_REDZONE_SZB) {} -+ if VG_STR_CLO(argv[i], "--aspace-minaddr", tmp_str) { -+# if VG_WORDSIZE == 4 -+ const Addr max = (Addr) 0x40000000; // 1Gb -+# else -+ const Addr max = (Addr) 0x200000000; // 8Gb -+# endif -+ Bool ok = VG_(parse_Addr) (&tmp_str, &VG_(clo_aspacem_minAddr)); -+ if (!ok) -+ VG_(fmsg_bad_option)(argv[i], "Invalid address\n"); -+ -+ if (!VG_IS_PAGE_ALIGNED(VG_(clo_aspacem_minAddr)) -+ || VG_(clo_aspacem_minAddr) < (Addr) 0x1000 -+ || VG_(clo_aspacem_minAddr) > max) // 1Gb -+ VG_(fmsg_bad_option)(argv[i], -+ "Must be a page aligned address between " -+ "0x1000 and 0x%lx\n", max); -+ } - } - - /* ... and start the debug logger. Now we can safely emit logging -@@ -2021,6 +2026,8 @@ - iters = 5; - # elif defined(VGP_arm_linux) - iters = 5; -+# elif defined(VGP_arm64_linux) -+ iters = 5; - # elif defined(VGP_s390x_linux) - iters = 10; - # elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -@@ -2435,7 +2442,13 @@ - vg_assert(VG_(count_living_threads)() >= 1); - } - -+ /* Final call to gdbserver, if requested. */ -+ if (VG_(gdbserver_stop_at) (VgdbStopAt_Exit)) { -+ VG_(umsg)("(action at exit) vgdb me ... \n"); -+ VG_(gdbserver) (tid); -+ } - VG_(threads)[tid].status = VgTs_Empty; -+ - //-------------------------------------------------------------- - // Finalisation: cleanup, messages, etc. Order not so important, only - // affects what order the messages come. -@@ -2485,7 +2498,8 @@ - VG_(sanity_check_general)( True /*include expensive checks*/ ); - - if (VG_(clo_stats)) -- print_all_stats(); -+ VG_(print_all_stats)(VG_(clo_verbosity) > 2, /* Memory stats */ -+ False /* tool prints stats in the tool fini */); - - /* Show a profile of the heap(s) at shutdown. Optionally, first - throw away all the debug info, as that makes it easy to spot -@@ -2509,7 +2523,7 @@ - /* Flush any output cached by previous calls to VG_(message). */ - VG_(message_flush)(); - -- /* terminate gdbserver if ever it was started. We terminate it here -+ /* Terminate gdbserver if ever it was started. We terminate it here - so that it get the output above if output was redirected to - gdb */ - VG_(gdbserver_exit) (tid, tids_schedretcode); -@@ -2528,11 +2542,11 @@ - if an error was found */ - if (VG_(clo_error_exitcode) > 0 - && VG_(get_n_errs_found)() > 0) { -- VG_(exit)( VG_(clo_error_exitcode) ); -+ VG_(client_exit)( VG_(clo_error_exitcode) ); - } else { - /* otherwise, return the client's exit code, in the normal - way. */ -- VG_(exit)( VG_(threads)[tid].os_state.exitcode ); -+ VG_(client_exit)( VG_(threads)[tid].os_state.exitcode ); - } - /* NOT ALIVE HERE! */ - VG_(core_panic)("entered the afterlife in main() -- ExitT/P"); -@@ -2908,6 +2922,31 @@ - "\t.word "VG_STRINGIFY(VG_STACK_GUARD_SZB)"\n" - "\t.word "VG_STRINGIFY(VG_STACK_ACTIVE_SZB)"\n" - ); -+#elif defined(VGP_arm64_linux) -+asm("\n" -+ "\t.text\n" -+ "\t.align 2\n" -+ "\t.type _start,#function\n" -+ "\t.global _start\n" -+ "_start:\n" -+ "\tadrp x0, vgPlain_interim_stack\n" -+ "\tadd x0, x0, :lo12:vgPlain_interim_stack\n" -+ // The next 2 assume that VG_STACK_GUARD_SZB fits in 32 bits -+ "\tmov x1, (("VG_STRINGIFY(VG_STACK_GUARD_SZB)") >> 0) & 0xFFFF\n" -+ "\tmovk x1, (("VG_STRINGIFY(VG_STACK_GUARD_SZB)") >> 16) & 0xFFFF," -+ " lsl 16\n" -+ "\tadd x0, x0, x1\n" -+ // The next 2 assume that VG_STACK_ACTIVE_SZB fits in 32 bits -+ "\tmov x1, (("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)") >> 0) & 0xFFFF\n" -+ "\tmovk x1, (("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)") >> 16) & 0xFFFF," -+ " lsl 16\n" -+ "\tadd x0, x0, x1\n" -+ "\tand x0, x0, -16\n" -+ "\tmov x1, sp\n" -+ "\tmov sp, x0\n" -+ "\tmov x0, x1\n" -+ "\tb _start_in_C_linux\n" -+); - #elif defined(VGP_mips32_linux) - asm("\n" - "\t.type _gp_disp,@object\n" -@@ -3033,7 +3072,8 @@ - - the_iicii.sp_at_startup = (Addr)pArgc; - --# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -+ || defined(VGP_arm64_linux) - { - /* ppc/ppc64 can be configured with different page sizes. - Determine this early. This is an ugly hack and really should -Index: coregrind/m_mallocfree.c -=================================================================== ---- coregrind/m_mallocfree.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_mallocfree.c (.../trunk) (revision 13981) -@@ -40,6 +40,7 @@ - #include "pub_core_options.h" - #include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy - #include "pub_core_threadstate.h" // For VG_INVALID_THREADID -+#include "pub_core_gdbserver.h" - #include "pub_core_transtab.h" - #include "pub_core_tooliface.h" - -@@ -742,11 +743,18 @@ - if (outputTrial <= 1) { - if (outputTrial == 0) { - outputTrial++; -+ // First print the memory stats with the aspacemgr data. - VG_(am_show_nsegments) (0, "out_of_memory"); - VG_(print_all_arena_stats) (); - if (VG_(clo_profile_heap)) - VG_(print_arena_cc_analysis) (); -- /* In case we are an inner valgrind, asks the outer to report -+ // And then print some other information that might help. -+ VG_(print_all_stats) (False, /* Memory stats */ -+ True /* Tool stats */); -+ VG_(show_sched_status) (True, // host_stacktrace -+ True, // valgrind_stack_usage -+ True); // exited_threads -+ /* In case we are an inner valgrind, asks the outer to report - its memory state in its log output. */ - INNER_REQUEST(VALGRIND_MONITOR_COMMAND("v.set log_output")); - INNER_REQUEST(VALGRIND_MONITOR_COMMAND("v.info memory aspacemgr")); -@@ -807,12 +815,8 @@ - - if (a->clientmem) { - // client allocation -- return 0 to client if it fails -- if (unsplittable) -- sres = VG_(am_mmap_anon_float_client) -- ( cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC ); -- else -- sres = VG_(am_sbrk_anon_float_client) -- ( cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC ); -+ sres = VG_(am_mmap_anon_float_client) -+ ( cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC ); - if (sr_isError(sres)) - return 0; - sb = (Superblock*)(AddrH)sr_Res(sres); -@@ -822,10 +826,7 @@ - VG_(am_set_segment_isCH_if_SkAnonC)( VG_(am_find_nsegment)( (Addr)sb ) ); - } else { - // non-client allocation -- abort if it fails -- if (unsplittable) -- sres = VG_(am_mmap_anon_float_valgrind)( cszB ); -- else -- sres = VG_(am_sbrk_anon_float_valgrind)( cszB ); -+ sres = VG_(am_mmap_anon_float_valgrind)( cszB ); - if (sr_isError(sres)) { - VG_(out_of_memory_NORETURN)("newSuperblock", cszB); - /* NOTREACHED */ -@@ -942,6 +943,33 @@ - } - - -+// Find the superblock containing the given address. -+// If superblock not found, return NULL. -+static -+Superblock* maybe_findSb ( Arena* a, Addr ad ) -+{ -+ SizeT min = 0; -+ SizeT max = a->sblocks_used; -+ -+ while (min <= max) { -+ Superblock * sb; -+ SizeT pos = min + (max - min)/2; -+ if (pos < 0 || pos >= a->sblocks_used) -+ return NULL; -+ sb = a->sblocks[pos]; -+ if ((Addr)&sb->payload_bytes[0] <= ad -+ && ad < (Addr)&sb->payload_bytes[sb->n_payload_bytes]) { -+ return sb; -+ } else if ((Addr)&sb->payload_bytes[0] <= ad) { -+ min = pos + 1; -+ } else { -+ max = pos - 1; -+ } -+ } -+ return NULL; -+} -+ -+ - /*------------------------------------------------------------*/ - /*--- Functions for working with freelists. ---*/ - /*------------------------------------------------------------*/ -@@ -1289,11 +1317,13 @@ - - static AnCC anCCs[N_AN_CCS]; - -+/* Sorting by decreasing cost center nBytes, to have the biggest -+ cost centres at the top. */ - static Int cmp_AnCC_by_vol ( const void* v1, const void* v2 ) { - const AnCC* ancc1 = v1; - const AnCC* ancc2 = v2; -- if (ancc1->nBytes < ancc2->nBytes) return -1; -- if (ancc1->nBytes > ancc2->nBytes) return 1; -+ if (ancc1->nBytes < ancc2->nBytes) return 1; -+ if (ancc1->nBytes > ancc2->nBytes) return -1; - return 0; - } - -@@ -1410,7 +1440,44 @@ - } - } - -+void VG_(describe_arena_addr) ( Addr a, AddrArenaInfo* aai ) -+{ -+ UInt i; -+ Superblock *sb; -+ Arena *arena; - -+ for (i = 0; i < VG_N_ARENAS; i++) { -+ if (i == VG_AR_CLIENT && !client_inited) -+ continue; -+ arena = arenaId_to_ArenaP(i); -+ sb = maybe_findSb( arena, a ); -+ if (sb != NULL) { -+ Word j; -+ SizeT b_bszB; -+ Block *b = NULL; -+ -+ aai->aid = i; -+ aai->name = arena->name; -+ for (j = 0; j < sb->n_payload_bytes; j += mk_plain_bszB(b_bszB)) { -+ b = (Block*)&sb->payload_bytes[j]; -+ b_bszB = get_bszB_as_is(b); -+ if (a < (Addr)b + mk_plain_bszB(b_bszB)) -+ break; -+ } -+ vg_assert (b); -+ aai->block_szB = get_pszB(arena, b); -+ aai->rwoffset = a - (Addr)get_block_payload(arena, b); -+ aai->free = !is_inuse_block(b); -+ return; -+ } -+ } -+ aai->aid = 0; -+ aai->name = NULL; -+ aai->block_szB = 0; -+ aai->rwoffset = 0; -+ aai->free = False; -+} -+ - /*------------------------------------------------------------*/ - /*--- Creating and deleting blocks. ---*/ - /*------------------------------------------------------------*/ -@@ -1600,7 +1667,7 @@ - vg_assert(a->sblocks_used <= a->sblocks_size); - if (a->sblocks_used == a->sblocks_size) { - Superblock ** array; -- SysRes sres = VG_(am_sbrk_anon_float_valgrind)(sizeof(Superblock *) * -+ SysRes sres = VG_(am_mmap_anon_float_valgrind)(sizeof(Superblock *) * - a->sblocks_size * 2); - if (sr_isError(sres)) { - VG_(out_of_memory_NORETURN)("arena_init", sizeof(Superblock *) * -Index: coregrind/m_options.c -=================================================================== ---- coregrind/m_options.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_options.c (.../trunk) (revision 13981) -@@ -47,7 +47,8 @@ - Bool VG_(clo_error_limit) = True; - Int VG_(clo_error_exitcode) = 0; - --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - VgVgdb VG_(clo_vgdb) = Vg_VgdbNo; // currently disabled on Android - #else - VgVgdb VG_(clo_vgdb) = Vg_VgdbYes; -@@ -54,7 +55,9 @@ - #endif - Int VG_(clo_vgdb_poll) = 5000; - Int VG_(clo_vgdb_error) = 999999999; --const HChar* VG_(clo_vgdb_prefix) = NULL; -+UInt VG_(clo_vgdb_stop_at) = 0; -+const HChar *VG_(clo_vgdb_prefix) = NULL; -+const HChar *VG_(arg_vgdb_prefix) = NULL; - Bool VG_(clo_vgdb_shadow_registers) = False; - - Bool VG_(clo_db_attach) = False; -@@ -165,18 +168,8 @@ - goto bad; - } - -- // If 'format' starts with a '/', do not prefix with startup dir. -- if (format[0] != '/') { -- j += VG_(strlen)(base_dir); -- } -- -- // The 10 is slop, it should be enough in most cases. -- len = j + VG_(strlen)(format) + 10; -+ len = VG_(strlen)(format) + 1; - out = VG_(malloc)( "options.efn.1", len ); -- if (format[0] != '/') { -- VG_(strcpy)(out, base_dir); -- out[j++] = '/'; -- } - - #define ENSURE_THIS_MUCH_SPACE(x) \ - if (j + x >= len) { \ -@@ -258,6 +251,18 @@ - ENSURE_THIS_MUCH_SPACE(1); - out[j++] = 0; - -+ // If 'out' is not an absolute path name, prefix it with the startup dir. -+ if (out[0] != '/') { -+ len = VG_(strlen)(base_dir) + 1 + VG_(strlen)(out) + 1; -+ -+ HChar *absout = VG_(malloc)("options.efn.4", len); -+ VG_(strcpy)(absout, base_dir); -+ VG_(strcat)(absout, "/"); -+ VG_(strcat)(absout, out); -+ VG_(free)(out); -+ out = absout; -+ } -+ - return out; - - bad: { -Index: coregrind/m_rangemap.c -=================================================================== ---- coregrind/m_rangemap.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/m_rangemap.c (.../trunk) (revision 13981) -@@ -0,0 +1,218 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- A mapping where the keys exactly cover the address space. ---*/ -+/*--- m_rangemap.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2014-2014 Mozilla Foundation -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+/* Contributed by Julian Seward */ -+ -+#include "pub_core_basics.h" -+#include "pub_core_libcassert.h" -+#include "pub_core_libcprint.h" -+#include "pub_core_xarray.h" -+#include "pub_core_rangemap.h" /* self */ -+ -+ -+/* See pub_tool_rangemap.h for details of what this is all about. */ -+ -+#define UWORD_MIN ((UWord)0) -+#define UWORD_MAX (~(UWord)0) -+ -+typedef -+ struct { UWord key_min; UWord key_max; UWord val; } -+ Range; -+ -+ -+struct _RangeMap { -+ void* (*alloc) ( const HChar*, SizeT ); /* alloc fn (nofail) */ -+ const HChar* cc; /* cost centre for alloc */ -+ void (*free) ( void* ); /* free fn */ -+ XArray* ranges; -+}; -+ -+ -+/* fwds */ -+static void preen (/*MOD*/RangeMap* rm); -+static Word find ( RangeMap* rm, UWord key ); -+static void split_at ( /*MOD*/RangeMap* rm, UWord key ); -+static void show ( RangeMap* rm ); -+ -+ -+RangeMap* VG_(newRangeMap) ( void*(*alloc_fn)(const HChar*,SizeT), -+ const HChar* cc, -+ void(*free_fn)(void*), -+ UWord initialVal ) -+{ -+ /* check user-supplied info .. */ -+ vg_assert(alloc_fn); -+ vg_assert(free_fn); -+ RangeMap* rm = alloc_fn(cc, sizeof(RangeMap)); -+ vg_assert(rm); -+ rm->alloc = alloc_fn; -+ rm->cc = cc; -+ rm->free = free_fn; -+ rm->ranges = VG_(newXA)( alloc_fn, cc, free_fn, sizeof(Range) ); -+ vg_assert(rm->ranges); -+ /* Add the initial range */ -+ Range r; -+ r.key_min = UWORD_MIN; -+ r.key_max = UWORD_MAX; -+ r.val = initialVal; -+ Word i = VG_(addToXA)(rm->ranges, &r); -+ vg_assert(i == 0); -+ vg_assert(VG_(sizeXA)(rm->ranges) == 1); -+ /* */ -+ return rm; -+} -+ -+void VG_(deleteRangeMap) ( RangeMap* rm ) -+{ -+ vg_assert(rm); -+ vg_assert(rm->free); -+ vg_assert(rm->ranges); -+ VG_(deleteXA)(rm->ranges); -+ rm->free(rm); -+} -+ -+void VG_(bindRangeMap) ( RangeMap* rm, -+ UWord key_min, UWord key_max, UWord val ) -+{ -+ vg_assert(key_min <= key_max); -+ split_at(rm, key_min); -+ if (key_max < UWORD_MAX) -+ split_at(rm, key_max + 1); -+ Word iMin, iMax, i; -+ iMin = find(rm, key_min); -+ iMax = find(rm, key_max); -+ for (i = iMin; i <= iMax; i++) { -+ Range* rng = VG_(indexXA)(rm->ranges, i); -+ rng->val = val; -+ } -+ preen(rm); -+} -+ -+void VG_(lookupRangeMap) ( /*OUT*/UWord* key_min, /*OUT*/UWord* key_max, -+ /*OUT*/UWord* val, RangeMap* rm, UWord key ) -+{ -+ Word i = find(rm, key); -+ Range* rng = (Range*)VG_(indexXA)(rm->ranges, i); -+ *key_min = rng->key_min; -+ *key_max = rng->key_max; -+ *val = rng->val; -+} -+ -+Word VG_(sizeRangeMap) ( RangeMap* rm ) -+{ -+ vg_assert(rm && rm->ranges); -+ return VG_(sizeXA)(rm->ranges); -+} -+ -+void VG_(indexRangeMap) ( /*OUT*/UWord* key_min, /*OUT*/UWord* key_max, -+ /*OUT*/UWord* val, RangeMap* rm, Word ix ) -+{ -+ vg_assert(rm && rm->ranges); -+ Range* rng = (Range*)VG_(indexXA)(rm->ranges, ix); -+ *key_min = rng->key_min; -+ *key_max = rng->key_max; -+ *val = rng->val; -+} -+ -+/* Helper functions, not externally visible. */ -+ -+static void preen (/*MOD*/RangeMap* rm) -+{ -+ Word i; -+ XArray* ranges = rm->ranges; -+ for (i = 0; i < VG_(sizeXA)(ranges) - 1; i++) { -+ Range* rng0 = VG_(indexXA)(ranges, i+0); -+ Range* rng1 = VG_(indexXA)(ranges, i+1); -+ if (rng0->val != rng1->val) -+ continue; -+ rng0->key_max = rng1->key_max; -+ VG_(removeIndexXA)(ranges, i+1); -+ /* Back up one, so as not to miss an opportunity to merge with -+ the entry after this one. */ -+ i--; -+ } -+} -+ -+static Word find ( RangeMap* rm, UWord key ) -+{ -+ XArray* ranges = rm->ranges; -+ Word lo = 0; -+ Word hi = VG_(sizeXA)(ranges); -+ while (True) { -+ /* The unsearched space is lo .. hi inclusive */ -+ if (lo > hi) { -+ /* Not found. This can't happen. */ -+ VG_(core_panic)("RangeMap::find: not found"); -+ /*NOTREACHED*/ -+ return -1; -+ } -+ Word mid = (lo + hi) / 2; -+ Range* mid_rng = (Range*)VG_(indexXA)(ranges, mid); -+ UWord key_mid_min = mid_rng->key_min; -+ UWord key_mid_max = mid_rng->key_max; -+ if (key < key_mid_min) { hi = mid-1; continue; } -+ if (key > key_mid_max) { lo = mid+1; continue; } -+ return mid; -+ } -+} -+ -+static void split_at ( /*MOD*/RangeMap* rm, UWord key ) -+{ -+ XArray* ranges = rm->ranges; -+ Word i = find(rm, key); -+ Range rng_i0 = *(Range*)VG_(indexXA)( ranges, i+0 ); -+ if (rng_i0.key_min == key) -+ return; -+ VG_(insertIndexXA)( ranges, i+1, &rng_i0 ); -+ /* The insert could have relocated the payload, hence the -+ re-indexing of i+0 here. */ -+ Range* rng_i0p = (Range*)VG_(indexXA)( ranges, i+0 ); -+ Range* rng_i1p = (Range*)VG_(indexXA)( ranges, i+1 ); -+ rng_i0p->key_max = key-1; -+ rng_i1p->key_min = key; -+} -+ -+__attribute__((unused)) -+static void show ( RangeMap* rm ) -+{ -+ Word i; -+ VG_(printf)("<< %ld entries:\n", VG_(sizeXA)(rm->ranges) ); -+ for (i = 0; i < VG_(sizeXA)(rm->ranges); i++) { -+ Range* rng = (Range*)VG_(indexXA)(rm->ranges, i); -+ VG_(printf)(" %016llx %016llx --> 0x%llx\n", -+ (ULong)rng->key_min, (ULong)rng->key_max, (ULong)rng->val); -+ } -+ VG_(printf)(">>\n"); -+} -+ -+ -+/*--------------------------------------------------------------------*/ -+/*--- end m_rangemap.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_redir.c -=================================================================== ---- coregrind/m_redir.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_redir.c (.../trunk) (revision 13981) -@@ -1299,27 +1299,61 @@ - } - - # elif defined(VGP_arm_linux) -- /* If we're using memcheck, use these intercepts right from -- the start, otherwise ld.so makes a lot of noise. */ -+ /* If we're using memcheck, use these intercepts right from the -+ start, otherwise ld.so makes a lot of noise. In most ARM-linux -+ distros, ld.so's soname is ld-linux.so.3, but Ubuntu 14.04 on -+ Odroid uses ld-linux-armhf.so.3 for some reason. */ - if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { -+ /* strlen */ - add_hardwired_spec( - "ld-linux.so.3", "strlen", - (Addr)&VG_(arm_linux_REDIR_FOR_strlen), - complain_about_stripped_glibc_ldso - ); -- //add_hardwired_spec( -- // "ld-linux.so.3", "index", -- // (Addr)&VG_(arm_linux_REDIR_FOR_index), -- // NULL -- //); - add_hardwired_spec( -+ "ld-linux-armhf.so.3", "strlen", -+ (Addr)&VG_(arm_linux_REDIR_FOR_strlen), -+ complain_about_stripped_glibc_ldso -+ ); -+ /* memcpy */ -+ add_hardwired_spec( - "ld-linux.so.3", "memcpy", - (Addr)&VG_(arm_linux_REDIR_FOR_memcpy), - complain_about_stripped_glibc_ldso - ); -+ add_hardwired_spec( -+ "ld-linux-armhf.so.3", "memcpy", -+ (Addr)&VG_(arm_linux_REDIR_FOR_memcpy), -+ complain_about_stripped_glibc_ldso -+ ); - } -- /* nothing so far */ - -+# elif defined(VGP_arm64_linux) -+ /* If we're using memcheck, use these intercepts right from -+ the start, otherwise ld.so makes a lot of noise. */ -+ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { -+ add_hardwired_spec( -+ "ld-linux-aarch64.so.1", "strlen", -+ (Addr)&VG_(arm64_linux_REDIR_FOR_strlen), -+ complain_about_stripped_glibc_ldso -+ ); -+ add_hardwired_spec( -+ "ld-linux-aarch64.so.1", "index", -+ (Addr)&VG_(arm64_linux_REDIR_FOR_index), -+ NULL -+ ); -+ add_hardwired_spec( -+ "ld-linux-aarch64.so.1", "strcmp", -+ (Addr)&VG_(arm64_linux_REDIR_FOR_strcmp), -+ NULL -+ ); -+ //add_hardwired_spec( -+ // "ld-linux.so.3", "memcpy", -+ // (Addr)&VG_(arm_linux_REDIR_FOR_memcpy), -+ // complain_about_stripped_glibc_ldso -+ //); -+ } -+ - # elif defined(VGP_x86_darwin) - /* If we're using memcheck, use these intercepts right from - the start, otherwise dyld makes a lot of noise. */ -Index: coregrind/m_replacemalloc/vg_replace_malloc.c -=================================================================== ---- coregrind/m_replacemalloc/vg_replace_malloc.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_replacemalloc/vg_replace_malloc.c (.../trunk) (revision 13981) -@@ -116,7 +116,7 @@ - __attribute__ ((__noreturn__)) - static inline void my_exit ( int x ) - { --# if defined(VGPV_arm_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_mips32_linux_android) - __asm__ __volatile__(".word 0xFFFFFFFF"); - while (1) {} - # elif defined(VGPV_x86_linux_android) -@@ -131,7 +131,8 @@ - /* Same problem with getpagesize. */ - static inline int my_getpagesize ( void ) - { --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - return 4096; /* kludge - link failure on Android, for some reason */ - # else - extern int getpagesize (void); -@@ -939,7 +940,8 @@ - MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_usable_size); - MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, malloc_size); - MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_size); --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, dlmalloc_usable_size); - MALLOC_USABLE_SIZE(SO_SYN_MALLOC, dlmalloc_usable_size); - # endif -Index: coregrind/m_scheduler/scheduler.c -=================================================================== ---- coregrind/m_scheduler/scheduler.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_scheduler/scheduler.c (.../trunk) (revision 13981) -@@ -198,8 +198,10 @@ - const HChar* name_of_sched_event ( UInt event ) - { - switch (event) { -- case VEX_TRC_JMP_TINVAL: return "TINVAL"; -+ case VEX_TRC_JMP_INVALICACHE: return "INVALICACHE"; -+ case VEX_TRC_JMP_FLUSHDCACHE: return "FLUSHDCACHE"; - case VEX_TRC_JMP_NOREDIR: return "NOREDIR"; -+ case VEX_TRC_JMP_SIGILL: return "SIGILL"; - case VEX_TRC_JMP_SIGTRAP: return "SIGTRAP"; - case VEX_TRC_JMP_SIGSEGV: return "SIGSEGV"; - case VEX_TRC_JMP_SIGBUS: return "SIGBUS"; -@@ -790,12 +792,21 @@ - vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow2.guest_D1)); - # endif - -+# if defined(VGA_arm64) -+ vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_X0)); -+ vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow1.guest_X0)); -+ vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow2.guest_X0)); -+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_Q0)); -+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_Q0)); -+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_Q0)); -+# endif -+ - # if defined(VGA_s390x) - /* no special requirements */ - # endif - - # if defined(VGA_mips32) || defined(VGA_mips64) -- /* no special requirements */ -+ /* no special requirements */ - # endif - } - -@@ -1425,6 +1436,10 @@ - break; - } - -+ case VEX_TRC_JMP_SIGILL: -+ VG_(synth_sigill)(tid, VG_(get_IP)(tid)); -+ break; -+ - case VEX_TRC_JMP_SIGTRAP: - VG_(synth_sigtrap)(tid); - break; -@@ -1452,21 +1467,20 @@ - VG_(umsg)( - "valgrind: Unrecognised instruction at address %#lx.\n", addr); - VG_(get_and_pp_StackTrace)(tid, VG_(clo_backtrace_size)); --#define M(a) VG_(umsg)(a "\n"); -- M("Your program just tried to execute an instruction that Valgrind" ); -- M("did not recognise. There are two possible reasons for this." ); -- M("1. Your program has a bug and erroneously jumped to a non-code" ); -- M(" location. If you are running Memcheck and you just saw a" ); -- M(" warning about a bad jump, it's probably your program's fault."); -- M("2. The instruction is legitimate but Valgrind doesn't handle it,"); -- M(" i.e. it's Valgrind's fault. If you think this is the case or"); -- M(" you are not sure, please let us know and we'll try to fix it."); -- M("Either way, Valgrind will now raise a SIGILL signal which will" ); -- M("probably kill your program." ); --#undef M -+# define M(a) VG_(umsg)(a "\n"); -+ M("Your program just tried to execute an instruction that Valgrind" ); -+ M("did not recognise. There are two possible reasons for this." ); -+ M("1. Your program has a bug and erroneously jumped to a non-code" ); -+ M(" location. If you are running Memcheck and you just saw a" ); -+ M(" warning about a bad jump, it's probably your program's fault."); -+ M("2. The instruction is legitimate but Valgrind doesn't handle it,"); -+ M(" i.e. it's Valgrind's fault. If you think this is the case or"); -+ M(" you are not sure, please let us know and we'll try to fix it."); -+ M("Either way, Valgrind will now raise a SIGILL signal which will" ); -+ M("probably kill your program." ); -+# undef M - } -- --#if defined(VGA_s390x) -+# if defined(VGA_s390x) - /* Now that the complaint is out we need to adjust the guest_IA. The - reason is that -- after raising the exception -- execution will - continue with the insn that follows the invalid insn. As the first -@@ -1478,22 +1492,30 @@ - UChar byte = ((UChar *)addr)[0]; - UInt insn_length = ((((byte >> 6) + 1) >> 1) + 1) << 1; - Addr next_insn_addr = addr + insn_length; -- - VG_(set_IP)(tid, next_insn_addr); --#endif -+# endif - VG_(synth_sigill)(tid, addr); - break; - } -- case VEX_TRC_JMP_TINVAL: -+ -+ case VEX_TRC_JMP_INVALICACHE: - VG_(discard_translations)( -- (Addr64)VG_(threads)[tid].arch.vex.guest_TISTART, -- VG_(threads)[tid].arch.vex.guest_TILEN, -- "scheduler(VEX_TRC_JMP_TINVAL)" -+ (Addr64)VG_(threads)[tid].arch.vex.guest_CMSTART, -+ VG_(threads)[tid].arch.vex.guest_CMLEN, -+ "scheduler(VEX_TRC_JMP_INVALICACHE)" - ); - if (0) - VG_(printf)("dump translations done.\n"); - break; - -+ case VEX_TRC_JMP_FLUSHDCACHE: { -+ void* start = (void*)VG_(threads)[tid].arch.vex.guest_CMSTART; -+ SizeT len = VG_(threads)[tid].arch.vex.guest_CMLEN; -+ VG_(debugLog)(2, "sched", "flush_dcache(%p, %lu)\n", start, len); -+ VG_(flush_dcache)(start, len); -+ break; -+ } -+ - case VG_TRC_INVARIANT_FAILED: - /* This typically happens if, after running generated code, - it is detected that host CPU settings (eg, FPU/Vector -@@ -1598,6 +1620,9 @@ - #elif defined(VGA_arm) - # define VG_CLREQ_ARGS guest_R4 - # define VG_CLREQ_RET guest_R3 -+#elif defined(VGA_arm64) -+# define VG_CLREQ_ARGS guest_X4 -+# define VG_CLREQ_RET guest_X3 - #elif defined (VGA_s390x) - # define VG_CLREQ_ARGS guest_r2 - # define VG_CLREQ_RET guest_r3 -@@ -2084,7 +2109,9 @@ - lasttime = now; - VG_(printf)("\n------------ Sched State at %d ms ------------\n", - (Int)now); -- VG_(show_sched_status)(); -+ VG_(show_sched_status)(True, // host_stacktrace -+ True, // valgrind_stack_usage -+ True); // exited_threads); - } - } - -Index: coregrind/m_sigframe/sigframe-amd64-linux.c -=================================================================== ---- coregrind/m_sigframe/sigframe-amd64-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_sigframe/sigframe-amd64-linux.c (.../trunk) (revision 13981) -@@ -521,6 +521,16 @@ - tst->arch.vex.guest_RDI = (ULong) siginfo->si_signo; - tst->arch.vex.guest_RSI = (Addr) &frame->sigInfo; - tst->arch.vex.guest_RDX = (Addr) &frame->uContext; -+ /* And tell the tool that these registers have been written. */ -+ VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, -+ offsetof(VexGuestAMD64State,guest_RIP), sizeof(UWord) ); -+ VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, -+ offsetof(VexGuestAMD64State,guest_RDI), sizeof(UWord) ); -+ VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, -+ offsetof(VexGuestAMD64State,guest_RSI), sizeof(UWord) ); -+ VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, -+ offsetof(VexGuestAMD64State,guest_RDX), sizeof(UWord) ); -+ - /* This thread needs to be marked runnable, but we leave that the - caller to do. */ - -Index: coregrind/m_sigframe/sigframe-arm64-linux.c -=================================================================== ---- coregrind/m_sigframe/sigframe-arm64-linux.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/m_sigframe/sigframe-arm64-linux.c (.../trunk) (revision 13981) -@@ -0,0 +1,337 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Create/destroy signal delivery frames. ---*/ -+/*--- sigframe-arm64-linux.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics.h" -+#include "pub_core_vki.h" -+//ZZ #include "pub_core_vkiscnums.h" -+#include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy -+#include "pub_core_threadstate.h" -+#include "pub_core_aspacemgr.h" -+#include "pub_core_libcbase.h" -+#include "pub_core_libcassert.h" -+#include "pub_core_libcprint.h" -+#include "pub_core_machine.h" -+#include "pub_core_options.h" -+#include "pub_core_sigframe.h" -+#include "pub_core_signals.h" -+#include "pub_core_tooliface.h" -+#include "pub_core_trampoline.h" -+//ZZ #include "pub_core_transtab.h" // VG_(discard_translations) -+ -+ -+/* This uses the hack of dumping the vex guest state along with both -+ shadows in the frame, and restoring it afterwards from there, -+ rather than pulling it out of the ucontext. That means that signal -+ handlers which modify the ucontext and then return, expecting their -+ modifications to take effect, will have those modifications -+ ignored. This could be fixed properly with an hour or so more -+ effort. */ -+ -+/* This also always does the 'has siginfo' behaviour whether or -+ not it is requested. */ -+ -+struct vg_sig_private { -+ UInt magicPI; -+ UInt sigNo_private; -+ VexGuestARM64State vex; -+ VexGuestARM64State vex_shadow1; -+ VexGuestARM64State vex_shadow2; -+}; -+ -+struct sigframe { -+ struct vki_ucontext uc; -+ unsigned long retcode[2]; -+ struct vg_sig_private vp; -+}; -+ -+struct rt_sigframe { -+ vki_siginfo_t info; -+ struct sigframe sig; -+}; -+ -+static Bool extend ( ThreadState *tst, Addr addr, SizeT size ) -+{ -+ ThreadId tid = tst->tid; -+ NSegment const* stackseg = NULL; -+ -+ if (VG_(extend_stack)(addr, tst->client_stack_szB)) { -+ stackseg = VG_(am_find_nsegment)(addr); -+ if (0 && stackseg) -+ VG_(printf)("frame=%#lx seg=%#lx-%#lx\n", -+ addr, stackseg->start, stackseg->end); -+ } -+ -+ if (stackseg == NULL || !stackseg->hasR || !stackseg->hasW) { -+ VG_(message)( -+ Vg_UserMsg, -+ "Can't extend stack to %#lx during signal delivery for thread %d:", -+ addr, tid); -+ if (stackseg == NULL) -+ VG_(message)(Vg_UserMsg, " no stack segment"); -+ else -+ VG_(message)(Vg_UserMsg, " too small or bad protection modes"); -+ -+ /* set SIGSEGV to default handler */ -+ VG_(set_default_handler)(VKI_SIGSEGV); -+ VG_(synth_fault_mapping)(tid, addr); -+ -+ /* The whole process should be about to die, since the default -+ action of SIGSEGV to kill the whole process. */ -+ return False; -+ } -+ -+ /* For tracking memory events, indicate the entire frame has been -+ allocated. */ -+ VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB, -+ size + VG_STACK_REDZONE_SZB, tid ); -+ -+ return True; -+} -+ -+static void synth_ucontext( ThreadId tid, const vki_siginfo_t *si, -+ UWord trapno, UWord err, const vki_sigset_t *set, -+ struct vki_ucontext *uc) -+{ -+ -+ ThreadState *tst = VG_(get_ThreadState)(tid); -+ struct vki_sigcontext *sc = &uc->uc_mcontext; -+ -+ VG_(memset)(uc, 0, sizeof(*uc)); -+ -+ uc->uc_flags = 0; -+ uc->uc_link = 0; -+ uc->uc_sigmask = *set; -+ uc->uc_stack = tst->altstack; -+ -+# define SC2(reg) sc->regs[reg] = tst->arch.vex.guest_X##reg -+ SC2(0); SC2(1); SC2(2); SC2(3); -+ SC2(4); SC2(5); SC2(6); SC2(7); -+ SC2(8); SC2(9); SC2(10); SC2(11); -+ SC2(12); SC2(13); SC2(14); SC2(15); -+ SC2(16); SC2(17); SC2(18); SC2(19); -+ SC2(20); SC2(21); SC2(22); SC2(23); -+ SC2(24); SC2(25); SC2(26); SC2(27); -+ SC2(28); SC2(29); SC2(30); -+# undef SC2 -+ sc->sp = tst->arch.vex.guest_XSP; -+ sc->pc = tst->arch.vex.guest_PC; -+ sc->pstate = 0; /* slack .. could do better */ -+ -+ //sc->trap_no = trapno; -+ //sc->error_code = err; -+ sc->fault_address = (ULong)si->_sifields._sigfault._addr; -+} -+ -+ -+static void build_sigframe(ThreadState *tst, -+ struct sigframe *frame, -+ const vki_siginfo_t *siginfo, -+ const struct vki_ucontext *siguc, -+ void *handler, UInt flags, -+ const vki_sigset_t *mask, -+ void *restorer) -+{ -+ UWord trapno; -+ UWord err; -+ Int sigNo = siginfo->si_signo; -+ struct vg_sig_private *priv = &frame->vp; -+ -+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal handler frame", -+ (Addr)frame, offsetof(struct sigframe, vp)); -+ -+ if (siguc) { -+ trapno = 0; //siguc->uc_mcontext.trap_no; -+ err = 0; //siguc->uc_mcontext.error_code; -+ } else { -+ trapno = 0; -+ err = 0; -+ } -+ -+ synth_ucontext(tst->tid, siginfo, trapno, err, mask, &frame->uc); -+ -+ VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, -+ (Addr)frame, offsetof(struct sigframe, vp)); -+ -+ priv->magicPI = 0x31415927; -+ priv->sigNo_private = sigNo; -+ priv->vex = tst->arch.vex; -+ priv->vex_shadow1 = tst->arch.vex_shadow1; -+ priv->vex_shadow2 = tst->arch.vex_shadow2; -+} -+ -+ -+/* EXPORTED */ -+void VG_(sigframe_create)( ThreadId tid, -+ Addr sp_top_of_frame, -+ const vki_siginfo_t *siginfo, -+ const struct vki_ucontext *siguc, -+ void *handler, -+ UInt flags, -+ const vki_sigset_t *mask, -+ void *restorer ) -+{ -+ ThreadState *tst; -+ Addr sp = sp_top_of_frame; -+ Int sigNo = siginfo->si_signo; -+ UInt size; -+ -+ tst = VG_(get_ThreadState)(tid); -+ -+ size = sizeof(struct rt_sigframe); -+ -+ sp -= size; -+ sp = VG_ROUNDDN(sp, 16); -+ -+ if (!extend(tst, sp, size)) -+ return; // Give up. No idea if this is correct -+ -+ struct rt_sigframe *rsf = (struct rt_sigframe *)sp; -+ -+ /* Track our writes to siginfo */ -+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, /* VVVVV */ -+ "signal handler siginfo", (Addr)rsf, -+ offsetof(struct rt_sigframe, sig)); -+ -+ VG_(memcpy)(&rsf->info, siginfo, sizeof(vki_siginfo_t)); -+ -+ if (sigNo == VKI_SIGILL && siginfo->si_code > 0) { -+ rsf->info._sifields._sigfault._addr -+ = (Addr*)(tst)->arch.vex.guest_PC; -+ } -+ VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, /* ^^^^^ */ -+ (Addr)rsf, offsetof(struct rt_sigframe, sig)); -+ -+ build_sigframe(tst, &rsf->sig, siginfo, siguc, -+ handler, flags, mask, restorer); -+ tst->arch.vex.guest_X1 = (Addr)&rsf->info; -+ tst->arch.vex.guest_X2 = (Addr)&rsf->sig.uc; -+ -+ VG_(set_SP)(tid, sp); -+ VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, -+ sizeof(Addr)); -+ tst->arch.vex.guest_X0 = sigNo; -+ -+ if (flags & VKI_SA_RESTORER) -+ tst->arch.vex.guest_X30 = (Addr)restorer; -+ else -+ tst->arch.vex.guest_X30 -+ = (Addr)&VG_(arm64_linux_SUBST_FOR_rt_sigreturn); -+ -+ tst->arch.vex.guest_PC = (Addr)handler; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Destroying signal frames ---*/ -+/*------------------------------------------------------------*/ -+ -+/* EXPORTED */ -+void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) -+{ -+ ThreadState *tst; -+ struct vg_sig_private *priv; -+ Addr sp; -+ UInt frame_size; -+//ZZ struct vki_sigcontext *mc; -+ Int sigNo; -+ Bool has_siginfo = isRT; -+ -+ vg_assert(VG_(is_valid_tid)(tid)); -+ tst = VG_(get_ThreadState)(tid); -+ sp = tst->arch.vex.guest_XSP; -+ -+//ZZ if (has_siginfo) { -+ struct rt_sigframe *frame = (struct rt_sigframe *)sp; -+ frame_size = sizeof(*frame); -+ //mc = &frame->sig.uc.uc_mcontext; -+ priv = &frame->sig.vp; -+ vg_assert(priv->magicPI == 0x31415927); -+ tst->sig_mask = frame->sig.uc.uc_sigmask; -+//ZZ } else { -+//ZZ struct sigframe *frame = (struct sigframe *)sp; -+//ZZ frame_size = sizeof(*frame); -+//ZZ mc = &frame->uc.uc_mcontext; -+//ZZ priv = &frame->vp; -+//ZZ vg_assert(priv->magicPI == 0x31415927); -+//ZZ tst->sig_mask = frame->uc.uc_sigmask; -+//ZZ //VG_(printf)("Setting signmask to %08x%08x\n", -+//ZZ // tst->sig_mask[0],tst->sig_mask[1]); -+//ZZ } -+ tst->tmp_sig_mask = tst->sig_mask; -+ -+ sigNo = priv->sigNo_private; -+ -+//ZZ //XXX: restore regs -+//ZZ # define REST(reg,REG) tst->arch.vex.guest_##REG = mc->arm_##reg; -+//ZZ REST(r0,R0); -+//ZZ REST(r1,R1); -+//ZZ REST(r2,R2); -+//ZZ REST(r3,R3); -+//ZZ REST(r4,R4); -+//ZZ REST(r5,R5); -+//ZZ REST(r6,R6); -+//ZZ REST(r7,R7); -+//ZZ REST(r8,R8); -+//ZZ REST(r9,R9); -+//ZZ REST(r10,R10); -+//ZZ REST(fp,R11); -+//ZZ REST(ip,R12); -+//ZZ REST(sp,R13); -+//ZZ REST(lr,R14); -+//ZZ REST(pc,R15T); -+//ZZ # undef REST -+ -+ /* Uh, the next line makes all the REST() above pointless. */ -+ tst->arch.vex = priv->vex; -+ -+ tst->arch.vex_shadow1 = priv->vex_shadow1; -+ tst->arch.vex_shadow2 = priv->vex_shadow2; -+ -+ VG_TRACK( die_mem_stack_signal, sp - VG_STACK_REDZONE_SZB, -+ frame_size + VG_STACK_REDZONE_SZB ); -+ -+ if (VG_(clo_trace_signals)) -+ VG_(message)(Vg_DebugMsg, -+ "vg_pop_signal_frame (thread %d): " -+ "isRT=%d valid magic; PC=%#llx\n", -+ tid, has_siginfo, tst->arch.vex.guest_PC); -+ -+ /* tell the tools */ -+ VG_TRACK( post_deliver_signal, tid, sigNo ); -+} -+ -+#endif // defined(VGP_arm_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end sigframe-arm64-linux.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_signals.c -=================================================================== ---- coregrind/m_signals.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_signals.c (.../trunk) (revision 13981) -@@ -386,6 +386,19 @@ - (srP)->misc.ARM.r7 = (uc)->uc_mcontext.arm_r7; \ - } - -+#elif defined(VGP_arm64_linux) -+# define VG_UCONTEXT_INSTR_PTR(uc) ((UWord)((uc)->uc_mcontext.pc)) -+# define VG_UCONTEXT_STACK_PTR(uc) ((UWord)((uc)->uc_mcontext.sp)) -+# define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ -+ /* Convert the value in uc_mcontext.regs[0] into a SysRes. */ \ -+ VG_(mk_SysRes_arm64_linux)( (uc)->uc_mcontext.regs[0] ) -+# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ -+ { (srP)->r_pc = (uc)->uc_mcontext.pc; \ -+ (srP)->r_sp = (uc)->uc_mcontext.sp; \ -+ (srP)->misc.ARM64.x29 = (uc)->uc_mcontext.regs[29]; \ -+ (srP)->misc.ARM64.x30 = (uc)->uc_mcontext.regs[30]; \ -+ } -+ - #elif defined(VGP_x86_darwin) - - static inline Addr VG_UCONTEXT_INSTR_PTR( void* ucV ) { -@@ -862,6 +875,15 @@ - " svc 0x00000000\n" \ - ".previous\n" - -+#elif defined(VGP_arm64_linux) -+# define _MY_SIGRETURN(name) \ -+ ".text\n" \ -+ ".globl my_sigreturn\n" \ -+ "my_sigreturn:\n\t" \ -+ " mov x8, #" #name "\n\t" \ -+ " svc 0x0\n" \ -+ ".previous\n" -+ - #elif defined(VGP_x86_darwin) - # define _MY_SIGRETURN(name) \ - ".text\n" \ -@@ -980,8 +1002,7 @@ - # if !defined(VGP_ppc32_linux) && \ - !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \ - !defined(VGP_mips32_linux) && !defined(VGP_mips64_linux) -- vg_assert(ksa_old.sa_restorer -- == my_sigreturn); -+ vg_assert(ksa_old.sa_restorer == my_sigreturn); - # endif - VG_(sigaddset)( &ksa_old.sa_mask, VKI_SIGKILL ); - VG_(sigaddset)( &ksa_old.sa_mask, VKI_SIGSTOP ); -Index: coregrind/m_stacktrace.c -=================================================================== ---- coregrind/m_stacktrace.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_stacktrace.c (.../trunk) (revision 13981) -@@ -1034,6 +1034,102 @@ - - #endif - -+/* ------------------------ arm64 ------------------------- */ -+ -+#if defined(VGP_arm64_linux) -+ -+UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, -+ /*OUT*/Addr* ips, UInt max_n_ips, -+ /*OUT*/Addr* sps, /*OUT*/Addr* fps, -+ UnwindStartRegs* startRegs, -+ Addr fp_max_orig ) -+{ -+ Bool debug = False; -+ Int i; -+ Addr fp_max; -+ UInt n_found = 0; -+ const Int cmrf = VG_(clo_merge_recursive_frames); -+ -+ vg_assert(sizeof(Addr) == sizeof(UWord)); -+ vg_assert(sizeof(Addr) == sizeof(void*)); -+ -+ D3UnwindRegs uregs; -+ uregs.pc = startRegs->r_pc; -+ uregs.sp = startRegs->r_sp; -+ uregs.x30 = startRegs->misc.ARM64.x30; -+ uregs.x29 = startRegs->misc.ARM64.x29; -+ Addr fp_min = uregs.sp; -+ -+ /* Snaffle IPs from the client's stack into ips[0 .. max_n_ips-1], -+ stopping when the trail goes cold, which we guess to be -+ when FP is not a reasonable stack location. */ -+ -+ // JRS 2002-sep-17: hack, to round up fp_max to the end of the -+ // current page, at least. Dunno if it helps. -+ // NJN 2002-sep-17: seems to -- stack traces look like 1.0.X again -+ fp_max = VG_PGROUNDUP(fp_max_orig); -+ if (fp_max >= sizeof(Addr)) -+ fp_max -= sizeof(Addr); -+ -+ if (debug) -+ VG_(printf)("\nmax_n_ips=%d fp_min=0x%lx fp_max_orig=0x%lx, " -+ "fp_max=0x%lx PC=0x%lx SP=0x%lx\n", -+ max_n_ips, fp_min, fp_max_orig, fp_max, -+ uregs.pc, uregs.sp); -+ -+ /* Assertion broken before main() is reached in pthreaded programs; the -+ * offending stack traces only have one item. --njn, 2002-aug-16 */ -+ /* vg_assert(fp_min <= fp_max);*/ -+ // On Darwin, this kicks in for pthread-related stack traces, so they're -+ // only 1 entry long which is wrong. -+ if (fp_min + 512 >= fp_max) { -+ /* If the stack limits look bogus, don't poke around ... but -+ don't bomb out either. */ -+ if (sps) sps[0] = uregs.sp; -+ if (fps) fps[0] = uregs.x29; -+ ips[0] = uregs.pc; -+ return 1; -+ } -+ -+ /* */ -+ -+ if (sps) sps[0] = uregs.sp; -+ if (fps) fps[0] = uregs.x29; -+ ips[0] = uregs.pc; -+ i = 1; -+ -+ /* Loop unwinding the stack, using CFI. */ -+ while (True) { -+ if (debug) { -+ VG_(printf)("i: %d, pc: 0x%lx, sp: 0x%lx\n", -+ i, uregs.pc, uregs.sp); -+ } -+ -+ if (i >= max_n_ips) -+ break; -+ -+ if (VG_(use_CF_info)( &uregs, fp_min, fp_max )) { -+ if (sps) sps[i] = uregs.sp; -+ if (fps) fps[i] = uregs.x29; -+ ips[i++] = uregs.pc - 1; -+ if (debug) -+ VG_(printf)("USING CFI: pc: 0x%lx, sp: 0x%lx\n", -+ uregs.pc, uregs.sp); -+ uregs.pc = uregs.pc - 1; -+ if (UNLIKELY(cmrf > 0)) {RECURSIVE_MERGE(cmrf,ips,i);}; -+ continue; -+ } -+ -+ /* No luck. We have to give up. */ -+ break; -+ } -+ -+ n_found = i; -+ return n_found; -+} -+ -+#endif -+ - /* ------------------------ s390x ------------------------- */ - - #if defined(VGP_s390x_linux) -Index: coregrind/m_syscall.c -=================================================================== ---- coregrind/m_syscall.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syscall.c (.../trunk) (revision 13981) -@@ -128,6 +128,18 @@ - return res; - } - -+SysRes VG_(mk_SysRes_arm64_linux) ( Long val ) { -+ SysRes res; -+ res._valEx = 0; /* unused except on mips-linux */ -+ res._isError = val >= -4095 && val <= -1; -+ if (res._isError) { -+ res._val = (ULong)(-val); -+ } else { -+ res._val = (ULong)val; -+ } -+ return res; -+} -+ - /* MIPS uses a3 != 0 to flag an error */ - SysRes VG_(mk_SysRes_mips32_linux) ( UWord v0, UWord v1, UWord a3 ) { - SysRes res; -@@ -437,6 +449,34 @@ - ".previous\n" - ); - -+#elif defined(VGP_arm64_linux) -+/* I think the conventions are: -+ args in r0 r1 r2 r3 r4 r5 -+ sysno in r8 -+ return value in r0, w/ same conventions as x86-linux, viz r0 in -+ -4096 .. -1 is an error value. All other values are success -+ values. -+ -+ r0 to r5 remain unchanged, but syscall_no is in r6 and needs -+ to be moved to r8 (??) -+*/ -+extern UWord do_syscall_WRK ( -+ UWord a1, UWord a2, UWord a3, -+ UWord a4, UWord a5, UWord a6, -+ UWord syscall_no -+ ); -+asm( -+".text\n" -+".globl do_syscall_WRK\n" -+"do_syscall_WRK:\n" -+" mov x8, x6\n" -+" mov x6, 0\n" -+" mov x7, 0\n" -+" svc 0\n" -+" ret\n" -+".previous\n" -+); -+ - #elif defined(VGP_x86_darwin) - - /* Incoming args (syscall number + up to 8 args) come in on the stack -@@ -696,6 +736,10 @@ - UWord val = do_syscall_WRK(a1,a2,a3,a4,a5,a6,sysno); - return VG_(mk_SysRes_arm_linux)( val ); - -+# elif defined(VGP_arm64_linux) -+ UWord val = do_syscall_WRK(a1,a2,a3,a4,a5,a6,sysno); -+ return VG_(mk_SysRes_arm64_linux)( val ); -+ - # elif defined(VGP_x86_darwin) - UInt wLO = 0, wHI = 0, err = 0; - ULong u64; -Index: coregrind/m_syswrap/priv_syswrap-linux.h -=================================================================== ---- coregrind/m_syswrap/priv_syswrap-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/priv_syswrap-linux.h (.../trunk) (revision 13981) -@@ -146,6 +146,7 @@ - DECL_TEMPLATE(linux, sys_clock_gettime); - DECL_TEMPLATE(linux, sys_clock_getres); - DECL_TEMPLATE(linux, sys_clock_nanosleep); -+DECL_TEMPLATE(linux, sys_clock_adjtime); - - DECL_TEMPLATE(linux, sys_timer_create); // Linux: varies across archs? - DECL_TEMPLATE(linux, sys_timer_settime); -Index: coregrind/m_syswrap/priv_types_n_macros.h -=================================================================== ---- coregrind/m_syswrap/priv_types_n_macros.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/priv_types_n_macros.h (.../trunk) (revision 13981) -@@ -92,7 +92,7 @@ - # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ - || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_arm_linux) || defined(VGP_s390x_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - Int o_arg1; - Int o_arg2; - Int o_arg3; -Index: coregrind/m_syswrap/syscall-arm-linux.S -=================================================================== ---- coregrind/m_syswrap/syscall-arm-linux.S (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syscall-arm-linux.S (.../trunk) (revision 13981) -@@ -112,7 +112,7 @@ - ldr r3, [sp, #32] /* nsigwords */ - svc 0x00000000 - -- cmp r0, #0 -+ cmp r0, #0 - blt 7f - add sp, sp, #4 /* r0 contains return value */ - -Index: coregrind/m_syswrap/syscall-arm64-linux.S -=================================================================== ---- coregrind/m_syswrap/syscall-arm64-linux.S (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/m_syswrap/syscall-arm64-linux.S (.../trunk) (revision 13981) -@@ -0,0 +1,180 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Support for doing system calls. syscall-arm64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_vkiscnums_asm.h" -+#include "libvex_guest_offsets.h" -+ -+ -+/*----------------------------------------------------------------*/ -+/* -+ Perform a syscall for the client. This will run a syscall -+ with the client's specific per-thread signal mask. -+ -+ The structure of this function is such that, if the syscall is -+ interrupted by a signal, we can determine exactly what -+ execution state we were in with respect to the execution of -+ the syscall by examining the value of IP in the signal -+ handler. This means that we can always do the appropriate -+ thing to precisely emulate the kernel's signal/syscall -+ interactions. -+ -+ The syscall number is taken from the argument, even though it -+ should also be in guest_state->guest_X8. The syscall result -+ is written back to guest_state->guest_X0 on completion. -+ -+ Returns 0 if the syscall was successfully called (even if the -+ syscall itself failed), or a nonzero error code in the lowest -+ 8 bits if one of the sigprocmasks failed (there's no way to -+ determine which one failed). And there's no obvious way to -+ recover from that either, but nevertheless we want to know. -+ -+ VG_(fixup_guest_state_after_syscall_interrupted) does the -+ thread state fixup in the case where we were interrupted by a -+ signal. -+ -+ Prototype: -+ -+ UWord ML_(do_syscall_for_client_WRK)( -+ Int syscallno, // x0 -+ void* guest_state, // x1 -+ const vki_sigset_t *sysmask, // x2 -+ const vki_sigset_t *postmask, // x3 -+ Int nsigwords) // x4 -+*/ -+/* from vki-arm64-linux.h */ -+#define VKI_SIG_SETMASK 2 -+ -+.globl ML_(do_syscall_for_client_WRK) -+ML_(do_syscall_for_client_WRK): -+ -+ /* Stash callee-saves and our args on the stack */ -+ stp x29, x30, [sp, #-16]! -+ stp x27, x28, [sp, #-16]! -+ stp x25, x26, [sp, #-16]! -+ stp x23, x24, [sp, #-16]! -+ stp x21, x22, [sp, #-16]! -+ stp x19, x20, [sp, #-16]! -+ stp x4, x5, [sp, #-16]! -+ stp x2, x3, [sp, #-16]! -+ stp x0, x1, [sp, #-16]! -+ -+1: -+ -+ mov x8, #__NR_rt_sigprocmask -+ mov x0, #VKI_SIG_SETMASK -+ mov x1, x2 /* sysmask */ -+ mov x2, x3 /* postmask */ -+ mov x3, x4 /* nsigwords */ -+ svc 0x00000000 -+ -+ -+ ldr x5, [sp, #8] /* saved x1 == guest_state */ -+ -+ ldr x8, [sp, #0] /* saved x0 == syscall# */ -+ ldr x0, [x5, #OFFSET_arm64_X0] -+ ldr x1, [x5, #OFFSET_arm64_X1] -+ ldr x2, [x5, #OFFSET_arm64_X2] -+ ldr x3, [x5, #OFFSET_arm64_X3] -+ ldr x4, [x5, #OFFSET_arm64_X4] -+ ldr x5, [x5, #OFFSET_arm64_X5] -+ -+2: svc 0x00000000 -+3: -+ ldr x5, [sp, #8] /* saved x1 == guest_state */ -+ str x0, [x5, #OFFSET_arm64_X0] -+ -+4: -+ mov x8, #__NR_rt_sigprocmask -+ mov x0, #VKI_SIG_SETMASK -+ ldr x1, [sp, #24] /* saved x3 == postmask */ -+ mov x2, #0 -+ ldr x3, [sp, #32] /* saved x4 == nsigwords */ -+ svc 0x00000000 -+ -+ cmp x0, #0 -+ blt 7f -+ -+5: /* Success: return zero */ -+ mov x0, #0 -+ ldp xzr, x1, [sp], #16 -+ ldp x2, x3, [sp], #16 -+ ldp x4, x5, [sp], #16 -+ ldp x19, x20, [sp], #16 -+ ldp x21, x22, [sp], #16 -+ ldp x23, x24, [sp], #16 -+ ldp x25, x26, [sp], #16 -+ ldp x27, x28, [sp], #16 -+ ldp x29, x30, [sp], #16 -+ ret -+ -+7: /* Failure: return 0x8000 | error code */ -+ orr x0, x0, #0x8000 -+ ldp xzr, x1, [sp], #16 -+ ldp x2, x3, [sp], #16 -+ ldp x4, x5, [sp], #16 -+ ldp x19, x20, [sp], #16 -+ ldp x21, x22, [sp], #16 -+ ldp x23, x24, [sp], #16 -+ ldp x25, x26, [sp], #16 -+ ldp x27, x28, [sp], #16 -+ ldp x29, x30, [sp], #16 -+ ret -+ -+ -+ -+.section .rodata -+/* export the ranges so that -+ VG_(fixup_guest_state_after_syscall_interrupted) can do the -+ right thing */ -+ -+.globl ML_(blksys_setup) -+.globl ML_(blksys_restart) -+.globl ML_(blksys_complete) -+.globl ML_(blksys_committed) -+.globl ML_(blksys_finished) -+ML_(blksys_setup): .quad 1b -+ML_(blksys_restart): .quad 2b -+ML_(blksys_complete): .quad 3b -+ML_(blksys_committed): .quad 4b -+ML_(blksys_finished): .quad 5b -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",%progbits -+ -+.previous -+ -+#endif // defined(VGP_arm_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_syswrap/syswrap-amd64-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-amd64-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-amd64-linux.c (.../trunk) (revision 13981) -@@ -1048,7 +1048,7 @@ - LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 281 - LINXY(__NR_signalfd, sys_signalfd), // 282 - LINXY(__NR_timerfd_create, sys_timerfd_create), // 283 -- LINX_(__NR_eventfd, sys_eventfd), // 284 -+ LINXY(__NR_eventfd, sys_eventfd), // 284 - - LINX_(__NR_fallocate, sys_fallocate), // 285 - LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 286 -@@ -1056,7 +1056,7 @@ - LINXY(__NR_accept4, sys_accept4), // 288 - LINXY(__NR_signalfd4, sys_signalfd4), // 289 - -- LINX_(__NR_eventfd2, sys_eventfd2), // 290 -+ LINXY(__NR_eventfd2, sys_eventfd2), // 290 - LINXY(__NR_epoll_create1, sys_epoll_create1), // 291 - LINXY(__NR_dup3, sys_dup3), // 292 - LINXY(__NR_pipe2, sys_pipe2), // 293 -@@ -1074,7 +1074,7 @@ - LINXY(__NR_name_to_handle_at, sys_name_to_handle_at),// 303 - LINXY(__NR_open_by_handle_at, sys_open_by_handle_at),// 304 - --// LINX_(__NR_clock_adjtime, sys_ni_syscall), // 305 -+ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 305 - // LINX_(__NR_syncfs, sys_ni_syscall), // 306 - LINXY(__NR_sendmmsg, sys_sendmmsg), // 307 - // LINX_(__NR_setns, sys_ni_syscall), // 308 -Index: coregrind/m_syswrap/syswrap-arm-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-arm-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-arm-linux.c (.../trunk) (revision 13981) -@@ -1189,7 +1189,7 @@ - LINX_(__NR_utimensat, sys_utimensat), // 320 - LINXY(__NR_signalfd, sys_signalfd), // 321 - LINXY(__NR_timerfd_create, sys_timerfd_create), // 322 -- LINX_(__NR_eventfd, sys_eventfd), // 323 -+ LINXY(__NR_eventfd, sys_eventfd), // 323 - - LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 325 - LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 326 -@@ -1211,7 +1211,7 @@ - LINX_(__NR_fallocate, sys_fallocate), // 352 - - LINXY(__NR_signalfd4, sys_signalfd4), // 355 -- LINX_(__NR_eventfd2, sys_eventfd2), // 356 -+ LINXY(__NR_eventfd2, sys_eventfd2), // 356 - LINXY(__NR_epoll_create1, sys_epoll_create1), // 357 - LINXY(__NR_dup3, sys_dup3), // 358 - LINXY(__NR_pipe2, sys_pipe2), // 359 -@@ -1226,7 +1226,9 @@ - LINX_(__NR_fanotify_mark, sys_fanotify_mark), // 368 - LINXY(__NR_prlimit64, sys_prlimit64), // 369 - LINXY(__NR_name_to_handle_at, sys_name_to_handle_at),// 370 -- LINXY(__NR_open_by_handle_at, sys_open_by_handle_at) // 371 -+ LINXY(__NR_open_by_handle_at, sys_open_by_handle_at),// 371 -+ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 372 -+ LINXY(__NR_sendmmsg, sys_sendmmsg) // 374 - }; - - -Index: coregrind/m_syswrap/syswrap-arm64-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-arm64-linux.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/m_syswrap/syswrap-arm64-linux.c (.../trunk) (revision 13981) -@@ -0,0 +1,1449 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Platform-specific syscalls stuff. syswrap-arm64-linux.c -----*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics.h" -+#include "pub_core_vki.h" -+#include "pub_core_vkiscnums.h" -+#include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy -+#include "pub_core_threadstate.h" -+#include "pub_core_aspacemgr.h" -+//ZZ #include "pub_core_debuglog.h" -+#include "pub_core_libcbase.h" -+#include "pub_core_libcassert.h" -+#include "pub_core_libcprint.h" -+//ZZ #include "pub_core_libcproc.h" -+#include "pub_core_libcsignal.h" -+#include "pub_core_options.h" -+#include "pub_core_scheduler.h" -+#include "pub_core_sigframe.h" // For VG_(sigframe_destroy)() -+//ZZ #include "pub_core_signals.h" -+#include "pub_core_syscall.h" -+#include "pub_core_syswrap.h" -+#include "pub_core_tooliface.h" -+#include "pub_core_stacks.h" // VG_(register_stack) -+//ZZ #include "pub_core_transtab.h" // VG_(discard_translations) -+ -+#include "priv_types_n_macros.h" -+#include "priv_syswrap-generic.h" /* for decls of generic wrappers */ -+#include "priv_syswrap-linux.h" /* for decls of linux-ish wrappers */ -+//ZZ #include "priv_syswrap-main.h" -+ -+ -+/* --------------------------------------------------------------------- -+ clone() handling -+ ------------------------------------------------------------------ */ -+ -+/* Call f(arg1), but first switch stacks, using 'stack' as the new -+ stack, and use 'retaddr' as f's return-to address. Also, clear all -+ the integer registers before entering f.*/ -+__attribute__((noreturn)) -+void ML_(call_on_new_stack_0_1) ( Addr stack, -+ Addr retaddr, -+ void (*f)(Word), -+ Word arg1 ); -+// r0 = stack -+// r1 = retaddr -+// r2 = f -+// r3 = arg1 -+asm( -+".text\n" -+".globl vgModuleLocal_call_on_new_stack_0_1\n" -+"vgModuleLocal_call_on_new_stack_0_1:\n" -+" mov sp, x0\n\t" /* Stack pointer */ -+" mov x30, x1\n\t" /* Return address (x30 is LR) */ -+" mov x0, x3\n\t" /* First argument */ -+" mov x9, x2\n\t" /* 'f': x9 won't be zeroed at start of f. Oh well. */ -+" mov x1, #0\n\t" /* Clear our GPRs */ -+" mov x2, #0\n\t" -+" mov x3, #0\n\t" -+" mov x4, #0\n\t" -+" mov x5, #0\n\t" -+" mov x6, #0\n\t" -+" mov x7, #0\n\t" -+" mov x8, #0\n\t" -+/* don't zero out x9 */ -+" mov x10, #0\n\t" -+" mov x11, #0\n\t" -+" mov x12, #0\n\t" -+" mov x13, #0\n\t" -+" mov x14, #0\n\t" -+" mov x15, #0\n\t" -+" mov x16, #0\n\t" -+" mov x17, #0\n\t" -+" mov x18, #0\n\t" -+" mov x19, #0\n\t" -+" mov x20, #0\n\t" -+" mov x21, #0\n\t" -+" mov x22, #0\n\t" -+" mov x23, #0\n\t" -+" mov x24, #0\n\t" -+" mov x25, #0\n\t" -+" mov x26, #0\n\t" -+" mov x27, #0\n\t" -+" mov x28, #0\n\t" -+" mov x29, sp\n\t" /* FP = SP, in the absence of better suggestions */ -+" br x9\n\t" -+".previous\n" -+); -+ -+ -+/* -+ Perform a clone system call. clone is strange because it has -+ fork()-like return-twice semantics, so it needs special -+ handling here. -+ -+ Upon entry, we have: -+ -+ Word (*fn)(void*) in x0 -+ void* child_stack in x1 -+ int flags in x2 -+ void* arg in x3 -+ pid_t* child_tid in x4 -+ pid_t* parent_tid in x5 -+ void* tls_ptr in x6 -+ -+ System call requires: -+ -+ int $__NR_clone in x8 -+ int flags in x0 -+ void* child_stack in x1 -+ pid_t* parent_tid in x2 -+ void* tls_ptr in x3 -+ pid_t* child_tid in x4 -+ -+ Returns a Long encoded in the linux-arm64 way, not a SysRes. -+*/ -+#define __NR_CLONE VG_STRINGIFY(__NR_clone) -+#define __NR_EXIT VG_STRINGIFY(__NR_exit) -+ -+extern -+Long do_syscall_clone_arm64_linux ( Word (*fn)(void *), -+ void* child_stack, -+ Long flags, -+ void* arg, -+ Int* child_tid, -+ Int* parent_tid, -+ void* tls ); -+asm( -+".text\n" -+".globl do_syscall_clone_arm64_linux\n" -+"do_syscall_clone_arm64_linux:\n" -+ // set up child stack, temporarily preserving fn and arg -+" sub x1, x1, #16\n" // make space on stack -+" str x3, [x1, #8]\n" // save arg -+" str x0, [x1, #0]\n" // save fn -+ -+ // setup syscall -+" mov x8, #"__NR_CLONE"\n" // syscall number -+" mov x0, x2\n" // syscall arg1: flags -+" mov x1, x1\n" // syscall arg2: child_stack -+" mov x2, x5\n" // syscall arg3: parent_tid -+" mov x3, x6\n" // syscall arg4: tls_ptr -+" mov x4, x4\n" // syscall arg5: child_tid -+ -+" svc 0\n" // clone() -+ -+" cmp x0, #0\n" // child if retval == 0 -+" bne 1f\n" -+ -+ // CHILD - call thread function -+" ldr x1, [sp, #0]\n" // pop fn -+" ldr x0, [sp, #8]\n" // pop fn arg1: arg -+" add sp, sp, #16\n" -+" blr x1\n" // call fn -+ -+ // exit with result -+" mov x0, x0\n" // arg1: return value from fn -+" mov x8, #"__NR_EXIT"\n" -+ -+" svc 0\n" -+ -+ // Exit returned?! -+" .word 0xFFFFFFFF\n" -+ -+"1:\n" // PARENT or ERROR. x0 holds return value from the clone syscall. -+" ret\n" -+".previous\n" -+); -+ -+#undef __NR_CLONE -+#undef __NR_EXIT -+ -+// forward declaration -+static void setup_child ( ThreadArchState*, ThreadArchState* ); -+static void assign_guest_tls(ThreadId ctid, Addr tlsptr); -+//ZZ static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ); -+ -+/* -+ When a client clones, we need to keep track of the new thread. This means: -+ 1. allocate a ThreadId+ThreadState+stack for the the thread -+ -+ 2. initialize the thread's new VCPU state -+ -+ 3. create the thread using the same args as the client requested, -+ but using the scheduler entrypoint for IP, and a separate stack -+ for SP. -+ */ -+static SysRes do_clone ( ThreadId ptid, -+ ULong flags, -+ Addr child_xsp, -+ Int* parent_tidptr, -+ Int* child_tidptr, -+ Addr child_tls ) -+{ -+ const Bool debug = False; -+ -+ ThreadId ctid = VG_(alloc_ThreadState)(); -+ ThreadState* ptst = VG_(get_ThreadState)(ptid); -+ ThreadState* ctst = VG_(get_ThreadState)(ctid); -+ UWord* stack; -+ NSegment const* seg; -+ SysRes res; -+ ULong x0; -+ vki_sigset_t blockall, savedmask; -+ -+ VG_(sigfillset)(&blockall); -+ -+ vg_assert(VG_(is_running_thread)(ptid)); -+ vg_assert(VG_(is_valid_tid)(ctid)); -+ -+ stack = (UWord*)ML_(allocstack)(ctid); -+ if (stack == NULL) { -+ res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -+ goto out; -+ } -+ -+ /* Copy register state -+ -+ Both parent and child return to the same place, and the code -+ following the clone syscall works out which is which, so we -+ don't need to worry about it. -+ -+ The parent gets the child's new tid returned from clone, but the -+ child gets 0. -+ -+ If the clone call specifies a NULL xsp for the new thread, then -+ it actually gets a copy of the parent's xsp. -+ */ -+ setup_child( &ctst->arch, &ptst->arch ); -+ -+ /* Make sys_clone appear to have returned Success(0) in the -+ child. */ -+ ctst->arch.vex.guest_X0 = 0; -+ -+ if (child_xsp != 0) -+ ctst->arch.vex.guest_XSP = child_xsp; -+ -+ ctst->os_state.parent = ptid; -+ -+ /* inherit signal mask */ -+ ctst->sig_mask = ptst->sig_mask; -+ ctst->tmp_sig_mask = ptst->sig_mask; -+ -+ /* Start the child with its threadgroup being the same as the -+ parent's. This is so that any exit_group calls that happen -+ after the child is created but before it sets its -+ os_state.threadgroup field for real (in thread_wrapper in -+ syswrap-linux.c), really kill the new thread. a.k.a this avoids -+ a race condition in which the thread is unkillable (via -+ exit_group) because its threadgroup is not set. The race window -+ is probably only a few hundred or a few thousand cycles long. -+ See #226116. */ -+ ctst->os_state.threadgroup = ptst->os_state.threadgroup; -+ -+ /* We don't really know where the client stack is, because its -+ allocated by the client. The best we can do is look at the -+ memory mappings and try to derive some useful information. We -+ assume that xsp starts near its highest possible value, and can -+ only go down to the start of the mmaped segment. */ -+ seg = VG_(am_find_nsegment)((Addr)child_xsp); -+ if (seg && seg->kind != SkResvn) { -+ ctst->client_stack_highest_word = (Addr)VG_PGROUNDUP(child_xsp); -+ ctst->client_stack_szB = ctst->client_stack_highest_word - seg->start; -+ -+ VG_(register_stack)(seg->start, ctst->client_stack_highest_word); -+ -+ if (debug) -+ VG_(printf)("tid %d: guessed client stack range %#lx-%#lx\n", -+ ctid, seg->start, VG_PGROUNDUP(child_xsp)); -+ } else { -+ VG_(message)( -+ Vg_UserMsg, -+ "!? New thread %d starts with sp+%#lx) unmapped\n", ctid, child_xsp -+ ); -+ ctst->client_stack_szB = 0; -+ } -+ -+ /* Assume the clone will succeed, and tell any tool that wants to -+ know that this thread has come into existence. If the clone -+ fails, we'll send out a ll_exit notification for it at the out: -+ label below, to clean up. */ -+ vg_assert(VG_(owns_BigLock_LL)(ptid)); -+ VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -+ -+ if (flags & VKI_CLONE_SETTLS) { -+ /* Just assign the tls pointer in the guest TPIDR_EL0. */ -+ assign_guest_tls(ctid, child_tls); -+ } -+ -+ flags &= ~VKI_CLONE_SETTLS; -+ -+ /* start the thread with everything blocked */ -+ VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -+ -+ x0 = do_syscall_clone_arm64_linux( -+ ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], -+ child_tidptr, parent_tidptr, NULL -+ ); -+ -+ res = VG_(mk_SysRes_arm64_linux)( x0 ); -+ -+ VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -+ -+ out: -+ if (sr_isError(res)) { -+ /* clone failed */ -+ VG_(cleanup_thread)(&ctst->arch); -+ ctst->status = VgTs_Empty; -+ /* oops. Better tell the tool the thread exited in a hurry :-) */ -+ VG_TRACK( pre_thread_ll_exit, ctid ); -+ } -+ -+ return res; -+} -+ -+ -+/* --------------------------------------------------------------------- -+ More thread stuff -+ ------------------------------------------------------------------ */ -+ -+// ARM64 doesn't have any architecture specific thread stuff that -+// needs to be cleaned up -+void VG_(cleanup_thread) ( ThreadArchState* arch ) -+{ -+} -+ -+void setup_child ( /*OUT*/ ThreadArchState *child, -+ /*IN*/ ThreadArchState *parent ) -+{ -+ child->vex = parent->vex; -+ child->vex_shadow1 = parent->vex_shadow1; -+ child->vex_shadow2 = parent->vex_shadow2; -+} -+ -+static void assign_guest_tls(ThreadId tid, Addr tlsptr) -+{ -+ VG_(threads)[tid].arch.vex.guest_TPIDR_EL0 = tlsptr; -+} -+ -+//ZZ /* Assigns tlsptr to the guest TPIDRURO. -+//ZZ If needed for the specific hardware, really executes -+//ZZ the set_tls syscall. -+//ZZ */ -+//ZZ static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) -+//ZZ { -+//ZZ assign_guest_tls(tid, tlsptr); -+//ZZ #if defined(ANDROID_HARDWARE_emulator) -+//ZZ /* Android emulator does not provide an hw tls register. -+//ZZ So, the tls register is emulated by the kernel. -+//ZZ This emulated value is set by the __NR_ARM_set_tls syscall. -+//ZZ The emulated value must be read by the kernel helper function -+//ZZ located at 0xffff0fe0. -+//ZZ -+//ZZ The emulated tlsptr is located at 0xffff0ff0 -+//ZZ (so slightly after the kernel helper function). -+//ZZ Note that applications are not supposed to read this directly. -+//ZZ -+//ZZ For compatibility : if there is a hw tls register, the kernel -+//ZZ will put at 0xffff0fe0 the instructions to read it, so -+//ZZ as to have old applications calling the kernel helper -+//ZZ working properly. -+//ZZ -+//ZZ For having emulated guest TLS working correctly with -+//ZZ Valgrind, it is needed to execute the syscall to set -+//ZZ the emulated TLS value in addition to the assignment -+//ZZ of TPIDRURO. -+//ZZ -+//ZZ Note: the below means that if we need thread local storage -+//ZZ for Valgrind host, then there will be a conflict between -+//ZZ the need of the guest tls and of the host tls. -+//ZZ If all the guest code would cleanly call 0xffff0fe0, -+//ZZ then we might maybe intercept this. However, at least -+//ZZ __libc_preinit reads directly 0xffff0ff0. -+//ZZ */ -+//ZZ /* ??? might call the below if auxv->u.a_val & VKI_HWCAP_TLS ??? -+//ZZ Unclear if real hardware having tls hw register sets -+//ZZ VKI_HWCAP_TLS. */ -+//ZZ return VG_(do_syscall1) (__NR_ARM_set_tls, tlsptr); -+//ZZ #else -+//ZZ return VG_(mk_SysRes_Success)( 0 ); -+//ZZ #endif -+//ZZ } -+ -+/* --------------------------------------------------------------------- -+ PRE/POST wrappers for arm/Linux-specific syscalls -+ ------------------------------------------------------------------ */ -+ -+#define PRE(name) DEFN_PRE_TEMPLATE(arm64_linux, name) -+#define POST(name) DEFN_POST_TEMPLATE(arm64_linux, name) -+ -+/* Add prototypes for the wrappers declared here, so that gcc doesn't -+ harass us for not having prototypes. Really this is a kludge -- -+ the right thing to do is to make these wrappers 'static' since they -+ aren't visible outside this file, but that requires even more macro -+ magic. */ -+ -+DECL_TEMPLATE(arm64_linux, sys_fadvise64); -+DECL_TEMPLATE(arm64_linux, sys_mmap); -+//ZZ DECL_TEMPLATE(arm_linux, sys_stat64); -+//ZZ DECL_TEMPLATE(arm_linux, sys_lstat64); -+//ZZ DECL_TEMPLATE(arm_linux, sys_fstatat64); -+//ZZ DECL_TEMPLATE(arm_linux, sys_fstat64); -+DECL_TEMPLATE(arm64_linux, sys_clone); -+//ZZ DECL_TEMPLATE(arm_linux, sys_sigreturn); -+DECL_TEMPLATE(arm64_linux, sys_rt_sigreturn); -+//ZZ DECL_TEMPLATE(arm_linux, sys_sigsuspend); -+//ZZ DECL_TEMPLATE(arm_linux, sys_set_tls); -+//ZZ DECL_TEMPLATE(arm_linux, sys_cacheflush); -+//ZZ DECL_TEMPLATE(arm_linux, sys_ptrace); -+ -+//ZZ PRE(sys_mmap2) -+//ZZ { -+//ZZ SysRes r; -+//ZZ -+//ZZ // Exactly like old_mmap() except: -+//ZZ // - all 6 args are passed in regs, rather than in a memory-block. -+//ZZ // - the file offset is specified in pagesize units rather than bytes, -+//ZZ // so that it can be used for files bigger than 2^32 bytes. -+//ZZ // pagesize or 4K-size units in offset? For ppc32/64-linux, this is -+//ZZ // 4K-sized. Assert that the page size is 4K here for safety. -+//ZZ vg_assert(VKI_PAGE_SIZE == 4096); -+//ZZ PRINT("sys_mmap2 ( %#lx, %llu, %ld, %ld, %ld, %ld )", -+//ZZ ARG1, (ULong)ARG2, ARG3, ARG4, ARG5, ARG6 ); -+//ZZ PRE_REG_READ6(long, "mmap2", -+//ZZ unsigned long, start, unsigned long, length, -+//ZZ unsigned long, prot, unsigned long, flags, -+//ZZ unsigned long, fd, unsigned long, offset); -+//ZZ -+//ZZ r = ML_(generic_PRE_sys_mmap)( tid, ARG1, ARG2, ARG3, ARG4, ARG5, -+//ZZ 4096 * (Off64T)ARG6 ); -+//ZZ SET_STATUS_from_SysRes(r); -+//ZZ } -+ -+// ARM64 FIXME is this correct? -+PRE(sys_fadvise64) -+{ -+ PRINT("sys_fadvise64 ( %ld, %ld, %lu, %ld )", ARG1,ARG2,ARG3,ARG4); -+ PRE_REG_READ4(long, "fadvise64", -+ int, fd, vki_loff_t, offset, vki_size_t, len, int, advice); -+} -+ -+// ARM64 FIXME is this correct? -+PRE(sys_mmap) -+{ -+ SysRes r; -+ -+ PRINT("sys_mmap ( %#lx, %llu, %ld, %ld, %d, %ld )", -+ ARG1, (ULong)ARG2, ARG3, ARG4, (Int)ARG5, ARG6 ); -+ PRE_REG_READ6(long, "mmap", -+ unsigned long, start, unsigned long, length, -+ unsigned long, prot, unsigned long, flags, -+ unsigned long, fd, unsigned long, offset); -+ -+ r = ML_(generic_PRE_sys_mmap)( tid, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 ); -+ SET_STATUS_from_SysRes(r); -+} -+ -+//ZZ -+//ZZ // XXX: lstat64/fstat64/stat64 are generic, but not necessarily -+//ZZ // applicable to every architecture -- I think only to 32-bit archs. -+//ZZ // We're going to need something like linux/core_os32.h for such -+//ZZ // things, eventually, I think. --njn -+//ZZ PRE(sys_lstat64) -+//ZZ { -+//ZZ PRINT("sys_lstat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); -+//ZZ PRE_REG_READ2(long, "lstat64", char *, file_name, struct stat64 *, buf); -+//ZZ PRE_MEM_RASCIIZ( "lstat64(file_name)", ARG1 ); -+//ZZ PRE_MEM_WRITE( "lstat64(buf)", ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_lstat64) -+//ZZ { -+//ZZ vg_assert(SUCCESS); -+//ZZ if (RES == 0) { -+//ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ PRE(sys_stat64) -+//ZZ { -+//ZZ PRINT("sys_stat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); -+//ZZ PRE_REG_READ2(long, "stat64", char *, file_name, struct stat64 *, buf); -+//ZZ PRE_MEM_RASCIIZ( "stat64(file_name)", ARG1 ); -+//ZZ PRE_MEM_WRITE( "stat64(buf)", ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_stat64) -+//ZZ { -+//ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ PRE(sys_fstatat64) -+//ZZ { -+//ZZ PRINT("sys_fstatat64 ( %ld, %#lx(%s), %#lx )",ARG1,ARG2,(char*)ARG2,ARG3); -+//ZZ PRE_REG_READ3(long, "fstatat64", -+//ZZ int, dfd, char *, file_name, struct stat64 *, buf); -+//ZZ PRE_MEM_RASCIIZ( "fstatat64(file_name)", ARG2 ); -+//ZZ PRE_MEM_WRITE( "fstatat64(buf)", ARG3, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_fstatat64) -+//ZZ { -+//ZZ POST_MEM_WRITE( ARG3, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ PRE(sys_fstat64) -+//ZZ { -+//ZZ PRINT("sys_fstat64 ( %ld, %#lx )",ARG1,ARG2); -+//ZZ PRE_REG_READ2(long, "fstat64", unsigned long, fd, struct stat64 *, buf); -+//ZZ PRE_MEM_WRITE( "fstat64(buf)", ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_fstat64) -+//ZZ { -+//ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+ -+/* Aarch64 seems to use CONFIG_CLONE_BACKWARDS in the kernel. See: -+ http://dev.gentoo.org/~vapier/aarch64/linux-3.12.6.config -+ http://people.redhat.com/wcohen/aarch64/aarch64_config -+ from linux-3.10.5/kernel/fork.c -+ #ifdef CONFIG_CLONE_BACKWARDS -+ SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp, -+ int __user *, parent_tidptr, -+ int, tls_val, -+ int __user *, child_tidptr) -+*/ -+PRE(sys_clone) -+{ -+ UInt cloneflags; -+ -+ PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -+ PRE_REG_READ5(int, "clone", -+ unsigned long, flags, -+ void *, child_stack, -+ int *, parent_tidptr, -+ void *, child_tls, -+ int *, child_tidptr); -+ -+ if (ARG1 & VKI_CLONE_PARENT_SETTID) { -+ PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -+ if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -+ VKI_PROT_WRITE)) { -+ SET_STATUS_Failure( VKI_EFAULT ); -+ return; -+ } -+ } -+//ZZ if (ARG1 & VKI_CLONE_SETTLS) { -+//ZZ PRE_MEM_READ("clone(tls_user_desc)", ARG4, sizeof(vki_modify_ldt_t)); -+//ZZ if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t), -+//ZZ VKI_PROT_READ)) { -+//ZZ SET_STATUS_Failure( VKI_EFAULT ); -+//ZZ return; -+//ZZ } -+//ZZ } -+ if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -+ PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); -+ if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), -+ VKI_PROT_WRITE)) { -+ SET_STATUS_Failure( VKI_EFAULT ); -+ return; -+ } -+ } -+ -+ cloneflags = ARG1; -+ -+ if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -+ SET_STATUS_Failure( VKI_EINVAL ); -+ return; -+ } -+ -+ /* Only look at the flags we really care about */ -+ switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -+ | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -+ case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -+ /* thread creation */ -+ SET_STATUS_from_SysRes( -+ do_clone(tid, -+ ARG1, /* flags */ -+ (Addr)ARG2, /* child SP */ -+ (Int*)ARG3, /* parent_tidptr */ -+ (Int*)ARG5, /* child_tidptr */ -+ (Addr)ARG4)); /* tls_val */ -+ break; -+ -+ case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -+ /* FALLTHROUGH - assume vfork == fork */ -+ cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -+ -+ case 0: /* plain fork */ -+ SET_STATUS_from_SysRes( -+ ML_(do_fork_clone)(tid, -+ cloneflags, /* flags */ -+ (Int*)ARG3, /* parent_tidptr */ -+ (Int*)ARG5)); /* child_tidptr */ -+ break; -+ -+ default: -+ /* should we just ENOSYS? */ -+ VG_(message)(Vg_UserMsg, ""); -+ VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx", ARG1); -+ VG_(message)(Vg_UserMsg, ""); -+ VG_(message)(Vg_UserMsg, "The only supported clone() uses are:"); -+ VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)"); -+ VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork"); -+ VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver"); -+ VG_(unimplemented) -+ ("Valgrind does not support general clone()."); -+ } -+ -+ if (SUCCESS) { -+ if (ARG1 & VKI_CLONE_PARENT_SETTID) -+ POST_MEM_WRITE(ARG3, sizeof(Int)); -+ if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -+ POST_MEM_WRITE(ARG5, sizeof(Int)); -+ -+ /* Thread creation was successful; let the child have the chance -+ to run */ -+ *flags |= SfYieldAfter; -+ } -+} -+ -+//ZZ PRE(sys_sigreturn) -+//ZZ { -+//ZZ /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -+//ZZ an explanation of what follows. */ -+//ZZ -+//ZZ PRINT("sys_sigreturn ( )"); -+//ZZ -+//ZZ vg_assert(VG_(is_valid_tid)(tid)); -+//ZZ vg_assert(tid >= 1 && tid < VG_N_THREADS); -+//ZZ vg_assert(VG_(is_running_thread)(tid)); -+//ZZ -+//ZZ /* Restore register state from frame and remove it */ -+//ZZ VG_(sigframe_destroy)(tid, False); -+//ZZ -+//ZZ /* Tell the driver not to update the guest state with the "result", -+//ZZ and set a bogus result to keep it happy. */ -+//ZZ *flags |= SfNoWriteResult; -+//ZZ SET_STATUS_Success(0); -+//ZZ -+//ZZ /* Check to see if any signals arose as a result of this. */ -+//ZZ *flags |= SfPollAfter; -+//ZZ } -+ -+PRE(sys_rt_sigreturn) -+{ -+ /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -+ an explanation of what follows. */ -+ -+ PRINT("rt_sigreturn ( )"); -+ -+ vg_assert(VG_(is_valid_tid)(tid)); -+ vg_assert(tid >= 1 && tid < VG_N_THREADS); -+ vg_assert(VG_(is_running_thread)(tid)); -+ -+ /* Restore register state from frame and remove it */ -+ VG_(sigframe_destroy)(tid, True); -+ -+ /* Tell the driver not to update the guest state with the "result", -+ and set a bogus result to keep it happy. */ -+ *flags |= SfNoWriteResult; -+ SET_STATUS_Success(0); -+ -+ /* Check to see if any signals arose as a result of this. */ -+ *flags |= SfPollAfter; -+} -+ -+//ZZ /* NB: clone of x86-linux version, and ppc32-linux has an almost -+//ZZ identical one. */ -+//ZZ PRE(sys_sigsuspend) -+//ZZ { -+//ZZ /* The C library interface to sigsuspend just takes a pointer to -+//ZZ a signal mask but this system call has three arguments - the first -+//ZZ two don't appear to be used by the kernel and are always passed as -+//ZZ zero by glibc and the third is the first word of the signal mask -+//ZZ so only 32 signals are supported. -+//ZZ -+//ZZ In fact glibc normally uses rt_sigsuspend if it is available as -+//ZZ that takes a pointer to the signal mask so supports more signals. -+//ZZ */ -+//ZZ *flags |= SfMayBlock; -+//ZZ PRINT("sys_sigsuspend ( %ld, %ld, %ld )", ARG1,ARG2,ARG3 ); -+//ZZ PRE_REG_READ3(int, "sigsuspend", -+//ZZ int, history0, int, history1, -+//ZZ vki_old_sigset_t, mask); -+//ZZ } -+//ZZ -+//ZZ /* Very much ARM specific */ -+//ZZ -+//ZZ PRE(sys_set_tls) -+//ZZ { -+//ZZ PRINT("set_tls (%lx)",ARG1); -+//ZZ PRE_REG_READ1(long, "set_tls", unsigned long, addr); -+//ZZ -+//ZZ SET_STATUS_from_SysRes( sys_set_tls( tid, ARG1 ) ); -+//ZZ } -+//ZZ -+//ZZ PRE(sys_cacheflush) -+//ZZ { -+//ZZ PRINT("cacheflush (%lx, %#lx, %#lx)",ARG1,ARG2,ARG3); -+//ZZ PRE_REG_READ3(long, "cacheflush", void*, addrlow,void*, addrhigh,int, flags); -+//ZZ VG_(discard_translations)( (Addr64)ARG1, -+//ZZ ((ULong)ARG2) - ((ULong)ARG1) + 1ULL/*paranoia*/, -+//ZZ "PRE(sys_cacheflush)" ); -+//ZZ SET_STATUS_Success(0); -+//ZZ } -+//ZZ -+//ZZ // ARG3 is only used for pointers into the traced process's address -+//ZZ // space and for offsets into the traced process's struct -+//ZZ // user_regs_struct. It is never a pointer into this process's memory -+//ZZ // space, and we should therefore not check anything it points to. -+//ZZ PRE(sys_ptrace) -+//ZZ { -+//ZZ PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4); -+//ZZ PRE_REG_READ4(int, "ptrace", -+//ZZ long, request, long, pid, long, addr, long, data); -+//ZZ switch (ARG1) { -+//ZZ case VKI_PTRACE_PEEKTEXT: -+//ZZ case VKI_PTRACE_PEEKDATA: -+//ZZ case VKI_PTRACE_PEEKUSR: -+//ZZ PRE_MEM_WRITE( "ptrace(peek)", ARG4, -+//ZZ sizeof (long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getregs)", ARG4, -+//ZZ sizeof (struct vki_user_regs_struct)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETFPREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_fp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETWMMXREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getwmmxregs)", ARG4, -+//ZZ VKI_IWMMXT_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETCRUNCHREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getcrunchregs)", ARG4, -+//ZZ VKI_CRUNCH_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETVFPREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getvfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_vfp) ); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETHBPREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(gethbpregs)", ARG4, -+//ZZ sizeof (unsigned long) ); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETREGS: -+//ZZ PRE_MEM_READ( "ptrace(setregs)", ARG4, -+//ZZ sizeof (struct vki_user_regs_struct)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETFPREGS: -+//ZZ PRE_MEM_READ( "ptrace(setfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_fp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETWMMXREGS: -+//ZZ PRE_MEM_READ( "ptrace(setwmmxregs)", ARG4, -+//ZZ VKI_IWMMXT_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETCRUNCHREGS: -+//ZZ PRE_MEM_READ( "ptrace(setcrunchregs)", ARG4, -+//ZZ VKI_CRUNCH_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETVFPREGS: -+//ZZ PRE_MEM_READ( "ptrace(setvfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_vfp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETHBPREGS: -+//ZZ PRE_MEM_READ( "ptrace(sethbpregs)", ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GET_THREAD_AREA: -+//ZZ PRE_MEM_WRITE( "ptrace(get_thread_area)", ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETEVENTMSG: -+//ZZ PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETSIGINFO: -+//ZZ PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETSIGINFO: -+//ZZ PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGSET: -+//ZZ ML_(linux_PRE_getregset)(tid, ARG3, ARG4); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETREGSET: -+//ZZ ML_(linux_PRE_setregset)(tid, ARG3, ARG4); -+//ZZ break; -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ POST(sys_ptrace) -+//ZZ { -+//ZZ switch (ARG1) { -+//ZZ case VKI_PTRACE_PEEKTEXT: -+//ZZ case VKI_PTRACE_PEEKDATA: -+//ZZ case VKI_PTRACE_PEEKUSR: -+//ZZ POST_MEM_WRITE( ARG4, sizeof (long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGS: -+//ZZ POST_MEM_WRITE( ARG4, sizeof (struct vki_user_regs_struct)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETFPREGS: -+//ZZ POST_MEM_WRITE( ARG4, sizeof (struct vki_user_fp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETWMMXREGS: -+//ZZ POST_MEM_WRITE( ARG4, VKI_IWMMXT_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETCRUNCHREGS: -+//ZZ POST_MEM_WRITE( ARG4, VKI_CRUNCH_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETVFPREGS: -+//ZZ POST_MEM_WRITE( ARG4, sizeof(struct vki_user_vfp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GET_THREAD_AREA: -+//ZZ case VKI_PTRACE_GETHBPREGS: -+//ZZ case VKI_PTRACE_GETEVENTMSG: -+//ZZ POST_MEM_WRITE( ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETSIGINFO: -+//ZZ /* XXX: This is a simplification. Different parts of the -+//ZZ * siginfo_t are valid depending on the type of signal. -+//ZZ */ -+//ZZ POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGSET: -+//ZZ ML_(linux_POST_getregset)(tid, ARG3, ARG4); -+//ZZ break; -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ #undef PRE -+//ZZ #undef POST -+ -+/* --------------------------------------------------------------------- -+ The arm64/Linux syscall table -+ ------------------------------------------------------------------ */ -+ -+//ZZ #if 0 -+//ZZ #define __NR_OABI_SYSCALL_BASE 0x900000 -+//ZZ #else -+//ZZ #define __NR_OABI_SYSCALL_BASE 0x0 -+//ZZ #endif -+ -+#define PLAX_(sysno, name) WRAPPER_ENTRY_X_(arm64_linux, sysno, name) -+#define PLAXY(sysno, name) WRAPPER_ENTRY_XY(arm64_linux, sysno, name) -+ -+// This table maps from __NR_xxx syscall numbers (from -+// linux/include/asm-arm/unistd.h) to the appropriate PRE/POST sys_foo() -+// wrappers on arm64 (as per sys_call_table in linux/arch/arm/kernel/entry.S). -+// -+// For those syscalls not handled by Valgrind, the annotation indicate its -+// arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/? -+// (unknown). -+ -+static SyscallTableEntry syscall_main_table[] = { -+ LINXY(__NR_getxattr, sys_getxattr), // 8 -+ LINXY(__NR_lgetxattr, sys_lgetxattr), // 9 -+ GENXY(__NR_getcwd, sys_getcwd), // 17 -+ LINXY(__NR_eventfd2, sys_eventfd2), // 19 -+ LINXY(__NR_epoll_create1, sys_epoll_create1), // 20 -+ LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 21 -+ LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 22 -+ GENXY(__NR_dup, sys_dup), // 23 -+ LINXY(__NR_dup3, sys_dup3), // 24 -+ -+ // FIXME IS THIS CORRECT? -+ LINXY(__NR3264_fcntl, sys_fcntl), // 25 -+ -+ LINXY(__NR_inotify_init1, sys_inotify_init1), // 26 -+ LINX_(__NR_inotify_add_watch, sys_inotify_add_watch), // 27 -+ LINX_(__NR_inotify_rm_watch, sys_inotify_rm_watch), // 28 -+ LINXY(__NR_ioctl, sys_ioctl), // 29 -+ LINX_(__NR_mkdirat, sys_mkdirat), // 34 -+ LINX_(__NR_unlinkat, sys_unlinkat), // 35 -+ LINX_(__NR_symlinkat, sys_symlinkat), // 36 -+ LINX_(__NR_linkat, sys_linkat), // 37 -+ LINX_(__NR_renameat, sys_renameat), // 38 -+ -+ // FIXME IS THIS CORRECT? it may well not be. -+ GENXY(__NR3264_statfs, sys_statfs), // 43 -+ GENXY(__NR3264_fstatfs, sys_fstatfs), // 44 -+ -+ // FIXME IS THIS CORRECT? it may well not be. -+ GENX_(__NR3264_ftruncate, sys_ftruncate), // 46 -+ -+ LINX_(__NR_fallocate, sys_fallocate), // 47 -+ LINX_(__NR_faccessat, sys_faccessat), // 48 -+ GENX_(__NR_chdir, sys_chdir), // 49 -+ LINXY(__NR_openat, sys_openat), // 56 -+ GENXY(__NR_close, sys_close), // 57 -+ LINXY(__NR_pipe2, sys_pipe2), // 59 -+ LINX_(__NR_quotactl, sys_quotactl), // 60 -+ GENXY(__NR_getdents64, sys_getdents64), // 61 -+ -+ // FIXME IS THIS CORRECT? -+ LINX_(__NR3264_lseek, sys_lseek), // 62 -+ -+ GENXY(__NR_read, sys_read), // 63 -+ GENX_(__NR_write, sys_write), // 64 -+ GENXY(__NR_readv, sys_readv), // 65 -+ GENX_(__NR_writev, sys_writev), // 66 -+ GENX_(__NR_pwrite64, sys_pwrite64), // 68 -+ LINX_(__NR_pselect6, sys_pselect6), // 72 -+ LINXY(__NR_ppoll, sys_ppoll), // 73 -+ LINXY(__NR_signalfd4, sys_signalfd4), // 74 -+ LINX_(__NR_readlinkat, sys_readlinkat), // 78 -+ -+ // FIXME IS THIS CORRECT? -+ LINXY(__NR3264_fstatat, sys_newfstatat), // 79 -+ GENXY(__NR3264_fstat, sys_newfstat), // 80 -+ -+ LINX_(__NR_utimensat, sys_utimensat), // 88 -+ GENX_(__NR_fsync, sys_fsync), // 82 -+ LINXY(__NR_timerfd_create, sys_timerfd_create), // 85 -+ LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 86 -+ LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 87 -+ LINXY(__NR_capget, sys_capget), // 90 -+ GENX_(__NR_exit, sys_exit), // 93 -+ LINX_(__NR_exit_group, sys_exit_group), // 94 -+ LINX_(__NR_set_tid_address, sys_set_tid_address), // 96 -+ LINXY(__NR_futex, sys_futex), // 98 -+ LINX_(__NR_set_robust_list, sys_set_robust_list), // 99 -+ GENXY(__NR_nanosleep, sys_nanosleep), // 101 -+ GENXY(__NR_setitimer, sys_setitimer), // 103 -+ LINXY(__NR_clock_gettime, sys_clock_gettime), // 113 -+ LINXY(__NR_clock_getres, sys_clock_getres), // 114 -+ LINXY(__NR_syslog, sys_syslog), // 116 -+ LINX_(__NR_sched_setaffinity, sys_sched_setaffinity), // 122 -+ LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 123 -+ LINX_(__NR_sched_yield, sys_sched_yield), // 124 -+ GENX_(__NR_kill, sys_kill), // 129 -+ LINX_(__NR_tgkill, sys_tgkill), // 131 -+ GENXY(__NR_sigaltstack, sys_sigaltstack), // 132 -+ LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 133 -+ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 134 -+ LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 135 -+ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 137 -+ LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 138 -+ PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139 -+ GENX_(__NR_setpriority, sys_setpriority), // 140 -+ GENX_(__NR_getpriority, sys_getpriority), // 141 -+ LINX_(__NR_setresuid, sys_setresuid), // 147 -+ LINXY(__NR_getresuid, sys_getresuid), // 148 -+ LINXY(__NR_getresgid, sys_getresgid), // 150 -+ GENX_(__NR_setpgid, sys_setpgid), // 154 -+ GENX_(__NR_getpgid, sys_getpgid), // 155 -+ GENXY(__NR_uname, sys_newuname), // 160 -+ GENXY(__NR_getrlimit, sys_old_getrlimit), // 163 -+ GENX_(__NR_setrlimit, sys_setrlimit), // 164 -+ GENXY(__NR_getrusage, sys_getrusage), // 165 -+ GENX_(__NR_umask, sys_umask), // 166 -+ LINXY(__NR_prctl, sys_prctl), // 167 -+ GENXY(__NR_gettimeofday, sys_gettimeofday), // 169 -+ GENX_(__NR_getpid, sys_getpid), // 172 -+ GENX_(__NR_getppid, sys_getppid), // 173 -+ GENX_(__NR_getuid, sys_getuid), // 174 -+ GENX_(__NR_geteuid, sys_geteuid), // 175 -+ GENX_(__NR_getgid, sys_getgid), // 176 -+ GENX_(__NR_getegid, sys_getegid), // 177 -+ LINX_(__NR_gettid, sys_gettid), // 178 -+ LINXY(__NR_sysinfo, sys_sysinfo), // 179 -+ LINXY(__NR_mq_open, sys_mq_open), // 180 -+ LINX_(__NR_mq_unlink, sys_mq_unlink), // 181 -+ LINX_(__NR_mq_timedsend, sys_mq_timedsend), // 182 -+ LINXY(__NR_mq_timedreceive, sys_mq_timedreceive), // 183 -+ LINX_(__NR_mq_notify, sys_mq_notify), // 184 -+ LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // 185 -+ LINX_(__NR_semget, sys_semget), // 190 -+ LINXY(__NR_semctl, sys_semctl), // 191 -+ LINX_(__NR_semtimedop, sys_semtimedop), // 192 -+ LINX_(__NR_semop, sys_semop), // 193 -+ LINX_(__NR_shmget, sys_shmget), // 194 -+ LINXY(__NR_shmctl, sys_shmctl), // 195 -+ LINXY(__NR_shmat, wrap_sys_shmat), // 196 -+ LINXY(__NR_shmdt, sys_shmdt), // 197 -+ LINXY(__NR_socket, sys_socket), // 198 -+ LINXY(__NR_socketpair, sys_socketpair), // 199 -+ LINX_(__NR_bind, sys_bind), // 200 -+ LINX_(__NR_listen, sys_listen), // 201 -+ LINXY(__NR_accept, sys_accept), // 202 -+ LINX_(__NR_connect, sys_connect), // 203 -+ LINXY(__NR_getsockname, sys_getsockname), // 204 -+ LINXY(__NR_getpeername, sys_getpeername), // 205 -+ LINX_(__NR_sendto, sys_sendto), // 206 -+ LINXY(__NR_recvfrom, sys_recvfrom), // 207 -+ LINX_(__NR_setsockopt, sys_setsockopt), // 208 -+ LINXY(__NR_getsockopt, sys_getsockopt), // 209 -+ LINX_(__NR_shutdown, sys_shutdown), // 210 -+ LINX_(__NR_sendmsg, sys_sendmsg), // 211 -+ LINXY(__NR_recvmsg, sys_recvmsg), // 212 -+ LINX_(__NR_readahead, sys_readahead), // 213 -+ GENX_(__NR_brk, sys_brk), // 214 -+ GENXY(__NR_munmap, sys_munmap), // 215 -+ GENX_(__NR_mremap, sys_mremap), // 216 -+ LINX_(__NR_add_key, sys_add_key), // 217 -+ LINXY(__NR_keyctl, sys_keyctl), // 219 -+ PLAX_(__NR_clone, sys_clone), // 220 -+ GENX_(__NR_execve, sys_execve), // 221 -+ -+ // FIXME IS THIS CORRECT? -+ PLAX_(__NR3264_mmap, sys_mmap), // 222 -+ PLAX_(__NR3264_fadvise64, sys_fadvise64), // 223 -+ -+ GENXY(__NR_mprotect, sys_mprotect), // 226 -+ GENX_(__NR_madvise, sys_madvise), // 233 -+ GENXY(__NR_wait4, sys_wait4), // 260 -+ -+ LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 270 -+ LINX_(__NR_process_vm_writev, sys_process_vm_writev), // 271 -+ -+// The numbers below are bogus. (See comment further down.) -+// When pulling entries above this line, change the numbers -+// to be correct. -+ -+//ZZ //zz // (restart_syscall) // 0 -+//ZZ GENX_(__NR_fork, sys_fork), // 2 -+//ZZ -+//ZZ GENXY(__NR_open, sys_open), // 5 -+//ZZ // GENXY(__NR_waitpid, sys_waitpid), // 7 -+//ZZ GENXY(__NR_creat, sys_creat), // 8 -+//ZZ GENX_(__NR_link, sys_link), // 9 -+//ZZ -+//ZZ GENX_(__NR_unlink, sys_unlink), // 10 -+//ZZ GENXY(__NR_time, sys_time), // 13 -+//ZZ GENX_(__NR_mknod, sys_mknod), // 14 -+//ZZ -+//ZZ GENX_(__NR_chmod, sys_chmod), // 15 -+//ZZ //zz LINX_(__NR_lchown, sys_lchown16), // 16 -+//ZZ // GENX_(__NR_break, sys_ni_syscall), // 17 -+//ZZ //zz // (__NR_oldstat, sys_stat), // 18 (obsolete) -+//ZZ LINX_(__NR_lseek, sys_lseek), // 19 -+//ZZ -+//ZZ GENX_(__NR_getpid, sys_getpid), // 20 -+//ZZ LINX_(__NR_mount, sys_mount), // 21 -+//ZZ LINX_(__NR_umount, sys_oldumount), // 22 -+//ZZ LINX_(__NR_setuid, sys_setuid16), // 23 ## P -+//ZZ LINX_(__NR_getuid, sys_getuid16), // 24 ## P -+//ZZ //zz -+//ZZ //zz // (__NR_stime, sys_stime), // 25 * (SVr4,SVID,X/OPEN) -+//ZZ PLAXY(__NR_ptrace, sys_ptrace), // 26 -+//ZZ GENX_(__NR_alarm, sys_alarm), // 27 -+//ZZ //zz // (__NR_oldfstat, sys_fstat), // 28 * L -- obsolete -+//ZZ GENX_(__NR_pause, sys_pause), // 29 -+//ZZ -+//ZZ LINX_(__NR_utime, sys_utime), // 30 -+//ZZ // GENX_(__NR_stty, sys_ni_syscall), // 31 -+//ZZ // GENX_(__NR_gtty, sys_ni_syscall), // 32 -+//ZZ GENX_(__NR_access, sys_access), // 33 -+//ZZ GENX_(__NR_nice, sys_nice), // 34 -+//ZZ -+//ZZ // GENX_(__NR_ftime, sys_ni_syscall), // 35 -+//ZZ GENX_(__NR_sync, sys_sync), // 36 -+//ZZ GENX_(__NR_rename, sys_rename), // 38 -+//ZZ GENX_(__NR_mkdir, sys_mkdir), // 39 -+//ZZ -+//ZZ GENX_(__NR_rmdir, sys_rmdir), // 40 -+//ZZ LINXY(__NR_pipe, sys_pipe), // 42 -+//ZZ GENXY(__NR_times, sys_times), // 43 -+//ZZ // GENX_(__NR_prof, sys_ni_syscall), // 44 -+ -+//ZZ LINX_(__NR_setgid, sys_setgid16), // 46 -+//ZZ LINX_(__NR_getgid, sys_getgid16), // 47 -+//ZZ //zz // (__NR_signal, sys_signal), // 48 */* (ANSI C) -+//ZZ LINX_(__NR_geteuid, sys_geteuid16), // 49 -+//ZZ -+//ZZ LINX_(__NR_getegid, sys_getegid16), // 50 -+//ZZ GENX_(__NR_acct, sys_acct), // 51 -+//ZZ LINX_(__NR_umount2, sys_umount), // 52 -+//ZZ // GENX_(__NR_lock, sys_ni_syscall), // 53 -+//ZZ -+//ZZ LINXY(__NR_fcntl, sys_fcntl), // 55 -+//ZZ // GENX_(__NR_mpx, sys_ni_syscall), // 56 -+//ZZ // GENX_(__NR_ulimit, sys_ni_syscall), // 58 -+//ZZ //zz // (__NR_oldolduname, sys_olduname), // 59 Linux -- obsolete -+//ZZ //zz -+//ZZ GENX_(__NR_chroot, sys_chroot), // 61 -+//ZZ //zz // (__NR_ustat, sys_ustat) // 62 SVr4 -- deprecated -+//ZZ GENXY(__NR_dup2, sys_dup2), // 63 -+//ZZ GENX_(__NR_getppid, sys_getppid), // 64 -+//ZZ -+//ZZ GENX_(__NR_getpgrp, sys_getpgrp), // 65 -+//ZZ GENX_(__NR_setsid, sys_setsid), // 66 -+//ZZ LINXY(__NR_sigaction, sys_sigaction), // 67 -+//ZZ //zz // (__NR_sgetmask, sys_sgetmask), // 68 */* (ANSI C) -+//ZZ //zz // (__NR_ssetmask, sys_ssetmask), // 69 */* (ANSI C) -+//ZZ //zz -+//ZZ LINX_(__NR_setreuid, sys_setreuid16), // 70 -+//ZZ LINX_(__NR_setregid, sys_setregid16), // 71 -+//ZZ PLAX_(__NR_sigsuspend, sys_sigsuspend), // 72 -+//ZZ LINXY(__NR_sigpending, sys_sigpending), // 73 -+//ZZ //zz // (__NR_sethostname, sys_sethostname), // 74 */* -+//ZZ //zz -+//ZZ GENXY(__NR_getrlimit, sys_old_getrlimit), // 76 -+//ZZ GENX_(__NR_settimeofday, sys_settimeofday), // 79 -+//ZZ -+//ZZ LINXY(__NR_getgroups, sys_getgroups16), // 80 -+//ZZ LINX_(__NR_setgroups, sys_setgroups16), // 81 -+//ZZ // PLAX_(__NR_select, old_select), // 82 -+//ZZ GENX_(__NR_symlink, sys_symlink), // 83 -+//ZZ //zz // (__NR_oldlstat, sys_lstat), // 84 -- obsolete -+//ZZ //zz -+//ZZ GENX_(__NR_readlink, sys_readlink), // 85 -+//ZZ //zz // (__NR_uselib, sys_uselib), // 86 */Linux -+//ZZ //zz // (__NR_swapon, sys_swapon), // 87 */Linux -+//ZZ //zz // (__NR_reboot, sys_reboot), // 88 */Linux -+//ZZ //zz // (__NR_readdir, old_readdir), // 89 -- superseded -+//ZZ //zz -+//ZZ // _____(__NR_mmap, old_mmap), // 90 -+//ZZ GENXY(__NR_munmap, sys_munmap), // 91 -+//ZZ GENX_(__NR_truncate, sys_truncate), // 92 -+//ZZ GENX_(__NR_ftruncate, sys_ftruncate), // 93 -+//ZZ GENX_(__NR_fchmod, sys_fchmod), // 94 -+//ZZ -+//ZZ LINX_(__NR_fchown, sys_fchown16), // 95 -+//ZZ // GENX_(__NR_profil, sys_ni_syscall), // 98 -+//ZZ GENXY(__NR_statfs, sys_statfs), // 99 -+//ZZ -+//ZZ GENXY(__NR_fstatfs, sys_fstatfs), // 100 -+//ZZ // LINX_(__NR_ioperm, sys_ioperm), // 101 -+//ZZ LINXY(__NR_socketcall, sys_socketcall), // 102 -+//ZZ -+//ZZ GENXY(__NR_getitimer, sys_getitimer), // 105 -+//ZZ GENXY(__NR_stat, sys_newstat), // 106 -+//ZZ GENXY(__NR_lstat, sys_newlstat), // 107 -+//ZZ GENXY(__NR_fstat, sys_newfstat), // 108 -+//ZZ //zz // (__NR_olduname, sys_uname), // 109 -- obsolete -+//ZZ //zz -+//ZZ // GENX_(__NR_iopl, sys_iopl), // 110 -+//ZZ LINX_(__NR_vhangup, sys_vhangup), // 111 -+//ZZ // GENX_(__NR_idle, sys_ni_syscall), // 112 -+//ZZ // PLAXY(__NR_vm86old, sys_vm86old), // 113 __NR_syscall... weird -+//ZZ //zz -+//ZZ //zz // (__NR_swapoff, sys_swapoff), // 115 */Linux -+//ZZ // _____(__NR_ipc, sys_ipc), // 117 -+//ZZ GENX_(__NR_fsync, sys_fsync), // 118 -+//ZZ PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux -+//ZZ -+//ZZ //zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) -+//ZZ // PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 -+//ZZ //zz LINXY(__NR_adjtimex, sys_adjtimex), // 124 -+//ZZ //zz -+//ZZ LINXY(__NR_sigprocmask, sys_sigprocmask), // 126 -+//ZZ //zz // Nb: create_module() was removed 2.4-->2.6 -+//ZZ // GENX_(__NR_create_module, sys_ni_syscall), // 127 -+//ZZ LINX_(__NR_init_module, sys_init_module), // 128 -+//ZZ LINX_(__NR_delete_module, sys_delete_module), // 129 -+//ZZ //zz -+//ZZ //zz // Nb: get_kernel_syms() was removed 2.4-->2.6 -+//ZZ // GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 130 -+//ZZ GENX_(__NR_getpgid, sys_getpgid), // 132 -+//ZZ GENX_(__NR_fchdir, sys_fchdir), // 133 -+//ZZ //zz // (__NR_bdflush, sys_bdflush), // 134 */Linux -+//ZZ //zz -+//ZZ //zz // (__NR_sysfs, sys_sysfs), // 135 SVr4 -+//ZZ LINX_(__NR_personality, sys_personality), // 136 -+//ZZ // GENX_(__NR_afs_syscall, sys_ni_syscall), // 137 -+//ZZ LINX_(__NR_setfsuid, sys_setfsuid16), // 138 -+//ZZ LINX_(__NR_setfsgid, sys_setfsgid16), // 139 -+//ZZ -+//ZZ LINXY(__NR__llseek, sys_llseek), // 140 -+//ZZ GENXY(__NR_getdents, sys_getdents), // 141 -+//ZZ GENX_(__NR__newselect, sys_select), // 142 -+//ZZ GENX_(__NR_flock, sys_flock), // 143 -+//ZZ GENX_(__NR_msync, sys_msync), // 144 -+//ZZ -+//ZZ GENX_(__NR_getsid, sys_getsid), // 147 -+//ZZ GENX_(__NR_fdatasync, sys_fdatasync), // 148 -+//ZZ LINXY(__NR__sysctl, sys_sysctl), // 149 -+//ZZ -+//ZZ GENX_(__NR_mlock, sys_mlock), // 150 -+//ZZ GENX_(__NR_munlock, sys_munlock), // 151 -+//ZZ GENX_(__NR_mlockall, sys_mlockall), // 152 -+//ZZ LINX_(__NR_munlockall, sys_munlockall), // 153 -+//ZZ LINXY(__NR_sched_setparam, sys_sched_setparam), // 154 -+//ZZ -+//ZZ LINXY(__NR_sched_getparam, sys_sched_getparam), // 155 -+//ZZ LINX_(__NR_sched_setscheduler, sys_sched_setscheduler), // 156 -+//ZZ LINX_(__NR_sched_getscheduler, sys_sched_getscheduler), // 157 -+//ZZ LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 159 -+//ZZ -+//ZZ LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 160 -+//ZZ //zz //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 */* -+//ZZ LINX_(__NR_setresuid, sys_setresuid16), // 164 -+//ZZ -+//ZZ LINXY(__NR_getresuid, sys_getresuid16), // 165 -+//ZZ // PLAXY(__NR_vm86, sys_vm86), // 166 x86/Linux-only -+//ZZ // GENX_(__NR_query_module, sys_ni_syscall), // 167 -+//ZZ GENXY(__NR_poll, sys_poll), // 168 -+//ZZ //zz // (__NR_nfsservctl, sys_nfsservctl), // 169 */Linux -+//ZZ //zz -+//ZZ LINX_(__NR_setresgid, sys_setresgid16), // 170 -+//ZZ LINXY(__NR_getresgid, sys_getresgid16), // 171 -+//ZZ LINXY(__NR_prctl, sys_prctl), // 172 -+//ZZ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 174 -+//ZZ -+//ZZ LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 176 -+//ZZ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait),// 177 -+//ZZ -+//ZZ GENXY(__NR_pread64, sys_pread64), // 180 -+//ZZ LINX_(__NR_chown, sys_chown16), // 182 -+//ZZ -+//ZZ LINX_(__NR_capset, sys_capset), // 185 -+//ZZ LINXY(__NR_sendfile, sys_sendfile), // 187 -+//ZZ // GENXY(__NR_getpmsg, sys_getpmsg), // 188 -+//ZZ // GENX_(__NR_putpmsg, sys_putpmsg), // 189 -+//ZZ -+//ZZ // Nb: we treat vfork as fork -+//ZZ GENX_(__NR_vfork, sys_fork), // 190 -+//ZZ GENXY(__NR_ugetrlimit, sys_getrlimit), // 191 -+//ZZ GENX_(__NR_truncate64, sys_truncate64), // 193 -+//ZZ GENX_(__NR_ftruncate64, sys_ftruncate64), // 194 -+//ZZ -+//ZZ PLAXY(__NR_stat64, sys_stat64), // 195 -+//ZZ PLAXY(__NR_lstat64, sys_lstat64), // 196 -+//ZZ PLAXY(__NR_fstat64, sys_fstat64), // 197 -+//ZZ GENX_(__NR_lchown32, sys_lchown), // 198 -+//ZZ GENX_(__NR_getuid32, sys_getuid), // 199 -+//ZZ -+//ZZ GENX_(__NR_getgid32, sys_getgid), // 200 -+//ZZ GENX_(__NR_geteuid32, sys_geteuid), // 201 -+//ZZ GENX_(__NR_getegid32, sys_getegid), // 202 -+//ZZ GENX_(__NR_setreuid32, sys_setreuid), // 203 -+//ZZ GENX_(__NR_setregid32, sys_setregid), // 204 -+//ZZ -+//ZZ GENXY(__NR_getgroups32, sys_getgroups), // 205 -+//ZZ GENX_(__NR_setgroups32, sys_setgroups), // 206 -+//ZZ GENX_(__NR_fchown32, sys_fchown), // 207 -+//ZZ LINX_(__NR_setresuid32, sys_setresuid), // 208 -+//ZZ LINXY(__NR_getresuid32, sys_getresuid), // 209 -+//ZZ -+//ZZ LINX_(__NR_setresgid32, sys_setresgid), // 210 -+//ZZ LINXY(__NR_getresgid32, sys_getresgid), // 211 -+//ZZ GENX_(__NR_chown32, sys_chown), // 212 -+//ZZ GENX_(__NR_setuid32, sys_setuid), // 213 -+//ZZ GENX_(__NR_setgid32, sys_setgid), // 214 -+//ZZ -+//ZZ LINX_(__NR_setfsuid32, sys_setfsuid), // 215 -+//ZZ LINX_(__NR_setfsgid32, sys_setfsgid), // 216 -+//ZZ //zz // (__NR_pivot_root, sys_pivot_root), // 217 */Linux -+//ZZ GENXY(__NR_mincore, sys_mincore), // 218 -+//ZZ -+//ZZ LINXY(__NR_fcntl64, sys_fcntl64), // 221 -+//ZZ // GENX_(222, sys_ni_syscall), // 222 -+//ZZ // PLAXY(223, sys_syscall223), // 223 // sys_bproc? -+//ZZ -+//ZZ LINX_(__NR_setxattr, sys_setxattr), // 226 -+//ZZ LINX_(__NR_lsetxattr, sys_lsetxattr), // 227 -+//ZZ LINX_(__NR_fsetxattr, sys_fsetxattr), // 228 -+//ZZ -+//ZZ LINXY(__NR_fgetxattr, sys_fgetxattr), // 231 -+//ZZ LINXY(__NR_listxattr, sys_listxattr), // 232 -+//ZZ LINXY(__NR_llistxattr, sys_llistxattr), // 233 -+//ZZ LINXY(__NR_flistxattr, sys_flistxattr), // 234 -+//ZZ -+//ZZ LINX_(__NR_removexattr, sys_removexattr), // 235 -+//ZZ LINX_(__NR_lremovexattr, sys_lremovexattr), // 236 -+//ZZ LINX_(__NR_fremovexattr, sys_fremovexattr), // 237 -+//ZZ LINXY(__NR_tkill, sys_tkill), // 238 */Linux -+//ZZ LINXY(__NR_sendfile64, sys_sendfile64), // 239 -+//ZZ -+//ZZ LINXY(__NR_futex, sys_futex), // 240 -+//ZZ LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 242 -+//ZZ // PLAX_(__NR_set_thread_area, sys_set_thread_area), // 243 -+//ZZ // PLAX_(__NR_get_thread_area, sys_get_thread_area), // 244 -+//ZZ -+//ZZ LINXY(__NR_io_setup, sys_io_setup), // 245 -+//ZZ LINX_(__NR_io_destroy, sys_io_destroy), // 246 -+//ZZ LINXY(__NR_io_getevents, sys_io_getevents), // 247 -+//ZZ LINX_(__NR_io_submit, sys_io_submit), // 248 -+//ZZ LINXY(__NR_io_cancel, sys_io_cancel), // 249 -+//ZZ -+//ZZ // LINX_(__NR_fadvise64, sys_fadvise64), // 250 */(Linux?) -+//ZZ GENX_(251, sys_ni_syscall), // 251 -+//ZZ // GENXY(__NR_lookup_dcookie, sys_lookup_dcookie), // 253 -+//ZZ LINXY(__NR_epoll_create, sys_epoll_create), // 254 -+//ZZ -+//ZZ LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 255 -+//ZZ LINXY(__NR_epoll_wait, sys_epoll_wait), // 256 -+//ZZ //zz // (__NR_remap_file_pages, sys_remap_file_pages), // 257 */Linux -+//ZZ LINX_(__NR_set_tid_address, sys_set_tid_address), // 258 -+//ZZ LINXY(__NR_timer_create, sys_timer_create), // 259 -+//ZZ -+//ZZ LINXY(__NR_timer_settime, sys_timer_settime), // (timer_create+1) -+//ZZ LINXY(__NR_timer_gettime, sys_timer_gettime), // (timer_create+2) -+//ZZ LINX_(__NR_timer_getoverrun, sys_timer_getoverrun),//(timer_create+3) -+//ZZ LINX_(__NR_timer_delete, sys_timer_delete), // (timer_create+4) -+//ZZ LINX_(__NR_clock_settime, sys_clock_settime), // (timer_create+5) -+//ZZ -+//ZZ LINXY(__NR_clock_getres, sys_clock_getres), // (timer_create+7) -+//ZZ LINXY(__NR_clock_nanosleep, sys_clock_nanosleep),// (timer_create+8) */* -+//ZZ GENXY(__NR_statfs64, sys_statfs64), // 268 -+//ZZ GENXY(__NR_fstatfs64, sys_fstatfs64), // 269 -+//ZZ -+//ZZ GENX_(__NR_utimes, sys_utimes), // 271 -+//ZZ // LINX_(__NR_fadvise64_64, sys_fadvise64_64), // 272 */(Linux?) -+//ZZ GENX_(__NR_vserver, sys_ni_syscall), // 273 -+//ZZ LINX_(__NR_mbind, sys_mbind), // 274 ?/? -+//ZZ -+//ZZ LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 275 ?/? -+//ZZ LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 276 ?/? -+//ZZ -+//ZZ LINXY(__NR_waitid, sys_waitid), // 280 -+//ZZ -+//ZZ LINX_(__NR_send, sys_send), -+//ZZ LINXY(__NR_recv, sys_recv), -+//ZZ LINXY(__NR_recvfrom, sys_recvfrom), // 292 -+//ZZ LINX_(__NR_semget, sys_semget), // 299 -+//ZZ LINXY(__NR_semctl, sys_semctl), // 300 -+//ZZ LINX_(__NR_msgget, sys_msgget), -+//ZZ LINX_(__NR_msgsnd, sys_msgsnd), -+//ZZ LINXY(__NR_msgrcv, sys_msgrcv), -+//ZZ LINXY(__NR_msgctl, sys_msgctl), // 304 -+//ZZ -+//ZZ LINX_(__NR_request_key, sys_request_key), // 287 -+//ZZ // LINX_(__NR_ioprio_set, sys_ioprio_set), // 289 -+//ZZ -+//ZZ // LINX_(__NR_ioprio_get, sys_ioprio_get), // 290 -+//ZZ LINX_(__NR_inotify_init, sys_inotify_init), // 291 -+//ZZ // LINX_(__NR_migrate_pages, sys_migrate_pages), // 294 -+//ZZ -+//ZZ LINX_(__NR_mknodat, sys_mknodat), // 297 -+//ZZ LINX_(__NR_fchownat, sys_fchownat), // 298 -+//ZZ LINX_(__NR_futimesat, sys_futimesat), // 326 on arm -+//ZZ -+//ZZ PLAXY(__NR_fstatat64, sys_fstatat64), // 300 -+//ZZ LINX_(__NR_renameat, sys_renameat), // 302 -+//ZZ LINX_(__NR_symlinkat, sys_symlinkat), // 304 -+//ZZ -+//ZZ LINX_(__NR_fchmodat, sys_fchmodat), // -+//ZZ LINX_(__NR_shmget, sys_shmget), //307 -+//ZZ // LINX_(__NR_pselect6, sys_pselect6), // -+//ZZ -+//ZZ // LINX_(__NR_unshare, sys_unshare), // 310 -+//ZZ LINX_(__NR_set_robust_list, sys_set_robust_list), // 311 -+//ZZ LINXY(__NR_get_robust_list, sys_get_robust_list), // 312 -+//ZZ // LINX_(__NR_splice, sys_ni_syscall), // 313 -+//ZZ // LINX_(__NR_sync_file_range, sys_sync_file_range), // 314 -+//ZZ -+//ZZ // LINX_(__NR_tee, sys_ni_syscall), // 315 -+//ZZ // LINX_(__NR_vmsplice, sys_ni_syscall), // 316 -+//ZZ LINXY(__NR_move_pages, sys_move_pages), // 317 -+//ZZ // LINX_(__NR_getcpu, sys_ni_syscall), // 318 -+//ZZ -+//ZZ LINXY(__NR_signalfd, sys_signalfd), // 321 -+//ZZ LINXY(__NR_eventfd, sys_eventfd), // 323 -+//ZZ -+//ZZ -+//ZZ /////////////// -+//ZZ -+//ZZ // JRS 2010-Jan-03: I believe that all the numbers listed -+//ZZ // in comments in the table prior to this point (eg "// 326", -+//ZZ // etc) are bogus since it looks to me like they are copied -+//ZZ // verbatim from syswrap-x86-linux.c and they certainly do not -+//ZZ // correspond to what's in include/vki/vki-scnums-arm-linux.h. -+//ZZ // From here onwards, please ensure the numbers are correct. -+//ZZ -+//ZZ -+//ZZ LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 346 -+//ZZ -+//ZZ -+//ZZ LINXY(__NR_eventfd2, sys_eventfd2), // 356 -+//ZZ LINXY(__NR_epoll_create1, sys_epoll_create1), // 357 -+//ZZ LINXY(__NR_preadv, sys_preadv), // 361 -+//ZZ LINX_(__NR_pwritev, sys_pwritev), // 362 -+//ZZ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 363 -+//ZZ LINXY(__NR_perf_event_open, sys_perf_event_open), // 364 -+//ZZ -+//ZZ LINXY(__NR_accept4, sys_accept4), // 366 -+//ZZ -+//ZZ LINXY(__NR_name_to_handle_at, sys_name_to_handle_at),// 370 -+//ZZ LINXY(__NR_open_by_handle_at, sys_open_by_handle_at),// 371 -+//ZZ LINXY(__NR_clock_adjtime, sys_clock_adjtime) // 372 -+}; -+ -+ -+//ZZ /* These are not in the main table because there indexes are not small -+//ZZ integers, but rather values close to one million. So their -+//ZZ inclusion would force the main table to be huge (about 8 MB). */ -+//ZZ -+//ZZ static SyscallTableEntry ste___ARM_set_tls -+//ZZ = { WRAPPER_PRE_NAME(arm_linux,sys_set_tls), NULL }; -+//ZZ -+//ZZ static SyscallTableEntry ste___ARM_cacheflush -+//ZZ = { WRAPPER_PRE_NAME(arm_linux,sys_cacheflush), NULL }; -+ -+SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) -+{ -+ const UInt syscall_main_table_size -+ = sizeof(syscall_main_table) / sizeof(syscall_main_table[0]); -+ -+ /* Is it in the contiguous initial section of the table? */ -+ if (sysno < syscall_main_table_size) { -+ SyscallTableEntry* sys = &syscall_main_table[sysno]; -+ if (sys->before == NULL) -+ return NULL; /* no entry */ -+ else -+ return sys; -+ } -+ -+//ZZ /* Check if it's one of the out-of-line entries. */ -+//ZZ switch (sysno) { -+//ZZ case __NR_ARM_set_tls: return &ste___ARM_set_tls; -+//ZZ case __NR_ARM_cacheflush: return &ste___ARM_cacheflush; -+//ZZ default: break; -+//ZZ } -+ -+ /* Can't find a wrapper */ -+ return NULL; -+} -+ -+#endif // defined(VGP_arm64_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end syswrap-arm64-linux.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_syswrap/syswrap-generic.c -=================================================================== ---- coregrind/m_syswrap/syswrap-generic.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-generic.c (.../trunk) (revision 13981) -@@ -608,7 +608,7 @@ - } - - static --HChar *unix2name(struct vki_sockaddr_un *sa, UInt len, HChar *name) -+HChar *unix_to_name(struct vki_sockaddr_un *sa, UInt len, HChar *name) - { - if (sa == NULL || len == 0 || sa->sun_path[0] == '\0') { - VG_(sprintf)(name, ""); -@@ -620,22 +620,82 @@ - } - - static --HChar *inet2name(struct vki_sockaddr_in *sa, UInt len, HChar *name) -+HChar *inet_to_name(struct vki_sockaddr_in *sa, UInt len, HChar *name) - { - if (sa == NULL || len == 0) { - VG_(sprintf)(name, ""); -+ } else if (sa->sin_port == 0) { -+ VG_(sprintf)(name, ""); - } else { - UInt addr = VG_(ntohl)(sa->sin_addr.s_addr); -- if (addr == 0) { -- VG_(sprintf)(name, ""); -- } else { -- VG_(sprintf)(name, "%u.%u.%u.%u:%u", -- (addr>>24) & 0xFF, (addr>>16) & 0xFF, -- (addr>>8) & 0xFF, addr & 0xFF, -- VG_(ntohs)(sa->sin_port)); -+ VG_(sprintf)(name, "%u.%u.%u.%u:%u", -+ (addr>>24) & 0xFF, (addr>>16) & 0xFF, -+ (addr>>8) & 0xFF, addr & 0xFF, -+ VG_(ntohs)(sa->sin_port)); -+ } -+ -+ return name; -+} -+ -+static -+void inet6_format(HChar *s, const UChar ip[16]) -+{ -+ static const unsigned char V4mappedprefix[12] = {0,0,0,0,0,0,0,0,0,0,0xff,0xff}; -+ -+ if (!VG_(memcmp)(ip, V4mappedprefix, 12)) { -+ struct vki_in_addr *sin_addr = (struct vki_in_addr *)(ip + 12); -+ UInt addr = VG_(ntohl)(sin_addr->s_addr); -+ -+ VG_(sprintf)(s, "::ffff:%u.%u.%u.%u", -+ (addr>>24) & 0xFF, (addr>>16) & 0xFF, -+ (addr>>8) & 0xFF, addr & 0xFF); -+ } else { -+ Bool compressing = False; -+ Bool compressed = False; -+ Int len = 0; -+ Int i; -+ -+ for (i = 0; i < 16; i += 2) { -+ UInt word = ((UInt)ip[i] << 8) | (UInt)ip[i+1]; -+ if (word == 0 && !compressed) { -+ compressing = True; -+ } else { -+ if (compressing) { -+ compressing = False; -+ compressed = True; -+ s[len++] = ':'; -+ } -+ if (i > 0) { -+ s[len++] = ':'; -+ } -+ len += VG_(sprintf)(s + len, "%x", word); -+ } - } -+ -+ if (compressing) { -+ s[len++] = ':'; -+ s[len++] = ':'; -+ } -+ -+ s[len++] = 0; - } - -+ return; -+} -+ -+static -+HChar *inet6_to_name(struct vki_sockaddr_in6 *sa, UInt len, HChar *name) -+{ -+ if (sa == NULL || len == 0) { -+ VG_(sprintf)(name, ""); -+ } else if (sa->sin6_port == 0) { -+ VG_(sprintf)(name, ""); -+ } else { -+ char addr[128]; -+ inet6_format(addr, (void *)&(sa->sin6_addr)); -+ VG_(sprintf)(name, "[%s]:%u", addr, VG_(ntohs)(sa->sin6_port)); -+ } -+ - return name; - } - -@@ -648,6 +708,7 @@ - union u { - struct vki_sockaddr a; - struct vki_sockaddr_in in; -+ struct vki_sockaddr_in6 in6; - struct vki_sockaddr_un un; - } laddr; - Int llen; -@@ -665,18 +726,34 @@ - - if (VG_(getpeername)(fd, (struct vki_sockaddr *)&paddr, &plen) != -1) { - VG_(message)(Vg_UserMsg, "Open AF_INET socket %d: %s <-> %s\n", fd, -- inet2name(&(laddr.in), llen, lname), -- inet2name(&paddr, plen, pname)); -+ inet_to_name(&(laddr.in), llen, lname), -+ inet_to_name(&paddr, plen, pname)); - } else { - VG_(message)(Vg_UserMsg, "Open AF_INET socket %d: %s <-> unbound\n", -- fd, inet2name(&(laddr.in), llen, lname)); -+ fd, inet_to_name(&(laddr.in), llen, lname)); - } - return; - } -+ case VKI_AF_INET6: { -+ static char lname[128]; -+ static char pname[128]; -+ struct vki_sockaddr_in6 paddr; -+ Int plen = sizeof(struct vki_sockaddr_in6); -+ -+ if (VG_(getpeername)(fd, (struct vki_sockaddr *)&paddr, &plen) != -1) { -+ VG_(message)(Vg_UserMsg, "Open AF_INET6 socket %d: %s <-> %s\n", fd, -+ inet6_to_name(&(laddr.in6), llen, lname), -+ inet6_to_name(&paddr, plen, pname)); -+ } else { -+ VG_(message)(Vg_UserMsg, "Open AF_INET6 socket %d: %s <-> unbound\n", -+ fd, inet6_to_name(&(laddr.in6), llen, lname)); -+ } -+ return; -+ } - case VKI_AF_UNIX: { - static char lname[256]; - VG_(message)(Vg_UserMsg, "Open AF_UNIX socket %d: %s\n", fd, -- unix2name(&(laddr.un), llen, lname)); -+ unix_to_name(&(laddr.un), llen, lname)); - return; - } - default: -@@ -874,13 +951,15 @@ - if ( recv ) - foreach_func ( tid, False, fieldName, (Addr)&msg->msg_flags, sizeof( msg->msg_flags ) ); - -- if ( msg->msg_name ) { -+ if ( ML_(safe_to_deref)(&msg->msg_name, sizeof (void *)) -+ && msg->msg_name ) { - VG_(sprintf) ( fieldName, "(%s.msg_name)", name ); - foreach_func ( tid, False, fieldName, - (Addr)msg->msg_name, msg->msg_namelen ); - } - -- if ( msg->msg_iov ) { -+ if ( ML_(safe_to_deref)(&msg->msg_iov, sizeof (void *)) -+ && msg->msg_iov ) { - struct vki_iovec *iov = msg->msg_iov; - UInt i; - -@@ -898,7 +977,8 @@ - } - } - -- if ( msg->msg_control ) -+ if ( ML_(safe_to_deref) (&msg->msg_control, sizeof (void *)) -+ && msg->msg_control ) - { - VG_(sprintf) ( fieldName, "(%s.msg_control)", name ); - foreach_func ( tid, False, fieldName, -@@ -3785,7 +3865,7 @@ - (Addr)(&ufds[i].fd), sizeof(ufds[i].fd) ); - PRE_MEM_READ( "poll(ufds.events)", - (Addr)(&ufds[i].events), sizeof(ufds[i].events) ); -- PRE_MEM_WRITE( "poll(ufds.reventss)", -+ PRE_MEM_WRITE( "poll(ufds.revents)", - (Addr)(&ufds[i].revents), sizeof(ufds[i].revents) ); - } - } -Index: coregrind/m_syswrap/syswrap-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-linux.c (.../trunk) (revision 13981) -@@ -209,6 +209,8 @@ - /* This releases the run lock */ - VG_(exit_thread)(tid); - vg_assert(tst->status == VgTs_Zombie); -+ vg_assert(sizeof(tst->status) == 4); -+ vg_assert(sizeof(tst->os_state.exitcode) == sizeof(Word)); - - INNER_REQUEST (VALGRIND_STACK_DEREGISTER (registered_vgstack_id)); - -@@ -264,6 +266,16 @@ - : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) - : "r0", "r7" - ); -+#elif defined(VGP_arm64_linux) -+ asm volatile ( -+ "str %w1, %0\n" /* set tst->status = VgTs_Empty (32-bit store) */ -+ "mov x8, %2\n" /* set %r7 = __NR_exit */ -+ "ldr x0, %3\n" /* set %r0 = tst->os_state.exitcode */ -+ "svc 0x00000000\n" /* exit(tst->os_state.exitcode) */ -+ : "=m" (tst->status) -+ : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) -+ : "r0", "r7" -+ ); - #elif defined(VGP_s390x_linux) - asm volatile ( - "st %1, %0\n" /* set tst->status = VgTs_Empty */ -@@ -276,7 +288,7 @@ - #elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) - asm volatile ( - "sw %1, %0\n\t" /* set tst->status = VgTs_Empty */ -- "li $2, %2\n\t" /* set v0 = __NR_exit */ -+ "li $2, %2\n\t" /* set v0 = __NR_exit */ - "lw $4, %3\n\t" /* set a0 = tst->os_state.exitcode */ - "syscall\n\t" /* exit(tst->os_state.exitcode) */ - "nop" -@@ -428,7 +440,7 @@ - #if defined(VGP_x86_linux) \ - || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - res = VG_(do_syscall5)( __NR_clone, flags, - (UWord)NULL, (UWord)parent_tidptr, - (UWord)NULL, (UWord)child_tidptr ); -@@ -802,6 +814,40 @@ - POST_MEM_WRITE( ARG1, sizeof(struct vki_timex) ); - } - -+PRE(sys_clock_adjtime) -+{ -+ struct vki_timex *tx = (struct vki_timex *)ARG2; -+ PRINT("sys_clock_adjtime ( %ld, %#lx )", ARG1,ARG2); -+ PRE_REG_READ2(long, "clock_adjtime", vki_clockid_t, id, struct timex *, buf); -+ PRE_MEM_READ( "clock_adjtime(timex->modes)", ARG2, sizeof(tx->modes)); -+ -+#define ADJX(bits,field) \ -+ if (tx->modes & (bits)) \ -+ PRE_MEM_READ( "clock_adjtime(timex->"#field")", \ -+ (Addr)&tx->field, sizeof(tx->field)) -+ -+ if (tx->modes & VKI_ADJ_ADJTIME) { -+ if (!(tx->modes & VKI_ADJ_OFFSET_READONLY)) -+ PRE_MEM_READ( "clock_adjtime(timex->offset)", (Addr)&tx->offset, sizeof(tx->offset)); -+ } else { -+ ADJX(VKI_ADJ_OFFSET, offset); -+ ADJX(VKI_ADJ_FREQUENCY, freq); -+ ADJX(VKI_ADJ_MAXERROR, maxerror); -+ ADJX(VKI_ADJ_ESTERROR, esterror); -+ ADJX(VKI_ADJ_STATUS, status); -+ ADJX(VKI_ADJ_TIMECONST|VKI_ADJ_TAI, constant); -+ ADJX(VKI_ADJ_TICK, tick); -+ } -+#undef ADJX -+ -+ PRE_MEM_WRITE( "adjtimex(timex)", ARG2, sizeof(struct vki_timex)); -+} -+ -+POST(sys_clock_adjtime) -+{ -+ POST_MEM_WRITE( ARG2, sizeof(struct vki_timex) ); -+} -+ - PRE(sys_ioperm) - { - PRINT("sys_ioperm ( %ld, %ld, %ld )", ARG1, ARG2, ARG3 ); -@@ -1223,7 +1269,7 @@ - (Addr)(&ufds[i].fd), sizeof(ufds[i].fd) ); - PRE_MEM_READ( "ppoll(ufds.events)", - (Addr)(&ufds[i].events), sizeof(ufds[i].events) ); -- PRE_MEM_WRITE( "ppoll(ufd.reventss)", -+ PRE_MEM_WRITE( "ppoll(ufd.revents)", - (Addr)(&ufds[i].revents), sizeof(ufds[i].revents) ); - } - -@@ -2129,8 +2175,19 @@ - PRE_REG_READ3(long, "timer_create", - vki_clockid_t, clockid, struct sigevent *, evp, - vki_timer_t *, timerid); -- if (ARG2 != 0) -- PRE_MEM_READ( "timer_create(evp)", ARG2, sizeof(struct vki_sigevent) ); -+ if (ARG2 != 0) { -+ struct vki_sigevent *evp = (struct vki_sigevent *) ARG2; -+ PRE_MEM_READ( "timer_create(evp.sigev_value)", (Addr)&evp->sigev_value, -+ sizeof(vki_sigval_t) ); -+ PRE_MEM_READ( "timer_create(evp.sigev_signo)", (Addr)&evp->sigev_signo, -+ sizeof(int) ); -+ PRE_MEM_READ( "timer_create(evp.sigev_notify)", (Addr)&evp->sigev_notify, -+ sizeof(int) ); -+ if (ML_(safe_to_deref)(&evp->sigev_notify, sizeof(int)) -+ && (evp->sigev_notify & VKI_SIGEV_THREAD_ID) != 0) -+ PRE_MEM_READ( "timer_create(evp.sigev_notify_thread_id)", -+ (Addr)&evp->vki_sigev_notify_thread_id, sizeof(int) ); -+ } - PRE_MEM_WRITE( "timer_create(timerid)", ARG3, sizeof(vki_timer_t) ); - } - POST(sys_timer_create) -@@ -5482,9 +5539,10 @@ - /* SCSI no operand */ - case VKI_SCSI_IOCTL_DOORLOCK: - case VKI_SCSI_IOCTL_DOORUNLOCK: -- -+ - /* KVM ioctls that dont check for a numeric value as parameter */ - case VKI_KVM_S390_ENABLE_SIE: -+ case VKI_KVM_CREATE_IRQCHIP: - case VKI_KVM_S390_INITIAL_RESET: - - /* vhost without parameter */ -@@ -6764,7 +6822,8 @@ - /* These just take an int by value */ - break; - --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* ashmem */ - case VKI_ASHMEM_GET_SIZE: - case VKI_ASHMEM_SET_SIZE: -@@ -6842,7 +6901,7 @@ - ir->num_rsp * sizeof(struct vki_inquiry_info)); - } - break; -- -+ - /* KVM ioctls that check for a numeric value as parameter */ - case VKI_KVM_GET_API_VERSION: - case VKI_KVM_CREATE_VM: -@@ -6957,7 +7016,8 @@ - - /* --- BEGIN special IOCTL handlers for specific Android hardware --- */ - --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - - # if defined(ANDROID_HARDWARE_nexus_s) - -@@ -7875,7 +7935,8 @@ - } - break; - --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* ashmem */ - case VKI_ASHMEM_GET_SIZE: - case VKI_ASHMEM_SET_SIZE: -@@ -7933,6 +7994,7 @@ - case VKI_KVM_GET_VCPU_MMAP_SIZE: - case VKI_KVM_S390_ENABLE_SIE: - case VKI_KVM_CREATE_VCPU: -+ case VKI_KVM_CREATE_IRQCHIP: - case VKI_KVM_RUN: - case VKI_KVM_S390_INITIAL_RESET: - break; -Index: coregrind/m_syswrap/syswrap-main.c -=================================================================== ---- coregrind/m_syswrap/syswrap-main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-main.c (.../trunk) (revision 13981) -@@ -70,6 +70,7 @@ - arm r7 r0 r1 r2 r3 r4 r5 n/a n/a r0 (== ARG1) - mips32 v0 a0 a1 a2 a3 stack stack n/a n/a v0 (== NUM) - mips64 v0 a0 a1 a2 a3 a4 a5 a6 a7 v0 (== NUM) -+ arm64 x8 x0 x1 x2 x3 x4 x5 n/a n/a x0 ?? (== ARG1??) - - On s390x the svc instruction is used for system calls. The system call - number is encoded in the instruction (8 bit immediate field). Since Linux -@@ -464,10 +465,30 @@ - canonical->arg7 = 0; - canonical->arg8 = 0; - -+#elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ canonical->sysno = gst->guest_X8; -+ canonical->arg1 = gst->guest_X0; -+ canonical->arg2 = gst->guest_X1; -+ canonical->arg3 = gst->guest_X2; -+ canonical->arg4 = gst->guest_X3; -+ canonical->arg5 = gst->guest_X4; -+ canonical->arg6 = gst->guest_X5; -+ canonical->arg7 = 0; -+ canonical->arg8 = 0; -+ - #elif defined(VGP_mips32_linux) - VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla; - canonical->sysno = gst->guest_r2; // v0 -- if (canonical->sysno != __NR_syscall) { -+ if (canonical->sysno == __NR_exit) { -+ canonical->arg1 = gst->guest_r4; // a0 -+ canonical->arg2 = 0; -+ canonical->arg3 = 0; -+ canonical->arg4 = 0; -+ canonical->arg5 = 0; -+ canonical->arg6 = 0; -+ canonical->arg8 = 0; -+ } else if (canonical->sysno != __NR_syscall) { - canonical->arg1 = gst->guest_r4; // a0 - canonical->arg2 = gst->guest_r5; // a1 - canonical->arg3 = gst->guest_r6; // a2 -@@ -686,6 +707,16 @@ - gst->guest_R4 = canonical->arg5; - gst->guest_R5 = canonical->arg6; - -+#elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ gst->guest_X8 = canonical->sysno; -+ gst->guest_X0 = canonical->arg1; -+ gst->guest_X1 = canonical->arg2; -+ gst->guest_X2 = canonical->arg3; -+ gst->guest_X3 = canonical->arg4; -+ gst->guest_X4 = canonical->arg5; -+ gst->guest_X5 = canonical->arg6; -+ - #elif defined(VGP_x86_darwin) - VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; - UWord *stack = (UWord *)gst->guest_ESP; -@@ -738,8 +769,8 @@ - gst->guest_r5 = canonical->arg2; - gst->guest_r6 = canonical->arg3; - gst->guest_r7 = canonical->arg4; -- *((UInt*) (gst->guest_r29 + 16)) = canonical->arg5; // 16(guest_GPR29/sp) -- *((UInt*) (gst->guest_r29 + 20)) = canonical->arg6; // 20(sp) -+ *((UInt*) (gst->guest_r29 + 16)) = canonical->arg5; // 16(guest_GPR29/sp) -+ *((UInt*) (gst->guest_r29 + 20)) = canonical->arg6; // 20(sp) - } else { - canonical->arg8 = 0; - gst->guest_r2 = __NR_syscall; -@@ -747,9 +778,9 @@ - gst->guest_r5 = canonical->arg1; - gst->guest_r6 = canonical->arg2; - gst->guest_r7 = canonical->arg3; -- *((UInt*) (gst->guest_r29 + 16)) = canonical->arg4; // 16(guest_GPR29/sp) -- *((UInt*) (gst->guest_r29 + 20)) = canonical->arg5; // 20(sp) -- *((UInt*) (gst->guest_r29 + 24)) = canonical->arg6; // 24(sp) -+ *((UInt*) (gst->guest_r29 + 16)) = canonical->arg4; // 16(guest_GPR29/sp) -+ *((UInt*) (gst->guest_r29 + 20)) = canonical->arg5; // 20(sp) -+ *((UInt*) (gst->guest_r29 + 24)) = canonical->arg6; // 24(sp) - } - - #elif defined(VGP_mips64_linux) -@@ -799,6 +830,11 @@ - canonical->sres = VG_(mk_SysRes_arm_linux)( gst->guest_R0 ); - canonical->what = SsComplete; - -+# elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ canonical->sres = VG_(mk_SysRes_arm64_linux)( gst->guest_X0 ); -+ canonical->what = SsComplete; -+ - # elif defined(VGP_mips32_linux) - VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla; - UInt v0 = gst->guest_r2; // v0 -@@ -972,6 +1008,20 @@ - VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, - OFFSET_arm_R0, sizeof(UWord) ); - -+# elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ vg_assert(canonical->what == SsComplete); -+ if (sr_isError(canonical->sres)) { -+ /* This isn't exactly right, in that really a Failure with res -+ not in the range 1 .. 4095 is unrepresentable in the -+ Linux-arm64 scheme. Oh well. */ -+ gst->guest_X0 = - (Long)sr_Err(canonical->sres); -+ } else { -+ gst->guest_X0 = sr_Res(canonical->sres); -+ } -+ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, -+ OFFSET_arm64_X0, sizeof(UWord) ); -+ - #elif defined(VGP_x86_darwin) - VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; - SysRes sres = canonical->sres; -@@ -1096,6 +1146,8 @@ - static - void getSyscallArgLayout ( /*OUT*/SyscallArgLayout* layout ) - { -+ VG_(bzero_inline)(layout, sizeof(*layout)); -+ - #if defined(VGP_x86_linux) - layout->o_sysno = OFFSET_x86_EAX; - layout->o_arg1 = OFFSET_x86_EBX; -@@ -1151,6 +1203,17 @@ - layout->uu_arg7 = -1; /* impossible value */ - layout->uu_arg8 = -1; /* impossible value */ - -+#elif defined(VGP_arm64_linux) -+ layout->o_sysno = OFFSET_arm64_X8; -+ layout->o_arg1 = OFFSET_arm64_X0; -+ layout->o_arg2 = OFFSET_arm64_X1; -+ layout->o_arg3 = OFFSET_arm64_X2; -+ layout->o_arg4 = OFFSET_arm64_X3; -+ layout->o_arg5 = OFFSET_arm64_X4; -+ layout->o_arg6 = OFFSET_arm64_X5; -+ layout->uu_arg7 = -1; /* impossible value */ -+ layout->uu_arg8 = -1; /* impossible value */ -+ - #elif defined(VGP_mips32_linux) - layout->o_sysno = OFFSET_mips32_r2; - layout->o_arg1 = OFFSET_mips32_r4; -@@ -1982,6 +2045,27 @@ - vg_assert(valid); - } - -+#elif defined(VGP_arm64_linux) -+ arch->vex.guest_PC -= 4; // sizeof(arm64 instr) -+ -+ /* Make sure our caller is actually sane, and we're really backing -+ back over a syscall. -+ -+ svc #0 == d4 00 00 01 -+ */ -+ { -+ UChar *p = (UChar *)arch->vex.guest_PC; -+ -+ if (p[0] != 0x01 || p[1] != 0x00 || p[2] != 0x00 || p[3] != 0xD4) -+ VG_(message)( -+ Vg_DebugMsg, -+ "?! restarting over syscall at %#llx %02x %02x %02x %02x\n", -+ arch->vex.guest_PC + 0ULL, p[0], p[1], p[2], p[3] -+ ); -+ -+ vg_assert(p[0] == 0x01 && p[1] == 0x00 && p[2] == 0x00 && p[3] == 0xD4); -+ } -+ - #elif defined(VGP_x86_darwin) - arch->vex.guest_EIP = arch->vex.guest_IP_AT_SYSCALL; - -Index: coregrind/m_syswrap/syswrap-mips32-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-mips32-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-mips32-linux.c (.../trunk) (revision 13981) -@@ -764,11 +764,11 @@ - /* Very much MIPS specific */ - PRE (sys_cacheflush) - { -- PRINT ("cacheflush (%lx, %#lx, %#lx)", ARG1, ARG2, ARG3); -- PRE_REG_READ3 (long, "cacheflush", void *, addrlow, void *, addrhigh, int, -- flags); -- VG_ (discard_translations) ((Addr64) ARG1, ((ULong) ARG2) - ((ULong) ARG1) + -- 1ULL /*paranoia */ , "PRE(sys_cacheflush)"); -+ PRINT ("cacheflush (%lx, %lx, %lx)", ARG1, ARG2, ARG3); -+ PRE_REG_READ3(long, "cacheflush", unsigned long, addr, -+ int, nbytes, int, cache); -+ VG_ (discard_translations) ((Addr64) ARG1, ((ULong) ARG2), -+ "PRE(sys_cacheflush)"); - SET_STATUS_Success (0); - } - -@@ -884,7 +884,7 @@ - GENX_ (__NR_getppid, sys_getppid), // 64 - GENX_ (__NR_getpgrp, sys_getpgrp), // 65 - GENX_ (__NR_setsid, sys_setsid), // 66 -- // PLAXY(__NR_sigaction, sys_sigaction), // 67 -+ LINXY (__NR_sigaction, sys_sigaction), // 67 - //.. // (__NR_sgetmask, sys_sgetmask), // 68 - //.. // (__NR_ssetmask, sys_ssetmask), // 69 - GENX_ (__NR_setreuid, sys_setreuid), // 70 -@@ -1121,7 +1121,7 @@ - LINXY (__NR_timerfd_gettime, sys_timerfd_gettime), // 322 - LINXY (__NR_timerfd_settime, sys_timerfd_settime), // 323 - LINXY (__NR_signalfd4, sys_signalfd4), // 324 -- LINX_ (__NR_eventfd2, sys_eventfd2), // 325 -+ LINXY (__NR_eventfd2, sys_eventfd2), // 325 - //.. - LINXY (__NR_pipe2, sys_pipe2), // 328 - LINXY (__NR_inotify_init1, sys_inotify_init1), // 329 -@@ -1128,6 +1128,8 @@ - //.. - LINXY (__NR_prlimit64, sys_prlimit64), // 338 - //.. -+ LINXY (__NR_clock_adjtime, sys_clock_adjtime), // 341 -+ //.. - LINXY (__NR_process_vm_readv, sys_process_vm_readv), // 345 - LINX_ (__NR_process_vm_writev, sys_process_vm_writev) // 346 - }; -Index: coregrind/m_syswrap/syswrap-mips64-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-mips64-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-mips64-linux.c (.../trunk) (revision 13981) -@@ -398,11 +398,11 @@ - /* Very much MIPS specific */ - PRE(sys_cacheflush) - { -- PRINT("cacheflush (%lx, %#lx, %#lx)", ARG1, ARG2, ARG3); -- PRE_REG_READ3(long, "cacheflush", void *, addrlow, void *, addrhigh, -- int, flags); -- VG_(discard_translations)((Addr64) ARG1, ((ULong) ARG2) - ((ULong) ARG1) + -- 1ULL /*paranoia */ , "PRE(sys_cacheflush)"); -+ PRINT("cacheflush (%lx, %lx, %lx)", ARG1, ARG2, ARG3); -+ PRE_REG_READ3(long, "cacheflush", unsigned long, addr, -+ int, nbytes, int, cache); -+ VG_ (discard_translations) ((Addr64) ARG1, ((ULong) ARG2), -+ "PRE(sys_cacheflush)"); - SET_STATUS_Success(0); - } - -@@ -921,6 +921,7 @@ - LINXY (__NR_timerfd_settime, sys_timerfd_settime), - LINXY (__NR_newfstatat, sys_newfstatat), - LINXY (__NR_prlimit64, sys_prlimit64), -+ LINXY (__NR_clock_adjtime, sys_clock_adjtime), - LINXY (__NR_process_vm_readv, sys_process_vm_readv), - LINX_ (__NR_process_vm_writev, sys_process_vm_writev) - }; -Index: coregrind/m_syswrap/syswrap-ppc32-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-ppc32-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-ppc32-linux.c (.../trunk) (revision 13981) -@@ -1240,7 +1240,7 @@ - LINX_(__NR_utimensat, sys_utimensat), // 304 - LINXY(__NR_signalfd, sys_signalfd), // 305 - LINXY(__NR_timerfd_create, sys_timerfd_create), // 306 -- LINX_(__NR_eventfd, sys_eventfd), // 307 -+ LINXY(__NR_eventfd, sys_eventfd), // 307 - LINX_(__NR_sync_file_range2, sys_sync_file_range2), // 308 - LINX_(__NR_fallocate, sys_fallocate), // 309 - // LINXY(__NR_subpage_prot, sys_ni_syscall), // 310 -@@ -1247,7 +1247,7 @@ - LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 311 - LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 312 - LINXY(__NR_signalfd4, sys_signalfd4), // 313 -- LINX_(__NR_eventfd2, sys_eventfd2), // 314 -+ LINXY(__NR_eventfd2, sys_eventfd2), // 314 - LINXY(__NR_epoll_create1, sys_epoll_create1), // 315 - LINXY(__NR_dup3, sys_dup3), // 316 - LINXY(__NR_pipe2, sys_pipe2), // 317 -@@ -1257,6 +1257,8 @@ - LINX_(__NR_pwritev, sys_pwritev), // 321 - LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 322 - -+ LINX_(__NR_clock_adjtime, sys_clock_adjtime), // 347 -+ - LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 351 - LINX_(__NR_process_vm_writev, sys_process_vm_writev) // 352 - }; -Index: coregrind/m_syswrap/syswrap-ppc64-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-ppc64-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-ppc64-linux.c (.../trunk) (revision 13981) -@@ -792,8 +792,8 @@ - GENX_(__NR_fchmod, sys_fchmod), // 94 - - GENX_(__NR_fchown, sys_fchown), // 95 --// _____(__NR_getpriority, sys_getpriority), // 96 --// _____(__NR_setpriority, sys_setpriority), // 97 -+ GENX_(__NR_getpriority, sys_getpriority), // 96 -+ GENX_(__NR_setpriority, sys_setpriority), // 97 - // _____(__NR_profil, sys_profil), // 98 - GENXY(__NR_statfs, sys_statfs), // 99 - -@@ -1033,7 +1033,7 @@ - LINX_(__NR_utimensat, sys_utimensat), // 304 - LINXY(__NR_signalfd, sys_signalfd), // 305 - LINXY(__NR_timerfd_create, sys_timerfd_create), // 306 -- LINX_(__NR_eventfd, sys_eventfd), // 307 -+ LINXY(__NR_eventfd, sys_eventfd), // 307 - LINX_(__NR_sync_file_range2, sys_sync_file_range2), // 308 - LINX_(__NR_fallocate, sys_fallocate), // 309 - // LINXY(__NR_subpage_prot, sys_ni_syscall), // 310 -@@ -1040,7 +1040,7 @@ - LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 311 - LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 312 - LINXY(__NR_signalfd4, sys_signalfd4), // 313 -- LINX_(__NR_eventfd2, sys_eventfd2), // 314 -+ LINXY(__NR_eventfd2, sys_eventfd2), // 314 - LINXY(__NR_epoll_create1, sys_epoll_create1), // 315 - LINXY(__NR_dup3, sys_dup3), // 316 - LINXY(__NR_pipe2, sys_pipe2), // 317 -@@ -1050,6 +1050,8 @@ - LINX_(__NR_pwritev, sys_pwritev), // 321 - LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 322 - -+ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 347 -+ - LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 351 - LINX_(__NR_process_vm_writev, sys_process_vm_writev) // 352 - }; -Index: coregrind/m_syswrap/syswrap-s390x-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-s390x-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-s390x-linux.c (.../trunk) (revision 13981) -@@ -846,7 +846,7 @@ - LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max), // 159 - - LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min), // 160 --// ?????(__NR_sched_rr_get_interval, ), // 161 -+ LINXY(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 162 - GENXY(__NR_nanosleep, sys_nanosleep), // 162 - GENX_(__NR_mremap, sys_mremap), // 163 - GENX_(164, sys_ni_syscall), /* unimplemented (by the kernel) */ // 164 -@@ -1020,13 +1020,13 @@ - LINX_(__NR_set_robust_list, sys_set_robust_list), // 304 - - LINXY(__NR_get_robust_list, sys_get_robust_list), // 305 --// ?????(__NR_splice, ), -+ LINX_(__NR_splice, sys_splice), // 306 - LINX_(__NR_sync_file_range, sys_sync_file_range), // 307 --// ?????(__NR_tee, ), --// ?????(__NR_vmsplice, ), -+ LINX_(__NR_tee, sys_tee), // 308 -+ LINXY(__NR_vmsplice, sys_vmsplice), // 309 - - GENX_(310, sys_ni_syscall), /* unimplemented (by the kernel) */ // 310 --// ?????(__NR_getcpu, ), -+ LINXY(__NR_getcpu, sys_getcpu), // 311 - LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 312 - GENX_(__NR_utimes, sys_utimes), // 313 - LINX_(__NR_fallocate, sys_fallocate), // 314 -@@ -1034,31 +1034,33 @@ - LINX_(__NR_utimensat, sys_utimensat), // 315 - LINXY(__NR_signalfd, sys_signalfd), // 316 - GENX_(317, sys_ni_syscall), /* unimplemented (by the kernel) */ // 317 -- LINX_(__NR_eventfd, sys_eventfd), // 318 -+ LINXY(__NR_eventfd, sys_eventfd), // 318 - LINXY(__NR_timerfd_create, sys_timerfd_create), // 319 - - LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 320 - LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 321 - LINXY(__NR_signalfd4, sys_signalfd4), // 322 -- LINX_(__NR_eventfd2, sys_eventfd2), // 323 -+ LINXY(__NR_eventfd2, sys_eventfd2), // 323 - LINXY(__NR_inotify_init1, sys_inotify_init1), // 324 - - LINXY(__NR_pipe2, sys_pipe2), // 325 -- // (__NR_dup3, ), -+ LINXY(__NR_dup3, sys_dup3), // 326 - LINXY(__NR_epoll_create1, sys_epoll_create1), // 327 - LINXY(__NR_preadv, sys_preadv), // 328 - LINX_(__NR_pwritev, sys_pwritev), // 329 - --// ?????(__NR_rt_tgsigqueueinfo, ), -+ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo), // 330 - LINXY(__NR_perf_event_open, sys_perf_event_open), // 331 --// ?????(__NR_fanotify_init, ), // 332 --// ?????(__NR_fanotify_mark, ), // 333 -+ LINXY(__NR_fanotify_init, sys_fanotify_init), // 332 -+ LINX_(__NR_fanotify_mark, sys_fanotify_mark), // 333 - LINXY(__NR_prlimit64, sys_prlimit64), // 334 --// ?????(__NR_name_to_handle_at, ), // 335 --// ?????(__NR_open_by_handle_at, ), // 336 --// ?????(__NR_clock_adjtime, ), // 337 -+ -+ LINXY(__NR_name_to_handle_at, sys_name_to_handle_at), // 335 -+ LINXY(__NR_open_by_handle_at, sys_open_by_handle_at), // 336 -+ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 337 - // ?????(__NR_syncfs, ), // 338 - // ?????(__NR_setns, ), // 339 -+ - LINXY(__NR_process_vm_readv, sys_process_vm_readv), // 340 - LINX_(__NR_process_vm_writev, sys_process_vm_writev), // 341 - }; -Index: coregrind/m_syswrap/syswrap-x86-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-x86-linux.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-x86-linux.c (.../trunk) (revision 13981) -@@ -1803,13 +1803,13 @@ - LINX_(__NR_utimensat, sys_utimensat), // 320 - LINXY(__NR_signalfd, sys_signalfd), // 321 - LINXY(__NR_timerfd_create, sys_timerfd_create), // 322 -- LINX_(__NR_eventfd, sys_eventfd), // 323 -+ LINXY(__NR_eventfd, sys_eventfd), // 323 - LINX_(__NR_fallocate, sys_fallocate), // 324 - - LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 325 - LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 326 - LINXY(__NR_signalfd4, sys_signalfd4), // 327 -- LINX_(__NR_eventfd2, sys_eventfd2), // 328 -+ LINXY(__NR_eventfd2, sys_eventfd2), // 328 - LINXY(__NR_epoll_create1, sys_epoll_create1), // 329 - - LINXY(__NR_dup3, sys_dup3), // 330 -@@ -1827,7 +1827,7 @@ - LINXY(__NR_prlimit64, sys_prlimit64), // 340 - LINXY(__NR_name_to_handle_at, sys_name_to_handle_at),// 341 - LINXY(__NR_open_by_handle_at, sys_open_by_handle_at),// 342 --// LINX_(__NR_clock_adjtime, sys_ni_syscall), // 343 -+ LINXY(__NR_clock_adjtime, sys_clock_adjtime), // 343 - // LINX_(__NR_syncfs, sys_ni_syscall), // 344 - - LINXY(__NR_sendmmsg, sys_sendmmsg), // 345 -Index: coregrind/m_syswrap/syswrap-xen.c -=================================================================== ---- coregrind/m_syswrap/syswrap-xen.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_syswrap/syswrap-xen.c (.../trunk) (revision 13981) -@@ -93,6 +93,26 @@ - PRINT("__HYPERVISOR_memory_op ( %ld, %lx )", ARG1, ARG2); - - switch (ARG1) { -+ -+ case VKI_XENMEM_maximum_ram_page: -+ /* No inputs */ -+ break; -+ -+ case VKI_XENMEM_maximum_gpfn: -+ PRE_MEM_READ("XENMEM_maximum_gpfn domid", -+ (Addr)ARG2, sizeof(vki_xen_domid_t)); -+ break; -+ -+ case VKI_XENMEM_machphys_mfn_list: { -+ struct vki_xen_machphys_mfn_list *arg = -+ (struct vki_xen_machphys_mfn_list *)ARG2; -+ PRE_MEM_READ("XENMEM_machphys_mfn_list max_extents", -+ (Addr)&arg->max_extents, sizeof(arg->max_extents)); -+ PRE_MEM_READ("XENMEM_machphys_mfn_list extent_start", -+ (Addr)&arg->extent_start, sizeof(arg->extent_start)); -+ break; -+ } -+ - case VKI_XENMEM_set_memory_map: { - struct vki_xen_foreign_memory_map *arg = - (struct vki_xen_foreign_memory_map *)ARG2; -@@ -152,6 +172,31 @@ - break; - } - -+ case VKI_XENMEM_add_to_physmap: { -+ struct vki_xen_add_to_physmap *arg = -+ (struct vki_xen_add_to_physmap *)ARG2; -+ PRE_MEM_READ("XENMEM_add_to_physmap domid", -+ (Addr)&arg->domid, sizeof(arg->domid)); -+ PRE_MEM_READ("XENMEM_add_to_physmap size", -+ (Addr)&arg->size, sizeof(arg->size)); -+ PRE_MEM_READ("XENMEM_add_to_physmap space", -+ (Addr)&arg->space, sizeof(arg->space)); -+ PRE_MEM_READ("XENMEM_add_to_physmap idx", -+ (Addr)&arg->idx, sizeof(arg->idx)); -+ PRE_MEM_READ("XENMEM_add_to_physmap gpfn", -+ (Addr)&arg->gpfn, sizeof(arg->gpfn)); -+ break; -+ }; -+ -+ case VKI_XENMEM_remove_from_physmap: { -+ struct vki_xen_remove_from_physmap *arg = -+ (struct vki_xen_remove_from_physmap *)ARG2; -+ PRE_MEM_READ("XENMEM_remove_from_physmap domid", -+ (Addr)&arg->domid, sizeof(arg->domid)); -+ PRE_MEM_READ("XENMEM_remove_from_physmap gpfn", -+ (Addr)&arg->gpfn, sizeof(arg->gpfn)); -+ } -+ - case VKI_XENMEM_get_sharing_freed_pages: - case VKI_XENMEM_get_sharing_shared_pages: - break; -@@ -388,6 +433,18 @@ - __PRE_XEN_SYSCTL_READ(_sysctl, _sysctl, _field) - - switch (sysctl->cmd) { -+ case VKI_XEN_SYSCTL_readconsole: -+ /* These are all unconditionally read */ -+ PRE_XEN_SYSCTL_READ(readconsole, clear); -+ PRE_XEN_SYSCTL_READ(readconsole, incremental); -+ PRE_XEN_SYSCTL_READ(readconsole, buffer); -+ PRE_XEN_SYSCTL_READ(readconsole, count); -+ -+ /* 'index' only read if 'incremental' is nonzero */ -+ if (sysctl->u.readconsole.incremental) -+ PRE_XEN_SYSCTL_READ(readconsole, index); -+ break; -+ - case VKI_XEN_SYSCTL_getdomaininfolist: - switch (sysctl->interface_version) - { -@@ -401,9 +458,28 @@ - PRE_XEN_SYSCTL_READ(getdomaininfolist_00000009, max_domains); - PRE_XEN_SYSCTL_READ(getdomaininfolist_00000009, buffer); - break; -+ case 0x0000000a: -+ PRE_XEN_SYSCTL_READ(getdomaininfolist_0000000a, first_domain); -+ PRE_XEN_SYSCTL_READ(getdomaininfolist_0000000a, max_domains); -+ PRE_XEN_SYSCTL_READ(getdomaininfolist_0000000a, buffer); -+ break; -+ default: -+ VG_(dmsg)("WARNING: XEN_SYSCTL_getdomaininfolist for sysctl version " -+ "%"PRIx32" not implemented yet\n", -+ sysctl->interface_version); -+ SET_STATUS_Failure(VKI_EINVAL); -+ return; - } - break; - -+ case VKI_XEN_SYSCTL_debug_keys: -+ PRE_XEN_SYSCTL_READ(debug_keys, keys); -+ PRE_XEN_SYSCTL_READ(debug_keys, nr_keys); -+ PRE_MEM_READ("XEN_SYSCTL_debug_keys *keys", -+ (Addr)sysctl->u.debug_keys.keys.p, -+ sysctl->u.debug_keys.nr_keys * sizeof(char)); -+ break; -+ - case VKI_XEN_SYSCTL_sched_id: - /* No inputs */ - break; -@@ -516,6 +592,7 @@ - case VKI_XEN_DOMCTL_gettscinfo: - case VKI_XEN_DOMCTL_getdomaininfo: - case VKI_XEN_DOMCTL_unpausedomain: -+ case VKI_XEN_DOMCTL_resumedomain: - /* No input fields. */ - break; - -@@ -525,6 +602,23 @@ - PRE_XEN_DOMCTL_READ(createdomain, flags); - break; - -+ case VKI_XEN_DOMCTL_gethvmcontext: -+ /* Xen unconditionally reads the 'buffer' pointer */ -+ __PRE_XEN_DOMCTL_READ(gethvmcontext, hvmcontext, buffer); -+ /* Xen only consumes 'size' if 'buffer' is non NULL. A NULL -+ * buffer is a request for the required size. */ -+ if ( domctl->u.hvmcontext.buffer.p ) -+ __PRE_XEN_DOMCTL_READ(gethvmcontext, hvmcontext, size); -+ break; -+ -+ case VKI_XEN_DOMCTL_sethvmcontext: -+ __PRE_XEN_DOMCTL_READ(sethvmcontext, hvmcontext, size); -+ __PRE_XEN_DOMCTL_READ(sethvmcontext, hvmcontext, buffer); -+ PRE_MEM_READ("XEN_DOMCTL_sethvmcontext *buffer", -+ (Addr)domctl->u.hvmcontext.buffer.p, -+ domctl->u.hvmcontext.size); -+ break; -+ - case VKI_XEN_DOMCTL_max_mem: - PRE_XEN_DOMCTL_READ(max_mem, max_memkb); - break; -@@ -544,6 +638,10 @@ - PRE_XEN_DOMCTL_READ(hypercall_init, gmfn); - break; - -+ case VKI_XEN_DOMCTL_settimeoffset: -+ PRE_XEN_DOMCTL_READ(settimeoffset, time_offset_seconds); -+ break; -+ - case VKI_XEN_DOMCTL_getvcpuinfo: - PRE_XEN_DOMCTL_READ(getvcpuinfo, vcpu); - break; -@@ -608,6 +706,14 @@ - (Addr)&domctl->u.cpuid, sizeof(domctl->u.cpuid)); - break; - -+ case VKI_XEN_DOMCTL_getpageframeinfo3: -+ PRE_XEN_DOMCTL_READ(getpageframeinfo3, num); -+ PRE_XEN_DOMCTL_READ(getpageframeinfo3, array.p); -+ PRE_MEM_READ("XEN_DOMCTL_getpageframeinfo3 *u.getpageframeinfo3.array.p", -+ (Addr)domctl->u.getpageframeinfo3.array.p, -+ domctl->u.getpageframeinfo3.num * sizeof(vki_xen_pfn_t)); -+ break; -+ - case VKI_XEN_DOMCTL_getvcpuextstate: - __PRE_XEN_DOMCTL_READ(getvcpuextstate, vcpuextstate, vcpu); - __PRE_XEN_DOMCTL_READ(getvcpuextstate, vcpuextstate, xfeature_mask); -@@ -615,6 +721,58 @@ - __PRE_XEN_DOMCTL_READ(getvcpuextstate, vcpuextstate, buffer); - break; - -+ case VKI_XEN_DOMCTL_shadow_op: -+ PRE_XEN_DOMCTL_READ(shadow_op, op); -+ -+ switch(domctl->u.shadow_op.op) -+ { -+ case VKI_XEN_DOMCTL_SHADOW_OP_OFF: -+ /* No further inputs */ -+ break; -+ -+ case VKI_XEN_DOMCTL_SHADOW_OP_ENABLE: -+ PRE_XEN_DOMCTL_READ(shadow_op, mode); -+ switch(domctl->u.shadow_op.mode) -+ { -+ case XEN_DOMCTL_SHADOW_ENABLE_LOG_DIRTY: -+ goto domctl_shadow_op_enable_logdirty; -+ -+ -+ default: -+ bad_subop(tid, layout, arrghs, status, flags, -+ "__HYPERVISOR_domctl shadowop mode", -+ domctl->u.shadow_op.mode); -+ break; -+ } -+ -+ case VKI_XEN_DOMCTL_SHADOW_OP_ENABLE_LOGDIRTY: -+ domctl_shadow_op_enable_logdirty: -+ /* No further inputs */ -+ break; -+ -+ case VKI_XEN_DOMCTL_SHADOW_OP_CLEAN: -+ case VKI_XEN_DOMCTL_SHADOW_OP_PEEK: -+ PRE_XEN_DOMCTL_READ(shadow_op, dirty_bitmap); -+ PRE_XEN_DOMCTL_READ(shadow_op, pages); -+ break; -+ -+ default: -+ bad_subop(tid, layout, arrghs, status, flags, -+ "__HYPERVISOR_domctl shadow(10)", -+ domctl->u.shadow_op.op); -+ break; -+ } -+ break; -+ -+ case VKI_XEN_DOMCTL_set_max_evtchn: -+ PRE_XEN_DOMCTL_READ(set_max_evtchn, max_port); -+ break; -+ -+ case VKI_XEN_DOMCTL_cacheflush: -+ PRE_XEN_DOMCTL_READ(cacheflush, start_pfn); -+ PRE_XEN_DOMCTL_READ(cacheflush, nr_pfns); -+ break; -+ - default: - bad_subop(tid, layout, arrghs, status, flags, - "__HYPERVISOR_domctl", domctl->cmd); -@@ -636,7 +794,7 @@ - (Addr)&((_type*)arg)->_field, \ - sizeof(((_type*)arg)->_field)) - #define PRE_XEN_HVMOP_READ(_hvm_op, _field) \ -- __PRE_XEN_HVMOP_READ(_hvm_op, "xen_hvm_" # _hvm_op "_t", _field) -+ __PRE_XEN_HVMOP_READ(_hvm_op, vki_xen_hvm_ ## _hvm_op ## _t, _field) - - switch (op) { - case VKI_XEN_HVMOP_set_param: -@@ -650,6 +808,25 @@ - __PRE_XEN_HVMOP_READ(get_param, struct vki_xen_hvm_param, index); - break; - -+ case VKI_XEN_HVMOP_set_isa_irq_level: -+ PRE_XEN_HVMOP_READ(set_isa_irq_level, domid); -+ PRE_XEN_HVMOP_READ(set_isa_irq_level, isa_irq); -+ PRE_XEN_HVMOP_READ(set_isa_irq_level, level); -+ break; -+ -+ case VKI_XEN_HVMOP_set_pci_link_route: -+ PRE_XEN_HVMOP_READ(set_pci_link_route, domid); -+ PRE_XEN_HVMOP_READ(set_pci_link_route, link); -+ PRE_XEN_HVMOP_READ(set_pci_link_route, isa_irq); -+ break; -+ -+ case VKI_XEN_HVMOP_set_mem_type: -+ PRE_XEN_HVMOP_READ(set_mem_type, domid); -+ PRE_XEN_HVMOP_READ(set_mem_type, hvmmem_type); -+ PRE_XEN_HVMOP_READ(set_mem_type, nr); -+ PRE_XEN_HVMOP_READ(set_mem_type, first_pfn); -+ break; -+ - default: - bad_subop(tid, layout, arrghs, status, flags, - "__HYPERVISOR_hvm_op", op); -@@ -659,12 +836,70 @@ - #undef PRE_XEN_HVMOP_READ - } - -+PRE(tmem_op) -+{ -+ struct vki_xen_tmem_op *tmem = (struct vki_xen_tmem_op *)ARG1; -+ -+ PRINT("__HYPERVISOR_tmem_op ( %d )", tmem->cmd); -+ -+ /* Common part for xen_tmem_op: -+ * vki_uint32_t cmd; -+ */ -+ PRE_MEM_READ("__HYPERVISOR_tmem_op cmd", ARG1, sizeof(vki_uint32_t)); -+ -+ -+#define __PRE_XEN_TMEMOP_READ(_tmem, _union, _field) \ -+ PRE_MEM_READ("XEN_tmem_op_" #_tmem " u." #_union "." #_field, \ -+ (Addr)&tmem->u._union._field, \ -+ sizeof(tmem->u._union._field)) -+#define PRE_XEN_TMEMOP_READ(_tmem, _field) \ -+ __PRE_XEN_TMEMOP_READ(_tmem, _tmem, _field) -+ -+ switch(tmem->cmd) { -+ -+ case VKI_XEN_TMEM_control: -+ -+ /* Common part for control hypercall: -+ * vki_int32_t pool_id; -+ * vki_uint32_t subop; -+ */ -+ PRE_MEM_READ("__HYPERVISOR_tmem_op pool_id", -+ (Addr)&tmem->pool_id, sizeof(&tmem->pool_id)); -+ PRE_XEN_TMEMOP_READ(ctrl, subop); -+ -+ switch (tmem->u.ctrl.subop) { -+ -+ case VKI_XEN_TMEMC_save_begin: -+ PRE_XEN_TMEMOP_READ(ctrl, cli_id); -+ PRE_XEN_TMEMOP_READ(ctrl, arg1); -+ PRE_XEN_TMEMOP_READ(ctrl, buf); -+ break; -+ -+ default: -+ bad_subop(tid, layout, arrghs, status, flags, -+ "__HYPERVISOR_tmem_op_control", tmem->u.ctrl.subop); -+ } -+ -+ break; -+ -+ default: -+ bad_subop(tid, layout, arrghs, status, flags, -+ "__HYPERVISOR_tmem_op", ARG1); -+ } -+ -+#undef PRE_XEN_TMEMOP_READ -+#undef __PRE_XEN_TMEMOP_READ -+} -+ - POST(memory_op) - { - switch (ARG1) { -+ case VKI_XENMEM_maximum_ram_page: - case VKI_XENMEM_set_memory_map: - case VKI_XENMEM_decrease_reservation: - case VKI_XENMEM_claim_pages: -+ case VKI_XENMEM_maximum_gpfn: -+ case VKI_XENMEM_remove_from_physmap: - /* No outputs */ - break; - case VKI_XENMEM_increase_reservation: -@@ -677,6 +912,22 @@ - break; - } - -+ case VKI_XENMEM_machphys_mfn_list: { -+ struct vki_xen_machphys_mfn_list *arg = -+ (struct vki_xen_machphys_mfn_list *)ARG2; -+ POST_MEM_WRITE((Addr)&arg->nr_extents, sizeof(arg->nr_extents)); -+ POST_MEM_WRITE((Addr)arg->extent_start.p, -+ sizeof(vki_xen_pfn_t) * arg->nr_extents); -+ break; -+ } -+ -+ case VKI_XENMEM_add_to_physmap: { -+ struct vki_xen_add_to_physmap *arg = -+ (struct vki_xen_add_to_physmap *)ARG2; -+ if (arg->space == VKI_XENMAPSPACE_gmfn_range) -+ POST_MEM_WRITE(ARG2, sizeof(*arg)); -+ } -+ - case VKI_XENMEM_get_sharing_freed_pages: - case VKI_XENMEM_get_sharing_shared_pages: - /* No outputs */ -@@ -786,6 +1037,11 @@ - __POST_XEN_SYSCTL_WRITE(_sysctl, _sysctl, _field) - - switch (sysctl->cmd) { -+ case VKI_XEN_SYSCTL_readconsole: -+ POST_MEM_WRITE((Addr)sysctl->u.readconsole.buffer.p, -+ sysctl->u.readconsole.count * sizeof(char)); -+ break; -+ - case VKI_XEN_SYSCTL_getdomaininfolist: - switch (sysctl->interface_version) - { -@@ -801,6 +1057,12 @@ - sizeof(*sysctl->u.getdomaininfolist_00000009.buffer.p) - * sysctl->u.getdomaininfolist_00000009.num_domains); - break; -+ case 0x0000000a: -+ POST_XEN_SYSCTL_WRITE(getdomaininfolist_0000000a, num_domains); -+ POST_MEM_WRITE((Addr)sysctl->u.getdomaininfolist_0000000a.buffer.p, -+ sizeof(*sysctl->u.getdomaininfolist_0000000a.buffer.p) -+ * sysctl->u.getdomaininfolist_0000000a.num_domains); -+ break; - } - break; - -@@ -879,6 +1141,10 @@ - POST_MEM_WRITE((Addr)sysctl->u.numainfo.node_to_node_distance.p, - sizeof(uint32_t) * sysctl->u.numainfo.max_node_index); - break; -+ -+ /* No outputs */ -+ case VKI_XEN_SYSCTL_debug_keys: -+ break; - } - #undef POST_XEN_SYSCTL_WRITE - #undef __POST_XEN_SYSCTL_WRITE -@@ -915,6 +1181,10 @@ - case VKI_XEN_DOMCTL_setnodeaffinity: - case VKI_XEN_DOMCTL_set_cpuid: - case VKI_XEN_DOMCTL_unpausedomain: -+ case VKI_XEN_DOMCTL_sethvmcontext: -+ case VKI_XEN_DOMCTL_set_max_evtchn: -+ case VKI_XEN_DOMCTL_cacheflush: -+ case VKI_XEN_DOMCTL_resumedomain: - /* No output fields */ - break; - -@@ -941,6 +1211,16 @@ - POST_XEN_DOMCTL_WRITE(getvcpuinfo, cpu); - break; - -+ case VKI_XEN_DOMCTL_gethvmcontext: -+ /* Xen unconditionally writes size... */ -+ __POST_XEN_DOMCTL_WRITE(gethvmcontext, hvmcontext, size); -+ /* ...but only writes to the buffer if it was non NULL */ -+ if ( domctl->u.hvmcontext.buffer.p ) -+ POST_MEM_WRITE((Addr)domctl->u.hvmcontext.buffer.p, -+ sizeof(*domctl->u.hvmcontext.buffer.p) -+ * domctl->u.hvmcontext.size); -+ break; -+ - case VKI_XEN_DOMCTL_scheduler_op: - if ( domctl->u.scheduler_op.cmd == VKI_XEN_DOMCTL_SCHEDOP_getinfo ) { - switch(domctl->u.scheduler_op.sched_id) { -@@ -1027,6 +1307,12 @@ - __POST_XEN_DOMCTL_WRITE(getvcpucontext, vcpucontext, ctxt.p); - break; - -+ case VKI_XEN_DOMCTL_getpageframeinfo3: -+ POST_MEM_WRITE((Addr)domctl->u.getpageframeinfo3.array.p, -+ domctl->u.getpageframeinfo3.num * sizeof(vki_xen_pfn_t)); -+ break; -+ -+ - case VKI_XEN_DOMCTL_getvcpuextstate: - __POST_XEN_DOMCTL_WRITE(getvcpuextstate, vcpuextstate, xfeature_mask); - __POST_XEN_DOMCTL_WRITE(getvcpuextstate, vcpuextstate, size); -@@ -1034,6 +1320,27 @@ - domctl->u.vcpuextstate.size); - break; - -+ case VKI_XEN_DOMCTL_shadow_op: -+ switch(domctl->u.shadow_op.op) -+ { -+ case VKI_XEN_DOMCTL_SHADOW_OP_OFF: -+ /* No outputs */ -+ break; -+ -+ case VKI_XEN_DOMCTL_SHADOW_OP_CLEAN: -+ case VKI_XEN_DOMCTL_SHADOW_OP_PEEK: -+ POST_XEN_DOMCTL_WRITE(shadow_op, pages); -+ POST_XEN_DOMCTL_WRITE(shadow_op, stats.fault_count); -+ POST_XEN_DOMCTL_WRITE(shadow_op, stats.dirty_count); -+ if(domctl->u.shadow_op.dirty_bitmap.p) -+ POST_MEM_WRITE((Addr)domctl->u.shadow_op.dirty_bitmap.p, -+ domctl->u.shadow_op.pages * sizeof(vki_uint8_t)); -+ break; -+ -+ default: -+ break; -+ } -+ break; - } - #undef POST_XEN_DOMCTL_WRITE - #undef __POST_XEN_DOMCTL_WRITE -@@ -1048,10 +1355,13 @@ - POST_MEM_WRITE((Addr)&((_type*)arg)->_field, \ - sizeof(((_type*)arg)->_field)) - #define POST_XEN_HVMOP_WRITE(_hvm_op, _field) \ -- __PRE_XEN_HVMOP_READ(_hvm_op, "xen_hvm_" # _hvm_op "_t", _field) -+ __PRE_XEN_HVMOP_READ(_hvm_op, vki_xen_hvm_ ## _hvm_op ## _t, _field) - - switch (op) { - case VKI_XEN_HVMOP_set_param: -+ case VKI_XEN_HVMOP_set_isa_irq_level: -+ case VKI_XEN_HVMOP_set_pci_link_route: -+ case VKI_XEN_HVMOP_set_mem_type: - /* No output paramters */ - break; - -@@ -1063,6 +1373,24 @@ - #undef POST_XEN_HVMOP_WRITE - } - -+POST(tmem_op) -+{ -+ struct vki_xen_tmem_op *tmem = (struct vki_xen_tmem_op *)ARG1; -+ -+ switch(tmem->cmd) { -+ -+ case VKI_XEN_TMEM_control: -+ -+ switch(tmem->u.ctrl.subop) { -+ /* No outputs */ -+ case VKI_XEN_TMEMC_save_begin: -+ break; -+ } -+ -+ break; -+ } -+} -+ - typedef - struct { - SyscallTableEntry entry; -@@ -1123,7 +1451,7 @@ - HYPXY(__VKI_XEN_sysctl, sysctl, 1), // 35 - HYPXY(__VKI_XEN_domctl, domctl, 1), // 36 - // __VKI_XEN_kexec_op // 37 -- // __VKI_XEN_tmem_op // 38 -+ HYPXY(__VKI_XEN_tmem_op, tmem_op, 1), // 38 - }; - - static void bad_before ( ThreadId tid, -Index: coregrind/m_tooliface.c -=================================================================== ---- coregrind/m_tooliface.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_tooliface.c (.../trunk) (revision 13981) -@@ -92,6 +92,8 @@ - .client_requests = False, - .syscall_wrapper = False, - .sanity_checks = False, -+ .print_stats = False, -+ .info_location = False, - .var_info = False, - .malloc_replacement = False, - .xml_output = False, -@@ -294,6 +296,22 @@ - VG_(tdict).tool_expensive_sanity_check = expen; - } - -+void VG_(needs_print_stats) ( -+ void (*print_stats)(void) -+) -+{ -+ VG_(needs).print_stats = True; -+ VG_(tdict).tool_print_stats = print_stats; -+} -+ -+void VG_(needs_info_location) ( -+ void (*info_location)(Addr) -+) -+{ -+ VG_(needs).info_location = True; -+ VG_(tdict).tool_info_location = info_location; -+} -+ - void VG_(needs_malloc_replacement)( - void* (*malloc) ( ThreadId, SizeT ), - void* (*__builtin_new) ( ThreadId, SizeT ), -Index: coregrind/m_trampoline.S -=================================================================== ---- coregrind/m_trampoline.S (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_trampoline.S (.../trunk) (revision 13981) -@@ -519,10 +519,10 @@ - # undef UD2_1024 - # undef UD2_PAGE - --/*---------------- ppc32-linux ----------------*/ -+/*---------------- arm-linux ----------------*/ -+#else -+#if defined(VGP_arm_linux) - --#elif defined(VGP_arm_linux) -- - # define UD2_4 .word 0xFFFFFFFF - # define UD2_16 UD2_4 ; UD2_4 ; UD2_4 ; UD2_4 - # define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16 -@@ -680,6 +680,106 @@ - # undef UD2_1024 - # undef UD2_PAGE - -+/*---------------- arm64-linux ----------------*/ -+#else -+#if defined(VGP_arm64_linux) -+ -+# define UD2_4 .word 0xFFFFFFFF -+# define UD2_16 UD2_4 ; UD2_4 ; UD2_4 ; UD2_4 -+# define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16 -+# define UD2_256 UD2_64 ; UD2_64 ; UD2_64 ; UD2_64 -+# define UD2_1024 UD2_256 ; UD2_256 ; UD2_256 ; UD2_256 -+# define UD2_PAGE UD2_1024 ; UD2_1024 ; UD2_1024 ; UD2_1024 -+ -+ /* a leading page of unexecutable code */ -+ UD2_PAGE -+ -+.global VG_(trampoline_stuff_start) -+VG_(trampoline_stuff_start): -+ -+.global VG_(arm64_linux_SUBST_FOR_rt_sigreturn) -+.type VG_(arm64_linux_SUBST_FOR_rt_sigreturn),#function -+VG_(arm64_linux_SUBST_FOR_rt_sigreturn): -+ mov x8, # __NR_rt_sigreturn -+ svc #0 -+ .long 0xFFFFFFFF /*illegal insn*/ -+.size VG_(arm64_linux_SUBST_FOR_rt_sigreturn), \ -+ .-VG_(arm64_linux_SUBST_FOR_rt_sigreturn) -+ -+.global VG_(arm64_linux_REDIR_FOR_strlen) -+.type VG_(arm64_linux_REDIR_FOR_strlen),#function -+VG_(arm64_linux_REDIR_FOR_strlen): -+ mov x2, x0 -+ ldrb w0, [x0] -+ cbz w0, .L5 -+ mov x0, 0 -+.L4: -+ add x0, x0, 1 -+ ldrb w1, [x2,x0] -+ cbnz w1, .L4 -+ ret -+.L5: -+ mov x0, 0 -+ ret -+.size VG_(arm64_linux_REDIR_FOR_strlen), .-VG_(arm64_linux_REDIR_FOR_strlen) -+ -+.global VG_(arm64_linux_REDIR_FOR_index) -+.type VG_(arm64_linux_REDIR_FOR_index),#function -+VG_(arm64_linux_REDIR_FOR_index): -+ ldrb w2, [x0] -+ uxtb w1, w1 -+ cmp w2, w1 -+ beq .L11 -+.L13: -+ cbz w2, .L16 -+ ldrb w2, [x0,1]! -+ cmp w2, w1 -+ bne .L13 -+.L11: -+ ret -+.L16: -+ mov x0, 0 -+ ret -+.size VG_(arm64_linux_REDIR_FOR_index), .-VG_(arm64_linux_REDIR_FOR_index) -+ -+.global VG_(arm64_linux_REDIR_FOR_strcmp) -+.type VG_(arm64_linux_REDIR_FOR_strcmp),#function -+VG_(arm64_linux_REDIR_FOR_strcmp): -+ ldrb w2, [x0] -+ ldrb w3, [x1] -+ cmp w2, w3 -+ bcc .L22 -+.L21: -+ bhi .L25 -+ cbz w2, .L26 -+ ldrb w2, [x0,1]! -+ ldrb w3, [x1,1]! -+ cmp w2, w3 -+ bcs .L21 -+.L22: -+ mov x0, -1 -+ ret -+.L25: -+ mov x0, 1 -+ ret -+.L26: -+ mov x0, 0 -+ ret -+.size VG_(arm64_linux_REDIR_FOR_strcmp), .-VG_(arm64_linux_REDIR_FOR_strcmp) -+ -+.global VG_(trampoline_stuff_end) -+VG_(trampoline_stuff_end): -+ -+ /* and a trailing page of unexecutable code */ -+ UD2_PAGE -+ -+# undef UD2_4 -+# undef UD2_16 -+# undef UD2_64 -+# undef UD2_256 -+# undef UD2_1024 -+# undef UD2_PAGE -+ - /*---------------- x86-darwin ----------------*/ - #else - #if defined(VGP_x86_darwin) -@@ -1148,6 +1248,8 @@ - #endif - #endif - #endif -+#endif -+#endif - - #if defined(VGO_linux) - /* Let the linker know we don't need an executable stack */ -Index: coregrind/m_ume/elf.c -=================================================================== ---- coregrind/m_ume/elf.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_ume/elf.c (.../trunk) (revision 13981) -@@ -310,11 +310,6 @@ - void *entry; - ESZ(Addr) ebase = 0; - -- /* The difference between where the interpreter got mapped and -- where it asked to be mapped. Needed for computing the ppc64 ELF -- entry point and initial tocptr (R2) value. */ -- ESZ(Word) interp_offset = 0; -- - # if defined(HAVE_PIE) - ebase = info->exe_base; - # endif -@@ -500,8 +495,7 @@ - VG_(close)(interp->fd); - - entry = (void *)(advised - interp_addr + interp->e.e_entry); -- info->interp_base = (ESZ(Addr))advised; -- interp_offset = advised - interp_addr; -+ info->interp_offset = advised - interp_addr; - - VG_(free)(interp->p); - VG_(free)(interp); -@@ -518,12 +512,11 @@ - is the static chain value. */ - info->init_ip = ((ULong*)entry)[0]; - info->init_toc = ((ULong*)entry)[1]; -- info->init_ip += interp_offset; -- info->init_toc += interp_offset; -+ info->init_ip += info->interp_offset; -+ info->init_toc += info->interp_offset; - #else - info->init_ip = (Addr)entry; - info->init_toc = 0; /* meaningless on this platform */ -- (void) interp_offset; /* stop gcc complaining it is unused */ - #endif - VG_(free)(e->p); - VG_(free)(e); -Index: coregrind/m_ume/main.c -=================================================================== ---- coregrind/m_ume/main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_ume/main.c (.../trunk) (revision 13981) -@@ -199,7 +199,8 @@ - // will refuse to (eg. scripts lacking a "#!" prefix). - static Int do_exec_shell_followup(Int ret, const HChar* exe_name, ExeInfo* info) - { --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - const HChar* default_interp_name = "/system/bin/sh"; - # else - const HChar* default_interp_name = "/bin/sh"; -Index: coregrind/m_vki.c -=================================================================== ---- coregrind/m_vki.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_vki.c (.../trunk) (revision 13981) -@@ -42,7 +42,8 @@ - /* ppc32/64-linux determines page size at startup, hence m_vki is - the logical place to store that info. */ - --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -+ || defined(VGP_arm64_linux) - unsigned long VKI_PAGE_SHIFT = 12; - unsigned long VKI_PAGE_SIZE = 1UL << 12; - #endif -Index: coregrind/m_xarray.c -=================================================================== ---- coregrind/m_xarray.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/m_xarray.c (.../trunk) (revision 13981) -@@ -325,6 +325,27 @@ - xa->usedsizeE--; - } - -+void VG_(insertIndexXA)( XArray* xao, Word n, const void* elem ) -+{ -+ struct _XArray* xa = (struct _XArray*)xao; -+ vg_assert(xa); -+ vg_assert(n >= 0); -+ vg_assert(n <= xa->usedsizeE); -+ vg_assert(xa->usedsizeE >= 0 && xa->usedsizeE <= xa->totsizeE); -+ ensureSpaceXA( xa ); -+ vg_assert(xa->usedsizeE < xa->totsizeE); -+ vg_assert(xa->arr); -+ if (n < xa->usedsizeE) { -+ VG_(memmove) ( ((char*)xa->arr) + (n+1) * xa->elemSzB, -+ ((char*)xa->arr) + (n+0) * xa->elemSzB, -+ (xa->usedsizeE - n) * xa->elemSzB ); -+ } -+ VG_(memcpy)( ((UChar*)xa->arr) + n * xa->elemSzB, -+ elem, xa->elemSzB ); -+ xa->usedsizeE++; -+ xa->sorted = False; -+} -+ - void VG_(getContentsXA_UNSAFE)( XArray* xao, - /*OUT*/void** ctsP, - /*OUT*/Word* usedP ) -Index: coregrind/pub_core_addrinfo.h -=================================================================== ---- coregrind/pub_core_addrinfo.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/pub_core_addrinfo.h (.../trunk) (revision 13981) -@@ -0,0 +1,42 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Obtaining information about an address. pub_core_addrinfo.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2014-2014 Philippe Waroquiers -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __PUB_CORE_ADDRINFO_H -+#define __PUB_CORE_ADDRINFO_H -+ -+#include "pub_tool_addrinfo.h" -+ -+// No core-only exports; everything in this module is visible to both -+// the core and tools. -+ -+#endif // __PUB_CORE_ADDRINFO_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/pub_core_aspacemgr.h -=================================================================== ---- coregrind/pub_core_aspacemgr.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_aspacemgr.h (.../trunk) (revision 13981) -@@ -86,6 +86,12 @@ - // extern Bool VG_(am_is_valid_for_client) - // ( Addr start, SizeT len, UInt prot ); - -+/* Same as VG_(am_is_valid_for_client) but for valgrind : -+ test if memory is addressable by valgrind with at least -+ the protection 'prot'. */ -+extern Bool VG_(am_is_valid_for_valgrind) -+ ( Addr start, SizeT len, UInt prot ); -+ - /* Variant of VG_(am_is_valid_for_client) which allows free areas to - be consider part of the client's addressable space. It also - considers reservations to be allowable, since from the client's -@@ -229,27 +235,11 @@ - update the segment array accordingly. */ - extern SysRes VG_(am_mmap_anon_float_client) ( SizeT length, Int prot ); - --/* Similarly, acquire new address space for the client but with -- considerable restrictions on what can be done with it: (1) the -- actual protections may exceed those stated in 'prot', (2) the -- area's protections cannot be later changed using any form of -- mprotect, and (3) the area cannot be freed using any form of -- munmap. On Linux this behaves the same as -- VG_(am_mmap_anon_float_client). On AIX5 this *may* allocate memory -- by using sbrk, so as to make use of large pages on AIX. */ --extern SysRes VG_(am_sbrk_anon_float_client) ( SizeT length, Int prot ); -- -- - /* Map anonymously at an unconstrained address for V, and update the - segment array accordingly. This is fundamentally how V allocates - itself more address space when needed. */ - extern SysRes VG_(am_mmap_anon_float_valgrind)( SizeT cszB ); - --/* Same comments apply as per VG_(am_sbrk_anon_float_client). On -- Linux this behaves the same as VG_(am_mmap_anon_float_valgrind). */ --extern SysRes VG_(am_sbrk_anon_float_valgrind)( SizeT cszB ); -- -- - /* Map privately a file at an unconstrained address for V, and update the - segment array accordingly. This is used by V for transiently - mapping in object files to read their debug info. */ -@@ -345,7 +335,8 @@ - // protects such stacks. - - #if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - # define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages - # define VG_STACK_ACTIVE_SZB (4096 * 256) // 1Mb - #else -@@ -362,7 +353,7 @@ - VgStack; - - --/* Allocate and initialise a VgStack (anonymous client space). -+/* Allocate and initialise a VgStack (anonymous valgrind space). - Protect the stack active area and the guard areas appropriately. - Returns NULL on failure, else the address of the bottom of the - stack. On success, also sets *initial_sp to what the stack pointer -Index: coregrind/pub_core_basics.h -=================================================================== ---- coregrind/pub_core_basics.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_basics.h (.../trunk) (revision 13981) -@@ -58,6 +58,8 @@ - # include "libvex_guest_ppc64.h" - #elif defined(VGA_arm) - # include "libvex_guest_arm.h" -+#elif defined(VGA_arm64) -+# include "libvex_guest_arm64.h" - #elif defined(VGA_s390x) - # include "libvex_guest_s390x.h" - #elif defined(VGA_mips32) -@@ -109,6 +111,10 @@ - UInt r7; - } ARM; - struct { -+ ULong x29; /* FP */ -+ ULong x30; /* LR */ -+ } ARM64; -+ struct { - ULong r_fp; - ULong r_lr; - } S390X; -Index: coregrind/pub_core_coredump.h -=================================================================== ---- coregrind/pub_core_coredump.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_coredump.h (.../trunk) (revision 13981) -@@ -39,7 +39,7 @@ - //-------------------------------------------------------------------- - - extern void VG_(make_coredump) ( ThreadId tid, const vki_siginfo_t *si, -- UInt max_size ); -+ ULong max_size ); - - #endif // __PUB_CORE_COREDUMP_H - -Index: coregrind/pub_core_debuginfo.h -=================================================================== ---- coregrind/pub_core_debuginfo.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_debuginfo.h (.../trunk) (revision 13981) -@@ -112,6 +112,10 @@ - typedef - struct { Addr r15; Addr r14; Addr r13; Addr r12; Addr r11; Addr r7; } - D3UnwindRegs; -+#elif defined(VGA_arm64) -+typedef -+ struct { Addr pc; Addr sp; Addr x30; Addr x29; } /* PC, SP, LR, FP */ -+ D3UnwindRegs; - #elif defined(VGA_ppc32) || defined(VGA_ppc64) - typedef - UChar /* should be void, but gcc complains at use points */ -Index: coregrind/pub_core_gdbserver.h -=================================================================== ---- coregrind/pub_core_gdbserver.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_gdbserver.h (.../trunk) (revision 13981) -@@ -31,11 +31,12 @@ - #define __PUB_CORE_GDBSERVER_H - - #include "pub_tool_gdbserver.h" -+#include "pub_core_options.h" - #include "pub_core_threadstate.h" // VgSchedReturnCode - --/* Return the path prefix for the named pipes (FIFOs) used by vgdb/gdb -+/* Return the default path prefix for the named pipes (FIFOs) used by vgdb/gdb - to communicate with valgrind */ --HChar* VG_(vgdb_prefix_default)(void); -+HChar* VG_(vgdb_prefix_default)(void); - - // After a fork or after an exec, call the below to (possibly) terminate - // the previous gdbserver and then activate a new gdbserver -@@ -44,6 +45,13 @@ - // If VG_(clo_vgdb) == No, the below has no effect. - void VG_(gdbserver_prerun_action) (ThreadId tid); - -+// True if the initialisation of gdbserver was done, -+// i.e. VG_(gdbserver_prerun_action) was called. -+Bool VG_(gdbserver_init_done) (void); -+ -+// True if gdbserver should stop execution for the specified stop at reason -+Bool VG_(gdbserver_stop_at) (VgdbStopAt stopat); -+ - // True if there is some activity from vgdb - // If it returns True, then extern void VG_(gdbserver) can be called - // to handle this incoming vgdb request. -Index: coregrind/pub_core_libcassert.h -=================================================================== ---- coregrind/pub_core_libcassert.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_libcassert.h (.../trunk) (revision 13981) -@@ -66,13 +66,25 @@ - __attribute__ ((__noreturn__)) - extern void VG_(core_panic_at) ( const HChar* str, UnwindStartRegs* ); - -+/* Exits with status as client exit code. */ -+extern void VG_(client_exit)( Int status ); -+ - /* Called when some unhandleable client behaviour is detected. - Prints a msg and aborts. */ - extern void VG_(unimplemented) ( const HChar* msg ) - __attribute__((__noreturn__)); - --/* Show the state of all threads. Mostly for debugging V. */ --extern void VG_(show_sched_status) ( void ); -+/* Show the state of various threads related information, such -+ as the guest stacktrace for each thread. -+ Mostly for debugging V. -+ The following activates optional output: -+ host_stacktrace : shows the host stacktrace. -+ valgrind_stack_usage : shows how much of the valgrind stack was used. -+ exited_thread_slots : show information for thread slots that were used -+ but the thread has now exited. */ -+extern void VG_(show_sched_status) ( Bool host_stacktrace, -+ Bool valgrind_stack_usage, -+ Bool exited_threads); - - #endif // __PUB_CORE_LIBCASSERT_H - -Index: coregrind/pub_core_libcproc.h -=================================================================== ---- coregrind/pub_core_libcproc.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_libcproc.h (.../trunk) (revision 13981) -@@ -87,6 +87,8 @@ - // icache invalidation - extern void VG_(invalidate_icache) ( void *ptr, SizeT nbytes ); - -+// dcache flushing -+extern void VG_(flush_dcache) ( void *ptr, SizeT nbytes ); - - #endif // __PUB_CORE_LIBCPROC_H - -Index: coregrind/pub_core_machine.h -=================================================================== ---- coregrind/pub_core_machine.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_machine.h (.../trunk) (revision 13981) -@@ -66,6 +66,11 @@ - # define VG_ELF_MACHINE EM_ARM - # define VG_ELF_CLASS ELFCLASS32 - # undef VG_PLAT_USES_PPCTOC -+#elif defined(VGP_arm64_linux) -+# define VG_ELF_DATA2XXX ELFDATA2LSB -+# define VG_ELF_MACHINE EM_AARCH64 -+# define VG_ELF_CLASS ELFCLASS64 -+# undef VG_PLAT_USES_PPCTOC - #elif defined(VGO_darwin) - # undef VG_ELF_DATA2XXX - # undef VG_ELF_MACHINE -@@ -122,6 +127,10 @@ - # define VG_INSTR_PTR guest_R15T - # define VG_STACK_PTR guest_R13 - # define VG_FRAME_PTR guest_R11 -+#elif defined(VGA_arm64) -+# define VG_INSTR_PTR guest_PC -+# define VG_STACK_PTR guest_XSP -+# define VG_FRAME_PTR guest_X29 // FIXME: is this right? - #elif defined(VGA_s390x) - # define VG_INSTR_PTR guest_IA - # define VG_STACK_PTR guest_SP -Index: coregrind/pub_core_mallocfree.h -=================================================================== ---- coregrind/pub_core_mallocfree.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_mallocfree.h (.../trunk) (revision 13981) -@@ -77,7 +77,8 @@ - defined(VGP_s390x_linux) || \ - defined(VGP_mips64_linux) || \ - defined(VGP_x86_darwin) || \ -- defined(VGP_amd64_darwin) -+ defined(VGP_amd64_darwin) || \ -+ defined(VGP_arm64_linux) - # define VG_MIN_MALLOC_SZB 16 - #else - # error Unknown platform -@@ -126,6 +127,23 @@ - - extern void VG_(print_arena_cc_analysis) ( void ); - -+typedef -+ struct _AddrArenaInfo -+ AddrArenaInfo; -+ -+struct _AddrArenaInfo { -+ ArenaId aid; -+ const HChar* name; // arena name, !NULL if Addr a points in an arena. -+ SizeT block_szB; -+ PtrdiffT rwoffset; -+ Bool free; // True if this is in the arena free zone. -+}; -+/* If Addr a points in one of the allocation arenas, describes Addr a in *aai -+ otherwise sets *aai to 0/NULL/... -+ Note that no information is produced for addresses allocated with -+ VG_(arena_perm_malloc). */ -+extern void VG_(describe_arena_addr) ( Addr a, /*OUT*/AddrArenaInfo* aai ); -+ - #endif // __PUB_CORE_MALLOCFREE_H - - /*--------------------------------------------------------------------*/ -Index: coregrind/pub_core_options.h -=================================================================== ---- coregrind/pub_core_options.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_options.h (.../trunk) (revision 13981) -@@ -68,8 +68,30 @@ - extern VgVgdb VG_(clo_vgdb); - /* if > 0, checks every VG_(clo_vgdb_poll) BBS if vgdb wants to be served. */ - extern Int VG_(clo_vgdb_poll); -+ -+/* Specify when Valgrind gdbserver stops the execution and wait -+ for a GDB to connect. */ -+typedef -+ enum { // Stop : -+ VgdbStopAt_Startup, // just before the client starts to execute. -+ VgdbStopAt_Exit, // just before the client exits. -+ VgdbStopAt_ValgrindAbExit // on abnormal valgrind exit. -+ } -+ VgdbStopAt; -+// Build mask to check or set VgdbStop_At a membership -+#define VgdbStopAt2S(a) (1 << (a)) -+// VgdbStopAt a is member of the Set s ? -+#define VgdbStopAtiS(a,s) ((s) & VgdbStopAt2S(a)) -+// A set with all VgdbStopAt: -+#define VgdbStopAtallS \ -+ (VgdbStopAt2S(VgdbStopAt_Startup) \ -+ | VgdbStopAt2S(VgdbStopAt_Exit) \ -+ | VgdbStopAt2S(VgdbStopAt_ValgrindAbExit) -+extern UInt VG_(clo_vgdb_stop_at); // A set of VgdbStopAt reasons. -+ - /* prefix for the named pipes (FIFOs) used by vgdb/gdb to communicate with valgrind */ --extern const HChar* VG_(clo_vgdb_prefix); -+extern const HChar *VG_(clo_vgdb_prefix); -+ - /* if True, gdbserver in valgrind will expose a target description containing - shadow registers */ - extern Bool VG_(clo_vgdb_shadow_registers); -@@ -275,6 +297,10 @@ - /* Max number of sectors that will be used by the translation code cache. */ - extern UInt VG_(clo_num_transtab_sectors); - -+/* Only client requested fixed mapping can be done below -+ VG_(clo_aspacem_minAddr). */ -+extern Addr VG_(clo_aspacem_minAddr); -+ - /* Delay startup to allow GDB to be attached? Default: NO */ - extern Bool VG_(clo_wait_for_gdb); - -Index: coregrind/pub_core_rangemap.h -=================================================================== ---- coregrind/pub_core_rangemap.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/pub_core_rangemap.h (.../trunk) (revision 13981) -@@ -0,0 +1,51 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- A mapping where the keys exactly cover the address space. ---*/ -+/*--- pub_core_rangemap.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2014-2014 Mozilla Foundation -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+/* Contributed by Julian Seward */ -+ -+#ifndef __PUB_CORE_RANGEMAP_H -+#define __PUB_CORE_RANGEMAP_H -+ -+//-------------------------------------------------------------------- -+// PURPOSE: a mapping from the host machine word (UWord) ranges to -+// arbitrary other UWord values. The set of ranges exactly covers all -+// possible UWord values. -+// -------------------------------------------------------------------- -+ -+// No core-only exports; everything in this module is visible to both -+// the core and tools. -+ -+#include "pub_tool_rangemap.h" -+ -+#endif // __PUB_CORE_RANGEMAP_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end pub_core_rangemap.h ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/pub_core_syscall.h -=================================================================== ---- coregrind/pub_core_syscall.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_syscall.h (.../trunk) (revision 13981) -@@ -76,6 +76,7 @@ - extern SysRes VG_(mk_SysRes_ppc32_linux) ( UInt val, UInt cr0so ); - extern SysRes VG_(mk_SysRes_ppc64_linux) ( ULong val, ULong cr0so ); - extern SysRes VG_(mk_SysRes_arm_linux) ( Int val ); -+extern SysRes VG_(mk_SysRes_arm64_linux) ( Long val ); - extern SysRes VG_(mk_SysRes_x86_darwin) ( UChar scclass, Bool isErr, - UInt wHI, UInt wLO ); - extern SysRes VG_(mk_SysRes_amd64_darwin)( UChar scclass, Bool isErr, -Index: coregrind/pub_core_threadstate.h -=================================================================== ---- coregrind/pub_core_threadstate.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_threadstate.h (.../trunk) (revision 13981) -@@ -88,6 +88,8 @@ - typedef VexGuestPPC64State VexGuestArchState; - #elif defined(VGA_arm) - typedef VexGuestARMState VexGuestArchState; -+#elif defined(VGA_arm64) -+ typedef VexGuestARM64State VexGuestArchState; - #elif defined(VGA_s390x) - typedef VexGuestS390XState VexGuestArchState; - #elif defined(VGA_mips32) -Index: coregrind/pub_core_tooliface.h -=================================================================== ---- coregrind/pub_core_tooliface.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_tooliface.h (.../trunk) (revision 13981) -@@ -88,6 +88,8 @@ - Bool client_requests; - Bool syscall_wrapper; - Bool sanity_checks; -+ Bool print_stats; -+ Bool info_location; - Bool var_info; - Bool malloc_replacement; - Bool xml_output; -@@ -149,6 +151,12 @@ - Bool (*tool_cheap_sanity_check)(void); - Bool (*tool_expensive_sanity_check)(void); - -+ // VG_(needs).print_stats -+ void (*tool_print_stats)(void); -+ -+ // VG_(needs).info_location -+ void (*tool_info_location)(Addr a); -+ - // VG_(needs).malloc_replacement - void* (*tool_malloc) (ThreadId, SizeT); - void* (*tool___builtin_new) (ThreadId, SizeT); -Index: coregrind/pub_core_trampoline.h -=================================================================== ---- coregrind/pub_core_trampoline.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_trampoline.h (.../trunk) (revision 13981) -@@ -103,6 +103,13 @@ - extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int ); - #endif - -+#if defined(VGP_arm64_linux) -+extern Addr VG_(arm64_linux_SUBST_FOR_rt_sigreturn); -+extern ULong VG_(arm64_linux_REDIR_FOR_strlen)( void* ); -+extern void* VG_(arm64_linux_REDIR_FOR_index) ( void*, Long ); -+extern Long VG_(arm64_linux_REDIR_FOR_strcmp)( void*, void* ); -+#endif -+ - #if defined(VGP_x86_darwin) - extern Addr VG_(x86_darwin_SUBST_FOR_sigreturn); - extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* ); -Index: coregrind/pub_core_transtab_asm.h -=================================================================== ---- coregrind/pub_core_transtab_asm.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_transtab_asm.h (.../trunk) (revision 13981) -@@ -37,10 +37,10 @@ - On x86/amd64, the cache index is computed as - 'address[VG_TT_FAST_BITS-1 : 0]'. - -- On ppc32/ppc64, the bottom two bits of instruction addresses are -- zero, which means that function causes only 1/4 of the entries to -- ever be used. So instead the function is '(address >>u -- 2)[VG_TT_FAST_BITS-1 : 0]' on those targets. -+ On ppc32/ppc64/mips32/mips64/arm64, the bottom two bits of -+ instruction addresses are zero, which means that function causes -+ only 1/4 of the entries to ever be used. So instead the function -+ is '(address >>u 2)[VG_TT_FAST_BITS-1 : 0]' on those targets. - - On ARM we shift by 1, since Thumb insns can be of size 2, hence to - minimise collisions and maximise cache utilisation we need to take -@@ -63,7 +63,7 @@ - # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK) - - #elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_mips32) \ -- || defined(VGA_mips64) -+ || defined(VGA_mips64) || defined(VGA_arm64) - # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK) - - #else -Index: coregrind/pub_core_ume.h -=================================================================== ---- coregrind/pub_core_ume.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/pub_core_ume.h (.../trunk) (revision 13981) -@@ -52,10 +52,10 @@ - Addr exe_end; // INOUT: highest (allowed) address - - #if !defined(VGO_darwin) -- Addr phdr; // OUT: address phdr was mapped at -- Int phnum; // OUT: number of phdrs -- UInt stack_prot; // OUT: stack permissions -- Addr interp_base; // OUT: where interpreter (ld.so) was mapped -+ Addr phdr; // OUT: address phdr was mapped at -+ Int phnum; // OUT: number of phdrs -+ UInt stack_prot; // OUT: stack permissions -+ PtrdiffT interp_offset; // OUT: relocation offset for ld.so - #else - Addr stack_start; // OUT: address of start of stack segment (hot) - Addr stack_end; // OUT: address of end of stack segment (cold) -Index: coregrind/vg_preloaded.c -=================================================================== ---- coregrind/vg_preloaded.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/vg_preloaded.c (.../trunk) (revision 13981) -@@ -57,7 +57,8 @@ - void VG_NOTIFY_ON_LOAD(freeres)( void ) - { - # if !defined(__UCLIBC__) \ -- && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+ && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - extern void __libc_freeres(void); - __libc_freeres(); - # endif -Index: coregrind/vgdb-invoker-none.c -=================================================================== ---- coregrind/vgdb-invoker-none.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/vgdb-invoker-none.c (.../trunk) (revision 13981) -@@ -0,0 +1,56 @@ -+/*--------------------------------------------------------------------*/ -+/*--- Empty implementation of vgdb invoker subsystem. ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2011-2013 Philippe Waroquiers -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "vgdb.h" -+ -+#include -+#include -+ -+void invoker_restrictions_msg(void) -+{ -+ fprintf(stderr, -+ "Note: vgdb invoker not implemented on this platform.\n" -+ "For more info: read user manual section" -+ " 'Limitations of the Valgrind gdbserver'.\n"); -+} -+ -+void invoker_cleanup_restore_and_detach(void *v_pid) -+{ -+ DEBUG(1, "invoker_cleanup_restore_and_detach"); -+} -+ -+Bool invoker_invoke_gdbserver(pid_t pid) -+{ -+ DEBUG(2, "invoker_invoke_gdbserver not implemented\n"); -+ /* Returning True signals to not retry (too soon) to invoke. */ -+ return True; -+} -+ -+void invoker_valgrind_dying(void) -+{ -+} -Index: coregrind/vgdb-invoker-ptrace.c -=================================================================== ---- coregrind/vgdb-invoker-ptrace.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/vgdb-invoker-ptrace.c (.../trunk) (revision 13981) -@@ -0,0 +1,1102 @@ -+/*--------------------------------------------------------------------*/ -+/*--- Implementation of vgdb invoker subsystem via ptrace() calls. ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2011-2013 Philippe Waroquiers -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "config.h" -+ -+#include "vgdb.h" -+#include "pub_core_threadstate.h" -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef PTRACE_GETREGSET -+// TBD: better have a configure test instead ? -+#define HAVE_PTRACE_GETREGSET -+ -+// A bi-arch build using PTRACE_GET/SETREGSET needs -+// some conversion code for register structures. -+// So, better do not use PTRACE_GET/SETREGSET -+// Rather we use PTRACE_GETREGS or PTRACE_PEEKUSER. -+ -+// The only platform on which we must use PTRACE_GETREGSET is arm64. -+// The resulting vgdb cannot work in a bi-arch setup. -+// -1 means we will check that PTRACE_GETREGSET works. -+# if defined(VGA_arm64) -+#define USE_PTRACE_GETREGSET -+# endif -+#endif -+ -+#include -+#include -+ -+#include -+ -+#if VEX_HOST_WORDSIZE == 8 -+typedef Addr64 CORE_ADDR; -+#elif VEX_HOST_WORDSIZE == 4 -+typedef Addr32 CORE_ADDR; -+#else -+# error "unexpected wordsize" -+#endif -+ -+#if VEX_HOST_WORDSIZE == 8 -+typedef Addr64 PTRACE_XFER_TYPE; -+typedef void* PTRACE_ARG3_TYPE; -+#elif VEX_HOST_WORDSIZE == 4 -+typedef Addr32 PTRACE_XFER_TYPE; -+typedef void* PTRACE_ARG3_TYPE; -+#else -+# error "unexpected wordsize" -+#endif -+ -+// if > 0, pid for which registers have to be restored. -+// if == 0, means we have not yet called setregs (or have already -+// restored the registers). -+static int pid_of_save_regs = 0; -+/* True if we have continued pid_of_save_regs after PTRACE_ATTACH. */ -+static Bool pid_of_save_regs_continued = False; -+// When setregs has been called to change the registers of pid_of_save_regs, -+// vgdb cannot transmit the signals intercepted during ptrace. -+// So, we queue them, and will deliver them when detaching. -+// See function waitstopped for more info. -+static int signal_queue_sz = 0; -+static siginfo_t *signal_queue; -+ -+/* True when loss of connection indicating that the Valgrind -+ process is dying. */ -+static Bool dying = False; -+ -+/* ptrace_(read|write)_memory are modified extracts of linux-low.c -+ from gdb 6.6. Copyrighted FSF */ -+/* Copy LEN bytes from valgrind memory starting at MEMADDR -+ to vgdb memory starting at MYADDR. */ -+static -+int ptrace_read_memory (pid_t inferior_pid, CORE_ADDR memaddr, -+ void *myaddr, size_t len) -+{ -+ register int i; -+ /* Round starting address down to longword boundary. */ -+ register CORE_ADDR addr = memaddr & -(CORE_ADDR) sizeof (PTRACE_XFER_TYPE); -+ /* Round ending address up; get number of longwords that makes. */ -+ register int count -+ = (((memaddr + len) - addr) + sizeof (PTRACE_XFER_TYPE) - 1) -+ / sizeof (PTRACE_XFER_TYPE); -+ /* Allocate buffer of that many longwords. */ -+ register PTRACE_XFER_TYPE *buffer -+ = (PTRACE_XFER_TYPE *) alloca (count * sizeof (PTRACE_XFER_TYPE)); -+ -+ /* Read all the longwords */ -+ for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE)) { -+ errno = 0; -+ buffer[i] = ptrace (PTRACE_PEEKTEXT, inferior_pid, -+ (PTRACE_ARG3_TYPE) addr, 0); -+ if (errno) -+ return errno; -+ } -+ -+ /* Copy appropriate bytes out of the buffer. */ -+ memcpy (myaddr, -+ (char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)), len); -+ -+ return 0; -+} -+ -+/* Copy LEN bytes of data from vgdb memory at MYADDR -+ to valgrind memory at MEMADDR. -+ On failure (cannot write the valgrind memory) -+ returns the value of errno. */ -+__attribute__((unused)) /* not used on all platforms */ -+static -+int ptrace_write_memory (pid_t inferior_pid, CORE_ADDR memaddr, -+ const void *myaddr, size_t len) -+{ -+ register int i; -+ /* Round starting address down to longword boundary. */ -+ register CORE_ADDR addr = memaddr & -(CORE_ADDR) sizeof (PTRACE_XFER_TYPE); -+ /* Round ending address up; get number of longwords that makes. */ -+ register int count -+ = (((memaddr + len) - addr) + sizeof (PTRACE_XFER_TYPE) - 1) -+ / sizeof (PTRACE_XFER_TYPE); -+ /* Allocate buffer of that many longwords. */ -+ register PTRACE_XFER_TYPE *buffer -+ = (PTRACE_XFER_TYPE *) alloca (count * sizeof (PTRACE_XFER_TYPE)); -+ -+ if (debuglevel >= 1) { -+ DEBUG (1, "Writing "); -+ for (i = 0; i < len; i++) -+ PDEBUG (1, "%02x", ((const unsigned char*)myaddr)[i]); -+ PDEBUG(1, " to %p\n", (void *) memaddr); -+ } -+ -+ /* Fill start and end extra bytes of buffer with existing memory data. */ -+ -+ buffer[0] = ptrace (PTRACE_PEEKTEXT, inferior_pid, -+ (PTRACE_ARG3_TYPE) addr, 0); -+ -+ if (count > 1) { -+ buffer[count - 1] -+ = ptrace (PTRACE_PEEKTEXT, inferior_pid, -+ (PTRACE_ARG3_TYPE) (addr + (count - 1) -+ * sizeof (PTRACE_XFER_TYPE)), -+ 0); -+ } -+ -+ /* Copy data to be written over corresponding part of buffer */ -+ -+ memcpy ((char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)), -+ myaddr, len); -+ -+ /* Write the entire buffer. */ -+ -+ for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE)) { -+ errno = 0; -+ ptrace (PTRACE_POKETEXT, inferior_pid, -+ (PTRACE_ARG3_TYPE) addr, buffer[i]); -+ if (errno) -+ return errno; -+ } -+ -+ return 0; -+} -+ -+/* subset of VG_(threads) needed for vgdb ptrace. -+ This is initialized when process is attached. */ -+typedef struct { -+ ThreadStatus status; -+ Int lwpid; -+} -+VgdbThreadState; -+static VgdbThreadState vgdb_threads[VG_N_THREADS]; -+ -+static const -+HChar* name_of_ThreadStatus ( ThreadStatus status ) -+{ -+ switch (status) { -+ case VgTs_Empty: return "VgTs_Empty"; -+ case VgTs_Init: return "VgTs_Init"; -+ case VgTs_Runnable: return "VgTs_Runnable"; -+ case VgTs_WaitSys: return "VgTs_WaitSys"; -+ case VgTs_Yielding: return "VgTs_Yielding"; -+ case VgTs_Zombie: return "VgTs_Zombie"; -+ default: return "VgTs_???"; -+ } -+} -+ -+static -+char *status_image (int status) -+{ -+ static char result[256]; -+ int sz = 0; -+#define APPEND(...) sz += snprintf (result+sz, 256 - sz - 1, __VA_ARGS__) -+ -+ result[0] = 0; -+ -+ if (WIFEXITED(status)) -+ APPEND ("WIFEXITED %d ", WEXITSTATUS(status)); -+ -+ if (WIFSIGNALED(status)) { -+ APPEND ("WIFSIGNALED %d ", WTERMSIG(status)); -+ if (WCOREDUMP(status)) APPEND ("WCOREDUMP "); -+ } -+ -+ if (WIFSTOPPED(status)) -+ APPEND ("WIFSTOPPED %d ", WSTOPSIG(status)); -+ -+#ifdef WIFCONTINUED -+ if (WIFCONTINUED(status)) -+ APPEND ("WIFCONTINUED "); -+#endif -+ -+ return result; -+#undef APPEND -+} -+ -+/* Wait till the process pid is reported as stopped with signal_expected. -+ If other signal(s) than signal_expected are received, waitstopped -+ will pass them to pid, waiting for signal_expected to stop pid. -+ Returns True when process is in stopped state with signal_expected. -+ Returns False if a problem was encountered while waiting for pid -+ to be stopped. -+ -+ If pid is reported as being dead/exited, waitstopped will return False. -+*/ -+static -+Bool waitstopped (pid_t pid, int signal_expected, const char *msg) -+{ -+ pid_t p; -+ int status = 0; -+ int signal_received; -+ int res; -+ -+ while (1) { -+ DEBUG(1, "waitstopped %s before waitpid signal_expected %d\n", -+ msg, signal_expected); -+ p = waitpid(pid, &status, __WALL); -+ DEBUG(1, "after waitpid pid %d p %d status 0x%x %s\n", pid, p, -+ status, status_image (status)); -+ if (p != pid) { -+ ERROR(errno, "%s waitpid pid %d in waitstopped %d status 0x%x %s\n", -+ msg, pid, p, status, status_image (status)); -+ return False; -+ } -+ -+ if (WIFEXITED(status)) { -+ shutting_down = True; -+ return False; -+ } -+ -+ assert (WIFSTOPPED(status)); -+ signal_received = WSTOPSIG(status); -+ if (signal_received == signal_expected) -+ break; -+ -+ /* pid received a signal which is not the signal we are waiting for. -+ If we have not (yet) changed the registers of the inferior -+ or we have (already) reset them, we can transmit the signal. -+ -+ If we have already set the registers of the inferior, we cannot -+ transmit the signal, as this signal would arrive when the -+ gdbserver code runs. And valgrind only expects signals to -+ arrive in a small code portion around -+ client syscall logic, where signal are unmasked (see e.g. -+ m_syswrap/syscall-x86-linux.S ML_(do_syscall_for_client_WRK). -+ -+ As ptrace is forcing a call to gdbserver by jumping -+ 'out of this region', signals are not masked, but -+ will arrive outside of the allowed/expected code region. -+ So, if we have changed the registers of the inferior, we -+ rather queue the signal to transmit them when detaching, -+ after having restored the registers to the initial values. */ -+ if (pid_of_save_regs) { -+ siginfo_t *newsiginfo; -+ -+ // realloc a bigger queue, and store new signal at the end. -+ // This is not very efficient but we assume not many sigs are queued. -+ signal_queue_sz++; -+ signal_queue = vrealloc(signal_queue, sizeof(siginfo_t) * signal_queue_sz); -+ newsiginfo = signal_queue + (signal_queue_sz - 1); -+ -+ res = ptrace (PTRACE_GETSIGINFO, pid, NULL, newsiginfo); -+ if (res != 0) { -+ ERROR(errno, "PTRACE_GETSIGINFO failed: signal lost !!!!\n"); -+ signal_queue_sz--; -+ } else -+ DEBUG(1, "waitstopped PTRACE_CONT, queuing signal %d" -+ " si_signo %d si_pid %d\n", -+ signal_received, newsiginfo->si_signo, newsiginfo->si_pid); -+ res = ptrace (PTRACE_CONT, pid, NULL, 0); -+ } else { -+ DEBUG(1, "waitstopped PTRACE_CONT with signal %d\n", signal_received); -+ res = ptrace (PTRACE_CONT, pid, NULL, signal_received); -+ } -+ if (res != 0) { -+ ERROR(errno, "waitstopped PTRACE_CONT\n"); -+ return False; -+ } -+ } -+ -+ return True; -+} -+ -+/* Stops the given pid, wait for the process to be stopped. -+ Returns True if succesful, False otherwise. -+ msg is used in tracing and error reporting. */ -+static -+Bool stop (pid_t pid, const char *msg) -+{ -+ long res; -+ -+ DEBUG(1, "%s SIGSTOP pid %d\n", msg, pid); -+ res = kill (pid, SIGSTOP); -+ if (res != 0) { -+ ERROR(errno, "%s SIGSTOP pid %d %ld\n", msg, pid, res); -+ return False; -+ } -+ -+ return waitstopped (pid, SIGSTOP, msg); -+ -+} -+ -+/* Attaches to given pid, wait for the process to be stopped. -+ Returns True if succesful, False otherwise. -+ msg is used in tracing and error reporting. */ -+static -+Bool attach (pid_t pid, const char *msg) -+{ -+ long res; -+ static Bool output_error = True; -+ static Bool initial_attach = True; -+ // For a ptrace_scope protected system, we do not want to output -+ // repetitively attach error. We will output once an error -+ // for the initial_attach. Once the 1st attach has succeeded, we -+ // again show all errors. -+ -+ DEBUG(1, "%s PTRACE_ATTACH pid %d\n", msg, pid); -+ res = ptrace (PTRACE_ATTACH, pid, NULL, NULL); -+ if (res != 0) { -+ if (output_error || debuglevel > 0) { -+ ERROR(errno, "%s PTRACE_ATTACH pid %d %ld\n", msg, pid, res); -+ if (initial_attach) -+ output_error = False; -+ } -+ return False; -+ } -+ -+ initial_attach = False; -+ output_error = True; -+ return waitstopped(pid, SIGSTOP, msg); -+} -+ -+/* once we are attached to the pid, get the list of threads and stop -+ them all. -+ Returns True if all threads properly suspended, False otherwise. */ -+static -+Bool acquire_and_suspend_threads (pid_t pid) -+{ -+ int i; -+ int rw; -+ Bool pid_found = False; -+ Addr vgt; -+ int sz_tst; -+ int off_status; -+ int off_lwpid; -+ int nr_live_threads = 0; -+ -+ if (shared32 != NULL) { -+ vgt = shared32->threads; -+ sz_tst = shared32->sizeof_ThreadState; -+ off_status = shared32->offset_status; -+ off_lwpid = shared32->offset_lwpid; -+ } -+ else if (shared64 != NULL) { -+ vgt = shared64->threads; -+ sz_tst = shared64->sizeof_ThreadState; -+ off_status = shared64->offset_status; -+ off_lwpid = shared64->offset_lwpid; -+ } else { -+ assert (0); -+ } -+ -+ /* note: the entry 0 is unused */ -+ for (i = 1; i < VG_N_THREADS; i++) { -+ vgt += sz_tst; -+ rw = ptrace_read_memory(pid, vgt+off_status, -+ &(vgdb_threads[i].status), -+ sizeof(ThreadStatus)); -+ if (rw != 0) { -+ ERROR(rw, "status ptrace_read_memory\n"); -+ return False; -+ } -+ -+ rw = ptrace_read_memory(pid, vgt+off_lwpid, -+ &(vgdb_threads[i].lwpid), -+ sizeof(Int)); -+ if (rw != 0) { -+ ERROR(rw, "lwpid ptrace_read_memory\n"); -+ return False; -+ } -+ -+ if (vgdb_threads[i].status != VgTs_Empty) { -+ DEBUG(1, "found tid %d status %s lwpid %d\n", -+ i, name_of_ThreadStatus(vgdb_threads[i].status), -+ vgdb_threads[i].lwpid); -+ nr_live_threads++; -+ if (vgdb_threads[i].lwpid <= 1) { -+ if (vgdb_threads[i].lwpid == 0 -+ && vgdb_threads[i].status == VgTs_Init) { -+ DEBUG(1, "not set lwpid tid %d status %s lwpid %d\n", -+ i, name_of_ThreadStatus(vgdb_threads[i].status), -+ vgdb_threads[i].lwpid); -+ } else { -+ ERROR(1, "unexpected lwpid tid %d status %s lwpid %d\n", -+ i, name_of_ThreadStatus(vgdb_threads[i].status), -+ vgdb_threads[i].lwpid); -+ } -+ /* in case we have a VtTs_Init thread with lwpid not yet set, -+ we try again later. */ -+ return False; -+ } -+ if (vgdb_threads[i].lwpid == pid) { -+ assert (!pid_found); -+ assert (i == 1); -+ pid_found = True; -+ } else { -+ if (!attach(vgdb_threads[i].lwpid, "attach_thread")) { -+ ERROR(0, "ERROR attach pid %d tid %d\n", -+ vgdb_threads[i].lwpid, i); -+ return False; -+ } -+ } -+ } -+ } -+ /* If we found no thread, it means the process is stopping, and -+ we better do not force anything to happen during that. */ -+ if (nr_live_threads > 0) -+ return True; -+ else -+ return False; -+} -+ -+static -+void detach_from_all_threads (pid_t pid) -+{ -+ int i; -+ long res; -+ Bool pid_found = False; -+ -+ /* detach from all the threads */ -+ for (i = 1; i < VG_N_THREADS; i++) { -+ if (vgdb_threads[i].status != VgTs_Empty) { -+ if (vgdb_threads[i].status == VgTs_Init -+ && vgdb_threads[i].lwpid == 0) { -+ DEBUG(1, "skipping PTRACE_DETACH pid %d tid %d status %s\n", -+ vgdb_threads[i].lwpid, i, -+ name_of_ThreadStatus (vgdb_threads[i].status)); -+ } else { -+ if (vgdb_threads[i].lwpid == pid) { -+ assert (!pid_found); -+ pid_found = True; -+ } -+ DEBUG(1, "PTRACE_DETACH pid %d tid %d status %s\n", -+ vgdb_threads[i].lwpid, i, -+ name_of_ThreadStatus (vgdb_threads[i].status)); -+ res = ptrace (PTRACE_DETACH, vgdb_threads[i].lwpid, NULL, NULL); -+ if (res != 0) { -+ ERROR(errno, "PTRACE_DETACH pid %d tid %d status %s res %ld\n", -+ vgdb_threads[i].lwpid, i, -+ name_of_ThreadStatus (vgdb_threads[i].status), -+ res); -+ } -+ } -+ } -+ } -+ -+ if (!pid_found && pid) { -+ /* No threads are live. Process is busy stopping. -+ We need to detach from pid explicitely. */ -+ DEBUG(1, "no thread live => PTRACE_DETACH pid %d\n", pid); -+ res = ptrace (PTRACE_DETACH, pid, NULL, NULL); -+ if (res != 0) -+ ERROR(errno, "PTRACE_DETACH pid %d res %ld\n", pid, res); -+ } -+} -+ -+# if defined(VGA_arm64) -+static struct user_pt_regs user_save; -+# else -+static struct user user_save; -+# endif -+// The below indicates if ptrace_getregs (and ptrace_setregs) can be used. -+// Note that some linux versions are defining PTRACE_GETREGS but using -+// it gives back EIO. -+// has_working_ptrace_getregs can take the following values: -+// -1 : PTRACE_GETREGS is defined -+// runtime check not yet done. -+// 0 : PTRACE_GETREGS runtime check has failed. -+// 1 : PTRACE_GETREGS defined and runtime check ok. -+#ifdef HAVE_PTRACE_GETREGS -+static int has_working_ptrace_getregs = -1; -+#endif -+// Similar but for PTRACE_GETREGSET -+#ifdef HAVE_PTRACE_GETREGSET -+static int has_working_ptrace_getregset = -1; -+#endif -+ -+/* Get the registers from pid into regs. -+ regs_bsz value gives the length of *regs. -+ Returns True if all ok, otherwise False. */ -+static -+Bool getregs (pid_t pid, void *regs, long regs_bsz) -+{ -+ DEBUG(1, "getregs regs_bsz %ld\n", regs_bsz); -+# ifdef HAVE_PTRACE_GETREGSET -+# ifndef USE_PTRACE_GETREGSET -+ if (has_working_ptrace_getregset) -+ DEBUG(1, "PTRACE_GETREGSET defined, not used (yet?) by vgdb\n"); -+ has_working_ptrace_getregset = 0; -+# endif -+ if (has_working_ptrace_getregset) { -+ // Platforms having GETREGSET -+ long res; -+ elf_gregset_t elf_regs; -+ struct iovec iovec; -+ -+ DEBUG(1, "getregs PTRACE_GETREGSET sizeof(elf_regs) %d\n", sizeof(elf_regs)); -+ iovec.iov_base = regs; -+ iovec.iov_len = sizeof(elf_regs); -+ -+ res = ptrace (PTRACE_GETREGSET, pid, NT_PRSTATUS, &iovec); -+ if (res == 0) { -+ if (has_working_ptrace_getregset == -1) { -+ // First call to PTRACE_GETREGSET succesful => -+ has_working_ptrace_getregset = 1; -+ DEBUG(1, "detected a working PTRACE_GETREGSET\n"); -+ } -+ assert (has_working_ptrace_getregset == 1); -+ return True; -+ } -+ else if (has_working_ptrace_getregset == 1) { -+ // We had a working call, but now it fails. -+ // This is unexpected. -+ ERROR(errno, "PTRACE_GETREGSET %ld\n", res); -+ return False; -+ } else { -+ // Check this is the first call: -+ assert (has_working_ptrace_getregset == -1); -+ if (errno == EIO) { -+ DEBUG(1, "detected a broken PTRACE_GETREGSET with EIO\n"); -+ has_working_ptrace_getregset = 0; -+ // Fall over to the PTRACE_GETREGS or PTRACE_PEEKUSER case. -+ } else { -+ ERROR(errno, "broken PTRACE_GETREGSET unexpected errno %ld\n", res); -+ return False; -+ } -+ } -+ } -+# endif -+ -+# ifdef HAVE_PTRACE_GETREGS -+ if (has_working_ptrace_getregs) { -+ // Platforms having GETREGS -+ long res; -+ DEBUG(1, "getregs PTRACE_GETREGS\n"); -+ res = ptrace (PTRACE_GETREGS, pid, NULL, regs); -+ if (res == 0) { -+ if (has_working_ptrace_getregs == -1) { -+ // First call to PTRACE_GETREGS succesful => -+ has_working_ptrace_getregs = 1; -+ DEBUG(1, "detected a working PTRACE_GETREGS\n"); -+ } -+ assert (has_working_ptrace_getregs == 1); -+ return True; -+ } -+ else if (has_working_ptrace_getregs == 1) { -+ // We had a working call, but now it fails. -+ // This is unexpected. -+ ERROR(errno, "PTRACE_GETREGS %ld\n", res); -+ return False; -+ } else { -+ // Check this is the first call: -+ assert (has_working_ptrace_getregs == -1); -+ if (errno == EIO) { -+ DEBUG(1, "detected a broken PTRACE_GETREGS with EIO\n"); -+ has_working_ptrace_getregs = 0; -+ // Fall over to the PTRACE_PEEKUSER case. -+ } else { -+ ERROR(errno, "broken PTRACE_GETREGS unexpected errno %ld\n", res); -+ return False; -+ } -+ } -+ } -+# endif -+ -+ // We assume PTRACE_PEEKUSER is defined everywhere. -+ { -+# ifdef PT_ENDREGS -+ long peek_bsz = PT_ENDREGS; -+ assert (peek_bsz <= regs_bsz); -+# else -+ long peek_bsz = regs_bsz-1; -+# endif -+ char *pregs = (char *) regs; -+ long offset; -+ errno = 0; -+ DEBUG(1, "getregs PTRACE_PEEKUSER(s) peek_bsz %ld\n", peek_bsz); -+ for (offset = 0; offset < peek_bsz; offset = offset + sizeof(long)) { -+ *(long *)(pregs+offset) = ptrace(PTRACE_PEEKUSER, pid, offset, NULL); -+ if (errno != 0) { -+ ERROR(errno, "PTRACE_PEEKUSER offset %ld\n", offset); -+ return False; -+ } -+ } -+ return True; -+ } -+ -+ // If neither of PTRACE_GETREGSET PTRACE_GETREGS PTRACE_PEEKUSER have -+ // returned, then we are in serious trouble. -+ assert (0); -+} -+ -+/* Set the registers of pid to regs. -+ regs_bsz value gives the length of *regs. -+ Returns True if all ok, otherwise False. */ -+static -+Bool setregs (pid_t pid, void *regs, long regs_bsz) -+{ -+ DEBUG(1, "setregs regs_bsz %ld\n", regs_bsz); -+ -+// Note : the below is checking for GETREGSET, not SETREGSET -+// as if one is defined and working, the other one should also work. -+# ifdef HAVE_PTRACE_GETREGSET -+ if (has_working_ptrace_getregset) { -+ // Platforms having SETREGSET -+ long res; -+ elf_gregset_t elf_regs; -+ struct iovec iovec; -+ -+ // setregset can never be called before getregset has done a runtime check. -+ assert (has_working_ptrace_getregset == 1); -+ DEBUG(1, "setregs PTRACE_SETREGSET sizeof(elf_regs) %d\n", sizeof(elf_regs)); -+ iovec.iov_base = regs; -+ iovec.iov_len = sizeof(elf_regs); -+ res = ptrace (PTRACE_SETREGSET, pid, NT_PRSTATUS, &iovec); -+ if (res != 0) { -+ ERROR(errno, "PTRACE_SETREGSET %ld\n", res); -+ return False; -+ } -+ return True; -+ } -+# endif -+ -+// Note : the below is checking for GETREGS, not SETREGS -+// as if one is defined and working, the other one should also work. -+# ifdef HAVE_PTRACE_GETREGS -+ if (has_working_ptrace_getregs) { -+ // Platforms having SETREGS -+ long res; -+ // setregs can never be called before getregs has done a runtime check. -+ assert (has_working_ptrace_getregs == 1); -+ DEBUG(1, "setregs PTRACE_SETREGS\n"); -+ res = ptrace (PTRACE_SETREGS, pid, NULL, regs); -+ if (res != 0) { -+ ERROR(errno, "PTRACE_SETREGS %ld\n", res); -+ return False; -+ } -+ return True; -+ } -+# endif -+ -+ { -+ char *pregs = (char *) regs; -+ long offset; -+ long res; -+# ifdef PT_ENDREGS -+ long peek_bsz = PT_ENDREGS; -+ assert (peek_bsz <= regs_bsz); -+# else -+ long peek_bsz = regs_bsz-1; -+# endif -+ errno = 0; -+ DEBUG(1, "setregs PTRACE_POKEUSER(s) %ld\n", peek_bsz); -+ for (offset = 0; offset < peek_bsz; offset = offset + sizeof(long)) { -+ res = ptrace(PTRACE_POKEUSER, pid, offset, *(long*)(pregs+offset)); -+ if (errno != 0) { -+ ERROR(errno, "PTRACE_POKEUSER offset %ld res %ld\n", offset, res); -+ return False; -+ } -+ } -+ return True; -+ } -+ -+ // If neither PTRACE_SETREGS not PTRACE_POKEUSER have returned, -+ // then we are in serious trouble. -+ assert (0); -+} -+ -+/* Restore the registers to the saved value, then detaches from all threads */ -+static -+void restore_and_detach (pid_t pid) -+{ -+ int res; -+ -+ DEBUG(1, "restore_and_detach pid %d pid_of_save_regs %d\n", -+ pid, pid_of_save_regs); -+ -+ if (pid_of_save_regs) { -+ /* In case the 'main pid' has been continued, we need to stop it -+ before resetting the registers. */ -+ if (pid_of_save_regs_continued) { -+ pid_of_save_regs_continued = False; -+ if (!stop(pid_of_save_regs, "sigstop before reset regs")) -+ DEBUG(0, "Could not sigstop before reset"); -+ } -+ -+ DEBUG(1, "setregs restore registers pid %d\n", pid_of_save_regs); -+ if (!setregs(pid_of_save_regs, &user_save.regs, sizeof(user_save.regs))) { -+ ERROR(errno, "setregs restore registers pid %d after cont\n", -+ pid_of_save_regs); -+ } -+ -+ /* Now, we transmit all the signals we have queued. */ -+ if (signal_queue_sz > 0) { -+ int i; -+ for (i = 0; i < signal_queue_sz; i++) { -+ DEBUG(1, "PTRACE_CONT to transmit queued signal %d\n", -+ signal_queue[i].si_signo); -+ res = ptrace (PTRACE_CONT, pid_of_save_regs, NULL, -+ signal_queue[i].si_signo); -+ if (res != 0) -+ ERROR(errno, "PTRACE_CONT with signal %d\n", -+ signal_queue[i].si_signo); -+ if (!stop(pid_of_save_regs, "sigstop after transmit sig")) -+ DEBUG(0, "Could not sigstop after transmit sig"); -+ } -+ free (signal_queue); -+ signal_queue = NULL; -+ signal_queue_sz = 0; -+ } -+ pid_of_save_regs = 0; -+ } else { -+ DEBUG(1, "PTRACE_SETREGS restore registers: no pid\n"); -+ } -+ if (signal_queue) -+ ERROR (0, "One or more signals queued were not delivered. " -+ "First signal: %d\n", signal_queue); -+ detach_from_all_threads(pid); -+} -+ -+Bool invoker_invoke_gdbserver (pid_t pid) -+{ -+ long res; -+ Bool stopped; -+# if defined(VGA_arm64) -+ struct user_pt_regs user_mod; -+# else -+ struct user user_mod; -+# endif -+ Addr sp; -+ /* A specific int value is passed to invoke_gdbserver, to check -+ everything goes according to the plan. */ -+ const int check = 0x8BADF00D; // ate bad food. -+ -+ const Addr bad_return = 0; -+ // A bad return address will be pushed on the stack. -+ // The function invoke_gdbserver cannot return. If ever it returns, a NULL -+ // address pushed on the stack should ensure this is detected. -+ -+ /* Not yet attached. If problem, vgdb can abort, -+ no cleanup needed. */ -+ -+ DEBUG(1, "attach to 'main' pid %d\n", pid); -+ if (!attach(pid, "attach main pid")) { -+ ERROR(0, "error attach main pid %d\n", pid); -+ return False; -+ } -+ -+ /* Now, we are attached. If problem, detach and return. */ -+ -+ if (!acquire_and_suspend_threads(pid)) { -+ detach_from_all_threads(pid); -+ /* if the pid does not exist anymore, we better stop */ -+ if (kill(pid, 0) != 0) -+ XERROR (errno, "invoke_gdbserver: check for pid %d existence failed\n", -+ pid); -+ return False; -+ } -+ -+ if (!getregs(pid, &user_mod.regs, sizeof(user_mod.regs))) { -+ detach_from_all_threads(pid); -+ return False; -+ } -+ user_save = user_mod; -+ -+#if defined(VGA_x86) -+ sp = user_mod.regs.esp; -+#elif defined(VGA_amd64) -+ sp = user_mod.regs.rsp; -+ if (shared32 != NULL) { -+ /* 64bit vgdb speaking with a 32bit executable. -+ To have system call restart properly, we need to sign extend rax. -+ For more info: -+ web search '[patch] Fix syscall restarts for amd64->i386 biarch' -+ e.g. http://sourceware.org/ml/gdb-patches/2009-11/msg00592.html */ -+ *(long *)&user_save.regs.rax = *(int*)&user_save.regs.rax; -+ DEBUG(1, "Sign extending %8.8lx to %8.8lx\n", -+ user_mod.regs.rax, user_save.regs.rax); -+ } -+#elif defined(VGA_arm) -+ sp = user_mod.regs.uregs[13]; -+#elif defined(VGA_arm64) -+ sp = user_mod.sp; -+#elif defined(VGA_ppc32) -+ sp = user_mod.regs.gpr[1]; -+#elif defined(VGA_ppc64) -+ sp = user_mod.regs.gpr[1]; -+#elif defined(VGA_s390x) -+ sp = user_mod.regs.gprs[15]; -+#elif defined(VGA_mips32) -+ long long *p = (long long *)user_mod.regs; -+ sp = p[29]; -+#elif defined(VGA_mips64) -+ sp = user_mod.regs[29]; -+#else -+ I_die_here : (sp) architecture missing in vgdb.c -+#endif -+ -+ -+ // the magic below is derived from spying what gdb sends to -+ // the (classical) gdbserver when invoking a C function. -+ if (shared32 != NULL) { -+ // vgdb speaking with a 32bit executable. -+#if defined(VGA_x86) || defined(VGA_amd64) -+ const int regsize = 4; -+ int rw; -+ /* push check arg on the stack */ -+ sp = sp - regsize; -+ DEBUG(1, "push check arg ptrace_write_memory\n"); -+ assert(regsize == sizeof(check)); -+ rw = ptrace_write_memory(pid, sp, -+ &check, -+ regsize); -+ if (rw != 0) { -+ ERROR(rw, "push check arg ptrace_write_memory"); -+ detach_from_all_threads(pid); -+ return False; -+ } -+ -+ sp = sp - regsize; -+ DEBUG(1, "push bad_return return address ptrace_write_memory\n"); -+ // Note that for a 64 bits vgdb, only 4 bytes of NULL bad_return -+ // are written. -+ rw = ptrace_write_memory(pid, sp, -+ &bad_return, -+ regsize); -+ if (rw != 0) { -+ ERROR(rw, "push bad_return return address ptrace_write_memory"); -+ detach_from_all_threads(pid); -+ return False; -+ } -+#if defined(VGA_x86) -+ /* set ebp, esp, eip and orig_eax to invoke gdbserver */ -+ // compiled in 32bits, speaking with a 32bits exe -+ user_mod.regs.ebp = sp; // bp set to sp -+ user_mod.regs.esp = sp; -+ user_mod.regs.eip = shared32->invoke_gdbserver; -+ user_mod.regs.orig_eax = -1L; -+#elif defined(VGA_amd64) -+ /* set ebp, esp, eip and orig_eax to invoke gdbserver */ -+ // compiled in 64bits, speaking with a 32bits exe -+ user_mod.regs.rbp = sp; // bp set to sp -+ user_mod.regs.rsp = sp; -+ user_mod.regs.rip = shared32->invoke_gdbserver; -+ user_mod.regs.orig_rax = -1L; -+#else -+ I_die_here : not x86 or amd64 in x86/amd64 section/ -+#endif -+ -+#elif defined(VGA_ppc32) || defined(VGA_ppc64) -+ user_mod.regs.nip = shared32->invoke_gdbserver; -+ user_mod.regs.trap = -1L; -+ /* put check arg in register 3 */ -+ user_mod.regs.gpr[3] = check; -+ /* put NULL return address in Link Register */ -+ user_mod.regs.link = bad_return; -+ -+#elif defined(VGA_arm) -+ /* put check arg in register 0 */ -+ user_mod.regs.uregs[0] = check; -+ /* put NULL return address in Link Register */ -+ user_mod.regs.uregs[14] = bad_return; -+ user_mod.regs.uregs[15] = shared32->invoke_gdbserver; -+ -+#elif defined(VGA_arm64) -+ XERROR(0, "TBD arm64: vgdb a 32 bits executable with a 64 bits exe"); -+ -+#elif defined(VGA_s390x) -+ XERROR(0, "(fn32) s390x has no 32bits implementation"); -+#elif defined(VGA_mips32) -+ /* put check arg in register 4 */ -+ p[4] = check; -+ /* put NULL return address in ra */ -+ p[31] = bad_return; -+ p[34] = shared32->invoke_gdbserver; -+ p[25] = shared32->invoke_gdbserver; -+ /* make stack space for args */ -+ p[29] = sp - 32; -+ -+#elif defined(VGA_mips64) -+ assert(0); // cannot vgdb a 32 bits executable with a 64 bits exe -+#else -+ I_die_here : architecture missing in vgdb.c -+#endif -+ } -+ -+ else if (shared64 != NULL) { -+#if defined(VGA_x86) -+ assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe -+#elif defined(VGA_amd64) -+ // vgdb speaking with a 64 bit executable. -+ const int regsize = 8; -+ int rw; -+ -+ /* give check arg in rdi */ -+ user_mod.regs.rdi = check; -+ -+ /* push return address on stack : return to breakaddr */ -+ sp = sp - regsize; -+ DEBUG(1, "push bad_return return address ptrace_write_memory\n"); -+ rw = ptrace_write_memory(pid, sp, -+ &bad_return, -+ sizeof(bad_return)); -+ if (rw != 0) { -+ ERROR(rw, "push bad_return return address ptrace_write_memory"); -+ detach_from_all_threads(pid); -+ return False; -+ } -+ -+ /* set rbp, rsp, rip and orig_rax to invoke gdbserver */ -+ user_mod.regs.rbp = sp; // bp set to sp -+ user_mod.regs.rsp = sp; -+ user_mod.regs.rip = shared64->invoke_gdbserver; -+ user_mod.regs.orig_rax = -1L; -+ -+#elif defined(VGA_arm) -+ assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe -+#elif defined(VGA_arm64) -+ user_mod.regs[0] = check; -+ user_mod.sp = sp; -+ user_mod.pc = shared64->invoke_gdbserver; -+ /* put NULL return address in Link Register */ -+ user_mod.regs[30] = bad_return; -+ -+#elif defined(VGA_ppc32) -+ assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe -+#elif defined(VGA_ppc64) -+ Addr64 func_addr; -+ Addr64 toc_addr; -+ int rw; -+ rw = ptrace_read_memory(pid, shared64->invoke_gdbserver, -+ &func_addr, -+ sizeof(Addr64)); -+ if (rw != 0) { -+ ERROR(rw, "ppc64 read func_addr\n"); -+ detach_from_all_threads(pid); -+ return False; -+ } -+ rw = ptrace_read_memory(pid, shared64->invoke_gdbserver+8, -+ &toc_addr, -+ sizeof(Addr64)); -+ if (rw != 0) { -+ ERROR(rw, "ppc64 read toc_addr\n"); -+ detach_from_all_threads(pid); -+ return False; -+ } -+ // We are not pushing anything on the stack, so it is not -+ // very clear why the sp has to be decreased, but it seems -+ // needed. The ppc64 ABI might give some lights on this ? -+ user_mod.regs.gpr[1] = sp - 220; -+ user_mod.regs.gpr[2] = toc_addr; -+ user_mod.regs.nip = func_addr; -+ user_mod.regs.trap = -1L; -+ /* put check arg in register 3 */ -+ user_mod.regs.gpr[3] = check; -+ /* put bad_return return address in Link Register */ -+ user_mod.regs.link = bad_return; -+#elif defined(VGA_s390x) -+ /* put check arg in register r2 */ -+ user_mod.regs.gprs[2] = check; -+ /* bad_return Return address is in r14 */ -+ user_mod.regs.gprs[14] = bad_return; -+ /* minimum stack frame */ -+ sp = sp - 160; -+ user_mod.regs.gprs[15] = sp; -+ /* set program counter */ -+ user_mod.regs.psw.addr = shared64->invoke_gdbserver; -+#elif defined(VGA_mips32) -+ assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe -+#elif defined(VGA_mips64) -+ /* put check arg in register 4 */ -+ user_mod.regs[4] = check; -+ /* put NULL return address in ra */ -+ user_mod.regs[31] = bad_return; -+ user_mod.regs[34] = shared64->invoke_gdbserver; -+ user_mod.regs[25] = shared64->invoke_gdbserver; -+#else -+ I_die_here: architecture missing in vgdb.c -+#endif -+ } -+ else { -+ assert(0); -+ } -+ -+ if (!setregs(pid, &user_mod.regs, sizeof(user_mod.regs))) { -+ detach_from_all_threads(pid); -+ return False; -+ } -+ /* Now that we have modified the registers, we set -+ pid_of_save_regs to indicate that restore_and_detach -+ must restore the registers in case of cleanup. */ -+ pid_of_save_regs = pid; -+ pid_of_save_regs_continued = False; -+ -+ -+ /* We PTRACE_CONT-inue pid. -+ Either gdbserver will be invoked directly (if all -+ threads are interruptible) or gdbserver will be -+ called soon by the scheduler. In the first case, -+ pid will stop on the break inserted above when -+ gdbserver returns. In the 2nd case, the break will -+ be encountered directly. */ -+ DEBUG(1, "PTRACE_CONT to invoke\n"); -+ res = ptrace (PTRACE_CONT, pid, NULL, NULL); -+ if (res != 0) { -+ ERROR(errno, "PTRACE_CONT\n"); -+ restore_and_detach(pid); -+ return False; -+ } -+ pid_of_save_regs_continued = True; -+ /* Wait for SIGSTOP generated by m_gdbserver.c give_control_back_to_vgdb */ -+ stopped = waitstopped (pid, SIGSTOP, -+ "waitpid status after PTRACE_CONT to invoke"); -+ if (stopped) { -+ /* Here pid has properly stopped on the break. */ -+ pid_of_save_regs_continued = False; -+ restore_and_detach(pid); -+ return True; -+ } else { -+ /* Whatever kind of problem happened. We shutdown. */ -+ shutting_down = True; -+ return False; -+ } -+} -+ -+void invoker_cleanup_restore_and_detach(void *v_pid) -+{ -+ DEBUG(1, "invoker_cleanup_restore_and_detach dying: %d\n", dying); -+ if (!dying) -+ restore_and_detach(*(int*)v_pid); -+} -+ -+void invoker_restrictions_msg(void) -+{ -+} -+ -+void invoker_valgrind_dying(void) -+{ -+ /* Avoid messing up with registers of valgrind when it is dying. */ -+ pid_of_save_regs_continued = False; -+ dying = True; -+} -Index: coregrind/vgdb.c -=================================================================== ---- coregrind/vgdb.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ coregrind/vgdb.c (.../trunk) (revision 13981) -@@ -26,34 +26,28 @@ - The GNU General Public License is contained in the file COPYING. - */ - --#include "pub_core_basics.h" --#include "pub_core_vki.h" --#include "pub_core_libcsetjmp.h" --#include "pub_core_threadstate.h" --#include "pub_core_gdbserver.h" -+#include "vgdb.h" -+ - #include "config.h" - -+#include -+#include -+#include -+#include - #include --#include --#include - #include - #include -+#include - #include - #include --#include --#include -+#include -+#include -+#include -+#include -+#include - #include - #include --#include --#include --#include --#include --#include --#include --#include --#include --#include --#include -+ - /* vgdb has two usages: - 1. relay application between gdb and the gdbserver embedded in valgrind. - 2. standalone to send monitor commands to a running valgrind-ified process -@@ -72,75 +66,18 @@ - As a standalone utility, vgdb builds command packets to write to valgrind, - sends it and reads the reply. The same two threads are used to write/read. - Once all the commands are sent and their replies received, vgdb will exit. -- - */ - --/* define PTRACEINVOKER to compile the ptrace related code -- which ensures a valgrind process blocked in a system call -- can be "waken up". PTRACEINVOKER implies some architecture -- specific code and/or some OS specific code. */ --#if defined(VGA_arm) || defined(VGA_x86) || defined(VGA_amd64) \ -- || defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \ -- || defined(VGA_mips32) || defined(VGA_mips64) --#define PTRACEINVOKER --#else --I_die_here : (PTRACEINVOKER) architecture missing in vgdb.c --#endif -- --/* Some darwin specific stuff is needed as ptrace is not -- fully supported on MacOS. Till we find someone courageous -- having access to Darwin, there is no PTRACEINVOKER. */ --#if defined(VGO_darwin) --#undef PTRACEINVOKER --#endif -- --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) --#undef PTRACEINVOKER --#endif -- --#if defined(PTRACEINVOKER) --#include --#endif -- -- --// Outputs information for the user about ptrace not working. --static void ptrace_restrictions_msg(void); -- --static int debuglevel; --static struct timeval dbgtv; --/* if level <= debuglevel, print timestamp, then print provided by debug info */ --#define DEBUG(level, ...) (level <= debuglevel ? \ -- gettimeofday(&dbgtv, NULL), \ -- fprintf(stderr, "%ld.%6.6ld ", \ -- (long int)dbgtv.tv_sec, \ -- (long int)dbgtv.tv_usec), \ -- fprintf(stderr, __VA_ARGS__),fflush(stderr) \ -- : 0) -- --/* same as DEBUG but does not print time stamp info */ --#define PDEBUG(level, ...) (level <= debuglevel ? \ -- fprintf(stderr, __VA_ARGS__),fflush(stderr) \ -- : 0) -- --/* if errno != 0, -- report the errno and fprintf the ... varargs on stderr. */ --#define ERROR(errno, ...) ((errno == 0 ? 0 : perror("syscall failed")), \ -- fprintf(stderr, __VA_ARGS__), \ -- fflush(stderr)) --/* same as ERROR, but also exits with status 1 */ --#define XERROR(errno, ...) ((errno == 0 ? 0 : perror("syscall failed")), \ -- fprintf(stderr, __VA_ARGS__), \ -- fflush(stderr), \ -- exit(1)) -- -+int debuglevel; -+struct timeval dbgtv; - static char *vgdb_prefix = NULL; - - /* Will be set to True when any condition indicating we have to shutdown - is encountered. */ --static Bool shutting_down = False; -+Bool shutting_down = False; - --static VgdbShared32 *shared32; --static VgdbShared64 *shared64; -+VgdbShared32 *shared32; -+VgdbShared64 *shared64; - #define VS_written_by_vgdb (shared32 != NULL ? \ - shared32->written_by_vgdb \ - : shared64->written_by_vgdb) -@@ -150,8 +87,6 @@ - - #define VS_vgdb_pid (shared32 != NULL ? shared32->vgdb_pid : shared64->vgdb_pid) - --/* Calls malloc (size). Exits if memory can't be allocated. */ --static - void *vmalloc(size_t size) - { - void * mem = malloc(size); -@@ -160,8 +95,6 @@ - return mem; - } - --/* Calls realloc (size). Exits if memory can't be allocated. */ --static - void *vrealloc(void *ptr,size_t size) - { - void * mem = realloc(ptr, size); -@@ -266,898 +199,11 @@ - - } - --#if VEX_HOST_WORDSIZE == 8 --typedef Addr64 CORE_ADDR; --typedef Addr64 PTRACE_XFER_TYPE; --typedef void* PTRACE_ARG3_TYPE; --#elif VEX_HOST_WORDSIZE == 4 --typedef Addr32 CORE_ADDR; --typedef Addr32 PTRACE_XFER_TYPE; --typedef void* PTRACE_ARG3_TYPE; --#else --# error "unexpected wordsize" --#endif -- --static Bool pid_of_save_regs_continued = False; --// True if we have continued pid_of_save_regs after PTRACE_ATTACH -- --static Bool dying = False; --// Set to True when loss of connection indicating that the Valgrind --// process is dying. -- --/* To be called when connection with valgrind is lost. In case we --have lost the connection, it means that Valgrind has closed the --connection and is busy exiting. We can't and don't have to stop it in --this case. */ --static --void valgrind_dying(void) --{ -- pid_of_save_regs_continued = False; -- dying = True; --} -- -- --#ifdef PTRACEINVOKER --/* ptrace_(read|write)_memory are modified extracts of linux-low.c -- from gdb 6.6. Copyrighted FSF */ --/* Copy LEN bytes from valgrind memory starting at MEMADDR -- to vgdb memory starting at MYADDR. */ -- --static --int ptrace_read_memory (pid_t inferior_pid, CORE_ADDR memaddr, -- void *myaddr, int len) --{ -- register int i; -- /* Round starting address down to longword boundary. */ -- register CORE_ADDR addr = memaddr & -(CORE_ADDR) sizeof (PTRACE_XFER_TYPE); -- /* Round ending address up; get number of longwords that makes. */ -- register int count -- = (((memaddr + len) - addr) + sizeof (PTRACE_XFER_TYPE) - 1) -- / sizeof (PTRACE_XFER_TYPE); -- /* Allocate buffer of that many longwords. */ -- register PTRACE_XFER_TYPE *buffer -- = (PTRACE_XFER_TYPE *) alloca (count * sizeof (PTRACE_XFER_TYPE)); -- -- /* Read all the longwords */ -- for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE)) { -- errno = 0; -- buffer[i] = ptrace (PTRACE_PEEKTEXT, inferior_pid, -- (PTRACE_ARG3_TYPE) addr, 0); -- if (errno) -- return errno; -- } -- -- /* Copy appropriate bytes out of the buffer. */ -- memcpy (myaddr, -- (char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)), len); -- -- return 0; --} -- --/* Copy LEN bytes of data from vgdb memory at MYADDR -- to valgrind memory at MEMADDR. -- On failure (cannot write the valgrind memory) -- returns the value of errno. */ --__attribute__((unused)) /* not used on all platforms */ --static --int ptrace_write_memory (pid_t inferior_pid, CORE_ADDR memaddr, -- const void *myaddr, int len) --{ -- register int i; -- /* Round starting address down to longword boundary. */ -- register CORE_ADDR addr = memaddr & -(CORE_ADDR) sizeof (PTRACE_XFER_TYPE); -- /* Round ending address up; get number of longwords that makes. */ -- register int count -- = (((memaddr + len) - addr) + sizeof (PTRACE_XFER_TYPE) - 1) -- / sizeof (PTRACE_XFER_TYPE); -- /* Allocate buffer of that many longwords. */ -- register PTRACE_XFER_TYPE *buffer -- = (PTRACE_XFER_TYPE *) alloca (count * sizeof (PTRACE_XFER_TYPE)); -- -- if (debuglevel >= 1) { -- DEBUG (1, "Writing "); -- for (i = 0; i < len; i++) -- PDEBUG (1, "%02x", ((const unsigned char*)myaddr)[i]); -- PDEBUG(1, " to %p\n", (void *) memaddr); -- } -- -- /* Fill start and end extra bytes of buffer with existing memory data. */ -- -- buffer[0] = ptrace (PTRACE_PEEKTEXT, inferior_pid, -- (PTRACE_ARG3_TYPE) addr, 0); -- -- if (count > 1) { -- buffer[count - 1] -- = ptrace (PTRACE_PEEKTEXT, inferior_pid, -- (PTRACE_ARG3_TYPE) (addr + (count - 1) -- * sizeof (PTRACE_XFER_TYPE)), -- 0); -- } -- -- /* Copy data to be written over corresponding part of buffer */ -- -- memcpy ((char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)), -- myaddr, len); -- -- /* Write the entire buffer. */ -- -- for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE)) { -- errno = 0; -- ptrace (PTRACE_POKETEXT, inferior_pid, -- (PTRACE_ARG3_TYPE) addr, buffer[i]); -- if (errno) -- return errno; -- } -- -- return 0; --} -- --/* subset of VG_(threads) needed for vgdb ptrace. -- This is initialized when process is attached. */ --typedef struct { -- ThreadStatus status; -- Int lwpid; --} --VgdbThreadState; --static VgdbThreadState vgdb_threads[VG_N_THREADS]; -- --static const --HChar* name_of_ThreadStatus ( ThreadStatus status ) --{ -- switch (status) { -- case VgTs_Empty: return "VgTs_Empty"; -- case VgTs_Init: return "VgTs_Init"; -- case VgTs_Runnable: return "VgTs_Runnable"; -- case VgTs_WaitSys: return "VgTs_WaitSys"; -- case VgTs_Yielding: return "VgTs_Yielding"; -- case VgTs_Zombie: return "VgTs_Zombie"; -- default: return "VgTs_???"; -- } --} -- --static --char *status_image (int status) --{ -- static char result[256]; -- int sz = 0; --#define APPEND(...) sz += snprintf (result+sz, 256 - sz - 1, __VA_ARGS__) -- -- result[0] = 0; -- -- if (WIFEXITED(status)) -- APPEND ("WIFEXITED %d ", WEXITSTATUS(status)); -- -- if (WIFSIGNALED(status)) { -- APPEND ("WIFSIGNALED %d ", WTERMSIG(status)); -- if (WCOREDUMP(status)) APPEND ("WCOREDUMP "); -- } -- -- if (WIFSTOPPED(status)) -- APPEND ("WIFSTOPPED %d ", WSTOPSIG(status)); -- --#ifdef WIFCONTINUED -- if (WIFCONTINUED(status)) -- APPEND ("WIFCONTINUED "); --#endif -- -- return result; --#undef APPEND --} -- --/* Wait till the process pid is reported as stopped with signal_expected. -- If other signal(s) than signal_expected are received, waitstopped -- will pass them to pid, waiting for signal_expected to stop pid. -- Returns True when process is in stopped state with signal_expected. -- Returns False if a problem was encountered while waiting for pid -- to be stopped. -- -- If pid is reported as being dead/exited, waitstopped will return False. --*/ --static --Bool waitstopped (int pid, int signal_expected, const char *msg) --{ -- pid_t p; -- int status = 0; -- int signal_received; -- int res; -- -- while (1) { -- DEBUG(1, "waitstopped %s before waitpid signal_expected %d\n", -- msg, signal_expected); -- p = waitpid(pid, &status, __WALL); -- DEBUG(1, "after waitpid pid %d p %d status 0x%x %s\n", pid, p, -- status, status_image (status)); -- if (p != pid) { -- ERROR(errno, "%s waitpid pid %d in waitstopped %d status 0x%x %s\n", -- msg, pid, p, status, status_image (status)); -- return False; -- } -- -- if (WIFEXITED(status)) { -- shutting_down = True; -- return False; -- } -- -- assert (WIFSTOPPED(status)); -- signal_received = WSTOPSIG(status); -- if (signal_received == signal_expected) -- break; -- -- /* pid received a signal which is not the signal we are waiting for. -- We continue pid, transmitting this signal. */ -- DEBUG(1, "waitstopped PTRACE_CONT with signal %d\n", signal_received); -- res = ptrace (PTRACE_CONT, pid, NULL, signal_received); -- if (res != 0) { -- ERROR(errno, "waitstopped PTRACE_CONT\n"); -- return False; -- } -- } -- -- return True; --} -- --/* Stops the given pid, wait for the process to be stopped. -- Returns True if succesful, False otherwise. -- msg is used in tracing and error reporting. */ --static --Bool stop (int pid, const char *msg) --{ -- long res; -- -- DEBUG(1, "%s SIGSTOP pid %d\n", msg, pid); -- res = kill (pid, SIGSTOP); -- if (res != 0) { -- ERROR(errno, "%s SIGSTOP pid %d %ld\n", msg, pid, res); -- return False; -- } -- -- return waitstopped (pid, SIGSTOP, msg); -- --} -- --/* Attaches to given pid, wait for the process to be stopped. -- Returns True if succesful, False otherwise. -- msg is used in tracing and error reporting. */ --static --Bool attach (int pid, const char *msg) --{ -- long res; -- static Bool output_error = True; -- static Bool initial_attach = True; -- // For a ptrace_scope protected system, we do not want to output -- // repetitively attach error. We will output once an error -- // for the initial_attach. Once the 1st attach has succeeded, we -- // again show all errors. -- -- DEBUG(1, "%s PTRACE_ATTACH pid %d\n", msg, pid); -- res = ptrace (PTRACE_ATTACH, pid, NULL, NULL); -- if (res != 0) { -- if (output_error || debuglevel > 0) { -- ERROR(errno, "%s PTRACE_ATTACH pid %d %ld\n", msg, pid, res); -- if (initial_attach) -- output_error = False; -- } -- return False; -- } -- -- initial_attach = False; -- output_error = True; -- return waitstopped(pid, SIGSTOP, msg); --} -- --/* once we are attached to the pid, get the list of threads and stop -- them all. -- Returns True if all threads properly suspended, False otherwise. */ --static --Bool acquire_and_suspend_threads(int pid) --{ -- int i; -- int rw; -- Bool pid_found = False; -- Addr vgt; -- int sz_tst; -- int off_status; -- int off_lwpid; -- int nr_live_threads = 0; -- -- if (shared32 != NULL) { -- vgt = shared32->threads; -- sz_tst = shared32->sizeof_ThreadState; -- off_status = shared32->offset_status; -- off_lwpid = shared32->offset_lwpid; -- } -- else if (shared64 != NULL) { -- vgt = shared64->threads; -- sz_tst = shared64->sizeof_ThreadState; -- off_status = shared64->offset_status; -- off_lwpid = shared64->offset_lwpid; -- } else { -- assert (0); -- } -- -- /* note: the entry 0 is unused */ -- for (i = 1; i < VG_N_THREADS; i++) { -- vgt += sz_tst; -- rw = ptrace_read_memory(pid, vgt+off_status, -- &(vgdb_threads[i].status), -- sizeof(ThreadStatus)); -- if (rw != 0) { -- ERROR(rw, "status ptrace_read_memory\n"); -- return False; -- } -- -- rw = ptrace_read_memory(pid, vgt+off_lwpid, -- &(vgdb_threads[i].lwpid), -- sizeof(Int)); -- if (rw != 0) { -- ERROR(rw, "lwpid ptrace_read_memory\n"); -- return False; -- } -- -- if (vgdb_threads[i].status != VgTs_Empty) { -- DEBUG(1, "found tid %d status %s lwpid %d\n", -- i, name_of_ThreadStatus(vgdb_threads[i].status), -- vgdb_threads[i].lwpid); -- nr_live_threads++; -- if (vgdb_threads[i].lwpid <= 1) { -- if (vgdb_threads[i].lwpid == 0 -- && vgdb_threads[i].status == VgTs_Init) { -- DEBUG(1, "not set lwpid tid %d status %s lwpid %d\n", -- i, name_of_ThreadStatus(vgdb_threads[i].status), -- vgdb_threads[i].lwpid); -- } else { -- ERROR(1, "unexpected lwpid tid %d status %s lwpid %d\n", -- i, name_of_ThreadStatus(vgdb_threads[i].status), -- vgdb_threads[i].lwpid); -- } -- /* in case we have a VtTs_Init thread with lwpid not yet set, -- we try again later. */ -- return False; -- } -- if (vgdb_threads[i].lwpid == pid) { -- assert (!pid_found); -- assert (i == 1); -- pid_found = True; -- } else { -- if (!attach(vgdb_threads[i].lwpid, "attach_thread")) { -- ERROR(0, "ERROR attach pid %d tid %d\n", -- vgdb_threads[i].lwpid, i); -- return False; -- } -- } -- } -- } -- /* If we found no thread, it means the process is stopping, and -- we better do not force anything to happen during that. */ -- if (nr_live_threads > 0) -- return True; -- else -- return False; --} -- --static --void detach_from_all_threads(int pid) --{ -- int i; -- long res; -- Bool pid_found = False; -- -- /* detach from all the threads */ -- for (i = 1; i < VG_N_THREADS; i++) { -- if (vgdb_threads[i].status != VgTs_Empty) { -- if (vgdb_threads[i].status == VgTs_Init -- && vgdb_threads[i].lwpid == 0) { -- DEBUG(1, "skipping PTRACE_DETACH pid %d tid %d status %s\n", -- vgdb_threads[i].lwpid, i, -- name_of_ThreadStatus (vgdb_threads[i].status)); -- } else { -- if (vgdb_threads[i].lwpid == pid) { -- assert (!pid_found); -- pid_found = True; -- } -- DEBUG(1, "PTRACE_DETACH pid %d tid %d status %s\n", -- vgdb_threads[i].lwpid, i, -- name_of_ThreadStatus (vgdb_threads[i].status)); -- res = ptrace (PTRACE_DETACH, vgdb_threads[i].lwpid, NULL, NULL); -- if (res != 0) { -- ERROR(errno, "PTRACE_DETACH pid %d tid %d status %s res %ld\n", -- vgdb_threads[i].lwpid, i, -- name_of_ThreadStatus (vgdb_threads[i].status), -- res); -- } -- } -- } -- } -- -- if (!pid_found && pid) { -- /* No threads are live. Process is busy stopping. -- We need to detach from pid explicitely. */ -- DEBUG(1, "no thread live => PTRACE_DETACH pid %d\n", pid); -- res = ptrace (PTRACE_DETACH, pid, NULL, NULL); -- if (res != 0) -- ERROR(errno, "PTRACE_DETACH pid %d res %ld\n", pid, res); -- } --} -- --// if > 0, pid for which registers have to be restored. --static int pid_of_save_regs = 0; --static struct user user_save; -- --// The below indicates if ptrace_getregs (and ptrace_setregs) can be used. --// Note that some linux versions are defining PTRACE_GETREGS but using --// it gives back EIO. --// has_working_ptrace_getregs can take the following values: --// -1 : PTRACE_GETREGS is defined --// runtime check not yet done. --// 0 : PTRACE_GETREGS runtime check has failed. --// 1 : PTRACE_GETREGS defined and runtime check ok. --#ifdef HAVE_PTRACE_GETREGS --static int has_working_ptrace_getregs = -1; --#endif -- --/* Get the registers from pid into regs. -- regs_bsz value gives the length of *regs. -- Returns True if all ok, otherwise False. */ --static --Bool getregs (int pid, void *regs, long regs_bsz) --{ -- DEBUG(1, "getregs regs_bsz %ld\n", regs_bsz); --# ifdef HAVE_PTRACE_GETREGS -- if (has_working_ptrace_getregs) { -- // Platforms having GETREGS -- long res; -- DEBUG(1, "getregs PTRACE_GETREGS\n"); -- res = ptrace (PTRACE_GETREGS, pid, NULL, regs); -- if (res == 0) { -- if (has_working_ptrace_getregs == -1) { -- // First call to PTRACE_GETREGS succesful => -- has_working_ptrace_getregs = 1; -- DEBUG(1, "detected a working PTRACE_GETREGS\n"); -- } -- assert (has_working_ptrace_getregs == 1); -- return True; -- } -- else if (has_working_ptrace_getregs == 1) { -- // We had a working call, but now it fails. -- // This is unexpected. -- ERROR(errno, "PTRACE_GETREGS %ld\n", res); -- return False; -- } else { -- // Check this is the first call: -- assert (has_working_ptrace_getregs == -1); -- if (errno == EIO) { -- DEBUG(1, "detected a broken PTRACE_GETREGS with EIO\n"); -- has_working_ptrace_getregs = 0; -- // Fall over to the PTRACE_PEEKUSER case. -- } else { -- ERROR(errno, "broken PTRACE_GETREGS unexpected errno %ld\n", res); -- return False; -- } -- } -- } --# endif -- -- // We assume PTRACE_PEEKUSER is defined everywhere. -- { --# ifdef PT_ENDREGS -- long peek_bsz = PT_ENDREGS; -- assert (peek_bsz <= regs_bsz); --# else -- long peek_bsz = regs_bsz-1; --# endif -- char *pregs = (char *) regs; -- long offset; -- errno = 0; -- DEBUG(1, "getregs PTRACE_PEEKUSER(s) peek_bsz %ld\n", peek_bsz); -- for (offset = 0; offset < peek_bsz; offset = offset + sizeof(long)) { -- *(long *)(pregs+offset) = ptrace(PTRACE_PEEKUSER, pid, offset, NULL); -- if (errno != 0) { -- ERROR(errno, "PTRACE_PEEKUSER offset %ld\n", offset); -- return False; -- } -- } -- return True; -- } -- -- // If neither PTRACE_GETREGS not PTRACE_PEEKUSER have returned, -- // then we are in serious trouble. -- assert (0); --} -- --/* Set the registers of pid to regs. -- regs_bsz value gives the length of *regs. -- Returns True if all ok, otherwise False. */ --static --Bool setregs (int pid, void *regs, long regs_bsz) --{ -- DEBUG(1, "setregs regs_bsz %ld\n", regs_bsz); --// Note : the below is checking for GETREGS, not SETREGS --// as if one is defined and working, the other one should also work. --# ifdef HAVE_PTRACE_GETREGS -- if (has_working_ptrace_getregs) { -- // Platforms having SETREGS -- long res; -- // setregs can never be called before getregs has done a runtime check. -- assert (has_working_ptrace_getregs == 1); -- DEBUG(1, "setregs PTRACE_SETREGS\n"); -- res = ptrace (PTRACE_SETREGS, pid, NULL, regs); -- if (res != 0) { -- ERROR(errno, "PTRACE_SETREGS %ld\n", res); -- return False; -- } -- return True; -- } --# endif -- -- { -- char *pregs = (char *) regs; -- long offset; -- long res; --# ifdef PT_ENDREGS -- long peek_bsz = PT_ENDREGS; -- assert (peek_bsz <= regs_bsz); --# else -- long peek_bsz = regs_bsz-1; --# endif -- errno = 0; -- DEBUG(1, "setregs PTRACE_POKEUSER(s) %ld\n", peek_bsz); -- for (offset = 0; offset < peek_bsz; offset = offset + sizeof(long)) { -- res = ptrace(PTRACE_POKEUSER, pid, offset, *(long*)(pregs+offset)); -- if (errno != 0) { -- ERROR(errno, "PTRACE_POKEUSER offset %ld res %ld\n", offset, res); -- return False; -- } -- } -- return True; -- } -- -- // If neither PTRACE_SETREGS not PTRACE_POKEUSER have returned, -- // then we are in serious trouble. -- assert (0); --} -- --/* Restore the registers to the saved value, then detaches from all threads */ --static --void restore_and_detach(int pid) --{ -- if (pid_of_save_regs) { -- /* In case the 'main pid' has been continued, we need to stop it -- before resetting the registers. */ -- if (pid_of_save_regs_continued) { -- pid_of_save_regs_continued = False; -- if (!stop(pid_of_save_regs, "sigstop before reset regs")) -- DEBUG(0, "Could not sigstop before reset"); -- } -- -- DEBUG(1, "setregs restore registers pid %d\n", pid_of_save_regs); -- if (!setregs(pid_of_save_regs, &user_save.regs, sizeof(user_save.regs))) { -- ERROR(errno, "setregs restore registers pid %d after cont\n", -- pid_of_save_regs); -- } -- pid_of_save_regs = 0; -- } else { -- DEBUG(1, "PTRACE_SETREGS restore registers: no pid\n"); -- } -- detach_from_all_threads(pid); --} -- --/* Ensures that the gdbserver code is invoked by pid. -- If an error occurs, resets to the valgrind process -- to the state it has before being ptrace-d. -- Returns True if invoke successful, False otherwise. --*/ --static --Bool invoke_gdbserver (int pid) --{ -- static Bool ptrace_restrictions_msg_given = False; -- long res; -- Bool stopped; -- struct user user_mod; -- Addr sp; -- /* A specific int value is passed to invoke_gdbserver, to check -- everything goes according to the plan. */ -- const int check = 0x8BADF00D; // ate bad food. -- -- const Addr bad_return = 0; -- // A bad return address will be pushed on the stack. -- // The function invoke_gdbserver cannot return. If ever it returns, a NULL -- // address pushed on the stack should ensure this is detected. -- -- /* Not yet attached. If problem, vgdb can abort, -- no cleanup needed. */ -- -- DEBUG(1, "attach to 'main' pid %d\n", pid); -- if (!attach(pid, "attach main pid")) { -- if (!ptrace_restrictions_msg_given) { -- ptrace_restrictions_msg_given = True; -- ERROR(0, "error attach main pid %d\n", pid); -- ptrace_restrictions_msg(); -- } -- return False; -- } -- -- /* Now, we are attached. If problem, detach and return. */ -- -- if (!acquire_and_suspend_threads(pid)) { -- detach_from_all_threads(pid); -- /* if the pid does not exist anymore, we better stop */ -- if (kill(pid, 0) != 0) -- XERROR (errno, "invoke_gdbserver: check for pid %d existence failed\n", -- pid); -- return False; -- } -- -- if (!getregs(pid, &user_mod.regs, sizeof(user_mod.regs))) { -- detach_from_all_threads(pid); -- return False; -- } -- user_save = user_mod; -- --#if defined(VGA_x86) -- sp = user_mod.regs.esp; --#elif defined(VGA_amd64) -- sp = user_mod.regs.rsp; -- if (shared32 != NULL) { -- /* 64bit vgdb speaking with a 32bit executable. -- To have system call restart properly, we need to sign extend rax. -- For more info: -- web search '[patch] Fix syscall restarts for amd64->i386 biarch' -- e.g. http://sourceware.org/ml/gdb-patches/2009-11/msg00592.html */ -- *(long *)&user_save.regs.rax = *(int*)&user_save.regs.rax; -- DEBUG(1, "Sign extending %8.8lx to %8.8lx\n", -- user_mod.regs.rax, user_save.regs.rax); -- } --#elif defined(VGA_arm) -- sp = user_mod.regs.uregs[13]; --#elif defined(VGA_ppc32) -- sp = user_mod.regs.gpr[1]; --#elif defined(VGA_ppc64) -- sp = user_mod.regs.gpr[1]; --#elif defined(VGA_s390x) -- sp = user_mod.regs.gprs[15]; --#elif defined(VGA_mips32) -- long long *p = (long long *)user_mod.regs; -- sp = p[29]; --#elif defined(VGA_mips64) -- sp = user_mod.regs[29]; --#else -- I_die_here : (sp) architecture missing in vgdb.c --#endif -- -- -- // the magic below is derived from spying what gdb sends to -- // the (classical) gdbserver when invoking a C function. -- if (shared32 != NULL) { -- // vgdb speaking with a 32bit executable. --#if defined(VGA_x86) || defined(VGA_amd64) -- const int regsize = 4; -- int rw; -- /* push check arg on the stack */ -- sp = sp - regsize; -- DEBUG(1, "push check arg ptrace_write_memory\n"); -- assert(regsize == sizeof(check)); -- rw = ptrace_write_memory(pid, sp, -- &check, -- regsize); -- if (rw != 0) { -- ERROR(rw, "push check arg ptrace_write_memory"); -- detach_from_all_threads(pid); -- return False; -- } -- -- sp = sp - regsize; -- DEBUG(1, "push bad_return return address ptrace_write_memory\n"); -- // Note that for a 64 bits vgdb, only 4 bytes of NULL bad_return -- // are written. -- rw = ptrace_write_memory(pid, sp, -- &bad_return, -- regsize); -- if (rw != 0) { -- ERROR(rw, "push bad_return return address ptrace_write_memory"); -- detach_from_all_threads(pid); -- return False; -- } --#if defined(VGA_x86) -- /* set ebp, esp, eip and orig_eax to invoke gdbserver */ -- // compiled in 32bits, speaking with a 32bits exe -- user_mod.regs.ebp = sp; // bp set to sp -- user_mod.regs.esp = sp; -- user_mod.regs.eip = shared32->invoke_gdbserver; -- user_mod.regs.orig_eax = -1L; --#elif defined(VGA_amd64) -- /* set ebp, esp, eip and orig_eax to invoke gdbserver */ -- // compiled in 64bits, speaking with a 32bits exe -- user_mod.regs.rbp = sp; // bp set to sp -- user_mod.regs.rsp = sp; -- user_mod.regs.rip = shared32->invoke_gdbserver; -- user_mod.regs.orig_rax = -1L; --#else -- I_die_here : not x86 or amd64 in x86/amd64 section/ --#endif -- --#elif defined(VGA_ppc32) || defined(VGA_ppc64) -- user_mod.regs.nip = shared32->invoke_gdbserver; -- user_mod.regs.trap = -1L; -- /* put check arg in register 3 */ -- user_mod.regs.gpr[3] = check; -- /* put NULL return address in Link Register */ -- user_mod.regs.link = bad_return; -- --#elif defined(VGA_arm) -- /* put check arg in register 0 */ -- user_mod.regs.uregs[0] = check; -- /* put NULL return address in Link Register */ -- user_mod.regs.uregs[14] = bad_return; -- user_mod.regs.uregs[15] = shared32->invoke_gdbserver; -- --#elif defined(VGA_s390x) -- XERROR(0, "(fn32) s390x has no 32bits implementation"); --#elif defined(VGA_mips32) -- /* put check arg in register 4 */ -- p[4] = check; -- /* put NULL return address in ra */ -- p[31] = bad_return; -- p[34] = shared32->invoke_gdbserver; -- p[25] = shared32->invoke_gdbserver; -- /* make stack space for args */ -- p[29] = sp - 32; -- --#elif defined(VGA_mips64) -- assert(0); // cannot vgdb a 32 bits executable with a 64 bits exe --#else -- I_die_here : architecture missing in vgdb.c --#endif -- } -- -- else if (shared64 != NULL) { --#if defined(VGA_x86) -- assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe --#elif defined(VGA_amd64) -- // vgdb speaking with a 64 bit executable. -- const int regsize = 8; -- int rw; -- -- /* give check arg in rdi */ -- user_mod.regs.rdi = check; -- -- /* push return address on stack : return to breakaddr */ -- sp = sp - regsize; -- DEBUG(1, "push bad_return return address ptrace_write_memory\n"); -- rw = ptrace_write_memory(pid, sp, -- &bad_return, -- sizeof(bad_return)); -- if (rw != 0) { -- ERROR(rw, "push bad_return return address ptrace_write_memory"); -- detach_from_all_threads(pid); -- return False; -- } -- -- /* set rbp, rsp, rip and orig_rax to invoke gdbserver */ -- user_mod.regs.rbp = sp; // bp set to sp -- user_mod.regs.rsp = sp; -- user_mod.regs.rip = shared64->invoke_gdbserver; -- user_mod.regs.orig_rax = -1L; -- --#elif defined(VGA_arm) -- assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe --#elif defined(VGA_ppc32) -- assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe --#elif defined(VGA_ppc64) -- Addr64 func_addr; -- Addr64 toc_addr; -- int rw; -- rw = ptrace_read_memory(pid, shared64->invoke_gdbserver, -- &func_addr, -- sizeof(Addr64)); -- if (rw != 0) { -- ERROR(rw, "ppc64 read func_addr\n"); -- detach_from_all_threads(pid); -- return False; -- } -- rw = ptrace_read_memory(pid, shared64->invoke_gdbserver+8, -- &toc_addr, -- sizeof(Addr64)); -- if (rw != 0) { -- ERROR(rw, "ppc64 read toc_addr\n"); -- detach_from_all_threads(pid); -- return False; -- } -- // We are not pushing anything on the stack, so it is not -- // very clear why the sp has to be decreased, but it seems -- // needed. The ppc64 ABI might give some lights on this ? -- user_mod.regs.gpr[1] = sp - 220; -- user_mod.regs.gpr[2] = toc_addr; -- user_mod.regs.nip = func_addr; -- user_mod.regs.trap = -1L; -- /* put check arg in register 3 */ -- user_mod.regs.gpr[3] = check; -- /* put bad_return return address in Link Register */ -- user_mod.regs.link = bad_return; --#elif defined(VGA_s390x) -- /* put check arg in register r2 */ -- user_mod.regs.gprs[2] = check; -- /* bad_return Return address is in r14 */ -- user_mod.regs.gprs[14] = bad_return; -- /* minimum stack frame */ -- sp = sp - 160; -- user_mod.regs.gprs[15] = sp; -- /* set program counter */ -- user_mod.regs.psw.addr = shared64->invoke_gdbserver; --#elif defined(VGA_mips32) -- assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe --#elif defined(VGA_mips64) -- /* put check arg in register 4 */ -- user_mod.regs[4] = check; -- /* put NULL return address in ra */ -- user_mod.regs[31] = bad_return; -- user_mod.regs[34] = shared64->invoke_gdbserver; -- user_mod.regs[25] = shared64->invoke_gdbserver; --#else -- I_die_here: architecture missing in vgdb.c --#endif -- } -- else { -- assert(0); -- } -- -- if (!setregs(pid, &user_mod.regs, sizeof(user_mod.regs))) { -- detach_from_all_threads(pid); -- return False; -- } -- /* Now that we have modified the registers, we set -- pid_of_save_regs to indicate that restore_and_detach -- must restore the registers in case of cleanup. */ -- pid_of_save_regs = pid; -- pid_of_save_regs_continued = False; -- -- -- /* We PTRACE_CONT-inue pid. -- Either gdbserver will be invoked directly (if all -- threads are interruptible) or gdbserver will be -- called soon by the scheduler. In the first case, -- pid will stop on the break inserted above when -- gdbserver returns. In the 2nd case, the break will -- be encountered directly. */ -- DEBUG(1, "PTRACE_CONT to invoke\n"); -- res = ptrace (PTRACE_CONT, pid, NULL, NULL); -- if (res != 0) { -- ERROR(errno, "PTRACE_CONT\n"); -- restore_and_detach(pid); -- return False; -- } -- pid_of_save_regs_continued = True; -- /* Wait for SIGSTOP generated by m_gdbserver.c give_control_back_to_vgdb */ -- stopped = waitstopped (pid, SIGSTOP, -- "waitpid status after PTRACE_CONT to invoke"); -- if (stopped) { -- /* Here pid has properly stopped on the break. */ -- pid_of_save_regs_continued = False; -- restore_and_detach(pid); -- return True; -- } else { -- /* Whatever kind of problem happened. We shutdown */ -- shutting_down = True; -- return False; -- } --} --#endif -- --static --void cleanup_restore_and_detach(void *v_pid) --{ -- DEBUG(1, "cleanup_restore_and_detach dying: %d\n", dying); --#ifdef PTRACEINVOKER -- if (!dying) -- restore_and_detach(*(int*)v_pid); --#endif --} -- - /* This function loops till shutting_down becomes true. In this loop, - it verifies if valgrind process is reading the characters written - by vgdb. The verification is done every max_invoke_ms ms. If -- valgrind is not reading characters, it will use invoke_gdbserver -- (if PTRACE_INVOKER is defined) to ensure that the gdbserver code is -- called soon by valgrind. */ -+ valgrind is not reading characters, it will use invoker_invoke_gdbserver -+ to ensure that the gdbserver code is called soon by valgrind. */ - static int max_invoke_ms = 100; - #define NEVER 99999999 - static int cmd_time_out = NEVER; -@@ -1175,7 +221,7 @@ - int invoked_written = -1; - unsigned int usecs; - -- pthread_cleanup_push(cleanup_restore_and_detach, v_pid); -+ pthread_cleanup_push(invoker_cleanup_restore_and_detach, v_pid); - - while (!shutting_down) { - written_by_vgdb_before_sleep = VS_written_by_vgdb; -@@ -1240,19 +286,15 @@ - pid, cmd_time_out); - } - if (max_invoke_ms > 0 && timercmp (&now, &invoke_time, >=)) { -- #if defined(PTRACEINVOKER) - /* only need to wake up if the nr written has changed since - last invoke. */ - if (invoked_written != written_by_vgdb_before_sleep) { -- if (invoke_gdbserver(pid)) { -+ if (invoker_invoke_gdbserver(pid)) { - /* If invoke succesful, no need to invoke again - for the same value of written_by_vgdb_before_sleep. */ - invoked_written = written_by_vgdb_before_sleep; - } - } -- #else -- DEBUG(2, "invoke_gdbserver via ptrace not (yet) implemented\n"); -- #endif - } - } else { - // Something happened => restart timer check. -@@ -1643,9 +685,10 @@ - sigpipe++; - } else if (signum == SIGALRM) { - sigalrm++; --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* Android has no pthread_cancel. As it also does not have -- PTRACE_INVOKER, there is no need for cleanup action. -+ an invoker implementation, there is no need for cleanup action. - So, we just do nothing. */ - DEBUG(1, "sigalrm received, no action on android\n"); - #else -@@ -1849,19 +892,19 @@ - if (pollfds[ck].revents & POLLERR) { - DEBUG(1, "connection %s fd %d POLLERR error condition\n", - ppConnectionKind(ck), pollfds[ck].fd); -- valgrind_dying(); -+ invoker_valgrind_dying(); - shutting_down = True; - } - if (pollfds[ck].revents & POLLHUP) { - DEBUG(1, "connection %s fd %d POLLHUP error condition\n", - ppConnectionKind(ck), pollfds[ck].fd); -- valgrind_dying(); -+ invoker_valgrind_dying(); - shutting_down = True; - } - if (pollfds[ck].revents & POLLNVAL) { - DEBUG(1, "connection %s fd %d POLLNVAL error condition\n", - ppConnectionKind(ck), pollfds[ck].fd); -- valgrind_dying(); -+ invoker_valgrind_dying(); - shutting_down = True; - } - } -@@ -1950,7 +993,7 @@ - if (buflen < 0) { - ERROR (0, "error reading packet\n"); - if (buflen == -2) -- valgrind_dying(); -+ invoker_valgrind_dying(); - break; - } - if (strlen(buf) == 0) { -@@ -2033,20 +1076,7 @@ - fflush((on_stdout ? stdout : stderr)); - } - --/* Possibly produces additional usage information documenting the -- ptrace restrictions. */ - static --void ptrace_restrictions_msg(void) --{ --# ifndef PTRACEINVOKER -- fprintf(stderr, -- "Note: ptrace invoker not implemented\n" -- "For more info: read user manual section" -- " 'Limitations of the Valgrind gdbserver'\n"); --# endif --} -- --static - void usage(void) - { - fprintf(stderr, -@@ -2083,7 +1113,7 @@ - " To get help from the Valgrind gdbserver, use vgdb help\n" - "\n", vgdb_prefix_default() - ); -- ptrace_restrictions_msg(); -+ invoker_restrictions_msg(); - } - - /* If show_list, outputs on stdout the list of Valgrind processes with gdbserver activated. -Index: coregrind/vgdb.h -=================================================================== ---- coregrind/vgdb.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ coregrind/vgdb.h (.../trunk) (revision 13981) -@@ -0,0 +1,108 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Declarations common for vgdb and implementations ---*/ -+/*--- of vgdb-invoker. vgdb.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2011-2013 Philippe Waroquiers -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VGDB_H -+#define __VGDB_H -+ -+#include "pub_core_basics.h" -+#include "pub_core_vki.h" -+#include "pub_core_gdbserver.h" -+ -+#include -+ -+extern int debuglevel; -+extern struct timeval dbgtv; -+/* if level <= debuglevel, print timestamp, then print provided by debug info */ -+#define DEBUG(level, ...) (level <= debuglevel ? \ -+ gettimeofday(&dbgtv, NULL), \ -+ fprintf(stderr, "%ld.%6.6ld ", \ -+ (long int)dbgtv.tv_sec, \ -+ (long int)dbgtv.tv_usec), \ -+ fprintf(stderr, __VA_ARGS__),fflush(stderr) \ -+ : 0) -+ -+/* same as DEBUG but does not print time stamp info */ -+#define PDEBUG(level, ...) (level <= debuglevel ? \ -+ fprintf(stderr, __VA_ARGS__),fflush(stderr) \ -+ : 0) -+ -+/* if errno != 0, -+ report the errno and fprintf the ... varargs on stderr. */ -+#define ERROR(errno, ...) ((errno == 0 ? 0 : perror("syscall failed")), \ -+ fprintf(stderr, __VA_ARGS__), \ -+ fflush(stderr)) -+/* same as ERROR, but also exits with status 1 */ -+#define XERROR(errno, ...) ((errno == 0 ? 0 : perror("syscall failed")), \ -+ fprintf(stderr, __VA_ARGS__), \ -+ fflush(stderr), \ -+ exit(1)) -+ -+/* Calls malloc (size). Exits if memory can't be allocated. */ -+extern void *vmalloc(size_t size); -+/* Calls realloc (size). Exits if memory can't be allocated. */ -+extern void *vrealloc(void *ptr,size_t size); -+ -+/* Will be set to True when any condition indicating we have to shutdown -+ is encountered. */ -+extern Bool shutting_down; -+ -+extern VgdbShared32 *shared32; -+extern VgdbShared64 *shared64; -+ -+/*--------------------------------------------------------------------*/ -+/*--- Below is vgdb-invoker interface which must be implemented by ---*/ -+/*--- all vgdb-invoker implementations. ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* Possibly produces additional usage information documenting the -+ invoker restrictions. */ -+void invoker_restrictions_msg(void); -+ -+/* Restore the registers to the saved value, then detaches from all threads. -+ Used as a cleanup handler for thread cancellation. */ -+void invoker_cleanup_restore_and_detach(void *v_pid); -+ -+/* Ensures that the gdbserver code is invoked by pid. -+ If an error occurs, resets the valgrind process -+ to the state it had before being invoked. -+ Returns True if invoke successful, False otherwise. */ -+Bool invoker_invoke_gdbserver(pid_t pid); -+ -+/* Called when connection with valgrind is lost. In case we -+ have lost the connection, it means that Valgrind has closed the -+ connection and is busy exiting. We can't and don't have to stop it in -+ this case. */ -+void invoker_valgrind_dying(void); -+ -+#endif // __VGDB_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: docs/Makefile.am -=================================================================== ---- docs/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ docs/Makefile.am (.../trunk) (revision 13981) -@@ -27,6 +27,7 @@ - internals/3_5_BUGSTATUS.txt \ - internals/3_7_BUGSTATUS.txt \ - internals/3_8_BUGSTATUS.txt \ -+ internals/3_9_BUGSTATUS.txt \ - internals/arm_thumb_notes_gdbserver.txt \ - internals/avx-notes.txt \ - internals/BIG_APP_NOTES.txt \ -@@ -229,6 +230,7 @@ - - distclean-local: - rm -rf html print -+ rm -f FAQ.txt - rm -f $(top_builddir)/FAQ.txt $(top_builddir)/docs/*.1 - - -Index: docs/internals/3_9_BUGSTATUS.txt -=================================================================== ---- docs/internals/3_9_BUGSTATUS.txt (.../tags/VALGRIND_3_9_0) (revision 0) -+++ docs/internals/3_9_BUGSTATUS.txt (.../trunk) (revision 13981) -@@ -0,0 +1,177 @@ -+ -+Bugs reported after Thu Sep 19 10:34:49 CEST 2013 -+For bugs reported before this time, see 3_8_BUGSTATUS.txt -+ -+=== VEX/amd64 ========================================================== -+ -+325328 __float128 loses precision under memcheck -+ == 197915 -+326469 amd64->IR: 0x66 0xF 0x3A 0x63 0xC1 0xE (pcmpistri 0x0E) -+326821 Double overflow/underflow handling broken (after exp()) -+327285 amd64->IR: 0x8F 0xEA 0xF8 0x10 0xCE 0x3 0x1D 0x0 -+ == 323431 (probably amd specific, vpcmov) -+327639 vex amd64->IR pcmpestri SSE4.2 instruction is unsupported 0x34 -+328878 vex amd64->IR pcmpestri SSE4.2 instruction is unsupported 0x14 -+328357 amd64->IR: 0x8F 0xEA 0xF8 0x10 0xEF 0x3 0x5 0x0 -+329245 amd64->IR: 0x48 0xF 0x5A 0x7 (rex.W cvtps2pd (%rdi),%xmm0) -+330319 amd64->IR: 0xF 0x1 0xD5 0x31 0xC0 0xC3 0x48 0x8D (xend) -+330590 Missing support for multiple VEX CMP instruction Opcodes (Causes SIGILL) -+330808 Crash with Intel IPP samples (MMX related assertion) -+ -+=== VEX/arm ============================================================ -+ -+329963 Half precision floating point conversion on ARM is not supported -+330349 Endless loop happen when using lackey with --trace-mem=yes on ARM -+331178 disInstr(arm): unhandled instruction: 0xEE190F1D (read PMCCNTR) -+ Probably WONTFIX or CANTFIX -+ == 328423 -+ -+=== VEX/x86 ============================================================ -+ -+333625 Program under valgrind calculates complex exp() wrogly -+ -+=== VEX/mips =========================================================== -+ -+327223 Support for Cavium MIPS Octeon Atomic and Count Instructions -+328147 vex mips->IR: unhandled instruction bytes: 0x0 0x0 0x0 0xE -+ -+=== VEX/ppc ============================================================ -+ -+334384 Valgrind does not have support Little Endian support for -+ IBM POWER PPC 64 -+ -+=== VEX general ======================================================== -+ -+326026 Iop names for count leading zeros/sign bits incorrectly imply a -+ "signedness" in incoming lanes -+330887 doRegisterAllocation performance improvements -+ -+=== Syscalls/ioctls ==================================================== -+ -+330594 Missing sysalls on PowerPC / uClibc -+331311 Valgrind shows open files in /proc/self/fd that don't -+ work for the process -+ Probable wontfix -+333434 In some weird corner case Valgrind cannot execute -+ executable files symlinked by /proc/self/fd (related to 331311?) -+331476 Patch to handle ioctl 0x5422 on Linux (x86 and amd64) (landable?) -+331829 Unexpected ioctl opcode sign extension -+333051 handling hugepages (is largely broken) -+333788 Valgrind does not support the CDROM_DISC_STATUS ioctl (has patch) -+333817 Valgrind reports the memory areas written to by the SG_IO -+ ioctl as untouched -+334585 recvmmsg unhandled (+patch) (arm) -+ -+=== Debuginfo reader =================================================== -+ -+327427 ifunc wrapper crashes when symbols are discarded because of false mmap -+ overlaps -+328454 add support Backtraces with ARM unwind tables (EXIDX) (wishlist) -+328468 unwind x86/amd64 gcc <= 4.4 compiled code does not unwind properly -+ at "ret" instruction -+328559 Some back trace generation (from mmap function) problem on ARM -+330321 Serious error when reading debug info: -+ DW_AT_signature 9b d0 55 13 bb 1e e9 37 -+333175 dwarf3 reader problems with Fortran -+ -+=== Tools/Memcheck ===================================================== -+ -+329619 leak-check gets assertion failure when nesting VALGRIND_MALLOCLIKE_BLOCK -+329694 clang warns about using uninitialized variable -+330617 ppc false positive conditional jump depends on uninitialised value -+331833 the memory initialized by semget(key, 0, GETALL, semun) -+ is treated as uninitialized on some platforms -+ -+331550 Detect the potential of mis-malloc/free in different libraries -+ (wishlist) -+333775 Wishlist: Have valgrind (memcheck) only check memory -+ alloc/free traces -+ -+=== Tools/DRD ========================================================== -+ -+333072 DRD: semaphore annotations -+ -+=== Tools/Helgrind ===================================================== -+ -+325333 VALGRIND_HG_DISABLE_CHECKING does not seem to work locally -+ probably invalid -+327548 Helgrind: false positive while destroying mutex -+327881 Helgrind: False Positive Warning on std::atomic_bool -+ -+=== Tools/SGCheck ====================================================== -+ -+332577 exp-sgcheck: sg_main.c:560 (add_blocks_to_StackTree): -+ Assertion '!already_present' failed. -+332591 False positive: invalid read in vfprintf (KNOWN BUG) -+ -+=== Tools/Massif ======================================================= -+ -+332765 ms_print reports bad error if temp file can't be created -+ in current directory -+ -+=== Tools/Cachegrind =================================================== -+ -+333501 [cachegrind - 3.9] LL cache configuration not supported: -+ Cache set count is not a power of two. -+ -+=== other/mips ========================================================= -+ -+325538 cavim octeon mips64, valgrind reported "dumping core" and -+ "Assertion 'sizeof(*regs) == sizeof(prs->pr_reg)' failed. -+ QUERIED, maybe closable -+328441 valgrind_3.9.0 failed to compile in mips32 -+ Error: illegal operands `cfc1 $t0,$31' -+331126 Compiling with mipsbe toolchain -+331314 [MIPS]Valgrind crash just after startup -+334649 Cavium Octeon 2 MIPS64: valgrind is up but ld.so assert -+ "rtld.c: 1257: dl_main: Assertion -+ '_rtld_local._dl_rtld_map.l_relocated' failed" and exits -+ -+=== other/arm ========================================================== -+ -+327583 libpixman error on ARM system (memcheck false +) -+331033 valgrind crashes on arm-linux while running an executable (ARM TLS?) -+ -+=== other/s390 ========================================================= -+ -+327943 s390x missing index/strchr suppression for ld.so (bad backtrace?) -+ -+=== other/MacOS ======================================================== -+ -+326724 Valgrind does not compile on OSX 1.9 Mavericks -+326797 Assertion 'sizeof(UWord) == sizeof(UInt)' failed. -+327745 valgrind 3.9.0 build fails on Mac OS X 10.6.8 -+330257 LLVM does not support `-mno-dynamic-no-pic` option -+333248 WARNING: unhandled syscall: unix:443 -+ -+=== GDB server ========================================================= -+ -+328081 embedded gdbserver and non-stop mode (wishlist) -+ -+=== Output ============================================================= -+ -+328563 make track-fds support xml output -+ -+=== MPI ================================================================ -+ -+330147 libmpiwrap: byte count from PMPI_Get_count should be made defined -+ -+=== Documentation ====================================================== -+ -+332060 Please document how best to use massif with libgc -+332917 Valgrind should warn the user that SSE4 is not supported -+ in the 32-bit mode -+ -+=== Uncategorised ====================================================== -+ -+326487 child of debugged process exits without becoming zombie -+327665 out of memory error -+328721 MSVC 2008 compiler warns about while(0) in warning level 4 -+330293 Please add a AppData application description (Valkyrie) -+333628 Out of tree build -+ == 256174 -+334110 Why install internal headers/libraries/.pc file? -+ -+======================================================================== -+======================================================================== -+ -Index: docs/internals/register-uses.txt -=================================================================== ---- docs/internals/register-uses.txt (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ docs/internals/register-uses.txt (.../trunk) (revision 13981) -@@ -134,6 +134,46 @@ - often isn't enough. - - -+arm64-linux -+~~~~~~~~~~~ -+ -+Reg Callee Arg -+Name Saves? Reg? Comment Vex-uses? -+--------------------------------------------------------------- -+r0 int#0 ret#0 (??) -+r1 int#1 ret#1 (??) -+r2-7 int#2..7 -+r8 "Indirect res loc reg" -+r9 "Temporary regs" chaining scratch -+r10-15 "Temporary regs" avail -+r16(IP0) -+r17(IP1) -+r18 "Platform reg" -+r19-20 "Temporary regs" -+r21 y "Callee saved" GSP -+r22-28 y "Callee saved" -+r29(FP) y -+r30(LR) y -+ -+NZCV "Status register" -+ -+Is there a TLS register? -+ -+x21 is the GSP. x9 is a scratch chaining/spill temp. Neither -+are available to the register allocator. -+ -+Q registers: -+It's a little awkward. Basically, D registers are the same as ARM, -+so d0-d7 and d16-d31 are caller-saved, but d8-d15 are callee-saved. -+ -+Q registers are the same, except that the upper 64 bits of q8-q15 -+are caller-saved. -+ -+The idea is that you only need to preserve D registers, not Q -+registers. -+ -+ -+ - s390x-linux - ~~~~~~~~~~~ - -Index: docs/xml/manual-core-adv.xml -=================================================================== ---- docs/xml/manual-core-adv.xml (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ docs/xml/manual-core-adv.xml (.../trunk) (revision 13981) -@@ -603,6 +603,9 @@ - - - -+ -+ -+ - - - -@@ -1264,6 +1267,7 @@ - This section describes the Valgrind monitor commands, available - regardless of the Valgrind tool selected. For the tool specific - commands, refer to , -+, - and - . - -@@ -1293,6 +1297,32 @@ - - - -+ v.info location <addr> outputs -+ information about the location <addr>. Possibly, the -+ following are described: global variables, local (stack) -+ variables, allocated or freed blocks, ... The information -+ produced depends on the tool and on the options given to valgrind. -+ Some tools (e.g. memcheck and helgrind) produce more detailed -+ information for client heap blocks. For example, these tools show -+ the stacktrace where the heap block was allocated. If a tool does -+ not replace the malloc/free/... functions, then client heap blocks -+ will not be described. Use the -+ option --read-var-info=yes to obtain more -+ detailed information about global or local (stack) variables. -+ -+ -+ -+ -+ - v.info n_errs_found [msg] shows the number of - errors found so far, the nr of errors shown so far and the current - value of the argument. The optional -@@ -1418,18 +1448,24 @@ - - - -- v.info scheduler shows the state and -- stack trace for all threads, as known by Valgrind. This allows to -- compare the stack traces produced by the Valgrind unwinder with -- the stack traces produced by GDB+Valgrind gdbserver. Pay attention -- that GDB and Valgrind scheduler status have their own thread -- numbering scheme. To make the link between the GDB thread -- number and the corresponding Valgrind scheduler thread number, -- use the GDB command info -- threads. The output of this command shows the -- GDB thread number and the valgrind 'tid'. The 'tid' is the thread number -- output by v.info scheduler. -- When using the callgrind tool, the callgrind monitor command -+ v.info scheduler shows various -+ information about threads. First, it outputs the host stack trace, -+ i.e. the Valgrind code being executed. Then, for each thread, it -+ outputs the thread state. For non terminated threads, the state is -+ followed by the guest (client) stack trace. Finally, for each -+ active thread or for each terminated thread slot not yet re-used, -+ it shows the max usage of the valgrind stack. -+ Showing the client stack traces allows to compare the stack -+ traces produced by the Valgrind unwinder with the stack traces -+ produced by GDB+Valgrind gdbserver. Pay attention that GDB and -+ Valgrind scheduler status have their own thread numbering -+ scheme. To make the link between the GDB thread number and the -+ corresponding Valgrind scheduler thread number, use the GDB -+ command info threads. The output -+ of this command shows the GDB thread number and the valgrind -+ 'tid'. The 'tid' is the thread number output -+ by v.info scheduler. When using -+ the callgrind tool, the callgrind monitor command - status outputs internal callgrind - information about the stack/call graph it maintains. - -@@ -1436,6 +1472,13 @@ - - - -+ v.info stats shows various valgrind core and -+ tool statistics. With this, Valgrind and tool statistics can -+ be examined while running, even without option . -+ -+ -+ -+ - v.set debuglog <intvalue> sets the - Valgrind debug log level to <intvalue>. This allows to - dynamically change the log level of Valgrind e.g. when a problem -@@ -1443,6 +1486,40 @@ - - - -+ v.set hostvisibility [yes*|no] The value -+ "yes" indicates to gdbserver that GDB can look at the Valgrind -+ 'host' (internal) status/memory. "no" disables this access. -+ When hostvisibility is activated, GDB can e.g. look at Valgrind -+ global variables. As an example, to examine a Valgrind global -+ variable of the memcheck tool on an x86, do the following setup: -+ -+ -+ -+ After that, variables defined in memcheck-x86-linux can be accessed, e.g. -+ -+ -+ -+ -+ - v.translate <address> - [<traceflags>] shows the translation of the block - containing address with the given -Index: docs/xml/manual-core.xml -=================================================================== ---- docs/xml/manual-core.xml (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ docs/xml/manual-core.xml (.../trunk) (revision 13981) -@@ -584,7 +584,8 @@ - - - Run the Valgrind tool called toolname, -- e.g. Memcheck, Cachegrind, etc. -+ e.g. memcheck, cachegrind, callgrind, helgrind, drd, massif, -+ lackey, none, exp-sgcheck, exp-bbv, exp-dhat, etc. - - - -@@ -777,6 +778,46 @@ - - - -+ -+ -+ -+ -+ -+ Use this option when the Valgrind gdbserver is enabled with -+ or . -+ The Valgrind gdbserver will be invoked for each error after -+ have been reported. -+ You can additionally ask the Valgrind gdbserver to be invoked -+ for other events, specified in one of the following ways: -+ -+ a comma separated list of one or more of -+ . -+ -+ The values -+ respectively indicate to -+ invoke gdbserver before your program is executed, after the -+ last instruction of your program, on Valgrind abnormal exit -+ (e.g. internal error, out of memory, ...). -+ -+ Note: and -+ will both cause Valgrind -+ gdbserver to be invoked before your program is executed. The -+ will in addition cause your -+ program to stop on all subsequent errors. -+ -+ -+ -+ to specify the complete set. -+ It is equivalent to -+ . -+ -+ -+ for the empty set. -+ -+ -+ -+ -+ - - - -@@ -851,6 +892,13 @@ - - If an is followed by any other character, it - causes an abort. -+ -+ If the file name specifies a relative file name, it is put -+ in the program's initial working directory : this is the current -+ directory when the program started its execution after the fork -+ or after the exec. If it specifies an absolute file name (ie. -+ starts with '/') then it is put there. -+ - - - -@@ -1907,7 +1955,7 @@ - between fairness and performance. For more details about the - Valgrind thread serialisation scheme and its impact on - performance and thread scheduling, see -- . -+ . - - - The value -@@ -1935,7 +1983,7 @@ - highest performance. - - -- -+ - - - -@@ -2022,6 +2070,35 @@ - - - -+ -+ -+ -+ -+ -+ To avoid potential conflicts with some system libraries, -+ Valgrind does not use the address space -+ below value, keeping it -+ reserved in case a library specifically requests memory in this -+ region. So, some "pessimistic" value is guessed by Valgrind -+ depending on the platform. On linux, by default, Valgrind avoids -+ using the first 64MB even if typically there is no conflict in -+ this complete zone. You can use the -+ option to have your memory -+ hungry application benefitting from more of this lower memory. -+ On the other hand, if you encounter a conflict, increasing -+ aspace-minaddr value might solve it. Conflicts will typically -+ manifest themselves with mmap failures in the low range of the -+ address space. The -+ provided address must be page -+ aligned and must be equal or bigger to 0x1000 (4KB). To find the -+ default value on your platform, do something such as -+ valgrind -d -d date 2>&1 | grep -i minaddr. Values lower than 0x10000 (64KB) are known to create problems -+ on some distributions. -+ -+ -+ -+ - - - -Index: drd/docs/drd-manual.xml -=================================================================== ---- drd/docs/drd-manual.xml (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/docs/drd-manual.xml (.../trunk) (revision 13981) -@@ -385,30 +385,29 @@ - - Whether to report races between accessing memory and freeing - memory. Enabling this option may cause DRD to run slightly -- slower. Notes: -- -- -- -- Don't enable this option when using custom memory allocators -- that use -- the VG_USERREQ__MALLOCLIKE_BLOCK -- and VG_USERREQ__FREELIKE_BLOCK -- because that would result in false positives. -- -- -- -- Don't enable this option when using reference-counted -- objects because that will result in false positives, even when -- that code has been annotated properly with -- ANNOTATE_HAPPENS_BEFORE -- and ANNOTATE_HAPPENS_AFTER. See -- e.g. the output of the following command for an example: -- valgrind --tool=drd --free-is-write=yes -- drd/tests/annotate_smart_pointer. -- -- -- -- -+ slower. Notes: -+ -+ -+ -+ Don't enable this option when using custom memory allocators -+ that use -+ the VG_USERREQ__MALLOCLIKE_BLOCK -+ and VG_USERREQ__FREELIKE_BLOCK -+ because that would result in false positives. -+ -+ -+ -+ Don't enable this option when using reference-counted -+ objects because that will result in false positives, even when -+ that code has been annotated properly with -+ ANNOTATE_HAPPENS_BEFORE -+ and ANNOTATE_HAPPENS_AFTER. See -+ e.g. the output of the following command for an example: -+ valgrind --tool=drd --free-is-write=yes -+ drd/tests/annotate_smart_pointer. -+ -+ -+ - - - -Index: drd/drd_bitmap.h -=================================================================== ---- drd/drd_bitmap.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_bitmap.h (.../trunk) (revision 13981) -@@ -140,7 +140,7 @@ - || defined(VGA_mips32) - #define BITS_PER_BITS_PER_UWORD 5 - #elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_s390x) \ -- || defined(VGA_mips64) -+ || defined(VGA_mips64) || defined(VGA_arm64) - #define BITS_PER_BITS_PER_UWORD 6 - #else - #error Unknown platform. -Index: drd/drd_clientreq.c -=================================================================== ---- drd/drd_clientreq.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_clientreq.c (.../trunk) (revision 13981) -@@ -81,7 +81,16 @@ - const DrdThreadId drd_tid = DRD_(thread_get_running_tid)(); - - tl_assert(vg_tid == VG_(get_running_tid())); -- tl_assert(DRD_(VgThreadIdToDrdThreadId)(vg_tid) == drd_tid); -+ tl_assert(DRD_(VgThreadIdToDrdThreadId)(vg_tid) == drd_tid -+ || (VG_USERREQ__GDB_MONITOR_COMMAND == arg[0] -+ && vg_tid == VG_INVALID_THREADID)); -+ /* Check the consistency of vg_tid and drd_tid, unless -+ vgdb has forced the invokation of a gdb monitor cmd -+ when no threads was running (i.e. all threads blocked -+ in a syscall. In such a case, vg_tid is invalid, -+ its conversion to a drd thread id gives also an invalid -+ drd thread id, but drd_tid is not invalid (probably -+ equal to the last running drd thread. */ - - switch (arg[0]) - { -@@ -501,11 +510,21 @@ - break; - - case VG_USERREQ__PRE_RWLOCK_INIT: -- DRD_(rwlock_pre_init)(arg[1], pthread_rwlock); -+ if (DRD_(thread_enter_synchr)(drd_tid) == 0) -+ DRD_(rwlock_pre_init)(arg[1], pthread_rwlock); - break; - -+ case VG_USERREQ__POST_RWLOCK_INIT: -+ DRD_(thread_leave_synchr)(drd_tid); -+ break; -+ -+ case VG_USERREQ__PRE_RWLOCK_DESTROY: -+ DRD_(thread_enter_synchr)(drd_tid); -+ break; -+ - case VG_USERREQ__POST_RWLOCK_DESTROY: -- DRD_(rwlock_post_destroy)(arg[1], pthread_rwlock); -+ if (DRD_(thread_leave_synchr)(drd_tid) == 0) -+ DRD_(rwlock_post_destroy)(arg[1], pthread_rwlock); - break; - - case VG_USERREQ__PRE_RWLOCK_RDLOCK: -Index: drd/drd_clientreq.h -=================================================================== ---- drd/drd_clientreq.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_clientreq.h (.../trunk) (revision 13981) -@@ -197,6 +197,12 @@ - - /* To notify the drd tool of a pthread_rwlock_init call. */ - VG_USERREQ__PRE_RWLOCK_INIT, -+ /* args: Addr rwlock */ -+ /* To notify the drd tool of a pthread_rwlock_init call. */ -+ VG_USERREQ__POST_RWLOCK_INIT, -+ /* args: Addr rwlock */ -+ /* To notify the drd tool of a pthread_rwlock_destroy call. */ -+ VG_USERREQ__PRE_RWLOCK_DESTROY, - /* args: Addr rwlock, RwLockT */ - /* To notify the drd tool of a pthread_rwlock_destroy call. */ - VG_USERREQ__POST_RWLOCK_DESTROY, -Index: drd/drd_load_store.c -=================================================================== ---- drd/drd_load_store.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_load_store.c (.../trunk) (revision 13981) -@@ -47,6 +47,8 @@ - #define STACK_POINTER_OFFSET OFFSET_ppc64_GPR1 - #elif defined(VGA_arm) - #define STACK_POINTER_OFFSET OFFSET_arm_R13 -+#elif defined(VGA_arm64) -+#define STACK_POINTER_OFFSET OFFSET_arm64_XSP - #elif defined(VGA_s390x) - #define STACK_POINTER_OFFSET OFFSET_s390x_r15 - #elif defined(VGA_mips32) -Index: drd/drd_main.c -=================================================================== ---- drd/drd_main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_main.c (.../trunk) (revision 13981) -@@ -160,8 +160,13 @@ - DRD_(start_tracing_address_range)(addr, addr + 1, False); - } - if (ptrace_address) { -- const Addr addr = VG_(strtoll16)(ptrace_address, 0); -- DRD_(start_tracing_address_range)(addr, addr + 1, True); -+ char *plus = VG_(strchr)(ptrace_address, '+'); -+ Addr addr, length; -+ if (plus) -+ *plus = '\0'; -+ addr = VG_(strtoll16)(ptrace_address, 0); -+ length = plus ? VG_(strtoll16)(plus + 1, 0) : 1; -+ DRD_(start_tracing_address_range)(addr, addr + length, True); - } - if (trace_barrier != -1) - DRD_(barrier_set_trace)(trace_barrier); -@@ -224,13 +229,14 @@ - " --show-stack-usage=yes|no Print stack usage at thread exit time [no].\n" - "\n" - " drd options for monitoring process behavior:\n" --" --ptrace-addr=
Trace all load and store activity for the\n" --" specified address and keep doing that even after\n" --" the memory at that address has been freed and\n" --" reallocated [off].\n" -+" --ptrace-addr=
[+] Trace all load and store activity for\n" -+" the specified address range and keep doing that\n" -+" even after the memory at that address has been\n" -+" freed and reallocated [off].\n" - " --trace-addr=
Trace all load and store activity for the\n" - " specified address [off].\n" --" --trace-alloc=yes|no Trace all memory allocations and deallocations\n"" [no].\n" -+" --trace-alloc=yes|no Trace all memory allocations and deallocations\n" -+" [no].\n" - " --trace-barrier=yes|no Trace all barrier activity [no].\n" - " --trace-cond=yes|no Trace all condition variable activity [no].\n" - " --trace-fork-join=yes|no Trace all thread fork/join activity [no].\n" -@@ -270,6 +276,7 @@ - const Addr a, - const SizeT size) - { -+ DRD_(thread_set_vg_running_tid)(VG_(get_running_tid)()); - if (size > 0) - { - DRD_(trace_load)(a, size); -Index: drd/drd_pthread_intercepts.c -=================================================================== ---- drd/drd_pthread_intercepts.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_pthread_intercepts.c (.../trunk) (revision 13981) -@@ -243,8 +243,15 @@ - * statement because some of the PTHREAD_MUTEX_ macro's may have the same - * value. - */ --static MutexT DRD_(pthread_to_drd_mutex_type)(const int kind) -+static MutexT DRD_(pthread_to_drd_mutex_type)(int kind) - { -+ /* -+ * See also PTHREAD_MUTEX_KIND_MASK_NP in glibc source file -+ * . -+ */ -+ kind &= PTHREAD_MUTEX_RECURSIVE | PTHREAD_MUTEX_ERRORCHECK | -+ PTHREAD_MUTEX_NORMAL | PTHREAD_MUTEX_DEFAULT; -+ - if (kind == PTHREAD_MUTEX_RECURSIVE) - return mutex_type_recursive_mutex; - else if (kind == PTHREAD_MUTEX_ERRORCHECK) -@@ -258,9 +265,7 @@ - return mutex_type_default_mutex; - #endif - else -- { - return mutex_type_invalid_mutex; -- } - } - - #define IS_ALIGNED(p) (((uintptr_t)(p) & (sizeof(*(p)) - 1)) == 0) -@@ -1096,6 +1101,8 @@ - VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__PRE_RWLOCK_INIT, - rwlock, 0, 0, 0, 0); - CALL_FN_W_WW(ret, fn, rwlock, attr); -+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__POST_RWLOCK_INIT, -+ rwlock, 0, 0, 0, 0); - return ret; - } - -@@ -1110,6 +1117,8 @@ - int ret; - OrigFn fn; - VALGRIND_GET_ORIG_FN(fn); -+ VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__PRE_RWLOCK_DESTROY, -+ rwlock, 0, 0, 0, 0); - CALL_FN_W_W(ret, fn, rwlock); - VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__POST_RWLOCK_DESTROY, - rwlock, 0, 0, 0, 0); -@@ -1157,7 +1166,8 @@ - (pthread_rwlock_t* rwlock), (rwlock)); - - static __always_inline --int pthread_rwlock_timedrdlock_intercept(pthread_rwlock_t* rwlock) -+int pthread_rwlock_timedrdlock_intercept(pthread_rwlock_t* rwlock, -+ const struct timespec *timeout) - { - int ret; - OrigFn fn; -@@ -1164,7 +1174,7 @@ - VALGRIND_GET_ORIG_FN(fn); - VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__PRE_RWLOCK_RDLOCK, - rwlock, 0, 0, 0, 0); -- CALL_FN_W_W(ret, fn, rwlock); -+ CALL_FN_W_WW(ret, fn, rwlock, timeout); - VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__POST_RWLOCK_RDLOCK, - rwlock, ret == 0, 0, 0, 0); - return ret; -@@ -1172,10 +1182,12 @@ - - PTH_FUNCS(int, - pthreadZurwlockZutimedrdlock, pthread_rwlock_timedrdlock_intercept, -- (pthread_rwlock_t* rwlock), (rwlock)); -+ (pthread_rwlock_t* rwlock, const struct timespec *timeout), -+ (rwlock, timeout)); - - static __always_inline --int pthread_rwlock_timedwrlock_intercept(pthread_rwlock_t* rwlock) -+int pthread_rwlock_timedwrlock_intercept(pthread_rwlock_t* rwlock, -+ const struct timespec *timeout) - { - int ret; - OrigFn fn; -@@ -1182,7 +1194,7 @@ - VALGRIND_GET_ORIG_FN(fn); - VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__PRE_RWLOCK_WRLOCK, - rwlock, 0, 0, 0, 0); -- CALL_FN_W_W(ret, fn, rwlock); -+ CALL_FN_W_WW(ret, fn, rwlock, timeout); - VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__POST_RWLOCK_WRLOCK, - rwlock, ret == 0, 0, 0, 0); - return ret; -@@ -1190,7 +1202,8 @@ - - PTH_FUNCS(int, - pthreadZurwlockZutimedwrlock, pthread_rwlock_timedwrlock_intercept, -- (pthread_rwlock_t* rwlock), (rwlock)); -+ (pthread_rwlock_t* rwlock, const struct timespec *timeout), -+ (rwlock, timeout)); - - static __always_inline - int pthread_rwlock_tryrdlock_intercept(pthread_rwlock_t* rwlock) -Index: drd/drd_strmem_intercepts.c -=================================================================== ---- drd/drd_strmem_intercepts.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_strmem_intercepts.c (.../trunk) (revision 13981) -@@ -30,51 +30,4 @@ - The GNU General Public License is contained in the file COPYING. - */ - --#include "pub_tool_basics.h" --#include "pub_tool_hashtable.h" --#include "pub_tool_redir.h" --#include "pub_tool_tooliface.h" --#include "pub_tool_clreq.h" -- -- --#define STRNLEN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* str, SizeT n ); \ -- SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* str, SizeT n ) \ -- { \ -- SizeT i = 0; \ -- while (i < n && str[i] != 0) i++; \ -- return i; \ -- } -- --#if defined(VGO_linux) -- STRNLEN(VG_Z_LIBC_SONAME, strnlen) --#elif defined(VGO_darwin) -- STRNLEN(VG_Z_LIBC_SONAME, strnlen) --#endif -- -- --// Note that this replacement often doesn't get used because gcc inlines --// calls to strlen() with its own built-in version. This can be very --// confusing if you aren't expecting it. Other small functions in this file --// may also be inline by gcc. --#define STRLEN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname)( const char* str ); \ -- SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname)( const char* str ) \ -- { \ -- SizeT i = 0; \ -- while (str[i] != 0) i++; \ -- return i; \ -- } -- --#if defined(VGO_linux) -- STRLEN(VG_Z_LIBC_SONAME, strlen) -- STRLEN(VG_Z_LD_LINUX_SO_2, strlen) -- STRLEN(VG_Z_LD_LINUX_X86_64_SO_2, strlen) -- STRLEN(VG_Z_LIBC_SONAME, __GI_strlen) --#elif defined(VGO_darwin) -- STRLEN(VG_Z_LIBC_SONAME, strlen) --#endif -- --/*--------------------------------------------------------------------*/ --/*--- end ---*/ --/*--------------------------------------------------------------------*/ -+#include "../shared/vg_replace_strmem.c" -Index: drd/drd_thread.c -=================================================================== ---- drd/drd_thread.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_thread.c (.../trunk) (revision 13981) -@@ -255,16 +255,16 @@ - { - Segment* p; - -- for (p = ti->first; p; p = p->next) { -- if (p->next && p->next->prev != p) -+ for (p = ti->sg_first; p; p = p->thr_next) { -+ if (p->thr_next && p->thr_next->thr_prev != p) - return False; -- if (p->next == 0 && p != ti->last) -+ if (p->thr_next == 0 && p != ti->sg_last) - return False; - } -- for (p = ti->last; p; p = p->prev) { -- if (p->prev && p->prev->next != p) -+ for (p = ti->sg_last; p; p = p->thr_prev) { -+ if (p->thr_prev && p->thr_prev->thr_next != p) - return False; -- if (p->prev == 0 && p != ti->first) -+ if (p->thr_prev == 0 && p != ti->sg_first) - return False; - } - return True; -Index: drd/drd_thread.h -=================================================================== ---- drd/drd_thread.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/drd_thread.h (.../trunk) (revision 13981) -@@ -295,7 +295,7 @@ - /* This function can be called after the thread has been created but */ - /* before drd_post_thread_create() has filled in stack_max. */ - tl_assert(DRD_(g_threadinfo)[tid].stack_min -- < DRD_(g_threadinfo)[tid].stack_max -+ <= DRD_(g_threadinfo)[tid].stack_max - || DRD_(g_threadinfo)[tid].stack_max == 0); - #endif - if (UNLIKELY(stack_min < DRD_(g_threadinfo)[tid].stack_min_min)) -Index: drd/tests -=================================================================== ---- drd/tests (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/tests (.../trunk) (revision 13981) - -Property changes on: drd/tests -___________________________________________________________________ -Modified: svn:ignore -## -74,6 +74,9 ## - sem_open - sem_wait - sigalrm -+std_atomic -+std_list -+std_string - std_thread - tc01_simple_race - tc02_simple_tls -Index: drd/tests/Makefile.am -=================================================================== ---- drd/tests/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/tests/Makefile.am (.../trunk) (revision 13981) -@@ -91,10 +91,14 @@ - custom_alloc_fiw.stderr.exp \ - custom_alloc_fiw.vgtest \ - fp_race.stderr.exp \ -+ fp_race.stderr.exp-mips32-be \ -+ fp_race.stderr.exp-mips32-le \ - fp_race.vgtest \ - fp_race2.stderr.exp \ - fp_race2.vgtest \ - fp_race_xml.stderr.exp \ -+ fp_race_xml.stderr.exp-mips32-be \ -+ fp_race_xml.stderr.exp-mips32-le \ - fp_race_xml.vgtest \ - free_is_write.stderr.exp \ - free_is_write.vgtest \ -@@ -211,16 +215,24 @@ - rwlock_type_checking.stderr.exp \ - rwlock_type_checking.vgtest \ - sem_as_mutex.stderr.exp \ -+ sem_as_mutex.stderr.exp-mips32-be \ -+ sem_as_mutex.stderr.exp-mips32-le \ - sem_as_mutex.vgtest \ - sem_as_mutex2.stderr.exp \ - sem_as_mutex2.vgtest \ - sem_as_mutex3.stderr.exp \ -+ sem_as_mutex3.stderr.exp-mips32-be \ -+ sem_as_mutex3.stderr.exp-mips32-le \ - sem_as_mutex3.vgtest \ - sem_open.stderr.exp \ -+ sem_open.stderr.exp-mips32-be \ -+ sem_open.stderr.exp-mips32-le \ - sem_open.vgtest \ - sem_open2.stderr.exp \ - sem_open2.vgtest \ - sem_open3.stderr.exp \ -+ sem_open3.stderr.exp-mips32-be \ -+ sem_open3.stderr.exp-mips32-le \ - sem_open3.vgtest \ - sem_open_traced.stderr.exp \ - sem_open_traced.vgtest \ -@@ -230,8 +242,16 @@ - sigalrm.vgtest \ - sigaltstack.stderr.exp \ - sigaltstack.vgtest \ -+ std_atomic.stderr.exp \ -+ std_atomic.vgtest \ -+ std_list.stderr.exp \ -+ std_list.vgtest \ -+ std_string.stderr.exp \ -+ std_string.vgtest \ - std_thread.stderr.exp \ - std_thread.vgtest \ -+ str_tester.stderr.exp \ -+ str_tester.vgtest \ - tc01_simple_race.stderr.exp \ - tc01_simple_race.vgtest \ - tc02_simple_tls.stderr.exp \ -@@ -370,6 +390,9 @@ - if CXX_CAN_INCLUDE_THREAD_HEADER - if HAVE_SHARED_POINTER_ANNOTATION - check_PROGRAMS += \ -+ std_atomic \ -+ std_list \ -+ std_string \ - std_thread - endif - endif -@@ -450,6 +473,15 @@ - matinv_LDADD = $(LDADD) -lm - endif - -+std_atomic_SOURCES = std_atomic.cpp -+std_atomic_CXXFLAGS = $(AM_CXXFLAGS) -std=c++0x -Wno-sign-compare -+ -+std_list_SOURCES = std_list.cpp -+std_list_CXXFLAGS = $(AM_CXXFLAGS) -std=c++0x -Wno-sign-compare -+ -+std_string_SOURCES = std_string.cpp -+std_string_CXXFLAGS = $(AM_CXXFLAGS) -std=c++0x -Wno-sign-compare -+ - std_thread_SOURCES = std_thread.cpp - std_thread_CXXFLAGS = $(AM_CXXFLAGS) -std=c++0x - -Index: drd/tests/fp_race.stderr.exp-mips32-be -=================================================================== ---- drd/tests/fp_race.stderr.exp-mips32-be (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/fp_race.stderr.exp-mips32-be (.../trunk) (revision 13981) -@@ -0,0 +1,39 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0) -Index: drd/tests/fp_race.stderr.exp-mips32-le -=================================================================== ---- drd/tests/fp_race.stderr.exp-mips32-le (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/fp_race.stderr.exp-mips32-le (.../trunk) (revision 13981) -@@ -0,0 +1,39 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (fp_race.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at fp_race.c:24 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0) -Index: drd/tests/fp_race_xml.stderr.exp-mips32-be -=================================================================== ---- drd/tests/fp_race_xml.stderr.exp-mips32-be (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/fp_race_xml.stderr.exp-mips32-be (.../trunk) (revision 13981) -@@ -0,0 +1,158 @@ -+ -+ -+ -+ -+4 -+drd -+ -+ -+ ... -+ ... -+ ... -+ ... -+ -+ -+... -+... -+drd -+ -+ -+ ... -+ -+ ./fp_race -+ -+ -+ -+ -+ RUNNING -+ -+ -+ -+ drd_pre_thread_create creator = 0, created = 1 -+ drd_post_thread_create created = 1 -+ drd_pre_thread_create creator = 1, created = 2 -+ drd_post_thread_create created = 2 -+ drd_thread_finished tid = 2 -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting load by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 4 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting load by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 0 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting store by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 4 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting store by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 0 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ drd_post_thread_join joiner = 1, joinee = 2, new vc: [ ... ] -+ drd_thread_finished tid = 1 -+ -+ -+ FINISHED -+ -+ -+ -+ -+ -+ ... -+ 0x........ -+ -+ -+ ... -+ 0x........ -+ -+ -+ ... -+ 0x........ -+ -+ -+ ... -+ 0x........ -+ -+ -+ -+... -+ -+ -+ -Index: drd/tests/fp_race_xml.stderr.exp-mips32-le -=================================================================== ---- drd/tests/fp_race_xml.stderr.exp-mips32-le (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/fp_race_xml.stderr.exp-mips32-le (.../trunk) (revision 13981) -@@ -0,0 +1,158 @@ -+ -+ -+ -+ -+4 -+drd -+ -+ -+ ... -+ ... -+ ... -+ ... -+ -+ -+... -+... -+drd -+ -+ -+ ... -+ -+ ./fp_race -+ -+ -+ -+ -+ RUNNING -+ -+ -+ -+ drd_pre_thread_create creator = 0, created = 1 -+ drd_post_thread_create created = 1 -+ drd_pre_thread_create creator = 1, created = 2 -+ drd_post_thread_create created = 2 -+ drd_thread_finished tid = 2 -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting load by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 0 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting load by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 4 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting store by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 0 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ -+ 0x........ -+ ... -+ ConflictingAccess -+ Conflicting store by thread x at 0x........ size 4 -+ -+ -+ 0x........ -+ ... -+ main -+ ... -+ fp_race.c -+ ... -+ -+ -+ Location 0x........ is 4 bytes inside global var "s_d3" -+ declared at fp_race.c:24 fp_race.c ... -+ -+ -+ -+ -+ -+ -+ drd_post_thread_join joiner = 1, joinee = 2, new vc: [ ... ] -+ drd_thread_finished tid = 1 -+ -+ -+ FINISHED -+ -+ -+ -+ -+ -+ ... -+ 0x........ -+ -+ -+ ... -+ 0x........ -+ -+ -+ ... -+ 0x........ -+ -+ -+ ... -+ 0x........ -+ -+ -+ -+... -+ -+ -+ -Index: drd/tests/sem_as_mutex.stderr.exp-mips32-be -=================================================================== ---- drd/tests/sem_as_mutex.stderr.exp-mips32-be (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_as_mutex.stderr.exp-mips32-be (.../trunk) (revision 13981) -@@ -0,0 +1,39 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_as_mutex.stderr.exp-mips32-le -=================================================================== ---- drd/tests/sem_as_mutex.stderr.exp-mips32-le (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_as_mutex.stderr.exp-mips32-le (.../trunk) (revision 13981) -@@ -0,0 +1,39 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_as_mutex3.stderr.exp-mips32-be -=================================================================== ---- drd/tests/sem_as_mutex3.stderr.exp-mips32-be (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_as_mutex3.stderr.exp-mips32-be (.../trunk) (revision 13981) -@@ -0,0 +1,21 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_as_mutex3.stderr.exp-mips32-le -=================================================================== ---- drd/tests/sem_as_mutex3.stderr.exp-mips32-le (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_as_mutex3.stderr.exp-mips32-le (.../trunk) (revision 13981) -@@ -0,0 +1,21 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_as_mutex.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_as_mutex.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_open.c -=================================================================== ---- drd/tests/sem_open.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/tests/sem_open.c (.../trunk) (revision 13981) -@@ -58,7 +58,7 @@ - * Use the ipcs and ipcrm commands to clean up named semaphores left by - * aborted instances of this process. - */ -- snprintf(semaphore_name, sizeof(semaphore_name), "drd-sem-open-test-%d", -+ snprintf(semaphore_name, sizeof(semaphore_name), "/drd-sem-open-test-%d", - getpid()); - s_sem = sem_open(semaphore_name, O_CREAT | O_EXCL, 0600, 1); - if (s_sem == SEM_FAILED) -Index: drd/tests/sem_open.stderr.exp-mips32-be -=================================================================== ---- drd/tests/sem_open.stderr.exp-mips32-be (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_open.stderr.exp-mips32-be (.../trunk) (revision 13981) -@@ -0,0 +1,39 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_open.stderr.exp-mips32-le -=================================================================== ---- drd/tests/sem_open.stderr.exp-mips32-le (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_open.stderr.exp-mips32-le (.../trunk) (revision 13981) -@@ -0,0 +1,39 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting store by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_open3.stderr.exp-mips32-be -=================================================================== ---- drd/tests/sem_open3.stderr.exp-mips32-be (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_open3.stderr.exp-mips32-be (.../trunk) (revision 13981) -@@ -0,0 +1,21 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_open3.stderr.exp-mips32-le -=================================================================== ---- drd/tests/sem_open3.stderr.exp-mips32-le (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/sem_open3.stderr.exp-mips32-le (.../trunk) (revision 13981) -@@ -0,0 +1,21 @@ -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 0 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+Conflicting load by thread 1 at 0x........ size 4 -+ at 0x........: main (sem_open.c:?) -+Location 0x........ is 4 bytes inside global var "s_d3" -+declared at sem_open.c:25 -+Other segment start (thread 2) -+ (thread finished, call stack no longer available) -+Other segment end (thread 2) -+ (thread finished, call stack no longer available) -+ -+ -+ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: drd/tests/sem_open_traced.stderr.exp -=================================================================== ---- drd/tests/sem_open_traced.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/tests/sem_open_traced.stderr.exp (.../trunk) (revision 13981) -@@ -1,5 +1,5 @@ - --[1] sem_open 0x........ name drd-sem-open-test oflag 0x........ mode 0600 value 1 -+[1] sem_open 0x........ name /drd-sem-open-test oflag 0x........ mode 0600 value 1 - [2] sem_wait 0x........ value 1 -> 0 - [2] sem_post 0x........ value 0 -> 1 - [1] sem_wait 0x........ value 1 -> 0 -Index: drd/tests/std_atomic.cpp -=================================================================== ---- drd/tests/std_atomic.cpp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_atomic.cpp (.../trunk) (revision 13981) -@@ -0,0 +1,56 @@ -+/* -+ * Test program for std::atomic<> -+ * -+ * See also https://bugs.kde.org/show_bug.cgi?id=328490. -+ */ -+ -+#include "../drd.h" -+#include -+#include -+#include -+#include -+ -+std::atomic g_b; -+ -+void *func1(void *instance) -+{ -+ while (!g_b) { -+ timespec delay = { 0, 100 * 1000 * 1000 }; -+ nanosleep(&delay, NULL); -+ } -+ return NULL; -+} -+ -+void *func2(void *instance) -+{ -+ g_b = true; -+ return NULL; -+} -+ -+int main(int argc, char* argv[]) -+{ -+ int err; -+ pthread_t thread1; -+ pthread_t thread2; -+ -+ std::cerr << "Started.\n"; -+ -+ if (argc > 1) -+ DRD_IGNORE_VAR(g_b); -+ -+ err = pthread_create(&thread1, NULL, &func1, NULL); -+ if (err != 0) -+ throw std::string("failed to create a thread."); -+ err = pthread_create(&thread2, NULL, &func2, NULL); -+ if (err != 0) -+ throw std::string("failed to create a thread."); -+ -+ err = pthread_join(thread1, NULL); -+ if (err != 0) -+ throw std::string("Thread::join(): failed to join."); -+ err = pthread_join(thread2, NULL); -+ if (err != 0) -+ throw std::string("Thread::join(): failed to join."); -+ -+ std::cerr << "Done.\n"; -+} -Index: drd/tests/std_atomic.stderr.exp -=================================================================== ---- drd/tests/std_atomic.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_atomic.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,5 @@ -+ -+Started. -+Done. -+ -+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) -Index: drd/tests/std_atomic.vgtest -=================================================================== ---- drd/tests/std_atomic.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_atomic.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,4 @@ -+prereq: test -e std_atomic && ./supported_libpthread -+vgopts: --check-stack-var=yes --show-confl-seg=no -+prog: std_atomic 1 -+stderr_filter: filter_stderr -Index: drd/tests/std_list.cpp -=================================================================== ---- drd/tests/std_list.cpp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_list.cpp (.../trunk) (revision 13981) -@@ -0,0 +1,99 @@ -+/* -+ * Test program that triggers strcpy() from one thread and a memory allocation -+ * immediately after the region read by strcpy() from another thread. Without -+ * strcpy() intercept there is about 50% chance that this test program triggers -+ * a false positive race report on Ubuntu 12.10 amd64. -+ * -+ * See also https://bugs.kde.org/show_bug.cgi?id=326436. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+using namespace std; -+ -+class SubTest { -+public: -+ SubTest() { -+ list ffList; -+ ffList.push_back((int *) NULL); -+ for (list::iterator ff = ffList.begin(); ff != ffList.end(); ff++) { -+ usleep(1000); -+ } -+ } -+ void subTest() { -+ list ffList; -+ ffList.push_back((int *) NULL); -+ for (list::const_iterator ff = ffList.begin(); ff != ffList.end(); ff++) { -+ usleep(1000); -+ } -+ } -+}; -+ -+class Test { -+ SubTest *subTest; -+public: -+ void setUp() { -+ subTest = new SubTest(); -+ setlocale(LC_ALL, "English"); -+ } -+ void tearDown() { -+ delete subTest; } -+ void func1() { -+ for (size_t i = 0; i < 10000; i++) { -+ subTest->subTest(); -+ usleep(1000); -+ } -+ } -+ void func2() { -+ usleep(1000); -+ } -+}; -+ -+void *func1(void *instance) -+{ -+ Test *casted = reinterpret_cast(instance); -+ casted->setUp(); -+ casted->func1(); -+ casted->tearDown(); -+ return NULL; -+} -+ -+void *func2(void *instance) -+{ -+ Test *casted = reinterpret_cast(instance); -+ casted->setUp(); -+ casted->func2(); -+ casted->tearDown(); -+ return NULL; -+} -+ -+int main(int argc, char* argv[]) -+{ -+ int err; -+ pthread_t thread1; -+ pthread_t thread2; -+ Test instance1; -+ Test instance2; -+ -+ // create -+ err = pthread_create(&thread1, NULL, &func1, &instance1); -+ if (err != 0) -+ throw string("failed to create a thread."); -+ err = pthread_create(&thread2, NULL, &func2, &instance2); -+ if (err != 0) -+ throw string("failed to create a thread."); -+ // join -+ err = pthread_join(thread1, NULL); -+ if (err != 0) -+ throw string("Thread::join(): failed to join."); -+ err = pthread_join(thread2, NULL); -+ if (err != 0) -+ throw string("Thread::join(): failed to join."); -+} -Index: drd/tests/std_list.stderr.exp -=================================================================== ---- drd/tests/std_list.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_list.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+ -+ -+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) -Index: drd/tests/std_list.vgtest -=================================================================== ---- drd/tests/std_list.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_list.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,4 @@ -+prereq: test -e std_list && ./supported_libpthread -+vgopts: --check-stack-var=yes --show-confl-seg=no -+prog: std_list -+stderr_filter: filter_stderr -Index: drd/tests/std_string.cpp -=================================================================== ---- drd/tests/std_string.cpp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_string.cpp (.../trunk) (revision 13981) -@@ -0,0 +1,67 @@ -+/* -+ * Test program that uses std::string object from more than one thread and -+ * that also triggers a call to __GI_strlen() (from inside strdup()). See also -+ * https://bugs.kde.org/show_bug.cgi?id=326091. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+char* list2byteArray() -+{ -+ size_t data_size = 24; -+ char *data = new char[data_size]; -+ for (size_t i = 0; i < data_size; i++) -+ data[i] = 'a'; -+ data[data_size - 1] = 0; -+ char *ret = strdup(data); -+ delete[] data; -+ return ret; -+} -+ -+int addRecord() -+{ -+ char *data = list2byteArray(); -+ usleep(100); -+ free(data); -+ return 0; -+} -+ -+void *fillTable(void *ptr) -+{ -+ for (int i = 0; i < 100; i++) { -+ std::string id("000"); -+ id.append(1, 'a' + i); -+ std::list record; -+ record.push_back("some data"); -+ addRecord(); -+ } -+ usleep(1000 * 1000); -+ return NULL; -+} -+ -+int main(int argc, char* argv[]) -+{ -+ pthread_t thread[2]; -+ -+ for (int i = 0; i < sizeof(thread)/sizeof(thread[0]); i++) { -+ int ret = pthread_create(&thread[i], NULL, &fillTable, NULL); -+ if (ret) { -+ fprintf(stderr, "Failed to create thread %d: %d\n", i, ret); -+ return 1; -+ } -+ } -+ -+ for (int i = 0; i < sizeof(thread)/sizeof(thread[0]); i++) { -+ int ret = pthread_join(thread[i], NULL); -+ if (ret != 0) { -+ fprintf(stderr, "Failed to join thread %d: %d\n", i, ret); -+ return 1; -+ } -+ } -+ -+ return 0; -+} -Index: drd/tests/std_string.stderr.exp -=================================================================== ---- drd/tests/std_string.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_string.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+ -+ -+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) -Index: drd/tests/std_string.vgtest -=================================================================== ---- drd/tests/std_string.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/std_string.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,4 @@ -+prereq: test -e std_string && ./supported_libpthread -+vgopts: --check-stack-var=yes --show-confl-seg=no -+prog: std_string -+stderr_filter: filter_stderr -Index: drd/tests/str_tester.stderr.exp -=================================================================== ---- drd/tests/str_tester.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/str_tester.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+ -+ -+ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) -Index: drd/tests/str_tester.vgtest -=================================================================== ---- drd/tests/str_tester.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ drd/tests/str_tester.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prog: ../../memcheck/tests/str_tester -+ -Index: drd/tests/tc21_pthonce.stdout.exp -=================================================================== ---- drd/tests/tc21_pthonce.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/tests/tc21_pthonce.stdout.exp (.../trunk) (revision 13981) -@@ -1,3 +1,4 @@ -+main: Hello - welcome: Welcome - child: Hi, I'm thread 0 - child: Hi, I'm thread 1 -Index: drd/tests/thread_name.c -=================================================================== ---- drd/tests/thread_name.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/tests/thread_name.c (.../trunk) (revision 13981) -@@ -11,6 +11,7 @@ - #define NUM_THREADS 10 - - -+static pthread_barrier_t s_barrier; - static pthread_mutex_t s_mutex; - static pthread_cond_t s_cond; - static int s_counter; -@@ -27,6 +28,8 @@ - - memset(&invalid_mutex, 0xff, sizeof(invalid_mutex)); - -+ pthread_barrier_wait(&s_barrier); -+ - pthread_mutex_lock(&s_mutex); - while (s_counter != thread_num) - pthread_cond_wait(&s_cond, &s_mutex); -@@ -45,6 +48,7 @@ - int i; - pthread_t tid[NUM_THREADS]; - -+ pthread_barrier_init(&s_barrier, NULL, NUM_THREADS); - pthread_mutex_init(&s_mutex, 0); - pthread_cond_init(&s_cond, 0); - -Index: drd/tests/trylock.c -=================================================================== ---- drd/tests/trylock.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ drd/tests/trylock.c (.../trunk) (revision 13981) -@@ -72,7 +72,7 @@ - r = pthread_mutex_timedlock(&mutex, &abs_timeout); assert(r == 0); - r = pthread_mutex_unlock(&mutex); assert(r == 0); - #endif -- r = pthread_mutex_destroy(&mutex); assert(r == 0); -+ r = pthread_mutex_destroy(&mutex); - - return 0; - } -Index: exp-sgcheck/pc_main.c -=================================================================== ---- exp-sgcheck/pc_main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ exp-sgcheck/pc_main.c (.../trunk) (revision 13981) -@@ -62,9 +62,21 @@ - #endif - #if defined(VGA_s390x) - /* fixs390: to be done. */ -- VG_(printf)("SGCheck doesn't work s390x yet, sorry.\n"); -+ VG_(printf)("SGCheck doesn't work on s390x yet, sorry.\n"); - VG_(exit)(1); - #endif -+#if defined(VGA_ppc32) || defined(VGA_ppc64) -+ VG_(printf)("SGCheck doesn't work on PPC yet, sorry.\n"); -+ VG_(exit)(1); -+#endif -+#if defined(VGA_arm) || defined(VGA_arm64) -+ VG_(printf)("SGCheck doesn't work on ARM yet, sorry.\n"); -+ VG_(exit)(1); -+#endif -+#if defined(VGA_mips32) || defined(VGA_mips64) -+ VG_(printf)("SGCheck doesn't work on MIPS yet, sorry.\n"); -+ VG_(exit)(1); -+#endif - - // Can't change the name until we change the names in suppressions - // too. -Index: gdbserver_tests/Makefile.am -=================================================================== ---- gdbserver_tests/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/Makefile.am (.../trunk) (revision 13981) -@@ -4,10 +4,16 @@ - dist_noinst_SCRIPTS = \ - invoker simulate_control_c make_local_links \ - filter_gdb filter_make_empty \ -- filter_memcheck_monitor filter_stderr filter_vgdb -+ filter_memcheck_monitor filter_stderr filter_vgdb \ -+ filter_helgrind_monitor send_signal - - EXTRA_DIST = \ - README_DEVELOPERS \ -+ hginfo.stderrB.exp \ -+ hginfo.stderr.exp \ -+ hginfo.stdinB.gdb \ -+ hginfo.stdoutB.exp \ -+ hginfo.vgtest \ - mcblocklistsearch.stderr.exp \ - mcblocklistsearch.stdinB.gdb \ - mcblocklistsearch.vgtest \ -@@ -119,7 +125,12 @@ - nlsigvgdb.vgtest \ - nlsigvgdb.stderr.exp \ - nlsigvgdb.stderrB.exp \ -- nlsigvgdb.stdinB.gdb -+ nlsigvgdb.stdinB.gdb \ -+ nlvgdbsigqueue.vgtest \ -+ nlvgdbsigqueue.stderrB.exp \ -+ nlvgdbsigqueue.stderr.exp \ -+ nlvgdbsigqueue.stdinB.gdb \ -+ nlvgdbsigqueue.stdoutB.exp - - check_PROGRAMS = \ - clean_after_fork \ -Index: gdbserver_tests/filter_gdb -=================================================================== ---- gdbserver_tests/filter_gdb (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/filter_gdb (.../trunk) (revision 13981) -@@ -20,6 +20,9 @@ - # output of the echo command telling it is launched. - # This removes a whole lot of uninteresting lines varying - # with OS/glibc/gdb dep -+# then have a general way to delete uninteresting and vayring -+# lines. -+# suppress lines telling file _exit.c does not exist - # initial tty control character sent by gdb 7.0 - # remove missing debuginfos - # vgdb message -@@ -54,8 +57,10 @@ - # 'exited with code' and 'exited normally' are printed slightly - # differently between gdb versions, normalize to "Program exited...". - sed -e '/Remote debugging using/,/vgdb launched process attached/d' \ -+ -e '/filter_gdb BEGIN drop/,/filter_gdb END drop/d' \ - -e 's/^\[?1034hReading symbols/Reading symbols/' \ - -e '/^Missing separate debuginfo/d' \ -+ -e '/\/_exit.c: No such file or directory/d' \ - -e '/^Try: zypper install -C/d' \ - -e 's/\(relaying data between gdb and process \)[0-9][0-9]*/\1..../' \ - -e 's/pid [0-9][0-9]*/pid ..../g' \ -@@ -68,8 +73,8 @@ - -e '/^Loaded symbols for .*$/d' \ - -e '/^Current language.*/d' \ - -e '/^The current source language is.*/d' \ -- -e 's/^.*\( exited with code [0-9]\+\).$/Program\1\./g' \ -- -e 's/^.*\( exited normally\).$/Program\1\./g' \ -+ -e 's/^.*\( exited with code [0-9]\+\).$/Program\1\./g' \ -+ -e 's/^.*\( exited normally\).$/Program\1\./g' \ - -e 's/(gdb) //g' \ - -e 's/^>[> ]*//' \ - -e '/^done\.$/d' \ -@@ -83,7 +88,7 @@ - -e 's/in \(.__\)\{0,1\}select () from \/.*$/in syscall .../' \ - -e '/^ from \/lib\/libc.so.*$/d' \ - -e '/^ from \/lib64\/libc.so.*$/d' \ -- -e '/^ from \/lib64\/.*\/libc.so.*$/d' \ -+ -e '/^ from \/lib64\/.*\/libc.so.*$/d' \ - -e 's/in select ()$/in syscall .../' \ - -e 's/in \.__select ()$/in syscall .../' \ - -e 's/in select () at \.\.\/sysdeps\/unix\/syscall-template\.S.*$/in syscall .../' \ -@@ -101,10 +106,10 @@ - -e 's/^\([ \*] [1234] \) *Thread /\1Thread /' \ - -e 's/VgTs_WaitSys) 0x/VgTs_WaitSys) 0x/' \ - -e '/Cannot access memory at address 0x......../d' \ -- -e '/^$/d' | -+ -e '/^$/d' | - - # remove all the lines telling where the SIGFPE was trapped. --sed -e '/after trap SIGFPE/,/after continue SIGFPE/d' | -+sed -e '/after trap SIGFPE/,/after continue SIGFPE/d' | - - # join together two lines that gdb 7.1 splits in two (???) - # (in a separate sed, as the below influences the behaviour of the other expressions) -Index: gdbserver_tests/filter_helgrind_monitor -=================================================================== ---- gdbserver_tests/filter_helgrind_monitor (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/filter_helgrind_monitor (.../trunk) (revision 13981) -@@ -0,0 +1,10 @@ -+#! /bin/sh -+ -+# used to filter helgrind output shown by gdb/vgdb. -+ -+dir=`dirname $0` -+ -+$dir/../helgrind/tests/filter_stderr "$@" | -+ -+# filter vgdb messages -+$dir/filter_vgdb - -Property changes on: gdbserver_tests/filter_helgrind_monitor -___________________________________________________________________ -Added: svn:executable -## -0,0 +1 ## -+* -\ No newline at end of property -Index: gdbserver_tests/hginfo.stderr.exp -=================================================================== ---- gdbserver_tests/hginfo.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/hginfo.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+(action at startup) vgdb me ... -+ -+ -Index: gdbserver_tests/hginfo.stderrB.exp -=================================================================== ---- gdbserver_tests/hginfo.stderrB.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/hginfo.stderrB.exp (.../trunk) (revision 13981) -@@ -0,0 +1,18 @@ -+relaying data between gdb and process .... -+vgdb-error value changed from 0 to 999999 -+Lock ga 0x........ { -+ Address 0x........ is 0 bytes inside data symbol "mx" -+ kind mbRec -+ { W1:thread #x tid 2 } -+} -+ Address 0x........ is 0 bytes inside a block of size 1,008 alloc'd -+ at 0x........: malloc (vg_replace_malloc.c:...) -+ by 0x........: th (hg01_all_ok.c:22) -+ by 0x........: mythread_wrapper (hg_intercepts.c:...) -+ ... -+Lock ga 0x........ { -+ Address 0x........ is 0 bytes inside data symbol "mx" -+ kind mbRec -+ { W1:thread #x tid 3 } -+} -+ Address 0x........ is 0 bytes inside an unallocated block of size 1,008 in arena "client" -Index: gdbserver_tests/hginfo.stdinB.gdb -=================================================================== ---- gdbserver_tests/hginfo.stdinB.gdb (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/hginfo.stdinB.gdb (.../trunk) (revision 13981) -@@ -0,0 +1,20 @@ -+# connect gdb to Valgrind gdbserver: -+target remote | ./vgdb --wait=60 --vgdb-prefix=./vgdb-prefix-hginfo -+echo vgdb launched process attached\n -+monitor v.set vgdb-error 999999 -+# -+# -+# insert break: -+break breakme -+# -+# continue till each break and execute via gdb the monitor commands -+# ptr must be allocated at this state: -+continue -+monitor info locks -+eval "monitor v.info location %p", ptr -+# ptr must be freed at this state -+continue -+monitor info locks -+eval "monitor v.info location %p", ptr -+continue -+quit -Index: gdbserver_tests/hginfo.stdoutB.exp -=================================================================== ---- gdbserver_tests/hginfo.stdoutB.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/hginfo.stdoutB.exp (.../trunk) (revision 13981) -@@ -0,0 +1,11 @@ -+Breakpoint 1 at 0x........: file hg01_all_ok.c, line 13. -+Continuing. -+[New Thread ....] -+Breakpoint 1, breakme () at hg01_all_ok.c:13 -+13 if (shared == 1) -+Continuing. -+[New Thread ....] -+Breakpoint 1, breakme () at hg01_all_ok.c:13 -+13 if (shared == 1) -+Continuing. -+Program exited normally. -Index: gdbserver_tests/hginfo.vgtest -=================================================================== ---- gdbserver_tests/hginfo.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/hginfo.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,13 @@ -+# test helgrind monitor command -+# test 'v.info location' monitor command -+prog: ../helgrind/tests/hg01_all_ok -+vgopts: --tool=helgrind --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-hginfo -q -+prereq: test -e gdb.eval -+stdout_filter: filter_make_empty -+stderr_filter: filter_stderr -+progB: gdb -+argsB: --quiet -l 60 --nx ../helgrind/tests/hg01_all_ok -+stdinB: hginfo.stdinB.gdb -+stdoutB_filter: filter_gdb -+stderrB_filter: filter_helgrind_monitor -+stderrB_filter_args: hg01_all_ok.c -Index: gdbserver_tests/make_local_links -=================================================================== ---- gdbserver_tests/make_local_links (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/make_local_links (.../trunk) (revision 13981) -@@ -99,11 +99,11 @@ - # if ptrace not implemented in vgdb or OS restricts the initial attach, - # some tests would block for a loooonnnng time. - if gdbserver_tests/vgdb --help 2>&1 | -- grep -e 'ptrace invoker not implemented' > /dev/null -+ grep -e 'invoker not implemented' > /dev/null - then -- rm -f gdbserver_tests/vgdb.ptraceinvoker -+ rm -f gdbserver_tests/vgdb.invoker - else -- touch gdbserver_tests/vgdb.ptraceinvoker -+ touch gdbserver_tests/vgdb.invoker - fi - - # cleanup the possibly big garbage previously collected output -Index: gdbserver_tests/mchelp.stdoutB.exp -=================================================================== ---- gdbserver_tests/mchelp.stdoutB.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/mchelp.stdoutB.exp (.../trunk) (revision 13981) -@@ -3,6 +3,7 @@ - v.wait [] : sleep (default 0) then continue - v.info all_errors : show all errors found so far - v.info last_error : show last error found -+ v.info location : show information about location - v.info n_errs_found [msg] : show the nr of errors found so far and the given msg - v.info open_fds : show open file descriptors (only if --track-fds=yes) - v.kill : kill the Valgrind process -@@ -47,6 +48,7 @@ - v.wait [] : sleep (default 0) then continue - v.info all_errors : show all errors found so far - v.info last_error : show last error found -+ v.info location : show information about location - v.info n_errs_found [msg] : show the nr of errors found so far and the given msg - v.info open_fds : show open file descriptors (only if --track-fds=yes) - v.kill : kill the Valgrind process -@@ -62,7 +64,10 @@ - (with aspacemgr arg, also shows valgrind segments on log ouput) - v.info exectxt : show stacktraces and stats of all execontexts - v.info scheduler : show valgrind thread state and stacktrace -+ v.info stats : show various valgrind and tool stats - v.set debuglog : set valgrind debug log level to -+ v.set hostvisibility [yes*|no] : (en/dis)ables access by gdb/gdbserver to -+ Valgrind internal host status/memory - v.translate [] : debug translation of with - (default traceflags 0b00100000 : show after instrumentation) - An additional flag 0b100000000 allows to show gdbserver instrumentation -Index: gdbserver_tests/mcinvokeRU.vgtest -=================================================================== ---- gdbserver_tests/mcinvokeRU.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/mcinvokeRU.vgtest (.../trunk) (revision 13981) -@@ -4,8 +4,8 @@ - args: 1 0 1000000000 B-B-B-B- - vgopts: --tool=memcheck --vgdb=yes --vgdb-prefix=./vgdb-prefix-mcinvokeRU - stderr_filter: filter_make_empty --# as the Valgrind process is always busy, we do not need the vgdb.ptraceinvoker prereq. --# We even disable ptrace invoker to avoid spurious attach error message -+# as the Valgrind process is always busy, we do not need the vgdb.invoker prereq. -+# We even disable invoker to avoid spurious attach error message - # on kernels where ptrace is restricted. - progB: invoker - argsB: 10 --vgdb-prefix=./vgdb-prefix-mcinvokeRU --max-invoke-ms=0 --wait=60 -c v.wait 0 -Index: gdbserver_tests/mcinvokeWS.vgtest -=================================================================== ---- gdbserver_tests/mcinvokeWS.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/mcinvokeWS.vgtest (.../trunk) (revision 13981) -@@ -4,7 +4,7 @@ - args: 1 10000000 0 -S-S-S-S - vgopts: --tool=memcheck --vgdb=yes --vgdb-prefix=./vgdb-prefix-mcinvokeWS - stderr_filter: filter_make_empty --prereq: test -f vgdb.ptraceinvoker -+prereq: test -f vgdb.invoker - progB: invoker - argsB: 10 --vgdb-prefix=./vgdb-prefix-mcinvokeWS --wait=60 -c v.wait 0 - # if the --wait is not enough, the test will fail or block -Index: gdbserver_tests/mssnapshot.stderrB.exp -=================================================================== ---- gdbserver_tests/mssnapshot.stderrB.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/mssnapshot.stderrB.exp (.../trunk) (revision 13981) -@@ -5,6 +5,7 @@ - v.wait [] : sleep (default 0) then continue - v.info all_errors : show all errors found so far - v.info last_error : show last error found -+ v.info location : show information about location - v.info n_errs_found [msg] : show the nr of errors found so far and the given msg - v.info open_fds : show open file descriptors (only if --track-fds=yes) - v.kill : kill the Valgrind process -Index: gdbserver_tests/mssnapshot.vgtest -=================================================================== ---- gdbserver_tests/mssnapshot.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/mssnapshot.vgtest (.../trunk) (revision 13981) -@@ -1,4 +1,4 @@ --# test the memcheck monitor help -+# test the massif help and massif snapshots. - prereq: test -e gdb - prog: t - vgopts: --tool=massif --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-mssnapshot -Index: gdbserver_tests/nlcontrolc.vgtest -=================================================================== ---- gdbserver_tests/nlcontrolc.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlcontrolc.vgtest (.../trunk) (revision 13981) -@@ -10,7 +10,7 @@ - args: 1000000000 1000000000 1000000000 BSBSBSBS - vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlcontrolc - stderr_filter: filter_stderr --prereq: test -e gdb -a -f vgdb.ptraceinvoker -+prereq: test -e gdb -a -f vgdb.invoker - progB: gdb - argsB: --quiet -l 60 --nx ./sleepers - stdinB: nlcontrolc.stdinB.gdb -Index: gdbserver_tests/nlgone_abrt.stdinB.gdb -=================================================================== ---- gdbserver_tests/nlgone_abrt.stdinB.gdb (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_abrt.stdinB.gdb (.../trunk) (revision 13981) -@@ -1,7 +1,6 @@ - # connect gdb to Valgrind gdbserver: - target remote | ./vgdb --wait=60 --vgdb-prefix=./vgdb-prefix-nlgone-abrt - echo vgdb launched process attached\n -- - continue - # see process get a fatal signal - continue -Index: gdbserver_tests/nlgone_abrt.stdoutB.exp -=================================================================== ---- gdbserver_tests/nlgone_abrt.stdoutB.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_abrt.stdoutB.exp (.../trunk) (revision 13981) -@@ -1,4 +1,3 @@ --vgdb launched process attached - Continuing. - Program received signal SIGABRT, Aborted. - 0x........ in syscall ... -Index: gdbserver_tests/nlgone_exit.stderr.exp -=================================================================== ---- gdbserver_tests/nlgone_exit.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_exit.stderr.exp (.../trunk) (revision 13981) -@@ -5,4 +5,5 @@ - - starting ... - exiting ... -+(action at exit) vgdb me ... - -Index: gdbserver_tests/nlgone_exit.stdinB.gdb -=================================================================== ---- gdbserver_tests/nlgone_exit.stdinB.gdb (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_exit.stdinB.gdb (.../trunk) (revision 13981) -@@ -1,7 +1,11 @@ - # connect gdb to Valgrind gdbserver: - target remote | ./vgdb --wait=60 --vgdb-prefix=./vgdb-prefix-nlgone-exit - echo vgdb launched process attached\n -- -+# continue after startup -+echo filter_gdb BEGIN drop\n - continue -+echo filter_gdb END drop\n -+# continue at the last instruction -+continue - # see program is gone with exit code - quit -Index: gdbserver_tests/nlgone_exit.stdoutB.exp -=================================================================== ---- gdbserver_tests/nlgone_exit.stdoutB.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_exit.stdoutB.exp (.../trunk) (revision 13981) -@@ -1,3 +1,2 @@ --vgdb launched process attached - Continuing. - Program exited with code 01. -Index: gdbserver_tests/nlgone_exit.vgtest -=================================================================== ---- gdbserver_tests/nlgone_exit.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_exit.vgtest (.../trunk) (revision 13981) -@@ -1,8 +1,9 @@ - # test that an exit (with return value) is properly passed on to gdb. -- -+# also test the --vgdb-stop-at startup and exit args (so we do not use -+# --vgdb-error=0 here) - prog: gone - args: exit --vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlgone-exit -+vgopts: --tool=none --vgdb=yes --vgdb-stop-at=startup,exit --vgdb-prefix=./vgdb-prefix-nlgone-exit - stderr_filter: filter_stderr - prereq: test -e gdb - progB: gdb -Index: gdbserver_tests/nlgone_return.stdinB.gdb -=================================================================== ---- gdbserver_tests/nlgone_return.stdinB.gdb (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_return.stdinB.gdb (.../trunk) (revision 13981) -@@ -1,7 +1,6 @@ - # connect gdb to Valgrind gdbserver: - target remote | ./vgdb --wait=60 --vgdb-prefix=./vgdb-prefix-nlgone-return - echo vgdb launched process attached\n -- - continue - # see program is gone - quit -Index: gdbserver_tests/nlgone_return.stdoutB.exp -=================================================================== ---- gdbserver_tests/nlgone_return.stdoutB.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlgone_return.stdoutB.exp (.../trunk) (revision 13981) -@@ -1,3 +1,2 @@ --vgdb launched process attached - Continuing. - Program exited normally. -Index: gdbserver_tests/nlsigvgdb.vgtest -=================================================================== ---- gdbserver_tests/nlsigvgdb.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/nlsigvgdb.vgtest (.../trunk) (revision 13981) -@@ -7,7 +7,7 @@ - args: 1 10000000 0 -S-S-S-S - vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlsigvgdb - stderr_filter: filter_stderr --prereq: test -e gdb -a -f vgdb.ptraceinvoker -+prereq: test -e gdb -a -f vgdb.invoker - progB: gdb - argsB: --quiet -l 60 --nx ./sleepers - stdinB: nlsigvgdb.stdinB.gdb -Index: gdbserver_tests/nlvgdbsigqueue.stderr.exp -=================================================================== ---- gdbserver_tests/nlvgdbsigqueue.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/nlvgdbsigqueue.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,11 @@ -+Nulgrind, the minimal Valgrind tool -+ -+(action at startup) vgdb me ... -+ -+ -+loops/sleep_ms/burn/threads_spec: 1000000000 1000000000 1 BSBSBSBS -+Brussels ready to sleep and/or burn -+London ready to sleep and/or burn -+Petaouchnok ready to sleep and/or burn -+main ready to sleep and/or burn -+Gdb request to kill this process -Index: gdbserver_tests/nlvgdbsigqueue.stderrB.exp -=================================================================== -Index: gdbserver_tests/nlvgdbsigqueue.stdinB.gdb -=================================================================== ---- gdbserver_tests/nlvgdbsigqueue.stdinB.gdb (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/nlvgdbsigqueue.stdinB.gdb (.../trunk) (revision 13981) -@@ -0,0 +1,33 @@ -+# connect gdb to Valgrind gdbserver: -+target remote | ./vgdb --wait=60 --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue -+echo vgdb launched process attached\n -+monitor v.set vgdb-error 999999 -+# -+# -+# simulate control-c 1 second after having seen sleepers program outputting 'main' -+shell ./simulate_control_c --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue 1 grep main nlvgdbsigqueue.stderr.out -+# -+# send SIGUSR1/SIGUSR1 in a few seconds, after vgdb has attached -+# vgdb will attach when it will receive the control-c -+shell ./send_signal USR1 --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue 0 grep attachedwaitingforsigusr1 nlvgdbsigqueue.stdoutB.out -+shell ./send_signal USR1 --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue 1 grep attachedwaitingforsigusr1 nlvgdbsigqueue.stdoutB.out -+# -+echo continuing to have vgdb interrupted by simulate_control_c\n -+continue -+# -+# Now vgdb should have received the interrupt, and so has -+# attached to the sleeping process. -+# wait for the USR sig to be sent, that will be queued by vgdb. -+echo attachedwaitingforsigusr1\n -+# send_signal tries every second the guardcmd -+# so we must now wait to be (somewhat) sure the 2 SIGUSR1 are emitted -+shell sleep 4 -+# continue, so as to have vgdb sending queued signals when PTRACE_DETACHing -+echo continuing to receive first SIGUSR1\n -+continue -+# simulate a control c to afterwards stop the execution -+shell ./simulate_control_c --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue 1 -+echo continuing to receive second SIGUSR1\n -+continue -+kill -+quit -Index: gdbserver_tests/nlvgdbsigqueue.stdoutB.exp -=================================================================== ---- gdbserver_tests/nlvgdbsigqueue.stdoutB.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/nlvgdbsigqueue.stdoutB.exp (.../trunk) (revision 13981) -@@ -0,0 +1,16 @@ -+continuing to have vgdb interrupted by simulate_control_c -+Continuing. -+Program received signal SIGTRAP, Trace/breakpoint trap. -+0x........ in syscall ... -+attachedwaitingforsigusr1 -+sending signal -+sending signal -+continuing to receive first SIGUSR1 -+Continuing. -+Program received signal SIGUSR1, User defined signal 1. -+0x........ in syscall ... -+continuing to receive second SIGUSR1 -+Continuing. -+Program received signal SIGUSR1, User defined signal 1. -+0x........ in syscall ... -+Kill the program being debugged? (y or n) [answered Y; input not from terminal] -Index: gdbserver_tests/nlvgdbsigqueue.vgtest -=================================================================== ---- gdbserver_tests/nlvgdbsigqueue.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/nlvgdbsigqueue.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,14 @@ -+# test : -+# sending signal when all threads are in WaitSys -+# vgdb must queue these signals and deliver them before PTRACE_DETACHing. -+# sleepers is started with argument so that it will mostly sleep. -+prog: sleepers -+args: 1000000000 1000000000 1 BSBSBSBS -+vgopts: --tool=none --vgdb=yes --vgdb-error=0 --vgdb-prefix=./vgdb-prefix-nlvgdbsigqueue -+stderr_filter: filter_stderr -+prereq: test -e gdb -a -f vgdb.invoker -+progB: gdb -+argsB: --quiet -l 60 --nx ./sleepers -+stdinB: nlvgdbsigqueue.stdinB.gdb -+stdoutB_filter: filter_gdb -+stderrB_filter: filter_make_empty -Index: gdbserver_tests/send_signal -=================================================================== ---- gdbserver_tests/send_signal (.../tags/VALGRIND_3_9_0) (revision 0) -+++ gdbserver_tests/send_signal (.../trunk) (revision 13981) -@@ -0,0 +1,30 @@ -+#! /bin/sh -+ -+# send_signal sends signal $1 to the Valgrind process using prefix $2 in $3 seconds -+# If there are some args after $3, the rest of these args is a command and its arg -+# which is run every second. When this command is succesful, then the sleep and -+# the signal sending is done -+SIG=$1 -+shift -+PREFIX=$1 -+shift -+SLEEP=$1 -+shift -+GUARDCMD="$@" -+if [ "$GUARDCMD" = "" ] -+then -+ GUARDCMD="true" -+fi -+VPID=`./vgdb -l $PREFIX 2>&1 | awk '{print $2}' | sed -e 's/--pid=//'` -+if [ "$VPID" = "" ] -+then -+ echo "send_signal could not determine the valgrind pid with " $PREFIX -+ exit 1 -+fi -+(while ! $GUARDCMD >> garbage.filtered.out 2>&1 -+ do -+ sleep 1 -+ done -+ sleep $SLEEP -+ echo sending signal -+ kill -s $SIG $VPID) & - -Property changes on: gdbserver_tests/send_signal -___________________________________________________________________ -Added: svn:executable -## -0,0 +1 ## -+* -\ No newline at end of property -Index: gdbserver_tests/sleepers.c -=================================================================== ---- gdbserver_tests/sleepers.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ gdbserver_tests/sleepers.c (.../trunk) (revision 13981) -@@ -8,12 +8,12 @@ - #include - #include - #include -- -+#include - static int loops = 15; // each thread+main will do this amount of loop - static int sleepms = 1000; // in each loop, will sleep "sleepms" milliseconds - static int burn = 0; // after each sleep, will burn cpu in a tight 'burn' loop -+static void setup_sigusr_handler(void); // sigusr1 and 2 sigaction setup. - -- - static pid_t gettid() - { - #ifdef __NR_gettid -@@ -133,7 +133,7 @@ - struct spec b, l, p, m; - char *some_mem __attribute__((unused)) = malloc(100); - setaffinity(); -- -+ setup_sigusr_handler(); - if (argc > 1) - loops = atoi(argv[1]); - -@@ -194,3 +194,24 @@ - - return 0; - } -+ -+static int sigusr1_received = 0; -+static void sigusr1_handler(int signr) -+{ -+ sigusr1_received++; -+} -+static void setup_sigusr_handler(void) -+{ -+ struct sigaction sa; -+ sa.sa_handler = sigusr1_handler; -+ sigemptyset(&sa.sa_mask); -+ sa.sa_flags = 0; -+ -+ if (sigaction (SIGUSR1, &sa, NULL) != 0) -+ perror("sigaction SIGUSR1"); -+ -+ sa.sa_handler = SIG_IGN; -+ if (sigaction (SIGUSR2, &sa, NULL) != 0) -+ perror("sigaction SIGUSR2"); -+} -+ -Index: glibc-2.34567-NPTL-helgrind.supp -=================================================================== ---- glibc-2.34567-NPTL-helgrind.supp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ glibc-2.34567-NPTL-helgrind.supp (.../trunk) (revision 13981) -@@ -244,6 +244,15 @@ - # - # helgrind---ld.so-...-dlsym was merged into helgrind-glibc2X-001 - -+{ -+ helgrind---_dl_allocate_tls -+ Helgrind:Race -+ fun:mempcpy -+ fun:_dl_allocate_tls_init -+ fun:pthread_create@@GLIBC_2.2* -+ fun:pthread_create_WRK -+ fun:pthread_create@* -+} - - #################################################### - # To do with GNU libgomp -Index: helgrind/Makefile.am -=================================================================== ---- helgrind/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/Makefile.am (.../trunk) (revision 13981) -@@ -12,6 +12,7 @@ - pkginclude_HEADERS = helgrind.h - - noinst_HEADERS = \ -+ hg_addrdescr.h \ - hg_basics.h \ - hg_errors.h \ - hg_lock_n_thread.h \ -@@ -28,6 +29,7 @@ - endif - - HELGRIND_SOURCES_COMMON = \ -+ hg_addrdescr.c \ - hg_basics.c \ - hg_errors.c \ - hg_lock_n_thread.c \ -Index: helgrind/docs/hg-manual.xml -=================================================================== ---- helgrind/docs/hg-manual.xml (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/docs/hg-manual.xml (.../trunk) (revision 13981) -@@ -1254,7 +1254,56 @@ - - - -+ -+Helgrind Monitor Commands -+The Helgrind tool provides monitor commands handled by Valgrind's -+built-in gdbserver (see ). -+ -+ -+ -+ info locks shows the list of locks and their -+ status. -+ -+ In the following example, helgrind knows about one lock. -+ This lock is located at the guest address ga 0x8049a20. -+ The lock kind is rdwr indicating a reader-writer lock. -+ Other possible lock kinds are nonRec (simple mutex, non recursive) -+ and mbRec (simple mutex, possibly recursive). -+ The lock kind is then followed by the list of threads helding the lock. -+ In the below example, R1:thread #6 tid 3 indicates that the -+ helgrind thread #6 has acquired (once, as the counter following the letter R is one) -+ the lock in read mode. The helgrind thread nr is incremented for each started thread. -+ The presence of 'tid 3' indicates that the thread #6 is has not exited yet and is the -+ valgrind tid 3. If a thread has terminated, then this is indicated with 'tid (exited)'. -+ -+ - -+ If you give the option --read-var-info=yes, then more -+ information will be provided about the lock location, such as the global variable -+ or the heap block that contains the lock: -+ -+ -+ -+ -+ -+ -+ -+ -+ - - Helgrind Client Requests - -Index: helgrind/hg_addrdescr.c -=================================================================== ---- helgrind/hg_addrdescr.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ helgrind/hg_addrdescr.c (.../trunk) (revision 13981) -@@ -0,0 +1,98 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Address Description. ---*/ -+/*--- hg_addrdescr.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Helgrind, a Valgrind tool for detecting errors -+ in threaded programs. -+ -+ Copyright (C) 2007-2012 OpenWorks Ltd -+ info@open-works.co.uk -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+#include "pub_tool_basics.h" -+#include "pub_tool_libcbase.h" -+#include "pub_tool_libcprint.h" -+#include "pub_tool_libcassert.h" -+#include "pub_tool_xarray.h" -+#include "pub_tool_execontext.h" -+#include "pub_tool_debuginfo.h" -+#include "pub_tool_threadstate.h" -+#include "pub_tool_addrinfo.h" -+ -+#include "hg_basics.h" -+#include "hg_addrdescr.h" /* self */ -+ -+void HG_(describe_addr) ( Addr a, /*OUT*/AddrInfo* ai ) -+{ -+ tl_assert(ai->tag == Addr_Undescribed); -+ -+ /* hctxt/haddr/hszB describe the addr if it is a heap block. */ -+ ExeContext* hctxt; -+ Addr haddr; -+ SizeT hszB; -+ -+ /* First, see if it's in any heap block. Unfortunately this -+ means a linear search through all allocated heap blocks. The -+ assertion says that if it's detected as a heap block, then we -+ must have an allocation context for it, since all heap blocks -+ should have an allocation context. */ -+ Bool is_heapblock -+ = HG_(mm_find_containing_block)( -+ &hctxt, -+ &haddr, -+ &hszB, -+ a -+ ); -+ if (is_heapblock) { -+ tl_assert(is_heapblock == (hctxt != NULL)); -+ ai->tag = Addr_Block; -+ ai->Addr.Block.block_kind = Block_Mallocd; -+ ai->Addr.Block.block_desc = "block"; -+ ai->Addr.Block.block_szB = hszB; -+ ai->Addr.Block.rwoffset = (Word)(a) - (Word)(haddr); -+ ai->Addr.Block.allocated_at = hctxt; -+ ai->Addr.Block.freed_at = VG_(null_ExeContext)();; -+ } else { -+ /* No block found. Search a non-heap block description. */ -+ VG_(describe_addr) (a, ai); -+ } -+} -+ -+Bool HG_(get_and_pp_addrdescr) (Addr addr) -+{ -+ -+ Bool ret; -+ AddrInfo glai; -+ -+ glai.tag = Addr_Undescribed; -+ HG_(describe_addr) (addr, &glai); -+ VG_(pp_addrinfo) (addr, &glai); -+ ret = glai.tag != Addr_Unknown; -+ -+ VG_(clear_addrinfo) (&glai); -+ -+ return ret; -+} -+ -+/*--------------------------------------------------------------------*/ -+/*--- end hg_addrdescr.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: helgrind/hg_addrdescr.h -=================================================================== ---- helgrind/hg_addrdescr.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ helgrind/hg_addrdescr.h (.../trunk) (revision 13981) -@@ -0,0 +1,71 @@ -+ -+/*---------------------------------------------------------------------*/ -+/*--- Address Description, used e.g. to describe addresses involved ---*/ -+/*--- in race conditions, locks. ---*/ -+/*--- hg_addrdescr.h ---*/ -+/*---------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Helgrind, a Valgrind tool for detecting errors -+ in threaded programs. -+ -+ Copyright (C) 2007-2012 OpenWorks Ltd -+ info@open-works.co.uk -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __HG_ADDRDESCR_H -+#define __HG_ADDRDESCR_H -+ -+/* Describe an address as best you can, for error messages or -+ lock description, putting the result in ai. -+ This might allocate some memory in ai, to be cleared with -+ VG_(clear_addrinfo). */ -+extern void HG_(describe_addr) ( Addr a, /*OUT*/AddrInfo* ai ); -+ -+/* Prints (using *print) the readable description of addr given in ai. -+ "what" identifies the type pointed to by addr (e.g. a lock). */ -+extern void HG_(pp_addrdescr) (Bool xml, const HChar* what, Addr addr, -+ AddrInfo* ai, -+ void(*print)(const HChar *format, ...)); -+ -+/* Get a readable description of addr, then print it using HG_(pp_addrdescr) -+ using xml False and VG_(printf) to emit the characters. -+ Returns True if a description was found/printed, False otherwise. */ -+extern Bool HG_(get_and_pp_addrdescr) (Addr a); -+ -+/* For error creation/address description: -+ map 'data_addr' to a malloc'd chunk, if any. -+ Slow linear search accelerated in some special cases normal hash -+ search of the mallocmeta table. This is an abuse of the normal file -+ structure since this is exported by hg_main.c, not hg_addrdesc.c. Oh -+ Well. Returns True if found, False if not. Zero-sized blocks are -+ considered to contain the searched-for address if they equal that -+ address. */ -+Bool HG_(mm_find_containing_block)( /*OUT*/ExeContext** where, -+ /*OUT*/Addr* payload, -+ /*OUT*/SizeT* szB, -+ Addr data_addr ); -+ -+ -+#endif /* ! __HG_ADDRDESCR_H */ -+ -+/*--------------------------------------------------------------------*/ -+/*--- end hg_addrdescr.h ---*/ -+/*--------------------------------------------------------------------*/ -Index: helgrind/hg_errors.c -=================================================================== ---- helgrind/hg_errors.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/hg_errors.c (.../trunk) (revision 13981) -@@ -40,8 +40,10 @@ - #include "pub_tool_debuginfo.h" - #include "pub_tool_threadstate.h" - #include "pub_tool_options.h" // VG_(clo_xml) -+#include "pub_tool_addrinfo.h" - - #include "hg_basics.h" -+#include "hg_addrdescr.h" - #include "hg_wordset.h" - #include "hg_lock_n_thread.h" - #include "libhb.h" -@@ -291,16 +293,10 @@ - struct { - Addr data_addr; - Int szB; -+ AddrInfo data_addrinfo; - Bool isWrite; - Thread* thr; - Lock** locksHeldW; -- /* descr1/2 provide a description of stack/global locs */ -- XArray* descr1; /* XArray* of HChar */ -- XArray* descr2; /* XArray* of HChar */ -- /* halloc/haddr/hszB describe the addr if it is a heap block. */ -- ExeContext* hctxt; -- Addr haddr; -- SizeT hszB; - /* h1_* and h2_* provide some description of a previously - observed access with which we are conflicting. */ - Thread* h1_ct; /* non-NULL means h1 info present */ -@@ -411,53 +407,8 @@ - VG_(printf)("HG_(update_extra): " - "%d conflicting-event queries\n", xxx); - -- tl_assert(!xe->XE.Race.hctxt); -- tl_assert(!xe->XE.Race.descr1); -- tl_assert(!xe->XE.Race.descr2); -+ HG_(describe_addr) (xe->XE.Race.data_addr, &xe->XE.Race.data_addrinfo); - -- /* First, see if it's in any heap block. Unfortunately this -- means a linear search through all allocated heap blocks. The -- assertion says that if it's detected as a heap block, then we -- must have an allocation context for it, since all heap blocks -- should have an allocation context. */ -- Bool is_heapblock -- = HG_(mm_find_containing_block)( -- &xe->XE.Race.hctxt, &xe->XE.Race.haddr, &xe->XE.Race.hszB, -- xe->XE.Race.data_addr -- ); -- tl_assert(is_heapblock == (xe->XE.Race.hctxt != NULL)); -- -- if (!xe->XE.Race.hctxt) { -- /* It's not in any heap block. See if we can map it to a -- stack or global symbol. */ -- -- xe->XE.Race.descr1 -- = VG_(newXA)( HG_(zalloc), "hg.update_extra.Race.descr1", -- HG_(free), sizeof(HChar) ); -- xe->XE.Race.descr2 -- = VG_(newXA)( HG_(zalloc), "hg.update_extra.Race.descr2", -- HG_(free), sizeof(HChar) ); -- -- (void) VG_(get_data_description)( xe->XE.Race.descr1, -- xe->XE.Race.descr2, -- xe->XE.Race.data_addr ); -- -- /* If there's nothing in descr1/2, free it. Why is it safe to -- to VG_(indexXA) at zero here? Because -- VG_(get_data_description) guarantees to zero terminate -- descr1/2 regardless of the outcome of the call. So there's -- always at least one element in each XA after the call. -- */ -- if (0 == VG_(strlen)( VG_(indexXA)( xe->XE.Race.descr1, 0 ))) { -- VG_(deleteXA)( xe->XE.Race.descr1 ); -- xe->XE.Race.descr1 = NULL; -- } -- if (0 == VG_(strlen)( VG_(indexXA)( xe->XE.Race.descr2, 0 ))) { -- VG_(deleteXA)( xe->XE.Race.descr2 ); -- xe->XE.Race.descr2 = NULL; -- } -- } -- - /* And poke around in the conflicting-event map, to see if we - can rustle up a plausible-looking conflicting memory access - to show. */ -@@ -538,8 +489,7 @@ - /* Skip on the detailed description of the raced-on address at this - point; it's expensive. Leave it for the update_extra function - if we ever make it that far. */ -- tl_assert(xe.XE.Race.descr1 == NULL); -- tl_assert(xe.XE.Race.descr2 == NULL); -+ xe.XE.Race.data_addrinfo.tag = Addr_Undescribed; - // FIXME: tid vs thr - // Skip on any of the conflicting-access info at this point. - // It's expensive to obtain, and this error is more likely than -@@ -807,7 +757,6 @@ - return True; - } - -- - /* Announce 'lk'. */ - static void announce_LockP ( Lock* lk ) - { -@@ -1284,47 +1233,7 @@ - } - - } -- -- /* If we have a description of the address in terms of a heap -- block, show it. */ -- if (xe->XE.Race.hctxt) { -- SizeT delta = err_ga - xe->XE.Race.haddr; -- if (xml) { -- emit(" Address %p is %ld bytes inside a block " -- "of size %ld alloc'd\n", (void*)err_ga, delta, -- xe->XE.Race.hszB); -- VG_(pp_ExeContext)( xe->XE.Race.hctxt ); -- } else { -- emit("\n"); -- emit("Address %p is %ld bytes inside a block " -- "of size %ld alloc'd\n", (void*)err_ga, delta, -- xe->XE.Race.hszB); -- VG_(pp_ExeContext)( xe->XE.Race.hctxt ); -- } -- } -- -- /* If we have a better description of the address, show it. -- Note that in XML mode, it will already by nicely wrapped up -- in tags, either or , so we can just emit -- it verbatim. */ -- if (xml) { -- if (xe->XE.Race.descr1) -- emit( " %s\n", -- (HChar*)VG_(indexXA)( xe->XE.Race.descr1, 0 ) ); -- if (xe->XE.Race.descr2) -- emit( " %s\n", -- (HChar*)VG_(indexXA)( xe->XE.Race.descr2, 0 ) ); -- } else { -- if (xe->XE.Race.descr1 || xe->XE.Race.descr2) -- emit("\n"); -- if (xe->XE.Race.descr1) -- emit( "%s\n", -- (HChar*)VG_(indexXA)( xe->XE.Race.descr1, 0 ) ); -- if (xe->XE.Race.descr2) -- emit( "%s\n", -- (HChar*)VG_(indexXA)( xe->XE.Race.descr2, 0 ) ); -- } -- -+ VG_(pp_addrinfo) (err_ga, &xe->XE.Race.data_addrinfo); - break; /* case XE_Race */ - } /* case XE_Race */ - -Index: helgrind/hg_errors.h -=================================================================== ---- helgrind/hg_errors.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/hg_errors.h (.../trunk) (revision 13981) -@@ -79,18 +79,6 @@ - extern ULong HG_(stats__string_table_queries); - extern ULong HG_(stats__string_table_get_map_size) ( void ); - --/* For error creation: map 'data_addr' to a malloc'd chunk, if any. -- Slow linear search accelerated in some special cases normal hash -- search of the mallocmeta table. This is an abuse of the normal file -- structure since this is exported by hg_main.c, not hg_errors.c. Oh -- Well. Returns True if found, False if not. Zero-sized blocks are -- considered to contain the searched-for address if they equal that -- address. */ --Bool HG_(mm_find_containing_block)( /*OUT*/ExeContext** where, -- /*OUT*/Addr* payload, -- /*OUT*/SizeT* szB, -- Addr data_addr ); -- - #endif /* ! __HG_ERRORS_H */ - - /*--------------------------------------------------------------------*/ -Index: helgrind/hg_intercepts.c -=================================================================== ---- helgrind/hg_intercepts.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/hg_intercepts.c (.../trunk) (revision 13981) -@@ -2434,202 +2434,8 @@ - /*--- overrun the input arrays. ---*/ - /*----------------------------------------------------------------*/ - --/* Copied verbatim from memcheck/mc_replace_strmem.c. When copying -- new functions, please keep them in the same order as they appear in -- mc_replace_strmem.c. */ -+#include "../shared/vg_replace_strmem.c" - -- --#define STRCHR(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* s, int c ); \ -- char* VG_REPLACE_FUNCTION_ZU(soname,fnname) ( const char* s, int c ) \ -- { \ -- HChar ch = (HChar)c ; \ -- const HChar* p = s; \ -- while (True) { \ -- if (*p == ch) return (HChar *)p; \ -- if (*p == 0) return NULL; \ -- p++; \ -- } \ -- } -- --// Apparently index() is the same thing as strchr() --#if defined(VGO_linux) -- STRCHR(VG_Z_LIBC_SONAME, strchr) -- STRCHR(VG_Z_LIBC_SONAME, index) -- STRCHR(VG_Z_LD_LINUX_SO_2, strchr) -- STRCHR(VG_Z_LD_LINUX_SO_2, index) -- STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, strchr) -- STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, index) --#elif defined(VGO_darwin) -- STRCHR(VG_Z_LIBC_SONAME, strchr) -- STRCHR(VG_Z_LIBC_SONAME, index) --#endif -- -- --// Note that this replacement often doesn't get used because gcc inlines --// calls to strlen() with its own built-in version. This can be very --// confusing if you aren't expecting it. Other small functions in this file --// may also be inline by gcc. --#define STRLEN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname)( const char* str ); \ -- SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname)( const char* str ) \ -- { \ -- SizeT i = 0; \ -- while (str[i] != 0) i++; \ -- return i; \ -- } -- --#if defined(VGO_linux) -- STRLEN(VG_Z_LIBC_SONAME, strlen) -- STRLEN(VG_Z_LD_LINUX_SO_2, strlen) -- STRLEN(VG_Z_LD_LINUX_X86_64_SO_2, strlen) --#elif defined(VGO_darwin) -- STRLEN(VG_Z_LIBC_SONAME, strlen) --#endif -- -- --#define STRCPY(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_ZU(soname, fnname) ( char* dst, const char* src ); \ -- char* VG_REPLACE_FUNCTION_ZU(soname, fnname) ( char* dst, const char* src ) \ -- { \ -- HChar* dst_orig = dst; \ -- \ -- while (*src) *dst++ = *src++; \ -- *dst = 0; \ -- \ -- return dst_orig; \ -- } -- --#if defined(VGO_linux) -- STRCPY(VG_Z_LIBC_SONAME, strcpy) --#elif defined(VGO_darwin) -- STRCPY(VG_Z_LIBC_SONAME, strcpy) --#endif -- -- --#define STRCMP(soname, fnname) \ -- int VG_REPLACE_FUNCTION_ZU(soname,fnname) \ -- ( const char* s1, const char* s2 ); \ -- int VG_REPLACE_FUNCTION_ZU(soname,fnname) \ -- ( const char* s1, const char* s2 ) \ -- { \ -- register UChar c1; \ -- register UChar c2; \ -- while (True) { \ -- c1 = *(UChar *)s1; \ -- c2 = *(UChar *)s2; \ -- if (c1 != c2) break; \ -- if (c1 == 0) break; \ -- s1++; s2++; \ -- } \ -- if ((UChar)c1 < (UChar)c2) return -1; \ -- if ((UChar)c1 > (UChar)c2) return 1; \ -- return 0; \ -- } -- --#if defined(VGO_linux) -- STRCMP(VG_Z_LIBC_SONAME, strcmp) -- STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp) -- STRCMP(VG_Z_LD64_SO_1, strcmp) --#elif defined(VGO_darwin) -- STRCMP(VG_Z_LIBC_SONAME, strcmp) --#endif -- -- --#define MEMCPY(soname, fnname) \ -- void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ -- ( void *dst, const void *src, SizeT len ); \ -- void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \ -- ( void *dst, const void *src, SizeT len ) \ -- { \ -- const Addr WS = sizeof(UWord); /* 8 or 4 */ \ -- const Addr WM = WS - 1; /* 7 or 3 */ \ -- \ -- if (len > 0) { \ -- if (dst < src) { \ -- \ -- /* Copying backwards. */ \ -- SizeT n = len; \ -- Addr d = (Addr)dst; \ -- Addr s = (Addr)src; \ -- \ -- if (((s^d) & WM) == 0) { \ -- /* s and d have same UWord alignment. */ \ -- /* Pull up to a UWord boundary. */ \ -- while ((s & WM) != 0 && n >= 1) \ -- { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ -- /* Copy UWords. */ \ -- while (n >= WS) \ -- { *(UWord*)d = *(UWord*)s; s += WS; d += WS; n -= WS; } \ -- if (n == 0) \ -- return dst; \ -- } \ -- if (((s|d) & 1) == 0) { \ -- /* Both are 16-aligned; copy what we can thusly. */ \ -- while (n >= 2) \ -- { *(UShort*)d = *(UShort*)s; s += 2; d += 2; n -= 2; } \ -- } \ -- /* Copy leftovers, or everything if misaligned. */ \ -- while (n >= 1) \ -- { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ -- \ -- } else if (dst > src) { \ -- \ -- SizeT n = len; \ -- Addr d = ((Addr)dst) + n; \ -- Addr s = ((Addr)src) + n; \ -- \ -- /* Copying forwards. */ \ -- if (((s^d) & WM) == 0) { \ -- /* s and d have same UWord alignment. */ \ -- /* Back down to a UWord boundary. */ \ -- while ((s & WM) != 0 && n >= 1) \ -- { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ -- /* Copy UWords. */ \ -- while (n >= WS) \ -- { s -= WS; d -= WS; *(UWord*)d = *(UWord*)s; n -= WS; } \ -- if (n == 0) \ -- return dst; \ -- } \ -- if (((s|d) & 1) == 0) { \ -- /* Both are 16-aligned; copy what we can thusly. */ \ -- while (n >= 2) \ -- { s -= 2; d -= 2; *(UShort*)d = *(UShort*)s; n -= 2; } \ -- } \ -- /* Copy leftovers, or everything if misaligned. */ \ -- while (n >= 1) \ -- { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ -- \ -- } \ -- } \ -- \ -- return dst; \ -- } -- --#if defined(VGO_linux) -- MEMCPY(VG_Z_LIBC_SONAME, memcpy) -- MEMCPY(VG_Z_LD_SO_1, memcpy) /* ld.so.1 */ -- MEMCPY(VG_Z_LD64_SO_1, memcpy) /* ld64.so.1 */ -- /* icc9 blats these around all over the place. Not only in the main -- executable but various .so's. They are highly tuned and read -- memory beyond the source boundary (although work correctly and -- never go across page boundaries), so give errors when run -- natively, at least for misaligned source arg. Just intercepting -- in the exe only until we understand more about the problem. See -- http://bugs.kde.org/show_bug.cgi?id=139776 -- */ -- MEMCPY(NONE, _intel_fast_memcpy) -- --#elif defined(VGO_darwin) --# if DARWIN_VERS <= DARWIN_10_6 -- MEMCPY(VG_Z_LIBC_SONAME, memcpy) --# endif -- MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse3x) /* memcpy$VARIANT$sse3x */ -- MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse42) /* memcpy$VARIANT$sse42 */ -- --#endif -- -- - /*--------------------------------------------------------------------*/ - /*--- end hg_intercepts.c ---*/ - /*--------------------------------------------------------------------*/ -Index: helgrind/hg_main.c -=================================================================== ---- helgrind/hg_main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/hg_main.c (.../trunk) (revision 13981) -@@ -37,6 +37,7 @@ - */ - - #include "pub_tool_basics.h" -+#include "pub_tool_gdbserver.h" - #include "pub_tool_libcassert.h" - #include "pub_tool_libcbase.h" - #include "pub_tool_libcprint.h" -@@ -54,9 +55,12 @@ - #include "pub_tool_vki.h" // VKI_PAGE_SIZE - #include "pub_tool_libcproc.h" // VG_(atfork) - #include "pub_tool_aspacemgr.h" // VG_(am_is_valid_for_client) -+#include "pub_tool_poolalloc.h" -+#include "pub_tool_addrinfo.h" - - #include "hg_basics.h" - #include "hg_wordset.h" -+#include "hg_addrdescr.h" - #include "hg_lock_n_thread.h" - #include "hg_errors.h" - -@@ -456,29 +460,61 @@ - } - } - --static void pp_Lock ( Int d, Lock* lk ) -+/* Pretty Print lock lk. -+ if show_lock_addrdescr, describes the (guest) lock address. -+ (this description will be more complete with --read-var-info=yes). -+ if show_internal_data, shows also helgrind internal information. -+ d is the level at which output is indented. */ -+static void pp_Lock ( Int d, Lock* lk, -+ Bool show_lock_addrdescr, -+ Bool show_internal_data) - { -- space(d+0); VG_(printf)("Lock %p (ga %#lx) {\n", lk, lk->guestaddr); -+ space(d+0); -+ if (show_internal_data) -+ VG_(printf)("Lock %p (ga %#lx) {\n", lk, lk->guestaddr); -+ else -+ VG_(printf)("Lock ga %#lx {\n", lk->guestaddr); -+ if (!show_lock_addrdescr -+ || !HG_(get_and_pp_addrdescr) ((Addr) lk->guestaddr)) -+ VG_(printf)("\n"); -+ - if (sHOW_ADMIN) { - space(d+3); VG_(printf)("admin_n %p\n", lk->admin_next); - space(d+3); VG_(printf)("admin_p %p\n", lk->admin_prev); - space(d+3); VG_(printf)("magic 0x%x\n", (UInt)lk->magic); - } -- space(d+3); VG_(printf)("unique %llu\n", lk->unique); -+ if (show_internal_data) { -+ space(d+3); VG_(printf)("unique %llu\n", lk->unique); -+ } - space(d+3); VG_(printf)("kind %s\n", show_LockKind(lk->kind)); -- space(d+3); VG_(printf)("heldW %s\n", lk->heldW ? "yes" : "no"); -- space(d+3); VG_(printf)("heldBy %p", lk->heldBy); -+ if (show_internal_data) { -+ space(d+3); VG_(printf)("heldW %s\n", lk->heldW ? "yes" : "no"); -+ } -+ if (show_internal_data) { -+ space(d+3); VG_(printf)("heldBy %p", lk->heldBy); -+ } - if (lk->heldBy) { - Thread* thr; - UWord count; - VG_(printf)(" { "); - VG_(initIterBag)( lk->heldBy ); -- while (VG_(nextIterBag)( lk->heldBy, (UWord*)&thr, &count )) -- VG_(printf)("%lu:%p ", count, thr); -+ while (VG_(nextIterBag)( lk->heldBy, (UWord*)&thr, &count )) { -+ if (show_internal_data) -+ VG_(printf)("%lu:%p ", count, thr); -+ else { -+ VG_(printf)("%c%lu:thread #%d ", -+ lk->heldW ? 'W' : 'R', -+ count, thr->errmsg_index); -+ if (thr->coretid == VG_INVALID_THREADID) -+ VG_(printf)("tid (exited) "); -+ else -+ VG_(printf)("tid %d ", thr->coretid); -+ -+ } -+ } - VG_(doneIterBag)( lk->heldBy ); -- VG_(printf)("}"); -+ VG_(printf)("}\n"); - } -- VG_(printf)("\n"); - space(d+0); VG_(printf)("}\n"); - } - -@@ -495,12 +531,14 @@ - space(n); - VG_(printf)("admin_locks record %d of %d:\n", i, n); - } -- pp_Lock(d+3, lk); -+ pp_Lock(d+3, lk, -+ False /* show_lock_addrdescr */, -+ True /* show_internal_data */); - } - space(d); VG_(printf)("}\n"); - } - --static void pp_map_locks ( Int d ) -+static void pp_map_locks ( Int d) - { - void* gla; - Lock* lk; -@@ -3943,14 +3981,17 @@ - (obviously). */ - static VgHashTable hg_mallocmeta_table = NULL; - -+/* MallocMeta are small elements. We use a pool to avoid -+ the overhead of malloc for each MallocMeta. */ -+static PoolAlloc *MallocMeta_poolalloc = NULL; - - static MallocMeta* new_MallocMeta ( void ) { -- MallocMeta* md = HG_(zalloc)( "hg.new_MallocMeta.1", sizeof(MallocMeta) ); -- tl_assert(md); -+ MallocMeta* md = VG_(allocEltPA) (MallocMeta_poolalloc); -+ VG_(memset)(md, 0, sizeof(MallocMeta)); - return md; - } - static void delete_MallocMeta ( MallocMeta* md ) { -- HG_(free)(md); -+ VG_(freeEltPA)(MallocMeta_poolalloc, md); - } - - -@@ -4699,11 +4740,76 @@ - } - } - -+static void print_monitor_help ( void ) -+{ -+ VG_(gdb_printf) -+ ( -+"\n" -+"helgrind monitor commands:\n" -+" info locks : show list of locks and their status\n" -+"\n"); -+} - -+/* return True if request recognised, False otherwise */ -+static Bool handle_gdb_monitor_command (ThreadId tid, HChar *req) -+{ -+ HChar* wcmd; -+ HChar s[VG_(strlen(req))]; /* copy for strtok_r */ -+ HChar *ssaveptr; -+ Int kwdid; -+ -+ VG_(strcpy) (s, req); -+ -+ wcmd = VG_(strtok_r) (s, " ", &ssaveptr); -+ /* NB: if possible, avoid introducing a new command below which -+ starts with the same first letter(s) as an already existing -+ command. This ensures a shorter abbreviation for the user. */ -+ switch (VG_(keyword_id) -+ ("help info", -+ wcmd, kwd_report_duplicated_matches)) { -+ case -2: /* multiple matches */ -+ return True; -+ case -1: /* not found */ -+ return False; -+ case 0: /* help */ -+ print_monitor_help(); -+ return True; -+ case 1: /* info */ -+ wcmd = VG_(strtok_r) (NULL, " ", &ssaveptr); -+ switch (kwdid = VG_(keyword_id) -+ ("locks", -+ wcmd, kwd_report_all)) { -+ case -2: -+ case -1: -+ break; -+ case 0: // locks -+ { -+ Int i; -+ Lock* lk; -+ for (i = 0, lk = admin_locks; lk; i++, lk = lk->admin_next) { -+ pp_Lock(0, lk, -+ True /* show_lock_addrdescr */, -+ False /* show_internal_data */); -+ } -+ if (i == 0) -+ VG_(gdb_printf) ("no locks\n"); -+ } -+ break; -+ default: -+ tl_assert(0); -+ } -+ return True; -+ default: -+ tl_assert(0); -+ return False; -+ } -+} -+ - static - Bool hg_handle_client_request ( ThreadId tid, UWord* args, UWord* ret) - { -- if (!VG_IS_TOOL_USERREQ('H','G',args[0])) -+ if (!VG_IS_TOOL_USERREQ('H','G',args[0]) -+ && VG_USERREQ__GDB_MONITOR_COMMAND != args[0]) - return False; - - /* Anything that gets past the above check is one of ours, so we -@@ -5017,6 +5123,15 @@ - evh__HG_USERSO_FORGET_ALL( tid, args[1] ); - break; - -+ case VG_USERREQ__GDB_MONITOR_COMMAND: { -+ Bool handled = handle_gdb_monitor_command (tid, (HChar*)args[1]); -+ if (handled) -+ *ret = 1; -+ else -+ *ret = 0; -+ return handled; -+ } -+ - default: - /* Unhandled Helgrind client request! */ - tl_assert2(0, "unhandled Helgrind client request 0x%lx", -@@ -5129,6 +5244,67 @@ - ); - } - -+static void hg_print_stats (void) -+{ -+ -+ if (1) { -+ VG_(printf)("\n"); -+ HG_(ppWSUstats)( univ_lsets, "univ_lsets" ); -+ if (HG_(clo_track_lockorders)) { -+ VG_(printf)("\n"); -+ HG_(ppWSUstats)( univ_laog, "univ_laog" ); -+ } -+ } -+ -+ //zz VG_(printf)("\n"); -+ //zz VG_(printf)(" hbefore: %'10lu queries\n", stats__hbefore_queries); -+ //zz VG_(printf)(" hbefore: %'10lu cache 0 hits\n", stats__hbefore_cache0s); -+ //zz VG_(printf)(" hbefore: %'10lu cache > 0 hits\n", stats__hbefore_cacheNs); -+ //zz VG_(printf)(" hbefore: %'10lu graph searches\n", stats__hbefore_gsearches); -+ //zz VG_(printf)(" hbefore: %'10lu of which slow\n", -+ //zz stats__hbefore_gsearches - stats__hbefore_gsearchFs); -+ //zz VG_(printf)(" hbefore: %'10lu stack high water mark\n", -+ //zz stats__hbefore_stk_hwm); -+ //zz VG_(printf)(" hbefore: %'10lu cache invals\n", stats__hbefore_invals); -+ //zz VG_(printf)(" hbefore: %'10lu probes\n", stats__hbefore_probes); -+ -+ VG_(printf)("\n"); -+ VG_(printf)(" locksets: %'8d unique lock sets\n", -+ (Int)HG_(cardinalityWSU)( univ_lsets )); -+ if (HG_(clo_track_lockorders)) { -+ VG_(printf)(" univ_laog: %'8d unique lock sets\n", -+ (Int)HG_(cardinalityWSU)( univ_laog )); -+ } -+ -+ //VG_(printf)("L(ast)L(ock) map: %'8lu inserts (%d map size)\n", -+ // stats__ga_LL_adds, -+ // (Int)(ga_to_lastlock ? VG_(sizeFM)( ga_to_lastlock ) : 0) ); -+ -+ VG_(printf)(" LockN-to-P map: %'8llu queries (%llu map size)\n", -+ HG_(stats__LockN_to_P_queries), -+ HG_(stats__LockN_to_P_get_map_size)() ); -+ -+ VG_(printf)("string table map: %'8llu queries (%llu map size)\n", -+ HG_(stats__string_table_queries), -+ HG_(stats__string_table_get_map_size)() ); -+ if (HG_(clo_track_lockorders)) { -+ VG_(printf)(" LAOG: %'8d map size\n", -+ (Int)(laog ? VG_(sizeFM)( laog ) : 0)); -+ VG_(printf)(" LAOG exposition: %'8d map size\n", -+ (Int)(laog_exposition ? VG_(sizeFM)( laog_exposition ) : 0)); -+ } -+ -+ VG_(printf)(" locks: %'8lu acquires, " -+ "%'lu releases\n", -+ stats__lockN_acquires, -+ stats__lockN_releases -+ ); -+ VG_(printf)(" sanity checks: %'8lu\n", stats__sanity_checks); -+ -+ VG_(printf)("\n"); -+ libhb_shutdown(True); // This in fact only print stats. -+} -+ - static void hg_fini ( Int exitcode ) - { - if (VG_(clo_verbosity) == 1 && !VG_(clo_xml)) { -@@ -5150,65 +5326,8 @@ - if (HG_(clo_sanity_flags)) - all__sanity_check("SK_(fini)"); - -- if (VG_(clo_stats)) { -- -- if (1) { -- VG_(printf)("\n"); -- HG_(ppWSUstats)( univ_lsets, "univ_lsets" ); -- if (HG_(clo_track_lockorders)) { -- VG_(printf)("\n"); -- HG_(ppWSUstats)( univ_laog, "univ_laog" ); -- } -- } -- -- //zz VG_(printf)("\n"); -- //zz VG_(printf)(" hbefore: %'10lu queries\n", stats__hbefore_queries); -- //zz VG_(printf)(" hbefore: %'10lu cache 0 hits\n", stats__hbefore_cache0s); -- //zz VG_(printf)(" hbefore: %'10lu cache > 0 hits\n", stats__hbefore_cacheNs); -- //zz VG_(printf)(" hbefore: %'10lu graph searches\n", stats__hbefore_gsearches); -- //zz VG_(printf)(" hbefore: %'10lu of which slow\n", -- //zz stats__hbefore_gsearches - stats__hbefore_gsearchFs); -- //zz VG_(printf)(" hbefore: %'10lu stack high water mark\n", -- //zz stats__hbefore_stk_hwm); -- //zz VG_(printf)(" hbefore: %'10lu cache invals\n", stats__hbefore_invals); -- //zz VG_(printf)(" hbefore: %'10lu probes\n", stats__hbefore_probes); -- -- VG_(printf)("\n"); -- VG_(printf)(" locksets: %'8d unique lock sets\n", -- (Int)HG_(cardinalityWSU)( univ_lsets )); -- if (HG_(clo_track_lockorders)) { -- VG_(printf)(" univ_laog: %'8d unique lock sets\n", -- (Int)HG_(cardinalityWSU)( univ_laog )); -- } -- -- //VG_(printf)("L(ast)L(ock) map: %'8lu inserts (%d map size)\n", -- // stats__ga_LL_adds, -- // (Int)(ga_to_lastlock ? VG_(sizeFM)( ga_to_lastlock ) : 0) ); -- -- VG_(printf)(" LockN-to-P map: %'8llu queries (%llu map size)\n", -- HG_(stats__LockN_to_P_queries), -- HG_(stats__LockN_to_P_get_map_size)() ); -- -- VG_(printf)("string table map: %'8llu queries (%llu map size)\n", -- HG_(stats__string_table_queries), -- HG_(stats__string_table_get_map_size)() ); -- if (HG_(clo_track_lockorders)) { -- VG_(printf)(" LAOG: %'8d map size\n", -- (Int)(laog ? VG_(sizeFM)( laog ) : 0)); -- VG_(printf)(" LAOG exposition: %'8d map size\n", -- (Int)(laog_exposition ? VG_(sizeFM)( laog_exposition ) : 0)); -- } -- -- VG_(printf)(" locks: %'8lu acquires, " -- "%'lu releases\n", -- stats__lockN_acquires, -- stats__lockN_releases -- ); -- VG_(printf)(" sanity checks: %'8lu\n", stats__sanity_checks); -- -- VG_(printf)("\n"); -- libhb_shutdown(True); -- } -+ if (VG_(clo_stats)) -+ hg_print_stats(); - } - - /* FIXME: move these somewhere sane */ -@@ -5262,6 +5381,11 @@ - initialise_data_structures(hbthr_root); - } - -+static void hg_info_location (Addr a) -+{ -+ (void) HG_(get_and_pp_addrdescr) (a); -+} -+ - static void hg_pre_clo_init ( void ) - { - VG_(details_name) ("Helgrind"); -@@ -5301,6 +5425,9 @@ - //VG_(needs_sanity_checks) (hg_cheap_sanity_check, - // hg_expensive_sanity_check); - -+ VG_(needs_print_stats) (hg_print_stats); -+ VG_(needs_info_location) (hg_info_location); -+ - VG_(needs_malloc_replacement) (hg_cli__malloc, - hg_cli____builtin_new, - hg_cli____builtin_vec_new, -@@ -5359,6 +5486,12 @@ - hg_mallocmeta_table - = VG_(HT_construct)( "hg_malloc_metadata_table" ); - -+ MallocMeta_poolalloc = VG_(newPA) ( sizeof(MallocMeta), -+ 1000, -+ HG_(zalloc), -+ "hg_malloc_metadata_pool", -+ HG_(free)); -+ - // add a callback to clean up on (threaded) fork. - VG_(atfork)(NULL/*pre*/, NULL/*parent*/, evh__atfork_child/*child*/); - } -Index: helgrind/libhb_core.c -=================================================================== ---- helgrind/libhb_core.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/libhb_core.c (.../trunk) (revision 13981) -@@ -3668,14 +3668,11 @@ - thr->llexit_done = False; - thr->joinedwith_done = False; - thr->filter = HG_(zalloc)( "libhb.Thr__new.2", sizeof(Filter) ); -- /* We only really need this at history level 1, but unfortunately -- this routine is called before the command line processing is -- done (sigh), so we can't rely on HG_(clo_history_level) at this -- point. Hence always allocate it. Bah. */ -- thr->local_Kws_n_stacks -- = VG_(newXA)( HG_(zalloc), -- "libhb.Thr__new.3 (local_Kws_and_stacks)", -- HG_(free), sizeof(ULong_n_EC) ); -+ if (HG_(clo_history_level) == 1) -+ thr->local_Kws_n_stacks -+ = VG_(newXA)( HG_(zalloc), -+ "libhb.Thr__new.3 (local_Kws_and_stacks)", -+ HG_(free), sizeof(ULong_n_EC) ); - - /* Add this Thr* <-> ThrID binding to the mapping, and - cross-check */ -Index: helgrind/tests/Makefile.am -=================================================================== ---- helgrind/tests/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/Makefile.am (.../trunk) (revision 13981) -@@ -83,10 +83,12 @@ - tc18_semabuse.vgtest tc18_semabuse.stdout.exp \ - tc18_semabuse.stderr.exp \ - tc18_semabuse.stderr.exp-linux-mips32 \ -+ tc18_semabuse.stderr.exp-linux-mips32-b \ - tc19_shadowmem.vgtest tc19_shadowmem.stdout.exp \ - tc19_shadowmem.stderr.exp tc19_shadowmem.stderr.exp-mips32 \ - tc20_verifywrap.vgtest tc20_verifywrap.stdout.exp \ - tc20_verifywrap.stderr.exp tc20_verifywrap.stderr.exp-mips32 \ -+ tc20_verifywrap.stderr.exp-mips32-b \ - tc20_verifywrap.stderr.exp-s390x \ - tc21_pthonce.vgtest tc21_pthonce.stdout.exp tc21_pthonce.stderr.exp \ - tc22_exit_w_lock.vgtest tc22_exit_w_lock.stdout.exp \ -Index: helgrind/tests/annotate_hbefore.c -=================================================================== ---- helgrind/tests/annotate_hbefore.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/annotate_hbefore.c (.../trunk) (revision 13981) -@@ -167,6 +167,39 @@ - return success; - } - -+#elif defined(VGA_arm64) -+ -+// arm64 -+/* return 1 if success, 0 if failure */ -+UWord do_acasW ( UWord* addr, UWord expected, UWord nyu ) -+{ -+ UWord old, success; -+ UWord block[2] = { (UWord)addr, nyu }; -+ -+ /* Fetch the old value, and set the reservation */ -+ __asm__ __volatile__ ( -+ "ldxr %0, [%1]" "\n" -+ : /*out*/ "=r"(old) -+ : /*in*/ "r"(addr) -+ ); -+ -+ /* If the old value isn't as expected, we've had it */ -+ if (old != expected) return 0; -+ -+ /* otherwise try to stuff the new value in */ -+ __asm__ __volatile__( -+ "ldr x4, [%1, #0]" "\n\t" -+ "ldr x5, [%1, #8]" "\n\t" -+ "stxr w6, x5, [x4, #0]" "\n\t" -+ "eor %0, x6, #1" "\n\t" -+ : /*out*/ "=r"(success) -+ : /*in*/ "r"(&block[0]) -+ : /*trash*/ "x4","x5","x6","memory" -+ ); -+ assert(success == 0 || success == 1); -+ return success; -+} -+ - #elif defined(VGA_s390x) - - // s390x -Index: helgrind/tests/annotate_rwlock.stderr.exp -=================================================================== ---- helgrind/tests/annotate_rwlock.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/annotate_rwlock.stderr.exp (.../trunk) (revision 13981) -@@ -29,6 +29,7 @@ - by 0x........: thread_func (annotate_rwlock.c:147) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 4 bytes inside data symbol "s_rwlock" - - ---------------------------------------------------------------- - -@@ -45,6 +46,7 @@ - by 0x........: thread_func (annotate_rwlock.c:144) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 8 bytes inside data symbol "s_rwlock" - - ---------------------------------------------------------------- - -@@ -61,6 +63,7 @@ - by 0x........: thread_func (annotate_rwlock.c:149) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 8 bytes inside data symbol "s_rwlock" - - ---------------------------------------------------------------- - -@@ -77,6 +80,7 @@ - by 0x........: thread_func (annotate_rwlock.c:149) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 8 bytes inside data symbol "s_rwlock" - - ---------------------------------------------------------------- - -@@ -93,6 +97,7 @@ - by 0x........: thread_func (annotate_rwlock.c:149) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 4 bytes inside data symbol "s_rwlock" - - ---------------------------------------------------------------- - -@@ -113,5 +118,6 @@ - by 0x........: thread_func (annotate_rwlock.c:149) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 4 bytes inside data symbol "s_rwlock" - - Finished. -Index: helgrind/tests/free_is_write.stderr.exp -=================================================================== ---- helgrind/tests/free_is_write.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/free_is_write.stderr.exp (.../trunk) (revision 13981) -@@ -24,6 +24,7 @@ - This conflicts with a previous read of size 1 by thread #x - Locks held: none - at 0x........: main (free_is_write.c:36) -+ Address 0x........ is 5 bytes inside an unallocated block of size 16 in arena "client" - - Done. - -Index: helgrind/tests/hg01_all_ok.c -=================================================================== ---- helgrind/tests/hg01_all_ok.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/hg01_all_ok.c (.../trunk) (revision 13981) -@@ -1,15 +1,31 @@ - /* All OK */ -- -+#include -+#include - #include - - static pthread_mutex_t mx = PTHREAD_MUTEX_INITIALIZER; - --static int shared; -+static int shared = 0; -+static char *ptr; - -+static void breakme(void) -+{ -+ if (shared == 1) -+ memset (ptr, 0x55, 1000); -+} -+ - static void *th(void *v) - { - pthread_mutex_lock(&mx); - shared++; -+ if (shared == 1) { -+ ptr = malloc (1008); -+ breakme(); -+ } -+ if (shared == 2) { -+ free (ptr); -+ breakme(); -+ } - pthread_mutex_unlock(&mx); - - return 0; -Index: helgrind/tests/hg03_inherit.stderr.exp -=================================================================== ---- helgrind/tests/hg03_inherit.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/hg03_inherit.stderr.exp (.../trunk) (revision 13981) -@@ -22,9 +22,8 @@ - This conflicts with a previous read of size 4 by thread #x - Locks held: none - at 0x........: main (hg03_inherit.c:60) -+ Location 0x........ is 0 bytes inside shared[1], -+ a global variable declared at hg03_inherit.c:11 - --Location 0x........ is 0 bytes inside shared[1], --a global variable declared at hg03_inherit.c:11 - -- - ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0) -Index: helgrind/tests/hg04_race.stderr.exp -=================================================================== ---- helgrind/tests/hg04_race.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/hg04_race.stderr.exp (.../trunk) (revision 13981) -@@ -28,10 +28,9 @@ - at 0x........: th (hg04_race.c:10) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "shared" -+ declared at hg04_race.c:6 - --Location 0x........ is 0 bytes inside global var "shared" --declared at hg04_race.c:6 -- - ---------------------------------------------------------------- - - Possible data race during write of size 4 at 0x........ by thread #x -@@ -45,9 +44,8 @@ - at 0x........: th (hg04_race.c:10) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "shared" -+ declared at hg04_race.c:6 - --Location 0x........ is 0 bytes inside global var "shared" --declared at hg04_race.c:6 - -- - ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: helgrind/tests/hg05_race2.stderr.exp -=================================================================== ---- helgrind/tests/hg05_race2.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/hg05_race2.stderr.exp (.../trunk) (revision 13981) -@@ -28,10 +28,9 @@ - at 0x........: th (hg05_race2.c:17) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside foo.poot[5].plop[11], -+ declared at hg05_race2.c:24, in frame #x of thread x - --Location 0x........ is 0 bytes inside foo.poot[5].plop[11], --declared at hg05_race2.c:24, in frame #x of thread x -- - ---------------------------------------------------------------- - - Possible data race during write of size 4 at 0x........ by thread #x -@@ -45,9 +44,8 @@ - at 0x........: th (hg05_race2.c:17) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside foo.poot[5].plop[11], -+ declared at hg05_race2.c:24, in frame #x of thread x - --Location 0x........ is 0 bytes inside foo.poot[5].plop[11], --declared at hg05_race2.c:24, in frame #x of thread x - -- - ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: helgrind/tests/locked_vs_unlocked1_fwd.stderr.exp -=================================================================== ---- helgrind/tests/locked_vs_unlocked1_fwd.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/locked_vs_unlocked1_fwd.stderr.exp (.../trunk) (revision 13981) -@@ -33,4 +33,5 @@ - at 0x........: child_fn (locked_vs_unlocked1.c:19) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 0 bytes inside data symbol "x" - -Index: helgrind/tests/locked_vs_unlocked1_rev.stderr.exp -=================================================================== ---- helgrind/tests/locked_vs_unlocked1_rev.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/locked_vs_unlocked1_rev.stderr.exp (.../trunk) (revision 13981) -@@ -33,4 +33,5 @@ - at 0x........: child_fn (locked_vs_unlocked1.c:19) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 0 bytes inside data symbol "x" - -Index: helgrind/tests/locked_vs_unlocked2.stderr.exp -=================================================================== ---- helgrind/tests/locked_vs_unlocked2.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/locked_vs_unlocked2.stderr.exp (.../trunk) (revision 13981) -@@ -39,4 +39,5 @@ - at 0x........: child_fn1 (locked_vs_unlocked2.c:29) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 0 bytes inside data symbol "x" - -Index: helgrind/tests/locked_vs_unlocked3.stderr.exp -=================================================================== ---- helgrind/tests/locked_vs_unlocked3.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/locked_vs_unlocked3.stderr.exp (.../trunk) (revision 13981) -@@ -31,4 +31,5 @@ - at 0x........: child_fn1 (locked_vs_unlocked3.c:28) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 0 bytes inside data symbol "x" - -Index: helgrind/tests/pth_barrier1.stderr.exp -=================================================================== ---- helgrind/tests/pth_barrier1.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/pth_barrier1.stderr.exp (.../trunk) (revision 13981) -@@ -29,8 +29,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 0 bytes inside a block of size 1 alloc'd -+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -Index: helgrind/tests/pth_barrier2.stderr.exp -=================================================================== ---- helgrind/tests/pth_barrier2.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/pth_barrier2.stderr.exp (.../trunk) (revision 13981) -@@ -29,8 +29,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 0 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 0 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -48,8 +47,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 1 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 1 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -67,8 +65,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -86,8 +83,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 3 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 3 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -105,8 +101,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -124,8 +119,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -143,8 +137,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -162,8 +155,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -181,8 +173,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -200,8 +191,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -219,8 +209,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -238,8 +227,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -257,8 +245,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -276,8 +263,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -295,8 +281,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -314,8 +299,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -333,8 +317,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -352,8 +335,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -371,8 +353,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -390,8 +371,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -409,8 +389,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -428,8 +407,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -447,8 +425,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -466,8 +443,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -485,8 +461,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -504,8 +479,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -523,8 +497,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -542,8 +515,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -561,8 +533,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -580,8 +551,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -599,8 +569,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -@@ -618,8 +587,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 32 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -Index: helgrind/tests/pth_barrier3.stderr.exp -=================================================================== ---- helgrind/tests/pth_barrier3.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/pth_barrier3.stderr.exp (.../trunk) (revision 13981) -@@ -29,8 +29,7 @@ - at 0x........: threadfunc (pth_barrier.c:60) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 0 bytes inside a block of size 1 alloc'd -+ Address 0x........ is 0 bytes inside a block of size 1 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: barriers_and_races (pth_barrier.c:76) - by 0x........: main (pth_barrier.c:122) -Index: helgrind/tests/pth_cond_destroy_busy.stderr.exp -=================================================================== ---- helgrind/tests/pth_cond_destroy_busy.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/pth_cond_destroy_busy.stderr.exp (.../trunk) (revision 13981) -@@ -28,6 +28,7 @@ - by 0x........: thread_func (pth_cond_destroy_busy.c:31) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Address 0x........ is 4 bytes inside data symbol "s_cond" - - ---------------------------------------------------------------- - -Index: helgrind/tests/rwlock_race.stderr.exp -=================================================================== ---- helgrind/tests/rwlock_race.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/rwlock_race.stderr.exp (.../trunk) (revision 13981) -@@ -28,10 +28,9 @@ - at 0x........: thread_func (rwlock_race.c:29) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "s_racy" -+ declared at rwlock_race.c:18 - --Location 0x........ is 0 bytes inside global var "s_racy" --declared at rwlock_race.c:18 -- - Result: 2 - - ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc01_simple_race.stderr.exp -=================================================================== ---- helgrind/tests/tc01_simple_race.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc01_simple_race.stderr.exp (.../trunk) (revision 13981) -@@ -22,10 +22,9 @@ - at 0x........: child_fn (tc01_simple_race.c:14) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "x" -+ declared at tc01_simple_race.c:9 - --Location 0x........ is 0 bytes inside global var "x" --declared at tc01_simple_race.c:9 -- - ---------------------------------------------------------------- - - Possible data race during write of size 4 at 0x........ by thread #x -@@ -37,9 +36,8 @@ - at 0x........: child_fn (tc01_simple_race.c:14) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "x" -+ declared at tc01_simple_race.c:9 - --Location 0x........ is 0 bytes inside global var "x" --declared at tc01_simple_race.c:9 - -- - ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc05_simple_race.stderr.exp -=================================================================== ---- helgrind/tests/tc05_simple_race.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc05_simple_race.stderr.exp (.../trunk) (revision 13981) -@@ -22,10 +22,9 @@ - at 0x........: child_fn (tc05_simple_race.c:19) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "y" -+ declared at tc05_simple_race.c:10 - --Location 0x........ is 0 bytes inside global var "y" --declared at tc05_simple_race.c:10 -- - ---------------------------------------------------------------- - - Possible data race during write of size 4 at 0x........ by thread #x -@@ -37,9 +36,8 @@ - at 0x........: child_fn (tc05_simple_race.c:19) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "y" -+ declared at tc05_simple_race.c:10 - --Location 0x........ is 0 bytes inside global var "y" --declared at tc05_simple_race.c:10 - -- - ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc06_two_races.stderr.exp -=================================================================== ---- helgrind/tests/tc06_two_races.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc06_two_races.stderr.exp (.../trunk) (revision 13981) -@@ -22,10 +22,9 @@ - at 0x........: child_fn (tc06_two_races.c:14) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "unprot1" -+ declared at tc06_two_races.c:9 - --Location 0x........ is 0 bytes inside global var "unprot1" --declared at tc06_two_races.c:9 -- - ---------------------------------------------------------------- - - Possible data race during write of size 4 at 0x........ by thread #x -@@ -37,10 +36,9 @@ - at 0x........: child_fn (tc06_two_races.c:14) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "unprot1" -+ declared at tc06_two_races.c:9 - --Location 0x........ is 0 bytes inside global var "unprot1" --declared at tc06_two_races.c:9 -- - ---------------------------------------------------------------- - - Possible data race during read of size 4 at 0x........ by thread #x -@@ -52,10 +50,9 @@ - at 0x........: child_fn (tc06_two_races.c:18) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "unprot2" -+ declared at tc06_two_races.c:9 - --Location 0x........ is 0 bytes inside global var "unprot2" --declared at tc06_two_races.c:9 -- - ---------------------------------------------------------------- - - Possible data race during write of size 4 at 0x........ by thread #x -@@ -67,9 +64,8 @@ - at 0x........: child_fn (tc06_two_races.c:18) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "unprot2" -+ declared at tc06_two_races.c:9 - --Location 0x........ is 0 bytes inside global var "unprot2" --declared at tc06_two_races.c:9 - -- - ERROR SUMMARY: 4 errors from 4 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc07_hbl1.c -=================================================================== ---- helgrind/tests/tc07_hbl1.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc07_hbl1.c (.../trunk) (revision 13981) -@@ -13,6 +13,7 @@ - #undef PLAT_ppc32_linux - #undef PLAT_ppc64_linux - #undef PLAT_arm_linux -+#undef PLAT_arm64_linux - #undef PLAT_s390x_linux - #undef PLAT_mips32_linux - -@@ -28,8 +29,10 @@ - # define PLAT_ppc32_linux 1 - #elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) - # define PLAT_ppc64_linux 1 --#elif defined(__linux__) && defined(__arm__) -+#elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__) - # define PLAT_arm_linux 1 -+#elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__) -+# define PLAT_arm64_linux 1 - #elif defined(__linux__) && defined(__s390x__) - # define PLAT_s390x_linux 1 - #elif defined(__linux__) && defined(__mips__) -@@ -64,6 +67,18 @@ - : /*out*/ : /*in*/ "r"(&(_lval)) \ - : /*trash*/ "r8", "r9", "cc", "memory" \ - ); -+#elif defined(PLAT_arm64_linux) -+# define INC(_lval,_lqual) \ -+ __asm__ __volatile__( \ -+ "1:\n" \ -+ " ldxr w8, [%0, #0]\n" \ -+ " add w8, w8, #1\n" \ -+ " stxr w9, w8, [%0, #0]\n" \ -+ " cmp w9, #0\n" \ -+ " bne 1b\n" \ -+ : /*out*/ : /*in*/ "r"(&(_lval)) \ -+ : /*trash*/ "x8", "x9", "cc", "memory" \ -+ ); - #elif defined(PLAT_s390x_linux) - # define INC(_lval,_lqual) \ - __asm__ __volatile__( \ -Index: helgrind/tests/tc08_hbl2.c -=================================================================== ---- helgrind/tests/tc08_hbl2.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc08_hbl2.c (.../trunk) (revision 13981) -@@ -29,6 +29,7 @@ - #undef PLAT_ppc32_linux - #undef PLAT_ppc64_linux - #undef PLAT_arm_linux -+#undef PLAT_arm64_linux - #undef PLAT_s390x_linux - #undef PLAT_mips32_linux - #undef PLAT_mips64_linux -@@ -45,8 +46,10 @@ - # define PLAT_ppc32_linux 1 - #elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) - # define PLAT_ppc64_linux 1 --#elif defined(__linux__) && defined(__arm__) -+#elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__) - # define PLAT_arm_linux 1 -+#elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__) -+# define PLAT_arm64_linux 1 - #elif defined(__linux__) && defined(__s390x__) - # define PLAT_s390x_linux 1 - #elif defined(__linux__) && defined(__mips__) -@@ -86,6 +89,18 @@ - : /*out*/ : /*in*/ "r"(&(_lval)) \ - : /*trash*/ "r8", "r9", "cc", "memory" \ - ); -+#elif defined(PLAT_arm64_linux) -+# define INC(_lval,_lqual) \ -+ __asm__ __volatile__( \ -+ "1:\n" \ -+ " ldxr w8, [%0, #0]\n" \ -+ " add w8, w8, #1\n" \ -+ " stxr w9, w8, [%0, #0]\n" \ -+ " cmp w9, #0\n" \ -+ " bne 1b\n" \ -+ : /*out*/ : /*in*/ "r"(&(_lval)) \ -+ : /*trash*/ "x8", "x9", "cc", "memory" \ -+ ); - #elif defined(PLAT_s390x_linux) - # define INC(_lval,_lqual) \ - __asm__ __volatile__( \ -Index: helgrind/tests/tc11_XCHG.c -=================================================================== ---- helgrind/tests/tc11_XCHG.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc11_XCHG.c (.../trunk) (revision 13981) -@@ -31,8 +31,10 @@ - # define PLAT_ppc32_linux 1 - #elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) - # define PLAT_ppc64_linux 1 --#elif defined(__linux__) && defined(__arm__) -+#elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__) - # define PLAT_arm_linux 1 -+#elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__) -+# define PLAT_arm64_linux 1 - #elif defined(__linux__) && defined(__s390x__) - # define PLAT_s390x_linux 1 - #elif defined(__linux__) && defined(__mips__) -@@ -91,7 +93,7 @@ - XCHG_M_R(_addr,_lval) - - #elif defined(PLAT_ppc32_linux) || defined(PLAT_ppc64_linux) \ -- || defined(PLAT_arm_linux) -+ || defined(PLAT_arm_linux) || defined(PLAT_arm64_linux) - # if defined(HAVE_BUILTIN_ATOMIC) - # define XCHG_M_R(_addr,_lval) \ - do { \ -Index: helgrind/tests/tc16_byterace.stderr.exp -=================================================================== ---- helgrind/tests/tc16_byterace.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc16_byterace.stderr.exp (.../trunk) (revision 13981) -@@ -22,10 +22,9 @@ - at 0x........: child_fn (tc16_byterace.c:13) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside bytes[4], -+ a global variable declared at tc16_byterace.c:7 - --Location 0x........ is 0 bytes inside bytes[4], --a global variable declared at tc16_byterace.c:7 -- - ---------------------------------------------------------------- - - Possible data race during write of size 1 at 0x........ by thread #x -@@ -37,9 +36,8 @@ - at 0x........: child_fn (tc16_byterace.c:13) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside bytes[4], -+ a global variable declared at tc16_byterace.c:7 - --Location 0x........ is 0 bytes inside bytes[4], --a global variable declared at tc16_byterace.c:7 - -- - ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc18_semabuse.stderr.exp-linux-mips32-b -=================================================================== ---- helgrind/tests/tc18_semabuse.stderr.exp-linux-mips32-b (.../tags/VALGRIND_3_9_0) (revision 0) -+++ helgrind/tests/tc18_semabuse.stderr.exp-linux-mips32-b (.../trunk) (revision 13981) -@@ -0,0 +1,30 @@ -+ -+---Thread-Announcement------------------------------------------ -+ -+Thread #x is the program's root thread -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to sem_init failed -+ with error code 22 (EINVAL: Invalid argument) -+ at 0x........: sem_init_WRK (hg_intercepts.c:...) -+ by 0x........: sem_init@* (hg_intercepts.c:...) -+ by 0x........: main (tc18_semabuse.c:23) -+ -+---------------------------------------------------------------- -+ -+Thread #x: Bug in libpthread: sem_wait succeeded on semaphore without prior sem_post -+ at 0x........: sem_wait_WRK (hg_intercepts.c:...) -+ by 0x........: sem_wait (hg_intercepts.c:...) -+ by 0x........: main (tc18_semabuse.c:34) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to sem_post failed -+ with error code 89 (ENOSYS: Function not implemented) -+ at 0x........: sem_post_WRK (hg_intercepts.c:...) -+ by 0x........: sem_post (hg_intercepts.c:...) -+ by 0x........: main (tc18_semabuse.c:37) -+ -+ -+ERROR SUMMARY: 3 errors from 3 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc19_shadowmem.stderr.exp -=================================================================== ---- helgrind/tests/tc19_shadowmem.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc19_shadowmem.stderr.exp (.../trunk) (revision 13981) -@@ -36,8 +36,7 @@ - by 0x........: steer (tc19_shadowmem.c:288) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 0 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 0 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -73,8 +72,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 1 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 1 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -110,8 +108,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -147,8 +144,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 3 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 3 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -184,8 +180,7 @@ - by 0x........: steer (tc19_shadowmem.c:296) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -221,8 +216,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -258,8 +252,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -295,8 +288,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -332,8 +324,7 @@ - by 0x........: steer (tc19_shadowmem.c:304) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -369,8 +360,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -406,8 +396,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -443,8 +432,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -480,8 +468,7 @@ - by 0x........: steer (tc19_shadowmem.c:312) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -517,8 +504,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -554,8 +540,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -591,8 +576,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -628,8 +612,7 @@ - by 0x........: steer (tc19_shadowmem.c:320) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -665,8 +648,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -702,8 +684,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -739,8 +720,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -776,8 +756,7 @@ - by 0x........: steer (tc19_shadowmem.c:328) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -813,8 +792,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -850,8 +828,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -887,8 +864,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -924,8 +900,7 @@ - by 0x........: steer (tc19_shadowmem.c:336) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -961,8 +936,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -998,8 +972,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1035,8 +1008,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1072,8 +1044,7 @@ - by 0x........: steer (tc19_shadowmem.c:344) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1109,8 +1080,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1146,8 +1116,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1183,8 +1152,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1220,8 +1188,7 @@ - by 0x........: steer (tc19_shadowmem.c:352) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1257,8 +1224,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1294,8 +1260,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1331,8 +1296,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1368,8 +1332,7 @@ - by 0x........: steer (tc19_shadowmem.c:360) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1405,8 +1368,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1442,8 +1404,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1479,8 +1440,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1516,8 +1476,7 @@ - by 0x........: steer (tc19_shadowmem.c:368) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1553,8 +1512,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1590,8 +1548,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1627,8 +1584,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1664,8 +1620,7 @@ - by 0x........: steer (tc19_shadowmem.c:376) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1701,8 +1656,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1738,8 +1692,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1775,8 +1728,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1812,8 +1764,7 @@ - by 0x........: steer (tc19_shadowmem.c:384) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1849,8 +1800,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1886,8 +1836,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1923,8 +1872,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1960,8 +1908,7 @@ - by 0x........: steer (tc19_shadowmem.c:392) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -1997,8 +1944,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2034,8 +1980,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2071,8 +2016,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2108,8 +2052,7 @@ - by 0x........: steer (tc19_shadowmem.c:400) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2145,8 +2088,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2182,8 +2124,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2219,8 +2160,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2256,8 +2196,7 @@ - by 0x........: steer (tc19_shadowmem.c:408) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2293,8 +2232,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2330,8 +2268,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2367,8 +2304,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2404,8 +2340,7 @@ - by 0x........: steer (tc19_shadowmem.c:416) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2441,8 +2376,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2478,8 +2412,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2515,8 +2448,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2552,8 +2484,7 @@ - by 0x........: steer (tc19_shadowmem.c:424) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2589,8 +2520,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2626,8 +2556,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2663,8 +2592,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2700,8 +2628,7 @@ - by 0x........: steer (tc19_shadowmem.c:432) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2737,8 +2664,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2774,8 +2700,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2811,8 +2736,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2848,8 +2772,7 @@ - by 0x........: steer (tc19_shadowmem.c:440) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2885,8 +2808,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2922,8 +2844,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2959,8 +2880,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -2996,8 +2916,7 @@ - by 0x........: steer (tc19_shadowmem.c:448) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3033,8 +2952,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3070,8 +2988,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3107,8 +3024,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3144,8 +3060,7 @@ - by 0x........: steer (tc19_shadowmem.c:456) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3181,8 +3096,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3218,8 +3132,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3255,8 +3168,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3292,8 +3204,7 @@ - by 0x........: steer (tc19_shadowmem.c:464) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3329,8 +3240,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3366,8 +3276,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3403,8 +3312,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3440,8 +3348,7 @@ - by 0x........: steer (tc19_shadowmem.c:472) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3477,8 +3384,7 @@ - by 0x........: steer (tc19_shadowmem.c:474) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 93 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 93 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3514,8 +3420,7 @@ - by 0x........: steer (tc19_shadowmem.c:476) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3551,8 +3456,7 @@ - by 0x........: steer (tc19_shadowmem.c:478) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 95 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 95 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3588,8 +3492,7 @@ - by 0x........: steer (tc19_shadowmem.c:480) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3625,8 +3528,7 @@ - by 0x........: steer (tc19_shadowmem.c:482) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 97 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 97 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3662,8 +3564,7 @@ - by 0x........: steer (tc19_shadowmem.c:484) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 98 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 98 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3704,8 +3605,7 @@ - by 0x........: steer (tc19_shadowmem.c:288) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 0 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 0 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3744,8 +3644,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 1 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 1 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3764,8 +3663,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3801,8 +3699,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3838,8 +3735,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 3 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 3 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3858,8 +3754,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3895,8 +3790,7 @@ - by 0x........: steer (tc19_shadowmem.c:296) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3932,8 +3826,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3952,8 +3845,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -3989,8 +3881,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4026,8 +3917,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4046,8 +3936,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4083,8 +3972,7 @@ - by 0x........: steer (tc19_shadowmem.c:304) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4120,8 +4008,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4140,8 +4027,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4177,8 +4063,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4214,8 +4099,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4234,8 +4118,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4271,8 +4154,7 @@ - by 0x........: steer (tc19_shadowmem.c:312) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4308,8 +4190,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4328,8 +4209,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4365,8 +4245,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4402,8 +4281,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4422,8 +4300,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4459,8 +4336,7 @@ - by 0x........: steer (tc19_shadowmem.c:320) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4496,8 +4372,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4516,8 +4391,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4553,8 +4427,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4590,8 +4463,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4610,8 +4482,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4647,8 +4518,7 @@ - by 0x........: steer (tc19_shadowmem.c:328) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4684,8 +4554,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4704,8 +4573,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4741,8 +4609,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4778,8 +4645,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4798,8 +4664,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4835,8 +4700,7 @@ - by 0x........: steer (tc19_shadowmem.c:336) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4872,8 +4736,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4892,8 +4755,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4929,8 +4791,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4966,8 +4827,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -4986,8 +4846,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5023,8 +4882,7 @@ - by 0x........: steer (tc19_shadowmem.c:344) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5060,8 +4918,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5080,8 +4937,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5117,8 +4973,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5154,8 +5009,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5174,8 +5028,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5211,8 +5064,7 @@ - by 0x........: steer (tc19_shadowmem.c:352) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5248,8 +5100,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5268,8 +5119,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5305,8 +5155,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5342,8 +5191,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5362,8 +5210,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5399,8 +5246,7 @@ - by 0x........: steer (tc19_shadowmem.c:360) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5436,8 +5282,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5456,8 +5301,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5493,8 +5337,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5530,8 +5373,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5550,8 +5392,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5587,8 +5428,7 @@ - by 0x........: steer (tc19_shadowmem.c:368) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5624,8 +5464,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5644,8 +5483,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5681,8 +5519,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5718,8 +5555,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5738,8 +5574,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5775,8 +5610,7 @@ - by 0x........: steer (tc19_shadowmem.c:376) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5812,8 +5646,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5832,8 +5665,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5869,8 +5701,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5906,8 +5737,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5926,8 +5756,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -5963,8 +5792,7 @@ - by 0x........: steer (tc19_shadowmem.c:384) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6000,8 +5828,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6020,8 +5847,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6057,8 +5883,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6094,8 +5919,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6114,8 +5938,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6151,8 +5974,7 @@ - by 0x........: steer (tc19_shadowmem.c:392) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6188,8 +6010,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6208,8 +6029,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6245,8 +6065,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6282,8 +6101,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6302,8 +6120,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6339,8 +6156,7 @@ - by 0x........: steer (tc19_shadowmem.c:400) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6376,8 +6192,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6396,8 +6211,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6433,8 +6247,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6470,8 +6283,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6490,8 +6302,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6527,8 +6338,7 @@ - by 0x........: steer (tc19_shadowmem.c:408) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6564,8 +6374,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6584,8 +6393,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6621,8 +6429,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6658,8 +6465,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6678,8 +6484,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6715,8 +6520,7 @@ - by 0x........: steer (tc19_shadowmem.c:416) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6752,8 +6556,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6772,8 +6575,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6809,8 +6611,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6846,8 +6647,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6866,8 +6666,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6903,8 +6702,7 @@ - by 0x........: steer (tc19_shadowmem.c:424) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6940,8 +6738,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6960,8 +6757,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -6997,8 +6793,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7034,8 +6829,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7054,8 +6848,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7091,8 +6884,7 @@ - by 0x........: steer (tc19_shadowmem.c:432) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7128,8 +6920,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7148,8 +6939,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7185,8 +6975,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7222,8 +7011,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7242,8 +7030,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7279,8 +7066,7 @@ - by 0x........: steer (tc19_shadowmem.c:440) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7316,8 +7102,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7336,8 +7121,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7373,8 +7157,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7410,8 +7193,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7430,8 +7212,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7467,8 +7248,7 @@ - by 0x........: steer (tc19_shadowmem.c:448) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7504,8 +7284,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7524,8 +7303,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7561,8 +7339,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7598,8 +7375,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7618,8 +7394,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7655,8 +7430,7 @@ - by 0x........: steer (tc19_shadowmem.c:456) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7692,8 +7466,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7712,8 +7485,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7749,8 +7521,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7786,8 +7557,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7806,8 +7576,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7843,8 +7612,7 @@ - by 0x........: steer (tc19_shadowmem.c:464) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7880,8 +7648,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7900,8 +7667,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7937,8 +7703,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7974,8 +7739,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -7994,8 +7758,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8031,8 +7794,7 @@ - by 0x........: steer (tc19_shadowmem.c:472) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8068,8 +7830,7 @@ - by 0x........: steer (tc19_shadowmem.c:474) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 93 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 93 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8088,8 +7849,7 @@ - by 0x........: steer (tc19_shadowmem.c:474) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8125,8 +7885,7 @@ - by 0x........: steer (tc19_shadowmem.c:476) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8162,8 +7921,7 @@ - by 0x........: steer (tc19_shadowmem.c:478) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 95 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 95 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8182,8 +7940,7 @@ - by 0x........: steer (tc19_shadowmem.c:478) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8219,8 +7976,7 @@ - by 0x........: steer (tc19_shadowmem.c:480) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8256,8 +8012,7 @@ - by 0x........: steer (tc19_shadowmem.c:482) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 97 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 97 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8276,8 +8031,7 @@ - by 0x........: steer (tc19_shadowmem.c:482) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 98 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 98 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8318,8 +8072,7 @@ - by 0x........: steer (tc19_shadowmem.c:288) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 0 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 0 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8355,8 +8108,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 1 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 1 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8375,8 +8127,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8395,8 +8146,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 3 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 3 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8415,8 +8165,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8452,8 +8201,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8472,8 +8220,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8509,8 +8256,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 3 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 3 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8529,8 +8275,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8549,8 +8294,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8569,8 +8313,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8606,8 +8349,7 @@ - by 0x........: steer (tc19_shadowmem.c:296) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8643,8 +8385,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8663,8 +8404,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8683,8 +8423,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8703,8 +8442,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8740,8 +8478,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8760,8 +8497,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8797,8 +8533,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8817,8 +8552,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8837,8 +8571,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8857,8 +8590,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8894,8 +8626,7 @@ - by 0x........: steer (tc19_shadowmem.c:304) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8931,8 +8662,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8951,8 +8681,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8971,8 +8700,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -8991,8 +8719,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9028,8 +8755,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9048,8 +8774,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9085,8 +8810,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9105,8 +8829,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9125,8 +8848,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9145,8 +8867,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9182,8 +8903,7 @@ - by 0x........: steer (tc19_shadowmem.c:312) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9219,8 +8939,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9239,8 +8958,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9259,8 +8977,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9279,8 +8996,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9316,8 +9032,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9336,8 +9051,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9373,8 +9087,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9393,8 +9106,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9413,8 +9125,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9433,8 +9144,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9470,8 +9180,7 @@ - by 0x........: steer (tc19_shadowmem.c:320) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9507,8 +9216,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9527,8 +9235,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9547,8 +9254,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9567,8 +9273,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9604,8 +9309,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9624,8 +9328,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9661,8 +9364,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9681,8 +9383,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9701,8 +9402,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9721,8 +9421,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9758,8 +9457,7 @@ - by 0x........: steer (tc19_shadowmem.c:328) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9795,8 +9493,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9815,8 +9512,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9835,8 +9531,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9855,8 +9550,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9892,8 +9586,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9912,8 +9605,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9949,8 +9641,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9969,8 +9660,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -9989,8 +9679,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10009,8 +9698,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10046,8 +9734,7 @@ - by 0x........: steer (tc19_shadowmem.c:336) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10083,8 +9770,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10103,8 +9789,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10123,8 +9808,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10143,8 +9827,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10180,8 +9863,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10200,8 +9882,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10237,8 +9918,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10257,8 +9937,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10277,8 +9956,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10297,8 +9975,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10334,8 +10011,7 @@ - by 0x........: steer (tc19_shadowmem.c:344) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10371,8 +10047,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10391,8 +10066,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10411,8 +10085,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10431,8 +10104,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10468,8 +10140,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10488,8 +10159,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10525,8 +10195,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10545,8 +10214,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10565,8 +10233,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10585,8 +10252,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10622,8 +10288,7 @@ - by 0x........: steer (tc19_shadowmem.c:352) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10659,8 +10324,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10679,8 +10343,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10699,8 +10362,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10719,8 +10381,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10756,8 +10417,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10776,8 +10436,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10813,8 +10472,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10833,8 +10491,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10853,8 +10510,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10873,8 +10529,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10910,8 +10565,7 @@ - by 0x........: steer (tc19_shadowmem.c:360) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10947,8 +10601,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10967,8 +10620,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -10987,8 +10639,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11007,8 +10658,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11044,8 +10694,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11064,8 +10713,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11101,8 +10749,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11121,8 +10768,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11141,8 +10787,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11161,8 +10806,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11198,8 +10842,7 @@ - by 0x........: steer (tc19_shadowmem.c:368) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11235,8 +10878,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11255,8 +10897,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11275,8 +10916,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11295,8 +10935,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11332,8 +10971,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11352,8 +10990,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11389,8 +11026,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11409,8 +11045,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11429,8 +11064,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11449,8 +11083,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11486,8 +11119,7 @@ - by 0x........: steer (tc19_shadowmem.c:376) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11523,8 +11155,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11543,8 +11174,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11563,8 +11193,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11583,8 +11212,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11620,8 +11248,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11640,8 +11267,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11677,8 +11303,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11697,8 +11322,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11717,8 +11341,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11737,8 +11360,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11774,8 +11396,7 @@ - by 0x........: steer (tc19_shadowmem.c:384) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11811,8 +11432,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11831,8 +11451,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11851,8 +11470,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11871,8 +11489,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11908,8 +11525,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11928,8 +11544,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11965,8 +11580,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -11985,8 +11599,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12005,8 +11618,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12025,8 +11637,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12062,8 +11673,7 @@ - by 0x........: steer (tc19_shadowmem.c:392) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12099,8 +11709,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12119,8 +11728,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12139,8 +11747,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12159,8 +11766,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12196,8 +11802,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12216,8 +11821,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12253,8 +11857,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12273,8 +11876,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12293,8 +11895,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12313,8 +11914,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12350,8 +11950,7 @@ - by 0x........: steer (tc19_shadowmem.c:400) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12387,8 +11986,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12407,8 +12005,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12427,8 +12024,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12447,8 +12043,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12484,8 +12079,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12504,8 +12098,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12541,8 +12134,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12561,8 +12153,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12581,8 +12172,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12601,8 +12191,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12638,8 +12227,7 @@ - by 0x........: steer (tc19_shadowmem.c:408) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12675,8 +12263,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12695,8 +12282,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12715,8 +12301,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12735,8 +12320,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12772,8 +12356,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12792,8 +12375,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12829,8 +12411,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12849,8 +12430,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12869,8 +12449,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12889,8 +12468,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12926,8 +12504,7 @@ - by 0x........: steer (tc19_shadowmem.c:416) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12963,8 +12540,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -12983,8 +12559,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13003,8 +12578,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13023,8 +12597,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13060,8 +12633,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13080,8 +12652,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13117,8 +12688,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13137,8 +12707,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13157,8 +12726,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13177,8 +12745,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13214,8 +12781,7 @@ - by 0x........: steer (tc19_shadowmem.c:424) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13251,8 +12817,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13271,8 +12836,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13291,8 +12855,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13311,8 +12874,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13348,8 +12910,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13368,8 +12929,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13405,8 +12965,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13425,8 +12984,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13445,8 +13003,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13465,8 +13022,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13502,8 +13058,7 @@ - by 0x........: steer (tc19_shadowmem.c:432) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13539,8 +13094,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13559,8 +13113,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13579,8 +13132,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13599,8 +13151,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13636,8 +13187,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13656,8 +13206,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13693,8 +13242,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13713,8 +13261,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13733,8 +13280,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13753,8 +13299,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13790,8 +13335,7 @@ - by 0x........: steer (tc19_shadowmem.c:440) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13827,8 +13371,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13847,8 +13390,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13867,8 +13409,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13887,8 +13428,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13924,8 +13464,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13944,8 +13483,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -13981,8 +13519,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14001,8 +13538,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14021,8 +13557,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14041,8 +13576,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14078,8 +13612,7 @@ - by 0x........: steer (tc19_shadowmem.c:448) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14115,8 +13648,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14135,8 +13667,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14155,8 +13686,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14175,8 +13705,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14212,8 +13741,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14232,8 +13760,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14269,8 +13796,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14289,8 +13815,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14309,8 +13834,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14329,8 +13853,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14366,8 +13889,7 @@ - by 0x........: steer (tc19_shadowmem.c:456) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14403,8 +13925,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14423,8 +13944,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14443,8 +13963,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14463,8 +13982,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14500,8 +14018,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14520,8 +14037,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14557,8 +14073,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14577,8 +14092,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14597,8 +14111,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14617,8 +14130,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14654,8 +14166,7 @@ - by 0x........: steer (tc19_shadowmem.c:464) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14691,8 +14202,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14711,8 +14221,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14731,8 +14240,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14751,8 +14259,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14788,8 +14295,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14808,8 +14314,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14845,8 +14350,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14865,8 +14369,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14885,8 +14388,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 93 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 93 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14905,8 +14407,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14942,8 +14443,7 @@ - by 0x........: steer (tc19_shadowmem.c:472) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14979,8 +14479,7 @@ - by 0x........: steer (tc19_shadowmem.c:474) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 93 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 93 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -14999,8 +14498,7 @@ - by 0x........: steer (tc19_shadowmem.c:474) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15019,8 +14517,7 @@ - by 0x........: steer (tc19_shadowmem.c:474) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 95 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 95 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15039,8 +14536,7 @@ - by 0x........: steer (tc19_shadowmem.c:474) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15076,8 +14572,7 @@ - by 0x........: steer (tc19_shadowmem.c:476) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15096,8 +14591,7 @@ - by 0x........: steer (tc19_shadowmem.c:476) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15133,8 +14627,7 @@ - by 0x........: steer (tc19_shadowmem.c:478) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 95 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 95 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15153,8 +14646,7 @@ - by 0x........: steer (tc19_shadowmem.c:478) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15173,8 +14665,7 @@ - by 0x........: steer (tc19_shadowmem.c:478) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 97 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 97 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15193,8 +14684,7 @@ - by 0x........: steer (tc19_shadowmem.c:478) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 98 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 98 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15235,8 +14725,7 @@ - by 0x........: steer (tc19_shadowmem.c:288) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 0 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 0 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15272,8 +14761,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 1 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 1 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15292,8 +14780,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15312,8 +14799,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 3 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 3 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15332,8 +14818,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15352,8 +14837,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15372,8 +14856,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15392,8 +14875,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15412,8 +14894,7 @@ - by 0x........: steer (tc19_shadowmem.c:290) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15449,8 +14930,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 2 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 2 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15469,8 +14949,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15489,8 +14968,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15509,8 +14987,7 @@ - by 0x........: steer (tc19_shadowmem.c:292) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15546,8 +15023,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 3 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 3 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15566,8 +15042,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15586,8 +15061,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15606,8 +15080,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15626,8 +15099,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15646,8 +15118,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15666,8 +15137,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15686,8 +15156,7 @@ - by 0x........: steer (tc19_shadowmem.c:294) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15723,8 +15192,7 @@ - by 0x........: steer (tc19_shadowmem.c:296) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 4 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 4 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15743,8 +15211,7 @@ - by 0x........: steer (tc19_shadowmem.c:296) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15780,8 +15247,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 5 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 5 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15800,8 +15266,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15820,8 +15285,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15840,8 +15304,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15860,8 +15323,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15880,8 +15342,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15900,8 +15361,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15920,8 +15380,7 @@ - by 0x........: steer (tc19_shadowmem.c:298) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15957,8 +15416,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 6 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 6 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15977,8 +15435,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -15997,8 +15454,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16017,8 +15473,7 @@ - by 0x........: steer (tc19_shadowmem.c:300) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16054,8 +15509,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 7 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 7 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16074,8 +15528,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16094,8 +15547,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16114,8 +15566,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16134,8 +15585,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16154,8 +15604,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16174,8 +15623,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16194,8 +15642,7 @@ - by 0x........: steer (tc19_shadowmem.c:302) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16231,8 +15678,7 @@ - by 0x........: steer (tc19_shadowmem.c:304) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 8 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 8 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16268,8 +15714,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 9 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 9 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16288,8 +15733,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16308,8 +15752,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16328,8 +15771,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16348,8 +15790,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16368,8 +15809,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16388,8 +15828,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16408,8 +15847,7 @@ - by 0x........: steer (tc19_shadowmem.c:306) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16445,8 +15883,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 10 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 10 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16465,8 +15902,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16485,8 +15921,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16505,8 +15940,7 @@ - by 0x........: steer (tc19_shadowmem.c:308) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16542,8 +15976,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 11 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 11 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16562,8 +15995,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16582,8 +16014,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16602,8 +16033,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16622,8 +16052,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16642,8 +16071,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16662,8 +16090,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16682,8 +16109,7 @@ - by 0x........: steer (tc19_shadowmem.c:310) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16719,8 +16145,7 @@ - by 0x........: steer (tc19_shadowmem.c:312) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 12 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 12 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16739,8 +16164,7 @@ - by 0x........: steer (tc19_shadowmem.c:312) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16776,8 +16200,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 13 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 13 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16796,8 +16219,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16816,8 +16238,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16836,8 +16257,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16856,8 +16276,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16876,8 +16295,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16896,8 +16314,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16916,8 +16333,7 @@ - by 0x........: steer (tc19_shadowmem.c:314) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16953,8 +16369,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 14 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 14 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16973,8 +16388,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -16993,8 +16407,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17013,8 +16426,7 @@ - by 0x........: steer (tc19_shadowmem.c:316) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17050,8 +16462,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 15 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 15 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17070,8 +16481,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17090,8 +16500,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17110,8 +16519,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17130,8 +16538,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17150,8 +16557,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17170,8 +16576,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17190,8 +16595,7 @@ - by 0x........: steer (tc19_shadowmem.c:318) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17227,8 +16631,7 @@ - by 0x........: steer (tc19_shadowmem.c:320) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 16 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 16 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17264,8 +16667,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 17 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 17 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17284,8 +16686,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17304,8 +16705,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17324,8 +16724,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17344,8 +16743,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17364,8 +16762,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17384,8 +16781,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17404,8 +16800,7 @@ - by 0x........: steer (tc19_shadowmem.c:322) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17441,8 +16836,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 18 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 18 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17461,8 +16855,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17481,8 +16874,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17501,8 +16893,7 @@ - by 0x........: steer (tc19_shadowmem.c:324) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17538,8 +16929,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 19 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 19 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17558,8 +16948,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17578,8 +16967,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17598,8 +16986,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17618,8 +17005,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17638,8 +17024,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17658,8 +17043,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17678,8 +17062,7 @@ - by 0x........: steer (tc19_shadowmem.c:326) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17715,8 +17098,7 @@ - by 0x........: steer (tc19_shadowmem.c:328) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 20 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 20 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17735,8 +17117,7 @@ - by 0x........: steer (tc19_shadowmem.c:328) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17772,8 +17153,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 21 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 21 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17792,8 +17172,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17812,8 +17191,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17832,8 +17210,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17852,8 +17229,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17872,8 +17248,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17892,8 +17267,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17912,8 +17286,7 @@ - by 0x........: steer (tc19_shadowmem.c:330) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17949,8 +17322,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 22 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 22 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17969,8 +17341,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -17989,8 +17360,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18009,8 +17379,7 @@ - by 0x........: steer (tc19_shadowmem.c:332) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18046,8 +17415,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 23 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 23 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18066,8 +17434,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18086,8 +17453,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18106,8 +17472,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18126,8 +17491,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18146,8 +17510,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18166,8 +17529,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18186,8 +17548,7 @@ - by 0x........: steer (tc19_shadowmem.c:334) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18223,8 +17584,7 @@ - by 0x........: steer (tc19_shadowmem.c:336) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 24 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 24 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18260,8 +17620,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 25 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 25 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18280,8 +17639,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18300,8 +17658,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18320,8 +17677,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18340,8 +17696,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18360,8 +17715,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18380,8 +17734,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18400,8 +17753,7 @@ - by 0x........: steer (tc19_shadowmem.c:338) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18437,8 +17789,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 26 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 26 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18457,8 +17808,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18477,8 +17827,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18497,8 +17846,7 @@ - by 0x........: steer (tc19_shadowmem.c:340) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18534,8 +17882,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 27 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 27 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18554,8 +17901,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18574,8 +17920,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18594,8 +17939,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18614,8 +17958,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18634,8 +17977,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18654,8 +17996,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18674,8 +18015,7 @@ - by 0x........: steer (tc19_shadowmem.c:342) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18711,8 +18051,7 @@ - by 0x........: steer (tc19_shadowmem.c:344) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 28 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 28 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18731,8 +18070,7 @@ - by 0x........: steer (tc19_shadowmem.c:344) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18768,8 +18106,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 29 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 29 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18788,8 +18125,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18808,8 +18144,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18828,8 +18163,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18848,8 +18182,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18868,8 +18201,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18888,8 +18220,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18908,8 +18239,7 @@ - by 0x........: steer (tc19_shadowmem.c:346) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18945,8 +18275,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 30 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 30 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18965,8 +18294,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -18985,8 +18313,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19005,8 +18332,7 @@ - by 0x........: steer (tc19_shadowmem.c:348) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19042,8 +18368,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 31 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 31 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19062,8 +18387,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19082,8 +18406,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19102,8 +18425,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19122,8 +18444,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19142,8 +18463,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19162,8 +18482,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19182,8 +18501,7 @@ - by 0x........: steer (tc19_shadowmem.c:350) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19219,8 +18537,7 @@ - by 0x........: steer (tc19_shadowmem.c:352) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 32 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 32 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19256,8 +18573,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 33 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 33 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19276,8 +18592,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19296,8 +18611,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19316,8 +18630,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19336,8 +18649,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19356,8 +18668,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19376,8 +18687,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19396,8 +18706,7 @@ - by 0x........: steer (tc19_shadowmem.c:354) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19433,8 +18742,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 34 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 34 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19453,8 +18761,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19473,8 +18780,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19493,8 +18799,7 @@ - by 0x........: steer (tc19_shadowmem.c:356) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19530,8 +18835,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 35 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 35 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19550,8 +18854,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19570,8 +18873,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19590,8 +18892,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19610,8 +18911,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19630,8 +18930,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19650,8 +18949,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19670,8 +18968,7 @@ - by 0x........: steer (tc19_shadowmem.c:358) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19707,8 +19004,7 @@ - by 0x........: steer (tc19_shadowmem.c:360) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 36 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 36 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19727,8 +19023,7 @@ - by 0x........: steer (tc19_shadowmem.c:360) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19764,8 +19059,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 37 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 37 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19784,8 +19078,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19804,8 +19097,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19824,8 +19116,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19844,8 +19135,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19864,8 +19154,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19884,8 +19173,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19904,8 +19192,7 @@ - by 0x........: steer (tc19_shadowmem.c:362) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19941,8 +19228,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 38 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 38 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19961,8 +19247,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -19981,8 +19266,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20001,8 +19285,7 @@ - by 0x........: steer (tc19_shadowmem.c:364) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20038,8 +19321,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 39 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 39 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20058,8 +19340,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20078,8 +19359,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20098,8 +19378,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20118,8 +19397,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20138,8 +19416,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20158,8 +19435,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20178,8 +19454,7 @@ - by 0x........: steer (tc19_shadowmem.c:366) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20215,8 +19490,7 @@ - by 0x........: steer (tc19_shadowmem.c:368) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 40 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 40 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20252,8 +19526,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 41 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 41 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20272,8 +19545,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20292,8 +19564,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20312,8 +19583,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20332,8 +19602,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20352,8 +19621,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20372,8 +19640,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20392,8 +19659,7 @@ - by 0x........: steer (tc19_shadowmem.c:370) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20429,8 +19695,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 42 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 42 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20449,8 +19714,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20469,8 +19733,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20489,8 +19752,7 @@ - by 0x........: steer (tc19_shadowmem.c:372) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20526,8 +19788,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 43 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 43 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20546,8 +19807,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20566,8 +19826,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20586,8 +19845,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20606,8 +19864,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20626,8 +19883,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20646,8 +19902,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20666,8 +19921,7 @@ - by 0x........: steer (tc19_shadowmem.c:374) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20703,8 +19957,7 @@ - by 0x........: steer (tc19_shadowmem.c:376) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 44 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 44 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20723,8 +19976,7 @@ - by 0x........: steer (tc19_shadowmem.c:376) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20760,8 +20012,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 45 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 45 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20780,8 +20031,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20800,8 +20050,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20820,8 +20069,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20840,8 +20088,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20860,8 +20107,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20880,8 +20126,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20900,8 +20145,7 @@ - by 0x........: steer (tc19_shadowmem.c:378) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20937,8 +20181,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 46 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 46 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20957,8 +20200,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20977,8 +20219,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -20997,8 +20238,7 @@ - by 0x........: steer (tc19_shadowmem.c:380) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21034,8 +20274,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 47 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 47 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21054,8 +20293,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21074,8 +20312,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21094,8 +20331,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21114,8 +20350,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21134,8 +20369,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21154,8 +20388,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21174,8 +20407,7 @@ - by 0x........: steer (tc19_shadowmem.c:382) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21211,8 +20443,7 @@ - by 0x........: steer (tc19_shadowmem.c:384) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 48 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 48 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21248,8 +20479,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 49 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 49 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21268,8 +20498,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21288,8 +20517,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21308,8 +20536,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21328,8 +20555,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21348,8 +20574,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21368,8 +20593,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21388,8 +20612,7 @@ - by 0x........: steer (tc19_shadowmem.c:386) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21425,8 +20648,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 50 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 50 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21445,8 +20667,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21465,8 +20686,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21485,8 +20705,7 @@ - by 0x........: steer (tc19_shadowmem.c:388) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21522,8 +20741,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 51 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 51 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21542,8 +20760,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21562,8 +20779,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21582,8 +20798,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21602,8 +20817,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21622,8 +20836,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21642,8 +20855,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21662,8 +20874,7 @@ - by 0x........: steer (tc19_shadowmem.c:390) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21699,8 +20910,7 @@ - by 0x........: steer (tc19_shadowmem.c:392) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 52 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 52 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21719,8 +20929,7 @@ - by 0x........: steer (tc19_shadowmem.c:392) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21756,8 +20965,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 53 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 53 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21776,8 +20984,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21796,8 +21003,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21816,8 +21022,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21836,8 +21041,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21856,8 +21060,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21876,8 +21079,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21896,8 +21098,7 @@ - by 0x........: steer (tc19_shadowmem.c:394) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21933,8 +21134,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 54 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 54 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21953,8 +21153,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21973,8 +21172,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -21993,8 +21191,7 @@ - by 0x........: steer (tc19_shadowmem.c:396) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22030,8 +21227,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 55 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 55 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22050,8 +21246,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22070,8 +21265,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22090,8 +21284,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22110,8 +21303,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22130,8 +21322,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22150,8 +21341,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22170,8 +21360,7 @@ - by 0x........: steer (tc19_shadowmem.c:398) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22207,8 +21396,7 @@ - by 0x........: steer (tc19_shadowmem.c:400) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 56 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 56 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22244,8 +21432,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 57 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 57 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22264,8 +21451,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22284,8 +21470,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22304,8 +21489,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22324,8 +21508,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22344,8 +21527,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22364,8 +21546,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22384,8 +21565,7 @@ - by 0x........: steer (tc19_shadowmem.c:402) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22421,8 +21601,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 58 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 58 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22441,8 +21620,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22461,8 +21639,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22481,8 +21658,7 @@ - by 0x........: steer (tc19_shadowmem.c:404) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22518,8 +21694,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 59 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 59 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22538,8 +21713,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22558,8 +21732,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22578,8 +21751,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22598,8 +21770,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22618,8 +21789,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22638,8 +21808,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22658,8 +21827,7 @@ - by 0x........: steer (tc19_shadowmem.c:406) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22695,8 +21863,7 @@ - by 0x........: steer (tc19_shadowmem.c:408) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 60 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 60 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22715,8 +21882,7 @@ - by 0x........: steer (tc19_shadowmem.c:408) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22752,8 +21918,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 61 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 61 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22772,8 +21937,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22792,8 +21956,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22812,8 +21975,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22832,8 +21994,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22852,8 +22013,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22872,8 +22032,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22892,8 +22051,7 @@ - by 0x........: steer (tc19_shadowmem.c:410) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22929,8 +22087,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 62 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 62 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22949,8 +22106,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22969,8 +22125,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -22989,8 +22144,7 @@ - by 0x........: steer (tc19_shadowmem.c:412) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23026,8 +22180,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 63 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 63 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23046,8 +22199,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23066,8 +22218,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23086,8 +22237,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23106,8 +22256,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23126,8 +22275,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23146,8 +22294,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23166,8 +22313,7 @@ - by 0x........: steer (tc19_shadowmem.c:414) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23203,8 +22349,7 @@ - by 0x........: steer (tc19_shadowmem.c:416) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 64 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 64 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23240,8 +22385,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 65 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 65 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23260,8 +22404,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23280,8 +22423,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23300,8 +22442,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23320,8 +22461,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23340,8 +22480,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23360,8 +22499,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23380,8 +22518,7 @@ - by 0x........: steer (tc19_shadowmem.c:418) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23417,8 +22554,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 66 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 66 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23437,8 +22573,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23457,8 +22592,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23477,8 +22611,7 @@ - by 0x........: steer (tc19_shadowmem.c:420) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23514,8 +22647,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 67 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 67 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23534,8 +22666,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23554,8 +22685,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23574,8 +22704,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23594,8 +22723,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23614,8 +22742,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23634,8 +22761,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23654,8 +22780,7 @@ - by 0x........: steer (tc19_shadowmem.c:422) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23691,8 +22816,7 @@ - by 0x........: steer (tc19_shadowmem.c:424) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 68 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 68 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23711,8 +22835,7 @@ - by 0x........: steer (tc19_shadowmem.c:424) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23748,8 +22871,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 69 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 69 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23768,8 +22890,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23788,8 +22909,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23808,8 +22928,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23828,8 +22947,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23848,8 +22966,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23868,8 +22985,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23888,8 +23004,7 @@ - by 0x........: steer (tc19_shadowmem.c:426) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23925,8 +23040,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 70 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 70 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23945,8 +23059,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23965,8 +23078,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -23985,8 +23097,7 @@ - by 0x........: steer (tc19_shadowmem.c:428) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24022,8 +23133,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 71 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 71 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24042,8 +23152,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24062,8 +23171,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24082,8 +23190,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24102,8 +23209,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24122,8 +23228,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24142,8 +23247,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24162,8 +23266,7 @@ - by 0x........: steer (tc19_shadowmem.c:430) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24199,8 +23302,7 @@ - by 0x........: steer (tc19_shadowmem.c:432) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 72 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 72 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24236,8 +23338,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 73 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 73 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24256,8 +23357,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24276,8 +23376,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24296,8 +23395,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24316,8 +23414,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24336,8 +23433,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24356,8 +23452,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24376,8 +23471,7 @@ - by 0x........: steer (tc19_shadowmem.c:434) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24413,8 +23507,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 74 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 74 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24433,8 +23526,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24453,8 +23545,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24473,8 +23564,7 @@ - by 0x........: steer (tc19_shadowmem.c:436) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24510,8 +23600,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 75 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 75 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24530,8 +23619,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24550,8 +23638,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24570,8 +23657,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24590,8 +23676,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24610,8 +23695,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24630,8 +23714,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24650,8 +23733,7 @@ - by 0x........: steer (tc19_shadowmem.c:438) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24687,8 +23769,7 @@ - by 0x........: steer (tc19_shadowmem.c:440) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 76 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 76 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24707,8 +23788,7 @@ - by 0x........: steer (tc19_shadowmem.c:440) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24744,8 +23824,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 77 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 77 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24764,8 +23843,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24784,8 +23862,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24804,8 +23881,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24824,8 +23900,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24844,8 +23919,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24864,8 +23938,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24884,8 +23957,7 @@ - by 0x........: steer (tc19_shadowmem.c:442) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24921,8 +23993,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 78 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 78 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24941,8 +24012,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24961,8 +24031,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -24981,8 +24050,7 @@ - by 0x........: steer (tc19_shadowmem.c:444) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25018,8 +24086,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 79 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 79 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25038,8 +24105,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25058,8 +24124,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25078,8 +24143,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25098,8 +24162,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25118,8 +24181,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25138,8 +24200,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25158,8 +24219,7 @@ - by 0x........: steer (tc19_shadowmem.c:446) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25195,8 +24255,7 @@ - by 0x........: steer (tc19_shadowmem.c:448) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 80 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 80 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25232,8 +24291,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 81 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 81 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25252,8 +24310,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25272,8 +24329,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25292,8 +24348,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25312,8 +24367,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25332,8 +24386,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25352,8 +24405,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25372,8 +24424,7 @@ - by 0x........: steer (tc19_shadowmem.c:450) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25409,8 +24460,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 82 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 82 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25429,8 +24479,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25449,8 +24498,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25469,8 +24517,7 @@ - by 0x........: steer (tc19_shadowmem.c:452) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25506,8 +24553,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 83 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 83 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25526,8 +24572,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25546,8 +24591,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25566,8 +24610,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25586,8 +24629,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25606,8 +24648,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25626,8 +24667,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25646,8 +24686,7 @@ - by 0x........: steer (tc19_shadowmem.c:454) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25683,8 +24722,7 @@ - by 0x........: steer (tc19_shadowmem.c:456) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 84 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 84 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25703,8 +24741,7 @@ - by 0x........: steer (tc19_shadowmem.c:456) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25740,8 +24777,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 85 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 85 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25760,8 +24796,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25780,8 +24815,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25800,8 +24834,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25820,8 +24853,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25840,8 +24872,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25860,8 +24891,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25880,8 +24910,7 @@ - by 0x........: steer (tc19_shadowmem.c:458) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25917,8 +24946,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 86 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 86 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25937,8 +24965,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25957,8 +24984,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -25977,8 +25003,7 @@ - by 0x........: steer (tc19_shadowmem.c:460) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26014,8 +25039,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 87 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 87 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26034,8 +25058,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26054,8 +25077,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26074,8 +25096,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26094,8 +25115,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26114,8 +25134,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26134,8 +25153,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 93 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 93 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26154,8 +25172,7 @@ - by 0x........: steer (tc19_shadowmem.c:462) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26191,8 +25208,7 @@ - by 0x........: steer (tc19_shadowmem.c:464) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 88 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 88 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26228,8 +25244,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 89 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 89 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26248,8 +25263,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26268,8 +25282,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26288,8 +25301,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26308,8 +25320,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 93 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 93 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26328,8 +25339,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26348,8 +25358,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 95 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 95 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26368,8 +25377,7 @@ - by 0x........: steer (tc19_shadowmem.c:466) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26405,8 +25413,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 90 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 90 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26425,8 +25432,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26445,8 +25451,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26465,8 +25470,7 @@ - by 0x........: steer (tc19_shadowmem.c:468) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26502,8 +25506,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 91 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 91 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26522,8 +25525,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 92 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 92 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26542,8 +25544,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 93 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 93 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26562,8 +25563,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 94 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 94 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26582,8 +25582,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 95 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 95 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26602,8 +25601,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 96 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 96 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26622,8 +25620,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 97 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 97 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -@@ -26642,8 +25639,7 @@ - by 0x........: steer (tc19_shadowmem.c:470) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -- --Address 0x........ is 98 bytes inside a block of size 100 alloc'd -+ Address 0x........ is 98 bytes inside a block of size 100 alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (tc19_shadowmem.c:144) - -Index: helgrind/tests/tc20_verifywrap.stderr.exp -=================================================================== ---- helgrind/tests/tc20_verifywrap.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc20_verifywrap.stderr.exp (.../trunk) (revision 13981) -@@ -28,10 +28,9 @@ - at 0x........: racy_child (tc20_verifywrap.c:34) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "unprotected" -+ declared at tc20_verifywrap.c:27 - --Location 0x........ is 0 bytes inside global var "unprotected" --declared at tc20_verifywrap.c:27 -- - ---------------------------------------------------------------- - - Thread #x's call to pthread_join failed -Index: helgrind/tests/tc20_verifywrap.stderr.exp-mips32-b -=================================================================== ---- helgrind/tests/tc20_verifywrap.stderr.exp-mips32-b (.../tags/VALGRIND_3_9_0) (revision 0) -+++ helgrind/tests/tc20_verifywrap.stderr.exp-mips32-b (.../trunk) (revision 13981) -@@ -0,0 +1,238 @@ -+ -+ -+ -+------ This is output for >= glibc 2.4 ------ -+ -+---------------- pthread_create/join ---------------- -+ -+---Thread-Announcement------------------------------------------ -+ -+Thread #x is the program's root thread -+ -+---Thread-Announcement------------------------------------------ -+ -+Thread #x was created -+ ... -+ by 0x........: pthread_create_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_create@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:76) -+ -+---------------------------------------------------------------- -+ -+Possible data race during write of size 2 at 0x........ by thread #x -+Locks held: none -+ at 0x........: main (tc20_verifywrap.c:78) -+ -+This conflicts with a previous write of size 2 by thread #x -+Locks held: none -+ at 0x........: racy_child (tc20_verifywrap.c:34) -+ by 0x........: mythread_wrapper (hg_intercepts.c:...) -+ ... -+ -+Location 0x........ is 0 bytes inside global var "unprotected" -+declared at tc20_verifywrap.c:27 -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_join failed -+ with error code 45 (EDEADLK: Resource deadlock would occur) -+ at 0x........: pthread_join_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_join (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:83) -+ -+ -+---------------- pthread_mutex_lock et al ---------------- -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_mutex_init failed -+ with error code 122 (EOPNOTSUPP: Operation not supported on transport endpoint) -+ at 0x........: pthread_mutex_init (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:92) -+ -+---------------------------------------------------------------- -+ -+Thread #x: pthread_mutex_destroy of a locked mutex -+ at 0x........: pthread_mutex_destroy (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:102) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_mutex_destroy failed -+ with error code 16 (EBUSY: Device or resource busy) -+ at 0x........: pthread_mutex_destroy (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:102) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_mutex_lock failed -+ with error code 22 (EINVAL: Invalid argument) -+ at 0x........: pthread_mutex_lock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:108) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_mutex_trylock failed -+ with error code 22 (EINVAL: Invalid argument) -+ at 0x........: pthread_mutex_trylock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:116) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_mutex_timedlock failed -+ with error code 22 (EINVAL: Invalid argument) -+ at 0x........: pthread_mutex_timedlock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:121) -+ -+---------------------------------------------------------------- -+ -+Thread #x unlocked an invalid lock at 0x........ -+ at 0x........: pthread_mutex_unlock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:125) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_mutex_unlock failed -+ with error code 22 (EINVAL: Invalid argument) -+ at 0x........: pthread_mutex_unlock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:125) -+ -+ -+---------------- pthread_cond_wait et al ---------------- -+ -+---------------------------------------------------------------- -+ -+Thread #x: pthread_cond_{timed}wait called with un-held mutex -+ at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:147) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_cond_wait failed -+ with error code 1 (EPERM: Operation not permitted) -+ at 0x........: pthread_cond_wait_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_cond_wait@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:147) -+ -+---------------------------------------------------------------- -+ -+Thread #x: pthread_cond_{signal,broadcast}: dubious: associated lock is not held by any thread -+ at 0x........: pthread_cond_signal_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_cond_signal@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:152) -+ -+ -+FIXME: can't figure out how to verify wrap of pthread_cond_signal -+ -+---------------------------------------------------------------- -+ -+Thread #x: pthread_cond_{signal,broadcast}: dubious: associated lock is not held by any thread -+ at 0x........: pthread_cond_broadcast_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_cond_broadcast@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:158) -+ -+ -+FIXME: can't figure out how to verify wrap of pthread_broadcast_signal -+ -+---------------------------------------------------------------- -+ -+Thread #x: pthread_cond_{timed}wait called with un-held mutex -+ at 0x........: pthread_cond_timedwait_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:165) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to pthread_cond_timedwait failed -+ with error code 22 (EINVAL: Invalid argument) -+ at 0x........: pthread_cond_timedwait_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_cond_timedwait@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:165) -+ -+ -+---------------- pthread_rwlock_* ---------------- -+ -+---------------------------------------------------------------- -+ -+Thread #x unlocked a not-locked lock at 0x........ -+ at 0x........: pthread_rwlock_unlock_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_rwlock_unlock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:179) -+ Lock at 0x........ was first observed -+ at 0x........: pthread_rwlock_init_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_rwlock_init (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:178) -+ -+(1) no error on next line -+(2) no error on next line -+(3) ERROR on next line -+---------------------------------------------------------------- -+ -+Thread #x unlocked a not-locked lock at 0x........ -+ at 0x........: pthread_rwlock_unlock_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_rwlock_unlock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:196) -+ Lock at 0x........ was first observed -+ at 0x........: pthread_rwlock_init_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_rwlock_init (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:186) -+ -+(4) no error on next line -+(5) no error on next line -+(6) no error on next line -+(7) no error on next line -+(8) ERROR on next line -+---------------------------------------------------------------- -+ -+Thread #x unlocked a not-locked lock at 0x........ -+ at 0x........: pthread_rwlock_unlock_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_rwlock_unlock (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:212) -+ Lock at 0x........ was first observed -+ at 0x........: pthread_rwlock_init_WRK (hg_intercepts.c:...) -+ by 0x........: pthread_rwlock_init (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:186) -+ -+ -+---------------- sem_* ---------------- -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to sem_init failed -+ with error code 22 (EINVAL: Invalid argument) -+ at 0x........: sem_init_WRK (hg_intercepts.c:...) -+ by 0x........: sem_init@* (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:228) -+ -+ -+FIXME: can't figure out how to verify wrap of sem_destroy -+ -+---------------------------------------------------------------- -+ -+Thread #x: Bug in libpthread: sem_wait succeeded on semaphore without prior sem_post -+ at 0x........: sem_wait_WRK (hg_intercepts.c:...) -+ by 0x........: sem_wait (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:242) -+ -+---------------------------------------------------------------- -+ -+Thread #x's call to sem_post failed -+ with error code 89 (ENOSYS: Function not implemented) -+ at 0x........: sem_post_WRK (hg_intercepts.c:...) -+ by 0x........: sem_post (hg_intercepts.c:...) -+ by 0x........: main (tc20_verifywrap.c:245) -+ -+ -+FIXME: can't figure out how to verify wrap of sem_post -+ -+ -+------------ dealloc of mem holding locks ------------ -+ -+---------------------------------------------------------------- -+ -+Thread #x: Exiting thread still holds 1 lock -+ ... -+ -+ -+ERROR SUMMARY: 23 errors from 23 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc21_pthonce.c -=================================================================== ---- helgrind/tests/tc21_pthonce.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc21_pthonce.c (.../trunk) (revision 13981) -@@ -81,6 +81,7 @@ - - id_arg = (int *)malloc(NUM_THREADS*sizeof(int)); - -+ printf("main: Hello\n"); - for (i = 0; i < NUM_THREADS; i++) { - id_arg[i] = i; - r= pthread_create(&threads[i], NULL, child, &id_arg[i]); -Index: helgrind/tests/tc21_pthonce.stderr.exp -=================================================================== ---- helgrind/tests/tc21_pthonce.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc21_pthonce.stderr.exp (.../trunk) (revision 13981) -@@ -5,7 +5,7 @@ - ... - by 0x........: pthread_create_WRK (hg_intercepts.c:...) - by 0x........: pthread_create@* (hg_intercepts.c:...) -- by 0x........: main (tc21_pthonce.c:86) -+ by 0x........: main (tc21_pthonce.c:87) - - ---Thread-Announcement------------------------------------------ - -@@ -13,7 +13,7 @@ - ... - by 0x........: pthread_create_WRK (hg_intercepts.c:...) - by 0x........: pthread_create@* (hg_intercepts.c:...) -- by 0x........: main (tc21_pthonce.c:86) -+ by 0x........: main (tc21_pthonce.c:87) - - ---------------------------------------------------------------- - -@@ -28,10 +28,9 @@ - at 0x........: child (tc21_pthonce.c:74) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "unprotected2" -+ declared at tc21_pthonce.c:51 - --Location 0x........ is 0 bytes inside global var "unprotected2" --declared at tc21_pthonce.c:51 -- - ---------------------------------------------------------------- - - Possible data race during write of size 4 at 0x........ by thread #x -@@ -45,9 +44,8 @@ - at 0x........: child (tc21_pthonce.c:74) - by 0x........: mythread_wrapper (hg_intercepts.c:...) - ... -+ Location 0x........ is 0 bytes inside global var "unprotected2" -+ declared at tc21_pthonce.c:51 - --Location 0x........ is 0 bytes inside global var "unprotected2" --declared at tc21_pthonce.c:51 - -- - ERROR SUMMARY: 2 errors from 2 contexts (suppressed: 0 from 0) -Index: helgrind/tests/tc21_pthonce.stdout.exp -=================================================================== ---- helgrind/tests/tc21_pthonce.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ helgrind/tests/tc21_pthonce.stdout.exp (.../trunk) (revision 13981) -@@ -1,3 +1,4 @@ -+main: Hello - welcome: Welcome - child: Hi, I'm thread 0 - child: Hi, I'm thread 1 -Index: include/Makefile.am -=================================================================== ---- include/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/Makefile.am (.../trunk) (revision 13981) -@@ -4,6 +4,7 @@ - nobase_pkginclude_HEADERS = \ - pub_tool_basics.h \ - pub_tool_basics_asm.h \ -+ pub_tool_addrinfo.h \ - pub_tool_aspacehl.h \ - pub_tool_aspacemgr.h \ - pub_tool_clientstate.h \ -@@ -25,6 +26,7 @@ - pub_tool_mallocfree.h \ - pub_tool_options.h \ - pub_tool_oset.h \ -+ pub_tool_rangemap.h \ - pub_tool_redir.h \ - pub_tool_replacemalloc.h \ - pub_tool_seqmatch.h \ -@@ -42,6 +44,7 @@ - vki/vki-linux.h \ - vki/vki-darwin.h \ - vki/vki-posixtypes-amd64-linux.h \ -+ vki/vki-posixtypes-arm64-linux.h \ - vki/vki-posixtypes-ppc32-linux.h \ - vki/vki-posixtypes-ppc64-linux.h \ - vki/vki-posixtypes-x86-linux.h \ -@@ -50,6 +53,7 @@ - vki/vki-posixtypes-mips32-linux.h \ - vki/vki-posixtypes-mips64-linux.h \ - vki/vki-amd64-linux.h \ -+ vki/vki-arm64-linux.h \ - vki/vki-ppc32-linux.h \ - vki/vki-ppc64-linux.h \ - vki/vki-x86-linux.h \ -@@ -58,6 +62,7 @@ - vki/vki-mips32-linux.h \ - vki/vki-mips64-linux.h \ - vki/vki-scnums-amd64-linux.h \ -+ vki/vki-scnums-arm64-linux.h \ - vki/vki-scnums-ppc32-linux.h \ - vki/vki-scnums-ppc64-linux.h \ - vki/vki-scnums-x86-linux.h \ -@@ -74,6 +79,7 @@ - vki/vki-xen-memory.h \ - vki/vki-xen-mmuext.h \ - vki/vki-xen-sysctl.h \ -+ vki/vki-xen-tmem.h \ - vki/vki-xen-version.h \ - vki/vki-xen-x86.h \ - vki/vki-linux-drm.h -Index: include/pub_tool_addrinfo.h -=================================================================== ---- include/pub_tool_addrinfo.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ include/pub_tool_addrinfo.h (.../trunk) (revision 13981) -@@ -0,0 +1,153 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Obtaining information about an address. pub_tool_addrinfo.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2000-2013 Julian Seward -+ jseward@acm.org -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __PUB_TOOL_ADDRINFO_H -+#define __PUB_TOOL_ADDRINFO_H -+ -+#include "pub_tool_basics.h" // VG_ macro -+ -+/*====================================================================*/ -+/*=== Obtaining information about an address ===*/ -+/*====================================================================*/ -+ -+// Different kinds of blocks. -+// Block_Mallocd is used by tools that maintain detailed information about -+// Client allocated heap blocks. -+// Block_Freed is used by tools such as memcheck that maintain a 'quarantine' -+// list of blocks freed by the Client but not yet physically freed. -+// Block_MempoolChunk and Block_UserG are used for mempool or user defined heap -+// blocks. -+// Block_ClientArenaMallocd and Block_ClientArenaFree are used when the tool -+// replaces the malloc/free/... functions but does not maintain detailed -+// information about Client allocated heap blocks. -+// Block_ValgrindArenaMallocd and Block_ValgrindArenaFree are used for heap -+// blocks of Valgrind internal heap. -+typedef enum { -+ Block_Mallocd = 111, -+ Block_Freed, -+ Block_MempoolChunk, -+ Block_UserG, -+ Block_ClientArenaMallocd, -+ Block_ClientArenaFree, -+ Block_ValgrindArenaMallocd, -+ Block_ValgrindArenaFree, -+} BlockKind; -+ -+/* ------------------ Addresses -------------------- */ -+ -+/* The classification of a faulting address. */ -+typedef -+ enum { -+ Addr_Undescribed, // as-yet unclassified -+ Addr_Unknown, // classification yielded nothing useful -+ Addr_Block, // in malloc'd/free'd block -+ Addr_Stack, // on a thread's stack -+ Addr_DataSym, // in a global data sym -+ Addr_Variable, // variable described by the debug info -+ Addr_SectKind // last-ditch classification attempt -+ } -+ AddrTag; -+ -+typedef -+ struct _AddrInfo -+ AddrInfo; -+ -+struct _AddrInfo { -+ AddrTag tag; -+ union { -+ // As-yet unclassified. -+ struct { } Undescribed; -+ -+ // On a stack. -+ struct { -+ ThreadId tid; // Which thread's stack? -+ } Stack; -+ -+ // This covers heap blocks (normal and from mempools), user-defined -+ // blocks and Arena blocks. -+ struct { -+ BlockKind block_kind; -+ const HChar* block_desc; // "block","mempool","user-defined",arena -+ SizeT block_szB; -+ PtrdiffT rwoffset; -+ ExeContext* allocated_at; // might be null_ExeContext. -+ ExeContext* freed_at; // might be null_ExeContext. -+ } Block; -+ -+ // In a global .data symbol. This holds the first 127 chars of -+ // the variable's name (zero terminated), plus a (memory) offset. -+ struct { -+ HChar name[128]; -+ PtrdiffT offset; -+ } DataSym; -+ -+ // Is described by Dwarf debug info. XArray*s of HChar. -+ struct { -+ XArray* /* of HChar */ descr1; -+ XArray* /* of HChar */ descr2; -+ } Variable; -+ -+ // Could only narrow it down to be the PLT/GOT/etc of a given -+ // object. Better than nothing, perhaps. -+ struct { -+ HChar objname[128]; -+ VgSectKind kind; -+ } SectKind; -+ -+ // Classification yielded nothing useful. -+ struct { } Unknown; -+ -+ } Addr; -+}; -+ -+ -+/* Describe an address as best you can, putting the result in ai. -+ On entry, ai->tag must be equal to Addr_Undescribed. -+ This might allocate some memory, that can be cleared with -+ VG_(clear_addrinfo). */ -+extern void VG_(describe_addr) ( Addr a, /*OUT*/AddrInfo* ai ); -+ -+extern void VG_(clear_addrinfo) ( AddrInfo* ai); -+ -+/* Prints the AddrInfo ai describing a. */ -+extern void VG_(pp_addrinfo) ( Addr a, AddrInfo* ai ); -+ -+/* Same as VG_(pp_addrinfo) but provides some memcheck specific behaviour: -+ * maybe_gcc indicates Addr a was just below the stack ptr when the error -+ with a was encountered. -+ * the message for Unknown tag is slightly different, as memcheck -+ has a recently freed list. */ -+extern void VG_(pp_addrinfo_mc) ( Addr a, AddrInfo* ai, Bool maybe_gcc ); -+ -+#endif // __PUB_TOOL_ADDRINFO_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/pub_tool_basics.h -=================================================================== ---- include/pub_tool_basics.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_basics.h (.../trunk) (revision 13981) -@@ -269,7 +269,8 @@ - #undef VG_LITTLEENDIAN - - #if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \ -- || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEL)) -+ || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEL)) \ -+ || defined(VGA_arm64) - # define VG_LITTLEENDIAN 1 - #elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \ - || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEB)) -@@ -283,7 +284,8 @@ - # define VG_REGPARM(n) __attribute__((regparm(n))) - #elif defined(VGA_amd64) || defined(VGA_ppc32) \ - || defined(VGA_ppc64) || defined(VGA_arm) || defined(VGA_s390x) \ -- || defined(VGA_mips32) || defined(VGA_mips64) -+ || defined(VGA_mips32) || defined(VGA_mips64) \ -+ || defined(VGA_arm64) - # define VG_REGPARM(n) /* */ - #else - # error Unknown arch -Index: include/pub_tool_gdbserver.h -=================================================================== ---- include/pub_tool_gdbserver.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_gdbserver.h (.../trunk) (revision 13981) -@@ -180,12 +180,20 @@ - /* Extract an address and (optionally) a size from the string - currently being parsed by strtok_r (see pub_tool_libcbase.h). - If no size in the string, keeps the current value of szB. -- Returns address 0 and szB 0 if there is an error. Reports to the -- user problems via VG_(gdb_printf). */ --extern void VG_(strtok_get_address_and_size) (Addr* address, -+ If parsing is ok, -+ returns True. -+ If parsing is not ok; -+ set *address and *szB to 0, -+ reports problem to the user using VG_(gdb_printf) -+ returns False. */ -+extern Bool VG_(strtok_get_address_and_size) (Addr* address, - SizeT* szB, - HChar **ssaveptr); - -+/* Print various statistics about Valgrind core, -+ and optionally tool and memory statistics. */ -+extern void VG_(print_all_stats) (Bool memory_stats, Bool tool_stats); -+ - #endif // __PUB_TOOL_GDBSERVER_H - - /*--------------------------------------------------------------------*/ -Index: include/pub_tool_libcbase.h -=================================================================== ---- include/pub_tool_libcbase.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_libcbase.h (.../trunk) (revision 13981) -@@ -111,6 +111,24 @@ - False. */ - extern Bool VG_(parse_Addr) ( const HChar** ppc, Addr* result ); - -+/* Parse an "enum set" made of one or more words comma separated. -+ The allowed word values are given in 'tokens', separated by comma. -+ If a word in 'tokens' is found in 'input', the corresponding bit -+ will be set in *enum_set (words in 'tokens' are numbered starting from 0). -+ Using in 'tokens' the special token "-" (a minus character) indicates that -+ the corresponding bit position cannot be set. -+ In addition to the words specified in 'tokens', VG_(parse_enum_set) -+ automatically accept the words "none" and "all" to indicate respectively -+ an empty enum_set (0) or an enum_set with all bits corresponding -+ to the words in tokens set. -+ If "none" or "all" is present in 'input', no other word can be given -+ in 'input'. -+ If parsing is successful, returns True and sets *enum_set. -+ If parsing fails, returns False. */ -+extern Bool VG_(parse_enum_set) ( const HChar *tokens, -+ const HChar *input, -+ UInt *enum_set); -+ - /* Like strncpy(), but if 'src' is longer than 'ndest' inserts a '\0' as the - last character. */ - extern void VG_(strncpy_safely) ( HChar* dest, const HChar* src, SizeT ndest ); -@@ -124,7 +142,7 @@ - extern void* VG_(memset) ( void *s, Int c, SizeT sz ); - extern Int VG_(memcmp) ( const void* s1, const void* s2, SizeT n ); - --/* Zero out up to 8 words quickly in-line. Do not use this for blocks -+/* Zero out up to 12 words quickly in-line. Do not use this for blocks - of size which are unknown at compile time, since the whole point is - for it to be inlined, and then for gcc to remove all code except - for the relevant 'sz' case. */ -@@ -135,6 +153,18 @@ - && LIKELY(0 == (((Addr)s) & (Addr)(sizeof(UWord)-1)))) { - UWord* p = (UWord*)s; - switch (sz / (SizeT)sizeof(UWord)) { -+ case 12: p[0] = p[1] = p[2] = p[3] -+ = p[4] = p[5] = p[6] = p[7] -+ = p[8] = p[9] = p[10] = p[11] = 0UL; return; -+ case 11: p[0] = p[1] = p[2] = p[3] -+ = p[4] = p[5] = p[6] = p[7] -+ = p[8] = p[9] = p[10] = 0UL; return; -+ case 10: p[0] = p[1] = p[2] = p[3] -+ = p[4] = p[5] = p[6] = p[7] -+ = p[8] = p[9] = 0UL; return; -+ case 9: p[0] = p[1] = p[2] = p[3] -+ = p[4] = p[5] = p[6] = p[7] -+ = p[8] = 0UL; return; - case 8: p[0] = p[1] = p[2] = p[3] - = p[4] = p[5] = p[6] = p[7] = 0UL; return; - case 7: p[0] = p[1] = p[2] = p[3] -Index: include/pub_tool_libcfile.h -=================================================================== ---- include/pub_tool_libcfile.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_libcfile.h (.../trunk) (revision 13981) -@@ -89,7 +89,7 @@ - extern Int VG_(rename) ( const HChar* old_name, const HChar* new_name ); - extern Int VG_(unlink) ( const HChar* file_name ); - --extern Int VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout); -+extern SysRes VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout); - - extern Int VG_(readlink)( const HChar* path, HChar* buf, UInt bufsize ); - extern Int VG_(getdents)( Int fd, struct vki_dirent *dirp, UInt count ); -Index: include/pub_tool_libcprint.h -=================================================================== ---- include/pub_tool_libcprint.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_libcprint.h (.../trunk) (revision 13981) -@@ -37,6 +37,18 @@ - Formatting functions - ------------------------------------------------------------------ */ - -+/* The formatting functions supports a subset (and 2 extensions) of -+ the 'printf' format. -+ The extensions are: -+ %pS : print a string (like %s) but escaping chars for XML safety. -+ %ps : with --xml=no, synonym for %s, with --xml=yes, synonym of %pS. -+ -+ Note: these extensions do not cause the compiler to barf with PRINTF_CHECK -+ as for the classical printf, %p requires a pointer, which must also -+ be provided for the %ps and %pS extensions. The s/S following %p -+ are understood by PRINTF_CHECK as characters to output. -+*/ -+ - extern UInt VG_(sprintf) ( HChar* buf, const HChar* format, ... ) - PRINTF_CHECK(2, 3); - -@@ -94,6 +106,12 @@ - extern UInt VG_(vprintf_xml) ( const HChar *format, va_list vargs ) - PRINTF_CHECK(1, 0); - -+/* Do a printf-style operation on either the XML -+ or normal output channel -+ or gdb output channel, depending on the setting of VG_(clo_xml) -+ and the state of VG_(log_output_sink). */ -+extern UInt VG_(emit) ( const HChar* format, ... ) PRINTF_CHECK(1, 2); -+ - /* Yet another, totally general, version of vprintf, which hands all - output bytes to CHAR_SINK, passing it OPAQUE as the second arg. */ - extern void VG_(vcbprintf)( void(*char_sink)(HChar, void* opaque), -Index: include/pub_tool_machine.h -=================================================================== ---- include/pub_tool_machine.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_machine.h (.../trunk) (revision 13981) -@@ -67,6 +67,12 @@ - # define VG_CLREQ_SZB 20 - # define VG_STACK_REDZONE_SZB 0 - -+#elif defined(VGP_arm64_linux) -+# define VG_MIN_INSTR_SZB 4 -+# define VG_MAX_INSTR_SZB 4 -+# define VG_CLREQ_SZB 20 -+# define VG_STACK_REDZONE_SZB 0 -+ - #elif defined(VGP_s390x_linux) - # define VG_MIN_INSTR_SZB 2 - # define VG_MAX_INSTR_SZB 6 -@@ -124,14 +130,6 @@ - /*DST*/Int shadowNo, PtrdiffT offset, SizeT size, - /*SRC*/const UChar* src ); - --// Sets the shadow values for the syscall return value register(s). --// This is platform specific. --void VG_(set_syscall_return_shadows) ( ThreadId tid, -- /* shadow vals for the result */ -- UWord s1res, UWord s2res, -- /* shadow vals for the error val */ -- UWord s1err, UWord s2err ); -- - // Apply a function 'f' to all the general purpose registers in all the - // current threads. This is all live threads, or (when the process is exiting) - // all threads that were instructed to die by the thread calling exit. -Index: include/pub_tool_options.h -=================================================================== ---- include/pub_tool_options.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_options.h (.../trunk) (revision 13981) -@@ -155,6 +155,14 @@ - can be changed dynamically.*/ - extern Int VG_(clo_vgdb_error); - -+/* If user has provided the --vgdb-prefix command line option, -+ VG_(arg_vgdb_prefix) points at the provided argument (including the -+ '--vgdb-prefix=' string). -+ Otherwise, it is NULL. -+ Typically, this is used by tools to produce user message with the -+ expected vgdb prefix argument, if the user has changed the default. */ -+extern const HChar *VG_(arg_vgdb_prefix); -+ - /* Emit all messages as XML? default: NO */ - /* If clo_xml is set, various other options are set in a non-default - way. See vg_main.c and mc_main.c. */ -Index: include/pub_tool_rangemap.h -=================================================================== ---- include/pub_tool_rangemap.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ include/pub_tool_rangemap.h (.../trunk) (revision 13981) -@@ -0,0 +1,83 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- A mapping where the keys exactly cover the address space. ---*/ -+/*--- pub_tool_rangemap.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2014-2014 Mozilla Foundation -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+/* Contributed by Julian Seward */ -+ -+#ifndef __PUB_TOOL_RANGEMAP_H -+#define __PUB_TOOL_RANGEMAP_H -+ -+//-------------------------------------------------------------------- -+// PURPOSE: a mapping from the host machine word (UWord) ranges to -+// arbitrary other UWord values. The set of ranges exactly covers all -+// possible UWord values. -+// -------------------------------------------------------------------- -+ -+/* It's an abstract type. */ -+typedef struct _RangeMap RangeMap; -+ -+/* Create a new RangeMap, using given allocation and free functions. -+ Alloc fn must not fail (that is, if it returns it must have -+ succeeded.) The new array will contain a single range covering the -+ entire key space, which will be bound to the value |initialVal|. */ -+RangeMap* VG_(newRangeMap) ( void*(*alloc_fn)(const HChar*,SizeT), -+ const HChar* cc, -+ void(*free_fn)(void*), -+ UWord initialVal ); -+ -+/* Free all memory associated with a RangeMap. */ -+void VG_(deleteRangeMap) ( RangeMap* ); -+ -+/* Bind the range [key_min, key_max] to val, overwriting any other -+ bindings existing in the range. Asserts if key_min > key_max. If -+ as a result of this addition, there come to be multiple adjacent -+ ranges with the same value, these ranges are merged together. Note -+ that this is slow: O(N) in the number of existing ranges. */ -+void VG_(bindRangeMap) ( RangeMap* rm, -+ UWord key_min, UWord key_max, UWord val ); -+ -+/* Looks up |key| in the array and returns the associated value and -+ the key bounds. Can never fail since the RangeMap covers the -+ entire key space. This is fast: O(log N) in the number of -+ ranges. */ -+void VG_(lookupRangeMap) ( /*OUT*/UWord* key_min, /*OUT*/UWord* key_max, -+ /*OUT*/UWord* val, RangeMap* rm, UWord key ); -+ -+/* How many elements are there in the map? */ -+Word VG_(sizeRangeMap) ( RangeMap* rm ); -+ -+/* Get the i'th component */ -+void VG_(indexRangeMap) ( /*OUT*/UWord* key_min, /*OUT*/UWord* key_max, -+ /*OUT*/UWord* val, RangeMap* rm, Word ix ); -+ -+#endif // __PUB_TOOL_RANGEMAP_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end pub_tool_rangemap.h ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/pub_tool_tooliface.h -=================================================================== ---- include/pub_tool_tooliface.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_tooliface.h (.../trunk) (revision 13981) -@@ -451,6 +451,20 @@ - Bool(*expensive_sanity_check)(void) - ); - -+/* Can the tool produce stats during execution? */ -+extern void VG_(needs_print_stats) ( -+ // Print out tool status. Note that the stats at end of execution -+ // should be output by the VG_(basic_tool_funcs) "fini" function. -+ void (*print_stats)(void) -+); -+ -+/* Has the tool a tool specific function to retrieve and print location info -+ of an address ? */ -+extern void VG_(needs_info_location) ( -+ // Get and pp information about Addr -+ void (*info_location)(Addr) -+); -+ - /* Do we need to see variable type and location information? */ - extern void VG_(needs_var_info) ( void ); - -Index: include/pub_tool_vkiscnums_asm.h -=================================================================== ---- include/pub_tool_vkiscnums_asm.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_vkiscnums_asm.h (.../trunk) (revision 13981) -@@ -51,6 +51,9 @@ - #elif defined(VGP_arm_linux) - # include "vki/vki-scnums-arm-linux.h" - -+#elif defined(VGP_arm64_linux) -+# include "vki/vki-scnums-arm64-linux.h" -+ - #elif defined(VGP_mips32_linux) - # include "vki/vki-scnums-mips32-linux.h" - -Index: include/pub_tool_xarray.h -=================================================================== ---- include/pub_tool_xarray.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/pub_tool_xarray.h (.../trunk) (revision 13981) -@@ -106,10 +106,10 @@ - /* Index into the XArray. Checks bounds and bombs if the index is - invalid. What this returns is the address of the specified element - in the array, not (of course) the element itself. Note that the -- element may get moved by subsequent addToXAs/sortXAs, so you should -- copy it out immediately and not regard its address as unchanging. -- Note also that indexXA will of course not return NULL if it -- succeeds. */ -+ element may get moved by subsequent calls to addToXA / sortXA / -+ insertIndexXA, so you should copy it out immediately and not regard -+ its address as unchanging. Note also that indexXA will of course -+ not return NULL if it succeeds. */ - extern void* VG_(indexXA) ( XArray*, Word ); - - /* Drop the last n elements of an XArray. Bombs if there are less -@@ -127,6 +127,13 @@ - array. */ - extern void VG_(removeIndexXA)( XArray*, Word ); - -+/* Insert an element into an XArray at the given index. The existing -+ element at the index and all above it are slid upwards one slot so -+ as to make space. Element is copied into the XArray. This is an -+ O(N) operation, when N is the number of elements after the -+ specified element, in the array. */ -+extern void VG_(insertIndexXA)( XArray*, Word, const void* elem ); -+ - /* Make a new, completely independent copy of the given XArray, using - the existing allocation function to allocate the new space. - Returns NULL if the allocation function didn't manage to allocate -Index: include/valgrind.h -=================================================================== ---- include/valgrind.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/valgrind.h (.../trunk) (revision 13981) -@@ -89,7 +89,7 @@ - || (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6)) - */ - #define __VALGRIND_MAJOR__ 3 --#define __VALGRIND_MINOR__ 8 -+#define __VALGRIND_MINOR__ 10 - - - #include -@@ -117,6 +117,7 @@ - #undef PLAT_ppc32_linux - #undef PLAT_ppc64_linux - #undef PLAT_arm_linux -+#undef PLAT_arm64_linux - #undef PLAT_s390x_linux - #undef PLAT_mips32_linux - #undef PLAT_mips64_linux -@@ -126,10 +127,12 @@ - # define PLAT_x86_darwin 1 - #elif defined(__APPLE__) && defined(__x86_64__) - # define PLAT_amd64_darwin 1 --#elif defined(__MINGW32__) || defined(__CYGWIN32__) \ -+#elif (defined(__MINGW32__) && !defined(__MINGW64__)) \ -+ || defined(__CYGWIN32__) \ - || (defined(_WIN32) && defined(_M_IX86)) - # define PLAT_x86_win32 1 --#elif defined(__MINGW64__) || (defined(_WIN64) && defined(_M_X64)) -+#elif defined(__MINGW64__) \ -+ || (defined(_WIN64) && defined(_M_X64)) - # define PLAT_amd64_win64 1 - #elif defined(__linux__) && defined(__i386__) - # define PLAT_x86_linux 1 -@@ -139,16 +142,16 @@ - # define PLAT_ppc32_linux 1 - #elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) - # define PLAT_ppc64_linux 1 --#elif defined(__linux__) && defined(__arm__) -+#elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__) - # define PLAT_arm_linux 1 -+#elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__) -+# define PLAT_arm64_linux 1 - #elif defined(__linux__) && defined(__s390__) && defined(__s390x__) - # define PLAT_s390x_linux 1 --#elif defined(__linux__) && defined(__mips__) --#if (__mips==64) -+#elif defined(__linux__) && defined(__mips__) && (__mips==64) - # define PLAT_mips64_linux 1 --#else -+#elif defined(__linux__) && defined(__mips__) && (__mips!=64) - # define PLAT_mips32_linux 1 --#endif - #else - /* If we're not compiling for our target platform, don't generate - any inline asms. */ -@@ -376,7 +379,8 @@ - - /* ------------------------ amd64-{linux,darwin} --------------- */ - --#if defined(PLAT_amd64_linux) || defined(PLAT_amd64_darwin) -+#if defined(PLAT_amd64_linux) || defined(PLAT_amd64_darwin) \ -+ || (defined(PLAT_amd64_win64) && defined(__GNUC__)) - - typedef - struct { -@@ -438,6 +442,14 @@ - - #endif /* PLAT_amd64_linux || PLAT_amd64_darwin */ - -+/* ------------------------- amd64-Win64 ------------------------- */ -+ -+#if defined(PLAT_amd64_win64) && !defined(__GNUC__) -+ -+#error Unsupported compiler. -+ -+#endif /* PLAT_amd64_win64 */ -+ - /* ------------------------ ppc32-linux ------------------------ */ - - #if defined(PLAT_ppc32_linux) -@@ -449,8 +461,8 @@ - OrigFn; - - #define __SPECIAL_INSTRUCTION_PREAMBLE \ -- "rlwinm 0,0,3,0,0 ; rlwinm 0,0,13,0,0\n\t" \ -- "rlwinm 0,0,29,0,0 ; rlwinm 0,0,19,0,0\n\t" -+ "rlwinm 0,0,3,0,31 ; rlwinm 0,0,13,0,31\n\t" \ -+ "rlwinm 0,0,29,0,31 ; rlwinm 0,0,19,0,31\n\t" - - #define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ - _zzq_default, _zzq_request, \ -@@ -654,6 +666,74 @@ - - #endif /* PLAT_arm_linux */ - -+/* ------------------------ arm64-linux ------------------------- */ -+ -+#if defined(PLAT_arm64_linux) -+ -+typedef -+ struct { -+ unsigned long long int nraddr; /* where's the code? */ -+ } -+ OrigFn; -+ -+#define __SPECIAL_INSTRUCTION_PREAMBLE \ -+ "ror x12, x12, #3 ; ror x12, x12, #13 \n\t" \ -+ "ror x12, x12, #51 ; ror x12, x12, #61 \n\t" -+ -+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ -+ _zzq_default, _zzq_request, \ -+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ -+ \ -+ __extension__ \ -+ ({volatile unsigned long long int _zzq_args[6]; \ -+ volatile unsigned long long int _zzq_result; \ -+ _zzq_args[0] = (unsigned long long int)(_zzq_request); \ -+ _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \ -+ _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \ -+ _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \ -+ _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \ -+ _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \ -+ __asm__ volatile("mov x3, %1\n\t" /*default*/ \ -+ "mov x4, %2\n\t" /*ptr*/ \ -+ __SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* X3 = client_request ( X4 ) */ \ -+ "orr x10, x10, x10\n\t" \ -+ "mov %0, x3" /*result*/ \ -+ : "=r" (_zzq_result) \ -+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \ -+ : "cc","memory", "x3", "x4"); \ -+ _zzq_result; \ -+ }) -+ -+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ -+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ -+ unsigned long long int __addr; \ -+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* X3 = guest_NRADDR */ \ -+ "orr x11, x11, x11\n\t" \ -+ "mov %0, x3" \ -+ : "=r" (__addr) \ -+ : \ -+ : "cc", "memory", "x3" \ -+ ); \ -+ _zzq_orig->nraddr = __addr; \ -+ } -+ -+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ __SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* branch-and-link-to-noredir X8 */ \ -+ "orr x12, x12, x12\n\t" -+ -+#define VALGRIND_VEX_INJECT_IR() \ -+ do { \ -+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ -+ "orr x9, x9, x9\n\t" \ -+ : : : "cc", "memory" \ -+ ); \ -+ } while (0) -+ -+#endif /* PLAT_arm64_linux */ -+ - /* ------------------------ s390x-linux ------------------------ */ - - #if defined(PLAT_s390x_linux) -@@ -3470,6 +3550,457 @@ - - #endif /* PLAT_arm_linux */ - -+/* ------------------------ arm64-linux ------------------------ */ -+ -+#if defined(PLAT_arm64_linux) -+ -+/* These regs are trashed by the hidden call. */ -+#define __CALLER_SAVED_REGS \ -+ "x0", "x1", "x2", "x3","x4", "x5", "x6", "x7", "x8", "x9", \ -+ "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", \ -+ "x18", "x19", "x20", "x30", \ -+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", \ -+ "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", \ -+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", \ -+ "v26", "v27", "v28", "v29", "v30", "v31" -+ -+/* x21 is callee-saved, so we can use it to save and restore SP around -+ the hidden call. */ -+#define VALGRIND_ALIGN_STACK \ -+ "mov x21, sp\n\t" \ -+ "bic sp, x21, #15\n\t" -+#define VALGRIND_RESTORE_STACK \ -+ "mov sp, x21\n\t" -+ -+/* These CALL_FN_ macros assume that on arm64-linux, -+ sizeof(unsigned long) == 8. */ -+ -+#define CALL_FN_W_v(lval, orig) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[1]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_W(lval, orig, arg1) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[2]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[4]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[5]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[6]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[7]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ _argvec[6] = (unsigned long)(arg6); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x5, [%1, #48] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[8]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ _argvec[6] = (unsigned long)(arg6); \ -+ _argvec[7] = (unsigned long)(arg7); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x5, [%1, #48] \n\t" \ -+ "ldr x6, [%1, #56] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[9]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ _argvec[6] = (unsigned long)(arg6); \ -+ _argvec[7] = (unsigned long)(arg7); \ -+ _argvec[8] = (unsigned long)(arg8); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x5, [%1, #48] \n\t" \ -+ "ldr x6, [%1, #56] \n\t" \ -+ "ldr x7, [%1, #64] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[10]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ _argvec[6] = (unsigned long)(arg6); \ -+ _argvec[7] = (unsigned long)(arg7); \ -+ _argvec[8] = (unsigned long)(arg8); \ -+ _argvec[9] = (unsigned long)(arg9); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "sub sp, sp, #0x20 \n\t" \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x5, [%1, #48] \n\t" \ -+ "ldr x6, [%1, #56] \n\t" \ -+ "ldr x7, [%1, #64] \n\t" \ -+ "ldr x8, [%1, #72] \n\t" \ -+ "str x8, [sp, #0] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9,arg10) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[11]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ _argvec[6] = (unsigned long)(arg6); \ -+ _argvec[7] = (unsigned long)(arg7); \ -+ _argvec[8] = (unsigned long)(arg8); \ -+ _argvec[9] = (unsigned long)(arg9); \ -+ _argvec[10] = (unsigned long)(arg10); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "sub sp, sp, #0x20 \n\t" \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x5, [%1, #48] \n\t" \ -+ "ldr x6, [%1, #56] \n\t" \ -+ "ldr x7, [%1, #64] \n\t" \ -+ "ldr x8, [%1, #72] \n\t" \ -+ "str x8, [sp, #0] \n\t" \ -+ "ldr x8, [%1, #80] \n\t" \ -+ "str x8, [sp, #8] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9,arg10,arg11) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[12]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ _argvec[6] = (unsigned long)(arg6); \ -+ _argvec[7] = (unsigned long)(arg7); \ -+ _argvec[8] = (unsigned long)(arg8); \ -+ _argvec[9] = (unsigned long)(arg9); \ -+ _argvec[10] = (unsigned long)(arg10); \ -+ _argvec[11] = (unsigned long)(arg11); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "sub sp, sp, #0x30 \n\t" \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x5, [%1, #48] \n\t" \ -+ "ldr x6, [%1, #56] \n\t" \ -+ "ldr x7, [%1, #64] \n\t" \ -+ "ldr x8, [%1, #72] \n\t" \ -+ "str x8, [sp, #0] \n\t" \ -+ "ldr x8, [%1, #80] \n\t" \ -+ "str x8, [sp, #8] \n\t" \ -+ "ldr x8, [%1, #88] \n\t" \ -+ "str x8, [sp, #16] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9,arg10,arg11, \ -+ arg12) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[13]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ _argvec[5] = (unsigned long)(arg5); \ -+ _argvec[6] = (unsigned long)(arg6); \ -+ _argvec[7] = (unsigned long)(arg7); \ -+ _argvec[8] = (unsigned long)(arg8); \ -+ _argvec[9] = (unsigned long)(arg9); \ -+ _argvec[10] = (unsigned long)(arg10); \ -+ _argvec[11] = (unsigned long)(arg11); \ -+ _argvec[12] = (unsigned long)(arg12); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "sub sp, sp, #0x30 \n\t" \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x4, [%1, #40] \n\t" \ -+ "ldr x5, [%1, #48] \n\t" \ -+ "ldr x6, [%1, #56] \n\t" \ -+ "ldr x7, [%1, #64] \n\t" \ -+ "ldr x8, [%1, #72] \n\t" \ -+ "str x8, [sp, #0] \n\t" \ -+ "ldr x8, [%1, #80] \n\t" \ -+ "str x8, [sp, #8] \n\t" \ -+ "ldr x8, [%1, #88] \n\t" \ -+ "str x8, [sp, #16] \n\t" \ -+ "ldr x8, [%1, #96] \n\t" \ -+ "str x8, [sp, #24] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "x21" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#endif /* PLAT_arm64_linux */ -+ - /* ------------------------- s390x-linux ------------------------- */ - - #if defined(PLAT_s390x_linux) -Index: include/vki/vki-amd64-linux.h -=================================================================== ---- include/vki/vki-amd64-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-amd64-linux.h (.../trunk) (revision 13981) -@@ -678,6 +678,13 @@ - #define VKI_PTRACE_SETFPREGS 15 - - //---------------------------------------------------------------------- -+// From linux-2.6.8.1/include/asm-generic/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 38 /* Function not implemented */ -+#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -+ -+//---------------------------------------------------------------------- - // And that's it! - //---------------------------------------------------------------------- - -Index: include/vki/vki-arm-linux.h -=================================================================== ---- include/vki/vki-arm-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-arm-linux.h (.../trunk) (revision 13981) -@@ -888,6 +888,13 @@ - #define VKI_HWCAP_NEON 4096 - - //---------------------------------------------------------------------- -+// From linux-2.6.8.1/include/asm-generic/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 38 /* Function not implemented */ -+#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -+ -+//---------------------------------------------------------------------- - // And that's it! - //---------------------------------------------------------------------- - -Index: include/vki/vki-arm64-linux.h -=================================================================== ---- include/vki/vki-arm64-linux.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ include/vki/vki-arm64-linux.h (.../trunk) (revision 13981) -@@ -0,0 +1,688 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- ARM64/Linux-specific kernel interface. vki-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VKI_ARM64_LINUX_H -+#define __VKI_ARM64_LINUX_H -+ -+// ARM64 is little-endian. -+#define VKI_LITTLE_ENDIAN 1 -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/int-ll64.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned char __vki_u8; -+ -+typedef __signed__ short __vki_s16; -+typedef unsigned short __vki_u16; -+ -+typedef __signed__ int __vki_s32; -+typedef unsigned int __vki_u32; -+ -+typedef __signed__ long long __vki_s64; -+typedef unsigned long long __vki_u64; -+ -+typedef unsigned short vki_u16; -+ -+typedef unsigned int vki_u32; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/arch/arm64/include/asm/page.h -+//---------------------------------------------------------------------- -+ -+/* Looks like arm64 can do both 4k and 64k pages, so we -+ use the at-startup detection scheme that ppc32/64 do. */ -+extern UWord VKI_PAGE_SHIFT; -+extern UWord VKI_PAGE_SIZE; -+#define VKI_MAX_PAGE_SHIFT 16 -+#define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/arch/arm64/include/asm/shmparam.h -+//---------------------------------------------------------------------- -+ -+// Trying to make sense of this .. it seems as if, for doing -+// shared memory with 64 bit processes, VKI_PAGE_SIZE is good -+// enough. But if sharing with a 32 bit process then we need -+// the old-style 16k value (4 * VKI_PAGE_SIZE) to be safe. -+// (From reading between the lines of arch/arm64/include/asm/shmparam.h) -+#define VKI_SHMLBA (4 * VKI_PAGE_SIZE) -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/signal.h -+//---------------------------------------------------------------------- -+ -+#define _VKI_NSIG 64 -+#define _VKI_NSIG_BPW 64 -+#define _VKI_NSIG_WORDS (_VKI_NSIG / _VKI_NSIG_BPW) -+ -+typedef unsigned long vki_old_sigset_t; -+ -+typedef struct { -+ unsigned long sig[_VKI_NSIG_WORDS]; -+} vki_sigset_t; -+ -+#define VKI_SIGHUP 1 -+#define VKI_SIGINT 2 -+#define VKI_SIGQUIT 3 -+#define VKI_SIGILL 4 -+#define VKI_SIGTRAP 5 -+#define VKI_SIGABRT 6 -+#define VKI_SIGBUS 7 -+#define VKI_SIGFPE 8 -+#define VKI_SIGKILL 9 -+#define VKI_SIGUSR1 10 -+#define VKI_SIGSEGV 11 -+#define VKI_SIGUSR2 12 -+#define VKI_SIGPIPE 13 -+#define VKI_SIGALRM 14 -+#define VKI_SIGTERM 15 -+#define VKI_SIGSTKFLT 16 -+#define VKI_SIGCHLD 17 -+#define VKI_SIGCONT 18 -+#define VKI_SIGSTOP 19 -+#define VKI_SIGTSTP 20 -+#define VKI_SIGTTIN 21 -+#define VKI_SIGTTOU 22 -+#define VKI_SIGURG 23 -+#define VKI_SIGXCPU 24 -+#define VKI_SIGXFSZ 25 -+#define VKI_SIGVTALRM 26 -+#define VKI_SIGPROF 27 -+#define VKI_SIGWINCH 28 -+#define VKI_SIGIO 29 -+#define VKI_SIGPWR 30 -+#define VKI_SIGSYS 31 -+#define VKI_SIGUNUSED 31 -+ -+#define VKI_SIGRTMIN 32 -+#define VKI_SIGRTMAX _VKI_NSIG -+ -+#define VKI_SA_NOCLDSTOP 0x00000001 -+#define VKI_SA_NOCLDWAIT 0x00000002 -+#define VKI_SA_SIGINFO 0x00000004 -+#define VKI_SA_ONSTACK 0x08000000 -+#define VKI_SA_RESTART 0x10000000 -+#define VKI_SA_NODEFER 0x40000000 -+#define VKI_SA_RESETHAND 0x80000000 -+ -+#define VKI_SA_NOMASK VKI_SA_NODEFER -+#define VKI_SA_ONESHOT VKI_SA_RESETHAND -+ -+// This is obsolete and should not be defined for new archs -+#define VKI_SA_RESTORER 0x04000000 -+ -+#define VKI_SS_ONSTACK 1 -+#define VKI_SS_DISABLE 2 -+ -+#define VKI_MINSIGSTKSZ 2048 -+ -+#define VKI_SIG_BLOCK 0 /* for blocking signals */ -+#define VKI_SIG_UNBLOCK 1 /* for unblocking signals */ -+#define VKI_SIG_SETMASK 2 /* for setting the signal mask */ -+ -+typedef void __vki_signalfn_t(int); -+typedef __vki_signalfn_t __user *__vki_sighandler_t; -+ -+typedef void __vki_restorefn_t(void); -+typedef __vki_restorefn_t __user *__vki_sigrestore_t; -+ -+#define VKI_SIG_DFL ((__vki_sighandler_t)0) /* default signal handling */ -+#define VKI_SIG_IGN ((__vki_sighandler_t)1) /* ignore signal */ -+ -+struct vki_sigaction_base { -+ // [[Nb: a 'k' prefix is added to "sa_handler" because -+ // bits/sigaction.h (which gets dragged in somehow via signal.h) -+ // #defines it as something else. Since that is done for glibc's -+ // purposes, which we don't care about here, we use our own name.]] -+ __vki_sighandler_t ksa_handler; -+ unsigned long sa_flags; -+ __vki_sigrestore_t sa_restorer; // I don't think arm64 has this -+ vki_sigset_t sa_mask; /* mask last for extensibility */ -+}; -+ -+/* On Linux we use the same type for passing sigactions to -+ and from the kernel. Hence: */ -+typedef struct vki_sigaction_base vki_sigaction_toK_t; -+typedef struct vki_sigaction_base vki_sigaction_fromK_t; -+ -+ -+typedef struct vki_sigaltstack { -+ void __user *ss_sp; -+ int ss_flags; -+ vki_size_t ss_size; -+} vki_stack_t; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/arch/arm64/include/uapi/asm/sigcontext.h -+//---------------------------------------------------------------------- -+ -+struct vki_sigcontext { -+ __vki_u64 fault_address; -+ /* AArch64 registers */ -+ __vki_u64 regs[31]; -+ __vki_u64 sp; -+ __vki_u64 pc; -+ __vki_u64 pstate; -+ /* 4K reserved for FP/SIMD state and future expansion */ -+ __vki_u8 __reserved[4096] __attribute__((__aligned__(16))); -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/uapi/include/asm-generic/mman-common.h -+//---------------------------------------------------------------------- -+ -+#define VKI_PROT_READ 0x1 /* page can be read */ -+#define VKI_PROT_WRITE 0x2 /* page can be written */ -+#define VKI_PROT_EXEC 0x4 /* page can be executed */ -+#define VKI_PROT_NONE 0x0 /* page can not be accessed */ -+#define VKI_PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ -+#define VKI_PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ -+ -+#define VKI_MAP_SHARED 0x01 /* Share changes */ -+#define VKI_MAP_PRIVATE 0x02 /* Changes are private */ -+#define VKI_MAP_FIXED 0x10 /* Interpret addr exactly */ -+#define VKI_MAP_ANONYMOUS 0x20 /* don't use a file */ -+#define VKI_MAP_NORESERVE 0x4000 /* don't check for reservations */ -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/uapi/include/asm-generic/fcntl.h -+//---------------------------------------------------------------------- -+ -+#define VKI_O_ACCMODE 03 -+#define VKI_O_RDONLY 00 -+#define VKI_O_WRONLY 01 -+#define VKI_O_RDWR 02 -+#define VKI_O_CREAT 0100 /* not fcntl */ -+#define VKI_O_EXCL 0200 /* not fcntl */ -+#define VKI_O_TRUNC 01000 /* not fcntl */ -+#define VKI_O_APPEND 02000 -+#define VKI_O_NONBLOCK 04000 -+#define VKI_O_LARGEFILE 0100000 -+ -+#define VKI_AT_FDCWD -100 -+ -+#define VKI_F_DUPFD 0 /* dup */ -+#define VKI_F_GETFD 1 /* get close_on_exec */ -+#define VKI_F_SETFD 2 /* set/clear close_on_exec */ -+#define VKI_F_GETFL 3 /* get file->f_flags */ -+#define VKI_F_SETFL 4 /* set file->f_flags */ -+#define VKI_F_GETLK 5 -+#define VKI_F_SETLK 6 -+#define VKI_F_SETLKW 7 -+ -+#define VKI_F_SETOWN 8 /* for sockets. */ -+#define VKI_F_GETOWN 9 /* for sockets. */ -+#define VKI_F_SETSIG 10 /* for sockets. */ -+#define VKI_F_GETSIG 11 /* for sockets. */ -+ -+#define VKI_F_SETOWN_EX 15 -+#define VKI_F_GETOWN_EX 16 -+ -+#define VKI_F_OWNER_TID 0 -+#define VKI_F_OWNER_PID 1 -+#define VKI_F_OWNER_PGRP 2 -+ -+struct vki_f_owner_ex { -+ int type; -+ __vki_kernel_pid_t pid; -+}; -+ -+#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */ -+ -+#define VKI_F_LINUX_SPECIFIC_BASE 1024 -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/resource.h -+//---------------------------------------------------------------------- -+ -+#define VKI_RLIMIT_DATA 2 /* max data size */ -+#define VKI_RLIMIT_STACK 3 /* max stack size */ -+#define VKI_RLIMIT_CORE 4 /* max core file size */ -+#define VKI_RLIMIT_NOFILE 7 /* max number of open files */ -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/socket.h -+//---------------------------------------------------------------------- -+ -+#define VKI_SOL_SOCKET 1 -+ -+#define VKI_SO_TYPE 3 -+ -+#define VKI_SO_ATTACH_FILTER 26 -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/sockios.h -+//---------------------------------------------------------------------- -+ -+#define VKI_SIOCSPGRP 0x8902 -+#define VKI_SIOCGPGRP 0x8904 -+#define VKI_SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -+#define VKI_SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/stat.h -+//---------------------------------------------------------------------- -+ -+struct vki_stat { -+ unsigned long st_dev; -+ unsigned long st_ino; -+ unsigned int st_mode; -+ unsigned int st_nlink; -+ unsigned int st_uid; -+ unsigned int st_gid; -+ unsigned long st_rdev; -+ unsigned long __pad1; -+ long st_size; -+ int st_blksize; -+ int __pad2; -+ long st_blocks; -+ long st_atime; -+ unsigned long st_atime_nsec; -+ long st_mtime; -+ unsigned long st_mtime_nsec; -+ long st_ctime; -+ unsigned long st_ctime_nsec; -+ unsigned int __unused4; -+ unsigned int __unused5; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/statfs.h -+//---------------------------------------------------------------------- -+ -+struct vki_statfs { -+ long f_type; -+ long f_bsize; -+ long f_blocks; -+ long f_bfree; -+ long f_bavail; -+ long f_files; -+ long f_ffree; -+ __vki_kernel_fsid_t f_fsid; -+ long f_namelen; -+ long f_frsize; -+ long f_flags; -+ long f_spare[4]; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/termios.h -+//---------------------------------------------------------------------- -+ -+struct vki_winsize { -+ unsigned short ws_row; -+ unsigned short ws_col; -+ unsigned short ws_xpixel; -+ unsigned short ws_ypixel; -+}; -+ -+#define VKI_NCC 8 -+struct vki_termio { -+ unsigned short c_iflag; /* input mode flags */ -+ unsigned short c_oflag; /* output mode flags */ -+ unsigned short c_cflag; /* control mode flags */ -+ unsigned short c_lflag; /* local mode flags */ -+ unsigned char c_line; /* line discipline */ -+ unsigned char c_cc[VKI_NCC]; /* control characters */ -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/termbits.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned char vki_cc_t; -+typedef unsigned int vki_tcflag_t; -+ -+#define VKI_NCCS 19 -+struct vki_termios { -+ vki_tcflag_t c_iflag; /* input mode flags */ -+ vki_tcflag_t c_oflag; /* output mode flags */ -+ vki_tcflag_t c_cflag; /* control mode flags */ -+ vki_tcflag_t c_lflag; /* local mode flags */ -+ vki_cc_t c_line; /* line discipline */ -+ vki_cc_t c_cc[VKI_NCCS]; /* control characters */ -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/ioctl.h -+//---------------------------------------------------------------------- -+ -+#define _VKI_IOC_NRBITS 8 -+#define _VKI_IOC_TYPEBITS 8 -+#define _VKI_IOC_SIZEBITS 14 -+#define _VKI_IOC_DIRBITS 2 -+ -+#define _VKI_IOC_SIZEMASK ((1 << _VKI_IOC_SIZEBITS)-1) -+#define _VKI_IOC_DIRMASK ((1 << _VKI_IOC_DIRBITS)-1) -+ -+#define _VKI_IOC_NRSHIFT 0 -+#define _VKI_IOC_TYPESHIFT (_VKI_IOC_NRSHIFT+_VKI_IOC_NRBITS) -+#define _VKI_IOC_SIZESHIFT (_VKI_IOC_TYPESHIFT+_VKI_IOC_TYPEBITS) -+#define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS) -+ -+#define _VKI_IOC_NONE 0U -+#define _VKI_IOC_WRITE 1U -+#define _VKI_IOC_READ 2U -+ -+#define _VKI_IOC(dir,type,nr,size) \ -+ (((dir) << _VKI_IOC_DIRSHIFT) | \ -+ ((type) << _VKI_IOC_TYPESHIFT) | \ -+ ((nr) << _VKI_IOC_NRSHIFT) | \ -+ ((size) << _VKI_IOC_SIZESHIFT)) -+ -+#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) -+#define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),sizeof(size)) -+#define _VKI_IOW(type,nr,size) _VKI_IOC(_VKI_IOC_WRITE,(type),(nr),sizeof(size)) -+#define _VKI_IOWR(type,nr,size) _VKI_IOC(_VKI_IOC_READ|_VKI_IOC_WRITE,(type),(nr),sizeof(size)) -+ -+#define _VKI_IOC_DIR(nr) (((nr) >> _VKI_IOC_DIRSHIFT) & _VKI_IOC_DIRMASK) -+#define _VKI_IOC_SIZE(nr) (((nr) >> _VKI_IOC_SIZESHIFT) & _VKI_IOC_SIZEMASK) -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/ioctls.h -+//---------------------------------------------------------------------- -+ -+#define VKI_TCGETS 0x5401 -+#define VKI_TCSETS 0x5402 -+#define VKI_TCSETSW 0x5403 -+#define VKI_TCSETSF 0x5404 -+#define VKI_TCGETA 0x5405 -+#define VKI_TCSETA 0x5406 -+#define VKI_TCSETAW 0x5407 -+#define VKI_TCSETAF 0x5408 -+#define VKI_TCSBRK 0x5409 -+#define VKI_TCXONC 0x540A -+#define VKI_TCFLSH 0x540B -+#define VKI_TIOCSCTTY 0x540E -+#define VKI_TIOCGPGRP 0x540F -+#define VKI_TIOCSPGRP 0x5410 -+#define VKI_TIOCOUTQ 0x5411 -+#define VKI_TIOCGWINSZ 0x5413 -+#define VKI_TIOCSWINSZ 0x5414 -+#define VKI_TIOCMGET 0x5415 -+#define VKI_TIOCMBIS 0x5416 -+#define VKI_TIOCMBIC 0x5417 -+#define VKI_TIOCMSET 0x5418 -+#define VKI_FIONREAD 0x541B -+#define VKI_TIOCLINUX 0x541C -+#define VKI_FIONBIO 0x5421 -+#define VKI_TCSBRKP 0x5425 -+#define VKI_TIOCGPTN _VKI_IOR('T',0x30, unsigned int) -+#define VKI_TIOCSPTLCK _VKI_IOW('T',0x31, int) -+ -+#define VKI_FIONCLEX 0x5450 -+#define VKI_FIOCLEX 0x5451 -+#define VKI_FIOASYNC 0x5452 -+#define VKI_TIOCSERGETLSR 0x5459 -+ -+#define VKI_TIOCGICOUNT 0x545D -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/poll.h -+//---------------------------------------------------------------------- -+ -+#define VKI_POLLIN 0x0001 -+ -+struct vki_pollfd { -+ int fd; -+ short events; -+ short revents; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/arch/arm64/include/uapi/asm/ptrace.h -+//---------------------------------------------------------------------- -+ -+//ZZ struct vki_user_i387_struct { -+//ZZ unsigned short cwd; -+//ZZ unsigned short swd; -+//ZZ unsigned short twd; /* Note this is not the same as the 32bit/x87/FSAVE twd */ -+//ZZ unsigned short fop; -+//ZZ __vki_u64 rip; -+//ZZ __vki_u64 rdp; -+//ZZ __vki_u32 mxcsr; -+//ZZ __vki_u32 mxcsr_mask; -+//ZZ __vki_u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ -+//ZZ __vki_u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ -+//ZZ __vki_u32 padding[24]; -+//ZZ }; -+//ZZ -+//ZZ struct vki_user_regs_struct { -+//ZZ unsigned long r15,r14,r13,r12,rbp,rbx,r11,r10; -+//ZZ unsigned long r9,r8,rax,rcx,rdx,rsi,rdi,orig_rax; -+//ZZ unsigned long rip,cs,eflags; -+//ZZ unsigned long rsp,ss; -+//ZZ unsigned long fs_base, gs_base; -+//ZZ unsigned long ds,es,fs,gs; -+//ZZ }; -+ -+struct vki_user_pt_regs { -+ __vki_u64 regs[31]; -+ __vki_u64 sp; -+ __vki_u64 pc; -+ __vki_u64 pstate; -+}; -+ -+/* I think that the new name in the kernel for these is "user_pt_regs" -+ and the old name is "user_regs_struct". Unfortunately can't clone -+ a 'struct' type using 'typedef' and still have a 'struct' type, so -+ use a blunter instrument instead. */ -+#define vki_user_regs_struct vki_user_pt_regs -+ -+struct vki_user_fpsimd_state { -+ __uint128_t vregs[32]; -+ __vki_u32 fpsr; -+ __vki_u32 fpcr; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/arch/arm64/include/asm/elf.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned long vki_elf_greg_t; -+ -+#define VKI_ELF_NGREG (sizeof (struct vki_user_pt_regs) / sizeof(vki_elf_greg_t)) -+typedef vki_elf_greg_t vki_elf_gregset_t[VKI_ELF_NGREG]; -+ -+typedef struct vki_user_fpsimd_state vki_elf_fpregset_t; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/arch/arm64/include/asm/ucontext.h -+//---------------------------------------------------------------------- -+ -+struct vki_ucontext { -+ unsigned long uc_flags; -+ struct vki_ucontext *uc_link; -+ vki_stack_t uc_stack; -+ vki_sigset_t uc_sigmask; -+ /* glibc uses a 1024-bit sigset_t */ -+ __vki_u8 __unused[1024 / 8 - sizeof(vki_sigset_t)]; -+ /* last for future expansion */ -+ struct vki_sigcontext uc_mcontext; -+}; -+ -+//ZZ //---------------------------------------------------------------------- -+//ZZ // From linux-2.6.9/include/asm-x86_64/segment.h -+//ZZ //---------------------------------------------------------------------- -+//ZZ -+//ZZ #define VKI_GDT_ENTRY_TLS_ENTRIES 3 -+//ZZ -+//ZZ #define VKI_GDT_ENTRY_TLS_MIN 11 -+//ZZ #define VKI_GDT_ENTRY_TLS_MAX 13 -+//ZZ -+//ZZ //---------------------------------------------------------------------- -+//ZZ // From linux-2.6.11.9/include/asm-x86_64/prctl.h -+//ZZ //---------------------------------------------------------------------- -+//ZZ -+//ZZ #define VKI_ARCH_SET_GS 0x1001 -+//ZZ #define VKI_ARCH_SET_FS 0x1002 -+//ZZ #define VKI_ARCH_GET_FS 0x1003 -+//ZZ #define VKI_ARCH_GET_GS 0x1004 -+//ZZ -+//ZZ //---------------------------------------------------------------------- -+//ZZ // From linux-2.6.9/include/asm-x86_64/ldt.h -+//ZZ //---------------------------------------------------------------------- -+//ZZ -+//ZZ // I think this LDT stuff will have to be reinstated for amd64, but I'm not -+//ZZ // certain. (Nb: The sys_arch_prctl seems to have replaced -+//ZZ // [gs]et_thread_area syscalls.) -+//ZZ // -+//ZZ // Note that the type here is very slightly different to the -+//ZZ // type for x86 (the final 'lm' field is added); I'm not sure about the -+//ZZ // significance of that... --njn -+//ZZ -+//ZZ /* [[Nb: This is the structure passed to the modify_ldt syscall. Just so as -+//ZZ to confuse and annoy everyone, this is _not_ the same as an -+//ZZ VgLdtEntry and has to be translated into such. The logic for doing -+//ZZ so, in vg_ldt.c, is copied from the kernel sources.]] */ -+//ZZ /* Note also that a comment in ldt.h indicates that the below -+//ZZ contains several fields ignored on 64bit, and that modify_ldt -+//ZZ is rather for 32bit. */ -+//ZZ struct vki_user_desc { -+//ZZ unsigned int entry_number; -+//ZZ unsigned long base_addr; -+//ZZ unsigned int limit; -+//ZZ unsigned int seg_32bit:1; -+//ZZ unsigned int contents:2; -+//ZZ unsigned int read_exec_only:1; -+//ZZ unsigned int limit_in_pages:1; -+//ZZ unsigned int seg_not_present:1; -+//ZZ unsigned int useable:1; -+//ZZ unsigned int lm:1; -+//ZZ }; -+//ZZ -+//ZZ // [[Nb: for our convenience within Valgrind, use a more specific name]] -+//ZZ typedef struct vki_user_desc vki_modify_ldt_t; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/asm-generic/ipcbuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_ipc64_perm -+{ -+ __vki_kernel_key_t key; -+ __vki_kernel_uid32_t uid; -+ __vki_kernel_gid32_t gid; -+ __vki_kernel_uid32_t cuid; -+ __vki_kernel_gid32_t cgid; -+ __vki_kernel_mode_t mode; -+ unsigned char __pad1[4 - sizeof(__vki_kernel_mode_t)]; -+ unsigned short seq; -+ unsigned short __pad2; -+ unsigned long __unused1; -+ unsigned long __unused2; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/sembuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_semid64_ds { -+ struct vki_ipc64_perm sem_perm; /* permissions .. see ipc.h */ -+ __vki_kernel_time_t sem_otime; /* last semop time */ -+ __vki_kernel_time_t sem_ctime; /* last change time */ -+ unsigned long sem_nsems; /* no. of semaphores in array */ -+ unsigned long __unused3; -+ unsigned long __unused4; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/msgbuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_msqid64_ds { -+ struct vki_ipc64_perm msg_perm; -+ __vki_kernel_time_t msg_stime; /* last msgsnd time */ -+ __vki_kernel_time_t msg_rtime; /* last msgrcv time */ -+ __vki_kernel_time_t msg_ctime; /* last change time */ -+ unsigned long msg_cbytes; /* current number of bytes on queue */ -+ unsigned long msg_qnum; /* number of messages in queue */ -+ unsigned long msg_qbytes; /* max number of bytes on queue */ -+ __vki_kernel_pid_t msg_lspid; /* pid of last msgsnd */ -+ __vki_kernel_pid_t msg_lrpid; /* last receive pid */ -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/shmbuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_shmid64_ds { -+ struct vki_ipc64_perm shm_perm; /* operation perms */ -+ vki_size_t shm_segsz; /* size of segment (bytes) */ -+ __vki_kernel_time_t shm_atime; /* last attach time */ -+ __vki_kernel_time_t shm_dtime; /* last detach time */ -+ __vki_kernel_time_t shm_ctime; /* last change time */ -+ __vki_kernel_pid_t shm_cpid; /* pid of creator */ -+ __vki_kernel_pid_t shm_lpid; /* pid of last operator */ -+ unsigned long shm_nattch; /* no. of current attaches */ -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+struct vki_shminfo64 { -+ unsigned long shmmax; -+ unsigned long shmmin; -+ unsigned long shmmni; -+ unsigned long shmseg; -+ unsigned long shmall; -+ unsigned long __unused1; -+ unsigned long __unused2; -+ unsigned long __unused3; -+ unsigned long __unused4; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/arch/arm64/include/asm/ptrace.h -+//---------------------------------------------------------------------- -+ -+#define VKI_PTRACE_GETREGS 12 -+#define VKI_PTRACE_SETREGS 13 -+//#define VKI_PTRACE_GETFPREGS 14 -+//#define VKI_PTRACE_SETFPREGS 15 -+ -+//---------------------------------------------------------------------- -+// From linux-2.6.8.1/include/asm-generic/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 38 /* Function not implemented */ -+#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -+ -+//---------------------------------------------------------------------- -+// And that's it! -+//---------------------------------------------------------------------- -+ -+#endif // __VKI_ARM64_LINUX_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/vki/vki-linux.h -=================================================================== ---- include/vki/vki-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-linux.h (.../trunk) (revision 13981) -@@ -89,6 +89,8 @@ - # include "vki-posixtypes-ppc64-linux.h" - #elif defined(VGA_arm) - # include "vki-posixtypes-arm-linux.h" -+#elif defined(VGA_arm64) -+# include "vki-posixtypes-arm64-linux.h" - #elif defined(VGA_s390x) - # include "vki-posixtypes-s390x-linux.h" - #elif defined(VGA_mips32) -@@ -213,6 +215,8 @@ - # include "vki-ppc64-linux.h" - #elif defined(VGA_arm) - # include "vki-arm-linux.h" -+#elif defined(VGA_arm64) -+# include "vki-arm64-linux.h" - #elif defined(VGA_s390x) - # include "vki-s390x-linux.h" - #elif defined(VGA_mips32) -@@ -540,6 +544,9 @@ - #define VKI_SIGEV_PAD_SIZE ((VKI_SIGEV_MAX_SIZE - VKI___ARCH_SIGEV_PREAMBLE_SIZE) \ - / sizeof(int)) - -+/* This is the flag the kernel handles, userspace/glibc handles SEGEV_THEAD. */ -+#define VKI_SIGEV_THREAD_ID 4 -+ - typedef struct vki_sigevent { - vki_sigval_t sigev_value; - int sigev_signo; -@@ -555,6 +562,8 @@ - } _sigev_un; - } vki_sigevent_t; - -+#define vki_sigev_notify_thread_id _sigev_un._tid -+ - //---------------------------------------------------------------------- - // From elsewhere... - //---------------------------------------------------------------------- -@@ -1235,9 +1244,6 @@ - - #define VKI_EWOULDBLOCK VKI_EAGAIN - --#define VKI_ENOSYS 38 /* Function not implemented */ --#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -- - //---------------------------------------------------------------------- - // From linux-2.6.8.1/include/linux/wait.h - //---------------------------------------------------------------------- -@@ -2865,7 +2871,8 @@ - // From kernel/common/include/linux/ashmem.h - //---------------------------------------------------------------------- - --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - - #define VKI_ASHMEM_NAME_LEN 256 - -Index: include/vki/vki-mips32-linux.h -=================================================================== ---- include/vki/vki-mips32-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-mips32-linux.h (.../trunk) (revision 13981) -@@ -524,8 +524,8 @@ - - #define _VKI_IOC_NRBITS 8 - #define _VKI_IOC_TYPEBITS 8 --#define _VKI_IOC_SIZEBITS 14 --#define _VKI_IOC_DIRBITS 2 -+#define _VKI_IOC_SIZEBITS 13 -+#define _VKI_IOC_DIRBITS 3 - - #define _VKI_IOC_NRMASK ((1 << _VKI_IOC_NRBITS)-1) - #define _VKI_IOC_TYPEMASK ((1 << _VKI_IOC_TYPEBITS)-1) -@@ -538,8 +538,8 @@ - #define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS) - - #define _VKI_IOC_NONE 1U --#define _VKI_IOC_WRITE 2U --#define _VKI_IOC_READ 4U -+#define _VKI_IOC_READ 2U -+#define _VKI_IOC_WRITE 4U - - #define _VKI_IOC(dir,type,nr,size) \ - (((dir) << _VKI_IOC_DIRSHIFT) | \ -@@ -976,6 +976,13 @@ - }; - #define ARCH_HAS_SOCKET_TYPES 1 - -+//---------------------------------------------------------------------- -+// From linux-3.13.0/include/asm/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 89 /* Function not implemented */ -+#define VKI_EOVERFLOW 79 /* Value too large for defined data type */ -+ - #endif // __VKI_MIPS32_LINUX_H - - /*--------------------------------------------------------------------*/ -Index: include/vki/vki-mips64-linux.h -=================================================================== ---- include/vki/vki-mips64-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-mips64-linux.h (.../trunk) (revision 13981) -@@ -530,8 +530,8 @@ - - #define _VKI_IOC_NRBITS 8 - #define _VKI_IOC_TYPEBITS 8 --#define _VKI_IOC_SIZEBITS 14 --#define _VKI_IOC_DIRBITS 2 -+#define _VKI_IOC_SIZEBITS 13 -+#define _VKI_IOC_DIRBITS 3 - - #define _VKI_IOC_NRMASK ((1 << _VKI_IOC_NRBITS)-1) - #define _VKI_IOC_TYPEMASK ((1 << _VKI_IOC_TYPEBITS)-1) -@@ -544,8 +544,8 @@ - #define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS) - - #define _VKI_IOC_NONE 1U --#define _VKI_IOC_WRITE 2U --#define _VKI_IOC_READ 4U -+#define _VKI_IOC_READ 2U -+#define _VKI_IOC_WRITE 4U - - #define _VKI_IOC(dir,type,nr,size) \ - (((dir) << _VKI_IOC_DIRSHIFT) | \ -@@ -999,6 +999,13 @@ - }; - #define ARCH_HAS_SOCKET_TYPES 1 - -+//---------------------------------------------------------------------- -+// From linux-3.13.0/include/asm/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 89 /* Function not implemented */ -+#define VKI_EOVERFLOW 79 /* Value too large for defined data type */ -+ - #endif // __VKI_MIPS64_LINUX_H - - /*--------------------------------------------------------------------*/ -Index: include/vki/vki-posixtypes-arm64-linux.h -=================================================================== ---- include/vki/vki-posixtypes-arm64-linux.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ include/vki/vki-posixtypes-arm64-linux.h (.../trunk) (revision 13981) -@@ -0,0 +1,68 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- arm64/Linux-specific kernel interface: posix types. ---*/ -+/*--- vki-posixtypes-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VKI_POSIXTYPES_ARM64_LINUX_H -+#define __VKI_POSIXTYPES_ARM64_LINUX_H -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/posix_types.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned int __vki_kernel_mode_t; -+typedef long __vki_kernel_off_t; -+typedef int __vki_kernel_pid_t; -+typedef int __vki_kernel_ipc_pid_t; -+typedef unsigned int __vki_kernel_uid_t; -+typedef unsigned int __vki_kernel_gid_t; -+typedef unsigned long __vki_kernel_size_t; -+typedef long __vki_kernel_time_t; -+typedef long __vki_kernel_suseconds_t; -+typedef long __vki_kernel_clock_t; -+typedef int __vki_kernel_timer_t; -+typedef int __vki_kernel_clockid_t; -+typedef char * __vki_kernel_caddr_t; -+typedef unsigned int __vki_kernel_uid32_t; -+typedef unsigned int __vki_kernel_gid32_t; -+ -+typedef unsigned int __vki_kernel_old_uid_t; -+typedef unsigned int __vki_kernel_old_gid_t; -+ -+typedef long long __vki_kernel_loff_t; -+ -+typedef struct { -+ int val[2]; -+} __vki_kernel_fsid_t; -+ -+#endif // __VKI_POSIXTYPES_ARM64_LINUX_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end vki-posixtypes-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/vki/vki-ppc32-linux.h -=================================================================== ---- include/vki/vki-ppc32-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-ppc32-linux.h (.../trunk) (revision 13981) -@@ -63,8 +63,8 @@ - - /* PAGE_SHIFT determines the page size, unfortunately - page size might vary between 32-bit and 64-bit ppc kernels */ --extern unsigned long VKI_PAGE_SHIFT; --extern unsigned long VKI_PAGE_SIZE; -+extern UWord VKI_PAGE_SHIFT; -+extern UWord VKI_PAGE_SIZE; - #define VKI_MAX_PAGE_SHIFT 16 - #define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) - -@@ -921,6 +921,13 @@ - unsigned long __unused4; - }; - -+//---------------------------------------------------------------------- -+// From linux-2.6.8.1/include/asm-generic/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 38 /* Function not implemented */ -+#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -+ - //.. //---------------------------------------------------------------------- - //.. // DRM ioctls - //.. //---------------------------------------------------------------------- -Index: include/vki/vki-ppc64-linux.h -=================================================================== ---- include/vki/vki-ppc64-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-ppc64-linux.h (.../trunk) (revision 13981) -@@ -64,8 +64,8 @@ - - /* PAGE_SHIFT determines the page size, unfortunately - page size might vary between 32-bit and 64-bit ppc kernels */ --extern unsigned long VKI_PAGE_SHIFT; --extern unsigned long VKI_PAGE_SIZE; -+extern UWord VKI_PAGE_SHIFT; -+extern UWord VKI_PAGE_SIZE; - #define VKI_MAX_PAGE_SHIFT 16 - #define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) - -@@ -780,6 +780,13 @@ - }; - - //---------------------------------------------------------------------- -+// From linux-2.6.8.1/include/asm-generic/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 38 /* Function not implemented */ -+#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -+ -+//---------------------------------------------------------------------- - // end - //---------------------------------------------------------------------- - -Index: include/vki/vki-s390x-linux.h -=================================================================== ---- include/vki/vki-s390x-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-s390x-linux.h (.../trunk) (revision 13981) -@@ -957,6 +957,13 @@ - an error condition. I.e. the system call failed. */ - #define VKI_MAX_ERRNO -125 - -+//---------------------------------------------------------------------- -+// From linux-2.6.8.1/include/asm-generic/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 38 /* Function not implemented */ -+#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -+ - #endif // __VKI_S390X_LINUX_H - - /*--------------------------------------------------------------------*/ -Index: include/vki/vki-scnums-arm64-linux.h -=================================================================== ---- include/vki/vki-scnums-arm64-linux.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ include/vki/vki-scnums-arm64-linux.h (.../trunk) (revision 13981) -@@ -0,0 +1,510 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- System call numbers for arm64-linux. ---*/ -+/*--- vki-scnums-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VKI_SCNUMS_ARM64_LINUX_H -+#define __VKI_SCNUMS_ARM64_LINUX_H -+ -+// From linux-3.10.5/arch/arm64/include/uapi/asm/unistd.h -+// is a #include of -+// linux-3.10.5/include/uapi/asm-generic/unistd.h -+ -+#define __NR_io_setup 0 -+#define __NR_io_destroy 1 -+#define __NR_io_submit 2 -+#define __NR_io_cancel 3 -+#define __NR_io_getevents 4 -+#define __NR_setxattr 5 -+#define __NR_lsetxattr 6 -+#define __NR_fsetxattr 7 -+#define __NR_getxattr 8 -+#define __NR_lgetxattr 9 -+#define __NR_fgetxattr 10 -+#define __NR_listxattr 11 -+#define __NR_llistxattr 12 -+#define __NR_flistxattr 13 -+#define __NR_removexattr 14 -+#define __NR_lremovexattr 15 -+#define __NR_fremovexattr 16 -+#define __NR_getcwd 17 -+#define __NR_lookup_dcookie 18 -+#define __NR_eventfd2 19 -+#define __NR_epoll_create1 20 -+#define __NR_epoll_ctl 21 -+#define __NR_epoll_pwait 22 -+#define __NR_dup 23 -+#define __NR_dup3 24 -+#define __NR3264_fcntl 25 -+#define __NR_inotify_init1 26 -+#define __NR_inotify_add_watch 27 -+#define __NR_inotify_rm_watch 28 -+#define __NR_ioctl 29 -+#define __NR_ioprio_set 30 -+#define __NR_ioprio_get 31 -+#define __NR_flock 32 -+#define __NR_mknodat 33 -+#define __NR_mkdirat 34 -+#define __NR_unlinkat 35 -+#define __NR_symlinkat 36 -+#define __NR_linkat 37 -+#define __NR_renameat 38 -+#define __NR_umount2 39 -+#define __NR_mount 40 -+#define __NR_pivot_root 41 -+#define __NR_nfsservctl 42 -+#define __NR3264_statfs 43 -+#define __NR3264_fstatfs 44 -+#define __NR3264_truncate 45 -+#define __NR3264_ftruncate 46 -+#define __NR_fallocate 47 -+#define __NR_faccessat 48 -+#define __NR_chdir 49 -+#define __NR_fchdir 50 -+#define __NR_chroot 51 -+#define __NR_fchmod 52 -+#define __NR_fchmodat 53 -+#define __NR_fchownat 54 -+#define __NR_fchown 55 -+#define __NR_openat 56 -+#define __NR_close 57 -+#define __NR_vhangup 58 -+#define __NR_pipe2 59 -+#define __NR_quotactl 60 -+#define __NR_getdents64 61 -+#define __NR3264_lseek 62 -+#define __NR_read 63 -+#define __NR_write 64 -+#define __NR_readv 65 -+#define __NR_writev 66 -+#define __NR_pread64 67 -+#define __NR_pwrite64 68 -+#define __NR_preadv 69 -+#define __NR_pwritev 70 -+#define __NR3264_sendfile 71 -+#define __NR_pselect6 72 -+#define __NR_ppoll 73 -+#define __NR_signalfd4 74 -+#define __NR_vmsplice 75 -+#define __NR_splice 76 -+#define __NR_tee 77 -+#define __NR_readlinkat 78 -+#define __NR3264_fstatat 79 -+#define __NR3264_fstat 80 -+#define __NR_sync 81 -+#define __NR_fsync 82 -+#define __NR_fdatasync 83 -+ -+//#ifdef __ARCH_WANT_SYNC_FILE_RANGE2 -+//#define __NR_sync_file_range2 84 -+//#else -+#define __NR_sync_file_range 84 -+//#endif -+ -+#define __NR_timerfd_create 85 -+#define __NR_timerfd_settime 86 -+#define __NR_timerfd_gettime 87 -+#define __NR_utimensat 88 -+#define __NR_acct 89 -+#define __NR_capget 90 -+#define __NR_capset 91 -+#define __NR_personality 92 -+#define __NR_exit 93 -+#define __NR_exit_group 94 -+#define __NR_waitid 95 -+#define __NR_set_tid_address 96 -+#define __NR_unshare 97 -+#define __NR_futex 98 -+#define __NR_set_robust_list 99 -+#define __NR_get_robust_list 100 -+#define __NR_nanosleep 101 -+#define __NR_getitimer 102 -+#define __NR_setitimer 103 -+#define __NR_kexec_load 104 -+#define __NR_init_module 105 -+#define __NR_delete_module 106 -+#define __NR_timer_create 107 -+#define __NR_timer_gettime 108 -+#define __NR_timer_getoverrun 109 -+#define __NR_timer_settime 110 -+#define __NR_timer_delete 111 -+#define __NR_clock_settime 112 -+#define __NR_clock_gettime 113 -+#define __NR_clock_getres 114 -+#define __NR_clock_nanosleep 115 -+#define __NR_syslog 116 -+#define __NR_ptrace 117 -+#define __NR_sched_setparam 118 -+#define __NR_sched_setscheduler 119 -+#define __NR_sched_getscheduler 120 -+#define __NR_sched_getparam 121 -+#define __NR_sched_setaffinity 122 -+#define __NR_sched_getaffinity 123 -+#define __NR_sched_yield 124 -+#define __NR_sched_get_priority_max 125 -+#define __NR_sched_get_priority_min 126 -+#define __NR_sched_rr_get_interval 127 -+#define __NR_restart_syscall 128 -+#define __NR_kill 129 -+#define __NR_tkill 130 -+#define __NR_tgkill 131 -+#define __NR_sigaltstack 132 -+#define __NR_rt_sigsuspend 133 -+#define __NR_rt_sigaction 134 -+#define __NR_rt_sigprocmask 135 -+#define __NR_rt_sigpending 136 -+#define __NR_rt_sigtimedwait 137 -+#define __NR_rt_sigqueueinfo 138 -+#define __NR_rt_sigreturn 139 -+#define __NR_setpriority 140 -+#define __NR_getpriority 141 -+#define __NR_reboot 142 -+#define __NR_setregid 143 -+#define __NR_setgid 144 -+#define __NR_setreuid 145 -+#define __NR_setuid 146 -+#define __NR_setresuid 147 -+#define __NR_getresuid 148 -+#define __NR_setresgid 149 -+#define __NR_getresgid 150 -+#define __NR_setfsuid 151 -+#define __NR_setfsgid 152 -+#define __NR_times 153 -+#define __NR_setpgid 154 -+#define __NR_getpgid 155 -+#define __NR_getsid 156 -+#define __NR_setsid 157 -+#define __NR_getgroups 158 -+#define __NR_setgroups 159 -+#define __NR_uname 160 -+#define __NR_sethostname 161 -+#define __NR_setdomainname 162 -+#define __NR_getrlimit 163 -+#define __NR_setrlimit 164 -+#define __NR_getrusage 165 -+#define __NR_umask 166 -+#define __NR_prctl 167 -+#define __NR_getcpu 168 -+#define __NR_gettimeofday 169 -+#define __NR_settimeofday 170 -+#define __NR_adjtimex 171 -+#define __NR_getpid 172 -+#define __NR_getppid 173 -+#define __NR_getuid 174 -+#define __NR_geteuid 175 -+#define __NR_getgid 176 -+#define __NR_getegid 177 -+#define __NR_gettid 178 -+#define __NR_sysinfo 179 -+#define __NR_mq_open 180 -+#define __NR_mq_unlink 181 -+#define __NR_mq_timedsend 182 -+#define __NR_mq_timedreceive 183 -+#define __NR_mq_notify 184 -+#define __NR_mq_getsetattr 185 -+#define __NR_msgget 186 -+#define __NR_msgctl 187 -+#define __NR_msgrcv 188 -+#define __NR_msgsnd 189 -+#define __NR_semget 190 -+#define __NR_semctl 191 -+#define __NR_semtimedop 192 -+#define __NR_semop 193 -+#define __NR_shmget 194 -+#define __NR_shmctl 195 -+#define __NR_shmat 196 -+#define __NR_shmdt 197 -+#define __NR_socket 198 -+#define __NR_socketpair 199 -+#define __NR_bind 200 -+#define __NR_listen 201 -+#define __NR_accept 202 -+#define __NR_connect 203 -+#define __NR_getsockname 204 -+#define __NR_getpeername 205 -+#define __NR_sendto 206 -+#define __NR_recvfrom 207 -+#define __NR_setsockopt 208 -+#define __NR_getsockopt 209 -+#define __NR_shutdown 210 -+#define __NR_sendmsg 211 -+#define __NR_recvmsg 212 -+#define __NR_readahead 213 -+#define __NR_brk 214 -+#define __NR_munmap 215 -+#define __NR_mremap 216 -+#define __NR_add_key 217 -+#define __NR_request_key 218 -+#define __NR_keyctl 219 -+#define __NR_clone 220 -+#define __NR_execve 221 -+#define __NR3264_mmap 222 -+#define __NR3264_fadvise64 223 -+#define __NR_swapon 224 -+#define __NR_swapoff 225 -+#define __NR_mprotect 226 -+#define __NR_msync 227 -+#define __NR_mlock 228 -+#define __NR_munlock 229 -+#define __NR_mlockall 230 -+#define __NR_munlockall 231 -+#define __NR_mincore 232 -+#define __NR_madvise 233 -+#define __NR_remap_file_pages 234 -+#define __NR_mbind 235 -+#define __NR_get_mempolicy 236 -+#define __NR_set_mempolicy 237 -+#define __NR_migrate_pages 238 -+#define __NR_move_pages 239 -+#define __NR_rt_tgsigqueueinfo 240 -+#define __NR_perf_event_open 241 -+#define __NR_accept4 242 -+#define __NR_recvmmsg 243 -+ -+///* -+// * Architectures may provide up to 16 syscalls of their own -+// * starting with this value. -+// */ -+//#define __NR_arch_specific_syscall 244 -+ -+#define __NR_wait4 260 -+#define __NR_prlimit64 261 -+#define __NR_fanotify_init 262 -+#define __NR_fanotify_mark 263 -+#define __NR_name_to_handle_at 264 -+#define __NR_open_by_handle_at 265 -+#define __NR_clock_adjtime 266 -+#define __NR_syncfs 267 -+#define __NR_setns 268 -+#define __NR_sendmmsg 269 -+#define __NR_process_vm_readv 270 -+#define __NR_process_vm_writev 271 -+#define __NR_kcmp 272 -+#define __NR_finit_module 273 -+ -+#undef __NR_syscalls -+#define __NR_syscalls 274 -+ -+///* -+// * All syscalls below here should go away really, -+// * these are provided for both review and as a porting -+// * help for the C library version. -+//* -+// * Last chance: are any of these important enough to -+// * enable by default? -+// */ -+//#ifdef __ARCH_WANT_SYSCALL_NO_AT -+//ZZZZ#define __NR_open 1024 -+//#define __NR_link 1025 -+//__SYSCALL(__NR_link, sys_link) -+//#define __NR_unlink 1026 -+#define __NR_mknod 1027 -+//#define __NR_chmod 1028 -+//__SYSCALL(__NR_chmod, sys_chmod) -+//#define __NR_chown 1029 -+//__SYSCALL(__NR_chown, sys_chown) -+//#define __NR_mkdir 1030 -+//__SYSCALL(__NR_mkdir, sys_mkdir) -+//#define __NR_rmdir 1031 -+//__SYSCALL(__NR_rmdir, sys_rmdir) -+//#define __NR_lchown 1032 -+//__SYSCALL(__NR_lchown, sys_lchown) -+#define __NR_access 1033 -+#define __NR_rename 1034 -+//#define __NR_readlink 1035 -+//#define __NR_symlink 1036 -+//__SYSCALL(__NR_symlink, sys_symlink) -+//#define __NR_utimes 1037 -+//__SYSCALL(__NR_utimes, sys_utimes) -+//#define __NR3264_stat 1038 -+//__SC_3264(__NR3264_stat, sys_stat64, sys_newstat) -+//#define __NR3264_lstat 1039 -+//__SC_3264(__NR3264_lstat, sys_lstat64, sys_newlstat) -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR3264_lstat+1) -+//#endif /* __ARCH_WANT_SYSCALL_NO_AT */ -+// -+//#ifdef __ARCH_WANT_SYSCALL_NO_FLAGS -+#define __NR_pipe 1040 -+#define __NR_dup2 1041 -+//#define __NR_epoll_create 1042 -+//__SYSCALL(__NR_epoll_create, sys_epoll_create) -+//#define __NR_inotify_init 1043 -+//__SYSCALL(__NR_inotify_init, sys_inotify_init) -+//#define __NR_eventfd 1044 -+//__SYSCALL(__NR_eventfd, sys_eventfd) -+//#define __NR_signalfd 1045 -+//__SYSCALL(__NR_signalfd, sys_signalfd) -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR_signalfd+1) -+//#endif /* __ARCH_WANT_SYSCALL_NO_FLAGS */ -+// -+/* #if (__BITS_PER_LONG == 32 || defined(__SYSCALL_COMPAT)) && \ -+ defined(__ARCH_WANT_SYSCALL_OFF_T) -+*/ -+//#define __NR_sendfile 1046 -+//__SYSCALL(__NR_sendfile, sys_sendfile) -+//#define __NR_ftruncate 1047 -+//__SYSCALL(__NR_ftruncate, sys_ftruncate) -+//#define __NR_truncate 1048 -+//__SYSCALL(__NR_truncate, sys_truncate) -+#define __NR_stat 1049 -+//#define __NR_lstat 1050 -+//__SYSCALL(__NR_lstat, sys_newlstat) -+//ZZ#define __NR_fstat 1051 -+//#define __NR_fcntl 1052 -+//#define __NR_fadvise64 1053 -+//#define __ARCH_WANT_SYS_FADVISE64 -+//__SYSCALL(__NR_fadvise64, sys_fadvise64) -+//#define __NR_newfstatat 1054 -+//#define __ARCH_WANT_SYS_NEWFSTATAT -+//__SYSCALL(__NR_newfstatat, sys_newfstatat) -+//#define __NR_fstatfs 1055 -+//__SYSCALL(__NR_fstatfs, sys_fstatfs) -+//#define __NR_statfs 1056 -+//__SYSCALL(__NR_statfs, sys_statfs) -+#define __NR_lseek 1057 -+#define __NR_mmap 1058 -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR_mmap+1) -+//#endif /* 32 bit off_t syscalls */ -+// -+//#ifdef __ARCH_WANT_SYSCALL_DEPRECATED -+//#define __NR_alarm 1059 -+//#define __ARCH_WANT_SYS_ALARM -+//__SYSCALL(__NR_alarm, sys_alarm) -+#define __NR_getpgrp 1060 -+//#define __ARCH_WANT_SYS_GETPGRP -+//__SYSCALL(__NR_getpgrp, sys_getpgrp) -+//#define __NR_pause 1061 -+//#define __ARCH_WANT_SYS_PAUSE -+//__SYSCALL(__NR_pause, sys_pause) -+//#define __NR_time 1062 -+//#define __ARCH_WANT_SYS_TIME -+//#define __ARCH_WANT_COMPAT_SYS_TIME -+//__SYSCALL(__NR_time, sys_time) -+//#define __NR_utime 1063 -+//#define __ARCH_WANT_SYS_UTIME -+//__SYSCALL(__NR_utime, sys_utime) -+// -+//#define __NR_creat 1064 -+//__SYSCALL(__NR_creat, sys_creat) -+#define __NR_getdents 1065 -+//#define __NR_futimesat 1066 -+//__SYSCALL(__NR_futimesat, sys_futimesat) -+//#define __NR_select 1067 -+//#define __ARCH_WANT_SYS_SELECT -+//__SYSCALL(__NR_select, sys_select) -+#define __NR_poll 1068 -+//#define __NR_epoll_wait 1069 -+//__SYSCALL(__NR_epoll_wait, sys_epoll_wait) -+//#define __NR_ustat 1070 -+//__SYSCALL(__NR_ustat, sys_ustat) -+//#define __NR_vfork 1071 -+//__SYSCALL(__NR_vfork, sys_vfork) -+//#define __NR_oldwait4 1072 -+//__SYSCALL(__NR_oldwait4, sys_wait4) -+//#define __NR_recv 1073 -+//__SYSCALL(__NR_recv, sys_recv) -+//#define __NR_send 1074 -+//__SYSCALL(__NR_send, sys_send) -+//#define __NR_bdflush 1075 -+//__SYSCALL(__NR_bdflush, sys_bdflush) -+//#define __NR_umount 1076 -+//__SYSCALL(__NR_umount, sys_oldumount) -+//#define __ARCH_WANT_SYS_OLDUMOUNT -+//#define __NR_uselib 1077 -+//__SYSCALL(__NR_uselib, sys_uselib) -+//#define __NR__sysctl 1078 -+//__SYSCALL(__NR__sysctl, sys_sysctl) -+// -+#define __NR_fork 1079 -+//#ifdef CONFIG_MMU -+//__SYSCALL(__NR_fork, sys_fork) -+//#else -+//__SYSCALL(__NR_fork, sys_ni_syscall) -+//#endif /* CONFIG_MMU */ -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR_fork+1) -+// -+//#endif /* __ARCH_WANT_SYSCALL_DEPRECATED */ -+// -+///* -+// * 32 bit systems traditionally used different -+// * syscalls for off_t and loff_t arguments, while -+// * 64 bit systems only need the off_t version. -+// * For new 32 bit platforms, there is no need to -+// * implement the old 32 bit off_t syscalls, so -+// * they take different names. -+// * Here we map the numbers so that both versions -+// * use the same syscall table layout. -+// */ -+//#if __BITS_PER_LONG == 64 && !defined(__SYSCALL_COMPAT) -+#define __NR_fcntl __NR3264_fcntl -+//#define __NR_statfs __NR3264_statfs -+//#define __NR_fstatfs __NR3264_fstatfs -+//#define __NR_truncate __NR3264_truncate -+//#define __NR_ftruncate __NR3264_ftruncate -+//#define __NR_lseek __NR3264_lseek -+//#define __NR_sendfile __NR3264_sendfile -+//#define __NR_newfstatat __NR3264_fstatat -+#define __NR_fstat __NR3264_fstat -+//#define __NR_mmap __NR3264_mmap -+//#define __NR_fadvise64 __NR3264_fadvise64 -+//#ifdef __NR3264_stat -+//#define __NR_stat __NR3264_stat -+//#define __NR_lstat __NR3264_lstat -+//#endif -+//#else -+//#define __NR_fcntl64 __NR3264_fcntl -+//#define __NR_statfs64 __NR3264_statfs -+//#define __NR_fstatfs64 __NR3264_fstatfs -+//#define __NR_truncate64 __NR3264_truncate -+//#define __NR_ftruncate64 __NR3264_ftruncate -+//#define __NR_llseek __NR3264_lseek -+//#define __NR_sendfile64 __NR3264_sendfile -+//#define __NR_fstatat64 __NR3264_fstatat -+//#define __NR_fstat64 __NR3264_fstat -+//#define __NR_mmap2 __NR3264_mmap -+//#define __NR_fadvise64_64 __NR3264_fadvise64 -+//#ifdef __NR3264_stat -+//#define __NR_stat64 __NR3264_stat -+//#define __NR_lstat64 __NR3264_lstat -+//#endif -+//#endif -+ -+#endif /* __VKI_SCNUMS_ARM64_LINUX_H */ -+ -+/*--------------------------------------------------------------------*/ -+/*--- end vki-scnums-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/vki/vki-x86-linux.h -=================================================================== ---- include/vki/vki-x86-linux.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-x86-linux.h (.../trunk) (revision 13981) -@@ -894,6 +894,13 @@ - }; - - //---------------------------------------------------------------------- -+// From linux-2.6.8.1/include/asm-generic/errno.h -+//---------------------------------------------------------------------- -+ -+#define VKI_ENOSYS 38 /* Function not implemented */ -+#define VKI_EOVERFLOW 75 /* Value too large for defined data type */ -+ -+//---------------------------------------------------------------------- - // And that's it! - //---------------------------------------------------------------------- - -Index: include/vki/vki-xen-domctl.h -=================================================================== ---- include/vki/vki-xen-domctl.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-xen-domctl.h (.../trunk) (revision 13981) -@@ -84,6 +84,8 @@ - #define VKI_XEN_DOMCTL_set_broken_page_p2m 67 - #define VKI_XEN_DOMCTL_setnodeaffinity 68 - #define VKI_XEN_DOMCTL_getnodeaffinity 69 -+#define VKI_XEN_DOMCTL_set_max_evtchn 70 -+#define VKI_XEN_DOMCTL_cacheflush 71 - #define VKI_XEN_DOMCTL_gdbsx_guestmemio 1000 - #define VKI_XEN_DOMCTL_gdbsx_pausevcpu 1001 - #define VKI_XEN_DOMCTL_gdbsx_unpausevcpu 1002 -@@ -163,6 +165,10 @@ - typedef struct vki_xen_domctl_nodeaffinity vki_xen_domctl_nodeaffinity_t; - DEFINE_VKI_XEN_GUEST_HANDLE(vki_xen_domctl_nodeaffinity_t); - -+struct vki_xen_domctl_getpageframeinfo3 { -+ vki_xen_uint64_aligned_t num; /* IN */ -+ VKI_XEN_GUEST_HANDLE_64(vki_xen_pfn_t) array; /* IN/OUT */ -+}; - - struct vki_xen_domctl_vcpuaffinity { - vki_uint32_t vcpu; /* IN */ -@@ -169,6 +175,40 @@ - struct vki_xenctl_bitmap cpumap; /* IN/OUT */ - }; - -+struct vki_xen_domctl_shadow_op_stats { -+ vki_uint32_t fault_count; -+ vki_uint32_t dirty_count; -+}; -+ -+/* vki_xen_domctl_shadow_op.op is an utter mess for compatibily reasons. */ -+ -+struct vki_xen_domctl_shadow_op { -+ vki_uint32_t op; /* IN */ -+ -+#define VKI_XEN_DOMCTL_SHADOW_OP_OFF 0 -+#define VKI_XEN_DOMCTL_SHADOW_OP_ENABLE 32 -+#define VKI_XEN_DOMCTL_SHADOW_OP_CLEAN 11 -+#define VKI_XEN_DOMCTL_SHADOW_OP_PEEK 12 -+#define VKI_XEN_DOMCTL_SHADOW_OP_GET_ALLOCATION 30 -+#define VKI_XEN_DOMCTL_SHADOW_OP_SET_ALLOCATION 31 -+ -+#define VKI_XEN_DOMCTL_SHADOW_OP_ENABLE_TEST 1 -+#define VKI_XEN_DOMCTL_SHADOW_OP_ENABLE_LOGDIRTY 2 -+#define VKI_XEN_DOMCTL_SHADOW_OP_ENABLE_TRANSLATE 3 -+ -+ vki_uint32_t mode; -+ -+#define XEN_DOMCTL_SHADOW_ENABLE_REFCOUNT (1 << 1) -+#define XEN_DOMCTL_SHADOW_ENABLE_LOG_DIRTY (1 << 2) -+#define XEN_DOMCTL_SHADOW_ENABLE_TRANSLATE (1 << 3) -+#define XEN_DOMCTL_SHADOW_ENABLE_EXTERNAL (1 << 4) -+ -+ vki_uint32_t mb; -+ VKI_XEN_GUEST_HANDLE_64(vki_uint8) dirty_bitmap; -+ vki_xen_uint64_aligned_t pages; -+ struct vki_xen_domctl_shadow_op_stats stats; -+}; -+ - struct vki_xen_domctl_max_mem { - /* IN variables. */ - vki_xen_uint64_aligned_t max_memkb; -@@ -225,6 +265,10 @@ - vki_xen_uint64_aligned_t gmfn; /* GMFN to be initialised */ - }; - -+struct vki_xen_domctl_settimeoffset { -+ vki_int32_t time_offset_seconds; -+}; -+ - struct vki_xen_domctl_cpuid { - vki_uint32_t input[2]; - vki_uint32_t eax; -@@ -243,6 +287,13 @@ - typedef struct vki_xen_guest_tsc_info vki_xen_guest_tsc_info_t; - DEFINE_VKI_XEN_GUEST_HANDLE(vki_xen_guest_tsc_info_t); - -+struct vki_xen_domctl_hvmcontext { -+ vki_uint32_t size; /* IN/OUT size of buffer */ -+ VKI_XEN_GUEST_HANDLE_64(vki_uint8) buffer; /* IN/OUT */ -+}; -+typedef struct vki_xen_domctl_hvmcontext vki_xen_domctl_hvmcontext_t; -+DEFINE_VKI_XEN_GUEST_HANDLE(vki_xen_domctl_hvmcontext_t); -+ - struct vki_xen_domctl_tsc_info { - VKI_XEN_GUEST_HANDLE_64(vki_xen_guest_tsc_info_t) out_info; /* OUT */ - vki_xen_guest_tsc_info_t info; /* IN */ -@@ -259,6 +310,15 @@ - vki_uint32_t size; - }; - -+struct vki_xen_domctl_set_max_evtchn { -+ vki_uint32_t max_port; -+}; -+ -+struct vki_xen_domctl_cacheflush { -+ /* IN: page range to flush. */ -+ vki_xen_pfn_t start_pfn, nr_pfns; -+}; -+ - struct vki_xen_domctl { - vki_uint32_t cmd; - vki_uint32_t interface_version; /* XEN_DOMCTL_INTERFACE_VERSION */ -@@ -271,10 +331,10 @@ - //struct vki_xen_domctl_getmemlist getmemlist; - //struct vki_xen_domctl_getpageframeinfo getpageframeinfo; - //struct vki_xen_domctl_getpageframeinfo2 getpageframeinfo2; -- //struct vki_xen_domctl_getpageframeinfo3 getpageframeinfo3; -+ struct vki_xen_domctl_getpageframeinfo3 getpageframeinfo3; - struct vki_xen_domctl_nodeaffinity nodeaffinity; - struct vki_xen_domctl_vcpuaffinity vcpuaffinity; -- //struct vki_xen_domctl_shadow_op shadow_op; -+ struct vki_xen_domctl_shadow_op shadow_op; - struct vki_xen_domctl_max_mem max_mem; - struct vki_xen_domctl_vcpucontext vcpucontext; - struct vki_xen_domctl_getvcpuinfo getvcpuinfo; -@@ -287,11 +347,11 @@ - //struct vki_xen_domctl_ioport_permission ioport_permission; - struct vki_xen_domctl_hypercall_init hypercall_init; - //struct vki_xen_domctl_arch_setup arch_setup; -- //struct vki_xen_domctl_settimeoffset settimeoffset; -+ struct vki_xen_domctl_settimeoffset settimeoffset; - //struct vki_xen_domctl_disable_migrate disable_migrate; - struct vki_xen_domctl_tsc_info tsc_info; - //struct vki_xen_domctl_real_mode_area real_mode_area; -- //struct vki_xen_domctl_hvmcontext hvmcontext; -+ struct vki_xen_domctl_hvmcontext hvmcontext; - //struct vki_xen_domctl_hvmcontext_partial hvmcontext_partial; - struct vki_xen_domctl_address_size address_size; - //struct vki_xen_domctl_sendtrigger sendtrigger; -@@ -314,8 +374,10 @@ - //struct vki_xen_domctl_set_access_required access_required; - //struct vki_xen_domctl_audit_p2m audit_p2m; - //struct vki_xen_domctl_set_virq_handler set_virq_handler; -+ struct vki_xen_domctl_set_max_evtchn set_max_evtchn; - //struct vki_xen_domctl_gdbsx_memio gdbsx_guest_memio; - //struct vki_xen_domctl_set_broken_page_p2m set_broken_page_p2m; -+ struct vki_xen_domctl_cacheflush cacheflush; - //struct vki_xen_domctl_gdbsx_pauseunp_vcpu gdbsx_pauseunp_vcpu; - //struct vki_xen_domctl_gdbsx_domstatus gdbsx_domstatus; - vki_uint8_t pad[128]; -Index: include/vki/vki-xen-hvm.h -=================================================================== ---- include/vki/vki-xen-hvm.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-xen-hvm.h (.../trunk) (revision 13981) -@@ -10,6 +10,31 @@ - vki_uint64_t value; /* IN/OUT */ - }; - -+#define VKI_XEN_HVMOP_set_isa_irq_level 3 -+struct vki_xen_hvm_set_isa_irq_level { -+ vki_xen_domid_t domid; -+ vki_uint8_t isa_irq; -+ vki_uint8_t level; -+}; -+typedef struct vki_xen_hvm_set_isa_irq_level vki_xen_hvm_set_isa_irq_level_t; -+ -+#define VKI_XEN_HVMOP_set_pci_link_route 4 -+struct vki_xen_hvm_set_pci_link_route { -+ vki_xen_domid_t domid; -+ vki_uint8_t link; -+ vki_uint8_t isa_irq; -+}; -+typedef struct vki_xen_hvm_set_pci_link_route vki_xen_hvm_set_pci_link_route_t; -+ -+#define VKI_XEN_HVMOP_set_mem_type 8 -+struct vki_xen_hvm_set_mem_type { -+ vki_xen_domid_t domid; -+ vki_uint16_t hvmmem_type; -+ vki_uint32_t nr; -+ vki_xen_uint64_aligned_t first_pfn; -+}; -+typedef struct vki_xen_hvm_set_mem_type vki_xen_hvm_set_mem_type_t; -+ - #endif // __VKI_XEN_HVM_H - - /*--------------------------------------------------------------------*/ -Index: include/vki/vki-xen-memory.h -=================================================================== ---- include/vki/vki-xen-memory.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-xen-memory.h (.../trunk) (revision 13981) -@@ -40,6 +40,32 @@ - vki_xen_domid_t domid; - }; - -+struct vki_xen_machphys_mfn_list { -+ unsigned int max_extents; /* IN */ -+ VKI_XEN_GUEST_HANDLE(vki_xen_pfn_t) extent_start; /* OUT */ -+ unsigned int nr_extents; /* OUT */ -+}; -+ -+struct vki_xen_add_to_physmap { -+ vki_xen_domid_t domid; -+ vki_uint16_t size; -+ -+#define VKI_XENMAPSPACE_shared_info 0 -+#define VKI_XENMAPSPACE_grant_table 1 -+#define VKI_XENMAPSPACE_gmfn 2 -+#define VKI_XENMAPSPACE_gmfn_range 3 -+#define VKI_XENMAPSPACE_gmfn_foreign 4 -+ -+ unsigned int space; -+ vki_xen_ulong_t idx; -+ vki_xen_pfn_t gpfn; -+}; -+ -+struct vki_xen_remove_from_physmap { -+ vki_xen_domid_t domid; -+ vki_xen_pfn_t gpfn; -+}; -+ - #endif // __VKI_XEN_MEMORY_H - - /*--------------------------------------------------------------------*/ -Index: include/vki/vki-xen-sysctl.h -=================================================================== ---- include/vki/vki-xen-sysctl.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-xen-sysctl.h (.../trunk) (revision 13981) -@@ -38,6 +38,27 @@ - #define VKI_XEN_SYSCTL_scheduler_op 19 - #define VKI_XEN_SYSCTL_coverage_op 20 - -+struct vki_xen_sysctl_readconsole { -+ /* IN */ -+ vki_uint8_t clear; -+ vki_uint8_t incremental; -+ -+ vki_uint8_t pad0, pad1; -+ -+ /* -+ * IN: Start index for consumption if @incremental. -+ * OUT: End index after consuming from the console. -+ */ -+ vki_uint32_t index; -+ VKI_XEN_GUEST_HANDLE_64(char) buffer; /* IN */ -+ -+ /* -+ * IN: size of buffer. -+ * OUT: bytes written into buffer. -+ */ -+ vki_uint32_t count; -+}; -+ - struct vki_xen_sysctl_getdomaininfolist_00000008 { - /* IN variables. */ - vki_xen_domid_t first_domain; -@@ -56,6 +77,15 @@ - vki_uint32_t num_domains; - }; - -+struct vki_xen_sysctl_getdomaininfolist_0000000a { -+ /* IN variables. */ -+ vki_xen_domid_t first_domain; -+ vki_uint32_t max_domains; -+ VKI_XEN_GUEST_HANDLE_64(vki_xen_domctl_getdomaininfo_00000009_t) buffer; -+ /* OUT variables. */ -+ vki_uint32_t num_domains; -+}; -+ - #define VKI_XEN_SYSCTL_CPUPOOL_OP_CREATE 1 /* C */ - #define VKI_XEN_SYSCTL_CPUPOOL_OP_DESTROY 2 /* D */ - #define VKI_XEN_SYSCTL_CPUPOOL_OP_INFO 3 /* I */ -@@ -74,6 +104,12 @@ - struct vki_xenctl_bitmap cpumap; /* OUT: IF */ - }; - -+struct vki_xen_sysctl_debug_keys { -+ /* IN variables. */ -+ VKI_XEN_GUEST_HANDLE_64(char) keys; -+ vki_uint32_t nr_keys; -+}; -+ - struct vki_xen_sysctl_topologyinfo { - vki_uint32_t max_cpu_index; - VKI_XEN_GUEST_HANDLE_64(vki_uint32) cpu_to_core; -@@ -129,7 +165,7 @@ - vki_uint32_t cmd; - vki_uint32_t interface_version; /* XEN_SYSCTL_INTERFACE_VERSION */ - union { -- //struct vki_xen_sysctl_readconsole readconsole; -+ struct vki_xen_sysctl_readconsole readconsole; - //struct vki_xen_sysctl_tbuf_op tbuf_op; - struct vki_xen_sysctl_physinfo_00000008 physinfo_00000008; - struct vki_xen_sysctl_physinfo_0000000a physinfo_0000000a; -@@ -139,7 +175,8 @@ - //struct vki_xen_sysctl_perfc_op perfc_op; - struct vki_xen_sysctl_getdomaininfolist_00000008 getdomaininfolist_00000008; - struct vki_xen_sysctl_getdomaininfolist_00000009 getdomaininfolist_00000009; -- //struct vki_xen_sysctl_debug_keys debug_keys; -+ struct vki_xen_sysctl_getdomaininfolist_0000000a getdomaininfolist_0000000a; -+ struct vki_xen_sysctl_debug_keys debug_keys; - //struct vki_xen_sysctl_getcpuinfo getcpuinfo; - //struct vki_xen_sysctl_availheap availheap; - //struct vki_xen_sysctl_get_pmstat get_pmstat; -Index: include/vki/vki-xen-tmem.h -=================================================================== ---- include/vki/vki-xen-tmem.h (.../tags/VALGRIND_3_9_0) (revision 0) -+++ include/vki/vki-xen-tmem.h (.../trunk) (revision 13981) -@@ -0,0 +1,75 @@ -+#ifndef __VKI_XEN_TMEM_H -+#define __VKI_XEN_TMEM_H -+ -+typedef VKI_XEN_GUEST_HANDLE(char) vki_xen_tmem_cli_va_t; -+ -+ -+/* version of ABI */ -+#define VKI_XEN_TMEM_spec_version 1 -+ -+/* Commands to HYPERVISOR_tmem_op() */ -+#define VKI_XEN_TMEM_control 0 -+#define VKI_XEN_TMEM_new_pool 1 -+#define VKI_XEN_TMEM_destroy_pool 2 -+#define VKI_XEN_TMEM_new_page 3 -+#define VKI_XEN_TMEM_put_page 4 -+#define VKI_XEN_TMEM_get_page 5 -+#define VKI_XEN_TMEM_flush_page 6 -+#define VKI_XEN_TMEM_flush_object 7 -+#define VKI_XEN_TMEM_read 8 -+#define VKI_XEN_TMEM_write 9 -+#define VKI_XEN_TMEM_xchg 10 -+/* Privileged commands to HYPERVISOR_tmem_op() */ -+#define VKI_XEN_tmem_auth 101 -+#define VKI_XEN_tmem_restore_new 102 -+ -+/* for cmd = TMEM_CONTROL */ -+struct vki_xen_tmem_ctrl { -+ vki_uint32_t subop; -+ -+/* Subops for HYPERVISOR_tmem_op(TMEM_CONTROL) */ -+#define VKI_XEN_TMEMC_thaw 0 -+#define VKI_XEN_TMEMC_freeze 1 -+#define VKI_XEN_TMEMC_flush 2 -+#define VKI_XEN_TMEMC_destroy 3 -+#define VKI_XEN_TMEMC_list 4 -+#define VKI_XEN_TMEMC_set_weight 5 -+#define VKI_XEN_TMEMC_set_cap 6 -+#define VKI_XEN_TMEMC_set_compress 7 -+#define VKI_XEN_TMEMC_query_freeable_mb 8 -+#define VKI_XEN_TMEMC_save_begin 10 -+#define VKI_XEN_TMEMC_save_get_version 11 -+#define VKI_XEN_TMEMC_save_get_maxpools 12 -+#define VKI_XEN_TMEMC_save_get_client_weight 13 -+#define VKI_XEN_TMEMC_save_get_client_cap 14 -+#define VKI_XEN_TMEMC_save_get_client_flags 15 -+#define VKI_XEN_TMEMC_save_get_pool_flags 16 -+#define VKI_XEN_TMEMC_save_get_pool_npages 17 -+#define VKI_XEN_TMEMC_save_get_pool_uuid 18 -+#define VKI_XEN_TMEMC_save_get_next_page 19 -+#define VKI_XEN_TMEMC_save_get_next_inv 20 -+#define VKI_XEN_TMEMC_save_end 21 -+#define VKI_XEN_TMEMC_restore_begin 30 -+#define VKI_XEN_TMEMC_restore_put_page 32 -+#define VKI_XEN_TMEMC_restore_flush_page 33 -+ -+ vki_uint32_t cli_id; -+ vki_uint32_t arg1; -+ vki_uint32_t arg2; -+ vki_uint64_t oid[3]; -+ vki_xen_tmem_cli_va_t buf; -+}; -+ -+struct vki_xen_tmem_op { -+ vki_uint32_t cmd; -+ vki_int32_t pool_id; -+ union { -+ struct vki_xen_tmem_ctrl ctrl; -+ } u; -+}; -+ -+#endif // __VKI_XEN_TMEM_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/vki/vki-xen.h -=================================================================== ---- include/vki/vki-xen.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ include/vki/vki-xen.h (.../trunk) (revision 13981) -@@ -58,6 +58,7 @@ - #endif - - DEFINE_VKI_XEN_GUEST_HANDLE(void); -+DEFINE_VKI_XEN_GUEST_HANDLE(char); - DEFINE_VKI_XEN_GUEST_HANDLE(vki_xen_pfn_t); - - __DEFINE_VKI_XEN_GUEST_HANDLE(vki_ulong, unsigned long); -@@ -84,6 +85,7 @@ - #include - #include - #include -+#include - - #endif // __VKI_XEN_H - -Index: massif/ms_main.c -=================================================================== ---- massif/ms_main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ massif/ms_main.c (.../trunk) (revision 13981) -@@ -226,12 +226,6 @@ - VG_(dmsg)("Massif: " format, ##args); \ - } - --// Used for printing stats when clo_stats == True. --#define STATS(format, args...) \ -- if (VG_(clo_stats)) { \ -- VG_(dmsg)("Massif: " format, ##args); \ -- } -- - //------------------------------------------------------------// - //--- Statistics ---// - //------------------------------------------------------------// -@@ -2395,7 +2389,7 @@ - static Bool handle_gdb_monitor_command (ThreadId tid, HChar *req) - { - HChar* wcmd; -- HChar s[VG_(strlen(req))]; /* copy for strtok_r */ -+ HChar s[VG_(strlen(req)) + 1]; /* copy for strtok_r */ - HChar *ssaveptr; - - VG_(strcpy) (s, req); -@@ -2428,17 +2422,11 @@ - } - } - --//------------------------------------------------------------// --//--- Finalisation ---// --//------------------------------------------------------------// -- --static void ms_fini(Int exit_status) -+static void ms_print_stats (void) - { -- // Output. -- write_snapshots_array_to_file(); -+#define STATS(format, args...) \ -+ VG_(dmsg)("Massif: " format, ##args) - -- // Stats -- tl_assert(n_xpts > 0); // always have alloc_xpt - STATS("heap allocs: %u\n", n_heap_allocs); - STATS("heap reallocs: %u\n", n_heap_reallocs); - STATS("heap frees: %u\n", n_heap_frees); -@@ -2461,9 +2449,26 @@ - STATS("peak snapshots: %u\n", n_peak_snapshots); - STATS("cullings: %u\n", n_cullings); - STATS("XCon redos: %u\n", n_XCon_redos); -+#undef STATS - } - -+//------------------------------------------------------------// -+//--- Finalisation ---// -+//------------------------------------------------------------// - -+static void ms_fini(Int exit_status) -+{ -+ // Output. -+ write_snapshots_array_to_file(); -+ -+ // Stats -+ tl_assert(n_xpts > 0); // always have alloc_xpt -+ -+ if (VG_(clo_stats)) -+ ms_print_stats(); -+} -+ -+ - //------------------------------------------------------------// - //--- Initialisation ---// - //------------------------------------------------------------// -@@ -2594,6 +2599,7 @@ - VG_(needs_client_requests) (ms_handle_client_request); - VG_(needs_sanity_checks) (ms_cheap_sanity_check, - ms_expensive_sanity_check); -+ VG_(needs_print_stats) (ms_print_stats); - VG_(needs_malloc_replacement) (ms_malloc, - ms___builtin_new, - ms___builtin_vec_new, -Index: memcheck/docs/mc-manual.xml -=================================================================== ---- memcheck/docs/mc-manual.xml (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/docs/mc-manual.xml (.../trunk) (revision 13981) -@@ -610,14 +610,14 @@ - in one of the following ways: - - -- a comma separated list of one or more of -- . -+ a comma separated list of one or more of -+ . - - -- to specify the complete set (all leak kinds). -+ to specify the complete set (all leak kinds). - - -- for the empty set. -+ for the empty set. - - - -@@ -718,22 +718,21 @@ - - - Specifies the leak kinds to show in a full leak search, in -- one of the following ways: -+ one of the following ways: - -- -- a comma separated list of one or more of -- . -- -- -- to specify the complete set (all leak kinds). -+ -+ a comma separated list of one or more of -+ . -+ -+ -+ to specify the complete set (all leak kinds). - It is equivalent to -- . -- -- -- for the empty set. -- -- -- -+ . -+ -+ -+ for the empty set. -+ -+ - - - -@@ -757,32 +756,30 @@ - - - Specifies the set of leak check heuristics to be used -- during -- leak searches. The heuristics control which interior pointers -+ during leak searches. The heuristics control which interior pointers - to a block cause it to be considered as reachable. -- The heuristic set is specified in one of the following ways: -+ The heuristic set is specified in one of the following ways: - -- -- a comma separated list of one or more of -- . -- -+ -+ a comma separated list of one or more of -+ . -+ - -- to activate the complete set of -+ to activate the complete set of - heuristics. - It is equivalent to -- . -- -- -- for the empty set. -- -- -- -+ . -+ -+ -+ for the empty set. -+ -+ -+ - -- Note that these heuristics are dependent on the layout of the objects -+ Note that these heuristics are dependent on the layout of the objects - produced by the C++ compiler. They have been tested with some gcc versions - (e.g. 4.4 and 4.7). They might not work properly with other C++ compilers. -- -- -+ - - - -@@ -795,24 +792,30 @@ - - - These options provide an alternative way to specify the leak kinds to show: -- -- -+ -+ -+ -+ - is equivalent to - . -- -- -+ -+ -+ -+ - is equivalent to - . -- -- -+ -+ -+ -+ - is equivalent to - . -- Note that has no effect -- if is specified. -- -- -- -+ -+ -+ - -+ Note that has no effect -+ if is specified. - - - -Index: memcheck/mc_errors.c -=================================================================== ---- memcheck/mc_errors.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/mc_errors.c (.../trunk) (revision 13981) -@@ -44,6 +44,7 @@ - #include "pub_tool_threadstate.h" - #include "pub_tool_debuginfo.h" // VG_(get_dataname_and_offset) - #include "pub_tool_xarray.h" -+#include "pub_tool_addrinfo.h" - - #include "mc_include.h" - -@@ -56,81 +57,6 @@ - Bool MC_(any_value_errors) = False; - - --// Different kinds of blocks. --typedef enum { -- Block_Mallocd = 111, -- Block_Freed, -- Block_MempoolChunk, -- Block_UserG --} BlockKind; -- --/* ------------------ Addresses -------------------- */ -- --/* The classification of a faulting address. */ --typedef -- enum { -- Addr_Undescribed, // as-yet unclassified -- Addr_Unknown, // classification yielded nothing useful -- Addr_Block, // in malloc'd/free'd block -- Addr_Stack, // on a thread's stack -- Addr_DataSym, // in a global data sym -- Addr_Variable, // variable described by the debug info -- Addr_SectKind // last-ditch classification attempt -- } -- AddrTag; -- --typedef -- struct _AddrInfo -- AddrInfo; -- --struct _AddrInfo { -- AddrTag tag; -- union { -- // As-yet unclassified. -- struct { } Undescribed; -- -- // On a stack. -- struct { -- ThreadId tid; // Which thread's stack? -- } Stack; -- -- // This covers heap blocks (normal and from mempools) and user-defined -- // blocks. -- struct { -- BlockKind block_kind; -- const HChar* block_desc; // "block", "mempool" or user-defined -- SizeT block_szB; -- PtrdiffT rwoffset; -- ExeContext* allocated_at; // might be null_ExeContext. -- ExeContext* freed_at; // might be null_ExeContext. -- } Block; -- -- // In a global .data symbol. This holds the first 127 chars of -- // the variable's name (zero terminated), plus a (memory) offset. -- struct { -- HChar name[128]; -- PtrdiffT offset; -- } DataSym; -- -- // Is described by Dwarf debug info. XArray*s of HChar. -- struct { -- XArray* /* of HChar */ descr1; -- XArray* /* of HChar */ descr2; -- } Variable; -- -- // Could only narrow it down to be the PLT/GOT/etc of a given -- // object. Better than nothing, perhaps. -- struct { -- HChar objname[128]; -- VgSectKind kind; -- } SectKind; -- -- // Classification yielded nothing useful. -- struct { } Unknown; -- -- } Addr; --}; -- - /* ------------------ Errors ----------------------- */ - - /* What kind of error it is. */ -@@ -286,128 +212,8 @@ - emit_WRK(format, vargs); - va_end(vargs); - } --static void emiN ( const HChar* format, ... ) /* NO FORMAT CHECK */ --{ -- va_list vargs; -- va_start(vargs, format); -- emit_WRK(format, vargs); -- va_end(vargs); --} - - --static void mc_pp_AddrInfo ( Addr a, AddrInfo* ai, Bool maybe_gcc ) --{ -- const HChar* xpre = VG_(clo_xml) ? " " : " "; -- const HChar* xpost = VG_(clo_xml) ? "" : ""; -- -- switch (ai->tag) { -- case Addr_Unknown: -- if (maybe_gcc) { -- emit( "%sAddress 0x%llx is just below the stack ptr. " -- "To suppress, use: --workaround-gcc296-bugs=yes%s\n", -- xpre, (ULong)a, xpost ); -- } else { -- emit( "%sAddress 0x%llx " -- "is not stack'd, malloc'd or (recently) free'd%s\n", -- xpre, (ULong)a, xpost ); -- } -- break; -- -- case Addr_Stack: -- emit( "%sAddress 0x%llx is on thread %d's stack%s\n", -- xpre, (ULong)a, ai->Addr.Stack.tid, xpost ); -- break; -- -- case Addr_Block: { -- SizeT block_szB = ai->Addr.Block.block_szB; -- PtrdiffT rwoffset = ai->Addr.Block.rwoffset; -- SizeT delta; -- const HChar* relative; -- -- if (rwoffset < 0) { -- delta = (SizeT)(-rwoffset); -- relative = "before"; -- } else if (rwoffset >= block_szB) { -- delta = rwoffset - block_szB; -- relative = "after"; -- } else { -- delta = rwoffset; -- relative = "inside"; -- } -- emit( -- "%sAddress 0x%lx is %'lu bytes %s a %s of size %'lu %s%s\n", -- xpre, -- a, delta, relative, ai->Addr.Block.block_desc, -- block_szB, -- ai->Addr.Block.block_kind==Block_Mallocd ? "alloc'd" -- : ai->Addr.Block.block_kind==Block_Freed ? "free'd" -- : "client-defined", -- xpost -- ); -- if (ai->Addr.Block.block_kind==Block_Mallocd) { -- VG_(pp_ExeContext)(ai->Addr.Block.allocated_at); -- tl_assert (ai->Addr.Block.freed_at == VG_(null_ExeContext)()); -- } -- else if (ai->Addr.Block.block_kind==Block_Freed) { -- VG_(pp_ExeContext)(ai->Addr.Block.freed_at); -- if (ai->Addr.Block.allocated_at != VG_(null_ExeContext)()) { -- emit( -- "%s block was alloc'd at%s\n", -- xpre, -- xpost -- ); -- VG_(pp_ExeContext)(ai->Addr.Block.allocated_at); -- } -- } -- else { -- // client-defined -- VG_(pp_ExeContext)(ai->Addr.Block.allocated_at); -- tl_assert (ai->Addr.Block.freed_at == VG_(null_ExeContext)()); -- /* Nb: cannot have a freed_at, as a freed client-defined block -- has a Block_Freed block_kind. */ -- } -- -- break; -- } -- -- case Addr_DataSym: -- emiN( "%sAddress 0x%llx is %llu bytes " -- "inside data symbol \"%pS\"%s\n", -- xpre, -- (ULong)a, -- (ULong)ai->Addr.DataSym.offset, -- ai->Addr.DataSym.name, -- xpost ); -- break; -- -- case Addr_Variable: -- /* Note, no need for XML tags here, because descr1/2 will -- already have or s on them, in XML -- mode. */ -- if (ai->Addr.Variable.descr1) -- emit( "%s%s\n", -- VG_(clo_xml) ? " " : " ", -- (HChar*)VG_(indexXA)(ai->Addr.Variable.descr1, 0) ); -- if (ai->Addr.Variable.descr2) -- emit( "%s%s\n", -- VG_(clo_xml) ? " " : " ", -- (HChar*)VG_(indexXA)(ai->Addr.Variable.descr2, 0) ); -- break; -- -- case Addr_SectKind: -- emiN( "%sAddress 0x%llx is in the %pS segment of %pS%s\n", -- xpre, -- (ULong)a, -- VG_(pp_SectKind)(ai->Addr.SectKind.kind), -- ai->Addr.SectKind.objname, -- xpost ); -- break; -- -- default: -- VG_(tool_panic)("mc_pp_AddrInfo"); -- } --} -- - static const HChar* str_leak_lossmode ( Reachedness lossmode ) - { - const HChar *loss = "?"; -@@ -434,50 +240,8 @@ - - Bool MC_(parse_leak_kinds) ( const HChar* str0, UInt* lks ) - { -- HChar tok_str0[VG_(strlen)(str0)+1]; -- HChar* saveptr; -- HChar* token; -- -- Bool seen_all_kw = False; -- Bool seen_none_kw = False; -- -- VG_(strcpy) (tok_str0, str0); -- *lks = 0; -- -- for (token = VG_(strtok_r)(tok_str0, ",", &saveptr); -- token; -- token = VG_(strtok_r)(NULL, ",", &saveptr)) { -- if (0 == VG_(strcmp)(token, "reachable")) -- *lks |= R2S(Reachable); -- else if (0 == VG_(strcmp)(token, "possible")) -- *lks |= R2S(Possible); -- else if (0 == VG_(strcmp)(token, "indirect")) -- *lks |= R2S(IndirectLeak); -- else if (0 == VG_(strcmp)(token, "definite")) -- *lks |= R2S(Unreached); -- else if (0 == VG_(strcmp)(token, "all")) -- seen_all_kw = True; -- else if (0 == VG_(strcmp)(token, "none")) -- seen_none_kw = True; -- else -- return False; -- } -- -- if (seen_all_kw) { -- if (seen_none_kw || *lks) -- return False; // mixing all with either none or a specific value. -- *lks = RallS; -- } else if (seen_none_kw) { -- if (seen_all_kw || *lks) -- return False; // mixing none with either all or a specific value. -- *lks = 0; -- } else { -- // seen neither all or none, we must see at least one value -- if (*lks == 0) -- return False; -- } -- -- return True; -+ return VG_(parse_enum_set)("reachable,possible,indirect,definite", -+ str0, lks); - } - - static const HChar* pp_Reachedness_for_leak_kinds(Reachedness r) -@@ -631,7 +395,7 @@ - // the following code is untested. Bad. - if (xml) { - emit( " CoreMemError\n" ); -- emiN( " %pS contains unaddressable byte(s)\n", -+ emit( " %pS contains unaddressable byte(s)\n", - VG_(get_error_string)(err)); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); - } else { -@@ -689,7 +453,7 @@ - MC_(any_value_errors) = True; - if (xml) { - emit( " SyscallParam\n" ); -- emiN( " Syscall param %pS contains " -+ emit( " Syscall param %pS contains " - "uninitialised byte(s)\n", - VG_(get_error_string)(err) ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -@@ -711,13 +475,13 @@ - MC_(any_value_errors) = True; - if (xml) { - emit( " SyscallParam\n" ); -- emiN( " Syscall param %pS points to %s byte(s)\n", -+ emit( " Syscall param %pS points to %s byte(s)\n", - VG_(get_error_string)(err), - extra->Err.MemParam.isAddrErr - ? "unaddressable" : "uninitialised" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo(VG_(get_error_address)(err), -- &extra->Err.MemParam.ai, False); -+ VG_(pp_addrinfo_mc)(VG_(get_error_address)(err), -+ &extra->Err.MemParam.ai, False); - if (extra->Err.MemParam.origin_ec - && !extra->Err.MemParam.isAddrErr) - mc_pp_origin( extra->Err.MemParam.origin_ec, -@@ -728,8 +492,8 @@ - extra->Err.MemParam.isAddrErr - ? "unaddressable" : "uninitialised" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo(VG_(get_error_address)(err), -- &extra->Err.MemParam.ai, False); -+ VG_(pp_addrinfo_mc)(VG_(get_error_address)(err), -+ &extra->Err.MemParam.ai, False); - if (extra->Err.MemParam.origin_ec - && !extra->Err.MemParam.isAddrErr) - mc_pp_origin( extra->Err.MemParam.origin_ec, -@@ -747,8 +511,8 @@ - extra->Err.User.isAddrErr - ? "Unaddressable" : "Uninitialised" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo(VG_(get_error_address)(err), &extra->Err.User.ai, -- False); -+ VG_(pp_addrinfo_mc)(VG_(get_error_address)(err), &extra->Err.User.ai, -+ False); - if (extra->Err.User.origin_ec && !extra->Err.User.isAddrErr) - mc_pp_origin( extra->Err.User.origin_ec, - extra->Err.User.otag & 3 ); -@@ -757,8 +521,8 @@ - extra->Err.User.isAddrErr - ? "Unaddressable" : "Uninitialised" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo(VG_(get_error_address)(err), &extra->Err.User.ai, -- False); -+ VG_(pp_addrinfo_mc)(VG_(get_error_address)(err), &extra->Err.User.ai, -+ False); - if (extra->Err.User.origin_ec && !extra->Err.User.isAddrErr) - mc_pp_origin( extra->Err.User.origin_ec, - extra->Err.User.otag & 3 ); -@@ -771,13 +535,13 @@ - emit( " Invalid free() / delete / delete[]" - " / realloc()\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo( VG_(get_error_address)(err), -- &extra->Err.Free.ai, False ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), -+ &extra->Err.Free.ai, False ); - } else { - emit( "Invalid free() / delete / delete[] / realloc()\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo( VG_(get_error_address)(err), -- &extra->Err.Free.ai, False ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), -+ &extra->Err.Free.ai, False ); - } - break; - -@@ -786,13 +550,13 @@ - emit( " MismatchedFree\n" ); - emit( " Mismatched free() / delete / delete []\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo(VG_(get_error_address)(err), -- &extra->Err.FreeMismatch.ai, False); -+ VG_(pp_addrinfo_mc)(VG_(get_error_address)(err), -+ &extra->Err.FreeMismatch.ai, False); - } else { - emit( "Mismatched free() / delete / delete []\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo(VG_(get_error_address)(err), -- &extra->Err.FreeMismatch.ai, False); -+ VG_(pp_addrinfo_mc)(VG_(get_error_address)(err), -+ &extra->Err.FreeMismatch.ai, False); - } - break; - -@@ -804,9 +568,9 @@ - extra->Err.Addr.isWrite ? "write" : "read", - extra->Err.Addr.szB ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo( VG_(get_error_address)(err), -- &extra->Err.Addr.ai, -- extra->Err.Addr.maybe_gcc ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), -+ &extra->Err.Addr.ai, -+ extra->Err.Addr.maybe_gcc ); - } else { - emit( "Invalid %s of size %ld\n", - extra->Err.Addr.isWrite ? "write" : "read", -@@ -813,9 +577,9 @@ - extra->Err.Addr.szB ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); - -- mc_pp_AddrInfo( VG_(get_error_address)(err), -- &extra->Err.Addr.ai, -- extra->Err.Addr.maybe_gcc ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), -+ &extra->Err.Addr.ai, -+ extra->Err.Addr.maybe_gcc ); - } - break; - -@@ -825,13 +589,13 @@ - emit( " Jump to the invalid address stated " - "on the next line\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo( VG_(get_error_address)(err), &extra->Err.Jump.ai, -- False ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), &extra->Err.Jump.ai, -+ False ); - } else { - emit( "Jump to the invalid address stated on the next line\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo( VG_(get_error_address)(err), &extra->Err.Jump.ai, -- False ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), &extra->Err.Jump.ai, -+ False ); - } - break; - -@@ -839,7 +603,7 @@ - if (xml) { - emit( " Overlap\n" ); - if (extra->Err.Overlap.szB == 0) { -- emiN( " Source and destination overlap " -+ emit( " Source and destination overlap " - "in %pS(%#lx, %#lx)\n\n", - VG_(get_error_string)(err), - extra->Err.Overlap.dst, extra->Err.Overlap.src ); -@@ -853,7 +617,7 @@ - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); - } else { - if (extra->Err.Overlap.szB == 0) { -- emiN( "Source and destination overlap in %pS(%#lx, %#lx)\n", -+ emit( "Source and destination overlap in %pS(%#lx, %#lx)\n", - VG_(get_error_string)(err), - extra->Err.Overlap.dst, extra->Err.Overlap.src ); - } else { -@@ -873,13 +637,13 @@ - emit( " InvalidMemPool\n" ); - emit( " Illegal memory pool address\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo( VG_(get_error_address)(err), -- &extra->Err.IllegalMempool.ai, False ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), -+ &extra->Err.IllegalMempool.ai, False ); - } else { - emit( "Illegal memory pool address\n" ); - VG_(pp_ExeContext)( VG_(get_error_where)(err) ); -- mc_pp_AddrInfo( VG_(get_error_address)(err), -- &extra->Err.IllegalMempool.ai, False ); -+ VG_(pp_addrinfo_mc)( VG_(get_error_address)(err), -+ &extra->Err.IllegalMempool.ai, False ); - } - break; - -@@ -1183,9 +947,6 @@ - static void describe_addr ( Addr a, /*OUT*/AddrInfo* ai ) - { - MC_Chunk* mc; -- ThreadId tid; -- Addr stack_min, stack_max; -- VgSectKind sect; - - tl_assert(Addr_Undescribed == ai->tag); - -@@ -1234,78 +995,9 @@ - ai->Addr.Block.freed_at = MC_(freed_at)(mc); - return; - } -- /* -- Perhaps the variable type/location data describes it? -- */ -- ai->Addr.Variable.descr1 -- = VG_(newXA)( VG_(malloc), "mc.da.descr1", -- VG_(free), sizeof(HChar) ); -- ai->Addr.Variable.descr2 -- = VG_(newXA)( VG_(malloc), "mc.da.descr2", -- VG_(free), sizeof(HChar) ); - -- (void) VG_(get_data_description)( ai->Addr.Variable.descr1, -- ai->Addr.Variable.descr2, a ); -- /* If there's nothing in descr1/2, free them. Why is it safe to to -- VG_(indexXA) at zero here? Because VG_(get_data_description) -- guarantees to zero terminate descr1/2 regardless of the outcome -- of the call. So there's always at least one element in each XA -- after the call. -- */ -- if (0 == VG_(strlen)( VG_(indexXA)( ai->Addr.Variable.descr1, 0 ))) { -- VG_(deleteXA)( ai->Addr.Variable.descr1 ); -- ai->Addr.Variable.descr1 = NULL; -- } -- if (0 == VG_(strlen)( VG_(indexXA)( ai->Addr.Variable.descr2, 0 ))) { -- VG_(deleteXA)( ai->Addr.Variable.descr2 ); -- ai->Addr.Variable.descr2 = NULL; -- } -- /* Assume (assert) that VG_(get_data_description) fills in descr1 -- before it fills in descr2 */ -- if (ai->Addr.Variable.descr1 == NULL) -- tl_assert(ai->Addr.Variable.descr2 == NULL); -- /* So did we get lucky? */ -- if (ai->Addr.Variable.descr1 != NULL) { -- ai->tag = Addr_Variable; -- return; -- } -- /* -- Have a look at the low level data symbols - perhaps it's in -- there. -- */ -- VG_(memset)( &ai->Addr.DataSym.name, -- 0, sizeof(ai->Addr.DataSym.name)); -- if (VG_(get_datasym_and_offset)( -- a, &ai->Addr.DataSym.name[0], -- sizeof(ai->Addr.DataSym.name)-1, -- &ai->Addr.DataSym.offset )) { -- ai->tag = Addr_DataSym; -- tl_assert( ai->Addr.DataSym.name -- [ sizeof(ai->Addr.DataSym.name)-1 ] == 0); -- return; -- } -- /* -- Perhaps it's on a thread's stack? -- */ -- VG_(thread_stack_reset_iter)(&tid); -- while ( VG_(thread_stack_next)(&tid, &stack_min, &stack_max) ) { -- if (stack_min - VG_STACK_REDZONE_SZB <= a && a <= stack_max) { -- ai->tag = Addr_Stack; -- ai->Addr.Stack.tid = tid; -- return; -- } -- } -- /* -- last ditch attempt at classification -- */ -- tl_assert( sizeof(ai->Addr.SectKind.objname) > 4 ); -- VG_(memset)( &ai->Addr.SectKind.objname, -- 0, sizeof(ai->Addr.SectKind.objname)); -- VG_(strcpy)( ai->Addr.SectKind.objname, "???" ); -- sect = VG_(DebugInfo_sect_kind)( &ai->Addr.SectKind.objname[0], -- sizeof(ai->Addr.SectKind.objname)-1, a); -- if (sect != Vg_SectUnknown) { -- ai->tag = Addr_SectKind; -- ai->Addr.SectKind.kind = sect; -- tl_assert( ai->Addr.SectKind.objname -- [ sizeof(ai->Addr.SectKind.objname)-1 ] == 0); -- return; -- } -- /* -- Clueless ... -- */ -- ai->tag = Addr_Unknown; -- return; -+ /* No block found. Search a non-heap block description. */ -+ VG_(describe_addr) (a, ai); - } - - void MC_(pp_describe_addr) ( Addr a ) -@@ -1314,7 +1006,7 @@ - - ai.tag = Addr_Undescribed; - describe_addr (a, &ai); -- mc_pp_AddrInfo (a, &ai, /* maybe_gcc */ False); -+ VG_(pp_addrinfo_mc) (a, &ai, /* maybe_gcc */ False); - } - - /* Fill in *origin_ec as specified by otag, or NULL it out if otag -Index: memcheck/mc_machine.c -=================================================================== ---- memcheck/mc_machine.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/mc_machine.c (.../trunk) (revision 13981) -@@ -76,6 +76,11 @@ - # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARMState) - #endif - -+#if defined(VGA_arm64) -+# include "libvex_guest_arm64.h" -+# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARM64State) -+#endif -+ - #if defined(VGA_mips32) - # include "libvex_guest_mips32.h" - # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestMIPS32State) -@@ -206,8 +211,8 @@ - if (o == GOF(FPROUND) && sz == 1) return -1; - if (o == GOF(DFPROUND) && sz == 1) return -1; - if (o == GOF(EMNOTE) && sz == 4) return -1; -- if (o == GOF(TISTART) && sz == 8) return -1; -- if (o == GOF(TILEN) && sz == 8) return -1; -+ if (o == GOF(CMSTART) && sz == 8) return -1; -+ if (o == GOF(CMLEN) && sz == 8) return -1; - if (o == GOF(VSCR) && sz == 4) return -1; - if (o == GOF(VRSAVE) && sz == 4) return -1; - if (o == GOF(REDIR_SP) && sz == 8) return -1; -@@ -407,8 +412,8 @@ - if (o == GOF(DFPROUND) && sz == 1) return -1; - if (o == GOF(VRSAVE) && sz == 4) return -1; - if (o == GOF(EMNOTE) && sz == 4) return -1; -- if (o == GOF(TISTART) && sz == 4) return -1; -- if (o == GOF(TILEN) && sz == 4) return -1; -+ if (o == GOF(CMSTART) && sz == 4) return -1; -+ if (o == GOF(CMLEN) && sz == 4) return -1; - if (o == GOF(VSCR) && sz == 4) return -1; - if (o == GOF(REDIR_SP) && sz == 4) return -1; - if (o == GOF(SPRG3_RO) && sz == 4) return -1; -@@ -596,8 +601,8 @@ - if (o == GOF(ACFLAG) && sz == 8) return -1; /* slot unused */ - if (o == GOF(FS_ZERO) && sz == 8) return -1; /* slot unused */ - if (o == GOF(GS_0x60) && sz == 8) return -1; /* slot unused */ -- if (o == GOF(TISTART) && sz == 8) return -1; /* slot unused */ -- if (o == GOF(TILEN) && sz == 8) return -1; /* slot unused */ -+ if (o == GOF(CMSTART) && sz == 8) return -1; /* slot unused */ -+ if (o == GOF(CMLEN) && sz == 8) return -1; /* slot unused */ - if (o == GOF(NRADDR) && sz == 8) return -1; /* slot unused */ - - /* Treat %AH, %BH, %CH, %DH as independent registers. To do this -@@ -709,8 +714,8 @@ - if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */ - if (o == GOF(IDFLAG) && sz == 4) return -1; /* slot used for %DH */ - if (o == GOF(ACFLAG) && sz == 4) return -1; /* slot unused */ -- if (o == GOF(TISTART) && sz == 4) return -1; /* slot unused */ -- if (o == GOF(TILEN) && sz == 4) return -1; /* slot unused */ -+ if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */ -+ if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */ - if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */ - - /* Treat %AH, %BH, %CH, %DH as independent registers. To do this -@@ -822,8 +827,8 @@ - return o; - if (o == GOF(CC_DEP2) && sz == 8) return o; - if (o == GOF(CC_NDEP) && sz == 8) return -1; -- if (o == GOF(TISTART) && sz == 8) return -1; -- if (o == GOF(TILEN) && sz == 8) return -1; -+ if (o == GOF(CMSTART) && sz == 8) return -1; -+ if (o == GOF(CMLEN) && sz == 8) return -1; - if (o == GOF(NRADDR) && sz == 8) return -1; - if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1; - if (o == GOF(fpc) && sz == 4) return -1; -@@ -885,7 +890,7 @@ - //if (o == GOF(SYSCALLNO) && sz == 4) return -1; /* slot unused */ - //if (o == GOF(CC) && sz == 4) return -1; /* slot unused */ - //if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */ -- //if (o == GOF(TISTART) && sz == 4) return -1; /* slot unused */ -+ //if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */ - //if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */ - - if (o == GOF(FPSCR) && sz == 4) return -1; -@@ -948,8 +953,8 @@ - if (o >= GOF(D30) && o+sz <= GOF(D30)+2*SZB(D30)) return GOF(D30); // Q15 - } - -- if (o == GOF(TISTART) && sz == 4) return -1; -- if (o == GOF(TILEN) && sz == 4) return -1; -+ if (o == GOF(CMSTART) && sz == 4) return -1; -+ if (o == GOF(CMLEN) && sz == 4) return -1; - - VG_(printf)("MC_(get_otrack_shadow_offset)(arm)(off=%d,sz=%d)\n", - offset,szB); -@@ -957,6 +962,108 @@ - # undef GOF - # undef SZB - -+ /* --------------------- arm64 --------------------- */ -+ -+# elif defined(VGA_arm64) -+ -+# define GOF(_fieldname) \ -+ (offsetof(VexGuestARM64State,guest_##_fieldname)) -+# define SZB(_fieldname) \ -+ (sizeof(((VexGuestARM64State*)0)->guest_##_fieldname)) -+ -+ Int o = offset; -+ Int sz = szB; -+ Bool is48 = sz == 8 || sz == 4; -+ -+ tl_assert(sz > 0); -+ tl_assert(host_is_little_endian()); -+ -+ if (o == GOF(X0) && is48) return o; -+ if (o == GOF(X1) && is48) return o; -+ if (o == GOF(X2) && is48) return o; -+ if (o == GOF(X3) && is48) return o; -+ if (o == GOF(X4) && is48) return o; -+ if (o == GOF(X5) && is48) return o; -+ if (o == GOF(X6) && is48) return o; -+ if (o == GOF(X7) && is48) return o; -+ if (o == GOF(X8) && is48) return o; -+ if (o == GOF(X9) && is48) return o; -+ if (o == GOF(X10) && is48) return o; -+ if (o == GOF(X11) && is48) return o; -+ if (o == GOF(X12) && is48) return o; -+ if (o == GOF(X13) && is48) return o; -+ if (o == GOF(X14) && is48) return o; -+ if (o == GOF(X15) && is48) return o; -+ if (o == GOF(X16) && is48) return o; -+ if (o == GOF(X17) && is48) return o; -+ if (o == GOF(X18) && is48) return o; -+ if (o == GOF(X19) && is48) return o; -+ if (o == GOF(X20) && is48) return o; -+ if (o == GOF(X21) && is48) return o; -+ if (o == GOF(X22) && is48) return o; -+ if (o == GOF(X23) && is48) return o; -+ if (o == GOF(X24) && is48) return o; -+ if (o == GOF(X25) && is48) return o; -+ if (o == GOF(X26) && is48) return o; -+ if (o == GOF(X27) && is48) return o; -+ if (o == GOF(X28) && is48) return o; -+ if (o == GOF(X29) && is48) return o; -+ if (o == GOF(X30) && is48) return o; -+ if (o == GOF(XSP) && is48) return o; -+ -+ if (o == GOF(PC) && is48) return -1; // untracked -+ if (o == GOF(CC_DEP1) && sz == 8) return o; -+ if (o == GOF(CC_DEP2) && sz == 8) return o; -+ -+ if (o == GOF(CC_OP) && sz == 8) return -1; // untracked -+ if (o == GOF(CC_NDEP) && sz == 8) return -1; // untracked -+ if (o == GOF(TPIDR_EL0) && sz == 8) return -1; // untracked -+ -+ if (o >= GOF(Q0) && o+sz <= GOF(Q0) +SZB(Q0)) return GOF(Q0); -+ if (o >= GOF(Q1) && o+sz <= GOF(Q1) +SZB(Q1)) return GOF(Q1); -+ if (o >= GOF(Q2) && o+sz <= GOF(Q2) +SZB(Q2)) return GOF(Q2); -+ if (o >= GOF(Q3) && o+sz <= GOF(Q3) +SZB(Q3)) return GOF(Q3); -+ if (o >= GOF(Q4) && o+sz <= GOF(Q4) +SZB(Q4)) return GOF(Q4); -+ if (o >= GOF(Q5) && o+sz <= GOF(Q5) +SZB(Q5)) return GOF(Q5); -+ if (o >= GOF(Q6) && o+sz <= GOF(Q6) +SZB(Q6)) return GOF(Q6); -+ if (o >= GOF(Q7) && o+sz <= GOF(Q7) +SZB(Q7)) return GOF(Q7); -+ if (o >= GOF(Q8) && o+sz <= GOF(Q8) +SZB(Q8)) return GOF(Q8); -+ if (o >= GOF(Q9) && o+sz <= GOF(Q9) +SZB(Q9)) return GOF(Q9); -+ if (o >= GOF(Q10) && o+sz <= GOF(Q10)+SZB(Q10)) return GOF(Q10); -+ if (o >= GOF(Q11) && o+sz <= GOF(Q11)+SZB(Q11)) return GOF(Q11); -+ if (o >= GOF(Q12) && o+sz <= GOF(Q12)+SZB(Q12)) return GOF(Q12); -+ if (o >= GOF(Q13) && o+sz <= GOF(Q13)+SZB(Q13)) return GOF(Q13); -+ if (o >= GOF(Q14) && o+sz <= GOF(Q14)+SZB(Q14)) return GOF(Q14); -+ if (o >= GOF(Q15) && o+sz <= GOF(Q15)+SZB(Q15)) return GOF(Q15); -+ if (o >= GOF(Q16) && o+sz <= GOF(Q16)+SZB(Q16)) return GOF(Q16); -+ if (o >= GOF(Q17) && o+sz <= GOF(Q17)+SZB(Q17)) return GOF(Q17); -+ if (o >= GOF(Q18) && o+sz <= GOF(Q18)+SZB(Q18)) return GOF(Q18); -+ if (o >= GOF(Q19) && o+sz <= GOF(Q19)+SZB(Q19)) return GOF(Q19); -+ if (o >= GOF(Q20) && o+sz <= GOF(Q20)+SZB(Q20)) return GOF(Q20); -+ if (o >= GOF(Q21) && o+sz <= GOF(Q21)+SZB(Q21)) return GOF(Q21); -+ if (o >= GOF(Q22) && o+sz <= GOF(Q22)+SZB(Q22)) return GOF(Q22); -+ if (o >= GOF(Q23) && o+sz <= GOF(Q23)+SZB(Q23)) return GOF(Q23); -+ if (o >= GOF(Q24) && o+sz <= GOF(Q24)+SZB(Q24)) return GOF(Q24); -+ if (o >= GOF(Q25) && o+sz <= GOF(Q25)+SZB(Q25)) return GOF(Q25); -+ if (o >= GOF(Q26) && o+sz <= GOF(Q26)+SZB(Q26)) return GOF(Q26); -+ if (o >= GOF(Q27) && o+sz <= GOF(Q27)+SZB(Q27)) return GOF(Q27); -+ if (o >= GOF(Q28) && o+sz <= GOF(Q28)+SZB(Q28)) return GOF(Q28); -+ if (o >= GOF(Q29) && o+sz <= GOF(Q29)+SZB(Q29)) return GOF(Q29); -+ if (o >= GOF(Q30) && o+sz <= GOF(Q30)+SZB(Q30)) return GOF(Q30); -+ if (o >= GOF(Q31) && o+sz <= GOF(Q31)+SZB(Q31)) return GOF(Q31); -+ -+ if (o == GOF(FPCR) && sz == 4) return -1; // untracked -+ if (o == GOF(FPSR) && sz == 4) return -1; // untracked -+ -+ if (o == GOF(CMSTART) && sz == 8) return -1; // untracked -+ if (o == GOF(CMLEN) && sz == 8) return -1; // untracked -+ -+ VG_(printf)("MC_(get_otrack_shadow_offset)(arm64)(off=%d,sz=%d)\n", -+ offset,szB); -+ tl_assert(0); -+# undef GOF -+# undef SZB -+ - /* --------------------- mips32 --------------------- */ - - # elif defined(VGA_mips32) -@@ -1022,8 +1129,8 @@ - if (o == GOF(ULR) && sz == 4) return -1; - - if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */ -- if (o == GOF(TISTART) && sz == 4) return -1; /* slot unused */ -- if (o == GOF(TILEN) && sz == 4) return -1; /* slot unused */ -+ if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */ -+ if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */ - if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */ - - if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0); -@@ -1110,8 +1217,8 @@ - if (o == GOF(ULR) && sz == 8) return o; - - if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */ -- if (o == GOF(TISTART) && sz == 4) return -1; /* slot unused */ -- if (o == GOF(TILEN) && sz == 4) return -1; /* slot unused */ -+ if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */ -+ if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */ - if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */ - - if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0); -@@ -1243,6 +1350,13 @@ - VG_(printf)("\n"); - tl_assert(0); - -+ /* --------------------- arm64 --------------------- */ -+# elif defined(VGA_arm64) -+ VG_(printf)("get_reg_array_equiv_int_type(arm64): unhandled: "); -+ ppIRRegArray(arr); -+ VG_(printf)("\n"); -+ tl_assert(0); -+ - /* --------------------- s390x --------------------- */ - # elif defined(VGA_s390x) - /* Should never het here because s390x does not use Ist_PutI -Index: memcheck/mc_main.c -=================================================================== ---- memcheck/mc_main.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/mc_main.c (.../trunk) (revision 13981) -@@ -42,6 +42,7 @@ - #include "pub_tool_mallocfree.h" - #include "pub_tool_options.h" - #include "pub_tool_oset.h" -+#include "pub_tool_rangemap.h" - #include "pub_tool_replacemalloc.h" - #include "pub_tool_tooliface.h" - #include "pub_tool_threadstate.h" -@@ -606,7 +607,7 @@ - return &am->sm; - } - --static SecMap** get_secmap_ptr ( Addr a ) -+static INLINE SecMap** get_secmap_ptr ( Addr a ) - { - return ( a <= MAX_PRIMARY_ADDRESS - ? get_secmap_low_ptr(a) -@@ -658,7 +659,7 @@ - writable copy of it, install it, and return the copy instead. (COW - semantics). - */ --static SecMap* get_secmap_for_writing ( Addr a ) -+static INLINE SecMap* get_secmap_for_writing ( Addr a ) - { - return ( a <= MAX_PRIMARY_ADDRESS - ? get_secmap_for_writing_low (a) -@@ -1056,28 +1057,58 @@ - - /* --------------- Ignored address ranges --------------- */ - --#define M_IGNORE_RANGES 4 -+/* Denotes the address-error-reportability status for address ranges: -+ IAR_NotIgnored: the usual case -- report errors in this range -+ IAR_CommandLine: don't report errors -- from command line setting -+ IAR_ClientReq: don't report errors -- from client request -+*/ -+typedef -+ enum { IAR_INVALID=99, -+ IAR_NotIgnored, -+ IAR_CommandLine, -+ IAR_ClientReq } -+ IARKind; - --typedef -- struct { -- Int used; -- Addr start[M_IGNORE_RANGES]; -- Addr end[M_IGNORE_RANGES]; -+static const HChar* showIARKind ( IARKind iark ) -+{ -+ switch (iark) { -+ case IAR_INVALID: return "INVALID"; -+ case IAR_NotIgnored: return "NotIgnored"; -+ case IAR_CommandLine: return "CommandLine"; -+ case IAR_ClientReq: return "ClientReq"; -+ default: return "???"; - } -- IgnoreRanges; -+} - --static IgnoreRanges ignoreRanges; -+// RangeMap -+static RangeMap* gIgnoredAddressRanges = NULL; - -+static void init_gIgnoredAddressRanges ( void ) -+{ -+ if (LIKELY(gIgnoredAddressRanges != NULL)) -+ return; -+ gIgnoredAddressRanges = VG_(newRangeMap)( VG_(malloc), "mc.igIAR.1", -+ VG_(free), IAR_NotIgnored ); -+ tl_assert(gIgnoredAddressRanges != NULL); -+} -+ - INLINE Bool MC_(in_ignored_range) ( Addr a ) - { -- Int i; -- if (LIKELY(ignoreRanges.used == 0)) -+ if (LIKELY(gIgnoredAddressRanges == NULL)) - return False; -- for (i = 0; i < ignoreRanges.used; i++) { -- if (a >= ignoreRanges.start[i] && a < ignoreRanges.end[i]) -- return True; -+ UWord how = IAR_INVALID; -+ UWord key_min = ~(UWord)0; -+ UWord key_max = (UWord)0; -+ VG_(lookupRangeMap)(&key_min, &key_max, &how, gIgnoredAddressRanges, a); -+ tl_assert(key_min <= a && a <= key_max); -+ switch (how) { -+ case IAR_NotIgnored: return False; -+ case IAR_CommandLine: return True; -+ case IAR_ClientReq: return True; -+ default: break; /* invalid */ - } -- return False; -+ VG_(tool_panic)("MC_(in_ignore_range)"); -+ /*NOTREACHED*/ - } - - /* Parse two Addr separated by a dash, or fail. */ -@@ -1097,24 +1128,22 @@ - } - - /* Parse a set of ranges separated by commas into 'ignoreRanges', or -- fail. */ -- -+ fail. If they are valid, add them to the global set of ignored -+ ranges. */ - static Bool parse_ignore_ranges ( const HChar* str0 ) - { -- Addr start, end; -- Bool ok; -+ init_gIgnoredAddressRanges(); - const HChar* str = str0; - const HChar** ppc = &str; -- ignoreRanges.used = 0; - while (1) { -- ok = parse_range(ppc, &start, &end); -+ Addr start = ~(Addr)0; -+ Addr end = (Addr)0; -+ Bool ok = parse_range(ppc, &start, &end); - if (!ok) - return False; -- if (ignoreRanges.used >= M_IGNORE_RANGES) -+ if (start > end) - return False; -- ignoreRanges.start[ignoreRanges.used] = start; -- ignoreRanges.end[ignoreRanges.used] = end; -- ignoreRanges.used++; -+ VG_(bindRangeMap)( gIgnoredAddressRanges, start, end, IAR_CommandLine ); - if (**ppc == 0) - return True; - if (**ppc != ',') -@@ -1125,7 +1154,45 @@ - return False; - } - -+/* Add or remove [start, +len) from the set of ignored ranges. */ -+static Bool modify_ignore_ranges ( Bool addRange, Addr start, Addr len ) -+{ -+ init_gIgnoredAddressRanges(); -+ const Bool verbose = (VG_(clo_verbosity) > 1); -+ if (len == 0) { -+ return False; -+ } -+ if (addRange) { -+ VG_(bindRangeMap)(gIgnoredAddressRanges, -+ start, start+len-1, IAR_ClientReq); -+ if (verbose) -+ VG_(dmsg)("memcheck: modify_ignore_ranges: add %p %p\n", -+ (void*)start, (void*)(start+len-1)); -+ } else { -+ VG_(bindRangeMap)(gIgnoredAddressRanges, -+ start, start+len-1, IAR_NotIgnored); -+ if (verbose) -+ VG_(dmsg)("memcheck: modify_ignore_ranges: del %p %p\n", -+ (void*)start, (void*)(start+len-1)); -+ } -+ if (verbose) { -+ VG_(dmsg)("memcheck: now have %ld ranges:\n", -+ VG_(sizeRangeMap)(gIgnoredAddressRanges)); -+ Word i; -+ for (i = 0; i < VG_(sizeRangeMap)(gIgnoredAddressRanges); i++) { -+ UWord val = IAR_INVALID; -+ UWord key_min = ~(UWord)0; -+ UWord key_max = (UWord)0; -+ VG_(indexRangeMap)( &key_min, &key_max, &val, -+ gIgnoredAddressRanges, i ); -+ VG_(dmsg)("memcheck: [%ld] %016llx-%016llx %s\n", -+ i, (ULong)key_min, (ULong)key_max, showIARKind(val)); -+ } -+ } -+ return True; -+} - -+ - /* --------------- Load/store slow cases. --------------- */ - - static -@@ -1168,7 +1235,7 @@ - ULong pessim64 = V_BITS64_DEFINED; - UWord long_index = byte_offset_w(szL, bigendian, j); - for (i = 8-1; i >= 0; i--) { -- PROF_EVENT(31, "mc_LOADV_128_or_256_slow(loop)"); -+ PROF_EVENT(29, "mc_LOADV_128_or_256_slow(loop)"); - ai = a + 8*long_index + byte_offset_w(8, bigendian, i); - ok = get_vbits8(ai, &vbits8); - vbits64 <<= 8; -@@ -1405,8 +1472,9 @@ - cases on 64-bit platforms. Are merely a speedup hack; can be - omitted without loss of correctness/functionality. Note that in - both cases the "sizeof(void*) == 8" causes these cases to be -- folded out by compilers on 32-bit platforms. These are derived -- from STOREV64 and STOREV32. -+ folded out by compilers on 32-bit platforms. The logic below -+ is somewhat similar to some cases extensively commented in -+ MC_(helperc_STOREV8). - */ - if (LIKELY(sizeof(void*) == 8 - && nBits == 64 && VG_IS_8_ALIGNED(a))) { -@@ -1729,7 +1797,7 @@ - - void MC_(make_mem_undefined_w_otag) ( Addr a, SizeT len, UInt otag ) - { -- PROF_EVENT(41, "MC_(make_mem_undefined)"); -+ PROF_EVENT(43, "MC_(make_mem_undefined)"); - DEBUG("MC_(make_mem_undefined)(%p, %lu)\n", a, len); - set_address_range_perms ( a, len, VA_BITS16_UNDEFINED, SM_DIST_UNDEFINED ); - if (UNLIKELY( MC_(clo_mc_level) == 3 )) -@@ -4361,27 +4429,35 @@ - sm_off16 = SM_OFF_16(a); - vabits16 = ((UShort*)(sm->vabits8))[sm_off16]; - -- if (LIKELY( !is_distinguished_sm(sm) && -- (VA_BITS16_DEFINED == vabits16 || -- VA_BITS16_UNDEFINED == vabits16) )) -- { -- /* Handle common case quickly: a is suitably aligned, */ -- /* is mapped, and is addressible. */ -- // Convert full V-bits in register to compact 2-bit form. -- if (V_BITS64_DEFINED == vbits64) { -+ // To understand the below cleverness, see the extensive comments -+ // in MC_(helperc_STOREV8). -+ if (LIKELY(V_BITS64_DEFINED == vbits64)) { -+ if (LIKELY(vabits16 == (UShort)VA_BITS16_DEFINED)) { -+ return; -+ } -+ if (!is_distinguished_sm(sm) && VA_BITS16_UNDEFINED == vabits16) { - ((UShort*)(sm->vabits8))[sm_off16] = (UShort)VA_BITS16_DEFINED; -- } else if (V_BITS64_UNDEFINED == vbits64) { -- ((UShort*)(sm->vabits8))[sm_off16] = (UShort)VA_BITS16_UNDEFINED; -- } else { -- /* Slow but general case -- writing partially defined bytes. */ -- PROF_EVENT(212, "mc_STOREV64-slow2"); -- mc_STOREVn_slow( a, 64, vbits64, isBigEndian ); -+ return; - } -- } else { -- /* Slow but general case. */ -- PROF_EVENT(213, "mc_STOREV64-slow3"); -+ PROF_EVENT(232, "mc_STOREV64-slow2"); - mc_STOREVn_slow( a, 64, vbits64, isBigEndian ); -+ return; - } -+ if (V_BITS64_UNDEFINED == vbits64) { -+ if (vabits16 == (UShort)VA_BITS16_UNDEFINED) { -+ return; -+ } -+ if (!is_distinguished_sm(sm) && VA_BITS16_DEFINED == vabits16) { -+ ((UShort*)(sm->vabits8))[sm_off16] = (UShort)VA_BITS16_UNDEFINED; -+ return; -+ } -+ PROF_EVENT(232, "mc_STOREV64-slow3"); -+ mc_STOREVn_slow( a, 64, vbits64, isBigEndian ); -+ return; -+ } -+ -+ PROF_EVENT(212, "mc_STOREV64-slow4"); -+ mc_STOREVn_slow( a, 64, vbits64, isBigEndian ); - } - #endif - } -@@ -4469,35 +4545,35 @@ - sm_off = SM_OFF(a); - vabits8 = sm->vabits8[sm_off]; - -- // Cleverness: sometimes we don't have to write the shadow memory at -- // all, if we can tell that what we want to write is the same as what is -- // already there. The 64/16/8 bit cases also have cleverness at this -- // point, but it works a little differently to the code below. -- if (V_BITS32_DEFINED == vbits32) { -- if (vabits8 == (UInt)VA_BITS8_DEFINED) { -+ // To understand the below cleverness, see the extensive comments -+ // in MC_(helperc_STOREV8). -+ if (LIKELY(V_BITS32_DEFINED == vbits32)) { -+ if (LIKELY(vabits8 == (UInt)VA_BITS8_DEFINED)) { - return; -- } else if (!is_distinguished_sm(sm) && VA_BITS8_UNDEFINED == vabits8) { -+ } -+ if (!is_distinguished_sm(sm) && VA_BITS8_UNDEFINED == vabits8) { - sm->vabits8[sm_off] = (UInt)VA_BITS8_DEFINED; -- } else { -- // not defined/undefined, or distinguished and changing state -- PROF_EVENT(232, "mc_STOREV32-slow2"); -- mc_STOREVn_slow( a, 32, (ULong)vbits32, isBigEndian ); -+ return; - } -- } else if (V_BITS32_UNDEFINED == vbits32) { -+ PROF_EVENT(232, "mc_STOREV32-slow2"); -+ mc_STOREVn_slow( a, 32, (ULong)vbits32, isBigEndian ); -+ return; -+ } -+ if (V_BITS32_UNDEFINED == vbits32) { - if (vabits8 == (UInt)VA_BITS8_UNDEFINED) { - return; -- } else if (!is_distinguished_sm(sm) && VA_BITS8_DEFINED == vabits8) { -+ } -+ if (!is_distinguished_sm(sm) && VA_BITS8_DEFINED == vabits8) { - sm->vabits8[sm_off] = (UInt)VA_BITS8_UNDEFINED; -- } else { -- // not defined/undefined, or distinguished and changing state -- PROF_EVENT(233, "mc_STOREV32-slow3"); -- mc_STOREVn_slow( a, 32, (ULong)vbits32, isBigEndian ); -+ return; - } -- } else { -- // Partially defined word -- PROF_EVENT(234, "mc_STOREV32-slow4"); -+ PROF_EVENT(233, "mc_STOREV32-slow3"); - mc_STOREVn_slow( a, 32, (ULong)vbits32, isBigEndian ); -+ return; - } -+ -+ PROF_EVENT(234, "mc_STOREV32-slow4"); -+ mc_STOREVn_slow( a, 32, (ULong)vbits32, isBigEndian ); - } - #endif - } -@@ -4564,6 +4640,18 @@ - return mc_LOADV16(a, False); - } - -+/* True if the vabits4 in vabits8 indicate a and a+1 are accessible. */ -+static INLINE -+Bool accessible_vabits4_in_vabits8 ( Addr a, UChar vabits8 ) -+{ -+ UInt shift; -+ tl_assert(VG_IS_2_ALIGNED(a)); // Must be 2-aligned -+ shift = (a & 2) << 1; // shift by 0 or 4 -+ vabits8 >>= shift; // shift the four bits to the bottom -+ // check 2 x vabits2 != VA_BITS2_NOACCESS -+ return ((0x3 & vabits8) != VA_BITS2_NOACCESS) -+ && ((0xc & vabits8) != VA_BITS2_NOACCESS << 2); -+} - - static INLINE - void mc_STOREV16 ( Addr a, UWord vbits16, Bool isBigEndian ) -@@ -4586,29 +4674,39 @@ - sm = get_secmap_for_reading_low(a); - sm_off = SM_OFF(a); - vabits8 = sm->vabits8[sm_off]; -- if (LIKELY( !is_distinguished_sm(sm) && -- (VA_BITS8_DEFINED == vabits8 || -- VA_BITS8_UNDEFINED == vabits8) )) -- { -- /* Handle common case quickly: a is suitably aligned, */ -- /* is mapped, and is addressible. */ -- // Convert full V-bits in register to compact 2-bit form. -- if (V_BITS16_DEFINED == vbits16) { -- insert_vabits4_into_vabits8( a, VA_BITS4_DEFINED , -+ -+ // To understand the below cleverness, see the extensive comments -+ // in MC_(helperc_STOREV8). -+ if (LIKELY(V_BITS16_DEFINED == vbits16)) { -+ if (LIKELY(vabits8 == VA_BITS8_DEFINED)) { -+ return; -+ } -+ if (!is_distinguished_sm(sm) -+ && accessible_vabits4_in_vabits8(a, vabits8)) { -+ insert_vabits4_into_vabits8( a, VA_BITS4_DEFINED, - &(sm->vabits8[sm_off]) ); -- } else if (V_BITS16_UNDEFINED == vbits16) { -+ return; -+ } -+ PROF_EVENT(232, "mc_STOREV16-slow2"); -+ mc_STOREVn_slow( a, 16, (ULong)vbits16, isBigEndian ); -+ } -+ if (V_BITS16_UNDEFINED == vbits16) { -+ if (vabits8 == VA_BITS8_UNDEFINED) { -+ return; -+ } -+ if (!is_distinguished_sm(sm) -+ && accessible_vabits4_in_vabits8(a, vabits8)) { - insert_vabits4_into_vabits8( a, VA_BITS4_UNDEFINED, - &(sm->vabits8[sm_off]) ); -- } else { -- /* Slow but general case -- writing partially defined bytes. */ -- PROF_EVENT(252, "mc_STOREV16-slow2"); -- mc_STOREVn_slow( a, 16, (ULong)vbits16, isBigEndian ); -+ return; - } -- } else { -- /* Slow but general case. */ -- PROF_EVENT(253, "mc_STOREV16-slow3"); -+ PROF_EVENT(233, "mc_STOREV16-slow3"); - mc_STOREVn_slow( a, 16, (ULong)vbits16, isBigEndian ); -+ return; - } -+ -+ PROF_EVENT(234, "mc_STOREV16-slow4"); -+ mc_STOREVn_slow( a, 16, (ULong)vbits16, isBigEndian ); - } - #endif - } -@@ -4689,33 +4787,78 @@ - sm = get_secmap_for_reading_low(a); - sm_off = SM_OFF(a); - vabits8 = sm->vabits8[sm_off]; -- if (LIKELY -- ( !is_distinguished_sm(sm) && -- ( (VA_BITS8_DEFINED == vabits8 || VA_BITS8_UNDEFINED == vabits8) -- || (VA_BITS2_NOACCESS != extract_vabits2_from_vabits8(a, vabits8)) -- ) -- ) -- ) -- { -- /* Handle common case quickly: a is mapped, the entire word32 it -- lives in is addressible. */ -- // Convert full V-bits in register to compact 2-bit form. -- if (V_BITS8_DEFINED == vbits8) { -+ -+ // Clevernesses to speed up storing V bits. -+ // The 64/32/16 bit cases also have similar clevernesses, but it -+ // works a little differently to the code below. -+ // -+ // Cleverness 1: sometimes we don't have to write the shadow memory at -+ // all, if we can tell that what we want to write is the same as what is -+ // already there. These cases are marked below as "defined on defined" and -+ // "undefined on undefined". -+ // -+ // Cleverness 2: -+ // We also avoid to call mc_STOREVn_slow if the V bits can directly -+ // be written in the secondary map. V bits can be directly written -+ // if 4 conditions are respected: -+ // * The address for which V bits are written is naturally aligned -+ // on 1 byte for STOREV8 (this is always true) -+ // on 2 bytes for STOREV16 -+ // on 4 bytes for STOREV32 -+ // on 8 bytes for STOREV64. -+ // * V bits being written are either fully defined or fully undefined. -+ // (for partially defined V bits, V bits cannot be directly written, -+ // as the secondary vbits table must be maintained). -+ // * the secmap is not distinguished (distinguished maps cannot be -+ // modified). -+ // * the memory corresponding to the V bits being written is -+ // accessible (if one or more bytes are not accessible, -+ // we must call mc_STOREVn_slow in order to report accessibility -+ // errors). -+ // Note that for STOREV32 and STOREV64, it is too expensive -+ // to verify the accessibility of each byte for the benefit it -+ // brings. Instead, a quicker check is done by comparing to -+ // VA_BITS(8|16)_(UN)DEFINED. This guarantees accessibility, -+ // but misses some opportunity of direct modifications. -+ // Checking each byte accessibility was measured for -+ // STOREV32+perf tests and was slowing down all perf tests. -+ // The cases corresponding to cleverness 2 are marked below as -+ // "direct mod". -+ if (LIKELY(V_BITS8_DEFINED == vbits8)) { -+ if (LIKELY(vabits8 == VA_BITS8_DEFINED)) { -+ return; // defined on defined -+ } -+ if (!is_distinguished_sm(sm) -+ && VA_BITS2_NOACCESS != extract_vabits2_from_vabits8(a, vabits8)) { -+ // direct mod - insert_vabits2_into_vabits8( a, VA_BITS2_DEFINED, -- &(sm->vabits8[sm_off]) ); -- } else if (V_BITS8_UNDEFINED == vbits8) { -+ &(sm->vabits8[sm_off]) ); -+ return; -+ } -+ PROF_EVENT(232, "mc_STOREV8-slow2"); -+ mc_STOREVn_slow( a, 8, (ULong)vbits8, False/*irrelevant*/ ); -+ return; -+ } -+ if (V_BITS8_UNDEFINED == vbits8) { -+ if (vabits8 == VA_BITS8_UNDEFINED) { -+ return; // undefined on undefined -+ } -+ if (!is_distinguished_sm(sm) -+ && (VA_BITS2_NOACCESS -+ != extract_vabits2_from_vabits8(a, vabits8))) { -+ // direct mod - insert_vabits2_into_vabits8( a, VA_BITS2_UNDEFINED, -- &(sm->vabits8[sm_off]) ); -- } else { -- /* Slow but general case -- writing partially defined bytes. */ -- PROF_EVENT(272, "mc_STOREV8-slow2"); -- mc_STOREVn_slow( a, 8, (ULong)vbits8, False/*irrelevant*/ ); -+ &(sm->vabits8[sm_off]) ); -+ return; - } -- } else { -- /* Slow but general case. */ -- PROF_EVENT(273, "mc_STOREV8-slow3"); -+ PROF_EVENT(233, "mc_STOREV8-slow3"); - mc_STOREVn_slow( a, 8, (ULong)vbits8, False/*irrelevant*/ ); -+ return; - } -+ -+ // Partially defined word -+ PROF_EVENT(234, "mc_STOREV8-slow4"); -+ mc_STOREVn_slow( a, 8, (ULong)vbits8, False/*irrelevant*/ ); - } - #endif - } -@@ -5047,50 +5190,8 @@ - - static Bool MC_(parse_leak_heuristics) ( const HChar *str0, UInt *lhs ) - { -- SizeT str0len = VG_(strlen)(str0); -- if (str0len > 1000) return False; /* "obviously invalid" */ -- HChar tok_str0[str0len+1]; -- HChar *saveptr; -- HChar *token; -- -- Bool seen_all_kw = False; -- Bool seen_none_kw = False; -- -- VG_(strcpy) (tok_str0, str0); -- *lhs = 0; -- -- for (token = VG_(strtok_r)(tok_str0, ",", &saveptr); -- token; -- token = VG_(strtok_r)(NULL, ",", &saveptr)) { -- if (0 == VG_(strcmp)(token, "stdstring")) -- *lhs |= H2S(LchStdString); -- else if (0 == VG_(strcmp)(token, "newarray")) -- *lhs |= H2S(LchNewArray); -- else if (0 == VG_(strcmp)(token, "multipleinheritance")) -- *lhs |= H2S(LchMultipleInheritance); -- else if (0 == VG_(strcmp)(token, "all")) -- seen_all_kw = True; -- else if (0 == VG_(strcmp)(token, "none")) -- seen_none_kw = True; -- else -- return False; -- } -- -- if (seen_all_kw) { -- if (seen_none_kw || *lhs) -- return False; // mixing all with either none or a specific value. -- *lhs = HallS; -- } else if (seen_none_kw) { -- if (seen_all_kw || *lhs) -- return False; // mixing none with either all or a specific value. -- *lhs = 0; -- } else { -- // seen neither all or none, we must see at least one value -- if (*lhs == 0) -- return False; -- } -- -- return True; -+ return VG_(parse_enum_set) ("-,stdstring,newarray,multipleinheritance", -+ str0, lhs); - } - - -@@ -5191,30 +5292,32 @@ - MC_(clo_leak_resolution), Vg_HighRes) {} - - else if VG_STR_CLO(arg, "--ignore-ranges", tmp_str) { -- Int i; -- Bool ok = parse_ignore_ranges(tmp_str); -- if (!ok) -- return False; -- tl_assert(ignoreRanges.used >= 0); -- tl_assert(ignoreRanges.used < M_IGNORE_RANGES); -- for (i = 0; i < ignoreRanges.used; i++) { -- Addr s = ignoreRanges.start[i]; -- Addr e = ignoreRanges.end[i]; -- Addr limit = 0x4000000; /* 64M - entirely arbitrary limit */ -- if (e <= s) { -- VG_(message)(Vg_DebugMsg, -- "ERROR: --ignore-ranges: end <= start in range:\n"); -- VG_(message)(Vg_DebugMsg, -- " 0x%lx-0x%lx\n", s, e); -- return False; -+ Bool ok = parse_ignore_ranges(tmp_str); -+ if (!ok) { -+ VG_(message)(Vg_DebugMsg, -+ "ERROR: --ignore-ranges: " -+ "invalid syntax, or end <= start in range\n"); -+ return False; -+ } -+ if (gIgnoredAddressRanges) { -+ Word i; -+ for (i = 0; i < VG_(sizeRangeMap)(gIgnoredAddressRanges); i++) { -+ UWord val = IAR_INVALID; -+ UWord key_min = ~(UWord)0; -+ UWord key_max = (UWord)0; -+ VG_(indexRangeMap)( &key_min, &key_max, &val, -+ gIgnoredAddressRanges, i ); -+ tl_assert(key_min <= key_max); -+ UWord limit = 0x4000000; /* 64M - entirely arbitrary limit */ -+ if (key_max - key_min > limit) { -+ VG_(message)(Vg_DebugMsg, -+ "ERROR: --ignore-ranges: suspiciously large range:\n"); -+ VG_(message)(Vg_DebugMsg, -+ " 0x%lx-0x%lx (size %ld)\n", key_min, key_max, -+ key_max - key_min + 1); -+ return False; -+ } - } -- if (e - s > limit) { -- VG_(message)(Vg_DebugMsg, -- "ERROR: --ignore-ranges: suspiciously large range:\n"); -- VG_(message)(Vg_DebugMsg, -- " 0x%lx-0x%lx (size %ld)\n", s, e, (UWord)(e-s)); -- return False; -- } - } - } - -@@ -5410,7 +5513,7 @@ - static Bool handle_gdb_monitor_command (ThreadId tid, HChar *req) - { - HChar* wcmd; -- HChar s[VG_(strlen(req))]; /* copy for strtok_r */ -+ HChar s[VG_(strlen(req)) + 1]; /* copy for strtok_r */ - HChar *ssaveptr; - - VG_(strcpy) (s, req); -@@ -5433,8 +5536,7 @@ - case 1: { /* get_vbits */ - Addr address; - SizeT szB = 1; -- VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr); -- if (szB != 0) { -+ if (VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr)) { - UChar vbits; - Int i; - Int unaddressable = 0; -@@ -5568,8 +5670,8 @@ - Int kwdid = VG_(keyword_id) - ("noaccess undefined defined Definedifaddressable", - VG_(strtok_r) (NULL, " ", &ssaveptr), kwd_report_all); -- VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr); -- if (address == (Addr) 0 && szB == 0) return True; -+ if (!VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr)) -+ return True; - switch (kwdid) { - case -2: break; - case -1: break; -@@ -5597,8 +5699,8 @@ - Int kwdid = VG_(keyword_id) - ("addressable defined", - VG_(strtok_r) (NULL, " ", &ssaveptr), kwd_report_all); -- VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr); -- if (address == (Addr) 0 && szB == 0) return True; -+ if (!VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr)) -+ return True; - switch (kwdid) { - case -2: break; - case -1: break; -@@ -5672,7 +5774,8 @@ - Addr address; - SizeT szB = 1; - -- VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr); -+ if (!VG_(strtok_get_address_and_size) (&address, &szB, &ssaveptr)) -+ return True; - if (address == (Addr) 0) { - VG_(gdb_printf) ("Cannot search who points at 0x0\n"); - return True; -@@ -5694,7 +5797,6 @@ - static Bool mc_handle_client_request ( ThreadId tid, UWord* arg, UWord* ret ) - { - Int i; -- Bool ok; - Addr bad_addr; - - if (!VG_IS_TOOL_USERREQ('M','C',arg[0]) -@@ -5709,16 +5811,19 @@ - && VG_USERREQ__MOVE_MEMPOOL != arg[0] - && VG_USERREQ__MEMPOOL_CHANGE != arg[0] - && VG_USERREQ__MEMPOOL_EXISTS != arg[0] -- && VG_USERREQ__GDB_MONITOR_COMMAND != arg[0]) -+ && VG_USERREQ__GDB_MONITOR_COMMAND != arg[0] -+ && VG_USERREQ__ENABLE_ADDR_ERROR_REPORTING_IN_RANGE != arg[0] -+ && VG_USERREQ__DISABLE_ADDR_ERROR_REPORTING_IN_RANGE != arg[0]) - return False; - - switch (arg[0]) { -- case VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE: -- ok = is_mem_addressable ( arg[1], arg[2], &bad_addr ); -+ case VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE: { -+ Bool ok = is_mem_addressable ( arg[1], arg[2], &bad_addr ); - if (!ok) - MC_(record_user_error) ( tid, bad_addr, /*isAddrErr*/True, 0 ); - *ret = ok ? (UWord)NULL : bad_addr; - break; -+ } - - case VG_USERREQ__CHECK_MEM_IS_DEFINED: { - Bool errorV = False; -@@ -5997,6 +6102,16 @@ - return handled; - } - -+ case VG_USERREQ__DISABLE_ADDR_ERROR_REPORTING_IN_RANGE: -+ case VG_USERREQ__ENABLE_ADDR_ERROR_REPORTING_IN_RANGE: { -+ Bool addRange -+ = arg[0] == VG_USERREQ__DISABLE_ADDR_ERROR_REPORTING_IN_RANGE; -+ Bool ok -+ = modify_ignore_ranges(addRange, arg[1], arg[2]); -+ *ret = ok ? 1 : 0; -+ return True; -+ } -+ - default: - VG_(message)( - Vg_UserMsg, -@@ -6539,6 +6654,100 @@ - n_SMs * sizeof(SecMap) / (1024 * 1024UL) ); - } - -+static void mc_print_stats (void) -+{ -+ SizeT max_secVBit_szB, max_SMs_szB, max_shmem_szB; -+ -+ VG_(message)(Vg_DebugMsg, " memcheck: freelist: vol %lld length %lld\n", -+ VG_(free_queue_volume), VG_(free_queue_length)); -+ VG_(message)(Vg_DebugMsg, -+ " memcheck: sanity checks: %d cheap, %d expensive\n", -+ n_sanity_cheap, n_sanity_expensive ); -+ VG_(message)(Vg_DebugMsg, -+ " memcheck: auxmaps: %lld auxmap entries (%lldk, %lldM) in use\n", -+ n_auxmap_L2_nodes, -+ n_auxmap_L2_nodes * 64, -+ n_auxmap_L2_nodes / 16 ); -+ VG_(message)(Vg_DebugMsg, -+ " memcheck: auxmaps_L1: %lld searches, %lld cmps, ratio %lld:10\n", -+ n_auxmap_L1_searches, n_auxmap_L1_cmps, -+ (10ULL * n_auxmap_L1_cmps) -+ / (n_auxmap_L1_searches ? n_auxmap_L1_searches : 1) -+ ); -+ VG_(message)(Vg_DebugMsg, -+ " memcheck: auxmaps_L2: %lld searches, %lld nodes\n", -+ n_auxmap_L2_searches, n_auxmap_L2_nodes -+ ); -+ -+ print_SM_info("n_issued ", n_issued_SMs); -+ print_SM_info("n_deissued ", n_deissued_SMs); -+ print_SM_info("max_noaccess ", max_noaccess_SMs); -+ print_SM_info("max_undefined", max_undefined_SMs); -+ print_SM_info("max_defined ", max_defined_SMs); -+ print_SM_info("max_non_DSM ", max_non_DSM_SMs); -+ -+ // Three DSMs, plus the non-DSM ones -+ max_SMs_szB = (3 + max_non_DSM_SMs) * sizeof(SecMap); -+ // The 3*sizeof(Word) bytes is the AVL node metadata size. -+ // The VG_ROUNDUP is because the OSet pool allocator will/must align -+ // the elements on pointer size. -+ // Note that the pool allocator has some additional small overhead -+ // which is not counted in the below. -+ // Hardwiring this logic sucks, but I don't see how else to do it. -+ max_secVBit_szB = max_secVBit_nodes * -+ (3*sizeof(Word) + VG_ROUNDUP(sizeof(SecVBitNode), sizeof(void*))); -+ max_shmem_szB = sizeof(primary_map) + max_SMs_szB + max_secVBit_szB; -+ -+ VG_(message)(Vg_DebugMsg, -+ " memcheck: max sec V bit nodes: %d (%ldk, %ldM)\n", -+ max_secVBit_nodes, max_secVBit_szB / 1024, -+ max_secVBit_szB / (1024 * 1024)); -+ VG_(message)(Vg_DebugMsg, -+ " memcheck: set_sec_vbits8 calls: %llu (new: %llu, updates: %llu)\n", -+ sec_vbits_new_nodes + sec_vbits_updates, -+ sec_vbits_new_nodes, sec_vbits_updates ); -+ VG_(message)(Vg_DebugMsg, -+ " memcheck: max shadow mem size: %ldk, %ldM\n", -+ max_shmem_szB / 1024, max_shmem_szB / (1024 * 1024)); -+ -+ if (MC_(clo_mc_level) >= 3) { -+ VG_(message)(Vg_DebugMsg, -+ " ocacheL1: %'12lu refs %'12lu misses (%'lu lossage)\n", -+ stats_ocacheL1_find, -+ stats_ocacheL1_misses, -+ stats_ocacheL1_lossage ); -+ VG_(message)(Vg_DebugMsg, -+ " ocacheL1: %'12lu at 0 %'12lu at 1\n", -+ stats_ocacheL1_find - stats_ocacheL1_misses -+ - stats_ocacheL1_found_at_1 -+ - stats_ocacheL1_found_at_N, -+ stats_ocacheL1_found_at_1 ); -+ VG_(message)(Vg_DebugMsg, -+ " ocacheL1: %'12lu at 2+ %'12lu move-fwds\n", -+ stats_ocacheL1_found_at_N, -+ stats_ocacheL1_movefwds ); -+ VG_(message)(Vg_DebugMsg, -+ " ocacheL1: %'12lu sizeB %'12u useful\n", -+ (UWord)sizeof(OCache), -+ 4 * OC_W32S_PER_LINE * OC_LINES_PER_SET * OC_N_SETS ); -+ VG_(message)(Vg_DebugMsg, -+ " ocacheL2: %'12lu refs %'12lu misses\n", -+ stats__ocacheL2_refs, -+ stats__ocacheL2_misses ); -+ VG_(message)(Vg_DebugMsg, -+ " ocacheL2: %'9lu max nodes %'9lu curr nodes\n", -+ stats__ocacheL2_n_nodes_max, -+ stats__ocacheL2_n_nodes ); -+ VG_(message)(Vg_DebugMsg, -+ " niacache: %'12lu refs %'12lu misses\n", -+ stats__nia_cache_queries, stats__nia_cache_misses); -+ } else { -+ tl_assert(ocacheL1 == NULL); -+ tl_assert(ocacheL2 == NULL); -+ } -+} -+ -+ - static void mc_fini ( Int exitcode ) - { - MC_(print_malloc_stats)(); -@@ -6574,98 +6783,46 @@ - "uninitialised values come from\n"); - } - -+ /* Print a warning if any client-request generated ignore-ranges -+ still exist. It would be reasonable to expect that a properly -+ written program would remove any such ranges before exiting, and -+ since they are a bit on the dangerous side, let's comment. By -+ contrast ranges which are specified on the command line normally -+ pertain to hardware mapped into the address space, and so we -+ can't expect the client to have got rid of them. */ -+ if (gIgnoredAddressRanges) { -+ Word i, nBad = 0; -+ for (i = 0; i < VG_(sizeRangeMap)(gIgnoredAddressRanges); i++) { -+ UWord val = IAR_INVALID; -+ UWord key_min = ~(UWord)0; -+ UWord key_max = (UWord)0; -+ VG_(indexRangeMap)( &key_min, &key_max, &val, -+ gIgnoredAddressRanges, i ); -+ if (val != IAR_ClientReq) -+ continue; -+ /* Print the offending range. Also, if it is the first, -+ print a banner before it. */ -+ nBad++; -+ if (nBad == 1) { -+ VG_(umsg)( -+ "WARNING: exiting program has the following client-requested\n" -+ "WARNING: address error disablement range(s) still in force,\n" -+ "WARNING: " -+ "possibly as a result of some mistake in the use of the\n" -+ "WARNING: " -+ "VALGRIND_{DISABLE,ENABLE}_ERROR_REPORTING_IN_RANGE macros.\n" -+ ); -+ } -+ VG_(umsg)(" [%ld] 0x%016llx-0x%016llx %s\n", -+ i, (ULong)key_min, (ULong)key_max, showIARKind(val)); -+ } -+ } -+ - done_prof_mem(); - -- if (VG_(clo_stats)) { -- SizeT max_secVBit_szB, max_SMs_szB, max_shmem_szB; -- -- VG_(message)(Vg_DebugMsg, -- " memcheck: sanity checks: %d cheap, %d expensive\n", -- n_sanity_cheap, n_sanity_expensive ); -- VG_(message)(Vg_DebugMsg, -- " memcheck: auxmaps: %lld auxmap entries (%lldk, %lldM) in use\n", -- n_auxmap_L2_nodes, -- n_auxmap_L2_nodes * 64, -- n_auxmap_L2_nodes / 16 ); -- VG_(message)(Vg_DebugMsg, -- " memcheck: auxmaps_L1: %lld searches, %lld cmps, ratio %lld:10\n", -- n_auxmap_L1_searches, n_auxmap_L1_cmps, -- (10ULL * n_auxmap_L1_cmps) -- / (n_auxmap_L1_searches ? n_auxmap_L1_searches : 1) -- ); -- VG_(message)(Vg_DebugMsg, -- " memcheck: auxmaps_L2: %lld searches, %lld nodes\n", -- n_auxmap_L2_searches, n_auxmap_L2_nodes -- ); -+ if (VG_(clo_stats)) -+ mc_print_stats(); - -- print_SM_info("n_issued ", n_issued_SMs); -- print_SM_info("n_deissued ", n_deissued_SMs); -- print_SM_info("max_noaccess ", max_noaccess_SMs); -- print_SM_info("max_undefined", max_undefined_SMs); -- print_SM_info("max_defined ", max_defined_SMs); -- print_SM_info("max_non_DSM ", max_non_DSM_SMs); -- -- // Three DSMs, plus the non-DSM ones -- max_SMs_szB = (3 + max_non_DSM_SMs) * sizeof(SecMap); -- // The 3*sizeof(Word) bytes is the AVL node metadata size. -- // The VG_ROUNDUP is because the OSet pool allocator will/must align -- // the elements on pointer size. -- // Note that the pool allocator has some additional small overhead -- // which is not counted in the below. -- // Hardwiring this logic sucks, but I don't see how else to do it. -- max_secVBit_szB = max_secVBit_nodes * -- (3*sizeof(Word) + VG_ROUNDUP(sizeof(SecVBitNode), sizeof(void*))); -- max_shmem_szB = sizeof(primary_map) + max_SMs_szB + max_secVBit_szB; -- -- VG_(message)(Vg_DebugMsg, -- " memcheck: max sec V bit nodes: %d (%ldk, %ldM)\n", -- max_secVBit_nodes, max_secVBit_szB / 1024, -- max_secVBit_szB / (1024 * 1024)); -- VG_(message)(Vg_DebugMsg, -- " memcheck: set_sec_vbits8 calls: %llu (new: %llu, updates: %llu)\n", -- sec_vbits_new_nodes + sec_vbits_updates, -- sec_vbits_new_nodes, sec_vbits_updates ); -- VG_(message)(Vg_DebugMsg, -- " memcheck: max shadow mem size: %ldk, %ldM\n", -- max_shmem_szB / 1024, max_shmem_szB / (1024 * 1024)); -- -- if (MC_(clo_mc_level) >= 3) { -- VG_(message)(Vg_DebugMsg, -- " ocacheL1: %'12lu refs %'12lu misses (%'lu lossage)\n", -- stats_ocacheL1_find, -- stats_ocacheL1_misses, -- stats_ocacheL1_lossage ); -- VG_(message)(Vg_DebugMsg, -- " ocacheL1: %'12lu at 0 %'12lu at 1\n", -- stats_ocacheL1_find - stats_ocacheL1_misses -- - stats_ocacheL1_found_at_1 -- - stats_ocacheL1_found_at_N, -- stats_ocacheL1_found_at_1 ); -- VG_(message)(Vg_DebugMsg, -- " ocacheL1: %'12lu at 2+ %'12lu move-fwds\n", -- stats_ocacheL1_found_at_N, -- stats_ocacheL1_movefwds ); -- VG_(message)(Vg_DebugMsg, -- " ocacheL1: %'12lu sizeB %'12u useful\n", -- (UWord)sizeof(OCache), -- 4 * OC_W32S_PER_LINE * OC_LINES_PER_SET * OC_N_SETS ); -- VG_(message)(Vg_DebugMsg, -- " ocacheL2: %'12lu refs %'12lu misses\n", -- stats__ocacheL2_refs, -- stats__ocacheL2_misses ); -- VG_(message)(Vg_DebugMsg, -- " ocacheL2: %'9lu max nodes %'9lu curr nodes\n", -- stats__ocacheL2_n_nodes_max, -- stats__ocacheL2_n_nodes ); -- VG_(message)(Vg_DebugMsg, -- " niacache: %'12lu refs %'12lu misses\n", -- stats__nia_cache_queries, stats__nia_cache_misses); -- } else { -- tl_assert(ocacheL1 == NULL); -- tl_assert(ocacheL2 == NULL); -- } -- } -- - if (0) { - VG_(message)(Vg_DebugMsg, - "------ Valgrind's client block stats follow ---------------\n" ); -@@ -6726,6 +6883,8 @@ - VG_(needs_client_requests) (mc_handle_client_request); - VG_(needs_sanity_checks) (mc_cheap_sanity_check, - mc_expensive_sanity_check); -+ VG_(needs_print_stats) (mc_print_stats); -+ VG_(needs_info_location) (MC_(pp_describe_addr)); - VG_(needs_malloc_replacement) (MC_(malloc), - MC_(__builtin_new), - MC_(__builtin_vec_new), -Index: memcheck/mc_replace_strmem.c -=================================================================== ---- memcheck/mc_replace_strmem.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/mc_replace_strmem.c (.../trunk) (revision 13981) -@@ -9,7 +9,7 @@ - This file is part of MemCheck, a heavyweight Valgrind tool for - detecting memory errors. - -- Copyright (C) 2000-2013 Julian Seward -+ Copyright (C) 2000-2013 Julian Seward - jseward@acm.org - - This program is free software; you can redistribute it and/or -@@ -40,1769 +40,9 @@ - #include "mc_include.h" - #include "memcheck.h" - --/* --------------------------------------------------------------------- -- We have our own versions of these functions for two reasons: -- (a) it allows us to do overlap checking -- (b) some of the normal versions are hyper-optimised, which fools -- Memcheck and cause spurious value warnings. Our versions are -- simpler. -- -- Note that overenthusiastic use of PLT bypassing by the glibc people also -- means that we need to patch multiple versions of some of the functions to -- our own implementations. -- -- THEY RUN ON THE SIMD CPU! -- ------------------------------------------------------------------ */ -- --/* Assignment of behavioural equivalence class tags: 2NNNP is intended -- to be reserved for Memcheck. Current usage: -- -- 20010 STRRCHR -- 20020 STRCHR -- 20030 STRCAT -- 20040 STRNCAT -- 20050 STRLCAT -- 20060 STRNLEN -- 20070 STRLEN -- 20080 STRCPY -- 20090 STRNCPY -- 20100 STRLCPY -- 20110 STRNCMP -- 20120 STRCASECMP -- 20130 STRNCASECMP -- 20140 STRCASECMP_L -- 20150 STRNCASECMP_L -- 20160 STRCMP -- 20170 MEMCHR -- -- 20180 MEMCPY if there's a conflict between memcpy and -- 20181 MEMMOVE memmove, prefer memmove -- -- 20190 MEMCMP -- 20200 STPCPY -- 20210 MEMSET -- 2022P unused (was previously MEMMOVE) -- 20230 BCOPY -- 20240 GLIBC25___MEMMOVE_CHK -- 20250 GLIBC232_STRCHRNUL -- 20260 GLIBC232_RAWMEMCHR -- 20270 GLIBC25___STRCPY_CHK -- 20280 GLIBC25___STPCPY_CHK -- 20290 GLIBC25_MEMPCPY -- 20300 GLIBC26___MEMCPY_CHK -- 20310 STRSTR -- 20320 STRPBRK -- 20330 STRCSPN -- 20340 STRSPN -- 20350 STRCASESTR -- 20360 MEMRCHR -- 20370 WCSLEN -- 20380 WCSCMP -- 20390 WCSCPY -- 20400 WCSCHR -- 20410 WCSRCHR -- 20420 STPNCPY --*/ -- -- --/* Figure out if [dst .. dst+dstlen-1] overlaps with -- [src .. src+srclen-1]. -- We assume that the address ranges do not wrap around -- (which is safe since on Linux addresses >= 0xC0000000 -- are not accessible and the program will segfault in this -- circumstance, presumably). --*/ --static inline --Bool is_overlap ( void* dst, const void* src, SizeT dstlen, SizeT srclen ) --{ -- Addr loS, hiS, loD, hiD; -- -- if (dstlen == 0 || srclen == 0) -- return False; -- -- loS = (Addr)src; -- loD = (Addr)dst; -- hiS = loS + srclen - 1; -- hiD = loD + dstlen - 1; -- -- /* So figure out if [loS .. hiS] overlaps with [loD .. hiD]. */ -- if (loS < loD) { -- return !(hiS < loD); -- } -- else if (loD < loS) { -- return !(hiD < loS); -- } -- else { -- /* They start at same place. Since we know neither of them has -- zero length, they must overlap. */ -- return True; -- } --} -- -- --/* Call here to exit if we can't continue. On Android we can't call -- _exit for some reason, so we have to blunt-instrument it. */ --__attribute__ ((__noreturn__)) --static inline void my_exit ( int x ) --{ --# if defined(VGPV_arm_linux_android) -- __asm__ __volatile__(".word 0xFFFFFFFF"); -- while (1) {} --# elif defined(VGPV_x86_linux_android) -- __asm__ __volatile__("ud2"); -- while (1) {} --# else -- extern __attribute__ ((__noreturn__)) void _exit(int status); -- _exit(x); --# endif --} -- -- --// This is a macro rather than a function because we don't want to have an --// extra function in the stack trace. - #define RECORD_OVERLAP_ERROR(s, src, dst, len) \ - VALGRIND_DO_CLIENT_REQUEST_STMT( \ - _VG_USERREQ__MEMCHECK_RECORD_OVERLAP_ERROR, \ - s, src, dst, len, 0) - -- --/*---------------------- strrchr ----------------------*/ -- --#define STRRCHR(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20010,soname,fnname)( const char* s, int c ); \ -- char* VG_REPLACE_FUNCTION_EZU(20010,soname,fnname)( const char* s, int c ) \ -- { \ -- HChar ch = (HChar)c; \ -- const HChar* p = s; \ -- const HChar* last = NULL; \ -- while (True) { \ -- if (*p == ch) last = p; \ -- if (*p == 0) return (HChar *)last; \ -- p++; \ -- } \ -- } -- --// Apparently rindex() is the same thing as strrchr() --#if defined(VGO_linux) -- STRRCHR(VG_Z_LIBC_SONAME, strrchr) -- STRRCHR(VG_Z_LIBC_SONAME, rindex) -- STRRCHR(VG_Z_LIBC_SONAME, __GI_strrchr) -- STRRCHR(VG_Z_LD_LINUX_SO_2, rindex) --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -- STRRCHR(NONE, __dl_strrchr); /* in /system/bin/linker */ --#endif -- --#elif defined(VGO_darwin) -- //STRRCHR(VG_Z_LIBC_SONAME, strrchr) -- //STRRCHR(VG_Z_LIBC_SONAME, rindex) -- //STRRCHR(VG_Z_DYLD, strrchr) -- //STRRCHR(VG_Z_DYLD, rindex) -- STRRCHR(VG_Z_LIBC_SONAME, strrchr) -- --#endif -- -- --/*---------------------- strchr ----------------------*/ -- --#define STRCHR(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20020,soname,fnname) ( const char* s, int c ); \ -- char* VG_REPLACE_FUNCTION_EZU(20020,soname,fnname) ( const char* s, int c ) \ -- { \ -- HChar ch = (HChar)c ; \ -- const HChar* p = s; \ -- while (True) { \ -- if (*p == ch) return (HChar *)p; \ -- if (*p == 0) return NULL; \ -- p++; \ -- } \ -- } -- --// Apparently index() is the same thing as strchr() --#if defined(VGO_linux) -- STRCHR(VG_Z_LIBC_SONAME, strchr) -- STRCHR(VG_Z_LIBC_SONAME, index) -- STRCHR(VG_Z_LIBC_SONAME, __GI_strchr) --# if !defined(VGP_x86_linux) -- STRCHR(VG_Z_LD_LINUX_SO_2, strchr) -- STRCHR(VG_Z_LD_LINUX_SO_2, index) -- STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, strchr) -- STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, index) --# endif -- --#elif defined(VGO_darwin) -- //STRCHR(VG_Z_LIBC_SONAME, strchr) -- //STRCHR(VG_Z_LIBC_SONAME, index) -- //STRCHR(VG_Z_DYLD, strchr) -- //STRCHR(VG_Z_DYLD, index) -- STRCHR(VG_Z_LIBC_SONAME, strchr) -- --#endif -- -- --/*---------------------- strcat ----------------------*/ -- --#define STRCAT(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20030,soname,fnname) \ -- ( char* dst, const char* src ); \ -- char* VG_REPLACE_FUNCTION_EZU(20030,soname,fnname) \ -- ( char* dst, const char* src ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_orig = dst; \ -- while (*dst) dst++; \ -- while (*src) *dst++ = *src++; \ -- *dst = 0; \ -- \ -- /* This is a bit redundant, I think; any overlap and the strcat will */ \ -- /* go forever... or until a seg fault occurs. */ \ -- if (is_overlap(dst_orig, \ -- src_orig, \ -- (Addr)dst-(Addr)dst_orig+1, \ -- (Addr)src-(Addr)src_orig+1)) \ -- RECORD_OVERLAP_ERROR("strcat", dst_orig, src_orig, 0); \ -- \ -- return dst_orig; \ -- } -- --#if defined(VGO_linux) -- STRCAT(VG_Z_LIBC_SONAME, strcat) -- STRCAT(VG_Z_LIBC_SONAME, __GI_strcat) -- --#elif defined(VGO_darwin) -- //STRCAT(VG_Z_LIBC_SONAME, strcat) -- --#endif -- -- --/*---------------------- strncat ----------------------*/ -- --#define STRNCAT(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20040,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ); \ -- char* VG_REPLACE_FUNCTION_EZU(20040,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_orig = dst; \ -- SizeT m = 0; \ -- \ -- while (*dst) dst++; \ -- while (m < n && *src) { m++; *dst++ = *src++; } /* concat <= n chars */ \ -- *dst = 0; /* always add null */ \ -- \ -- /* This checks for overlap after copying, unavoidable without */ \ -- /* pre-counting lengths... should be ok */ \ -- if (is_overlap(dst_orig, \ -- src_orig, \ -- (Addr)dst-(Addr)dst_orig+1, \ -- (Addr)src-(Addr)src_orig+1)) \ -- RECORD_OVERLAP_ERROR("strncat", dst_orig, src_orig, n); \ -- \ -- return dst_orig; \ -- } -- --#if defined(VGO_linux) -- STRNCAT(VG_Z_LIBC_SONAME, strncat) -- --#elif defined(VGO_darwin) -- //STRNCAT(VG_Z_LIBC_SONAME, strncat) -- //STRNCAT(VG_Z_DYLD, strncat) -- --#endif -- -- --/*---------------------- strlcat ----------------------*/ -- --/* Append src to dst. n is the size of dst's buffer. dst is guaranteed -- to be nul-terminated after the copy, unless n <= strlen(dst_orig). -- Returns min(n, strlen(dst_orig)) + strlen(src_orig). -- Truncation occurred if retval >= n. --*/ --#define STRLCAT(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_EZU(20050,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ); \ -- SizeT VG_REPLACE_FUNCTION_EZU(20050,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_orig = dst; \ -- SizeT m = 0; \ -- \ -- while (m < n && *dst) { m++; dst++; } \ -- if (m < n) { \ -- /* Fill as far as dst_orig[n-2], then nul-terminate. */ \ -- while (m < n-1 && *src) { m++; *dst++ = *src++; } \ -- *dst = 0; \ -- } else { \ -- /* No space to copy anything to dst. m == n */ \ -- } \ -- /* Finish counting min(n, strlen(dst_orig)) + strlen(src_orig) */ \ -- while (*src) { m++; src++; } \ -- /* This checks for overlap after copying, unavoidable without */ \ -- /* pre-counting lengths... should be ok */ \ -- if (is_overlap(dst_orig, \ -- src_orig, \ -- (Addr)dst-(Addr)dst_orig+1, \ -- (Addr)src-(Addr)src_orig+1)) \ -- RECORD_OVERLAP_ERROR("strlcat", dst_orig, src_orig, n); \ -- \ -- return m; \ -- } -- --#if defined(VGO_linux) -- --#elif defined(VGO_darwin) -- //STRLCAT(VG_Z_LIBC_SONAME, strlcat) -- //STRLCAT(VG_Z_DYLD, strlcat) -- STRLCAT(VG_Z_LIBC_SONAME, strlcat) -- --#endif -- -- --/*---------------------- strnlen ----------------------*/ -- --#define STRNLEN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_EZU(20060,soname,fnname) \ -- ( const char* str, SizeT n ); \ -- SizeT VG_REPLACE_FUNCTION_EZU(20060,soname,fnname) \ -- ( const char* str, SizeT n ) \ -- { \ -- SizeT i = 0; \ -- while (i < n && str[i] != 0) i++; \ -- return i; \ -- } -- --#if defined(VGO_linux) -- STRNLEN(VG_Z_LIBC_SONAME, strnlen) -- STRNLEN(VG_Z_LIBC_SONAME, __GI_strnlen) -- --#elif defined(VGO_darwin) -- //STRNLEN(VG_Z_LIBC_SONAME, strnlen) -- --#endif -- -- --/*---------------------- strlen ----------------------*/ -- --// Note that this replacement often doesn't get used because gcc inlines --// calls to strlen() with its own built-in version. This can be very --// confusing if you aren't expecting it. Other small functions in --// this file may also be inline by gcc. -- --#define STRLEN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_EZU(20070,soname,fnname) \ -- ( const char* str ); \ -- SizeT VG_REPLACE_FUNCTION_EZU(20070,soname,fnname) \ -- ( const char* str ) \ -- { \ -- SizeT i = 0; \ -- while (str[i] != 0) i++; \ -- return i; \ -- } -- --#if defined(VGO_linux) -- STRLEN(VG_Z_LIBC_SONAME, strlen) -- STRLEN(VG_Z_LIBC_SONAME, __GI_strlen) --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -- STRLEN(NONE, __dl_strlen); /* in /system/bin/linker */ --# endif -- --#elif defined(VGO_darwin) -- //STRLEN(VG_Z_LIBC_SONAME, strlen) -- STRLEN(VG_Z_LIBC_SONAME, strlen) -- --#endif -- -- --/*---------------------- strcpy ----------------------*/ -- --#define STRCPY(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20080,soname,fnname) \ -- ( char* dst, const char* src ); \ -- char* VG_REPLACE_FUNCTION_EZU(20080,soname,fnname) \ -- ( char* dst, const char* src ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_orig = dst; \ -- \ -- while (*src) *dst++ = *src++; \ -- *dst = 0; \ -- \ -- /* This checks for overlap after copying, unavoidable without */ \ -- /* pre-counting length... should be ok */ \ -- if (is_overlap(dst_orig, \ -- src_orig, \ -- (Addr)dst-(Addr)dst_orig+1, \ -- (Addr)src-(Addr)src_orig+1)) \ -- RECORD_OVERLAP_ERROR("strcpy", dst_orig, src_orig, 0); \ -- \ -- return dst_orig; \ -- } -- --#if defined(VGO_linux) -- STRCPY(VG_Z_LIBC_SONAME, strcpy) -- STRCPY(VG_Z_LIBC_SONAME, __GI_strcpy) -- --#elif defined(VGO_darwin) -- //STRCPY(VG_Z_LIBC_SONAME, strcpy) -- //STRCPY(VG_Z_DYLD, strcpy) -- STRCPY(VG_Z_LIBC_SONAME, strcpy) -- --#endif -- -- --/*---------------------- strncpy ----------------------*/ -- --#define STRNCPY(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20090,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ); \ -- char* VG_REPLACE_FUNCTION_EZU(20090,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_orig = dst; \ -- SizeT m = 0; \ -- \ -- while (m < n && *src) { m++; *dst++ = *src++; } \ -- /* Check for overlap after copying; all n bytes of dst are relevant, */ \ -- /* but only m+1 bytes of src if terminator was found */ \ -- if (is_overlap(dst_orig, src_orig, n, (m < n) ? m+1 : n)) \ -- RECORD_OVERLAP_ERROR("strncpy", dst, src, n); \ -- while (m++ < n) *dst++ = 0; /* must pad remainder with nulls */ \ -- \ -- return dst_orig; \ -- } -- --#if defined(VGO_linux) -- STRNCPY(VG_Z_LIBC_SONAME, strncpy) -- STRNCPY(VG_Z_LIBC_SONAME, __GI_strncpy) -- --#elif defined(VGO_darwin) -- //STRNCPY(VG_Z_LIBC_SONAME, strncpy) -- //STRNCPY(VG_Z_DYLD, strncpy) -- STRNCPY(VG_Z_LIBC_SONAME, strncpy) -- --#endif -- -- --/*---------------------- strlcpy ----------------------*/ -- --/* Copy up to n-1 bytes from src to dst. Then nul-terminate dst if n > 0. -- Returns strlen(src). Does not zero-fill the remainder of dst. */ --#define STRLCPY(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_EZU(20100,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ); \ -- SizeT VG_REPLACE_FUNCTION_EZU(20100,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_orig = dst; \ -- SizeT m = 0; \ -- \ -- while (m < n-1 && *src) { m++; *dst++ = *src++; } \ -- /* m non-nul bytes have now been copied, and m <= n-1. */ \ -- /* Check for overlap after copying; all n bytes of dst are relevant, */ \ -- /* but only m+1 bytes of src if terminator was found */ \ -- if (is_overlap(dst_orig, src_orig, n, (m < n) ? m+1 : n)) \ -- RECORD_OVERLAP_ERROR("strlcpy", dst, src, n); \ -- /* Nul-terminate dst. */ \ -- if (n > 0) *dst = 0; \ -- /* Finish counting strlen(src). */ \ -- while (*src) src++; \ -- return src - src_orig; \ -- } -- --#if defined(VGO_linux) -- --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -- STRLCPY(VG_Z_LIBC_SONAME, strlcpy); --#endif -- --#elif defined(VGO_darwin) -- //STRLCPY(VG_Z_LIBC_SONAME, strlcpy) -- //STRLCPY(VG_Z_DYLD, strlcpy) -- STRLCPY(VG_Z_LIBC_SONAME, strlcpy) -- --#endif -- -- --/*---------------------- strncmp ----------------------*/ -- --#define STRNCMP(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20110,soname,fnname) \ -- ( const char* s1, const char* s2, SizeT nmax ); \ -- int VG_REPLACE_FUNCTION_EZU(20110,soname,fnname) \ -- ( const char* s1, const char* s2, SizeT nmax ) \ -- { \ -- SizeT n = 0; \ -- while (True) { \ -- if (n >= nmax) return 0; \ -- if (*s1 == 0 && *s2 == 0) return 0; \ -- if (*s1 == 0) return -1; \ -- if (*s2 == 0) return 1; \ -- \ -- if (*(const UChar*)s1 < *(const UChar*)s2) return -1; \ -- if (*(const UChar*)s1 > *(const UChar*)s2) return 1; \ -- \ -- s1++; s2++; n++; \ -- } \ -- } -- --#if defined(VGO_linux) -- STRNCMP(VG_Z_LIBC_SONAME, strncmp) -- STRNCMP(VG_Z_LIBC_SONAME, __GI_strncmp) -- --#elif defined(VGO_darwin) -- //STRNCMP(VG_Z_LIBC_SONAME, strncmp) -- //STRNCMP(VG_Z_DYLD, strncmp) -- STRNCMP(VG_Z_LIBC_SONAME, strncmp) -- --#endif -- -- --/*---------------------- strcasecmp ----------------------*/ -- --#define STRCASECMP(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20120,soname,fnname) \ -- ( const char* s1, const char* s2 ); \ -- int VG_REPLACE_FUNCTION_EZU(20120,soname,fnname) \ -- ( const char* s1, const char* s2 ) \ -- { \ -- extern int tolower(int); \ -- register UChar c1; \ -- register UChar c2; \ -- while (True) { \ -- c1 = tolower(*(const UChar *)s1); \ -- c2 = tolower(*(const UChar *)s2); \ -- if (c1 != c2) break; \ -- if (c1 == 0) break; \ -- s1++; s2++; \ -- } \ -- if ((UChar)c1 < (UChar)c2) return -1; \ -- if ((UChar)c1 > (UChar)c2) return 1; \ -- return 0; \ -- } -- --#if defined(VGO_linux) --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -- STRCASECMP(VG_Z_LIBC_SONAME, strcasecmp) -- STRCASECMP(VG_Z_LIBC_SONAME, __GI_strcasecmp) --# endif -- --#elif defined(VGO_darwin) -- //STRCASECMP(VG_Z_LIBC_SONAME, strcasecmp) -- --#endif -- -- --/*---------------------- strncasecmp ----------------------*/ -- --#define STRNCASECMP(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20130,soname,fnname) \ -- ( const char* s1, const char* s2, SizeT nmax ); \ -- int VG_REPLACE_FUNCTION_EZU(20130,soname,fnname) \ -- ( const char* s1, const char* s2, SizeT nmax ) \ -- { \ -- extern int tolower(int); \ -- SizeT n = 0; \ -- while (True) { \ -- if (n >= nmax) return 0; \ -- if (*s1 == 0 && *s2 == 0) return 0; \ -- if (*s1 == 0) return -1; \ -- if (*s2 == 0) return 1; \ -- \ -- if (tolower(*(const UChar *)s1) \ -- < tolower(*(const UChar*)s2)) return -1; \ -- if (tolower(*(const UChar *)s1) \ -- > tolower(*(const UChar *)s2)) return 1; \ -- \ -- s1++; s2++; n++; \ -- } \ -- } -- --#if defined(VGO_linux) --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -- STRNCASECMP(VG_Z_LIBC_SONAME, strncasecmp) -- STRNCASECMP(VG_Z_LIBC_SONAME, __GI_strncasecmp) --# endif -- --#elif defined(VGO_darwin) -- //STRNCASECMP(VG_Z_LIBC_SONAME, strncasecmp) -- //STRNCASECMP(VG_Z_DYLD, strncasecmp) -- --#endif -- -- --/*---------------------- strcasecmp_l ----------------------*/ -- --#define STRCASECMP_L(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20140,soname,fnname) \ -- ( const char* s1, const char* s2, void* locale ); \ -- int VG_REPLACE_FUNCTION_EZU(20140,soname,fnname) \ -- ( const char* s1, const char* s2, void* locale ) \ -- { \ -- extern int tolower_l(int, void*) __attribute__((weak)); \ -- register UChar c1; \ -- register UChar c2; \ -- while (True) { \ -- c1 = tolower_l(*(const UChar *)s1, locale); \ -- c2 = tolower_l(*(const UChar *)s2, locale); \ -- if (c1 != c2) break; \ -- if (c1 == 0) break; \ -- s1++; s2++; \ -- } \ -- if ((UChar)c1 < (UChar)c2) return -1; \ -- if ((UChar)c1 > (UChar)c2) return 1; \ -- return 0; \ -- } -- --#if defined(VGO_linux) -- STRCASECMP_L(VG_Z_LIBC_SONAME, strcasecmp_l) -- STRCASECMP_L(VG_Z_LIBC_SONAME, __GI_strcasecmp_l) -- STRCASECMP_L(VG_Z_LIBC_SONAME, __GI___strcasecmp_l) -- --#elif defined(VGO_darwin) -- //STRCASECMP_L(VG_Z_LIBC_SONAME, strcasecmp_l) -- --#endif -- -- --/*---------------------- strncasecmp_l ----------------------*/ -- --#define STRNCASECMP_L(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20150,soname,fnname) \ -- ( const char* s1, const char* s2, SizeT nmax, void* locale ); \ -- int VG_REPLACE_FUNCTION_EZU(20150,soname,fnname) \ -- ( const char* s1, const char* s2, SizeT nmax, void* locale ) \ -- { \ -- extern int tolower_l(int, void*) __attribute__((weak)); \ -- SizeT n = 0; \ -- while (True) { \ -- if (n >= nmax) return 0; \ -- if (*s1 == 0 && *s2 == 0) return 0; \ -- if (*s1 == 0) return -1; \ -- if (*s2 == 0) return 1; \ -- \ -- if (tolower_l(*(const UChar *)s1, locale) \ -- < tolower_l(*(const UChar *)s2, locale)) return -1; \ -- if (tolower_l(*(const UChar *)s1, locale) \ -- > tolower_l(*(const UChar *)s2, locale)) return 1; \ -- \ -- s1++; s2++; n++; \ -- } \ -- } -- --#if defined(VGO_linux) -- STRNCASECMP_L(VG_Z_LIBC_SONAME, strncasecmp_l) -- STRNCASECMP_L(VG_Z_LIBC_SONAME, __GI_strncasecmp_l) -- STRNCASECMP_L(VG_Z_LIBC_SONAME, __GI___strncasecmp_l) -- --#elif defined(VGO_darwin) -- //STRNCASECMP_L(VG_Z_LIBC_SONAME, strncasecmp_l) -- //STRNCASECMP_L(VG_Z_DYLD, strncasecmp_l) -- --#endif -- -- --/*---------------------- strcmp ----------------------*/ -- --#define STRCMP(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20160,soname,fnname) \ -- ( const char* s1, const char* s2 ); \ -- int VG_REPLACE_FUNCTION_EZU(20160,soname,fnname) \ -- ( const char* s1, const char* s2 ) \ -- { \ -- register UChar c1; \ -- register UChar c2; \ -- while (True) { \ -- c1 = *(const UChar *)s1; \ -- c2 = *(const UChar *)s2; \ -- if (c1 != c2) break; \ -- if (c1 == 0) break; \ -- s1++; s2++; \ -- } \ -- if ((UChar)c1 < (UChar)c2) return -1; \ -- if ((UChar)c1 > (UChar)c2) return 1; \ -- return 0; \ -- } -- --#if defined(VGO_linux) -- STRCMP(VG_Z_LIBC_SONAME, strcmp) -- STRCMP(VG_Z_LIBC_SONAME, __GI_strcmp) -- STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp) -- STRCMP(VG_Z_LD64_SO_1, strcmp) --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -- STRCMP(NONE, __dl_strcmp); /* in /system/bin/linker */ --# endif -- --#elif defined(VGO_darwin) -- //STRCMP(VG_Z_LIBC_SONAME, strcmp) -- STRCMP(VG_Z_LIBC_SONAME, strcmp) -- --#endif -- -- --/*---------------------- memchr ----------------------*/ -- --#define MEMCHR(soname, fnname) \ -- void* VG_REPLACE_FUNCTION_EZU(20170,soname,fnname) \ -- (const void *s, int c, SizeT n); \ -- void* VG_REPLACE_FUNCTION_EZU(20170,soname,fnname) \ -- (const void *s, int c, SizeT n) \ -- { \ -- SizeT i; \ -- UChar c0 = (UChar)c; \ -- UChar* p = (UChar*)s; \ -- for (i = 0; i < n; i++) \ -- if (p[i] == c0) return (void*)(&p[i]); \ -- return NULL; \ -- } -- --#if defined(VGO_linux) -- MEMCHR(VG_Z_LIBC_SONAME, memchr) -- --#elif defined(VGO_darwin) -- //MEMCHR(VG_Z_LIBC_SONAME, memchr) -- //MEMCHR(VG_Z_DYLD, memchr) -- --#endif -- -- --/*---------------------- memrchr ----------------------*/ -- --#define MEMRCHR(soname, fnname) \ -- void* VG_REPLACE_FUNCTION_EZU(20360,soname,fnname) \ -- (const void *s, int c, SizeT n); \ -- void* VG_REPLACE_FUNCTION_EZU(20360,soname,fnname) \ -- (const void *s, int c, SizeT n) \ -- { \ -- SizeT i; \ -- UChar c0 = (UChar)c; \ -- UChar* p = (UChar*)s; \ -- for (i = 0; i < n; i++) \ -- if (p[n-1-i] == c0) return (void*)(&p[n-1-i]); \ -- return NULL; \ -- } -- --#if defined(VGO_linux) -- MEMRCHR(VG_Z_LIBC_SONAME, memrchr) -- --#elif defined(VGO_darwin) -- //MEMRCHR(VG_Z_LIBC_SONAME, memrchr) -- //MEMRCHR(VG_Z_DYLD, memrchr) -- --#endif -- -- --/*---------------------- memcpy ----------------------*/ -- --#define MEMMOVE_OR_MEMCPY(becTag, soname, fnname, do_ol_check) \ -- void* VG_REPLACE_FUNCTION_EZZ(becTag,soname,fnname) \ -- ( void *dst, const void *src, SizeT len ); \ -- void* VG_REPLACE_FUNCTION_EZZ(becTag,soname,fnname) \ -- ( void *dst, const void *src, SizeT len ) \ -- { \ -- if (do_ol_check && is_overlap(dst, src, len, len)) \ -- RECORD_OVERLAP_ERROR("memcpy", dst, src, len); \ -- \ -- const Addr WS = sizeof(UWord); /* 8 or 4 */ \ -- const Addr WM = WS - 1; /* 7 or 3 */ \ -- \ -- if (len > 0) { \ -- if (dst < src) { \ -- \ -- /* Copying backwards. */ \ -- SizeT n = len; \ -- Addr d = (Addr)dst; \ -- Addr s = (Addr)src; \ -- \ -- if (((s^d) & WM) == 0) { \ -- /* s and d have same UWord alignment. */ \ -- /* Pull up to a UWord boundary. */ \ -- while ((s & WM) != 0 && n >= 1) \ -- { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ -- /* Copy UWords. */ \ -- while (n >= WS) \ -- { *(UWord*)d = *(UWord*)s; s += WS; d += WS; n -= WS; } \ -- if (n == 0) \ -- return dst; \ -- } \ -- if (((s|d) & 1) == 0) { \ -- /* Both are 16-aligned; copy what we can thusly. */ \ -- while (n >= 2) \ -- { *(UShort*)d = *(UShort*)s; s += 2; d += 2; n -= 2; } \ -- } \ -- /* Copy leftovers, or everything if misaligned. */ \ -- while (n >= 1) \ -- { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ -- \ -- } else if (dst > src) { \ -- \ -- SizeT n = len; \ -- Addr d = ((Addr)dst) + n; \ -- Addr s = ((Addr)src) + n; \ -- \ -- /* Copying forwards. */ \ -- if (((s^d) & WM) == 0) { \ -- /* s and d have same UWord alignment. */ \ -- /* Back down to a UWord boundary. */ \ -- while ((s & WM) != 0 && n >= 1) \ -- { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ -- /* Copy UWords. */ \ -- while (n >= WS) \ -- { s -= WS; d -= WS; *(UWord*)d = *(UWord*)s; n -= WS; } \ -- if (n == 0) \ -- return dst; \ -- } \ -- if (((s|d) & 1) == 0) { \ -- /* Both are 16-aligned; copy what we can thusly. */ \ -- while (n >= 2) \ -- { s -= 2; d -= 2; *(UShort*)d = *(UShort*)s; n -= 2; } \ -- } \ -- /* Copy leftovers, or everything if misaligned. */ \ -- while (n >= 1) \ -- { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ -- \ -- } \ -- } \ -- \ -- return dst; \ -- } -- --#define MEMMOVE(soname, fnname) \ -- MEMMOVE_OR_MEMCPY(20181, soname, fnname, 0) -- --#define MEMCPY(soname, fnname) \ -- MEMMOVE_OR_MEMCPY(20180, soname, fnname, 1) -- --#if defined(VGO_linux) -- /* For older memcpy we have to use memmove-like semantics and skip -- the overlap check; sigh; see #275284. */ -- MEMMOVE(VG_Z_LIBC_SONAME, memcpyZAGLIBCZu2Zd2Zd5) /* memcpy@GLIBC_2.2.5 */ -- MEMCPY(VG_Z_LIBC_SONAME, memcpyZAZAGLIBCZu2Zd14) /* memcpy@@GLIBC_2.14 */ -- MEMCPY(VG_Z_LIBC_SONAME, memcpy) /* fallback case */ -- MEMCPY(VG_Z_LD_SO_1, memcpy) /* ld.so.1 */ -- MEMCPY(VG_Z_LD64_SO_1, memcpy) /* ld64.so.1 */ -- /* icc9 blats these around all over the place. Not only in the main -- executable but various .so's. They are highly tuned and read -- memory beyond the source boundary (although work correctly and -- never go across page boundaries), so give errors when run -- natively, at least for misaligned source arg. Just intercepting -- in the exe only until we understand more about the problem. See -- http://bugs.kde.org/show_bug.cgi?id=139776 -- */ -- MEMCPY(NONE, ZuintelZufastZumemcpy) -- --#elif defined(VGO_darwin) --# if DARWIN_VERS <= DARWIN_10_6 -- MEMCPY(VG_Z_LIBC_SONAME, memcpy) --# endif -- MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse3x) /* memcpy$VARIANT$sse3x */ -- MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse42) /* memcpy$VARIANT$sse42 */ -- --#endif -- -- --/*---------------------- memcmp ----------------------*/ -- --#define MEMCMP(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20190,soname,fnname) \ -- ( const void *s1V, const void *s2V, SizeT n ); \ -- int VG_REPLACE_FUNCTION_EZU(20190,soname,fnname) \ -- ( const void *s1V, const void *s2V, SizeT n ) \ -- { \ -- int res; \ -- UChar a0; \ -- UChar b0; \ -- const UChar* s1 = s1V; \ -- const UChar* s2 = s2V; \ -- \ -- while (n != 0) { \ -- a0 = s1[0]; \ -- b0 = s2[0]; \ -- s1 += 1; \ -- s2 += 1; \ -- res = ((int)a0) - ((int)b0); \ -- if (res != 0) \ -- return res; \ -- n -= 1; \ -- } \ -- return 0; \ -- } -- --#if defined(VGO_linux) -- MEMCMP(VG_Z_LIBC_SONAME, memcmp) -- MEMCMP(VG_Z_LIBC_SONAME, bcmp) -- MEMCMP(VG_Z_LD_SO_1, bcmp) -- --#elif defined(VGO_darwin) -- //MEMCMP(VG_Z_LIBC_SONAME, memcmp) -- //MEMCMP(VG_Z_LIBC_SONAME, bcmp) -- //MEMCMP(VG_Z_DYLD, memcmp) -- //MEMCMP(VG_Z_DYLD, bcmp) -- --#endif -- -- --/*---------------------- stpcpy ----------------------*/ -- --/* Copy SRC to DEST, returning the address of the terminating '\0' in -- DEST. (minor variant of strcpy) */ --#define STPCPY(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20200,soname,fnname) \ -- ( char* dst, const char* src ); \ -- char* VG_REPLACE_FUNCTION_EZU(20200,soname,fnname) \ -- ( char* dst, const char* src ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_orig = dst; \ -- \ -- while (*src) *dst++ = *src++; \ -- *dst = 0; \ -- \ -- /* This checks for overlap after copying, unavoidable without */ \ -- /* pre-counting length... should be ok */ \ -- if (is_overlap(dst_orig, \ -- src_orig, \ -- (Addr)dst-(Addr)dst_orig+1, \ -- (Addr)src-(Addr)src_orig+1)) \ -- RECORD_OVERLAP_ERROR("stpcpy", dst_orig, src_orig, 0); \ -- \ -- return dst; \ -- } -- --#if defined(VGO_linux) -- STPCPY(VG_Z_LIBC_SONAME, stpcpy) -- STPCPY(VG_Z_LIBC_SONAME, __GI_stpcpy) -- STPCPY(VG_Z_LD_LINUX_SO_2, stpcpy) -- STPCPY(VG_Z_LD_LINUX_X86_64_SO_2, stpcpy) -- --#elif defined(VGO_darwin) -- //STPCPY(VG_Z_LIBC_SONAME, stpcpy) -- //STPCPY(VG_Z_DYLD, stpcpy) -- --#endif -- -- --/*---------------------- stpncpy ----------------------*/ -- --#define STPNCPY(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20420,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ); \ -- char* VG_REPLACE_FUNCTION_EZU(20420,soname,fnname) \ -- ( char* dst, const char* src, SizeT n ) \ -- { \ -- const HChar* src_orig = src; \ -- HChar* dst_str = dst; \ -- SizeT m = 0; \ -- \ -- while (m < n && *src) { m++; *dst++ = *src++; } \ -- /* Check for overlap after copying; all n bytes of dst are relevant, */ \ -- /* but only m+1 bytes of src if terminator was found */ \ -- if (is_overlap(dst_str, src_orig, n, (m < n) ? m+1 : n)) \ -- RECORD_OVERLAP_ERROR("stpncpy", dst, src, n); \ -- dst_str = dst; \ -- while (m++ < n) *dst++ = 0; /* must pad remainder with nulls */ \ -- \ -- return dst_str; \ -- } -- --#if defined(VGO_linux) -- STPNCPY(VG_Z_LIBC_SONAME, stpncpy) --#endif -- -- --/*---------------------- memset ----------------------*/ -- --/* Why are we bothering to intercept this? It seems entirely -- pointless. */ -- --#define MEMSET(soname, fnname) \ -- void* VG_REPLACE_FUNCTION_EZU(20210,soname,fnname) \ -- (void *s, Int c, SizeT n); \ -- void* VG_REPLACE_FUNCTION_EZU(20210,soname,fnname) \ -- (void *s, Int c, SizeT n) \ -- { \ -- if (sizeof(void*) == 8) { \ -- Addr a = (Addr)s; \ -- ULong c8 = (c & 0xFF); \ -- c8 = (c8 << 8) | c8; \ -- c8 = (c8 << 16) | c8; \ -- c8 = (c8 << 32) | c8; \ -- while ((a & 7) != 0 && n >= 1) \ -- { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -- while (n >= 8) \ -- { *(ULong*)a = c8; a += 8; n -= 8; } \ -- while (n >= 1) \ -- { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -- return s; \ -- } else { \ -- Addr a = (Addr)s; \ -- UInt c4 = (c & 0xFF); \ -- c4 = (c4 << 8) | c4; \ -- c4 = (c4 << 16) | c4; \ -- while ((a & 3) != 0 && n >= 1) \ -- { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -- while (n >= 4) \ -- { *(UInt*)a = c4; a += 4; n -= 4; } \ -- while (n >= 1) \ -- { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -- return s; \ -- } \ -- } -- --#if defined(VGO_linux) -- MEMSET(VG_Z_LIBC_SONAME, memset) -- --#elif defined(VGO_darwin) -- //MEMSET(VG_Z_LIBC_SONAME, memset) -- //MEMSET(VG_Z_DYLD, memset) -- MEMSET(VG_Z_LIBC_SONAME, memset) -- --#endif -- -- --/*---------------------- memmove ----------------------*/ -- --/* memmove -- use the MEMMOVE defn above. */ -- --#if defined(VGO_linux) -- MEMMOVE(VG_Z_LIBC_SONAME, memmove) -- MEMMOVE(VG_Z_LIBC_SONAME, __GI_memmove) -- --#elif defined(VGO_darwin) --# if DARWIN_VERS <= DARWIN_10_6 -- MEMMOVE(VG_Z_LIBC_SONAME, memmove) --# endif -- MEMMOVE(VG_Z_LIBC_SONAME, memmoveZDVARIANTZDsse3x) /* memmove$VARIANT$sse3x */ -- MEMMOVE(VG_Z_LIBC_SONAME, memmoveZDVARIANTZDsse42) /* memmove$VARIANT$sse42 */ -- --#endif -- -- --/*---------------------- bcopy ----------------------*/ -- --#define BCOPY(soname, fnname) \ -- void VG_REPLACE_FUNCTION_EZU(20230,soname,fnname) \ -- (const void *srcV, void *dstV, SizeT n); \ -- void VG_REPLACE_FUNCTION_EZU(20230,soname,fnname) \ -- (const void *srcV, void *dstV, SizeT n) \ -- { \ -- SizeT i; \ -- HChar* dst = dstV; \ -- const HChar* src = srcV; \ -- if (dst < src) { \ -- for (i = 0; i < n; i++) \ -- dst[i] = src[i]; \ -- } \ -- else \ -- if (dst > src) { \ -- for (i = 0; i < n; i++) \ -- dst[n-i-1] = src[n-i-1]; \ -- } \ -- } -- --#if defined(VGO_linux) -- BCOPY(VG_Z_LIBC_SONAME, bcopy) -- --#elif defined(VGO_darwin) -- //BCOPY(VG_Z_LIBC_SONAME, bcopy) -- //BCOPY(VG_Z_DYLD, bcopy) -- --#endif -- -- --/*-------------------- memmove_chk --------------------*/ -- --/* glibc 2.5 variant of memmove which checks the dest is big enough. -- There is no specific part of glibc that this is copied from. */ --#define GLIBC25___MEMMOVE_CHK(soname, fnname) \ -- void* VG_REPLACE_FUNCTION_EZU(20240,soname,fnname) \ -- (void *dstV, const void *srcV, SizeT n, SizeT destlen); \ -- void* VG_REPLACE_FUNCTION_EZU(20240,soname,fnname) \ -- (void *dstV, const void *srcV, SizeT n, SizeT destlen) \ -- { \ -- SizeT i; \ -- HChar* dst = dstV; \ -- const HChar* src = srcV; \ -- if (destlen < n) \ -- goto badness; \ -- if (dst < src) { \ -- for (i = 0; i < n; i++) \ -- dst[i] = src[i]; \ -- } \ -- else \ -- if (dst > src) { \ -- for (i = 0; i < n; i++) \ -- dst[n-i-1] = src[n-i-1]; \ -- } \ -- return dst; \ -- badness: \ -- VALGRIND_PRINTF_BACKTRACE( \ -- "*** memmove_chk: buffer overflow detected ***: " \ -- "program terminated\n"); \ -- my_exit(127); \ -- /*NOTREACHED*/ \ -- return NULL; \ -- } -- --#if defined(VGO_linux) -- GLIBC25___MEMMOVE_CHK(VG_Z_LIBC_SONAME, __memmove_chk) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*-------------------- strchrnul --------------------*/ -- --/* Find the first occurrence of C in S or the final NUL byte. */ --#define GLIBC232_STRCHRNUL(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20250,soname,fnname) \ -- (const char* s, int c_in); \ -- char* VG_REPLACE_FUNCTION_EZU(20250,soname,fnname) \ -- (const char* s, int c_in) \ -- { \ -- UChar c = (UChar) c_in; \ -- UChar* char_ptr = (UChar *)s; \ -- while (1) { \ -- if (*char_ptr == 0) return (HChar *)char_ptr; \ -- if (*char_ptr == c) return (HChar *)char_ptr; \ -- char_ptr++; \ -- } \ -- } -- --#if defined(VGO_linux) -- GLIBC232_STRCHRNUL(VG_Z_LIBC_SONAME, strchrnul) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- rawmemchr ----------------------*/ -- --/* Find the first occurrence of C in S. */ --#define GLIBC232_RAWMEMCHR(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20260,soname,fnname) \ -- (const char* s, int c_in); \ -- char* VG_REPLACE_FUNCTION_EZU(20260,soname,fnname) \ -- (const char* s, int c_in) \ -- { \ -- UChar c = (UChar) c_in; \ -- UChar* char_ptr = (UChar *)s; \ -- while (1) { \ -- if (*char_ptr == c) return (HChar *)char_ptr; \ -- char_ptr++; \ -- } \ -- } -- --#if defined (VGO_linux) -- GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, rawmemchr) -- GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, __GI___rawmemchr) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- strcpy_chk ----------------------*/ -- --/* glibc variant of strcpy that checks the dest is big enough. -- Copied from glibc-2.5/debug/test-strcpy_chk.c. */ --#define GLIBC25___STRCPY_CHK(soname,fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20270,soname,fnname) \ -- (char* dst, const char* src, SizeT len); \ -- char* VG_REPLACE_FUNCTION_EZU(20270,soname,fnname) \ -- (char* dst, const char* src, SizeT len) \ -- { \ -- HChar* ret = dst; \ -- if (! len) \ -- goto badness; \ -- while ((*dst++ = *src++) != '\0') \ -- if (--len == 0) \ -- goto badness; \ -- return ret; \ -- badness: \ -- VALGRIND_PRINTF_BACKTRACE( \ -- "*** strcpy_chk: buffer overflow detected ***: " \ -- "program terminated\n"); \ -- my_exit(127); \ -- /*NOTREACHED*/ \ -- return NULL; \ -- } -- --#if defined(VGO_linux) -- GLIBC25___STRCPY_CHK(VG_Z_LIBC_SONAME, __strcpy_chk) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- stpcpy_chk ----------------------*/ -- --/* glibc variant of stpcpy that checks the dest is big enough. -- Copied from glibc-2.5/debug/test-stpcpy_chk.c. */ --#define GLIBC25___STPCPY_CHK(soname,fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20280,soname,fnname) \ -- (char* dst, const char* src, SizeT len); \ -- char* VG_REPLACE_FUNCTION_EZU(20280,soname,fnname) \ -- (char* dst, const char* src, SizeT len) \ -- { \ -- if (! len) \ -- goto badness; \ -- while ((*dst++ = *src++) != '\0') \ -- if (--len == 0) \ -- goto badness; \ -- return dst - 1; \ -- badness: \ -- VALGRIND_PRINTF_BACKTRACE( \ -- "*** stpcpy_chk: buffer overflow detected ***: " \ -- "program terminated\n"); \ -- my_exit(127); \ -- /*NOTREACHED*/ \ -- return NULL; \ -- } -- --#if defined(VGO_linux) -- GLIBC25___STPCPY_CHK(VG_Z_LIBC_SONAME, __stpcpy_chk) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- mempcpy ----------------------*/ -- --/* mempcpy */ --#define GLIBC25_MEMPCPY(soname, fnname) \ -- void* VG_REPLACE_FUNCTION_EZU(20290,soname,fnname) \ -- ( void *dst, const void *src, SizeT len ); \ -- void* VG_REPLACE_FUNCTION_EZU(20290,soname,fnname) \ -- ( void *dst, const void *src, SizeT len ) \ -- { \ -- register HChar *d; \ -- register HChar *s; \ -- SizeT len_saved = len; \ -- \ -- if (len == 0) \ -- return dst; \ -- \ -- if (is_overlap(dst, src, len, len)) \ -- RECORD_OVERLAP_ERROR("mempcpy", dst, src, len); \ -- \ -- if ( dst > src ) { \ -- d = (char *)dst + len - 1; \ -- s = (char *)src + len - 1; \ -- while ( len-- ) { \ -- *d-- = *s--; \ -- } \ -- } else if ( dst < src ) { \ -- d = (char *)dst; \ -- s = (char *)src; \ -- while ( len-- ) { \ -- *d++ = *s++; \ -- } \ -- } \ -- return (void*)( ((char*)dst) + len_saved ); \ -- } -- --#if defined(VGO_linux) -- GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy) -- GLIBC25_MEMPCPY(VG_Z_LD_SO_1, mempcpy) /* ld.so.1 */ -- --#elif defined(VGO_darwin) -- //GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy) -- --#endif -- -- --/*-------------------- memcpy_chk --------------------*/ -- --#define GLIBC26___MEMCPY_CHK(soname, fnname) \ -- void* VG_REPLACE_FUNCTION_EZU(20300,soname,fnname) \ -- (void* dst, const void* src, SizeT len, SizeT dstlen ); \ -- void* VG_REPLACE_FUNCTION_EZU(20300,soname,fnname) \ -- (void* dst, const void* src, SizeT len, SizeT dstlen ) \ -- { \ -- register HChar *d; \ -- register const HChar *s; \ -- \ -- if (dstlen < len) goto badness; \ -- \ -- if (len == 0) \ -- return dst; \ -- \ -- if (is_overlap(dst, src, len, len)) \ -- RECORD_OVERLAP_ERROR("memcpy_chk", dst, src, len); \ -- \ -- if ( dst > src ) { \ -- d = (HChar *)dst + len - 1; \ -- s = (const HChar *)src + len - 1; \ -- while ( len-- ) { \ -- *d-- = *s--; \ -- } \ -- } else if ( dst < src ) { \ -- d = (HChar *)dst; \ -- s = (const HChar *)src; \ -- while ( len-- ) { \ -- *d++ = *s++; \ -- } \ -- } \ -- return dst; \ -- badness: \ -- VALGRIND_PRINTF_BACKTRACE( \ -- "*** memcpy_chk: buffer overflow detected ***: " \ -- "program terminated\n"); \ -- my_exit(127); \ -- /*NOTREACHED*/ \ -- return NULL; \ -- } -- --#if defined(VGO_linux) -- GLIBC26___MEMCPY_CHK(VG_Z_LIBC_SONAME, __memcpy_chk) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- strstr ----------------------*/ -- --#define STRSTR(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20310,soname,fnname) \ -- (const char* haystack, const char* needle); \ -- char* VG_REPLACE_FUNCTION_EZU(20310,soname,fnname) \ -- (const char* haystack, const char* needle) \ -- { \ -- const HChar* h = haystack; \ -- const HChar* n = needle; \ -- \ -- /* find the length of n, not including terminating zero */ \ -- UWord nlen = 0; \ -- while (n[nlen]) nlen++; \ -- \ -- /* if n is the empty string, match immediately. */ \ -- if (nlen == 0) return (HChar *)h; \ -- \ -- /* assert(nlen >= 1); */ \ -- HChar n0 = n[0]; \ -- \ -- while (1) { \ -- const HChar hh = *h; \ -- if (hh == 0) return NULL; \ -- if (hh != n0) { h++; continue; } \ -- \ -- UWord i; \ -- for (i = 0; i < nlen; i++) { \ -- if (n[i] != h[i]) \ -- break; \ -- } \ -- /* assert(i >= 0 && i <= nlen); */ \ -- if (i == nlen) \ -- return (HChar *)h; \ -- \ -- h++; \ -- } \ -- } -- --#if defined(VGO_linux) -- STRSTR(VG_Z_LIBC_SONAME, strstr) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- strpbrk ----------------------*/ -- --#define STRPBRK(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20320,soname,fnname) \ -- (const char* sV, const char* acceptV); \ -- char* VG_REPLACE_FUNCTION_EZU(20320,soname,fnname) \ -- (const char* sV, const char* acceptV) \ -- { \ -- const HChar* s = sV; \ -- const HChar* accept = acceptV; \ -- \ -- /* find the length of 'accept', not including terminating zero */ \ -- UWord nacc = 0; \ -- while (accept[nacc]) nacc++; \ -- \ -- /* if n is the empty string, fail immediately. */ \ -- if (nacc == 0) return NULL; \ -- \ -- /* assert(nacc >= 1); */ \ -- while (1) { \ -- UWord i; \ -- HChar sc = *s; \ -- if (sc == 0) \ -- break; \ -- for (i = 0; i < nacc; i++) { \ -- if (sc == accept[i]) \ -- return (HChar *)s; \ -- } \ -- s++; \ -- } \ -- \ -- return NULL; \ -- } -- --#if defined(VGO_linux) -- STRPBRK(VG_Z_LIBC_SONAME, strpbrk) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- strcspn ----------------------*/ -- --#define STRCSPN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_EZU(20330,soname,fnname) \ -- (const char* sV, const char* rejectV); \ -- SizeT VG_REPLACE_FUNCTION_EZU(20330,soname,fnname) \ -- (const char* sV, const char* rejectV) \ -- { \ -- const HChar* s = sV; \ -- const HChar* reject = rejectV; \ -- \ -- /* find the length of 'reject', not including terminating zero */ \ -- UWord nrej = 0; \ -- while (reject[nrej]) nrej++; \ -- \ -- UWord len = 0; \ -- while (1) { \ -- UWord i; \ -- HChar sc = *s; \ -- if (sc == 0) \ -- break; \ -- for (i = 0; i < nrej; i++) { \ -- if (sc == reject[i]) \ -- break; \ -- } \ -- /* assert(i >= 0 && i <= nrej); */ \ -- if (i < nrej) \ -- break; \ -- s++; \ -- len++; \ -- } \ -- \ -- return len; \ -- } -- --#if defined(VGO_linux) -- STRCSPN(VG_Z_LIBC_SONAME, strcspn) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- strspn ----------------------*/ -- --#define STRSPN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_EZU(20340,soname,fnname) \ -- (const char* sV, const char* acceptV); \ -- SizeT VG_REPLACE_FUNCTION_EZU(20340,soname,fnname) \ -- (const char* sV, const char* acceptV) \ -- { \ -- const UChar* s = (const UChar *)sV; \ -- const UChar* accept = (const UChar *)acceptV; \ -- \ -- /* find the length of 'accept', not including terminating zero */ \ -- UWord nacc = 0; \ -- while (accept[nacc]) nacc++; \ -- if (nacc == 0) return 0; \ -- \ -- UWord len = 0; \ -- while (1) { \ -- UWord i; \ -- HChar sc = *s; \ -- if (sc == 0) \ -- break; \ -- for (i = 0; i < nacc; i++) { \ -- if (sc == accept[i]) \ -- break; \ -- } \ -- /* assert(i >= 0 && i <= nacc); */ \ -- if (i == nacc) \ -- break; \ -- s++; \ -- len++; \ -- } \ -- \ -- return len; \ -- } -- --#if defined(VGO_linux) -- STRSPN(VG_Z_LIBC_SONAME, strspn) -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- strcasestr ----------------------*/ -- --#define STRCASESTR(soname, fnname) \ -- char* VG_REPLACE_FUNCTION_EZU(20350,soname,fnname) \ -- (const char* haystack, const char* needle); \ -- char* VG_REPLACE_FUNCTION_EZU(20350,soname,fnname) \ -- (const char* haystack, const char* needle) \ -- { \ -- extern int tolower(int); \ -- const HChar* h = haystack; \ -- const HChar* n = needle; \ -- \ -- /* find the length of n, not including terminating zero */ \ -- UWord nlen = 0; \ -- while (n[nlen]) nlen++; \ -- \ -- /* if n is the empty string, match immediately. */ \ -- if (nlen == 0) return (HChar *)h; \ -- \ -- /* assert(nlen >= 1); */ \ -- UChar n0 = tolower(n[0]); \ -- \ -- while (1) { \ -- UChar hh = tolower(*h); \ -- if (hh == 0) return NULL; \ -- if (hh != n0) { h++; continue; } \ -- \ -- UWord i; \ -- for (i = 0; i < nlen; i++) { \ -- if (tolower(n[i]) != tolower(h[i])) \ -- break; \ -- } \ -- /* assert(i >= 0 && i <= nlen); */ \ -- if (i == nlen) \ -- return (HChar *)h; \ -- \ -- h++; \ -- } \ -- } -- --#if defined(VGO_linux) --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -- STRCASESTR(VG_Z_LIBC_SONAME, strcasestr) --# endif -- --#elif defined(VGO_darwin) -- --#endif -- -- --/*---------------------- wcslen ----------------------*/ -- --// This is a wchar_t equivalent to strlen. Unfortunately --// we don't have wchar_t available here, but it looks like --// a 32 bit int on Linux. I don't know if that is also --// valid on MacOSX. -- --#define WCSLEN(soname, fnname) \ -- SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \ -- ( const UInt* str ); \ -- SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \ -- ( const UInt* str ) \ -- { \ -- SizeT i = 0; \ -- while (str[i] != 0) i++; \ -- return i; \ -- } -- --#if defined(VGO_linux) -- WCSLEN(VG_Z_LIBC_SONAME, wcslen) -- --#elif defined(VGO_darwin) -- --#endif -- --/*---------------------- wcscmp ----------------------*/ -- --// This is a wchar_t equivalent to strcmp. We don't --// have wchar_t available here, but in the GNU C Library --// wchar_t is always 32 bits wide and wcscmp uses signed --// comparison, not unsigned as in strcmp function. -- --#define WCSCMP(soname, fnname) \ -- int VG_REPLACE_FUNCTION_EZU(20380,soname,fnname) \ -- ( const Int* s1, const Int* s2 ); \ -- int VG_REPLACE_FUNCTION_EZU(20380,soname,fnname) \ -- ( const Int* s1, const Int* s2 ) \ -- { \ -- register Int c1; \ -- register Int c2; \ -- while (True) { \ -- c1 = *s1; \ -- c2 = *s2; \ -- if (c1 != c2) break; \ -- if (c1 == 0) break; \ -- s1++; s2++; \ -- } \ -- if (c1 < c2) return -1; \ -- if (c1 > c2) return 1; \ -- return 0; \ -- } -- --#if defined(VGO_linux) -- WCSCMP(VG_Z_LIBC_SONAME, wcscmp) --#endif -- --/*---------------------- wcscpy ----------------------*/ -- --// This is a wchar_t equivalent to strcpy. We don't --// have wchar_t available here, but in the GNU C Library --// wchar_t is always 32 bits wide. -- --#define WCSCPY(soname, fnname) \ -- Int* VG_REPLACE_FUNCTION_EZU(20390,soname,fnname) \ -- ( Int* dst, const Int* src ); \ -- Int* VG_REPLACE_FUNCTION_EZU(20390,soname,fnname) \ -- ( Int* dst, const Int* src ) \ -- { \ -- const Int* src_orig = src; \ -- Int* dst_orig = dst; \ -- \ -- while (*src) *dst++ = *src++; \ -- *dst = 0; \ -- \ -- /* This checks for overlap after copying, unavoidable without */ \ -- /* pre-counting length... should be ok */ \ -- if (is_overlap(dst_orig, \ -- src_orig, \ -- (Addr)dst-(Addr)dst_orig+1, \ -- (Addr)src-(Addr)src_orig+1)) \ -- RECORD_OVERLAP_ERROR("wcscpy", dst_orig, src_orig, 0); \ -- \ -- return dst_orig; \ -- } -- --#if defined(VGO_linux) -- WCSCPY(VG_Z_LIBC_SONAME, wcscpy) --#endif -- -- --/*---------------------- wcschr ----------------------*/ -- --// This is a wchar_t equivalent to strchr. We don't --// have wchar_t available here, but in the GNU C Library --// wchar_t is always 32 bits wide. -- --#define WCSCHR(soname, fnname) \ -- Int* VG_REPLACE_FUNCTION_EZU(20400,soname,fnname) ( const Int* s, Int c ); \ -- Int* VG_REPLACE_FUNCTION_EZU(20400,soname,fnname) ( const Int* s, Int c ) \ -- { \ -- Int* p = (Int*)s; \ -- while (True) { \ -- if (*p == c) return p; \ -- if (*p == 0) return NULL; \ -- p++; \ -- } \ -- } -- --#if defined(VGO_linux) -- WCSCHR(VG_Z_LIBC_SONAME, wcschr) --#endif --/*---------------------- wcsrchr ----------------------*/ -- --// This is a wchar_t equivalent to strrchr. We don't --// have wchar_t available here, but in the GNU C Library --// wchar_t is always 32 bits wide. -- --#define WCSRCHR(soname, fnname) \ -- Int* VG_REPLACE_FUNCTION_EZU(20410,soname,fnname)( const Int* s, Int c ); \ -- Int* VG_REPLACE_FUNCTION_EZU(20410,soname,fnname)( const Int* s, Int c ) \ -- { \ -- Int* p = (Int*) s; \ -- Int* last = NULL; \ -- while (True) { \ -- if (*p == c) last = p; \ -- if (*p == 0) return last; \ -- p++; \ -- } \ -- } -- --#if defined(VGO_linux) -- WCSRCHR(VG_Z_LIBC_SONAME, wcsrchr) --#endif -- --/*------------------------------------------------------------*/ --/*--- Improve definedness checking of process environment ---*/ --/*------------------------------------------------------------*/ -- --#if defined(VGO_linux) -- --/* If these wind up getting generated via a macro, so that multiple -- versions of each function exist (as above), use the _EZU variants -- to assign equivalance class tags. */ -- --/*---------------------- putenv ----------------------*/ -- --int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, putenv) (char* string); --int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, putenv) (char* string) --{ -- OrigFn fn; -- Word result; -- const HChar* p = string; -- VALGRIND_GET_ORIG_FN(fn); -- /* Now by walking over the string we magically produce -- traces when hitting undefined memory. */ -- if (p) -- while (*p++) -- __asm__ __volatile__("" ::: "memory"); -- CALL_FN_W_W(result, fn, string); -- return result; --} -- -- --/*---------------------- unsetenv ----------------------*/ -- --int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, unsetenv) (const char* name); --int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, unsetenv) (const char* name) --{ -- OrigFn fn; -- Word result; -- const HChar* p = name; -- VALGRIND_GET_ORIG_FN(fn); -- /* Now by walking over the string we magically produce -- traces when hitting undefined memory. */ -- if (p) -- while (*p++) -- __asm__ __volatile__("" ::: "memory"); -- CALL_FN_W_W(result, fn, name); -- return result; --} -- -- --/*---------------------- setenv ----------------------*/ -- --/* setenv */ --int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, setenv) -- (const char* name, const char* value, int overwrite); --int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, setenv) -- (const char* name, const char* value, int overwrite) --{ -- OrigFn fn; -- Word result; -- const HChar* p; -- VALGRIND_GET_ORIG_FN(fn); -- /* Now by walking over the string we magically produce -- traces when hitting undefined memory. */ -- if (name) -- for (p = name; *p; p++) -- __asm__ __volatile__("" ::: "memory"); -- if (value) -- for (p = value; *p; p++) -- __asm__ __volatile__("" ::: "memory"); -- (void) VALGRIND_CHECK_VALUE_IS_DEFINED (overwrite); -- CALL_FN_W_WWW(result, fn, name, value, overwrite); -- return result; --} -- --#endif /* defined(VGO_linux) */ -- --/*--------------------------------------------------------------------*/ --/*--- end ---*/ --/*--------------------------------------------------------------------*/ -+#include "../shared/vg_replace_strmem.c" -Index: memcheck/mc_translate.c -=================================================================== ---- memcheck/mc_translate.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/mc_translate.c (.../trunk) (revision 13981) -@@ -398,6 +398,7 @@ - case Ity_I64: return IRExpr_Const(IRConst_U64(0)); - case Ity_I128: return i128_const_zero(); - case Ity_V128: return IRExpr_Const(IRConst_V128(0x0000)); -+ case Ity_V256: return IRExpr_Const(IRConst_V256(0x00000000)); - default: VG_(tool_panic)("memcheck:definedOfType"); - } - } -@@ -767,6 +768,21 @@ - return assignNew('V', mce, Ity_I64, binop(Iop_32HLto64, tmp, tmp)); - } - -+ if (src_ty == Ity_I32 && dst_ty == Ity_V128) { -+ /* PCast the arg, then clone it 4 times. */ -+ IRAtom* tmp = assignNew('V', mce, Ity_I32, unop(Iop_CmpwNEZ32, vbits)); -+ tmp = assignNew('V', mce, Ity_I64, binop(Iop_32HLto64, tmp, tmp)); -+ return assignNew('V', mce, Ity_V128, binop(Iop_64HLtoV128, tmp, tmp)); -+ } -+ -+ if (src_ty == Ity_I32 && dst_ty == Ity_V256) { -+ /* PCast the arg, then clone it 8 times. */ -+ IRAtom* tmp = assignNew('V', mce, Ity_I32, unop(Iop_CmpwNEZ32, vbits)); -+ tmp = assignNew('V', mce, Ity_I64, binop(Iop_32HLto64, tmp, tmp)); -+ tmp = assignNew('V', mce, Ity_V128, binop(Iop_64HLtoV128, tmp, tmp)); -+ return assignNew('V', mce, Ity_V256, binop(Iop_V128HLtoV256, tmp, tmp)); -+ } -+ - if (src_ty == Ity_I64 && dst_ty == Ity_I32) { - /* PCast the arg. This gives all 0s or all 1s. Then throw away - the top half. */ -@@ -2244,6 +2260,69 @@ - return at; - } - -+/* --- 64Fx2 binary FP ops, with rounding mode --- */ -+ -+static -+IRAtom* binary64Fx2_w_rm ( MCEnv* mce, IRAtom* vRM, -+ IRAtom* vatomX, IRAtom* vatomY ) -+{ -+ /* This is the same as binary64Fx2, except that we subsequently -+ pessimise vRM (definedness of the rounding mode), widen to 128 -+ bits and UifU it into the result. As with the scalar cases, if -+ the RM is a constant then it is defined and so this extra bit -+ will get constant-folded out later. */ -+ // "do" the vector args -+ IRAtom* t1 = binary64Fx2(mce, vatomX, vatomY); -+ // PCast the RM, and widen it to 128 bits -+ IRAtom* t2 = mkPCastTo(mce, Ity_V128, vRM); -+ // Roll it into the result -+ t1 = mkUifUV128(mce, t1, t2); -+ return t1; -+} -+ -+/* --- ... and ... 32Fx4 versions of the same --- */ -+ -+static -+IRAtom* binary32Fx4_w_rm ( MCEnv* mce, IRAtom* vRM, -+ IRAtom* vatomX, IRAtom* vatomY ) -+{ -+ IRAtom* t1 = binary32Fx4(mce, vatomX, vatomY); -+ // PCast the RM, and widen it to 128 bits -+ IRAtom* t2 = mkPCastTo(mce, Ity_V128, vRM); -+ // Roll it into the result -+ t1 = mkUifUV128(mce, t1, t2); -+ return t1; -+} -+ -+/* --- ... and ... 64Fx4 versions of the same --- */ -+ -+static -+IRAtom* binary64Fx4_w_rm ( MCEnv* mce, IRAtom* vRM, -+ IRAtom* vatomX, IRAtom* vatomY ) -+{ -+ IRAtom* t1 = binary64Fx4(mce, vatomX, vatomY); -+ // PCast the RM, and widen it to 256 bits -+ IRAtom* t2 = mkPCastTo(mce, Ity_V256, vRM); -+ // Roll it into the result -+ t1 = mkUifUV256(mce, t1, t2); -+ return t1; -+} -+ -+/* --- ... and ... 32Fx8 versions of the same --- */ -+ -+static -+IRAtom* binary32Fx8_w_rm ( MCEnv* mce, IRAtom* vRM, -+ IRAtom* vatomX, IRAtom* vatomY ) -+{ -+ IRAtom* t1 = binary32Fx8(mce, vatomX, vatomY); -+ // PCast the RM, and widen it to 256 bits -+ IRAtom* t2 = mkPCastTo(mce, Ity_V256, vRM); -+ // Roll it into the result -+ t1 = mkUifUV256(mce, t1, t2); -+ return t1; -+} -+ -+ - /* --- --- Vector saturated narrowing --- --- */ - - /* We used to do something very clever here, but on closer inspection -@@ -2715,6 +2794,31 @@ - complainIfUndefined(mce, atom3, NULL); - return assignNew('V', mce, Ity_V128, triop(op, vatom1, vatom2, atom3)); - -+ /* Vector FP with rounding mode as the first arg */ -+ case Iop_Add64Fx2: -+ case Iop_Sub64Fx2: -+ case Iop_Mul64Fx2: -+ case Iop_Div64Fx2: -+ return binary64Fx2_w_rm(mce, vatom1, vatom2, vatom3); -+ -+ case Iop_Add32Fx4: -+ case Iop_Sub32Fx4: -+ case Iop_Mul32Fx4: -+ case Iop_Div32Fx4: -+ return binary32Fx4_w_rm(mce, vatom1, vatom2, vatom3); -+ -+ case Iop_Add64Fx4: -+ case Iop_Sub64Fx4: -+ case Iop_Mul64Fx4: -+ case Iop_Div64Fx4: -+ return binary64Fx4_w_rm(mce, vatom1, vatom2, vatom3); -+ -+ case Iop_Add32Fx8: -+ case Iop_Sub32Fx8: -+ case Iop_Mul32Fx8: -+ case Iop_Div32Fx8: -+ return binary32Fx8_w_rm(mce, vatom1, vatom2, vatom3); -+ - default: - ppIROp(op); - VG_(tool_panic)("memcheck:expr2vbits_Triop"); -@@ -3175,16 +3279,12 @@ - case Iop_QNarrowBin16Sto8Ux16: - return vectorNarrowBinV128(mce, op, vatom1, vatom2); - -- case Iop_Sub64Fx2: -- case Iop_Mul64Fx2: - case Iop_Min64Fx2: - case Iop_Max64Fx2: -- case Iop_Div64Fx2: - case Iop_CmpLT64Fx2: - case Iop_CmpLE64Fx2: - case Iop_CmpEQ64Fx2: - case Iop_CmpUN64Fx2: -- case Iop_Add64Fx2: - return binary64Fx2(mce, vatom1, vatom2); - - case Iop_Sub64F0x2: -@@ -3199,11 +3299,8 @@ - case Iop_Add64F0x2: - return binary64F0x2(mce, vatom1, vatom2); - -- case Iop_Sub32Fx4: -- case Iop_Mul32Fx4: - case Iop_Min32Fx4: - case Iop_Max32Fx4: -- case Iop_Div32Fx4: - case Iop_CmpLT32Fx4: - case Iop_CmpLE32Fx4: - case Iop_CmpEQ32Fx4: -@@ -3210,7 +3307,6 @@ - case Iop_CmpUN32Fx4: - case Iop_CmpGT32Fx4: - case Iop_CmpGE32Fx4: -- case Iop_Add32Fx4: - case Iop_Recps32Fx4: - case Iop_Rsqrts32Fx4: - return binary32Fx4(mce, vatom1, vatom2); -@@ -3417,18 +3513,10 @@ - - /* V256-bit SIMD */ - -- case Iop_Add64Fx4: -- case Iop_Sub64Fx4: -- case Iop_Mul64Fx4: -- case Iop_Div64Fx4: - case Iop_Max64Fx4: - case Iop_Min64Fx4: - return binary64Fx4(mce, vatom1, vatom2); - -- case Iop_Add32Fx8: -- case Iop_Sub32Fx8: -- case Iop_Mul32Fx8: -- case Iop_Div32Fx8: - case Iop_Max32Fx8: - case Iop_Min32Fx8: - return binary32Fx8(mce, vatom1, vatom2); -@@ -3909,6 +3997,8 @@ - switch (op) { - - case Iop_Sqrt64Fx2: -+ case Iop_Abs64Fx2: -+ case Iop_Neg64Fx2: - return unary64Fx2(mce, vatom); - - case Iop_Sqrt64F0x2: -@@ -3965,6 +4055,10 @@ - case Iop_Reverse64_16x8: - case Iop_Reverse64_32x4: - case Iop_V256toV128_1: case Iop_V256toV128_0: -+ case Iop_ZeroHI64ofV128: -+ case Iop_ZeroHI96ofV128: -+ case Iop_ZeroHI112ofV128: -+ case Iop_ZeroHI120ofV128: - return assignNew('V', mce, Ity_V128, unop(op, vatom)); - - case Iop_F128HItoF64: /* F128 -> high half of F128 */ -@@ -5730,6 +5824,7 @@ - case Ico_F32i: return False; - case Ico_F64i: return False; - case Ico_V128: return False; -+ case Ico_V256: return False; - default: ppIRExpr(at); tl_assert(0); - } - /* VG_(printf)("%llx\n", n); */ -@@ -5736,6 +5831,8 @@ - return (/*32*/ n == 0xFEFEFEFFULL - /*32*/ || n == 0x80808080ULL - /*32*/ || n == 0x7F7F7F7FULL -+ /*32*/ || n == 0x7EFEFEFFULL -+ /*32*/ || n == 0x81010100ULL - /*64*/ || n == 0xFFFFFFFFFEFEFEFFULL - /*64*/ || n == 0xFEFEFEFEFEFEFEFFULL - /*64*/ || n == 0x0000000000008080ULL -@@ -5760,7 +5857,8 @@ - case Iex_Const: - return isBogusAtom(e); - case Iex_Unop: -- return isBogusAtom(e->Iex.Unop.arg); -+ return isBogusAtom(e->Iex.Unop.arg) -+ || e->Iex.Unop.op == Iop_GetMSBs8x16; - case Iex_GetI: - return isBogusAtom(e->Iex.GetI.ix); - case Iex_Binop: -Index: memcheck/memcheck.h -=================================================================== ---- memcheck/memcheck.h (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/memcheck.h (.../trunk) (revision 13981) -@@ -96,6 +96,9 @@ - /* Not next to VG_USERREQ__COUNT_LEAKS because it was added later. */ - VG_USERREQ__COUNT_LEAK_BLOCKS, - -+ VG_USERREQ__ENABLE_ADDR_ERROR_REPORTING_IN_RANGE, -+ VG_USERREQ__DISABLE_ADDR_ERROR_REPORTING_IN_RANGE, -+ - /* This is just for memcheck's internal use - don't use it */ - _VG_USERREQ__MEMCHECK_RECORD_OVERLAP_ERROR - = VG_USERREQ_TOOL_BASE('M','C') + 256 -@@ -283,5 +286,17 @@ - (const char*)(zzvbits), \ - (zznbytes), 0, 0 ) - -+/* Disable and re-enable reporting of addressing errors in the -+ specified address range. */ -+#define VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE(_qzz_addr,_qzz_len) \ -+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ -+ VG_USERREQ__DISABLE_ADDR_ERROR_REPORTING_IN_RANGE, \ -+ (_qzz_addr), (_qzz_len), 0, 0, 0) -+ -+#define VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE(_qzz_addr,_qzz_len) \ -+ VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */, \ -+ VG_USERREQ__ENABLE_ADDR_ERROR_REPORTING_IN_RANGE, \ -+ (_qzz_addr), (_qzz_len), 0, 0, 0) -+ - #endif - -Index: memcheck/tests -=================================================================== ---- memcheck/tests (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests (.../trunk) (revision 13981) - -Property changes on: memcheck/tests -___________________________________________________________________ -Modified: svn:ignore -## -62,6 +62,7 ## - leak-segv-jmp - leak-tree - leakotron -+leak_cpp_interior - linux-capget - linux-syscalls-2007 - linux-syslog-syscall -## -112,6 +113,7 ## - pipe - pointer-trace - post-syscall -+reach_thread_register - realloc1 - realloc2 - realloc3 -## -132,6 +134,7 ## - stack_changes - stack_switch - static_malloc -+stpncpy - strchr - str_tester - supp1 -## -140,6 +143,8 ## - supp_unknown - test-plo - threadederrno -+threadname -+thread_alloca - trivialleak - undef_malloc_args - unit_libcbase -## -155,6 +160,7 ## - vcpu_fbench - vcpu_fnfns - vgtest_ume -+wcs - weirdioctl - with space - wrap1 -## -169,8 +175,3 ## - writev1 - xml1 - zeropage --stpncpy --wcs --thread_alloca --threadname --leak_cpp_interior -Index: memcheck/tests/Makefile.am -=================================================================== ---- memcheck/tests/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/Makefile.am (.../trunk) (revision 13981) -@@ -42,12 +42,12 @@ - dist_noinst_SCRIPTS = \ - filter_addressable \ - filter_allocs \ -+ filter_dw4 \ - filter_leak_cases_possible \ - filter_stderr filter_xml \ - filter_strchr \ - filter_varinfo3 \ -- filter_memcheck \ -- filter_memcpy -+ filter_memcheck - - noinst_HEADERS = leak.h - -@@ -102,6 +102,7 @@ - err_disable2.vgtest err_disable2.stderr.exp \ - err_disable3.vgtest err_disable3.stderr.exp \ - err_disable4.vgtest err_disable4.stderr.exp \ -+ err_disable_arange1.vgtest err_disable_arange1.stderr.exp \ - erringfds.stderr.exp erringfds.stdout.exp erringfds.vgtest \ - error_counts.stderr.exp error_counts.vgtest \ - errs1.stderr.exp errs1.vgtest \ -@@ -109,7 +110,8 @@ - execve1.stderr.exp execve1.vgtest execve1.stderr.exp-kfail \ - execve2.stderr.exp execve2.vgtest execve2.stderr.exp-kfail \ - file_locking.stderr.exp file_locking.vgtest \ -- fprw.stderr.exp fprw.vgtest \ -+ fprw.stderr.exp fprw.stderr.exp-mips32-be fprw.stderr.exp-mips32-le \ -+ fprw.vgtest \ - fwrite.stderr.exp fwrite.vgtest fwrite.stderr.exp-kfail \ - holey_buffer_too_small.vgtest holey_buffer_too_small.stdout.exp \ - holey_buffer_too_small.stderr.exp \ -@@ -174,9 +176,11 @@ - origin5-bz2.vgtest origin5-bz2.stdout.exp \ - origin5-bz2.stderr.exp-glibc25-x86 \ - origin5-bz2.stderr.exp-glibc25-amd64 \ -+ origin5-bz2.stderr.exp-glibc25-amd64-b \ - origin5-bz2.stderr.exp-glibc27-ppc64 \ - origin5-bz2.stderr.exp-glibc212-s390x \ - origin5-bz2.stderr.exp-glibc234-s390x \ -+ origin5-bz2.stderr.exp-glibc218-mips32 \ - origin6-fp.vgtest origin6-fp.stdout.exp \ - origin6-fp.stderr.exp-glibc25-amd64 \ - origin6-fp.stderr.exp-glibc27-ppc64 \ -@@ -198,6 +202,8 @@ - pointer-trace.stderr.exp \ - post-syscall.stderr.exp post-syscall.vgtest \ - reach_thread_register.stderr.exp reach_thread_register.vgtest \ -+ reach_thread_register.stderr.exp-mips32 \ -+ reach_thread_register.stderr.exp-mips64 \ - realloc1.stderr.exp realloc1.vgtest \ - realloc2.stderr.exp realloc2.vgtest \ - realloc3.stderr.exp realloc3.vgtest \ -@@ -215,8 +221,7 @@ - sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \ - static_malloc.stderr.exp static_malloc.vgtest \ - stpncpy.vgtest stpncpy.stderr.exp stpncpy.stdout.exp \ -- strchr.stderr.exp strchr.stderr.exp2 strchr.stderr.exp-darwin \ -- strchr.stderr.exp3 strchr.vgtest \ -+ strchr.stderr.exp strchr.stderr.exp2 strchr.stderr.exp3 strchr.vgtest \ - str_tester.stderr.exp str_tester.vgtest \ - supp-dir.vgtest supp-dir.stderr.exp \ - supp_unknown.stderr.exp supp_unknown.vgtest supp_unknown.supp \ -@@ -225,6 +230,7 @@ - supp2.stderr.exp supp2.vgtest \ - supp.supp \ - suppfree.stderr.exp suppfree.supp suppfree.vgtest \ -+ suppfreecollision.stderr.exp suppfreecollision.supp suppfreecollision.vgtest \ - test-plo-no.vgtest test-plo-no.stdout.exp \ - test-plo-no.stderr.exp-le64 test-plo-no.stderr.exp-le32 \ - test-plo-yes.vgtest test-plo-yes.stdout.exp \ -@@ -291,6 +297,7 @@ - describe-block \ - doublefree error_counts errs1 exitprog execve1 execve2 erringfds \ - err_disable1 err_disable2 err_disable3 err_disable4 \ -+ err_disable_arange1 \ - file_locking \ - fprw fwrite inits inline \ - holey_buffer_too_small \ -Index: memcheck/tests/atomic_incs.c -=================================================================== ---- memcheck/tests/atomic_incs.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/atomic_incs.c (.../trunk) (revision 13981) -@@ -96,6 +96,24 @@ - : /*trash*/ "memory", "cc", "r5", "r8", "r9", "r10", "r4" - ); - } while (block[2] != 0); -+#elif defined(VGA_arm64) -+ unsigned long long int block[3] -+ = { (unsigned long long int)p, (unsigned long long int)n, -+ 0xFFFFFFFFFFFFFFFFULL}; -+ do { -+ __asm__ __volatile__( -+ "mov x5, %0" "\n\t" -+ "ldr x9, [x5, #0]" "\n\t" // p -+ "ldr x10, [x5, #8]" "\n\t" // n -+ "ldxrb w8, [x9]" "\n\t" -+ "add x8, x8, x10" "\n\t" -+ "stxrb w4, w8, [x9]" "\n\t" -+ "str x4, [x5, #16]" "\n\t" -+ : /*out*/ -+ : /*in*/ "r"(&block[0]) -+ : /*trash*/ "memory", "cc", "x5", "x8", "x9", "x10", "x4" -+ ); -+ } while (block[2] != 0); - #elif defined(VGA_s390x) - int dummy; - __asm__ __volatile__( -@@ -277,6 +295,24 @@ - : /*trash*/ "memory", "cc", "r5", "r8", "r9", "r10", "r4" - ); - } while (block[2] != 0); -+#elif defined(VGA_arm64) -+ unsigned long long int block[3] -+ = { (unsigned long long int)p, (unsigned long long int)n, -+ 0xFFFFFFFFFFFFFFFFULL}; -+ do { -+ __asm__ __volatile__( -+ "mov x5, %0" "\n\t" -+ "ldr x9, [x5, #0]" "\n\t" // p -+ "ldr x10, [x5, #8]" "\n\t" // n -+ "ldxrh w8, [x9]" "\n\t" -+ "add x8, x8, x10" "\n\t" -+ "stxrh w4, w8, [x9]" "\n\t" -+ "str x4, [x5, #16]" "\n\t" -+ : /*out*/ -+ : /*in*/ "r"(&block[0]) -+ : /*trash*/ "memory", "cc", "x5", "x8", "x9", "x10", "x4" -+ ); -+ } while (block[2] != 0); - #elif defined(VGA_s390x) - int dummy; - __asm__ __volatile__( -@@ -455,6 +491,24 @@ - : /*trash*/ "memory", "cc", "r5", "r8", "r9", "r10", "r4" - ); - } while (block[2] != 0); -+#elif defined(VGA_arm64) -+ unsigned long long int block[3] -+ = { (unsigned long long int)p, (unsigned long long int)n, -+ 0xFFFFFFFFFFFFFFFFULL}; -+ do { -+ __asm__ __volatile__( -+ "mov x5, %0" "\n\t" -+ "ldr x9, [x5, #0]" "\n\t" // p -+ "ldr x10, [x5, #8]" "\n\t" // n -+ "ldxr w8, [x9]" "\n\t" -+ "add x8, x8, x10" "\n\t" -+ "stxr w4, w8, [x9]" "\n\t" -+ "str x4, [x5, #16]" "\n\t" -+ : /*out*/ -+ : /*in*/ "r"(&block[0]) -+ : /*trash*/ "memory", "cc", "x5", "x8", "x9", "x10", "x4" -+ ); -+ } while (block[2] != 0); - #elif defined(VGA_s390x) - __asm__ __volatile__( - " l 0,%0\n\t" -@@ -555,6 +609,24 @@ - : /*trash*/ "memory", "cc", "r5", "r0", "r1", "r8", "r2", "r3" - ); - } while (block[2] != 0xFFFFFFFF00000000ULL); -+#elif defined(VGA_arm64) -+ unsigned long long int block[3] -+ = { (unsigned long long int)p, (unsigned long long int)n, -+ 0xFFFFFFFFFFFFFFFFULL}; -+ do { -+ __asm__ __volatile__( -+ "mov x5, %0" "\n\t" -+ "ldr x9, [x5, #0]" "\n\t" // p -+ "ldr x10, [x5, #8]" "\n\t" // n -+ "ldxr x8, [x9]" "\n\t" -+ "add x8, x8, x10" "\n\t" -+ "stxr w4, x8, [x9]" "\n\t" -+ "str x4, [x5, #16]" "\n\t" -+ : /*out*/ -+ : /*in*/ "r"(&block[0]) -+ : /*trash*/ "memory", "cc", "x5", "x8", "x9", "x10", "x4" -+ ); -+ } while (block[2] != 0); - #elif defined(VGA_s390x) - __asm__ __volatile__( - " lg 0,%0\n\t" -Index: memcheck/tests/badpoll.stderr.exp -=================================================================== ---- memcheck/tests/badpoll.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/badpoll.stderr.exp (.../trunk) (revision 13981) -@@ -5,7 +5,7 @@ - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (badpoll.c:12) - --Syscall param poll(ufds.reventss) points to unaddressable byte(s) -+Syscall param poll(ufds.revents) points to unaddressable byte(s) - ... - by 0x........: main (badpoll.c:22) - Address 0x........ is 0 bytes after a block of size 15 alloc'd -Index: memcheck/tests/big_blocks_freed_list.c -=================================================================== ---- memcheck/tests/big_blocks_freed_list.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/big_blocks_freed_list.c (.../trunk) (revision 13981) -@@ -16,7 +16,7 @@ - /* Verify that access via a dangling pointer to a big block bigger than - the free list is found by memcheck (still on the free list). */ - semi_big = malloc (900000); -- big = malloc (1000001); -+ big = malloc (1000015); - free(semi_big); - free(big); - if (big[1000] > 0x0) jumped(); -@@ -36,7 +36,7 @@ - big = NULL; - - { -- big = malloc (1000001); -+ big = malloc (1000015); - free(big); - if (small[10] > 0x0) jumped(); - -Index: memcheck/tests/big_blocks_freed_list.stderr.exp -=================================================================== ---- memcheck/tests/big_blocks_freed_list.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/big_blocks_freed_list.stderr.exp (.../trunk) (revision 13981) -@@ -1,7 +1,7 @@ - - Invalid read of size 1 - at 0x........: main (big_blocks_freed_list.c:22) -- Address 0x........ is 1,000 bytes inside a block of size 1,000,001 free'd -+ Address 0x........ is 1,000 bytes inside a block of size 1,000,015 free'd - at 0x........: free (vg_replace_malloc.c:...) - by 0x........: main (big_blocks_freed_list.c:21) - -@@ -13,7 +13,7 @@ - - Invalid read of size 1 - at 0x........: main (big_blocks_freed_list.c:33) -- Address 0x........ is not stack'd, malloc'd or (recently) free'd -+ Address 0x........ is 2,000 bytes inside an unallocated block of size 1,000,016 in arena "client" - - Invalid read of size 1 - at 0x........: main (big_blocks_freed_list.c:34) -@@ -29,7 +29,7 @@ - - Invalid read of size 1 - at 0x........: main (big_blocks_freed_list.c:46) -- Address 0x........ is 10 bytes inside a block of size 1,000,001 free'd -+ Address 0x........ is 10 bytes inside a block of size 1,000,015 free'd - at 0x........: free (vg_replace_malloc.c:...) - by 0x........: main (big_blocks_freed_list.c:40) - -@@ -42,7 +42,7 @@ - - HEAP SUMMARY: - in use at exit: 1,000,000 bytes in 100 blocks -- total heap usage: 104 allocs, 4 frees, 3,910,002 bytes allocated -+ total heap usage: 104 allocs, 4 frees, 3,910,030 bytes allocated - - For a detailed leak analysis, rerun with: --leak-check=full - -Index: memcheck/tests/dw4.stderr.exp -=================================================================== ---- memcheck/tests/dw4.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/dw4.stderr.exp (.../trunk) (revision 13981) -@@ -1,7 +1,7 @@ - Uninitialised byte(s) found during client check request - at 0x........: croak (dw4.c:27) - by 0x........: main (dw4.c:49) -- Address 0x........ is 4 bytes inside a block of size 32 alloc'd -+ Address 0x........ is 4 bytes inside a block of size ... alloc'd - at 0x........: malloc (vg_replace_malloc.c:...) - by 0x........: main (dw4.c:47) - -Index: memcheck/tests/dw4.vgtest -=================================================================== ---- memcheck/tests/dw4.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/dw4.vgtest (.../trunk) (revision 13981) -@@ -1,3 +1,4 @@ - prereq: test -e dw4 - prog: dw4 - vgopts: --read-var-info=yes -q -+stderr_filter: filter_dw4 -Index: memcheck/tests/err_disable_arange1.c -=================================================================== ---- memcheck/tests/err_disable_arange1.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/err_disable_arange1.c (.../trunk) (revision 13981) -@@ -0,0 +1,41 @@ -+ -+/* Check some aspects of the use of the -+ VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE and -+ VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE macros. */ -+ -+#include -+#include -+ -+#include "../memcheck.h" -+ -+int main ( void ) -+{ -+ volatile int* volatile mem -+ = (volatile int* volatile)malloc(1000 * sizeof(int)); -+ free((void*)mem); -+ -+ // Check that we get an invalid access complaint -+ fprintf(stderr, "\nDoing invalid access. Expect complaint.\n\n"); -+ mem[123] = 0; -+ -+ // Now disable error reporting in the range -+ fprintf(stderr, "\nDisabling address error reporting for the range.\n\n"); -+ VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE(mem, 1000 * sizeof(int)); -+ -+ // Check that we get an invalid access complaint -+ fprintf(stderr, "\nDoing invalid another access. Expect no complaint.\n\n"); -+ mem[456] = 0; -+ -+ // Re-enable reporting on the first byte of one word from the ignore range -+ fprintf(stderr, "\nPartially reenabling address error reporting.\n\n"); -+ VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE(&mem[789], 1); -+ -+ // Check that we get an invalid access complaint -+ fprintf(stderr, "\nDoing a third access. Expect complaint.\n\n"); -+ mem[789] = 0; -+ -+ // And now quit and expect to see a warning about two remaining ranges -+ fprintf(stderr, "\nExiting. Expect warnings of 2 remaining ranges.\n\n"); -+ -+ return 0; -+} -Index: memcheck/tests/err_disable_arange1.stderr.exp -=================================================================== ---- memcheck/tests/err_disable_arange1.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/err_disable_arange1.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,36 @@ -+ -+Doing invalid access. Expect complaint. -+ -+Invalid write of size 4 -+ at 0x........: main (err_disable_arange1.c:19) -+ Address 0x........ is 492 bytes inside a block of size 4,000 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (err_disable_arange1.c:15) -+ -+ -+Disabling address error reporting for the range. -+ -+ -+Doing invalid another access. Expect no complaint. -+ -+ -+Partially reenabling address error reporting. -+ -+ -+Doing a third access. Expect complaint. -+ -+Invalid write of size 4 -+ at 0x........: main (err_disable_arange1.c:35) -+ Address 0x........ is 3,156 bytes inside a block of size 4,000 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (err_disable_arange1.c:15) -+ -+ -+Exiting. Expect warnings of 2 remaining ranges. -+ -+WARNING: exiting program has the following client-requested -+WARNING: address error disablement range(s) still in force, -+WARNING: possibly as a result of some mistake in the use of the -+WARNING: VALGRIND_{DISABLE,ENABLE}_ERROR_REPORTING_IN_RANGE macros. -+ [1] 0x........-0x........ ClientReq -+ [3] 0x........-0x........ ClientReq -Index: memcheck/tests/err_disable_arange1.vgtest -=================================================================== ---- memcheck/tests/err_disable_arange1.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/err_disable_arange1.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prog: err_disable_arange1 -+vgopts: -q -Index: memcheck/tests/filter_dw4 -=================================================================== ---- memcheck/tests/filter_dw4 (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/filter_dw4 (.../trunk) (revision 13981) -@@ -0,0 +1,8 @@ -+#! /bin/sh -+ -+# Size of structure s1 differs between 32-bit and 64-bit programs. -+sed "s/inside a block of size [0-9]* alloc'd/inside a block of size ... alloc'd/" | -+ -+./filter_stderr "$@" -+ -+exit 0 - -Property changes on: memcheck/tests/filter_dw4 -___________________________________________________________________ -Added: svn:executable -## -0,0 +1 ## -+* -\ No newline at end of property -Index: memcheck/tests/filter_memcheck -=================================================================== ---- memcheck/tests/filter_memcheck (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/filter_memcheck (.../trunk) (revision 13981) -@@ -7,7 +7,7 @@ - # A list of files specific to the tool at hand. Line numbers in - # these files will be removed from backtrace entries matching these files. - #--------------------------------------------------------------------- --my @tool_files = ( "mc_replace_strmem.c", "vg_replace_malloc.c" ); -+my @tool_files = ( "vg_replace_strmem.c", "vg_replace_malloc.c" ); - - - sub massage_backtrace_line ($$$) { -Index: memcheck/tests/filter_memcpy -=================================================================== ---- memcheck/tests/filter_memcpy (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/filter_memcpy (.../trunk) (revision 13981) -@@ -1,8 +0,0 @@ --#! /bin/sh -- --# mc_replace_strmem.c intercepts various memcpy glibc versions. --# mc_replace_strmem.c str[n]cpy and __GI_str[n]cpy are the same. --./filter_stderr "$@" | --perl -p -e "s/: memcpy\@\@?GLIBC_[.1-9]+ \(mc_replace_strmem.c:...\)/: memcpy \(mc_replace_strmem.c:...\)/" | --sed -e "s/: __GI_strcpy (mc_replace_strmem.c:/: strcpy (mc_replace_strmem.c:/" | --sed -e "s/: __GI_strncpy (mc_replace_strmem.c:/: strncpy (mc_replace_strmem.c:/" -Index: memcheck/tests/filter_strchr -=================================================================== ---- memcheck/tests/filter_strchr (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/filter_strchr (.../trunk) (revision 13981) -@@ -1,8 +1,6 @@ - #! /bin/sh - --# mc_replace_strmem.c [r]index and [__GI_]str[r]chr are the same. -+# vg_replace_strmem.c [r]index and [__GI_]str[r]chr are the same. - ./filter_stderr "$@" | --sed -e "s/: __GI_strchr (mc_replace_strmem.c:/: strchr (mc_replace_strmem.c:/" | --sed -e "s/: strchr (mc_replace_strmem.c:/: index (mc_replace_strmem.c:/" | --sed -e "s/: __GI_strrchr (mc_replace_strmem.c:/: strrchr (mc_replace_strmem.c:/" | --sed -e "s/: strrchr (mc_replace_strmem.c:/: rindex (mc_replace_strmem.c:/" -+sed -e "s/: strchr (vg_replace_strmem.c:/: index (vg_replace_strmem.c:/; -+ s/: strrchr (vg_replace_strmem.c:/: rindex (vg_replace_strmem.c:/" -Index: memcheck/tests/fprw.stderr.exp-mips32-be -=================================================================== ---- memcheck/tests/fprw.stderr.exp-mips32-be (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/fprw.stderr.exp-mips32-be (.../trunk) (revision 13981) -@@ -0,0 +1,53 @@ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (fprw.c:16) -+ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (fprw.c:17) -+ -+Invalid read of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 4 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid read of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 0 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 4 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 0 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid read of size 4 -+ at 0x........: main (fprw.c:21) -+ Address 0x........ is 0 bytes inside a block of size 4 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:19) -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:21) -+ Address 0x........ is 0 bytes inside a block of size 4 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:19) -+ -+Invalid free() / delete / delete[] / realloc() -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:22) -+ Address 0x........ is not stack'd, malloc'd or (recently) free'd -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:24) -+ Address 0x........ is 0 bytes after a block of size 4 alloc'd -+ at 0x........: malloc (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:23) -+ -Index: memcheck/tests/fprw.stderr.exp-mips32-le -=================================================================== ---- memcheck/tests/fprw.stderr.exp-mips32-le (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/fprw.stderr.exp-mips32-le (.../trunk) (revision 13981) -@@ -0,0 +1,53 @@ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (fprw.c:16) -+ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (fprw.c:17) -+ -+Invalid read of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 0 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid read of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 4 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 0 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:20) -+ Address 0x........ is 4 bytes inside a block of size 8 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:18) -+ -+Invalid read of size 4 -+ at 0x........: main (fprw.c:21) -+ Address 0x........ is 0 bytes inside a block of size 4 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:19) -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:21) -+ Address 0x........ is 0 bytes inside a block of size 4 free'd -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:19) -+ -+Invalid free() / delete / delete[] / realloc() -+ at 0x........: free (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:22) -+ Address 0x........ is not stack'd, malloc'd or (recently) free'd -+ -+Invalid write of size 4 -+ at 0x........: main (fprw.c:24) -+ Address 0x........ is 0 bytes after a block of size 4 alloc'd -+ at 0x........: malloc (vg_replace_malloc.c:...) -+ by 0x........: main (fprw.c:23) -+ -Index: memcheck/tests/memcmptest.stderr.exp -=================================================================== ---- memcheck/tests/memcmptest.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/memcmptest.stderr.exp (.../trunk) (revision 13981) -@@ -1,4 +1,4 @@ - Conditional jump or move depends on uninitialised value(s) -- at 0x........: memcmp (mc_replace_strmem.c:...) -+ at 0x........: memcmp (vg_replace_strmem.c:...) - by 0x........: main (memcmptest.c:13) - -Index: memcheck/tests/memcmptest.stderr.exp2 -=================================================================== ---- memcheck/tests/memcmptest.stderr.exp2 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/memcmptest.stderr.exp2 (.../trunk) (revision 13981) -@@ -1,4 +1,4 @@ - Conditional jump or move depends on uninitialised value(s) -- at 0x........: bcmp (mc_replace_strmem.c:...) -+ at 0x........: bcmp (vg_replace_strmem.c:...) - by 0x........: main (memcmptest.c:13) - -Index: memcheck/tests/origin5-bz2.stderr.exp-glibc218-mips32 -=================================================================== ---- memcheck/tests/origin5-bz2.stderr.exp-glibc218-mips32 (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/origin5-bz2.stderr.exp-glibc218-mips32 (.../trunk) (revision 13981) -@@ -0,0 +1,131 @@ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (origin5-bz2.c:6481) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686) -+ by 0x........: handle_compress (origin5-bz2.c:4750) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686) -+ by 0x........: handle_compress (origin5-bz2.c:4750) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686) -+ by 0x........: handle_compress (origin5-bz2.c:4750) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: mainSort (origin5-bz2.c:2820) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: mainSort (origin5-bz2.c:2823) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: mainSort (origin5-bz2.c:2854) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: mainSort (origin5-bz2.c:2858) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: mainSort (origin5-bz2.c:2963) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: mainSort (origin5-bz2.c:2964) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: fallbackSort (origin5-bz2.c:2269) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 4 -+ at 0x........: fallbackSort (origin5-bz2.c:2275) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (origin5-bz2.c:6512) -+ Uninitialised value was created by a heap allocation -+ at 0x........: malloc (vg_replace_malloc.c:...) -+ by 0x........: g_serviceFn (origin5-bz2.c:6429) -+ by 0x........: default_bzalloc (origin5-bz2.c:4470) -+ by 0x........: BZ2_decompress (origin5-bz2.c:1578) -+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192) -+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678) -+ by 0x........: main (origin5-bz2.c:6498) -+ -Index: memcheck/tests/origin5-bz2.stderr.exp-glibc25-amd64-b -=================================================================== ---- memcheck/tests/origin5-bz2.stderr.exp-glibc25-amd64-b (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/origin5-bz2.stderr.exp-glibc25-amd64-b (.../trunk) (revision 13981) -@@ -0,0 +1,131 @@ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (origin5-bz2.c:6481) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686) -+ by 0x........: handle_compress (origin5-bz2.c:4750) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686) -+ by 0x........: handle_compress (origin5-bz2.c:4750) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: copy_input_until_stop (origin5-bz2.c:4686) -+ by 0x........: handle_compress (origin5-bz2.c:4750) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: mainSort (origin5-bz2.c:2820) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: mainSort (origin5-bz2.c:2823) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: mainSort (origin5-bz2.c:2854) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: mainSort (origin5-bz2.c:2858) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: mainSort (origin5-bz2.c:2963) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: mainSort (origin5-bz2.c:2964) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3105) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: fallbackSort (origin5-bz2.c:2269) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Use of uninitialised value of size 8 -+ at 0x........: fallbackSort (origin5-bz2.c:2275) -+ by 0x........: BZ2_blockSort (origin5-bz2.c:3116) -+ by 0x........: BZ2_compressBlock (origin5-bz2.c:4034) -+ by 0x........: handle_compress (origin5-bz2.c:4753) -+ by 0x........: BZ2_bzCompress (origin5-bz2.c:4822) -+ by 0x........: BZ2_bzBuffToBuffCompress (origin5-bz2.c:5630) -+ by 0x........: main (origin5-bz2.c:6484) -+ Uninitialised value was created by a client request -+ at 0x........: main (origin5-bz2.c:6479) -+ -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: main (origin5-bz2.c:6512) -+ Uninitialised value was created by a heap allocation -+ at 0x........: malloc (vg_replace_malloc.c:...) -+ by 0x........: g_serviceFn (origin5-bz2.c:6429) -+ by 0x........: default_bzalloc (origin5-bz2.c:4470) -+ by 0x........: BZ2_decompress (origin5-bz2.c:1578) -+ by 0x........: BZ2_bzDecompress (origin5-bz2.c:5192) -+ by 0x........: BZ2_bzBuffToBuffDecompress (origin5-bz2.c:5678) -+ by 0x........: main (origin5-bz2.c:6498) -+ -Index: memcheck/tests/overlap.stderr.exp -=================================================================== ---- memcheck/tests/overlap.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/overlap.stderr.exp (.../trunk) (revision 13981) -@@ -1,28 +1,28 @@ - Source and destination overlap in memcpy(0x........, 0x........, 21) -- at 0x........: memcpy (mc_replace_strmem.c:...) -+ at 0x........: memcpy (vg_replace_strmem.c:...) - by 0x........: main (overlap.c:40) - - Source and destination overlap in memcpy(0x........, 0x........, 21) -- at 0x........: memcpy (mc_replace_strmem.c:...) -+ at 0x........: memcpy (vg_replace_strmem.c:...) - by 0x........: main (overlap.c:42) - - Source and destination overlap in strncpy(0x........, 0x........, 21) -- at 0x........: strncpy (mc_replace_strmem.c:...) -+ at 0x........: strncpy (vg_replace_strmem.c:...) - by 0x........: main (overlap.c:45) - - Source and destination overlap in strncpy(0x........, 0x........, 21) -- at 0x........: strncpy (mc_replace_strmem.c:...) -+ at 0x........: strncpy (vg_replace_strmem.c:...) - by 0x........: main (overlap.c:47) - - Source and destination overlap in strcpy(0x........, 0x........) -- at 0x........: strcpy (mc_replace_strmem.c:...) -+ at 0x........: strcpy (vg_replace_strmem.c:...) - by 0x........: main (overlap.c:54) - - Source and destination overlap in strncat(0x........, 0x........, 21) -- at 0x........: strncat (mc_replace_strmem.c:...) -+ at 0x........: strncat (vg_replace_strmem.c:...) - by 0x........: main (overlap.c:112) - - Source and destination overlap in strncat(0x........, 0x........, 21) -- at 0x........: strncat (mc_replace_strmem.c:...) -+ at 0x........: strncat (vg_replace_strmem.c:...) - by 0x........: main (overlap.c:113) - -Index: memcheck/tests/overlap.vgtest -=================================================================== ---- memcheck/tests/overlap.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/overlap.vgtest (.../trunk) (revision 13981) -@@ -1,3 +1,2 @@ - prog: overlap - vgopts: -q --stderr_filter: filter_memcpy -Index: memcheck/tests/reach_thread_register.stderr.exp-mips32 -=================================================================== ---- memcheck/tests/reach_thread_register.stderr.exp-mips32 (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/reach_thread_register.stderr.exp-mips32 (.../trunk) (revision 13981) -@@ -0,0 +1,6 @@ -+Abandoning the helper. -+136 bytes in 1 blocks are definitely lost in loss record ... of ... -+ at 0x........: calloc (vg_replace_malloc.c:...) -+ ... -+ by 0x........: main (reach_thread_register.c:47) -+ -Index: memcheck/tests/reach_thread_register.stderr.exp-mips64 -=================================================================== ---- memcheck/tests/reach_thread_register.stderr.exp-mips64 (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/reach_thread_register.stderr.exp-mips64 (.../trunk) (revision 13981) -@@ -0,0 +1,6 @@ -+Abandoning the helper. -+272 bytes in 1 blocks are definitely lost in loss record ... of ... -+ at 0x........: calloc (vg_replace_malloc.c:...) -+ ... -+ by 0x........: main (reach_thread_register.c:47) -+ -Index: memcheck/tests/strchr.stderr.exp -=================================================================== ---- memcheck/tests/strchr.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/strchr.stderr.exp (.../trunk) (revision 13981) -@@ -1,16 +1,12 @@ - Conditional jump or move depends on uninitialised value(s) -- at 0x........: index (mc_replace_strmem.c:...) -+ at 0x........: index (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:15) - - Conditional jump or move depends on uninitialised value(s) -- at 0x........: index (mc_replace_strmem.c:...) -+ at 0x........: index (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:15) - - Conditional jump or move depends on uninitialised value(s) -- at 0x........: rindex (mc_replace_strmem.c:...) -+ at 0x........: rindex (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:16) - --Conditional jump or move depends on uninitialised value(s) -- at 0x........: rindex (mc_replace_strmem.c:...) -- by 0x........: main (strchr.c:16) -- -Index: memcheck/tests/strchr.stderr.exp-darwin -=================================================================== ---- memcheck/tests/strchr.stderr.exp-darwin (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/strchr.stderr.exp-darwin (.../trunk) (revision 13981) -@@ -1,12 +0,0 @@ --Conditional jump or move depends on uninitialised value(s) -- at 0x........: strchr (mc_replace_strmem.c:...) -- by 0x........: main (strchr.c:15) -- --Conditional jump or move depends on uninitialised value(s) -- at 0x........: strchr (mc_replace_strmem.c:...) -- by 0x........: main (strchr.c:15) -- --Conditional jump or move depends on uninitialised value(s) -- at 0x........: strrchr (mc_replace_strmem.c:...) -- by 0x........: main (strchr.c:16) -- -Index: memcheck/tests/strchr.stderr.exp2 -=================================================================== ---- memcheck/tests/strchr.stderr.exp2 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/strchr.stderr.exp2 (.../trunk) (revision 13981) -@@ -1,12 +1,16 @@ - Conditional jump or move depends on uninitialised value(s) -- at 0x........: index (mc_replace_strmem.c:...) -+ at 0x........: index (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:15) - - Conditional jump or move depends on uninitialised value(s) -- at 0x........: index (mc_replace_strmem.c:...) -+ at 0x........: index (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:15) - - Conditional jump or move depends on uninitialised value(s) -- at 0x........: rindex (mc_replace_strmem.c:...) -+ at 0x........: rindex (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:16) - -+Conditional jump or move depends on uninitialised value(s) -+ at 0x........: rindex (vg_replace_strmem.c:...) -+ by 0x........: main (strchr.c:16) -+ -Index: memcheck/tests/strchr.stderr.exp3 -=================================================================== ---- memcheck/tests/strchr.stderr.exp3 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/strchr.stderr.exp3 (.../trunk) (revision 13981) -@@ -1,12 +1,12 @@ - Conditional jump or move depends on uninitialised value(s) -- at 0x........: __GI_strchr (mc_replace_strmem.c:...) -+ at 0x........: strchr (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:15) - - Conditional jump or move depends on uninitialised value(s) -- at 0x........: __GI_strchr (mc_replace_strmem.c:...) -+ at 0x........: strchr (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:15) - - Conditional jump or move depends on uninitialised value(s) -- at 0x........: __GI_strrchr (mc_replace_strmem.c:...) -+ at 0x........: strrchr (vg_replace_strmem.c:...) - by 0x........: main (strchr.c:16) - -Index: memcheck/tests/suppfree.c -=================================================================== ---- memcheck/tests/suppfree.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/suppfree.c (.../trunk) (revision 13981) -@@ -22,9 +22,17 @@ - bbb(x); - } - --int main ( void ) -+void ok_to_suppress_double_free_from_this_fun(char* y) - { -+ aaa(y); -+} -+ -+int main ( int argc, char*argv[] ) -+{ - char* x = malloc(10); -+ char* y = malloc(10); -+ if (argc > 1) -+ ok_to_suppress_double_free_from_this_fun(y); - aaa(x); - return 0; - } -Index: memcheck/tests/suppfree.stderr.exp -=================================================================== ---- memcheck/tests/suppfree.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/suppfree.stderr.exp (.../trunk) (revision 13981) -@@ -4,7 +4,7 @@ - by 0x........: ccc (suppfree.c:12) - by 0x........: bbb (suppfree.c:17) - by 0x........: aaa (suppfree.c:22) -- by 0x........: main (suppfree.c:28) -+ by 0x........: main (suppfree.c:36) - Address 0x........ is 0 bytes inside a block of size 10 free'd - at 0x........: free (vg_replace_malloc.c:...) - by 0x........: ddd (suppfree.c:6) -@@ -11,5 +11,5 @@ - by 0x........: ccc (suppfree.c:12) - by 0x........: bbb (suppfree.c:17) - by 0x........: aaa (suppfree.c:22) -- by 0x........: main (suppfree.c:28) -+ by 0x........: main (suppfree.c:36) - -Index: memcheck/tests/suppfreecollision.stderr.exp -=================================================================== -Index: memcheck/tests/suppfreecollision.supp -=================================================================== ---- memcheck/tests/suppfreecollision.supp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/suppfreecollision.supp (.../trunk) (revision 13981) -@@ -0,0 +1,11 @@ -+{ -+ suppressnondangerouserror -+ Memcheck:Free -+ fun:free -+ fun:ddd -+ fun:ccc -+ fun:bbb -+ fun:aaa -+ fun:ok_to_suppress_double_free_from_this_fun -+ fun:main -+} -Index: memcheck/tests/suppfreecollision.vgtest -=================================================================== ---- memcheck/tests/suppfreecollision.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ memcheck/tests/suppfreecollision.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,13 @@ -+# this test the case of two errors, one considered not dangerous and -+# suppressed, the other considered dangerous, and the user does -+# not want to supress it. -+# The suppression entry only match the non dangerous error. -+# However, when a medium resolution is used to compare 2 errors, -+# only the last 4 calls are used to determine that two errors are similar -+# So, the nondangerous suppressed error "absorbs and hides" the dangerous -+# error. -+# This side effect of a medium (or low) resolution for error matching -+# is I guess unexpected by most users. -+prog: suppfree -+args: activatenondangerouserror -+vgopts: --suppressions=suppfreecollision.supp -q -Index: memcheck/tests/test-plo-yes.vgtest -=================================================================== ---- memcheck/tests/test-plo-yes.vgtest (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/test-plo-yes.vgtest (.../trunk) (revision 13981) -@@ -1,3 +1,3 @@ --prereq: test ! `../../tests/arch_test ppc32` && ! `../../tests/arch_test ppc64` && ! `../../tests/arch_test s390x` -+prereq: test ! `../../tests/arch_test ppc32` && ! `../../tests/arch_test ppc64` && ! `../../tests/arch_test s390x` && ! `../../tests/mips_features mips-be` - prog: test-plo - vgopts: -q --partial-loads-ok=yes -Index: memcheck/tests/unit_libcbase.c -=================================================================== ---- memcheck/tests/unit_libcbase.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/unit_libcbase.c (.../trunk) (revision 13981) -@@ -58,6 +58,8 @@ - // On PPC/Linux VKI_PAGE_SIZE is a variable, not a macro. - #if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) - unsigned long VKI_PAGE_SIZE = 1UL << 12; -+#elif defined(VGP_arm64_linux) -+unsigned long VKI_PAGE_SIZE = 1UL << 16; - #endif - - void test_VG_IS_XYZ_ALIGNED(void) -Index: memcheck/tests/vbit-test/irops.c -=================================================================== ---- memcheck/tests/vbit-test/irops.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/vbit-test/irops.c (.../trunk) (revision 13981) -@@ -10,12 +10,12 @@ - That is not necessary but helpful when supporting a new architecture. - */ - static irop_t irops[] = { -- { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -- { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_Add8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_Add16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Add32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Add64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_Sub8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_Sub16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Sub32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Sub64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_Mul8, UNDEF_LEFT), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -@@ -22,18 +22,18 @@ - { DEFOP(Iop_Mul16, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Mul32, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Mul64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert -- { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -- { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_Or8, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_Or16, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Or32, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Or64, UNDEF_OR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -- { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_And8, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_And16, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_And32, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -- { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_And64, UNDEF_AND), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_Xor8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_Xor16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Xor32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_Xor64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Shl8, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Shl16, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_Shl32, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -@@ -47,7 +47,7 @@ - { DEFOP(Iop_Sar32, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts - { DEFOP(Iop_CmpEQ8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -- { DEFOP(Iop_CmpEQ16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_CmpEQ16, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpEQ32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpEQ64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_CmpNE8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -@@ -57,7 +57,7 @@ - { DEFOP(Iop_Not8, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Not16, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_Not32, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_Not64, UNDEF_SAME), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpEQ8, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpEQ16, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_CasCmpEQ32, UNDEF_NONE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -@@ -76,23 +76,23 @@ - { DEFOP(Iop_MullS32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - // s390 has signed multiplication of 64-bit values but the result - // is 64-bit (not 128-bit). So we cannot test this op standalone. -- { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert -- { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -- { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -- { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert -- { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts -- { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -- { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -- { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc, mips assert -- { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc, mips assert -- { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert -- { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -- { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32 asserts -+ { DEFOP(Iop_MullS64, UNDEF_LEFT), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert -+ { DEFOP(Iop_MullU8, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, -+ { DEFOP(Iop_MullU16, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, -+ { DEFOP(Iop_MullU32, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_MullU64, UNDEF_LEFT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert -+ { DEFOP(Iop_Clz64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32 asserts -+ { DEFOP(Iop_Clz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, -+ { DEFOP(Iop_Ctz64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, -+ { DEFOP(Iop_Ctz32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, -+ { DEFOP(Iop_CmpLT32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, -+ { DEFOP(Iop_CmpLT64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert -+ { DEFOP(Iop_CmpLE32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, -+ { DEFOP(Iop_CmpLE64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc, mips assert -+ { DEFOP(Iop_CmpLT32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, -+ { DEFOP(Iop_CmpLT64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 1 }, // ppc32, mips assert -+ { DEFOP(Iop_CmpLE32U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 =1, .mips64 = 1 }, -+ { DEFOP(Iop_CmpLE64U, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 =0, .mips64 = 0 }, // ppc32 asserts - { DEFOP(Iop_CmpNEZ8, UNDEF_ALL), }, // not supported by mc_translate - { DEFOP(Iop_CmpNEZ16, UNDEF_ALL), }, // not supported by mc_translate - { DEFOP(Iop_CmpNEZ32, UNDEF_ALL), }, // not supported by mc_translate -@@ -118,8 +118,8 @@ - { DEFOP(Iop_DivS32E, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - // On s390 the DivMod operations always appear in a certain context - // So they cannot be tested in isolation on that platform. -- { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_DivModU64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_DivModS64to32, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_DivModU128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_DivModS128to64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_DivModS64to64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts -@@ -129,7 +129,7 @@ - { DEFOP(Iop_16Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_16Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert - { DEFOP(Iop_32Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_8Sto16, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_16Sto32, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -@@ -136,13 +136,13 @@ - { DEFOP(Iop_16Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert - { DEFOP(Iop_32Sto64, UNDEF_SEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_64to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert -- { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_32to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_64to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert -- { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_16to8, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_16HIto8, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_8HLto16, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel - { DEFOP(Iop_32to16, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, -+ { DEFOP(Iop_32HIto16, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_16HLto32, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc isel - { DEFOP(Iop_64to32, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_64HIto32, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, -@@ -151,15 +151,15 @@ - { DEFOP(Iop_128HIto64, UNDEF_UPPER), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_64HLto128, UNDEF_CONCAT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_Not1, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_32to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_64to1, UNDEF_TRUNC), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32, mips assert -- { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_1Uto8, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_1Uto32, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_1Uto64, UNDEF_ZEXT), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 assert -- { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_1Sto8, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_1Sto16, UNDEF_ALL), }, // not handled by mc_translate -- { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -- { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_1Sto32, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, -+ { DEFOP(Iop_1Sto64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_AddF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_SubF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_MulF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -@@ -178,11 +178,11 @@ - { DEFOP(Iop_AbsF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_SqrtF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts - { DEFOP(Iop_SqrtF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, -- { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_CmpF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_CmpF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // mips asserts - { DEFOP(Iop_CmpF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, -- { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 1 }, // mips asserts -+ { DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, - { DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, - { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0, .mips64 = 0 }, -@@ -565,9 +565,9 @@ - { DEFOP(Iop_CmpUN32Fx4, UNDEF_UNKNOWN), }, - { DEFOP(Iop_CmpGT32Fx4, UNDEF_UNKNOWN), }, - { DEFOP(Iop_CmpGE32Fx4, UNDEF_UNKNOWN), }, -- { DEFOP(Iop_Abs32Fx4, UNDEF_UNKNOWN), }, - { DEFOP(Iop_PwMax32Fx4, UNDEF_UNKNOWN), }, - { DEFOP(Iop_PwMin32Fx4, UNDEF_UNKNOWN), }, -+ { DEFOP(Iop_Abs32Fx4, UNDEF_UNKNOWN), }, - { DEFOP(Iop_Sqrt32Fx4, UNDEF_UNKNOWN), }, - { DEFOP(Iop_RSqrt32Fx4, UNDEF_UNKNOWN), }, - { DEFOP(Iop_Neg32Fx4, UNDEF_UNKNOWN), }, -@@ -614,9 +614,11 @@ - { DEFOP(Iop_CmpLT64Fx2, UNDEF_UNKNOWN), }, - { DEFOP(Iop_CmpLE64Fx2, UNDEF_UNKNOWN), }, - { DEFOP(Iop_CmpUN64Fx2, UNDEF_UNKNOWN), }, -- { DEFOP(Iop_Recip64Fx2, UNDEF_UNKNOWN), }, -+ { DEFOP(Iop_Abs64Fx2, UNDEF_UNKNOWN), }, - { DEFOP(Iop_Sqrt64Fx2, UNDEF_UNKNOWN), }, - { DEFOP(Iop_RSqrt64Fx2, UNDEF_UNKNOWN), }, -+ { DEFOP(Iop_Neg64Fx2, UNDEF_UNKNOWN), }, -+ { DEFOP(Iop_Recip64Fx2, UNDEF_UNKNOWN), }, - { DEFOP(Iop_Add64F0x2, UNDEF_UNKNOWN), }, - { DEFOP(Iop_Sub64F0x2, UNDEF_UNKNOWN), }, - { DEFOP(Iop_Mul64F0x2, UNDEF_UNKNOWN), }, -@@ -635,6 +637,10 @@ - { DEFOP(Iop_64HLtoV128, UNDEF_UNKNOWN), }, - { DEFOP(Iop_64UtoV128, UNDEF_UNKNOWN), }, - { DEFOP(Iop_SetV128lo64, UNDEF_UNKNOWN), }, -+ { DEFOP(Iop_ZeroHI64ofV128, UNDEF_UNKNOWN) }, -+ { DEFOP(Iop_ZeroHI96ofV128, UNDEF_UNKNOWN) }, -+ { DEFOP(Iop_ZeroHI112ofV128, UNDEF_UNKNOWN) }, -+ { DEFOP(Iop_ZeroHI120ofV128, UNDEF_UNKNOWN) }, - { DEFOP(Iop_32UtoV128, UNDEF_UNKNOWN), }, - { DEFOP(Iop_V128to32, UNDEF_UNKNOWN), }, - { DEFOP(Iop_SetV128lo32, UNDEF_UNKNOWN), }, -Index: memcheck/tests/x86-linux/scalar.stderr.exp -=================================================================== ---- memcheck/tests/x86-linux/scalar.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ memcheck/tests/x86-linux/scalar.stderr.exp (.../trunk) (revision 13981) -@@ -2008,7 +2008,7 @@ - by 0x........: main (scalar.c:752) - Address 0x........ is not stack'd, malloc'd or (recently) free'd - --Syscall param poll(ufds.reventss) points to unaddressable byte(s) -+Syscall param poll(ufds.revents) points to unaddressable byte(s) - ... - by 0x........: main (scalar.c:752) - Address 0x........ is not stack'd, malloc'd or (recently) free'd -@@ -3602,11 +3602,21 @@ - ... - by 0x........: main (scalar.c:1158) - --Syscall param timer_create(evp) points to unaddressable byte(s) -+Syscall param timer_create(evp.sigev_value) points to unaddressable byte(s) - ... - by 0x........: main (scalar.c:1158) - Address 0x........ is not stack'd, malloc'd or (recently) free'd - -+Syscall param timer_create(evp.sigev_signo) points to unaddressable byte(s) -+ ... -+ by 0x........: main (scalar.c:1158) -+ Address 0x........ is not stack'd, malloc'd or (recently) free'd -+ -+Syscall param timer_create(evp.sigev_notify) points to unaddressable byte(s) -+ ... -+ by 0x........: main (scalar.c:1158) -+ Address 0x........ is not stack'd, malloc'd or (recently) free'd -+ - Syscall param timer_create(timerid) points to unaddressable byte(s) - ... - by 0x........: main (scalar.c:1158) -Index: mpi/Makefile.am -=================================================================== ---- mpi/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ mpi/Makefile.am (.../trunk) (revision 13981) -@@ -69,3 +69,5 @@ - - install-exec-local: install-noinst_PROGRAMS install-noinst_DSYMS - -+uninstall-local: uninstall-noinst_PROGRAMS uninstall-noinst_DSYMS -+ -Index: none/tests/allexec_prepare_prereq -=================================================================== ---- none/tests/allexec_prepare_prereq (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/allexec_prepare_prereq (.../trunk) (revision 13981) -@@ -31,7 +31,7 @@ - pair x86 amd64 - pair ppc32 ppc64 - pair s390x_unexisting_in_32bits s390x --pair arm arm_unexisting_in_64bits -+pair arm arm64 - pair mips32 mips64 - - exit 0 -Index: none/tests/amd64 -=================================================================== ---- none/tests/amd64 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/amd64 (.../trunk) (revision 13981) - -Property changes on: none/tests/amd64 -___________________________________________________________________ -Modified: svn:ignore -## -61,4 +61,5 ## - sse4-64 - ssse3_misaligned - tm1 -+xacq_xrel - xadd -Index: none/tests/amd64/Makefile.am -=================================================================== ---- none/tests/amd64/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/amd64/Makefile.am (.../trunk) (revision 13981) -@@ -56,6 +56,7 @@ - loopnel.stderr.exp loopnel.stdout.exp loopnel.vgtest \ - lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \ - movbe.stderr.exp movbe.stdout.exp movbe.vgtest \ -+ mpx.stderr.exp mpx.stdout.exp mpx.vgtest \ - nan80and64.stderr.exp nan80and64.stdout.exp nan80and64.vgtest \ - nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \ - nibz_bennee_mmap.vgtest \ -@@ -80,6 +81,7 @@ - slahf-amd64.stderr.exp slahf-amd64.stdout.exp \ - slahf-amd64.vgtest \ - tm1.vgtest tm1.stderr.exp tm1.stdout.exp \ -+ x87trigOOR.vgtest x87trigOOR.stderr.exp x87trigOOR.stdout.exp \ - xacq_xrel.stderr.exp xacq_xrel.stdout.exp xacq_xrel.vgtest \ - xadd.stderr.exp xadd.stdout.exp xadd.vgtest - -@@ -96,6 +98,7 @@ - smc1 \ - sbbmisc \ - nibz_bennee_mmap \ -+ x87trigOOR \ - xadd - if BUILD_ADDR32_TESTS - check_PROGRAMS += asorep -@@ -131,7 +134,11 @@ - if BUILD_MOVBE_TESTS - check_PROGRAMS += movbe - endif -+if BUILD_MPX_TESTS -+ check_PROGRAMS += mpx -+endif - -+ - # DDD: these need to be made to work on Darwin like the x86/ ones were. - if ! VGCONF_OS_IS_DARWIN - check_PROGRAMS += \ -Index: none/tests/amd64/gen_insn_test.pl -=================================================================== ---- none/tests/amd64/gen_insn_test.pl (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/amd64/gen_insn_test.pl (.../trunk) (revision 13981) -@@ -850,6 +850,7 @@ - } - - # print qq| \"frstor %$stateargnum\\n\"\n|; -+ print qq| \"cld\\n\"\n|; - - print qq| :|; - -Index: none/tests/amd64/mpx.c -=================================================================== ---- none/tests/amd64/mpx.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/amd64/mpx.c (.../trunk) (revision 13981) -@@ -0,0 +1,38 @@ -+int -+main (int argc, char **argv) -+{ -+ // Since MPX is disabled all these are just NOPS. -+ // Some of these instructions are just random. -+ // Once the GCC support is merged creating real test cases will be easier. -+ // http://gcc.gnu.org/wiki/Intel%20MPX%20support%20in%20the%20GCC%20compiler -+ -+ // This is what ld.so does in _dl_runtime_resolve to save the bnds. -+ asm ("bndmov %bnd0, (%rsp)"); -+ asm ("bndmov %bnd1, 16(%rsp)"); -+ asm ("bndmov %bnd2, 32(%rsp)"); -+ asm ("bndmov %bnd3, 48(%rsp)"); -+ -+ // Create a bnd, check lower and upper... -+ asm ("bndmk (%rax,%rdx), %bnd0"); -+ asm ("bndcl (%rax,%rdi,4), %bnd0"); -+ asm ("bndcu 3(%rax,%rdi,4), %bnd0"); -+ asm ("bndcn 3(%rax,%rdi,4), %bnd0"); -+ -+ // Load bnd pointer and update... -+ asm ("bndldx 3(%rbx,%rdx), %bnd2"); -+ asm ("bndstx %bnd2, 3(,%r12,1)"); -+ -+ // "bnd" prefixed call, return and jmp... -+ asm ("bnd call foo\n\ -+ bnd jmp end\n\ -+ foo: bnd ret\n\ -+ end: nop"); -+ -+ // And set the bnds back... -+ asm ("bndmov 48(%rsp), %bnd3"); -+ asm ("bndmov 32(%rsp), %bnd2"); -+ asm ("bndmov 16(%rsp), %bnd1"); -+ asm ("bndmov (%rsp), %bnd0"); -+ -+ return 0; -+} -Index: none/tests/amd64/mpx.stderr.exp -=================================================================== -Index: none/tests/amd64/mpx.stdout.exp -=================================================================== -Index: none/tests/amd64/mpx.vgtest -=================================================================== ---- none/tests/amd64/mpx.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/amd64/mpx.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+prog: mpx -+prereq: test -x mpx -+vgopts: -q -Index: none/tests/amd64/tm1.c -=================================================================== ---- none/tests/amd64/tm1.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/amd64/tm1.c (.../trunk) (revision 13981) -@@ -58,5 +58,9 @@ - : : "r"(&n) : "cc", "memory" - ); - */ -+ -+ __asm__ __volatile__( "xabort $0x1" ); -+ printf("xabort: outside transaction is nop.\n"); -+ - return 0; - } -Index: none/tests/amd64/tm1.stdout.exp -=================================================================== ---- none/tests/amd64/tm1.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/amd64/tm1.stdout.exp (.../trunk) (revision 13981) -@@ -1,2 +1,3 @@ - transactionally_apply: ok = 0 (expected 0) - xtest: rflags.Z = 1 (expected 1) -+xabort: outside transaction is nop. -Index: none/tests/amd64/x87trigOOR.c -=================================================================== ---- none/tests/amd64/x87trigOOR.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/amd64/x87trigOOR.c (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+link ../x86/x87trigOOR.c -\ No newline at end of file - -Property changes on: none/tests/amd64/x87trigOOR.c -___________________________________________________________________ -Added: svn:special -## -0,0 +1 ## -+* -\ No newline at end of property -Index: none/tests/amd64/x87trigOOR.stderr.exp -=================================================================== ---- none/tests/amd64/x87trigOOR.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/amd64/x87trigOOR.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+ -+ -Index: none/tests/amd64/x87trigOOR.stdout.exp -=================================================================== ---- none/tests/amd64/x87trigOOR.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/amd64/x87trigOOR.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,72 @@ -+fsin 0.000000e+00 --> 0.000000e+00 3.141593e+00 0000 -+fsin 1.230000e-01 --> 1.226901e-01 3.141593e+00 0000 -+fsin -4.560000e-01 --> -4.403604e-01 3.141593e+00 0000 -+fsin 3.700000e+01 --> -6.435381e-01 3.141593e+00 0000 -+fsin -5.300000e+01 --> -3.959252e-01 3.141593e+00 0000 -+ -+fsin 8.301035e+18 --> -1.249775e-01 3.141593e+00 0000 -+fsin 9.223363e+18 --> 2.344065e-01 3.141593e+00 0000 -+fsin 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fsin 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fsin 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fsin -8.301035e+18 --> 1.249775e-01 3.141593e+00 0000 -+fsin -9.223363e+18 --> -2.344065e-01 3.141593e+00 0000 -+fsin -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fsin -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fsin -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -+fcos 0.000000e+00 --> 1.000000e+00 3.141593e+00 0000 -+fcos 1.230000e-01 --> 9.924450e-01 3.141593e+00 0000 -+fcos -4.560000e-01 --> 8.978211e-01 3.141593e+00 0000 -+fcos 3.700000e+01 --> 7.654141e-01 3.141593e+00 0000 -+fcos -5.300000e+01 --> -9.182828e-01 3.141593e+00 0000 -+ -+fcos 8.301035e+18 --> -9.921596e-01 3.141593e+00 0000 -+fcos 9.223363e+18 --> 9.721387e-01 3.141593e+00 0000 -+fcos 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fcos 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fcos 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fcos -8.301035e+18 --> -9.921596e-01 3.141593e+00 0000 -+fcos -9.223363e+18 --> 9.721387e-01 3.141593e+00 0000 -+fcos -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fcos -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fcos -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -+fsincos 0.000000e+00 --> 1.000000e+00 0.000000e+00 0000 -+fsincos 1.230000e-01 --> 9.924450e-01 1.226901e-01 0000 -+fsincos -4.560000e-01 --> 8.978211e-01 -4.403604e-01 0000 -+fsincos 3.700000e+01 --> 7.654141e-01 -6.435381e-01 0000 -+fsincos -5.300000e+01 --> -9.182828e-01 -3.959252e-01 0000 -+ -+fsincos 8.301035e+18 --> -9.921596e-01 -1.249775e-01 0000 -+fsincos 9.223363e+18 --> 9.721387e-01 2.344065e-01 0000 -+fsincos 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fsincos 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fsincos 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fsincos -8.301035e+18 --> -9.921596e-01 1.249775e-01 0000 -+fsincos -9.223363e+18 --> 9.721387e-01 -2.344065e-01 0000 -+fsincos -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fsincos -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fsincos -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -+fptan 0.000000e+00 --> 1.000000e+00 0.000000e+00 0000 -+fptan 1.230000e-01 --> 1.000000e+00 1.236241e-01 0000 -+fptan -4.560000e-01 --> 1.000000e+00 -4.904767e-01 0000 -+fptan 3.700000e+01 --> 1.000000e+00 -8.407713e-01 0000 -+fptan -5.300000e+01 --> 1.000000e+00 4.311582e-01 0000 -+ -+fptan 8.301035e+18 --> 1.000000e+00 1.259651e-01 0000 -+fptan 9.223363e+18 --> 1.000000e+00 2.411246e-01 0000 -+fptan 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fptan 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fptan 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fptan -8.301035e+18 --> 1.000000e+00 -1.259651e-01 0000 -+fptan -9.223363e+18 --> 1.000000e+00 -2.411246e-01 0000 -+fptan -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fptan -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fptan -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -Index: none/tests/amd64/x87trigOOR.vgtest -=================================================================== ---- none/tests/amd64/x87trigOOR.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/amd64/x87trigOOR.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+prog: x87trigOOR -Index: none/tests/arm/Makefile.am -=================================================================== ---- none/tests/arm/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/arm/Makefile.am (.../trunk) (revision 13981) -@@ -14,7 +14,8 @@ - v6media.stdout.exp v6media.stderr.exp v6media.vgtest \ - vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \ - vcvt_fixed_float_VFP.vgtest \ -- vfp.stdout.exp vfp.stderr.exp vfp.vgtest -+ vfp.stdout.exp vfp.stderr.exp vfp.vgtest \ -+ vfpv4_fma.stdout.exp vfpv4_fma.stderr.exp vfpv4_fma.vgtest - - check_PROGRAMS = \ - allexec \ -@@ -27,7 +28,8 @@ - v6intThumb \ - v6media \ - vcvt_fixed_float_VFP \ -- vfp -+ vfp \ -+ vfpv4_fma - - AM_CFLAGS += @FLAG_M32@ - AM_CXXFLAGS += @FLAG_M32@ -@@ -63,3 +65,5 @@ - intdiv_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a15 -mthumb - ldrt_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a8 -mthumb - ldrt_arm_CFLAGS = $(AM_CFLAGS) -g -mcpu=cortex-a8 -marm -+ -+vfpv4_fma_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a15 -mfpu=vfpv4 -marm -Index: none/tests/arm/v6intThumb.c -=================================================================== ---- none/tests/arm/v6intThumb.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/arm/v6intThumb.c (.../trunk) (revision 13981) -@@ -5,7 +5,7 @@ - - #include - --static int gen_cvin(cvin) -+static int gen_cvin(int cvin) - { - int r = ((cvin & 2) ? (1<<29) : 0) | ((cvin & 1) ? (1<<28) : 0); - r |= (1 << 31) | (1 << 30); -@@ -218,6 +218,123 @@ - ); \ - } - -+// Tests misaligned access via PC+$#imm -+#define TESTINSTPCMISALIGNED(instruction, RD, label, cvin) \ -+{ \ -+ unsigned int out; \ -+ unsigned int cpsr; \ -+ __asm__ volatile(\ -+ ".align 4;" \ -+ "msr cpsr_f, %2;" \ -+ "mov " #RD ", #0;" \ -+ ".align 2;" \ -+ ".thumb;" \ -+ ".syntax unified;" \ -+ "nop;" \ -+ instruction ";" \ -+ "b .Lend" #label ";" \ -+ ".align 4;" \ -+ #label ": " \ -+ ".word 0x8191881b;" \ -+ ".word 0x18fe9c93;" \ -+ ".word 0x00000000;" \ -+ ".word 0x00000000;" \ -+ ".Lend" #label ":" \ -+ "mov %0, " #RD ";" \ -+ "mrs %1, cpsr;" \ -+ : "=&r" (out), "=&r" (cpsr) \ -+ : "r" (gen_cvin(cvin)) \ -+ : #RD, "cc", "memory" \ -+ ); \ -+ printf("%s :: rd 0x%08x, cpsr 0x%08x %c%c%c%c\n", \ -+ instruction, out, \ -+ cpsr & 0xffff0000, \ -+ ((1<<31) & cpsr) ? 'N' : ' ', \ -+ ((1<<30) & cpsr) ? 'Z' : ' ', \ -+ ((1<<29) & cpsr) ? 'C' : ' ', \ -+ ((1<<28) & cpsr) ? 'V' : ' ' \ -+ ); \ -+} -+ -+// this one uses d0, s0 and s2 (hardcoded) -+#define TESTINSTPCMISALIGNED_DWORDOUT(instruction, label, cvin, extratrash) \ -+{ \ -+ unsigned int out; \ -+ unsigned int out2; \ -+ unsigned int cpsr; \ -+ __asm__ volatile(\ -+ ".align 4;" \ -+ "msr cpsr_f, %3;" \ -+ ".align 2;" \ -+ ".thumb;" \ -+ ".syntax unified;" \ -+ "nop;" \ -+ instruction ";" \ -+ "b .Lend" #label ";" \ -+ ".align 4;" \ -+ #label ": " \ -+ ".word 0x8191881b;" \ -+ ".word 0x18fe9c93;" \ -+ ".word 0x00000000;" \ -+ ".word 0x00000000;" \ -+ ".Lend" #label ":" \ -+ "vmov %0, s0;" \ -+ "vmov %1, s1;" \ -+ "mrs %2, cpsr;" \ -+ : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \ -+ : "r" (gen_cvin(cvin)) \ -+ : "cc", "memory", "s0", "s1", extratrash \ -+ ); \ -+ printf("%s :: s0 0x%08x s1 0x%08x, cpsr 0x%08x %c%c%c%c\n", \ -+ instruction, out, out2, \ -+ cpsr & 0xffff0000, \ -+ ((1<<31) & cpsr) ? 'N' : ' ', \ -+ ((1<<30) & cpsr) ? 'Z' : ' ', \ -+ ((1<<29) & cpsr) ? 'C' : ' ', \ -+ ((1<<28) & cpsr) ? 'V' : ' ' \ -+ ); \ -+} -+ -+#define TESTINSTPCMISALIGNED_2OUT(instruction, RD, RD2, label, cvin) \ -+{ \ -+ unsigned int out; \ -+ unsigned int out2; \ -+ unsigned int cpsr; \ -+ __asm__ volatile(\ -+ ".align 4;" \ -+ "msr cpsr_f, %3;" \ -+ "mov " #RD ", #0;" \ -+ "mov " #RD2 ", #0;" \ -+ ".align 2;" \ -+ ".thumb;" \ -+ ".syntax unified;" \ -+ "nop;" \ -+ instruction ";" \ -+ "b .Lend" #label ";" \ -+ ".align 4;" \ -+ #label ": " \ -+ ".word 0x8191881b;" \ -+ ".word 0x18fe9c93;" \ -+ ".word 0x00000000;" \ -+ ".word 0x00000000;" \ -+ ".Lend" #label ":" \ -+ "mov %0, " #RD ";" \ -+ "mov %1, " #RD2 ";" \ -+ "mrs %2, cpsr;" \ -+ : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \ -+ : "r" (gen_cvin(cvin)) \ -+ : #RD, #RD2, "cc", "memory" \ -+ ); \ -+ printf("%s :: rd 0x%08x rd2 0x%08x, cpsr 0x%08x %c%c%c%c\n", \ -+ instruction, out, out2, \ -+ cpsr & 0xffff0000, \ -+ ((1<<31) & cpsr) ? 'N' : ' ', \ -+ ((1<<30) & cpsr) ? 'Z' : ' ', \ -+ ((1<<29) & cpsr) ? 'C' : ' ', \ -+ ((1<<28) & cpsr) ? 'V' : ' ' \ -+ ); \ -+} -+ - /* helpers */ - #define NOCARRY { int cv = 0; { - #define TESTCARRY { int cv = 0; for (cv = 0; cv < 4; cv++) { -@@ -228,6 +345,57 @@ - /////////////////////////////////////////////////////////// - /////////////////////////////////////////////////////////// - -+__attribute__((noinline)) -+void test_ldr_pc(void) { -+ // special case of ldr PC, [rN, +imm?] -+ printf("tests for instructions modifying pc (ldr pc, add pc)\n"); -+ { -+ unsigned int out; -+ unsigned int cpsr; -+ unsigned char tmpbuff[512]; // we use tmpbuff+432 -+ int cvin = 0; -+ -+ __asm__ volatile( -+ ".thumb;\n" -+ ".syntax unified ;\n" -+ "msr cpsr_f, %3 ;\n" -+ "mov r9, %2 ;\n" -+ "movw r2, #:lower16:.ldrwpclabel1 ;\n" -+ "movt r2, #:upper16:.ldrwpclabel1 ;\n" -+ "mov r0, #1 ;\n" -+ "orr r2, r0 ;\n" // set thumb bit to 1 -+ "str r2, [r9, +#432] ;\n" -+ "bl .ldrwpclabel_continue ;\n" -+ ".align 4 ;\n" -+ ".ldrwpclabel1: \n" -+ "mov r1, #42 ;\n" // expected output value -+ "bl .ldrwpclabel_end ;\n" -+ ".ldrwpclabel_continue: \n" -+ "ldr.w pc, [r9, +#432] ;\n" -+ "mov r1, #0 ;\n" // should never get here -+ ".ldrwpclabel_end: \n" -+ "mov %0, r1 ;\n" -+ "mrs %1, cpsr ;\n" -+ : "=r"(out), "=r"(cpsr) -+ : "r"(tmpbuff), "r"(gen_cvin(cvin)) -+ : "r9", "r2", "r0", "r1", "cc", "memory" -+ ); -+ -+ // print -+ printf("ldr.w pc, [r9, +#432] :: r1 0x%08x c:v-in %d, " -+ "cpsr 0x%08x %c%c%c%c\n", \ -+ out, \ -+ cvin, \ -+ cpsr & 0xffff0000, \ -+ ((1<<31) & cpsr) ? 'N' : ' ', \ -+ ((1<<30) & cpsr) ? 'Z' : ' ', \ -+ ((1<<29) & cpsr) ? 'C' : ' ', \ -+ ((1<<28) & cpsr) ? 'V' : ' ' \ -+ ); \ -+ -+ } -+} -+ - static int old_main(void) - { - -@@ -457,6 +625,31 @@ - TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, cv); - TESTCARRYEND - -+ printf("literal access [PC+#imm]\n"); -+ NOCARRY -+ // this should result in r1=0 -+ TESTINSTPCMISALIGNED("adr.w r1, label_magic_adrw; and r1, r1, #0x3", -+ r1, label_magic_adrw, cv); -+ // omitting LDC/LDC2 -+ TESTINSTPCMISALIGNED("ldr r1, label_magic_ldr", -+ r1, label_magic_ldr, cv); -+ TESTINSTPCMISALIGNED("ldrb r1, label_magic_ldrb", -+ r1, label_magic_ldrb, cv); -+ TESTINSTPCMISALIGNED_2OUT("ldrd r0, r1, label_magic_ldrd", -+ r0, r1, label_magic_ldrd, cv); -+ TESTINSTPCMISALIGNED("ldrh r1, label_magic_ldrh", -+ r1, label_magic_ldrh, cv); -+ TESTINSTPCMISALIGNED("ldrsb r1, label_magic_ldrsb", -+ r1, label_magic_ldrsb, cv); -+ TESTINSTPCMISALIGNED("ldrsh r1, label_magic_ldrsh", -+ r1, label_magic_ldrsh, cv); -+ // omitting PLD/PLI -+ TESTINSTPCMISALIGNED_DWORDOUT("vldr d0, label_magic_vldr", -+ label_magic_vldr, cv, "d0"); -+ -+ TESTCARRYEND -+ -+ test_ldr_pc(); - #if 0 - printf("ROR\n"); - TESTCARRY -Index: none/tests/arm/v6intThumb.stdout.exp -=================================================================== ---- none/tests/arm/v6intThumb.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/arm/v6intThumb.stdout.exp (.../trunk) (revision 13981) -@@ -17307,6 +17307,17 @@ - asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 3, cpsr 0x10000000 V - asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x70000000 ZCV - asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x50000000 Z V -+literal access [PC+#imm] -+adr.w r1, label_magic_adrw; and r1, r1, #0x3 :: rd 0x00000000, cpsr 0xc0000000 NZ -+ldr r1, label_magic_ldr :: rd 0x8191881b, cpsr 0xc0000000 NZ -+ldrb r1, label_magic_ldrb :: rd 0x0000001b, cpsr 0xc0000000 NZ -+ldrd r0, r1, label_magic_ldrd :: rd 0x8191881b rd2 0x18fe9c93, cpsr 0xc0000000 NZ -+ldrh r1, label_magic_ldrh :: rd 0x0000881b, cpsr 0xc0000000 NZ -+ldrsb r1, label_magic_ldrsb :: rd 0x0000001b, cpsr 0xc0000000 NZ -+ldrsh r1, label_magic_ldrsh :: rd 0xffff881b, cpsr 0xc0000000 NZ -+vldr d0, label_magic_vldr :: s0 0x8191881b s1 0x18fe9c93, cpsr 0xc0000000 NZ -+tests for instructions modifying pc (ldr pc, add pc) -+ldr.w pc, [r9, +#432] :: r1 0x0000002a c:v-in 0, cpsr 0xc0000000 NZ - MUL - mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ - mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ -Index: none/tests/arm/vfpv4_fma.c -=================================================================== ---- none/tests/arm/vfpv4_fma.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/arm/vfpv4_fma.c (.../trunk) (revision 13981) -@@ -0,0 +1,182 @@ -+ -+/* Can be compiled both as ARM or Thumb using -+ gcc -Wall -g -O0 -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -m{arm,thumb} -o vfp vfp.c -+*/ -+ -+#include -+#include -+#include -+ -+static unsigned int f2u(float x) { -+ union { -+ float f; -+ unsigned int u; -+ } cvt; -+ cvt.f = x; -+ return cvt.u; -+} -+ -+static unsigned int f2u0(double x) { -+ union { -+ double f; -+ unsigned int u[2]; -+ } cvt; -+ cvt.f = x; -+ return cvt.u[0]; -+} -+ -+static unsigned int f2u1(double x) { -+ union { -+ double f; -+ unsigned int u[2]; -+ } cvt; -+ cvt.f = x; -+ return cvt.u[1]; -+} -+ -+/* test macros to generate and output the result of a single instruction */ -+ -+#define TESTINSN_bin_f64(instruction, QD, QM, QMtype, QMval0, QMval1, QN, QNtype, QNval0, QNval1) \ -+{ \ -+ unsigned int out[2] = { 0x55555555, 0x55555555 }; \ -+ unsigned int block[2]; \ -+ block[0] = block[1] = 0x3f800000; \ -+ \ -+ __asm__ volatile( \ -+ "vldr " #QD ", [%5]\n\t" \ -+ "vmov " #QM ", %1, %2 \n\t" \ -+ "vmov " #QN ", %3, %4 \n\t" \ -+ instruction "\n\t" \ -+ "vstmia %0, {" #QD "}\n\t" \ -+ : \ -+ : "r" (&out[0]), "r" (QMval0), "r" (QMval1), "r" (QNval0), "r" (QNval1), "r"(&block[0]) \ -+ : #QD, #QM, #QN, "memory" \ -+ ); \ -+ printf("%-24s :: Qd 0x%08x 0x%08x Qm 0x%08x %08x" \ -+ " Qn 0x%08x %08x\n", \ -+ instruction, out[1], out[0], QMval1, QMval0, QNval1, QNval0); \ -+} -+ -+#define TESTINSN_bin_f32(instruction, SD, SM, SMtype, SMval, SN, SNtype, SNval) \ -+{ \ -+ unsigned int out[2] = { 0x55555555, 0x55555555 }; \ -+ \ -+ __asm__ volatile( \ -+ "vmov.f32 " #SM ", %1\n\t" \ -+ "vmov.f32 " #SN ", %2\n\t" \ -+ "vmov.f32 " #SD ", %3\n\t" \ -+ instruction "\n\t" \ -+ "vstmia %0, {" #SD "}\n\t" \ -+ : \ -+ : "r" (&out[0]), "r" (SMval), "r" (SNval), "r" (0xaaaaaaaa) \ -+ : #SD, #SM, #SN, "memory" \ -+ ); \ -+ printf("%-24s :: Qd 0x%08x 0x%08x Sm (" #SMtype ")0x%08x" \ -+ " Sn (" #SNtype ")0x%08x\n", \ -+ instruction, out[1], out[0], SMval, SNval); \ -+} -+ -+int main(int argc, char **argv) -+{ -+ printf("---- VFMA (fp, VFPv4) ----\n"); -+ TESTINSN_bin_f64("vfma.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); -+ TESTINSN_bin_f64("vfma.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); -+ TESTINSN_bin_f64("vfma.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); -+ TESTINSN_bin_f64("vfma.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); -+ TESTINSN_bin_f64("vfma.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); -+ TESTINSN_bin_f64("vfma.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); -+ TESTINSN_bin_f64("vfma.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); -+ TESTINSN_bin_f64("vfma.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); -+ TESTINSN_bin_f64("vfma.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); -+ TESTINSN_bin_f64("vfma.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); -+ TESTINSN_bin_f64("vfma.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); -+ TESTINSN_bin_f64("vfma.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); -+ TESTINSN_bin_f64("vfma.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); -+ TESTINSN_bin_f64("vfma.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); -+ TESTINSN_bin_f64("vfma.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); -+ TESTINSN_bin_f64("vfma.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); -+ TESTINSN_bin_f64("vfma.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); -+ TESTINSN_bin_f64("vfma.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); -+ TESTINSN_bin_f64("vfma.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); -+ TESTINSN_bin_f64("vfma.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); -+ TESTINSN_bin_f64("vfma.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); -+ TESTINSN_bin_f64("vfma.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); -+ TESTINSN_bin_f64("vfma.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); -+ TESTINSN_bin_f64("vfma.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); -+ TESTINSN_bin_f32("vfma.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); -+ TESTINSN_bin_f32("vfma.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); -+ TESTINSN_bin_f32("vfma.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); -+ TESTINSN_bin_f32("vfma.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); -+ TESTINSN_bin_f32("vfma.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); -+ TESTINSN_bin_f32("vfma.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); -+ TESTINSN_bin_f32("vfma.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); -+ TESTINSN_bin_f32("vfma.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); -+ TESTINSN_bin_f32("vfma.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); -+ TESTINSN_bin_f32("vfma.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); -+ TESTINSN_bin_f32("vfma.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); -+ TESTINSN_bin_f32("vfma.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); -+ TESTINSN_bin_f32("vfma.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); -+ TESTINSN_bin_f32("vfma.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); -+ TESTINSN_bin_f32("vfma.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); -+ TESTINSN_bin_f32("vfma.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); -+ TESTINSN_bin_f32("vfma.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); -+ TESTINSN_bin_f32("vfma.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); -+ TESTINSN_bin_f32("vfma.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); -+ TESTINSN_bin_f32("vfma.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); -+ TESTINSN_bin_f32("vfma.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); -+ TESTINSN_bin_f32("vfma.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); -+ TESTINSN_bin_f32("vfma.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); -+ TESTINSN_bin_f32("vfma.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); -+ -+ printf("---- VFMS (fp, VFPv4) ----\n"); -+ TESTINSN_bin_f64("vfms.f64 d0, d11, d12", d0, d11, i32, f2u0(-INFINITY), f2u1(-INFINITY), d12, i32, f2u0(NAN), f2u1(NAN)); -+ TESTINSN_bin_f64("vfms.f64 d7, d1, d6", d7, d1, i32, f2u0(INFINITY), f2u1(INFINITY), d6, i32, f2u0(NAN), f2u1(NAN)); -+ TESTINSN_bin_f64("vfms.f64 d0, d5, d2", d0, d5, i32, f2u0(NAN), f2u1(NAN), d2, i32, f2u0(-1.0), f2u1(-1.0)); -+ TESTINSN_bin_f64("vfms.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(0.0), f2u1(0.0)); -+ TESTINSN_bin_f64("vfms.f64 d10, d13, d15", d10, d13, i32, f2u0(NAN), f2u1(NAN), d15, i32, f2u0(NAN), f2u1(NAN)); -+ TESTINSN_bin_f64("vfms.f64 d20, d25, d22", d20, d25, i32, f2u0(23.04), f2u1(23.04), d22, i32, f2u0(-45.5687), f2u1(-45.5687)); -+ TESTINSN_bin_f64("vfms.f64 d23, d24, d25", d23, d24, i32, f2u0(-347856.475), f2u1(-347856.475), d25, i32, f2u0(1346), f2u1(1346)); -+ TESTINSN_bin_f64("vfms.f64 d20, d31, d12", d20, d31, i32, f2u0(48755), f2u1(48755), d12, i32, f2u0(-45786.476), f2u1(-45786.476)); -+ TESTINSN_bin_f64("vfms.f64 d19, d25, d27", d19, d25, i32, f2u0(95867.76), f2u1(95867.76), d27, i32, f2u0(17065), f2u1(17065)); -+ TESTINSN_bin_f64("vfms.f64 d30, d15, d2", d30, d15, i32, f2u0(-45667.24), f2u1(-45667.24), d2, i32, f2u0(-248562.76), f2u1(-248562.76)); -+ TESTINSN_bin_f64("vfms.f64 d23, d24, d5", d23, d24, i32, f2u0(24), f2u1(24), d5, i32, f2u0(1346), f2u1(1346)); -+ TESTINSN_bin_f64("vfms.f64 d10, d11, d2", d10, d11, i32, f2u0(48755), f2u1(48755), d2, i32, f2u0(1089), f2u1(1089)); -+ TESTINSN_bin_f64("vfms.f64 d29, d15, d7", d29, d15, i32, f2u0(214), f2u1(214), d7, i32, f2u0(1752065), f2u1(1752065)); -+ TESTINSN_bin_f64("vfms.f64 d30, d11, d12", d30, d11, i32, f2u0(356047.56), f2u1(356047.56), d12, i32, f2u0(5867.009), f2u1(5867.009)); -+ TESTINSN_bin_f64("vfms.f64 d27, d21, d6", d27, d21, i32, f2u0(34.00046), f2u1(34.00046), d6, i32, f2u0(0.0024575), f2u1(0.0024575)); -+ TESTINSN_bin_f64("vfms.f64 d30, d31, d2", d30, d31, i32, f2u0(2754), f2u1(2754), d2, i32, f2u0(107), f2u1(107)); -+ TESTINSN_bin_f64("vfms.f64 d13, d24, d5", d13, d24, i32, f2u0(874), f2u1(874), d5, i32, f2u0(1384.6), f2u1(1384.6)); -+ TESTINSN_bin_f64("vfms.f64 d10, d11, d2", d10, d11, i32, f2u0(487.587), f2u1(487.587), d2, i32, f2u0(109), f2u1(109)); -+ TESTINSN_bin_f64("vfms.f64 d29, d25, d7", d29, d25, i32, f2u0(-INFINITY), f2u1(-INFINITY), d7, i32, f2u0(1752), f2u1(1752)); -+ TESTINSN_bin_f64("vfms.f64 d0, d11, d12", d0, d11, i32, f2u0(INFINITY), f2u1(INFINITY), d12, i32, f2u0(-5786.47), f2u1(-5786.47)); -+ TESTINSN_bin_f64("vfms.f64 d27, d21, d16", d27, d21, i32, f2u0(456.2489562), f2u1(456.2489562), d16, i32, f2u0(-7.2945676), f2u1(-7.2945676)); -+ TESTINSN_bin_f64("vfms.f64 d0, d5, d2", d0, d5, i32, f2u0(INFINITY), f2u1(INFINITY), d2, i32, f2u0(-INFINITY), f2u1(-INFINITY)); -+ TESTINSN_bin_f64("vfms.f64 d20, d13, d15", d20, d13, i32, f2u0(-INFINITY), f2u1(-INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); -+ TESTINSN_bin_f64("vfms.f64 d10, d23, d15", d10, d23, i32, f2u0(INFINITY), f2u1(INFINITY), d15, i32, f2u0(0.0), f2u1(0.0)); -+ TESTINSN_bin_f32("vfms.f32 s0, s11, s12", s0, s11, i32, f2u(-INFINITY), s12, i32, f2u(NAN)); -+ TESTINSN_bin_f32("vfms.f32 s7, s1, s6", s7, s1, i32, f2u(INFINITY), s6, i32, f2u(NAN)); -+ TESTINSN_bin_f32("vfms.f32 s0, s5, s2", s0, s5, i32, f2u(NAN), s2, i32, f2u(-1.0)); -+ TESTINSN_bin_f32("vfms.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(0.0)); -+ TESTINSN_bin_f32("vfms.f32 s10, s13, s15", s10, s13, i32, f2u(NAN), s15, i32, f2u(NAN)); -+ TESTINSN_bin_f32("vfms.f32 s20, s25, s22", s20, s25, i32, f2u(23.04), s22, i32, f2u(-45.5687)); -+ TESTINSN_bin_f32("vfms.f32 s23, s24, s25", s23, s24, i32, f2u(-347856.475), s25, i32, f2u(1346)); -+ TESTINSN_bin_f32("vfms.f32 s20, s31, s12", s20, s31, i32, f2u(48755), s12, i32, f2u(-45786.476)); -+ TESTINSN_bin_f32("vfms.f32 s19, s25, s27", s19, s25, i32, f2u(95867.76), s27, i32, f2u(17065)); -+ TESTINSN_bin_f32("vfms.f32 s30, s15, s2", s30, s15, i32, f2u(-45667.24), s2, i32, f2u(-248562.76)); -+ TESTINSN_bin_f32("vfms.f32 s23, s24, s5", s23, s24, i32, f2u(24), s5, i32, f2u(1346)); -+ TESTINSN_bin_f32("vfms.f32 s10, s11, s2", s10, s11, i32, f2u(48755), s2, i32, f2u(1089)); -+ TESTINSN_bin_f32("vfms.f32 s29, s15, s7", s29, s15, i32, f2u(214), s7, i32, f2u(1752065)); -+ TESTINSN_bin_f32("vfms.f32 s30, s11, s12", s30, s11, i32, f2u(356047.56), s12, i32, f2u(5867.009)); -+ TESTINSN_bin_f32("vfms.f32 s27, s21, s6", s27, s21, i32, f2u(34.00046), s6, i32, f2u(0.0024575)); -+ TESTINSN_bin_f32("vfms.f32 s30, s31, s2", s30, s31, i32, f2u(2754), s2, i32, f2u(107)); -+ TESTINSN_bin_f32("vfms.f32 s13, s24, s5", s13, s24, i32, f2u(874), s5, i32, f2u(1384.6)); -+ TESTINSN_bin_f32("vfms.f32 s10, s11, s2", s10, s11, i32, f2u(487.587), s2, i32, f2u(109)); -+ TESTINSN_bin_f32("vfms.f32 s29, s25, s7", s29, s25, i32, f2u(-INFINITY), s7, i32, f2u(1752)); -+ TESTINSN_bin_f32("vfms.f32 s0, s11, s12", s0, s11, i32, f2u(INFINITY), s12, i32, f2u(-5786.47)); -+ TESTINSN_bin_f32("vfms.f32 s27, s21, s16", s27, s21, i32, f2u(456.2489562), s16, i32, f2u(-7.2945676)); -+ TESTINSN_bin_f32("vfms.f32 s0, s5, s2", s0, s5, i32, f2u(INFINITY), s2, i32, f2u(-INFINITY)); -+ TESTINSN_bin_f32("vfms.f32 s20, s13, s15", s20, s13, i32, f2u(-INFINITY), s15, i32, f2u(0.0)); -+ TESTINSN_bin_f32("vfms.f32 s10, s23, s15", s10, s23, i32, f2u(INFINITY), s15, i32, f2u(0.0)); -+ -+ return 0; -+} -Index: none/tests/arm/vfpv4_fma.stderr.exp -=================================================================== -Index: none/tests/arm/vfpv4_fma.stdout.exp -=================================================================== ---- none/tests/arm/vfpv4_fma.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/arm/vfpv4_fma.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,98 @@ -+---- VFMA (fp, VFPv4) ---- -+vfma.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 -+vfma.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 -+vfma.f64 d0, d5, d2 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 -+vfma.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 -+vfma.f64 d10, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 -+vfma.f64 d20, d25, d22 :: Qd 0xc0906794 0x842f8549 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b -+vfma.f64 d23, d24, d25 :: Qd 0xc1bbe864 0x1f579999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 -+vfma.f64 d20, d31, d12 :: Qd 0xc1e0a1cf 0xd2abe8f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d -+vfma.f64 d19, d25, d27 :: Qd 0x41d860c7 0xf71a1999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 -+vfma.f64 d30, d15, d2 :: Qd 0x420524a9 0x817febf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 -+vfma.f64 d23, d24, d5 :: Qd 0x40df8c00 0x800001fc Qm 0x40380000 00000000 Qn 0x40950800 00000000 -+vfma.f64 d10, d11, d2 :: Qd 0x41895139 0x98100000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 -+vfma.f64 d29, d15, d7 :: Qd 0x41b65928 0xd6020000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 -+vfma.f64 d30, d11, d12 :: Qd 0x41df20a6 0xd7bd2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa -+vfma.f64 d27, d21, d6 :: Qd 0x3fb763ef 0x4799be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd -+vfma.f64 d30, d31, d2 :: Qd 0x4111fc58 0x08000020 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 -+vfma.f64 d13, d24, d5 :: Qd 0x4132771c 0x6866666e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 -+vfma.f64 d10, d11, d2 :: Qd 0x40e9f35f 0xb4bc6b7d Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 -+vfma.f64 d29, d25, d7 :: Qd 0xfff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 -+vfma.f64 d0, d11, d12 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f -+vfma.f64 d27, d21, d16 :: Qd 0xc0aa0043 0x17cbec9d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 -+vfma.f64 d0, d5, d2 :: Qd 0xfff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 -+vfma.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 -+vfma.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 -+vfma.f32 s0, s11, s12 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 -+vfma.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 -+vfma.f32 s0, s5, s2 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 -+vfma.f32 s10, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 -+vfma.f32 s10, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 -+vfma.f32 s20, s25, s22 :: Qd 0x55555555 0xc4833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 -+vfma.f32 s23, s24, s25 :: Qd 0x55555555 0xcddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 -+vfma.f32 s20, s31, s12 :: Qd 0x55555555 0xcf050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a -+vfma.f32 s19, s25, s27 :: Qd 0x55555555 0x4ec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 -+vfma.f32 s30, s15, s2 :: Qd 0x55555555 0x5029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 -+vfma.f32 s23, s24, s5 :: Qd 0x55555555 0x46fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 -+vfma.f32 s10, s11, s2 :: Qd 0x55555555 0x4c4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 -+vfma.f32 s29, s15, s7 :: Qd 0x55555555 0x4db2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 -+vfma.f32 s30, s11, s12 :: Qd 0x55555555 0x4ef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 -+vfma.f32 s27, s21, s6 :: Qd 0x55555555 0x3dab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 -+vfma.f32 s30, s31, s2 :: Qd 0x55555555 0x488fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 -+vfma.f32 s13, s24, s5 :: Qd 0x55555555 0x4993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 -+vfma.f32 s10, s11, s2 :: Qd 0x55555555 0x474f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 -+vfma.f32 s29, s25, s7 :: Qd 0x55555555 0xff800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 -+vfma.f32 s0, s11, s12 :: Qd 0x55555555 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 -+vfma.f32 s27, s21, s16 :: Qd 0x55555555 0xc5500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 -+vfma.f32 s0, s5, s2 :: Qd 0x55555555 0xff800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 -+vfma.f32 s20, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 -+vfma.f32 s10, s23, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 -+---- VFMS (fp, VFPv4) ---- -+vfms.f64 d0, d11, d12 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x7ff80000 00000000 -+vfms.f64 d7, d1, d6 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x7ff80000 00000000 -+vfms.f64 d0, d5, d2 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0xbff00000 00000000 -+vfms.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x00000000 00000000 -+vfms.f64 d10, d13, d15 :: Qd 0xfff80000 0x00000000 Qm 0x7ff80000 00000000 Qn 0x7ff80000 00000000 -+vfms.f64 d20, d25, d22 :: Qd 0x409067a4 0x842fc4c9 Qm 0x40370a3d 70a3d70a Qn 0xc046c8cb 295e9e1b -+vfms.f64 d23, d24, d25 :: Qd 0x41bbe864 0x1f5b9999 Qm 0xc1153b41 e6666666 Qn 0x40950800 00000000 -+vfms.f64 d20, d31, d12 :: Qd 0x41e0a1cf 0xd2ac68f6 Qm 0x40e7ce60 00000000 Qn 0xc0e65b4f 3b645a1d -+vfms.f64 d19, d25, d27 :: Qd 0xc1d860c7 0xf7191999 Qm 0x40f767bc 28f5c28f Qn 0x40d0aa40 00000000 -+vfms.f64 d30, d15, d2 :: Qd 0xc20524a9 0x817fcbf4 Qm 0xc0e64c67 ae147ae1 Qn 0xc10e5796 147ae148 -+vfms.f64 d23, d24, d5 :: Qd 0xc0df8bff 0x7ffffe04 Qm 0x40380000 00000000 Qn 0x40950800 00000000 -+vfms.f64 d10, d11, d2 :: Qd 0xc1895139 0x97f00000 Qm 0x40e7ce60 00000000 Qn 0x40910400 00000000 -+vfms.f64 d29, d15, d7 :: Qd 0xc1b65928 0xd5fe0000 Qm 0x406ac000 00000000 Qn 0x413abc01 00000000 -+vfms.f64 d30, d11, d12 :: Qd 0xc1df20a6 0xd7bc2cb0 Qm 0x4115bb3e 3d70a3d7 Qn 0x40b6eb02 4dd2f1aa -+vfms.f64 d27, d21, d6 :: Qd 0xbfb363ef 0x37b9be48 Qm 0x4041000f 12c27a63 Qn 0x3f6421c0 44284dfd -+vfms.f64 d30, d31, d2 :: Qd 0xc111fc57 0xf7ffffe0 Qm 0x40a58400 00000000 Qn 0x405ac000 00000000 -+vfms.f64 d13, d24, d5 :: Qd 0xc132771c 0x6466665e Qm 0x408b5000 00000000 Qn 0x4095a266 66666666 -+vfms.f64 d10, d11, d2 :: Qd 0xc0e9f35f 0x34bc6981 Qm 0x407e7964 5a1cac08 Qn 0x405b4000 00000000 -+vfms.f64 d29, d25, d7 :: Qd 0x7ff00000 0x00000000 Qm 0xfff00000 00000000 Qn 0x409b6000 00000000 -+vfms.f64 d0, d11, d12 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xc0b69a78 51eb851f -+vfms.f64 d27, d21, d16 :: Qd 0x40aa004b 0x17cc0c5d Qm 0x407c83fb b97f122f Qn 0xc01d2da3 2101d847 -+vfms.f64 d0, d5, d2 :: Qd 0x7ff00000 0x00000000 Qm 0x7ff00000 00000000 Qn 0xfff00000 00000000 -+vfms.f64 d20, d13, d15 :: Qd 0x7ff80000 0x00000000 Qm 0xfff00000 00000000 Qn 0x00000000 00000000 -+vfms.f64 d10, d23, d15 :: Qd 0x7ff80000 0x00000000 Qm 0x7ff00000 00000000 Qn 0x00000000 00000000 -+vfms.f32 s0, s11, s12 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x7fc00000 -+vfms.f32 s7, s1, s6 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x7fc00000 -+vfms.f32 s0, s5, s2 :: Qd 0x55555555 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0xbf800000 -+vfms.f32 s10, s13, s15 :: Qd 0x55555555 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x00000000 -+vfms.f32 s10, s13, s15 :: Qd 0x55555555 0xffc00000 Sm (i32)0x7fc00000 Sn (i32)0x7fc00000 -+vfms.f32 s20, s25, s22 :: Qd 0x55555555 0x44833ce4 Sm (i32)0x41b851ec Sn (i32)0xc2364659 -+vfms.f32 s23, s24, s25 :: Qd 0x55555555 0x4ddf4321 Sm (i32)0xc8a9da0f Sn (i32)0x44a84000 -+vfms.f32 s20, s31, s12 :: Qd 0x55555555 0x4f050e7f Sm (i32)0x473e7300 Sn (i32)0xc732da7a -+vfms.f32 s19, s25, s27 :: Qd 0x55555555 0xcec3063f Sm (i32)0x47bb3de1 Sn (i32)0x46855200 -+vfms.f32 s30, s15, s2 :: Qd 0x55555555 0xd029254c Sm (i32)0xc732633d Sn (i32)0xc872bcb1 -+vfms.f32 s23, s24, s5 :: Qd 0x55555555 0xc6fc6000 Sm (i32)0x41c00000 Sn (i32)0x44a84000 -+vfms.f32 s10, s11, s2 :: Qd 0x55555555 0xcc4a89cd Sm (i32)0x473e7300 Sn (i32)0x44882000 -+vfms.f32 s29, s15, s7 :: Qd 0x55555555 0xcdb2c947 Sm (i32)0x43560000 Sn (i32)0x49d5e008 -+vfms.f32 s30, s11, s12 :: Qd 0x55555555 0xcef90536 Sm (i32)0x48add9f2 Sn (i32)0x45b75812 -+vfms.f32 s27, s21, s6 :: Qd 0x55555555 0xbdab1f7a Sm (i32)0x42080079 Sn (i32)0x3b210e02 -+vfms.f32 s30, s31, s2 :: Qd 0x55555555 0xc88fe2c0 Sm (i32)0x452c2000 Sn (i32)0x42d60000 -+vfms.f32 s13, s24, s5 :: Qd 0x55555555 0xc993b8e3 Sm (i32)0x445a8000 Sn (i32)0x44ad1333 -+vfms.f32 s10, s11, s2 :: Qd 0x55555555 0xc74f9afc Sm (i32)0x43f3cb23 Sn (i32)0x42da0000 -+vfms.f32 s29, s25, s7 :: Qd 0x55555555 0x7f800000 Sm (i32)0xff800000 Sn (i32)0x44db0000 -+vfms.f32 s0, s11, s12 :: Qd 0x55555555 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xc5b4d3c3 -+vfms.f32 s27, s21, s16 :: Qd 0x55555555 0x45500239 Sm (i32)0x43e41fde Sn (i32)0xc0e96d19 -+vfms.f32 s0, s5, s2 :: Qd 0x55555555 0x7f800000 Sm (i32)0x7f800000 Sn (i32)0xff800000 -+vfms.f32 s20, s13, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0xff800000 Sn (i32)0x00000000 -+vfms.f32 s10, s23, s15 :: Qd 0x55555555 0x7fc00000 Sm (i32)0x7f800000 Sn (i32)0x00000000 -Index: none/tests/arm/vfpv4_fma.vgtest -=================================================================== ---- none/tests/arm/vfpv4_fma.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/arm/vfpv4_fma.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prog: vfpv4_fma -+vgopts: -q -Index: none/tests/arm64/fp_and_simd.c -=================================================================== ---- none/tests/arm64/fp_and_simd.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/arm64/fp_and_simd.c (.../trunk) (revision 13981) -@@ -0,0 +1,6677 @@ -+ -+#include -+#include -+#include // memalign -+#include // memset -+#include // isnormal -+ -+typedef unsigned char UChar; -+typedef unsigned short int UShort; -+typedef unsigned int UInt; -+typedef signed int Int; -+typedef unsigned char UChar; -+typedef unsigned long long int ULong; -+ -+typedef unsigned char Bool; -+#define False ((Bool)0) -+#define True ((Bool)1) -+ -+ -+#define ITERS 1 -+ -+typedef -+ enum { TySF=1234, TyDF, TyB, TyH, TyS, TyD, TyNONE } -+ LaneTy; -+ -+union _V128 { -+ UChar u8[16]; -+ UShort u16[8]; -+ UInt u32[4]; -+ ULong u64[2]; -+ float f32[4]; -+ double f64[2]; -+}; -+typedef union _V128 V128; -+ -+static inline UChar randUChar ( void ) -+{ -+ static UInt seed = 80021; -+ seed = 1103515245 * seed + 12345; -+ return (seed >> 17) & 0xFF; -+} -+ -+static ULong randULong ( LaneTy ty ) -+{ -+ Int i; -+ ULong r = 0; -+ for (i = 0; i < 8; i++) { -+ r = (r << 8) | (ULong)(0xFF & randUChar()); -+ } -+ return r; -+} -+ -+/* Generates a random V128. Ensures that that it contains normalised -+ FP numbers when viewed as either F32x4 or F64x2, so that it is -+ reasonable to use in FP test cases. */ -+static void randV128 ( /*OUT*/V128* v, LaneTy ty ) -+{ -+ static UInt nCalls = 0, nIters = 0; -+ Int i; -+ nCalls++; -+ while (1) { -+ nIters++; -+ for (i = 0; i < 16; i++) { -+ v->u8[i] = randUChar(); -+ } -+ if (isnormal(v->f32[0]) && isnormal(v->f32[1]) && isnormal(v->f32[2]) -+ && isnormal(v->f32[3]) && isnormal(v->f64[0]) && isnormal(v->f64[1])) -+ break; -+ } -+ if (0 == (nCalls & 0xFF)) -+ printf("randV128: %u calls, %u iters\n", nCalls, nIters); -+} -+ -+static void showV128 ( V128* v ) -+{ -+ Int i; -+ for (i = 15; i >= 0; i--) -+ printf("%02x", (Int)v->u8[i]); -+} -+ -+__attribute__((unused)) -+static void* memalign16(size_t szB) -+{ -+ void* x; -+ x = memalign(16, szB); -+ assert(x); -+ assert(0 == ((16-1) & (unsigned long)x)); -+ return x; -+} -+ -+ -+/* ---------------------------------------------------------------- */ -+/* -- Test functions -- */ -+/* ---------------------------------------------------------------- */ -+ -+/* Note this also sets the destination register to a known value (0x55..55) -+ since it can sometimes be an input to the instruction too. */ -+#define GEN_UNARY_TEST(INSN,SUFFIXD,SUFFIXN) \ -+ __attribute__((noinline)) \ -+ static void test_##INSN##_##SUFFIXD##_##SUFFIXN ( LaneTy ty ) { \ -+ Int i; \ -+ for (i = 0; i < ITERS; i++) { \ -+ V128 block[2]; \ -+ memset(block, 0x55, sizeof(block)); \ -+ randV128(&block[0], ty); \ -+ randV128(&block[1], ty); \ -+ __asm__ __volatile__( \ -+ "ldr q7, [%0, #0] ; " \ -+ "ldr q8, [%0, #16] ; " \ -+ #INSN " v8." #SUFFIXD ", v7." #SUFFIXN " ; " \ -+ "str q8, [%0, #16] " \ -+ : : "r"(&block[0]) : "memory", "v7", "v8" \ -+ ); \ -+ printf(#INSN " v8." #SUFFIXD ", v7." #SUFFIXN); \ -+ showV128(&block[0]); printf(" "); \ -+ showV128(&block[1]); printf("\n"); \ -+ } \ -+ } -+ -+ -+/* Note this also sets the destination register to a known value (0x55..55) -+ since it can sometimes be an input to the instruction too. */ -+#define GEN_BINARY_TEST(INSN,SUFFIXD,SUFFIXN,SUFFIXM) \ -+ __attribute__((noinline)) \ -+ static void test_##INSN##_##SUFFIXD##_##SUFFIXN##_##SUFFIXM ( LaneTy ty ) { \ -+ Int i; \ -+ for (i = 0; i < ITERS; i++) { \ -+ V128 block[3]; \ -+ memset(block, 0x55, sizeof(block)); \ -+ randV128(&block[0], ty); \ -+ randV128(&block[1], ty); \ -+ randV128(&block[2], ty); \ -+ __asm__ __volatile__( \ -+ "ldr q7, [%0, #0] ; " \ -+ "ldr q8, [%0, #16] ; " \ -+ "ldr q9, [%0, #32] ; " \ -+ #INSN " v9." #SUFFIXD ", v7." #SUFFIXN ", v8." #SUFFIXM " ; " \ -+ "str q9, [%0, #32] " \ -+ : : "r"(&block[0]) : "memory", "v7", "v8", "v9" \ -+ ); \ -+ printf(#INSN " v9." #SUFFIXD \ -+ ", v7." #SUFFIXN ", v8." #SUFFIXM " "); \ -+ showV128(&block[0]); printf(" "); \ -+ showV128(&block[1]); printf(" "); \ -+ showV128(&block[2]); printf("\n"); \ -+ } \ -+ } -+ -+ -+/* Note this also sets the destination register to a known value (0x55..55) -+ since it can sometimes be an input to the instruction too. */ -+#define GEN_SHIFT_TEST(INSN,SUFFIXD,SUFFIXN,AMOUNT) \ -+ __attribute__((noinline)) \ -+ static void test_##INSN##_##SUFFIXD##_##SUFFIXN##_##AMOUNT ( LaneTy ty ) { \ -+ Int i; \ -+ for (i = 0; i < ITERS; i++) { \ -+ V128 block[2]; \ -+ memset(block, 0x55, sizeof(block)); \ -+ randV128(&block[0], ty); \ -+ randV128(&block[1], ty); \ -+ __asm__ __volatile__( \ -+ "ldr q7, [%0, #0] ; " \ -+ "ldr q8, [%0, #16] ; " \ -+ #INSN " v8." #SUFFIXD ", v7." #SUFFIXN ", #" #AMOUNT " ; " \ -+ "str q8, [%0, #16] " \ -+ : : "r"(&block[0]) : "memory", "v7", "v8" \ -+ ); \ -+ printf(#INSN " v8." #SUFFIXD ", v7." #SUFFIXN ", #" #AMOUNT " "); \ -+ showV128(&block[0]); printf(" "); \ -+ showV128(&block[1]); printf("\n"); \ -+ } \ -+ } -+ -+ -+/* Generate a test that involves one integer reg and one vector reg, -+ with no bias as towards which is input or output. */ -+#define GEN_ONEINT_ONEVEC_TEST(TESTNAME,INSN,INTREGNO,VECREGNO) \ -+ __attribute__((noinline)) \ -+ static void test_##TESTNAME ( LaneTy ty ) { \ -+ Int i; \ -+ for (i = 0; i < ITERS; i++) { \ -+ V128 block[4]; \ -+ memset(block, 0x55, sizeof(block)); \ -+ randV128(&block[0], ty); \ -+ randV128(&block[1], ty); \ -+ randV128(&block[2], ty); \ -+ randV128(&block[3], ty); \ -+ __asm__ __volatile__( \ -+ "ldr q"#VECREGNO", [%0, #0] ; " \ -+ "ldr x"#INTREGNO", [%0, #16] ; " \ -+ INSN " ; " \ -+ "str q"#VECREGNO", [%0, #32] ; " \ -+ "str x"#INTREGNO", [%0, #48] ; " \ -+ : : "r"(&block[0]) : "memory", "v"#VECREGNO, "x"#INTREGNO \ -+ ); \ -+ printf(INSN " "); \ -+ showV128(&block[0]); printf(" "); \ -+ showV128(&block[1]); printf(" "); \ -+ showV128(&block[2]); printf(" "); \ -+ showV128(&block[3]); printf("\n"); \ -+ } \ -+ } -+ -+ -+/* Generate a test that involves two vector regs, -+ with no bias as towards which is input or output. -+ It's OK to use x10 as scratch.*/ -+#define GEN_TWOVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO) \ -+ __attribute__((noinline)) \ -+ static void test_##TESTNAME ( LaneTy ty ) { \ -+ Int i; \ -+ for (i = 0; i < ITERS; i++) { \ -+ V128 block[4]; \ -+ memset(block, 0x55, sizeof(block)); \ -+ randV128(&block[0], ty); \ -+ randV128(&block[1], ty); \ -+ randV128(&block[2], ty); \ -+ randV128(&block[3], ty); \ -+ __asm__ __volatile__( \ -+ "ldr q"#VECREG1NO", [%0, #0] ; " \ -+ "ldr q"#VECREG2NO", [%0, #16] ; " \ -+ INSN " ; " \ -+ "str q"#VECREG1NO", [%0, #32] ; " \ -+ "str q"#VECREG2NO", [%0, #48] ; " \ -+ : : "r"(&block[0]) \ -+ : "memory", "v"#VECREG1NO, "v"#VECREG2NO, "x10" \ -+ ); \ -+ printf(INSN " "); \ -+ showV128(&block[0]); printf(" "); \ -+ showV128(&block[1]); printf(" "); \ -+ showV128(&block[2]); printf(" "); \ -+ showV128(&block[3]); printf("\n"); \ -+ } \ -+ } -+ -+ -+/* Generate a test that involves three vector regs, -+ with no bias as towards which is input or output. It's also OK -+ to use v16, v17, v18 as scratch. */ -+#define GEN_THREEVEC_TEST(TESTNAME,INSN,VECREG1NO,VECREG2NO,VECREG3NO) \ -+ __attribute__((noinline)) \ -+ static void test_##TESTNAME ( LaneTy ty ) { \ -+ Int i; \ -+ for (i = 0; i < ITERS; i++) { \ -+ V128 block[6]; \ -+ memset(block, 0x55, sizeof(block)); \ -+ randV128(&block[0], ty); \ -+ randV128(&block[1], ty); \ -+ randV128(&block[2], ty); \ -+ randV128(&block[3], ty); \ -+ randV128(&block[4], ty); \ -+ randV128(&block[5], ty); \ -+ __asm__ __volatile__( \ -+ "ldr q"#VECREG1NO", [%0, #0] ; " \ -+ "ldr q"#VECREG2NO", [%0, #16] ; " \ -+ "ldr q"#VECREG3NO", [%0, #32] ; " \ -+ INSN " ; " \ -+ "str q"#VECREG1NO", [%0, #48] ; " \ -+ "str q"#VECREG2NO", [%0, #64] ; " \ -+ "str q"#VECREG3NO", [%0, #80] ; " \ -+ : : "r"(&block[0]) \ -+ : "memory", "v"#VECREG1NO, "v"#VECREG2NO, "v"#VECREG3NO, \ -+ "v16", "v17", "v18" \ -+ ); \ -+ printf(INSN " "); \ -+ showV128(&block[0]); printf(" "); \ -+ showV128(&block[1]); printf(" "); \ -+ showV128(&block[2]); printf(" "); \ -+ showV128(&block[3]); printf(" "); \ -+ showV128(&block[4]); printf(" "); \ -+ showV128(&block[5]); printf("\n"); \ -+ } \ -+ } -+ -+ -+void test_UMINV ( void ) -+{ -+ int i; -+ V128 block[2]; -+ -+ /* -- 4s -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyS); -+ randV128(&block[1], TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "uminv s8, v7.4s ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMINV v8, v7.4s "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "uminv h8, v7.8h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMINV h8, v7.8h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 4h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "uminv h8, v7.4h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMINV h8, v7.4h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 16b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "uminv b8, v7.16b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMINV b8, v7.16b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "uminv b8, v7.8b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMINV b8, v7.8b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+} -+ -+ -+void test_UMAXV ( void ) -+{ -+ int i; -+ V128 block[2]; -+ -+ /* -- 4s -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyS); -+ randV128(&block[1], TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "umaxv s8, v7.4s ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMAXV v8, v7.4s "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "umaxv h8, v7.8h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMAXV h8, v7.8h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 4h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "umaxv h8, v7.4h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMAXV h8, v7.4h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 16b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "umaxv b8, v7.16b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMAXV b8, v7.16b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "umaxv b8, v7.8b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("UMAXV b8, v7.8b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+} -+ -+ -+void test_INS_general ( void ) -+{ -+ V128 block[3]; -+ -+ /* -- D[0..1] -- */ -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyD); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.d[0], x19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.u64[0],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyD); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.d[1], x19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.d[1],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ /* -- S[0..3] -- */ -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.s[0], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.s[0],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.s[1], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.s[1],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.s[2], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.s[2],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.s[3], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.s[3],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ /* -- H[0..7] -- */ -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[0], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[0],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[1], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[1],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[2], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[2],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[3], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[3],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[4], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[4],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[5], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[5],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[6], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[6],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.h[7], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.h[7],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ /* -- B[0,15] -- */ -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.b[0], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.b[0],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+ -+ memset(&block, 0x55, sizeof(block)); -+ block[1].u64[0] = randULong(TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "ldr x19, [%0, #16] ; " -+ "ins v7.b[15], w19 ; " -+ "str q7, [%0, #32] " -+ : : "r"(&block[0]) : "memory", "x19", "v7" -+ ); -+ printf("INS v7.b[15],x19 "); -+ showV128(&block[0]); printf(" %016llx ", block[1].u64[0]); -+ showV128(&block[2]); printf("\n"); -+} -+ -+ -+ -+void test_SMINV ( void ) -+{ -+ int i; -+ V128 block[2]; -+ -+ /* -- 4s -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyS); -+ randV128(&block[1], TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "sminv s8, v7.4s ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMINV v8, v7.4s "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "sminv h8, v7.8h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMINV h8, v7.8h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 4h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "sminv h8, v7.4h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMINV h8, v7.4h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 16b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "sminv b8, v7.16b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMINV b8, v7.16b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "sminv b8, v7.8b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMINV b8, v7.8b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+} -+ -+ -+void test_SMAXV ( void ) -+{ -+ int i; -+ V128 block[2]; -+ -+ /* -- 4s -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyS); -+ randV128(&block[1], TyS); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "smaxv s8, v7.4s ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMAXV v8, v7.4s "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "smaxv h8, v7.8h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMAXV h8, v7.8h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 4h -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyH); -+ randV128(&block[1], TyH); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "smaxv h8, v7.4h ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMAXV h8, v7.4h "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 16b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "smaxv b8, v7.16b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMAXV b8, v7.16b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+ /* -- 8b -- */ -+ -+ for (i = 0; i < 10; i++) { -+ memset(&block, 0x55, sizeof(block)); -+ randV128(&block[0], TyB); -+ randV128(&block[1], TyB); -+ __asm__ __volatile__( -+ "ldr q7, [%0, #0] ; " -+ "smaxv b8, v7.8b ; " -+ "str q8, [%0, #16] " -+ : : "r"(&block[0]) : "memory", "v7", "v8" -+ ); -+ printf("SMAXV b8, v7.8b "); -+ showV128(&block[0]); printf(" "); -+ showV128(&block[1]); printf("\n"); -+ } -+ -+} -+ -+ -+GEN_BINARY_TEST(umax, 4s, 4s, 4s) -+GEN_BINARY_TEST(umax, 2s, 2s, 2s) -+GEN_BINARY_TEST(umax, 8h, 8h, 8h) -+GEN_BINARY_TEST(umax, 4h, 4h, 4h) -+GEN_BINARY_TEST(umax, 16b, 16b, 16b) -+GEN_BINARY_TEST(umax, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(umin, 4s, 4s, 4s) -+GEN_BINARY_TEST(umin, 2s, 2s, 2s) -+GEN_BINARY_TEST(umin, 8h, 8h, 8h) -+GEN_BINARY_TEST(umin, 4h, 4h, 4h) -+GEN_BINARY_TEST(umin, 16b, 16b, 16b) -+GEN_BINARY_TEST(umin, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(smax, 4s, 4s, 4s) -+GEN_BINARY_TEST(smax, 2s, 2s, 2s) -+GEN_BINARY_TEST(smax, 8h, 8h, 8h) -+GEN_BINARY_TEST(smax, 4h, 4h, 4h) -+GEN_BINARY_TEST(smax, 16b, 16b, 16b) -+GEN_BINARY_TEST(smax, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(smin, 4s, 4s, 4s) -+GEN_BINARY_TEST(smin, 2s, 2s, 2s) -+GEN_BINARY_TEST(smin, 8h, 8h, 8h) -+GEN_BINARY_TEST(smin, 4h, 4h, 4h) -+GEN_BINARY_TEST(smin, 16b, 16b, 16b) -+GEN_BINARY_TEST(smin, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(add, 2d, 2d, 2d) -+GEN_BINARY_TEST(add, 4s, 4s, 4s) -+GEN_BINARY_TEST(add, 2s, 2s, 2s) -+GEN_BINARY_TEST(add, 8h, 8h, 8h) -+GEN_BINARY_TEST(add, 4h, 4h, 4h) -+GEN_BINARY_TEST(add, 16b, 16b, 16b) -+GEN_BINARY_TEST(add, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(sub, 2d, 2d, 2d) -+GEN_BINARY_TEST(sub, 4s, 4s, 4s) -+GEN_BINARY_TEST(sub, 2s, 2s, 2s) -+GEN_BINARY_TEST(sub, 8h, 8h, 8h) -+GEN_BINARY_TEST(sub, 4h, 4h, 4h) -+GEN_BINARY_TEST(sub, 16b, 16b, 16b) -+GEN_BINARY_TEST(sub, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(mul, 4s, 4s, 4s) -+GEN_BINARY_TEST(mul, 2s, 2s, 2s) -+GEN_BINARY_TEST(mul, 8h, 8h, 8h) -+GEN_BINARY_TEST(mul, 4h, 4h, 4h) -+GEN_BINARY_TEST(mul, 16b, 16b, 16b) -+GEN_BINARY_TEST(mul, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(mla, 4s, 4s, 4s) -+GEN_BINARY_TEST(mla, 2s, 2s, 2s) -+GEN_BINARY_TEST(mla, 8h, 8h, 8h) -+GEN_BINARY_TEST(mla, 4h, 4h, 4h) -+GEN_BINARY_TEST(mla, 16b, 16b, 16b) -+GEN_BINARY_TEST(mla, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(mls, 4s, 4s, 4s) -+GEN_BINARY_TEST(mls, 2s, 2s, 2s) -+GEN_BINARY_TEST(mls, 8h, 8h, 8h) -+GEN_BINARY_TEST(mls, 4h, 4h, 4h) -+GEN_BINARY_TEST(mls, 16b, 16b, 16b) -+GEN_BINARY_TEST(mls, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(and, 16b, 16b, 16b) -+GEN_BINARY_TEST(and, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(bic, 16b, 16b, 16b) -+GEN_BINARY_TEST(bic, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(orr, 16b, 16b, 16b) -+GEN_BINARY_TEST(orr, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(orn, 16b, 16b, 16b) -+GEN_BINARY_TEST(orn, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(eor, 16b, 16b, 16b) -+GEN_BINARY_TEST(eor, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(bsl, 16b, 16b, 16b) -+GEN_BINARY_TEST(bsl, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(bit, 16b, 16b, 16b) -+GEN_BINARY_TEST(bit, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(bif, 16b, 16b, 16b) -+GEN_BINARY_TEST(bif, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(cmeq, 2d, 2d, 2d) -+GEN_BINARY_TEST(cmeq, 4s, 4s, 4s) -+GEN_BINARY_TEST(cmeq, 2s, 2s, 2s) -+GEN_BINARY_TEST(cmeq, 8h, 8h, 8h) -+GEN_BINARY_TEST(cmeq, 4h, 4h, 4h) -+GEN_BINARY_TEST(cmeq, 16b, 16b, 16b) -+GEN_BINARY_TEST(cmeq, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(cmtst, 2d, 2d, 2d) -+GEN_BINARY_TEST(cmtst, 4s, 4s, 4s) -+GEN_BINARY_TEST(cmtst, 2s, 2s, 2s) -+GEN_BINARY_TEST(cmtst, 8h, 8h, 8h) -+GEN_BINARY_TEST(cmtst, 4h, 4h, 4h) -+GEN_BINARY_TEST(cmtst, 16b, 16b, 16b) -+GEN_BINARY_TEST(cmtst, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(cmhi, 2d, 2d, 2d) -+GEN_BINARY_TEST(cmhi, 4s, 4s, 4s) -+GEN_BINARY_TEST(cmhi, 2s, 2s, 2s) -+GEN_BINARY_TEST(cmhi, 8h, 8h, 8h) -+GEN_BINARY_TEST(cmhi, 4h, 4h, 4h) -+GEN_BINARY_TEST(cmhi, 16b, 16b, 16b) -+GEN_BINARY_TEST(cmhi, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(cmgt, 2d, 2d, 2d) -+GEN_BINARY_TEST(cmgt, 4s, 4s, 4s) -+GEN_BINARY_TEST(cmgt, 2s, 2s, 2s) -+GEN_BINARY_TEST(cmgt, 8h, 8h, 8h) -+GEN_BINARY_TEST(cmgt, 4h, 4h, 4h) -+GEN_BINARY_TEST(cmgt, 16b, 16b, 16b) -+GEN_BINARY_TEST(cmgt, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(cmhs, 2d, 2d, 2d) -+GEN_BINARY_TEST(cmhs, 4s, 4s, 4s) -+GEN_BINARY_TEST(cmhs, 2s, 2s, 2s) -+GEN_BINARY_TEST(cmhs, 8h, 8h, 8h) -+GEN_BINARY_TEST(cmhs, 4h, 4h, 4h) -+GEN_BINARY_TEST(cmhs, 16b, 16b, 16b) -+GEN_BINARY_TEST(cmhs, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(cmge, 2d, 2d, 2d) -+GEN_BINARY_TEST(cmge, 4s, 4s, 4s) -+GEN_BINARY_TEST(cmge, 2s, 2s, 2s) -+GEN_BINARY_TEST(cmge, 8h, 8h, 8h) -+GEN_BINARY_TEST(cmge, 4h, 4h, 4h) -+GEN_BINARY_TEST(cmge, 16b, 16b, 16b) -+GEN_BINARY_TEST(cmge, 8b, 8b, 8b) -+ -+GEN_SHIFT_TEST(ushr, 2d, 2d, 1) -+GEN_SHIFT_TEST(ushr, 2d, 2d, 13) -+GEN_SHIFT_TEST(ushr, 2d, 2d, 64) -+GEN_SHIFT_TEST(sshr, 2d, 2d, 1) -+GEN_SHIFT_TEST(sshr, 2d, 2d, 13) -+GEN_SHIFT_TEST(sshr, 2d, 2d, 64) -+GEN_SHIFT_TEST(shl, 2d, 2d, 0) -+GEN_SHIFT_TEST(shl, 2d, 2d, 13) -+GEN_SHIFT_TEST(shl, 2d, 2d, 63) -+ -+GEN_SHIFT_TEST(ushr, 4s, 4s, 1) -+GEN_SHIFT_TEST(ushr, 4s, 4s, 13) -+GEN_SHIFT_TEST(ushr, 4s, 4s, 32) -+GEN_SHIFT_TEST(sshr, 4s, 4s, 1) -+GEN_SHIFT_TEST(sshr, 4s, 4s, 13) -+GEN_SHIFT_TEST(sshr, 4s, 4s, 32) -+GEN_SHIFT_TEST(shl, 4s, 4s, 0) -+GEN_SHIFT_TEST(shl, 4s, 4s, 13) -+GEN_SHIFT_TEST(shl, 4s, 4s, 31) -+ -+GEN_SHIFT_TEST(ushr, 2s, 2s, 1) -+GEN_SHIFT_TEST(ushr, 2s, 2s, 13) -+GEN_SHIFT_TEST(ushr, 2s, 2s, 32) -+GEN_SHIFT_TEST(sshr, 2s, 2s, 1) -+GEN_SHIFT_TEST(sshr, 2s, 2s, 13) -+GEN_SHIFT_TEST(sshr, 2s, 2s, 32) -+GEN_SHIFT_TEST(shl, 2s, 2s, 0) -+GEN_SHIFT_TEST(shl, 2s, 2s, 13) -+GEN_SHIFT_TEST(shl, 2s, 2s, 31) -+ -+GEN_SHIFT_TEST(ushr, 8h, 8h, 1) -+GEN_SHIFT_TEST(ushr, 8h, 8h, 13) -+GEN_SHIFT_TEST(ushr, 8h, 8h, 16) -+GEN_SHIFT_TEST(sshr, 8h, 8h, 1) -+GEN_SHIFT_TEST(sshr, 8h, 8h, 13) -+GEN_SHIFT_TEST(sshr, 8h, 8h, 16) -+GEN_SHIFT_TEST(shl, 8h, 8h, 0) -+GEN_SHIFT_TEST(shl, 8h, 8h, 13) -+GEN_SHIFT_TEST(shl, 8h, 8h, 15) -+ -+GEN_SHIFT_TEST(ushr, 4h, 4h, 1) -+GEN_SHIFT_TEST(ushr, 4h, 4h, 13) -+GEN_SHIFT_TEST(ushr, 4h, 4h, 16) -+GEN_SHIFT_TEST(sshr, 4h, 4h, 1) -+GEN_SHIFT_TEST(sshr, 4h, 4h, 13) -+GEN_SHIFT_TEST(sshr, 4h, 4h, 16) -+GEN_SHIFT_TEST(shl, 4h, 4h, 0) -+GEN_SHIFT_TEST(shl, 4h, 4h, 13) -+GEN_SHIFT_TEST(shl, 4h, 4h, 15) -+ -+GEN_SHIFT_TEST(ushr, 16b, 16b, 1) -+GEN_SHIFT_TEST(ushr, 16b, 16b, 8) -+GEN_SHIFT_TEST(sshr, 16b, 16b, 1) -+GEN_SHIFT_TEST(sshr, 16b, 16b, 8) -+GEN_SHIFT_TEST(shl, 16b, 16b, 0) -+GEN_SHIFT_TEST(shl, 16b, 16b, 7) -+ -+GEN_SHIFT_TEST(ushr, 8b, 8b, 1) -+GEN_SHIFT_TEST(ushr, 8b, 8b, 8) -+GEN_SHIFT_TEST(sshr, 8b, 8b, 1) -+GEN_SHIFT_TEST(sshr, 8b, 8b, 8) -+GEN_SHIFT_TEST(shl, 8b, 8b, 0) -+GEN_SHIFT_TEST(shl, 8b, 8b, 7) -+ -+GEN_SHIFT_TEST(ushll, 2d, 2s, 0) -+GEN_SHIFT_TEST(ushll, 2d, 2s, 15) -+GEN_SHIFT_TEST(ushll, 2d, 2s, 31) -+GEN_SHIFT_TEST(ushll2, 2d, 4s, 0) -+GEN_SHIFT_TEST(ushll2, 2d, 4s, 15) -+GEN_SHIFT_TEST(ushll2, 2d, 4s, 31) -+GEN_SHIFT_TEST(ushll, 4s, 4h, 0) -+GEN_SHIFT_TEST(ushll, 4s, 4h, 7) -+GEN_SHIFT_TEST(ushll, 4s, 4h, 15) -+GEN_SHIFT_TEST(ushll2, 4s, 8h, 0) -+GEN_SHIFT_TEST(ushll2, 4s, 8h, 7) -+GEN_SHIFT_TEST(ushll2, 4s, 8h, 15) -+GEN_SHIFT_TEST(ushll, 8h, 8b, 0) -+GEN_SHIFT_TEST(ushll, 8h, 8b, 3) -+GEN_SHIFT_TEST(ushll, 8h, 8b, 7) -+GEN_SHIFT_TEST(ushll2, 8h, 16b, 0) -+GEN_SHIFT_TEST(ushll2, 8h, 16b, 3) -+GEN_SHIFT_TEST(ushll2, 8h, 16b, 7) -+ -+GEN_SHIFT_TEST(sshll, 2d, 2s, 0) -+GEN_SHIFT_TEST(sshll, 2d, 2s, 15) -+GEN_SHIFT_TEST(sshll, 2d, 2s, 31) -+GEN_SHIFT_TEST(sshll2, 2d, 4s, 0) -+GEN_SHIFT_TEST(sshll2, 2d, 4s, 15) -+GEN_SHIFT_TEST(sshll2, 2d, 4s, 31) -+GEN_SHIFT_TEST(sshll, 4s, 4h, 0) -+GEN_SHIFT_TEST(sshll, 4s, 4h, 7) -+GEN_SHIFT_TEST(sshll, 4s, 4h, 15) -+GEN_SHIFT_TEST(sshll2, 4s, 8h, 0) -+GEN_SHIFT_TEST(sshll2, 4s, 8h, 7) -+GEN_SHIFT_TEST(sshll2, 4s, 8h, 15) -+GEN_SHIFT_TEST(sshll, 8h, 8b, 0) -+GEN_SHIFT_TEST(sshll, 8h, 8b, 3) -+GEN_SHIFT_TEST(sshll, 8h, 8b, 7) -+GEN_SHIFT_TEST(sshll2, 8h, 16b, 0) -+GEN_SHIFT_TEST(sshll2, 8h, 16b, 3) -+GEN_SHIFT_TEST(sshll2, 8h, 16b, 7) -+ -+ -+GEN_UNARY_TEST(xtn, 2s, 2d) -+GEN_UNARY_TEST(xtn2, 4s, 2d) -+GEN_UNARY_TEST(xtn, 4h, 4s) -+GEN_UNARY_TEST(xtn2, 8h, 4s) -+GEN_UNARY_TEST(xtn, 8b, 8h) -+GEN_UNARY_TEST(xtn2, 16b, 8h) -+ -+GEN_ONEINT_ONEVEC_TEST(umov_x_d0, "umov x9, v10.d[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(umov_x_d1, "umov x9, v10.d[1]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(umov_w_s0, "umov w9, v10.s[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(umov_w_s3, "umov w9, v10.s[3]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(umov_w_h0, "umov w9, v10.h[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(umov_w_h7, "umov w9, v10.h[7]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(umov_w_b0, "umov w9, v10.b[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(umov_w_b15, "umov w9, v10.b[15]", 9, 10) -+ -+GEN_ONEINT_ONEVEC_TEST(smov_x_s0, "smov x9, v10.s[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_x_s3, "smov x9, v10.s[3]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_x_h0, "smov x9, v10.h[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_x_h7, "smov x9, v10.h[7]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_w_h0, "smov w9, v10.h[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_w_h7, "smov w9, v10.h[7]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_x_b0, "smov x9, v10.b[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_x_b15, "smov x9, v10.b[15]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_w_b0, "smov w9, v10.b[0]", 9, 10) -+GEN_ONEINT_ONEVEC_TEST(smov_w_b15, "smov w9, v10.b[15]", 9, 10) -+ -+GEN_TWOVEC_TEST(fcvtn_2s_2d, "fcvtn v22.2s, v23.2d", 22, 23) -+GEN_TWOVEC_TEST(fcvtn_4s_2d, "fcvtn2 v22.4s, v23.2d", 22, 23) -+ -+GEN_UNARY_TEST(neg, 2d, 2d) -+GEN_UNARY_TEST(neg, 4s, 4s) -+GEN_UNARY_TEST(neg, 2s, 2s) -+GEN_UNARY_TEST(neg, 8h, 8h) -+GEN_UNARY_TEST(neg, 4h, 4h) -+GEN_UNARY_TEST(neg, 16b, 16b) -+GEN_UNARY_TEST(neg, 8b, 8b) -+ -+GEN_BINARY_TEST(fadd, 2d, 2d, 2d) -+GEN_BINARY_TEST(fadd, 4s, 4s, 4s) -+GEN_BINARY_TEST(fadd, 2s, 2s, 2s) -+GEN_BINARY_TEST(fsub, 2d, 2d, 2d) -+GEN_BINARY_TEST(fsub, 4s, 4s, 4s) -+GEN_BINARY_TEST(fsub, 2s, 2s, 2s) -+GEN_BINARY_TEST(fmul, 2d, 2d, 2d) -+GEN_BINARY_TEST(fmul, 4s, 4s, 4s) -+GEN_BINARY_TEST(fmul, 2s, 2s, 2s) -+GEN_BINARY_TEST(fdiv, 2d, 2d, 2d) -+GEN_BINARY_TEST(fdiv, 4s, 4s, 4s) -+GEN_BINARY_TEST(fdiv, 2s, 2s, 2s) -+GEN_BINARY_TEST(fmla, 2d, 2d, 2d) -+GEN_BINARY_TEST(fmla, 4s, 4s, 4s) -+GEN_BINARY_TEST(fmla, 2s, 2s, 2s) -+GEN_BINARY_TEST(fmls, 2d, 2d, 2d) -+GEN_BINARY_TEST(fmls, 4s, 4s, 4s) -+GEN_BINARY_TEST(fmls, 2s, 2s, 2s) -+GEN_BINARY_TEST(fabd, 2d, 2d, 2d) -+GEN_BINARY_TEST(fabd, 4s, 4s, 4s) -+GEN_BINARY_TEST(fabd, 2s, 2s, 2s) -+ -+GEN_THREEVEC_TEST(add_d_d_d, "add d21, d22, d23", 21, 22, 23) -+GEN_THREEVEC_TEST(sub_d_d_d, "sub d21, d22, d23", 21, 22, 23) -+ -+/* overkill -- don't need two vecs, only one */ -+GEN_TWOVEC_TEST(fmov_d_imm_01, "fmov d22, #0.125", 22, 23) -+GEN_TWOVEC_TEST(fmov_d_imm_02, "fmov d22, #-4.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_d_imm_03, "fmov d22, #1.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_s_imm_01, "fmov s22, #0.125", 22, 23) -+GEN_TWOVEC_TEST(fmov_s_imm_02, "fmov s22, #-4.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_s_imm_03, "fmov s22, #-1.0", 22, 23) -+ -+GEN_ONEINT_ONEVEC_TEST(fmov_s_w, "fmov s7, w15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(fmov_d_x, "fmov d7, x15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(fmov_d1_x, "fmov v7.d[1], x15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(fmov_w_s, "fmov w15, s7", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(fmov_x_d, "fmov x15, d7", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(fmov_x_d1, "fmov x15, v7.d[1]", 15, 7) -+ -+GEN_TWOVEC_TEST(fmov_2d_imm_01, "fmov v22.2d, #0.125", 22, 23) -+GEN_TWOVEC_TEST(fmov_2d_imm_02, "fmov v22.2d, #-4.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_2d_imm_03, "fmov v22.2d, #1.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_4s_imm_01, "fmov v22.4s, #0.125", 22, 23) -+GEN_TWOVEC_TEST(fmov_4s_imm_02, "fmov v22.4s, #-4.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_4s_imm_03, "fmov v22.4s, #1.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_2s_imm_01, "fmov v22.2s, #0.125", 22, 23) -+GEN_TWOVEC_TEST(fmov_2s_imm_02, "fmov v22.2s, #-4.0", 22, 23) -+GEN_TWOVEC_TEST(fmov_2s_imm_03, "fmov v22.2s, #1.0", 22, 23) -+ -+GEN_ONEINT_ONEVEC_TEST(scvtf_s_w, "scvtf s7, w15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(scvtf_d_w, "scvtf d7, w15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(scvtf_s_x, "scvtf s7, x15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(scvtf_d_x, "scvtf d7, x15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w, "ucvtf s7, w15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w, "ucvtf d7, w15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x, "ucvtf s7, x15", 15, 7) -+GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x, "ucvtf d7, x15", 15, 7) -+ -+GEN_THREEVEC_TEST(fadd_d_d_d, "fadd d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(fadd_s_s_s, "fadd s2, s11, s29", 2, 11, 29) -+GEN_THREEVEC_TEST(fsub_d_d_d, "fsub d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(fsub_s_s_s, "fsub s2, s11, s29", 2, 11, 29) -+GEN_THREEVEC_TEST(fmul_d_d_d, "fmul d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(fmul_s_s_s, "fmul s2, s11, s29", 2, 11, 29) -+GEN_THREEVEC_TEST(fdiv_d_d_d, "fdiv d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(fdiv_s_s_s, "fdiv s2, s11, s29", 2, 11, 29) -+GEN_THREEVEC_TEST(fnmul_d_d_d, "fnmul d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(fnmul_s_s_s, "fnmul s2, s11, s29", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(fabd_d_d_d, "fabd d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(fabd_s_s_s, "fabd s2, s11, s29", 2, 11, 29) -+ -+GEN_TWOVEC_TEST(fmov_d_d, "fmov d22, d23", 22, 23) -+GEN_TWOVEC_TEST(fmov_s_s, "fmov s22, s23", 22, 23) -+GEN_TWOVEC_TEST(fabs_d_d, "fabs d22, d23", 22, 23) -+GEN_TWOVEC_TEST(fabs_s_s, "fabs s22, s23", 22, 23) -+GEN_TWOVEC_TEST(fneg_d_d, "fneg d22, d23", 22, 23) -+GEN_TWOVEC_TEST(fneg_s_s, "fneg s22, s23", 22, 23) -+GEN_TWOVEC_TEST(fsqrt_d_d, "fsqrt d22, d23", 22, 23) -+GEN_TWOVEC_TEST(fsqrt_s_s, "fsqrt s22, s23", 22, 23) -+ -+GEN_UNARY_TEST(fneg, 2d, 2d) -+GEN_UNARY_TEST(fneg, 4s, 4s) -+GEN_UNARY_TEST(fneg, 2s, 2s) -+GEN_UNARY_TEST(fabs, 2d, 2d) -+GEN_UNARY_TEST(fabs, 4s, 4s) -+GEN_UNARY_TEST(fabs, 2s, 2s) -+ -+GEN_BINARY_TEST(fcmeq, 2d, 2d, 2d) -+GEN_BINARY_TEST(fcmeq, 4s, 4s, 4s) -+GEN_BINARY_TEST(fcmeq, 2s, 2s, 2s) -+GEN_BINARY_TEST(fcmge, 2d, 2d, 2d) -+GEN_BINARY_TEST(fcmge, 4s, 4s, 4s) -+GEN_BINARY_TEST(fcmge, 2s, 2s, 2s) -+GEN_BINARY_TEST(fcmgt, 2d, 2d, 2d) -+GEN_BINARY_TEST(fcmgt, 4s, 4s, 4s) -+GEN_BINARY_TEST(fcmgt, 2s, 2s, 2s) -+GEN_BINARY_TEST(facge, 2d, 2d, 2d) -+GEN_BINARY_TEST(facge, 4s, 4s, 4s) -+GEN_BINARY_TEST(facge, 2s, 2s, 2s) -+GEN_BINARY_TEST(facgt, 2d, 2d, 2d) -+GEN_BINARY_TEST(facgt, 4s, 4s, 4s) -+GEN_BINARY_TEST(facgt, 2s, 2s, 2s) -+ -+// Uses v15 as the first table entry -+GEN_THREEVEC_TEST( -+ tbl_16b_1reg, "tbl v21.16b, {v15.16b}, v23.16b", 21, 15, 23) -+// and v15 ^ v21 as the second table entry -+GEN_THREEVEC_TEST( -+ tbl_16b_2reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "tbl v21.16b, {v15.16b, v16.16b}, v23.16b", 21, 15, 23) -+// and v15 ^ v23 as the third table entry -+GEN_THREEVEC_TEST( -+ tbl_16b_3reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "tbl v21.16b, {v15.16b, v16.16b, v17.16b}, v23.16b", -+ 21, 15, 23) -+// and v21 ^ v23 as the fourth table entry -+GEN_THREEVEC_TEST( -+ tbl_16b_4reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "eor v18.16b, v21.16b, v23.16b ; " -+ "tbl v21.16b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.16b", -+ 21, 15, 23) -+ -+// Same register scheme for tbl .8b, tbx .16b, tbx.8b -+GEN_THREEVEC_TEST( -+ tbl_8b_1reg, "tbl v21.8b, {v15.16b}, v23.8b", 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbl_8b_2reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "tbl v21.8b, {v15.16b, v16.16b}, v23.8b", 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbl_8b_3reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "tbl v21.8b, {v15.16b, v16.16b, v17.16b}, v23.8b", -+ 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbl_8b_4reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "eor v18.16b, v21.16b, v23.16b ; " -+ "tbl v21.8b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.8b", -+ 21, 15, 23) -+ -+GEN_THREEVEC_TEST( -+ tbx_16b_1reg, "tbx v21.16b, {v15.16b}, v23.16b", 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbx_16b_2reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "tbx v21.16b, {v15.16b, v16.16b}, v23.16b", 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbx_16b_3reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "tbx v21.16b, {v15.16b, v16.16b, v17.16b}, v23.16b", -+ 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbx_16b_4reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "eor v18.16b, v21.16b, v23.16b ; " -+ "tbx v21.16b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.16b", -+ 21, 15, 23) -+ -+// Same register scheme for tbx .8b, tbx .16b, tbx.8b -+GEN_THREEVEC_TEST( -+ tbx_8b_1reg, "tbx v21.8b, {v15.16b}, v23.8b", 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbx_8b_2reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "tbx v21.8b, {v15.16b, v16.16b}, v23.8b", 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbx_8b_3reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "tbx v21.8b, {v15.16b, v16.16b, v17.16b}, v23.8b", -+ 21, 15, 23) -+GEN_THREEVEC_TEST( -+ tbx_8b_4reg, "eor v16.16b, v15.16b, v21.16b ; " -+ "eor v17.16b, v15.16b, v23.16b ; " -+ "eor v18.16b, v21.16b, v23.16b ; " -+ "tbx v21.8b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.8b", -+ 21, 15, 23) -+ -+GEN_TWOVEC_TEST(cmge_zero_2d_2d, "cmge v5.2d, v22.2d, #0", 5, 22) -+GEN_TWOVEC_TEST(cmge_zero_4s_4s, "cmge v5.4s, v22.4s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmge_zero_2s_2s, "cmge v5.2s, v22.2s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmge_zero_8h_8h, "cmge v5.8h, v22.8h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmge_zero_4h_4h, "cmge v5.4h, v22.4h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmge_zero_16b_16b, "cmge v5.16b, v22.16b, #0", 5, 22) -+GEN_TWOVEC_TEST(cmge_zero_8b_8b, "cmge v5.8b, v22.8b, #0", 5, 22) -+ -+GEN_TWOVEC_TEST(cmgt_zero_2d_2d, "cmgt v5.2d, v22.2d, #0", 5, 22) -+GEN_TWOVEC_TEST(cmgt_zero_4s_4s, "cmgt v5.4s, v22.4s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmgt_zero_2s_2s, "cmgt v5.2s, v22.2s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmgt_zero_8h_8h, "cmgt v5.8h, v22.8h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmgt_zero_4h_4h, "cmgt v5.4h, v22.4h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmgt_zero_16b_16b, "cmgt v5.16b, v22.16b, #0", 5, 22) -+GEN_TWOVEC_TEST(cmgt_zero_8b_8b, "cmgt v5.8b, v22.8b, #0", 5, 22) -+ -+GEN_TWOVEC_TEST(cmle_zero_2d_2d, "cmle v5.2d, v22.2d, #0", 5, 22) -+GEN_TWOVEC_TEST(cmle_zero_4s_4s, "cmle v5.4s, v22.4s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmle_zero_2s_2s, "cmle v5.2s, v22.2s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmle_zero_8h_8h, "cmle v5.8h, v22.8h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmle_zero_4h_4h, "cmle v5.4h, v22.4h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmle_zero_16b_16b, "cmle v5.16b, v22.16b, #0", 5, 22) -+GEN_TWOVEC_TEST(cmle_zero_8b_8b, "cmle v5.8b, v22.8b, #0", 5, 22) -+ -+GEN_TWOVEC_TEST(cmeq_zero_2d_2d, "cmeq v5.2d, v22.2d, #0", 5, 22) -+GEN_TWOVEC_TEST(cmeq_zero_4s_4s, "cmeq v5.4s, v22.4s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmeq_zero_2s_2s, "cmeq v5.2s, v22.2s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmeq_zero_8h_8h, "cmeq v5.8h, v22.8h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmeq_zero_4h_4h, "cmeq v5.4h, v22.4h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmeq_zero_16b_16b, "cmeq v5.16b, v22.16b, #0", 5, 22) -+GEN_TWOVEC_TEST(cmeq_zero_8b_8b, "cmeq v5.8b, v22.8b, #0", 5, 22) -+ -+GEN_TWOVEC_TEST(cmlt_zero_2d_2d, "cmlt v5.2d, v22.2d, #0", 5, 22) -+GEN_TWOVEC_TEST(cmlt_zero_4s_4s, "cmlt v5.4s, v22.4s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmlt_zero_2s_2s, "cmlt v5.2s, v22.2s, #0", 5, 22) -+GEN_TWOVEC_TEST(cmlt_zero_8h_8h, "cmlt v5.8h, v22.8h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmlt_zero_4h_4h, "cmlt v5.4h, v22.4h, #0", 5, 22) -+GEN_TWOVEC_TEST(cmlt_zero_16b_16b, "cmlt v5.16b, v22.16b, #0", 5, 22) -+GEN_TWOVEC_TEST(cmlt_zero_8b_8b, "cmlt v5.8b, v22.8b, #0", 5, 22) -+ -+GEN_TWOVEC_TEST(abs_d_d, "abs d22, d23", 22, 23) -+GEN_TWOVEC_TEST(neg_d_d, "neg d22, d23", 22, 23) -+ -+GEN_UNARY_TEST(abs, 2d, 2d) -+GEN_UNARY_TEST(abs, 4s, 4s) -+GEN_UNARY_TEST(abs, 2s, 2s) -+GEN_UNARY_TEST(abs, 8h, 8h) -+GEN_UNARY_TEST(abs, 4h, 4h) -+GEN_UNARY_TEST(abs, 16b, 16b) -+GEN_UNARY_TEST(abs, 8b, 8b) -+ -+GEN_BINARY_TEST(addhn, 2s, 2d, 2d) -+GEN_BINARY_TEST(addhn2, 4s, 2d, 2d) -+GEN_BINARY_TEST(addhn, 4h, 4s, 4s) -+GEN_BINARY_TEST(addhn2, 8h, 4s, 4s) -+GEN_BINARY_TEST(addhn, 8b, 8h, 8h) -+GEN_BINARY_TEST(addhn2, 16b, 8h, 8h) -+GEN_BINARY_TEST(subhn, 2s, 2d, 2d) -+GEN_BINARY_TEST(subhn2, 4s, 2d, 2d) -+GEN_BINARY_TEST(subhn, 4h, 4s, 4s) -+GEN_BINARY_TEST(subhn2, 8h, 4s, 4s) -+GEN_BINARY_TEST(subhn, 8b, 8h, 8h) -+GEN_BINARY_TEST(subhn2, 16b, 8h, 8h) -+GEN_BINARY_TEST(raddhn, 2s, 2d, 2d) -+GEN_BINARY_TEST(raddhn2, 4s, 2d, 2d) -+GEN_BINARY_TEST(raddhn, 4h, 4s, 4s) -+GEN_BINARY_TEST(raddhn2, 8h, 4s, 4s) -+GEN_BINARY_TEST(raddhn, 8b, 8h, 8h) -+GEN_BINARY_TEST(raddhn2, 16b, 8h, 8h) -+GEN_BINARY_TEST(rsubhn, 2s, 2d, 2d) -+GEN_BINARY_TEST(rsubhn2, 4s, 2d, 2d) -+GEN_BINARY_TEST(rsubhn, 4h, 4s, 4s) -+GEN_BINARY_TEST(rsubhn2, 8h, 4s, 4s) -+GEN_BINARY_TEST(rsubhn, 8b, 8h, 8h) -+GEN_BINARY_TEST(rsubhn2, 16b, 8h, 8h) -+ -+GEN_TWOVEC_TEST(addp_d_2d, "addp d22, v23.2d", 22, 23) -+ -+GEN_BINARY_TEST(addp, 2d, 2d, 2d) -+GEN_BINARY_TEST(addp, 4s, 4s, 4s) -+GEN_BINARY_TEST(addp, 2s, 2s, 2s) -+GEN_BINARY_TEST(addp, 8h, 8h, 8h) -+GEN_BINARY_TEST(addp, 4h, 4h, 4h) -+GEN_BINARY_TEST(addp, 16b, 16b, 16b) -+GEN_BINARY_TEST(addp, 8b, 8b, 8b) -+ -+GEN_TWOVEC_TEST(addv_s_4s, "addv s22, v23.4s", 22, 23) -+GEN_TWOVEC_TEST(addv_h_8h, "addv h22, v23.8h", 22, 23) -+GEN_TWOVEC_TEST(addv_h_4h, "addv h22, v23.4h", 22, 23) -+GEN_TWOVEC_TEST(addv_b_16b, "addv b22, v23.16b", 22, 23) -+GEN_TWOVEC_TEST(addv_b_8b, "addv b22, v23.8b", 22, 23) -+ -+/* overkill -- don't need two vecs, only one */ -+GEN_TWOVEC_TEST(orr_8h_0x5A_lsl0, "orr v22.8h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(orr_8h_0xA5_lsl8, "orr v22.8h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(orr_4h_0x5A_lsl0, "orr v22.4h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(orr_4h_0xA5_lsl8, "orr v22.4h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(orr_4s_0x5A_lsl0, "orr v22.4s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(orr_4s_0x6B_lsl8, "orr v22.4s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(orr_4s_0x49_lsl16, "orr v22.4s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(orr_4s_0x3D_lsl24, "orr v22.4s, #0x3D, LSL #24", 22, 23) -+GEN_TWOVEC_TEST(orr_2s_0x5A_lsl0, "orr v22.2s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(orr_2s_0x6B_lsl8, "orr v22.2s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(orr_2s_0x49_lsl16, "orr v22.2s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(orr_2s_0x3D_lsl24, "orr v22.2s, #0x3D, LSL #24", 22, 23) -+GEN_TWOVEC_TEST(bic_8h_0x5A_lsl0, "bic v22.8h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(bic_8h_0xA5_lsl8, "bic v22.8h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(bic_4h_0x5A_lsl0, "bic v22.4h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(bic_4h_0xA5_lsl8, "bic v22.4h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(bic_4s_0x5A_lsl0, "bic v22.4s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(bic_4s_0x6B_lsl8, "bic v22.4s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(bic_4s_0x49_lsl16, "bic v22.4s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(bic_4s_0x3D_lsl24, "bic v22.4s, #0x3D, LSL #24", 22, 23) -+GEN_TWOVEC_TEST(bic_2s_0x5A_lsl0, "bic v22.2s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(bic_2s_0x6B_lsl8, "bic v22.2s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(bic_2s_0x49_lsl16, "bic v22.2s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(bic_2s_0x3D_lsl24, "bic v22.2s, #0x3D, LSL #24", 22, 23) -+ -+GEN_UNARY_TEST(cls, 4s, 4s) -+GEN_UNARY_TEST(cls, 2s, 2s) -+GEN_UNARY_TEST(cls, 8h, 8h) -+GEN_UNARY_TEST(cls, 4h, 4h) -+GEN_UNARY_TEST(cls, 16b, 16b) -+GEN_UNARY_TEST(cls, 8b, 8b) -+ -+GEN_UNARY_TEST(clz, 4s, 4s) -+GEN_UNARY_TEST(clz, 2s, 2s) -+GEN_UNARY_TEST(clz, 8h, 8h) -+GEN_UNARY_TEST(clz, 4h, 4h) -+GEN_UNARY_TEST(clz, 16b, 16b) -+GEN_UNARY_TEST(clz, 8b, 8b) -+ -+GEN_THREEVEC_TEST(cmeq_d_d_d, "cmeq d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(cmge_d_d_d, "cmge d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(cmgt_d_d_d, "cmgt d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(cmhi_d_d_d, "cmhi d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(cmhs_d_d_d, "cmhs d2, d11, d29", 2, 11, 29) -+GEN_THREEVEC_TEST(cmtst_d_d_d, "cmtst d2, d11, d29", 2, 11, 29) -+ -+GEN_TWOVEC_TEST(cmeq_zero_d_d, "cmeq d2, d11, #0", 2, 11) -+GEN_TWOVEC_TEST(cmge_zero_d_d, "cmge d2, d11, #0", 2, 11) -+GEN_TWOVEC_TEST(cmgt_zero_d_d, "cmgt d2, d11, #0", 2, 11) -+GEN_TWOVEC_TEST(cmle_zero_d_d, "cmle d2, d11, #0", 2, 11) -+GEN_TWOVEC_TEST(cmlt_zero_d_d, "cmlt d2, d11, #0", 2, 11) -+ -+GEN_UNARY_TEST(cnt, 16b, 16b) -+GEN_UNARY_TEST(cnt, 8b, 8b) -+ -+GEN_TWOVEC_TEST(dup_d_d0, "dup d22, v23.d[0]", 22, 23) -+GEN_TWOVEC_TEST(dup_d_d1, "dup d22, v23.d[1]", 22, 23) -+GEN_TWOVEC_TEST(dup_s_s0, "dup s22, v23.s[0]", 22, 23) -+GEN_TWOVEC_TEST(dup_s_s3, "dup s22, v23.s[3]", 22, 23) -+GEN_TWOVEC_TEST(dup_h_h0, "dup h22, v23.h[0]", 22, 23) -+GEN_TWOVEC_TEST(dup_h_h6, "dup h22, v23.h[6]", 22, 23) -+GEN_TWOVEC_TEST(dup_b_b0, "dup b0, v23.b[0]", 22, 23) -+GEN_TWOVEC_TEST(dup_b_b13, "dup b13, v23.b[13]", 22, 23) -+ -+GEN_TWOVEC_TEST(dup_2d_d0, "dup v9.2d, v17.d[0]", 9, 17) -+GEN_TWOVEC_TEST(dup_2d_d1, "dup v9.2d, v17.d[1]", 9, 17) -+GEN_TWOVEC_TEST(dup_4s_s0, "dup v9.4s, v17.s[0]", 9, 17) -+GEN_TWOVEC_TEST(dup_4s_s3, "dup v9.4s, v17.s[3]", 9, 17) -+GEN_TWOVEC_TEST(dup_2s_s0, "dup v9.2s, v17.s[0]", 9, 17) -+GEN_TWOVEC_TEST(dup_2s_s2, "dup v9.2s, v17.s[2]", 9, 17) -+GEN_TWOVEC_TEST(dup_8h_h0, "dup v9.8h, v17.h[0]", 9, 17) -+GEN_TWOVEC_TEST(dup_8h_h6, "dup v9.8h, v17.h[6]", 9, 17) -+GEN_TWOVEC_TEST(dup_4h_h1, "dup v9.4h, v17.h[1]", 9, 17) -+GEN_TWOVEC_TEST(dup_4h_h5, "dup v9.4h, v17.h[5]", 9, 17) -+GEN_TWOVEC_TEST(dup_16b_b2, "dup v9.16b, v17.b[2]", 9, 17) -+GEN_TWOVEC_TEST(dup_16b_b12, "dup v9.16b, v17.b[12]", 9, 17) -+GEN_TWOVEC_TEST(dup_8b_b3, "dup v9.8b, v17.b[3]", 9, 17) -+GEN_TWOVEC_TEST(dup_8b_b13, "dup v9.8b, v17.b[13]", 9, 17) -+ -+GEN_TWOVEC_TEST(dup_2d_x, "mov x10, v17.d[0]; dup v9.2d, x10", 9, 17) -+GEN_TWOVEC_TEST(dup_4s_w, "mov x10, v17.d[0]; dup v9.4s, w10", 9, 17) -+GEN_TWOVEC_TEST(dup_2s_w, "mov x10, v17.d[0]; dup v9.2s, w10", 9, 17) -+GEN_TWOVEC_TEST(dup_8h_w, "mov x10, v17.d[0]; dup v9.8h, w10", 9, 17) -+GEN_TWOVEC_TEST(dup_4h_w, "mov x10, v17.d[0]; dup v9.4h, w10", 9, 17) -+GEN_TWOVEC_TEST(dup_16b_w, "mov x10, v17.d[0]; dup v9.16b, w10", 9, 17) -+GEN_TWOVEC_TEST(dup_8b_w, "mov x10, v17.d[0]; dup v9.8b, w10", 9, 17) -+ -+GEN_THREEVEC_TEST(ext_16b_16b_16b_0x0, -+ "ext v2.16b, v11.16b, v29.16b, #0", 2, 11, 29) -+GEN_THREEVEC_TEST(ext_16b_16b_16b_0x7, -+ "ext v2.16b, v11.16b, v29.16b, #7", 2, 11, 29) -+GEN_THREEVEC_TEST(ext_16b_16b_16b_0x8, -+ "ext v2.16b, v11.16b, v29.16b, #8", 2, 11, 29) -+GEN_THREEVEC_TEST(ext_16b_16b_16b_0x9, -+ "ext v2.16b, v11.16b, v29.16b, #9", 2, 11, 29) -+GEN_THREEVEC_TEST(ext_16b_16b_16b_0xF, -+ "ext v2.16b, v11.16b, v29.16b, #15", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(ext_8b_8b_8b_0x0, -+ "ext v2.8b, v11.8b, v29.8b, #0", 2, 11, 29) -+GEN_THREEVEC_TEST(ext_8b_8b_8b_0x1, -+ "ext v2.8b, v11.8b, v29.8b, #1", 2, 11, 29) -+GEN_THREEVEC_TEST(ext_8b_8b_8b_0x6, -+ "ext v2.8b, v11.8b, v29.8b, #6", 2, 11, 29) -+GEN_THREEVEC_TEST(ext_8b_8b_8b_0x7, -+ "ext v2.8b, v11.8b, v29.8b, #7", 2, 11, 29) -+ -+ -+GEN_TWOVEC_TEST(ins_d0_d0, "ins v3.d[0], v24.d[0]", 3, 24) -+GEN_TWOVEC_TEST(ins_d0_d1, "ins v3.d[0], v24.d[1]", 3, 24) -+GEN_TWOVEC_TEST(ins_d1_d0, "ins v3.d[1], v24.d[0]", 3, 24) -+GEN_TWOVEC_TEST(ins_d1_d1, "ins v3.d[1], v24.d[1]", 3, 24) -+ -+GEN_TWOVEC_TEST(ins_s0_s2, "ins v3.s[0], v24.s[2]", 3, 24) -+GEN_TWOVEC_TEST(ins_s3_s0, "ins v3.s[3], v24.s[0]", 3, 24) -+GEN_TWOVEC_TEST(ins_s2_s1, "ins v3.s[2], v24.s[1]", 3, 24) -+GEN_TWOVEC_TEST(ins_s1_s3, "ins v3.s[1], v24.s[3]", 3, 24) -+ -+GEN_TWOVEC_TEST(ins_h0_h6, "ins v3.h[0], v24.h[6]", 3, 24) -+GEN_TWOVEC_TEST(ins_h7_h0, "ins v3.h[7], v24.h[0]", 3, 24) -+GEN_TWOVEC_TEST(ins_h6_h1, "ins v3.h[6], v24.h[1]", 3, 24) -+GEN_TWOVEC_TEST(ins_h1_h7, "ins v3.h[1], v24.h[7]", 3, 24) -+ -+GEN_TWOVEC_TEST(ins_b0_b14, "ins v3.b[0], v24.b[14]", 3, 24) -+GEN_TWOVEC_TEST(ins_b15_b8, "ins v3.b[15], v24.b[8]", 3, 24) -+GEN_TWOVEC_TEST(ins_b13_b9, "ins v3.b[13], v24.b[9]", 3, 24) -+GEN_TWOVEC_TEST(ins_b5_b12, "ins v3.b[5], v24.b[12]", 3, 24) -+ -+GEN_THREEVEC_TEST(mla_4s_4s_s0, "mla v2.4s, v11.4s, v29.s[0]", 2, 11, 29) -+GEN_THREEVEC_TEST(mla_4s_4s_s3, "mla v2.4s, v11.4s, v29.s[3]", 2, 11, 29) -+GEN_THREEVEC_TEST(mla_2s_2s_s0, "mla v2.2s, v11.2s, v29.s[0]", 2, 11, 29) -+GEN_THREEVEC_TEST(mla_2s_2s_s3, "mla v2.2s, v11.2s, v29.s[3]", 2, 11, 29) -+// For the 'h' version of these, Rm can only be <= 15 (!) -+GEN_THREEVEC_TEST(mla_8h_8h_h1, "mla v2.8h, v11.8h, v2.h[1]", 2, 11, 9) -+GEN_THREEVEC_TEST(mla_8h_8h_h5, "mla v2.8h, v11.8h, v2.h[5]", 2, 11, 9) -+GEN_THREEVEC_TEST(mla_4h_4h_h2, "mla v2.4h, v11.4h, v2.h[2]", 2, 11, 9) -+GEN_THREEVEC_TEST(mla_4h_4h_h7, "mla v2.4h, v11.4h, v2.h[7]", 2, 11, 9) -+ -+GEN_THREEVEC_TEST(mls_4s_4s_s0, "mls v2.4s, v11.4s, v29.s[0]", 2, 11, 29) -+GEN_THREEVEC_TEST(mls_4s_4s_s3, "mls v2.4s, v11.4s, v29.s[3]", 2, 11, 29) -+GEN_THREEVEC_TEST(mls_2s_2s_s0, "mls v2.2s, v11.2s, v29.s[0]", 2, 11, 29) -+GEN_THREEVEC_TEST(mls_2s_2s_s3, "mls v2.2s, v11.2s, v29.s[3]", 2, 11, 29) -+// For the 'h' version of these, Rm can only be <= 15 (!) -+GEN_THREEVEC_TEST(mls_8h_8h_h1, "mls v2.8h, v11.8h, v2.h[1]", 2, 11, 9) -+GEN_THREEVEC_TEST(mls_8h_8h_h5, "mls v2.8h, v11.8h, v2.h[5]", 2, 11, 9) -+GEN_THREEVEC_TEST(mls_4h_4h_h2, "mls v2.4h, v11.4h, v2.h[2]", 2, 11, 9) -+GEN_THREEVEC_TEST(mls_4h_4h_h7, "mls v2.4h, v11.4h, v2.h[7]", 2, 11, 9) -+ -+GEN_THREEVEC_TEST(mul_4s_4s_s0, "mul v2.4s, v11.4s, v29.s[0]", 2, 11, 29) -+GEN_THREEVEC_TEST(mul_4s_4s_s3, "mul v2.4s, v11.4s, v29.s[3]", 2, 11, 29) -+GEN_THREEVEC_TEST(mul_2s_2s_s0, "mul v2.2s, v11.2s, v29.s[0]", 2, 11, 29) -+GEN_THREEVEC_TEST(mul_2s_2s_s3, "mul v2.2s, v11.2s, v29.s[3]", 2, 11, 29) -+// For the 'h' version of these, Rm can only be <= 15 (!) -+GEN_THREEVEC_TEST(mul_8h_8h_h1, "mul v2.8h, v11.8h, v2.h[1]", 2, 11, 9) -+GEN_THREEVEC_TEST(mul_8h_8h_h5, "mul v2.8h, v11.8h, v2.h[5]", 2, 11, 9) -+GEN_THREEVEC_TEST(mul_4h_4h_h2, "mul v2.4h, v11.4h, v2.h[2]", 2, 11, 9) -+GEN_THREEVEC_TEST(mul_4h_4h_h7, "mul v2.4h, v11.4h, v2.h[7]", 2, 11, 9) -+ -+/* overkill -- don't need two vecs, only one */ -+GEN_TWOVEC_TEST(movi_16b_0x9C_lsl0, "movi v22.16b, #0x9C, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(movi_8b_0x8B_lsl0, "movi v22.8b, #0x8B, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(movi_8h_0x5A_lsl0, "movi v22.8h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(movi_8h_0xA5_lsl8, "movi v22.8h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(movi_4h_0x5A_lsl0, "movi v22.4h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(movi_4h_0xA5_lsl8, "movi v22.4h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(movi_4s_0x5A_lsl0, "movi v22.4s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(movi_4s_0x6B_lsl8, "movi v22.4s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(movi_4s_0x49_lsl16, "movi v22.4s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(movi_4s_0x3D_lsl24, "movi v22.4s, #0x3D, LSL #24", 22, 23) -+GEN_TWOVEC_TEST(movi_2s_0x5A_lsl0, "movi v22.2s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(movi_2s_0x6B_lsl8, "movi v22.2s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(movi_2s_0x49_lsl16, "movi v22.2s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(movi_2s_0x3D_lsl24, "movi v22.2s, #0x3D, LSL #24", 22, 23) -+GEN_TWOVEC_TEST(movi_4s_0x6B_msl8, "movi v22.4s, #0x6B, MSL #8", 22, 23) -+GEN_TWOVEC_TEST(movi_4s_0x94_msl16, "movi v22.4s, #0x94, MSL #16", 22, 23) -+GEN_TWOVEC_TEST(movi_2s_0x7A_msl8, "movi v22.2s, #0x7A, MSL #8", 22, 23) -+GEN_TWOVEC_TEST(movi_2s_0xA5_msl16, "movi v22.2s, #0xA5, MSL #16", 22, 23) -+ -+GEN_TWOVEC_TEST(movi_d_0xA5, "movi d22, #0xFF00FF0000FF00FF", 22, 23) -+GEN_TWOVEC_TEST(movi_2d_0xB4, "movi v22.2d, #0xFF00FFFF00FF0000", 22, 23) -+ -+/* overkill -- don't need two vecs, only one */ -+GEN_TWOVEC_TEST(mvni_8h_0x5A_lsl0, "mvni v22.8h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(mvni_8h_0xA5_lsl8, "mvni v22.8h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(mvni_4h_0x5A_lsl0, "mvni v22.4h, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(mvni_4h_0xA5_lsl8, "mvni v22.4h, #0xA5, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(mvni_4s_0x5A_lsl0, "mvni v22.4s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(mvni_4s_0x6B_lsl8, "mvni v22.4s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(mvni_4s_0x49_lsl16, "mvni v22.4s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(mvni_4s_0x3D_lsl24, "mvni v22.4s, #0x3D, LSL #24", 22, 23) -+GEN_TWOVEC_TEST(mvni_2s_0x5A_lsl0, "mvni v22.2s, #0x5A, LSL #0", 22, 23) -+GEN_TWOVEC_TEST(mvni_2s_0x6B_lsl8, "mvni v22.2s, #0x6B, LSL #8", 22, 23) -+GEN_TWOVEC_TEST(mvni_2s_0x49_lsl16, "mvni v22.2s, #0x49, LSL #16", 22, 23) -+GEN_TWOVEC_TEST(mvni_2s_0x3D_lsl24, "mvni v22.2s, #0x3D, LSL #24", 22, 23) -+GEN_TWOVEC_TEST(mvni_4s_0x6B_msl8, "mvni v22.4s, #0x6B, MSL #8", 22, 23) -+GEN_TWOVEC_TEST(mvni_4s_0x94_msl16, "mvni v22.4s, #0x94, MSL #16", 22, 23) -+GEN_TWOVEC_TEST(mvni_2s_0x7A_msl8, "mvni v22.2s, #0x7A, MSL #8", 22, 23) -+GEN_TWOVEC_TEST(mvni_2s_0xA5_msl16, "mvni v22.2s, #0xA5, MSL #16", 22, 23) -+ -+GEN_UNARY_TEST(not, 16b, 16b) -+GEN_UNARY_TEST(not, 8b, 8b) -+ -+GEN_BINARY_TEST(pmul, 16b, 16b, 16b) -+GEN_BINARY_TEST(pmul, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(pmull, 8h, 8b, 8b) -+GEN_BINARY_TEST(pmull2, 8h, 16b, 16b) -+//GEN_BINARY_TEST(pmull, 1q, 1d, 1d) -+//GEN_BINARY_TEST(pmull, 1q, 2d, 2d) -+ -+GEN_UNARY_TEST(rbit, 16b, 16b) -+GEN_UNARY_TEST(rbit, 8b, 8b) -+GEN_UNARY_TEST(rev16, 16b, 16b) -+GEN_UNARY_TEST(rev16, 8b, 8b) -+GEN_UNARY_TEST(rev32, 16b, 16b) -+GEN_UNARY_TEST(rev32, 8b, 8b) -+GEN_UNARY_TEST(rev32, 8h, 8h) -+GEN_UNARY_TEST(rev32, 4h, 4h) -+GEN_UNARY_TEST(rev64, 16b, 16b) -+GEN_UNARY_TEST(rev64, 8b, 8b) -+GEN_UNARY_TEST(rev64, 8h, 8h) -+GEN_UNARY_TEST(rev64, 4h, 4h) -+GEN_UNARY_TEST(rev64, 4s, 4s) -+GEN_UNARY_TEST(rev64, 2s, 2s) -+ -+GEN_BINARY_TEST(saba, 4s, 4s, 4s) -+GEN_BINARY_TEST(saba, 2s, 2s, 2s) -+GEN_BINARY_TEST(saba, 8h, 8h, 8h) -+GEN_BINARY_TEST(saba, 4h, 4h, 4h) -+GEN_BINARY_TEST(saba, 16b, 16b, 16b) -+GEN_BINARY_TEST(saba, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(uaba, 4s, 4s, 4s) -+GEN_BINARY_TEST(uaba, 2s, 2s, 2s) -+GEN_BINARY_TEST(uaba, 8h, 8h, 8h) -+GEN_BINARY_TEST(uaba, 4h, 4h, 4h) -+GEN_BINARY_TEST(uaba, 16b, 16b, 16b) -+GEN_BINARY_TEST(uaba, 8b, 8b, 8b) -+ -+GEN_THREEVEC_TEST(sabal_2d_2s_2s, "sabal v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(sabal2_2d_4s_4s, "sabal2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(sabal_4s_4h_4h, "sabal v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(sabal2_4s_8h_8h, "sabal2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(sabal_8h_8b_8b, "sabal v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(sabal2_8h_16b_16b, -+ "sabal2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uabal_2d_2s_2s, "uabal v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(uabal2_2d_4s_4s, "uabal2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uabal_4s_4h_4h, "uabal v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(uabal2_4s_8h_8h, "uabal2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uabal_8h_8b_8b, "uabal v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(uabal2_8h_16b_16b, -+ "uabal2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(sabd_4s_4s_4s, "sabd v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(sabd_2s_2s_2s, "sabd v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(sabd_8h_8h_8h, "sabd v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(sabd_4h_4h_4h, "sabd v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(sabd_16b_16b_16b, "sabd v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(sabd_8b_8b_8b, "sabd v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uabd_4s_4s_4s, "uabd v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(uabd_2s_2s_2s, "uabd v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(uabd_8h_8h_8h, "uabd v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(uabd_4h_4h_4h, "uabd v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(uabd_16b_16b_16b, "uabd v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(uabd_8b_8b_8b, "uabd v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(sabdl_2d_2s_2s, "sabdl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(sabdl2_2d_4s_4s, "sabdl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(sabdl_4s_4h_4h, "sabdl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(sabdl2_4s_8h_8h, "sabdl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(sabdl_8h_8b_8b, "sabdl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(sabdl2_8h_16b_16b, -+ "sabdl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uabdl_2d_2s_2s, "uabdl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(uabdl2_2d_4s_4s, "uabdl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uabdl_4s_4h_4h, "uabdl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(uabdl2_4s_8h_8h, "uabdl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uabdl_8h_8b_8b, "uabdl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(uabdl2_8h_16b_16b, -+ "uabdl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_TWOVEC_TEST(sadalp_4h_8b, "sadalp v3.4h, v19.8b", 3, 19) -+GEN_TWOVEC_TEST(sadalp_8h_16b, "sadalp v3.8h, v19.16b", 3, 19) -+GEN_TWOVEC_TEST(sadalp_2s_4h, "sadalp v3.2s, v19.4h", 3, 19) -+GEN_TWOVEC_TEST(sadalp_4s_8h, "sadalp v3.4s, v19.8h", 3, 19) -+GEN_TWOVEC_TEST(sadalp_1d_2s, "sadalp v3.1d, v19.2s", 3, 19) -+GEN_TWOVEC_TEST(sadalp_2d_4s, "sadalp v3.2d, v19.4s", 3, 19) -+ -+GEN_TWOVEC_TEST(uadalp_4h_8b, "uadalp v3.4h, v19.8b", 3, 19) -+GEN_TWOVEC_TEST(uadalp_8h_16b, "uadalp v3.8h, v19.16b", 3, 19) -+GEN_TWOVEC_TEST(uadalp_2s_4h, "uadalp v3.2s, v19.4h", 3, 19) -+GEN_TWOVEC_TEST(uadalp_4s_8h, "uadalp v3.4s, v19.8h", 3, 19) -+GEN_TWOVEC_TEST(uadalp_1d_2s, "uadalp v3.1d, v19.2s", 3, 19) -+GEN_TWOVEC_TEST(uadalp_2d_4s, "uadalp v3.2d, v19.4s", 3, 19) -+ -+GEN_THREEVEC_TEST(saddl_2d_2s_2s, "saddl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(saddl2_2d_4s_4s, "saddl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(saddl_4s_4h_4h, "saddl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(saddl2_4s_8h_8h, "saddl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(saddl_8h_8b_8b, "saddl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(saddl2_8h_16b_16b, -+ "saddl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uaddl_2d_2s_2s, "uaddl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(uaddl2_2d_4s_4s, "uaddl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uaddl_4s_4h_4h, "uaddl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(uaddl2_4s_8h_8h, "uaddl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uaddl_8h_8b_8b, "uaddl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(uaddl2_8h_16b_16b, -+ "uaddl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(ssubl_2d_2s_2s, "ssubl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(ssubl2_2d_4s_4s, "ssubl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(ssubl_4s_4h_4h, "ssubl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(ssubl2_4s_8h_8h, "ssubl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(ssubl_8h_8b_8b, "ssubl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(ssubl2_8h_16b_16b, -+ "ssubl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(usubl_2d_2s_2s, "usubl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(usubl2_2d_4s_4s, "usubl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(usubl_4s_4h_4h, "usubl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(usubl2_4s_8h_8h, "usubl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(usubl_8h_8b_8b, "usubl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(usubl2_8h_16b_16b, -+ "usubl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_TWOVEC_TEST(saddlp_4h_8b, "saddlp v3.4h, v19.8b", 3, 19) -+GEN_TWOVEC_TEST(saddlp_8h_16b, "saddlp v3.8h, v19.16b", 3, 19) -+GEN_TWOVEC_TEST(saddlp_2s_4h, "saddlp v3.2s, v19.4h", 3, 19) -+GEN_TWOVEC_TEST(saddlp_4s_8h, "saddlp v3.4s, v19.8h", 3, 19) -+GEN_TWOVEC_TEST(saddlp_1d_2s, "saddlp v3.1d, v19.2s", 3, 19) -+GEN_TWOVEC_TEST(saddlp_2d_4s, "saddlp v3.2d, v19.4s", 3, 19) -+ -+GEN_TWOVEC_TEST(uaddlp_4h_8b, "uaddlp v3.4h, v19.8b", 3, 19) -+GEN_TWOVEC_TEST(uaddlp_8h_16b, "uaddlp v3.8h, v19.16b", 3, 19) -+GEN_TWOVEC_TEST(uaddlp_2s_4h, "uaddlp v3.2s, v19.4h", 3, 19) -+GEN_TWOVEC_TEST(uaddlp_4s_8h, "uaddlp v3.4s, v19.8h", 3, 19) -+GEN_TWOVEC_TEST(uaddlp_1d_2s, "uaddlp v3.1d, v19.2s", 3, 19) -+GEN_TWOVEC_TEST(uaddlp_2d_4s, "uaddlp v3.2d, v19.4s", 3, 19) -+ -+GEN_TWOVEC_TEST(saddlv_h_16b, "saddlv h3, v19.16b", 3, 19) -+GEN_TWOVEC_TEST(saddlv_h_8b, "saddlv h3, v19.8b", 3, 19) -+GEN_TWOVEC_TEST(saddlv_s_8h, "saddlv s3, v19.8h", 3, 19) -+GEN_TWOVEC_TEST(saddlv_s_4h, "saddlv s3, v19.4h", 3, 19) -+GEN_TWOVEC_TEST(saddlv_d_4s, "saddlv d3, v19.4s", 3, 19) -+ -+GEN_TWOVEC_TEST(uaddlv_h_16b, "uaddlv h3, v19.16b", 3, 19) -+GEN_TWOVEC_TEST(uaddlv_h_8b, "uaddlv h3, v19.8b", 3, 19) -+GEN_TWOVEC_TEST(uaddlv_s_8h, "uaddlv s3, v19.8h", 3, 19) -+GEN_TWOVEC_TEST(uaddlv_s_4h, "uaddlv s3, v19.4h", 3, 19) -+GEN_TWOVEC_TEST(uaddlv_d_4s, "uaddlv d3, v19.4s", 3, 19) -+ -+GEN_THREEVEC_TEST(saddw2_8h_8h_16b, "saddw2 v5.8h, v13.8h, v31.16b", 5, 13, 31) -+GEN_THREEVEC_TEST(saddw_8h_8h_8b, "saddw v5.8h, v13.8h, v31.8b", 5, 13, 31) -+GEN_THREEVEC_TEST(saddw2_4s_4s_8h, "saddw2 v5.4s, v13.4s, v31.8h", 5, 13, 31) -+GEN_THREEVEC_TEST(saddw_4s_4s_4h, "saddw v5.4s, v13.4s, v31.4h", 5, 13, 31) -+GEN_THREEVEC_TEST(saddw2_2d_2d_4s, "saddw2 v5.2d, v13.2d, v31.4s", 5, 13, 31) -+GEN_THREEVEC_TEST(saddw_2d_2d_2s, "saddw v5.2d, v13.2d, v31.2s", 5, 13, 31) -+ -+GEN_THREEVEC_TEST(uaddw2_8h_8h_16b, "uaddw2 v5.8h, v13.8h, v31.16b", 5, 13, 31) -+GEN_THREEVEC_TEST(uaddw_8h_8h_8b, "uaddw v5.8h, v13.8h, v31.8b", 5, 13, 31) -+GEN_THREEVEC_TEST(uaddw2_4s_4s_8h, "uaddw2 v5.4s, v13.4s, v31.8h", 5, 13, 31) -+GEN_THREEVEC_TEST(uaddw_4s_4s_4h, "uaddw v5.4s, v13.4s, v31.4h", 5, 13, 31) -+GEN_THREEVEC_TEST(uaddw2_2d_2d_4s, "uaddw2 v5.2d, v13.2d, v31.4s", 5, 13, 31) -+GEN_THREEVEC_TEST(uaddw_2d_2d_2s, "uaddw v5.2d, v13.2d, v31.2s", 5, 13, 31) -+ -+GEN_THREEVEC_TEST(ssubw2_8h_8h_16b, "ssubw2 v5.8h, v13.8h, v31.16b", 5, 13, 31) -+GEN_THREEVEC_TEST(ssubw_8h_8h_8b, "ssubw v5.8h, v13.8h, v31.8b", 5, 13, 31) -+GEN_THREEVEC_TEST(ssubw2_4s_4s_8h, "ssubw2 v5.4s, v13.4s, v31.8h", 5, 13, 31) -+GEN_THREEVEC_TEST(ssubw_4s_4s_4h, "ssubw v5.4s, v13.4s, v31.4h", 5, 13, 31) -+GEN_THREEVEC_TEST(ssubw2_2d_2d_4s, "ssubw2 v5.2d, v13.2d, v31.4s", 5, 13, 31) -+GEN_THREEVEC_TEST(ssubw_2d_2d_2s, "ssubw v5.2d, v13.2d, v31.2s", 5, 13, 31) -+ -+GEN_THREEVEC_TEST(usubw2_8h_8h_16b, "usubw2 v5.8h, v13.8h, v31.16b", 5, 13, 31) -+GEN_THREEVEC_TEST(usubw_8h_8h_8b, "usubw v5.8h, v13.8h, v31.8b", 5, 13, 31) -+GEN_THREEVEC_TEST(usubw2_4s_4s_8h, "usubw2 v5.4s, v13.4s, v31.8h", 5, 13, 31) -+GEN_THREEVEC_TEST(usubw_4s_4s_4h, "usubw v5.4s, v13.4s, v31.4h", 5, 13, 31) -+GEN_THREEVEC_TEST(usubw2_2d_2d_4s, "usubw2 v5.2d, v13.2d, v31.4s", 5, 13, 31) -+GEN_THREEVEC_TEST(usubw_2d_2d_2s, "usubw v5.2d, v13.2d, v31.2s", 5, 13, 31) -+ -+GEN_THREEVEC_TEST(shadd_4s_4s_4s, "shadd v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(shadd_2s_2s_2s, "shadd v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(shadd_8h_8h_8h, "shadd v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(shadd_4h_4h_4h, "shadd v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(shadd_16b_16b_16b,"shadd v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(shadd_8b_8b_8b, "shadd v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uhadd_4s_4s_4s, "uhadd v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(uhadd_2s_2s_2s, "uhadd v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(uhadd_8h_8h_8h, "uhadd v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(uhadd_4h_4h_4h, "uhadd v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(uhadd_16b_16b_16b,"uhadd v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(uhadd_8b_8b_8b, "uhadd v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(shsub_4s_4s_4s, "shsub v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(shsub_2s_2s_2s, "shsub v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(shsub_8h_8h_8h, "shsub v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(shsub_4h_4h_4h, "shsub v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(shsub_16b_16b_16b,"shsub v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(shsub_8b_8b_8b, "shsub v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(uhsub_4s_4s_4s, "uhsub v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(uhsub_2s_2s_2s, "uhsub v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(uhsub_8h_8h_8h, "uhsub v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(uhsub_4h_4h_4h, "uhsub v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(uhsub_16b_16b_16b,"uhsub v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(uhsub_8b_8b_8b, "uhsub v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_TWOVEC_TEST(shll_8h_8b_8, "shll v3.8h, v24.8b, #8", 3, 24) -+GEN_TWOVEC_TEST(shll2_8h_16b_8, "shll2 v3.8h, v24.16b, #8", 3, 24) -+GEN_TWOVEC_TEST(shll_4s_4h_16, "shll v3.4s, v24.4h, #16", 3, 24) -+GEN_TWOVEC_TEST(shll2_4s_8h_16, "shll2 v3.4s, v24.8h, #16", 3, 24) -+GEN_TWOVEC_TEST(shll_2d_2s_32, "shll v3.2d, v24.2s, #32", 3, 24) -+GEN_TWOVEC_TEST(shll2_2d_4s_32, "shll2 v3.2d, v24.4s, #32", 3, 24) -+ -+GEN_TWOVEC_TEST(shrn_2s_2d_1, "shrn v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(shrn_2s_2d_32, "shrn v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(shrn2_4s_2d_1, "shrn2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(shrn2_4s_2d_32, "shrn2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(shrn_4h_4s_1, "shrn v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(shrn_4h_4s_16, "shrn v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(shrn2_8h_4s_1, "shrn2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(shrn2_8h_4s_16, "shrn2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(shrn_8b_8h_1, "shrn v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(shrn_8b_8h_8, "shrn v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(shrn2_16b_8h_1, "shrn2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(shrn2_16b_8h_8, "shrn2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(rshrn_2s_2d_1, "rshrn v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(rshrn_2s_2d_32, "rshrn v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(rshrn2_4s_2d_1, "rshrn2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(rshrn2_4s_2d_32, "rshrn2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(rshrn_4h_4s_1, "rshrn v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(rshrn_4h_4s_16, "rshrn v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(rshrn2_8h_4s_1, "rshrn2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(rshrn2_8h_4s_16, "rshrn2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(rshrn_8b_8h_1, "rshrn v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(rshrn_8b_8h_8, "rshrn v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(rshrn2_16b_8h_1, "rshrn2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(rshrn2_16b_8h_8, "rshrn2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(sli_d_d_0, "sli d5, d28, #0", 5, 28) -+GEN_TWOVEC_TEST(sli_d_d_32, "sli d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(sli_d_d_63, "sli d5, d28, #63", 5, 28) -+GEN_TWOVEC_TEST(sri_d_d_1, "sri d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(sri_d_d_33, "sri d5, d28, #33", 5, 28) -+GEN_TWOVEC_TEST(sri_d_d_64, "sri d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(sli_2d_2d_0, "sli v6.2d, v27.2d, #0", 6, 27) -+GEN_TWOVEC_TEST(sli_2d_2d_32, "sli v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(sli_2d_2d_63, "sli v6.2d, v27.2d, #63", 6, 27) -+GEN_TWOVEC_TEST(sli_4s_4s_0, "sli v6.4s, v27.4s, #0", 6, 27) -+GEN_TWOVEC_TEST(sli_4s_4s_16, "sli v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(sli_4s_4s_31, "sli v6.4s, v27.4s, #31", 6, 27) -+GEN_TWOVEC_TEST(sli_2s_2s_0, "sli v6.2s, v27.2s, #0", 6, 27) -+GEN_TWOVEC_TEST(sli_2s_2s_16, "sli v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(sli_2s_2s_31, "sli v6.2s, v27.2s, #31", 6, 27) -+GEN_TWOVEC_TEST(sli_8h_8h_0, "sli v6.8h, v27.8h, #0", 6, 27) -+GEN_TWOVEC_TEST(sli_8h_8h_8, "sli v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(sli_8h_8h_15, "sli v6.8h, v27.8h, #15", 6, 27) -+GEN_TWOVEC_TEST(sli_4h_4h_0, "sli v6.4h, v27.4h, #0", 6, 27) -+GEN_TWOVEC_TEST(sli_4h_4h_8, "sli v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(sli_4h_4h_15, "sli v6.4h, v27.4h, #15", 6, 27) -+GEN_TWOVEC_TEST(sli_16b_16b_0, "sli v6.16b, v27.16b, #0", 6, 27) -+GEN_TWOVEC_TEST(sli_16b_16b_3, "sli v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(sli_16b_16b_7, "sli v6.16b, v27.16b, #7", 6, 27) -+GEN_TWOVEC_TEST(sli_8b_8b_0, "sli v6.8b, v27.8b, #0", 6, 27) -+GEN_TWOVEC_TEST(sli_8b_8b_3, "sli v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(sli_8b_8b_7, "sli v6.8b, v27.8b, #7", 6, 27) -+ -+GEN_TWOVEC_TEST(sri_2d_2d_1, "sri v6.2d, v27.2d, #1", 6, 27) -+GEN_TWOVEC_TEST(sri_2d_2d_33, "sri v6.2d, v27.2d, #33", 6, 27) -+GEN_TWOVEC_TEST(sri_2d_2d_64, "sri v6.2d, v27.2d, #64", 6, 27) -+GEN_TWOVEC_TEST(sri_4s_4s_1, "sri v6.4s, v27.4s, #1", 6, 27) -+GEN_TWOVEC_TEST(sri_4s_4s_17, "sri v6.4s, v27.4s, #17", 6, 27) -+GEN_TWOVEC_TEST(sri_4s_4s_32, "sri v6.4s, v27.4s, #32", 6, 27) -+GEN_TWOVEC_TEST(sri_2s_2s_1, "sri v6.2s, v27.2s, #1", 6, 27) -+GEN_TWOVEC_TEST(sri_2s_2s_17, "sri v6.2s, v27.2s, #17", 6, 27) -+GEN_TWOVEC_TEST(sri_2s_2s_32, "sri v6.2s, v27.2s, #32", 6, 27) -+GEN_TWOVEC_TEST(sri_8h_8h_1, "sri v6.8h, v27.8h, #1", 6, 27) -+GEN_TWOVEC_TEST(sri_8h_8h_8, "sri v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(sri_8h_8h_16, "sri v6.8h, v27.8h, #16", 6, 27) -+GEN_TWOVEC_TEST(sri_4h_4h_1, "sri v6.4h, v27.4h, #1", 6, 27) -+GEN_TWOVEC_TEST(sri_4h_4h_8, "sri v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(sri_4h_4h_16, "sri v6.4h, v27.4h, #16", 6, 27) -+GEN_TWOVEC_TEST(sri_16b_16b_1, "sri v6.16b, v27.16b, #1", 6, 27) -+GEN_TWOVEC_TEST(sri_16b_16b_4, "sri v6.16b, v27.16b, #4", 6, 27) -+GEN_TWOVEC_TEST(sri_16b_16b_8, "sri v6.16b, v27.16b, #8", 6, 27) -+GEN_TWOVEC_TEST(sri_8b_8b_1, "sri v6.8b, v27.8b, #1", 6, 27) -+GEN_TWOVEC_TEST(sri_8b_8b_4, "sri v6.8b, v27.8b, #4", 6, 27) -+GEN_TWOVEC_TEST(sri_8b_8b_8, "sri v6.8b, v27.8b, #8", 6, 27) -+ -+GEN_BINARY_TEST(smaxp, 4s, 4s, 4s) -+GEN_BINARY_TEST(smaxp, 2s, 2s, 2s) -+GEN_BINARY_TEST(smaxp, 8h, 8h, 8h) -+GEN_BINARY_TEST(smaxp, 4h, 4h, 4h) -+GEN_BINARY_TEST(smaxp, 16b, 16b, 16b) -+GEN_BINARY_TEST(smaxp, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(umaxp, 4s, 4s, 4s) -+GEN_BINARY_TEST(umaxp, 2s, 2s, 2s) -+GEN_BINARY_TEST(umaxp, 8h, 8h, 8h) -+GEN_BINARY_TEST(umaxp, 4h, 4h, 4h) -+GEN_BINARY_TEST(umaxp, 16b, 16b, 16b) -+GEN_BINARY_TEST(umaxp, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(sminp, 4s, 4s, 4s) -+GEN_BINARY_TEST(sminp, 2s, 2s, 2s) -+GEN_BINARY_TEST(sminp, 8h, 8h, 8h) -+GEN_BINARY_TEST(sminp, 4h, 4h, 4h) -+GEN_BINARY_TEST(sminp, 16b, 16b, 16b) -+GEN_BINARY_TEST(sminp, 8b, 8b, 8b) -+ -+GEN_BINARY_TEST(uminp, 4s, 4s, 4s) -+GEN_BINARY_TEST(uminp, 2s, 2s, 2s) -+GEN_BINARY_TEST(uminp, 8h, 8h, 8h) -+GEN_BINARY_TEST(uminp, 4h, 4h, 4h) -+GEN_BINARY_TEST(uminp, 16b, 16b, 16b) -+GEN_BINARY_TEST(uminp, 8b, 8b, 8b) -+ -+GEN_THREEVEC_TEST(smlal_2d_2s_s0, "smlal v29.2d, v20.2s, v3.s[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlal_2d_2s_s3, "smlal v29.2d, v20.2s, v3.s[3]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlal2_2d_4s_s1, "smlal2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlal2_2d_4s_s2, "smlal2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlal_4s_4h_h0, "smlal v29.4s, v20.4h, v3.h[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlal_4s_4h_h7, "smlal v29.4s, v20.4h, v3.h[7]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlal2_4s_8h_h1, "smlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlal2_4s_8h_h4, "smlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+ -+GEN_THREEVEC_TEST(umlal_2d_2s_s0, "umlal v29.2d, v20.2s, v3.s[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlal_2d_2s_s3, "umlal v29.2d, v20.2s, v3.s[3]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlal2_2d_4s_s1, "umlal2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlal2_2d_4s_s2, "umlal2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlal_4s_4h_h0, "umlal v29.4s, v20.4h, v3.h[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlal_4s_4h_h7, "umlal v29.4s, v20.4h, v3.h[7]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlal2_4s_8h_h1, "umlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlal2_4s_8h_h4, "umlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+ -+GEN_THREEVEC_TEST(smlsl_2d_2s_s0, "smlsl v29.2d, v20.2s, v3.s[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlsl_2d_2s_s3, "smlsl v29.2d, v20.2s, v3.s[3]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlsl2_2d_4s_s1, "smlsl2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlsl2_2d_4s_s2, "smlsl2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlsl_4s_4h_h0, "smlsl v29.4s, v20.4h, v3.h[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlsl_4s_4h_h7, "smlsl v29.4s, v20.4h, v3.h[7]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlsl2_4s_8h_h1, "smlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(smlsl2_4s_8h_h4, "smlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+ -+GEN_THREEVEC_TEST(umlsl_2d_2s_s0, "umlsl v29.2d, v20.2s, v3.s[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlsl_2d_2s_s3, "umlsl v29.2d, v20.2s, v3.s[3]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlsl2_2d_4s_s1, "umlsl2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlsl2_2d_4s_s2, "umlsl2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlsl_4s_4h_h0, "umlsl v29.4s, v20.4h, v3.h[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlsl_4s_4h_h7, "umlsl v29.4s, v20.4h, v3.h[7]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlsl2_4s_8h_h1, "umlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(umlsl2_4s_8h_h4, "umlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+ -+GEN_THREEVEC_TEST(smull_2d_2s_s0, "smull v29.2d, v20.2s, v3.s[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(smull_2d_2s_s3, "smull v29.2d, v20.2s, v3.s[3]", 29, 20, 3) -+GEN_THREEVEC_TEST(smull2_2d_4s_s1, "smull2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(smull2_2d_4s_s2, "smull2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3) -+GEN_THREEVEC_TEST(smull_4s_4h_h0, "smull v29.4s, v20.4h, v3.h[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(smull_4s_4h_h7, "smull v29.4s, v20.4h, v3.h[7]", 29, 20, 3) -+GEN_THREEVEC_TEST(smull2_4s_8h_h1, "smull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(smull2_4s_8h_h4, "smull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+ -+GEN_THREEVEC_TEST(umull_2d_2s_s0, "umull v29.2d, v20.2s, v3.s[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(umull_2d_2s_s3, "umull v29.2d, v20.2s, v3.s[3]", 29, 20, 3) -+GEN_THREEVEC_TEST(umull2_2d_4s_s1, "umull2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(umull2_2d_4s_s2, "umull2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3) -+GEN_THREEVEC_TEST(umull_4s_4h_h0, "umull v29.4s, v20.4h, v3.h[0]", 29, 20, 3) -+GEN_THREEVEC_TEST(umull_4s_4h_h7, "umull v29.4s, v20.4h, v3.h[7]", 29, 20, 3) -+GEN_THREEVEC_TEST(umull2_4s_8h_h1, "umull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+GEN_THREEVEC_TEST(umull2_4s_8h_h4, "umull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3) -+ -+GEN_THREEVEC_TEST(smlal_2d_2s_2s, "smlal v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(smlal2_2d_4s_4s, "smlal2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smlal_4s_4h_4h, "smlal v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(smlal2_4s_8h_8h, "smlal2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smlal_8h_8b_8b, "smlal v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(smlal2_8h_16b_16b, -+ "smlal2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umlal_2d_2s_2s, "umlal v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(umlal2_2d_4s_4s, "umlal2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umlal_4s_4h_4h, "umlal v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(umlal2_4s_8h_8h, "umlal2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umlal_8h_8b_8b, "umlal v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(umlal2_8h_16b_16b, -+ "umlal2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smlsl_2d_2s_2s, "smlsl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(smlsl2_2d_4s_4s, "smlsl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smlsl_4s_4h_4h, "smlsl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(smlsl2_4s_8h_8h, "smlsl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smlsl_8h_8b_8b, "smlsl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(smlsl2_8h_16b_16b, -+ "smlsl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umlsl_2d_2s_2s, "umlsl v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(umlsl2_2d_4s_4s, "umlsl2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umlsl_4s_4h_4h, "umlsl v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(umlsl2_4s_8h_8h, "umlsl2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umlsl_8h_8b_8b, "umlsl v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(umlsl2_8h_16b_16b, -+ "umlsl2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smull_2d_2s_2s, "smull v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(smull2_2d_4s_4s, "smull2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smull_4s_4h_4h, "smull v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(smull2_4s_8h_8h, "smull2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(smull_8h_8b_8b, "smull v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(smull2_8h_16b_16b, -+ "smull2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umull_2d_2s_2s, "umull v2.2d, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(umull2_2d_4s_4s, "umull2 v2.2d, v11.4s, v29.4s", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umull_4s_4h_4h, "umull v2.4s, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(umull2_4s_8h_8h, "umull2 v2.4s, v11.8h, v29.8h", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(umull_8h_8b_8b, "umull v2.8h, v11.8b, v29.8b", 2, 11, 29) -+GEN_THREEVEC_TEST(umull2_8h_16b_16b, -+ "umull2 v2.8h, v11.16b, v29.16b", 2, 11, 29) -+ -+GEN_TWOVEC_TEST(sqabs_d_d, "sqabs d7, d30", 7, 30) -+GEN_TWOVEC_TEST(sqabs_s_s, "sqabs s7, s30", 7, 30) -+GEN_TWOVEC_TEST(sqabs_h_h, "sqabs h7, h30", 7, 30) -+GEN_TWOVEC_TEST(sqabs_b_b, "sqabs b7, b30", 7, 30) -+ -+GEN_TWOVEC_TEST(sqneg_d_d, "sqneg d7, d30", 7, 30) -+GEN_TWOVEC_TEST(sqneg_s_s, "sqneg s7, s30", 7, 30) -+GEN_TWOVEC_TEST(sqneg_h_h, "sqneg h7, h30", 7, 30) -+GEN_TWOVEC_TEST(sqneg_b_b, "sqneg b7, b30", 7, 30) -+ -+GEN_UNARY_TEST(sqabs, 2d, 2d) -+GEN_UNARY_TEST(sqabs, 4s, 4s) -+GEN_UNARY_TEST(sqabs, 2s, 2s) -+GEN_UNARY_TEST(sqabs, 8h, 8h) -+GEN_UNARY_TEST(sqabs, 4h, 4h) -+GEN_UNARY_TEST(sqabs, 16b, 16b) -+GEN_UNARY_TEST(sqabs, 8b, 8b) -+ -+GEN_UNARY_TEST(sqneg, 2d, 2d) -+GEN_UNARY_TEST(sqneg, 4s, 4s) -+GEN_UNARY_TEST(sqneg, 2s, 2s) -+GEN_UNARY_TEST(sqneg, 8h, 8h) -+GEN_UNARY_TEST(sqneg, 4h, 4h) -+GEN_UNARY_TEST(sqneg, 16b, 16b) -+GEN_UNARY_TEST(sqneg, 8b, 8b) -+ -+GEN_THREEVEC_TEST(sqadd_d_d_d, "sqadd d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_s_s_s, "sqadd s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_h_h_h, "sqadd h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_b_b_b, "sqadd b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_2d_2d_2d, "sqadd v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_4s_4s_4s, "sqadd v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_2s_2s_2s, "sqadd v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_8h_8h_8h, "sqadd v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_4h_4h_4h, "sqadd v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_16b_16b_16b, "sqadd v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(sqadd_8b_8b_8b, "sqadd v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(uqadd_d_d_d, "uqadd d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_s_s_s, "uqadd s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_h_h_h, "uqadd h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_b_b_b, "uqadd b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_2d_2d_2d, "uqadd v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_4s_4s_4s, "uqadd v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_2s_2s_2s, "uqadd v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_8h_8h_8h, "uqadd v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_4h_4h_4h, "uqadd v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_16b_16b_16b, "uqadd v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(uqadd_8b_8b_8b, "uqadd v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(sqsub_d_d_d, "sqsub d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_s_s_s, "sqsub s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_h_h_h, "sqsub h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_b_b_b, "sqsub b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_2d_2d_2d, "sqsub v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_4s_4s_4s, "sqsub v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_2s_2s_2s, "sqsub v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_8h_8h_8h, "sqsub v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_4h_4h_4h, "sqsub v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_16b_16b_16b, "sqsub v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(sqsub_8b_8b_8b, "sqsub v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(uqsub_d_d_d, "uqsub d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_s_s_s, "uqsub s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_h_h_h, "uqsub h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_b_b_b, "uqsub b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_2d_2d_2d, "uqsub v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_4s_4s_4s, "uqsub v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_2s_2s_2s, "uqsub v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_8h_8h_8h, "uqsub v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_4h_4h_4h, "uqsub v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_16b_16b_16b, "uqsub v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(uqsub_8b_8b_8b, "uqsub v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(sqdmlal_d_s_s0, "sqdmlal d31, s30, v29.s[0]", 31,30,29) -+GEN_THREEVEC_TEST(sqdmlal_d_s_s3, "sqdmlal d31, s30, v29.s[3]", 31,30,29) -+GEN_THREEVEC_TEST(sqdmlal_s_h_h1, "sqdmlal s31, h30, v13.h[1]", 31,30,13) -+GEN_THREEVEC_TEST(sqdmlal_s_h_h5, "sqdmlal s31, h30, v13.h[5]", 31,30,13) -+ -+GEN_THREEVEC_TEST(sqdmlsl_d_s_s0, "sqdmlsl d31, s30, v29.s[0]", 31,30,29) -+GEN_THREEVEC_TEST(sqdmlsl_d_s_s3, "sqdmlsl d31, s30, v29.s[3]", 31,30,29) -+GEN_THREEVEC_TEST(sqdmlsl_s_h_h1, "sqdmlsl s31, h30, v13.h[1]", 31,30,13) -+GEN_THREEVEC_TEST(sqdmlsl_s_h_h5, "sqdmlsl s31, h30, v13.h[5]", 31,30,13) -+ -+GEN_THREEVEC_TEST(sqdmull_d_s_s0, "sqdmull d31, s30, v29.s[0]", 31,30,29) -+GEN_THREEVEC_TEST(sqdmull_d_s_s3, "sqdmull d31, s30, v29.s[3]", 31,30,29) -+GEN_THREEVEC_TEST(sqdmull_s_h_h1, "sqdmull s31, h30, v13.h[1]", 31,30,13) -+GEN_THREEVEC_TEST(sqdmull_s_h_h5, "sqdmull s31, h30, v13.h[5]", 31,30,13) -+ -+GEN_THREEVEC_TEST(sqdmlal_2d_2s_s0, "sqdmlal v29.2d, v20.2s, v3.s[0]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlal_2d_2s_s3, "sqdmlal v29.2d, v20.2s, v3.s[3]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlal2_2d_4s_s1,"sqdmlal2 v29.2d, v20.4s, v3.s[1]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlal2_2d_4s_s2,"sqdmlal2 v29.2d, v20.4s, v3.s[2]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlal_4s_4h_h0, "sqdmlal v29.4s, v20.4h, v3.h[0]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlal_4s_4h_h7, "sqdmlal v29.4s, v20.4h, v3.h[7]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlal2_4s_8h_h1,"sqdmlal2 v29.4s, v20.8h, v3.h[1]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlal2_4s_8h_h4,"sqdmlal2 v29.4s, v20.8h, v3.h[1]",29,20,3) -+ -+GEN_THREEVEC_TEST(sqdmlsl_2d_2s_s0, "sqdmlsl v29.2d, v20.2s, v3.s[0]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlsl_2d_2s_s3, "sqdmlsl v29.2d, v20.2s, v3.s[3]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlsl2_2d_4s_s1,"sqdmlsl2 v29.2d, v20.4s, v3.s[1]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlsl2_2d_4s_s2,"sqdmlsl2 v29.2d, v20.4s, v3.s[2]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlsl_4s_4h_h0, "sqdmlsl v29.4s, v20.4h, v3.h[0]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlsl_4s_4h_h7, "sqdmlsl v29.4s, v20.4h, v3.h[7]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlsl2_4s_8h_h1,"sqdmlsl2 v29.4s, v20.8h, v3.h[1]",29,20,3) -+GEN_THREEVEC_TEST(sqdmlsl2_4s_8h_h4,"sqdmlsl2 v29.4s, v20.8h, v3.h[1]",29,20,3) -+ -+GEN_THREEVEC_TEST(sqdmull_2d_2s_s0, "sqdmull v29.2d, v20.2s, v3.s[0]",29,20,3) -+GEN_THREEVEC_TEST(sqdmull_2d_2s_s3, "sqdmull v29.2d, v20.2s, v3.s[3]",29,20,3) -+GEN_THREEVEC_TEST(sqdmull2_2d_4s_s1,"sqdmull2 v29.2d, v20.4s, v3.s[1]",29,20,3) -+GEN_THREEVEC_TEST(sqdmull2_2d_4s_s2,"sqdmull2 v29.2d, v20.4s, v3.s[2]",29,20,3) -+GEN_THREEVEC_TEST(sqdmull_4s_4h_h0, "sqdmull v29.4s, v20.4h, v3.h[0]",29,20,3) -+GEN_THREEVEC_TEST(sqdmull_4s_4h_h7, "sqdmull v29.4s, v20.4h, v3.h[7]",29,20,3) -+GEN_THREEVEC_TEST(sqdmull2_4s_8h_h1,"sqdmull2 v29.4s, v20.8h, v3.h[1]",29,20,3) -+GEN_THREEVEC_TEST(sqdmull2_4s_8h_h4,"sqdmull2 v29.4s, v20.8h, v3.h[1]",29,20,3) -+ -+GEN_THREEVEC_TEST(sqdmlal_d_s_s, "sqdmlal d0, s8, s16", 0, 8, 16) -+GEN_THREEVEC_TEST(sqdmlal_s_h_h, "sqdmlal s0, h8, h16", 0, 8, 16) -+GEN_THREEVEC_TEST(sqdmlsl_d_s_s, "sqdmlsl d0, s8, s16", 0, 8, 16) -+GEN_THREEVEC_TEST(sqdmlsl_s_h_h, "sqdmlsl s0, h8, h16", 0, 8, 16) -+GEN_THREEVEC_TEST(sqdmull_d_s_s, "sqdmull d0, s8, s16", 0, 8, 16) -+GEN_THREEVEC_TEST(sqdmull_s_h_h, "sqdmull s0, h8, h16", 0, 8, 16) -+ -+GEN_THREEVEC_TEST(sqdmlal_2d_2s_2s, "sqdmlal v2.2d, v11.2s, v29.2s", 2,11,29) -+GEN_THREEVEC_TEST(sqdmlal2_2d_4s_4s, "sqdmlal2 v2.2d, v11.4s, v29.4s", 2,11,29) -+GEN_THREEVEC_TEST(sqdmlal_4s_4h_4h, "sqdmlal v2.4s, v11.4h, v29.4h", 2,11,29) -+GEN_THREEVEC_TEST(sqdmlal2_4s_8h_8h, "sqdmlal2 v2.4s, v11.8h, v29.8h", 2,11,29) -+ -+GEN_THREEVEC_TEST(sqdmlsl_2d_2s_2s, "sqdmlsl v2.2d, v11.2s, v29.2s", 2,11,29) -+GEN_THREEVEC_TEST(sqdmlsl2_2d_4s_4s, "sqdmlsl2 v2.2d, v11.4s, v29.4s", 2,11,29) -+GEN_THREEVEC_TEST(sqdmlsl_4s_4h_4h, "sqdmlsl v2.4s, v11.4h, v29.4h", 2,11,29) -+GEN_THREEVEC_TEST(sqdmlsl2_4s_8h_8h, "sqdmlsl2 v2.4s, v11.8h, v29.8h", 2,11,29) -+ -+GEN_THREEVEC_TEST(sqdmull_2d_2s_2s, "sqdmull v2.2d, v11.2s, v29.2s", 2,11,29) -+GEN_THREEVEC_TEST(sqdmull2_2d_4s_4s, "sqdmull2 v2.2d, v11.4s, v29.4s", 2,11,29) -+GEN_THREEVEC_TEST(sqdmull_4s_4h_4h, "sqdmull v2.4s, v11.4h, v29.4h", 2,11,29) -+GEN_THREEVEC_TEST(sqdmull2_4s_8h_8h, "sqdmull2 v2.4s, v11.8h, v29.8h", 2,11,29) -+ -+GEN_THREEVEC_TEST(sqdmulh_s_s_s1, "sqdmulh s0, s1, v2.s[1]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_s_s_s3, "sqdmulh s0, s1, v2.s[3]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_h_h_h2, "sqdmulh h0, h1, v2.h[2]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_h_h_h7, "sqdmulh h0, h1, v2.h[7]", 0,1,2) -+ -+GEN_THREEVEC_TEST(sqrdmulh_s_s_s1, "sqrdmulh s0, s1, v2.s[1]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_s_s_s3, "sqrdmulh s0, s1, v2.s[3]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_h_h_h2, "sqrdmulh h0, h1, v2.h[2]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_h_h_h7, "sqrdmulh h0, h1, v2.h[7]", 0,1,2) -+ -+GEN_THREEVEC_TEST(sqdmulh_4s_4s_s1, "sqdmulh v0.4s, v1.4s, v2.s[1]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_4s_4s_s3, "sqdmulh v0.4s, v1.4s, v2.s[3]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_2s_2s_s1, "sqdmulh v0.2s, v1.2s, v2.s[1]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_2s_2s_s3, "sqdmulh v0.2s, v1.2s, v2.s[3]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_8h_8h_h2, "sqdmulh v0.8h, v1.8h, v2.h[2]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_8h_8h_h7, "sqdmulh v0.8h, v1.8h, v2.h[7]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_4h_4h_h2, "sqdmulh v0.4h, v1.4h, v2.h[2]", 0,1,2) -+GEN_THREEVEC_TEST(sqdmulh_4h_4h_h7, "sqdmulh v0.4h, v1.4h, v2.h[7]", 0,1,2) -+ -+GEN_THREEVEC_TEST(sqrdmulh_4s_4s_s1, "sqrdmulh v0.4s, v1.4s, v2.s[1]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_4s_4s_s3, "sqrdmulh v0.4s, v1.4s, v2.s[3]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_2s_2s_s1, "sqrdmulh v0.2s, v1.2s, v2.s[1]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_2s_2s_s3, "sqrdmulh v0.2s, v1.2s, v2.s[3]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_8h_8h_h2, "sqrdmulh v0.8h, v1.8h, v2.h[2]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_8h_8h_h7, "sqrdmulh v0.8h, v1.8h, v2.h[7]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_4h_4h_h2, "sqrdmulh v0.4h, v1.4h, v2.h[2]", 0,1,2) -+GEN_THREEVEC_TEST(sqrdmulh_4h_4h_h7, "sqrdmulh v0.4h, v1.4h, v2.h[7]", 0,1,2) -+ -+GEN_THREEVEC_TEST(sqdmulh_s_s_s, "sqdmulh s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqdmulh_h_h_h, "sqdmulh h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrdmulh_s_s_s, "sqrdmulh s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrdmulh_h_h_h, "sqrdmulh h1, h2, h4", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(sqdmulh_4s_4s_4s, "sqdmulh v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqdmulh_2s_2s_2s, "sqdmulh v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqdmulh_8h_8h_8h, "sqdmulh v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqdmulh_4h_4h_4h, "sqdmulh v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrdmulh_4s_4s_4s, "sqrdmulh v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrdmulh_2s_2s_2s, "sqrdmulh v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrdmulh_8h_8h_8h, "sqrdmulh v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrdmulh_4h_4h_4h, "sqrdmulh v1.4h, v2.4h, v4.4h", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(sqshl_d_d_d, "sqshl d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_s_s_s, "sqshl s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_h_h_h, "sqshl h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_b_b_b, "sqshl b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_2d_2d_2d, "sqshl v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_4s_4s_4s, "sqshl v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_2s_2s_2s, "sqshl v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_8h_8h_8h, "sqshl v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_4h_4h_4h, "sqshl v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_16b_16b_16b, "sqshl v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(sqshl_8b_8b_8b, "sqshl v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(uqshl_d_d_d, "uqshl d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_s_s_s, "uqshl s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_h_h_h, "uqshl h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_b_b_b, "uqshl b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_2d_2d_2d, "uqshl v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_4s_4s_4s, "uqshl v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_2s_2s_2s, "uqshl v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_8h_8h_8h, "uqshl v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_4h_4h_4h, "uqshl v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_16b_16b_16b, "uqshl v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(uqshl_8b_8b_8b, "uqshl v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(sqrshl_d_d_d, "sqrshl d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_s_s_s, "sqrshl s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_h_h_h, "sqrshl h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_b_b_b, "sqrshl b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_2d_2d_2d, "sqrshl v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_4s_4s_4s, "sqrshl v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_2s_2s_2s, "sqrshl v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_8h_8h_8h, "sqrshl v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_4h_4h_4h, "sqrshl v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_16b_16b_16b, "sqrshl v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(sqrshl_8b_8b_8b, "sqrshl v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(uqrshl_d_d_d, "uqrshl d1, d2, d4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_s_s_s, "uqrshl s1, s2, s4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_h_h_h, "uqrshl h1, h2, h4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_b_b_b, "uqrshl b1, b2, b4", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_2d_2d_2d, "uqrshl v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_4s_4s_4s, "uqrshl v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_2s_2s_2s, "uqrshl v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_8h_8h_8h, "uqrshl v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_4h_4h_4h, "uqrshl v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_16b_16b_16b, "uqrshl v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(uqrshl_8b_8b_8b, "uqrshl v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_TWOVEC_TEST(sqrshrn_s_d_1, "sqrshrn s2, d5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_s_d_17, "sqrshrn s2, d5, #17", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_s_d_32, "sqrshrn s2, d5, #32", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_h_s_1, "sqrshrn h2, s5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_h_s_9, "sqrshrn h2, s5, #9", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_h_s_16, "sqrshrn h2, s5, #16", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_b_h_1, "sqrshrn b2, h5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_b_h_4, "sqrshrn b2, h5, #4", 2, 5) -+GEN_TWOVEC_TEST(sqrshrn_b_h_8, "sqrshrn b2, h5, #8", 2, 5) -+ -+GEN_TWOVEC_TEST(uqrshrn_s_d_1, "uqrshrn s2, d5, #1", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_s_d_17, "uqrshrn s2, d5, #17", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_s_d_32, "uqrshrn s2, d5, #32", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_h_s_1, "uqrshrn h2, s5, #1", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_h_s_9, "uqrshrn h2, s5, #9", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_h_s_16, "uqrshrn h2, s5, #16", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_b_h_1, "uqrshrn b2, h5, #1", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_b_h_4, "uqrshrn b2, h5, #4", 2, 5) -+GEN_TWOVEC_TEST(uqrshrn_b_h_8, "uqrshrn b2, h5, #8", 2, 5) -+ -+GEN_TWOVEC_TEST(sqshrn_s_d_1, "sqshrn s2, d5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_s_d_17, "sqshrn s2, d5, #17", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_s_d_32, "sqshrn s2, d5, #32", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_h_s_1, "sqshrn h2, s5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_h_s_9, "sqshrn h2, s5, #9", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_h_s_16, "sqshrn h2, s5, #16", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_b_h_1, "sqshrn b2, h5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_b_h_4, "sqshrn b2, h5, #4", 2, 5) -+GEN_TWOVEC_TEST(sqshrn_b_h_8, "sqshrn b2, h5, #8", 2, 5) -+ -+GEN_TWOVEC_TEST(uqshrn_s_d_1, "uqshrn s2, d5, #1", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_s_d_17, "uqshrn s2, d5, #17", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_s_d_32, "uqshrn s2, d5, #32", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_h_s_1, "uqshrn h2, s5, #1", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_h_s_9, "uqshrn h2, s5, #9", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_h_s_16, "uqshrn h2, s5, #16", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_b_h_1, "uqshrn b2, h5, #1", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_b_h_4, "uqshrn b2, h5, #4", 2, 5) -+GEN_TWOVEC_TEST(uqshrn_b_h_8, "uqshrn b2, h5, #8", 2, 5) -+ -+GEN_TWOVEC_TEST(sqrshrun_s_d_1, "sqrshrun s2, d5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_s_d_17, "sqrshrun s2, d5, #17", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_s_d_32, "sqrshrun s2, d5, #32", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_h_s_1, "sqrshrun h2, s5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_h_s_9, "sqrshrun h2, s5, #9", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_h_s_16, "sqrshrun h2, s5, #16", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_b_h_1, "sqrshrun b2, h5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_b_h_4, "sqrshrun b2, h5, #4", 2, 5) -+GEN_TWOVEC_TEST(sqrshrun_b_h_8, "sqrshrun b2, h5, #8", 2, 5) -+ -+GEN_TWOVEC_TEST(sqshrun_s_d_1, "sqshrun s2, d5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_s_d_17, "sqshrun s2, d5, #17", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_s_d_32, "sqshrun s2, d5, #32", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_h_s_1, "sqshrun h2, s5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_h_s_9, "sqshrun h2, s5, #9", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_h_s_16, "sqshrun h2, s5, #16", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_b_h_1, "sqshrun b2, h5, #1", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_b_h_4, "sqshrun b2, h5, #4", 2, 5) -+GEN_TWOVEC_TEST(sqshrun_b_h_8, "sqshrun b2, h5, #8", 2, 5) -+ -+GEN_TWOVEC_TEST(sqrshrn_2s_2d_1, "sqrshrn v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_2s_2d_17, "sqrshrn v4.2s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_2s_2d_32, "sqrshrn v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_4s_2d_1, "sqrshrn2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_4s_2d_17, "sqrshrn2 v4.4s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_4s_2d_32, "sqrshrn2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_4h_4s_1, "sqrshrn v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_4h_4s_9, "sqrshrn v4.4h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_4h_4s_16, "sqrshrn v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_8h_4s_1, "sqrshrn2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_8h_4s_9, "sqrshrn2 v4.8h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_8h_4s_16, "sqrshrn2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_8b_8h_1, "sqrshrn v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_8b_8h_4, "sqrshrn v4.8b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn_8b_8h_8, "sqrshrn v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_16b_8h_1, "sqrshrn2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_16b_8h_4, "sqrshrn2 v4.16b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqrshrn2_16b_8h_8, "sqrshrn2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(uqrshrn_2s_2d_1, "uqrshrn v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_2s_2d_17, "uqrshrn v4.2s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_2s_2d_32, "uqrshrn v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_4s_2d_1, "uqrshrn2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_4s_2d_17, "uqrshrn2 v4.4s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_4s_2d_32, "uqrshrn2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_4h_4s_1, "uqrshrn v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_4h_4s_9, "uqrshrn v4.4h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_4h_4s_16, "uqrshrn v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_8h_4s_1, "uqrshrn2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_8h_4s_9, "uqrshrn2 v4.8h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_8h_4s_16, "uqrshrn2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_8b_8h_1, "uqrshrn v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_8b_8h_4, "uqrshrn v4.8b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn_8b_8h_8, "uqrshrn v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_16b_8h_1, "uqrshrn2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_16b_8h_4, "uqrshrn2 v4.16b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(uqrshrn2_16b_8h_8, "uqrshrn2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(sqshrn_2s_2d_1, "sqshrn v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_2s_2d_17, "sqshrn v4.2s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_2s_2d_32, "sqshrn v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_4s_2d_1, "sqshrn2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_4s_2d_17, "sqshrn2 v4.4s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_4s_2d_32, "sqshrn2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_4h_4s_1, "sqshrn v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_4h_4s_9, "sqshrn v4.4h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_4h_4s_16, "sqshrn v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_8h_4s_1, "sqshrn2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_8h_4s_9, "sqshrn2 v4.8h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_8h_4s_16, "sqshrn2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_8b_8h_1, "sqshrn v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_8b_8h_4, "sqshrn v4.8b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqshrn_8b_8h_8, "sqshrn v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_16b_8h_1, "sqshrn2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_16b_8h_4, "sqshrn2 v4.16b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqshrn2_16b_8h_8, "sqshrn2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(uqshrn_2s_2d_1, "uqshrn v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_2s_2d_17, "uqshrn v4.2s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_2s_2d_32, "uqshrn v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_4s_2d_1, "uqshrn2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_4s_2d_17, "uqshrn2 v4.4s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_4s_2d_32, "uqshrn2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_4h_4s_1, "uqshrn v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_4h_4s_9, "uqshrn v4.4h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_4h_4s_16, "uqshrn v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_8h_4s_1, "uqshrn2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_8h_4s_9, "uqshrn2 v4.8h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_8h_4s_16, "uqshrn2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_8b_8h_1, "uqshrn v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_8b_8h_4, "uqshrn v4.8b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(uqshrn_8b_8h_8, "uqshrn v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_16b_8h_1, "uqshrn2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_16b_8h_4, "uqshrn2 v4.16b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(uqshrn2_16b_8h_8, "uqshrn2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(sqrshrun_2s_2d_1, "sqrshrun v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_2s_2d_17, "sqrshrun v4.2s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_2s_2d_32, "sqrshrun v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_4s_2d_1, "sqrshrun2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_4s_2d_17, "sqrshrun2 v4.4s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_4s_2d_32, "sqrshrun2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_4h_4s_1, "sqrshrun v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_4h_4s_9, "sqrshrun v4.4h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_4h_4s_16, "sqrshrun v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_8h_4s_1, "sqrshrun2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_8h_4s_9, "sqrshrun2 v4.8h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_8h_4s_16, "sqrshrun2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_8b_8h_1, "sqrshrun v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_8b_8h_4, "sqrshrun v4.8b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun_8b_8h_8, "sqrshrun v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_16b_8h_1, "sqrshrun2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_16b_8h_4, "sqrshrun2 v4.16b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqrshrun2_16b_8h_8, "sqrshrun2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(sqshrun_2s_2d_1, "sqshrun v4.2s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_2s_2d_17, "sqshrun v4.2s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_2s_2d_32, "sqshrun v4.2s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_4s_2d_1, "sqshrun2 v4.4s, v29.2d, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_4s_2d_17, "sqshrun2 v4.4s, v29.2d, #17", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_4s_2d_32, "sqshrun2 v4.4s, v29.2d, #32", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_4h_4s_1, "sqshrun v4.4h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_4h_4s_9, "sqshrun v4.4h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_4h_4s_16, "sqshrun v4.4h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_8h_4s_1, "sqshrun2 v4.8h, v29.4s, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_8h_4s_9, "sqshrun2 v4.8h, v29.4s, #9", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_8h_4s_16, "sqshrun2 v4.8h, v29.4s, #16", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_8b_8h_1, "sqshrun v4.8b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_8b_8h_4, "sqshrun v4.8b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqshrun_8b_8h_8, "sqshrun v4.8b, v29.8h, #8", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_16b_8h_1, "sqshrun2 v4.16b, v29.8h, #1", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_16b_8h_4, "sqshrun2 v4.16b, v29.8h, #4", 4, 29) -+GEN_TWOVEC_TEST(sqshrun2_16b_8h_8, "sqshrun2 v4.16b, v29.8h, #8", 4, 29) -+ -+GEN_TWOVEC_TEST(sqshl_d_d_0, "sqshl d5, d28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshl_d_d_32, "sqshl d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(sqshl_d_d_63, "sqshl d5, d28, #63", 5, 28) -+GEN_TWOVEC_TEST(sqshl_s_s_0, "sqshl s5, s28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshl_s_s_16, "sqshl s5, s28, #16", 5, 28) -+GEN_TWOVEC_TEST(sqshl_s_s_31, "sqshl s5, s28, #31", 5, 28) -+GEN_TWOVEC_TEST(sqshl_h_h_0, "sqshl h5, h28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshl_h_h_8, "sqshl h5, h28, #8", 5, 28) -+GEN_TWOVEC_TEST(sqshl_h_h_15, "sqshl h5, h28, #15", 5, 28) -+GEN_TWOVEC_TEST(sqshl_b_b_0, "sqshl b5, b28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshl_b_b_4, "sqshl b5, b28, #4", 5, 28) -+GEN_TWOVEC_TEST(sqshl_b_b_7, "sqshl b5, b28, #7", 5, 28) -+ -+GEN_TWOVEC_TEST(uqshl_d_d_0, "uqshl d5, d28, #0", 5, 28) -+GEN_TWOVEC_TEST(uqshl_d_d_32, "uqshl d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(uqshl_d_d_63, "uqshl d5, d28, #63", 5, 28) -+GEN_TWOVEC_TEST(uqshl_s_s_0, "uqshl s5, s28, #0", 5, 28) -+GEN_TWOVEC_TEST(uqshl_s_s_16, "uqshl s5, s28, #16", 5, 28) -+GEN_TWOVEC_TEST(uqshl_s_s_31, "uqshl s5, s28, #31", 5, 28) -+GEN_TWOVEC_TEST(uqshl_h_h_0, "uqshl h5, h28, #0", 5, 28) -+GEN_TWOVEC_TEST(uqshl_h_h_8, "uqshl h5, h28, #8", 5, 28) -+GEN_TWOVEC_TEST(uqshl_h_h_15, "uqshl h5, h28, #15", 5, 28) -+GEN_TWOVEC_TEST(uqshl_b_b_0, "uqshl b5, b28, #0", 5, 28) -+GEN_TWOVEC_TEST(uqshl_b_b_4, "uqshl b5, b28, #4", 5, 28) -+GEN_TWOVEC_TEST(uqshl_b_b_7, "uqshl b5, b28, #7", 5, 28) -+ -+GEN_TWOVEC_TEST(sqshlu_d_d_0, "sqshlu d5, d28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_d_d_32, "sqshlu d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_d_d_63, "sqshlu d5, d28, #63", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_s_s_0, "sqshlu s5, s28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_s_s_16, "sqshlu s5, s28, #16", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_s_s_31, "sqshlu s5, s28, #31", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_h_h_0, "sqshlu h5, h28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_h_h_8, "sqshlu h5, h28, #8", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_h_h_15, "sqshlu h5, h28, #15", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_b_b_0, "sqshlu b5, b28, #0", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_b_b_4, "sqshlu b5, b28, #4", 5, 28) -+GEN_TWOVEC_TEST(sqshlu_b_b_7, "sqshlu b5, b28, #7", 5, 28) -+ -+GEN_TWOVEC_TEST(sqshl_2d_2d_0, "sqshl v6.2d, v27.2d, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshl_2d_2d_32, "sqshl v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(sqshl_2d_2d_63, "sqshl v6.2d, v27.2d, #63", 6, 27) -+GEN_TWOVEC_TEST(sqshl_4s_4s_0, "sqshl v6.4s, v27.4s, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshl_4s_4s_16, "sqshl v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(sqshl_4s_4s_31, "sqshl v6.4s, v27.4s, #31", 6, 27) -+GEN_TWOVEC_TEST(sqshl_2s_2s_0, "sqshl v6.2s, v27.2s, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshl_2s_2s_16, "sqshl v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(sqshl_2s_2s_31, "sqshl v6.2s, v27.2s, #31", 6, 27) -+GEN_TWOVEC_TEST(sqshl_8h_8h_0, "sqshl v6.8h, v27.8h, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshl_8h_8h_8, "sqshl v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(sqshl_8h_8h_15, "sqshl v6.8h, v27.8h, #15", 6, 27) -+GEN_TWOVEC_TEST(sqshl_4h_4h_0, "sqshl v6.4h, v27.4h, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshl_4h_4h_8, "sqshl v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(sqshl_4h_4h_15, "sqshl v6.4h, v27.4h, #15", 6, 27) -+GEN_TWOVEC_TEST(sqshl_16b_16b_0, "sqshl v6.16b, v27.16b, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshl_16b_16b_3, "sqshl v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(sqshl_16b_16b_7, "sqshl v6.16b, v27.16b, #7", 6, 27) -+GEN_TWOVEC_TEST(sqshl_8b_8b_0, "sqshl v6.8b, v27.8b, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshl_8b_8b_3, "sqshl v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(sqshl_8b_8b_7, "sqshl v6.8b, v27.8b, #7", 6, 27) -+ -+GEN_TWOVEC_TEST(uqshl_2d_2d_0, "uqshl v6.2d, v27.2d, #0", 6, 27) -+GEN_TWOVEC_TEST(uqshl_2d_2d_32, "uqshl v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(uqshl_2d_2d_63, "uqshl v6.2d, v27.2d, #63", 6, 27) -+GEN_TWOVEC_TEST(uqshl_4s_4s_0, "uqshl v6.4s, v27.4s, #0", 6, 27) -+GEN_TWOVEC_TEST(uqshl_4s_4s_16, "uqshl v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(uqshl_4s_4s_31, "uqshl v6.4s, v27.4s, #31", 6, 27) -+GEN_TWOVEC_TEST(uqshl_2s_2s_0, "uqshl v6.2s, v27.2s, #0", 6, 27) -+GEN_TWOVEC_TEST(uqshl_2s_2s_16, "uqshl v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(uqshl_2s_2s_31, "uqshl v6.2s, v27.2s, #31", 6, 27) -+GEN_TWOVEC_TEST(uqshl_8h_8h_0, "uqshl v6.8h, v27.8h, #0", 6, 27) -+GEN_TWOVEC_TEST(uqshl_8h_8h_8, "uqshl v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(uqshl_8h_8h_15, "uqshl v6.8h, v27.8h, #15", 6, 27) -+GEN_TWOVEC_TEST(uqshl_4h_4h_0, "uqshl v6.4h, v27.4h, #0", 6, 27) -+GEN_TWOVEC_TEST(uqshl_4h_4h_8, "uqshl v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(uqshl_4h_4h_15, "uqshl v6.4h, v27.4h, #15", 6, 27) -+GEN_TWOVEC_TEST(uqshl_16b_16b_0, "uqshl v6.16b, v27.16b, #0", 6, 27) -+GEN_TWOVEC_TEST(uqshl_16b_16b_3, "uqshl v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(uqshl_16b_16b_7, "uqshl v6.16b, v27.16b, #7", 6, 27) -+GEN_TWOVEC_TEST(uqshl_8b_8b_0, "uqshl v6.8b, v27.8b, #0", 6, 27) -+GEN_TWOVEC_TEST(uqshl_8b_8b_3, "uqshl v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(uqshl_8b_8b_7, "uqshl v6.8b, v27.8b, #7", 6, 27) -+ -+GEN_TWOVEC_TEST(sqshlu_2d_2d_0, "sqshlu v6.2d, v27.2d, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_2d_2d_32, "sqshlu v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_2d_2d_63, "sqshlu v6.2d, v27.2d, #63", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_4s_4s_0, "sqshlu v6.4s, v27.4s, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_4s_4s_16, "sqshlu v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_4s_4s_31, "sqshlu v6.4s, v27.4s, #31", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_2s_2s_0, "sqshlu v6.2s, v27.2s, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_2s_2s_16, "sqshlu v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_2s_2s_31, "sqshlu v6.2s, v27.2s, #31", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_8h_8h_0, "sqshlu v6.8h, v27.8h, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_8h_8h_8, "sqshlu v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_8h_8h_15, "sqshlu v6.8h, v27.8h, #15", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_4h_4h_0, "sqshlu v6.4h, v27.4h, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_4h_4h_8, "sqshlu v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_4h_4h_15, "sqshlu v6.4h, v27.4h, #15", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_16b_16b_0, "sqshlu v6.16b, v27.16b, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_16b_16b_3, "sqshlu v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_16b_16b_7, "sqshlu v6.16b, v27.16b, #7", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_8b_8b_0, "sqshlu v6.8b, v27.8b, #0", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_8b_8b_3, "sqshlu v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(sqshlu_8b_8b_7, "sqshlu v6.8b, v27.8b, #7", 6, 27) -+ -+GEN_TWOVEC_TEST(sqxtn_s_d, "sqxtn s31, d0", 31, 0) -+GEN_TWOVEC_TEST(sqxtn_h_s, "sqxtn h31, s0", 31, 0) -+GEN_TWOVEC_TEST(sqxtn_b_h, "sqxtn b31, h0", 31, 0) -+GEN_TWOVEC_TEST(uqxtn_s_d, "uqxtn s31, d0", 31, 0) -+GEN_TWOVEC_TEST(uqxtn_h_s, "uqxtn h31, s0", 31, 0) -+GEN_TWOVEC_TEST(uqxtn_b_h, "uqxtn b31, h0", 31, 0) -+GEN_TWOVEC_TEST(sqxtun_s_d, "sqxtun s31, d0", 31, 0) -+GEN_TWOVEC_TEST(sqxtun_h_s, "sqxtun h31, s0", 31, 0) -+GEN_TWOVEC_TEST(sqxtun_b_h, "sqxtun b31, h0", 31, 0) -+ -+GEN_UNARY_TEST(sqxtn, 2s, 2d) -+GEN_UNARY_TEST(sqxtn2, 4s, 2d) -+GEN_UNARY_TEST(sqxtn, 4h, 4s) -+GEN_UNARY_TEST(sqxtn2, 8h, 4s) -+GEN_UNARY_TEST(sqxtn, 8b, 8h) -+GEN_UNARY_TEST(sqxtn2, 16b, 8h) -+ -+GEN_UNARY_TEST(uqxtn, 2s, 2d) -+GEN_UNARY_TEST(uqxtn2, 4s, 2d) -+GEN_UNARY_TEST(uqxtn, 4h, 4s) -+GEN_UNARY_TEST(uqxtn2, 8h, 4s) -+GEN_UNARY_TEST(uqxtn, 8b, 8h) -+GEN_UNARY_TEST(uqxtn2, 16b, 8h) -+ -+GEN_UNARY_TEST(sqxtun, 2s, 2d) -+GEN_UNARY_TEST(sqxtun2, 4s, 2d) -+GEN_UNARY_TEST(sqxtun, 4h, 4s) -+GEN_UNARY_TEST(sqxtun2, 8h, 4s) -+GEN_UNARY_TEST(sqxtun, 8b, 8h) -+GEN_UNARY_TEST(sqxtun2, 16b, 8h) -+ -+GEN_THREEVEC_TEST(srhadd_4s_4s_4s,"srhadd v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(srhadd_2s_2s_2s,"srhadd v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(srhadd_8h_8h_8h,"srhadd v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(srhadd_4h_4h_4h,"srhadd v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(srhadd_16b_16b_16b, -+ "srhadd v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(srhadd_8b_8b_8b,"srhadd v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(urhadd_4s_4s_4s,"urhadd v2.4s, v11.4s, v29.4s", 2, 11, 29) -+GEN_THREEVEC_TEST(urhadd_2s_2s_2s,"urhadd v2.2s, v11.2s, v29.2s", 2, 11, 29) -+GEN_THREEVEC_TEST(urhadd_8h_8h_8h,"urhadd v2.8h, v11.8h, v29.8h", 2, 11, 29) -+GEN_THREEVEC_TEST(urhadd_4h_4h_4h,"urhadd v2.4h, v11.4h, v29.4h", 2, 11, 29) -+GEN_THREEVEC_TEST(urhadd_16b_16b_16b, -+ "urhadd v2.16b, v11.16b, v29.16b", 2, 11, 29) -+GEN_THREEVEC_TEST(urhadd_8b_8b_8b,"urhadd v2.8b, v11.8b, v29.8b", 2, 11, 29) -+ -+GEN_THREEVEC_TEST(sshl_d_d_d, "sshl d29, d28, d27", 29, 28, 27) -+GEN_THREEVEC_TEST(ushl_d_d_d, "ushl d29, d28, d27", 29, 28, 27) -+ -+GEN_THREEVEC_TEST(sshl_2d_2d_2d, "sshl v29.2d, v28.2d, v27.2d", 29,28,27) -+GEN_THREEVEC_TEST(sshl_4s_4s_4s, "sshl v29.4s, v28.4s, v27.4s", 29,28,27) -+GEN_THREEVEC_TEST(sshl_2s_2s_2s, "sshl v29.2s, v28.2s, v27.2s", 29,28,27) -+GEN_THREEVEC_TEST(sshl_8h_8h_8h, "sshl v29.8h, v28.8h, v27.8h", 29,28,27) -+GEN_THREEVEC_TEST(sshl_4h_4h_4h, "sshl v29.4h, v28.4h, v27.4h", 29,28,27) -+GEN_THREEVEC_TEST(sshl_16b_16b_16b, "sshl v29.16b, v28.16b, v27.16b", 29,28,27) -+GEN_THREEVEC_TEST(sshl_8b_8b_8b, "sshl v29.8b, v28.8b, v27.8b", 29,28,27) -+ -+GEN_THREEVEC_TEST(ushl_2d_2d_2d, "ushl v29.2d, v28.2d, v27.2d", 29,28,27) -+GEN_THREEVEC_TEST(ushl_4s_4s_4s, "ushl v29.4s, v28.4s, v27.4s", 29,28,27) -+GEN_THREEVEC_TEST(ushl_2s_2s_2s, "ushl v29.2s, v28.2s, v27.2s", 29,28,27) -+GEN_THREEVEC_TEST(ushl_8h_8h_8h, "ushl v29.8h, v28.8h, v27.8h", 29,28,27) -+GEN_THREEVEC_TEST(ushl_4h_4h_4h, "ushl v29.4h, v28.4h, v27.4h", 29,28,27) -+GEN_THREEVEC_TEST(ushl_16b_16b_16b, "ushl v29.16b, v28.16b, v27.16b", 29,28,27) -+GEN_THREEVEC_TEST(ushl_8b_8b_8b, "ushl v29.8b, v28.8b, v27.8b", 29,28,27) -+ -+GEN_TWOVEC_TEST(shl_d_d_0, "shl d5, d28, #0", 5, 28) -+GEN_TWOVEC_TEST(shl_d_d_32, "shl d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(shl_d_d_63, "shl d5, d28, #63", 5, 28) -+ -+GEN_TWOVEC_TEST(sshr_d_d_1, "sshr d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(sshr_d_d_32, "sshr d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(sshr_d_d_64, "sshr d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(ushr_d_d_1, "ushr d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(ushr_d_d_32, "ushr d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(ushr_d_d_64, "ushr d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(ssra_d_d_1, "ssra d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(ssra_d_d_32, "ssra d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(ssra_d_d_64, "ssra d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(usra_d_d_1, "usra d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(usra_d_d_32, "usra d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(usra_d_d_64, "usra d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(ssra_2d_2d_1, "ssra v6.2d, v27.2d, #1", 6, 27) -+GEN_TWOVEC_TEST(ssra_2d_2d_32, "ssra v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(ssra_2d_2d_64, "ssra v6.2d, v27.2d, #64", 6, 27) -+GEN_TWOVEC_TEST(ssra_4s_4s_1, "ssra v6.4s, v27.4s, #1", 6, 27) -+GEN_TWOVEC_TEST(ssra_4s_4s_16, "ssra v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(ssra_4s_4s_32, "ssra v6.4s, v27.4s, #32", 6, 27) -+GEN_TWOVEC_TEST(ssra_2s_2s_1, "ssra v6.2s, v27.2s, #1", 6, 27) -+GEN_TWOVEC_TEST(ssra_2s_2s_16, "ssra v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(ssra_2s_2s_32, "ssra v6.2s, v27.2s, #32", 6, 27) -+GEN_TWOVEC_TEST(ssra_8h_8h_1, "ssra v6.8h, v27.8h, #1", 6, 27) -+GEN_TWOVEC_TEST(ssra_8h_8h_8, "ssra v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(ssra_8h_8h_16, "ssra v6.8h, v27.8h, #16", 6, 27) -+GEN_TWOVEC_TEST(ssra_4h_4h_1, "ssra v6.4h, v27.4h, #1", 6, 27) -+GEN_TWOVEC_TEST(ssra_4h_4h_8, "ssra v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(ssra_4h_4h_16, "ssra v6.4h, v27.4h, #16", 6, 27) -+GEN_TWOVEC_TEST(ssra_16b_16b_1, "ssra v6.16b, v27.16b, #1", 6, 27) -+GEN_TWOVEC_TEST(ssra_16b_16b_3, "ssra v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(ssra_16b_16b_8, "ssra v6.16b, v27.16b, #8", 6, 27) -+GEN_TWOVEC_TEST(ssra_8b_8b_1, "ssra v6.8b, v27.8b, #1", 6, 27) -+GEN_TWOVEC_TEST(ssra_8b_8b_3, "ssra v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(ssra_8b_8b_8, "ssra v6.8b, v27.8b, #8", 6, 27) -+ -+GEN_TWOVEC_TEST(usra_2d_2d_1, "usra v6.2d, v27.2d, #1", 6, 27) -+GEN_TWOVEC_TEST(usra_2d_2d_32, "usra v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(usra_2d_2d_64, "usra v6.2d, v27.2d, #64", 6, 27) -+GEN_TWOVEC_TEST(usra_4s_4s_1, "usra v6.4s, v27.4s, #1", 6, 27) -+GEN_TWOVEC_TEST(usra_4s_4s_16, "usra v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(usra_4s_4s_32, "usra v6.4s, v27.4s, #32", 6, 27) -+GEN_TWOVEC_TEST(usra_2s_2s_1, "usra v6.2s, v27.2s, #1", 6, 27) -+GEN_TWOVEC_TEST(usra_2s_2s_16, "usra v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(usra_2s_2s_32, "usra v6.2s, v27.2s, #32", 6, 27) -+GEN_TWOVEC_TEST(usra_8h_8h_1, "usra v6.8h, v27.8h, #1", 6, 27) -+GEN_TWOVEC_TEST(usra_8h_8h_8, "usra v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(usra_8h_8h_16, "usra v6.8h, v27.8h, #16", 6, 27) -+GEN_TWOVEC_TEST(usra_4h_4h_1, "usra v6.4h, v27.4h, #1", 6, 27) -+GEN_TWOVEC_TEST(usra_4h_4h_8, "usra v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(usra_4h_4h_16, "usra v6.4h, v27.4h, #16", 6, 27) -+GEN_TWOVEC_TEST(usra_16b_16b_1, "usra v6.16b, v27.16b, #1", 6, 27) -+GEN_TWOVEC_TEST(usra_16b_16b_3, "usra v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(usra_16b_16b_8, "usra v6.16b, v27.16b, #8", 6, 27) -+GEN_TWOVEC_TEST(usra_8b_8b_1, "usra v6.8b, v27.8b, #1", 6, 27) -+GEN_TWOVEC_TEST(usra_8b_8b_3, "usra v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(usra_8b_8b_8, "usra v6.8b, v27.8b, #8", 6, 27) -+ -+GEN_THREEVEC_TEST(srshl_d_d_d, "srshl d29, d28, d27", 29, 28, 27) -+GEN_THREEVEC_TEST(urshl_d_d_d, "urshl d29, d28, d27", 29, 28, 27) -+ -+GEN_THREEVEC_TEST(srshl_2d_2d_2d, "srshl v29.2d, v28.2d, v27.2d", 29,28,27) -+GEN_THREEVEC_TEST(srshl_4s_4s_4s, "srshl v29.4s, v28.4s, v27.4s", 29,28,27) -+GEN_THREEVEC_TEST(srshl_2s_2s_2s, "srshl v29.2s, v28.2s, v27.2s", 29,28,27) -+GEN_THREEVEC_TEST(srshl_8h_8h_8h, "srshl v29.8h, v28.8h, v27.8h", 29,28,27) -+GEN_THREEVEC_TEST(srshl_4h_4h_4h, "srshl v29.4h, v28.4h, v27.4h", 29,28,27) -+GEN_THREEVEC_TEST(srshl_16b_16b_16b,"srshl v29.16b, v28.16b, v27.16b", 29,28,27) -+GEN_THREEVEC_TEST(srshl_8b_8b_8b, "srshl v29.8b, v28.8b, v27.8b", 29,28,27) -+ -+GEN_THREEVEC_TEST(urshl_2d_2d_2d, "urshl v29.2d, v28.2d, v27.2d", 29,28,27) -+GEN_THREEVEC_TEST(urshl_4s_4s_4s, "urshl v29.4s, v28.4s, v27.4s", 29,28,27) -+GEN_THREEVEC_TEST(urshl_2s_2s_2s, "urshl v29.2s, v28.2s, v27.2s", 29,28,27) -+GEN_THREEVEC_TEST(urshl_8h_8h_8h, "urshl v29.8h, v28.8h, v27.8h", 29,28,27) -+GEN_THREEVEC_TEST(urshl_4h_4h_4h, "urshl v29.4h, v28.4h, v27.4h", 29,28,27) -+GEN_THREEVEC_TEST(urshl_16b_16b_16b,"urshl v29.16b, v28.16b, v27.16b", 29,28,27) -+GEN_THREEVEC_TEST(urshl_8b_8b_8b, "urshl v29.8b, v28.8b, v27.8b", 29,28,27) -+ -+GEN_TWOVEC_TEST(srshr_d_d_1, "srshr d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(srshr_d_d_32, "srshr d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(srshr_d_d_64, "srshr d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(urshr_d_d_1, "urshr d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(urshr_d_d_32, "urshr d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(urshr_d_d_64, "urshr d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(srshr_2d_2d_1, "srshr v6.2d, v27.2d, #1", 6, 27) -+GEN_TWOVEC_TEST(srshr_2d_2d_32, "srshr v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(srshr_2d_2d_64, "srshr v6.2d, v27.2d, #64", 6, 27) -+GEN_TWOVEC_TEST(srshr_4s_4s_1, "srshr v6.4s, v27.4s, #1", 6, 27) -+GEN_TWOVEC_TEST(srshr_4s_4s_16, "srshr v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(srshr_4s_4s_32, "srshr v6.4s, v27.4s, #32", 6, 27) -+GEN_TWOVEC_TEST(srshr_2s_2s_1, "srshr v6.2s, v27.2s, #1", 6, 27) -+GEN_TWOVEC_TEST(srshr_2s_2s_16, "srshr v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(srshr_2s_2s_32, "srshr v6.2s, v27.2s, #32", 6, 27) -+GEN_TWOVEC_TEST(srshr_8h_8h_1, "srshr v6.8h, v27.8h, #1", 6, 27) -+GEN_TWOVEC_TEST(srshr_8h_8h_8, "srshr v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(srshr_8h_8h_16, "srshr v6.8h, v27.8h, #16", 6, 27) -+GEN_TWOVEC_TEST(srshr_4h_4h_1, "srshr v6.4h, v27.4h, #1", 6, 27) -+GEN_TWOVEC_TEST(srshr_4h_4h_8, "srshr v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(srshr_4h_4h_16, "srshr v6.4h, v27.4h, #16", 6, 27) -+GEN_TWOVEC_TEST(srshr_16b_16b_1, "srshr v6.16b, v27.16b, #1", 6, 27) -+GEN_TWOVEC_TEST(srshr_16b_16b_3, "srshr v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(srshr_16b_16b_8, "srshr v6.16b, v27.16b, #8", 6, 27) -+GEN_TWOVEC_TEST(srshr_8b_8b_1, "srshr v6.8b, v27.8b, #1", 6, 27) -+GEN_TWOVEC_TEST(srshr_8b_8b_3, "srshr v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(srshr_8b_8b_8, "srshr v6.8b, v27.8b, #8", 6, 27) -+ -+GEN_TWOVEC_TEST(urshr_2d_2d_1, "urshr v6.2d, v27.2d, #1", 6, 27) -+GEN_TWOVEC_TEST(urshr_2d_2d_32, "urshr v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(urshr_2d_2d_64, "urshr v6.2d, v27.2d, #64", 6, 27) -+GEN_TWOVEC_TEST(urshr_4s_4s_1, "urshr v6.4s, v27.4s, #1", 6, 27) -+GEN_TWOVEC_TEST(urshr_4s_4s_16, "urshr v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(urshr_4s_4s_32, "urshr v6.4s, v27.4s, #32", 6, 27) -+GEN_TWOVEC_TEST(urshr_2s_2s_1, "urshr v6.2s, v27.2s, #1", 6, 27) -+GEN_TWOVEC_TEST(urshr_2s_2s_16, "urshr v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(urshr_2s_2s_32, "urshr v6.2s, v27.2s, #32", 6, 27) -+GEN_TWOVEC_TEST(urshr_8h_8h_1, "urshr v6.8h, v27.8h, #1", 6, 27) -+GEN_TWOVEC_TEST(urshr_8h_8h_8, "urshr v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(urshr_8h_8h_16, "urshr v6.8h, v27.8h, #16", 6, 27) -+GEN_TWOVEC_TEST(urshr_4h_4h_1, "urshr v6.4h, v27.4h, #1", 6, 27) -+GEN_TWOVEC_TEST(urshr_4h_4h_8, "urshr v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(urshr_4h_4h_16, "urshr v6.4h, v27.4h, #16", 6, 27) -+GEN_TWOVEC_TEST(urshr_16b_16b_1, "urshr v6.16b, v27.16b, #1", 6, 27) -+GEN_TWOVEC_TEST(urshr_16b_16b_3, "urshr v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(urshr_16b_16b_8, "urshr v6.16b, v27.16b, #8", 6, 27) -+GEN_TWOVEC_TEST(urshr_8b_8b_1, "urshr v6.8b, v27.8b, #1", 6, 27) -+GEN_TWOVEC_TEST(urshr_8b_8b_3, "urshr v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(urshr_8b_8b_8, "urshr v6.8b, v27.8b, #8", 6, 27) -+ -+GEN_TWOVEC_TEST(srsra_d_d_1, "srsra d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(srsra_d_d_32, "srsra d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(srsra_d_d_64, "srsra d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(ursra_d_d_1, "ursra d5, d28, #1", 5, 28) -+GEN_TWOVEC_TEST(ursra_d_d_32, "ursra d5, d28, #32", 5, 28) -+GEN_TWOVEC_TEST(ursra_d_d_64, "ursra d5, d28, #64", 5, 28) -+ -+GEN_TWOVEC_TEST(srsra_2d_2d_1, "srsra v6.2d, v27.2d, #1", 6, 27) -+GEN_TWOVEC_TEST(srsra_2d_2d_32, "srsra v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(srsra_2d_2d_64, "srsra v6.2d, v27.2d, #64", 6, 27) -+GEN_TWOVEC_TEST(srsra_4s_4s_1, "srsra v6.4s, v27.4s, #1", 6, 27) -+GEN_TWOVEC_TEST(srsra_4s_4s_16, "srsra v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(srsra_4s_4s_32, "srsra v6.4s, v27.4s, #32", 6, 27) -+GEN_TWOVEC_TEST(srsra_2s_2s_1, "srsra v6.2s, v27.2s, #1", 6, 27) -+GEN_TWOVEC_TEST(srsra_2s_2s_16, "srsra v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(srsra_2s_2s_32, "srsra v6.2s, v27.2s, #32", 6, 27) -+GEN_TWOVEC_TEST(srsra_8h_8h_1, "srsra v6.8h, v27.8h, #1", 6, 27) -+GEN_TWOVEC_TEST(srsra_8h_8h_8, "srsra v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(srsra_8h_8h_16, "srsra v6.8h, v27.8h, #16", 6, 27) -+GEN_TWOVEC_TEST(srsra_4h_4h_1, "srsra v6.4h, v27.4h, #1", 6, 27) -+GEN_TWOVEC_TEST(srsra_4h_4h_8, "srsra v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(srsra_4h_4h_16, "srsra v6.4h, v27.4h, #16", 6, 27) -+GEN_TWOVEC_TEST(srsra_16b_16b_1, "srsra v6.16b, v27.16b, #1", 6, 27) -+GEN_TWOVEC_TEST(srsra_16b_16b_3, "srsra v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(srsra_16b_16b_8, "srsra v6.16b, v27.16b, #8", 6, 27) -+GEN_TWOVEC_TEST(srsra_8b_8b_1, "srsra v6.8b, v27.8b, #1", 6, 27) -+GEN_TWOVEC_TEST(srsra_8b_8b_3, "srsra v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(srsra_8b_8b_8, "srsra v6.8b, v27.8b, #8", 6, 27) -+ -+GEN_TWOVEC_TEST(ursra_2d_2d_1, "ursra v6.2d, v27.2d, #1", 6, 27) -+GEN_TWOVEC_TEST(ursra_2d_2d_32, "ursra v6.2d, v27.2d, #32", 6, 27) -+GEN_TWOVEC_TEST(ursra_2d_2d_64, "ursra v6.2d, v27.2d, #64", 6, 27) -+GEN_TWOVEC_TEST(ursra_4s_4s_1, "ursra v6.4s, v27.4s, #1", 6, 27) -+GEN_TWOVEC_TEST(ursra_4s_4s_16, "ursra v6.4s, v27.4s, #16", 6, 27) -+GEN_TWOVEC_TEST(ursra_4s_4s_32, "ursra v6.4s, v27.4s, #32", 6, 27) -+GEN_TWOVEC_TEST(ursra_2s_2s_1, "ursra v6.2s, v27.2s, #1", 6, 27) -+GEN_TWOVEC_TEST(ursra_2s_2s_16, "ursra v6.2s, v27.2s, #16", 6, 27) -+GEN_TWOVEC_TEST(ursra_2s_2s_32, "ursra v6.2s, v27.2s, #32", 6, 27) -+GEN_TWOVEC_TEST(ursra_8h_8h_1, "ursra v6.8h, v27.8h, #1", 6, 27) -+GEN_TWOVEC_TEST(ursra_8h_8h_8, "ursra v6.8h, v27.8h, #8", 6, 27) -+GEN_TWOVEC_TEST(ursra_8h_8h_16, "ursra v6.8h, v27.8h, #16", 6, 27) -+GEN_TWOVEC_TEST(ursra_4h_4h_1, "ursra v6.4h, v27.4h, #1", 6, 27) -+GEN_TWOVEC_TEST(ursra_4h_4h_8, "ursra v6.4h, v27.4h, #8", 6, 27) -+GEN_TWOVEC_TEST(ursra_4h_4h_16, "ursra v6.4h, v27.4h, #16", 6, 27) -+GEN_TWOVEC_TEST(ursra_16b_16b_1, "ursra v6.16b, v27.16b, #1", 6, 27) -+GEN_TWOVEC_TEST(ursra_16b_16b_3, "ursra v6.16b, v27.16b, #3", 6, 27) -+GEN_TWOVEC_TEST(ursra_16b_16b_8, "ursra v6.16b, v27.16b, #8", 6, 27) -+GEN_TWOVEC_TEST(ursra_8b_8b_1, "ursra v6.8b, v27.8b, #1", 6, 27) -+GEN_TWOVEC_TEST(ursra_8b_8b_3, "ursra v6.8b, v27.8b, #3", 6, 27) -+GEN_TWOVEC_TEST(ursra_8b_8b_8, "ursra v6.8b, v27.8b, #8", 6, 27) -+ -+GEN_TWOVEC_TEST(suqadd_d_d, "suqadd d22, d23", 22, 23) -+GEN_TWOVEC_TEST(suqadd_s_s, "suqadd s22, s23", 22, 23) -+GEN_TWOVEC_TEST(suqadd_h_h, "suqadd h22, h23", 22, 23) -+GEN_TWOVEC_TEST(suqadd_b_b, "suqadd b22, b23", 22, 23) -+ -+GEN_TWOVEC_TEST(suqadd_2d_2d, "suqadd v6.2d, v27.2d", 6, 27) -+GEN_TWOVEC_TEST(suqadd_4s_4s, "suqadd v6.4s, v27.4s", 6, 27) -+GEN_TWOVEC_TEST(suqadd_2s_2s, "suqadd v6.2s, v27.2s", 6, 27) -+GEN_TWOVEC_TEST(suqadd_8h_8h, "suqadd v6.8h, v27.8h", 6, 27) -+GEN_TWOVEC_TEST(suqadd_4h_4h, "suqadd v6.4h, v27.4h", 6, 27) -+GEN_TWOVEC_TEST(suqadd_16b_16b, "suqadd v6.16b, v27.16b", 6, 27) -+GEN_TWOVEC_TEST(suqadd_8b_8b, "suqadd v6.8b, v27.8b", 6, 27) -+ -+GEN_TWOVEC_TEST(usqadd_d_d, "usqadd d22, d23", 22, 23) -+GEN_TWOVEC_TEST(usqadd_s_s, "usqadd s22, s23", 22, 23) -+GEN_TWOVEC_TEST(usqadd_h_h, "usqadd h22, h23", 22, 23) -+GEN_TWOVEC_TEST(usqadd_b_b, "usqadd b22, b23", 22, 23) -+ -+GEN_TWOVEC_TEST(usqadd_2d_2d, "usqadd v6.2d, v27.2d", 6, 27) -+GEN_TWOVEC_TEST(usqadd_4s_4s, "usqadd v6.4s, v27.4s", 6, 27) -+GEN_TWOVEC_TEST(usqadd_2s_2s, "usqadd v6.2s, v27.2s", 6, 27) -+GEN_TWOVEC_TEST(usqadd_8h_8h, "usqadd v6.8h, v27.8h", 6, 27) -+GEN_TWOVEC_TEST(usqadd_4h_4h, "usqadd v6.4h, v27.4h", 6, 27) -+GEN_TWOVEC_TEST(usqadd_16b_16b, "usqadd v6.16b, v27.16b", 6, 27) -+GEN_TWOVEC_TEST(usqadd_8b_8b, "usqadd v6.8b, v27.8b", 6, 27) -+ -+GEN_THREEVEC_TEST(trn1_2d_2d_2d, "trn1 v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(trn1_4s_4s_4s, "trn1 v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(trn1_2s_2s_2s, "trn1 v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(trn1_8h_8h_8h, "trn1 v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(trn1_4h_4h_4h, "trn1 v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(trn1_16b_16b_16b, "trn1 v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(trn1_8b_8b_8b, "trn1 v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(trn2_2d_2d_2d, "trn2 v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(trn2_4s_4s_4s, "trn2 v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(trn2_2s_2s_2s, "trn2 v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(trn2_8h_8h_8h, "trn2 v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(trn2_4h_4h_4h, "trn2 v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(trn2_16b_16b_16b, "trn2 v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(trn2_8b_8b_8b, "trn2 v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(uzp1_2d_2d_2d, "uzp1 v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp1_4s_4s_4s, "uzp1 v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp1_2s_2s_2s, "uzp1 v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp1_8h_8h_8h, "uzp1 v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp1_4h_4h_4h, "uzp1 v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp1_16b_16b_16b, "uzp1 v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp1_8b_8b_8b, "uzp1 v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(uzp2_2d_2d_2d, "uzp2 v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp2_4s_4s_4s, "uzp2 v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp2_2s_2s_2s, "uzp2 v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp2_8h_8h_8h, "uzp2 v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp2_4h_4h_4h, "uzp2 v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp2_16b_16b_16b, "uzp2 v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(uzp2_8b_8b_8b, "uzp2 v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(zip1_2d_2d_2d, "zip1 v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(zip1_4s_4s_4s, "zip1 v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(zip1_2s_2s_2s, "zip1 v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(zip1_8h_8h_8h, "zip1 v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(zip1_4h_4h_4h, "zip1 v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(zip1_16b_16b_16b, "zip1 v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(zip1_8b_8b_8b, "zip1 v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_THREEVEC_TEST(zip2_2d_2d_2d, "zip2 v1.2d, v2.2d, v4.2d", 1, 2, 4) -+GEN_THREEVEC_TEST(zip2_4s_4s_4s, "zip2 v1.4s, v2.4s, v4.4s", 1, 2, 4) -+GEN_THREEVEC_TEST(zip2_2s_2s_2s, "zip2 v1.2s, v2.2s, v4.2s", 1, 2, 4) -+GEN_THREEVEC_TEST(zip2_8h_8h_8h, "zip2 v1.8h, v2.8h, v4.8h", 1, 2, 4) -+GEN_THREEVEC_TEST(zip2_4h_4h_4h, "zip2 v1.4h, v2.4h, v4.4h", 1, 2, 4) -+GEN_THREEVEC_TEST(zip2_16b_16b_16b, "zip2 v1.16b, v2.16b, v4.16b", 1, 2, 4) -+GEN_THREEVEC_TEST(zip2_8b_8b_8b, "zip2 v1.8b, v2.8b, v4.8b", 1, 2, 4) -+ -+GEN_TWOVEC_TEST(urecpe_4s_4s, "urecpe v6.4s, v27.4s", 6, 27) -+GEN_TWOVEC_TEST(urecpe_2s_2s, "urecpe v6.2s, v27.2s", 6, 27) -+ -+GEN_TWOVEC_TEST(ursqrte_4s_4s, "ursqrte v6.4s, v27.4s", 6, 27) -+GEN_TWOVEC_TEST(ursqrte_2s_2s, "ursqrte v6.2s, v27.2s", 6, 27) -+ -+ -+/* ---------------------------------------------------------------- */ -+/* -- main() -- */ -+/* ---------------------------------------------------------------- */ -+ -+int main ( void ) -+{ -+ assert(sizeof(V128) == 16); -+ -+ // ======================== FP ======================== -+ -+ // fabs d,s -+ // fabs 2d,4s,2s -+ test_fabs_d_d(TyDF); -+ test_fabs_s_s(TySF); -+ test_fabs_2d_2d(TyDF); -+ test_fabs_4s_4s(TySF); -+ test_fabs_2s_2s(TyDF); -+ test_fneg_2d_2d(TySF); -+ test_fneg_4s_4s(TyDF); -+ test_fneg_2s_2s(TySF); -+ -+ // fneg d,s -+ // fneg 2d,4s,2s -+ test_fneg_d_d(TyDF); -+ test_fneg_s_s(TySF); -+ -+ // fsqrt d,s -+ // fsqrt 2d,4s,2s -+ test_fsqrt_d_d(TyDF); -+ test_fsqrt_s_s(TySF); -+ -+ // fadd d,s -+ // fsub d,s -+ test_fadd_d_d_d(TyDF); -+ test_fadd_s_s_s(TySF); -+ test_fsub_d_d_d(TyDF); -+ test_fsub_s_s_s(TySF); -+ -+ // fadd 2d,4s,2s -+ // fsub 2d,4s,2s -+ test_fadd_2d_2d_2d(TyDF); -+ test_fadd_4s_4s_4s(TySF); -+ test_fadd_2s_2s_2s(TySF); -+ test_fsub_2d_2d_2d(TyDF); -+ test_fsub_4s_4s_4s(TySF); -+ test_fsub_2s_2s_2s(TySF); -+ -+ // fabd d,s -+ // fabd 2d,4s,2s -+ test_fabd_d_d_d(TyDF); -+ test_fabd_s_s_s(TySF); -+ test_fabd_2d_2d_2d(TyDF); -+ test_fabd_4s_4s_4s(TySF); -+ test_fabd_2s_2s_2s(TySF); -+ -+ // faddp d,s (floating add pair) -+ // faddp 2d,4s,2s -+ -+ // fccmp d,s (floating point conditional quiet compare) -+ // fccmpe d,s (floating point conditional signaling compare) -+ -+ // fcmeq d,s -+ // fcmge d,s -+ // fcmgt d,s -+ // facgt d,s (floating abs compare GE) -+ // facge d,s (floating abs compare GE) -+ -+ // fcmeq 2d,4s,2s -+ // fcmge 2d,4s,2s -+ // fcmgt 2d,4s,2s -+ // facge 2d,4s,2s -+ // facgt 2d,4s,2s -+ test_fcmeq_2d_2d_2d(TyDF); -+ test_fcmeq_4s_4s_4s(TySF); -+ test_fcmeq_2s_2s_2s(TySF); -+ test_fcmge_2d_2d_2d(TyDF); -+ test_fcmge_4s_4s_4s(TySF); -+ test_fcmge_2s_2s_2s(TySF); -+ test_fcmgt_2d_2d_2d(TyDF); -+ test_fcmgt_4s_4s_4s(TySF); -+ test_fcmgt_2s_2s_2s(TySF); -+ test_facge_2d_2d_2d(TyDF); -+ test_facge_4s_4s_4s(TySF); -+ test_facge_2s_2s_2s(TySF); -+ test_facgt_2d_2d_2d(TyDF); -+ test_facgt_4s_4s_4s(TySF); -+ test_facgt_2s_2s_2s(TySF); -+ -+ // fcmeq_z d,s -+ // fcmge_z d,s -+ // fcmgt_z d,s -+ // fcmle_z d,s -+ // fcmlt_z d,s -+ -+ // fcmeq_z 2d,4s,2s -+ // fcmge_z 2d,4s,2s -+ // fcmgt_z 2d,4s,2s -+ // fcmle_z 2d,4s,2s -+ // fcmlt_z 2d,4s,2s -+ -+ // fcmp_z d,s -+ // fcmpe_z d,s -+ // fcmp d,s (floating point quiet, set flags) -+ // fcmpe d,s (floating point signaling, set flags) -+ -+ // fcsel d,s (fp cond select) -+ -+ // fdiv d,s -+ // fdiv 2d,4s,2s -+ test_fdiv_d_d_d(TyDF); -+ test_fdiv_s_s_s(TySF); -+ test_fdiv_2d_2d_2d(TyDF); -+ test_fdiv_4s_4s_4s(TySF); -+ test_fdiv_2s_2s_2s(TySF); -+ -+ // fmadd d,s -+ // fnmadd d,s -+ // fmsub d,s -+ // fnmsub d,s -+ -+ // fnmul d,s -+ test_fnmul_d_d_d(TyDF); -+ test_fnmul_s_s_s(TySF); -+ -+ // fmax d,s -+ // fmin d,s -+ // fmaxnm d,s ("max number") -+ // fminnm d,s -+ -+ // fmax 2d,4s,2s -+ // fmin 2d,4s,2s -+ // fmaxnm 2d,4s,2s -+ // fminnm 2d,4s,2s -+ -+ // fmaxnmp d_2d,s_2s ("max number pairwise") -+ // fminnmp d_2d,s_2s -+ -+ // fmaxnmp 2d,4s,2s -+ // fminnmp 2d,4s,2s -+ -+ // fmaxnmv s_4s (maxnum across vector) -+ // fminnmv s_4s -+ -+ // fmaxp d_2d,s_2s (max of a pair) -+ // fminp d_2d,s_2s (max of a pair) -+ -+ // fmaxp 2d,4s,2s (max pairwise) -+ // fminp 2d,4s,2s -+ -+ // fmaxv s_4s (max across vector) -+ // fminv s_4s -+ -+ // fmla 2d,4s,2s -+ // fmls 2d,4s,2s -+ test_fmla_2d_2d_2d(TyDF); -+ test_fmla_4s_4s_4s(TySF); -+ test_fmla_2s_2s_2s(TySF); -+ test_fmls_2d_2d_2d(TyDF); -+ test_fmls_4s_4s_4s(TySF); -+ test_fmls_2s_2s_2s(TySF); -+ -+ // fmla d_d_d[],s_s_s[] (by element) -+ // fmls d_d_d[],s_s_s[] (by element) -+ -+ // fmla 2d_2d_d[],4s_4s_s[],2s_2s_s[] -+ // fmls 2d_2d_d[],4s_4s_s[],2s_2s_s[] -+ -+ // fmov 2d,4s,2s #imm (part of the MOVI/MVNI/ORR/BIC imm group) -+ // INCOMPLETE -+ test_fmov_2d_imm_01(TyD); -+ test_fmov_2d_imm_02(TyD); -+ test_fmov_2d_imm_03(TyD); -+ if (0) test_fmov_4s_imm_01(TyS); -+ if (0) test_fmov_4s_imm_02(TyS); -+ if (0) test_fmov_4s_imm_03(TyS); -+ if (0) test_fmov_2s_imm_01(TyS); -+ if (0) test_fmov_2s_imm_02(TyS); -+ if (0) test_fmov_2s_imm_03(TyS); -+ -+ // fmov d_d,s_s -+ test_fmov_d_d(TyDF); -+ test_fmov_s_s(TySF); -+ -+ // fmov s_w,w_s,d_x,d[1]_x,x_d,x_d[1] -+ test_fmov_s_w(TyS); -+ test_fmov_d_x(TyD); -+ test_fmov_d1_x(TyD); -+ test_fmov_w_s(TyS); -+ test_fmov_x_d(TyD); -+ test_fmov_x_d1(TyD); -+ -+ // fmov d,s #imm -+ test_fmov_d_imm_01(TyNONE); -+ test_fmov_d_imm_02(TyNONE); -+ test_fmov_d_imm_03(TyNONE); -+ test_fmov_s_imm_01(TyNONE); -+ test_fmov_s_imm_02(TyNONE); -+ test_fmov_s_imm_03(TyNONE); -+ -+ // fmul d_d_d[],s_s_s[] -+ // fmul 2d_2d_d[],4s_4s_s[],2s_2s_s[] -+ -+ // fmul 2d,4s,2s -+ // fmul d,s -+ test_fmul_d_d_d(TyDF); -+ test_fmul_s_s_s(TySF); -+ test_fmul_2d_2d_2d(TyDF); -+ test_fmul_4s_4s_4s(TySF); -+ test_fmul_2s_2s_2s(TySF); -+ -+ // fmulx d_d_d[],s_s_s[] -+ // fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[] -+ -+ // fmulx d,s -+ // fmulx 2d,4s,2s -+ -+ // frecpe d,s (recip estimate) -+ // frecpe 2d,4s,2s -+ -+ // frecps d,s (recip step) -+ // frecps 2d,4s,2s -+ -+ // frecpx d,s (recip exponent) -+ -+ // frinta d,s -+ // frinti d,s -+ // frintm d,s -+ // frintn d,s -+ // frintp d,s -+ // frintx d,s -+ // frintz d,s -+ -+ // frinta 2d,4s,2s (round to integral, nearest away) -+ // frinti 2d,4s,2s (round to integral, per FPCR) -+ // frintm 2d,4s,2s (round to integral, minus inf) -+ // frintn 2d,4s,2s (round to integral, nearest, to even) -+ // frintp 2d,4s,2s (round to integral, plus inf) -+ // frintx 2d,4s,2s (round to integral exact, per FPCR) -+ // frintz 2d,4s,2s (round to integral, zero) -+ -+ // frsqrte d,s (est) -+ // frsqrte 2d,4s,2s -+ -+ // frsqrts d,s (step) -+ // frsqrts 2d,4s,2s -+ -+ // ======================== CONV ======================== -+ -+ // fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar) -+ -+ // fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form) -+ -+ // fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form) -+ // INCOMPLETE -+ test_fcvtn_2s_2d(TyDF); -+ test_fcvtn_4s_2d(TyDF); -+ -+ // fcvtas d,s (fcvt to signed int, nearest, ties away) -+ // fcvtau d,s (fcvt to unsigned int, nearest, ties away) -+ // fcvtas 2d,4s,2s -+ // fcvtau 2d,4s,2s -+ // fcvtas w_s,x_s,w_d,x_d -+ // fcvtau w_s,x_s,w_d,x_d -+ -+ // fcvtms d,s (fcvt to signed int, minus inf) -+ // fcvtmu d,s (fcvt to unsigned int, minus inf) -+ // fcvtms 2d,4s,2s -+ // fcvtmu 2d,4s,2s -+ // fcvtms w_s,x_s,w_d,x_d -+ // fcvtmu w_s,x_s,w_d,x_d -+ -+ // fcvtns d,s (fcvt to signed int, nearest) -+ // fcvtnu d,s (fcvt to unsigned int, nearest) -+ // fcvtns 2d,4s,2s -+ // fcvtnu 2d,4s,2s -+ // fcvtns w_s,x_s,w_d,x_d -+ // fcvtnu w_s,x_s,w_d,x_d -+ -+ // fcvtps d,s (fcvt to signed int, plus inf) -+ // fcvtpu d,s (fcvt to unsigned int, plus inf) -+ // fcvtps 2d,4s,2s -+ // fcvtpu 2d,4s,2s -+ // fcvtps w_s,x_s,w_d,x_d -+ // fcvtpu w_s,x_s,w_d,x_d -+ -+ // fcvtzs d,s (fcvt to signed integer, to zero) -+ // fcvtzu d,s (fcvt to unsigned integer, to zero) -+ // fcvtzs 2d,4s,2s -+ // fcvtzu 2d,4s,2s -+ // fcvtzs w_s,x_s,w_d,x_d -+ // fcvtzu w_s,x_s,w_d,x_d -+ -+ // fcvtzs d,s (fcvt to signed fixedpt, to zero) (w/ #fbits) -+ // fcvtzu d,s (fcvt to unsigned fixedpt, to zero) (w/ #fbits) -+ // fcvtzs 2d,4s,2s -+ // fcvtzu 2d,4s,2s -+ // fcvtzs w_s,x_s,w_d,x_d (fcvt to signed fixedpt, to zero) (w/ #fbits) -+ // fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned fixedpt, to zero) (w/ #fbits) -+ -+ // fcvtxn s_d (fcvt to lower prec narrow, rounding to odd) -+ // fcvtxn 2s_2d,4s_2d -+ -+ // scvtf d,s _#fbits -+ // ucvtf d,s _#fbits -+ -+ // scvtf 2d,4s,2s _#fbits -+ // ucvtf 2d,4s,2s _#fbits -+ -+ // scvtf d,s -+ // ucvtf d,s -+ -+ // scvtf 2d,4s,2s -+ // ucvtf 2d,4s,2s -+ -+ // scvtf s_w, d_w, s_x, d_x, _#fbits -+ // ucvtf s_w, d_w, s_x, d_x, _#fbits -+ -+ // scvtf s_w, d_w, s_x, d_x -+ // ucvtf s_w, d_w, s_x, d_x -+ test_scvtf_s_w(TyS); -+ test_scvtf_d_w(TyS); -+ test_scvtf_s_x(TyD); -+ test_scvtf_d_x(TyD); -+ test_ucvtf_s_w(TyS); -+ test_ucvtf_d_w(TyS); -+ test_ucvtf_s_x(TyD); -+ test_ucvtf_d_x(TyD); -+ -+ // ======================== INT ======================== -+ -+ // abs d -+ // neg d -+ test_abs_d_d(TyD); -+ test_neg_d_d(TyD); -+ -+ // abs 2d,4s,2s,8h,4h,16b,8b -+ // neg 2d,4s,2s,8h,4h,16b,8b -+ test_abs_2d_2d(TyD); -+ test_abs_4s_4s(TyS); -+ test_abs_2s_2s(TyS); -+ test_abs_8h_8h(TyH); -+ test_abs_4h_4h(TyH); -+ test_abs_16b_16b(TyB); -+ test_abs_8b_8b(TyB); -+ test_neg_2d_2d(TyD); -+ test_neg_4s_4s(TyS); -+ test_neg_2s_2s(TyS); -+ test_neg_8h_8h(TyH); -+ test_neg_4h_4h(TyH); -+ test_neg_16b_16b(TyB); -+ test_neg_8b_8b(TyB); -+ -+ // add d -+ // sub d -+ test_add_d_d_d(TyD); -+ test_sub_d_d_d(TyD); -+ -+ // add 2d,4s,2s,8h,4h,16b,8b -+ // sub 2d,4s,2s,8h,4h,16b,8b -+ test_add_2d_2d_2d(TyD); -+ test_add_4s_4s_4s(TyS); -+ test_add_2s_2s_2s(TyS); -+ test_add_8h_8h_8h(TyH); -+ test_add_4h_4h_4h(TyH); -+ test_add_16b_16b_16b(TyB); -+ test_add_8b_8b_8b(TyB); -+ test_sub_2d_2d_2d(TyD); -+ test_sub_4s_4s_4s(TyS); -+ test_sub_2s_2s_2s(TyS); -+ test_sub_8h_8h_8h(TyH); -+ test_sub_4h_4h_4h(TyH); -+ test_sub_16b_16b_16b(TyB); -+ test_sub_8b_8b_8b(TyB); -+ -+ // addhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h -+ // subhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h -+ // raddhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h -+ // rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h -+ test_addhn_2s_2d_2d(TyD); -+ test_addhn2_4s_2d_2d(TyD); -+ test_addhn_4h_4s_4s(TyS); -+ test_addhn2_8h_4s_4s(TyS); -+ test_addhn_8b_8h_8h(TyH); -+ test_addhn2_16b_8h_8h(TyH); -+ test_subhn_2s_2d_2d(TyD); -+ test_subhn2_4s_2d_2d(TyD); -+ test_subhn_4h_4s_4s(TyS); -+ test_subhn2_8h_4s_4s(TyS); -+ test_subhn_8b_8h_8h(TyH); -+ test_subhn2_16b_8h_8h(TyH); -+ test_raddhn_2s_2d_2d(TyD); -+ test_raddhn2_4s_2d_2d(TyD); -+ test_raddhn_4h_4s_4s(TyS); -+ test_raddhn2_8h_4s_4s(TyS); -+ test_raddhn_8b_8h_8h(TyH); -+ test_raddhn2_16b_8h_8h(TyH); -+ test_rsubhn_2s_2d_2d(TyD); -+ test_rsubhn2_4s_2d_2d(TyD); -+ test_rsubhn_4h_4s_4s(TyS); -+ test_rsubhn2_8h_4s_4s(TyS); -+ test_rsubhn_8b_8h_8h(TyH); -+ test_rsubhn2_16b_8h_8h(TyH); -+ -+ // addp d (add pairs, across) -+ test_addp_d_2d(TyD); -+ -+ // addp 2d,4s,2s,8h,4h,16b,8b -+ test_addp_2d_2d_2d(TyD); -+ test_addp_4s_4s_4s(TyS); -+ test_addp_2s_2s_2s(TyS); -+ test_addp_8h_8h_8h(TyH); -+ test_addp_4h_4h_4h(TyH); -+ test_addp_16b_16b_16b(TyB); -+ test_addp_8b_8b_8b(TyB); -+ -+ // addv 4s,8h,4h,16b,18b (reduce across vector) -+ test_addv_s_4s(TyS); -+ test_addv_h_8h(TyH); -+ test_addv_h_4h(TyH); -+ test_addv_b_16b(TyB); -+ test_addv_b_8b(TyB); -+ -+ // and 16b,8b -+ // bic 16b,8b -+ // orn 16b,8b -+ // orr 16b,8b -+ test_and_16b_16b_16b(TyB); -+ test_and_8b_8b_8b(TyB); -+ test_bic_16b_16b_16b(TyB); -+ test_bic_8b_8b_8b(TyB); -+ test_orr_16b_16b_16b(TyB); -+ test_orr_8b_8b_8b(TyB); -+ test_orn_16b_16b_16b(TyB); -+ test_orn_8b_8b_8b(TyB); -+ -+ // orr 8h,4h #imm8, LSL #0 or 8 -+ // orr 4s,2s #imm8, LSL #0, 8, 16 or 24 -+ // bic 8h,4h #imm8, LSL #0 or 8 -+ // bic 4s,2s #imm8, LSL #0, 8, 16 or 24 -+ // movi and mvni are very similar, a superset of these. -+ // Cases are below. -+ test_orr_8h_0x5A_lsl0(TyH); -+ test_orr_8h_0xA5_lsl8(TyH); -+ test_orr_4h_0x5A_lsl0(TyH); -+ test_orr_4h_0xA5_lsl8(TyH); -+ test_orr_4s_0x5A_lsl0(TyS); -+ test_orr_4s_0x6B_lsl8(TyS); -+ test_orr_4s_0x49_lsl16(TyS); -+ test_orr_4s_0x3D_lsl24(TyS); -+ test_orr_2s_0x5A_lsl0(TyS); -+ test_orr_2s_0x6B_lsl8(TyS); -+ test_orr_2s_0x49_lsl16(TyS); -+ test_orr_2s_0x3D_lsl24(TyS); -+ test_bic_8h_0x5A_lsl0(TyH); -+ test_bic_8h_0xA5_lsl8(TyH); -+ test_bic_4h_0x5A_lsl0(TyH); -+ test_bic_4h_0xA5_lsl8(TyH); -+ test_bic_4s_0x5A_lsl0(TyS); -+ test_bic_4s_0x6B_lsl8(TyS); -+ test_bic_4s_0x49_lsl16(TyS); -+ test_bic_4s_0x3D_lsl24(TyS); -+ test_bic_2s_0x5A_lsl0(TyS); -+ test_bic_2s_0x6B_lsl8(TyS); -+ test_bic_2s_0x49_lsl16(TyS); -+ test_bic_2s_0x3D_lsl24(TyS); -+ -+ // bif 16b,8b (vector) (bit insert if false) -+ // bit 16b,8b (vector) (bit insert if true) -+ // bsl 16b,8b (vector) (bit select) -+ // eor 16b,8b (vector) -+ test_bif_16b_16b_16b(TyB); -+ test_bif_8b_8b_8b(TyB); -+ test_bit_16b_16b_16b(TyB); -+ test_bit_8b_8b_8b(TyB); -+ test_bsl_16b_16b_16b(TyB); -+ test_bsl_8b_8b_8b(TyB); -+ test_eor_16b_16b_16b(TyB); -+ test_eor_8b_8b_8b(TyB); -+ -+ // cls 4s,2s,8h,4h,16b,8b (count leading sign bits) -+ // clz 4s,2s,8h,4h,16b,8b (count leading zero bits) -+ test_cls_4s_4s(TyS); -+ test_cls_2s_2s(TyS); -+ test_cls_8h_8h(TyH); -+ test_cls_4h_4h(TyH); -+ test_cls_16b_16b(TyB); -+ test_cls_8b_8b(TyB); -+ test_clz_4s_4s(TyS); -+ test_clz_2s_2s(TyS); -+ test_clz_8h_8h(TyH); -+ test_clz_4h_4h(TyH); -+ test_clz_16b_16b(TyB); -+ test_clz_8b_8b(TyB); -+ -+ // cmeq d -+ // cmge d -+ // cmgt d -+ // cmhi d -+ // cmhs d -+ // cmtst d -+ test_cmeq_d_d_d(TyD); -+ test_cmge_d_d_d(TyD); -+ test_cmgt_d_d_d(TyD); -+ test_cmhi_d_d_d(TyD); -+ test_cmhs_d_d_d(TyD); -+ test_cmtst_d_d_d(TyD); -+ -+ // cmeq 2d,4s,2s,8h,4h,16b,8b -+ // cmge 2d,4s,2s,8h,4h,16b,8b -+ // cmgt 2d,4s,2s,8h,4h,16b,8b -+ // cmhi 2d,4s,2s,8h,4h,16b,8b -+ // cmhs 2d,4s,2s,8h,4h,16b,8b -+ // cmtst 2d,4s,2s,8h,4h,16b,8b -+ test_cmeq_2d_2d_2d(TyD); -+ test_cmeq_4s_4s_4s(TyS); -+ test_cmeq_2s_2s_2s(TyS); -+ test_cmeq_8h_8h_8h(TyH); -+ test_cmeq_4h_4h_4h(TyH); -+ test_cmeq_16b_16b_16b(TyB); -+ test_cmeq_8b_8b_8b(TyB); -+ test_cmge_2d_2d_2d(TyD); -+ test_cmge_4s_4s_4s(TyS); -+ test_cmge_2s_2s_2s(TyS); -+ test_cmge_8h_8h_8h(TyH); -+ test_cmge_4h_4h_4h(TyH); -+ test_cmge_16b_16b_16b(TyB); -+ test_cmge_8b_8b_8b(TyB); -+ test_cmgt_2d_2d_2d(TyD); -+ test_cmgt_4s_4s_4s(TyS); -+ test_cmgt_2s_2s_2s(TyS); -+ test_cmgt_8h_8h_8h(TyH); -+ test_cmgt_4h_4h_4h(TyH); -+ test_cmgt_16b_16b_16b(TyB); -+ test_cmgt_8b_8b_8b(TyB); -+ test_cmhi_2d_2d_2d(TyD); -+ test_cmhi_4s_4s_4s(TyS); -+ test_cmhi_2s_2s_2s(TyS); -+ test_cmhi_8h_8h_8h(TyH); -+ test_cmhi_4h_4h_4h(TyH); -+ test_cmhi_16b_16b_16b(TyB); -+ test_cmhi_8b_8b_8b(TyB); -+ test_cmhs_2d_2d_2d(TyD); -+ test_cmhs_4s_4s_4s(TyS); -+ test_cmhs_2s_2s_2s(TyS); -+ test_cmhs_8h_8h_8h(TyH); -+ test_cmhs_4h_4h_4h(TyH); -+ test_cmhs_16b_16b_16b(TyB); -+ test_cmhs_8b_8b_8b(TyB); -+ test_cmtst_2d_2d_2d(TyD); -+ test_cmtst_4s_4s_4s(TyS); -+ test_cmtst_2s_2s_2s(TyS); -+ test_cmtst_8h_8h_8h(TyH); -+ test_cmtst_4h_4h_4h(TyH); -+ test_cmtst_16b_16b_16b(TyB); -+ test_cmtst_8b_8b_8b(TyB); -+ -+ // cmeq_z d -+ // cmge_z d -+ // cmgt_z d -+ // cmle_z d -+ // cmlt_z d -+ test_cmeq_zero_d_d(TyD); -+ test_cmge_zero_d_d(TyD); -+ test_cmgt_zero_d_d(TyD); -+ test_cmle_zero_d_d(TyD); -+ test_cmlt_zero_d_d(TyD); -+ -+ // cmeq_z 2d,4s,2s,8h,4h,16b,8b -+ // cmge_z 2d,4s,2s,8h,4h,16b,8b -+ // cmgt_z 2d,4s,2s,8h,4h,16b,8b -+ // cmle_z 2d,4s,2s,8h,4h,16b,8b -+ // cmlt_z 2d,4s,2s,8h,4h,16b,8b -+ test_cmeq_zero_2d_2d(TyD); -+ test_cmeq_zero_4s_4s(TyS); -+ test_cmeq_zero_2s_2s(TyS); -+ test_cmeq_zero_8h_8h(TyH); -+ test_cmeq_zero_4h_4h(TyH); -+ test_cmeq_zero_16b_16b(TyB); -+ test_cmeq_zero_8b_8b(TyB); -+ test_cmge_zero_2d_2d(TyD); -+ test_cmge_zero_4s_4s(TyS); -+ test_cmge_zero_2s_2s(TyS); -+ test_cmge_zero_8h_8h(TyH); -+ test_cmge_zero_4h_4h(TyH); -+ test_cmge_zero_16b_16b(TyB); -+ test_cmge_zero_8b_8b(TyB); -+ test_cmgt_zero_2d_2d(TyD); -+ test_cmgt_zero_4s_4s(TyS); -+ test_cmgt_zero_2s_2s(TyS); -+ test_cmgt_zero_8h_8h(TyH); -+ test_cmgt_zero_4h_4h(TyH); -+ test_cmgt_zero_16b_16b(TyB); -+ test_cmgt_zero_8b_8b(TyB); -+ test_cmle_zero_2d_2d(TyD); -+ test_cmle_zero_4s_4s(TyS); -+ test_cmle_zero_2s_2s(TyS); -+ test_cmle_zero_8h_8h(TyH); -+ test_cmle_zero_4h_4h(TyH); -+ test_cmle_zero_16b_16b(TyB); -+ test_cmle_zero_8b_8b(TyB); -+ test_cmlt_zero_2d_2d(TyD); -+ test_cmlt_zero_4s_4s(TyS); -+ test_cmlt_zero_2s_2s(TyS); -+ test_cmlt_zero_8h_8h(TyH); -+ test_cmlt_zero_4h_4h(TyH); -+ test_cmlt_zero_16b_16b(TyB); -+ test_cmlt_zero_8b_8b(TyB); -+ -+ // cnt 16b,8b (population count per byte) -+ test_cnt_16b_16b(TyB); -+ test_cnt_8b_8b(TyB); -+ -+ // dup d,s,h,b (vec elem to scalar) -+ test_dup_d_d0(TyD); -+ test_dup_d_d1(TyD); -+ test_dup_s_s0(TyS); -+ test_dup_s_s3(TyS); -+ test_dup_h_h0(TyH); -+ test_dup_h_h6(TyH); -+ test_dup_b_b0(TyB); -+ test_dup_b_b13(TyB); -+ -+ // dup 2d,4s,2s,8h,4h,16b,8b (vec elem to vector) -+ test_dup_2d_d0(TyD); -+ test_dup_2d_d1(TyD); -+ test_dup_4s_s0(TyS); -+ test_dup_4s_s3(TyS); -+ test_dup_2s_s0(TyS); -+ test_dup_2s_s2(TyS); -+ test_dup_8h_h0(TyH); -+ test_dup_8h_h6(TyH); -+ test_dup_4h_h1(TyH); -+ test_dup_4h_h5(TyH); -+ test_dup_16b_b2(TyB); -+ test_dup_16b_b12(TyB); -+ test_dup_8b_b3(TyB); -+ test_dup_8b_b13(TyB); -+ -+ // dup 2d,4s,2s,8h,4h,16b,8b (general reg to vector) -+ test_dup_2d_x(TyD); -+ test_dup_4s_w(TyS); -+ test_dup_2s_w(TyS); -+ test_dup_8h_w(TyH); -+ test_dup_4h_w(TyH); -+ test_dup_16b_w(TyB); -+ test_dup_8b_w(TyB); -+ -+ // ext 16b,8b,#imm4 (concat 2 vectors, then slice) -+ test_ext_16b_16b_16b_0x0(TyB); -+ test_ext_16b_16b_16b_0x7(TyB); -+ test_ext_16b_16b_16b_0x8(TyB); -+ test_ext_16b_16b_16b_0x9(TyB); -+ test_ext_16b_16b_16b_0xF(TyB); -+ test_ext_8b_8b_8b_0x0(TyB); -+ test_ext_8b_8b_8b_0x1(TyB); -+ test_ext_8b_8b_8b_0x6(TyB); -+ test_ext_8b_8b_8b_0x7(TyB); -+ -+ // ins d[]_d[],s[]_s[],h[]_h[],b[]_b[] -+ test_ins_d0_d0(TyD); -+ test_ins_d0_d1(TyD); -+ test_ins_d1_d0(TyD); -+ test_ins_d1_d1(TyD); -+ test_ins_s0_s2(TyS); -+ test_ins_s3_s0(TyS); -+ test_ins_s2_s1(TyS); -+ test_ins_s1_s3(TyS); -+ test_ins_h0_h6(TyH); -+ test_ins_h7_h0(TyH); -+ test_ins_h6_h1(TyH); -+ test_ins_h1_h7(TyH); -+ test_ins_b0_b14(TyB); -+ test_ins_b15_b8(TyB); -+ test_ins_b13_b9(TyB); -+ test_ins_b5_b12(TyB); -+ -+ // ins d[]_x, s[]_w, h[]_w, b[]_w -+ test_INS_general(); -+ -+ // mla 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[] -+ // mls 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[] -+ // mul 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[] -+ test_mla_4s_4s_s0(TyS); -+ test_mla_4s_4s_s3(TyS); -+ test_mla_2s_2s_s0(TyS); -+ test_mla_2s_2s_s3(TyS); -+ test_mla_8h_8h_h1(TyH); -+ test_mla_8h_8h_h5(TyH); -+ test_mla_4h_4h_h2(TyH); -+ test_mla_4h_4h_h7(TyH); -+ test_mls_4s_4s_s0(TyS); -+ test_mls_4s_4s_s3(TyS); -+ test_mls_2s_2s_s0(TyS); -+ test_mls_2s_2s_s3(TyS); -+ test_mls_8h_8h_h1(TyH); -+ test_mls_8h_8h_h5(TyH); -+ test_mls_4h_4h_h2(TyH); -+ test_mls_4h_4h_h7(TyH); -+ test_mul_4s_4s_s0(TyS); -+ test_mul_4s_4s_s3(TyS); -+ test_mul_2s_2s_s0(TyS); -+ test_mul_2s_2s_s3(TyS); -+ test_mul_8h_8h_h1(TyH); -+ test_mul_8h_8h_h5(TyH); -+ test_mul_4h_4h_h2(TyH); -+ test_mul_4h_4h_h7(TyH); -+ -+ // mla 4s,2s,8h,4h,16b,8b -+ // mls 4s,2s,8h,4h,16b,8b -+ // mul 4s,2s,8h,4h,16b,8b -+ test_mla_4s_4s_4s(TyS); -+ test_mla_2s_2s_2s(TyS); -+ test_mla_8h_8h_8h(TyH); -+ test_mla_4h_4h_4h(TyH); -+ test_mla_16b_16b_16b(TyB); -+ test_mla_8b_8b_8b(TyB); -+ test_mls_4s_4s_4s(TyS); -+ test_mls_2s_2s_2s(TyS); -+ test_mls_8h_8h_8h(TyH); -+ test_mls_4h_4h_4h(TyH); -+ test_mls_16b_16b_16b(TyB); -+ test_mls_8b_8b_8b(TyB); -+ test_mul_4s_4s_4s(TyS); -+ test_mul_2s_2s_2s(TyS); -+ test_mul_8h_8h_8h(TyH); -+ test_mul_4h_4h_4h(TyH); -+ test_mul_16b_16b_16b(TyB); -+ test_mul_8b_8b_8b(TyB); -+ -+ // Some of these movi and mvni cases are similar to orr and bic -+ // cases with immediates. Maybe they should be moved together. -+ // movi 16b,8b #imm8, LSL #0 -+ test_movi_16b_0x9C_lsl0(TyB); -+ test_movi_8b_0x8B_lsl0(TyB); -+ -+ // movi 8h,4h #imm8, LSL #0 or 8 -+ // mvni 8h,4h #imm8, LSL #0 or 8 -+ test_movi_8h_0x5A_lsl0(TyH); -+ test_movi_8h_0xA5_lsl8(TyH); -+ test_movi_4h_0x5A_lsl0(TyH); -+ test_movi_4h_0xA5_lsl8(TyH); -+ test_mvni_8h_0x5A_lsl0(TyH); -+ test_mvni_8h_0xA5_lsl8(TyH); -+ test_mvni_4h_0x5A_lsl0(TyH); -+ test_mvni_4h_0xA5_lsl8(TyH); -+ -+ // movi 4s,2s #imm8, LSL #0, 8, 16, 24 -+ // mvni 4s,2s #imm8, LSL #0, 8, 16, 24 -+ test_movi_4s_0x5A_lsl0(TyS); -+ test_movi_4s_0x6B_lsl8(TyS); -+ test_movi_4s_0x49_lsl16(TyS); -+ test_movi_4s_0x3D_lsl24(TyS); -+ test_movi_2s_0x5A_lsl0(TyS); -+ test_movi_2s_0x6B_lsl8(TyS); -+ test_movi_2s_0x49_lsl16(TyS); -+ test_movi_2s_0x3D_lsl24(TyS); -+ test_mvni_4s_0x5A_lsl0(TyS); -+ test_mvni_4s_0x6B_lsl8(TyS); -+ test_mvni_4s_0x49_lsl16(TyS); -+ test_mvni_4s_0x3D_lsl24(TyS); -+ test_mvni_2s_0x5A_lsl0(TyS); -+ test_mvni_2s_0x6B_lsl8(TyS); -+ test_mvni_2s_0x49_lsl16(TyS); -+ test_mvni_2s_0x3D_lsl24(TyS); -+ -+ // movi 4s,2s #imm8, MSL #8 or 16 -+ // mvni 4s,2s #imm8, MSL #8 or 16 -+ test_movi_4s_0x6B_msl8(TyS); -+ test_movi_4s_0x94_msl16(TyS); -+ test_movi_2s_0x7A_msl8(TyS); -+ test_movi_2s_0xA5_msl16(TyS); -+ test_mvni_4s_0x6B_msl8(TyS); -+ test_mvni_4s_0x94_msl16(TyS); -+ test_mvni_2s_0x7A_msl8(TyS); -+ test_mvni_2s_0xA5_msl16(TyS); -+ -+ // movi d, #imm64 -+ // movi 2d, #imm64 -+ test_movi_d_0xA5(TyD); -+ test_movi_2d_0xB4(TyD); -+ -+ // not 16b,8b -+ test_not_16b_16b(TyB); -+ test_not_8b_8b(TyB); -+ -+ // pmul 16b,8b -+ test_pmul_16b_16b_16b(TyB); -+ test_pmul_8b_8b_8b(TyB); -+ -+ // pmull{2} 8h_8b_8b,8h_16b_16b,1q_1d_1d,1q_2d_2d -+ test_pmull_8h_8b_8b(TyB); -+ test_pmull2_8h_16b_16b(TyB); -+ //test_pmull_1q_1d_1d(TyD); -+ //test_pmull_1q_2d_2d(TyD); -+ -+ // rbit 16b,8b -+ // rev16 16b,8b -+ // rev32 16b,8b,8h,4h -+ // rev64 16b,8b,8h,4h,4s,2s -+ test_rbit_16b_16b(TyB); -+ test_rbit_8b_8b(TyB); -+ test_rev16_16b_16b(TyB); -+ test_rev16_8b_8b(TyB); -+ test_rev32_16b_16b(TyB); -+ test_rev32_8b_8b(TyB); -+ test_rev32_8h_8h(TyH); -+ test_rev32_4h_4h(TyH); -+ test_rev64_16b_16b(TyB); -+ test_rev64_8b_8b(TyB); -+ test_rev64_8h_8h(TyH); -+ test_rev64_4h_4h(TyH); -+ test_rev64_4s_4s(TyS); -+ test_rev64_2s_2s(TyS); -+ -+ // saba 16b,8b,8h,4h,4s,2s -+ // uaba 16b,8b,8h,4h,4s,2s -+ test_saba_4s_4s_4s(TyS); -+ test_saba_2s_2s_2s(TyS); -+ test_saba_8h_8h_8h(TyH); -+ test_saba_4h_4h_4h(TyH); -+ test_saba_16b_16b_16b(TyB); -+ test_saba_8b_8b_8b(TyB); -+ test_uaba_4s_4s_4s(TyS); -+ test_uaba_2s_2s_2s(TyS); -+ test_uaba_8h_8h_8h(TyH); -+ test_uaba_4h_4h_4h(TyH); -+ test_uaba_16b_16b_16b(TyB); -+ test_uaba_8b_8b_8b(TyB); -+ -+ // sabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // uabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ test_sabal_2d_2s_2s(TyS); -+ test_sabal2_2d_4s_4s(TyS); -+ test_sabal_4s_4h_4h(TyH); -+ test_sabal2_4s_8h_8h(TyH); -+ test_sabal_8h_8b_8b(TyB); -+ test_sabal2_8h_16b_16b(TyB); -+ test_uabal_2d_2s_2s(TyS); -+ test_uabal2_2d_4s_4s(TyS); -+ test_uabal_4s_4h_4h(TyH); -+ test_uabal2_4s_8h_8h(TyH); -+ test_uabal_8h_8b_8b(TyB); -+ test_uabal2_8h_16b_16b(TyB); -+ -+ // sabd 16b,8b,8h,4h,4s,2s -+ // uabd 16b,8b,8h,4h,4s,2s -+ test_sabd_4s_4s_4s(TyS); -+ test_sabd_2s_2s_2s(TyS); -+ test_sabd_8h_8h_8h(TyH); -+ test_sabd_4h_4h_4h(TyH); -+ test_sabd_16b_16b_16b(TyB); -+ test_sabd_8b_8b_8b(TyB); -+ test_uabd_4s_4s_4s(TyS); -+ test_uabd_2s_2s_2s(TyS); -+ test_uabd_8h_8h_8h(TyH); -+ test_uabd_4h_4h_4h(TyH); -+ test_uabd_16b_16b_16b(TyB); -+ test_uabd_8b_8b_8b(TyB); -+ -+ // sabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // uabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ test_sabdl_2d_2s_2s(TyS); -+ test_sabdl2_2d_4s_4s(TyS); -+ test_sabdl_4s_4h_4h(TyH); -+ test_sabdl2_4s_8h_8h(TyH); -+ test_sabdl_8h_8b_8b(TyB); -+ test_sabdl2_8h_16b_16b(TyB); -+ test_uabdl_2d_2s_2s(TyS); -+ test_uabdl2_2d_4s_4s(TyS); -+ test_uabdl_4s_4h_4h(TyH); -+ test_uabdl2_4s_8h_8h(TyH); -+ test_uabdl_8h_8b_8b(TyB); -+ test_uabdl2_8h_16b_16b(TyB); -+ -+ // sadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s -+ // uadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s -+ test_sadalp_1d_2s(TyS); -+ test_sadalp_2d_4s(TyS); -+ test_sadalp_2s_4h(TyH); -+ test_sadalp_4s_8h(TyH); -+ test_sadalp_4h_8b(TyB); -+ test_sadalp_8h_16b(TyB); -+ test_uadalp_1d_2s(TyS); -+ test_uadalp_2d_4s(TyS); -+ test_uadalp_2s_4h(TyH); -+ test_uadalp_4s_8h(TyH); -+ test_uadalp_4h_8b(TyB); -+ test_uadalp_8h_16b(TyB); -+ -+ // saddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // uaddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // ssubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // usubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ test_saddl_2d_2s_2s(TyS); -+ test_saddl2_2d_4s_4s(TyS); -+ test_saddl_4s_4h_4h(TyH); -+ test_saddl2_4s_8h_8h(TyH); -+ test_saddl_8h_8b_8b(TyB); -+ test_saddl2_8h_16b_16b(TyB); -+ test_uaddl_2d_2s_2s(TyS); -+ test_uaddl2_2d_4s_4s(TyS); -+ test_uaddl_4s_4h_4h(TyH); -+ test_uaddl2_4s_8h_8h(TyH); -+ test_uaddl_8h_8b_8b(TyB); -+ test_uaddl2_8h_16b_16b(TyB); -+ test_ssubl_2d_2s_2s(TyS); -+ test_ssubl2_2d_4s_4s(TyS); -+ test_ssubl_4s_4h_4h(TyH); -+ test_ssubl2_4s_8h_8h(TyH); -+ test_ssubl_8h_8b_8b(TyB); -+ test_ssubl2_8h_16b_16b(TyB); -+ test_usubl_2d_2s_2s(TyS); -+ test_usubl2_2d_4s_4s(TyS); -+ test_usubl_4s_4h_4h(TyH); -+ test_usubl2_4s_8h_8h(TyH); -+ test_usubl_8h_8b_8b(TyB); -+ test_usubl2_8h_16b_16b(TyB); -+ -+ // saddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s -+ // uaddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s -+ test_saddlp_1d_2s(TyS); -+ test_saddlp_2d_4s(TyS); -+ test_saddlp_2s_4h(TyH); -+ test_saddlp_4s_8h(TyH); -+ test_saddlp_4h_8b(TyB); -+ test_saddlp_8h_16b(TyB); -+ test_uaddlp_1d_2s(TyS); -+ test_uaddlp_2d_4s(TyS); -+ test_uaddlp_2s_4h(TyH); -+ test_uaddlp_4s_8h(TyH); -+ test_uaddlp_4h_8b(TyB); -+ test_uaddlp_8h_16b(TyB); -+ -+ // saddlv h_16b/8b, s_8h/4h, d_4s -+ // uaddlv h_16b/8b, s_8h/4h, d_4s -+ test_saddlv_h_16b(TyB); -+ test_saddlv_h_8b(TyB); -+ test_saddlv_s_8h(TyH); -+ test_saddlv_s_4h(TyH); -+ test_saddlv_d_4s(TyH); -+ test_uaddlv_h_16b(TyB); -+ test_uaddlv_h_8b(TyB); -+ test_uaddlv_s_8h(TyH); -+ test_uaddlv_s_4h(TyH); -+ test_uaddlv_d_4s(TyH); -+ -+ // saddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s -+ // uaddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s -+ // ssubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s -+ // usubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s -+ test_saddw2_8h_8h_16b(TyB); -+ test_saddw_8h_8h_8b(TyB); -+ test_saddw2_4s_4s_8h(TyH); -+ test_saddw_4s_4s_4h(TyH); -+ test_saddw2_2d_2d_4s(TyS); -+ test_saddw_2d_2d_2s(TyS); -+ test_uaddw2_8h_8h_16b(TyB); -+ test_uaddw_8h_8h_8b(TyB); -+ test_uaddw2_4s_4s_8h(TyH); -+ test_uaddw_4s_4s_4h(TyH); -+ test_uaddw2_2d_2d_4s(TyS); -+ test_uaddw_2d_2d_2s(TyS); -+ test_ssubw2_8h_8h_16b(TyB); -+ test_ssubw_8h_8h_8b(TyB); -+ test_ssubw2_4s_4s_8h(TyH); -+ test_ssubw_4s_4s_4h(TyH); -+ test_ssubw2_2d_2d_4s(TyS); -+ test_ssubw_2d_2d_2s(TyS); -+ test_usubw2_8h_8h_16b(TyB); -+ test_usubw_8h_8h_8b(TyB); -+ test_usubw2_4s_4s_8h(TyH); -+ test_usubw_4s_4s_4h(TyH); -+ test_usubw2_2d_2d_4s(TyS); -+ test_usubw_2d_2d_2s(TyS); -+ -+ // shadd 16b,8b,8h,4h,4s,2s -+ // uhadd 16b,8b,8h,4h,4s,2s -+ // shsub 16b,8b,8h,4h,4s,2s -+ // uhsub 16b,8b,8h,4h,4s,2s -+ test_shadd_4s_4s_4s(TyS); -+ test_shadd_2s_2s_2s(TyS); -+ test_shadd_8h_8h_8h(TyH); -+ test_shadd_4h_4h_4h(TyH); -+ test_shadd_16b_16b_16b(TyB); -+ test_shadd_8b_8b_8b(TyB); -+ test_uhadd_4s_4s_4s(TyS); -+ test_uhadd_2s_2s_2s(TyS); -+ test_uhadd_8h_8h_8h(TyH); -+ test_uhadd_4h_4h_4h(TyH); -+ test_uhadd_16b_16b_16b(TyB); -+ test_uhadd_8b_8b_8b(TyB); -+ test_shsub_4s_4s_4s(TyS); -+ test_shsub_2s_2s_2s(TyS); -+ test_shsub_8h_8h_8h(TyH); -+ test_shsub_4h_4h_4h(TyH); -+ test_shsub_16b_16b_16b(TyB); -+ test_shsub_8b_8b_8b(TyB); -+ test_uhsub_4s_4s_4s(TyS); -+ test_uhsub_2s_2s_2s(TyS); -+ test_uhsub_8h_8h_8h(TyH); -+ test_uhsub_4h_4h_4h(TyH); -+ test_uhsub_16b_16b_16b(TyB); -+ test_uhsub_8b_8b_8b(TyB); -+ -+ // shll{2} 8h_8b/16b_#8, 4s_4h/8h_#16, 2d_2s/4s_#32 -+ test_shll_8h_8b_8(TyB); -+ test_shll2_8h_16b_8(TyB); -+ test_shll_4s_4h_16(TyH); -+ test_shll2_4s_8h_16(TyH); -+ test_shll_2d_2s_32(TyS); -+ test_shll2_2d_4s_32(TyS); -+ -+ // shrn{2} 2s/4s_2d, 8h/4h_4s, 8b/16b_8h, #imm in 1 .. elem_bits -+ // rshrn{2} 2s/4s_2d, 8h/4h_4s, 8b/16b_8h, #imm in 1 .. elem_bits -+ test_shrn_2s_2d_1(TyD); -+ test_shrn_2s_2d_32(TyD); -+ test_shrn2_4s_2d_1(TyD); -+ test_shrn2_4s_2d_32(TyD); -+ test_shrn_4h_4s_1(TyS); -+ test_shrn_4h_4s_16(TyS); -+ test_shrn2_8h_4s_1(TyS); -+ test_shrn2_8h_4s_16(TyS); -+ test_shrn_8b_8h_1(TyH); -+ test_shrn_8b_8h_8(TyH); -+ test_shrn2_16b_8h_1(TyH); -+ test_shrn2_16b_8h_8(TyH); -+ test_rshrn_2s_2d_1(TyD); -+ test_rshrn_2s_2d_32(TyD); -+ test_rshrn2_4s_2d_1(TyD); -+ test_rshrn2_4s_2d_32(TyD); -+ test_rshrn_4h_4s_1(TyS); -+ test_rshrn_4h_4s_16(TyS); -+ test_rshrn2_8h_4s_1(TyS); -+ test_rshrn2_8h_4s_16(TyS); -+ test_rshrn_8b_8h_1(TyH); -+ test_rshrn_8b_8h_8(TyH); -+ test_rshrn2_16b_8h_1(TyH); -+ test_rshrn2_16b_8h_8(TyH); -+ -+ // sli d_#imm -+ // sri d_#imm -+ test_sli_d_d_0(TyD); -+ test_sli_d_d_32(TyD); -+ test_sli_d_d_63(TyD); -+ test_sri_d_d_1(TyD); -+ test_sri_d_d_33(TyD); -+ test_sri_d_d_64(TyD); -+ -+ // sli 2d,4s,2s,8h,4h,16b,8b _#imm -+ // sri 2d,4s,2s,8h,4h,16b,8b _#imm -+ test_sli_2d_2d_0(TyD); -+ test_sli_2d_2d_32(TyD); -+ test_sli_2d_2d_63(TyD); -+ test_sli_4s_4s_0(TyS); -+ test_sli_4s_4s_16(TyS); -+ test_sli_4s_4s_31(TyS); -+ test_sli_2s_2s_0(TyS); -+ test_sli_2s_2s_16(TyS); -+ test_sli_2s_2s_31(TyS); -+ test_sli_8h_8h_0(TyH); -+ test_sli_8h_8h_8(TyH); -+ test_sli_8h_8h_15(TyH); -+ test_sli_4h_4h_0(TyH); -+ test_sli_4h_4h_8(TyH); -+ test_sli_4h_4h_15(TyH); -+ test_sli_16b_16b_0(TyB); -+ test_sli_16b_16b_3(TyB); -+ test_sli_16b_16b_7(TyB); -+ test_sli_8b_8b_0(TyB); -+ test_sli_8b_8b_3(TyB); -+ test_sli_8b_8b_7(TyB); -+ test_sri_2d_2d_1(TyD); -+ test_sri_2d_2d_33(TyD); -+ test_sri_2d_2d_64(TyD); -+ test_sri_4s_4s_1(TyS); -+ test_sri_4s_4s_17(TyS); -+ test_sri_4s_4s_32(TyS); -+ test_sri_2s_2s_1(TyS); -+ test_sri_2s_2s_17(TyS); -+ test_sri_2s_2s_32(TyS); -+ test_sri_8h_8h_1(TyH); -+ test_sri_8h_8h_8(TyH); -+ test_sri_8h_8h_16(TyH); -+ test_sri_4h_4h_1(TyH); -+ test_sri_4h_4h_8(TyH); -+ test_sri_4h_4h_16(TyH); -+ test_sri_16b_16b_1(TyB); -+ test_sri_16b_16b_4(TyB); -+ test_sri_16b_16b_8(TyB); -+ test_sri_8b_8b_1(TyB); -+ test_sri_8b_8b_4(TyB); -+ test_sri_8b_8b_8(TyB); -+ -+ // smax 4s,2s,8h,4h,16b,8b -+ // umax 4s,2s,8h,4h,16b,8b -+ // smin 4s,2s,8h,4h,16b,8b -+ // umin 4s,2s,8h,4h,16b,8b -+ test_smax_4s_4s_4s(TyS); -+ test_smax_2s_2s_2s(TyS); -+ test_smax_8h_8h_8h(TyH); -+ test_smax_4h_4h_4h(TyH); -+ test_smax_16b_16b_16b(TyB); -+ test_smax_8b_8b_8b(TyB); -+ test_umax_4s_4s_4s(TyS); -+ test_umax_2s_2s_2s(TyS); -+ test_umax_8h_8h_8h(TyH); -+ test_umax_4h_4h_4h(TyH); -+ test_umax_16b_16b_16b(TyB); -+ test_umax_8b_8b_8b(TyB); -+ test_smin_4s_4s_4s(TyS); -+ test_smin_2s_2s_2s(TyS); -+ test_smin_8h_8h_8h(TyH); -+ test_smin_4h_4h_4h(TyH); -+ test_smin_16b_16b_16b(TyB); -+ test_smin_8b_8b_8b(TyB); -+ test_umin_4s_4s_4s(TyS); -+ test_umin_2s_2s_2s(TyS); -+ test_umin_8h_8h_8h(TyH); -+ test_umin_4h_4h_4h(TyH); -+ test_umin_16b_16b_16b(TyB); -+ test_umin_8b_8b_8b(TyB); -+ -+ // smaxp 4s,2s,8h,4h,16b,8b -+ // umaxp 4s,2s,8h,4h,16b,8b -+ // sminp 4s,2s,8h,4h,16b,8b -+ // uminp 4s,2s,8h,4h,16b,8b -+ test_smaxp_4s_4s_4s(TyS); -+ test_smaxp_2s_2s_2s(TyS); -+ test_smaxp_8h_8h_8h(TyH); -+ test_smaxp_4h_4h_4h(TyH); -+ test_smaxp_16b_16b_16b(TyB); -+ test_smaxp_8b_8b_8b(TyB); -+ test_umaxp_4s_4s_4s(TyS); -+ test_umaxp_2s_2s_2s(TyS); -+ test_umaxp_8h_8h_8h(TyH); -+ test_umaxp_4h_4h_4h(TyH); -+ test_umaxp_16b_16b_16b(TyB); -+ test_umaxp_8b_8b_8b(TyB); -+ test_sminp_4s_4s_4s(TyS); -+ test_sminp_2s_2s_2s(TyS); -+ test_sminp_8h_8h_8h(TyH); -+ test_sminp_4h_4h_4h(TyH); -+ test_sminp_16b_16b_16b(TyB); -+ test_sminp_8b_8b_8b(TyB); -+ test_uminp_4s_4s_4s(TyS); -+ test_uminp_2s_2s_2s(TyS); -+ test_uminp_8h_8h_8h(TyH); -+ test_uminp_4h_4h_4h(TyH); -+ test_uminp_16b_16b_16b(TyB); -+ test_uminp_8b_8b_8b(TyB); -+ -+ // smaxv s_4s,h_8h,h_4h,b_16b,b_8b -+ // umaxv s_4s,h_8h,h_4h,b_16b,b_8b -+ // sminv s_4s,h_8h,h_4h,b_16b,b_8b -+ // uminv s_4s,h_8h,h_4h,b_16b,b_8b -+ test_SMAXV(); -+ test_UMAXV(); -+ test_SMINV(); -+ test_UMINV(); -+ -+ // smlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[] -+ // umlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[] -+ // smlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[] -+ // umlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[] -+ // smull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[] -+ // umull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[] -+ test_smlal_2d_2s_s0(TyS); -+ test_smlal_2d_2s_s3(TyS); -+ test_smlal2_2d_4s_s1(TyS); -+ test_smlal2_2d_4s_s2(TyS); -+ test_smlal_4s_4h_h0(TyH); -+ test_smlal_4s_4h_h7(TyH); -+ test_smlal2_4s_8h_h1(TyH); -+ test_smlal2_4s_8h_h4(TyH); -+ test_umlal_2d_2s_s0(TyS); -+ test_umlal_2d_2s_s3(TyS); -+ test_umlal2_2d_4s_s1(TyS); -+ test_umlal2_2d_4s_s2(TyS); -+ test_umlal_4s_4h_h0(TyH); -+ test_umlal_4s_4h_h7(TyH); -+ test_umlal2_4s_8h_h1(TyH); -+ test_umlal2_4s_8h_h4(TyH); -+ test_smlsl_2d_2s_s0(TyS); -+ test_smlsl_2d_2s_s3(TyS); -+ test_smlsl2_2d_4s_s1(TyS); -+ test_smlsl2_2d_4s_s2(TyS); -+ test_smlsl_4s_4h_h0(TyH); -+ test_smlsl_4s_4h_h7(TyH); -+ test_smlsl2_4s_8h_h1(TyH); -+ test_smlsl2_4s_8h_h4(TyH); -+ test_umlsl_2d_2s_s0(TyS); -+ test_umlsl_2d_2s_s3(TyS); -+ test_umlsl2_2d_4s_s1(TyS); -+ test_umlsl2_2d_4s_s2(TyS); -+ test_umlsl_4s_4h_h0(TyH); -+ test_umlsl_4s_4h_h7(TyH); -+ test_umlsl2_4s_8h_h1(TyH); -+ test_umlsl2_4s_8h_h4(TyH); -+ test_smull_2d_2s_s0(TyS); -+ test_smull_2d_2s_s3(TyS); -+ test_smull2_2d_4s_s1(TyS); -+ test_smull2_2d_4s_s2(TyS); -+ test_smull_4s_4h_h0(TyH); -+ test_smull_4s_4h_h7(TyH); -+ test_smull2_4s_8h_h1(TyH); -+ test_smull2_4s_8h_h4(TyH); -+ test_umull_2d_2s_s0(TyS); -+ test_umull_2d_2s_s3(TyS); -+ test_umull2_2d_4s_s1(TyS); -+ test_umull2_2d_4s_s2(TyS); -+ test_umull_4s_4h_h0(TyH); -+ test_umull_4s_4h_h7(TyH); -+ test_umull2_4s_8h_h1(TyH); -+ test_umull2_4s_8h_h4(TyH); -+ -+ // smlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // umlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // smlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // umlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // smull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ // umull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b) -+ test_smlal_2d_2s_2s(TyS); -+ test_smlal2_2d_4s_4s(TyS); -+ test_smlal_4s_4h_4h(TyH); -+ test_smlal2_4s_8h_8h(TyH); -+ test_smlal_8h_8b_8b(TyB); -+ test_smlal2_8h_16b_16b(TyB); -+ test_umlal_2d_2s_2s(TyS); -+ test_umlal2_2d_4s_4s(TyS); -+ test_umlal_4s_4h_4h(TyH); -+ test_umlal2_4s_8h_8h(TyH); -+ test_umlal_8h_8b_8b(TyB); -+ test_umlal2_8h_16b_16b(TyB); -+ test_smlsl_2d_2s_2s(TyS); -+ test_smlsl2_2d_4s_4s(TyS); -+ test_smlsl_4s_4h_4h(TyH); -+ test_smlsl2_4s_8h_8h(TyH); -+ test_smlsl_8h_8b_8b(TyB); -+ test_smlsl2_8h_16b_16b(TyB); -+ test_umlsl_2d_2s_2s(TyS); -+ test_umlsl2_2d_4s_4s(TyS); -+ test_umlsl_4s_4h_4h(TyH); -+ test_umlsl2_4s_8h_8h(TyH); -+ test_umlsl_8h_8b_8b(TyB); -+ test_umlsl2_8h_16b_16b(TyB); -+ test_smull_2d_2s_2s(TyS); -+ test_smull2_2d_4s_4s(TyS); -+ test_smull_4s_4h_4h(TyH); -+ test_smull2_4s_8h_8h(TyH); -+ test_smull_8h_8b_8b(TyB); -+ test_smull2_8h_16b_16b(TyB); -+ test_umull_2d_2s_2s(TyS); -+ test_umull2_2d_4s_4s(TyS); -+ test_umull_4s_4h_4h(TyH); -+ test_umull2_4s_8h_8h(TyH); -+ test_umull_8h_8b_8b(TyB); -+ test_umull2_8h_16b_16b(TyB); -+ -+ // smov w_b[], w_h[], x_b[], x_h[], x_s[] -+ // umov w_b[], w_h[], w_s[], x_d[] -+ test_umov_x_d0(TyD); -+ test_umov_x_d1(TyD); -+ test_umov_w_s0(TyS); -+ test_umov_w_s3(TyS); -+ test_umov_w_h0(TyH); -+ test_umov_w_h7(TyH); -+ test_umov_w_b0(TyB); -+ test_umov_w_b15(TyB); -+ test_smov_x_s0(TyS); -+ test_smov_x_s3(TyS); -+ test_smov_x_h0(TyH); -+ test_smov_x_h7(TyH); -+ test_smov_w_h0(TyH); -+ test_smov_w_h7(TyH); -+ test_smov_x_b0(TyB); -+ test_smov_x_b15(TyB); -+ test_smov_w_b0(TyB); -+ test_smov_w_b15(TyB); -+ -+ // sqabs d,s,h,b -+ // sqneg d,s,h,b -+ test_sqabs_d_d(TyD); -+ test_sqabs_s_s(TyS); -+ test_sqabs_h_h(TyH); -+ test_sqabs_b_b(TyB); -+ test_sqneg_d_d(TyD); -+ test_sqneg_s_s(TyS); -+ test_sqneg_h_h(TyH); -+ test_sqneg_b_b(TyB); -+ -+ // sqabs 2d,4s,2s,8h,4h,16b,8b -+ // sqneg 2d,4s,2s,8h,4h,16b,8b -+ test_sqabs_2d_2d(TyD); -+ test_sqabs_4s_4s(TyS); -+ test_sqabs_2s_2s(TyS); -+ test_sqabs_8h_8h(TyH); -+ test_sqabs_4h_4h(TyH); -+ test_sqabs_16b_16b(TyB); -+ test_sqabs_8b_8b(TyB); -+ test_sqneg_2d_2d(TyD); -+ test_sqneg_4s_4s(TyS); -+ test_sqneg_2s_2s(TyS); -+ test_sqneg_8h_8h(TyH); -+ test_sqneg_4h_4h(TyH); -+ test_sqneg_16b_16b(TyB); -+ test_sqneg_8b_8b(TyB); -+ -+ // sqadd d,s,h,b -+ // uqadd d,s,h,b -+ // sqsub d,s,h,b -+ // uqsub d,s,h,b -+ test_sqadd_d_d_d(TyD); -+ test_sqadd_s_s_s(TyS); -+ test_sqadd_h_h_h(TyH); -+ test_sqadd_b_b_b(TyB); -+ test_uqadd_d_d_d(TyD); -+ test_uqadd_s_s_s(TyS); -+ test_uqadd_h_h_h(TyH); -+ test_uqadd_b_b_b(TyB); -+ test_sqsub_d_d_d(TyD); -+ test_sqsub_s_s_s(TyS); -+ test_sqsub_h_h_h(TyH); -+ test_sqsub_b_b_b(TyB); -+ test_uqsub_d_d_d(TyD); -+ test_uqsub_s_s_s(TyS); -+ test_uqsub_h_h_h(TyH); -+ test_uqsub_b_b_b(TyB); -+ -+ // sqadd 2d,4s,2s,8h,4h,16b,8b -+ // uqadd 2d,4s,2s,8h,4h,16b,8b -+ // sqsub 2d,4s,2s,8h,4h,16b,8b -+ // uqsub 2d,4s,2s,8h,4h,16b,8b -+ test_sqadd_2d_2d_2d(TyD); -+ test_sqadd_4s_4s_4s(TyS); -+ test_sqadd_2s_2s_2s(TyS); -+ test_sqadd_8h_8h_8h(TyH); -+ test_sqadd_4h_4h_4h(TyH); -+ test_sqadd_16b_16b_16b(TyB); -+ test_sqadd_8b_8b_8b(TyB); -+ test_uqadd_2d_2d_2d(TyD); -+ test_uqadd_4s_4s_4s(TyS); -+ test_uqadd_2s_2s_2s(TyS); -+ test_uqadd_8h_8h_8h(TyH); -+ test_uqadd_4h_4h_4h(TyH); -+ test_uqadd_16b_16b_16b(TyB); -+ test_uqadd_8b_8b_8b(TyB); -+ test_sqsub_2d_2d_2d(TyD); -+ test_sqsub_4s_4s_4s(TyS); -+ test_sqsub_2s_2s_2s(TyS); -+ test_sqsub_8h_8h_8h(TyH); -+ test_sqsub_4h_4h_4h(TyH); -+ test_sqsub_16b_16b_16b(TyB); -+ test_sqsub_8b_8b_8b(TyB); -+ test_uqsub_2d_2d_2d(TyD); -+ test_uqsub_4s_4s_4s(TyS); -+ test_uqsub_2s_2s_2s(TyS); -+ test_uqsub_8h_8h_8h(TyH); -+ test_uqsub_4h_4h_4h(TyH); -+ test_uqsub_16b_16b_16b(TyB); -+ test_uqsub_8b_8b_8b(TyB); -+ -+ // sqdmlal d_s_s[], s_h_h[] -+ // sqdmlsl d_s_s[], s_h_h[] -+ // sqdmull d_s_s[], s_h_h[] -+ test_sqdmlal_d_s_s0(TyS); -+ test_sqdmlal_d_s_s3(TyS); -+ test_sqdmlal_s_h_h1(TyH); -+ test_sqdmlal_s_h_h5(TyH); -+ test_sqdmlsl_d_s_s0(TyS); -+ test_sqdmlsl_d_s_s3(TyS); -+ test_sqdmlsl_s_h_h1(TyH); -+ test_sqdmlsl_s_h_h5(TyH); -+ test_sqdmull_d_s_s0(TyS); -+ test_sqdmull_d_s_s3(TyS); -+ test_sqdmull_s_h_h1(TyH); -+ test_sqdmull_s_h_h5(TyH); -+ -+ // sqdmlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[] -+ // sqdmlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[] -+ // sqdmull{2} 2d_2s/4s_s[], 4s_4h/2h_h[] -+ test_sqdmlal_2d_2s_s0(TyS); -+ test_sqdmlal_2d_2s_s3(TyS); -+ test_sqdmlal2_2d_4s_s1(TyS); -+ test_sqdmlal2_2d_4s_s2(TyS); -+ test_sqdmlal_4s_4h_h0(TyH); -+ test_sqdmlal_4s_4h_h7(TyH); -+ test_sqdmlal2_4s_8h_h1(TyH); -+ test_sqdmlal2_4s_8h_h4(TyH); -+ test_sqdmlsl_2d_2s_s0(TyS); -+ test_sqdmlsl_2d_2s_s3(TyS); -+ test_sqdmlsl2_2d_4s_s1(TyS); -+ test_sqdmlsl2_2d_4s_s2(TyS); -+ test_sqdmlsl_4s_4h_h0(TyH); -+ test_sqdmlsl_4s_4h_h7(TyH); -+ test_sqdmlsl2_4s_8h_h1(TyH); -+ test_sqdmlsl2_4s_8h_h4(TyH); -+ test_sqdmull_2d_2s_s0(TyS); -+ test_sqdmull_2d_2s_s3(TyS); -+ test_sqdmull2_2d_4s_s1(TyS); -+ test_sqdmull2_2d_4s_s2(TyS); -+ test_sqdmull_4s_4h_h0(TyH); -+ test_sqdmull_4s_4h_h7(TyH); -+ test_sqdmull2_4s_8h_h1(TyH); -+ test_sqdmull2_4s_8h_h4(TyH); -+ -+ // sqdmlal d_s_s, s_h_h -+ // sqdmlsl d_s_s, s_h_h -+ // sqdmull d_s_s, s_h_h -+ test_sqdmlal_d_s_s(TyS); -+ test_sqdmlal_s_h_h(TyH); -+ test_sqdmlsl_d_s_s(TyS); -+ test_sqdmlsl_s_h_h(TyH); -+ test_sqdmull_d_s_s(TyS); -+ test_sqdmull_s_h_h(TyH); -+ -+ // sqdmlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h) -+ // sqdmlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h) -+ // sqdmull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h) -+ test_sqdmlal_2d_2s_2s(TyS); -+ test_sqdmlal2_2d_4s_4s(TyS); -+ test_sqdmlal_4s_4h_4h(TyH); -+ test_sqdmlal2_4s_8h_8h(TyH); -+ test_sqdmlsl_2d_2s_2s(TyS); -+ test_sqdmlsl2_2d_4s_4s(TyS); -+ test_sqdmlsl_4s_4h_4h(TyH); -+ test_sqdmlsl2_4s_8h_8h(TyH); -+ test_sqdmull_2d_2s_2s(TyS); -+ test_sqdmull2_2d_4s_4s(TyS); -+ test_sqdmull_4s_4h_4h(TyH); -+ test_sqdmull2_4s_8h_8h(TyH); -+ -+ // sqdmulh s_s_s[], h_h_h[] -+ // sqrdmulh s_s_s[], h_h_h[] -+ test_sqdmulh_s_s_s1(TyS); -+ test_sqdmulh_s_s_s3(TyS); -+ test_sqdmulh_h_h_h2(TyH); -+ test_sqdmulh_h_h_h7(TyH); -+ test_sqrdmulh_s_s_s1(TyS); -+ test_sqrdmulh_s_s_s3(TyS); -+ test_sqrdmulh_h_h_h2(TyH); -+ test_sqrdmulh_h_h_h7(TyH); -+ -+ // sqdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[] -+ // sqrdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[] -+ test_sqdmulh_4s_4s_s1(TyS); -+ test_sqdmulh_4s_4s_s3(TyS); -+ test_sqdmulh_2s_2s_s1(TyS); -+ test_sqdmulh_2s_2s_s3(TyS); -+ test_sqdmulh_8h_8h_h2(TyH); -+ test_sqdmulh_8h_8h_h7(TyH); -+ test_sqdmulh_4h_4h_h2(TyH); -+ test_sqdmulh_4h_4h_h7(TyH); -+ test_sqrdmulh_4s_4s_s1(TyS); -+ test_sqrdmulh_4s_4s_s3(TyS); -+ test_sqrdmulh_2s_2s_s1(TyS); -+ test_sqrdmulh_2s_2s_s3(TyS); -+ test_sqrdmulh_8h_8h_h2(TyH); -+ test_sqrdmulh_8h_8h_h7(TyH); -+ test_sqrdmulh_4h_4h_h2(TyH); -+ test_sqrdmulh_4h_4h_h7(TyH); -+ -+ // sqdmulh h,s -+ // sqrdmulh h,s -+ test_sqdmulh_s_s_s(TyS); -+ test_sqdmulh_h_h_h(TyH); -+ test_sqrdmulh_s_s_s(TyS); -+ test_sqrdmulh_h_h_h(TyH); -+ -+ // sqdmulh 4s,2s,8h,4h -+ // sqrdmulh 4s,2s,8h,4h -+ test_sqdmulh_4s_4s_4s(TyS); -+ test_sqdmulh_2s_2s_2s(TyS); -+ test_sqdmulh_8h_8h_8h(TyH); -+ test_sqdmulh_4h_4h_4h(TyH); -+ test_sqrdmulh_4s_4s_4s(TyS); -+ test_sqrdmulh_2s_2s_2s(TyS); -+ test_sqrdmulh_8h_8h_8h(TyH); -+ test_sqrdmulh_4h_4h_4h(TyH); -+ -+ // sqshl (reg) d,s,h,b -+ // uqshl (reg) d,s,h,b -+ // sqrshl (reg) d,s,h,b -+ // uqrshl (reg) d,s,h,b -+ test_sqshl_d_d_d(TyD); -+ test_sqshl_s_s_s(TyS); -+ test_sqshl_h_h_h(TyH); -+ test_sqshl_b_b_b(TyB); -+ test_uqshl_d_d_d(TyD); -+ test_uqshl_s_s_s(TyS); -+ test_uqshl_h_h_h(TyH); -+ test_uqshl_b_b_b(TyB); -+ test_sqrshl_d_d_d(TyD); -+ test_sqrshl_s_s_s(TyS); -+ test_sqrshl_h_h_h(TyH); -+ test_sqrshl_b_b_b(TyB); -+ test_uqrshl_d_d_d(TyD); -+ test_uqrshl_s_s_s(TyS); -+ test_uqrshl_h_h_h(TyH); -+ test_uqrshl_b_b_b(TyB); -+ -+ // sqshl (reg) 2d,4s,2s,8h,4h,16b,8b -+ // uqshl (reg) 2d,4s,2s,8h,4h,16b,8b -+ // sqrshl (reg) 2d,4s,2s,8h,4h,16b,8b -+ // uqrshl (reg) 2d,4s,2s,8h,4h,16b,8b -+ test_sqshl_2d_2d_2d(TyD); -+ test_sqshl_4s_4s_4s(TyS); -+ test_sqshl_2s_2s_2s(TyS); -+ test_sqshl_8h_8h_8h(TyH); -+ test_sqshl_4h_4h_4h(TyH); -+ test_sqshl_16b_16b_16b(TyB); -+ test_sqshl_8b_8b_8b(TyB); -+ test_uqshl_2d_2d_2d(TyD); -+ test_uqshl_4s_4s_4s(TyS); -+ test_uqshl_2s_2s_2s(TyS); -+ test_uqshl_8h_8h_8h(TyH); -+ test_uqshl_4h_4h_4h(TyH); -+ test_uqshl_16b_16b_16b(TyB); -+ test_uqshl_8b_8b_8b(TyB); -+ test_sqrshl_2d_2d_2d(TyD); -+ test_sqrshl_4s_4s_4s(TyS); -+ test_sqrshl_2s_2s_2s(TyS); -+ test_sqrshl_8h_8h_8h(TyH); -+ test_sqrshl_4h_4h_4h(TyH); -+ test_sqrshl_16b_16b_16b(TyB); -+ test_sqrshl_8b_8b_8b(TyB); -+ test_uqrshl_2d_2d_2d(TyD); -+ test_uqrshl_4s_4s_4s(TyS); -+ test_uqrshl_2s_2s_2s(TyS); -+ test_uqrshl_8h_8h_8h(TyH); -+ test_uqrshl_4h_4h_4h(TyH); -+ test_uqrshl_16b_16b_16b(TyB); -+ test_uqrshl_8b_8b_8b(TyB); -+ -+ // sqrshrn s_d, h_s, b_h #imm -+ // uqrshrn s_d, h_s, b_h #imm -+ // sqshrn s_d, h_s, b_h #imm -+ // uqshrn s_d, h_s, b_h #imm -+ // sqrshrun s_d, h_s, b_h #imm -+ // sqshrun s_d, h_s, b_h #imm -+ test_sqrshrn_s_d_1(TyD); -+ test_sqrshrn_s_d_17(TyD); -+ test_sqrshrn_s_d_32(TyD); -+ test_sqrshrn_h_s_1(TyS); -+ test_sqrshrn_h_s_9(TyS); -+ test_sqrshrn_h_s_16(TyS); -+ test_sqrshrn_b_h_1(TyH); -+ test_sqrshrn_b_h_4(TyH); -+ test_sqrshrn_b_h_8(TyH); -+ test_uqrshrn_s_d_1(TyD); -+ test_uqrshrn_s_d_17(TyD); -+ test_uqrshrn_s_d_32(TyD); -+ test_uqrshrn_h_s_1(TyS); -+ test_uqrshrn_h_s_9(TyS); -+ test_uqrshrn_h_s_16(TyS); -+ test_uqrshrn_b_h_1(TyH); -+ test_uqrshrn_b_h_4(TyH); -+ test_uqrshrn_b_h_8(TyH); -+ test_sqshrn_s_d_1(TyD); -+ test_sqshrn_s_d_17(TyD); -+ test_sqshrn_s_d_32(TyD); -+ test_sqshrn_h_s_1(TyS); -+ test_sqshrn_h_s_9(TyS); -+ test_sqshrn_h_s_16(TyS); -+ test_sqshrn_b_h_1(TyH); -+ test_sqshrn_b_h_4(TyH); -+ test_sqshrn_b_h_8(TyH); -+ test_uqshrn_s_d_1(TyD); -+ test_uqshrn_s_d_17(TyD); -+ test_uqshrn_s_d_32(TyD); -+ test_uqshrn_h_s_1(TyS); -+ test_uqshrn_h_s_9(TyS); -+ test_uqshrn_h_s_16(TyS); -+ test_uqshrn_b_h_1(TyH); -+ test_uqshrn_b_h_4(TyH); -+ test_uqshrn_b_h_8(TyH); -+ test_sqrshrun_s_d_1(TyD); -+ test_sqrshrun_s_d_17(TyD); -+ test_sqrshrun_s_d_32(TyD); -+ test_sqrshrun_h_s_1(TyS); -+ test_sqrshrun_h_s_9(TyS); -+ test_sqrshrun_h_s_16(TyS); -+ test_sqrshrun_b_h_1(TyH); -+ test_sqrshrun_b_h_4(TyH); -+ test_sqrshrun_b_h_8(TyH); -+ test_sqshrun_s_d_1(TyD); -+ test_sqshrun_s_d_17(TyD); -+ test_sqshrun_s_d_32(TyD); -+ test_sqshrun_h_s_1(TyS); -+ test_sqshrun_h_s_9(TyS); -+ test_sqshrun_h_s_16(TyS); -+ test_sqshrun_b_h_1(TyH); -+ test_sqshrun_b_h_4(TyH); -+ test_sqshrun_b_h_8(TyH); -+ -+ // sqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm -+ // uqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm -+ // sqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm -+ // uqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm -+ // sqrshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm -+ // sqshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm -+ test_sqrshrn_2s_2d_1(TyD); -+ test_sqrshrn_2s_2d_17(TyD); -+ test_sqrshrn_2s_2d_32(TyD); -+ test_sqrshrn2_4s_2d_1(TyD); -+ test_sqrshrn2_4s_2d_17(TyD); -+ test_sqrshrn2_4s_2d_32(TyD); -+ test_sqrshrn_4h_4s_1(TyS); -+ test_sqrshrn_4h_4s_9(TyS); -+ test_sqrshrn_4h_4s_16(TyS); -+ test_sqrshrn2_8h_4s_1(TyS); -+ test_sqrshrn2_8h_4s_9(TyS); -+ test_sqrshrn2_8h_4s_16(TyS); -+ test_sqrshrn_8b_8h_1(TyH); -+ test_sqrshrn_8b_8h_4(TyH); -+ test_sqrshrn_8b_8h_8(TyH); -+ test_sqrshrn2_16b_8h_1(TyH); -+ test_sqrshrn2_16b_8h_4(TyH); -+ test_sqrshrn2_16b_8h_8(TyH); -+ test_uqrshrn_2s_2d_1(TyD); -+ test_uqrshrn_2s_2d_17(TyD); -+ test_uqrshrn_2s_2d_32(TyD); -+ test_uqrshrn2_4s_2d_1(TyD); -+ test_uqrshrn2_4s_2d_17(TyD); -+ test_uqrshrn2_4s_2d_32(TyD); -+ test_uqrshrn_4h_4s_1(TyS); -+ test_uqrshrn_4h_4s_9(TyS); -+ test_uqrshrn_4h_4s_16(TyS); -+ test_uqrshrn2_8h_4s_1(TyS); -+ test_uqrshrn2_8h_4s_9(TyS); -+ test_uqrshrn2_8h_4s_16(TyS); -+ test_uqrshrn_8b_8h_1(TyH); -+ test_uqrshrn_8b_8h_4(TyH); -+ test_uqrshrn_8b_8h_8(TyH); -+ test_uqrshrn2_16b_8h_1(TyH); -+ test_uqrshrn2_16b_8h_4(TyH); -+ test_uqrshrn2_16b_8h_8(TyH); -+ test_sqshrn_2s_2d_1(TyD); -+ test_sqshrn_2s_2d_17(TyD); -+ test_sqshrn_2s_2d_32(TyD); -+ test_sqshrn2_4s_2d_1(TyD); -+ test_sqshrn2_4s_2d_17(TyD); -+ test_sqshrn2_4s_2d_32(TyD); -+ test_sqshrn_4h_4s_1(TyS); -+ test_sqshrn_4h_4s_9(TyS); -+ test_sqshrn_4h_4s_16(TyS); -+ test_sqshrn2_8h_4s_1(TyS); -+ test_sqshrn2_8h_4s_9(TyS); -+ test_sqshrn2_8h_4s_16(TyS); -+ test_sqshrn_8b_8h_1(TyH); -+ test_sqshrn_8b_8h_4(TyH); -+ test_sqshrn_8b_8h_8(TyH); -+ test_sqshrn2_16b_8h_1(TyH); -+ test_sqshrn2_16b_8h_4(TyH); -+ test_sqshrn2_16b_8h_8(TyH); -+ test_uqshrn_2s_2d_1(TyD); -+ test_uqshrn_2s_2d_17(TyD); -+ test_uqshrn_2s_2d_32(TyD); -+ test_uqshrn2_4s_2d_1(TyD); -+ test_uqshrn2_4s_2d_17(TyD); -+ test_uqshrn2_4s_2d_32(TyD); -+ test_uqshrn_4h_4s_1(TyS); -+ test_uqshrn_4h_4s_9(TyS); -+ test_uqshrn_4h_4s_16(TyS); -+ test_uqshrn2_8h_4s_1(TyS); -+ test_uqshrn2_8h_4s_9(TyS); -+ test_uqshrn2_8h_4s_16(TyS); -+ test_uqshrn_8b_8h_1(TyH); -+ test_uqshrn_8b_8h_4(TyH); -+ test_uqshrn_8b_8h_8(TyH); -+ test_uqshrn2_16b_8h_1(TyH); -+ test_uqshrn2_16b_8h_4(TyH); -+ test_uqshrn2_16b_8h_8(TyH); -+ test_sqrshrun_2s_2d_1(TyD); -+ test_sqrshrun_2s_2d_17(TyD); -+ test_sqrshrun_2s_2d_32(TyD); -+ test_sqrshrun2_4s_2d_1(TyD); -+ test_sqrshrun2_4s_2d_17(TyD); -+ test_sqrshrun2_4s_2d_32(TyD); -+ test_sqrshrun_4h_4s_1(TyS); -+ test_sqrshrun_4h_4s_9(TyS); -+ test_sqrshrun_4h_4s_16(TyS); -+ test_sqrshrun2_8h_4s_1(TyS); -+ test_sqrshrun2_8h_4s_9(TyS); -+ test_sqrshrun2_8h_4s_16(TyS); -+ test_sqrshrun_8b_8h_1(TyH); -+ test_sqrshrun_8b_8h_4(TyH); -+ test_sqrshrun_8b_8h_8(TyH); -+ test_sqrshrun2_16b_8h_1(TyH); -+ test_sqrshrun2_16b_8h_4(TyH); -+ test_sqrshrun2_16b_8h_8(TyH); -+ test_sqshrun_2s_2d_1(TyD); -+ test_sqshrun_2s_2d_17(TyD); -+ test_sqshrun_2s_2d_32(TyD); -+ test_sqshrun2_4s_2d_1(TyD); -+ test_sqshrun2_4s_2d_17(TyD); -+ test_sqshrun2_4s_2d_32(TyD); -+ test_sqshrun_4h_4s_1(TyS); -+ test_sqshrun_4h_4s_9(TyS); -+ test_sqshrun_4h_4s_16(TyS); -+ test_sqshrun2_8h_4s_1(TyS); -+ test_sqshrun2_8h_4s_9(TyS); -+ test_sqshrun2_8h_4s_16(TyS); -+ test_sqshrun_8b_8h_1(TyH); -+ test_sqshrun_8b_8h_4(TyH); -+ test_sqshrun_8b_8h_8(TyH); -+ test_sqshrun2_16b_8h_1(TyH); -+ test_sqshrun2_16b_8h_4(TyH); -+ test_sqshrun2_16b_8h_8(TyH); -+ -+ // sqshl (imm) d,s,h,b _#imm -+ // uqshl (imm) d,s,h,b _#imm -+ // sqshlu (imm) d,s,h,b _#imm -+ test_sqshl_d_d_0(TyD); -+ test_sqshl_d_d_32(TyD); -+ test_sqshl_d_d_63(TyD); -+ test_sqshl_s_s_0(TyS); -+ test_sqshl_s_s_16(TyS); -+ test_sqshl_s_s_31(TyS); -+ test_sqshl_h_h_0(TyH); -+ test_sqshl_h_h_8(TyH); -+ test_sqshl_h_h_15(TyH); -+ test_sqshl_b_b_0(TyB); -+ test_sqshl_b_b_4(TyB); -+ test_sqshl_b_b_7(TyB); -+ test_uqshl_d_d_0(TyD); -+ test_uqshl_d_d_32(TyD); -+ test_uqshl_d_d_63(TyD); -+ test_uqshl_s_s_0(TyS); -+ test_uqshl_s_s_16(TyS); -+ test_uqshl_s_s_31(TyS); -+ test_uqshl_h_h_0(TyH); -+ test_uqshl_h_h_8(TyH); -+ test_uqshl_h_h_15(TyH); -+ test_uqshl_b_b_0(TyB); -+ test_uqshl_b_b_4(TyB); -+ test_uqshl_b_b_7(TyB); -+ test_sqshlu_d_d_0(TyD); -+ test_sqshlu_d_d_32(TyD); -+ test_sqshlu_d_d_63(TyD); -+ test_sqshlu_s_s_0(TyS); -+ test_sqshlu_s_s_16(TyS); -+ test_sqshlu_s_s_31(TyS); -+ test_sqshlu_h_h_0(TyH); -+ test_sqshlu_h_h_8(TyH); -+ test_sqshlu_h_h_15(TyH); -+ test_sqshlu_b_b_0(TyB); -+ test_sqshlu_b_b_4(TyB); -+ test_sqshlu_b_b_7(TyB); -+ -+ // sqshl (imm) 2d,4s,2s,8h,4h,16b,8b _#imm -+ // uqshl (imm) 2d,4s,2s,8h,4h,16b,8b _#imm -+ // sqshlu (imm) 2d,4s,2s,8h,4h,16b,8b _#imm -+ test_sqshl_2d_2d_0(TyD); -+ test_sqshl_2d_2d_32(TyD); -+ test_sqshl_2d_2d_63(TyD); -+ test_sqshl_4s_4s_0(TyS); -+ test_sqshl_4s_4s_16(TyS); -+ test_sqshl_4s_4s_31(TyS); -+ test_sqshl_2s_2s_0(TyS); -+ test_sqshl_2s_2s_16(TyS); -+ test_sqshl_2s_2s_31(TyS); -+ test_sqshl_8h_8h_0(TyH); -+ test_sqshl_8h_8h_8(TyH); -+ test_sqshl_8h_8h_15(TyH); -+ test_sqshl_4h_4h_0(TyH); -+ test_sqshl_4h_4h_8(TyH); -+ test_sqshl_4h_4h_15(TyH); -+ test_sqshl_16b_16b_0(TyB); -+ test_sqshl_16b_16b_3(TyB); -+ test_sqshl_16b_16b_7(TyB); -+ test_sqshl_8b_8b_0(TyB); -+ test_sqshl_8b_8b_3(TyB); -+ test_sqshl_8b_8b_7(TyB); -+ test_uqshl_2d_2d_0(TyD); -+ test_uqshl_2d_2d_32(TyD); -+ test_uqshl_2d_2d_63(TyD); -+ test_uqshl_4s_4s_0(TyS); -+ test_uqshl_4s_4s_16(TyS); -+ test_uqshl_4s_4s_31(TyS); -+ test_uqshl_2s_2s_0(TyS); -+ test_uqshl_2s_2s_16(TyS); -+ test_uqshl_2s_2s_31(TyS); -+ test_uqshl_8h_8h_0(TyH); -+ test_uqshl_8h_8h_8(TyH); -+ test_uqshl_8h_8h_15(TyH); -+ test_uqshl_4h_4h_0(TyH); -+ test_uqshl_4h_4h_8(TyH); -+ test_uqshl_4h_4h_15(TyH); -+ test_uqshl_16b_16b_0(TyB); -+ test_uqshl_16b_16b_3(TyB); -+ test_uqshl_16b_16b_7(TyB); -+ test_uqshl_8b_8b_0(TyB); -+ test_uqshl_8b_8b_3(TyB); -+ test_uqshl_8b_8b_7(TyB); -+ test_sqshlu_2d_2d_0(TyD); -+ test_sqshlu_2d_2d_32(TyD); -+ test_sqshlu_2d_2d_63(TyD); -+ test_sqshlu_4s_4s_0(TyS); -+ test_sqshlu_4s_4s_16(TyS); -+ test_sqshlu_4s_4s_31(TyS); -+ test_sqshlu_2s_2s_0(TyS); -+ test_sqshlu_2s_2s_16(TyS); -+ test_sqshlu_2s_2s_31(TyS); -+ test_sqshlu_8h_8h_0(TyH); -+ test_sqshlu_8h_8h_8(TyH); -+ test_sqshlu_8h_8h_15(TyH); -+ test_sqshlu_4h_4h_0(TyH); -+ test_sqshlu_4h_4h_8(TyH); -+ test_sqshlu_4h_4h_15(TyH); -+ test_sqshlu_16b_16b_0(TyB); -+ test_sqshlu_16b_16b_3(TyB); -+ test_sqshlu_16b_16b_7(TyB); -+ test_sqshlu_8b_8b_0(TyB); -+ test_sqshlu_8b_8b_3(TyB); -+ test_sqshlu_8b_8b_7(TyB); -+ -+ // sqxtn s_d,h_s,b_h -+ // uqxtn s_d,h_s,b_h -+ // sqxtun s_d,h_s,b_h -+ test_sqxtn_s_d(TyD); -+ test_sqxtn_h_s(TyS); -+ test_sqxtn_b_h(TyH); -+ test_uqxtn_s_d(TyD); -+ test_uqxtn_h_s(TyS); -+ test_uqxtn_b_h(TyH); -+ test_sqxtun_s_d(TyD); -+ test_sqxtun_h_s(TyS); -+ test_sqxtun_b_h(TyH); -+ -+ // sqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h -+ // uqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h -+ // sqxtun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h -+ test_sqxtn_2s_2d(TyD); -+ test_sqxtn2_4s_2d(TyD); -+ test_sqxtn_4h_4s(TyS); -+ test_sqxtn2_8h_4s(TyS); -+ test_sqxtn_8b_8h(TyH); -+ test_sqxtn2_16b_8h(TyH); -+ test_uqxtn_2s_2d(TyD); -+ test_uqxtn2_4s_2d(TyD); -+ test_uqxtn_4h_4s(TyS); -+ test_uqxtn2_8h_4s(TyS); -+ test_uqxtn_8b_8h(TyH); -+ test_uqxtn2_16b_8h(TyH); -+ test_sqxtun_2s_2d(TyD); -+ test_sqxtun2_4s_2d(TyD); -+ test_sqxtun_4h_4s(TyS); -+ test_sqxtun2_8h_4s(TyS); -+ test_sqxtun_8b_8h(TyH); -+ test_sqxtun2_16b_8h(TyH); -+ -+ // srhadd 4s,2s,8h,4h,16b,8b -+ // urhadd 4s,2s,8h,4h,16b,8b -+ test_srhadd_4s_4s_4s(TyS); -+ test_srhadd_2s_2s_2s(TyS); -+ test_srhadd_8h_8h_8h(TyH); -+ test_srhadd_4h_4h_4h(TyH); -+ test_srhadd_16b_16b_16b(TyB); -+ test_srhadd_8b_8b_8b(TyB); -+ test_urhadd_4s_4s_4s(TyS); -+ test_urhadd_2s_2s_2s(TyS); -+ test_urhadd_8h_8h_8h(TyH); -+ test_urhadd_4h_4h_4h(TyH); -+ test_urhadd_16b_16b_16b(TyB); -+ test_urhadd_8b_8b_8b(TyB); -+ -+ // sshl (reg) d -+ // ushl (reg) d -+ test_sshl_d_d_d(TyD); -+ test_ushl_d_d_d(TyD); -+ -+ // sshl (reg) 2d,4s,2s,8h,4h,16b,8b -+ // ushl (reg) 2d,4s,2s,8h,4h,16b,8b -+ test_sshl_2d_2d_2d(TyD); -+ test_sshl_4s_4s_4s(TyS); -+ test_sshl_2s_2s_2s(TyS); -+ test_sshl_8h_8h_8h(TyH); -+ test_sshl_4h_4h_4h(TyH); -+ test_sshl_16b_16b_16b(TyB); -+ test_sshl_8b_8b_8b(TyB); -+ test_ushl_2d_2d_2d(TyD); -+ test_ushl_4s_4s_4s(TyS); -+ test_ushl_2s_2s_2s(TyS); -+ test_ushl_8h_8h_8h(TyH); -+ test_ushl_4h_4h_4h(TyH); -+ test_ushl_16b_16b_16b(TyB); -+ test_ushl_8b_8b_8b(TyB); -+ -+ // shl (imm) d -+ // sshr (imm) d -+ // ushr (imm) d -+ test_shl_d_d_0(TyD); -+ test_shl_d_d_32(TyD); -+ test_shl_d_d_63(TyD); -+ test_sshr_d_d_1(TyD); -+ test_sshr_d_d_32(TyD); -+ test_sshr_d_d_64(TyD); -+ test_ushr_d_d_1(TyD); -+ test_ushr_d_d_32(TyD); -+ test_ushr_d_d_64(TyD); -+ -+ // shl (imm) 16b,8b,8h,4h,4s,2s,2d -+ // sshr (imm) 2d,4s,2s,8h,4h,16b,8b -+ // ushr (imm) 2d,4s,2s,8h,4h,16b,8b -+ test_shl_2d_2d_0(TyD); -+ test_shl_2d_2d_13(TyD); -+ test_shl_2d_2d_63(TyD); -+ test_shl_4s_4s_0(TyS); -+ test_shl_4s_4s_13(TyS); -+ test_shl_4s_4s_31(TyS); -+ test_shl_2s_2s_0(TyS); -+ test_shl_2s_2s_13(TyS); -+ test_shl_2s_2s_31(TyS); -+ test_shl_8h_8h_0(TyH); -+ test_shl_8h_8h_13(TyH); -+ test_shl_8h_8h_15(TyH); -+ test_shl_4h_4h_0(TyH); -+ test_shl_4h_4h_13(TyH); -+ test_shl_4h_4h_15(TyH); -+ test_shl_16b_16b_0(TyB); -+ test_shl_16b_16b_7(TyB); -+ test_shl_8b_8b_0(TyB); -+ test_shl_8b_8b_7(TyB); -+ test_sshr_2d_2d_1(TyD); -+ test_sshr_2d_2d_13(TyD); -+ test_sshr_2d_2d_64(TyD); -+ test_sshr_4s_4s_1(TyS); -+ test_sshr_4s_4s_13(TyS); -+ test_sshr_4s_4s_32(TyS); -+ test_sshr_2s_2s_1(TyS); -+ test_sshr_2s_2s_13(TyS); -+ test_sshr_2s_2s_32(TyS); -+ test_sshr_8h_8h_1(TyH); -+ test_sshr_8h_8h_13(TyH); -+ test_sshr_8h_8h_16(TyH); -+ test_sshr_4h_4h_1(TyH); -+ test_sshr_4h_4h_13(TyH); -+ test_sshr_4h_4h_16(TyH); -+ test_sshr_16b_16b_1(TyB); -+ test_sshr_16b_16b_8(TyB); -+ test_sshr_8b_8b_1(TyB); -+ test_sshr_8b_8b_8(TyB); -+ test_ushr_2d_2d_1(TyD); -+ test_ushr_2d_2d_13(TyD); -+ test_ushr_2d_2d_64(TyD); -+ test_ushr_4s_4s_1(TyS); -+ test_ushr_4s_4s_13(TyS); -+ test_ushr_4s_4s_32(TyS); -+ test_ushr_2s_2s_1(TyS); -+ test_ushr_2s_2s_13(TyS); -+ test_ushr_2s_2s_32(TyS); -+ test_ushr_8h_8h_1(TyH); -+ test_ushr_8h_8h_13(TyH); -+ test_ushr_8h_8h_16(TyH); -+ test_ushr_4h_4h_1(TyH); -+ test_ushr_4h_4h_13(TyH); -+ test_ushr_4h_4h_16(TyH); -+ test_ushr_16b_16b_1(TyB); -+ test_ushr_16b_16b_8(TyB); -+ test_ushr_8b_8b_1(TyB); -+ test_ushr_8b_8b_8(TyB); -+ -+ // ssra (imm) d -+ // usra (imm) d -+ test_ssra_d_d_1(TyD); -+ test_ssra_d_d_32(TyD); -+ test_ssra_d_d_64(TyD); -+ test_usra_d_d_1(TyD); -+ test_usra_d_d_32(TyD); -+ test_usra_d_d_64(TyD); -+ -+ // ssra (imm) 2d,4s,2s,8h,4h,16b,8b -+ // usra (imm) 2d,4s,2s,8h,4h,16b,8b -+ test_ssra_2d_2d_1(TyD); -+ test_ssra_2d_2d_32(TyD); -+ test_ssra_2d_2d_64(TyD); -+ test_ssra_4s_4s_1(TyS); -+ test_ssra_4s_4s_16(TyS); -+ test_ssra_4s_4s_32(TyS); -+ test_ssra_2s_2s_1(TyS); -+ test_ssra_2s_2s_16(TyS); -+ test_ssra_2s_2s_32(TyS); -+ test_ssra_8h_8h_1(TyH); -+ test_ssra_8h_8h_8(TyH); -+ test_ssra_8h_8h_16(TyH); -+ test_ssra_4h_4h_1(TyH); -+ test_ssra_4h_4h_8(TyH); -+ test_ssra_4h_4h_16(TyH); -+ test_ssra_16b_16b_1(TyB); -+ test_ssra_16b_16b_3(TyB); -+ test_ssra_16b_16b_8(TyB); -+ test_ssra_8b_8b_1(TyB); -+ test_ssra_8b_8b_3(TyB); -+ test_ssra_8b_8b_8(TyB); -+ test_usra_2d_2d_1(TyD); -+ test_usra_2d_2d_32(TyD); -+ test_usra_2d_2d_64(TyD); -+ test_usra_4s_4s_1(TyS); -+ test_usra_4s_4s_16(TyS); -+ test_usra_4s_4s_32(TyS); -+ test_usra_2s_2s_1(TyS); -+ test_usra_2s_2s_16(TyS); -+ test_usra_2s_2s_32(TyS); -+ test_usra_8h_8h_1(TyH); -+ test_usra_8h_8h_8(TyH); -+ test_usra_8h_8h_16(TyH); -+ test_usra_4h_4h_1(TyH); -+ test_usra_4h_4h_8(TyH); -+ test_usra_4h_4h_16(TyH); -+ test_usra_16b_16b_1(TyB); -+ test_usra_16b_16b_3(TyB); -+ test_usra_16b_16b_8(TyB); -+ test_usra_8b_8b_1(TyB); -+ test_usra_8b_8b_3(TyB); -+ test_usra_8b_8b_8(TyB); -+ -+ // srshl (reg) d -+ // urshl (reg) d -+ test_srshl_d_d_d(TyD); -+ test_urshl_d_d_d(TyD); -+ -+ // srshl (reg) 2d,4s,2s,8h,4h,16b,8b -+ // urshl (reg) 2d,4s,2s,8h,4h,16b,8b -+ test_srshl_2d_2d_2d(TyD); -+ test_srshl_4s_4s_4s(TyS); -+ test_srshl_2s_2s_2s(TyS); -+ test_srshl_8h_8h_8h(TyH); -+ test_srshl_4h_4h_4h(TyH); -+ test_srshl_16b_16b_16b(TyB); -+ test_srshl_8b_8b_8b(TyB); -+ test_urshl_2d_2d_2d(TyD); -+ test_urshl_4s_4s_4s(TyS); -+ test_urshl_2s_2s_2s(TyS); -+ test_urshl_8h_8h_8h(TyH); -+ test_urshl_4h_4h_4h(TyH); -+ test_urshl_16b_16b_16b(TyB); -+ test_urshl_8b_8b_8b(TyB); -+ -+ // srshr (imm) d -+ // urshr (imm) d -+ test_srshr_d_d_1(TyD); -+ test_srshr_d_d_32(TyD); -+ test_srshr_d_d_64(TyD); -+ test_urshr_d_d_1(TyD); -+ test_urshr_d_d_32(TyD); -+ test_urshr_d_d_64(TyD); -+ -+ // srshr (imm) 2d,4s,2s,8h,4h,16b,8b -+ // urshr (imm) 2d,4s,2s,8h,4h,16b,8b -+ test_srshr_2d_2d_1(TyD); -+ test_srshr_2d_2d_32(TyD); -+ test_srshr_2d_2d_64(TyD); -+ test_srshr_4s_4s_1(TyS); -+ test_srshr_4s_4s_16(TyS); -+ test_srshr_4s_4s_32(TyS); -+ test_srshr_2s_2s_1(TyS); -+ test_srshr_2s_2s_16(TyS); -+ test_srshr_2s_2s_32(TyS); -+ test_srshr_8h_8h_1(TyH); -+ test_srshr_8h_8h_8(TyH); -+ test_srshr_8h_8h_16(TyH); -+ test_srshr_4h_4h_1(TyH); -+ test_srshr_4h_4h_8(TyH); -+ test_srshr_4h_4h_16(TyH); -+ test_srshr_16b_16b_1(TyB); -+ test_srshr_16b_16b_3(TyB); -+ test_srshr_16b_16b_8(TyB); -+ test_srshr_8b_8b_1(TyB); -+ test_srshr_8b_8b_3(TyB); -+ test_srshr_8b_8b_8(TyB); -+ test_urshr_2d_2d_1(TyD); -+ test_urshr_2d_2d_32(TyD); -+ test_urshr_2d_2d_64(TyD); -+ test_urshr_4s_4s_1(TyS); -+ test_urshr_4s_4s_16(TyS); -+ test_urshr_4s_4s_32(TyS); -+ test_urshr_2s_2s_1(TyS); -+ test_urshr_2s_2s_16(TyS); -+ test_urshr_2s_2s_32(TyS); -+ test_urshr_8h_8h_1(TyH); -+ test_urshr_8h_8h_8(TyH); -+ test_urshr_8h_8h_16(TyH); -+ test_urshr_4h_4h_1(TyH); -+ test_urshr_4h_4h_8(TyH); -+ test_urshr_4h_4h_16(TyH); -+ test_urshr_16b_16b_1(TyB); -+ test_urshr_16b_16b_3(TyB); -+ test_urshr_16b_16b_8(TyB); -+ test_urshr_8b_8b_1(TyB); -+ test_urshr_8b_8b_3(TyB); -+ test_urshr_8b_8b_8(TyB); -+ -+ // srsra (imm) d -+ // ursra (imm) d -+ test_srsra_d_d_1(TyD); -+ test_srsra_d_d_32(TyD); -+ test_srsra_d_d_64(TyD); -+ test_ursra_d_d_1(TyD); -+ test_ursra_d_d_32(TyD); -+ test_ursra_d_d_64(TyD); -+ -+ // srsra (imm) 2d,4s,2s,8h,4h,16b,8b -+ // ursra (imm) 2d,4s,2s,8h,4h,16b,8b -+ test_srsra_2d_2d_1(TyD); -+ test_srsra_2d_2d_32(TyD); -+ test_srsra_2d_2d_64(TyD); -+ test_srsra_4s_4s_1(TyS); -+ test_srsra_4s_4s_16(TyS); -+ test_srsra_4s_4s_32(TyS); -+ test_srsra_2s_2s_1(TyS); -+ test_srsra_2s_2s_16(TyS); -+ test_srsra_2s_2s_32(TyS); -+ test_srsra_8h_8h_1(TyH); -+ test_srsra_8h_8h_8(TyH); -+ test_srsra_8h_8h_16(TyH); -+ test_srsra_4h_4h_1(TyH); -+ test_srsra_4h_4h_8(TyH); -+ test_srsra_4h_4h_16(TyH); -+ test_srsra_16b_16b_1(TyB); -+ test_srsra_16b_16b_3(TyB); -+ test_srsra_16b_16b_8(TyB); -+ test_srsra_8b_8b_1(TyB); -+ test_srsra_8b_8b_3(TyB); -+ test_srsra_8b_8b_8(TyB); -+ test_ursra_2d_2d_1(TyD); -+ test_ursra_2d_2d_32(TyD); -+ test_ursra_2d_2d_64(TyD); -+ test_ursra_4s_4s_1(TyS); -+ test_ursra_4s_4s_16(TyS); -+ test_ursra_4s_4s_32(TyS); -+ test_ursra_2s_2s_1(TyS); -+ test_ursra_2s_2s_16(TyS); -+ test_ursra_2s_2s_32(TyS); -+ test_ursra_8h_8h_1(TyH); -+ test_ursra_8h_8h_8(TyH); -+ test_ursra_8h_8h_16(TyH); -+ test_ursra_4h_4h_1(TyH); -+ test_ursra_4h_4h_8(TyH); -+ test_ursra_4h_4h_16(TyH); -+ test_ursra_16b_16b_1(TyB); -+ test_ursra_16b_16b_3(TyB); -+ test_ursra_16b_16b_8(TyB); -+ test_ursra_8b_8b_1(TyB); -+ test_ursra_8b_8b_3(TyB); -+ test_ursra_8b_8b_8(TyB); -+ -+ // sshll{2} (imm) 2d_2s/4s, 4s_4h/8h, 8h_8b/16b -+ // ushll{2} (imm) 2d_2s/4s, 4s_4h/8h, 8h_8b/16b -+ test_sshll_2d_2s_0(TyS); -+ test_sshll_2d_2s_15(TyS); -+ test_sshll_2d_2s_31(TyS); -+ test_sshll2_2d_4s_0(TyS); -+ test_sshll2_2d_4s_15(TyS); -+ test_sshll2_2d_4s_31(TyS); -+ test_sshll_4s_4h_0(TyH); -+ test_sshll_4s_4h_7(TyH); -+ test_sshll_4s_4h_15(TyH); -+ test_sshll2_4s_8h_0(TyH); -+ test_sshll2_4s_8h_7(TyH); -+ test_sshll2_4s_8h_15(TyH); -+ test_sshll_8h_8b_0(TyB); -+ test_sshll_8h_8b_3(TyB); -+ test_sshll_8h_8b_7(TyB); -+ test_sshll2_8h_16b_0(TyB); -+ test_sshll2_8h_16b_3(TyB); -+ test_sshll2_8h_16b_7(TyB); -+ test_ushll_2d_2s_0(TyS); -+ test_ushll_2d_2s_15(TyS); -+ test_ushll_2d_2s_31(TyS); -+ test_ushll2_2d_4s_0(TyS); -+ test_ushll2_2d_4s_15(TyS); -+ test_ushll2_2d_4s_31(TyS); -+ test_ushll_4s_4h_0(TyH); -+ test_ushll_4s_4h_7(TyH); -+ test_ushll_4s_4h_15(TyH); -+ test_ushll2_4s_8h_0(TyH); -+ test_ushll2_4s_8h_7(TyH); -+ test_ushll2_4s_8h_15(TyH); -+ test_ushll_8h_8b_0(TyB); -+ test_ushll_8h_8b_3(TyB); -+ test_ushll_8h_8b_7(TyB); -+ test_ushll2_8h_16b_0(TyB); -+ test_ushll2_8h_16b_3(TyB); -+ test_ushll2_8h_16b_7(TyB); -+ -+ // suqadd d,s,h,b -+ // usqadd d,s,h,b -+ test_suqadd_d_d(TyD); -+ test_suqadd_s_s(TyS); -+ test_suqadd_h_h(TyH); -+ test_suqadd_b_b(TyB); -+ test_usqadd_d_d(TyD); -+ test_usqadd_s_s(TyS); -+ test_usqadd_h_h(TyH); -+ test_usqadd_b_b(TyB); -+ -+ // suqadd 2d,4s,2s,8h,4h,16b,8b -+ // usqadd 2d,4s,2s,8h,4h,16b,8b -+ test_suqadd_2d_2d(TyD); -+ test_suqadd_4s_4s(TyS); -+ test_suqadd_2s_2s(TyS); -+ test_suqadd_8h_8h(TyH); -+ test_suqadd_4h_4h(TyH); -+ test_suqadd_16b_16b(TyB); -+ test_suqadd_8b_8b(TyB); -+ test_usqadd_2d_2d(TyD); -+ test_usqadd_4s_4s(TyS); -+ test_usqadd_2s_2s(TyS); -+ test_usqadd_8h_8h(TyH); -+ test_usqadd_4h_4h(TyH); -+ test_usqadd_16b_16b(TyB); -+ test_usqadd_8b_8b(TyB); -+ -+ // tbl 8b_{16b}_8b, 16b_{16b}_16b -+ // tbl 8b_{16b,16b}_8b, 16b_{16b,16b}_16b -+ // tbl 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b -+ // tbl 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b -+ test_tbl_16b_1reg(TyB); -+ test_tbl_16b_2reg(TyB); -+ test_tbl_16b_3reg(TyB); -+ test_tbl_16b_4reg(TyB); -+ test_tbl_8b_1reg(TyB); -+ test_tbl_8b_2reg(TyB); -+ test_tbl_8b_3reg(TyB); -+ test_tbl_8b_4reg(TyB); -+ -+ // tbx 8b_{16b}_8b, 16b_{16b}_16b -+ // tbx 8b_{16b,16b}_8b, 16b_{16b,16b}_16b -+ // tbx 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b -+ // tbx 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b -+ test_tbx_16b_1reg(TyB); -+ test_tbx_16b_2reg(TyB); -+ test_tbx_16b_3reg(TyB); -+ test_tbx_16b_4reg(TyB); -+ test_tbx_8b_1reg(TyB); -+ test_tbx_8b_2reg(TyB); -+ test_tbx_8b_3reg(TyB); -+ test_tbx_8b_4reg(TyB); -+ -+ // trn1 2d,4s,2s,8h,4h,16b,8b -+ // trn2 2d,4s,2s,8h,4h,16b,8b -+ test_trn1_2d_2d_2d(TyD); -+ test_trn1_4s_4s_4s(TyS); -+ test_trn1_2s_2s_2s(TyS); -+ test_trn1_8h_8h_8h(TyH); -+ test_trn1_4h_4h_4h(TyH); -+ test_trn1_16b_16b_16b(TyB); -+ test_trn1_8b_8b_8b(TyB); -+ test_trn2_2d_2d_2d(TyD); -+ test_trn2_4s_4s_4s(TyS); -+ test_trn2_2s_2s_2s(TyS); -+ test_trn2_8h_8h_8h(TyH); -+ test_trn2_4h_4h_4h(TyH); -+ test_trn2_16b_16b_16b(TyB); -+ test_trn2_8b_8b_8b(TyB); -+ -+ // urecpe 4s,2s -+ // ursqrte 4s,2s -+ test_urecpe_4s_4s(TyS); -+ test_urecpe_2s_2s(TyS); -+ test_ursqrte_4s_4s(TyS); -+ test_ursqrte_2s_2s(TyS); -+ -+ // uzp1 2d,4s,2s,8h,4h,16b,8b -+ // uzp2 2d,4s,2s,8h,4h,16b,8b -+ // zip1 2d,4s,2s,8h,4h,16b,8b -+ // zip2 2d,4s,2s,8h,4h,16b,8b -+ test_uzp1_2d_2d_2d(TyD); -+ test_uzp1_4s_4s_4s(TyS); -+ test_uzp1_2s_2s_2s(TyS); -+ test_uzp1_8h_8h_8h(TyH); -+ test_uzp1_4h_4h_4h(TyH); -+ test_uzp1_16b_16b_16b(TyB); -+ test_uzp1_8b_8b_8b(TyB); -+ test_uzp2_2d_2d_2d(TyD); -+ test_uzp2_4s_4s_4s(TyS); -+ test_uzp2_2s_2s_2s(TyS); -+ test_uzp2_8h_8h_8h(TyH); -+ test_uzp2_4h_4h_4h(TyH); -+ test_uzp2_16b_16b_16b(TyB); -+ test_uzp2_8b_8b_8b(TyB); -+ test_zip1_2d_2d_2d(TyD); -+ test_zip1_4s_4s_4s(TyS); -+ test_zip1_2s_2s_2s(TyS); -+ test_zip1_8h_8h_8h(TyH); -+ test_zip1_4h_4h_4h(TyH); -+ test_zip1_16b_16b_16b(TyB); -+ test_zip1_8b_8b_8b(TyB); -+ test_zip2_2d_2d_2d(TyD); -+ test_zip2_4s_4s_4s(TyS); -+ test_zip2_2s_2s_2s(TyS); -+ test_zip2_8h_8h_8h(TyH); -+ test_zip2_4h_4h_4h(TyH); -+ test_zip2_16b_16b_16b(TyB); -+ test_zip2_8b_8b_8b(TyB); -+ -+ // xtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h -+ test_xtn_2s_2d(TyD); -+ test_xtn2_4s_2d(TyD); -+ test_xtn_4h_4s(TyS); -+ test_xtn2_8h_4s(TyS); -+ test_xtn_8b_8h(TyH); -+ test_xtn2_16b_8h(TyH); -+ -+ // ======================== MEM ======================== -+ -+ // ld1 (multiple 1-element structures to 1/2/3/4 regs) -+ // ld1 (single 1-element structure to one lane of 1 reg) -+ // ld1r (single 1-element structure and rep to all lanes of 1 reg) -+ -+ // ld2 (multiple 2-element structures to 2 regs) -+ // ld2 (single 2-element structure to one lane of 2 regs) -+ // ld2r (single 2-element structure and rep to all lanes of 2 regs) -+ -+ // ld3 (multiple 3-element structures to 3 regs) -+ // ld3 (single 3-element structure to one lane of 3 regs) -+ // ld3r (single 3-element structure and rep to all lanes of 3 regs) -+ -+ // ld4 (multiple 4-element structures to 4 regs) -+ // ld4 (single 4-element structure to one lane of 4 regs) -+ // ld4r (single 4-element structure and rep to all lanes of 4 regs) -+ -+ // ldnp q_q_addr,d_d_addr,s_s_addr (load pair w/ non-temporal hint) -+ // addr = reg + uimm7 * reg_size -+ -+ // ldp q_q_addr,d_d_addr,s_s_addr (load pair) -+ // addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm] -+ -+ // ldr q,d,s,h,b from addr -+ // addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm] -+ -+ // ldr q,d,s from pc+#imm19 -+ -+ // ldr q,d,s,h,b from addr -+ // addr = [Xn|SP, R -+#include // memalign -+#include // memset -+#include -+ -+typedef unsigned char UChar; -+typedef unsigned short int UShort; -+typedef unsigned int UInt; -+typedef signed int Int; -+typedef unsigned char UChar; -+typedef signed long long int Long; -+typedef unsigned long long int ULong; -+ -+typedef unsigned char Bool; -+#define False ((Bool)0) -+#define True ((Bool)1) -+ -+__attribute__((noinline)) -+static void* memalign16(size_t szB) -+{ -+ void* x; -+ x = memalign(16, szB); -+ assert(x); -+ assert(0 == ((16-1) & (unsigned long)x)); -+ return x; -+} -+ -+static inline UChar randUChar ( void ) -+{ -+ static UInt seed = 80021; -+ seed = 1103515245 * seed + 12345; -+ return (seed >> 17) & 0xFF; -+} -+ -+static ULong randULong ( void ) -+{ -+ Int i; -+ ULong r = 0; -+ for (i = 0; i < 8; i++) { -+ r = (r << 8) | (ULong)(0xFF & randUChar()); -+ } -+ return r; -+} -+ -+ -+ -+#define TESTINST1(instruction, RD, carryin) \ -+{ \ -+ ULong out; \ -+ ULong nzcv_out; \ -+ ULong nzcv_in = (carryin ? (1<<29) : 0); \ -+ __asm__ __volatile__( \ -+ "msr nzcv,%2;" \ -+ instruction ";" \ -+ "mov %0," #RD ";" \ -+ "mrs %1,nzcv;" \ -+ : "=&r" (out), "=&r" (nzcv_out) \ -+ : "r" (nzcv_in) \ -+ : #RD, "cc", "memory" \ -+ ); \ -+ printf("%s :: rd %016llx " \ -+ "cin %d, nzcv %08llx %c%c%c%c\n", \ -+ instruction, out, \ -+ carryin ? 1 : 0, \ -+ nzcv_out & 0xffff0000, \ -+ ((1<<31) & nzcv_out) ? 'N' : ' ', \ -+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \ -+ ((1<<29) & nzcv_out) ? 'C' : ' ', \ -+ ((1<<28) & nzcv_out) ? 'V' : ' ' \ -+ ); \ -+} -+ -+#define TESTINST2(instruction, RNval, RD, RN, carryin) \ -+{ \ -+ ULong out; \ -+ ULong nzcv_out; \ -+ ULong nzcv_in = (carryin ? (1<<29) : 0); \ -+ __asm__ __volatile__( \ -+ "msr nzcv,%3;" \ -+ "mov " #RN ",%2;" \ -+ instruction ";" \ -+ "mov %0," #RD ";" \ -+ "mrs %1,nzcv;" \ -+ : "=&r" (out), "=&r" (nzcv_out) \ -+ : "r" (RNval), "r" (nzcv_in) \ -+ : #RD, #RN, "cc", "memory" \ -+ ); \ -+ printf("%s :: rd %016llx rn %016llx, " \ -+ "cin %d, nzcv %08llx %c%c%c%c\n", \ -+ instruction, out, ((ULong)RNval), \ -+ carryin ? 1 : 0, \ -+ nzcv_out & 0xffff0000, \ -+ ((1<<31) & nzcv_out) ? 'N' : ' ', \ -+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \ -+ ((1<<29) & nzcv_out) ? 'C' : ' ', \ -+ ((1<<28) & nzcv_out) ? 'V' : ' ' \ -+ ); \ -+} -+ -+#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \ -+{ \ -+ ULong out; \ -+ ULong nzcv_out; \ -+ ULong nzcv_in = (carryin ? (1<<29) : 0); \ -+ __asm__ __volatile__( \ -+ "msr nzcv,%4;" \ -+ "mov " #RM ",%2;" \ -+ "mov " #RN ",%3;" \ -+ instruction ";" \ -+ "mov %0," #RD ";" \ -+ "mrs %1,nzcv;" \ -+ : "=&r" (out), "=&r" (nzcv_out) \ -+ : "r" (RMval), "r" (RNval), "r" (nzcv_in) \ -+ : #RD, #RM, #RN, "cc", "memory" \ -+ ); \ -+ printf("%s :: rd %016llx rm %016llx, rn %016llx, " \ -+ "cin %d, nzcv %08llx %c%c%c%c\n", \ -+ instruction, out, ((ULong)RMval), ((ULong)RNval), \ -+ carryin ? 1 : 0, \ -+ nzcv_out & 0xffff0000, \ -+ ((1<<31) & nzcv_out) ? 'N' : ' ', \ -+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \ -+ ((1<<29) & nzcv_out) ? 'C' : ' ', \ -+ ((1<<28) & nzcv_out) ? 'V' : ' ' \ -+ ); \ -+} -+ -+#define TESTINST4(instruction, RMval, RNval, RAval, RD, RM, RN, RA, carryin) \ -+{ \ -+ ULong out; \ -+ ULong nzcv_out; \ -+ ULong nzcv_in = (carryin ? (1<<29) : 0); \ -+ __asm__ __volatile__( \ -+ "msr nzcv,%5;" \ -+ "mov " #RM ",%2;" \ -+ "mov " #RN ",%3;" \ -+ "mov " #RA ",%4;" \ -+ instruction ";" \ -+ "mov %0," #RD ";" \ -+ "mrs %1,nzcv;" \ -+ : "=&r" (out), "=&r" (nzcv_out) \ -+ : "r" (RMval), "r" (RNval), "r" (RAval), "r" (nzcv_in) \ -+ : #RD, #RM, #RN, #RA, "cc", "memory" \ -+ ); \ -+ printf("%s :: rd %016llx rm %016llx, rn %016llx, ra %016llx, " \ -+ "cin %d, nzcv %08llx %c%c%c%c\n", \ -+ instruction, out, ((ULong)RMval), ((ULong)RNval), ((ULong)RAval), \ -+ carryin ? 1 : 0, \ -+ nzcv_out & 0xffff0000, \ -+ ((1<<31) & nzcv_out) ? 'N' : ' ', \ -+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \ -+ ((1<<29) & nzcv_out) ? 'C' : ' ', \ -+ ((1<<28) & nzcv_out) ? 'V' : ' ' \ -+ ); \ -+} -+ -+// Same as TESTINST2 except it doesn't print the RN value, since -+// that may differ between runs (it's a stack address). Also, -+// claim it trashes x28 so that can be used as scratch if needed. -+#define TESTINST2_hide2(instruction, RNval, RD, RN, carryin) \ -+{ \ -+ ULong out; \ -+ ULong nzcv_out; \ -+ ULong nzcv_in = (carryin ? (1<<29) : 0); \ -+ __asm__ __volatile__( \ -+ "msr nzcv,%3;" \ -+ "mov " #RN ",%2;" \ -+ instruction ";" \ -+ "mov %0," #RD ";" \ -+ "mrs %1,nzcv;" \ -+ : "=&r" (out), "=&r" (nzcv_out) \ -+ : "r" (RNval), "r" (nzcv_in) \ -+ : #RD, #RN, "cc", "memory", "x28" \ -+ ); \ -+ printf("%s :: rd %016llx rn (hidden), " \ -+ "cin %d, nzcv %08llx %c%c%c%c\n", \ -+ instruction, out, \ -+ carryin ? 1 : 0, \ -+ nzcv_out & 0xffff0000, \ -+ ((1<<31) & nzcv_out) ? 'N' : ' ', \ -+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \ -+ ((1<<29) & nzcv_out) ? 'C' : ' ', \ -+ ((1<<28) & nzcv_out) ? 'V' : ' ' \ -+ ); \ -+} -+ -+#define TESTINST3_hide2and3(instruction, RMval, RNval, RD, RM, RN, carryin) \ -+{ \ -+ ULong out; \ -+ ULong nzcv_out; \ -+ ULong nzcv_in = (carryin ? (1<<29) : 0); \ -+ __asm__ __volatile__( \ -+ "msr nzcv,%4;" \ -+ "mov " #RM ",%2;" \ -+ "mov " #RN ",%3;" \ -+ instruction ";" \ -+ "mov %0," #RD ";" \ -+ "mrs %1,nzcv;" \ -+ : "=&r" (out), "=&r" (nzcv_out) \ -+ : "r" (RMval), "r" (RNval), "r" (nzcv_in) \ -+ : #RD, #RM, #RN, "cc", "memory" \ -+ ); \ -+ printf("%s :: rd %016llx rm (hidden), rn (hidden), " \ -+ "cin %d, nzcv %08llx %c%c%c%c\n", \ -+ instruction, out, \ -+ carryin ? 1 : 0, \ -+ nzcv_out & 0xffff0000, \ -+ ((1<<31) & nzcv_out) ? 'N' : ' ', \ -+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \ -+ ((1<<29) & nzcv_out) ? 'C' : ' ', \ -+ ((1<<28) & nzcv_out) ? 'V' : ' ' \ -+ ); \ -+} -+ -+ -+#define ALL5s 0x5555555555555555ULL -+#define ALLas 0xAAAAAAAAAAAAAAAAULL -+#define ALLfs 0xFFFFFFFFFFFFFFFFULL -+ -+ -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+ -+static __attribute__((noinline)) void test_arith ( void ) -+{ -+printf("misc ad-hoc tests\n"); -+ -+TESTINST3("add x3, x4, x5", 12345, 6789, x3, x4, x5, 0); -+TESTINST3("add w3, w4, w5", 12345, 6789, x3, x4, x5, 0); -+ -+TESTINST2("bfm x2, x4, #0, #63", 0x5555555555555555, x2, x4, 0); -+TESTINST2("bfm x2, x4, #0, #63", 0xaaaaaaaaaaaaaaaa, x2, x4, 0); -+ -+TESTINST3("cmp x4, x5 ; cset x3, ne", 12345, 6789, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; cset x3, eq", 12345, 6789, x3, x4, x5, 0); -+ -+TESTINST3("cmp w4, w5 ; cset x3, ne", -+ 0xAB12345678, 0xCD12345678, x3, x4, x5, 0); -+ -+TESTINST3("cmp w4, w5 ; cset x3, eq", -+ 0xCD12345678, 0xCD12345670, x3, x4, x5, 0); -+ -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x33566e6515990527, 0x3d7e7390195d82e2, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xe57b3a514f5207f4, 0x8ef7bac0f0ac903a, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x9d4a481b12743bf8, 0x9f014e8d2644ee47, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xefdd33d64e6d6a8b, 0x44e875422d202c19, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x5c6c9b2a7f109f5b, 0x568ee275e665f075, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x9b14b0a4fbbd2c11, 0x6b5bac44aaa93980, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x2e01dd24f43ab651, 0xe7d992b63e93eed4, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xf51464d0135fb75c, 0xcb60e536ad0b94e9, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0xca38ffb7de3bd6b0, 0xeef048dd9ed9490c, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x54ec6fe1530c7d86, 0xe7aa4d6f69edb5d0, x3, x4, x5, 0); -+TESTINST3("cmp x4, x5 ; mrs x3, nzcv", 0x401b30e3b8b5d629, 0x635a5c613cdb7919, x3, x4, x5, 0); -+ -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x33566e6515990527, 0x3d7e7390195d82e2, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xe57b3a514f5207f4, 0x8ef7bac0f0ac903a, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x9d4a481b12743bf8, 0x9f014e8d2644ee47, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xefdd33d64e6d6a8b, 0x44e875422d202c19, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x5c6c9b2a7f109f5b, 0x568ee275e665f075, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x9b14b0a4fbbd2c11, 0x6b5bac44aaa93980, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x2e01dd24f43ab651, 0xe7d992b63e93eed4, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xf51464d0135fb75c, 0xcb60e536ad0b94e9, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0xca38ffb7de3bd6b0, 0xeef048dd9ed9490c, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x54ec6fe1530c7d86, 0xe7aa4d6f69edb5d0, x3, x4, x5, 0); -+TESTINST3("cmp w4, w5 ; mrs x3, nzcv", 0x401b30e3b8b5d629, 0x635a5c613cdb7919, x3, x4, x5, 0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("ADD imm12\n"); -+TESTINST2("add x3, x4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("add x3, x4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("add x3, x4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("add x3, x4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+TESTINST2("add w3, w4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("add w3, w4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("add w3, w4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("add w3, w4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+TESTINST2("adds x3, x4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("adds x3, x4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("adds x3, x4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("adds x3, x4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+TESTINST2("adds w3, w4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("adds w3, w4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("adds w3, w4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("adds w3, w4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+ -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0xefdd33d64e6d6a8b, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x8b0a4c8f910c1a9a, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x5c6c9b2a7f109f5b, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x1f699b1d954a5abd, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x9b14b0a4fbbd2c11, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0xd55d1c942f951f5e, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x31d5b14395d5a53a, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x2e01dd24f43ab651, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0xf44e040002467809, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("adds x3, x4, #0xD87, lsl #0", 0x64d24626922b486c, x3, x4, 0); -+ -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0xefdd33d64e6d6a8b, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x8b0a4c8f910c1a9a, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x5c6c9b2a7f109f5b, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x1f699b1d954a5abd, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x9b14b0a4fbbd2c11, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0xd55d1c942f951f5e, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x31d5b14395d5a53a, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x2e01dd24f43ab651, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0xf44e040002467809, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("adds w3, w4, #0xD87, lsl #0", 0x64d24626922b486c, x3, x4, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("SUB imm12\n"); -+TESTINST2("sub w3, w4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("sub w3, w4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("sub w3, w4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("sub w3, w4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+TESTINST2("sub w3, w4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("sub w3, w4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("sub w3, w4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("sub w3, w4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #0", ALL5s, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #0", ALLfs, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #12", ALL5s, x3, x4, 0); -+TESTINST2("subs w3, w4, #0x876, lsl #12", ALLfs, x3, x4, 0); -+ -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0xefdd33d64e6d6a8b, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x8b0a4c8f910c1a9a, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x5c6c9b2a7f109f5b, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x1f699b1d954a5abd, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x9b14b0a4fbbd2c11, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0xd55d1c942f951f5e, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x31d5b14395d5a53a, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x2e01dd24f43ab651, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0xf44e040002467809, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x64d24626922b486c, x3, x4, 0); -+ -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0xefdd33d64e6d6a8b, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x8b0a4c8f910c1a9a, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x5c6c9b2a7f109f5b, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x1f699b1d954a5abd, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x9b14b0a4fbbd2c11, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0xd55d1c942f951f5e, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x31d5b14395d5a53a, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x2e01dd24f43ab651, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0xf44e040002467809, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x64d24626922b486c, x3, x4, 0); -+ -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x64d2462600000d86, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x64d2462600000d87, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x64d2462600000d88, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x64d2462680000d86, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x64d2462680000d87, x3, x4, 0); -+TESTINST2("subs w3, w4, #0xD87, lsl #0", 0x64d2462680000d88, x3, x4, 0); -+ -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x0000000000000d86, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x0000000000000d87, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x0000000000000d88, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x8000000000000d86, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x8000000000000d87, x3, x4, 0); -+TESTINST2("subs x3, x4, #0xD87, lsl #0", 0x8000000000000d88, x3, x4, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("ADR/ADRP MISSING (results are PC dependant)\n"); -+//TESTINST1("adrp x27, #0x987", x27, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("AND(imm)\n"); -+TESTINST2("and x3,x4, #0xF", ALL5s, x3, x4, 0); -+TESTINST2("and x3,x4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("and x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("ands x3,x4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("ands x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("ands x3,x4, #0x8080808080808080", 0x143fdf810277796e, x3, x4, 0); -+TESTINST2("ands x3,x4, #0xC0C0C0C0C0C0C0C0", 0xA5446fe48c610b28, x3, x4, 0); -+TESTINST2("ands x3,x4, #0x8080808080808080", 0x7070707070707070, x3, x4, 0); -+TESTINST2("ands x3,x4, #0x8080808080808080", 0xF070707070707070, x3, x4, 0); -+ -+TESTINST2("and w3,w4, #0xF", ALL5s, x3, x4, 0); -+TESTINST2("and w3,w4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("and w3,w4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("ands w3,w4, #0x80808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("ands w3,w4, #0xC0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+TESTINST2("ands w3,w4, #0x80808080", 0x143fdf810277796e, x3, x4, 0); -+TESTINST2("ands w3,w4, #0xC0C0C0C0", 0xA5446fe48c610b28, x3, x4, 0); -+TESTINST2("ands w3,w4, #0x80808080", 0x7070707070707070, x3, x4, 0); -+TESTINST2("ands w3,w4, #0x80808080", 0x70707070F0707070, x3, x4, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("ORR(imm)\n"); -+TESTINST2("orr x3,x4, #0xF", ALL5s, x3, x4, 0); -+TESTINST2("orr x3,x4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("orr x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+ -+TESTINST2("orr w3,w4, #0xF", ALL5s, x3, x4, 0); -+TESTINST2("orr w3,w4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("orr w3,w4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("EOR(imm)\n"); -+TESTINST2("eor x3,x4, #0xF", ALL5s, x3, x4, 0); -+TESTINST2("eor x3,x4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("eor x3,x4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+ -+TESTINST2("eor w3,w4, #0xF", ALL5s, x3, x4, 0); -+TESTINST2("eor w3,w4, #0x8080808080808080", 0x843fdf810277796e, x3, x4, 0); -+TESTINST2("eor w3,w4, #0xC0C0C0C0C0C0C0C0", 0xc5446fe48c610b28, x3, x4, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("MOVZ\n"); -+TESTINST1("movz x27, #0x987", x27, 0); -+TESTINST1("movz x27, #0x987, lsl #16", x27, 0); -+TESTINST1("movz x27, #0x987, lsl #32", x27, 0); -+TESTINST1("movz x27, #0x987, lsl #48", x27, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("MOVN\n"); -+TESTINST1("movn x27, #0x987", x27, 0); -+TESTINST1("movn x27, #0x987, lsl #16", x27, 0); -+TESTINST1("movn x27, #0x987, lsl #32", x27, 0); -+TESTINST1("movn x27, #0x987, lsl #48", x27, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("MOVK\n"); -+TESTINST1("movn x27, #0xdef, lsl #48 ; movk x27, #0x987, lsl #0 ; " -+ "movk x27, #0xabc, lsl #32 ; movk x27, #0x5123, lsl #16 ", x27, 0); -+ -+//////////////////////////////////////////////////////////////// -+ -+#if TEST_BFM -+ -+printf("UBFM(64)\n"); -+printf("SBFM(64)\n"); -+printf("BFM(64)\n"); -+ -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x643c986966334873, 0x6b8b4567327b23c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x2ae8944a625558ec, 0x74b0dc5119495cff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x3d1b58ba507ed7ab, 0x238e1f2946e87ccd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x79e2a9e37545e146, 0x2eb141f241b71efb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x122008544db127f8, 0x515f007c5bd062c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x1190cde766ef438d, 0x0216231b1f16e9e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x109cf92e0ded7263, 0x140e0f763352255a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x41a7c4c96b68079a, 0x7fdcc2331befd79f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x519b500d431bd7b7, 0x4e6afb6625e45d32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x257130a362bbd95a, 0x3f2dba317c83e458, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x333ab105721da317, 0x436c6125628c895d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x6763845e75a2a8d4, 0x2443a8582d1d5ae9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x4353d0cd0b03e0c6, 0x08edbdab79838cb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x71f324542ca88611, 0x189a769b54e49eb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x3a95f87408138641, 0x0836c40e02901d82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x737b8ddc6ceaf087, 0x1e7ff5217c3dbd3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x3006c83e614fd4a1, 0x22221a704516dde9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x440badfc05072367, 0x419ac2415577f8e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x7724c67e5c482a97, 0x3804823e77465f01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x51ead36b2d517796, 0x2463b9ea5e884adc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x3855585c70a64e2a, 0x580bd78f153ea438, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x1d4ed43b725a06fb, 0x6a2342ec2a487cb0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x7a6d8d3c4b588f54, 0x2cd89a3257e4ccaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x38437fdb7644a45c, 0x542289ec6de91b18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x579478fe749abb43, 0x32fff902684a481a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x79a1deaa75c6c33a, 0x3dc240fb1ba026fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x520eedd1374a3fe6, 0x12e685fb70c6a529, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #0", 0x649bb77c275ac794, 0x4f4ef00523f9c13c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #0", 0x180115be235ba861, 0x393865751cf10fd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #0", 0x15b5af5c741226bb, 0x47398c89354fe9f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x3f6ab60f61574095, 0x0d34b6a810233c99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x579be4f1310c50b3, 0x7e0c57b177ae35eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x25a70bf71dbabf00, 0x5ff87e052f305def, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x1381823a5db70ae5, 0x4ad084e91f48eaa1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x15014acb5f5e7fd0, 0x100f8fca6590700b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x06b9476442c296bd, 0x098a3148799d0247, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x661e3f1e5dc79ea8, 0x168e121f1eba5d23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x51d9c564613efdc5, 0x540a471c7bd3ee7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x42963e5a0a0382c5, 0x0bf72b1411447b73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x3b0fd37968eb2f63, 0x08f2b15e1a32234b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x06a5ee6414330624, 0x4962813b60b6df70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x71ea1109100f59dc, 0x7fffca111a27709e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x6f6dd9ac094211f2, 0x7fb7e0aa06eb5bd4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x4c04a8af1716703b, 0x00885e1b76272110, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x74de0ee368ebc550, 0x14e17e333222e7cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x4a2ac31539ee015c, 0x2df6d64846b7d447, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x43f1842260ef0119, 0x57fc4fbb0cc1016f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x49da307d7055a5f5, 0x26f324ba7f01579b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x0488ac1a5fb8011c, 0x5fb8370b50801ee1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x6fc75af86a5f7029, 0x6aa78f7f7672bd23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x73a1821b7de67713, 0x7d5e18f85f3534a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x14fce74e6a3dd3e8, 0x555c55b53fa62aca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x532999381fbfe8e0, 0x71c9129809daf632, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x59adea3d288f1a34, 0x5092ca791d545c4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x097e1b4e51088277, 0x2a155dbc1d9f6e5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x415e286c7c58fd05, 0x1ca0c5fa53584bcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x5c10fe210e7ffa2b, 0x23d86aac45e6d486, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #1", 0x78df6a5539b7aaa2, 0x3c5991aa4bd8591a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #1", 0x379e21b50069e373, 0x2b0d8dbe6c80ec70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #1", 0x6aa7b75c1df029d3, 0x2c27173b4c9b0904, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x3db012b32708c9af, 0x5675ff363dd15094, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x4f97e3e4053b0a9e, 0x5b25ace2175dfcf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x56438d15519e3149, 0x34fd6b4f5915ff32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x4df72e4e5046b5a9, 0x2c6e4afd17a1b582, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x5ec6afd419e21bb2, 0x5d888a082a082c70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x5399c65420ee1348, 0x75e0858a57a61a29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x2157f6bc704e1dd5, 0x4427069a0b37e80a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x0e3e47a82e48f044, 0x57d2f10e0bffae18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x5551b9f324f6ab8e, 0x49d0feac4bee5a5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x2a31b62d1849c29b, 0x634c574c24e99dd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x69e7f3e52a6de806, 0x7dff9d0900754342, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x7ab49daf759f82cd, 0x1816f8c437df2233, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x0f819e7f57c7d42d, 0x61e74ea3597b4d84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x78b5e77675486e47, 0x312167ad631b64d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x65968c1c46263dec, 0x6e534cde1a0dde32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x746f2e306fde8af6, 0x260d8c4a73d4d3c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x14d53685230f856c, 0x3fc32e2049c0e823, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x3b5948076caa2304, 0x6eaa85fb3f06ecb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x17180b0b579328b9, 0x3f7c2ff425413bec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x4d32ab863f07acc3, 0x5d205e2011cca8ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x16cf80f11c695dec, 0x6b47f63e5cb44a05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x11b1cc332e22fbb7, 0x3fcfaed90f856867, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x744939a34fa0d2e3, 0x2993469977485850, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x3f7f5dd92ae05a34, 0x6b1d2c1468b867d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x4defdfa02123d5f2, 0x32794ff75454945e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x0dcdf8f652d7b105, 0x135b8110094927a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x2a6ad9be0baac1b4, 0x2e8a639424e60401, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #2", 0x4ab26e7821faa2fa, 0x36b2acbc779d8544, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #2", 0x3e6400e614217e23, 0x5451cf496181ef69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #2", 0x424479da1a9a9e69, 0x710757d05015cd1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x6a3b714c327b517e, 0x475e256a368db37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x5d5babb351bf6b48, 0x1f461b5129bacf25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x72e3413a116ae494, 0x7e0f63842b4b8b53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x64429599631f1690, 0x3494b2fb00b13a31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x6ec9d8445c49eaee, 0x25973e320ead6f57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x7e448de95a9cc3e5, 0x064af49b397c46bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x6ebe42080c058df5, 0x1afe36253ca88ecf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x26a02c5e541c8153, 0x0cbe5be93102bbe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x0697d2d206d68ab2, 0x67906f6010db9daa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x5895f5fa38a5d054, 0x3a966cd063f37e85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x4a10b4e843d3bcd4, 0x0f3f09d84b793735, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x26f2d36471c1af98, 0x4c2a71662e534a82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x4e0b9a87434bae75, 0x3d00b9d915bcaba8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x1de8725a6a37288a, 0x4f38f2654c502870, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x763cb68015b71329, 0x08f8b73f0ca6b462, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x69d3947c2539dfa5, 0x3da970441cdce2de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x2c106a57684eed59, 0x2db88089706b674e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x20f4bdad639defac, 0x545ee5d304a66051, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x2771ac801c4a08ec, 0x501f97866b057295, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x0e0bb885565976f1, 0x1958bd174e647fe4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x19a52566335a1df1, 0x64212b8c5c17530c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x1d91467c316032bb, 0x28677b7c378d97c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x471745e401ddbc66, 0x44344c2213cdfcfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x27179c0b5e636063, 0x30aadfda30eada61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x46b24dbc75b52783, 0x215641af53280662, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x5953172f27edfe3a, 0x57ce66b467a70b69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x443807276c053b16, 0x52ac7dff00c4c3af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #3", 0x425eb207334a6f1f, 0x4f2943935243bfac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #3", 0x66a48d1156c28e34, 0x2e5b12b85c03d76d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #3", 0x0822c0ef57c5bb4f, 0x13916f2d0435d38d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x59a377b648aeb063, 0x1803d0894f3a06d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x271210c7217b22e4, 0x0024e13500bb13c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x17304a672bb180d8, 0x53e31a246dc45e83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x539f7f122817e7ec, 0x556b69ed70836196, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x141d2302407168d8, 0x7148254517d78639, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x73bbd7f81876589d, 0x6a1b45e5567bd50a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x6f38e6d146111ba5, 0x327fac775a606509, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x1dd6d6f4769a091f, 0x5e963896775ba7c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x3f48b98246ba8fca, 0x4695ae95777a4eaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x6835b2ae4c187c90, 0x7835626c665aca49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x77c9fd68298a92ba, 0x541f28cd7f65fd16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x51a27aa6613183f2, 0x6fe95eac4b697c7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x21a2ecca4d5c4899, 0x634102b465bf9da8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x65d2a1376ebb1f2a, 0x3c3b72b2155ec4c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x34cc3acf4e556261, 0x6fbf29cb550b8808, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x44ef6b8012fcde5e, 0x4c672fc952a311c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x59b76e284252c2da, 0x4a1d606e04382503, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x0e6b3f6a3eb21819, 0x6a92ef4c41ed20d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x683caad3313c7c99, 0x41531ded06353cd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x126e008b34dfbc00, 0x519eb94c39df2579, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x023c049a5bda35d4, 0x1f9ec3223410ed56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x4a9554fe392edbe4, 0x496fb218680ea5d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x07843e4509815da3, 0x3d1a2dd97f618fcd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x1c7e3c011c2201ff, 0x5204a1914c73a9c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x5e74c4d93b3ebe15, 0x50abcec97635aa2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x79f0d62f7975e8ee, 0x3822cb016ce00443, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x2ab2658744b3fa61, 0x73154115622d8102, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #16", 0x7993b6623bab699e, 0x1c0ca67c3d206613, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #16", 0x17859f723aa10581, 0x713153697bcfbafc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #16", 0x73cfe16520f88ea6, 0x63de60cd621af471, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x2a79ec49338125cf, 0x617c843e7b541fab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x4fa327ce1873983a, 0x47c7c97146f8284b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x53b2564f75509d76, 0x3d2dd2752e17eca7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x6ec686640e0d31ff, 0x1af7f0ea4da32c7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x52c12c614bdd53fd, 0x2fd0ad811978ebeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x0788bd9b47caa567, 0x569951fe4c54e2c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x026baae92c02fe8c, 0x48249dbf1f0e5d0d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x4cfb8d3262a5d5bd, 0x0129517e763b8c4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x1626fb8c3957756a, 0x718fabf97775797c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x51cb0da47b9b743c, 0x3e6da1c765ca235b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x70ec11b22eda00ed, 0x13e21002257d63f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x3ce732ec22f13df3, 0x732090725fb29816, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x6ece91f04fc4d600, 0x792b84010fa85f4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x178f7b672421dfcf, 0x5bfd421076574f8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x5024de5b168efe17, 0x1565ac9919fb2650, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x7934d3d401c65e98, 0x1036b29f1d206b8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x3b1dd403530386d1, 0x1495e50a0f5bcf61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x4e9efb0d090802be, 0x7525f2bc0ce8e1a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x37e203ab2586d60e, 0x3266459b3f8b0cbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x48781401186928d6, 0x1f3da4d574c93698, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x682dfed6606ed7f6, 0x047195e53746a5f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x0490b7c54303a216, 0x2d9df57d7fbd7a3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x5992a02e29ef532d, 0x19b8a08e54b59621, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x2bb5b1c6066be6b9, 0x71d601af52c77402, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x596f6d8a5749361f, 0x6223436366d385c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x605138de2622ad0c, 0x73bc6770280e6897, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x4ba9831a06d71a2b, 0x6799755618333c89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #29", 0x1f404301116e0907, 0x0cfc73211421971b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #29", 0x71dce0fd7906328b, 0x4b683d0d076e41d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #29", 0x3c09d4a120e45ca4, 0x072bbc16766d98c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x4ad3afd23cf93092, 0x4b232ee3159c74cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x4365174b4a872c35, 0x6863e8d276896198, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x21d0625551194ed1, 0x5d5ce7611cd484d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x773bfbdd2c7c62c2, 0x44e2ed6c02219b33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x33537ced27514ade, 0x1a54d7bc42e57ef7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x38bf53e5226f5320, 0x570716135293bfef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x1b7585ab612dbddd, 0x5a0201c72a9c34e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x02121a816c2cfc88, 0x2109cda4577f5a4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x29262d1a557fb7ee, 0x6d1bcf1c4ce5ca53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x2006e42420cc134c, 0x436f2beb6c8b4466, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x71e5621e4e42b6a8, 0x095fc93b41d74679, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x7abf196a5e4db968, 0x43f8e1ac69215dfb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x059f0446030df306, 0x2c06dcf32e129658, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x257d46265aa8580e, 0x00a656473e5e582b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x3bd615eb0a045ab2, 0x68fa8d0d40f2cbd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x7631573a058df53b, 0x1872261f3de8306c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x5b0dad2a4e3d26ab, 0x0acdfac01f578454, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x6f0939f8154291f6, 0x0be2c8ba7b14914e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x6385489e00e4b973, 0x3cebd7c760ee9c16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x5f3272db7616d704, 0x4a0ffa115e446208, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x7924ca0a0cfd4ea7, 0x0c56f86064d17722, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x67a5a6b50c2a5c5b, 0x232fcf4d1ea21031, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x162eb70d78070222, 0x5f94dc03237bbca0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x7d94f75d6c31e7cd, 0x6163ed0d0c600e47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x3a6f0e78379a5b56, 0x2bb7929b58a2a487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x4cdced4c10a30d9c, 0x53b735d529784870, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x1187c70f5476de98, 0x0a66e486306235ea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #42", 0x4a8db59c1afd9053, 0x0ea697f270ba39eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #42", 0x27fadefa78bb805a, 0x558bb10d43b27fa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #42", 0x04e5dcb541e96bdb, 0x62548fd80fa085b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x39f06dfd14802f5d, 0x331c42501b1493c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x00b2172a532c34a5, 0x2774a2093785655a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x0ac68ffb63df3fb7, 0x102809e23b2125a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x74824d546f00529a, 0x64996e1357a37d47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x4377313216ac4b23, 0x0805b331060a1463, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x31a9db764c4fff5b, 0x76c44e4e0e04e6ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x450b7fb6340bf64d, 0x51b7667559a4ba71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x75f562281c618271, 0x6945402149f15c6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x30e1b1cf0c7a9237, 0x6505f02e2fe5d025, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x5fa6c6dc77933f62, 0x676b35803193c8f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x5b727f19514e5cb0, 0x6cb4ee9c6a6d56d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x404eaf4a4a16874f, 0x4210d41e4ff4cc6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x60c2d2734cc32f1f, 0x55fee0d103c5e07c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x19132e7b63822dc0, 0x11cac74a126cade9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x178e240d5556a87b, 0x6c11685a5e1eae31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x71b82aed0d15faca, 0x28100a9c0d838636, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x19908d0224d48bdb, 0x3d69565b2299dcbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x1c67cb3d40e29452, 0x542da5b5793753de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x1230f10225b57ed4, 0x63a4aab677da4a57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x6fcc06241dcdf795, 0x47cf16c4527fa04c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x6a9126b568104812, 0x564580c8508ed897, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x4b9275d24f0ceedb, 0x62fb868003a45530, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x2463975609d30dfd, 0x61c30361632099e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x16e908c82e0d7671, 0x70a42016161bc243, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x52e2024d0ce344b5, 0x38b59eff307995ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x4dc5d9070d55945e, 0x29b0e9a86f49cd8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x330b13332ef32ea6, 0x672417e15ff6ca09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #55", 0x4cc1263b08bbeb1d, 0x32766a5522d71957, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #55", 0x70cc332f5661786e, 0x7365f1ee37524cf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #55", 0x256e67491cb9a581, 0x3af6a2203c5ea902, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x268cb37f102362f8, 0x1f7f42e249d1fea0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x3e30d96918a35fe3, 0x5fedc0e33d75bc47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x2586a49817a03bb9, 0x6def52111112dbb6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x24f5d0186780c122, 0x005ca941734c7d9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x1673efc805b9b1fd, 0x534347a85800e34b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x0e759d1a6e3dee90, 0x7ad7fca263351604, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x449f66fe557e0515, 0x1a8762f47f41d049, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x7237aa965b1fbc2d, 0x3ba0794b6a0dce48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x6b431f2513cd8dcb, 0x33dfcce818c45e15, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x2c70edae44296c6d, 0x563a1a5c2973f88f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x5bc9a8273ae37d86, 0x3a86d44551f79246, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x22643ea91887578d, 0x45440fe500bf783f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x1e41098a5398582c, 0x58c05b8a38d82e71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x41d646bc3694a76a, 0x1c0d44752cb6a6a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x0c12ac7f6798f039, 0x2bf876ee0675adba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x42b8ac67246348ea, 0x70837c027e4a5715, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x3830d6b66d48cf87, 0x170eb52b2dfbcb8c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x31723bf511f69861, 0x576fc41b64a1c464, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x4cda15e77bdd6690, 0x369956ab0d3be41c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x1464be1e66bbb7e5, 0x0dfb5c5b6f3e5490, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x3a5410114423c777, 0x2816830232a5c7a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x7ab86ee10b54e53b, 0x5f5c6e4d7c2a56cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x72edd5747323808a, 0x02a0048706cb1b60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x1786c9741c2427a1, 0x0515727635a681db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x096cf7283b121183, 0x63a24d684fb7a02a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x4d08a9e46af2bb3a, 0x3459648f3adf331d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x66d021ca56167394, 0x481b173919e2bfcc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #60", 0x3cd22b793137975e, 0x0921145c7b34dfe8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #60", 0x755b5ed60d3715de, 0x2ddaa79177263b8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #60", 0x188bfb1975f096df, 0x735092577013cdb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x691417697bf45b8e, 0x76dee9180b79d08d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x1818832f24c29fd1, 0x41205269009ae0dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x5fd4b15404abe597, 0x5052810821857a57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x6f9ea0d1247fc4ae, 0x5c64ad752cdd5b39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x7a9638434fe12f61, 0x46c01b05566ec29b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x0118c6c07f7e4a15, 0x51a3a284376863bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x0cb55ff321df319e, 0x2e8e9f4776742596, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x17cfc87d5d66dc65, 0x6687f34d25415b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x595b37f371db7e02, 0x30bb2b9900e3dfe6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x169e1dd351d141cc, 0x017ec0c47173bb22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x567d27636f5de2ef, 0x12f9357a7672cf28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x13dda79d6a104566, 0x23502a61461bc834, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x39f174c76e2e2d53, 0x1c8a8acf0e73dfe0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x6dac7768746ae2e4, 0x45dc439d3b0a3b87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x164a14821806546b, 0x317e611d7a61d75b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x756d30d0505e5e01, 0x1fa332672e19dd00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x4239dc03307c7daa, 0x2efdbce64ec868c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x024dbf7653355960, 0x403c23e658d7f9d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x42933c4f729af360, 0x4f4ac8ff58cae6d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x5cab38c63b7139dd, 0x1ee6af0d5670e3ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x299f67302ac1076a, 0x64e4c3cd169cad8d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x1f2bea4e03254a32, 0x51a6e915174bde99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x1b2b9e9d3150e85c, 0x11adb5f43575fed1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x01af465d128d98b7, 0x638fdbd11098cf6e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x430a16621f9d5c18, 0x5f61383243e92260, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x72d2b5796c0be536, 0x1cc11c374557d5d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x5ea6d8963d096bbf, 0x1e22bcb23565f1c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #61", 0x787aa59c70bb9983, 0x0bd6d5b53b52115c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #61", 0x1b7ca0ed2395a7ff, 0x51eebeea221a0ccd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #61", 0x26baf2314b13a15a, 0x3965eb663aa88b3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x7c6489b653ae65de, 0x701e8a0d41e690cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x663bfe9531e0986f, 0x527f603d7e13d013, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x517df4875ebe0eab, 0x41fcf274294614f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x4ac9f3e20cc0a782, 0x6e9dead04450aa00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x49ca1341058d717e, 0x79b69bc92970cc78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x76490b0136b19cbf, 0x64c2ddd54244b8de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x5a4744be1dc4b111, 0x645ec5ab11c5abef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x68d8526b3c8cc138, 0x4c6e372b010236ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x103b2716156827fb, 0x42e8c7be653cdc22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x4748c06a254d9ea9, 0x6350ac35767725ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x040bad550e5b2573, 0x1fbd3aa318c6b4f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x1b1bccf556cdfabb, 0x5d175ef24ed5a137, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x5c5b6c3a5d094b84, 0x78466daf64e5e036, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x13bae8430b895ebf, 0x272a991452a4773b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x294e0fd030d85a55, 0x646a232a6e022d01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x6d651b8d31ed2baf, 0x6f0463f11226623c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x475553ab5ab3ea93, 0x77633e5e7da042a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x0001893d13d4a2f2, 0x7417684f0e9e1415, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x222fc865047c27fa, 0x2764c907040d3692, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x5b4a22b54b294578, 0x52e2d7c93d4b955a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x283290fd495c0ea5, 0x2231759037a58eef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x54e56d646eb42955, 0x0a4a062b3bed7940, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x1f8c83ab18f40a33, 0x29efa6427e337d35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x4ae135e207bd1dcf, 0x1059df710cf19f38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x627108627ea94a2b, 0x0a91e1dc1236898d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x127ded1d483966aa, 0x20d49da36272919f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x4cb58ea439629ffa, 0x667fc83134adb582, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #62", 0x048be573142ac06c, 0x71f94adc27ffb15a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #62", 0x5d86cf1169ef4674, 0x5fa540492cbe7670, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #62", 0x58a36fca129b95f2, 0x68abefb0326c3c76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x2b8fa02540f9991c, 0x309fb9ab782ff375, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x48b6b6eb0fb37489, 0x052192ad7670d608, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x0e5cbeb4297bfd38, 0x08a75f952b27bf4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x71b563e3741a191e, 0x0d9a50ed20daabd1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x2d7cb9194781ac2f, 0x558861533e6af287, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x5bac6c9c460fe42b, 0x666aa3e132089e8c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x2fff2a9f477304ac, 0x5ec714fc39333bad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x5a0e9a9f1c3f31ce, 0x6b9f782308a29a69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x5d38caea05f4208c, 0x00d28dde059e3ac4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x15a7951504b67062, 0x7c0f10cc25ef81d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x2e326d9a5eb19210, 0x51174123240453ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x52cbab2e1a6760ef, 0x44deff9b1fe7d17d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x61e90d1e44bd67e6, 0x5e52c40500486447, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x0acd4c11111817cf, 0x325102d33d9579ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x588b1c7c62682d8b, 0x76c8b5683acc76b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x7ea75f5a44419ef9, 0x436f111a3299b71b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x4a35bf85344702ac, 0x3837f1df5be02a44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x38fd730e52e6ed3d, 0x01cfac1a5fdd549a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x31987f4d48c0a800, 0x03e1a864672fe0a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x632808ef656a762b, 0x0717b22604642a7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x2a27de1136fd9196, 0x04ac8ec34511160d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x4815a966796f4530, 0x02a68fc834f52a23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x5bd772bb3330b1ee, 0x6fc1a0d420a0c5e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x777250e70b726edc, 0x533a7cfd5a7ed215, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x3fb97188382ea874, 0x365efc5a41a8106c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x0b1595b125670d6b, 0x2185650778b6e496, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x6e27b56b66fe7765, 0x5fe6c53f3cae14fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #0, #63", 0x4c68ed9045bece3c, 0x41123f79514fbe5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #0, #63", 0x7cbc5fd319076430, 0x1660d4687690cba1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #0, #63", 0x1276a9601b479698, 0x2b85f5c444d20939, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x4e78488738ad4c18, 0x6572cf1b6e4e1c1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x441fbaf47f2bea8b, 0x48ccee3145ea996e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x375a92ff29180ee2, 0x0792a9db03d92c7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x4e7f1c4d5c76d652, 0x7c901113427028b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x43754db740307d27, 0x7f1e3dae3ca6d1b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x05ef4b642457647b, 0x0df690130fde3b47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x3d5ec8ab31f4fcad, 0x066f06e902abab37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x4d3c93462cf0838b, 0x477db4704fd5720b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x659dcfa306f07c58, 0x3e238e271bb4dbcd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x061c66e369321f16, 0x619f753b29bd8a97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x124a2df82a26c828, 0x2d96b7143d76f9e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x069d9e7a7f056040, 0x7fe7229260c94a46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x3f35dd672b66ac12, 0x1d701bff4a12ec32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x4fbe108e60602e62, 0x59f12779452528cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x12552b100f4e8872, 0x47d0d4020d1cd939, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x3c3f0bfd1b15d96c, 0x5cf24b455f91be56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x220655c45ce60f5e, 0x7b469a2321dcdba0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x46182e7579311d4c, 0x4b9a66382822bca7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x2357e5746580d91b, 0x6599b68958625c6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x6486395b569bc2b2, 0x392ba6b329f583ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x02026ec54df9979a, 0x7408702123bc16c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x2e59c5fd30b21390, 0x68e13f8e51c07f53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x40009c033bcfa3d1, 0x5edd588c40aef10d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x56e57d3d1b874986, 0x2040af637c3fa800, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x786d58e469b6e9d9, 0x1e1c83a178ebd301, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x62e8072506a84631, 0x210e8fa83e858759, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x6c291f4c50138a7a, 0x16e7e3c7063fec9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #0", 0x26af4d2d243de0aa, 0x3035708950af58a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #0", 0x723778445d4caef8, 0x746b6f6a28b1bbf2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #0", 0x0dfec288594f93d1, 0x7a723b4520913e41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x151f37a30180deb1, 0x61402f4e4dff5e8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x1d082837685b8a2d, 0x4a3f068c6c04b4e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x5212740605ff178a, 0x64f087e21575811c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x0ca75dbc6ae2ec3c, 0x53fb087534fa7b2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x3af676b76b6fd84e, 0x3b3a67c578d07d08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x0fadb8f83deb451a, 0x497fd5b061a5c3e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x1b37f41204c9bb1b, 0x0a577fd601e5313d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x5e194eec03b69ecd, 0x22766f7e2936b69a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x05377d7e41751bb2, 0x773615267338868f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x29d0a5df442dc352, 0x5f3d3b70223fa5b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x4a2cdadc0bb02f47, 0x37b526d27be319e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x76931b846c17fcd6, 0x30dd951056d43898, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x5787d52419248b51, 0x4fa4b5a13189923b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x570fd06b1d86d5f5, 0x132f561f67358e1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x225091100b912ed8, 0x691abf5a7247c47d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x0f47cda512b4903d, 0x1b7e7b170069dffc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x5429abef52dfa1fc, 0x73a2668c147f4b24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x170d654e6e7417ac, 0x36bef0da7dfa51ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x7a2446f32abb00c4, 0x79dd6bb3613a402a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x16d2fd9a07b32e64, 0x380e78c370b76277, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x20d7b9b535704ad1, 0x2240f4b26e5ad2be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x52f720c63eab2035, 0x559060db77e78a20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x4a3c4f0e05adc9b4, 0x6a2f4e9d7547b1d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x186259f26953f85f, 0x75b191d359841cb3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x3c339a5b24c258b1, 0x6e0367d76c8c05e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x1336705d6463c363, 0x6a8657b05340ffa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x0f1ec4276c89b896, 0x347b3fd30d5ab751, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #1", 0x743ce6fa20530e7b, 0x7e1219c825f1c1c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #1", 0x55c3594c69dcf55b, 0x144c94801514a0af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #1", 0x28881591772b796c, 0x0cfc2acf28ba7a13, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x7cd9432113b3bdbc, 0x1e022be972c4649f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x7d07b61b3a4be92a, 0x4c488152153b9d13, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x5f0e41db6c4dfaa4, 0x01c7a2f4393b5076, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x50b1be0840f78ff3, 0x0c7c501f7244b239, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x2d8148897db18352, 0x7f9f698a5fd0822f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x1e0491cd1a0ed871, 0x05c243f121be2f84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x03ebcdcc43cefb03, 0x36d2d03373c7eb1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x3afa746f3a849116, 0x1c82652d2c73e35d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x4e384ed36b80c94f, 0x1f3847fc37d3b790, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x25ccb2794ed6f798, 0x4d0f54a34b4004ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x3b24f23c10f7a584, 0x047b556504daf454, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x51ef357776bf1017, 0x771fa68d0bd6b044, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x7470936a71697665, 0x6ba732747f707e01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x0b784ed658017db8, 0x212ead8512752537, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x1bd078bb22bf757e, 0x063d10510f641ca2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x5d4406955b1047fc, 0x3bd8000056caed2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x4691114b5badf95f, 0x0e9ea4bb2b7c5568, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x2a84f0f77b37afbb, 0x76bc5a566c5dc3c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x0c2f554068585ea6, 0x7138b81965a9e333, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x5f176ebe5d27c5ec, 0x718093785e1e8ab7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x4e913c517ebdb63d, 0x5d8f08b853880228, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x56bf33f66c3a37b1, 0x65fd275f5a098b27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x0ef9ad2f2545a7c9, 0x696da7c9728facb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x0055efc657f93e98, 0x495a99dc6c3db3c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x33a737f70e766383, 0x17ba092c46e70111, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x09ae133e247d7cef, 0x3344c4d65e2c28ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x0cd5db9535569f99, 0x43d60c2115dd687e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #2", 0x127e6585518afbee, 0x73fbf3366bed4a53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #2", 0x5048b22c257273db, 0x3f754c7b610fa1d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #2", 0x11acab8c2486d4c7, 0x3b192cfd2707e622, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x49cc7c9062f22cb0, 0x199792d320a658bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x3aeb6b48249e15ac, 0x0ce40c804a226c56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x3314792f444e323e, 0x11096d686e92a33f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x68cbaf2d1094d84e, 0x4cbecc2d3cc28c6e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x45eb77e8469be822, 0x529ff4ec75a18ac2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x1826e41121042191, 0x618ed5165869dd6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x4676956c7492ac41, 0x39797f44686f963d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x19198108290f0f32, 0x0f777c5f582340f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x0c013be205ada634, 0x78c999b462e5fd99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x2a4bbbe03e11d757, 0x2d0869ef46eca72a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x02600995023e1696, 0x357f4a695d603510, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x12d2eee56cc2b66a, 0x1a22c17e6b2bb8c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x335e9e8d425c189b, 0x60cd438558be66cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x63603a2c6aa1c37e, 0x3128443a4b85829e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x5f346fc0436c953a, 0x33f518db29d6cf99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x6c7ba46c7ac3aa45, 0x01fa1091784df0c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x00715079083c5851, 0x5b33ee61787ce04f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x464e2fa874e8d1e3, 0x3f6987792abd0c5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x7726e879224002e8, 0x081d416a48ae393e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x0f02b95214a73585, 0x33d9f20009f9d75e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x57034e2013e08266, 0x62b83e2b426157df, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x7e8245e441dbf358, 0x0de6da7d3a63884d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x0548889266346877, 0x643a57e65db6b5a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x60f812bd313894ce, 0x5604a66d71c42cff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x3974ed1f29aa94c7, 0x6a410d4e61696336, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x1e9366aa1443b0fa, 0x0c266f907fc31cc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x3683b3e27c4b4806, 0x4871560615ba4f24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #3", 0x10f27d8c026c64ae, 0x1fb4268245866d35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #3", 0x164ce71415ce9f92, 0x07e7c51467f5cbac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #3", 0x57aa92ea0693abdf, 0x225953f914cf2cf8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x6cc81457488a890a, 0x7285e29d5cf31b7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x79c31dd838f855ca, 0x4eb7487c4dc02714, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x62a2ea913b4ff9db, 0x2f298a4a33380af8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x4f93aad57b6c7dc6, 0x32fb27c00136513c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x77b7c5cc36a4c6e2, 0x16f0a06006175eb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x39112b9053859101, 0x4b9dcbed08aa4358, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x6954309312f962fe, 0x70a00f054f5e12a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x198d0ede56b3223a, 0x642d3f9d40fec37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x1f3dab446ca92777, 0x1df1defb06552335, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x25a17d41033ed493, 0x54154a491900c91c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x3e8ece6e7f33fbd4, 0x4c38d414084467d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x7aa0799a206b596e, 0x097ab90e0e227944, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x571020515fd7a3e9, 0x1439d7fc72583f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x335d34ea6ba291c4, 0x7b0282bf10214be1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x7e9bf4c343ac9e23, 0x5f7f5e861cb1657e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x1a5fc05d7ba207f7, 0x5db028fc182903a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x684b2f6e7293711f, 0x1e7e26d6399d6ba1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x75d245b21ed708d2, 0x529e34bd0decacaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x1e0b04a61fabcd90, 0x1631148134611421, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x401726fe56bd6561, 0x42838d6518ab7e41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x3695094a06064067, 0x0b03bda81727474f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x71a8d22c06c7f1b7, 0x2748933169f23e34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x4a748fda6453ccae, 0x06a3a3b27044c6ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x5ff5d4a526ebf166, 0x086dca9064d45037, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x197f6285710ff095, 0x1e71bbd848410413, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x0fe6f9676c5ec544, 0x562db0c20f51a837, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x0c0a92d4063649bd, 0x43b2bc582df1fe0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #16", 0x5cf3af1e51a139f7, 0x469d7c4f4c21b9d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #16", 0x57a77a5e0a919453, 0x634901221388b868, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #16", 0x1159860a041e9a4f, 0x7d7af69d49504c8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x687266fe4202de09, 0x399513795bce15e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x68eecf6f5f1421f3, 0x40a2661b48683ba3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x5024128866d6f079, 0x10a93fb7026e31f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x5335b5bd55729684, 0x11bfda2c600b0bf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x5ba8e042549a864d, 0x0dfd09fe5f404891, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x263bc0440eab0386, 0x2b620264389c8f60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x193c97d949a03e66, 0x4c2547c97de33aa2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x4dbed8b500c89aa6, 0x4733872d2a961de3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x42cb78b0470699e2, 0x066433c736313fb3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x261abbd50f42bb0e, 0x7e997b572bba481f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x7619ab873fe85440, 0x2e287a14763ece5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x155aeac46446e44b, 0x5649da4d494f6145, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x38e16a9853f1ac3a, 0x288fa9d67103cb06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x629cafc075c5a230, 0x29a05a675f1d2adc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x3f65e0962433ecac, 0x5d00657f7bd94799, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x24fc87522cd39943, 0x266f657c0d24b94b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x73da332541ef7456, 0x4355f8ff67c80002, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x51322f6441aac236, 0x1382482219f4eefa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x01931676667d97a5, 0x1033bd58474bdaeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x4ac47bf1392ae607, 0x109b3c3016ee013a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x0d1c9241319226a8, 0x07f1cc4103a5e689, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x2757c8d83fc376e5, 0x62c311666fb94202, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x63f763911201ef18, 0x6b92899b66bda96e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x3ed5885b37385bb8, 0x73e262b908f3eae3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x7927d00e043e3308, 0x70bbeae632afbb81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x45e8f53e5cd867d3, 0x4ca4aa7b4a59ff72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x4355ff792241168e, 0x11a5da5e477c0bb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #29", 0x5b6bfc95665bd92f, 0x5e6a0cee0e1a7b6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #29", 0x17edffd774837359, 0x11c061f368888ed7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #29", 0x3446ea3e43d45a74, 0x5841d0d93f45c8af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x55d6498c19e5d4d7, 0x2603721d183e4dcf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x511e308f11ee2399, 0x213238b314abd1e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x162c56a1140037e4, 0x475b8d694a46009e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x70d89fb82645da6e, 0x14a000105c154bdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x4886f0fd01fb6481, 0x23915793342e9f31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x68573db154097c8e, 0x42491a9b23f2ed92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x488cefe864bd4d42, 0x0c7b7c6900453d88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x2891a7b7658e7855, 0x3f8b06387cd3da26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x7f744d2c364460a9, 0x151227f67e67f143, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x483284425a6f5094, 0x1313c32b50927dbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x6e6f88792f787e6a, 0x1ad87e5a5e5edae3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x55be58d95e057e55, 0x3a7426c25f482831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x6000e2d655bfe1fd, 0x1376c7621e4549d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x29c95e8b4eb3b3d2, 0x4238376848582087, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x3371011408286448, 0x489d5e1072564e73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x6db6dc9d043c5090, 0x6f2a289a5c02a8cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x3a80b1396d7e5d3a, 0x5a6a9a0f6d2b29ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x47edadcf589625e0, 0x3dbda78602b3357b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x080ea44a1b863720, 0x6112105e365d3648, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x798bb575291c25db, 0x15a55e795dccfd23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x7edc07d83e4a7e62, 0x7c1246f9598c984b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x0cfe32346a8216e3, 0x21e4b8d328a56663, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x72aa7b2b0a25dd71, 0x1afbb4d7406f3348, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x0e622e0176dc7623, 0x1c71dc14606157c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x645ad35d0b4a2918, 0x4d8c819248e2df3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x63e04ef82ca82513, 0x4b9614b52c48812c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x482e5c33784b15ed, 0x62a5b7746beef343, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #42", 0x21673bc845ce3760, 0x49bbf06641ba11a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #42", 0x0418b5c23d2b62c6, 0x1b46a9f3204343a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #42", 0x27ad79a963e45edb, 0x48e8aa041116e7f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x6e0a3c4c6df7f752, 0x51861b3e1a57f4d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x64d46d754845ce2f, 0x7ab94c9d7c6c6a4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x538ff74810e55e3c, 0x454f4987492f40d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x3d8d834f581d7974, 0x7577c1ff37704640, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x50688f616d1b29ea, 0x235f398305bbdf82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x32e9614a62bc9b1d, 0x4775f12a71cfcb2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x1fe7fde45afbb8ce, 0x12130eca3702170c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x3ee017a9199f1a40, 0x4818ff024795778d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x079711935ca6b8ff, 0x61ed6c622cea53f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x24ec872e6ea607c9, 0x2956be426c6b7f08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x7f8b66052b1281db, 0x359abfdb787c7e76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x032ffb4f534bfe3a, 0x2fecc4b73d18e954, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x406728240a4aba00, 0x42d4c8d653988ab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x6d07551e577b64a5, 0x456855da7350896e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x32771d73726b9f7c, 0x2a52a07a0cef5302, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x0c0ab9bd367236f1, 0x5484ca8f7157351d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x1318eff047984755, 0x1e41891213a1cb50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x363e4f1e35a80a34, 0x000d4a583805771f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x60ba8c0f606eba4c, 0x3081f59535c9b524, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x33bab88735b7674f, 0x72e29e7863ea875e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x4002214f7ceb67e9, 0x3783120e7421e0ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x5466cc8e11c50a94, 0x67726a1a2d09766d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x0430aa110e7d93ff, 0x39f8c96f06ddea01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x44efcaf01676a831, 0x78351f1e103b63ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x5e0eef8623ea7976, 0x23dd2f1e5808bae1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x599283aa40902795, 0x100e3200144d3ea4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x20fee1e23cf99241, 0x4a16f3c83a4d0fb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #55", 0x72b0f99055baa926, 0x1e37971754b99a69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #55", 0x52a6110f304de52e, 0x48db7b1432b31adf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #55", 0x4212efc319b55abc, 0x5fbc914d270cdd9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x2832eebb261fe6bd, 0x2deac79e464399d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x3c968eee7a5c2cc0, 0x567efda26d22b9ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x1e46a6365539a68d, 0x452b748d1aa57e74, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x15c9ce227909b0e1, 0x2ef2bd1877d929e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x36034322505dd0b2, 0x3226399a36c8b004, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x261879d8545dc582, 0x0b824a6d28b43cb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x04abaab03b23e8de, 0x5b67579178be8ae7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x54d9439b4db63022, 0x1fcb688446be9a73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x73d616df638131e9, 0x0d0234477d0c3256, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x5ddd5ea92f5a608f, 0x6a2eec02306ca5cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x0494071c7a04e15a, 0x4b1224417c2404e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x730e923b2623685b, 0x73fd2ec11a5dd53f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x7681390d5ca8cfb1, 0x512685432911d55d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x310695332d2d69a0, 0x51c6120f1c99b2e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x6851527f3523a650, 0x15583dcc35b23fe3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x02d9d67309730e9e, 0x7c70da573d2a961a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x6cf440882465b473, 0x3a36c87076afed52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x53c01502722eb761, 0x271c93204ad19f31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x6c3398bb3af2d2d2, 0x46f5a41158541c1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x61163b2e43d876a1, 0x72b1f15e5f422af6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x208146525a1a1262, 0x085400535797743b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x07477c03098964ed, 0x743127215187db85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x3ead0b3e03aaf5c0, 0x073a1b696f98ce82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x0d1e045e66fa2d0c, 0x2cc3649c4186e1b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x0b5fe17f5f536223, 0x3836cf037a1244e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x518219850bd98829, 0x44e3e4185f1ff682, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x46cc5afc2a2603ff, 0x377412a13db5b240, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #60", 0x6dfe7aa0254bdd8a, 0x1cf7dd3727e2962a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #60", 0x7f65efed73ab3186, 0x7f7a0a650e7fc0f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #60", 0x7d3496746741b7e1, 0x60079c7806ad6bf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x6aecada123099f0e, 0x76463a723be1a1b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x0a03cc1a359f5266, 0x7d688363780ab200, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x14f2b48a3700dafe, 0x721cf6e61563ad9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x42da63282bf7b6bd, 0x7483a41c6674ce0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x561dbabc41225d86, 0x242a804f09a6be24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x666e3b1131035eb3, 0x3189544e441c355c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x24ae903a32a392c8, 0x529bf64f65d42afe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x19e54aa962c7d160, 0x6c8196ee21e326ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x05d1706e5b2d4bc3, 0x5dc4c86004d1f84b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x10cc9e296ef9a131, 0x7cdcaa4b0fd53c88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x25fa7c3019bc8e3e, 0x2538ea2225bf52b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x45b444fb305ea112, 0x0c3420c268d4df58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x7180fe982404f1ca, 0x727b9d7c1bd1ffb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x5508507d328a2b63, 0x5fee351457ef39a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x652dbe2b2a44fb95, 0x3dc364a779b6e0b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x0d0cccf5795ecfc5, 0x1b9a07657f1308d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x548c1b8800c1ab6b, 0x03e5012012de3d63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x6fbb4c9c47ec640e, 0x22b379ec6558b9b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x61a8f24d174c2d28, 0x0b180c6515b5c8cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x47aace3a710645a0, 0x7e8aa824275d3748, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x150b376a231d6c14, 0x432f3700392bccd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x55a797774ede6b23, 0x111b067c6a1387e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x792366b97f647005, 0x63ca689f3ad555a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x78c33fca3dcd5f98, 0x39e85e78063033ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x3e8f0b033bc1eafe, 0x190e71124d4f5b53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x03ae4f0c3dc0216a, 0x32a815052e4a579f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x550c4e92428ac890, 0x4400206c65574159, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #61", 0x33910e314fe3afa2, 0x0cb478a21cb71ccc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #61", 0x73011bb666fdf01b, 0x55e2e99f489c459b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #61", 0x35dc5b3e167a3623, 0x32afcd8348a8b32d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x15dea6283d666748, 0x037e08d02effc1f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x7b33c6e04e3e66b8, 0x352ff5a60ea1e5f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x0a0051b60e99564a, 0x5bf1414539c2d1e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x4c5977b52c0d49ef, 0x680d29830daea0c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x6e98127f7fba5abe, 0x7305e21c2165c647, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x4f9e0a6013ffccb3, 0x3e1ce314222920b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x7afdbcce1d7533cf, 0x6ac5664c429f2616, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x33ef69f20ec5e214, 0x0b47d94330da180c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x4c2c495c1509cfaa, 0x5fd9da0449ce101a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x6348366234613752, 0x586ff60d4760103d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x42fa8d9d69300ba3, 0x0122e2206d488818, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x153d55926dfd0af6, 0x7af728da0f540552, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x6db765b46ed6aead, 0x30b9cb9903d56812, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x02d67b6010c3ef0e, 0x25fe88c23d557014, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x2e3922de0b3c6f6e, 0x7ff4962a7dd4382e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x1a0251820e882a3f, 0x2eae503b62288cd0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x2391f9e9046692f8, 0x2bf69ceb662e9ade, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x38c7ca4a2eb18d3c, 0x2d8eab1b06da304b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x17e198df6f19e13d, 0x7422b8637bc257e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x5d16ec343bd028d3, 0x0b165d392d1eee72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x2aa6d78056f2df46, 0x30f456844ace51e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x67b6ce5508185827, 0x0823c1fd2d7d52e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x1354c79559ffdb4a, 0x2b518b0f15eff133, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x68880589240f1aee, 0x78187e032d571917, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x2875ade641145f11, 0x1385b3f60c19ff72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x6fc5ec4d0716e820, 0x12f42fbd613d7831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x7630c95e68162d52, 0x5cffd01807a7852d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #62", 0x23e6562565baca23, 0x34c6739f5347b592, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #62", 0x3cada9692639c977, 0x1e16077a4e8d2da5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #62", 0x2e52219f275c0b96, 0x7c0a8086246477be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x015be6e0326ce6f5, 0x3a5468f141a6e934, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x567c01e30283b642, 0x6efe024c69e3ec6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x4398155308f21b9a, 0x75fdebdc7ef1afca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x100903ba3d2ef813, 0x602f27fb335e01a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x254525656fcbfa6d, 0x3b0586ce0639cd18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x5586c49077978a25, 0x598182aa492b7b8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x1dd1539c13c329b6, 0x17b8a93012346df9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x3b1f354c70ed4ea9, 0x3698e5b84c23753b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x235a359e7cc860bc, 0x0dca5e703c7b1c2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x7f4c16fe1c5cf473, 0x265f089779d63782, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x254f100d58f70f47, 0x78c7e74c42e42c51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x1626075a3147b4c0, 0x76422df2355813c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x2113af2d1513638b, 0x3b91e0e03b6b2cc0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x0caaedb01c4f517a, 0x0496a84a769a73bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x30127b313f67c76f, 0x08cee1b72a7c414c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x30551618046a14f8, 0x769fb6886b31b07d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x013275b44e0bd541, 0x27acccaa53af4bb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x6a68c9b5464d6a85, 0x4d858339007e8cb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x1f4479cc39a4e6f6, 0x4362b9030fb7d9c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x6aec9bb600a1ce6b, 0x450fed8a356a8126, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x15b531f6756c5631, 0x70d5ade60c004ae4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x11bba7ab0b69a058, 0x029abea122601fa6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x4ad167c7437c177a, 0x4cdc60f241ce22dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x47e62c7254aca004, 0x2cffd35a7b267de0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x22b875461c5b4cd0, 0x4ed5c9974918a226, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x62a8b7550cf9e7dc, 0x49972ed80d213efb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x469eced261e90648, 0x1cd918bd01ed3121, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #1, #63", 0x628ad4b3282d602e, 0x3757b247318b6a88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #1, #63", 0x1d99b65f4026740e, 0x3d8bb56c784006a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #1, #63", 0x4b901466677c8741, 0x1aa0264f2f555e0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x2af89ebc1e235441, 0x712380e716617c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x72cff445605dc3a5, 0x1187fa0e72decb2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x7cb91075058e9c2d, 0x3bf76d551588698b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x128884093f82c144, 0x22a9a8865f61c7ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x216bc78c18a6ab32, 0x614ef8eb592752db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x40d40b60483e72d0, 0x0ab2bd6403f69c3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x0864e6de16d6c937, 0x7c36a2e85e6dc1bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x7e5350787ee6a0b1, 0x0dc31fca53f4fb45, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x1d09f4f27bde7181, 0x6a567773294bef34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x5c3c3526582227b8, 0x1c2aba630fd9e937, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x5db0c3e5480bfb49, 0x256252c358f5459b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x078ebc8d19a60650, 0x38570d65703947ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x324cb1825413582e, 0x49609aca28fa8419, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x1c51caff2927c340, 0x2cf120587320bce3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x3ffe8c775f519e6c, 0x518e7ea224b6b1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x5e383f1d63022495, 0x78abad223e51dcf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x5ee0961603c88687, 0x679dcc247b42340f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x5beaae3f307e700a, 0x0b1c1d473b1ccb3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x788a6b534c691e3c, 0x141210d7399b7225, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x660f248c733554de, 0x29d4ba14001927e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x4748ad0d5604cc53, 0x2913abfa185bd60f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x7f2c8f935d0b1194, 0x0b7c92f2639a780c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x3c5cb00100fcd70c, 0x085129e93f2b1c0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x63fefba1651ac51f, 0x7d7cf8fb1a94ef1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x68e34ba720f34075, 0x15d7232e42df91b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x5171b07f120e6dcc, 0x7dfc5cf444cdf9e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x5e778c08283e261f, 0x7e696c0b49fc1bd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #0", 0x1b737afe7328efae, 0x4a1543b34486b095, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #0", 0x492dbc01685f1996, 0x5ce286a462bc280b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #0", 0x456a2b2a4ea7ca00, 0x4656a017485a4b94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x4fa4a10c0502609a, 0x0785679f01c6db2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x6a1d25ba3232ed78, 0x1c5bca4a33a39cae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x53262ded747f8b5a, 0x76832e6653007161, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x068df9261637d753, 0x17ce6b472497de6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x3e75fd7238a93df2, 0x6e93fa3e6505852f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x2bd22da0066ebc68, 0x298c35c459e97870, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x6ecdd5fe02fc4092, 0x3ca5a07b74ffe9a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x51a40a9344df9cd5, 0x3d5a353534380128, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x49e1fd6f525aa69e, 0x35fedc542148ab9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x048d94164b6f76b3, 0x54ec484d33ff2329, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x3fef020e1ecdffd2, 0x06ff948a57b3c203, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x3505d7256adf9aad, 0x7c4ba06f467cfb34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x2388d89f550eb627, 0x2b828063737bd497, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x5b7d728f0a0aed83, 0x4d654d084f5b063f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x0d072e1601b52516, 0x445aefe04a4b488d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x4694c1eb3482260a, 0x7e8349b65eab38a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x06dccca854e02c96, 0x7ff3e4481076bf5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x204fa3494b75770e, 0x4475e2840b6a60be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x6a4376e05f69c330, 0x631e22c1603ea557, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x4a495ddd523e20ef, 0x26bba08c1f494e05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x274cd717602a6fa5, 0x12c5229d6dd2367d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x6a355d2801882c9d, 0x3d2d3cbc02ca49a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x033d51b34b98dbea, 0x4d159234773c8b3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x001b01f455dba830, 0x55e7c3e749d2139e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x2abbd4c61ebeb57c, 0x5a48d2f806f7ce9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x6a342c8b7580521b, 0x12622f5a4b0b780f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x54ea154b5205bdf3, 0x2b4a1d675477a36b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #1", 0x2443dee20686140e, 0x73c0f1711f337328, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #1", 0x66b083b34a32e662, 0x0d05a9a54b90b5f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #1", 0x4bbb12ff1b7091d4, 0x4e5affa050e5e0db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x67096dbe1e0a3001, 0x48226c1a4ef864b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x73e5d83173134b48, 0x18ca785067246fb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x11d200c5007e6da8, 0x6e1c3e4e1ea1acf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x75febfc314f7426e, 0x69ad25077c062d50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x66fd0061443ec22c, 0x507dd0bb4ae8d50e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x4ac4d63a7721f1dc, 0x6a1c48360b40df43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x4154d83e252c94dd, 0x56d1953d317559ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x409d26b14a7da6e3, 0x025b3ac90d0feb3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x6887d6e474d2c83f, 0x5c084fef27a6946f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x67e613877ce7426f, 0x0ecb04215c6daf16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x7d65b01764bc8114, 0x7b0f5c0d79b8144c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x79b3c382463c1258, 0x75be419c73646fda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x0a7ad48428698d1e, 0x3e4d44e860b0c3e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x1f8b7efa42c33864, 0x6bf1a327553faabf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x67efcd4109103f75, 0x06b504ac60e05738, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x538de65849f89264, 0x6df04275288cf3f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x3ecb5aa35efe8c82, 0x503388613c15bd3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x5be5cef11392c860, 0x18836c5326b16e2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x784f49751627c414, 0x20698277594b7f08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x5c63d66c0afd33ca, 0x4cafeee272030cf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x3366c0e83ea57402, 0x52b3d0db66deaaf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x0168ac6642d35a5c, 0x3c1e55af52f23fe3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x4be399d121c2d991, 0x33d2971b695879a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x6bbb6bf56218f5fa, 0x11e56d991f71802a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x4117827c740aa9ba, 0x5b873d672a86c699, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x079d721a71a1b73b, 0x513834c41cfd516d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x07c97b4f42f8bf57, 0x7648d0757fecbb8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #2", 0x4df5f32144a39962, 0x71efc887642d51bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #2", 0x03490d64072a525b, 0x4b0bfcac015cb409, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #2", 0x49fdacb708218b08, 0x544ef3ec04b1b9ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x29e464997fefa10a, 0x6e0a337115e14689, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x6208970410da041a, 0x3552c6b3159fd08e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x04e4add4115ecbeb, 0x4026972723201980, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x0300832736663b62, 0x401d6aed0c821fee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x795efab97e5ea405, 0x0c6edb7e0ac9fe76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x43023d673a034cde, 0x6ef750324754edda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x412d9f391d0095d0, 0x48b1a1e3464b4acb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x252220d839073806, 0x4afd04950b2b4bf1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x38f6d910565f592d, 0x210c927a4f068571, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x67395d4724cced27, 0x64a655ff1aff7014, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x362bb9127e3cf481, 0x3e1f89946c1e0b1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x34a32fe3050f0687, 0x78a02b09392c3c39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x036daa8c32ed8ae2, 0x43f63ab02e022a9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x6cf0d7c03e08ba59, 0x75571876466fe7f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x5b09502957b83753, 0x0cbb32be2e1e76f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x10bf6f595a565564, 0x3949c2ea002b7101, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x30b5ae9133d84c72, 0x4f31f67249b64869, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x58a5399922d54211, 0x64b5b87d17ef0bd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x211236927cad41fd, 0x040d16f30ed0f2ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x01bc48840bf36995, 0x47fd2ee555b56675, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x3ee0f477790ea987, 0x03b791110529f311, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x371763e158550dc3, 0x4b99db042bd1cc37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x300d4516133a061b, 0x59f043301220b40a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x6d905b7f617e1b7e, 0x124c250c40ccb470, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x155667f06f38b557, 0x0a82fcd91e460a11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x120df7683a422cdd, 0x363515e96dfba189, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x36ef6eda44c9c31a, 0x7ccc943533202dfb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #3", 0x50bd2caf0c8d2582, 0x08d5947038abb75e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #3", 0x059bcf09096f8574, 0x3dd5aa6f0f9e2126, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #3", 0x61c493371560308d, 0x3b6fed5d3cb332ea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x289a36a861200c01, 0x4ed3e6f511d1d84d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x429e277f5d218997, 0x529e8cbd162a9228, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x4c5a3eee6aa5b222, 0x34709c3957f48f70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x24e7deff42bcc52e, 0x45f030f95e683656, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x078688481a5df8c2, 0x118864515bd74dd9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x26eb1e445258afa7, 0x148305385843b4f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x5bc8351b2351c37a, 0x67e1d61d2c86ed4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x38b1f408380e072d, 0x693a20383d8cc852, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x192e132e21fd2d5d, 0x4f5ea0a0614c2ab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x7f1eb6f42be75911, 0x7776bcd85bcc3aad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x168d0b3479b0fb17, 0x33c0ca1d4b78f5e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x3c6dc0453b69908a, 0x29e12c393b74ea33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x55c7894c2bcf3d45, 0x174c380d43f4488e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x7e27ecec0419d3a3, 0x1c37fd857cb2a790, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x276b971d1273b516, 0x293994de59f02208, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x4a81bc4366db8afa, 0x177cea5a601d8b25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x08d8b85838e072ae, 0x4169b5d663afcf71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x64c7cbc0733cd43c, 0x3f7c0a1e07f76f4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x6cedcf537d519168, 0x5370652f7b54d6f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x38bb21f24e15f934, 0x36c9c127295b8f98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x79e536790987d5ac, 0x6d4fd8260e82ab3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x0da1a94f346ee7ad, 0x0b3552cf780d2366, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x46e29cc3697a2fc8, 0x51fd456e350d406c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x5055bac356948168, 0x152acb9211645906, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x0f74f41634903296, 0x75142877592e731b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x27cd06d234964796, 0x6125e267743cbfd6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x31e7d8fe265b57f2, 0x6f9196ca14bad625, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #16", 0x747151262b663de4, 0x3e1665bd6aa2faf1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #16", 0x34ee1390045af8ff, 0x7925a6306e5687a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #16", 0x38c9e0ad3860f074, 0x6663ab06428fbcdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x21db203c0cc7c8dd, 0x779cfd4b7fac7d70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x635c4a450624feee, 0x1110d6777230daff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x3ab531842c853082, 0x4b5f4e1a72d13e5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x611b7818569f94fd, 0x670dfe3262823856, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x7cfaecef35537439, 0x773d0e7b13035117, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x60b9b21d76cbf238, 0x7da64c08716c3e15, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x7b26eb37462670bb, 0x5fc2c5b515a7c5ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x7e87612f4fd47fd7, 0x5837828c33f0cbe4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x5c9c48b544ae1fcc, 0x339d49552062816c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x4ad31eba5df2aa86, 0x12935c6b3ff892fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x0a77db0819d7cf89, 0x32c9d1560588503f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x707764865f479711, 0x680a88956b935320, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x149b0b4a7c3cf03f, 0x7e96a4376d725175, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x7308e2773ea15540, 0x5ede8f8a7554bd67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x04c7c5fb633405a0, 0x0afc83146e2fcdaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x3308857755bde2e8, 0x22209993034f272b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x1a6c02b436450502, 0x23b1a8970fa4ce2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x1437af880267327d, 0x4f9d6127653f216f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x1c3f020652d1fa43, 0x6ac771ae1eaf8a90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x3219915408d981e8, 0x0a42ddb10cb6668c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x051672285907478c, 0x7a28b80146b49c9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x17a89ccc4705dd19, 0x3c095a05781f549f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x2a39e2b9086fbbe2, 0x664f224e1c7062c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x5e2d9eca43713289, 0x1fbf89f25d426831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x79b6378c3c849784, 0x6ce7365d7899a17f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x3eebca0248a0349c, 0x5dd8c2ee0dede714, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x1b722edf36e04f56, 0x2c9d71a55b2acc08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #29", 0x3fb9d13e6209ea96, 0x67e132954d8bc034, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #29", 0x3b1132225049b6d8, 0x14405cd244d04366, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #29", 0x174f93f1233eba54, 0x3cef980652b9ceee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x2bae76360ee9bba8, 0x6f2a31b6418976ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x525aee320bb31539, 0x1ecbdedc09dc1501, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x4837acbe604e796e, 0x0275b6804c1125be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x28eeae0a069c7e77, 0x59ff0cd2072376c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x3d7ccdcd4a2f755d, 0x624e42c84460dce9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x2c395ff4262cf9f0, 0x11ec9d1d7d369f0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x7676b0c87ef67a78, 0x4206e272674a9216, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x223534cd292e92bb, 0x3a0461050dc644b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x38184e636e1b9a40, 0x4f4fbb644de3ab03, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x79ceaf7a5a357684, 0x57bfc0040a733c95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x3a83eff230836f26, 0x5684625342065c38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x371fed9d2b7815c0, 0x4929d2f863729dfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x75a78b1e39c01803, 0x27d37ae6749cbb6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x5fed11f333da3ce9, 0x71d35a7721e0eb12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x32d0b762432fde2d, 0x092b7d285663c2bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x6c5e70e83379c2d9, 0x642a07755505ec2f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x21955d1a7aa95737, 0x22e997322476bf4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x54decdbb056e5e35, 0x2ee9fbe11b640c94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x35f1cd5b26943bc4, 0x5d6a68cc0f62bdae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x520c51841aa8d690, 0x72d55baa6d11baf8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x5468ee945381d0da, 0x61ae766347b3dca2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x075c0dc472c044dd, 0x6994c7b434560087, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x35f0230a6ee3cab8, 0x0ab9c3433a2cc526, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x225d8d91321c4887, 0x0f32b155224e93f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x2cc59fbe75af4f20, 0x46c5533f43f2eaab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x7b1dad553cc1600b, 0x5f56f73f01a46d7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x63559bcf03dc86d2, 0x11072b28310f7ab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #42", 0x1e855d637fcfac0c, 0x1e2135a93561ed54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #42", 0x53517ce766aa91ab, 0x7d15c9f672ee4bf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #42", 0x596ad68831fe0fc1, 0x27444c7e5aad8aab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x20e1da79240d0126, 0x14da4fd10f5af992, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x562949ad786ee0c4, 0x31a98d85433f680b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x6e1e2fe5668949f6, 0x073252b602eee96c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x234aaa01159a820e, 0x049356e6693bdd3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x197708e0386c8d94, 0x1a4b57eb06a045d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x383c39a03917fd1b, 0x3c02332537fc6643, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x1fc28ec6522efeb9, 0x2aeab23a0b8db687, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x042d0e7a7b159103, 0x663b4132792d654e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x1f2292293a31ec66, 0x08885ee1250ee8f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x32a0cd2b6f80a3b5, 0x684e50ff754bdbd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x5609edab7cce1c29, 0x783ac54320befd10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x12689e3724463235, 0x09fada4a795497ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x5cb2bfc93bf710a3, 0x7ff4dd7e2bdfa717, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x750f0dbe0ec6bf95, 0x63dc0d5b14eef96a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x60f5be4e06b7f124, 0x207caff114d19c85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x01cd8227168760b4, 0x0dff01d36522ccc9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x50b94d1b728006bc, 0x0a31b5bd20f01451, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x6200aa710e76b56b, 0x163bf028035a1a46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x0b44d1942e13f1a0, 0x24191756380a981d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x525a23d631540d48, 0x315f2fca1dad6fcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x6d4b1deb2d69243d, 0x498d16e22f0ce39f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x3c2fe3d364788cfb, 0x43fbdd09625a2ba9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x6b307e1f052aca02, 0x772bc82e1d25a221, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x1bb22ab60c7a24a7, 0x02486eea6cfe0046, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x7efa2b63242a04bf, 0x0dee14976c6b77d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x32a0ba2a13dea96d, 0x6fc5921760fad5d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x41f29b0e4a649dbc, 0x19056df23de58bbe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #55", 0x7bb8ab042520126c, 0x5b92fb89144cbee4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #55", 0x528936a907557f8d, 0x4359a2836903c8ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #55", 0x6bce0c884289bcc7, 0x4b5df4980eb91a7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x47b486c92e272b88, 0x2bdebc9e56fe8aa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x3aa1503051ea9f85, 0x43fc8aed6366b17f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x7614a4443f97bb68, 0x4fd22951399b7b93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x537664d6339bbf5a, 0x1a96516828b55e6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x7e005d16422de5b7, 0x669aea2d1568ffe4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x674df8236d0f614b, 0x29b5bec879b9081a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x7464e0d82e1ac5a2, 0x62bcd10939d72ecc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x70a48269746f05e7, 0x489049496032ed60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x2296316f7b2e02f5, 0x3731780738590932, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x4d18a27a6b91e402, 0x1bbfbab15d37819f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x2b299f6b31694e9b, 0x16d2fd33432d46be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x65050df6527d8f5b, 0x6be2a52d7ea00441, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x14ab75123dbec2ed, 0x1409042563056b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x2ace24383f7b4430, 0x5cbe73277bf96d35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x6d9609d27e60e54a, 0x35d09c011f330511, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x72cfeb3136976a79, 0x7f65f2715e3a8c3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x31c56d6e3253501f, 0x1693956d15661ca1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x1de5342109709b73, 0x729d9e407ede0fe8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x3ad9ea0f2dedfbd4, 0x420b56a6490ed38c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x006b8b2f5bb7dbf2, 0x47aed7cd1fdef805, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x19769edf5fa2d638, 0x02e4631115170041, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x1f1e1a6946e10977, 0x11106d764444c318, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x4541eec262ddba9a, 0x6377c8290cb4243b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x19752513018245e4, 0x6aeeb0773811d9f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x33d59603401594d5, 0x4d77f6944b3a9281, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x498630480c23f910, 0x4a18a26951baca25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x3a11f4e46278757f, 0x1ac99db104601a57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #60", 0x3e3051712723756e, 0x243f125c3a7d8013, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #60", 0x06c64ba660a4edca, 0x4f94805457a6f051, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #60", 0x2785f7417f637b92, 0x1bebb36925e4660f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x6241362c1d873ac2, 0x32988a4b6cc7e603, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x1f0980a67251b68b, 0x24d9bff77bb65b40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x32674b601109902b, 0x46f0edc152df16aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x1d2d893b3f637e80, 0x2499e0cf7bed7ba9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x21dbf3ff248ca85d, 0x004d9600573f7e1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x4bb01dcb61517e86, 0x11bcfe32600c4571, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x41f66c50539ee92b, 0x37b335c252766971, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x530264bd2af359cc, 0x785acf81697c6391, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x487a948e7b1e098c, 0x5644499535439ae9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x6d6fc01777eae3eb, 0x30f9f62967841534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x08f474165efd0cad, 0x3a632bde1fd70b78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x1e608b2e1c121d21, 0x1bc487212621fd51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x409ec57e0f1e79a2, 0x7d617b70403c7f2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x706ff82857fbfa60, 0x2048c49e0c4ee349, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x2b9ae38b57201c3c, 0x5ec54cbb32666478, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x021376087227119e, 0x1be2c8097e9d4848, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x6d451b2a64dad95b, 0x33e0e3324a8e0a96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x5cc5bd466c754ba9, 0x32121fca5ab4db42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x4b72585616506ddb, 0x7a8be6ba65ba315c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x32628afc093daa1d, 0x0bdc2ead69d2e384, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x185c23bf4a582750, 0x2a0f62b27301507b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x225421b15e15807f, 0x7f5033c408cc1be7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x35359cbb57154869, 0x3b32805f4def053c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x493c5a07006d30b7, 0x4c8c4d85374912c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x65480a1233e93d24, 0x01d71d5936817532, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x205e88cd0bc2372e, 0x11365074420dc759, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x2212a50933a42763, 0x27c7f8b56bd0e123, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #61", 0x3ce1d1807fb3275a, 0x55a3c4a854753005, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #61", 0x4a0b4eaa46c6b445, 0x47768080553df540, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #61", 0x24dc34c4193c9187, 0x5e0a11276c5f705b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x7051d9f006dac31d, 0x3a4e75985a11d180, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x0747f3d41332019d, 0x115ae443398e33f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x471b3ec10145f99d, 0x700fa9296c8ffde6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x0d0830cb5665bdf5, 0x2e9dc53f6779c78e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x0a09e55828ee6d59, 0x534aa8b12f1ad5d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x28a194b34b06865a, 0x039005da46ebb6d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x11cd3a9f7a33bd40, 0x1c29ac1872ace35e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x13704ec7195ac951, 0x5f0c53b936a96f64, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x20358c6e22162527, 0x10bb40e403c228b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x354826c42d6005d8, 0x3d505cae277d8042, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x2ea5ff7542ab4368, 0x140d7e297c636585, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x1911015d3727d5c5, 0x63dd2d133bae3041, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x6016431e6e590bef, 0x6ac90615231ae6b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x395f924a063049a6, 0x6a069d8e08b7d7d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x006406e65a710ee9, 0x7b64bb304b2ccce9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x73cbd83b12917d31, 0x01d63c4d13d455ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x34a7a25954e6db13, 0x17967e64140164a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x0246e0eb4f8c6315, 0x3b7ee4ec69efc91d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x1237a67d4a305bb6, 0x66532ea330ece060, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x0158317b576416b7, 0x6c9b10a12b48a7db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x45bd22a6386a2c1e, 0x4e638e90616e749a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x3e9a75c5658b079c, 0x6a264c6c7f1cb4f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x3ffc16854c1fbe27, 0x4a4981da3efe7cab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x5eb13b596a6950bd, 0x52d2d25933c7eec0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x3f502bd003483856, 0x47c9536a1358ddb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x52d49b6b639bd572, 0x7d48a6cf41970cbb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x2dcc31295f1efdbd, 0x7283ed1c650c41e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #62", 0x368314745eb87854, 0x1054e9c32f2462a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #62", 0x1722a4727ab923aa, 0x1092d73e7c40371b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #62", 0x60442b4645a66de5, 0x7b5cec0b55bd1a37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x11c62c0d678e693c, 0x14bb96e3204041cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x51f7b9f91bd183f6, 0x5408308c70776766, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x1f19bc4c0118ebe7, 0x03d045181147e5ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x64b4c15a4562dfa1, 0x52def28571ee57b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x2481dd5f674f8363, 0x56fa99a01280f283, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x4607fbb752382c66, 0x41a555275b04f1d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x4cf1501052a214fa, 0x574528ee5d2aa02a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x184882df47a35144, 0x32e7ba612d357b57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x2f31ba80217dedaf, 0x4d75bd232a0eaeec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x3d4f71a61e565b6a, 0x1a8616520129747a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x1f6f475265504cc9, 0x12715a445c692df2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x2ab32c6b25521f4a, 0x4e5785aa042408ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x0ca1a2ad584a5056, 0x16a4fb2f4f3509ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x2a827cbc017f248c, 0x2a39fb9d52a99e65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x5421398662bbf8f0, 0x2fd43e8f7773cccd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x2a5f4a35721f0547, 0x24a948246c69bc65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x139cf2f630fe81a4, 0x16786b52599104b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x4f54dd0f6d2bd373, 0x5aba792f50ec649c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x527c203d7bad1839, 0x2d55928f6ec42461, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x20ff3783098d283c, 0x72e82d0d7d2f4ca8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x61d77892769e520f, 0x4c6456722da0da30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x781d769b301eb724, 0x004a78950c59f54f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x12dab01528770a40, 0x03cdc21c4c3eb021, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x1a960f874f20d7d9, 0x38a86c873d39fa4a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x001f597d7185782f, 0x16cafeff2e33027d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x5eb14ba22c74f9a9, 0x7f1f671a4f74368c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x282211e2312087fa, 0x3e385aed312d6bdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #2, #63", 0x3aadb0367ac10ef9, 0x2e5cb88749214965, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #2, #63", 0x715f6109770c9c2b, 0x76c223951c8528c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #2, #63", 0x272b534f2cace034, 0x28df1e18697cd7a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x5523ea746e63f44d, 0x35bb87c63a060364, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x3d84cc260e0afcae, 0x773ffdae6fb9f9fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x7f9074dd1d0c6392, 0x1decfc783da425a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x49815d3b4b50b71d, 0x0d185c305e41c07f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x7c713f183dcbe4e6, 0x0f6f2c5f71a36f1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x388cf3e03186dc18, 0x3ac4b882371eef4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x289378437c83362f, 0x53a4181729ec54e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x293016634924b453, 0x13692c8d4fbecb92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x3788a8a00104cca5, 0x09c4cef77e5400d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x0f0fc9530bfaf74b, 0x6e0dfad2750d74c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x29075add3fc9f69a, 0x32b19a6a0ea03e30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x0b1aadb77c512b0f, 0x6ce1feb07288b819, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x3a1d0ff51ef0dfb9, 0x642c2736078beccf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x5077bbd1124ef435, 0x3eaadc1e72aa03d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x0ed22a652fff854c, 0x1c9658be790b3414, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x7924399f528ece9d, 0x48c9ffa6380240c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x53939b4324643c72, 0x365641a030ace240, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x305f33bd586bf170, 0x25ba570662a36496, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x1835e80a5e25a177, 0x7143a2c759668e9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x5a76cc86301b6dea, 0x4bef46b4235095c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x4f0c4da369875eaf, 0x2adc82911493dc7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x7bd652e523d4390f, 0x073de0511f840974, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x53d3be5b61593d2f, 0x188f3d880aa87d4a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x33e80bcc7900ffb2, 0x42aabe124cf7f7fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x1d653c25235f3141, 0x7da4da3b077ba70f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x7bcb22b25b62ae6d, 0x6a1f0ba64dc46fe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x39884fe4731a4531, 0x272afe7d14010abc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #0", 0x2335b31c622e2310, 0x3751a07e13ff1c6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #0", 0x4bb581bf2fd0d936, 0x2892f8e5724200bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #0", 0x53a512462a5547bc, 0x11c60a34478bd4a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x0bae84eb14df1001, 0x523451ee2778d0a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x0de00fb37215a2d7, 0x7470c89c3f9690b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x1574d4193131436d, 0x471237c72b454bd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x0c93f1da2034ba38, 0x7909bbbb113ff6cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x134eff6a5c92a206, 0x25410187461c41be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x3ec0c51602ae570e, 0x5a1b5e283684b286, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x327f30443a8cbd79, 0x28c6b3450a7646d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x64e2053624366d68, 0x52021b7a0624428a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x39157d69220ddbc8, 0x2d9d132c70908a21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x14237ea0773952a1, 0x30271ad946f58d1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x286a960e6b4494b0, 0x723ad8f5299852b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x0b794ee960194b0b, 0x3ad8498434fe87e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x3cabed11553627d0, 0x7b1ac9a71ec84e53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x57e47ede7e13b41e, 0x554d00d97b6cb227, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x38a0719857e51477, 0x05e2f8fd0a63af22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x7c1b81df3e2504d9, 0x1087f1ad1d8276ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x6032e0a13e3a1bc9, 0x0e1300ef3530ff49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x35736e6a6e61655b, 0x7c268c6674565f41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x59a5fa0c58c6fb7e, 0x1deeb1fa5dde0478, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x38e0468a0df75609, 0x12dc8c61651f48f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x632d7dd959349821, 0x03e79748758c339b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x57484c3f76dbdec0, 0x70f8e5c33b11fcb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x4ec0f33755fd9d86, 0x4575abd90fe8bdd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x1422a25f3b7e3595, 0x2d6b34a54adc7516, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x79b8515e7c3400c5, 0x000d745f74558301, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x6a956621069a943d, 0x68abe2422f2bbfc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x5f618fbb1fe650a2, 0x0d09c440443b602d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #1", 0x2ddda6ab2d42406a, 0x295aa9221841d645, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #1", 0x0676d88b7ec6efa4, 0x0dce09e1110b2484, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #1", 0x75a2ce641192cd14, 0x4c1d213b5dbf24ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x67906a9b1b131747, 0x6da7e2a24463c19b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x56914cdc0f4dab11, 0x0f4036b17bb30cfa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x0b81abd658b4723e, 0x70088ffb50499e3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x5f4f067b0c7f2243, 0x7f755e02761711f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x2c6572e563ad1b46, 0x3a5272243eb09636, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x10ef5bb064c0765d, 0x56f26c7c5a431990, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x63876601376b5f4f, 0x6b4e3e141766343b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x48fe2c6362cd3ba8, 0x75255906592a3465, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x7de052ef2cce2cb1, 0x1d8df600308e96fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x3c1bd7c21c4a33f4, 0x2c41a3f954719fcc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x74fea63224309c09, 0x24bb3e06479d8399, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x30afbe4c780707b5, 0x3db49590544dacad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x5bb422fb69f0af60, 0x12fe42e45d153131, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x4eb125bd22a688d5, 0x37584ac16ca37eac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x5a11e824792f0bed, 0x0409b2e732388bbe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x5bfc479528f0b623, 0x0b62c02323101487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x55bee2d47fe04f7f, 0x539eab8659dc9a85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x1c2a837353097857, 0x2e4e3a5111daba97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x773a1460172cd3c0, 0x59783e30112929a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x0f33db7578751937, 0x6576d65327e9d2ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x6265c8973c574e9e, 0x04ff03dd6ae7fe71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x5efdd7735b953004, 0x578b7d1d3116ee54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x54c43bf26eb23a35, 0x634f7a12390fbf97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x17a2f0582fbe7fa5, 0x5c1fd41f30c08387, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x2f9ecf2438eb585d, 0x0a9d1e0c6d61d32d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x0bf4d0b558b4cbf4, 0x7f3c8dc44bc95297, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x6fe19fb442695291, 0x5cf27c3d032ee515, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #2", 0x3ade6bc83017bb9f, 0x2b18b7c27f157b2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #2", 0x6c6f0a3e4188f6b8, 0x69fd799b1d443460, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #2", 0x1d1e26bc31aa9cc7, 0x4e5b22b44b6ce1b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x205cd6fc609c7568, 0x047ca14971e262ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x105af50d2d400442, 0x22a2e63637ffc755, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x662b5ca0249e2846, 0x25619a823ff9c431, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x7d52f43a68b59306, 0x0bc316c872202d55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x2b1ee5972067ca2c, 0x754f126a6d3493ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x507f85cc564788b3, 0x6c4a0f1865fd515f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x17d07f6b519ca874, 0x034185bf3cee900a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x0347453b0cd81304, 0x085b71bb34eea628, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x6d74886c4973ef0c, 0x26d108d623a41c37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x76b3f34f01057e0e, 0x5ba3e38c7dcf7d79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x25a3a654498c5873, 0x3dc941aa5cdf4fef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x3241eb79444e8fae, 0x4eff7d4422f69a8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x64b659db7c753d95, 0x102b2e7d5d60d110, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x52bcc649469fa82f, 0x435e226f3535dfa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x183c50a37a7fe16c, 0x72246fb16a8d45b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x0757f471464cf4b3, 0x1f7bebdc1b8395de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x0fc0e3bf1acb95a2, 0x3f27b21574cc7cdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x1bd113b030653c01, 0x729bfa570674d70e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x79f194743253a441, 0x635426fd4174ba05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x76a233f074968310, 0x646b54932c337fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x710bc0a64cf2736d, 0x099450fd5b588dcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x13921b9c02b2dd23, 0x108e6d7243c886ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x7d32be8f4dd1b880, 0x2e55cca32bce6c3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x141ead330679b432, 0x4752021d048ab300, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x214549d46bf32a35, 0x79572fde23df90f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x1c5866360da88efe, 0x2a5468013d165d85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x3ffc334062f66c1d, 0x7e8b178a1649faab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #3", 0x578cef2e4c11cb96, 0x427d7a98369e6730, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #3", 0x19043f032285626d, 0x11f6f4fb4898afd4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #3", 0x25383f903ab70366, 0x0c6136c32c965a9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x0888bbe61fb6c8fb, 0x5864c6de226afe1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x26307d2d204ce0fe, 0x26f5b1201ca76919, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x0c400b336adb620d, 0x4086fa0c4775c702, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x7883f10b03173c11, 0x048c248728987169, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x660da82e015fe6ad, 0x3ee26c143880244b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x4d71b24301158076, 0x6f1e8b7b3d9a975c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x239ae2e312947df3, 0x063347306675f146, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x4d4b815a6b7112c3, 0x130c4be548d32273, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x0b27dbbe1233d1b3, 0x6b3e209355d43d40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x3280b2b13302a066, 0x727ba65a315858eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x1dde02737d5a4474, 0x78ce1fed3ec0bde4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x00718085263b9b62, 0x67592f4d1661f37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x279b820f3e00a345, 0x4ee217ca667f28b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x3f1623bc2a4d0741, 0x2419c010750d3452, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x3ce185346e8f717d, 0x5b83259862b1069f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x5a00844016c249a6, 0x2b8429130a2d068e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x28f61b59527cea29, 0x600143cf65285ffe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x057f8a8f0f4ed8d7, 0x1680b8e95b76ce0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x0ca91d4b0190bb3b, 0x1a378bee235d8d02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x27cc569d08a1984a, 0x39bf80800d1a9dd1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x46a23b9017b38695, 0x7399c6854f67d8ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x42008dd61ff83296, 0x44750cfe05b85f4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x0e87a41313ed8efe, 0x686965eb7ee2130b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x2aafd8a469105d68, 0x090f199968882853, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x3b8d47916431413b, 0x4db0885153a5f3fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x73801a1249544df5, 0x2f1cc207410cd220, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x4ae509311e29dfa3, 0x646a5f220029375d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #16", 0x26cb77ed00dd9bb3, 0x0d43d52e72b15fce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #16", 0x18912249068e4579, 0x4219387b6d6db37d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #16", 0x268678105b8f78b5, 0x732612c95a91b01f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x6f7d07b36282dcc4, 0x5973c32a350e1c23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x4b933a2c6b46ccc8, 0x1d9644771a2ce058, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x4f780e031cef965d, 0x6dd2d455072081be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x6643e4522c97b301, 0x482d53de42f82815, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x4ac192a4506534a1, 0x43215f733128ed83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x5142d05565f385cd, 0x23da4d52718d0a91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x6c81cb465220d0d8, 0x5efabe0f69d3f29e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x2db0498d1dd965e8, 0x4465a2bd13084356, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x005c42ac65aca3f1, 0x48165f7a1d2d5141, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x50f370b9252d05ee, 0x375a31994bef7cd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x421c9c4b1b3d5275, 0x530ffe96206b7ebd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x47d5057626850645, 0x6363a6d22860809e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x76ea3ae77d63bb73, 0x59896e211296981a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x63574140631e60ba, 0x0423a2ab482d0b3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x353f31937666a097, 0x3200fdda4fd90c87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x1440067f2af7af57, 0x62e14fdd62ef7b20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x10a453483776fdfa, 0x001ccc61149c492b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x5ca403e9339bc49a, 0x608bc6046197c402, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x4ed9170f6566e991, 0x020342bf1ec0a034, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x0bebefd720aa8ef4, 0x472120d216ae1c85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x1e0e4a672d68574b, 0x2944b49f02d62abe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x1086b8057d0433d4, 0x4b0335fa01658ba8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x736ad46b341fe80c, 0x513e982f45c5e998, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x5f17976428d2311a, 0x28b564b907aadaeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x60492f157cd2ea1a, 0x1c4724166fbbeaac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x306eaeb55356f16d, 0x5153aeae3ced32fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x38bddaff22cef405, 0x5badd3327f47c5c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #29", 0x437982f93f3a96e9, 0x15f5e24a44a9cad6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #29", 0x6ca2ee3412832b8e, 0x477ff5946187cd60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #29", 0x0f875f62342bf137, 0x62ed59087d29a63a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x684bd9446ba4f48b, 0x42ef8fd202f233cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x147725a626e432cf, 0x0a9d0eb8476370a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x23b71ce908730a03, 0x371f5b5474c054bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x5bc9fb700d5b5aeb, 0x31ad87b95425cb9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x302a4ef0696373ad, 0x536d91631487d66f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x289e0a9620b196d9, 0x5931a14573a3d1e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x3334c2673818f852, 0x552b9f4a1540f8cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x6c44e98a555a2ed7, 0x126a9f0542bc21c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x40ff2363504b644f, 0x45ae55975490c2ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x772f971e53138eca, 0x1bf4337655764909, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x5b8698cd7be4257d, 0x4a369dc41ae6b408, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x093f8068427a1109, 0x6f0c7fa63750943e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x2bdd84b6250a0bf3, 0x4bd86aad3969cf59, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x45bba2cc0239408c, 0x2d0da142547b8f4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x3a5238df7c27271d, 0x69bc881878f06534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x518155f4015adc94, 0x3bac86fd26972269, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x51a640e4171c18ad, 0x7b27e53712807957, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x6a2fa777322d6024, 0x67f6c26048d5d802, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x2e1185a152c90bb1, 0x63bc8c0a45b64045, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x15431cba48df3f30, 0x7d06d4833751060a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x6de94b231dc876a5, 0x70bad5634120a171, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x2001b7327f58b8d6, 0x159c30be33a4edf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x7b7fdff36841da21, 0x2c9553245a53f011, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x699cb6b67c12f7b1, 0x00eb127a4d0135e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x132f105e4778719f, 0x5f81af3f3b42f79a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x79a5d1c467d55ba7, 0x0418cf9c7d5eb7d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x3a9e6758401bcc9d, 0x4314f81a27b75765, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #42", 0x08fb0bce4fc332d2, 0x5f085d6f4fe18412, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #42", 0x6d8ba978269e5641, 0x1102258376e456f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #42", 0x25f70f17571e9805, 0x2a8944e10d8d60aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x3f60722768cc6335, 0x67e150bb2176ef0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x64df5ae64df9d431, 0x6e7824f228fd28dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x157245d06858f013, 0x64402077780e6b44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x502e4bba38821b34, 0x756d23190f181794, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x789de7d115d7cc69, 0x36cf6efa0accb312, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x659aff3c6bb05ca8, 0x5aae37250198f39f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x124eb2ea23068f72, 0x787d4a915326a8b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x7a25277848955a19, 0x60b4095e3845c201, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x3161bd4e4834d5fe, 0x59bcb10c3985999f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x162eaa2f46c2e2f3, 0x6282c27c16411834, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x2f1bd30603bca691, 0x0e4f83782ba0efff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x3c3ec1c57188768e, 0x3ab907947f4a1ec1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x076042f764c508f8, 0x0a16d1d334dca997, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x507565a12ef2e7c7, 0x36759d366cfb4233, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x51f9773a20d5f445, 0x4021eae762c4188b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x696b4e5e74c68b98, 0x1b09da8c4c1e9eb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x3cfb61966826facd, 0x05a438511acd0bac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x2ee9ddc03f5da758, 0x310e23e0532a0bc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x431a4dea39840359, 0x7ecafbc55e05b0c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x2b0c79e76766a15b, 0x5d4fcf877f590faf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x4c2baa536aab567d, 0x3435b946326cbcde, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x199e3e445f89e9f9, 0x1f67ff121ca10ff4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x005fde3f1a6f030c, 0x7f65287f6b97b57e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x0f358ea43d5a8c81, 0x37b6543069cb2c9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x2581874e35a65c2a, 0x0498384a4c30f03b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x750403831e25f7c5, 0x1f5afc00546b650e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x57a9fb1e0fc0e55c, 0x327115d5381e516d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #55", 0x772786b76bad1a63, 0x3777611c02b67505, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #55", 0x565870e0548b30f6, 0x352331e44353310b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #55", 0x34151aef5f59697f, 0x5ff440ff6ff6af24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x79c86c8b1344b8d3, 0x5b8e64a33474f92e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x509f455522d85e16, 0x1e4025cc08fdfb2f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x587eba407489e76b, 0x552eeb6a7620cca3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x12afdf307cfd4787, 0x4a8c31b24d82bdc3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x0cbe2ce33d18704d, 0x05a10f306a59da4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x28c58ab022338138, 0x6d104f5403e5b39b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x76beb22e272d25a5, 0x4738e4a67f1dfb90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x06868f244aa30f57, 0x6f14aab42ad3cd1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x5de7c82b7d88ec18, 0x5f48c64c004efbaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x20614a2e5e7be249, 0x094cf6df2e870d80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x5305c9b46f340bd5, 0x24a7da2378e0046f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x6c31535c4c03d163, 0x4662c23265b5a8e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x091c41b03d1fd288, 0x500f833478ef8040, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x5f5353c1440e1881, 0x7cd533db31e1cc60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x6b3b3e26201472a4, 0x30ffc7f0561205ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x6ab781fc602e995a, 0x00e5d30d71c1cd4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x5db785727b5dbfd9, 0x7210c8fa489f4a27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x59d9a2231bce31ca, 0x772657a77e18cfa1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x0b023da03d5b9642, 0x76f8d4102cdf6bd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x095f67a562a497f0, 0x129514bc773390fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x1fc46a796cf84517, 0x7023113c127ba955, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x31065d98755d3da5, 0x445d75b57f17be3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x1571b04a560f9737, 0x5529c4291c419bbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x363e309100143204, 0x0e03690a00293246, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x7b71f1de3feed414, 0x48c87c6d13f5b603, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x5bbd05de090759b4, 0x120e85a4554b9401, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x4662eff714c01495, 0x022affd866bf437e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #60", 0x7764ac854e15e5b7, 0x5df2d47b4fc2579c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #60", 0x3b0e2acf269b76a7, 0x623e00f2172916fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #60", 0x1bf8b44d6b6a9962, 0x1640d5386c148867, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x417a309916598d30, 0x08562426316a6497, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x166dbf357a5c134a, 0x319396dd77b8612a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x3a4ae75e1dbc9cd2, 0x0bae172d11dfb113, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x26c3f686695644ec, 0x672b45141607ed3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x7e1659815aba0536, 0x7cc730bb6d26e67d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x28cfeaed1f273f0c, 0x3ce93e1a757b0607, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x45c2b5b322e4f23e, 0x0ca41d0563de15bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x0e4f8ba05848c24a, 0x4ff29e2461bb6a00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x6ea24f7b44b96574, 0x1325ce974fc9bc39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x3f1578be53303490, 0x47821d6305100eb0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x70ecd1627e1b04d7, 0x16efbfc37960601c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x677149c30c2f7e14, 0x0f684d5917b0c7e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x66e9834a41c0ec80, 0x04d7ae666587a345, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x60e82b8c67a6c651, 0x5b02a94c0fb96e37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x0a8bb88f438a2218, 0x739783f426aae140, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x1bd2e4621b8c19d8, 0x08664b4018db442f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x60457f4c30271dcb, 0x68a500680a7533dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x0357525c26750250, 0x0f85428d1f5af80b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x249007272823a580, 0x18bb5827744423be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x3453239410cc9a0e, 0x0bf4eba70c0150eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x528d868e4c8b9d7c, 0x7188f4301b3ca6de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x343263cd1e8d990a, 0x2af615163375b21b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x6217bb226286de9b, 0x5a20935b3ebe1c5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x7e12f873403e60f5, 0x5799608c7dea9f84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x70657ec017e515ef, 0x085fd3625e5877c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x3e5a1840166ec7f2, 0x7db36fcb73bcd11c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x3e926d7373f5e082, 0x6800f4db62ea1f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #61", 0x04c27a9060746482, 0x6eeb705272e59107, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #61", 0x2d0001fe39184cfc, 0x0e2237e65750011f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #61", 0x57a5e60664e64695, 0x0ac5b33a613265cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x476d25307789e2b5, 0x1ff0822939bda128, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x37c843aa4008140e, 0x37a840ac45801da4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x57ed29fe218c052f, 0x23d89564282dc26b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x37facd2103eb8862, 0x1bea93871647423e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x77e168e5681cd1f8, 0x793161a5768d3a94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x4891367a77950382, 0x6972cb9c7ca3e375, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x30ad507e5eb997ce, 0x53f3e49475913879, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x439fde6376b4206e, 0x56c39e4508533684, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x6e3e032379b91858, 0x4210d7ac0b0d0394, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x39c12c677465b69c, 0x508d2138260646ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x15f1bbcb6a1e9cc0, 0x4e34093911ae5665, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x6e0a25232126fa48, 0x27f598a34dec88ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x0943cc402dec8f1d, 0x4479c38165eb8e08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x2581929f36835612, 0x628f717d51d502bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x153cede01e29d979, 0x47663b34562ee31d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x14ddf9e72092f14d, 0x5e8219a158dccc44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x1a4c09a53476f110, 0x63e9cfd8031bfd0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x28dca7ac77564d11, 0x292243d8540d360c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x6174e9d20db12514, 0x65bb8c713ece6377, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x2ed81f5d5134afe4, 0x0cbaec634f7f0ef5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x7f213f0117fa0e7a, 0x356a9cfd381beb9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x4e7d648c5157298c, 0x09f0ee5824a2d1a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x6f8103055953ce5e, 0x7ad1b4bd63ba526d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x79e6bfab2080ee89, 0x3c971eb1045efcec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x54f7df99309d3dcf, 0x077af9f71432c951, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x27f38ae14dfb8bcf, 0x683fff5d7dd48745, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x5bacb0e3495dd71f, 0x3ca2eabc096874b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #62", 0x1a9287040e5220a5, 0x58e783a80a84d040, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #62", 0x264c2f1f4c91aa36, 0x42a0bbde19b3c605, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #62", 0x1de8d3c339284c63, 0x3e5697a674c993ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x127c1ac2151b04ca, 0x5883e6190d69d6c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x359bf3531943cdac, 0x11c8d3b50c62da6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x49e10b7b08d5a31c, 0x2095a3be0a93d2ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x56d12eeb450b44ed, 0x08685a3171d4965c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x0e691c0c54248eb7, 0x7b3d0b0f327ddfce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x6276af5c7fa36bed, 0x3d02b00f28fba310, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x4c351623010600bc, 0x42af691608c2de7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x3a2e4d1f56105841, 0x7d8c72286a1de9e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x6b2b5d0b09509464, 0x7787c0af4caa67e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x2294621079a2e60d, 0x590d424f20c7505e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x0278892933c37d7b, 0x2b5b234a6c756d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x78cec26859870ef7, 0x5e4a03e85949b814, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x2dab9daf48ca47f2, 0x0bc797e30737de74, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x486db3df72e2ea9b, 0x3033818510224d0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x73e8eb5716719daf, 0x18e52b8714a2ca02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x6c81f5f076487498, 0x7ec0b3e92e173876, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x7f9908fc53cee2a7, 0x7ac1a05857ad52fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x4d71c8b423cfc6a3, 0x7874a359222d6b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x5793441e6cecdc7f, 0x0ea2d8974fea51de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x4673eb7734fba1d5, 0x293409f250620686, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x7dc5e9c707cd6680, 0x5799e4fb741f8926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x7ab0511b1d2701b9, 0x0441d63146339da6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x33989f6859971b92, 0x5ad667a96e993c72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x4fdf902a17721540, 0x1cb074e8201a9559, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x6b40f7e7703c8bae, 0x77c7e8544f789926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x140c52510048dcc9, 0x71a6043238b2c09c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x6d35b94931d11c6c, 0x089d127a6b9f9670, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #3, #63", 0x66ccbe42139b81f1, 0x3c019cf633a9a4c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #3, #63", 0x1b68e8712c0b0417, 0x27c92de66492a809, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #3, #63", 0x493205d0059cad59, 0x2ac645b01619398c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x5f33c8eb2162eae7, 0x04b275fe7ccaa539, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x38d5002714ad22e6, 0x1ce53a922f135915, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x04e9ae947031f66d, 0x7e8bf23b2415f80f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x707ad3366565cb25, 0x5cc8b8ab18f600e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x1736e7914097344c, 0x049597565db08c7f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x5432b63e39235f25, 0x115a313f7e03a5d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x652e633d0d5c938d, 0x62964ddd6f9b9eaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x12f940e60a674e3a, 0x05b4d83c2e60690d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x2bca3921481048d8, 0x2b2b0e46722d09d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x5cbd6bbf1fcc5521, 0x214062e6649f3949, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x0ffe4b8e657dea03, 0x08b5315861a71a53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x4ae3b5287f32b28f, 0x7a9d1b3900791ec4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x3fc9e6dc6f83dc83, 0x5e29ab44621a9cb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x28a73ba942b4906a, 0x601e428d13fc9d1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x501123f7094d1405, 0x03983bc90dd59ee6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x13b462406761163a, 0x3c3607f3630a64dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x2f715f127677d194, 0x55376eae3f7e9b61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x164426b52cd30602, 0x241dd4aa0c2ecad1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x1250f0056873005e, 0x6dd5e52526427243, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x67a5b2ee04e53c4b, 0x26bb91075d34a52d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x746918cf1f6d8474, 0x3f4f41e7276f99ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x622214de3f0472ad, 0x3b6c36e41d105478, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x485186b3671bfb51, 0x2ae5f35e323338d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x4e7d118b6a750c60, 0x153d9db25c05e8f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x60ecddf43fa258ff, 0x1b8484547dee709e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x6c755f0177f32094, 0x0a1d3b6f773104a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x606620f3442f07f3, 0x1d7376ec7ec64f07, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #0", 0x4914443f1b4a361b, 0x5bfaf434480bd3e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #0", 0x3ab7ba8f2ae7a48f, 0x6f7b6dab3d7d5d0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #0", 0x69ec173c0573a4e4, 0x5a8db1861cd9cf6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x6c8fa035644aa5f4, 0x4f0d0842323d9def, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x4ebfb25429c80b37, 0x0e4386e23b0cb1c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x696a643643185dce, 0x38fb225f2fac9048, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x3b0b7e6344510bdd, 0x26dd94f155dfc337, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x088013d130a10673, 0x54a6123e1b719f56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x4beb3c8e52f8e0e2, 0x637d733751945810, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x7de08571699f66a4, 0x0f11b51e06a2f71e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x6f130b887289cece, 0x237cc68b67cc9cad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x56d474c2284dc17f, 0x1a0a3a9d5ba2abbd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x5215ccb64faa7fdd, 0x16af5d7e25942717, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x12c2ddac7c1e4c51, 0x5540b75f3b8030ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x406f582e66060662, 0x115ff4244dce5c0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x16a70cd54cbd6e9c, 0x693ffb6548ef6bff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x1fb64f7e2995792d, 0x1a83c40f62924964, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x1334dfd10cb2070d, 0x693540821d96d4ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x7f3bd5db1f6dac39, 0x0563719c0247eb59, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x47bb6db97499f495, 0x5dea971756104a9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x4444747350e52914, 0x7ba471b519d13a6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x4d03756566b15f80, 0x55516b5c5707521f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x4cb765e20e15a993, 0x24d5ae2e0d72cd94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x5ad3182f70e5fda3, 0x56623993635e72b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x1a7b76d02f25fc9e, 0x45f0bc1c7a8967ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x3bd803ab1d83ae38, 0x18203c9c2db056a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x3cf15a720de2d912, 0x2ff841fb3b13d987, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x027ccda80cc895da, 0x1124242504acc82b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x5dadbeee73cf6df6, 0x1e7e029a46c1421b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x5a80cd76429e4268, 0x1dc8943a2ab13454, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #1", 0x50b3ebfb0e863b7b, 0x382401e827383359, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #1", 0x7f6c391e5087622d, 0x0a96a6112b87042a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #1", 0x7fad5ecb3e30a873, 0x26106bd719e7afef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x5bb456ab7790488c, 0x479806913b856276, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x0573219f07bd6022, 0x76993bfd18a5b11d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x1485f5fc3bd07be3, 0x1d52794807efef47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x2f9fe9d96c79c59c, 0x4eb131627233b4eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x2f1808045508eb27, 0x1ce4e93f0a20b750, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x638f26a23bef90ba, 0x3158eaa97fcbf3ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x0c76f2e751636400, 0x2b52f82962fb5fc1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x0f940c73447b1641, 0x7ce30fb00c2451b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x3c0b5ecd3e42f026, 0x47a9b4286b48631e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x4600504821408d84, 0x03ee143c417e806c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x5d110967181fa115, 0x496e6fb35a864645, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x049966b1699ee46f, 0x4cb9fb300cb0f341, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x3ea7cf96482a953a, 0x16d1aa9133b16eb5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x041a25f45ed05add, 0x337d62b42236f638, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x3033bedd021565a9, 0x053255f9109118db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x46907bea645f1eb5, 0x1cb56a8d3fc7cb50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x22a20edb2efe42ab, 0x2b102e6f029bdab8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x503ed02f0d88cad8, 0x441a5b2468a25f24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x25a86bed0fe2a099, 0x4328a5692d4fd997, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x7981850850d27769, 0x3a00ccd82a41d29f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x18fd0ca31170a409, 0x5df341543829549e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x7040fee65f92a0d0, 0x5a604ad61d173297, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x61a806794a5db5ff, 0x2da84b722074bdc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x2ebcd4b40b4cb783, 0x603c891428388264, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x3a4afa2e6eeeb840, 0x2ad45d1c515ee390, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x7c7783187d29e81d, 0x3a0142b40a89ca5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x0d0c88b671da70cd, 0x37d9a3f5221fef06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #2", 0x42ace8362a5502f9, 0x4c61c1a5068e0dbe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #2", 0x3bc5a7021917ad32, 0x3eb7625c5ba9f4d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #2", 0x78aa4e02266972e2, 0x78c127702c06a5e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x70c728e12cb7ecc1, 0x4c7b63ad5a52547c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x3804a4452d5f33fc, 0x028ad6e01f83fd95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x1c4dec3c2ae423d9, 0x70e2e125724f9e73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x280e0bf634b30cc6, 0x7cd968d118c56f55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x268d7d9307472000, 0x3ae55e5b351a94ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x319c22f97a6004c6, 0x3ba8a26a693a65c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x1377b1f93da58212, 0x44e45aa26d61c9fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x640ef4f465e3d392, 0x19686fe50c21fffb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x129bc05368ff2b57, 0x6674547754d61dd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x165e5f53653cfc90, 0x745a1b6b4aa06498, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x1021206a39c96bdd, 0x3cf0030c32ac4b90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x6e7c78a406571940, 0x4b71bae5382f2c60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x0d9e394028f26377, 0x6d49c10d1509f637, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x2352683e4328b6a3, 0x7e445c013f3a5c39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x00ce38b64604961a, 0x2c9c263536ca1a37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x2be869ac29606eaa, 0x42ec1a3264dd2daa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x125f9a012e0d66eb, 0x39b34b803e842a00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x134a637b461491a4, 0x09248e9828bdf955, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x7fddfd8226dbffca, 0x5b6a44e5236b83e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x2d33190a48e47153, 0x5b9ab0466e5a7626, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x71d6d4ca01a8c85e, 0x03646c5d3ad1524a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x44d17f0226a7d4b9, 0x7a0bae8315293d08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x6cac6ad30edf7172, 0x4bf3573f459fb7b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x383fe01c643030e2, 0x2a7ce5621894d480, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x123d97cd603d8d18, 0x5718fe804a9f7a1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x26521ebd4ec7b857, 0x735d73722587fb49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x75a3b821248e2f74, 0x48f37f2e26301c3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #3", 0x6d72a0c717eefec2, 0x148a926522d6d12b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #3", 0x1997c72157b3d1f9, 0x5da823755f497592, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #3", 0x7e5ba6b2406609da, 0x7472b29a5e694623, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x4f457b4c4e85e33d, 0x2408fddb6b081185, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x32b614205ab5e485, 0x039ce60507855b68, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x3af3719e458248f8, 0x5224d58544f3abed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x144a014f336f2665, 0x6a7ba7366145905b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x57fd55d91c003eff, 0x0775ac9a09edb971, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x33ef3dc10a6cae12, 0x2cc48a9c456ff6a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x6220800b192c1ecd, 0x24b96c334d8704e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x599228a74ff948e0, 0x2bf04b05607c26bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x1e7f2c1e4f211e48, 0x4b84384228d7a3f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x29d702cd0281d4e1, 0x305cff5b5135403e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x48041dd900a49362, 0x1628ec2b64ca746b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x3413b9c74d85b160, 0x461004c65c4e1f28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x6985f05f13006336, 0x663bd8990c110fa0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x1d6d1148763a7274, 0x518106411d752e21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x0f66914216ec7e09, 0x6afc33037f8d9153, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x66e5c6e92b8df052, 0x6009b81068f8b9e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x7aaf0e9a422d5d38, 0x11d05ddd0564f307, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x44af32196cc31f71, 0x569a334524861168, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x6d67b2d34f608a9a, 0x095085d30cb34ff2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x1ce63bfa4f3d47b4, 0x69016f1b217b6c9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x623daaea7f0d827c, 0x2d8c7c3a066c2c5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x7547f4f00edd8d7e, 0x23e15a7b7faabc32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x25ca0b875f420595, 0x7f384d8504ae8632, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x0acff5e87f779df9, 0x6da7401c0cafd271, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x41a4fb3168aef8be, 0x1214c578057f0482, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x5572182f33559bbe, 0x2a0515ea06542d4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x02b626587c08ec58, 0x13077d3d42d9cb02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #16", 0x4b46340d11e1b3d6, 0x6455379c1f9c6252, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #16", 0x10ef365249e9e927, 0x26088eac2d83def7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #16", 0x58c776a62c66e8af, 0x2d2e9b2a06372b43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x0ba8ee45788cf191, 0x0ae5b1757e91822d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x78048f8a1d561a17, 0x0b41549e1678e42d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x060512d545fcfe9a, 0x1bf7e8af39a98abc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x79529a5853053544, 0x3ffdb8075b772b04, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x4f0e219d02a62da2, 0x1e50f6067c08c0b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x1487e17841adb1af, 0x1ba523021a5455aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x0b979ad67506cfcb, 0x47d834a1257717cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x216db87b3693f483, 0x2bae430e645f117c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x2f20e6156e31e848, 0x62f093aa2d16a6c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x0b88025f5f87739c, 0x438f8aed2725759f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x2584723620ccb862, 0x60cf005b118d1534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x73d1eda70b55363e, 0x6d0440381ed70c8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x0dfb63e03684f041, 0x1adfcd3e42e00f44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x7832a1f0250c998f, 0x5d3464ee22834559, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x1a13695b73a8a032, 0x47fa5d2403ca3cc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x2a3c94b54b19e1ed, 0x68294e433b8121d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x394bca352c275383, 0x6897c896595d7aca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x0baec71f6151f0c5, 0x0082f06a44d3cc95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x021ea92843652202, 0x5660e1c931333956, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x4eba58406aea1323, 0x500a45e475f096cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x216f036416050b01, 0x38d0a6135cb5bc21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x3b11a49047335e9e, 0x7f39017a19a1a554, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x3adbfed00595305d, 0x1d6be21a55250deb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x50af124a793df857, 0x10a62fc165189385, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x25654bda3ef8feba, 0x3e760e5009fadc80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x204aef7f252f8ade, 0x4ecea915311412fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x6894ace032519234, 0x62474c50226998a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #29", 0x1d3ba557512ad589, 0x185a2f76374f0521, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #29", 0x672fe08a133dc2bc, 0x1404c1423eaaa8bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #29", 0x5a71215a75b8302a, 0x584c4e0f2241851b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x7b4d6087080cc2c8, 0x77669306154d202a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x014abb1f38dbc1ff, 0x7a65b3af4bfc72d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x77d4c0b924c5f867, 0x55f74f5226b006fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x49f583453a0b6644, 0x57c419f4181fb039, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x6c5cf87852e37857, 0x3a8948e0328a3026, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x240e4de07dddf689, 0x69d9354709989dd0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x111bb945208f949b, 0x4843468b0b3e2e6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x1647c4c524e6468c, 0x2d7fb3866b8cda9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x2cf309547b3fae78, 0x00d9fac91195254c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x341b70783388e770, 0x5d91981e2e3dc474, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x584edfd72cb1e562, 0x54edcb6e2bf03131, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x66bd4ba67e992a4b, 0x440fe16a2244631d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x517ca2a23ea7c88a, 0x54ce9343531a441e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x3c85bf1324f6287a, 0x5cb2e1ee758af082, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x4585bd152e48d273, 0x00c91eed4da17858, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x532f19003a084dc0, 0x392e52f75bcd81da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x3547fc384af43f45, 0x6d62a72600222254, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x7e7d26b5034db236, 0x2e5fe6c869636cb0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x2fff979859637f4c, 0x15539de256cc068d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x57fca9974ddefced, 0x791069aa16bce33e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x0c86c577468a094b, 0x69d7275d29794c39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x6b8031c51fcd5ba9, 0x1f043cbc490c848a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x4e162e1d4fdc4fd9, 0x16adfce23105eeda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x09e49d997a3617db, 0x0cd370b42145471d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x452a57204fc7503a, 0x216769713f2c99d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x531502703de3a464, 0x2890068243a77dd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x174723b01383ee0c, 0x1a73846203149a09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #42", 0x6162eaf903a8a4a4, 0x19d17d476f43cd48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #42", 0x4a32adf037c1563d, 0x18bd19816de9b070, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #42", 0x578eb1e74da431dc, 0x36f634fa35b2dfb5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x1d8081b5738c3f44, 0x66b8ce9025a4e004, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x6dc2571f68519092, 0x46ea272127651f4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x3818e0cc0f21bfa2, 0x6691b92032ecae3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x4d0564061107b077, 0x76942c150b2de33d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x248b9e842813fa8d, 0x0e427d46644c87b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x2bbc9f326c4d6e80, 0x539054fe05ee897d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x240ec4bd2ace6ee8, 0x73d839ee75ef4d22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x7872a0c5125afb67, 0x2ba22cd77b9d76a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x05e73aac682c7dc9, 0x214256a815f3227a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x507e0e5c23e9fae9, 0x3d5841c973a991cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x330bba8b1d2a6c20, 0x2696400b0896ef28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x2e321c9722074fab, 0x13c4d26500111e91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x4a1b4a3937edfb46, 0x645da64752bdbb1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x243b69c64c847e87, 0x58ac449975d7e96b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x7752ed6f17696364, 0x6bc7368d484a2e83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x29c45ecc6529fbd0, 0x43e7a5286fc58e34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x4d56799a4310f278, 0x05b8b0af2fab9978, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x66faed6149eb6b4e, 0x23552b431dd487f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x6715d76e3a304984, 0x266b771e1a06a7ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x5c37992f7e756cc4, 0x1a17c67d1547f406, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x3663680a40b1f3ba, 0x6805af212652e368, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x0d36724107f20360, 0x1c2accd35a9ed1d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x1f5b66c566d0a57c, 0x22e9005404895fb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x4bfaa14c7a079e94, 0x744eede5491fc591, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x3d18910c1c208a4c, 0x78cb5f0919511ae6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x660bf59b5d9119fb, 0x3725a2dc24137e6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x17c1637f5831ecd6, 0x3e1a26594d21cd09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #55", 0x56a7599b4a6f7031, 0x6269c10f73f8fcae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #55", 0x0b2163eb3676acea, 0x1a4be0170d0ac1a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #55", 0x3e68b04b0a9293ca, 0x67a993761857d62d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x71633946113023c3, 0x1ce135de5dc41710, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x0b37c2581faf3baa, 0x26e3dca13d5dda92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x3bcfc5f60dd49855, 0x56aef57948505364, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x6b65b2502a7df82b, 0x6c63d1d221dbbb91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x02afe502516749aa, 0x6efd889b032715cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x1bd6b9db116bf295, 0x7720127e59573e9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x47e29f7f4e0b93b8, 0x6662004226f81dc7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x589e27825c3129d2, 0x3f4ff3f4064b4fca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x6d614d950af3437b, 0x640f66da4a0160c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x2aa27f255e0e30d4, 0x075f3b5b78990fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x6be2c9292d4d3524, 0x40e963526672451c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x57cb2d4f774b8948, 0x084e00ad57487b7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x48b2d2f3518fa3c7, 0x5a6f91495a7b1251, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x62fb965c1a345131, 0x33d250ee64898cce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x683fe4e94ad19e89, 0x0b81aa952ade35dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x2702c85b1538ec81, 0x312985a640de0c6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x202c2ffc123ea88f, 0x0adf6d34146415f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x704cd9634de68930, 0x0cfd25de4aceaf22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x7b33be54398ef4eb, 0x3140f43e5c2fa28d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x30da7e340de7af50, 0x33781e0752feeba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x5f775318614c4ee4, 0x2d79fdf5798d5127, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x7b80a0156998888b, 0x5e16ddf54272e974, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x346a27141e7aa4f7, 0x6d511f5063c084fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x33b391782f7dfe9f, 0x249e916a5b6cef70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x41bca72e7cce2b3f, 0x6fd1056153dfc174, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x4ab4b4704fef64d4, 0x1eae709632098092, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x097e59c041b14126, 0x0e39231f45e872c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #60", 0x4f98f07646615c5e, 0x18e75e683a58d7f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #60", 0x27adab4211fd0710, 0x33e6291b2f10438e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #60", 0x7b958f9b5ed44c53, 0x71832d03232e4b57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x7d4ef14a2b8d61c0, 0x06eed0552fffb6b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x5b0b605f7b3dab81, 0x0b6ca620310282c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x780bd6c02390b4cd, 0x04e244371cc8078d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x738019a25d0aab3e, 0x4ed1881f42c08b30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x1ebbec6421905c5d, 0x08a8fdf57cfe7362, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x67f1b8bb6b3d7471, 0x37574b566e54dcdb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x7d3a7b810ee84d6c, 0x1d6520690f9f63fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x6dbc99c039bc7faa, 0x32cdaf5478d00b1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x6549e16a343c67ed, 0x28cfc1cd6b0b8b0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x2f7a136e20f05204, 0x1c0e0dcd405541c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x448106d12beed176, 0x5d1d49562785ea2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x08f97cb472ef7354, 0x6a46755f38012073, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x147fcfb16c56df2b, 0x34ff93d527b56919, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x5794539c336f665d, 0x160a45f47c71886d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x4257b3ca3ede9bbf, 0x0c10ec6a54cecf1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x789b1b69766e9c08, 0x4d9eda3b30144d8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x2aab03f5372de661, 0x1b1fd8945de4fcd3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x581e38657b5787f2, 0x1e3a3e9c5a251763, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x274659686bf176f0, 0x01ab01911c9f3f37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x5ee0ea44099ff380, 0x54a05faa303fd61d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x75f6d2ab6dff852a, 0x57f53f367360b9f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x216eeb877be32ecd, 0x6fd242634d8b2648, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x3ac1ca8c6ff8cfa1, 0x2259f56663c69f51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x66676ba92efac570, 0x13daecdb335ce5f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x6628abd12f7c2164, 0x1141e2c811126f9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x2ad3a9576ce28892, 0x6b3787013e46e437, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x58d3ff832f868318, 0x5ae6236e521a02bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #61", 0x392676985a4f1812, 0x0259d8dc37b4e9c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #61", 0x484e9d3c1ae7e620, 0x2b15a3bd2f1d4944, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #61", 0x16cb14ee1f0264f2, 0x7ca86f8c69bd88c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x0efb3493615f14f1, 0x4d842815518cdf7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x1059da61162ba838, 0x04e9c5707562a03c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x45a7c99d71ac96db, 0x06750fda76828632, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x5e8f1f6d0faf8dd7, 0x34c96a69707b72f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x3f3610f044ef4e90, 0x429575b337631ef0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x1f3e66a21a2dac75, 0x6f1808b8785c8788, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x3515929624224058, 0x2779d0cc678d03df, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x4324a54a1eceb4b8, 0x514a8ca34be0a784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x002dc9a922574c6e, 0x1d6d86fe521fd9dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x3882f4a74df789f3, 0x47827a191087a40a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x3fa420ce3bd394a6, 0x070a2a3d7e2abe44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x4b83227e313ba6eb, 0x6ea631381e33403c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x762af57b44ae67e4, 0x55965f2c0ab9336e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x5edc145a2a8f8bc3, 0x0315baf615695c1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x4eb1cc1b4e40eca0, 0x7cf65ffd13f1a6f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x6d0fa1587d3fd572, 0x5fd24e7411d67166, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x1f9721e12b78c55d, 0x63f64b436d3d6b02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x79704f5004cf3949, 0x7dc50f0c581a1688, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x40a2cdf044eb0604, 0x5644d4cc3914701f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x7626acef2cde0f87, 0x5747b05b0c25f06e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x718c776c19f4ded2, 0x16df23dc6c51a26b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x44846a957eb15e86, 0x01bafe8950688bc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x4cf24b26442c812a, 0x645a32b6133636b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x416c569c0902f35a, 0x250ca8173a01ec7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x347bb8b72504668d, 0x273f57806103787d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x29d39fd60f6263d1, 0x391d8f052dec0808, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x544d69d53e482882, 0x670078276a766dc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #62", 0x6b2638090d7b8210, 0x769c5e344a7416c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #62", 0x277060e33880b7b9, 0x36c5b9305cb2af75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #62", 0x3732163f11756df1, 0x2d1b3b3b6bf4cb78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x55a1ef1b2437aa40, 0x7f2b022904246165, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x2d3a9d9b6565a564, 0x3e264de3170e45b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x0a6a0bf1312f4d3b, 0x7811be3561b65652, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x4091b10c76a2d681, 0x0fa25e5a343dabc7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x34eaff03155077c2, 0x1eb4198e14df1ae2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x22cbf9d31618ead7, 0x5f5331a72011370d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x4e99a29029df21be, 0x7cc3e6824a3c5ab6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x3b548faf355c2858, 0x3631262e05cbb8cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x5993d29848166817, 0x09f01a3410f67ecb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x2d7c0d7b201682b8, 0x2804c48306ce7033, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x5145cff3782724e0, 0x6884c68637e6196c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x6ec9fb620ad7dec2, 0x6c23c53411d78100, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x202856840609cd89, 0x26b69be223b4fa65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x1c22b860408a17f5, 0x43c6317242f45057, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x6a6939b34361d13c, 0x0d30ab0d6abc5af0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x78bdf9947a782df3, 0x708813bf25bdc962, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x428e960a5eb90cb0, 0x36b4482d5251cc2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x7ecf8f6941a502e6, 0x59203c60700aa386, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x39cc27c614148226, 0x27f0bcf250155f5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x1eec60e808a37c3e, 0x61ece05c28962328, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x0ead49c710114f00, 0x4c4b1d8e3f14b76d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x509b66f50f39b2d2, 0x020907c42ad00227, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x529b840e061470d6, 0x158c5d173b04a0a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x008c9ec91776b238, 0x60c26a0b4b597da2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x762fbee976cb862e, 0x1dab49ce431b34d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x387089145b16954c, 0x3325d85a74ff4e52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x6f2b177327018e0b, 0x4514adae723cb0db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #16, #63", 0x2fa50a49671df191, 0x1ad2d4030e17785b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #16, #63", 0x772f40924f35378d, 0x4d2c2fc83e525411, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #16, #63", 0x5e6eea5f7eaeb350, 0x6922563847caa787, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x04c324266391b23b, 0x02cf4830310a6e6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x7b0864731a0f35dd, 0x7c63ec0f054fc2f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x10dabc0c7b90d01e, 0x486af7c47138235c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x56a7656a2b4c1f5d, 0x663771ae494b4520, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x524dad68565ac9ff, 0x3b87f5fb45d27cdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x3d78bb9021162501, 0x53e9f53901f2b7b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x704b5c8e296761fb, 0x40450bc234a7fc22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x2816154b7f41ebda, 0x7c72a3aa4eba46ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x62d39e157c28a169, 0x7fc4b55a2cd93971, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x1637d7477a93f425, 0x3228fc615ddc0288, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x7624c443354b9793, 0x4f1425e527129353, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x6097b6f02be5ce6f, 0x705dd8734ccc29ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x0240986e66889bc4, 0x129ea68b32e56458, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x079ec0c6751d27cc, 0x34d81c0a3fb953fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x1e8489c770d3f3cb, 0x7461502177ea1d54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x7015dfa54669199c, 0x46a46442469a9f12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x4291bb06259cd4e5, 0x7373d88452e97dba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x2030c90b7fd9a627, 0x30c5804258c9924d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x35253dbb7039fe13, 0x7fdc25a016558d4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x1c1fcc8275c05d88, 0x6321b6fc15bcf4ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x5c48f94c7d7a750e, 0x48a259041e6064f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x72979cda527b0910, 0x5e19b8ef63e7ba12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x434efcdb22763ba9, 0x5bd1d767111c26a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x68df55454b2a9e38, 0x57b6c5b43364dc80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x70c7731e3713da7c, 0x064e5a3a2b71104b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x36ed80a40416c838, 0x043aa29810f83c29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x7450c64c0a6f8074, 0x274dc9776c12be5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #0", 0x002fddfc4a720c0e, 0x01cfb30a107092ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #0", 0x47ec811c0ceab0ae, 0x2ed0f7bf5c78d748, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #0", 0x5f65b9be1c3268c2, 0x4060915b3a841df7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x3ea8a46b23570a4d, 0x4ba0449922b4b699, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x6e81a8865c67ed53, 0x561993192787f9b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x137bc7cf5733ac94, 0x52f909fc5f491ba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x5b4a74cd178f2144, 0x704157cd4a694873, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x21fea1b8384bb9dd, 0x367c06d24f9b3b19, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x02bdc5eb0edcc5a6, 0x600bcde7222e7fb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x1bc776543f07e858, 0x7ea756fd4aaa4708, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x5b3a511a50cea998, 0x052e64ff7b2d3012, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x7425b3e573fb79c4, 0x1de1e6ab19e2f585, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x506367171463f931, 0x416aef3562a75c6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x6b97a5c63231cfdc, 0x41f0780f63df2ee7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x49c0f12164c47e2d, 0x2e48775a46e21a93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x1d10380a76892393, 0x167d55ac6bbf92d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x0565e93a0c95698b, 0x0dee128e1fcdfdf5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x4b9d51e36fa6a9fc, 0x6a7844fd212d5f8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x407553943a3c764c, 0x1c5a8fa126d7a2fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x2e37f011022587b7, 0x40ba9882349b077a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x168980e95932dbf5, 0x174263e57e9b5728, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x0b64abd110c2fd6a, 0x627a860f022126af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x75877b975f8096ee, 0x4903414255259cf2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x5609ba814ed3425a, 0x40e52fcc1297b3a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x5b68abe51cddf694, 0x3265b1965b6fa3bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x0c84a09018f792eb, 0x7c9d034a2705fdc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x533409370e983947, 0x4ddda0c54cf9f425, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x10bdc0fe18d75f84, 0x0194fb9f016bf948, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x720a3b796281d680, 0x00075071274741e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x7344d3ea726ba9d8, 0x296868967d6ee74b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #1", 0x51ec40c61379b409, 0x5294843d68cc4f81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #1", 0x624cf6632dc9b4b9, 0x7b64032227f5fb48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #1", 0x4aa7ab4d0002a24d, 0x03659f033db5a248, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x18fa3538329940d5, 0x64bba010572c4bdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x41317a1c25bb3ba1, 0x242640026c2e3e70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x3e929b266da18829, 0x6d9a37b851ef3b1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x50235eaa229ee599, 0x79367d02309cd69f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x150a8f7100a04228, 0x2e0bbdea43683294, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x1419f63127988538, 0x2c34821666f6d038, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x556239f112526a83, 0x0eeccb807666ec95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x12550cd118d82eee, 0x341c8edd2009e53e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x4b716fc31b5c711e, 0x7736311c2b4f4209, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x4117acc00517b832, 0x177d80790ca2e9e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x72b9405b57c8a1fd, 0x5e9224fb7faa47e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x7a6787965e52dc70, 0x30471e8542dc9f05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x5ef31e98327953b0, 0x0644d19a0f721708, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x5a11d8e80555b2c0, 0x7668e740730d14c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x17a81d431d90903c, 0x6974015e2f7412da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x3668bf2a46b42934, 0x4f7df81829fd2a14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x62109a536cc9ec97, 0x554c6c1e01da2eed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x71e1a4c96d0f3dc8, 0x0e7d18cd23284713, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x44d7dfc65319ad7e, 0x22d28ef9649ae525, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x316c89ee2dbc55c4, 0x2777842a3f3f675c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x6035a974451a65a4, 0x4eb17e64105fa886, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x4a7018646ce0beae, 0x036cbd503a47825d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x0a714eea39398d4f, 0x69bb9537621835a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x7fedb6846161cbda, 0x0c155fbc40da0e14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x4e2bb872513155cf, 0x42b43d0261fe50d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x3e40939827f926e3, 0x052697ea400d5d3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x7b12d4614c1fc68b, 0x24a842600318735e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #2", 0x79dc1c4f1109591f, 0x4257daba2c7f5e50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #2", 0x5623bec3404bc426, 0x3cdf06d65a11c5c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #2", 0x2d2c82d57e14dd58, 0x145948212093d728, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x374e6aa70ec16c8c, 0x02ac0cd0379dd1bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x702338673b2c1cd6, 0x7877dfd4373c212b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x0c5d72a51e6109ec, 0x193a72023e4ef0d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x465a30cf23049075, 0x7e5c4e144a9e063d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x6f245700100e5456, 0x4db6799b416d0531, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x2117ad752acb6a57, 0x6dec63816900734f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x6b172e7e576b8134, 0x43123913773b6c38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x55805e8c1a7b5030, 0x17cf43601843b153, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x293cbcbd485962e6, 0x4fe183120ccec934, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x03857fbc5d455c62, 0x440aea5f195ff524, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x7ba6664e560b3411, 0x57aee5fd0fe2f262, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x790fc4862837723b, 0x5a80f89f4200971e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x3845c6917159ffd0, 0x036d9c4f68341b86, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x1c256a271446c7e9, 0x51348ed6595d7406, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x6bb2491e6868239f, 0x5098e03e073c98a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x02e373cf6f61cd0b, 0x1f8049f84132a7aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x37bb2ff1120c5b3e, 0x4e0170de2c20308c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x6f51b7a01d2f0bad, 0x458025b03b40afae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x733a3fbf25a49aaf, 0x4b23a2106af81dee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x4ddc0cea3066515b, 0x2cf8b50c6c4a0445, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x21c0512b25b2aea2, 0x547e1fcc0621d37b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x39f9768b301827c0, 0x5f7f47813de5bb53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x18804b5f64a29df1, 0x452253f825abbfa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x54046afc34dfd832, 0x66de67541b63bf2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x46ec33700d04156b, 0x4783efbb0bbf9aed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x2a3321191223ecab, 0x47004a9b363deb10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x37c8875b4e2ebe0b, 0x213608ff1d6d60d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #3", 0x7e950f675e3584e9, 0x09b7651d05a49445, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #3", 0x03e8338b6b45af42, 0x0bc667c120556092, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #3", 0x1b5dd702235d6fde, 0x5e3b1be53de1aa17, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x08000dcf4a6bd114, 0x638d69c033de2261, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x7f4ba94716c5d14b, 0x4f41e1905c0478cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x23c9e6b62ec45e54, 0x67c413b84637dcb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x40e84aff1dabd0c7, 0x7c75c7c84dfd07cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x6bda8ed27521cdc5, 0x6b6a68a778b0d25a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x535752ae0a1bce61, 0x7e5566a06a6f9e39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x75617da369001ab1, 0x0ac4fecc573f863a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x0c5d8a8f78ae9a11, 0x1521305110bf54a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x431a6b2613df5897, 0x449d7707145d985e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x2aa529e2582624e2, 0x706211294266146d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x06ea83360513b8ec, 0x089df1244e6f1099, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x22bf89b307d68110, 0x1c6c186847d2ce35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x7cf84ed53ed90730, 0x4083a0900e9a1886, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x48f4d59103ceb58b, 0x7909b6bf504fa183, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x6cced03d3cb0580e, 0x278f27bd3e565334, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x355ef22013b31ee2, 0x4f15a7da792c5acc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x279277797dec0454, 0x0d89f32b78795d46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x56122936437d62d7, 0x3adf71b35237a15c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x48911bc43d12ca5d, 0x20a6b1f55cfcac6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x44e94b6d65531b32, 0x24cf7aa26b50a577, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x242c226272f474bd, 0x79eabdfd41e19a42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x76c32a4839c06383, 0x12313bc66d20f7f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x7670bb927a8cf302, 0x2b774b276391fa85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x0e4011e46a48487d, 0x5cbe55522bcfadb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x68344cd15f287cab, 0x24490af835d2895d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x22a5df8228b0dcae, 0x080a2ab93e467608, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x65c3a70c40129d16, 0x1b4322746b36fb46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #16", 0x2565b84850725ebb, 0x5687a0be2aacf279, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #16", 0x4366d3787ebfc882, 0x6c8e8cbc4991daaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #16", 0x38802c05622a1dc5, 0x36b2d29d3a29fdc1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x5cb710c77a7a4d98, 0x1dbbf8462ef0e797, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x64c296157f09a041, 0x5ac095496af722ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x5e321cec28d3d6c2, 0x20c9ac084cf6e2e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x5184b37026807b63, 0x0b3d58ef00d7fc6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x6693187a42969873, 0x6c0ef7b537485a7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x1308f72f4e83d9b2, 0x61f54cf60bf8d0c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x4d43a2340c3d7e0a, 0x558aab6d566fcaa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x6e679bcf2e55c0af, 0x1099c86805c3ce39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x28d00e470f754b1a, 0x34b4b5d14b1eac96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x0e7eeb5c56df7b4a, 0x3615cf410d92a45d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x7fb3520c65c6e033, 0x5a8987446cb10848, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x0c475b965997fc6d, 0x6d8904b75138057c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x1c2e94e06a75acef, 0x08805ff972da7410, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x38f986a1545df040, 0x7ed344d32f378c0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x609b6e4a16411f1f, 0x05a756b7063d28d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x4496dfce40b5acdf, 0x0c00f70e4f030a1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x502af7fa503785f2, 0x1a21b6b06d66ee16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x2717013c558319b7, 0x7af992735ea9e356, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x3b49f9ea38e3f056, 0x4b5aeb9e26ca5348, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x127becc30082b8bd, 0x780258c447915580, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x6af865ac393f0e64, 0x3a6bc9912eaa81a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x0d9cfea46389646a, 0x5de20db323f1ec4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x79ca838936300c31, 0x2a2f15226e386cee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x76e5b910575d2db9, 0x3d3b77083e616358, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x2794b3ab26c1e3e1, 0x2bc8516e4710b10a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x7c44fd9871157fff, 0x25ba94604eabb4e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x29f970556d7860f3, 0x7576082f378ef782, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #29", 0x6dfb19b1398c1693, 0x7f204d023c755d18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #29", 0x72cb24f74901ec6e, 0x6b1fdebb58f37f5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #29", 0x2c8b50d8271480cd, 0x7ce56bab0068239b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x5d448cfe2bdc0792, 0x6ea0908a2655d462, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x0339354b107f8928, 0x64b737ba542a460f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x37416d0940f58b7a, 0x1b3af7192acde8f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x320b0b796eefa60c, 0x79799ddd33866aa1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x5c6807006a35af25, 0x6b1562235c047bce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x23c1c5b90399b7a1, 0x1879d8e64a6320b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x4c9ba410203c0bb9, 0x2356a00e168ceab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x47508c8705959ed6, 0x16f50e4c7926f4e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x3171a66804340104, 0x1f7cc94a24951985, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x14b38a2c13fa56ae, 0x78bf5f9434aadbb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x54efe22858f26288, 0x5f78c4aa4bf4f735, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x47e208946a90c3f9, 0x7f7b61d606faeda1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x54c6731f7b794255, 0x62ff696f244a0f94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x7f12f9f61203d054, 0x6ead3045788838d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x323fdc0d260a31d4, 0x0f1523884bae9e06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x2b9fd0aa64525c39, 0x44d592ef79906894, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x68865d3e16e4e1ae, 0x1e25821a5d117713, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x2adf385c71351771, 0x11bc52c77d39e76a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x4a2779f948aa4076, 0x492edea07fcf1a84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x333b047069c97194, 0x06ca08251209828e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x6542b3e92500c268, 0x365392220801778f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x370492bc0f9ed3ef, 0x0089b0676455ade0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x35a905c474d9ded5, 0x30044be669446ec9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x592c3b0f00fa5978, 0x62d4d75e6148d66e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x17df3b265016a048, 0x3e5a4d8141b2984d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x414bb7ba081b5e57, 0x3eec7fb742be7383, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x50c59ece4957962d, 0x428d8e070b7331b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #42", 0x332107c153d04664, 0x1d7cb4410400a33e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #42", 0x78d108cc0c8bcb34, 0x0c021acd1863bbab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #42", 0x1c2a9f232cbdb571, 0x7cb9698b2fd59b88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x219794477beee1af, 0x191a0a5151d3a4e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x7ce93b277176c8d7, 0x331c7b567ac3cf56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x418d69207b62e75a, 0x3c7667a314c8764e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x037e45b21a1477d8, 0x5786e9d102d920da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x636c0e052bc906cf, 0x0e4c528d5443e480, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x7f994d336446a28b, 0x584487be168d15c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x70d26dbf2baa3afd, 0x2ef0d172786a55ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x5867f06e4159fbd8, 0x283ff1870cfd0ce2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x3d48dd8811ed2d20, 0x5ed0b1ca79ff84b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x0363f5f73139bbae, 0x74c3540b3a3218af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x2c9ca309268178ce, 0x4efa8efd44f15f17, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x4095f0a75616d27f, 0x47ca7ff1301ae8bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x01dfd94e5ca354f9, 0x045ecd3b2401feac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x40e9f784697fe5e5, 0x3a8f147301792681, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x152a20e222236e07, 0x79e37c8031bc6543, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x637d69df1d8a23ef, 0x3eb972256d921151, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x2f77510f5c54ea12, 0x6791960620c64767, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x0d8ea5c029f2ef14, 0x5af8601732db4707, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x507467e33f972610, 0x77cca61e3a2b48c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x15adf88f6ea4febf, 0x6a463184110a588a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x4b4853b86f9b6baa, 0x350c5736178dd1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x591b518f12ea74de, 0x1906f85e0c324b3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x350de2e57ca822a5, 0x3deeb07f6e457272, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x1a324694436919c9, 0x5bd783c3188b4cc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x1fbe03db1449f443, 0x3951942c49a997a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x3e3ce357745184c9, 0x7c84deab2d4ca99c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x33e8aad951be23ea, 0x6777f2650eb14b3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #55", 0x406322a954c7fafb, 0x1fbba3c44996a368, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #55", 0x446366a57a2b6da3, 0x612475450bab7662, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #55", 0x0d15e28155cc721e, 0x17ddc19e1d7eb834, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x527494c3679bae69, 0x0bc42aa64223c566, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x2b04c8331400a657, 0x5aaf122b6ca6db57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x284a9a9a32d551a6, 0x365072fb4ac2cc0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x2726d6705f876810, 0x780f75aa66877df1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x31458bfa14f46cf0, 0x7538c92c5b0f8149, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x69bc67eb05ca99f7, 0x24a624b271a8aea3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x7ff6079b1531e6a4, 0x7d5425052e1fce90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x6afe58c25762b16b, 0x4b9e86c50d0bea1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x3efe5fd529dec1ae, 0x4f2faf833d72ed85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x3ddf6805606a3bd8, 0x2a19c8dc6a032808, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x133f8d7e2cd569c1, 0x34c5f416662a029f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x0c5cd1d141ea49bc, 0x4cb180903a6663ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x56deb6ad3a1c09ea, 0x1575e5383da25dcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x3fe6a3e12c9f3174, 0x2f4b0c6e409b1e98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x41d118183a5973ee, 0x6ebaed293fdcab7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x11bc25591c18451c, 0x4ce895992ccf70da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x45f706ca145c273b, 0x6a425e5f50ba852e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x74c663136f83a14d, 0x3abdad3603d66ecf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x1c590b0e36b1f1fe, 0x6a00716e0805f092, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x789c3bbb57e239b8, 0x426c548028b5dcdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x11fe43a215a34718, 0x66583aaa4f7af268, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x4242788c7ed0fe29, 0x1016110051e4e784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x392a72175eaa2899, 0x11c19300041390a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x7ac26db51b255fdd, 0x30e3017e4ae69771, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x2f818719565ec9d6, 0x1ba11c9f40b9747f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x45e26b232e9054bc, 0x448fe34e2447ea2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x654246bb6eba2f3f, 0x2c4ddabe623b7631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #60", 0x469c68f771498dba, 0x0af153105dde8276, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #60", 0x06ecd4d23d6f85de, 0x2d5974de589aac9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #60", 0x3c4084083c41271e, 0x2a7f941e492f4d5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x1aeb4fb87e25df82, 0x4d42de03756af61f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x194b3f5f5bf2aa30, 0x40518d9015adbd6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x325174061af7153b, 0x566731ed48ccc678, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x498769f819628b63, 0x6d14b0a57833df29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x081cbaa26560a86a, 0x5a6f555a2ec9b0b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x56aa36243a01a807, 0x0ca833294eb9239a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x77712de551d36452, 0x2753d0345d970af6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x0e148b7074093659, 0x26c6585533b1b1ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x722f15db696e359d, 0x291ca80d28ffdb28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x4560dfcd1514ca83, 0x3ead98960b7a553a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x300bdfbe415bcc58, 0x54471bb377b253d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x5abe57bb4a558856, 0x6fe632fc799349b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x2fb630c035052d92, 0x285cfa6962db125e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x6f06d59958e8062c, 0x319435f8066066e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x2abb6a7e0abdca30, 0x63f771db6678037f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x7ec7008943465d79, 0x1a29b56c38cff5ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x2cb49317207d69ad, 0x61cfd11770f61664, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x3592343050b78752, 0x7c706b9f721572e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x121353aa59adf9b4, 0x69c7c6b8659e13ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x2403820b078e580e, 0x5f315da56cd1ab65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x3c9385a10140f3bb, 0x4facbdc353b9b2cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x5a28f9e73e118b8b, 0x5a1a19b02b9a5b3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x48cf55bb2c3c1426, 0x12125eb904e46465, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x6f82719f1f842b6b, 0x3db45a5447965645, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x4001951834fcd848, 0x388c6ca91c3704b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x05b45f9a78143e53, 0x0e4c779b7593c948, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x51c238073a633adb, 0x5b31dd3617c7b344, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #61", 0x41f192ea54461c6d, 0x04995eaa75c5ba12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #61", 0x558710292399868e, 0x497f6cde7e85188b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #61", 0x61ab12193c31d27f, 0x2a1f73c52fb00a10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x686de6a57248c8ca, 0x34946e762a7a67d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x11ccf4352a9d2ac3, 0x7210be1957f05844, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x5f9a030b0273d496, 0x74275cfb51ce894d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x7a8812e922942fcb, 0x47625295654e62a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x5cf76aa701af7494, 0x7d1615ea4c4a4af0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x55f591020b8f71e1, 0x421005031ee8fd91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x2f28f86f478d89e1, 0x1d6e161c2b7ca12b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x03bf5c600fc119b1, 0x5b2cab3b10d40a88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x0209e27b2d5f3076, 0x3b4e725c6c2d4305, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x57fc5b393844f845, 0x441d9b4a13d6d6b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x3ab8ccdb2d07b292, 0x65a55ffd37965e44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x4f9be25e19fad6d5, 0x1ce4c0ea3540dfc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x1baa4b69439b2fb7, 0x018b2ab42c934d05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x4f2aa19868ea60b2, 0x4b7c4a96719fdc6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x3077ea93784928d2, 0x1d1c7d967e539a07, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x080a42834a7616ec, 0x0f27a48f343746f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x77d5476264822543, 0x206489f90a1424ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x1cc71d8803905bad, 0x1deafbaf4fd1a29b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x30980e3f244cc1ca, 0x076800df577fea63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x3e47989f0e4bf4dc, 0x0cc0ca270033f09d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x51e7249378438838, 0x2cc73da259f1e408, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x612de8ea68ae3e0a, 0x4b91c0742111c62c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x60f766dc2e8d04c3, 0x1f65603311a5d37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x79031baf6641a46b, 0x45dd1a726901a960, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x4ac3c9af1100ca0e, 0x7315ce5f70d86311, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x149125bb4812068b, 0x40aa05ac678ae737, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x6c5ec8554bcb9bc2, 0x3f0ad19b452933fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #62", 0x5a17909e7224623b, 0x455d24982aa660f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #62", 0x6a67ea73502a0571, 0x049844fd2bfeb532, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #62", 0x38d8437b6c75db91, 0x4d107b5e4b95d35e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x1b02e0542318c14e, 0x5d3ba6dc19cfaa58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x095a65b975e72217, 0x02d153b81405fc03, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x06e7ec25458864c0, 0x04de5f14541e2f68, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x0d9a6b4c7ab3e83b, 0x3ba916a01b7911e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x467f83fd25ff6a74, 0x60a245dc79f933a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x1823ccaf2937d993, 0x249f94962097149c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x7961df0419a6452c, 0x4c95c9ce028bb723, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x061c20bd2b5d315d, 0x4e218a81323a227f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x4e75f2ab4edb208f, 0x4c09ccd7211f0112, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x44c242a63a035c2a, 0x3524fd1557d05864, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x7f8bc0ea67979e6d, 0x2bee87cd4baa2ecc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x624b86a847c58689, 0x672340ad0d262c36, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x6dc4f0fd2bbef46e, 0x071f5fd828cb0aa5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x54f6ce0115f7e90f, 0x49621f4105e8bdad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x2f9e2e3b5695ff51, 0x087474d04e58ad05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x01f330ae4c9c9c5c, 0x0092cf8435ba4ef9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x1b77bceb0bfe4d20, 0x56d9500b50692359, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x4601a94a5428038a, 0x28397bbd6039ff92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x3bbfa1f713076f0b, 0x2be42e5e458d6a35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x5accf59459d2f643, 0x52b3966b1e0b289f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x0591eab110385286, 0x46d633454891e691, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x26303b9656ef190e, 0x4e7aa43e5a88b8b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x2d85185f2974353c, 0x28e165b755ce69d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x7610d198626208d5, 0x0b88b8ca2f78490d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x6e6055f6281ae824, 0x7fe16c6611888e83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x7c42ebae1da6bc73, 0x71c28e153461ff40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x30ae2b7e4ca2ffe1, 0x79ef697538028da6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #29, #63", 0x2675f6241ce3e98a, 0x560db6450b7b2112, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #29, #63", 0x2d1c3c112287abe2, 0x540d07a42c07e0d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #29, #63", 0x7976c4f12f71ff40, 0x06909988534c77a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x58e6347c34a39a43, 0x291ae17826fbdd50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x1705a318565592c4, 0x5674265e4ef70614, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x7e707ae8524222ad, 0x607f94970565f90e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x6fe8df2033b761c4, 0x39c7f84f7ab36697, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x005a61a508c3aa82, 0x32b5f43d20970a9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x25a7940d001f3355, 0x2c122bb126d057ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x22a6df385968d228, 0x52d838a052c3d01e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x08dad1684f2b293d, 0x261047c51c1da429, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x03cec380198da7d7, 0x4319817961c105e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x6fe33a9c1137a090, 0x30b80bf81ad46699, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x6379c33d5a0257f6, 0x203a5fa76e53b584, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x0db9b9bb1bbd1058, 0x69071c1b5362a25d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x2480badb200bd8ae, 0x73f9acfc0e141b60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x202b0c0307bcabca, 0x34e4732a4a284ee8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x61257df342fc66cb, 0x1cec1f0642d1eb3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x12279008220910de, 0x5eef8f646a004f5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x3b96b8b57c796138, 0x4bc1554015f65389, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x0db101c8510519c9, 0x30caba222b79f351, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x2b0771c002d4c4f1, 0x19cda8d6712ac505, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x1e91d54a3887145f, 0x448d676338c12b7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x5892ed0d7bb9ba06, 0x46d546db43129025, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x037665d02a26fe13, 0x0d3adf0d78bdf911, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x6d2364de1a7f73b1, 0x3b8fe44c649be3c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x3c88848f1a5d885f, 0x4e9c331f7f4af4e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x16d6e997460c0291, 0x1541486f781f3d44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x17111c5b3d66d96c, 0x239930962487eb60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x403b9e5d5a4017c8, 0x15b2b06542188e1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #0", 0x12c72c2841af0071, 0x7ad9b9965ecd73a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #0", 0x3d68ba772f1ae2d9, 0x21e003cc6b5a1935, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #0", 0x5941e0ec1fa7f693, 0x6418124640df2048, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x3a276a447417372a, 0x257b040b466545ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x0e74bf895af18320, 0x45b03ab176afeed3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x20fd85b212685cad, 0x6ecf2c17254ba921, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x4fcf36195f8644e6, 0x49d39481380ea20d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x39c65caf7500e9be, 0x7a273028100ad477, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x36afea2f10b84beb, 0x6ed8481e4c8d88d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x3fd32ec41bffb453, 0x37e7a20c7418a4a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x3ba7aae65a72c8fa, 0x34f7c4ef19150fb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x4e8a0025252a902c, 0x5f7a557b75cf152a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x001c134d5b4e3014, 0x6c7f03fd5cfebfae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x6db68cc24c1dfd50, 0x024a68cf211998ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x2ba44237534f6b34, 0x59283b0c3d85c2db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x485054f23c68df71, 0x4d909752656a9ee6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x4d212b5c69dfc9c9, 0x31f827bd7f003f21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x05df7e1c2810a8b7, 0x7318e3c80cf45a20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x028371b20583bf4d, 0x260969d141872902, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x2aae4f7923d54229, 0x37563e2c510d71d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x7f23723e30569a55, 0x2e0c31852aca62c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x7c7497a5250c36d1, 0x4be3fbc56cd9ff00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x785ba20577f0592e, 0x2a5fc1db2818d9dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x3459389f3f7ba07f, 0x0d8378c240abf6f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x295b6a4932c519e1, 0x3fac3619017a63fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x5ad5c299347827ed, 0x0e6ebe1b2f3ae865, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x39fbe73a28184f94, 0x70c211685d59344b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x4bed91be5c72d7a7, 0x2e66a62264aa36b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x0cc971fc5b58953f, 0x0f74997a4b1103fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x0064cc11624ac4d7, 0x37eb02fc093e09a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #1", 0x5a3b1e053eda5c41, 0x3156e37e78c06e16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #1", 0x7e55fcc079189b27, 0x396c650e0e9456a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #1", 0x2bddb5081e7d78bb, 0x100eba9f27b16709, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x52f5a0a847ae60d7, 0x56ec4f6f06b377a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x6fc6b06b1273520e, 0x640cabec0cf187e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x6ee629b60110580f, 0x719bbe953bb44229, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x5c68ed4f3eb04921, 0x06c546257baf9bb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x20fb0df9364488d3, 0x04eda5545ccdb960, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x751ee5140efa8c84, 0x558e27767b362bfe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x081327ab19d93d42, 0x09ca82a37374e1d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x3856b5fd7212984d, 0x1b2648de33f0dcb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x39c0f9241eb10042, 0x3aa454550b4c56a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x3124525009d99d1d, 0x183dde872987a98f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x0ae9f52c6c0131de, 0x653bebb9200a7c06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x2ab17b0020a7bd0d, 0x1bba17b96752e27b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x56ec45e019aec352, 0x44209bdb4bac88f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x28a94fd650ad379a, 0x46e2b4f74c0b2af4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x6a8674dd5aa655a7, 0x3f800cc930bc7782, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x4cb8edf41f51a88b, 0x64ad543622dd2ada, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x3e02a8cd46676007, 0x2e2981800679e718, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x5040fd24153d7c60, 0x300190a76f26fb1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x013eae3f2aeb8edd, 0x0f3177245b2af251, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x4b934beb069e70a8, 0x427dd4cc2bf0293f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x204d33fa3e7f672f, 0x779cb238227f91cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x0f2c9eca2e0ac989, 0x6e8abcc048f683d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x08b11f305e604f88, 0x79b2fb5279b313a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x7db1f8144ab9c001, 0x1c903e81556a0d24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x112120090be584e3, 0x5be3f43c3bb4a0e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x212301443a0d1324, 0x2adb9bff61621d2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x64f8a2017f0ae44b, 0x3c8d0f7e2261af83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #2", 0x05a954f345ee8afa, 0x4e51d8c2308bedec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #2", 0x046df22941963c78, 0x530b7fb825f688ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #2", 0x6fa1060168a00810, 0x6eed0cbd139a90f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x4700579829dde31c, 0x0d4da49a78522531, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x7497a31d29a02691, 0x4dbc325544b24fac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x3585ab742b428c8d, 0x0066f08e05b8c326, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x654f9fb123a7efd2, 0x671ae05456a8acb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x22b2d41d475c34fd, 0x790a5c3b4a4841b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x0d4abff74ddfaf57, 0x7ad42f9f285c2910, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x0f75ebcf3d3fbebb, 0x4e52b1fd11b8b221, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x25dfc6cb32a0e7af, 0x255343147f16f1d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x5c7ecacb45254956, 0x776917016ce01e63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x6ec56fe731f95e9e, 0x31926e1051166de8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x5d3beb2b3dea1163, 0x56cf310f244b1b5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x6192013573fe2450, 0x7af3c814428b8add, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x3b5a594d07a7fc2f, 0x0cd3cc900444d553, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x5587ab877af3b061, 0x2ca0fe6348a51945, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x38336f1c7fb10e7a, 0x5a5dcb6664fd9756, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x3251f6295b7da028, 0x641489275e1335e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x20a2e97f7c85c25a, 0x4af3544a0ed0c0f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x2e7f20f836b65fec, 0x5fe72edd0f685966, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x74a0714f2ea73cd7, 0x33b374c20bbb0c24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x22a561275b1a6391, 0x4e46970156327284, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x62c25fc00718463b, 0x5a7747d75dffba74, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x020bf69c01029f1f, 0x26a4d3b9384a0b47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x00b3ad9a015c2bc5, 0x1d47a29e3a3f65b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x5cd9cbed6345efe9, 0x18529b9f3305a3c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x5fcbb24421bd9395, 0x41d664b87d7cb56c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x5873f38140988395, 0x0ce50ed30e4ad33c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x6f3fc06c684c7661, 0x1a05df604d1464d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #3", 0x4366d9f27dbe1f2c, 0x2346d75411e52193, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #3", 0x04d665671689afc1, 0x6fe4dc08262939b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #3", 0x178c4ee17bbae798, 0x5e7344fa06e25c03, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x7d17135d59745d5a, 0x4121c1bb183ffc7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x3cba4d430d1c04f6, 0x4b45a03e59f0df4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x2ed9988b6452a38a, 0x576d94b71c85ff87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x24eb272044d6b224, 0x2ad0d2c4074d8c0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x2d23288677a8c831, 0x5461f0dc142ae78c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x7566e75d15f4e528, 0x26100920708a0278, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x2c7e94e975268126, 0x16b33c2b7a3d4cc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x70e168be42416a82, 0x011fa8c7440ae3ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x1bb5c7dc27908084, 0x5c4ae0456df87c1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x34ac857a1f56f01e, 0x47e95b675870151f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x03a993a91fc6e76b, 0x74f614a763861e06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x649d998f3f359aef, 0x6ad3aa122894bac9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x36de632062cfab75, 0x3cbfa25511c0c215, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x78c4909d18fe00b9, 0x024ac48e2c454a7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x0e2481df27a24008, 0x2682974125432587, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x69e3aa8a4598e997, 0x694e09517f05ea9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x6d296a1b34e7c221, 0x6cfe66ba05997266, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x543eb23f52ff9c2c, 0x5e09878521d5ef95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x72c68397702fb7ae, 0x055c0d9b57e845e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x2f65529d3d3ca307, 0x007d00b157641d27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x200c4e7c6b6fa3ca, 0x6924df3c6643b5bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x046da484390b977b, 0x1289003a18d0df1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x60add78327620df2, 0x3e1404a112922663, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x6cfaf7897e9677bb, 0x119811014a91820d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x337e39dc2e347bf8, 0x502af4735a2461a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x0134182501565ed5, 0x7bfa513a07bcec1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x71861683602232b6, 0x5fa5320473fa9bbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #16", 0x1d5ed5bd34839820, 0x4b5eb8e320eb6920, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #16", 0x1ff33bea19b81f17, 0x072f1edd3d6b2439, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #16", 0x52c3b692145007f4, 0x563c03532460e06e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x3bb215e7488b17d3, 0x36f306d233718e15, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x47218f8f4e2e0495, 0x7e03102228ad0d70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x7c62808e7ecbc04f, 0x02d16f157a9fc96b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x00221f246201e78c, 0x025cb5877d9698b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x42241a423cefed53, 0x7191346f71a835a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x7173857319c2bda6, 0x12939ec85f82efff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x337adcbd732a178c, 0x1cee14381166c15d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x077a1f806cbaa89e, 0x35c7a1cc063e9350, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x3545c07137b33188, 0x39b02165432c3567, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x05e1361d6eaab1ed, 0x6bd942d87c675000, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x6d76723c7963cef3, 0x7707196c0243b6ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x5b65b67f716b83ce, 0x7fda4f5e6d989160, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x2e5b712171d465d1, 0x5f40c7081d89d0c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x0b97237719fad4f9, 0x7d0cc0c01fcef694, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x0d24ec8566fd59bd, 0x3135b7f13f120034, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x53b8025b7f00b4ea, 0x45509384149f0c05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x36b3e67243a48445, 0x57cb416d08fdc2cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x324f36327c6c2c39, 0x056512cd3c951c8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x75cffb2d3eb32299, 0x3ed8d33b1fc5a86e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x301ea6676c9f00d7, 0x0d5e39ce5135b1ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x5e7366a86bcc432e, 0x6ebf826e5e7a1788, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x05c718272f7ec60e, 0x7e490e1c6a0a8a1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x167c1fcb6e6d1dd8, 0x291c8a5312ec04ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x6d6dd2c27f56521f, 0x278b10b26a342227, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x42fad6647896f7c1, 0x7331e4f42421b934, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x750323fb1f8fa8fe, 0x60b6d5c3754a0c96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x5e42cb98226deed2, 0x150fb5046ad31f28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #29", 0x0f0cefa92ac85342, 0x3c08d0d40e6171ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #29", 0x169496716b2497a4, 0x6cdb89886d805651, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #29", 0x1aa35db200a76ac4, 0x578ae0701c5bae98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x6f14889c56d2c3f7, 0x2f47b345311f7d7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x562916160e858499, 0x1b539fa55c825b5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x071c7c5a615aea55, 0x00a414921923ec7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x00ea9354237dae14, 0x0e6df9107c1fa055, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x45eb9ce622fb9052, 0x66f2bf7d5f2d5eec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x4dc3e3945a6a5a73, 0x6d8ed0eb54f88c90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x458ef2181a03c352, 0x4278e2e164587a05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x1aab2e162ffbdbe3, 0x00b4289e60324fca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x06ce9fda2ca56ced, 0x1151cd4809bfb6b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x3b2af18666e626a2, 0x664212105cf7b5f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x484110f704899b7a, 0x761ba26a42476de1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x2807498e2559cdb4, 0x3e670e36492ba44b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x48555e0615e7d423, 0x285903376df2e674, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x70522e96056455e6, 0x42eb73041619419a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x1f6819387b25e43e, 0x7a71bba035e120ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x2b21c02127653dc1, 0x161370793a13474e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x540aaaaf2a151010, 0x43d2fe0031f05ffb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x10fb36b20503b855, 0x0ee815eb0f359c35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x098d53cf0fe4184d, 0x517d0a16593c47a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x353de6014ac0ef2c, 0x2267ebf531949d5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x60a8c34f6272f6d6, 0x1f8783d17d934407, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x67d74cbc0e1e4141, 0x13ac85a150faf1e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x0944257f1cef830d, 0x06dc1294073f65f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x4454c0cf0525ab42, 0x4152ad423465e5a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x2f3abb52753e5b86, 0x6656459b185f6b7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x7a4213db791211ca, 0x279507b34035f204, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x08f62a173bda25a2, 0x197239ad03cf67aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #42", 0x069b14cf54eb88d9, 0x356405073e341018, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #42", 0x375e7faf4f73d9c0, 0x3bc7541f6743d81e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #42", 0x5d921b023f1adc99, 0x383eca041f35cc6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x5c0a5fa667c7dfa1, 0x2675325f66d64081, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x6ced8ae301926bbd, 0x1b3c2622205f2075, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x76d0c744605393a7, 0x38be8bf31c284635, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x5965a57175d071e6, 0x5c5e38397112db1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x31aa97892a4647d1, 0x74e242ca625bcf88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x7f31d0aa5c5733bf, 0x208fdfa03845ac58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x2bcb0d7f57c84e7b, 0x1f89847636905059, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x16e32b147c3b4f23, 0x55c61cc4095d2881, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x64032ec40b6f8f25, 0x7033690372ed8aba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x0d01fae24c0b3723, 0x134cab3050f0b9a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x2c5ecaca49773815, 0x6d18ffdc03d2c226, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x3f47a9fc69c7e010, 0x74e59d4605c4703b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x140e27e108b01f63, 0x68203fc370f24185, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x6507532248c17253, 0x2937eddd133ff88c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x2089c0ce1f9665aa, 0x49d048e510d260a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x1bd1b4cd0a62f226, 0x1a2f8923376cebe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x15d2814b3da721cd, 0x2a5a769d7fd4e392, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x09b258f03dde9d16, 0x50c59d3922d47c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x0755d52b1b8cdb9a, 0x26a73e54361123bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x0554bbaa23f5d3ba, 0x3bd593f6469d7f27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x2ca5f31d60c7ae89, 0x378fc0ac1962e38c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x298920dd767324fd, 0x2ca2dc1811ad4640, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x16098aa73caf3005, 0x227fa6e24a12e1ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x4712222c2bda442b, 0x017fcd8e31db3f75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x698165f80275c040, 0x31b023075ce4a377, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x40545d5626605dfa, 0x7fb91fa57333bee8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x41ed3994651a769a, 0x2944e2a347aa3282, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #55", 0x09104a5445d77256, 0x0e47b1a94741f53f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #55", 0x269f20df0d47b4e3, 0x60a4d8cb35b63d71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #55", 0x03bad9e069e32a93, 0x476383b1502841bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x26925a991bbaf0f6, 0x1a3b236819c46488, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x479535217d4fc704, 0x4b9fa3fd6da47cc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x7fc587444a423fe2, 0x4a89203c31169b19, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x70a29ddc4d8f3ca5, 0x244a5a014019e49b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x32a9b33f160bc8c6, 0x07c4171d328fd770, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x5be33b1c5a76a57a, 0x79d1ccaf3bb9fd93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x67be5a5d38d3beb6, 0x71703b0402825bfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x22b6e9496ce5c120, 0x52aa9db86b79343e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x08a0b21650dd3cc3, 0x053d98c6494943e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x4e2d03c70176e0e4, 0x36edc0a75035e737, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x4bb920c62596dc52, 0x014c82504df28b0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x732618f715d086c3, 0x0e0c6fa63c5bbea2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x2bdc4f8a68bd62c2, 0x6eeb961225cfcc36, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x4334083c52fa04cd, 0x6189c9c907bf8aa6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x0bcdc3835cec845b, 0x0a41e6a22af2629a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x49d2457b1ba92f9e, 0x166b96d82e84accd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x6c866c612ebbb157, 0x77cdf0af5272f792, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x3032923b23f5611a, 0x22a8dec93ab37028, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x498c3d6c16b26ada, 0x08a5fb337bebb301, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x2c82f19d273307b5, 0x384771a33cb25663, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x0ff06a77440bec62, 0x62822299585f4127, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x1705f12f6a60b270, 0x601ecbce532472b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x474d36cb14826c26, 0x7e16d54e22d3b4b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x302b9bc44926522f, 0x51586180111f7c47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x77e20386063b52a2, 0x639273d91cb20825, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x2a30b3bc600b7380, 0x5765784d281495c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x76bdde5a5c47ba65, 0x240048c273bcf128, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #60", 0x037ac21b12f16a24, 0x306f478b2340cff8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #60", 0x56fd56865bbedced, 0x7ba0111f136b2c92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #60", 0x461f8f5e64a67494, 0x668f9f466e0347b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x7928e0ba622f5de9, 0x10d6fc690d6cc629, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x2b55b018021eb649, 0x1e8c427029547c7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x085a08ec1d6bfcf0, 0x460684a32337b39f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x7d7770716f4c9223, 0x4b4c4960328abca8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x4b944c8856b6f55c, 0x2647add174354ecb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x69a85f8113162fe3, 0x17761ec34f0f0ea3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x6ed50cd04909da7c, 0x627a3b3640a5b607, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x2db04f113f7ffa26, 0x2ea8fdbd34f49c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x21af580f60eda4c8, 0x4261625826d92fcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x630c5b12163430ed, 0x502dac4a4d050828, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x33a02dde3b890527, 0x703cbbc76b6663fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x2ad5974a4438ce77, 0x1df120a631179e4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x1aefc3d43cc30bde, 0x254ced1a7669e3d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x4fd93bc127f32dac, 0x4578f27604982355, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x70fd082973e6d71a, 0x453dd95c3eae4891, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x3366d14036044718, 0x73a2e4c01ead573a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x16f1ebe015b4334f, 0x4586870555162950, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x2be8643d1257ed3f, 0x221b317879fe46f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x4de0f2660355cb97, 0x6564aaf05f88921b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x478e9a0e35ed1d84, 0x10a0306a78b689b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x72b0296234995ffa, 0x6f206d84627e5de2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x5c8c8da72c545a94, 0x6716813742896523, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x203b31ae74da9275, 0x0137adb54d8995d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x2aded98d31bd740f, 0x6c36ed0a53a202ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x4771a75f4ad35db6, 0x28b82c3e41d0c56d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x5d2b4af52133b750, 0x3bcf0c60735a0b9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x248982e76382ce21, 0x52e29db72b0c3d5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #61", 0x196feba512e33491, 0x23c2c70d6c181cf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #61", 0x477c948b35acfc10, 0x4e967ad80c201508, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #61", 0x620156a44fe127e0, 0x4ea97a2b24092232, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x44bbba555dc9a50c, 0x7192b802023c8852, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x0f87191c7e96b77f, 0x55de8b406f9a93e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x496a15356d3a65b0, 0x316b595056f8c07b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x0e6e1d001d3569ce, 0x4a52cc172695602b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x00b837ef75646494, 0x51a19d8732f79fe8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x084799256da637b6, 0x1f0fbcde1a282394, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x235333c674f1b2c8, 0x2648389c4fc42db0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x44d2daa8656007e5, 0x73cd4fe305548a6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x4329acf25d6f9dfd, 0x079112bc098e94fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x5c06557c2a948230, 0x792928e052b0c60e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x17cee7e073fc52a0, 0x29a9868925706ab1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x1131bc6e1da76863, 0x4c05cadc263d04e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x130bccf7784461a7, 0x5934a4c911e9f45d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x65ea995d525a508e, 0x2c1217f11b53661c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x474c03565ee4e3b0, 0x6b1793cd093dcd24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x4444eb9516236a4b, 0x0e92578e0c1eddfe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x739308480ed69bdd, 0x15ad72fc076e9887, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x396b1e0d03c8e51e, 0x5a1f5e954f995dc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x77c537be410f9352, 0x7509c875513a05ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x5eb6fbb550abaf98, 0x77770acf08f6f42c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x48f0113f46f3007b, 0x1ae0e88971c2c8ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x194d5109782dc296, 0x0d162ec92edaaa9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x5712a64646aacf4f, 0x381877c06099545f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x5cce399a0265a55a, 0x6cb8325d1b5791dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x113c41377ce588f9, 0x22c62a63506141e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x00ae6e171504681b, 0x1ffa9fa64aa75f44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x5613fb6d13587001, 0x1be165327873a5d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #62", 0x64041f991c4b828c, 0x016a9a0234caf723, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #62", 0x633e830733a3ee99, 0x268dbfd02cf430d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #62", 0x2bd1b13013e75335, 0x5bcedb757c8bd410, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x5a92228449dd5acc, 0x5d25286f02e45776, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x4c430026410213b6, 0x1e3be95237605c1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x3de79caf27bc3da6, 0x07c19e005d7f415d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x3cc0a5c2440805d4, 0x2826a0a23e960ac6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x576075d638744a9f, 0x3709b09c12d4a12f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x54bfcd2b6e2d5822, 0x479f98523b64956f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x21d146bc4427a1bd, 0x6858c64837fe5032, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x580ef4f211af4cb1, 0x348a24424da2f7ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x5b8ca77d6ec338b5, 0x50874f6232a11777, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x2fc54c6b71c31196, 0x6a01739527cfa7a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x197f4f3c2d7589a3, 0x054ee9016dace91a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x717d8f78634ca47d, 0x2c42f3e0563ff4fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x1bc0ef1c30b42e80, 0x6914962e48de054e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x1ee186a36c9b6105, 0x04429abd7080bc47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x30c302c25d0930bb, 0x287f0c7940b2cd5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x6eb87d6c5edd14ad, 0x0e55c54b08d1f7b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x4da04d62257482c1, 0x3b730f2c4a4524e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x173794577763b58f, 0x7214cc8d7d6599cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x24d93f32175576c8, 0x6b1282e730b6e394, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x7aa21b45700b6ec0, 0x06f6d8921656ceaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x20bf9d4163776eb6, 0x5f34d3f816630a61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x5012cfbb2f62d321, 0x06e3c6a83fa123e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x0c6c03dc0ea9b68e, 0x0053f14300d5d27e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x6d86cb3b451ad95f, 0x09a7ca337b248148, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x6a8f5c20377e72bf, 0x4569a6313b27189e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x2ee2284e239f3553, 0x388cb26b01c6f078, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x3af4ac1b3974ac9e, 0x327dd40c53bb6780, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #42, #63", 0x29801b5f49470a23, 0x6a12362b3596c760, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #42, #63", 0x2cbe78d952dd9869, 0x4bf9d1c14a3fb8a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #42, #63", 0x02406b8a0a34cdc7, 0x09e0dc847cd14895, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x18de8455074ee546, 0x7da71b130eac6f66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x4c69bea54f3a96df, 0x09d0f0ae06654f90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x06b9099e7a191a9a, 0x418c682e36f91ac5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x1db84fed6b3ddf49, 0x38c00b3d359b31ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x24b28be87368cf98, 0x0956996d58acfc08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x3cafd9bb5a3d9529, 0x0e43c3684e32a747, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x2d1b2d9222533c6b, 0x18725fe7696e5295, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x2c880a3263e6b63d, 0x663f9b2a2f5b991c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x6b359b8347d8f930, 0x3e08088245668e87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x1713900f0d584646, 0x4bcbde17379f5a28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x077160e02758802b, 0x6e9874ed1dcc99ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x12965f745cbe6507, 0x5367cb9a2529b0cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x5027349f0c1a703d, 0x7dd6acd53748eb5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x665805661dedf28a, 0x057b92a30cd70e5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x40412ef55c84fc1a, 0x764560f0137332f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x406bb25700d6d496, 0x42cecc146cc93927, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x48afcdc67dfba5c6, 0x322fc7ae2ba14dda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x0b53ec0c51d91cef, 0x6340a8025fc35dd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x79319d1a50f7c31e, 0x7d8ff78312c54cec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x2db6282535c5aa8e, 0x37eefdb90bc7fc8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x41e01acb488c7a8f, 0x4310e7eb7ddd5cc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x667a6d1900f9cc10, 0x0ab46b2028382031, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x5d7ec82a7e7a1f3d, 0x3bab532926bb9c0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x7f50f3d345b49ce5, 0x1384d5361dea7a81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x43b042ab2ccc705d, 0x498bc85b4800c199, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x7ea58d4c255416f2, 0x27c41f6e4f042eb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x764bda1019b8795c, 0x61c97ba377d72a67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #0", 0x4f7e23ea46b00ee1, 0x039f26f624020235, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #0", 0x0f3c89702c93ca1a, 0x21df5efa115e3eb5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #0", 0x2d8d962a7541b20f, 0x39965ee675b6f68a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x73bbd14c2ff767cf, 0x1c7292990b0c5e54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x75ac04b47282a130, 0x28f6d8d5730cc51f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x1f4f118d62d1a626, 0x3b0d86b8395c475f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x0825bd186a29f1b9, 0x086076161df49eda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x03e26b15196af037, 0x15cbc9417e719728, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x601aff184452f858, 0x2273995e53608eff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x70e6c2731e552c9a, 0x64becdb46f578889, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x1396dea9018111ac, 0x650e7f131e74589d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x3178797b52778fc7, 0x2980b6f20752aff5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x44fa30f8356cfbcc, 0x7a5f751427247e30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x183ea1f368e13ba6, 0x6080c58f64494285, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x530b2d5f1809aaa0, 0x023de15f20645f0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x31749ad741498f92, 0x1ed5f63456ed9875, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x059c87ea0f0cf529, 0x2a4e2774118f99f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x2d6221c365f5a18c, 0x00e7227976834a5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x6776b3383e7859ed, 0x14f7a2fb40f9006d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x10efe9b442ab2577, 0x484bb06218ef2cb3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x7818214320947073, 0x4013aae355ea1aac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x0975ac193c713e91, 0x3a335d321056c336, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x547ae9324f911876, 0x30bb22425c80d978, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x10daa8085dbc9962, 0x336e71ed05ef8409, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x6cc98e8b18664072, 0x177f1df916772ff2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x7e5be1fe21f21d4b, 0x0cfa7a501a2bb04e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x606a77382370611e, 0x5b24b0bb65d29536, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x661b86953ed56ccd, 0x7ec1c1ea715a60ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x5f69dd400177d8cb, 0x47447b995e33a7d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x3de9175c1f458d51, 0x6e8a6b0f68df8959, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #1", 0x6ed6a5c778ced4bf, 0x456062d21264008e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #1", 0x568b6e212fd2a291, 0x185384987fb14dcf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #1", 0x4838e3042322f811, 0x16287dc14354fcac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x4515155c38a55db6, 0x5d80acfb4694c502, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x5c15bed42b291c23, 0x2c675a39257f8c94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x69fe88f05e1e691a, 0x16d9ed8142314569, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x5f9641e50eef5851, 0x2064ed4249686631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x2e34e5a277a8525c, 0x3247ef8a1d7f5941, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x7077271c4836de68, 0x2fe359d01d0b8b69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x780980f932e556f9, 0x1cbcd9384702953d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x56084f0b67d83ee5, 0x0a5791ea404263fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x207d9c9b333e8339, 0x06d729001b1d6467, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x5e679f5c5776de7d, 0x409cf0fc7c935b70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x359547975f298e1b, 0x3ec4a0d94866284c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x6e18e66c44167e08, 0x11ce8e7d152b897c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x3bbed064628e3c8d, 0x32aae2bd1c4dcc0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x2ac51af5561630af, 0x395957772c35f780, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x08fb87a97d901ea8, 0x73388cbe22ce9bef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x65685d8d69e828ec, 0x6310ffec5f03d6b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x1d26ac253abe2c17, 0x7a213b1b05e5fa28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x12350a94413df672, 0x027955987b8e4b81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x2067848d55c3024b, 0x43f473ce47ca522b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x19d980530fa0be65, 0x5cf5dba70e806afa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x722efaf264278e80, 0x2ace3708559850b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x3a3dbf2f7506d4f6, 0x01ce48381cf415e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x7296f39e22d3b1c3, 0x3fc2b1d7433946d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x0cbbdab01c5e58a8, 0x223d1d8c57ff512b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x571c84bf605ea0ec, 0x5de54b5429e286d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x219c975e69654625, 0x2570d25769518f54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x3f2848700e11bd27, 0x311be17f42041bec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #2", 0x1db27b8c7b52bdee, 0x508486e65901c8c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #2", 0x5f7a4c6e306861b4, 0x2e9a197c0fe1767e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #2", 0x256f36ab6c983e3d, 0x2cd58c6619b80b9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x0f6bf0017f2e7003, 0x5cf1527618062a49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x1b8cc8ab4deac6c9, 0x70057b751c27cab1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x2e4967b56b7b23dd, 0x460a518672a94d6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x54e06a020d16be3e, 0x5bfadcbe4fe5ff14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x1b287b65626ea1e6, 0x11ea1b001408b273, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x5dc15fd41ba494b3, 0x6d0a7b3738daf6f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x4c0cf6677591f9d6, 0x48bc6d6f3d3bac43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x622a381333e50a57, 0x56f3b7e1717c2d12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x33137a5a7987d2d1, 0x0982575c71962814, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x4772999a53c8444c, 0x0dbdf2c54ea04305, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x3f4368291d446d2e, 0x4149907075bc014f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x2a5b2b6c578c1b63, 0x45a200631423d22c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x39fabd491536ffd6, 0x282c849f4583a6d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x30db9489471b0b32, 0x7e5e9dc217bc1d1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x3cad05082beb8142, 0x54f7c9617ce88af0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x5fd08b9977e70f5f, 0x6e64b8031ed73d1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x716ee2301e2b57f5, 0x106d653012e405f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x71f39c4122cdd969, 0x618448f938e17bca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x40124698743f7d7d, 0x2e9d7d193137046b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x4bcb98e06d875b36, 0x455ad6976a6d7204, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x02be5b0c2e4fb698, 0x2ff118d605c6562a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x756ac1ca727a3ca9, 0x1d8273483399ef95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x1e65bdeb1ee73288, 0x30827a853217c6d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x16ce41e7615c691e, 0x50ef03ee7e364984, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x7f87c113729e9872, 0x111a4f78083d2417, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x156c71db6fbc1cfb, 0x411e9fe1717b5d55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x63fb9a78680d3857, 0x22b261c0557eb873, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #3", 0x5594938d6fdd434e, 0x3fec2a782fc73358, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #3", 0x1e2cf9e6530ffcca, 0x358d89825852ee99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #3", 0x458a39733c6f58b3, 0x0becde2e1397bbb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x5b568b3c169e8671, 0x45af828363eff75e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x77faef8f7340905b, 0x622640e37224cd23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x65df28cd3b80911c, 0x7a61f13b7782b0a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x2b3cae170bb06fb8, 0x68fe0df87b4b9aa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x73bda80f10b67d94, 0x50ca531c0f38488f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x0093c0e2748d056a, 0x3eff7be849523b9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x479d02352d920863, 0x21a52a351ec0bac9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x6a0161167807f8fd, 0x3258767a0d273ba8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x0ea67f6f533d73ea, 0x711733074557ec52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x467e044531deaab1, 0x377cb97606a16efe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x6d5f3bcd67222d99, 0x7e241fa12c5d2d13, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x72d29d5178731ad8, 0x27a8c7bc189be9e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x0929986d66d3ae5c, 0x27d4327466904560, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x5b60b3c75187ab31, 0x2fe280fc09bd594f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x7f19b3945ad68a92, 0x287e141822fdb5fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x52de8390213c24ab, 0x3024f1a4691b14ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x7479989565efba73, 0x2e7300fd618502ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x17ce6524664a919f, 0x682671fd3af79cdb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x4d6cbf380efd91aa, 0x6754c9ee052da0f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x0770ac82459dbd4b, 0x1dc98ad7403f5c8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x2c716ba856b222e7, 0x26cfa1ea109a44ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x2839ce1842d5b257, 0x1a579e3f07d21f6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x1dac3cea5af4c70f, 0x2acfd56b275381ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x7c30ebbb3ee19755, 0x106e9658708ac07a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x24d151c93a363576, 0x520fc37970aa8450, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x2080c71512f6eb19, 0x2ba2212b3c9fb6ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x21f47cc35f96e2b6, 0x41cd57df6ded864e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #16", 0x2534a00254fc84c2, 0x2e2ce2d829652946, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #16", 0x2baea7a954570c74, 0x39ff6e3551a60baa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #16", 0x172cbecc04480084, 0x59782b1953e875c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x5f3cc7930baa8dc7, 0x7b3bf76f34d8fbb6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x4a8c251c77737fa9, 0x2563bc305b6db34e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x31a9b51f77ba58ca, 0x4c18379f6f5d76e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x0ab143e46dca85b2, 0x2bfd2dd3522a7c35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x4d6168696e44e55b, 0x401802832ca5c0a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x43416a1d100a5823, 0x560ae9ed7296086b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x646164971db43f2e, 0x443c14156ef011c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x21fc3fb23e147ef8, 0x42d887897b8e2363, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x49bf0cbf55cadb49, 0x30671f1901390745, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x4d3e5af228bef233, 0x5ca6ba94144b31db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x20794afd2fa5d694, 0x03a8a8c17ee81012, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x1d705c46112a8eca, 0x51128c472b2a8ee1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x7f6f74252ddb3976, 0x57d04f896ad1c4af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x3de5919921a3e12f, 0x5d67cd1a42b0de42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x3f58205d74797792, 0x31a0f0092246f631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x328df68a4e3c38ae, 0x1dd519946154600f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x240713f73f3421e9, 0x628d67557c4d0349, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x67f3141c1440dde6, 0x1098352571456eea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x43e6b47a41400b43, 0x702d7efc086c5f19, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x526a9a0d0b673d84, 0x3396edfb615710c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x394276fa2990a28a, 0x4c28d57051da0e32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x4b3483ba462bdc7e, 0x148aec7477280894, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x3aa5541037441859, 0x196efec50a8ca417, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x058051074e6e6b7c, 0x6be104276d334a9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x0da28d657a188309, 0x69804de4298764ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x0e5960ef0afa52e5, 0x1accd3e97595a181, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x4c3a5e283198ee95, 0x7e02009a52401569, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #29", 0x3d002c197fbffb9a, 0x3397262a1ea4f835, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #29", 0x29509e240509f2db, 0x707f06677642a314, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #29", 0x4b35cf5906d9aa6d, 0x6d6aaba8748521de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x3e1dc2c66af2ca1d, 0x7f11c5f605db236a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x396135995c8ebbe9, 0x730e6e05439e13ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x56a73ef307f24cb6, 0x6d2578cd4703c2fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x12ec9f9b3a9b6519, 0x3c99647f65009fe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x6c3453af6ad7db76, 0x3740b54c5f26fdc3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x6a97d7106e4afc5f, 0x7dcbf5f829347fc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x7354ef3a0ce1ce84, 0x1f7722dc13e87534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x13bb78f1077f5d09, 0x086d97133e8abe94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x7272272637745003, 0x4465e1fe51d93bb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x14030bec029cc853, 0x15774f862bd35cbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x0a8f15092f70843c, 0x72d71fbd6aaa4adf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x6a0be95506eba00e, 0x4faaeac21d7bb4a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x71c37b847a6ea85f, 0x7ca2b26756403d04, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x68b9a4be1eebdfa9, 0x7f74bccd5c5b5294, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x2bcdae2e78b15edb, 0x7043c7c85c0e93f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x0030bbe45eff348a, 0x1a99528c3f89271f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x1673848d26d9b25d, 0x116262d772a2e30a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x29767ab0114d5f86, 0x1e763fc92a76907a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x40bde3c264cbc61b, 0x1520db5934058fb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x6bb766294e23f6c4, 0x5181445d2ac9cd18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x48929f23007ec6e9, 0x010a0a1c5d7ae1ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x1f6aa6932a19fc0a, 0x39d63441314c43e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x22cb5ae527f42a66, 0x0d5ad7da4b3854c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x06f35ef11c23deb8, 0x0ac17be022fc16ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x42fd91153415399e, 0x159ef9d41d66e37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x456299245cfe4f52, 0x47dd73f86c740bc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x41ca156d71fadfdd, 0x20799b7f06207ce7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #42", 0x401ed6a131f4541b, 0x30ea49ff2d817b97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #42", 0x32731b0544d29186, 0x0afc5d4408b175c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #42", 0x6eec8d9047589180, 0x39fdb9a651ddc198, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x6f4cbbe727d79239, 0x1d16165911b7e875, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x43fb70f14a52f914, 0x34b3ff3f76401ad8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x7e6832b25b84724f, 0x13a6fe5606f90207, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x3882c1a113e6a94c, 0x736d0dcd43cacbd6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x05e189297ad592bc, 0x49eb48bd7a4cd70e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x2cc9e6d832caafea, 0x27ce52a546005fcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x779d417008af8f36, 0x4eb1d5905f3d01dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x500820b74e30d9ce, 0x311ac3756689cf00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x76086c072cf5b6b5, 0x7841b7753f54dc9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x7748afc9493bf5cc, 0x3594f7763a03dcf9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x24c0681b3469eccd, 0x40fcdf0075b0e27b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x485096190366f70f, 0x397bae515d4329bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x7e3c89cb7f5e5370, 0x579000cb4e321f43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x3229035a62e4549e, 0x14327f0e2b0670a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x6b93e3d43b5e35f5, 0x0a43728029c644ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x098f0fc30891cb40, 0x105013ca3b9c048b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x358781f53085d89f, 0x7af0e1297f977bcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x79c1ce6c7a9837c4, 0x399b58c42cd031be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x2f0224915bfcc28a, 0x228114391e823687, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x5f63b9995355610f, 0x7bc560447752baaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x52b3b47f59b758fb, 0x4584d9ed5da04365, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x3c9bad9912ea2689, 0x08a6b40804dcb7da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x4e485c7e3ef3106f, 0x2ea2fca4282f916e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x4784dbaf5ebc7723, 0x63cb95f957d76c42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x0f424fc2110a40d1, 0x576ee80d7d0c5da4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x0ba278954c5da39b, 0x29dc8f6209041e2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x285a6625234bb4fa, 0x278654b63aa49d26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #55", 0x76a11609777c31be, 0x31f757d007be1fbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #55", 0x51338ab96e05172c, 0x655e63244954ca88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #55", 0x00ef3db57cd47f07, 0x4e3182620dcf3853, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x3bc78f7619ca5fba, 0x35fec9c14f379a34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x7886d6dd7e7dee83, 0x270f0676034c6b25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x0f882f542a35582b, 0x0058c8c907c926a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x7692fbc638539984, 0x10cd44ce1b2aa7e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x5b9f4e7e07c69cdf, 0x55cf450f1eed61eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x7f42ce9d0c09e4ce, 0x26ab81aa52406487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x7a0efbfb69c6b172, 0x1b952f1050765957, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x669b307914445b6b, 0x5e4591aa7afe39b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x2e0ebb257144da5a, 0x4a35d3e42262bfef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x6fc2c8dd2607f3dd, 0x25af2b1426959203, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x503d4c083f2bfd71, 0x2e5eb8a37f4af831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x777f96f67044e529, 0x1a75a01a46d047ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x780b82090c692b64, 0x65bda9ba531ee574, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x1873103340f4790c, 0x255f49fc774e50a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x2abb2a7e260a3ba7, 0x47c4a9fd12820c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x3a4e971257b619c3, 0x0d8045de11565af8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x48faf41d596845fc, 0x33b91ae7685d5238, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x7f7039d93d519cde, 0x0ef2e43b38bdbcfb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x7c7d9a4f527e5547, 0x3808b52c4fad85e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x42c33a707c3b776a, 0x167dcdb073fd3145, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x08a4a2cf6c7b60b6, 0x471c16ba3acebc79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x2d6fd9c279e1b71d, 0x321d0d202117b302, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x1febf2c5411a050e, 0x3399bf30582b0440, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x18d01ed11d3a7a20, 0x69815f385a3a89d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x76a2c01c518ac04a, 0x4297dc0f61cb12ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x0edc5d2852918516, 0x1a88cfea7612f9f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x250fda5d5c3e4d88, 0x45c07fd70b59f778, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #60", 0x5879c4f246733f77, 0x7f5728bd67d314ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #60", 0x32eea02d54bede67, 0x22a1d147611e67c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #60", 0x4ea0958535cfd9f3, 0x02361ac3605e79ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x76e9df02220add68, 0x38897e306e8c884a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x3f4557880b5eee31, 0x48c712210fb9fdd3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x5ce9ae7b0c0de0ac, 0x718510c235e817a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x5e9f65c371bb9171, 0x2bfb119a6bc60ba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x4df9def976772bd9, 0x7720031c03af4020, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x3cea6b510e242636, 0x6b8254ee2673a3ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x62e3049d09c82671, 0x07920bad6fd90b7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x3f98006408c1039e, 0x5037856e31839a22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x2acbe10668d7348e, 0x2010226c3681df66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x743622bf37c0edfc, 0x463bdd3a6a11388f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x43cecea94bf461cd, 0x1ff95033511fd13a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x3daff33f3405dffa, 0x3ce5dcde226e346c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x2a7d0bd4119fc97b, 0x261d748c0ba9d238, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x1fc3efb139af81d2, 0x321d762467677725, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x4377a84327780811, 0x574082a302a6f44e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x30390baf543ab0dd, 0x342a8e71030fa8a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x3d11e56b7fcd6548, 0x3991880e5b04ecb6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x378e5344650f7578, 0x451625453148082a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x3103d7463f4db643, 0x0267d9657b5d21ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x7353963e43e8cae6, 0x1dcb56596eb3ca85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x558894612c7b12e2, 0x7a5d9cbd1dd0a212, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x662a94b45c789bda, 0x05381937754c8412, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x03f0a3ec2c1e06d1, 0x77f3786029a23cf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x0058b7af66436dac, 0x2cb1e59e3429af9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x6610d2f45444c196, 0x0f2e9c513d6a9d1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x3954370f711a7eaa, 0x6eb2a5451d9f2639, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x306834ed36c79e80, 0x18fc48266a580e55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #61", 0x7ab0696653697597, 0x590bd8da23bbcb2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #61", 0x7fe4887946c48674, 0x418c6d3d5038fdc7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #61", 0x233d224f3d78fa39, 0x458581d9660f1d2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x6997010b3c633fc3, 0x0fb15a24272dc63b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x22a6ad6f6a861228, 0x5b5775d669efb8ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x3ecad3be160cfb19, 0x275a55d408b78064, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x072779c33f52eec3, 0x2656a69d781f0acd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x761a8d433b82f1fc, 0x62771922378faeb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x0eec67941cd7e71a, 0x5b4b79dc70caf6a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x639c6d8e06897649, 0x4103f4700ed0f00d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x440270830491675f, 0x74e00d3b06d98fdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x40f4a722095ecbef, 0x2e0756182d99718e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x73e4de173ee3801c, 0x17892a48639b5492, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x54f07b3612a97b93, 0x6c52d4f632afb1d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x51fc6a560d45d5c5, 0x2acebca35c17f4f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x48c8c7c26ef31d87, 0x13a7a3aa4816f79a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x0bcb04a179e5e2b4, 0x38e1ee4357b52f56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x006f58fd5b662c9e, 0x66861f636f67722f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x5ff793fe24485825, 0x7641020d4471c980, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x2da7241409946556, 0x720b3b0e20ec3b20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x4877e57370da64a8, 0x04878fb2218c022b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x0383e03b7f0a70a4, 0x543bb4011d6860a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x0c5046690d27f94d, 0x798055a255804a92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x7c1b16d45679306f, 0x1d97422c55190e2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x505f132313545ce5, 0x2cce3d8107e61b75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x6eba89836d8e8fb1, 0x774d8da450ce6c21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x11d6e7d7074b70b0, 0x154035a14eb21d81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x10dfd6067425e854, 0x6f9e58a23f7e0beb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x65004cfd3545c218, 0x610a0e175957bb79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x345032bc704071c5, 0x76c01c2268842d38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #62", 0x7d686b125b9bb9f6, 0x3e0477ca40a07925, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #62", 0x3214ea664287c4d2, 0x15b98751798381e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #62", 0x55dc21b778b72aff, 0x01699d5b0273fd89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x6645bab168829f4c, 0x534269aa4496ab3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x6fce0ffc02e7215e, 0x1348c8bc781ca288, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x770d09b318a4bc8a, 0x379aae7300ade602, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x4dea7ea250c5bd9e, 0x5a05a17c5c0d56b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x41062f630295fbb3, 0x449183e8023ab15e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x5e31b5a95894b1d5, 0x42db2a843e6e9a75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x1b1c76a7395bb9b6, 0x37f21c5b1046a00f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x3212e4b665fd0743, 0x12ba9d9970f8985f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x4e7fa68f48d80c56, 0x358f439a18589f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x4bbf2db5480ff062, 0x107541ef3e4db68b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x60b4aced19013e0a, 0x3efb9c8e42cc3768, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x69c6fba8636b1200, 0x1ed98e182e9f2b8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x66010db373b50772, 0x30d9dcee2acd2b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x4c49b947212de1dd, 0x693bc5814432c35d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x5a899b9367340105, 0x5479636c67662fee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x4d3108490dee0be7, 0x585ec84d0c9c8049, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x56c6183e356a619f, 0x24f51fb01bb0aed8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x7d7a520218fa01f2, 0x59fe6564228545f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x31fb3ffc042b0b73, 0x65517d5b5e2efeef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x67961d733da8076c, 0x0cce2a7e1bc23ba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x315d0ede2fcb2c32, 0x468f66b04d972b27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x50f90e0f664351f0, 0x11c9ee847da6c825, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x4d7752f63d6bc061, 0x650cf8142b82a9a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x4b59cc495d14499c, 0x381f29ec1aa85b3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x127eab3c10576f7b, 0x36590a17221fe487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x2951716d29f6a7d5, 0x44a52a7a0ff8fd3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x2e21b3487af626ab, 0x6e27fc2d5b4cb169, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #55, #63", 0x389e2e183d9e53be, 0x770eed0e15b7d0bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #55, #63", 0x6d697ff07518ea66, 0x634efbe269fb3cf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #55, #63", 0x5b5c3c574caefd30, 0x67a2051c3e628dff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x0a1abd912204618e, 0x69e537a228d38f4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x7f18ab2a79d4f4a3, 0x437bea8c557489da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x0a2c641f3c3998db, 0x77946e6111975666, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x663040b00fb84fd1, 0x219053a4337dd58c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x0aae767d05d97404, 0x0eca86f61451f3f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x4377c7c20d58c096, 0x2a09c4b4434ca495, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x0271aafd14e9e6a7, 0x2d47e18b30e147b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x6198e3d759290d54, 0x6f43d5b25dcde754, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x7b2d6ee24a1d612d, 0x06a176a16bb3a169, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x43f255d038bc99a5, 0x41282b437a461a0d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x74f632802d6dc418, 0x0bdd70734e1eb9ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x3d2613e910671672, 0x019c8f7c5b267331, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x16408a7619822bdd, 0x6f78672947d48a66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x26daec7438691087, 0x0b212efb59b85238, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x4d52f72e79dd6f9e, 0x0a9999eb294c9771, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x53067cf20dbbf566, 0x071a7ec52eebdb06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x57d956935bc7a7b2, 0x1a9f7c6f4e33ebd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x1484415754577655, 0x487a05e21bcbac63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x01c53a6d6b86f5cf, 0x69ea6653097a73d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x7bee0c4154194e32, 0x64a0e7093eeb4e57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x6d9b7a1011e107b9, 0x06bfd8bd122e96b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x4a4a1840768082db, 0x6be6e8ef14766684, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x705df27944dd7cba, 0x3dc2fdf5179d0f6e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x52997220612866e3, 0x4688ea7443646f6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x3cf00e965a126122, 0x11985b402a72c8b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x2e69d7783028db69, 0x463e751651744fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x1bafd1383f8faace, 0x5aeec3c5302f11e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #0", 0x13a8f90175da38fa, 0x6f1a603c179ddd79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #0", 0x07bb40b315b35d20, 0x29cc743001447311, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #0", 0x0c33dffb537dd78a, 0x15bad995520558f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x185b5444302b52d6, 0x69a268617c91d274, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x1153b9b9518e9d20, 0x3ff641df6af4c664, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x2ba0fe425ba6042d, 0x15678f174e43c84f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x0bcedf977aa6dc02, 0x1fb8183d5a0ad5ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x3a3686d1795447dc, 0x0a39e7a0277eb0cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x6f2e80d668e90279, 0x3f1c8e494ddf7fd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x7e9c5f9964decc78, 0x4f23f2e376e9c189, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x385ca402329182de, 0x48ef1a7c0ad03f94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x62bcd5b4475853e8, 0x0762120850b7f846, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x18e6f10851144dc1, 0x3bacbeaa74108f6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x2cba51ee620c6ffa, 0x425457bd4487ef4a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x5cb34bfc28ccaca5, 0x1e92c50538893185, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x2220f4811f24709e, 0x6007e25516e9d2cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x080d731733ed4582, 0x64c9529f114f7558, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x18cc11fa5128515e, 0x083936e106a9d2b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x03b9d43c18dc244e, 0x117a12455128b5fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x603478365d8d6cec, 0x21e0ae426676a9f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x2ea1baad1cdb911a, 0x5a87395d791b693e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x7ee801145c361d8d, 0x3da358885b5c0c9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x0502ca3273ed2076, 0x13e53e215b9b4d11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x13119114574e727e, 0x72851fde2723beb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x0b3bb80040ac6aed, 0x3873340c1b1f042c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x11d4bc4b3342e922, 0x21c8d6dd2407c9fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x4c1f0d7017112e3a, 0x75307ff7158e9087, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x749e9b26568c73d5, 0x7c053a772c5385a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x736804ef6312476d, 0x256eeee4234055d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x3f4864fa1281a091, 0x7e9c627072500604, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #1", 0x066ec108407072f3, 0x4deb5315444b2f2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #1", 0x17bee57123e221ed, 0x6b6eede11980521c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #1", 0x648e8cda56682d25, 0x349f564822fa9d72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x09ab16483c32e764, 0x4702676d76634926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x5344159e07f71425, 0x0bf1d9ad55ca23b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x5e8387fa278c9843, 0x021da95f47e2b0c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x0a9edfb069bf6909, 0x6b23069951eb8ce9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x7c41099a1226e602, 0x443b92ed49e744ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x529758f679a161b9, 0x0e3273d802afcaa2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x1d8383a650cf7307, 0x1c301cbf6a563e67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x2737a02d54534346, 0x0d50dbd902121080, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x10862aab04673354, 0x787559a630e2b675, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x0c5e477908ca838c, 0x06acda2d63ca4049, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x30571bd016cff7a7, 0x2bacf10e6ae1cf73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x008f60b00108ef4a, 0x3ccd5c5c3af5fb80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x132fd54c130fb403, 0x04dd402b7cd06a4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x0cb115bc1bb051ac, 0x7f8034ed65c72e42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x6c7fc4b45d6e4883, 0x501d6caa2a349962, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x31c18bca24bc0389, 0x2c46a9e313b764e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x292336dd4b46f583, 0x449a1b564247b675, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x5411791051bee7cd, 0x2611f6be35817e56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x688edf745d30aa26, 0x20634dc9046894e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x5e399970443bd08c, 0x3f5e9060691e4025, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x574b848f656edf5d, 0x65eeaa7071696ebc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x011f310a274e09a9, 0x57309cff63fc9a4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x04bc522c3a77dd91, 0x0e3133ae6d9ef5be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x5f33e11b45f075f5, 0x01565a9f367dddf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x11376b781ed78b2a, 0x78c5946b085717f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x709672f75e3be418, 0x3dd8964f6548e488, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x3b6c8e3e291009c9, 0x69b179685925526b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #2", 0x6d4bda5528323d00, 0x4243929019a627ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #2", 0x0da11c5e6240336a, 0x0b0f966b44975ee4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #2", 0x098e3d1336c52cdf, 0x2893f9300ec04d68, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x713d0a707db59dc5, 0x7c5f43260e4a8f3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x43a613ba3d8e01a1, 0x44c86d365070eb8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x5c658ccb16a099d3, 0x58c8038454dd7f32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x74dc7deb23d7dd23, 0x3a2663bb4cfbffc2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x4ce7e6ec6864e4be, 0x2621522e30490c2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x109721bf54feca43, 0x49ef33d83a33c141, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x373efdad275f1956, 0x7ecb20261e383e1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x5e2446352957ceab, 0x2cf88b8540cd3ac0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x270d6c7013e03736, 0x4f17ca004f6150a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x516e38d7789a3fb5, 0x1fd23c316ab3802a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x0f3ad98879b76317, 0x3f90ff5c2dd3c5a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x1d8f403b20f11793, 0x7acfc56504175774, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x0955fc527e4f9776, 0x3460639e6a772727, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x534e61ba2376088f, 0x24aae86919ed1e11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x4ad521e5651de7b3, 0x38255c2e0a8d5f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x0e75b65e1a726428, 0x4b5a9a2828f9681b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x2e529b5e182cf4f2, 0x785ab8c1358322ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x10c734a85fc7a254, 0x2036a2f87fc0d435, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x597f056c28645f3e, 0x2d9499d820020e30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x495576d15879c942, 0x241965a4770e45a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x56c960b906305537, 0x61856cce52ab7323, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x29a65dc624bded62, 0x6c9891342a17c273, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x09dbd5157fffbc02, 0x34a521da747b7fac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x1a72202a15cfa088, 0x1d74e7c718518b73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x2dfc957a6e0b5139, 0x4dd4ae4148c4bb88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x4dd2f38e761a2996, 0x48858fbe3ec3ca22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x1e7e88d402df3df7, 0x5ec5d8532751f8fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #3", 0x5b59073a7fe5ab6f, 0x1e603ea167d3ffa6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #3", 0x061600a7271803fe, 0x3a7f72c9322267f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #3", 0x4bd5f16010df4c40, 0x5c3a2a662fbc5e6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x10df084341acc5e0, 0x2437de1955b1c676, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x577c66683bd8002b, 0x6e0351e92b51286d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x29e351643c9b73b4, 0x7415e3f60578fbe3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x32b59d4a23029e58, 0x443cc60577b644f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x25e1dc503d687c8d, 0x1f083dec5134261f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x3d4e27fd7387988e, 0x390825c5013ae38a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x1a9f9c8c0f9775e3, 0x335d4b7d436428a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x2076c2231758652b, 0x7320871166758ded, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x59052b0b2a2aa64c, 0x3c2754633155ca66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x6602a67750bcd6ca, 0x5ca6f2d430819174, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x0d584a7e7a37535c, 0x35fa8d570fe5f7dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x1d39f1b526a47abb, 0x079c3cce400de7c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x640cf7484a4a33ac, 0x11420de7431bce05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x3dd1cc3b77b3fd0c, 0x4456b18f215b1f45, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x074b72ef57dfcefb, 0x64bf47e9587168c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x6f3834267b0e4b17, 0x3ee6f6b427c23512, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x2538f16435bef24d, 0x5917ff79483d5f31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x067bc9172eb97dfc, 0x78bef0a50b3b97db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x28f0d15922bdcc86, 0x1b218fb713d41395, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x4962474165240945, 0x53e1fb5d462ac30e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x2f6e3cf14d9d42a2, 0x094691132d6f3e89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x45513fae3389a5b8, 0x4eca5dcf6d40092c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x0b6974b3049868a8, 0x45b171f44c9cb29d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x7fa6b3c04d76e728, 0x745ee7af7aa1a8d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x0335d9753b9df8b0, 0x42df080b24dfa524, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x6a5776ad4b3cccb7, 0x301b3cff09b1a28c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x6dfa993d7167b17f, 0x1d85b62113484806, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #16", 0x568bbac462b99c27, 0x59730b14375ce07e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #16", 0x3056dec933967cd6, 0x64cc1f0705f9f7b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #16", 0x6720228f38eb72d6, 0x733a00e275a81e77, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x3d83db7e36a3b8c3, 0x4244d11472899742, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x041a9fec300a4827, 0x6d2b401c3d2a8f3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x6ba840d712257162, 0x620a346207507961, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x5d623e192e87d20f, 0x11021bee55ffb784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x1fef838e42bb0a9e, 0x6947ff8a4b5cd756, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x2574a6c56785d6db, 0x02b9b7d4767b3e52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x1b1c53b26faf36ea, 0x7c75360855cb858e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x289aa9c00db87519, 0x4b73a405023c7641, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x445c2ddd61f14d9f, 0x74c60d83661e853e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x11fb95c6055348df, 0x2349147d4876cdc9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x1778ba4160c96318, 0x4fc7472a7da3d69e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x0f5135283ceb8dad, 0x53a38e2274daf85a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x7fa6984b42f18784, 0x4037cfb02f40b8b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x2a775e6022312d11, 0x25bbf709251b3f11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x11e063fb465a68a5, 0x7ae6c49f4593b212, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x5412ddbe3c9635d6, 0x47d028533a7b0dbb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x1e87837643e2a776, 0x209992f9186f0b9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x4935f05630ad208f, 0x60e5d9643083193c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x117683a701ca7dfd, 0x2e26efda60aeaa97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x3eb60baa15c172a2, 0x5589a2f220c7b8cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x58b2fa2775c4688f, 0x500871863e5ca3f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x17f595a05e5ea7a6, 0x6377e306032a5887, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x24b9104b108e32ec, 0x48be0a9929d5f99b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x4d2468c204ea9a4f, 0x6451075678cbee09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x48cd41c67220d309, 0x113af9a56babec38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x22cdf3984a55f54f, 0x1c2f05751203321c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x4c20734c483b7fa5, 0x72b1dcb334447740, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #29", 0x5dfcf2482514a195, 0x550c300f0ad67ef6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #29", 0x1ad90a242cab05f2, 0x493322ec36afec6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #29", 0x0b09ad9802984f8f, 0x39da44f632ce9fc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x1326827b40f5a0b5, 0x5ca4995f2fc2bde3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x45e03b0539c9a592, 0x288eabed604aeb3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x2bea789b6825dceb, 0x4bf6d7760ead7ccb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x327bd23a13628b9a, 0x20b0aee74eb86c34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x5b9e0b4058091383, 0x02fce3747e9c4587, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x7d1db51952a5e769, 0x0972c47d399afd88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x7f50ed5c2a252eed, 0x704ae9f717f6bf3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x2cbd7e7c2769f861, 0x4ac55f020a5a9af4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x685f991762ac04c5, 0x3a1d58d83fe400f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x1c75aa576c25c3aa, 0x202eec342e3fd41c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x544ba0955d9dffce, 0x3ced50e7486022f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x71008b681a15729a, 0x17188f2606c772d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x721e861e0ed67cd4, 0x0563b8574c9e96a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x617c643e76847e27, 0x063994306f3c3b37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x20a9ad1451f85976, 0x0732fa7460cd519a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x796251d825454566, 0x6b27ec8e4d672b90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x07f14a2b2d7a18bc, 0x0d4b2c8761c1eaef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x199fdc664cef0ff2, 0x1001bf0b2466f482, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x2a8d0fc003dfa69b, 0x6cc717756deb7cfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x1df519367a16a823, 0x74b2efcc1b8d9b28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x08ed24f76e65c601, 0x682c31d110139f54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x64ea44290682d4ff, 0x7f4fda8b6a698935, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x587b2e76365ec75e, 0x4b36dacf0593f13d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x5ba40cc460464955, 0x52fb1cce51dd804e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x0dc0621143a12a48, 0x339f6b3d639556f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x10903a3a74c362e7, 0x07fc4b7227603e78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x78a3098309feab40, 0x154bbb743b1d49fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #42", 0x041553633ed716f3, 0x56aae522169822b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #42", 0x2d3cdcf525fb9c98, 0x26abc20d0d02785a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #42", 0x2c7e719742a2dc5f, 0x776c01901227211e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x7901a3bd6ab62f29, 0x17bb125b04f9a00d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x4afc787f0a768b98, 0x56d7205b54a5b082, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x4e17b5e0403752e4, 0x383b077258bcda90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x34fab5cc1568d47c, 0x001d19085ea7f01a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x1f677fbc70701f37, 0x19c53a142d9dbf4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x2f47362a6ae1a415, 0x4435e208237cd31f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x10dd40ad27eb4d0a, 0x307f4b7a5c84131f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x6a8e296906664699, 0x6eab343d3d5bb244, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x711c75c2192c72ad, 0x42555252638fcd27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x23a2fe467070851b, 0x38357da93c18ee41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x30a7d7ff14f2e1da, 0x14d5c8d271bab426, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x2a5bb6576a27de55, 0x5062a44165a28dcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x5a97fd8c57762f22, 0x13404d1a49c33613, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x4257d3371dbf54ad, 0x6d40093309df33b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x45aaa1b7550e7b14, 0x666346d6533513e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x5b74c1ad52e6187b, 0x1090c6293038cb20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x6c128b284bfe15f0, 0x13c898474c91376f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x3c6e9b0b1d7fee83, 0x08aa25b10fb5896e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x3272d05d51d2e1d6, 0x01703d956d16730b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x3bfac02b65f94df1, 0x52b900d65cce86b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x3d6f7d1313d1c5fb, 0x2691bcc81692bdb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x31911aa806d53845, 0x2071f16f7fc7504b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x5be3b359638d2a58, 0x52fc642f773bbc5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x367342d33b3d1fc7, 0x2774877f37587506, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x073b35b70c93d227, 0x03e9ac762285cdfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x2a13c0aa33ab94ff, 0x323b576a43a9d0c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x057e76d5037944a4, 0x30c043ce5c869107, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #55", 0x697292955fe6d484, 0x395517bc41793701, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #55", 0x73b89a7f787de628, 0x580bf4b926e20fa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #55", 0x7f531e6d79a5c423, 0x26a95ff42549b527, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x5d32ee7c43f9f905, 0x1c8571865b36d1c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x7f3718cc1678f343, 0x128f46cd13a6314f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x230cc56a686756b6, 0x362bff4b06724e84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x1c12ebb57adc6315, 0x4a1c1f474d208614, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x7e55a7b962fc2ed8, 0x29a7171c2191628b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x42e3035c3b168e45, 0x630a998c67c83a4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x3394746d3553a9ec, 0x0eaa49f8369b9ddb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x2ef96e0f786ac488, 0x5be5530232e792da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x3c64bd8d20adab6f, 0x0e1e64a10c2c5c8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x37269eb255fe8d26, 0x1fd28ddb3b9bd65a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x3e65e3dc0c2a4425, 0x420e24de5a33641d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x0706a73a50fb014d, 0x2753ea315a78cf92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x33f730255f14cba9, 0x7c0a321d055c4ef3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x1a2b59ee7bced33a, 0x6d24894276da3381, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x31227d26095b245e, 0x2d75d15c4dbfce5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x01c5e8e60ec5c5d7, 0x00a76135601beb36, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x2f7371460c1ad59c, 0x6c4847c13e2aa674, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x621962c33bd4a1ac, 0x79c67cce669a0ff8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x47fee5d168215e47, 0x40cd7415207f469f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x391c5f947702484e, 0x7af816314f058d0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x561713f741866541, 0x5461dbfe6d138fba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x3d55387b11639498, 0x63edc33b70426de5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x1abeb8f63ea99d76, 0x3e023c406e77b5a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x4d6f634d3adbe899, 0x4e93a0d81c84a1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x46f6be365475c51f, 0x5aaf48517ce2d493, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x104a66cb244a58a1, 0x637ce48b291020f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x0c6bb6e844877dca, 0x498f679858494c9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #60", 0x3b89c6187bb0b5a5, 0x274ed9a74588167c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #60", 0x3d371ae616896972, 0x329ba63611a0da10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #60", 0x27ecfe0a3fe58436, 0x01e347f57a8c5362, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x7e8f21ac3797a9dc, 0x6904090442abb700, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x7273927539dfa12e, 0x5f3058dd4bfe84f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x0e55664d2c5e3e17, 0x48e1598c396a50ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x50a896b82c09d93d, 0x627a71a41e9fcd18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x709157071e37f35b, 0x76e919b45d144da0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x19e8a90155380a53, 0x229c641d2c1b1d1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x6bc173c53f9f3f25, 0x3dbbf72f571fc3e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x7f84c35b3ab0204d, 0x51ac174913ae71cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x7247ca29358a81ad, 0x565a28d07e13e507, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x6f6a22dc12f3c38c, 0x4a126a0064bb5c9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x3f5201a300a01eef, 0x1e25ad4a7dbf8929, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x2ca9f82c13486ff6, 0x1c5f56420ffa985c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x318063520fab4a19, 0x6d0ee5fc1d3b4f33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x64e3546d07126382, 0x49566c524b690c53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x46b1a2a77434e784, 0x2288d03a50a4c832, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x2ee507d13aad62d2, 0x64533a0246366602, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x7037e47f0e5cb509, 0x444a4b09212cd1fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x21507895240ddbe4, 0x05e82e9a5fa2075b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x24adfad379c0e6c7, 0x5d61908560a27a38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x0d0956bd5dabf891, 0x709d12945157f2ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x6d5742aa37e9ae85, 0x6e9342323e89ba0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x3efc12072c7b969d, 0x09f2c662523a9717, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x20b07e210732994c, 0x22df5f4a05adb4ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x41dffc1e102e65b9, 0x4be41ab04f9585f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x1e8b1ac276aa8687, 0x70c257ed3217e09d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x1ab8626c6f1b787e, 0x11b9e7f93fdb9357, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x68dc5f45111b2024, 0x207e0d8f3f665d3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #61", 0x6ec718b57f519271, 0x10be503f75e5b602, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #61", 0x373b40f63e623674, 0x346f70125c1e5b5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #61", 0x6addcd11513851c1, 0x2e58f277763752fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x586aeb0d47c9225b, 0x7be507ab0b8e4b32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x57f788144be62912, 0x5b23d1251a4ae72b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x4290af9a5e1cafc1, 0x4c62c7c87682a2d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x4d38283f56dc43bd, 0x365e362d5d491206, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x67f763e12d6dbf84, 0x1caf6f4536148784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x2cbf51f66069ad99, 0x2bfa3d8756be7c96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x1ecbe40d6135ca6c, 0x32dcd7f563fa92ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x326e1c2d5616ed95, 0x5a31e5ea09a9b11f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x1de00ff1705bcd76, 0x1537fc510ad9073a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x3c41f6897186b62e, 0x2523ee6575d79805, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x4fa365ef22b87109, 0x6c5a3adc7ed2a623, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x7994b4c678cb276e, 0x5c1bb8291cdb8e2f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x2638e6f37eea533a, 0x52f015b3618c18a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x5f5400d36b276d33, 0x384a953d52f838e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x4c5d379f1124b1bf, 0x36f2cbd57e1fe4e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x673b9f551d019251, 0x07c996007ecb53cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x0d5d5fc82ec8496d, 0x09a45b07051baf46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x204eff9b674d8227, 0x7af3474b499f5651, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x0a05f331248db49d, 0x4871fc746ff2658a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x1d58dc0b5fbe096d, 0x0ccdf3b9039aa7f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x5ea85ca71d7155dc, 0x6526c09f4391c2fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x0898c30f4d7cc7bd, 0x1689fbe73dfc5d7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x5ea1797c43e5d85c, 0x3c1c425c54f5faaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x60e76aad5d65a983, 0x53c14e7c45dd18d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x0c2df2f045ec0f63, 0x4af8c8176e44ca75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x2d39918a00561d3a, 0x37e420c62c7cf28b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x24e3d1d7293d4bcf, 0x1c6f5816373f84bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #62", 0x08fb553c2000ed52, 0x3ada2cb3423cade3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #62", 0x3d72432e1c586cc9, 0x05ce70e167a3b1e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #62", 0x69d5348661bc51bb, 0x25a00f5f460b063e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x25a22a176ec24f69, 0x1b0100ed4876ae02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x4c27f8ec594c8eeb, 0x0e53c6d4068994c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x1f389e4e2cb28000, 0x74ce5f3a5855ebdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x2d089d3b2142367e, 0x04d2de684c722fd9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x4a7f824e3e8be147, 0x03b1b49451ec6f12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x5e8cce9919f78dd7, 0x14291cf5537ad78a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x364ffaa060be98cd, 0x3b1e896e1bff11c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x427aea887d0b18f3, 0x620a180620252f26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x6bcd685c76efa3fc, 0x689bdd28681d149f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x503c32e86375089e, 0x6ea6a96437f56148, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x1027889e151e2b8e, 0x104b4d256f74d136, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x3660620c3f98b5a4, 0x3be7010f3d3025d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x7e2496eb2345b1e1, 0x0f1c94ec00dfe45a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x3d3d3fb80f794553, 0x545abbe55cb16585, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x7037de215aba8f53, 0x78b0774d738d3a58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x57c5a8467c4e46a7, 0x13b2697e32b2c8a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x733deaa3097686ad, 0x1acfdd49439310a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x6ceb8f4b0bd3bf10, 0x7b8871ea437a1d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x20f1ea9e6ed5efd1, 0x32eeeec27d1317e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x2e6ea575495fd2af, 0x3a433dc357524caa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x6ca584902c8cecea, 0x583231052c933c61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x3c06323d01f51933, 0x0944a1e629e2c449, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x5cafa88631226820, 0x1d6ffea12c3e105e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x2d70aec779c0b651, 0x5ef0d908347550cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x03373cfe7390d358, 0x7808616e20ae996a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x7f6492681717a5b8, 0x6428b6f67022cc49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x05ed9589277921f5, 0x6d35e43220567d06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #60, #63", 0x70d8f4a44fdafab6, 0x77a8c9b1345c3aff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #60, #63", 0x7c67e7a06a341946, 0x60ef77605d7e7935, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #60, #63", 0x6c29327924d13c1f, 0x07613d7e386e19dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x55f3a43f439d0344, 0x64ac2a3c48d8daff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x3d5db99575568d39, 0x7d4e2bcb03645306, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x68e76091083ba367, 0x2412ec714094f693, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x1f53491f1deda70e, 0x30b7c2dc684bf2fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x4566c904004b39b1, 0x08a270002540dea8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x502634673a8c9107, 0x599d19a7363fbda8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x24c0aa4d1b1f745b, 0x13be36dd4c8e1c07, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x3ff0b07b69a86021, 0x04fc35e510e9dcc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x2d4563655710e390, 0x59c2b7c515e454ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x4c6770c93d5b9432, 0x1948a7c16aa31cfa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x459737995befd669, 0x2b38138d354ed15b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x79dd7d77263d3455, 0x1d9ac45564ea80b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x26886e0763c87908, 0x0a2b5f603f44467b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x1e550a0f09423b01, 0x7584042476aea26e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x2461af5d4838f45b, 0x433cbe764315b45d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x31e1547c2dc248e9, 0x53ff912364525fd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x04d32c79137f5c53, 0x7a36b4925f26b7e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x50daf0857501e868, 0x49c9d4db513a9d43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x50f1bed1242432f3, 0x06896e9e1672281e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x4a61674805880837, 0x7b5ca8d64acf3c48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x6950813f7f9786e8, 0x0a1382c470e9d54f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x08d9c1e92ad53634, 0x679877be07a58b4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x730e2a8f1ebad0cf, 0x4abb3fab2d3b7146, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x4c7d19b80bc485b1, 0x118dd11e24ef7f0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x1f43e2044de00bc7, 0x041636ec51504631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x42e1f42f29145212, 0x228ae374701ed28a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x4d38850501eda37f, 0x0690faa813d3b300, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #0", 0x0775abb668b6720c, 0x5ea2ef481799ec4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #0", 0x684df8f4701c395b, 0x0883c19d70c62cf5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #0", 0x1af16f8f4326f7ef, 0x786bb8437127bade, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x61e1c8be2ff0fd43, 0x1e632c240dff9a1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x3bb582f437055015, 0x32ef19292e5ee276, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x04e55bdc223a0c1c, 0x7faf28a75af964f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x4b4e5e2e51a9322b, 0x4b18378247c7500b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x5396d5aa3a3df254, 0x5b9b030b1886e334, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x22f4646038a4911f, 0x3020cf825b0c8160, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x28c0ca7b443e6698, 0x4bd2ae550b425d55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x07655e871acd4457, 0x7c6a183343b23a0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x4abe419a04a0ed52, 0x51b1d42969472745, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x3ba63d6817553263, 0x17a609bb0673c48e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x398f3e7f2c856109, 0x616d2987408b9944, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x7e2e933463edec5b, 0x0852e95004dd9cad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x1e2bdeaf4d854f63, 0x1d647fe151c568de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x0629e08378a49893, 0x2cd1ea3e41204310, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x3ce2ff2c48ccb898, 0x4c62a0652eeaaafe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x6399fcef444eb931, 0x729ce50844485db3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x48efa68445358eb4, 0x2d8f84f92e583e8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x5c8ac11716392c9f, 0x34cc03180495e3ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x42be8da94d746680, 0x45217d301619ff96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x316252dc385c1c25, 0x1af79c4440ed20dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x05e16b893f8473fa, 0x12b289bc4f8e318b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x38290c8e5d111500, 0x10ae749b0c0b4c0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x25ddcd982d92dc12, 0x3af5f70a750c0bba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x71e1954466e3ee66, 0x3954696d0977ca88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x2c197d1b6c9c0c2a, 0x37d009123ad13bc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x02d538ca04889ce4, 0x3f671fb408a43e32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x51fd036539b5da0d, 0x1ebe3dc94593c673, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #1", 0x7211f6321933710c, 0x0680e750035f5641, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #1", 0x58b7e507639bfc68, 0x52ed87cc77f361bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #1", 0x40ad11683ef4a4d1, 0x03feadc710e0f195, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x6c8780e43f4166bc, 0x05ecfd4f668adf01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x2625552327d2b29b, 0x7002a9895e691628, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x146ebec558a171a4, 0x193a51f0523ed23e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x5d2a0e8879a14e39, 0x5ae310701743f78f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x335728466358a553, 0x5cd7be022f2711ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x7c8c165f0573effb, 0x3286682e25691e79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x690fec63215b2dfc, 0x1d5c80345543fb66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x604fd2cd6c11ea4a, 0x6624ecfb29bcfdcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x2b535107004a8655, 0x1047dccc4cd753b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x281d38f0447abbc9, 0x2b4069d95178a62a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x1d1c2d6d7e9a88d8, 0x23b778683c8bf7b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x783bd71230a7ad48, 0x53cfef457a463bf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x1400529b5bf3b612, 0x296d4de32b92ff58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x6167a60d6e589e06, 0x50fc1dd1108c68fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x0fb3cc024bf5515c, 0x65d064614a779270, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x38073ba7047c6d08, 0x7434903b70039ecf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x04c6f35d681b5c5a, 0x3cdaf281635a8cae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x2c961824588aab40, 0x34d332d82ce42c4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x572534183d401349, 0x6970240449b24591, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x6de7c0916d65cf6b, 0x43f881874f610b2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x4959857d4bf02854, 0x7af40a8301e8132c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x3a48c65a7844e088, 0x12747c272ac12b8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x443a31e4696d4e35, 0x7538bdfa49fc925c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x6de9bb3d76db23ad, 0x3a00312c7c416d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x5ef68007146f2d11, 0x5f9bfa3972b0ae9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x6cf9d8510904feed, 0x1f94dae90b8c982b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x4645123619375f44, 0x553eddbd441f0c6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #2", 0x069d2eaf0e742217, 0x13801794342cd2c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #2", 0x5a644a6c4889621b, 0x3614e5f44ff6b42c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #2", 0x40ce42a36ff09db0, 0x7ab7dfb614ad10c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x595debe618a9d44f, 0x5ea9a32305087488, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x0f84f7fc60e5dc4d, 0x0149e2134747a723, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x7555095e598d30a7, 0x39f855be6e7b7803, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x62922f944f46edec, 0x7a08102f624ee1b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x687e4d3039ee05ae, 0x266dee1a28d741cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x486227c61318fa87, 0x5d0414936f1b7be0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x5ba25ca339ca0fc3, 0x3f12300c22c67232, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x29baad73161d261b, 0x377382f81c709f46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x2ec6fa6a22c2f5e2, 0x217913ce03189959, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x03a8d22f0458963b, 0x4a60407d3e4bf266, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x5de5c6e326cf7a99, 0x2cc76a6a78fddb8d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x7616688501baab57, 0x5b4cbd3d4077f677, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x3ba8b10646534cd5, 0x694f38425e94b5b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x596c475d0cc261a2, 0x4db03195040ad8cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x468c71655e44cdf6, 0x26d14afe350ea400, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x7461f41272f85715, 0x517f434670471ed8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x15bb4cf73dbff8af, 0x735fb8322328ee7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x42188eea0e3c4b4d, 0x6174e0e319641f26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x350bc5e66daeb7f1, 0x1261fab31ffe55cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x6f69634849c58487, 0x60764c452b222e6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x1018d15d576715b6, 0x09b6e4202b12144e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x6429775855ee3818, 0x2f1ced1a698518ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x3433060f70130000, 0x1e93bcba2ab5e8bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x630b57150e5cbfc7, 0x1afd07952894fa21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x4c1cb8762d32c980, 0x4bbde89d78c6a40c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x3b6f14cd248cbde6, 0x122ac3320e354761, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x123b75d70ea9e973, 0x2e339d2e707adab3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #3", 0x586f6dfb2553ed3f, 0x1b9d091e01a4d91f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #3", 0x7cbb02f55bd3da88, 0x2cb6ed6e68883f58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #3", 0x31c212a170a114cc, 0x520d581260e47a4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x60b414cc26976a9f, 0x0b9a630a65f518b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x34f42a675a47fb6e, 0x0e8a12d143bf6be2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x077ac4ef4eb0d321, 0x3c860fee0110e2dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x733d91073d79c76d, 0x0f462a3e42e9d9bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x4c23b0e04f01bd8e, 0x3364b470057906de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x7455aacd33d4cd6b, 0x071ddffd24931edb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x0fa8a7f45f28b645, 0x0d1b5e337110adc2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x4fc9cb115d8f8b19, 0x51f5280f416aba95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x0426f5b935e9e616, 0x275fd345307ddfde, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x1031e18430c35bae, 0x743d4bc0391b2020, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x7f742ecf49722d3c, 0x3a2c02fd17aca673, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x06ebf4a90dfb34a0, 0x5a96803072b1bfd6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x5cfcf22e7f48a6b2, 0x782ac6b4530fa589, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x331d741d04be2298, 0x77a2c46551529cfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x63e6d8de145872ce, 0x42634abe42c61c11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x71e7fde72b90a9eb, 0x0430d6a633b0a3ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x617a9001586bcf8d, 0x642e83cd760ef3a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x092f2b3c695616be, 0x2f2a13c071ac7186, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x32c843fa63ef9829, 0x095917f908a35a0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x71eaccc9737fe096, 0x7b5519e239b438a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x72c887480466a291, 0x0cc3de2c4ee7bef8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x0924c52a629da6b2, 0x203a5bf425e5fb66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x76f619806cdcee1e, 0x68ac17776d0b9e08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x186d980904eac5c5, 0x20bc41f768de1768, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x5d5695520e171ec9, 0x5eed0b0879e8280b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x776d358774edb18a, 0x6b9499916685c08e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x58dd49b46a7e347c, 0x6f291a9a2a357981, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #16", 0x5dfe151270ad9050, 0x63e9b2244ac8167d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #16", 0x751432e239ea3169, 0x19afd57550c69c5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #16", 0x1c87d81c5f58af38, 0x76ac97c17e38f80c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x4c359d560c00d80b, 0x6b449614137df19c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x10eb9dd05b49140d, 0x7c5c090464a33560, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x696032d64a1ff6fc, 0x5e8b5d6b6e423323, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x3f0da88643f10e4b, 0x54c7f3b160cd685d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x2e6f42c76eec9402, 0x0b02e1de17eaf23a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x5f9a24527c62de2d, 0x62b308b80c6d57da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x364d0f9753e08bf6, 0x5d33f43554ae5734, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x33393b2e3e2be554, 0x52e74f4052d4e7b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x4a2cbd6062aee254, 0x6652d94f7f6ed885, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x3df7f661429d6b50, 0x64120de55b185b30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x0cbd624c1e228205, 0x495a8e5327582937, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x6213905013287372, 0x082591944bcb0ad2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x02150774466905c5, 0x63b5fd0d1082d318, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x42cbe3f27a241f27, 0x1cf02af261af2bc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x4e04ab1d0944d23b, 0x365d82fb7918f389, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x4770b7903240b48c, 0x4beddb3c013de64b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x14ef96e064beccb5, 0x00acbed0119d74f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x275c380536105e74, 0x6cb5d02052e78d41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x5432e0790265480c, 0x7a3fb67834199a51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x158dbb7e639aa231, 0x7fe4a524364670c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x2a03a7f663b96ed3, 0x46c943e117a2c2f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x5ddd8dfa2faf71b3, 0x7951eeb86ccf8be8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x38f443ef31d65aae, 0x65e87f722be23917, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x64170f3a2dccde33, 0x2d201f630064fb7f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x128baae97eb8408f, 0x1202706f7906a61a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x34c89f03462de9d3, 0x4bee335b39e7e2ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x489331df6de62264, 0x6e017d4008fb7f7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #29", 0x5180c495060b3427, 0x3f41f0465e20ed5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #29", 0x69c4a2fb6f159f08, 0x75c3b04f7b846c8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #29", 0x1ec510bb4e3c77e5, 0x6853f87347a230f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x0012d29420a48970, 0x73846a0d57b954aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x4e7167a36a20c098, 0x581e50296429e1ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x68d90128291ebb44, 0x5d3087e960fd128c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x6f4ca51808e672bb, 0x1ae4f57b1da1a02b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x76cc951f65df0fee, 0x269d1fa837dfd6f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x6bea44150bc474a4, 0x1600c455484d59b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x7ada13ac2c25beb2, 0x43d1c63f55aee710, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x7a62369810d58213, 0x1d511806199f2468, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x317a0b834976c93c, 0x715879127a75092c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x339789d43bcf72e3, 0x5e9eeafa7feb7326, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x64ee2e287bcd7b2e, 0x60e885b31c708afc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x04b3ede960af4ad0, 0x3a122b28543ad340, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x468e5abe221b6e8c, 0x0c1aaa377b808308, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x2ddfe331079fa2fb, 0x43cddcbc32789ed3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x33c561ad25789dea, 0x082785e428b9f6dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x364e1ffd33b19458, 0x42591b452e279845, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x7d285d94073b8c6c, 0x289ca17167c82b80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x430aff4f489c2459, 0x67b39ea630bfe768, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x44699f8707429d8d, 0x4d30726527f92d77, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x67f1e85d084eaaef, 0x7c3400b7491d8d70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x2a6a197b086bed34, 0x449e10782e80431b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x100b902f692067d2, 0x60f8e1ee5849fcac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x0e9905bc435d0ecf, 0x0103f38a43d0f1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x770ea3271a952b94, 0x71f88a2244e725b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x21d0b8001462efe0, 0x2caf5139743700bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x5cff143972275a89, 0x24f6e82464dbb74f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x7969f8160908e57e, 0x0cd4e4c72168b3c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #42", 0x1157906d2f2451aa, 0x6a864131615be073, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #42", 0x37903ede70d5057c, 0x0fdc238e3bc1a9e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #42", 0x59f56d4f150f9a1f, 0x140ba695479bcf0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x586ca8ef7d654b0d, 0x0b6cc0eb688e730b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x17fa76a15a24e9fe, 0x2d7598c54f7b4c16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x6e87d9de68a934f6, 0x43b24cd239cb2ea1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x5ad08f7f2b7bcab8, 0x1ea6e5f14b86ee18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x3484b0365775e30a, 0x6cefa1d9543a8795, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x069a34b445728b96, 0x3596680845dc40a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x3647911215a99122, 0x019dea8d3e2a7393, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x2ab92b421133038c, 0x05c642a1103cfe61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x0e984e9926410a32, 0x78cb716d0325d431, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x0065f43016536d19, 0x52a120472692c53b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x7efca20f7f04d9cd, 0x605df3dc6eedce0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x2a80a48527645e00, 0x3a74bc2759cd318e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x7eda410a639e212b, 0x2e07b9235f0554bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x2910acc1267f7fed, 0x24e19560057475bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x3c29110f49652bf3, 0x439ee9525f583dd4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x5a982f7f6860ada2, 0x6f953c3566e23c51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x0ea1b7d43ca930ca, 0x6a08108269307e18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x52fc9de370213730, 0x0fc343530f07ac05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x6f2610fd386a363b, 0x7df57a1451f93ff3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x5fce943b59ce2aa5, 0x2bc6718119a6b583, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x3d6c4bd01d8d9f9f, 0x78ac0a3f5ea8d545, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x440d1f8c27bc3456, 0x641d4b04667cf892, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x71216049356a729b, 0x45d536660036309b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x1dcb203e51207d6f, 0x67186ced4bb98fc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x0dc9ae3944ad5134, 0x34ea0de12c6cd812, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x34ce88643969fe2b, 0x3b74841760c64c1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x71d434665e85fd91, 0x32bf8c1023f49962, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #55", 0x3854283636475924, 0x3d9b4ee551a2c8a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #55", 0x53d4f8c31468e8eb, 0x304b9de775c07407, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #55", 0x3c251d422212a2ff, 0x5c3d6c9917e2184f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x577d159a7f30b5d7, 0x181848ea2d467d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x505133472dea1b35, 0x79000d54754835d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x72976c695d299202, 0x21b50deb5e1ae180, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x1693902e71a0b9ad, 0x3ee12d9d2765f4ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x5026b73f08f5dd15, 0x4b5a8e300867c494, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x3f3d36390a562b1d, 0x5a0a8d36087adf75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x1ebf14085a78c015, 0x7e3b537c13122efc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x7c8b6314430c9035, 0x2af4474b5ae4314a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x423d460d012abc2a, 0x082aaed6540878af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x2f14d75f6b05bc72, 0x4950ae87128e7954, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x482f4e752f8a8872, 0x70a95ad421ac43c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x212b421f146cc6c6, 0x491238965ec2dea3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x1d62a3db4135306d, 0x672aa3377151f95e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x4b8b5b8a78082c50, 0x79ccd8d45c9fda14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x5280ec661aa6505b, 0x6fb209106a4a6f93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x5db2e0914d594fb3, 0x452ea0dd4f0c4f7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x4e840bdd6c6576b1, 0x2314c8291ff0269e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x576b33232327fac6, 0x327e9ff27d98e33c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x52b2833868575f9b, 0x1f4527051f9a8198, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x7cc4266265880373, 0x7e5d603b73ddc558, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x26bd33e05efc978a, 0x652fbeb61a26ca3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x5704c3db6678ad62, 0x76c6a45272488f6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x011efdbe21c19fdb, 0x5c92fefe2985b041, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x6f1aef8f1ba6c7e5, 0x7891ffbb5ed1de4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x080c3e963140a4df, 0x7ec204ed3d9efb6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x54689fa55a7d05ae, 0x3b37dea95f7771b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x42d465497d6f538d, 0x7f11f352271b22de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #60", 0x62f757000028a6ec, 0x1af8e8363f988bab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #60", 0x5f253e775085fa3b, 0x59bf55e909b48ae1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #60", 0x36fea79d5890194a, 0x7bfd1a4c362a0252, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x7a51b9255841b24e, 0x5fafb293381da55b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x73e87a3315b18897, 0x16ef83aa696ca8b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x46f22d76624382ca, 0x270ba4217bf4b8c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x3cc088785a7e1dd5, 0x5b6c2a831b5acd1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x57ed71625d6ed830, 0x4275effa7f94edc1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x5d977f1c18eccf56, 0x3f2d796d3ae4c863, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x6972c99140966d90, 0x449953443cbcbd93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x192686da52967278, 0x72e6bfe52071712e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x2ad824c76f7e9a34, 0x588f168a13783fff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x053022cc23f08cd5, 0x7ce4e8b41ec09efa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x06340f9f76218247, 0x1ab557c44c225042, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x509fa01c29f30d58, 0x677d1d5e42f49817, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x0761e58801b6ff45, 0x428985d8288d117e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x1aa3ce9b280b2d25, 0x6371d9e164f964a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x68a19ab5149ce21e, 0x21b622380416982c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x673354967d171fe5, 0x2488095b01c8218f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x6c95ba1912254a43, 0x1540618f120b795d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x3615d7184b81701c, 0x30cc185871c5dce5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x41a2f26325654a86, 0x3de82d283c49e6b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x4f5857df41c804a6, 0x7f3e7ece1242927f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x437f03ec1e417ddf, 0x3acfa3fd56ba3d67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x464cab045d69c445, 0x3bb3a20c5e22d287, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x7206a66306c1740f, 0x62396ab42eee45ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x03d893f445f6c8d8, 0x30b667495939faf9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x581c131b1c118caf, 0x6b457457706e4e0d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x6792fccb201c581b, 0x62342af30e31ea33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x4581a2a149ba4fb8, 0x4a7bd0ea2935ef2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #61", 0x0b82545f764825aa, 0x3b7881ad14d9fa80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #61", 0x1489a3892747d9f4, 0x6b9437e84f01584b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #61", 0x04b19e390f5d9586, 0x2d242ad25ad64e8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x161f09953a7afb91, 0x09c4944876b8449c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x0071c46a3b37b3ed, 0x4ff23f9619f79d89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x5749409c6c9a168a, 0x0a65eb97588dd785, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x0cb66ea5313b92a3, 0x66bfc1b93edc3d67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x7af5e25c238aae42, 0x68122c9552381146, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x19d2d3ec52a643af, 0x67120bc7067836bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x79ee1da3029db9d8, 0x55798f062e5c7776, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x11fb4f5f12f75a4c, 0x0932c6047e9fbbdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x4d7255dd454a400f, 0x75580079281a58f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x0081f3fc4c77e215, 0x4211f67e4de41a47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x3911f89f0d31b386, 0x2671f1cd57cb3498, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x3e6d46297eb99e94, 0x16a771ff45c86744, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x22444cd67f128451, 0x1800788a39632885, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x51b8c8001554ee46, 0x3fdb5f403c1720c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x17f2a81f73a65e3d, 0x6a7398394ba6e5a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x069db8893f9ea1fa, 0x4a46a18129edf77e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x04e8e20a141a46f0, 0x5208507254100e66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x6092290548661a7b, 0x21f428ae056ad606, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x5597ce0173dd7c9e, 0x5d360a9f19a421a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x72971b33776d0173, 0x5f6c88e81405142a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x767f85c40d439bf0, 0x4d683cb014db6809, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x22988a373b662105, 0x50f288cc48384dc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x2f0c7f425e25d4ea, 0x13df33693a8b3256, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x1dc476e436817a46, 0x647929d435aa37cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x4a9bc1372bae6ee0, 0x09ba463222ad58ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x7414895b054e3994, 0x28182ef52b2dea3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x792bb632243e94c9, 0x44d20be149ac575c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #62", 0x1bab963c2b19a836, 0x5db16b866bc2d165, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #62", 0x385d44275190c23b, 0x009e396f122b1c01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #62", 0x0cf6e3416e429d2f, 0x5a6369c65af5ce5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x4c68721979fa2a88, 0x158100b43c036283, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x307ba4ce7b67e081, 0x71ad9a4f6a2ce8fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x27164f6134f270e1, 0x0cda41ec7b176605, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x3a40aa756b175c23, 0x264550421b2ad8bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x0f55f0ec42889b9e, 0x64d73018336c60a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x6da243d51fcd6b7c, 0x1f2f320d2b018729, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x715e2db717900cf0, 0x3d2ca32a25ff87fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x05d2aa1f1676570e, 0x00f5565a7e5510f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x107081962c060dcb, 0x3a58737c523b1c38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x276dee4c49424721, 0x3c68053540ec2664, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x7e34b8026248dcac, 0x3c038c6a4e843dad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x4d6038cf4e864681, 0x69af166938756277, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x110ee21f0b10f52c, 0x6be1c31f5cb629bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x2ade60a844e4540e, 0x07b7b0e47eb125f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x5c7460fe25a6044a, 0x24b0adf01c3c8e5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x3c1c5b5854ea12d4, 0x1a919f5862470b1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x00f0209f70ea2c8b, 0x348227554c8cdcee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x3a2c73ac497c8fbd, 0x0d790353285e0eeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x2bc56c6960916301, 0x76e24c9838612baf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x2f17a9825cb85145, 0x70d68e267925a538, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x67c946715d937fd8, 0x55dbcef340268ba1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x2277d3e663885f86, 0x3ed7b19612a7a719, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x092e63d14975d4d1, 0x2ee435797eec34e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x1e5fe7a515b56758, 0x61334002454abf29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x069f93e31f509f6b, 0x11d79c181f500844, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x68cd2f283e9063c7, 0x47ae172f40cc078f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x1f21c6c86a03c165, 0x792d333e14929b91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #61, #63", 0x46bc12aa63940fbc, 0x0db840c94e39704a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #61, #63", 0x41278f944d37ad81, 0x0e5ffbeb2e85591c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #61, #63", 0x30c00d08701135ae, 0x412d0035639f637b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x39870a7f43bed862, 0x628b986039ee70d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x59743fba1110cc1a, 0x7f39300257e6f224, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x30616b853ee51197, 0x7736fa686013d39d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x7d75755e1a0d0e6b, 0x20dfdb2d192e9aad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x0410cfd03b797707, 0x2dc1363e1c973c26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x1f0d86c47930a85c, 0x6ad0ac704acce27b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x466855dd3a7f3bcc, 0x79523b9760351658, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x2a90717b26601233, 0x43d479d3772862e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x6a1eea96305003c1, 0x3116d3be64177bfa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x4160cfdb33356887, 0x3bfe6e1f43932a50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x721a7a1f4486d91b, 0x23a6fdee71c23b61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x5e93e78638b20c4d, 0x0af0d60e6f8fef7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x742b835476f7d814, 0x0c272ba462a4b757, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x7028807026c3d569, 0x2d7199d213390a18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x6143113537429a44, 0x736e20713690d64e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x5da2ac785ed00cf2, 0x2db939330bd382b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x0f2010b32be96cca, 0x6feafeab47c1970e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x5f1ed5512efbbf4c, 0x0b54c15e5080e08e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x738298674d33f1fe, 0x42431bef51394f70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x05e5fe4b4cf06a92, 0x40c93eee52167fee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x43e842a6622cd117, 0x34bb37457a11819f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x08f0a68000b8ac29, 0x0d4a8bb83410c317, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x37fb466d185ad298, 0x6aa199656a33b7b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x772adf8a65f23911, 0x76073a66159df2e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x11dba5db68b44b52, 0x5d5f89f3064af03d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x17b00a9e190eecbb, 0x56cbd0cc70fa7b2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x6642deb902fd098b, 0x4233ca9d0b32a306, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #0", 0x4fed741d12045a39, 0x5d4922f46c28dd04, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #0", 0x74312b507384ea5c, 0x663a5ea413d5b6c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #0", 0x743d96853288133f, 0x47e679da7d21d1d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x4ae2e5d85d5cc3eb, 0x675589852c38dcf2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x434efcfc1f3659cb, 0x41d6cfd8420dc562, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x07eaa51d1f24866c, 0x4858b5a0552aa2d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x383373270858e8a1, 0x46251e041f9aafbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x0b55f22c081675b6, 0x2acd52c21e7651e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x1a1acfef70d98d89, 0x0a9f2ee55b436649, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x645e77e536ff96e7, 0x6f191d0c0e4bfb3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x6987aa2672c35694, 0x0b6dcd0f589c0e6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x50201a8046abbb35, 0x04d4eb5d346a8ffe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x65e215003ed10b01, 0x76785561136f177c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x5df5916d2ebed858, 0x6899ba546dccba1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x3717c0f93834bc9c, 0x0d6769da16290494, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x404b32523f3e855b, 0x349f5675426db325, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x301812e40cca367a, 0x1db1196e5a660241, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x43c9cd61741fca8f, 0x68b1fd8014768aca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x66e3212371e78491, 0x6d1299342d517788, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x38933fc658345ce7, 0x61bc078637033ba3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x170567e8330c0d74, 0x4a7253201e7554c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x61cae5cc19a978bf, 0x0c420ee574faf955, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x51de355b3fc3545f, 0x0b23fdea18e2a6c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x7f01d9ba79017358, 0x5b5059ea122967ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x05cba9d25541676e, 0x6c8f69ee2f19ec9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x496131fd30a3109d, 0x4390776949957734, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x228a952f58a2f642, 0x76e6eebc30445320, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x30d7532a31b9e1e4, 0x67478ec45b1dd4f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x64c5ef5805d538a1, 0x799329bc47dcbb12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x1f7eb16047fbb252, 0x3cd7b4684690d524, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #1", 0x07bf06b13ac3d5d3, 0x5f737be9715ce6bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #1", 0x33c5492b7015b856, 0x03864e6806c0e06c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #1", 0x45571fc4796b4474, 0x35dacd0b3990f2fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x2a0e55117a0d58ed, 0x03266a310eb851c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x52b04f30264433a6, 0x3efca4e24c98ea40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x57fe158a2149e8f2, 0x27b6bf360387a25a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x271f2194083c11d4, 0x4b645d6c3cc404e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x5037c42662c855ef, 0x0354da06469dd2f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x1d8c2bc23b810818, 0x37fab9b057f6cad8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x2b96c06f1492784f, 0x5eb7ab44515174ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x0dfdbcc30e08d21c, 0x0ae267ea70ede033, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x08162b093ea2d6d7, 0x7fa631f5380c11d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x64e70a7d2c5bbb4b, 0x04a4fc155ac67a39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x4da5a43d29b27a00, 0x5e4e1c933ce52007, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x31ee8bd47cfdfeef, 0x79a924e974c4c5d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x5fc654de735d5276, 0x3b6298c602264ffb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x2ede5a8e38d4c617, 0x5a1d1ad37d5280a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x4d673e6659865d77, 0x4ea3f58d5a751afd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x678f2f934b092d26, 0x4b62fb315b64fb29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x09ac03fd18160912, 0x13710cfd6fa55a9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x4471c45d28b9f16a, 0x4a6bd4d66e930e7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x526c6b6a2521536a, 0x2b782e811217689b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x221f5259423ec732, 0x06dc2e6c045af73e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x359c19a8609e620c, 0x0681473901e5a737, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x197328234ddc1d64, 0x7f3827d7647a7437, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x27627adb0a528a65, 0x3eef8f3466da6689, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x555bb78b55b06eb0, 0x423f61b20ef1aa6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x6dc677c24902d9e2, 0x7e97050c5f07bb88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x71bccb4c7912f883, 0x4d9aca0232383c20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x1e344bed4b2bd327, 0x444fa4bb442936b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #2", 0x0d6a9a5a4f05752e, 0x48842df540539e46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #2", 0x2fa3d73b41716d54, 0x4239457d4306b402, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #2", 0x0f4d8ab86670b76e, 0x278128394916ff5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x70c341d37230c79a, 0x2ff165e836b00594, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x47e1364a4438b50f, 0x45a1b003461ef95f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x0d3b8ef172c17eea, 0x2526b4e735a7ae0d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x6bd4776d2c2f8ee8, 0x67dfea2d7ef85a3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x775b620f0ba5bee9, 0x432190f40a08c35b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x5aab34180c95a71f, 0x4a5c61a104c5fc69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x4e0714736f4dd8a5, 0x47ccb06c0a4f0b53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x55be901303577099, 0x53660ab15d549f2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x7588383459a654c3, 0x1404a4c04681d1e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x1ddf09d231c7802d, 0x0ca0cb463d696e7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x2488ff175af106b8, 0x73111c8b2b1a98c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x072095a06d3483f6, 0x2a12f301105d7685, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x78da42df64c29b81, 0x1a6639e07e7bf7b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x715842a04b0ea485, 0x0341f419538576f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x3a5c7d2b313a8cfc, 0x5dd4824a3f5f5714, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x3491fd9530b89b00, 0x1cb3f640101b0d3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x0a5eefc3633daa6b, 0x569cdf252a1a35c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x15052a995a94c0d3, 0x6783a448283df995, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x3585c78c7d6b855a, 0x53589258398e29b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x6aa009506451da15, 0x49eba0353ca65d2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x491475973e6448f6, 0x3b2254dc637a4c2f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x0972ed7b14d44571, 0x36ffc3273a6cb837, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x460ed26d1680058b, 0x79cc0f4b43cf6aa6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x4738a08b2a87570a, 0x53ea77e57aa0d003, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x0dc501760c3eaa14, 0x24bb05cc5197904e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x66d36ae84d2e1c3c, 0x79d589e322ca2c0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x4a99a1962643f5f5, 0x5c5855bf1c593274, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #3", 0x0a95d00a1421e47d, 0x58ff8fa03539aae6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #3", 0x52862d734fb3ba3c, 0x18b3f71553aa45a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #3", 0x6487ffae07e30d24, 0x0e16fdd95bf91aee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x1e6312b073b2fd7a, 0x1fc885952a96d21b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x1e3a548449f2a7eb, 0x2537a21e659bb33b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x563151ff3108cd6d, 0x3733438a2bff55fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x7e36e9a92b21d7c9, 0x4ec982093d04bce7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x5165cdbe325d7efc, 0x595def5b48d08b3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x467f637916be2d3b, 0x7e0a36255bfb9dc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x6671e7773dbce143, 0x2fa5e36a190590ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x459fee6714c7316f, 0x74feabda4af9e725, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x087a2ee91ac85b5f, 0x7590b94164030117, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x64bb034a00d1f7dd, 0x499eb45326b4836e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x31dac54a217d5b72, 0x52b3d9683aec554a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x4c9f333b514f018d, 0x77f112313011aef4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x03ac808976ec7059, 0x78e23a331e0500f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x0daa9d9429a6822b, 0x7a009ec14a2be402, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x6763636e583020c8, 0x633174ee741c850b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x6cf7523834a72572, 0x3f166c312d0351d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x4f6f80d15aa50740, 0x110652ed75718121, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x5b76ff1d6ed9ddf8, 0x1c26048f342a841c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x1057396a6707eb97, 0x6f16d9660d51c468, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x3856ed243645ad8f, 0x3d63735c5cf66ca5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x2d321de874fc0c5f, 0x7afb6d9e3c036dad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x1ea28e8b6960c69d, 0x062f51af3adcbb7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x4190e7666e0facb9, 0x2ef940880605f1f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x22b6d22b440f96bd, 0x330943cf2e88399e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x1eb49dfd401fbf4f, 0x23f9babf722652fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x2ef99d471567b07e, 0x2650d7187a2b9d1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x7c6f9c1644e0d4df, 0x077d61833f50d6b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #16", 0x7b26826e1742b0f4, 0x1c47435634c6893a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #16", 0x0c3ebd5376f94897, 0x70c9f6e82858a057, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #16", 0x605a0f35122e9c5b, 0x63355bd32ae14bde, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x003e491463f081a7, 0x30e73dd821eaf69b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x28001864746ceaf8, 0x5073303922f51b3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x348caa473b6c4554, 0x151b6e3c46b4b662, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x50d3f5d3485db500, 0x40e0537d6386478e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x0d3e89df3f1e6195, 0x22d71e3f4d4391e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x5661128972d4120b, 0x020a1b2308650c4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x69cd5aa313f30878, 0x30bdaca4629fcfdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x2621a4d33e685993, 0x0d811bbb4a2769d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x2258db3b3c8590ac, 0x6c126073265fede8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x30f27ba45e707763, 0x495509274a58f39f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x19dcbcb851edfd7e, 0x110daa01657f25ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x1a4bb27e6bdc8bba, 0x49056d7a6ab0b28b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x2afaed4f39fe5f97, 0x37f44474278a3c5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x2cd271a360acf54f, 0x2fef48ab015bffd9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x749ffdc7717ceb71, 0x63fbcfb6169fcc46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x2fe545054cd99691, 0x60c7361e1ac1a29b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x095f273d0a7699aa, 0x41219083523e2040, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x68e7110e2da4bde1, 0x1c9713df3a51a2e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x7f92bb5f68d63648, 0x1fd0c8cd02c3cdc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x54b2c2022568c4c5, 0x6d74805119de6dde, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x5f67245c7157f2e6, 0x4168aa3b7fadaf51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x5204e83665057ee0, 0x0109af2a0c3995ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x56826a5203a09863, 0x22d9624546a4e5fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x507a2ef42288191b, 0x616688980667af57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x2cfeb2c6753ce376, 0x58a5cf9759d95631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x22e1a15733fbc1e0, 0x142af91315e5c3d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x1cd1f828061e11eb, 0x18a9919a22745cb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #29", 0x2b86d6b07dbb74d0, 0x3c52ca957184ba2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #29", 0x6f1367b7723c18a6, 0x7132697c0aedfb0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #29", 0x574197873a00f351, 0x1727910c41184fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x3da18bb56923be83, 0x07bd35ea2dc401d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x0babd79e0cd180c7, 0x342bb1300e1bbaa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x020e643d7c2009ee, 0x67f510db38aa8a64, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x301bcbce6739dfd2, 0x4e904e3824f00595, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x6d57f1bd03b72ce1, 0x4764624c4cedc3f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x0172a1b12fa4e79d, 0x3e727e2118dec86d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x21e100443af45486, 0x23ccc37a70860968, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x74f547d7395b8f40, 0x319e5955792297cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x227f4dc35b124ad4, 0x26e699a43296d38c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x67e3cb9b28a79f11, 0x40b28e362e2b2561, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x24c7a8ff3565fdfe, 0x66d5afc669f22fd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x1c9fddd1564697b9, 0x0ee2356d54e374cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x59fdc49a6043b6e6, 0x21d138c409f7cf8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x0fe89e8346a35b76, 0x22d697fc5b70664c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x0197affc7d94c90a, 0x4bf66fb431c99ec7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x36f0584a51d2d036, 0x2aec3692768cf7d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x2ce51b0a69d65996, 0x2923cb60596fa60d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x127df8a76e707b34, 0x079acb6e14c8e6a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x23d679330d9d4beb, 0x7ebb167e3745a1a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x63e3e3a52dfa4f38, 0x0c29167340765704, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x0e3e061e6d44be8e, 0x4a6e26923de1a83f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x33e81a0465487e40, 0x19520e8b1e26a4a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x62dd474a7adc79fb, 0x4ff04369357fca00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x4caf4a3255308d34, 0x2c0cc1d419cd9f94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x3f06e6ca7ad8110f, 0x733d45a17994653c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x69488c440d186260, 0x0e5d4be25184df71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x1ab5ae4b14f3978a, 0x08ca81170d1f0577, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #42", 0x42ede6c21803830d, 0x4d955c7b7e9991f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #42", 0x0548419c55cd48bb, 0x3c7b3a30512bece0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #42", 0x3b15c6fb3f42d4eb, 0x6f52918239305ba0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x3a1f4ee61abce775, 0x6eb025a11df30e45, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x6fed74a92afdf37a, 0x37c0add906ce9918, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x25d6048a0ec04a37, 0x0062fe552ef45b73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x1bd8ac970943bbfb, 0x00793ae40f1e90ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x1e37538569d2f2c0, 0x1c3d9645368e5ae2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x01d675cd71a32703, 0x3527ecd361253a48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x47706fbe21a3b8aa, 0x32512728071eb769, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x60e68d952eff38ab, 0x404f130a028636ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x49bc20205839f2d9, 0x207944ff1b05dc7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x0337e653223773e9, 0x21d4759439a994c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x30f7be2069172b20, 0x689df03c290deadd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x725ae71b546a11f0, 0x382c7bab4cd06ab7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x3e3d04b03886b26d, 0x035ec59a10923aa0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x2a29d97024089c11, 0x71b774e840137a7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x45ac54bb078144f1, 0x473231e7719a492e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x36807d9c1499c4e8, 0x74207fe82692e251, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x6cd3b7c1636d3461, 0x4198becd003c9dbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x05a4a84b228422c1, 0x39e63285700b9e14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x0b9b4de15146049d, 0x191988f2369c666b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x25b0168e06cb96bd, 0x036cd1237df634fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x3f52492a003fe485, 0x0e886f9d63ed1b3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x244880966b32c7a4, 0x240095bc697c229a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x72b40c954f36ebb1, 0x5b166bc869f4d552, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x63d0b09952207670, 0x1087b7a329348a32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x358daad163575a74, 0x297127ee50a4685a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x05db7d3559c98f60, 0x40b0066e3b32531c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x2b0f93fe753b8aab, 0x71ceb9881176cb17, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #55", 0x7c0721681df56fb0, 0x0f6d001350bfaa8c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #55", 0x1e35543658ad5b87, 0x34acc5ca3b596a92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #55", 0x43e0232b7febf8f4, 0x24d58d2c427dd4cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x4f22e4a53cfa61c1, 0x2c72aa1e36942fc0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x0f1ad8310939e1e1, 0x5fc8b9f232f3953e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x6c913c5544480407, 0x0397fd9844a88303, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x1e11936771a98fa7, 0x7fdad61f726cb98a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x66e51a52135084b5, 0x03e384a149212765, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x3145f4654e8d97bc, 0x19e0d1f162ec3bba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x273af343431b3378, 0x1e45a64c4f7b489b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x43072c6d3e6bc786, 0x11f91d686b1b166e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x7b66294801780021, 0x21af462e122a1112, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x0ab1e20248b5a3e9, 0x451da6510a810179, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x0cfda7f04f045a9c, 0x4f29847c77431e57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x40adea436d935c83, 0x69afd7e12b0f3b58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x00e3e1380e1134af, 0x743062bd27930496, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x5c9ecc6b28c4e69d, 0x0a7f40503229d59d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x6be01a15139e3ba1, 0x01a51e3903d9bfae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x520a032710a41c4a, 0x6ef4d61c2ee74682, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x121c1c6b062efde6, 0x411157954d702c6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x4ee4a1cf271ab265, 0x57f12de91ccdfe6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x761f0d017dc0f4a6, 0x14111cc45be249c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x6b5451297b21e7d5, 0x06f1851836ccf745, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x09331c8468df3c2b, 0x5e5ffbdb6c383261, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x11a422c820072637, 0x1e6207fe65d1e8ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x33a561d858a07eb9, 0x69aba89d7d843cde, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x69449b046d7cdaf5, 0x2c6b836005af6500, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x73abd8db2b10bf58, 0x531f916f7b60b76f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x522b71be2c3fd2a1, 0x182eb5dd42907aab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x2a00c74725644983, 0x1e72c46b484a7ebf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #60", 0x208631585d7771df, 0x7f17760415551870, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #60", 0x4656ae0b1fef52d0, 0x018d4ad129b94ddd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #60", 0x3ff679077936df6a, 0x0f8b36cc57fad0d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x51d75e2301ea9112, 0x557f0db1739bdae0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x6f676c074c6ad14f, 0x794b3fe03b1bf927, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x777b90a84eab6674, 0x367cb097631344e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x7aeb3915441683f9, 0x25a3bf8e49a70266, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x697acd7c1108f72a, 0x11f1812524ec005d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x6e8069093bce639f, 0x3a4118cd0a00fed4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x5bbdb66f4345837e, 0x33ba4cb134d71714, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x3c7c62e86250f599, 0x0cd1e7e81bb42f76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x643b86ab089b4a36, 0x0f500a560e53c10b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x55061b867fec6aca, 0x496fba3353a2f2b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x4e97d13e5c59f724, 0x36b637964c81ac2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x20707b1d281a2fb9, 0x1628ae9449830a53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x392326e328b0237e, 0x6e6f0ab009eb4899, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x647e871d47a6941f, 0x13ec476d27a38fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x0aec179d694c8ee9, 0x5c7aa701403c3d8c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x4b9d84836b407759, 0x5bf06d0247687a85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x73dbc18f1f2bf5c3, 0x55bc3b902fd90b2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x1f18608d3a323577, 0x037bfde148e1dd15, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x168c2c9b2b8c37d7, 0x156389436db031cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x53a6679125a246cf, 0x37333c1f36fca7b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x4e526a4d54d437bf, 0x40e7f0510cc98e74, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x1c7acbde10e7c563, 0x346d1e6132d0f16a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x7a34544c4efd9bf9, 0x730d2ef62766e37b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x3a3e1352448b9990, 0x6ecf5e0045d1d8cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x63b78f547926e1df, 0x75aae3fe2e19d4e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x335917570c5f3b3a, 0x76fbb1f702cfefe1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x37eb731227b35dcc, 0x708021ad49e543f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #61", 0x4d55a49b41c9dbfc, 0x00e1ebab0b91daa3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #61", 0x169e13bb4cc88779, 0x185b69171ba80ee9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #61", 0x5db04cdc41862f4a, 0x4e7900533318df99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x1083cb43494f2114, 0x5a7fc31457e4a128, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x0ddabaa513615df6, 0x1db679f84ac1de95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x0c883fd56fd7656d, 0x78dbb376719249f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x7c36a0a864e25b87, 0x746239da3fe1572c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x0c95b9530aa886ca, 0x09c69b1f342213ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x4c7262c6580f5774, 0x3fb3ee5d59eb5def, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x24d7deed440c6d2b, 0x75936cd863107682, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x05929c7570a91930, 0x1629561b02882bc9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x39f83a44782346ea, 0x5a6cccf2161667b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x0b84a4e059b3f9c4, 0x60d8464d47d2f4e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x498b5f312dc778bd, 0x39653ee2180ce4b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x12a9d44461b4d701, 0x57ee3be245c1ffd9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x6c5d5dcb399801f0, 0x79e413931f3f8d98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x11a759656ebe585f, 0x792aeb8738cfc091, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x32cac58a32098d2f, 0x1be03713367f3852, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x22b2a65f1374310e, 0x3907641c385d6200, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x0b9777f82f4c1006, 0x4e73c9b85caae0a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x090009ca5de3146f, 0x247dd58d171c1cd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x0baa8d2c07173d6f, 0x2f29018d528b68fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x68cc147012317c68, 0x184d68d51e546171, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x4bc97e5936beda90, 0x3d93ef095529723b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x257d32ef29d969e0, 0x0df932cd5d70d7be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x5be2f70f4cf7742c, 0x13f010105847f879, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x606ba53a5f192432, 0x10a55a797e959d6e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x0e6534387fbe539f, 0x5b407e126c031d32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x5da1680e32483b98, 0x031f3a0a17653e02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x395f7907023e0fd2, 0x69f0a6fd694bf53b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #62", 0x146f8c3b453445b5, 0x07a056ac222b8d78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #62", 0x7bf32045054e3280, 0x7754ffb360390a94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #62", 0x2f279c615199f262, 0x3da9e25221705334, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x1e91668f0a5da627, 0x79b84bad0b0a9370, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x6976ca5964e0aef1, 0x09a030df7efd0bc9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x649f02906e1f6306, 0x6b0028fc77dbfe91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x20679e9e7931e390, 0x0f413c9342406a9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x7b6ff363332cb685, 0x2b8c5fd959c717a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x7860fc3a7347a4d1, 0x7bf2a51e0fdf7f9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x7895d7522dc26c84, 0x70188a3274541c7f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x7f5c5ee60f7cbb61, 0x15c46fb327bd73b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x19da61883c683802, 0x32c807231dedc575, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x2148e6f307eafa3b, 0x1cead13f03512be1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x760a5d410a6e6705, 0x7b2d2a7205e7e983, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x03a04a9573b4b3fb, 0x482854221671fbe0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x26e16a816c2bb8a4, 0x703913867f103df8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x5f735d757f0847c8, 0x0eefbd961f4266bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x2ccab44c295af2ee, 0x1396833b580934c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x38d7ae4f328eaf9e, 0x7fc6a87a2c271333, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x6ef6e7a066ffa9e7, 0x4a14d8a852b20fd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x6eeaa4225130662a, 0x56033bb8103fce94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x5b9ecd2f5e500c39, 0x1627b81764f50164, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x5204c0356ba010ca, 0x7b66fd445f3f17c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x57cbc96e6d3f1354, 0x5e4f55bd78e62ab6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x6c475b1c2bbf14ac, 0x18289171373f26e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x551a079b0f0f0425, 0x0f485bab19120f69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x419db3c30f4dfb44, 0x4539229c0df1b5ea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x764da52c36a7017a, 0x60a3c5c230949b64, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x07d767a556fc220f, 0x40d469f86538494e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x354c2e49459447f6, 0x4a2d4ab2637634d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #62, #63", 0x313458c02104a257, 0x42b54c990750ee7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #62, #63", 0x0e43b5ab185faaa5, 0x003719340900222e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #62, #63", 0x441ebf524f87a4bd, 0x403f49127a8b10c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x5e96a8e258d642cc, 0x139d20301938c6ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x68243e1107ce4299, 0x272a7cd720345ca6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x3e754414119d6202, 0x50c8f80a5e71e33d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x689984110dd7773e, 0x43aa2c8b464cabb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x536bbf346c782d27, 0x29c2e08d1de5b25a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x0d7ccf7e256dba0c, 0x2536a0d804a017f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x3dcd64b24ddf8335, 0x0da03a231bc08529, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x1d6727f229e8b621, 0x164b95f001ec2404, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x02bef8ed424f67c8, 0x1b24eaf17bfdd0d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x4a1daa626cfb2585, 0x1c322d7b6ae336fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x7e9887870cff46c7, 0x49551a3b0892ee76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x1ad6be0578a27abc, 0x4edf9a2f67320b98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x651aa7e32a4e5ecb, 0x0517bdf36e427d39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x4fbc18d80082cf52, 0x72e2952e72977761, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x4e62528724a3927b, 0x0e57fc8a0d897d8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x4e8c489c2a9a8c7f, 0x0f75a18e6bc97a7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x6ce9f44703f978ca, 0x67c74b4f514b4189, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x70f49e4f058392c3, 0x3c2e788837079ea9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x1282d98a0e7a274e, 0x3f9a8d1f6f8d25d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x071ca20b5bd6ef61, 0x56bf316e2d59978f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x06254e2d0e7ea9f7, 0x1b9c14c96c3749ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x0f0179496d26bdda, 0x5ecec15055e16705, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x11ca505572e0861d, 0x636ae48f5d63cbd1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x1d7b129c30f4919a, 0x492d464b605698f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x34ee0a646dd05303, 0x31a1da7b0a6506e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x7353e5c6010732ac, 0x416ca58d25e2a8b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x0f8159fb6c2efff7, 0x156fce8905d6bf51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #0", 0x4805ef594ecc6ba9, 0x333056e0169dfc06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #0", 0x5d4b15a161a40744, 0x02d545f44e2b3d86, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #0", 0x4ecac51f0777891a, 0x240ca48b6c4c8eea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x7a580f3712dda106, 0x49b05abb60951574, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x43d232a0728d88e1, 0x40ebae6617d321d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x605ddbe463a4ce43, 0x223828b678c03d04, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x64ac00f03412b440, 0x1ea2e5b753b1c1aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x2041b4380cb8d7dc, 0x598880fb742d5aeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x5b8543850da09ce5, 0x0acb56f16847a391, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x6f44a42a5a7f85a2, 0x3672e11738d05926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x61f70ebc6ecd42cc, 0x251ce8113e0f6949, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x01aae3d35f902d23, 0x1ea47ebd5c4f1df3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x521db604165a687c, 0x74223fc6457d1673, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x79ff36c05ce0392f, 0x3e3d5378327b91e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x10f2ed705fb5d48e, 0x062d53935eab37b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x6c6eac6a5da3e98c, 0x52d8929b3134a1a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x6b4486714fef2650, 0x197c453947f3eff0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x2a6eabf225e13127, 0x00c449165a892a9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x14ae73f4373d12a2, 0x189893e40c65baae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x16cd3fc55cd71867, 0x68b4d8a1165957c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x733180e31a13c1b2, 0x5bd66e3a68eaf5ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x76f3fae22193db45, 0x1b6687b26d30b7a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x0149afd41eb481ee, 0x4bdbef5307e6e852, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x7c586b7a5297cf33, 0x391b89fa6db85c3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x2286f58336709545, 0x35ac4c2e679cf1ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x5c51c66c5abeb06c, 0x42261c874cf5a175, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x11fbc30e421034c4, 0x595b5c2371003a60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x1ee74d2b63300062, 0x0759922728c902d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x7d43c2142d1a8050, 0x11b3f89d1218ce0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x4eae5b954b257505, 0x7f4985b27437bcf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #1", 0x69d9f6f4353a2f42, 0x7c1ea5484ff80b69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #1", 0x07d1fe75735cb3d6, 0x3db067a86632626e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #1", 0x29cd491b0ff570e2, 0x4dcf545a2a58f3f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x6ab4214e50a9f190, 0x774e956d061f0f88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x12ba26547e78dc10, 0x771f49e87cafe45c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x61a8dc72372cdfcd, 0x2578e72f31a1737f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x6447601d4303c740, 0x43ba418e5eec9e86, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x0e293c454f4300c5, 0x53245b7d32f5bbb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x047d3008409e2ec4, 0x02edc71c78033339, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x33fae29a2c04ea02, 0x5e3595a80c4f2e7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x3bfa5ae42df6b7e3, 0x36a822765dc82bb6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x7ea0a9745b068526, 0x63e73b3e26ae7c32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x597f613648d747be, 0x235e608e115acfc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x0004278b06b684d6, 0x42fc43483b283da8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x49ba4c166d3937ac, 0x1a14dc2f644b87a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x3c7c38711a2f0a76, 0x1741435a57e3885b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x5acd393a2e1c513d, 0x4fe6bb9540f96879, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x5a213b3f03f0b96d, 0x4d4896f70ec81bd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x31e77150507782c9, 0x6c90478b161b9624, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x2b7e07ef602872e5, 0x3cca125630881ac4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x28ffbaa304df2dd5, 0x41e2ea8d04fd6926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x0b95b2ab5a3a82fd, 0x4025a6ce2903e22e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x4773baa92490ad30, 0x0d4f69d6554ffec1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x3ebfb7a77d1a42b1, 0x2d33871c03eff31b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x2b3693ee1231f28b, 0x44e95b94198cf0e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x1622abf814e55441, 0x28550cb60557cf2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x655cd70a583d77a8, 0x1b736552480a1d49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x3865ea8d3a75229a, 0x7892380d10dadefa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x3f54506f55fdeeee, 0x15d848206165a530, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x303871ec17b8f134, 0x0a69875e4aea031a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #2", 0x3c499e654d6d88f8, 0x203a01db77ac2c95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #2", 0x4a87cba940857b45, 0x7b9c1fb07b09560c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #2", 0x52b76dd03ceb53a4, 0x149646ed75be5f98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x51d0a7e516899418, 0x7b162ec668da19c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x6ec70bc029766f1f, 0x30e43712372d7ef0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x63eb91ba5de0a60a, 0x48085dea272cf64e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x33de94f812fc22dd, 0x08929b7e233fe229, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x2ab514110e63e71f, 0x6e29e544641706e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x5bd17017575f532a, 0x5bc3337a66feb276, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x17e4ce6f769e4f70, 0x6208088226593bc1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x3389a314172dca1f, 0x1c179b596a9c3c40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x2db75e37045a8d1b, 0x53765609055a4af9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x2dd0fc3a049027d3, 0x3c87c9e91c7e69f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x6270cddd4c3dfbc4, 0x43ab604511bc8df4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x5f3a1ea123265562, 0x34fc701e164f62d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x318a3c8156299d34, 0x7a6669ba09ef32b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x2d88f05f52f5edab, 0x70ede5290d5bac99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x49943d1b4fcc83b3, 0x33b4e85a456dbece, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x66fa4dd203805117, 0x3009fb0e7d1de02f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x07dade323efff512, 0x02782b2914b1ac09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x43901ce674db7646, 0x3130160035abda6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x4119720a7c64d87f, 0x476868612600eac3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x1f8b2de136b6b754, 0x3c504d99205390ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x0ce054881b30a886, 0x2a42c35d51156a63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x6e2696321225ff56, 0x5e7116fc3a6944e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x61f283092fe0fec4, 0x7fd703b637bad34d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x33614fdc3750dea6, 0x34d8b37d48ecd0db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x7650d3b80ece92e4, 0x5d9e7ce43b3c2e0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x03aa092a385070dd, 0x70e8087b39e0f09e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x34b5495c1c3228fb, 0x5fe1db6244c37b34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #3", 0x52e8e04f0f59cf3d, 0x65170bdf5440773e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #3", 0x2a8a77c303c6f89d, 0x2555e1a15fc934d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #3", 0x15ecf7f31a097d75, 0x1a3279bf18b10df5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x49ea7c3a054494c0, 0x506be14377df7afc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x3c9573661e6ac8bb, 0x40cc4bd77d4bcc16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x2d395b9f297002a0, 0x3887fa2432e6471e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x61c0737d4ca9131f, 0x6cc737bd30e364ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x68db3c1a5abdebde, 0x75a6dffe1675bcd9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x6a17bb1b100c15b8, 0x6ab634173bc41c6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x13d30e5535bfcb01, 0x1b8d514214a232de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x4fc948777dbf2217, 0x2d5340d429c00648, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x0303b6d7626bcd1b, 0x219f814419b3c4b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x00d695d64f878aeb, 0x16ff90c73f992a3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x78f78d8b5f46a918, 0x727f715b2e0ff176, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x2befbc37549a363e, 0x5ef356405ab80108, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x2f58221c5be3f1f9, 0x712dbde214caf852, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x6bf007b26c1c65fe, 0x508f14bc196fdd37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x21dc30ff5b6550ea, 0x2e1210167fc31607, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x592473014b229d94, 0x29831c5071a57976, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x2d8e6ab02258ceee, 0x0b593e275c2829d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x71e059da0e40c570, 0x1bc154152e650086, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x6d876e893b68483c, 0x5c74f1fc6ad7e765, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x10027e7b36bda650, 0x458fe86e19772ac0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x12a198497ed137ce, 0x2e4223123f5aa097, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x6aed9dcc06dc8de5, 0x58ca7dcf7e919ffb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x6241decf27d7d253, 0x7e54b6030cc9cecc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x72fa6fe709c8866a, 0x7e6f48423b6651d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x2c215558334fcfbd, 0x178e7ba82088da97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x4190952d2b62cd1a, 0x4eeddb1e1e01af32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x66cb15574e697f06, 0x08d996982f1803b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #16", 0x0527255676d15189, 0x488f2e7776cd93d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #16", 0x75a289580ef2b238, 0x3628346917c8bd9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #16", 0x15cf401d14af139e, 0x165a5d9b60902724, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x3c86e5f16bc93e33, 0x6d59f5f078111eec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x7591c49d4b05ec64, 0x337770bc2f8155d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x7e55bc211ef80b8e, 0x500a307021b319f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x4a5ad8a8488e5fc0, 0x3fb4c9283fe6514f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x16f7dec6378d837c, 0x6efe55053125edff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x2e5ed5065e1bb63b, 0x27f381d11c1f041c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x6d0e68734a421f56, 0x33e7c1bb24015e5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x5ef132f471eb7b73, 0x0491858202dda891, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x5db4b9a62e66383a, 0x7aeec77d1b7818e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x796c249e1b039f2e, 0x4af96ebe53467e43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x39fbaabc34ae6160, 0x74f9983877c1e0c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x7d3cc12026a68714, 0x37a8320f04568364, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x5e340a915d6ff335, 0x357c716414349fe6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x3b8ba970643b65be, 0x3053a4020c92df97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x2e7d85143525c377, 0x30943df5289a11e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x27113eea266681f2, 0x2b77ba750d6eb809, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x54ccba2c73e03fac, 0x28e6d0ee04c5f890, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x0ee3deda4d060f0c, 0x580c76d34e38decb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x01b4706c7da2f19a, 0x45fabf8b48df8996, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x244978ae02b27e5f, 0x4d360cfb7ef1318d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x6022719443797576, 0x1325d173027d833f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x27b4db343fa4a0cb, 0x0f1062d61bae1b05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x74ca64436fbfe75e, 0x44482ce956326048, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x162669500c87e940, 0x63a118511bdba32d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x006828ec78ae1291, 0x20a19bbe6af3237d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x45b4219d7f26c1d3, 0x392c02480f4c07c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x7cc9b36d25619e58, 0x582b915d4768920a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #29", 0x28141cb7597f950a, 0x4659c39721132c1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #29", 0x1cf90a8032a11231, 0x2390af5b08368e4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #29", 0x7245b2fd682cd63a, 0x23e4a95144ade5b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x57ecbd987e815e4e, 0x1ae045fd67101740, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x0b09478e238d562b, 0x02ebba6d6e1326e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x1c3b68bd12324cad, 0x59064a650b71707b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x11590e8072e9099f, 0x1abd784261ef8a5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x184aa7f86fb1dffb, 0x29581c640e22c1ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x4931750652c69d64, 0x2f35ee09405ec4af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x0567af956c79fc4c, 0x489552fb662a7f86, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x54a6d28645b8ab38, 0x2ad8653b77ad6292, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x443a098661a93440, 0x5ebd79d22c93901e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x05368a6b73ad016c, 0x1aa6b7074f435115, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x05df4e1a757239d2, 0x5ab4c1902171f328, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x685b43712cb999e7, 0x03617d8317385c9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x1c6b79e354910c91, 0x255b1e8800a5eb69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x2757a9f5099a0314, 0x4104b019659ceee9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x7613ff61769fd3aa, 0x4bc76e6f2cbf598a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x3c587ee2032a35ef, 0x246cbc1d4abad1e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x64d36a2f11f5190d, 0x774e620600928869, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x05a21a792a8a9b0e, 0x4fd5d97e6a09f49b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x1ffcd4e00edd6546, 0x0b7be7c30b816893, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x3b96ff2e4814e3b6, 0x22b9c52e08581851, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x1ca5f0474a02b3d4, 0x08fe03bb58027911, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x539cb6e80966d669, 0x3d9f67fa43fd9a3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x0006aa141529afe3, 0x70bcf3c649b0b649, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x1853e5d30bb9ea37, 0x146b88313c5f28f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x1daf03440cc78add, 0x3cf1b15f7d275002, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x375225eb72ad2c61, 0x6731449d23511dbd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x018a91a7518c4b7f, 0x2ed28651574efacb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #42", 0x19a12f3568a516d8, 0x5fa7131d3d2190d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #42", 0x32a7caac52c371e0, 0x152409e636471f7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #42", 0x5c2a484a6b01ad7e, 0x7a44b9b806448194, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x002b5d626460c00f, 0x4ff537de5c30f25e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x701aaa465581ccb4, 0x18901b54187f4335, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x624957917cd7d7d5, 0x15a693370dc9ad8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x6f8504365fed5198, 0x311acb47199b7d7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x31799d1750918b65, 0x70ea7848710f95dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x3936a23d43553099, 0x2e3126b34b1acc4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x1618a27a7ba6a580, 0x0161ebc86bde6ce9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x66a852ff4218265c, 0x7222ee7e7242eac4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x2678e66b6703f876, 0x4e73dd2266d3b061, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x3c85c52a14f986cd, 0x7f52f396169390b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x11d15ea255780982, 0x245d3e3b1ecf1cbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x35655b1b29551281, 0x386a9a39015662d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x79e69de720971f69, 0x7265f8b666def832, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x63ec5002335bb047, 0x31f9c47f331d4024, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x2f0255c8111e9b8c, 0x1efbad0e7a04f27c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x5336c1e83abbba62, 0x6c47dd4015aaa8c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x21bfb2d97bd14cbe, 0x7c7e592879afa853, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x10cad38b34a0773f, 0x104339045e457803, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x0a1880c1357f2ef8, 0x7d1494bf229c322e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x5ed4417a16588dbc, 0x23f295063f7ddbdc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x36efad255856988e, 0x265cd40f58badf61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x0bb248d52ad3cc93, 0x0bd81f851adbfd28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x3bf2681f0128cce5, 0x14e0efa43ab49e9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x3be487474cdda08c, 0x505f47640f292a07, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x48aeed4a191c0b5e, 0x08d8d25a5da43a20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x4dbc829d38fe46e3, 0x3be9b2245979c0d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x6e7d75dc2008880a, 0x7c15f30457d5035f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #55", 0x366115c73dafb34a, 0x1752df3b4d51b756, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #55", 0x16064bd831e4b63c, 0x260c96b76d50c2ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #55", 0x5cb882d01d0dafb9, 0x082cc01421b894ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x1e367c9e2ccc7ab0, 0x5c6d334b18aaeaef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x79aa1b3c30ace751, 0x27d414f75a1b03e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x49c8f2b073a8f02a, 0x37bf3e0642590887, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x2ca7370d17e8bc61, 0x1bd2c95d1785754d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x37f1446b06ad57e8, 0x6f5a78ac1b24ace9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x445d0b320e82faf6, 0x6876643f6e525a32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x4067b13363cfdd33, 0x5ba31d1f5a63570b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x00dd8cec58891f04, 0x7c1bebb91d203403, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x055599b45d9f33e9, 0x35cb1ef21f14098a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x0e4c1b3b30ee4b76, 0x792f0d707effb4f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x24973ba05d2b86d5, 0x4158bd7858150deb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x751443365ef4fbe5, 0x6f9a8338513e72ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x65a253cd54d983d6, 0x6c631f972d0587a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x635c7ecd76fafef3, 0x1b57e1d429ff5eff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x5acadc26007ea1c3, 0x0462b60a23c43000, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x5907c0c876af82f5, 0x40e464035ba86913, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x544eb6df73eb800d, 0x7abc729d5e5d5a7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x24d9cb831eb5cce5, 0x5d5d0f6d629ad21a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x7be153ba2a4a633d, 0x3aafe00549710723, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x093f5f2207129968, 0x1aaf79d170f596f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x5bec1d3e39530066, 0x1dfb1e926ee1b2ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x304dff591d43c7f9, 0x18e111ef3f489c0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x1dc269bd23f1300e, 0x630ccc0b0b18db7f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x1aa0b304617db730, 0x66c1449276ca2a85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x5569373d3284946f, 0x552785016eef69e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x513a61540c3a1c02, 0x518a3bfd7a4302c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x36847f3f5e6383b5, 0x43b409e44d1bb50f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #60", 0x65761d1d5c0c6a91, 0x3e114bff3fc3de62, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #60", 0x155f6af74786a340, 0x2ea5915141623a5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #60", 0x64ca6b3a63b7a273, 0x00aad66745ad6a50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x07a8d28137878a62, 0x50c645d0028cd4f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x190541924e7e847d, 0x7956ff7c22498585, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x010318ec62c32b65, 0x1138ef686e6e78d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x6efd47672c658575, 0x68b17b91523d7a41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x0ac9092b5d6a7b4f, 0x1f592f502581c6a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x3976e5e113eb365a, 0x6545a509703f2648, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x5b71d99b324c370c, 0x31a160a44ed650d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x1603d97f654a00f9, 0x1483bb29403c44d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x1cd18b5b3c201948, 0x42c919cc1dacac00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x0a9e9dc5512f20ee, 0x3ff6318635d6ccee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x33f24c540cf6c14f, 0x244545be0ba1b6b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x395c46c47d386043, 0x5ddf30f322ef93bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x5aa2db922db6ff6b, 0x48715a6244254fef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x41a235c66605d6dc, 0x346476381419c173, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x18520de87773cd75, 0x62f0124c1d140f61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x5cbdce6e20196e02, 0x5d5054362e55e767, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x5c39874a0bf8c4ee, 0x4c029368798f59c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x5d27e5dc53ab6c75, 0x2f6626b766d8250f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x60a22dc450590cb4, 0x7279dbc1111a3230, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x4d916cf77c7b204e, 0x3409c5ec19fe7489, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x2a321fba12883ab0, 0x5e23c4782834488a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x788e118d1f3e1c49, 0x3c4e09fd6bd45580, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x16b1e9be6638b917, 0x08e864e110e01f75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x065227190b389a45, 0x3f3606dd736fb82c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x17315f331c6538ad, 0x6cff11f6628bae63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x7010a5233bddaf34, 0x4963d3727459450f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x0c36bbe8397d3d2c, 0x0573774050b2d2e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #61", 0x35f85d7a48d50be9, 0x6ab1477059c828e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #61", 0x5b5d46993e4a7b67, 0x01fc716a602a7d34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #61", 0x5d8897b154e73795, 0x4bfed2b453eb5826, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x3b1ff0ac24017e79, 0x64cb779c743a816f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x2f3a18be54a94b92, 0x67aa399c417217c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x710e843f6d61999b, 0x23fdc628466b77f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x293f48cf40383440, 0x3ac4bd00611f2962, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x79b5716c1c8343ba, 0x31d1fc4a357604b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x65584fa3113a9f01, 0x0f3e2d972fadcee7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x4f851a695bd71ed0, 0x0fd84c1b40b5963d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x30be5665796c65ff, 0x14a0ee632d0db21a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x1d6de47808f26d25, 0x214833896bde4712, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x5d9bb8b7514e2500, 0x2d505ed74ca7fd36, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x3eafbe9b4dd83228, 0x131375274eaa3cf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x0e106668619b62a3, 0x2fc9665967ef076a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x7e1ea65e2ca339b9, 0x1d650c2107c5d7d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x3dddd8ba474bf2d7, 0x3773a6bc6376f601, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x232311a738cd7aa2, 0x242c8c3e0d62f323, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x3239e0a15bb8d8c7, 0x3a70a53d53e1680d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x64ab45ec6d100df6, 0x3fbfaf1f4fa7c51a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x3e5e32f62f633778, 0x1c4fc2504246fea4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x7d3b69a040baa1f4, 0x10f13b9b7d0df191, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x225604980262051d, 0x64fcf8fb0b4bd008, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x2f053ed64a854e99, 0x1311a7dd2074aaf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x11d1417128182d36, 0x03eba0f76ce31790, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x60e5a7d834b6aff1, 0x7a460ab434f45318, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x106f88b848956a44, 0x08d5bb25131f8879, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x35a5783b7f170fe4, 0x62c74d93751acea5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x2e7a475c485308e4, 0x3761cd497403ab31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x090daad8560e95be, 0x71119cc32bb5b0fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #62", 0x58709adb4a1328e2, 0x370181042b63af70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #62", 0x1498777b4fc3fb5e, 0x4bd85a660775d9b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #62", 0x77dc28946e9efbf6, 0x7458f1422669b8ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x2355abe76433c72a, 0x5b5e0c0558c1d06c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x2cc9316f4ea8a679, 0x6be158e533c534a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x4dbfb65d6041d08e, 0x28e00345626ea9aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x2894d9724783f19e, 0x567254db7c39fdb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x1d92875d5ef12fb9, 0x27efaeb531a2844a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x2904589b28de8e21, 0x5d0633bb76032238, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x78a2897f71d1ed2c, 0x7d78fbea3d9cd017, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x6070e9223f649508, 0x64068903707eb213, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x23985c333521db65, 0x4940827f03c69509, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x03ca81de606bccee, 0x378bc9a950618da2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x40ad9d7c09428c27, 0x32d0374c518a383b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x50c67dc675b3e4a9, 0x4dc435f4694276ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x54a5146277eb2ef4, 0x1ae4fb396e590523, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x20c9bd1561d52345, 0x645c275b7da96cfe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x53a710711f4cc618, 0x3b463d15196c4695, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x5eb15b21532b7b28, 0x09eaf8a83417f993, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x084d568d6f6a5846, 0x37de8e9d0249b754, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x4fd62535057b7c42, 0x52ab44f60c17d86b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x0ebe08692b66469a, 0x5da210a61083c2b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x211a2b4314ab34d9, 0x79c639a05f84862f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x0c9663cd3239b2ae, 0x4ddd8b5275bf3fa5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x140ed5f32eaee9b8, 0x7368aca32d6020e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x4dfbafd150b76020, 0x46cc677767b5e665, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x23e2db4853ac6e95, 0x1bcddff82cad0af2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x4316c6dc01a2073c, 0x2ef6c2462c3031d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x071d837e15ea1ae6, 0x38480a4012ecec11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x415061801d36e862, 0x2370aec215db8be7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm x3, x4, #63, #63", 0x31e21d3b433d9d69, 0x75601217626a8cc3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm x3, x4, #63, #63", 0x757750174b92790c, 0x5829cc683e788108, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm x3, x4, #63, #63", 0x7a4162c432a50962, 0x6bd8a1eb0986260b, x3, x4, x5, 0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("UBFM(32)\n"); -+printf("SBFM(32)\n"); -+printf("BFM(32)\n"); -+ -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x643c986966334873, 0x6b8b4567327b23c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x2ae8944a625558ec, 0x74b0dc5119495cff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x3d1b58ba507ed7ab, 0x238e1f2946e87ccd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x79e2a9e37545e146, 0x2eb141f241b71efb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x122008544db127f8, 0x515f007c5bd062c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x1190cde766ef438d, 0x0216231b1f16e9e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x109cf92e0ded7263, 0x140e0f763352255a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x41a7c4c96b68079a, 0x7fdcc2331befd79f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x519b500d431bd7b7, 0x4e6afb6625e45d32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x257130a362bbd95a, 0x3f2dba317c83e458, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x333ab105721da317, 0x436c6125628c895d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x6763845e75a2a8d4, 0x2443a8582d1d5ae9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x4353d0cd0b03e0c6, 0x08edbdab79838cb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x71f324542ca88611, 0x189a769b54e49eb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x3a95f87408138641, 0x0836c40e02901d82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x737b8ddc6ceaf087, 0x1e7ff5217c3dbd3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x3006c83e614fd4a1, 0x22221a704516dde9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x440badfc05072367, 0x419ac2415577f8e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x7724c67e5c482a97, 0x3804823e77465f01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x51ead36b2d517796, 0x2463b9ea5e884adc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x3855585c70a64e2a, 0x580bd78f153ea438, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x1d4ed43b725a06fb, 0x6a2342ec2a487cb0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x7a6d8d3c4b588f54, 0x2cd89a3257e4ccaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x38437fdb7644a45c, 0x542289ec6de91b18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x579478fe749abb43, 0x32fff902684a481a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x79a1deaa75c6c33a, 0x3dc240fb1ba026fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x520eedd1374a3fe6, 0x12e685fb70c6a529, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #0", 0x649bb77c275ac794, 0x4f4ef00523f9c13c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #0", 0x180115be235ba861, 0x393865751cf10fd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #0", 0x15b5af5c741226bb, 0x47398c89354fe9f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x3f6ab60f61574095, 0x0d34b6a810233c99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x579be4f1310c50b3, 0x7e0c57b177ae35eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x25a70bf71dbabf00, 0x5ff87e052f305def, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x1381823a5db70ae5, 0x4ad084e91f48eaa1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x15014acb5f5e7fd0, 0x100f8fca6590700b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x06b9476442c296bd, 0x098a3148799d0247, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x661e3f1e5dc79ea8, 0x168e121f1eba5d23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x51d9c564613efdc5, 0x540a471c7bd3ee7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x42963e5a0a0382c5, 0x0bf72b1411447b73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x3b0fd37968eb2f63, 0x08f2b15e1a32234b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x06a5ee6414330624, 0x4962813b60b6df70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x71ea1109100f59dc, 0x7fffca111a27709e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x6f6dd9ac094211f2, 0x7fb7e0aa06eb5bd4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x4c04a8af1716703b, 0x00885e1b76272110, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x74de0ee368ebc550, 0x14e17e333222e7cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x4a2ac31539ee015c, 0x2df6d64846b7d447, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x43f1842260ef0119, 0x57fc4fbb0cc1016f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x49da307d7055a5f5, 0x26f324ba7f01579b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x0488ac1a5fb8011c, 0x5fb8370b50801ee1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x6fc75af86a5f7029, 0x6aa78f7f7672bd23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x73a1821b7de67713, 0x7d5e18f85f3534a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x14fce74e6a3dd3e8, 0x555c55b53fa62aca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x532999381fbfe8e0, 0x71c9129809daf632, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x59adea3d288f1a34, 0x5092ca791d545c4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x097e1b4e51088277, 0x2a155dbc1d9f6e5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x415e286c7c58fd05, 0x1ca0c5fa53584bcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x5c10fe210e7ffa2b, 0x23d86aac45e6d486, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #1", 0x78df6a5539b7aaa2, 0x3c5991aa4bd8591a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #1", 0x379e21b50069e373, 0x2b0d8dbe6c80ec70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #1", 0x6aa7b75c1df029d3, 0x2c27173b4c9b0904, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x3db012b32708c9af, 0x5675ff363dd15094, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x4f97e3e4053b0a9e, 0x5b25ace2175dfcf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x56438d15519e3149, 0x34fd6b4f5915ff32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x4df72e4e5046b5a9, 0x2c6e4afd17a1b582, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x5ec6afd419e21bb2, 0x5d888a082a082c70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x5399c65420ee1348, 0x75e0858a57a61a29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x2157f6bc704e1dd5, 0x4427069a0b37e80a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x0e3e47a82e48f044, 0x57d2f10e0bffae18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x5551b9f324f6ab8e, 0x49d0feac4bee5a5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x2a31b62d1849c29b, 0x634c574c24e99dd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x69e7f3e52a6de806, 0x7dff9d0900754342, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x7ab49daf759f82cd, 0x1816f8c437df2233, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x0f819e7f57c7d42d, 0x61e74ea3597b4d84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x78b5e77675486e47, 0x312167ad631b64d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x65968c1c46263dec, 0x6e534cde1a0dde32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x746f2e306fde8af6, 0x260d8c4a73d4d3c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x14d53685230f856c, 0x3fc32e2049c0e823, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x3b5948076caa2304, 0x6eaa85fb3f06ecb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x17180b0b579328b9, 0x3f7c2ff425413bec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x4d32ab863f07acc3, 0x5d205e2011cca8ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x16cf80f11c695dec, 0x6b47f63e5cb44a05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x11b1cc332e22fbb7, 0x3fcfaed90f856867, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x744939a34fa0d2e3, 0x2993469977485850, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x3f7f5dd92ae05a34, 0x6b1d2c1468b867d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x4defdfa02123d5f2, 0x32794ff75454945e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x0dcdf8f652d7b105, 0x135b8110094927a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x2a6ad9be0baac1b4, 0x2e8a639424e60401, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #2", 0x4ab26e7821faa2fa, 0x36b2acbc779d8544, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #2", 0x3e6400e614217e23, 0x5451cf496181ef69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #2", 0x424479da1a9a9e69, 0x710757d05015cd1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x6a3b714c327b517e, 0x475e256a368db37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x5d5babb351bf6b48, 0x1f461b5129bacf25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x72e3413a116ae494, 0x7e0f63842b4b8b53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x64429599631f1690, 0x3494b2fb00b13a31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x6ec9d8445c49eaee, 0x25973e320ead6f57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x7e448de95a9cc3e5, 0x064af49b397c46bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x6ebe42080c058df5, 0x1afe36253ca88ecf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x26a02c5e541c8153, 0x0cbe5be93102bbe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x0697d2d206d68ab2, 0x67906f6010db9daa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x5895f5fa38a5d054, 0x3a966cd063f37e85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x4a10b4e843d3bcd4, 0x0f3f09d84b793735, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x26f2d36471c1af98, 0x4c2a71662e534a82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x4e0b9a87434bae75, 0x3d00b9d915bcaba8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x1de8725a6a37288a, 0x4f38f2654c502870, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x763cb68015b71329, 0x08f8b73f0ca6b462, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x69d3947c2539dfa5, 0x3da970441cdce2de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x2c106a57684eed59, 0x2db88089706b674e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x20f4bdad639defac, 0x545ee5d304a66051, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x2771ac801c4a08ec, 0x501f97866b057295, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x0e0bb885565976f1, 0x1958bd174e647fe4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x19a52566335a1df1, 0x64212b8c5c17530c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x1d91467c316032bb, 0x28677b7c378d97c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x471745e401ddbc66, 0x44344c2213cdfcfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x27179c0b5e636063, 0x30aadfda30eada61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x46b24dbc75b52783, 0x215641af53280662, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x5953172f27edfe3a, 0x57ce66b467a70b69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x443807276c053b16, 0x52ac7dff00c4c3af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #3", 0x425eb207334a6f1f, 0x4f2943935243bfac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #3", 0x66a48d1156c28e34, 0x2e5b12b85c03d76d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #3", 0x0822c0ef57c5bb4f, 0x13916f2d0435d38d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x59a377b648aeb063, 0x1803d0894f3a06d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x271210c7217b22e4, 0x0024e13500bb13c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x17304a672bb180d8, 0x53e31a246dc45e83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x539f7f122817e7ec, 0x556b69ed70836196, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x141d2302407168d8, 0x7148254517d78639, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x73bbd7f81876589d, 0x6a1b45e5567bd50a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x6f38e6d146111ba5, 0x327fac775a606509, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x1dd6d6f4769a091f, 0x5e963896775ba7c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x3f48b98246ba8fca, 0x4695ae95777a4eaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x6835b2ae4c187c90, 0x7835626c665aca49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x77c9fd68298a92ba, 0x541f28cd7f65fd16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x51a27aa6613183f2, 0x6fe95eac4b697c7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x21a2ecca4d5c4899, 0x634102b465bf9da8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x65d2a1376ebb1f2a, 0x3c3b72b2155ec4c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x34cc3acf4e556261, 0x6fbf29cb550b8808, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x44ef6b8012fcde5e, 0x4c672fc952a311c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x59b76e284252c2da, 0x4a1d606e04382503, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x0e6b3f6a3eb21819, 0x6a92ef4c41ed20d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x683caad3313c7c99, 0x41531ded06353cd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x126e008b34dfbc00, 0x519eb94c39df2579, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x023c049a5bda35d4, 0x1f9ec3223410ed56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x4a9554fe392edbe4, 0x496fb218680ea5d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x07843e4509815da3, 0x3d1a2dd97f618fcd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x1c7e3c011c2201ff, 0x5204a1914c73a9c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x5e74c4d93b3ebe15, 0x50abcec97635aa2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x79f0d62f7975e8ee, 0x3822cb016ce00443, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x2ab2658744b3fa61, 0x73154115622d8102, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #10", 0x7993b6623bab699e, 0x1c0ca67c3d206613, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #10", 0x17859f723aa10581, 0x713153697bcfbafc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #10", 0x73cfe16520f88ea6, 0x63de60cd621af471, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x2a79ec49338125cf, 0x617c843e7b541fab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x4fa327ce1873983a, 0x47c7c97146f8284b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x53b2564f75509d76, 0x3d2dd2752e17eca7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x6ec686640e0d31ff, 0x1af7f0ea4da32c7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x52c12c614bdd53fd, 0x2fd0ad811978ebeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x0788bd9b47caa567, 0x569951fe4c54e2c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x026baae92c02fe8c, 0x48249dbf1f0e5d0d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x4cfb8d3262a5d5bd, 0x0129517e763b8c4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x1626fb8c3957756a, 0x718fabf97775797c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x51cb0da47b9b743c, 0x3e6da1c765ca235b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x70ec11b22eda00ed, 0x13e21002257d63f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x3ce732ec22f13df3, 0x732090725fb29816, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x6ece91f04fc4d600, 0x792b84010fa85f4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x178f7b672421dfcf, 0x5bfd421076574f8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x5024de5b168efe17, 0x1565ac9919fb2650, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x7934d3d401c65e98, 0x1036b29f1d206b8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x3b1dd403530386d1, 0x1495e50a0f5bcf61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x4e9efb0d090802be, 0x7525f2bc0ce8e1a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x37e203ab2586d60e, 0x3266459b3f8b0cbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x48781401186928d6, 0x1f3da4d574c93698, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x682dfed6606ed7f6, 0x047195e53746a5f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x0490b7c54303a216, 0x2d9df57d7fbd7a3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x5992a02e29ef532d, 0x19b8a08e54b59621, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x2bb5b1c6066be6b9, 0x71d601af52c77402, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x596f6d8a5749361f, 0x6223436366d385c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x605138de2622ad0c, 0x73bc6770280e6897, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x4ba9831a06d71a2b, 0x6799755618333c89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #17", 0x1f404301116e0907, 0x0cfc73211421971b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #17", 0x71dce0fd7906328b, 0x4b683d0d076e41d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #17", 0x3c09d4a120e45ca4, 0x072bbc16766d98c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x4ad3afd23cf93092, 0x4b232ee3159c74cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x4365174b4a872c35, 0x6863e8d276896198, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x21d0625551194ed1, 0x5d5ce7611cd484d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x773bfbdd2c7c62c2, 0x44e2ed6c02219b33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x33537ced27514ade, 0x1a54d7bc42e57ef7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x38bf53e5226f5320, 0x570716135293bfef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x1b7585ab612dbddd, 0x5a0201c72a9c34e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x02121a816c2cfc88, 0x2109cda4577f5a4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x29262d1a557fb7ee, 0x6d1bcf1c4ce5ca53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x2006e42420cc134c, 0x436f2beb6c8b4466, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x71e5621e4e42b6a8, 0x095fc93b41d74679, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x7abf196a5e4db968, 0x43f8e1ac69215dfb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x059f0446030df306, 0x2c06dcf32e129658, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x257d46265aa8580e, 0x00a656473e5e582b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x3bd615eb0a045ab2, 0x68fa8d0d40f2cbd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x7631573a058df53b, 0x1872261f3de8306c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x5b0dad2a4e3d26ab, 0x0acdfac01f578454, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x6f0939f8154291f6, 0x0be2c8ba7b14914e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x6385489e00e4b973, 0x3cebd7c760ee9c16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x5f3272db7616d704, 0x4a0ffa115e446208, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x7924ca0a0cfd4ea7, 0x0c56f86064d17722, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x67a5a6b50c2a5c5b, 0x232fcf4d1ea21031, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x162eb70d78070222, 0x5f94dc03237bbca0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x7d94f75d6c31e7cd, 0x6163ed0d0c600e47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x3a6f0e78379a5b56, 0x2bb7929b58a2a487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x4cdced4c10a30d9c, 0x53b735d529784870, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x1187c70f5476de98, 0x0a66e486306235ea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #24", 0x4a8db59c1afd9053, 0x0ea697f270ba39eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #24", 0x27fadefa78bb805a, 0x558bb10d43b27fa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #24", 0x04e5dcb541e96bdb, 0x62548fd80fa085b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x39f06dfd14802f5d, 0x331c42501b1493c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x00b2172a532c34a5, 0x2774a2093785655a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x0ac68ffb63df3fb7, 0x102809e23b2125a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x74824d546f00529a, 0x64996e1357a37d47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x4377313216ac4b23, 0x0805b331060a1463, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x31a9db764c4fff5b, 0x76c44e4e0e04e6ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x450b7fb6340bf64d, 0x51b7667559a4ba71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x75f562281c618271, 0x6945402149f15c6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x30e1b1cf0c7a9237, 0x6505f02e2fe5d025, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x5fa6c6dc77933f62, 0x676b35803193c8f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x5b727f19514e5cb0, 0x6cb4ee9c6a6d56d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x404eaf4a4a16874f, 0x4210d41e4ff4cc6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x60c2d2734cc32f1f, 0x55fee0d103c5e07c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x19132e7b63822dc0, 0x11cac74a126cade9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x178e240d5556a87b, 0x6c11685a5e1eae31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x71b82aed0d15faca, 0x28100a9c0d838636, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x19908d0224d48bdb, 0x3d69565b2299dcbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x1c67cb3d40e29452, 0x542da5b5793753de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x1230f10225b57ed4, 0x63a4aab677da4a57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x6fcc06241dcdf795, 0x47cf16c4527fa04c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x6a9126b568104812, 0x564580c8508ed897, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x4b9275d24f0ceedb, 0x62fb868003a45530, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x2463975609d30dfd, 0x61c30361632099e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x16e908c82e0d7671, 0x70a42016161bc243, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x52e2024d0ce344b5, 0x38b59eff307995ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x4dc5d9070d55945e, 0x29b0e9a86f49cd8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x330b13332ef32ea6, 0x672417e15ff6ca09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #28", 0x4cc1263b08bbeb1d, 0x32766a5522d71957, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #28", 0x70cc332f5661786e, 0x7365f1ee37524cf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #28", 0x256e67491cb9a581, 0x3af6a2203c5ea902, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x268cb37f102362f8, 0x1f7f42e249d1fea0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x3e30d96918a35fe3, 0x5fedc0e33d75bc47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x2586a49817a03bb9, 0x6def52111112dbb6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x24f5d0186780c122, 0x005ca941734c7d9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x1673efc805b9b1fd, 0x534347a85800e34b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x0e759d1a6e3dee90, 0x7ad7fca263351604, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x449f66fe557e0515, 0x1a8762f47f41d049, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x7237aa965b1fbc2d, 0x3ba0794b6a0dce48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x6b431f2513cd8dcb, 0x33dfcce818c45e15, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x2c70edae44296c6d, 0x563a1a5c2973f88f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x5bc9a8273ae37d86, 0x3a86d44551f79246, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x22643ea91887578d, 0x45440fe500bf783f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x1e41098a5398582c, 0x58c05b8a38d82e71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x41d646bc3694a76a, 0x1c0d44752cb6a6a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x0c12ac7f6798f039, 0x2bf876ee0675adba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x42b8ac67246348ea, 0x70837c027e4a5715, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x3830d6b66d48cf87, 0x170eb52b2dfbcb8c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x31723bf511f69861, 0x576fc41b64a1c464, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x4cda15e77bdd6690, 0x369956ab0d3be41c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x1464be1e66bbb7e5, 0x0dfb5c5b6f3e5490, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x3a5410114423c777, 0x2816830232a5c7a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x7ab86ee10b54e53b, 0x5f5c6e4d7c2a56cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x72edd5747323808a, 0x02a0048706cb1b60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x1786c9741c2427a1, 0x0515727635a681db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x096cf7283b121183, 0x63a24d684fb7a02a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x4d08a9e46af2bb3a, 0x3459648f3adf331d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x66d021ca56167394, 0x481b173919e2bfcc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #29", 0x3cd22b793137975e, 0x0921145c7b34dfe8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #29", 0x755b5ed60d3715de, 0x2ddaa79177263b8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #29", 0x188bfb1975f096df, 0x735092577013cdb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x691417697bf45b8e, 0x76dee9180b79d08d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x1818832f24c29fd1, 0x41205269009ae0dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x5fd4b15404abe597, 0x5052810821857a57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x6f9ea0d1247fc4ae, 0x5c64ad752cdd5b39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x7a9638434fe12f61, 0x46c01b05566ec29b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x0118c6c07f7e4a15, 0x51a3a284376863bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x0cb55ff321df319e, 0x2e8e9f4776742596, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x17cfc87d5d66dc65, 0x6687f34d25415b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x595b37f371db7e02, 0x30bb2b9900e3dfe6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x169e1dd351d141cc, 0x017ec0c47173bb22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x567d27636f5de2ef, 0x12f9357a7672cf28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x13dda79d6a104566, 0x23502a61461bc834, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x39f174c76e2e2d53, 0x1c8a8acf0e73dfe0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x6dac7768746ae2e4, 0x45dc439d3b0a3b87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x164a14821806546b, 0x317e611d7a61d75b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x756d30d0505e5e01, 0x1fa332672e19dd00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x4239dc03307c7daa, 0x2efdbce64ec868c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x024dbf7653355960, 0x403c23e658d7f9d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x42933c4f729af360, 0x4f4ac8ff58cae6d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x5cab38c63b7139dd, 0x1ee6af0d5670e3ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x299f67302ac1076a, 0x64e4c3cd169cad8d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x1f2bea4e03254a32, 0x51a6e915174bde99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x1b2b9e9d3150e85c, 0x11adb5f43575fed1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x01af465d128d98b7, 0x638fdbd11098cf6e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x430a16621f9d5c18, 0x5f61383243e92260, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x72d2b5796c0be536, 0x1cc11c374557d5d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x5ea6d8963d096bbf, 0x1e22bcb23565f1c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #30", 0x787aa59c70bb9983, 0x0bd6d5b53b52115c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #30", 0x1b7ca0ed2395a7ff, 0x51eebeea221a0ccd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #30", 0x26baf2314b13a15a, 0x3965eb663aa88b3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x7c6489b653ae65de, 0x701e8a0d41e690cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x663bfe9531e0986f, 0x527f603d7e13d013, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x517df4875ebe0eab, 0x41fcf274294614f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x4ac9f3e20cc0a782, 0x6e9dead04450aa00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x49ca1341058d717e, 0x79b69bc92970cc78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x76490b0136b19cbf, 0x64c2ddd54244b8de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x5a4744be1dc4b111, 0x645ec5ab11c5abef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x68d8526b3c8cc138, 0x4c6e372b010236ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x103b2716156827fb, 0x42e8c7be653cdc22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x4748c06a254d9ea9, 0x6350ac35767725ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x040bad550e5b2573, 0x1fbd3aa318c6b4f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x1b1bccf556cdfabb, 0x5d175ef24ed5a137, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x5c5b6c3a5d094b84, 0x78466daf64e5e036, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x13bae8430b895ebf, 0x272a991452a4773b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x294e0fd030d85a55, 0x646a232a6e022d01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x6d651b8d31ed2baf, 0x6f0463f11226623c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x475553ab5ab3ea93, 0x77633e5e7da042a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x0001893d13d4a2f2, 0x7417684f0e9e1415, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x222fc865047c27fa, 0x2764c907040d3692, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x5b4a22b54b294578, 0x52e2d7c93d4b955a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x283290fd495c0ea5, 0x2231759037a58eef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x54e56d646eb42955, 0x0a4a062b3bed7940, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x1f8c83ab18f40a33, 0x29efa6427e337d35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x4ae135e207bd1dcf, 0x1059df710cf19f38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x627108627ea94a2b, 0x0a91e1dc1236898d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x127ded1d483966aa, 0x20d49da36272919f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x4cb58ea439629ffa, 0x667fc83134adb582, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #0, #31", 0x048be573142ac06c, 0x71f94adc27ffb15a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #0, #31", 0x5d86cf1169ef4674, 0x5fa540492cbe7670, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #0, #31", 0x58a36fca129b95f2, 0x68abefb0326c3c76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x2b8fa02540f9991c, 0x309fb9ab782ff375, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x48b6b6eb0fb37489, 0x052192ad7670d608, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x0e5cbeb4297bfd38, 0x08a75f952b27bf4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x71b563e3741a191e, 0x0d9a50ed20daabd1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x2d7cb9194781ac2f, 0x558861533e6af287, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x5bac6c9c460fe42b, 0x666aa3e132089e8c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x2fff2a9f477304ac, 0x5ec714fc39333bad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x5a0e9a9f1c3f31ce, 0x6b9f782308a29a69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x5d38caea05f4208c, 0x00d28dde059e3ac4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x15a7951504b67062, 0x7c0f10cc25ef81d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x2e326d9a5eb19210, 0x51174123240453ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x52cbab2e1a6760ef, 0x44deff9b1fe7d17d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x61e90d1e44bd67e6, 0x5e52c40500486447, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x0acd4c11111817cf, 0x325102d33d9579ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x588b1c7c62682d8b, 0x76c8b5683acc76b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x7ea75f5a44419ef9, 0x436f111a3299b71b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x4a35bf85344702ac, 0x3837f1df5be02a44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x38fd730e52e6ed3d, 0x01cfac1a5fdd549a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x31987f4d48c0a800, 0x03e1a864672fe0a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x632808ef656a762b, 0x0717b22604642a7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x2a27de1136fd9196, 0x04ac8ec34511160d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x4815a966796f4530, 0x02a68fc834f52a23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x5bd772bb3330b1ee, 0x6fc1a0d420a0c5e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x777250e70b726edc, 0x533a7cfd5a7ed215, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x3fb97188382ea874, 0x365efc5a41a8106c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x0b1595b125670d6b, 0x2185650778b6e496, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x6e27b56b66fe7765, 0x5fe6c53f3cae14fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #0", 0x4c68ed9045bece3c, 0x41123f79514fbe5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #0", 0x7cbc5fd319076430, 0x1660d4687690cba1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #0", 0x1276a9601b479698, 0x2b85f5c444d20939, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x4e78488738ad4c18, 0x6572cf1b6e4e1c1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x441fbaf47f2bea8b, 0x48ccee3145ea996e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x375a92ff29180ee2, 0x0792a9db03d92c7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x4e7f1c4d5c76d652, 0x7c901113427028b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x43754db740307d27, 0x7f1e3dae3ca6d1b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x05ef4b642457647b, 0x0df690130fde3b47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x3d5ec8ab31f4fcad, 0x066f06e902abab37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x4d3c93462cf0838b, 0x477db4704fd5720b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x659dcfa306f07c58, 0x3e238e271bb4dbcd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x061c66e369321f16, 0x619f753b29bd8a97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x124a2df82a26c828, 0x2d96b7143d76f9e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x069d9e7a7f056040, 0x7fe7229260c94a46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x3f35dd672b66ac12, 0x1d701bff4a12ec32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x4fbe108e60602e62, 0x59f12779452528cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x12552b100f4e8872, 0x47d0d4020d1cd939, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x3c3f0bfd1b15d96c, 0x5cf24b455f91be56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x220655c45ce60f5e, 0x7b469a2321dcdba0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x46182e7579311d4c, 0x4b9a66382822bca7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x2357e5746580d91b, 0x6599b68958625c6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x6486395b569bc2b2, 0x392ba6b329f583ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x02026ec54df9979a, 0x7408702123bc16c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x2e59c5fd30b21390, 0x68e13f8e51c07f53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x40009c033bcfa3d1, 0x5edd588c40aef10d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x56e57d3d1b874986, 0x2040af637c3fa800, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x786d58e469b6e9d9, 0x1e1c83a178ebd301, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x62e8072506a84631, 0x210e8fa83e858759, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x6c291f4c50138a7a, 0x16e7e3c7063fec9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #1", 0x26af4d2d243de0aa, 0x3035708950af58a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #1", 0x723778445d4caef8, 0x746b6f6a28b1bbf2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #1", 0x0dfec288594f93d1, 0x7a723b4520913e41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x151f37a30180deb1, 0x61402f4e4dff5e8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x1d082837685b8a2d, 0x4a3f068c6c04b4e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x5212740605ff178a, 0x64f087e21575811c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x0ca75dbc6ae2ec3c, 0x53fb087534fa7b2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x3af676b76b6fd84e, 0x3b3a67c578d07d08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x0fadb8f83deb451a, 0x497fd5b061a5c3e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x1b37f41204c9bb1b, 0x0a577fd601e5313d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x5e194eec03b69ecd, 0x22766f7e2936b69a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x05377d7e41751bb2, 0x773615267338868f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x29d0a5df442dc352, 0x5f3d3b70223fa5b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x4a2cdadc0bb02f47, 0x37b526d27be319e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x76931b846c17fcd6, 0x30dd951056d43898, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x5787d52419248b51, 0x4fa4b5a13189923b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x570fd06b1d86d5f5, 0x132f561f67358e1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x225091100b912ed8, 0x691abf5a7247c47d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x0f47cda512b4903d, 0x1b7e7b170069dffc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x5429abef52dfa1fc, 0x73a2668c147f4b24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x170d654e6e7417ac, 0x36bef0da7dfa51ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x7a2446f32abb00c4, 0x79dd6bb3613a402a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x16d2fd9a07b32e64, 0x380e78c370b76277, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x20d7b9b535704ad1, 0x2240f4b26e5ad2be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x52f720c63eab2035, 0x559060db77e78a20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x4a3c4f0e05adc9b4, 0x6a2f4e9d7547b1d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x186259f26953f85f, 0x75b191d359841cb3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x3c339a5b24c258b1, 0x6e0367d76c8c05e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x1336705d6463c363, 0x6a8657b05340ffa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x0f1ec4276c89b896, 0x347b3fd30d5ab751, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #2", 0x743ce6fa20530e7b, 0x7e1219c825f1c1c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #2", 0x55c3594c69dcf55b, 0x144c94801514a0af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #2", 0x28881591772b796c, 0x0cfc2acf28ba7a13, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x7cd9432113b3bdbc, 0x1e022be972c4649f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x7d07b61b3a4be92a, 0x4c488152153b9d13, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x5f0e41db6c4dfaa4, 0x01c7a2f4393b5076, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x50b1be0840f78ff3, 0x0c7c501f7244b239, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x2d8148897db18352, 0x7f9f698a5fd0822f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x1e0491cd1a0ed871, 0x05c243f121be2f84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x03ebcdcc43cefb03, 0x36d2d03373c7eb1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x3afa746f3a849116, 0x1c82652d2c73e35d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x4e384ed36b80c94f, 0x1f3847fc37d3b790, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x25ccb2794ed6f798, 0x4d0f54a34b4004ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x3b24f23c10f7a584, 0x047b556504daf454, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x51ef357776bf1017, 0x771fa68d0bd6b044, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x7470936a71697665, 0x6ba732747f707e01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x0b784ed658017db8, 0x212ead8512752537, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x1bd078bb22bf757e, 0x063d10510f641ca2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x5d4406955b1047fc, 0x3bd8000056caed2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x4691114b5badf95f, 0x0e9ea4bb2b7c5568, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x2a84f0f77b37afbb, 0x76bc5a566c5dc3c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x0c2f554068585ea6, 0x7138b81965a9e333, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x5f176ebe5d27c5ec, 0x718093785e1e8ab7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x4e913c517ebdb63d, 0x5d8f08b853880228, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x56bf33f66c3a37b1, 0x65fd275f5a098b27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x0ef9ad2f2545a7c9, 0x696da7c9728facb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x0055efc657f93e98, 0x495a99dc6c3db3c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x33a737f70e766383, 0x17ba092c46e70111, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x09ae133e247d7cef, 0x3344c4d65e2c28ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x0cd5db9535569f99, 0x43d60c2115dd687e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #3", 0x127e6585518afbee, 0x73fbf3366bed4a53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #3", 0x5048b22c257273db, 0x3f754c7b610fa1d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #3", 0x11acab8c2486d4c7, 0x3b192cfd2707e622, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x49cc7c9062f22cb0, 0x199792d320a658bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x3aeb6b48249e15ac, 0x0ce40c804a226c56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x3314792f444e323e, 0x11096d686e92a33f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x68cbaf2d1094d84e, 0x4cbecc2d3cc28c6e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x45eb77e8469be822, 0x529ff4ec75a18ac2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x1826e41121042191, 0x618ed5165869dd6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x4676956c7492ac41, 0x39797f44686f963d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x19198108290f0f32, 0x0f777c5f582340f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x0c013be205ada634, 0x78c999b462e5fd99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x2a4bbbe03e11d757, 0x2d0869ef46eca72a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x02600995023e1696, 0x357f4a695d603510, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x12d2eee56cc2b66a, 0x1a22c17e6b2bb8c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x335e9e8d425c189b, 0x60cd438558be66cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x63603a2c6aa1c37e, 0x3128443a4b85829e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x5f346fc0436c953a, 0x33f518db29d6cf99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x6c7ba46c7ac3aa45, 0x01fa1091784df0c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x00715079083c5851, 0x5b33ee61787ce04f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x464e2fa874e8d1e3, 0x3f6987792abd0c5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x7726e879224002e8, 0x081d416a48ae393e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x0f02b95214a73585, 0x33d9f20009f9d75e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x57034e2013e08266, 0x62b83e2b426157df, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x7e8245e441dbf358, 0x0de6da7d3a63884d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x0548889266346877, 0x643a57e65db6b5a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x60f812bd313894ce, 0x5604a66d71c42cff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x3974ed1f29aa94c7, 0x6a410d4e61696336, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x1e9366aa1443b0fa, 0x0c266f907fc31cc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x3683b3e27c4b4806, 0x4871560615ba4f24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #10", 0x10f27d8c026c64ae, 0x1fb4268245866d35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #10", 0x164ce71415ce9f92, 0x07e7c51467f5cbac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #10", 0x57aa92ea0693abdf, 0x225953f914cf2cf8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x6cc81457488a890a, 0x7285e29d5cf31b7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x79c31dd838f855ca, 0x4eb7487c4dc02714, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x62a2ea913b4ff9db, 0x2f298a4a33380af8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x4f93aad57b6c7dc6, 0x32fb27c00136513c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x77b7c5cc36a4c6e2, 0x16f0a06006175eb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x39112b9053859101, 0x4b9dcbed08aa4358, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x6954309312f962fe, 0x70a00f054f5e12a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x198d0ede56b3223a, 0x642d3f9d40fec37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x1f3dab446ca92777, 0x1df1defb06552335, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x25a17d41033ed493, 0x54154a491900c91c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x3e8ece6e7f33fbd4, 0x4c38d414084467d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x7aa0799a206b596e, 0x097ab90e0e227944, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x571020515fd7a3e9, 0x1439d7fc72583f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x335d34ea6ba291c4, 0x7b0282bf10214be1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x7e9bf4c343ac9e23, 0x5f7f5e861cb1657e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x1a5fc05d7ba207f7, 0x5db028fc182903a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x684b2f6e7293711f, 0x1e7e26d6399d6ba1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x75d245b21ed708d2, 0x529e34bd0decacaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x1e0b04a61fabcd90, 0x1631148134611421, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x401726fe56bd6561, 0x42838d6518ab7e41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x3695094a06064067, 0x0b03bda81727474f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x71a8d22c06c7f1b7, 0x2748933169f23e34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x4a748fda6453ccae, 0x06a3a3b27044c6ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x5ff5d4a526ebf166, 0x086dca9064d45037, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x197f6285710ff095, 0x1e71bbd848410413, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x0fe6f9676c5ec544, 0x562db0c20f51a837, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x0c0a92d4063649bd, 0x43b2bc582df1fe0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #17", 0x5cf3af1e51a139f7, 0x469d7c4f4c21b9d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #17", 0x57a77a5e0a919453, 0x634901221388b868, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #17", 0x1159860a041e9a4f, 0x7d7af69d49504c8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x687266fe4202de09, 0x399513795bce15e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x68eecf6f5f1421f3, 0x40a2661b48683ba3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x5024128866d6f079, 0x10a93fb7026e31f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x5335b5bd55729684, 0x11bfda2c600b0bf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x5ba8e042549a864d, 0x0dfd09fe5f404891, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x263bc0440eab0386, 0x2b620264389c8f60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x193c97d949a03e66, 0x4c2547c97de33aa2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x4dbed8b500c89aa6, 0x4733872d2a961de3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x42cb78b0470699e2, 0x066433c736313fb3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x261abbd50f42bb0e, 0x7e997b572bba481f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x7619ab873fe85440, 0x2e287a14763ece5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x155aeac46446e44b, 0x5649da4d494f6145, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x38e16a9853f1ac3a, 0x288fa9d67103cb06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x629cafc075c5a230, 0x29a05a675f1d2adc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x3f65e0962433ecac, 0x5d00657f7bd94799, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x24fc87522cd39943, 0x266f657c0d24b94b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x73da332541ef7456, 0x4355f8ff67c80002, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x51322f6441aac236, 0x1382482219f4eefa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x01931676667d97a5, 0x1033bd58474bdaeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x4ac47bf1392ae607, 0x109b3c3016ee013a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x0d1c9241319226a8, 0x07f1cc4103a5e689, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x2757c8d83fc376e5, 0x62c311666fb94202, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x63f763911201ef18, 0x6b92899b66bda96e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x3ed5885b37385bb8, 0x73e262b908f3eae3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x7927d00e043e3308, 0x70bbeae632afbb81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x45e8f53e5cd867d3, 0x4ca4aa7b4a59ff72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x4355ff792241168e, 0x11a5da5e477c0bb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #24", 0x5b6bfc95665bd92f, 0x5e6a0cee0e1a7b6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #24", 0x17edffd774837359, 0x11c061f368888ed7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #24", 0x3446ea3e43d45a74, 0x5841d0d93f45c8af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x55d6498c19e5d4d7, 0x2603721d183e4dcf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x511e308f11ee2399, 0x213238b314abd1e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x162c56a1140037e4, 0x475b8d694a46009e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x70d89fb82645da6e, 0x14a000105c154bdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x4886f0fd01fb6481, 0x23915793342e9f31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x68573db154097c8e, 0x42491a9b23f2ed92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x488cefe864bd4d42, 0x0c7b7c6900453d88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x2891a7b7658e7855, 0x3f8b06387cd3da26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x7f744d2c364460a9, 0x151227f67e67f143, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x483284425a6f5094, 0x1313c32b50927dbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x6e6f88792f787e6a, 0x1ad87e5a5e5edae3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x55be58d95e057e55, 0x3a7426c25f482831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x6000e2d655bfe1fd, 0x1376c7621e4549d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x29c95e8b4eb3b3d2, 0x4238376848582087, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x3371011408286448, 0x489d5e1072564e73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x6db6dc9d043c5090, 0x6f2a289a5c02a8cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x3a80b1396d7e5d3a, 0x5a6a9a0f6d2b29ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x47edadcf589625e0, 0x3dbda78602b3357b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x080ea44a1b863720, 0x6112105e365d3648, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x798bb575291c25db, 0x15a55e795dccfd23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x7edc07d83e4a7e62, 0x7c1246f9598c984b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x0cfe32346a8216e3, 0x21e4b8d328a56663, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x72aa7b2b0a25dd71, 0x1afbb4d7406f3348, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x0e622e0176dc7623, 0x1c71dc14606157c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x645ad35d0b4a2918, 0x4d8c819248e2df3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x63e04ef82ca82513, 0x4b9614b52c48812c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x482e5c33784b15ed, 0x62a5b7746beef343, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #28", 0x21673bc845ce3760, 0x49bbf06641ba11a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #28", 0x0418b5c23d2b62c6, 0x1b46a9f3204343a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #28", 0x27ad79a963e45edb, 0x48e8aa041116e7f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x6e0a3c4c6df7f752, 0x51861b3e1a57f4d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x64d46d754845ce2f, 0x7ab94c9d7c6c6a4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x538ff74810e55e3c, 0x454f4987492f40d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x3d8d834f581d7974, 0x7577c1ff37704640, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x50688f616d1b29ea, 0x235f398305bbdf82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x32e9614a62bc9b1d, 0x4775f12a71cfcb2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x1fe7fde45afbb8ce, 0x12130eca3702170c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x3ee017a9199f1a40, 0x4818ff024795778d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x079711935ca6b8ff, 0x61ed6c622cea53f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x24ec872e6ea607c9, 0x2956be426c6b7f08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x7f8b66052b1281db, 0x359abfdb787c7e76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x032ffb4f534bfe3a, 0x2fecc4b73d18e954, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x406728240a4aba00, 0x42d4c8d653988ab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x6d07551e577b64a5, 0x456855da7350896e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x32771d73726b9f7c, 0x2a52a07a0cef5302, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x0c0ab9bd367236f1, 0x5484ca8f7157351d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x1318eff047984755, 0x1e41891213a1cb50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x363e4f1e35a80a34, 0x000d4a583805771f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x60ba8c0f606eba4c, 0x3081f59535c9b524, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x33bab88735b7674f, 0x72e29e7863ea875e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x4002214f7ceb67e9, 0x3783120e7421e0ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x5466cc8e11c50a94, 0x67726a1a2d09766d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x0430aa110e7d93ff, 0x39f8c96f06ddea01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x44efcaf01676a831, 0x78351f1e103b63ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x5e0eef8623ea7976, 0x23dd2f1e5808bae1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x599283aa40902795, 0x100e3200144d3ea4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x20fee1e23cf99241, 0x4a16f3c83a4d0fb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #29", 0x72b0f99055baa926, 0x1e37971754b99a69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #29", 0x52a6110f304de52e, 0x48db7b1432b31adf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #29", 0x4212efc319b55abc, 0x5fbc914d270cdd9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x2832eebb261fe6bd, 0x2deac79e464399d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x3c968eee7a5c2cc0, 0x567efda26d22b9ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x1e46a6365539a68d, 0x452b748d1aa57e74, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x15c9ce227909b0e1, 0x2ef2bd1877d929e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x36034322505dd0b2, 0x3226399a36c8b004, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x261879d8545dc582, 0x0b824a6d28b43cb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x04abaab03b23e8de, 0x5b67579178be8ae7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x54d9439b4db63022, 0x1fcb688446be9a73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x73d616df638131e9, 0x0d0234477d0c3256, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x5ddd5ea92f5a608f, 0x6a2eec02306ca5cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x0494071c7a04e15a, 0x4b1224417c2404e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x730e923b2623685b, 0x73fd2ec11a5dd53f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x7681390d5ca8cfb1, 0x512685432911d55d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x310695332d2d69a0, 0x51c6120f1c99b2e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x6851527f3523a650, 0x15583dcc35b23fe3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x02d9d67309730e9e, 0x7c70da573d2a961a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x6cf440882465b473, 0x3a36c87076afed52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x53c01502722eb761, 0x271c93204ad19f31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x6c3398bb3af2d2d2, 0x46f5a41158541c1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x61163b2e43d876a1, 0x72b1f15e5f422af6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x208146525a1a1262, 0x085400535797743b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x07477c03098964ed, 0x743127215187db85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x3ead0b3e03aaf5c0, 0x073a1b696f98ce82, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x0d1e045e66fa2d0c, 0x2cc3649c4186e1b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x0b5fe17f5f536223, 0x3836cf037a1244e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x518219850bd98829, 0x44e3e4185f1ff682, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x46cc5afc2a2603ff, 0x377412a13db5b240, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #30", 0x6dfe7aa0254bdd8a, 0x1cf7dd3727e2962a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #30", 0x7f65efed73ab3186, 0x7f7a0a650e7fc0f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #30", 0x7d3496746741b7e1, 0x60079c7806ad6bf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x6aecada123099f0e, 0x76463a723be1a1b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x0a03cc1a359f5266, 0x7d688363780ab200, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x14f2b48a3700dafe, 0x721cf6e61563ad9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x42da63282bf7b6bd, 0x7483a41c6674ce0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x561dbabc41225d86, 0x242a804f09a6be24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x666e3b1131035eb3, 0x3189544e441c355c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x24ae903a32a392c8, 0x529bf64f65d42afe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x19e54aa962c7d160, 0x6c8196ee21e326ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x05d1706e5b2d4bc3, 0x5dc4c86004d1f84b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x10cc9e296ef9a131, 0x7cdcaa4b0fd53c88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x25fa7c3019bc8e3e, 0x2538ea2225bf52b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x45b444fb305ea112, 0x0c3420c268d4df58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x7180fe982404f1ca, 0x727b9d7c1bd1ffb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x5508507d328a2b63, 0x5fee351457ef39a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x652dbe2b2a44fb95, 0x3dc364a779b6e0b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x0d0cccf5795ecfc5, 0x1b9a07657f1308d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x548c1b8800c1ab6b, 0x03e5012012de3d63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x6fbb4c9c47ec640e, 0x22b379ec6558b9b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x61a8f24d174c2d28, 0x0b180c6515b5c8cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x47aace3a710645a0, 0x7e8aa824275d3748, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x150b376a231d6c14, 0x432f3700392bccd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x55a797774ede6b23, 0x111b067c6a1387e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x792366b97f647005, 0x63ca689f3ad555a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x78c33fca3dcd5f98, 0x39e85e78063033ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x3e8f0b033bc1eafe, 0x190e71124d4f5b53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x03ae4f0c3dc0216a, 0x32a815052e4a579f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x550c4e92428ac890, 0x4400206c65574159, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #1, #31", 0x33910e314fe3afa2, 0x0cb478a21cb71ccc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #1, #31", 0x73011bb666fdf01b, 0x55e2e99f489c459b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #1, #31", 0x35dc5b3e167a3623, 0x32afcd8348a8b32d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x15dea6283d666748, 0x037e08d02effc1f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x7b33c6e04e3e66b8, 0x352ff5a60ea1e5f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x0a0051b60e99564a, 0x5bf1414539c2d1e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x4c5977b52c0d49ef, 0x680d29830daea0c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x6e98127f7fba5abe, 0x7305e21c2165c647, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x4f9e0a6013ffccb3, 0x3e1ce314222920b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x7afdbcce1d7533cf, 0x6ac5664c429f2616, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x33ef69f20ec5e214, 0x0b47d94330da180c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x4c2c495c1509cfaa, 0x5fd9da0449ce101a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x6348366234613752, 0x586ff60d4760103d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x42fa8d9d69300ba3, 0x0122e2206d488818, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x153d55926dfd0af6, 0x7af728da0f540552, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x6db765b46ed6aead, 0x30b9cb9903d56812, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x02d67b6010c3ef0e, 0x25fe88c23d557014, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x2e3922de0b3c6f6e, 0x7ff4962a7dd4382e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x1a0251820e882a3f, 0x2eae503b62288cd0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x2391f9e9046692f8, 0x2bf69ceb662e9ade, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x38c7ca4a2eb18d3c, 0x2d8eab1b06da304b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x17e198df6f19e13d, 0x7422b8637bc257e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x5d16ec343bd028d3, 0x0b165d392d1eee72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x2aa6d78056f2df46, 0x30f456844ace51e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x67b6ce5508185827, 0x0823c1fd2d7d52e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x1354c79559ffdb4a, 0x2b518b0f15eff133, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x68880589240f1aee, 0x78187e032d571917, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x2875ade641145f11, 0x1385b3f60c19ff72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x6fc5ec4d0716e820, 0x12f42fbd613d7831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x7630c95e68162d52, 0x5cffd01807a7852d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #0", 0x23e6562565baca23, 0x34c6739f5347b592, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #0", 0x3cada9692639c977, 0x1e16077a4e8d2da5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #0", 0x2e52219f275c0b96, 0x7c0a8086246477be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x015be6e0326ce6f5, 0x3a5468f141a6e934, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x567c01e30283b642, 0x6efe024c69e3ec6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x4398155308f21b9a, 0x75fdebdc7ef1afca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x100903ba3d2ef813, 0x602f27fb335e01a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x254525656fcbfa6d, 0x3b0586ce0639cd18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x5586c49077978a25, 0x598182aa492b7b8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x1dd1539c13c329b6, 0x17b8a93012346df9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x3b1f354c70ed4ea9, 0x3698e5b84c23753b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x235a359e7cc860bc, 0x0dca5e703c7b1c2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x7f4c16fe1c5cf473, 0x265f089779d63782, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x254f100d58f70f47, 0x78c7e74c42e42c51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x1626075a3147b4c0, 0x76422df2355813c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x2113af2d1513638b, 0x3b91e0e03b6b2cc0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x0caaedb01c4f517a, 0x0496a84a769a73bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x30127b313f67c76f, 0x08cee1b72a7c414c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x30551618046a14f8, 0x769fb6886b31b07d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x013275b44e0bd541, 0x27acccaa53af4bb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x6a68c9b5464d6a85, 0x4d858339007e8cb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x1f4479cc39a4e6f6, 0x4362b9030fb7d9c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x6aec9bb600a1ce6b, 0x450fed8a356a8126, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x15b531f6756c5631, 0x70d5ade60c004ae4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x11bba7ab0b69a058, 0x029abea122601fa6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x4ad167c7437c177a, 0x4cdc60f241ce22dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x47e62c7254aca004, 0x2cffd35a7b267de0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x22b875461c5b4cd0, 0x4ed5c9974918a226, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x62a8b7550cf9e7dc, 0x49972ed80d213efb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x469eced261e90648, 0x1cd918bd01ed3121, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #1", 0x628ad4b3282d602e, 0x3757b247318b6a88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #1", 0x1d99b65f4026740e, 0x3d8bb56c784006a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #1", 0x4b901466677c8741, 0x1aa0264f2f555e0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x2af89ebc1e235441, 0x712380e716617c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x72cff445605dc3a5, 0x1187fa0e72decb2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x7cb91075058e9c2d, 0x3bf76d551588698b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x128884093f82c144, 0x22a9a8865f61c7ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x216bc78c18a6ab32, 0x614ef8eb592752db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x40d40b60483e72d0, 0x0ab2bd6403f69c3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x0864e6de16d6c937, 0x7c36a2e85e6dc1bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x7e5350787ee6a0b1, 0x0dc31fca53f4fb45, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x1d09f4f27bde7181, 0x6a567773294bef34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x5c3c3526582227b8, 0x1c2aba630fd9e937, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x5db0c3e5480bfb49, 0x256252c358f5459b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x078ebc8d19a60650, 0x38570d65703947ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x324cb1825413582e, 0x49609aca28fa8419, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x1c51caff2927c340, 0x2cf120587320bce3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x3ffe8c775f519e6c, 0x518e7ea224b6b1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x5e383f1d63022495, 0x78abad223e51dcf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x5ee0961603c88687, 0x679dcc247b42340f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x5beaae3f307e700a, 0x0b1c1d473b1ccb3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x788a6b534c691e3c, 0x141210d7399b7225, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x660f248c733554de, 0x29d4ba14001927e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x4748ad0d5604cc53, 0x2913abfa185bd60f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x7f2c8f935d0b1194, 0x0b7c92f2639a780c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x3c5cb00100fcd70c, 0x085129e93f2b1c0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x63fefba1651ac51f, 0x7d7cf8fb1a94ef1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x68e34ba720f34075, 0x15d7232e42df91b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x5171b07f120e6dcc, 0x7dfc5cf444cdf9e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x5e778c08283e261f, 0x7e696c0b49fc1bd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #2", 0x1b737afe7328efae, 0x4a1543b34486b095, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #2", 0x492dbc01685f1996, 0x5ce286a462bc280b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #2", 0x456a2b2a4ea7ca00, 0x4656a017485a4b94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x4fa4a10c0502609a, 0x0785679f01c6db2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x6a1d25ba3232ed78, 0x1c5bca4a33a39cae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x53262ded747f8b5a, 0x76832e6653007161, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x068df9261637d753, 0x17ce6b472497de6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x3e75fd7238a93df2, 0x6e93fa3e6505852f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x2bd22da0066ebc68, 0x298c35c459e97870, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x6ecdd5fe02fc4092, 0x3ca5a07b74ffe9a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x51a40a9344df9cd5, 0x3d5a353534380128, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x49e1fd6f525aa69e, 0x35fedc542148ab9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x048d94164b6f76b3, 0x54ec484d33ff2329, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x3fef020e1ecdffd2, 0x06ff948a57b3c203, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x3505d7256adf9aad, 0x7c4ba06f467cfb34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x2388d89f550eb627, 0x2b828063737bd497, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x5b7d728f0a0aed83, 0x4d654d084f5b063f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x0d072e1601b52516, 0x445aefe04a4b488d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x4694c1eb3482260a, 0x7e8349b65eab38a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x06dccca854e02c96, 0x7ff3e4481076bf5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x204fa3494b75770e, 0x4475e2840b6a60be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x6a4376e05f69c330, 0x631e22c1603ea557, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x4a495ddd523e20ef, 0x26bba08c1f494e05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x274cd717602a6fa5, 0x12c5229d6dd2367d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x6a355d2801882c9d, 0x3d2d3cbc02ca49a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x033d51b34b98dbea, 0x4d159234773c8b3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x001b01f455dba830, 0x55e7c3e749d2139e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x2abbd4c61ebeb57c, 0x5a48d2f806f7ce9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x6a342c8b7580521b, 0x12622f5a4b0b780f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x54ea154b5205bdf3, 0x2b4a1d675477a36b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #3", 0x2443dee20686140e, 0x73c0f1711f337328, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #3", 0x66b083b34a32e662, 0x0d05a9a54b90b5f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #3", 0x4bbb12ff1b7091d4, 0x4e5affa050e5e0db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x67096dbe1e0a3001, 0x48226c1a4ef864b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x73e5d83173134b48, 0x18ca785067246fb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x11d200c5007e6da8, 0x6e1c3e4e1ea1acf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x75febfc314f7426e, 0x69ad25077c062d50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x66fd0061443ec22c, 0x507dd0bb4ae8d50e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x4ac4d63a7721f1dc, 0x6a1c48360b40df43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x4154d83e252c94dd, 0x56d1953d317559ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x409d26b14a7da6e3, 0x025b3ac90d0feb3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x6887d6e474d2c83f, 0x5c084fef27a6946f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x67e613877ce7426f, 0x0ecb04215c6daf16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x7d65b01764bc8114, 0x7b0f5c0d79b8144c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x79b3c382463c1258, 0x75be419c73646fda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x0a7ad48428698d1e, 0x3e4d44e860b0c3e3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x1f8b7efa42c33864, 0x6bf1a327553faabf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x67efcd4109103f75, 0x06b504ac60e05738, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x538de65849f89264, 0x6df04275288cf3f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x3ecb5aa35efe8c82, 0x503388613c15bd3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x5be5cef11392c860, 0x18836c5326b16e2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x784f49751627c414, 0x20698277594b7f08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x5c63d66c0afd33ca, 0x4cafeee272030cf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x3366c0e83ea57402, 0x52b3d0db66deaaf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x0168ac6642d35a5c, 0x3c1e55af52f23fe3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x4be399d121c2d991, 0x33d2971b695879a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x6bbb6bf56218f5fa, 0x11e56d991f71802a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x4117827c740aa9ba, 0x5b873d672a86c699, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x079d721a71a1b73b, 0x513834c41cfd516d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x07c97b4f42f8bf57, 0x7648d0757fecbb8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #10", 0x4df5f32144a39962, 0x71efc887642d51bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #10", 0x03490d64072a525b, 0x4b0bfcac015cb409, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #10", 0x49fdacb708218b08, 0x544ef3ec04b1b9ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x29e464997fefa10a, 0x6e0a337115e14689, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x6208970410da041a, 0x3552c6b3159fd08e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x04e4add4115ecbeb, 0x4026972723201980, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x0300832736663b62, 0x401d6aed0c821fee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x795efab97e5ea405, 0x0c6edb7e0ac9fe76, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x43023d673a034cde, 0x6ef750324754edda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x412d9f391d0095d0, 0x48b1a1e3464b4acb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x252220d839073806, 0x4afd04950b2b4bf1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x38f6d910565f592d, 0x210c927a4f068571, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x67395d4724cced27, 0x64a655ff1aff7014, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x362bb9127e3cf481, 0x3e1f89946c1e0b1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x34a32fe3050f0687, 0x78a02b09392c3c39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x036daa8c32ed8ae2, 0x43f63ab02e022a9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x6cf0d7c03e08ba59, 0x75571876466fe7f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x5b09502957b83753, 0x0cbb32be2e1e76f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x10bf6f595a565564, 0x3949c2ea002b7101, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x30b5ae9133d84c72, 0x4f31f67249b64869, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x58a5399922d54211, 0x64b5b87d17ef0bd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x211236927cad41fd, 0x040d16f30ed0f2ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x01bc48840bf36995, 0x47fd2ee555b56675, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x3ee0f477790ea987, 0x03b791110529f311, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x371763e158550dc3, 0x4b99db042bd1cc37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x300d4516133a061b, 0x59f043301220b40a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x6d905b7f617e1b7e, 0x124c250c40ccb470, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x155667f06f38b557, 0x0a82fcd91e460a11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x120df7683a422cdd, 0x363515e96dfba189, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x36ef6eda44c9c31a, 0x7ccc943533202dfb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #17", 0x50bd2caf0c8d2582, 0x08d5947038abb75e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #17", 0x059bcf09096f8574, 0x3dd5aa6f0f9e2126, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #17", 0x61c493371560308d, 0x3b6fed5d3cb332ea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x289a36a861200c01, 0x4ed3e6f511d1d84d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x429e277f5d218997, 0x529e8cbd162a9228, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x4c5a3eee6aa5b222, 0x34709c3957f48f70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x24e7deff42bcc52e, 0x45f030f95e683656, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x078688481a5df8c2, 0x118864515bd74dd9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x26eb1e445258afa7, 0x148305385843b4f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x5bc8351b2351c37a, 0x67e1d61d2c86ed4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x38b1f408380e072d, 0x693a20383d8cc852, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x192e132e21fd2d5d, 0x4f5ea0a0614c2ab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x7f1eb6f42be75911, 0x7776bcd85bcc3aad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x168d0b3479b0fb17, 0x33c0ca1d4b78f5e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x3c6dc0453b69908a, 0x29e12c393b74ea33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x55c7894c2bcf3d45, 0x174c380d43f4488e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x7e27ecec0419d3a3, 0x1c37fd857cb2a790, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x276b971d1273b516, 0x293994de59f02208, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x4a81bc4366db8afa, 0x177cea5a601d8b25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x08d8b85838e072ae, 0x4169b5d663afcf71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x64c7cbc0733cd43c, 0x3f7c0a1e07f76f4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x6cedcf537d519168, 0x5370652f7b54d6f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x38bb21f24e15f934, 0x36c9c127295b8f98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x79e536790987d5ac, 0x6d4fd8260e82ab3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x0da1a94f346ee7ad, 0x0b3552cf780d2366, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x46e29cc3697a2fc8, 0x51fd456e350d406c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x5055bac356948168, 0x152acb9211645906, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x0f74f41634903296, 0x75142877592e731b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x27cd06d234964796, 0x6125e267743cbfd6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x31e7d8fe265b57f2, 0x6f9196ca14bad625, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #24", 0x747151262b663de4, 0x3e1665bd6aa2faf1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #24", 0x34ee1390045af8ff, 0x7925a6306e5687a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #24", 0x38c9e0ad3860f074, 0x6663ab06428fbcdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x21db203c0cc7c8dd, 0x779cfd4b7fac7d70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x635c4a450624feee, 0x1110d6777230daff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x3ab531842c853082, 0x4b5f4e1a72d13e5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x611b7818569f94fd, 0x670dfe3262823856, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x7cfaecef35537439, 0x773d0e7b13035117, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x60b9b21d76cbf238, 0x7da64c08716c3e15, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x7b26eb37462670bb, 0x5fc2c5b515a7c5ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x7e87612f4fd47fd7, 0x5837828c33f0cbe4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x5c9c48b544ae1fcc, 0x339d49552062816c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x4ad31eba5df2aa86, 0x12935c6b3ff892fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x0a77db0819d7cf89, 0x32c9d1560588503f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x707764865f479711, 0x680a88956b935320, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x149b0b4a7c3cf03f, 0x7e96a4376d725175, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x7308e2773ea15540, 0x5ede8f8a7554bd67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x04c7c5fb633405a0, 0x0afc83146e2fcdaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x3308857755bde2e8, 0x22209993034f272b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x1a6c02b436450502, 0x23b1a8970fa4ce2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x1437af880267327d, 0x4f9d6127653f216f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x1c3f020652d1fa43, 0x6ac771ae1eaf8a90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x3219915408d981e8, 0x0a42ddb10cb6668c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x051672285907478c, 0x7a28b80146b49c9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x17a89ccc4705dd19, 0x3c095a05781f549f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x2a39e2b9086fbbe2, 0x664f224e1c7062c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x5e2d9eca43713289, 0x1fbf89f25d426831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x79b6378c3c849784, 0x6ce7365d7899a17f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x3eebca0248a0349c, 0x5dd8c2ee0dede714, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x1b722edf36e04f56, 0x2c9d71a55b2acc08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #28", 0x3fb9d13e6209ea96, 0x67e132954d8bc034, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #28", 0x3b1132225049b6d8, 0x14405cd244d04366, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #28", 0x174f93f1233eba54, 0x3cef980652b9ceee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x2bae76360ee9bba8, 0x6f2a31b6418976ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x525aee320bb31539, 0x1ecbdedc09dc1501, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x4837acbe604e796e, 0x0275b6804c1125be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x28eeae0a069c7e77, 0x59ff0cd2072376c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x3d7ccdcd4a2f755d, 0x624e42c84460dce9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x2c395ff4262cf9f0, 0x11ec9d1d7d369f0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x7676b0c87ef67a78, 0x4206e272674a9216, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x223534cd292e92bb, 0x3a0461050dc644b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x38184e636e1b9a40, 0x4f4fbb644de3ab03, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x79ceaf7a5a357684, 0x57bfc0040a733c95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x3a83eff230836f26, 0x5684625342065c38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x371fed9d2b7815c0, 0x4929d2f863729dfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x75a78b1e39c01803, 0x27d37ae6749cbb6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x5fed11f333da3ce9, 0x71d35a7721e0eb12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x32d0b762432fde2d, 0x092b7d285663c2bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x6c5e70e83379c2d9, 0x642a07755505ec2f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x21955d1a7aa95737, 0x22e997322476bf4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x54decdbb056e5e35, 0x2ee9fbe11b640c94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x35f1cd5b26943bc4, 0x5d6a68cc0f62bdae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x520c51841aa8d690, 0x72d55baa6d11baf8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x5468ee945381d0da, 0x61ae766347b3dca2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x075c0dc472c044dd, 0x6994c7b434560087, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x35f0230a6ee3cab8, 0x0ab9c3433a2cc526, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x225d8d91321c4887, 0x0f32b155224e93f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x2cc59fbe75af4f20, 0x46c5533f43f2eaab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x7b1dad553cc1600b, 0x5f56f73f01a46d7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x63559bcf03dc86d2, 0x11072b28310f7ab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #29", 0x1e855d637fcfac0c, 0x1e2135a93561ed54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #29", 0x53517ce766aa91ab, 0x7d15c9f672ee4bf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #29", 0x596ad68831fe0fc1, 0x27444c7e5aad8aab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x20e1da79240d0126, 0x14da4fd10f5af992, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x562949ad786ee0c4, 0x31a98d85433f680b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x6e1e2fe5668949f6, 0x073252b602eee96c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x234aaa01159a820e, 0x049356e6693bdd3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x197708e0386c8d94, 0x1a4b57eb06a045d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x383c39a03917fd1b, 0x3c02332537fc6643, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x1fc28ec6522efeb9, 0x2aeab23a0b8db687, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x042d0e7a7b159103, 0x663b4132792d654e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x1f2292293a31ec66, 0x08885ee1250ee8f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x32a0cd2b6f80a3b5, 0x684e50ff754bdbd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x5609edab7cce1c29, 0x783ac54320befd10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x12689e3724463235, 0x09fada4a795497ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x5cb2bfc93bf710a3, 0x7ff4dd7e2bdfa717, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x750f0dbe0ec6bf95, 0x63dc0d5b14eef96a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x60f5be4e06b7f124, 0x207caff114d19c85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x01cd8227168760b4, 0x0dff01d36522ccc9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x50b94d1b728006bc, 0x0a31b5bd20f01451, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x6200aa710e76b56b, 0x163bf028035a1a46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x0b44d1942e13f1a0, 0x24191756380a981d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x525a23d631540d48, 0x315f2fca1dad6fcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x6d4b1deb2d69243d, 0x498d16e22f0ce39f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x3c2fe3d364788cfb, 0x43fbdd09625a2ba9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x6b307e1f052aca02, 0x772bc82e1d25a221, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x1bb22ab60c7a24a7, 0x02486eea6cfe0046, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x7efa2b63242a04bf, 0x0dee14976c6b77d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x32a0ba2a13dea96d, 0x6fc5921760fad5d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x41f29b0e4a649dbc, 0x19056df23de58bbe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #30", 0x7bb8ab042520126c, 0x5b92fb89144cbee4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #30", 0x528936a907557f8d, 0x4359a2836903c8ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #30", 0x6bce0c884289bcc7, 0x4b5df4980eb91a7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x47b486c92e272b88, 0x2bdebc9e56fe8aa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x3aa1503051ea9f85, 0x43fc8aed6366b17f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x7614a4443f97bb68, 0x4fd22951399b7b93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x537664d6339bbf5a, 0x1a96516828b55e6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x7e005d16422de5b7, 0x669aea2d1568ffe4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x674df8236d0f614b, 0x29b5bec879b9081a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x7464e0d82e1ac5a2, 0x62bcd10939d72ecc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x70a48269746f05e7, 0x489049496032ed60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x2296316f7b2e02f5, 0x3731780738590932, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x4d18a27a6b91e402, 0x1bbfbab15d37819f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x2b299f6b31694e9b, 0x16d2fd33432d46be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x65050df6527d8f5b, 0x6be2a52d7ea00441, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x14ab75123dbec2ed, 0x1409042563056b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x2ace24383f7b4430, 0x5cbe73277bf96d35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x6d9609d27e60e54a, 0x35d09c011f330511, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x72cfeb3136976a79, 0x7f65f2715e3a8c3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x31c56d6e3253501f, 0x1693956d15661ca1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x1de5342109709b73, 0x729d9e407ede0fe8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x3ad9ea0f2dedfbd4, 0x420b56a6490ed38c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x006b8b2f5bb7dbf2, 0x47aed7cd1fdef805, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x19769edf5fa2d638, 0x02e4631115170041, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x1f1e1a6946e10977, 0x11106d764444c318, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x4541eec262ddba9a, 0x6377c8290cb4243b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x19752513018245e4, 0x6aeeb0773811d9f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x33d59603401594d5, 0x4d77f6944b3a9281, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x498630480c23f910, 0x4a18a26951baca25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x3a11f4e46278757f, 0x1ac99db104601a57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #2, #31", 0x3e3051712723756e, 0x243f125c3a7d8013, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #2, #31", 0x06c64ba660a4edca, 0x4f94805457a6f051, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #2, #31", 0x2785f7417f637b92, 0x1bebb36925e4660f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x6241362c1d873ac2, 0x32988a4b6cc7e603, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x1f0980a67251b68b, 0x24d9bff77bb65b40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x32674b601109902b, 0x46f0edc152df16aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x1d2d893b3f637e80, 0x2499e0cf7bed7ba9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x21dbf3ff248ca85d, 0x004d9600573f7e1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x4bb01dcb61517e86, 0x11bcfe32600c4571, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x41f66c50539ee92b, 0x37b335c252766971, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x530264bd2af359cc, 0x785acf81697c6391, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x487a948e7b1e098c, 0x5644499535439ae9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x6d6fc01777eae3eb, 0x30f9f62967841534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x08f474165efd0cad, 0x3a632bde1fd70b78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x1e608b2e1c121d21, 0x1bc487212621fd51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x409ec57e0f1e79a2, 0x7d617b70403c7f2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x706ff82857fbfa60, 0x2048c49e0c4ee349, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x2b9ae38b57201c3c, 0x5ec54cbb32666478, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x021376087227119e, 0x1be2c8097e9d4848, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x6d451b2a64dad95b, 0x33e0e3324a8e0a96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x5cc5bd466c754ba9, 0x32121fca5ab4db42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x4b72585616506ddb, 0x7a8be6ba65ba315c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x32628afc093daa1d, 0x0bdc2ead69d2e384, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x185c23bf4a582750, 0x2a0f62b27301507b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x225421b15e15807f, 0x7f5033c408cc1be7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x35359cbb57154869, 0x3b32805f4def053c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x493c5a07006d30b7, 0x4c8c4d85374912c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x65480a1233e93d24, 0x01d71d5936817532, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x205e88cd0bc2372e, 0x11365074420dc759, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x2212a50933a42763, 0x27c7f8b56bd0e123, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #0", 0x3ce1d1807fb3275a, 0x55a3c4a854753005, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #0", 0x4a0b4eaa46c6b445, 0x47768080553df540, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #0", 0x24dc34c4193c9187, 0x5e0a11276c5f705b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x7051d9f006dac31d, 0x3a4e75985a11d180, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x0747f3d41332019d, 0x115ae443398e33f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x471b3ec10145f99d, 0x700fa9296c8ffde6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x0d0830cb5665bdf5, 0x2e9dc53f6779c78e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x0a09e55828ee6d59, 0x534aa8b12f1ad5d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x28a194b34b06865a, 0x039005da46ebb6d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x11cd3a9f7a33bd40, 0x1c29ac1872ace35e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x13704ec7195ac951, 0x5f0c53b936a96f64, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x20358c6e22162527, 0x10bb40e403c228b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x354826c42d6005d8, 0x3d505cae277d8042, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x2ea5ff7542ab4368, 0x140d7e297c636585, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x1911015d3727d5c5, 0x63dd2d133bae3041, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x6016431e6e590bef, 0x6ac90615231ae6b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x395f924a063049a6, 0x6a069d8e08b7d7d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x006406e65a710ee9, 0x7b64bb304b2ccce9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x73cbd83b12917d31, 0x01d63c4d13d455ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x34a7a25954e6db13, 0x17967e64140164a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x0246e0eb4f8c6315, 0x3b7ee4ec69efc91d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x1237a67d4a305bb6, 0x66532ea330ece060, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x0158317b576416b7, 0x6c9b10a12b48a7db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x45bd22a6386a2c1e, 0x4e638e90616e749a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x3e9a75c5658b079c, 0x6a264c6c7f1cb4f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x3ffc16854c1fbe27, 0x4a4981da3efe7cab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x5eb13b596a6950bd, 0x52d2d25933c7eec0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x3f502bd003483856, 0x47c9536a1358ddb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x52d49b6b639bd572, 0x7d48a6cf41970cbb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x2dcc31295f1efdbd, 0x7283ed1c650c41e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #1", 0x368314745eb87854, 0x1054e9c32f2462a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #1", 0x1722a4727ab923aa, 0x1092d73e7c40371b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #1", 0x60442b4645a66de5, 0x7b5cec0b55bd1a37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x11c62c0d678e693c, 0x14bb96e3204041cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x51f7b9f91bd183f6, 0x5408308c70776766, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x1f19bc4c0118ebe7, 0x03d045181147e5ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x64b4c15a4562dfa1, 0x52def28571ee57b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x2481dd5f674f8363, 0x56fa99a01280f283, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x4607fbb752382c66, 0x41a555275b04f1d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x4cf1501052a214fa, 0x574528ee5d2aa02a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x184882df47a35144, 0x32e7ba612d357b57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x2f31ba80217dedaf, 0x4d75bd232a0eaeec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x3d4f71a61e565b6a, 0x1a8616520129747a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x1f6f475265504cc9, 0x12715a445c692df2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x2ab32c6b25521f4a, 0x4e5785aa042408ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x0ca1a2ad584a5056, 0x16a4fb2f4f3509ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x2a827cbc017f248c, 0x2a39fb9d52a99e65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x5421398662bbf8f0, 0x2fd43e8f7773cccd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x2a5f4a35721f0547, 0x24a948246c69bc65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x139cf2f630fe81a4, 0x16786b52599104b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x4f54dd0f6d2bd373, 0x5aba792f50ec649c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x527c203d7bad1839, 0x2d55928f6ec42461, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x20ff3783098d283c, 0x72e82d0d7d2f4ca8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x61d77892769e520f, 0x4c6456722da0da30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x781d769b301eb724, 0x004a78950c59f54f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x12dab01528770a40, 0x03cdc21c4c3eb021, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x1a960f874f20d7d9, 0x38a86c873d39fa4a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x001f597d7185782f, 0x16cafeff2e33027d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x5eb14ba22c74f9a9, 0x7f1f671a4f74368c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x282211e2312087fa, 0x3e385aed312d6bdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #2", 0x3aadb0367ac10ef9, 0x2e5cb88749214965, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #2", 0x715f6109770c9c2b, 0x76c223951c8528c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #2", 0x272b534f2cace034, 0x28df1e18697cd7a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x5523ea746e63f44d, 0x35bb87c63a060364, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x3d84cc260e0afcae, 0x773ffdae6fb9f9fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x7f9074dd1d0c6392, 0x1decfc783da425a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x49815d3b4b50b71d, 0x0d185c305e41c07f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x7c713f183dcbe4e6, 0x0f6f2c5f71a36f1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x388cf3e03186dc18, 0x3ac4b882371eef4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x289378437c83362f, 0x53a4181729ec54e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x293016634924b453, 0x13692c8d4fbecb92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x3788a8a00104cca5, 0x09c4cef77e5400d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x0f0fc9530bfaf74b, 0x6e0dfad2750d74c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x29075add3fc9f69a, 0x32b19a6a0ea03e30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x0b1aadb77c512b0f, 0x6ce1feb07288b819, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x3a1d0ff51ef0dfb9, 0x642c2736078beccf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x5077bbd1124ef435, 0x3eaadc1e72aa03d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x0ed22a652fff854c, 0x1c9658be790b3414, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x7924399f528ece9d, 0x48c9ffa6380240c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x53939b4324643c72, 0x365641a030ace240, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x305f33bd586bf170, 0x25ba570662a36496, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x1835e80a5e25a177, 0x7143a2c759668e9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x5a76cc86301b6dea, 0x4bef46b4235095c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x4f0c4da369875eaf, 0x2adc82911493dc7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x7bd652e523d4390f, 0x073de0511f840974, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x53d3be5b61593d2f, 0x188f3d880aa87d4a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x33e80bcc7900ffb2, 0x42aabe124cf7f7fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x1d653c25235f3141, 0x7da4da3b077ba70f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x7bcb22b25b62ae6d, 0x6a1f0ba64dc46fe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x39884fe4731a4531, 0x272afe7d14010abc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #3", 0x2335b31c622e2310, 0x3751a07e13ff1c6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #3", 0x4bb581bf2fd0d936, 0x2892f8e5724200bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #3", 0x53a512462a5547bc, 0x11c60a34478bd4a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x0bae84eb14df1001, 0x523451ee2778d0a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x0de00fb37215a2d7, 0x7470c89c3f9690b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x1574d4193131436d, 0x471237c72b454bd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x0c93f1da2034ba38, 0x7909bbbb113ff6cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x134eff6a5c92a206, 0x25410187461c41be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x3ec0c51602ae570e, 0x5a1b5e283684b286, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x327f30443a8cbd79, 0x28c6b3450a7646d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x64e2053624366d68, 0x52021b7a0624428a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x39157d69220ddbc8, 0x2d9d132c70908a21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x14237ea0773952a1, 0x30271ad946f58d1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x286a960e6b4494b0, 0x723ad8f5299852b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x0b794ee960194b0b, 0x3ad8498434fe87e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x3cabed11553627d0, 0x7b1ac9a71ec84e53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x57e47ede7e13b41e, 0x554d00d97b6cb227, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x38a0719857e51477, 0x05e2f8fd0a63af22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x7c1b81df3e2504d9, 0x1087f1ad1d8276ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x6032e0a13e3a1bc9, 0x0e1300ef3530ff49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x35736e6a6e61655b, 0x7c268c6674565f41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x59a5fa0c58c6fb7e, 0x1deeb1fa5dde0478, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x38e0468a0df75609, 0x12dc8c61651f48f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x632d7dd959349821, 0x03e79748758c339b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x57484c3f76dbdec0, 0x70f8e5c33b11fcb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x4ec0f33755fd9d86, 0x4575abd90fe8bdd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x1422a25f3b7e3595, 0x2d6b34a54adc7516, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x79b8515e7c3400c5, 0x000d745f74558301, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x6a956621069a943d, 0x68abe2422f2bbfc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x5f618fbb1fe650a2, 0x0d09c440443b602d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #10", 0x2ddda6ab2d42406a, 0x295aa9221841d645, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #10", 0x0676d88b7ec6efa4, 0x0dce09e1110b2484, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #10", 0x75a2ce641192cd14, 0x4c1d213b5dbf24ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x67906a9b1b131747, 0x6da7e2a24463c19b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x56914cdc0f4dab11, 0x0f4036b17bb30cfa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x0b81abd658b4723e, 0x70088ffb50499e3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x5f4f067b0c7f2243, 0x7f755e02761711f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x2c6572e563ad1b46, 0x3a5272243eb09636, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x10ef5bb064c0765d, 0x56f26c7c5a431990, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x63876601376b5f4f, 0x6b4e3e141766343b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x48fe2c6362cd3ba8, 0x75255906592a3465, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x7de052ef2cce2cb1, 0x1d8df600308e96fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x3c1bd7c21c4a33f4, 0x2c41a3f954719fcc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x74fea63224309c09, 0x24bb3e06479d8399, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x30afbe4c780707b5, 0x3db49590544dacad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x5bb422fb69f0af60, 0x12fe42e45d153131, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x4eb125bd22a688d5, 0x37584ac16ca37eac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x5a11e824792f0bed, 0x0409b2e732388bbe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x5bfc479528f0b623, 0x0b62c02323101487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x55bee2d47fe04f7f, 0x539eab8659dc9a85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x1c2a837353097857, 0x2e4e3a5111daba97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x773a1460172cd3c0, 0x59783e30112929a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x0f33db7578751937, 0x6576d65327e9d2ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x6265c8973c574e9e, 0x04ff03dd6ae7fe71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x5efdd7735b953004, 0x578b7d1d3116ee54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x54c43bf26eb23a35, 0x634f7a12390fbf97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x17a2f0582fbe7fa5, 0x5c1fd41f30c08387, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x2f9ecf2438eb585d, 0x0a9d1e0c6d61d32d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x0bf4d0b558b4cbf4, 0x7f3c8dc44bc95297, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x6fe19fb442695291, 0x5cf27c3d032ee515, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #17", 0x3ade6bc83017bb9f, 0x2b18b7c27f157b2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #17", 0x6c6f0a3e4188f6b8, 0x69fd799b1d443460, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #17", 0x1d1e26bc31aa9cc7, 0x4e5b22b44b6ce1b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x205cd6fc609c7568, 0x047ca14971e262ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x105af50d2d400442, 0x22a2e63637ffc755, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x662b5ca0249e2846, 0x25619a823ff9c431, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x7d52f43a68b59306, 0x0bc316c872202d55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x2b1ee5972067ca2c, 0x754f126a6d3493ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x507f85cc564788b3, 0x6c4a0f1865fd515f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x17d07f6b519ca874, 0x034185bf3cee900a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x0347453b0cd81304, 0x085b71bb34eea628, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x6d74886c4973ef0c, 0x26d108d623a41c37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x76b3f34f01057e0e, 0x5ba3e38c7dcf7d79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x25a3a654498c5873, 0x3dc941aa5cdf4fef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x3241eb79444e8fae, 0x4eff7d4422f69a8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x64b659db7c753d95, 0x102b2e7d5d60d110, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x52bcc649469fa82f, 0x435e226f3535dfa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x183c50a37a7fe16c, 0x72246fb16a8d45b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x0757f471464cf4b3, 0x1f7bebdc1b8395de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x0fc0e3bf1acb95a2, 0x3f27b21574cc7cdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x1bd113b030653c01, 0x729bfa570674d70e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x79f194743253a441, 0x635426fd4174ba05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x76a233f074968310, 0x646b54932c337fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x710bc0a64cf2736d, 0x099450fd5b588dcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x13921b9c02b2dd23, 0x108e6d7243c886ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x7d32be8f4dd1b880, 0x2e55cca32bce6c3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x141ead330679b432, 0x4752021d048ab300, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x214549d46bf32a35, 0x79572fde23df90f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x1c5866360da88efe, 0x2a5468013d165d85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x3ffc334062f66c1d, 0x7e8b178a1649faab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #24", 0x578cef2e4c11cb96, 0x427d7a98369e6730, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #24", 0x19043f032285626d, 0x11f6f4fb4898afd4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #24", 0x25383f903ab70366, 0x0c6136c32c965a9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x0888bbe61fb6c8fb, 0x5864c6de226afe1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x26307d2d204ce0fe, 0x26f5b1201ca76919, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x0c400b336adb620d, 0x4086fa0c4775c702, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x7883f10b03173c11, 0x048c248728987169, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x660da82e015fe6ad, 0x3ee26c143880244b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x4d71b24301158076, 0x6f1e8b7b3d9a975c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x239ae2e312947df3, 0x063347306675f146, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x4d4b815a6b7112c3, 0x130c4be548d32273, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x0b27dbbe1233d1b3, 0x6b3e209355d43d40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x3280b2b13302a066, 0x727ba65a315858eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x1dde02737d5a4474, 0x78ce1fed3ec0bde4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x00718085263b9b62, 0x67592f4d1661f37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x279b820f3e00a345, 0x4ee217ca667f28b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x3f1623bc2a4d0741, 0x2419c010750d3452, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x3ce185346e8f717d, 0x5b83259862b1069f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x5a00844016c249a6, 0x2b8429130a2d068e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x28f61b59527cea29, 0x600143cf65285ffe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x057f8a8f0f4ed8d7, 0x1680b8e95b76ce0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x0ca91d4b0190bb3b, 0x1a378bee235d8d02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x27cc569d08a1984a, 0x39bf80800d1a9dd1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x46a23b9017b38695, 0x7399c6854f67d8ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x42008dd61ff83296, 0x44750cfe05b85f4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x0e87a41313ed8efe, 0x686965eb7ee2130b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x2aafd8a469105d68, 0x090f199968882853, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x3b8d47916431413b, 0x4db0885153a5f3fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x73801a1249544df5, 0x2f1cc207410cd220, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x4ae509311e29dfa3, 0x646a5f220029375d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #28", 0x26cb77ed00dd9bb3, 0x0d43d52e72b15fce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #28", 0x18912249068e4579, 0x4219387b6d6db37d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #28", 0x268678105b8f78b5, 0x732612c95a91b01f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x6f7d07b36282dcc4, 0x5973c32a350e1c23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x4b933a2c6b46ccc8, 0x1d9644771a2ce058, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x4f780e031cef965d, 0x6dd2d455072081be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x6643e4522c97b301, 0x482d53de42f82815, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x4ac192a4506534a1, 0x43215f733128ed83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x5142d05565f385cd, 0x23da4d52718d0a91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x6c81cb465220d0d8, 0x5efabe0f69d3f29e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x2db0498d1dd965e8, 0x4465a2bd13084356, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x005c42ac65aca3f1, 0x48165f7a1d2d5141, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x50f370b9252d05ee, 0x375a31994bef7cd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x421c9c4b1b3d5275, 0x530ffe96206b7ebd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x47d5057626850645, 0x6363a6d22860809e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x76ea3ae77d63bb73, 0x59896e211296981a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x63574140631e60ba, 0x0423a2ab482d0b3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x353f31937666a097, 0x3200fdda4fd90c87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x1440067f2af7af57, 0x62e14fdd62ef7b20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x10a453483776fdfa, 0x001ccc61149c492b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x5ca403e9339bc49a, 0x608bc6046197c402, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x4ed9170f6566e991, 0x020342bf1ec0a034, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x0bebefd720aa8ef4, 0x472120d216ae1c85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x1e0e4a672d68574b, 0x2944b49f02d62abe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x1086b8057d0433d4, 0x4b0335fa01658ba8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x736ad46b341fe80c, 0x513e982f45c5e998, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x5f17976428d2311a, 0x28b564b907aadaeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x60492f157cd2ea1a, 0x1c4724166fbbeaac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x306eaeb55356f16d, 0x5153aeae3ced32fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x38bddaff22cef405, 0x5badd3327f47c5c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #29", 0x437982f93f3a96e9, 0x15f5e24a44a9cad6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #29", 0x6ca2ee3412832b8e, 0x477ff5946187cd60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #29", 0x0f875f62342bf137, 0x62ed59087d29a63a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x684bd9446ba4f48b, 0x42ef8fd202f233cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x147725a626e432cf, 0x0a9d0eb8476370a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x23b71ce908730a03, 0x371f5b5474c054bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x5bc9fb700d5b5aeb, 0x31ad87b95425cb9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x302a4ef0696373ad, 0x536d91631487d66f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x289e0a9620b196d9, 0x5931a14573a3d1e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x3334c2673818f852, 0x552b9f4a1540f8cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x6c44e98a555a2ed7, 0x126a9f0542bc21c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x40ff2363504b644f, 0x45ae55975490c2ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x772f971e53138eca, 0x1bf4337655764909, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x5b8698cd7be4257d, 0x4a369dc41ae6b408, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x093f8068427a1109, 0x6f0c7fa63750943e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x2bdd84b6250a0bf3, 0x4bd86aad3969cf59, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x45bba2cc0239408c, 0x2d0da142547b8f4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x3a5238df7c27271d, 0x69bc881878f06534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x518155f4015adc94, 0x3bac86fd26972269, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x51a640e4171c18ad, 0x7b27e53712807957, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x6a2fa777322d6024, 0x67f6c26048d5d802, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x2e1185a152c90bb1, 0x63bc8c0a45b64045, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x15431cba48df3f30, 0x7d06d4833751060a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x6de94b231dc876a5, 0x70bad5634120a171, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x2001b7327f58b8d6, 0x159c30be33a4edf0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x7b7fdff36841da21, 0x2c9553245a53f011, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x699cb6b67c12f7b1, 0x00eb127a4d0135e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x132f105e4778719f, 0x5f81af3f3b42f79a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x79a5d1c467d55ba7, 0x0418cf9c7d5eb7d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x3a9e6758401bcc9d, 0x4314f81a27b75765, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #30", 0x08fb0bce4fc332d2, 0x5f085d6f4fe18412, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #30", 0x6d8ba978269e5641, 0x1102258376e456f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #30", 0x25f70f17571e9805, 0x2a8944e10d8d60aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x3f60722768cc6335, 0x67e150bb2176ef0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x64df5ae64df9d431, 0x6e7824f228fd28dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x157245d06858f013, 0x64402077780e6b44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x502e4bba38821b34, 0x756d23190f181794, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x789de7d115d7cc69, 0x36cf6efa0accb312, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x659aff3c6bb05ca8, 0x5aae37250198f39f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x124eb2ea23068f72, 0x787d4a915326a8b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x7a25277848955a19, 0x60b4095e3845c201, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x3161bd4e4834d5fe, 0x59bcb10c3985999f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x162eaa2f46c2e2f3, 0x6282c27c16411834, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x2f1bd30603bca691, 0x0e4f83782ba0efff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x3c3ec1c57188768e, 0x3ab907947f4a1ec1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x076042f764c508f8, 0x0a16d1d334dca997, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x507565a12ef2e7c7, 0x36759d366cfb4233, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x51f9773a20d5f445, 0x4021eae762c4188b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x696b4e5e74c68b98, 0x1b09da8c4c1e9eb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x3cfb61966826facd, 0x05a438511acd0bac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x2ee9ddc03f5da758, 0x310e23e0532a0bc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x431a4dea39840359, 0x7ecafbc55e05b0c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x2b0c79e76766a15b, 0x5d4fcf877f590faf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x4c2baa536aab567d, 0x3435b946326cbcde, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x199e3e445f89e9f9, 0x1f67ff121ca10ff4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x005fde3f1a6f030c, 0x7f65287f6b97b57e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x0f358ea43d5a8c81, 0x37b6543069cb2c9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x2581874e35a65c2a, 0x0498384a4c30f03b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x750403831e25f7c5, 0x1f5afc00546b650e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x57a9fb1e0fc0e55c, 0x327115d5381e516d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #3, #31", 0x772786b76bad1a63, 0x3777611c02b67505, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #3, #31", 0x565870e0548b30f6, 0x352331e44353310b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #3, #31", 0x34151aef5f59697f, 0x5ff440ff6ff6af24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x79c86c8b1344b8d3, 0x5b8e64a33474f92e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x509f455522d85e16, 0x1e4025cc08fdfb2f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x587eba407489e76b, 0x552eeb6a7620cca3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x12afdf307cfd4787, 0x4a8c31b24d82bdc3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x0cbe2ce33d18704d, 0x05a10f306a59da4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x28c58ab022338138, 0x6d104f5403e5b39b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x76beb22e272d25a5, 0x4738e4a67f1dfb90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x06868f244aa30f57, 0x6f14aab42ad3cd1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x5de7c82b7d88ec18, 0x5f48c64c004efbaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x20614a2e5e7be249, 0x094cf6df2e870d80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x5305c9b46f340bd5, 0x24a7da2378e0046f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x6c31535c4c03d163, 0x4662c23265b5a8e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x091c41b03d1fd288, 0x500f833478ef8040, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x5f5353c1440e1881, 0x7cd533db31e1cc60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x6b3b3e26201472a4, 0x30ffc7f0561205ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x6ab781fc602e995a, 0x00e5d30d71c1cd4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x5db785727b5dbfd9, 0x7210c8fa489f4a27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x59d9a2231bce31ca, 0x772657a77e18cfa1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x0b023da03d5b9642, 0x76f8d4102cdf6bd7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x095f67a562a497f0, 0x129514bc773390fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x1fc46a796cf84517, 0x7023113c127ba955, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x31065d98755d3da5, 0x445d75b57f17be3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x1571b04a560f9737, 0x5529c4291c419bbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x363e309100143204, 0x0e03690a00293246, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x7b71f1de3feed414, 0x48c87c6d13f5b603, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x5bbd05de090759b4, 0x120e85a4554b9401, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x4662eff714c01495, 0x022affd866bf437e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #0", 0x7764ac854e15e5b7, 0x5df2d47b4fc2579c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #0", 0x3b0e2acf269b76a7, 0x623e00f2172916fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #0", 0x1bf8b44d6b6a9962, 0x1640d5386c148867, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x417a309916598d30, 0x08562426316a6497, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x166dbf357a5c134a, 0x319396dd77b8612a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x3a4ae75e1dbc9cd2, 0x0bae172d11dfb113, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x26c3f686695644ec, 0x672b45141607ed3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x7e1659815aba0536, 0x7cc730bb6d26e67d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x28cfeaed1f273f0c, 0x3ce93e1a757b0607, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x45c2b5b322e4f23e, 0x0ca41d0563de15bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x0e4f8ba05848c24a, 0x4ff29e2461bb6a00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x6ea24f7b44b96574, 0x1325ce974fc9bc39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x3f1578be53303490, 0x47821d6305100eb0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x70ecd1627e1b04d7, 0x16efbfc37960601c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x677149c30c2f7e14, 0x0f684d5917b0c7e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x66e9834a41c0ec80, 0x04d7ae666587a345, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x60e82b8c67a6c651, 0x5b02a94c0fb96e37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x0a8bb88f438a2218, 0x739783f426aae140, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x1bd2e4621b8c19d8, 0x08664b4018db442f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x60457f4c30271dcb, 0x68a500680a7533dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x0357525c26750250, 0x0f85428d1f5af80b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x249007272823a580, 0x18bb5827744423be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x3453239410cc9a0e, 0x0bf4eba70c0150eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x528d868e4c8b9d7c, 0x7188f4301b3ca6de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x343263cd1e8d990a, 0x2af615163375b21b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x6217bb226286de9b, 0x5a20935b3ebe1c5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x7e12f873403e60f5, 0x5799608c7dea9f84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x70657ec017e515ef, 0x085fd3625e5877c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x3e5a1840166ec7f2, 0x7db36fcb73bcd11c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x3e926d7373f5e082, 0x6800f4db62ea1f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #1", 0x04c27a9060746482, 0x6eeb705272e59107, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #1", 0x2d0001fe39184cfc, 0x0e2237e65750011f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #1", 0x57a5e60664e64695, 0x0ac5b33a613265cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x476d25307789e2b5, 0x1ff0822939bda128, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x37c843aa4008140e, 0x37a840ac45801da4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x57ed29fe218c052f, 0x23d89564282dc26b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x37facd2103eb8862, 0x1bea93871647423e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x77e168e5681cd1f8, 0x793161a5768d3a94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x4891367a77950382, 0x6972cb9c7ca3e375, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x30ad507e5eb997ce, 0x53f3e49475913879, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x439fde6376b4206e, 0x56c39e4508533684, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x6e3e032379b91858, 0x4210d7ac0b0d0394, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x39c12c677465b69c, 0x508d2138260646ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x15f1bbcb6a1e9cc0, 0x4e34093911ae5665, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x6e0a25232126fa48, 0x27f598a34dec88ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x0943cc402dec8f1d, 0x4479c38165eb8e08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x2581929f36835612, 0x628f717d51d502bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x153cede01e29d979, 0x47663b34562ee31d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x14ddf9e72092f14d, 0x5e8219a158dccc44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x1a4c09a53476f110, 0x63e9cfd8031bfd0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x28dca7ac77564d11, 0x292243d8540d360c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x6174e9d20db12514, 0x65bb8c713ece6377, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x2ed81f5d5134afe4, 0x0cbaec634f7f0ef5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x7f213f0117fa0e7a, 0x356a9cfd381beb9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x4e7d648c5157298c, 0x09f0ee5824a2d1a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x6f8103055953ce5e, 0x7ad1b4bd63ba526d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x79e6bfab2080ee89, 0x3c971eb1045efcec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x54f7df99309d3dcf, 0x077af9f71432c951, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x27f38ae14dfb8bcf, 0x683fff5d7dd48745, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x5bacb0e3495dd71f, 0x3ca2eabc096874b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #2", 0x1a9287040e5220a5, 0x58e783a80a84d040, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #2", 0x264c2f1f4c91aa36, 0x42a0bbde19b3c605, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #2", 0x1de8d3c339284c63, 0x3e5697a674c993ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x127c1ac2151b04ca, 0x5883e6190d69d6c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x359bf3531943cdac, 0x11c8d3b50c62da6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x49e10b7b08d5a31c, 0x2095a3be0a93d2ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x56d12eeb450b44ed, 0x08685a3171d4965c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x0e691c0c54248eb7, 0x7b3d0b0f327ddfce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x6276af5c7fa36bed, 0x3d02b00f28fba310, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x4c351623010600bc, 0x42af691608c2de7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x3a2e4d1f56105841, 0x7d8c72286a1de9e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x6b2b5d0b09509464, 0x7787c0af4caa67e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x2294621079a2e60d, 0x590d424f20c7505e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x0278892933c37d7b, 0x2b5b234a6c756d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x78cec26859870ef7, 0x5e4a03e85949b814, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x2dab9daf48ca47f2, 0x0bc797e30737de74, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x486db3df72e2ea9b, 0x3033818510224d0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x73e8eb5716719daf, 0x18e52b8714a2ca02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x6c81f5f076487498, 0x7ec0b3e92e173876, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x7f9908fc53cee2a7, 0x7ac1a05857ad52fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x4d71c8b423cfc6a3, 0x7874a359222d6b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x5793441e6cecdc7f, 0x0ea2d8974fea51de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x4673eb7734fba1d5, 0x293409f250620686, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x7dc5e9c707cd6680, 0x5799e4fb741f8926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x7ab0511b1d2701b9, 0x0441d63146339da6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x33989f6859971b92, 0x5ad667a96e993c72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x4fdf902a17721540, 0x1cb074e8201a9559, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x6b40f7e7703c8bae, 0x77c7e8544f789926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x140c52510048dcc9, 0x71a6043238b2c09c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x6d35b94931d11c6c, 0x089d127a6b9f9670, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #3", 0x66ccbe42139b81f1, 0x3c019cf633a9a4c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #3", 0x1b68e8712c0b0417, 0x27c92de66492a809, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #3", 0x493205d0059cad59, 0x2ac645b01619398c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x5f33c8eb2162eae7, 0x04b275fe7ccaa539, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x38d5002714ad22e6, 0x1ce53a922f135915, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x04e9ae947031f66d, 0x7e8bf23b2415f80f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x707ad3366565cb25, 0x5cc8b8ab18f600e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x1736e7914097344c, 0x049597565db08c7f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x5432b63e39235f25, 0x115a313f7e03a5d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x652e633d0d5c938d, 0x62964ddd6f9b9eaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x12f940e60a674e3a, 0x05b4d83c2e60690d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x2bca3921481048d8, 0x2b2b0e46722d09d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x5cbd6bbf1fcc5521, 0x214062e6649f3949, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x0ffe4b8e657dea03, 0x08b5315861a71a53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x4ae3b5287f32b28f, 0x7a9d1b3900791ec4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x3fc9e6dc6f83dc83, 0x5e29ab44621a9cb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x28a73ba942b4906a, 0x601e428d13fc9d1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x501123f7094d1405, 0x03983bc90dd59ee6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x13b462406761163a, 0x3c3607f3630a64dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x2f715f127677d194, 0x55376eae3f7e9b61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x164426b52cd30602, 0x241dd4aa0c2ecad1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x1250f0056873005e, 0x6dd5e52526427243, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x67a5b2ee04e53c4b, 0x26bb91075d34a52d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x746918cf1f6d8474, 0x3f4f41e7276f99ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x622214de3f0472ad, 0x3b6c36e41d105478, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x485186b3671bfb51, 0x2ae5f35e323338d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x4e7d118b6a750c60, 0x153d9db25c05e8f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x60ecddf43fa258ff, 0x1b8484547dee709e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x6c755f0177f32094, 0x0a1d3b6f773104a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x606620f3442f07f3, 0x1d7376ec7ec64f07, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #10", 0x4914443f1b4a361b, 0x5bfaf434480bd3e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #10", 0x3ab7ba8f2ae7a48f, 0x6f7b6dab3d7d5d0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #10", 0x69ec173c0573a4e4, 0x5a8db1861cd9cf6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x6c8fa035644aa5f4, 0x4f0d0842323d9def, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x4ebfb25429c80b37, 0x0e4386e23b0cb1c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x696a643643185dce, 0x38fb225f2fac9048, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x3b0b7e6344510bdd, 0x26dd94f155dfc337, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x088013d130a10673, 0x54a6123e1b719f56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x4beb3c8e52f8e0e2, 0x637d733751945810, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x7de08571699f66a4, 0x0f11b51e06a2f71e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x6f130b887289cece, 0x237cc68b67cc9cad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x56d474c2284dc17f, 0x1a0a3a9d5ba2abbd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x5215ccb64faa7fdd, 0x16af5d7e25942717, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x12c2ddac7c1e4c51, 0x5540b75f3b8030ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x406f582e66060662, 0x115ff4244dce5c0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x16a70cd54cbd6e9c, 0x693ffb6548ef6bff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x1fb64f7e2995792d, 0x1a83c40f62924964, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x1334dfd10cb2070d, 0x693540821d96d4ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x7f3bd5db1f6dac39, 0x0563719c0247eb59, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x47bb6db97499f495, 0x5dea971756104a9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x4444747350e52914, 0x7ba471b519d13a6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x4d03756566b15f80, 0x55516b5c5707521f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x4cb765e20e15a993, 0x24d5ae2e0d72cd94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x5ad3182f70e5fda3, 0x56623993635e72b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x1a7b76d02f25fc9e, 0x45f0bc1c7a8967ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x3bd803ab1d83ae38, 0x18203c9c2db056a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x3cf15a720de2d912, 0x2ff841fb3b13d987, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x027ccda80cc895da, 0x1124242504acc82b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x5dadbeee73cf6df6, 0x1e7e029a46c1421b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x5a80cd76429e4268, 0x1dc8943a2ab13454, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #17", 0x50b3ebfb0e863b7b, 0x382401e827383359, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #17", 0x7f6c391e5087622d, 0x0a96a6112b87042a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #17", 0x7fad5ecb3e30a873, 0x26106bd719e7afef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x5bb456ab7790488c, 0x479806913b856276, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x0573219f07bd6022, 0x76993bfd18a5b11d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x1485f5fc3bd07be3, 0x1d52794807efef47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x2f9fe9d96c79c59c, 0x4eb131627233b4eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x2f1808045508eb27, 0x1ce4e93f0a20b750, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x638f26a23bef90ba, 0x3158eaa97fcbf3ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x0c76f2e751636400, 0x2b52f82962fb5fc1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x0f940c73447b1641, 0x7ce30fb00c2451b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x3c0b5ecd3e42f026, 0x47a9b4286b48631e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x4600504821408d84, 0x03ee143c417e806c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x5d110967181fa115, 0x496e6fb35a864645, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x049966b1699ee46f, 0x4cb9fb300cb0f341, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x3ea7cf96482a953a, 0x16d1aa9133b16eb5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x041a25f45ed05add, 0x337d62b42236f638, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x3033bedd021565a9, 0x053255f9109118db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x46907bea645f1eb5, 0x1cb56a8d3fc7cb50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x22a20edb2efe42ab, 0x2b102e6f029bdab8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x503ed02f0d88cad8, 0x441a5b2468a25f24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x25a86bed0fe2a099, 0x4328a5692d4fd997, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x7981850850d27769, 0x3a00ccd82a41d29f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x18fd0ca31170a409, 0x5df341543829549e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x7040fee65f92a0d0, 0x5a604ad61d173297, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x61a806794a5db5ff, 0x2da84b722074bdc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x2ebcd4b40b4cb783, 0x603c891428388264, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x3a4afa2e6eeeb840, 0x2ad45d1c515ee390, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x7c7783187d29e81d, 0x3a0142b40a89ca5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x0d0c88b671da70cd, 0x37d9a3f5221fef06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #24", 0x42ace8362a5502f9, 0x4c61c1a5068e0dbe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #24", 0x3bc5a7021917ad32, 0x3eb7625c5ba9f4d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #24", 0x78aa4e02266972e2, 0x78c127702c06a5e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x70c728e12cb7ecc1, 0x4c7b63ad5a52547c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x3804a4452d5f33fc, 0x028ad6e01f83fd95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x1c4dec3c2ae423d9, 0x70e2e125724f9e73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x280e0bf634b30cc6, 0x7cd968d118c56f55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x268d7d9307472000, 0x3ae55e5b351a94ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x319c22f97a6004c6, 0x3ba8a26a693a65c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x1377b1f93da58212, 0x44e45aa26d61c9fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x640ef4f465e3d392, 0x19686fe50c21fffb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x129bc05368ff2b57, 0x6674547754d61dd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x165e5f53653cfc90, 0x745a1b6b4aa06498, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x1021206a39c96bdd, 0x3cf0030c32ac4b90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x6e7c78a406571940, 0x4b71bae5382f2c60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x0d9e394028f26377, 0x6d49c10d1509f637, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x2352683e4328b6a3, 0x7e445c013f3a5c39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x00ce38b64604961a, 0x2c9c263536ca1a37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x2be869ac29606eaa, 0x42ec1a3264dd2daa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x125f9a012e0d66eb, 0x39b34b803e842a00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x134a637b461491a4, 0x09248e9828bdf955, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x7fddfd8226dbffca, 0x5b6a44e5236b83e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x2d33190a48e47153, 0x5b9ab0466e5a7626, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x71d6d4ca01a8c85e, 0x03646c5d3ad1524a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x44d17f0226a7d4b9, 0x7a0bae8315293d08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x6cac6ad30edf7172, 0x4bf3573f459fb7b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x383fe01c643030e2, 0x2a7ce5621894d480, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x123d97cd603d8d18, 0x5718fe804a9f7a1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x26521ebd4ec7b857, 0x735d73722587fb49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x75a3b821248e2f74, 0x48f37f2e26301c3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #28", 0x6d72a0c717eefec2, 0x148a926522d6d12b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #28", 0x1997c72157b3d1f9, 0x5da823755f497592, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #28", 0x7e5ba6b2406609da, 0x7472b29a5e694623, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x4f457b4c4e85e33d, 0x2408fddb6b081185, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x32b614205ab5e485, 0x039ce60507855b68, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x3af3719e458248f8, 0x5224d58544f3abed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x144a014f336f2665, 0x6a7ba7366145905b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x57fd55d91c003eff, 0x0775ac9a09edb971, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x33ef3dc10a6cae12, 0x2cc48a9c456ff6a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x6220800b192c1ecd, 0x24b96c334d8704e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x599228a74ff948e0, 0x2bf04b05607c26bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x1e7f2c1e4f211e48, 0x4b84384228d7a3f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x29d702cd0281d4e1, 0x305cff5b5135403e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x48041dd900a49362, 0x1628ec2b64ca746b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x3413b9c74d85b160, 0x461004c65c4e1f28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x6985f05f13006336, 0x663bd8990c110fa0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x1d6d1148763a7274, 0x518106411d752e21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x0f66914216ec7e09, 0x6afc33037f8d9153, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x66e5c6e92b8df052, 0x6009b81068f8b9e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x7aaf0e9a422d5d38, 0x11d05ddd0564f307, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x44af32196cc31f71, 0x569a334524861168, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x6d67b2d34f608a9a, 0x095085d30cb34ff2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x1ce63bfa4f3d47b4, 0x69016f1b217b6c9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x623daaea7f0d827c, 0x2d8c7c3a066c2c5a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x7547f4f00edd8d7e, 0x23e15a7b7faabc32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x25ca0b875f420595, 0x7f384d8504ae8632, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x0acff5e87f779df9, 0x6da7401c0cafd271, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x41a4fb3168aef8be, 0x1214c578057f0482, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x5572182f33559bbe, 0x2a0515ea06542d4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x02b626587c08ec58, 0x13077d3d42d9cb02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #29", 0x4b46340d11e1b3d6, 0x6455379c1f9c6252, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #29", 0x10ef365249e9e927, 0x26088eac2d83def7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #29", 0x58c776a62c66e8af, 0x2d2e9b2a06372b43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x0ba8ee45788cf191, 0x0ae5b1757e91822d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x78048f8a1d561a17, 0x0b41549e1678e42d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x060512d545fcfe9a, 0x1bf7e8af39a98abc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x79529a5853053544, 0x3ffdb8075b772b04, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x4f0e219d02a62da2, 0x1e50f6067c08c0b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x1487e17841adb1af, 0x1ba523021a5455aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x0b979ad67506cfcb, 0x47d834a1257717cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x216db87b3693f483, 0x2bae430e645f117c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x2f20e6156e31e848, 0x62f093aa2d16a6c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x0b88025f5f87739c, 0x438f8aed2725759f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x2584723620ccb862, 0x60cf005b118d1534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x73d1eda70b55363e, 0x6d0440381ed70c8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x0dfb63e03684f041, 0x1adfcd3e42e00f44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x7832a1f0250c998f, 0x5d3464ee22834559, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x1a13695b73a8a032, 0x47fa5d2403ca3cc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x2a3c94b54b19e1ed, 0x68294e433b8121d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x394bca352c275383, 0x6897c896595d7aca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x0baec71f6151f0c5, 0x0082f06a44d3cc95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x021ea92843652202, 0x5660e1c931333956, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x4eba58406aea1323, 0x500a45e475f096cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x216f036416050b01, 0x38d0a6135cb5bc21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x3b11a49047335e9e, 0x7f39017a19a1a554, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x3adbfed00595305d, 0x1d6be21a55250deb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x50af124a793df857, 0x10a62fc165189385, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x25654bda3ef8feba, 0x3e760e5009fadc80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x204aef7f252f8ade, 0x4ecea915311412fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x6894ace032519234, 0x62474c50226998a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #30", 0x1d3ba557512ad589, 0x185a2f76374f0521, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #30", 0x672fe08a133dc2bc, 0x1404c1423eaaa8bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #30", 0x5a71215a75b8302a, 0x584c4e0f2241851b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x7b4d6087080cc2c8, 0x77669306154d202a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x014abb1f38dbc1ff, 0x7a65b3af4bfc72d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x77d4c0b924c5f867, 0x55f74f5226b006fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x49f583453a0b6644, 0x57c419f4181fb039, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x6c5cf87852e37857, 0x3a8948e0328a3026, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x240e4de07dddf689, 0x69d9354709989dd0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x111bb945208f949b, 0x4843468b0b3e2e6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x1647c4c524e6468c, 0x2d7fb3866b8cda9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x2cf309547b3fae78, 0x00d9fac91195254c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x341b70783388e770, 0x5d91981e2e3dc474, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x584edfd72cb1e562, 0x54edcb6e2bf03131, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x66bd4ba67e992a4b, 0x440fe16a2244631d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x517ca2a23ea7c88a, 0x54ce9343531a441e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x3c85bf1324f6287a, 0x5cb2e1ee758af082, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x4585bd152e48d273, 0x00c91eed4da17858, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x532f19003a084dc0, 0x392e52f75bcd81da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x3547fc384af43f45, 0x6d62a72600222254, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x7e7d26b5034db236, 0x2e5fe6c869636cb0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x2fff979859637f4c, 0x15539de256cc068d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x57fca9974ddefced, 0x791069aa16bce33e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x0c86c577468a094b, 0x69d7275d29794c39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x6b8031c51fcd5ba9, 0x1f043cbc490c848a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x4e162e1d4fdc4fd9, 0x16adfce23105eeda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x09e49d997a3617db, 0x0cd370b42145471d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x452a57204fc7503a, 0x216769713f2c99d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x531502703de3a464, 0x2890068243a77dd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x174723b01383ee0c, 0x1a73846203149a09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #10, #31", 0x6162eaf903a8a4a4, 0x19d17d476f43cd48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #10, #31", 0x4a32adf037c1563d, 0x18bd19816de9b070, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #10, #31", 0x578eb1e74da431dc, 0x36f634fa35b2dfb5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x1d8081b5738c3f44, 0x66b8ce9025a4e004, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x6dc2571f68519092, 0x46ea272127651f4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x3818e0cc0f21bfa2, 0x6691b92032ecae3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x4d0564061107b077, 0x76942c150b2de33d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x248b9e842813fa8d, 0x0e427d46644c87b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x2bbc9f326c4d6e80, 0x539054fe05ee897d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x240ec4bd2ace6ee8, 0x73d839ee75ef4d22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x7872a0c5125afb67, 0x2ba22cd77b9d76a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x05e73aac682c7dc9, 0x214256a815f3227a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x507e0e5c23e9fae9, 0x3d5841c973a991cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x330bba8b1d2a6c20, 0x2696400b0896ef28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x2e321c9722074fab, 0x13c4d26500111e91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x4a1b4a3937edfb46, 0x645da64752bdbb1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x243b69c64c847e87, 0x58ac449975d7e96b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x7752ed6f17696364, 0x6bc7368d484a2e83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x29c45ecc6529fbd0, 0x43e7a5286fc58e34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x4d56799a4310f278, 0x05b8b0af2fab9978, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x66faed6149eb6b4e, 0x23552b431dd487f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x6715d76e3a304984, 0x266b771e1a06a7ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x5c37992f7e756cc4, 0x1a17c67d1547f406, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x3663680a40b1f3ba, 0x6805af212652e368, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x0d36724107f20360, 0x1c2accd35a9ed1d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x1f5b66c566d0a57c, 0x22e9005404895fb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x4bfaa14c7a079e94, 0x744eede5491fc591, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x3d18910c1c208a4c, 0x78cb5f0919511ae6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x660bf59b5d9119fb, 0x3725a2dc24137e6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x17c1637f5831ecd6, 0x3e1a26594d21cd09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #0", 0x56a7599b4a6f7031, 0x6269c10f73f8fcae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #0", 0x0b2163eb3676acea, 0x1a4be0170d0ac1a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #0", 0x3e68b04b0a9293ca, 0x67a993761857d62d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x71633946113023c3, 0x1ce135de5dc41710, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x0b37c2581faf3baa, 0x26e3dca13d5dda92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x3bcfc5f60dd49855, 0x56aef57948505364, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x6b65b2502a7df82b, 0x6c63d1d221dbbb91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x02afe502516749aa, 0x6efd889b032715cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x1bd6b9db116bf295, 0x7720127e59573e9d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x47e29f7f4e0b93b8, 0x6662004226f81dc7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x589e27825c3129d2, 0x3f4ff3f4064b4fca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x6d614d950af3437b, 0x640f66da4a0160c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x2aa27f255e0e30d4, 0x075f3b5b78990fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x6be2c9292d4d3524, 0x40e963526672451c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x57cb2d4f774b8948, 0x084e00ad57487b7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x48b2d2f3518fa3c7, 0x5a6f91495a7b1251, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x62fb965c1a345131, 0x33d250ee64898cce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x683fe4e94ad19e89, 0x0b81aa952ade35dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x2702c85b1538ec81, 0x312985a640de0c6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x202c2ffc123ea88f, 0x0adf6d34146415f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x704cd9634de68930, 0x0cfd25de4aceaf22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x7b33be54398ef4eb, 0x3140f43e5c2fa28d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x30da7e340de7af50, 0x33781e0752feeba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x5f775318614c4ee4, 0x2d79fdf5798d5127, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x7b80a0156998888b, 0x5e16ddf54272e974, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x346a27141e7aa4f7, 0x6d511f5063c084fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x33b391782f7dfe9f, 0x249e916a5b6cef70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x41bca72e7cce2b3f, 0x6fd1056153dfc174, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x4ab4b4704fef64d4, 0x1eae709632098092, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x097e59c041b14126, 0x0e39231f45e872c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #1", 0x4f98f07646615c5e, 0x18e75e683a58d7f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #1", 0x27adab4211fd0710, 0x33e6291b2f10438e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #1", 0x7b958f9b5ed44c53, 0x71832d03232e4b57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x7d4ef14a2b8d61c0, 0x06eed0552fffb6b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x5b0b605f7b3dab81, 0x0b6ca620310282c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x780bd6c02390b4cd, 0x04e244371cc8078d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x738019a25d0aab3e, 0x4ed1881f42c08b30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x1ebbec6421905c5d, 0x08a8fdf57cfe7362, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x67f1b8bb6b3d7471, 0x37574b566e54dcdb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x7d3a7b810ee84d6c, 0x1d6520690f9f63fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x6dbc99c039bc7faa, 0x32cdaf5478d00b1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x6549e16a343c67ed, 0x28cfc1cd6b0b8b0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x2f7a136e20f05204, 0x1c0e0dcd405541c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x448106d12beed176, 0x5d1d49562785ea2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x08f97cb472ef7354, 0x6a46755f38012073, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x147fcfb16c56df2b, 0x34ff93d527b56919, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x5794539c336f665d, 0x160a45f47c71886d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x4257b3ca3ede9bbf, 0x0c10ec6a54cecf1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x789b1b69766e9c08, 0x4d9eda3b30144d8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x2aab03f5372de661, 0x1b1fd8945de4fcd3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x581e38657b5787f2, 0x1e3a3e9c5a251763, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x274659686bf176f0, 0x01ab01911c9f3f37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x5ee0ea44099ff380, 0x54a05faa303fd61d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x75f6d2ab6dff852a, 0x57f53f367360b9f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x216eeb877be32ecd, 0x6fd242634d8b2648, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x3ac1ca8c6ff8cfa1, 0x2259f56663c69f51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x66676ba92efac570, 0x13daecdb335ce5f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x6628abd12f7c2164, 0x1141e2c811126f9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x2ad3a9576ce28892, 0x6b3787013e46e437, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x58d3ff832f868318, 0x5ae6236e521a02bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #2", 0x392676985a4f1812, 0x0259d8dc37b4e9c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #2", 0x484e9d3c1ae7e620, 0x2b15a3bd2f1d4944, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #2", 0x16cb14ee1f0264f2, 0x7ca86f8c69bd88c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x0efb3493615f14f1, 0x4d842815518cdf7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x1059da61162ba838, 0x04e9c5707562a03c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x45a7c99d71ac96db, 0x06750fda76828632, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x5e8f1f6d0faf8dd7, 0x34c96a69707b72f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x3f3610f044ef4e90, 0x429575b337631ef0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x1f3e66a21a2dac75, 0x6f1808b8785c8788, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x3515929624224058, 0x2779d0cc678d03df, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x4324a54a1eceb4b8, 0x514a8ca34be0a784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x002dc9a922574c6e, 0x1d6d86fe521fd9dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x3882f4a74df789f3, 0x47827a191087a40a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x3fa420ce3bd394a6, 0x070a2a3d7e2abe44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x4b83227e313ba6eb, 0x6ea631381e33403c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x762af57b44ae67e4, 0x55965f2c0ab9336e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x5edc145a2a8f8bc3, 0x0315baf615695c1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x4eb1cc1b4e40eca0, 0x7cf65ffd13f1a6f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x6d0fa1587d3fd572, 0x5fd24e7411d67166, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x1f9721e12b78c55d, 0x63f64b436d3d6b02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x79704f5004cf3949, 0x7dc50f0c581a1688, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x40a2cdf044eb0604, 0x5644d4cc3914701f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x7626acef2cde0f87, 0x5747b05b0c25f06e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x718c776c19f4ded2, 0x16df23dc6c51a26b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x44846a957eb15e86, 0x01bafe8950688bc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x4cf24b26442c812a, 0x645a32b6133636b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x416c569c0902f35a, 0x250ca8173a01ec7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x347bb8b72504668d, 0x273f57806103787d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x29d39fd60f6263d1, 0x391d8f052dec0808, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x544d69d53e482882, 0x670078276a766dc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #3", 0x6b2638090d7b8210, 0x769c5e344a7416c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #3", 0x277060e33880b7b9, 0x36c5b9305cb2af75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #3", 0x3732163f11756df1, 0x2d1b3b3b6bf4cb78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x55a1ef1b2437aa40, 0x7f2b022904246165, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x2d3a9d9b6565a564, 0x3e264de3170e45b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x0a6a0bf1312f4d3b, 0x7811be3561b65652, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x4091b10c76a2d681, 0x0fa25e5a343dabc7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x34eaff03155077c2, 0x1eb4198e14df1ae2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x22cbf9d31618ead7, 0x5f5331a72011370d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x4e99a29029df21be, 0x7cc3e6824a3c5ab6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x3b548faf355c2858, 0x3631262e05cbb8cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x5993d29848166817, 0x09f01a3410f67ecb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x2d7c0d7b201682b8, 0x2804c48306ce7033, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x5145cff3782724e0, 0x6884c68637e6196c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x6ec9fb620ad7dec2, 0x6c23c53411d78100, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x202856840609cd89, 0x26b69be223b4fa65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x1c22b860408a17f5, 0x43c6317242f45057, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x6a6939b34361d13c, 0x0d30ab0d6abc5af0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x78bdf9947a782df3, 0x708813bf25bdc962, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x428e960a5eb90cb0, 0x36b4482d5251cc2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x7ecf8f6941a502e6, 0x59203c60700aa386, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x39cc27c614148226, 0x27f0bcf250155f5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x1eec60e808a37c3e, 0x61ece05c28962328, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x0ead49c710114f00, 0x4c4b1d8e3f14b76d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x509b66f50f39b2d2, 0x020907c42ad00227, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x529b840e061470d6, 0x158c5d173b04a0a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x008c9ec91776b238, 0x60c26a0b4b597da2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x762fbee976cb862e, 0x1dab49ce431b34d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x387089145b16954c, 0x3325d85a74ff4e52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x6f2b177327018e0b, 0x4514adae723cb0db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #10", 0x2fa50a49671df191, 0x1ad2d4030e17785b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #10", 0x772f40924f35378d, 0x4d2c2fc83e525411, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #10", 0x5e6eea5f7eaeb350, 0x6922563847caa787, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x04c324266391b23b, 0x02cf4830310a6e6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x7b0864731a0f35dd, 0x7c63ec0f054fc2f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x10dabc0c7b90d01e, 0x486af7c47138235c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x56a7656a2b4c1f5d, 0x663771ae494b4520, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x524dad68565ac9ff, 0x3b87f5fb45d27cdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x3d78bb9021162501, 0x53e9f53901f2b7b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x704b5c8e296761fb, 0x40450bc234a7fc22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x2816154b7f41ebda, 0x7c72a3aa4eba46ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x62d39e157c28a169, 0x7fc4b55a2cd93971, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x1637d7477a93f425, 0x3228fc615ddc0288, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x7624c443354b9793, 0x4f1425e527129353, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x6097b6f02be5ce6f, 0x705dd8734ccc29ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x0240986e66889bc4, 0x129ea68b32e56458, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x079ec0c6751d27cc, 0x34d81c0a3fb953fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x1e8489c770d3f3cb, 0x7461502177ea1d54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x7015dfa54669199c, 0x46a46442469a9f12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x4291bb06259cd4e5, 0x7373d88452e97dba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x2030c90b7fd9a627, 0x30c5804258c9924d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x35253dbb7039fe13, 0x7fdc25a016558d4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x1c1fcc8275c05d88, 0x6321b6fc15bcf4ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x5c48f94c7d7a750e, 0x48a259041e6064f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x72979cda527b0910, 0x5e19b8ef63e7ba12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x434efcdb22763ba9, 0x5bd1d767111c26a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x68df55454b2a9e38, 0x57b6c5b43364dc80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x70c7731e3713da7c, 0x064e5a3a2b71104b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x36ed80a40416c838, 0x043aa29810f83c29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x7450c64c0a6f8074, 0x274dc9776c12be5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #17", 0x002fddfc4a720c0e, 0x01cfb30a107092ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #17", 0x47ec811c0ceab0ae, 0x2ed0f7bf5c78d748, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #17", 0x5f65b9be1c3268c2, 0x4060915b3a841df7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x3ea8a46b23570a4d, 0x4ba0449922b4b699, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x6e81a8865c67ed53, 0x561993192787f9b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x137bc7cf5733ac94, 0x52f909fc5f491ba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x5b4a74cd178f2144, 0x704157cd4a694873, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x21fea1b8384bb9dd, 0x367c06d24f9b3b19, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x02bdc5eb0edcc5a6, 0x600bcde7222e7fb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x1bc776543f07e858, 0x7ea756fd4aaa4708, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x5b3a511a50cea998, 0x052e64ff7b2d3012, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x7425b3e573fb79c4, 0x1de1e6ab19e2f585, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x506367171463f931, 0x416aef3562a75c6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x6b97a5c63231cfdc, 0x41f0780f63df2ee7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x49c0f12164c47e2d, 0x2e48775a46e21a93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x1d10380a76892393, 0x167d55ac6bbf92d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x0565e93a0c95698b, 0x0dee128e1fcdfdf5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x4b9d51e36fa6a9fc, 0x6a7844fd212d5f8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x407553943a3c764c, 0x1c5a8fa126d7a2fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x2e37f011022587b7, 0x40ba9882349b077a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x168980e95932dbf5, 0x174263e57e9b5728, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x0b64abd110c2fd6a, 0x627a860f022126af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x75877b975f8096ee, 0x4903414255259cf2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x5609ba814ed3425a, 0x40e52fcc1297b3a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x5b68abe51cddf694, 0x3265b1965b6fa3bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x0c84a09018f792eb, 0x7c9d034a2705fdc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x533409370e983947, 0x4ddda0c54cf9f425, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x10bdc0fe18d75f84, 0x0194fb9f016bf948, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x720a3b796281d680, 0x00075071274741e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x7344d3ea726ba9d8, 0x296868967d6ee74b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #24", 0x51ec40c61379b409, 0x5294843d68cc4f81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #24", 0x624cf6632dc9b4b9, 0x7b64032227f5fb48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #24", 0x4aa7ab4d0002a24d, 0x03659f033db5a248, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x18fa3538329940d5, 0x64bba010572c4bdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x41317a1c25bb3ba1, 0x242640026c2e3e70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x3e929b266da18829, 0x6d9a37b851ef3b1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x50235eaa229ee599, 0x79367d02309cd69f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x150a8f7100a04228, 0x2e0bbdea43683294, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x1419f63127988538, 0x2c34821666f6d038, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x556239f112526a83, 0x0eeccb807666ec95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x12550cd118d82eee, 0x341c8edd2009e53e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x4b716fc31b5c711e, 0x7736311c2b4f4209, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x4117acc00517b832, 0x177d80790ca2e9e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x72b9405b57c8a1fd, 0x5e9224fb7faa47e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x7a6787965e52dc70, 0x30471e8542dc9f05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x5ef31e98327953b0, 0x0644d19a0f721708, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x5a11d8e80555b2c0, 0x7668e740730d14c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x17a81d431d90903c, 0x6974015e2f7412da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x3668bf2a46b42934, 0x4f7df81829fd2a14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x62109a536cc9ec97, 0x554c6c1e01da2eed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x71e1a4c96d0f3dc8, 0x0e7d18cd23284713, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x44d7dfc65319ad7e, 0x22d28ef9649ae525, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x316c89ee2dbc55c4, 0x2777842a3f3f675c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x6035a974451a65a4, 0x4eb17e64105fa886, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x4a7018646ce0beae, 0x036cbd503a47825d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x0a714eea39398d4f, 0x69bb9537621835a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x7fedb6846161cbda, 0x0c155fbc40da0e14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x4e2bb872513155cf, 0x42b43d0261fe50d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x3e40939827f926e3, 0x052697ea400d5d3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x7b12d4614c1fc68b, 0x24a842600318735e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #28", 0x79dc1c4f1109591f, 0x4257daba2c7f5e50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #28", 0x5623bec3404bc426, 0x3cdf06d65a11c5c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #28", 0x2d2c82d57e14dd58, 0x145948212093d728, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x374e6aa70ec16c8c, 0x02ac0cd0379dd1bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x702338673b2c1cd6, 0x7877dfd4373c212b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x0c5d72a51e6109ec, 0x193a72023e4ef0d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x465a30cf23049075, 0x7e5c4e144a9e063d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x6f245700100e5456, 0x4db6799b416d0531, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x2117ad752acb6a57, 0x6dec63816900734f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x6b172e7e576b8134, 0x43123913773b6c38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x55805e8c1a7b5030, 0x17cf43601843b153, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x293cbcbd485962e6, 0x4fe183120ccec934, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x03857fbc5d455c62, 0x440aea5f195ff524, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x7ba6664e560b3411, 0x57aee5fd0fe2f262, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x790fc4862837723b, 0x5a80f89f4200971e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x3845c6917159ffd0, 0x036d9c4f68341b86, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x1c256a271446c7e9, 0x51348ed6595d7406, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x6bb2491e6868239f, 0x5098e03e073c98a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x02e373cf6f61cd0b, 0x1f8049f84132a7aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x37bb2ff1120c5b3e, 0x4e0170de2c20308c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x6f51b7a01d2f0bad, 0x458025b03b40afae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x733a3fbf25a49aaf, 0x4b23a2106af81dee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x4ddc0cea3066515b, 0x2cf8b50c6c4a0445, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x21c0512b25b2aea2, 0x547e1fcc0621d37b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x39f9768b301827c0, 0x5f7f47813de5bb53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x18804b5f64a29df1, 0x452253f825abbfa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x54046afc34dfd832, 0x66de67541b63bf2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x46ec33700d04156b, 0x4783efbb0bbf9aed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x2a3321191223ecab, 0x47004a9b363deb10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x37c8875b4e2ebe0b, 0x213608ff1d6d60d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #29", 0x7e950f675e3584e9, 0x09b7651d05a49445, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #29", 0x03e8338b6b45af42, 0x0bc667c120556092, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #29", 0x1b5dd702235d6fde, 0x5e3b1be53de1aa17, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x08000dcf4a6bd114, 0x638d69c033de2261, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x7f4ba94716c5d14b, 0x4f41e1905c0478cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x23c9e6b62ec45e54, 0x67c413b84637dcb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x40e84aff1dabd0c7, 0x7c75c7c84dfd07cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x6bda8ed27521cdc5, 0x6b6a68a778b0d25a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x535752ae0a1bce61, 0x7e5566a06a6f9e39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x75617da369001ab1, 0x0ac4fecc573f863a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x0c5d8a8f78ae9a11, 0x1521305110bf54a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x431a6b2613df5897, 0x449d7707145d985e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x2aa529e2582624e2, 0x706211294266146d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x06ea83360513b8ec, 0x089df1244e6f1099, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x22bf89b307d68110, 0x1c6c186847d2ce35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x7cf84ed53ed90730, 0x4083a0900e9a1886, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x48f4d59103ceb58b, 0x7909b6bf504fa183, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x6cced03d3cb0580e, 0x278f27bd3e565334, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x355ef22013b31ee2, 0x4f15a7da792c5acc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x279277797dec0454, 0x0d89f32b78795d46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x56122936437d62d7, 0x3adf71b35237a15c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x48911bc43d12ca5d, 0x20a6b1f55cfcac6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x44e94b6d65531b32, 0x24cf7aa26b50a577, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x242c226272f474bd, 0x79eabdfd41e19a42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x76c32a4839c06383, 0x12313bc66d20f7f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x7670bb927a8cf302, 0x2b774b276391fa85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x0e4011e46a48487d, 0x5cbe55522bcfadb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x68344cd15f287cab, 0x24490af835d2895d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x22a5df8228b0dcae, 0x080a2ab93e467608, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x65c3a70c40129d16, 0x1b4322746b36fb46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #30", 0x2565b84850725ebb, 0x5687a0be2aacf279, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #30", 0x4366d3787ebfc882, 0x6c8e8cbc4991daaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #30", 0x38802c05622a1dc5, 0x36b2d29d3a29fdc1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x5cb710c77a7a4d98, 0x1dbbf8462ef0e797, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x64c296157f09a041, 0x5ac095496af722ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x5e321cec28d3d6c2, 0x20c9ac084cf6e2e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x5184b37026807b63, 0x0b3d58ef00d7fc6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x6693187a42969873, 0x6c0ef7b537485a7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x1308f72f4e83d9b2, 0x61f54cf60bf8d0c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x4d43a2340c3d7e0a, 0x558aab6d566fcaa7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x6e679bcf2e55c0af, 0x1099c86805c3ce39, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x28d00e470f754b1a, 0x34b4b5d14b1eac96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x0e7eeb5c56df7b4a, 0x3615cf410d92a45d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x7fb3520c65c6e033, 0x5a8987446cb10848, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x0c475b965997fc6d, 0x6d8904b75138057c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x1c2e94e06a75acef, 0x08805ff972da7410, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x38f986a1545df040, 0x7ed344d32f378c0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x609b6e4a16411f1f, 0x05a756b7063d28d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x4496dfce40b5acdf, 0x0c00f70e4f030a1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x502af7fa503785f2, 0x1a21b6b06d66ee16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x2717013c558319b7, 0x7af992735ea9e356, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x3b49f9ea38e3f056, 0x4b5aeb9e26ca5348, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x127becc30082b8bd, 0x780258c447915580, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x6af865ac393f0e64, 0x3a6bc9912eaa81a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x0d9cfea46389646a, 0x5de20db323f1ec4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x79ca838936300c31, 0x2a2f15226e386cee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x76e5b910575d2db9, 0x3d3b77083e616358, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x2794b3ab26c1e3e1, 0x2bc8516e4710b10a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x7c44fd9871157fff, 0x25ba94604eabb4e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x29f970556d7860f3, 0x7576082f378ef782, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #17, #31", 0x6dfb19b1398c1693, 0x7f204d023c755d18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #17, #31", 0x72cb24f74901ec6e, 0x6b1fdebb58f37f5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #17, #31", 0x2c8b50d8271480cd, 0x7ce56bab0068239b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x5d448cfe2bdc0792, 0x6ea0908a2655d462, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x0339354b107f8928, 0x64b737ba542a460f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x37416d0940f58b7a, 0x1b3af7192acde8f6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x320b0b796eefa60c, 0x79799ddd33866aa1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x5c6807006a35af25, 0x6b1562235c047bce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x23c1c5b90399b7a1, 0x1879d8e64a6320b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x4c9ba410203c0bb9, 0x2356a00e168ceab0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x47508c8705959ed6, 0x16f50e4c7926f4e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x3171a66804340104, 0x1f7cc94a24951985, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x14b38a2c13fa56ae, 0x78bf5f9434aadbb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x54efe22858f26288, 0x5f78c4aa4bf4f735, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x47e208946a90c3f9, 0x7f7b61d606faeda1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x54c6731f7b794255, 0x62ff696f244a0f94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x7f12f9f61203d054, 0x6ead3045788838d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x323fdc0d260a31d4, 0x0f1523884bae9e06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x2b9fd0aa64525c39, 0x44d592ef79906894, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x68865d3e16e4e1ae, 0x1e25821a5d117713, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x2adf385c71351771, 0x11bc52c77d39e76a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x4a2779f948aa4076, 0x492edea07fcf1a84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x333b047069c97194, 0x06ca08251209828e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x6542b3e92500c268, 0x365392220801778f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x370492bc0f9ed3ef, 0x0089b0676455ade0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x35a905c474d9ded5, 0x30044be669446ec9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x592c3b0f00fa5978, 0x62d4d75e6148d66e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x17df3b265016a048, 0x3e5a4d8141b2984d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x414bb7ba081b5e57, 0x3eec7fb742be7383, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x50c59ece4957962d, 0x428d8e070b7331b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #0", 0x332107c153d04664, 0x1d7cb4410400a33e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #0", 0x78d108cc0c8bcb34, 0x0c021acd1863bbab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #0", 0x1c2a9f232cbdb571, 0x7cb9698b2fd59b88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x219794477beee1af, 0x191a0a5151d3a4e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x7ce93b277176c8d7, 0x331c7b567ac3cf56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x418d69207b62e75a, 0x3c7667a314c8764e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x037e45b21a1477d8, 0x5786e9d102d920da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x636c0e052bc906cf, 0x0e4c528d5443e480, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x7f994d336446a28b, 0x584487be168d15c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x70d26dbf2baa3afd, 0x2ef0d172786a55ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x5867f06e4159fbd8, 0x283ff1870cfd0ce2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x3d48dd8811ed2d20, 0x5ed0b1ca79ff84b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x0363f5f73139bbae, 0x74c3540b3a3218af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x2c9ca309268178ce, 0x4efa8efd44f15f17, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x4095f0a75616d27f, 0x47ca7ff1301ae8bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x01dfd94e5ca354f9, 0x045ecd3b2401feac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x40e9f784697fe5e5, 0x3a8f147301792681, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x152a20e222236e07, 0x79e37c8031bc6543, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x637d69df1d8a23ef, 0x3eb972256d921151, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x2f77510f5c54ea12, 0x6791960620c64767, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x0d8ea5c029f2ef14, 0x5af8601732db4707, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x507467e33f972610, 0x77cca61e3a2b48c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x15adf88f6ea4febf, 0x6a463184110a588a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x4b4853b86f9b6baa, 0x350c5736178dd1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x591b518f12ea74de, 0x1906f85e0c324b3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x350de2e57ca822a5, 0x3deeb07f6e457272, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x1a324694436919c9, 0x5bd783c3188b4cc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x1fbe03db1449f443, 0x3951942c49a997a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x3e3ce357745184c9, 0x7c84deab2d4ca99c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x33e8aad951be23ea, 0x6777f2650eb14b3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #1", 0x406322a954c7fafb, 0x1fbba3c44996a368, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #1", 0x446366a57a2b6da3, 0x612475450bab7662, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #1", 0x0d15e28155cc721e, 0x17ddc19e1d7eb834, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x527494c3679bae69, 0x0bc42aa64223c566, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x2b04c8331400a657, 0x5aaf122b6ca6db57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x284a9a9a32d551a6, 0x365072fb4ac2cc0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x2726d6705f876810, 0x780f75aa66877df1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x31458bfa14f46cf0, 0x7538c92c5b0f8149, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x69bc67eb05ca99f7, 0x24a624b271a8aea3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x7ff6079b1531e6a4, 0x7d5425052e1fce90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x6afe58c25762b16b, 0x4b9e86c50d0bea1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x3efe5fd529dec1ae, 0x4f2faf833d72ed85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x3ddf6805606a3bd8, 0x2a19c8dc6a032808, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x133f8d7e2cd569c1, 0x34c5f416662a029f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x0c5cd1d141ea49bc, 0x4cb180903a6663ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x56deb6ad3a1c09ea, 0x1575e5383da25dcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x3fe6a3e12c9f3174, 0x2f4b0c6e409b1e98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x41d118183a5973ee, 0x6ebaed293fdcab7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x11bc25591c18451c, 0x4ce895992ccf70da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x45f706ca145c273b, 0x6a425e5f50ba852e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x74c663136f83a14d, 0x3abdad3603d66ecf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x1c590b0e36b1f1fe, 0x6a00716e0805f092, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x789c3bbb57e239b8, 0x426c548028b5dcdf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x11fe43a215a34718, 0x66583aaa4f7af268, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x4242788c7ed0fe29, 0x1016110051e4e784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x392a72175eaa2899, 0x11c19300041390a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x7ac26db51b255fdd, 0x30e3017e4ae69771, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x2f818719565ec9d6, 0x1ba11c9f40b9747f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x45e26b232e9054bc, 0x448fe34e2447ea2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x654246bb6eba2f3f, 0x2c4ddabe623b7631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #2", 0x469c68f771498dba, 0x0af153105dde8276, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #2", 0x06ecd4d23d6f85de, 0x2d5974de589aac9a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #2", 0x3c4084083c41271e, 0x2a7f941e492f4d5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x1aeb4fb87e25df82, 0x4d42de03756af61f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x194b3f5f5bf2aa30, 0x40518d9015adbd6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x325174061af7153b, 0x566731ed48ccc678, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x498769f819628b63, 0x6d14b0a57833df29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x081cbaa26560a86a, 0x5a6f555a2ec9b0b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x56aa36243a01a807, 0x0ca833294eb9239a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x77712de551d36452, 0x2753d0345d970af6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x0e148b7074093659, 0x26c6585533b1b1ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x722f15db696e359d, 0x291ca80d28ffdb28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x4560dfcd1514ca83, 0x3ead98960b7a553a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x300bdfbe415bcc58, 0x54471bb377b253d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x5abe57bb4a558856, 0x6fe632fc799349b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x2fb630c035052d92, 0x285cfa6962db125e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x6f06d59958e8062c, 0x319435f8066066e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x2abb6a7e0abdca30, 0x63f771db6678037f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x7ec7008943465d79, 0x1a29b56c38cff5ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x2cb49317207d69ad, 0x61cfd11770f61664, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x3592343050b78752, 0x7c706b9f721572e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x121353aa59adf9b4, 0x69c7c6b8659e13ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x2403820b078e580e, 0x5f315da56cd1ab65, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x3c9385a10140f3bb, 0x4facbdc353b9b2cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x5a28f9e73e118b8b, 0x5a1a19b02b9a5b3a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x48cf55bb2c3c1426, 0x12125eb904e46465, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x6f82719f1f842b6b, 0x3db45a5447965645, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x4001951834fcd848, 0x388c6ca91c3704b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x05b45f9a78143e53, 0x0e4c779b7593c948, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x51c238073a633adb, 0x5b31dd3617c7b344, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #3", 0x41f192ea54461c6d, 0x04995eaa75c5ba12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #3", 0x558710292399868e, 0x497f6cde7e85188b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #3", 0x61ab12193c31d27f, 0x2a1f73c52fb00a10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x686de6a57248c8ca, 0x34946e762a7a67d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x11ccf4352a9d2ac3, 0x7210be1957f05844, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x5f9a030b0273d496, 0x74275cfb51ce894d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x7a8812e922942fcb, 0x47625295654e62a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x5cf76aa701af7494, 0x7d1615ea4c4a4af0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x55f591020b8f71e1, 0x421005031ee8fd91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x2f28f86f478d89e1, 0x1d6e161c2b7ca12b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x03bf5c600fc119b1, 0x5b2cab3b10d40a88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x0209e27b2d5f3076, 0x3b4e725c6c2d4305, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x57fc5b393844f845, 0x441d9b4a13d6d6b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x3ab8ccdb2d07b292, 0x65a55ffd37965e44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x4f9be25e19fad6d5, 0x1ce4c0ea3540dfc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x1baa4b69439b2fb7, 0x018b2ab42c934d05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x4f2aa19868ea60b2, 0x4b7c4a96719fdc6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x3077ea93784928d2, 0x1d1c7d967e539a07, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x080a42834a7616ec, 0x0f27a48f343746f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x77d5476264822543, 0x206489f90a1424ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x1cc71d8803905bad, 0x1deafbaf4fd1a29b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x30980e3f244cc1ca, 0x076800df577fea63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x3e47989f0e4bf4dc, 0x0cc0ca270033f09d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x51e7249378438838, 0x2cc73da259f1e408, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x612de8ea68ae3e0a, 0x4b91c0742111c62c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x60f766dc2e8d04c3, 0x1f65603311a5d37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x79031baf6641a46b, 0x45dd1a726901a960, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x4ac3c9af1100ca0e, 0x7315ce5f70d86311, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x149125bb4812068b, 0x40aa05ac678ae737, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x6c5ec8554bcb9bc2, 0x3f0ad19b452933fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #10", 0x5a17909e7224623b, 0x455d24982aa660f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #10", 0x6a67ea73502a0571, 0x049844fd2bfeb532, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #10", 0x38d8437b6c75db91, 0x4d107b5e4b95d35e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x1b02e0542318c14e, 0x5d3ba6dc19cfaa58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x095a65b975e72217, 0x02d153b81405fc03, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x06e7ec25458864c0, 0x04de5f14541e2f68, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x0d9a6b4c7ab3e83b, 0x3ba916a01b7911e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x467f83fd25ff6a74, 0x60a245dc79f933a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x1823ccaf2937d993, 0x249f94962097149c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x7961df0419a6452c, 0x4c95c9ce028bb723, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x061c20bd2b5d315d, 0x4e218a81323a227f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x4e75f2ab4edb208f, 0x4c09ccd7211f0112, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x44c242a63a035c2a, 0x3524fd1557d05864, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x7f8bc0ea67979e6d, 0x2bee87cd4baa2ecc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x624b86a847c58689, 0x672340ad0d262c36, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x6dc4f0fd2bbef46e, 0x071f5fd828cb0aa5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x54f6ce0115f7e90f, 0x49621f4105e8bdad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x2f9e2e3b5695ff51, 0x087474d04e58ad05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x01f330ae4c9c9c5c, 0x0092cf8435ba4ef9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x1b77bceb0bfe4d20, 0x56d9500b50692359, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x4601a94a5428038a, 0x28397bbd6039ff92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x3bbfa1f713076f0b, 0x2be42e5e458d6a35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x5accf59459d2f643, 0x52b3966b1e0b289f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x0591eab110385286, 0x46d633454891e691, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x26303b9656ef190e, 0x4e7aa43e5a88b8b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x2d85185f2974353c, 0x28e165b755ce69d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x7610d198626208d5, 0x0b88b8ca2f78490d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x6e6055f6281ae824, 0x7fe16c6611888e83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x7c42ebae1da6bc73, 0x71c28e153461ff40, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x30ae2b7e4ca2ffe1, 0x79ef697538028da6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #17", 0x2675f6241ce3e98a, 0x560db6450b7b2112, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #17", 0x2d1c3c112287abe2, 0x540d07a42c07e0d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #17", 0x7976c4f12f71ff40, 0x06909988534c77a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x58e6347c34a39a43, 0x291ae17826fbdd50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x1705a318565592c4, 0x5674265e4ef70614, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x7e707ae8524222ad, 0x607f94970565f90e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x6fe8df2033b761c4, 0x39c7f84f7ab36697, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x005a61a508c3aa82, 0x32b5f43d20970a9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x25a7940d001f3355, 0x2c122bb126d057ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x22a6df385968d228, 0x52d838a052c3d01e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x08dad1684f2b293d, 0x261047c51c1da429, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x03cec380198da7d7, 0x4319817961c105e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x6fe33a9c1137a090, 0x30b80bf81ad46699, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x6379c33d5a0257f6, 0x203a5fa76e53b584, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x0db9b9bb1bbd1058, 0x69071c1b5362a25d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x2480badb200bd8ae, 0x73f9acfc0e141b60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x202b0c0307bcabca, 0x34e4732a4a284ee8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x61257df342fc66cb, 0x1cec1f0642d1eb3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x12279008220910de, 0x5eef8f646a004f5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x3b96b8b57c796138, 0x4bc1554015f65389, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x0db101c8510519c9, 0x30caba222b79f351, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x2b0771c002d4c4f1, 0x19cda8d6712ac505, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x1e91d54a3887145f, 0x448d676338c12b7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x5892ed0d7bb9ba06, 0x46d546db43129025, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x037665d02a26fe13, 0x0d3adf0d78bdf911, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x6d2364de1a7f73b1, 0x3b8fe44c649be3c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x3c88848f1a5d885f, 0x4e9c331f7f4af4e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x16d6e997460c0291, 0x1541486f781f3d44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x17111c5b3d66d96c, 0x239930962487eb60, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x403b9e5d5a4017c8, 0x15b2b06542188e1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #24", 0x12c72c2841af0071, 0x7ad9b9965ecd73a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #24", 0x3d68ba772f1ae2d9, 0x21e003cc6b5a1935, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #24", 0x5941e0ec1fa7f693, 0x6418124640df2048, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x3a276a447417372a, 0x257b040b466545ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x0e74bf895af18320, 0x45b03ab176afeed3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x20fd85b212685cad, 0x6ecf2c17254ba921, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x4fcf36195f8644e6, 0x49d39481380ea20d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x39c65caf7500e9be, 0x7a273028100ad477, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x36afea2f10b84beb, 0x6ed8481e4c8d88d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x3fd32ec41bffb453, 0x37e7a20c7418a4a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x3ba7aae65a72c8fa, 0x34f7c4ef19150fb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x4e8a0025252a902c, 0x5f7a557b75cf152a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x001c134d5b4e3014, 0x6c7f03fd5cfebfae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x6db68cc24c1dfd50, 0x024a68cf211998ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x2ba44237534f6b34, 0x59283b0c3d85c2db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x485054f23c68df71, 0x4d909752656a9ee6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x4d212b5c69dfc9c9, 0x31f827bd7f003f21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x05df7e1c2810a8b7, 0x7318e3c80cf45a20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x028371b20583bf4d, 0x260969d141872902, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x2aae4f7923d54229, 0x37563e2c510d71d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x7f23723e30569a55, 0x2e0c31852aca62c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x7c7497a5250c36d1, 0x4be3fbc56cd9ff00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x785ba20577f0592e, 0x2a5fc1db2818d9dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x3459389f3f7ba07f, 0x0d8378c240abf6f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x295b6a4932c519e1, 0x3fac3619017a63fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x5ad5c299347827ed, 0x0e6ebe1b2f3ae865, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x39fbe73a28184f94, 0x70c211685d59344b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x4bed91be5c72d7a7, 0x2e66a62264aa36b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x0cc971fc5b58953f, 0x0f74997a4b1103fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x0064cc11624ac4d7, 0x37eb02fc093e09a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #28", 0x5a3b1e053eda5c41, 0x3156e37e78c06e16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #28", 0x7e55fcc079189b27, 0x396c650e0e9456a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #28", 0x2bddb5081e7d78bb, 0x100eba9f27b16709, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x52f5a0a847ae60d7, 0x56ec4f6f06b377a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x6fc6b06b1273520e, 0x640cabec0cf187e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x6ee629b60110580f, 0x719bbe953bb44229, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x5c68ed4f3eb04921, 0x06c546257baf9bb2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x20fb0df9364488d3, 0x04eda5545ccdb960, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x751ee5140efa8c84, 0x558e27767b362bfe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x081327ab19d93d42, 0x09ca82a37374e1d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x3856b5fd7212984d, 0x1b2648de33f0dcb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x39c0f9241eb10042, 0x3aa454550b4c56a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x3124525009d99d1d, 0x183dde872987a98f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x0ae9f52c6c0131de, 0x653bebb9200a7c06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x2ab17b0020a7bd0d, 0x1bba17b96752e27b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x56ec45e019aec352, 0x44209bdb4bac88f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x28a94fd650ad379a, 0x46e2b4f74c0b2af4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x6a8674dd5aa655a7, 0x3f800cc930bc7782, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x4cb8edf41f51a88b, 0x64ad543622dd2ada, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x3e02a8cd46676007, 0x2e2981800679e718, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x5040fd24153d7c60, 0x300190a76f26fb1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x013eae3f2aeb8edd, 0x0f3177245b2af251, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x4b934beb069e70a8, 0x427dd4cc2bf0293f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x204d33fa3e7f672f, 0x779cb238227f91cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x0f2c9eca2e0ac989, 0x6e8abcc048f683d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x08b11f305e604f88, 0x79b2fb5279b313a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x7db1f8144ab9c001, 0x1c903e81556a0d24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x112120090be584e3, 0x5be3f43c3bb4a0e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x212301443a0d1324, 0x2adb9bff61621d2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x64f8a2017f0ae44b, 0x3c8d0f7e2261af83, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #29", 0x05a954f345ee8afa, 0x4e51d8c2308bedec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #29", 0x046df22941963c78, 0x530b7fb825f688ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #29", 0x6fa1060168a00810, 0x6eed0cbd139a90f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x4700579829dde31c, 0x0d4da49a78522531, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x7497a31d29a02691, 0x4dbc325544b24fac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x3585ab742b428c8d, 0x0066f08e05b8c326, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x654f9fb123a7efd2, 0x671ae05456a8acb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x22b2d41d475c34fd, 0x790a5c3b4a4841b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x0d4abff74ddfaf57, 0x7ad42f9f285c2910, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x0f75ebcf3d3fbebb, 0x4e52b1fd11b8b221, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x25dfc6cb32a0e7af, 0x255343147f16f1d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x5c7ecacb45254956, 0x776917016ce01e63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x6ec56fe731f95e9e, 0x31926e1051166de8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x5d3beb2b3dea1163, 0x56cf310f244b1b5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x6192013573fe2450, 0x7af3c814428b8add, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x3b5a594d07a7fc2f, 0x0cd3cc900444d553, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x5587ab877af3b061, 0x2ca0fe6348a51945, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x38336f1c7fb10e7a, 0x5a5dcb6664fd9756, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x3251f6295b7da028, 0x641489275e1335e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x20a2e97f7c85c25a, 0x4af3544a0ed0c0f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x2e7f20f836b65fec, 0x5fe72edd0f685966, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x74a0714f2ea73cd7, 0x33b374c20bbb0c24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x22a561275b1a6391, 0x4e46970156327284, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x62c25fc00718463b, 0x5a7747d75dffba74, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x020bf69c01029f1f, 0x26a4d3b9384a0b47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x00b3ad9a015c2bc5, 0x1d47a29e3a3f65b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x5cd9cbed6345efe9, 0x18529b9f3305a3c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x5fcbb24421bd9395, 0x41d664b87d7cb56c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x5873f38140988395, 0x0ce50ed30e4ad33c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x6f3fc06c684c7661, 0x1a05df604d1464d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #30", 0x4366d9f27dbe1f2c, 0x2346d75411e52193, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #30", 0x04d665671689afc1, 0x6fe4dc08262939b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #30", 0x178c4ee17bbae798, 0x5e7344fa06e25c03, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x7d17135d59745d5a, 0x4121c1bb183ffc7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x3cba4d430d1c04f6, 0x4b45a03e59f0df4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x2ed9988b6452a38a, 0x576d94b71c85ff87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x24eb272044d6b224, 0x2ad0d2c4074d8c0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x2d23288677a8c831, 0x5461f0dc142ae78c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x7566e75d15f4e528, 0x26100920708a0278, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x2c7e94e975268126, 0x16b33c2b7a3d4cc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x70e168be42416a82, 0x011fa8c7440ae3ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x1bb5c7dc27908084, 0x5c4ae0456df87c1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x34ac857a1f56f01e, 0x47e95b675870151f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x03a993a91fc6e76b, 0x74f614a763861e06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x649d998f3f359aef, 0x6ad3aa122894bac9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x36de632062cfab75, 0x3cbfa25511c0c215, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x78c4909d18fe00b9, 0x024ac48e2c454a7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x0e2481df27a24008, 0x2682974125432587, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x69e3aa8a4598e997, 0x694e09517f05ea9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x6d296a1b34e7c221, 0x6cfe66ba05997266, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x543eb23f52ff9c2c, 0x5e09878521d5ef95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x72c68397702fb7ae, 0x055c0d9b57e845e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x2f65529d3d3ca307, 0x007d00b157641d27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x200c4e7c6b6fa3ca, 0x6924df3c6643b5bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x046da484390b977b, 0x1289003a18d0df1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x60add78327620df2, 0x3e1404a112922663, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x6cfaf7897e9677bb, 0x119811014a91820d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x337e39dc2e347bf8, 0x502af4735a2461a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x0134182501565ed5, 0x7bfa513a07bcec1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x71861683602232b6, 0x5fa5320473fa9bbc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #24, #31", 0x1d5ed5bd34839820, 0x4b5eb8e320eb6920, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #24, #31", 0x1ff33bea19b81f17, 0x072f1edd3d6b2439, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #24, #31", 0x52c3b692145007f4, 0x563c03532460e06e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x3bb215e7488b17d3, 0x36f306d233718e15, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x47218f8f4e2e0495, 0x7e03102228ad0d70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x7c62808e7ecbc04f, 0x02d16f157a9fc96b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x00221f246201e78c, 0x025cb5877d9698b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x42241a423cefed53, 0x7191346f71a835a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x7173857319c2bda6, 0x12939ec85f82efff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x337adcbd732a178c, 0x1cee14381166c15d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x077a1f806cbaa89e, 0x35c7a1cc063e9350, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x3545c07137b33188, 0x39b02165432c3567, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x05e1361d6eaab1ed, 0x6bd942d87c675000, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x6d76723c7963cef3, 0x7707196c0243b6ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x5b65b67f716b83ce, 0x7fda4f5e6d989160, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x2e5b712171d465d1, 0x5f40c7081d89d0c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x0b97237719fad4f9, 0x7d0cc0c01fcef694, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x0d24ec8566fd59bd, 0x3135b7f13f120034, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x53b8025b7f00b4ea, 0x45509384149f0c05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x36b3e67243a48445, 0x57cb416d08fdc2cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x324f36327c6c2c39, 0x056512cd3c951c8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x75cffb2d3eb32299, 0x3ed8d33b1fc5a86e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x301ea6676c9f00d7, 0x0d5e39ce5135b1ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x5e7366a86bcc432e, 0x6ebf826e5e7a1788, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x05c718272f7ec60e, 0x7e490e1c6a0a8a1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x167c1fcb6e6d1dd8, 0x291c8a5312ec04ac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x6d6dd2c27f56521f, 0x278b10b26a342227, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x42fad6647896f7c1, 0x7331e4f42421b934, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x750323fb1f8fa8fe, 0x60b6d5c3754a0c96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x5e42cb98226deed2, 0x150fb5046ad31f28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #0", 0x0f0cefa92ac85342, 0x3c08d0d40e6171ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #0", 0x169496716b2497a4, 0x6cdb89886d805651, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #0", 0x1aa35db200a76ac4, 0x578ae0701c5bae98, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x6f14889c56d2c3f7, 0x2f47b345311f7d7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x562916160e858499, 0x1b539fa55c825b5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x071c7c5a615aea55, 0x00a414921923ec7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x00ea9354237dae14, 0x0e6df9107c1fa055, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x45eb9ce622fb9052, 0x66f2bf7d5f2d5eec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x4dc3e3945a6a5a73, 0x6d8ed0eb54f88c90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x458ef2181a03c352, 0x4278e2e164587a05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x1aab2e162ffbdbe3, 0x00b4289e60324fca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x06ce9fda2ca56ced, 0x1151cd4809bfb6b2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x3b2af18666e626a2, 0x664212105cf7b5f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x484110f704899b7a, 0x761ba26a42476de1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x2807498e2559cdb4, 0x3e670e36492ba44b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x48555e0615e7d423, 0x285903376df2e674, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x70522e96056455e6, 0x42eb73041619419a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x1f6819387b25e43e, 0x7a71bba035e120ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x2b21c02127653dc1, 0x161370793a13474e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x540aaaaf2a151010, 0x43d2fe0031f05ffb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x10fb36b20503b855, 0x0ee815eb0f359c35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x098d53cf0fe4184d, 0x517d0a16593c47a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x353de6014ac0ef2c, 0x2267ebf531949d5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x60a8c34f6272f6d6, 0x1f8783d17d934407, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x67d74cbc0e1e4141, 0x13ac85a150faf1e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x0944257f1cef830d, 0x06dc1294073f65f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x4454c0cf0525ab42, 0x4152ad423465e5a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x2f3abb52753e5b86, 0x6656459b185f6b7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x7a4213db791211ca, 0x279507b34035f204, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x08f62a173bda25a2, 0x197239ad03cf67aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #1", 0x069b14cf54eb88d9, 0x356405073e341018, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #1", 0x375e7faf4f73d9c0, 0x3bc7541f6743d81e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #1", 0x5d921b023f1adc99, 0x383eca041f35cc6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x5c0a5fa667c7dfa1, 0x2675325f66d64081, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x6ced8ae301926bbd, 0x1b3c2622205f2075, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x76d0c744605393a7, 0x38be8bf31c284635, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x5965a57175d071e6, 0x5c5e38397112db1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x31aa97892a4647d1, 0x74e242ca625bcf88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x7f31d0aa5c5733bf, 0x208fdfa03845ac58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x2bcb0d7f57c84e7b, 0x1f89847636905059, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x16e32b147c3b4f23, 0x55c61cc4095d2881, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x64032ec40b6f8f25, 0x7033690372ed8aba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x0d01fae24c0b3723, 0x134cab3050f0b9a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x2c5ecaca49773815, 0x6d18ffdc03d2c226, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x3f47a9fc69c7e010, 0x74e59d4605c4703b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x140e27e108b01f63, 0x68203fc370f24185, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x6507532248c17253, 0x2937eddd133ff88c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x2089c0ce1f9665aa, 0x49d048e510d260a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x1bd1b4cd0a62f226, 0x1a2f8923376cebe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x15d2814b3da721cd, 0x2a5a769d7fd4e392, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x09b258f03dde9d16, 0x50c59d3922d47c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x0755d52b1b8cdb9a, 0x26a73e54361123bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x0554bbaa23f5d3ba, 0x3bd593f6469d7f27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x2ca5f31d60c7ae89, 0x378fc0ac1962e38c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x298920dd767324fd, 0x2ca2dc1811ad4640, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x16098aa73caf3005, 0x227fa6e24a12e1ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x4712222c2bda442b, 0x017fcd8e31db3f75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x698165f80275c040, 0x31b023075ce4a377, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x40545d5626605dfa, 0x7fb91fa57333bee8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x41ed3994651a769a, 0x2944e2a347aa3282, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #2", 0x09104a5445d77256, 0x0e47b1a94741f53f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #2", 0x269f20df0d47b4e3, 0x60a4d8cb35b63d71, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #2", 0x03bad9e069e32a93, 0x476383b1502841bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x26925a991bbaf0f6, 0x1a3b236819c46488, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x479535217d4fc704, 0x4b9fa3fd6da47cc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x7fc587444a423fe2, 0x4a89203c31169b19, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x70a29ddc4d8f3ca5, 0x244a5a014019e49b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x32a9b33f160bc8c6, 0x07c4171d328fd770, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x5be33b1c5a76a57a, 0x79d1ccaf3bb9fd93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x67be5a5d38d3beb6, 0x71703b0402825bfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x22b6e9496ce5c120, 0x52aa9db86b79343e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x08a0b21650dd3cc3, 0x053d98c6494943e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x4e2d03c70176e0e4, 0x36edc0a75035e737, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x4bb920c62596dc52, 0x014c82504df28b0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x732618f715d086c3, 0x0e0c6fa63c5bbea2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x2bdc4f8a68bd62c2, 0x6eeb961225cfcc36, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x4334083c52fa04cd, 0x6189c9c907bf8aa6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x0bcdc3835cec845b, 0x0a41e6a22af2629a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x49d2457b1ba92f9e, 0x166b96d82e84accd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x6c866c612ebbb157, 0x77cdf0af5272f792, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x3032923b23f5611a, 0x22a8dec93ab37028, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x498c3d6c16b26ada, 0x08a5fb337bebb301, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x2c82f19d273307b5, 0x384771a33cb25663, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x0ff06a77440bec62, 0x62822299585f4127, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x1705f12f6a60b270, 0x601ecbce532472b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x474d36cb14826c26, 0x7e16d54e22d3b4b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x302b9bc44926522f, 0x51586180111f7c47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x77e20386063b52a2, 0x639273d91cb20825, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x2a30b3bc600b7380, 0x5765784d281495c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x76bdde5a5c47ba65, 0x240048c273bcf128, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #3", 0x037ac21b12f16a24, 0x306f478b2340cff8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #3", 0x56fd56865bbedced, 0x7ba0111f136b2c92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #3", 0x461f8f5e64a67494, 0x668f9f466e0347b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x7928e0ba622f5de9, 0x10d6fc690d6cc629, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x2b55b018021eb649, 0x1e8c427029547c7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x085a08ec1d6bfcf0, 0x460684a32337b39f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x7d7770716f4c9223, 0x4b4c4960328abca8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x4b944c8856b6f55c, 0x2647add174354ecb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x69a85f8113162fe3, 0x17761ec34f0f0ea3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x6ed50cd04909da7c, 0x627a3b3640a5b607, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x2db04f113f7ffa26, 0x2ea8fdbd34f49c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x21af580f60eda4c8, 0x4261625826d92fcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x630c5b12163430ed, 0x502dac4a4d050828, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x33a02dde3b890527, 0x703cbbc76b6663fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x2ad5974a4438ce77, 0x1df120a631179e4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x1aefc3d43cc30bde, 0x254ced1a7669e3d3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x4fd93bc127f32dac, 0x4578f27604982355, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x70fd082973e6d71a, 0x453dd95c3eae4891, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x3366d14036044718, 0x73a2e4c01ead573a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x16f1ebe015b4334f, 0x4586870555162950, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x2be8643d1257ed3f, 0x221b317879fe46f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x4de0f2660355cb97, 0x6564aaf05f88921b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x478e9a0e35ed1d84, 0x10a0306a78b689b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x72b0296234995ffa, 0x6f206d84627e5de2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x5c8c8da72c545a94, 0x6716813742896523, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x203b31ae74da9275, 0x0137adb54d8995d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x2aded98d31bd740f, 0x6c36ed0a53a202ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x4771a75f4ad35db6, 0x28b82c3e41d0c56d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x5d2b4af52133b750, 0x3bcf0c60735a0b9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x248982e76382ce21, 0x52e29db72b0c3d5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #10", 0x196feba512e33491, 0x23c2c70d6c181cf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #10", 0x477c948b35acfc10, 0x4e967ad80c201508, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #10", 0x620156a44fe127e0, 0x4ea97a2b24092232, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x44bbba555dc9a50c, 0x7192b802023c8852, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x0f87191c7e96b77f, 0x55de8b406f9a93e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x496a15356d3a65b0, 0x316b595056f8c07b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x0e6e1d001d3569ce, 0x4a52cc172695602b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x00b837ef75646494, 0x51a19d8732f79fe8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x084799256da637b6, 0x1f0fbcde1a282394, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x235333c674f1b2c8, 0x2648389c4fc42db0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x44d2daa8656007e5, 0x73cd4fe305548a6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x4329acf25d6f9dfd, 0x079112bc098e94fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x5c06557c2a948230, 0x792928e052b0c60e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x17cee7e073fc52a0, 0x29a9868925706ab1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x1131bc6e1da76863, 0x4c05cadc263d04e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x130bccf7784461a7, 0x5934a4c911e9f45d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x65ea995d525a508e, 0x2c1217f11b53661c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x474c03565ee4e3b0, 0x6b1793cd093dcd24, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x4444eb9516236a4b, 0x0e92578e0c1eddfe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x739308480ed69bdd, 0x15ad72fc076e9887, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x396b1e0d03c8e51e, 0x5a1f5e954f995dc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x77c537be410f9352, 0x7509c875513a05ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x5eb6fbb550abaf98, 0x77770acf08f6f42c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x48f0113f46f3007b, 0x1ae0e88971c2c8ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x194d5109782dc296, 0x0d162ec92edaaa9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x5712a64646aacf4f, 0x381877c06099545f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x5cce399a0265a55a, 0x6cb8325d1b5791dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x113c41377ce588f9, 0x22c62a63506141e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x00ae6e171504681b, 0x1ffa9fa64aa75f44, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x5613fb6d13587001, 0x1be165327873a5d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #17", 0x64041f991c4b828c, 0x016a9a0234caf723, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #17", 0x633e830733a3ee99, 0x268dbfd02cf430d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #17", 0x2bd1b13013e75335, 0x5bcedb757c8bd410, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x5a92228449dd5acc, 0x5d25286f02e45776, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x4c430026410213b6, 0x1e3be95237605c1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x3de79caf27bc3da6, 0x07c19e005d7f415d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x3cc0a5c2440805d4, 0x2826a0a23e960ac6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x576075d638744a9f, 0x3709b09c12d4a12f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x54bfcd2b6e2d5822, 0x479f98523b64956f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x21d146bc4427a1bd, 0x6858c64837fe5032, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x580ef4f211af4cb1, 0x348a24424da2f7ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x5b8ca77d6ec338b5, 0x50874f6232a11777, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x2fc54c6b71c31196, 0x6a01739527cfa7a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x197f4f3c2d7589a3, 0x054ee9016dace91a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x717d8f78634ca47d, 0x2c42f3e0563ff4fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x1bc0ef1c30b42e80, 0x6914962e48de054e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x1ee186a36c9b6105, 0x04429abd7080bc47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x30c302c25d0930bb, 0x287f0c7940b2cd5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x6eb87d6c5edd14ad, 0x0e55c54b08d1f7b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x4da04d62257482c1, 0x3b730f2c4a4524e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x173794577763b58f, 0x7214cc8d7d6599cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x24d93f32175576c8, 0x6b1282e730b6e394, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x7aa21b45700b6ec0, 0x06f6d8921656ceaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x20bf9d4163776eb6, 0x5f34d3f816630a61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x5012cfbb2f62d321, 0x06e3c6a83fa123e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x0c6c03dc0ea9b68e, 0x0053f14300d5d27e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x6d86cb3b451ad95f, 0x09a7ca337b248148, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x6a8f5c20377e72bf, 0x4569a6313b27189e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x2ee2284e239f3553, 0x388cb26b01c6f078, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x3af4ac1b3974ac9e, 0x327dd40c53bb6780, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #24", 0x29801b5f49470a23, 0x6a12362b3596c760, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #24", 0x2cbe78d952dd9869, 0x4bf9d1c14a3fb8a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #24", 0x02406b8a0a34cdc7, 0x09e0dc847cd14895, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x18de8455074ee546, 0x7da71b130eac6f66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x4c69bea54f3a96df, 0x09d0f0ae06654f90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x06b9099e7a191a9a, 0x418c682e36f91ac5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x1db84fed6b3ddf49, 0x38c00b3d359b31ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x24b28be87368cf98, 0x0956996d58acfc08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x3cafd9bb5a3d9529, 0x0e43c3684e32a747, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x2d1b2d9222533c6b, 0x18725fe7696e5295, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x2c880a3263e6b63d, 0x663f9b2a2f5b991c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x6b359b8347d8f930, 0x3e08088245668e87, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x1713900f0d584646, 0x4bcbde17379f5a28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x077160e02758802b, 0x6e9874ed1dcc99ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x12965f745cbe6507, 0x5367cb9a2529b0cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x5027349f0c1a703d, 0x7dd6acd53748eb5c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x665805661dedf28a, 0x057b92a30cd70e5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x40412ef55c84fc1a, 0x764560f0137332f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x406bb25700d6d496, 0x42cecc146cc93927, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x48afcdc67dfba5c6, 0x322fc7ae2ba14dda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x0b53ec0c51d91cef, 0x6340a8025fc35dd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x79319d1a50f7c31e, 0x7d8ff78312c54cec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x2db6282535c5aa8e, 0x37eefdb90bc7fc8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x41e01acb488c7a8f, 0x4310e7eb7ddd5cc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x667a6d1900f9cc10, 0x0ab46b2028382031, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x5d7ec82a7e7a1f3d, 0x3bab532926bb9c0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x7f50f3d345b49ce5, 0x1384d5361dea7a81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x43b042ab2ccc705d, 0x498bc85b4800c199, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x7ea58d4c255416f2, 0x27c41f6e4f042eb7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x764bda1019b8795c, 0x61c97ba377d72a67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #28", 0x4f7e23ea46b00ee1, 0x039f26f624020235, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #28", 0x0f3c89702c93ca1a, 0x21df5efa115e3eb5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #28", 0x2d8d962a7541b20f, 0x39965ee675b6f68a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x73bbd14c2ff767cf, 0x1c7292990b0c5e54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x75ac04b47282a130, 0x28f6d8d5730cc51f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x1f4f118d62d1a626, 0x3b0d86b8395c475f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x0825bd186a29f1b9, 0x086076161df49eda, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x03e26b15196af037, 0x15cbc9417e719728, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x601aff184452f858, 0x2273995e53608eff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x70e6c2731e552c9a, 0x64becdb46f578889, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x1396dea9018111ac, 0x650e7f131e74589d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x3178797b52778fc7, 0x2980b6f20752aff5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x44fa30f8356cfbcc, 0x7a5f751427247e30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x183ea1f368e13ba6, 0x6080c58f64494285, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x530b2d5f1809aaa0, 0x023de15f20645f0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x31749ad741498f92, 0x1ed5f63456ed9875, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x059c87ea0f0cf529, 0x2a4e2774118f99f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x2d6221c365f5a18c, 0x00e7227976834a5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x6776b3383e7859ed, 0x14f7a2fb40f9006d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x10efe9b442ab2577, 0x484bb06218ef2cb3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x7818214320947073, 0x4013aae355ea1aac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x0975ac193c713e91, 0x3a335d321056c336, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x547ae9324f911876, 0x30bb22425c80d978, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x10daa8085dbc9962, 0x336e71ed05ef8409, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x6cc98e8b18664072, 0x177f1df916772ff2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x7e5be1fe21f21d4b, 0x0cfa7a501a2bb04e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x606a77382370611e, 0x5b24b0bb65d29536, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x661b86953ed56ccd, 0x7ec1c1ea715a60ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x5f69dd400177d8cb, 0x47447b995e33a7d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x3de9175c1f458d51, 0x6e8a6b0f68df8959, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #29", 0x6ed6a5c778ced4bf, 0x456062d21264008e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #29", 0x568b6e212fd2a291, 0x185384987fb14dcf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #29", 0x4838e3042322f811, 0x16287dc14354fcac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x4515155c38a55db6, 0x5d80acfb4694c502, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x5c15bed42b291c23, 0x2c675a39257f8c94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x69fe88f05e1e691a, 0x16d9ed8142314569, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x5f9641e50eef5851, 0x2064ed4249686631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x2e34e5a277a8525c, 0x3247ef8a1d7f5941, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x7077271c4836de68, 0x2fe359d01d0b8b69, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x780980f932e556f9, 0x1cbcd9384702953d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x56084f0b67d83ee5, 0x0a5791ea404263fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x207d9c9b333e8339, 0x06d729001b1d6467, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x5e679f5c5776de7d, 0x409cf0fc7c935b70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x359547975f298e1b, 0x3ec4a0d94866284c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x6e18e66c44167e08, 0x11ce8e7d152b897c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x3bbed064628e3c8d, 0x32aae2bd1c4dcc0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x2ac51af5561630af, 0x395957772c35f780, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x08fb87a97d901ea8, 0x73388cbe22ce9bef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x65685d8d69e828ec, 0x6310ffec5f03d6b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x1d26ac253abe2c17, 0x7a213b1b05e5fa28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x12350a94413df672, 0x027955987b8e4b81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x2067848d55c3024b, 0x43f473ce47ca522b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x19d980530fa0be65, 0x5cf5dba70e806afa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x722efaf264278e80, 0x2ace3708559850b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x3a3dbf2f7506d4f6, 0x01ce48381cf415e8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x7296f39e22d3b1c3, 0x3fc2b1d7433946d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x0cbbdab01c5e58a8, 0x223d1d8c57ff512b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x571c84bf605ea0ec, 0x5de54b5429e286d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x219c975e69654625, 0x2570d25769518f54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x3f2848700e11bd27, 0x311be17f42041bec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #30", 0x1db27b8c7b52bdee, 0x508486e65901c8c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #30", 0x5f7a4c6e306861b4, 0x2e9a197c0fe1767e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #30", 0x256f36ab6c983e3d, 0x2cd58c6619b80b9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x0f6bf0017f2e7003, 0x5cf1527618062a49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x1b8cc8ab4deac6c9, 0x70057b751c27cab1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x2e4967b56b7b23dd, 0x460a518672a94d6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x54e06a020d16be3e, 0x5bfadcbe4fe5ff14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x1b287b65626ea1e6, 0x11ea1b001408b273, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x5dc15fd41ba494b3, 0x6d0a7b3738daf6f1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x4c0cf6677591f9d6, 0x48bc6d6f3d3bac43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x622a381333e50a57, 0x56f3b7e1717c2d12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x33137a5a7987d2d1, 0x0982575c71962814, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x4772999a53c8444c, 0x0dbdf2c54ea04305, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x3f4368291d446d2e, 0x4149907075bc014f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x2a5b2b6c578c1b63, 0x45a200631423d22c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x39fabd491536ffd6, 0x282c849f4583a6d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x30db9489471b0b32, 0x7e5e9dc217bc1d1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x3cad05082beb8142, 0x54f7c9617ce88af0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x5fd08b9977e70f5f, 0x6e64b8031ed73d1b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x716ee2301e2b57f5, 0x106d653012e405f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x71f39c4122cdd969, 0x618448f938e17bca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x40124698743f7d7d, 0x2e9d7d193137046b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x4bcb98e06d875b36, 0x455ad6976a6d7204, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x02be5b0c2e4fb698, 0x2ff118d605c6562a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x756ac1ca727a3ca9, 0x1d8273483399ef95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x1e65bdeb1ee73288, 0x30827a853217c6d2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x16ce41e7615c691e, 0x50ef03ee7e364984, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x7f87c113729e9872, 0x111a4f78083d2417, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x156c71db6fbc1cfb, 0x411e9fe1717b5d55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x63fb9a78680d3857, 0x22b261c0557eb873, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #28, #31", 0x5594938d6fdd434e, 0x3fec2a782fc73358, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #28, #31", 0x1e2cf9e6530ffcca, 0x358d89825852ee99, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #28, #31", 0x458a39733c6f58b3, 0x0becde2e1397bbb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x5b568b3c169e8671, 0x45af828363eff75e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x77faef8f7340905b, 0x622640e37224cd23, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x65df28cd3b80911c, 0x7a61f13b7782b0a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x2b3cae170bb06fb8, 0x68fe0df87b4b9aa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x73bda80f10b67d94, 0x50ca531c0f38488f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x0093c0e2748d056a, 0x3eff7be849523b9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x479d02352d920863, 0x21a52a351ec0bac9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x6a0161167807f8fd, 0x3258767a0d273ba8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x0ea67f6f533d73ea, 0x711733074557ec52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x467e044531deaab1, 0x377cb97606a16efe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x6d5f3bcd67222d99, 0x7e241fa12c5d2d13, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x72d29d5178731ad8, 0x27a8c7bc189be9e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x0929986d66d3ae5c, 0x27d4327466904560, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x5b60b3c75187ab31, 0x2fe280fc09bd594f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x7f19b3945ad68a92, 0x287e141822fdb5fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x52de8390213c24ab, 0x3024f1a4691b14ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x7479989565efba73, 0x2e7300fd618502ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x17ce6524664a919f, 0x682671fd3af79cdb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x4d6cbf380efd91aa, 0x6754c9ee052da0f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x0770ac82459dbd4b, 0x1dc98ad7403f5c8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x2c716ba856b222e7, 0x26cfa1ea109a44ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x2839ce1842d5b257, 0x1a579e3f07d21f6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x1dac3cea5af4c70f, 0x2acfd56b275381ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x7c30ebbb3ee19755, 0x106e9658708ac07a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x24d151c93a363576, 0x520fc37970aa8450, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x2080c71512f6eb19, 0x2ba2212b3c9fb6ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x21f47cc35f96e2b6, 0x41cd57df6ded864e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #0", 0x2534a00254fc84c2, 0x2e2ce2d829652946, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #0", 0x2baea7a954570c74, 0x39ff6e3551a60baa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #0", 0x172cbecc04480084, 0x59782b1953e875c2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x5f3cc7930baa8dc7, 0x7b3bf76f34d8fbb6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x4a8c251c77737fa9, 0x2563bc305b6db34e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x31a9b51f77ba58ca, 0x4c18379f6f5d76e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x0ab143e46dca85b2, 0x2bfd2dd3522a7c35, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x4d6168696e44e55b, 0x401802832ca5c0a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x43416a1d100a5823, 0x560ae9ed7296086b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x646164971db43f2e, 0x443c14156ef011c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x21fc3fb23e147ef8, 0x42d887897b8e2363, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x49bf0cbf55cadb49, 0x30671f1901390745, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x4d3e5af228bef233, 0x5ca6ba94144b31db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x20794afd2fa5d694, 0x03a8a8c17ee81012, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x1d705c46112a8eca, 0x51128c472b2a8ee1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x7f6f74252ddb3976, 0x57d04f896ad1c4af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x3de5919921a3e12f, 0x5d67cd1a42b0de42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x3f58205d74797792, 0x31a0f0092246f631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x328df68a4e3c38ae, 0x1dd519946154600f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x240713f73f3421e9, 0x628d67557c4d0349, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x67f3141c1440dde6, 0x1098352571456eea, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x43e6b47a41400b43, 0x702d7efc086c5f19, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x526a9a0d0b673d84, 0x3396edfb615710c0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x394276fa2990a28a, 0x4c28d57051da0e32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x4b3483ba462bdc7e, 0x148aec7477280894, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x3aa5541037441859, 0x196efec50a8ca417, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x058051074e6e6b7c, 0x6be104276d334a9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x0da28d657a188309, 0x69804de4298764ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x0e5960ef0afa52e5, 0x1accd3e97595a181, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x4c3a5e283198ee95, 0x7e02009a52401569, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #1", 0x3d002c197fbffb9a, 0x3397262a1ea4f835, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #1", 0x29509e240509f2db, 0x707f06677642a314, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #1", 0x4b35cf5906d9aa6d, 0x6d6aaba8748521de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x3e1dc2c66af2ca1d, 0x7f11c5f605db236a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x396135995c8ebbe9, 0x730e6e05439e13ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x56a73ef307f24cb6, 0x6d2578cd4703c2fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x12ec9f9b3a9b6519, 0x3c99647f65009fe2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x6c3453af6ad7db76, 0x3740b54c5f26fdc3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x6a97d7106e4afc5f, 0x7dcbf5f829347fc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x7354ef3a0ce1ce84, 0x1f7722dc13e87534, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x13bb78f1077f5d09, 0x086d97133e8abe94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x7272272637745003, 0x4465e1fe51d93bb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x14030bec029cc853, 0x15774f862bd35cbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x0a8f15092f70843c, 0x72d71fbd6aaa4adf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x6a0be95506eba00e, 0x4faaeac21d7bb4a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x71c37b847a6ea85f, 0x7ca2b26756403d04, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x68b9a4be1eebdfa9, 0x7f74bccd5c5b5294, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x2bcdae2e78b15edb, 0x7043c7c85c0e93f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x0030bbe45eff348a, 0x1a99528c3f89271f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x1673848d26d9b25d, 0x116262d772a2e30a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x29767ab0114d5f86, 0x1e763fc92a76907a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x40bde3c264cbc61b, 0x1520db5934058fb9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x6bb766294e23f6c4, 0x5181445d2ac9cd18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x48929f23007ec6e9, 0x010a0a1c5d7ae1ad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x1f6aa6932a19fc0a, 0x39d63441314c43e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x22cb5ae527f42a66, 0x0d5ad7da4b3854c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x06f35ef11c23deb8, 0x0ac17be022fc16ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x42fd91153415399e, 0x159ef9d41d66e37e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x456299245cfe4f52, 0x47dd73f86c740bc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x41ca156d71fadfdd, 0x20799b7f06207ce7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #2", 0x401ed6a131f4541b, 0x30ea49ff2d817b97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #2", 0x32731b0544d29186, 0x0afc5d4408b175c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #2", 0x6eec8d9047589180, 0x39fdb9a651ddc198, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x6f4cbbe727d79239, 0x1d16165911b7e875, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x43fb70f14a52f914, 0x34b3ff3f76401ad8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x7e6832b25b84724f, 0x13a6fe5606f90207, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x3882c1a113e6a94c, 0x736d0dcd43cacbd6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x05e189297ad592bc, 0x49eb48bd7a4cd70e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x2cc9e6d832caafea, 0x27ce52a546005fcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x779d417008af8f36, 0x4eb1d5905f3d01dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x500820b74e30d9ce, 0x311ac3756689cf00, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x76086c072cf5b6b5, 0x7841b7753f54dc9e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x7748afc9493bf5cc, 0x3594f7763a03dcf9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x24c0681b3469eccd, 0x40fcdf0075b0e27b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x485096190366f70f, 0x397bae515d4329bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x7e3c89cb7f5e5370, 0x579000cb4e321f43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x3229035a62e4549e, 0x14327f0e2b0670a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x6b93e3d43b5e35f5, 0x0a43728029c644ca, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x098f0fc30891cb40, 0x105013ca3b9c048b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x358781f53085d89f, 0x7af0e1297f977bcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x79c1ce6c7a9837c4, 0x399b58c42cd031be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x2f0224915bfcc28a, 0x228114391e823687, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x5f63b9995355610f, 0x7bc560447752baaa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x52b3b47f59b758fb, 0x4584d9ed5da04365, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x3c9bad9912ea2689, 0x08a6b40804dcb7da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x4e485c7e3ef3106f, 0x2ea2fca4282f916e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x4784dbaf5ebc7723, 0x63cb95f957d76c42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x0f424fc2110a40d1, 0x576ee80d7d0c5da4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x0ba278954c5da39b, 0x29dc8f6209041e2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x285a6625234bb4fa, 0x278654b63aa49d26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #3", 0x76a11609777c31be, 0x31f757d007be1fbf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #3", 0x51338ab96e05172c, 0x655e63244954ca88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #3", 0x00ef3db57cd47f07, 0x4e3182620dcf3853, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x3bc78f7619ca5fba, 0x35fec9c14f379a34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x7886d6dd7e7dee83, 0x270f0676034c6b25, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x0f882f542a35582b, 0x0058c8c907c926a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x7692fbc638539984, 0x10cd44ce1b2aa7e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x5b9f4e7e07c69cdf, 0x55cf450f1eed61eb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x7f42ce9d0c09e4ce, 0x26ab81aa52406487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x7a0efbfb69c6b172, 0x1b952f1050765957, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x669b307914445b6b, 0x5e4591aa7afe39b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x2e0ebb257144da5a, 0x4a35d3e42262bfef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x6fc2c8dd2607f3dd, 0x25af2b1426959203, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x503d4c083f2bfd71, 0x2e5eb8a37f4af831, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x777f96f67044e529, 0x1a75a01a46d047ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x780b82090c692b64, 0x65bda9ba531ee574, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x1873103340f4790c, 0x255f49fc774e50a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x2abb2a7e260a3ba7, 0x47c4a9fd12820c2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x3a4e971257b619c3, 0x0d8045de11565af8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x48faf41d596845fc, 0x33b91ae7685d5238, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x7f7039d93d519cde, 0x0ef2e43b38bdbcfb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x7c7d9a4f527e5547, 0x3808b52c4fad85e2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x42c33a707c3b776a, 0x167dcdb073fd3145, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x08a4a2cf6c7b60b6, 0x471c16ba3acebc79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x2d6fd9c279e1b71d, 0x321d0d202117b302, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x1febf2c5411a050e, 0x3399bf30582b0440, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x18d01ed11d3a7a20, 0x69815f385a3a89d7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x76a2c01c518ac04a, 0x4297dc0f61cb12ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x0edc5d2852918516, 0x1a88cfea7612f9f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x250fda5d5c3e4d88, 0x45c07fd70b59f778, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #10", 0x5879c4f246733f77, 0x7f5728bd67d314ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #10", 0x32eea02d54bede67, 0x22a1d147611e67c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #10", 0x4ea0958535cfd9f3, 0x02361ac3605e79ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x76e9df02220add68, 0x38897e306e8c884a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x3f4557880b5eee31, 0x48c712210fb9fdd3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x5ce9ae7b0c0de0ac, 0x718510c235e817a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x5e9f65c371bb9171, 0x2bfb119a6bc60ba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x4df9def976772bd9, 0x7720031c03af4020, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x3cea6b510e242636, 0x6b8254ee2673a3ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x62e3049d09c82671, 0x07920bad6fd90b7e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x3f98006408c1039e, 0x5037856e31839a22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x2acbe10668d7348e, 0x2010226c3681df66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x743622bf37c0edfc, 0x463bdd3a6a11388f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x43cecea94bf461cd, 0x1ff95033511fd13a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x3daff33f3405dffa, 0x3ce5dcde226e346c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x2a7d0bd4119fc97b, 0x261d748c0ba9d238, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x1fc3efb139af81d2, 0x321d762467677725, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x4377a84327780811, 0x574082a302a6f44e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x30390baf543ab0dd, 0x342a8e71030fa8a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x3d11e56b7fcd6548, 0x3991880e5b04ecb6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x378e5344650f7578, 0x451625453148082a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x3103d7463f4db643, 0x0267d9657b5d21ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x7353963e43e8cae6, 0x1dcb56596eb3ca85, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x558894612c7b12e2, 0x7a5d9cbd1dd0a212, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x662a94b45c789bda, 0x05381937754c8412, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x03f0a3ec2c1e06d1, 0x77f3786029a23cf7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x0058b7af66436dac, 0x2cb1e59e3429af9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x6610d2f45444c196, 0x0f2e9c513d6a9d1a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x3954370f711a7eaa, 0x6eb2a5451d9f2639, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x306834ed36c79e80, 0x18fc48266a580e55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #17", 0x7ab0696653697597, 0x590bd8da23bbcb2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #17", 0x7fe4887946c48674, 0x418c6d3d5038fdc7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #17", 0x233d224f3d78fa39, 0x458581d9660f1d2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x6997010b3c633fc3, 0x0fb15a24272dc63b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x22a6ad6f6a861228, 0x5b5775d669efb8ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x3ecad3be160cfb19, 0x275a55d408b78064, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x072779c33f52eec3, 0x2656a69d781f0acd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x761a8d433b82f1fc, 0x62771922378faeb1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x0eec67941cd7e71a, 0x5b4b79dc70caf6a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x639c6d8e06897649, 0x4103f4700ed0f00d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x440270830491675f, 0x74e00d3b06d98fdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x40f4a722095ecbef, 0x2e0756182d99718e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x73e4de173ee3801c, 0x17892a48639b5492, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x54f07b3612a97b93, 0x6c52d4f632afb1d5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x51fc6a560d45d5c5, 0x2acebca35c17f4f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x48c8c7c26ef31d87, 0x13a7a3aa4816f79a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x0bcb04a179e5e2b4, 0x38e1ee4357b52f56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x006f58fd5b662c9e, 0x66861f636f67722f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x5ff793fe24485825, 0x7641020d4471c980, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x2da7241409946556, 0x720b3b0e20ec3b20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x4877e57370da64a8, 0x04878fb2218c022b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x0383e03b7f0a70a4, 0x543bb4011d6860a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x0c5046690d27f94d, 0x798055a255804a92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x7c1b16d45679306f, 0x1d97422c55190e2b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x505f132313545ce5, 0x2cce3d8107e61b75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x6eba89836d8e8fb1, 0x774d8da450ce6c21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x11d6e7d7074b70b0, 0x154035a14eb21d81, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x10dfd6067425e854, 0x6f9e58a23f7e0beb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x65004cfd3545c218, 0x610a0e175957bb79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x345032bc704071c5, 0x76c01c2268842d38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #24", 0x7d686b125b9bb9f6, 0x3e0477ca40a07925, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #24", 0x3214ea664287c4d2, 0x15b98751798381e6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #24", 0x55dc21b778b72aff, 0x01699d5b0273fd89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x6645bab168829f4c, 0x534269aa4496ab3b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x6fce0ffc02e7215e, 0x1348c8bc781ca288, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x770d09b318a4bc8a, 0x379aae7300ade602, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x4dea7ea250c5bd9e, 0x5a05a17c5c0d56b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x41062f630295fbb3, 0x449183e8023ab15e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x5e31b5a95894b1d5, 0x42db2a843e6e9a75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x1b1c76a7395bb9b6, 0x37f21c5b1046a00f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x3212e4b665fd0743, 0x12ba9d9970f8985f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x4e7fa68f48d80c56, 0x358f439a18589f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x4bbf2db5480ff062, 0x107541ef3e4db68b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x60b4aced19013e0a, 0x3efb9c8e42cc3768, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x69c6fba8636b1200, 0x1ed98e182e9f2b8f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x66010db373b50772, 0x30d9dcee2acd2b0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x4c49b947212de1dd, 0x693bc5814432c35d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x5a899b9367340105, 0x5479636c67662fee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x4d3108490dee0be7, 0x585ec84d0c9c8049, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x56c6183e356a619f, 0x24f51fb01bb0aed8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x7d7a520218fa01f2, 0x59fe6564228545f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x31fb3ffc042b0b73, 0x65517d5b5e2efeef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x67961d733da8076c, 0x0cce2a7e1bc23ba4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x315d0ede2fcb2c32, 0x468f66b04d972b27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x50f90e0f664351f0, 0x11c9ee847da6c825, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x4d7752f63d6bc061, 0x650cf8142b82a9a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x4b59cc495d14499c, 0x381f29ec1aa85b3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x127eab3c10576f7b, 0x36590a17221fe487, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x2951716d29f6a7d5, 0x44a52a7a0ff8fd3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x2e21b3487af626ab, 0x6e27fc2d5b4cb169, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #28", 0x389e2e183d9e53be, 0x770eed0e15b7d0bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #28", 0x6d697ff07518ea66, 0x634efbe269fb3cf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #28", 0x5b5c3c574caefd30, 0x67a2051c3e628dff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x0a1abd912204618e, 0x69e537a228d38f4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x7f18ab2a79d4f4a3, 0x437bea8c557489da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x0a2c641f3c3998db, 0x77946e6111975666, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x663040b00fb84fd1, 0x219053a4337dd58c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x0aae767d05d97404, 0x0eca86f61451f3f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x4377c7c20d58c096, 0x2a09c4b4434ca495, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x0271aafd14e9e6a7, 0x2d47e18b30e147b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x6198e3d759290d54, 0x6f43d5b25dcde754, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x7b2d6ee24a1d612d, 0x06a176a16bb3a169, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x43f255d038bc99a5, 0x41282b437a461a0d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x74f632802d6dc418, 0x0bdd70734e1eb9ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x3d2613e910671672, 0x019c8f7c5b267331, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x16408a7619822bdd, 0x6f78672947d48a66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x26daec7438691087, 0x0b212efb59b85238, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x4d52f72e79dd6f9e, 0x0a9999eb294c9771, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x53067cf20dbbf566, 0x071a7ec52eebdb06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x57d956935bc7a7b2, 0x1a9f7c6f4e33ebd5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x1484415754577655, 0x487a05e21bcbac63, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x01c53a6d6b86f5cf, 0x69ea6653097a73d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x7bee0c4154194e32, 0x64a0e7093eeb4e57, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x6d9b7a1011e107b9, 0x06bfd8bd122e96b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x4a4a1840768082db, 0x6be6e8ef14766684, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x705df27944dd7cba, 0x3dc2fdf5179d0f6e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x52997220612866e3, 0x4688ea7443646f6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x3cf00e965a126122, 0x11985b402a72c8b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x2e69d7783028db69, 0x463e751651744fed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x1bafd1383f8faace, 0x5aeec3c5302f11e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #29", 0x13a8f90175da38fa, 0x6f1a603c179ddd79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #29", 0x07bb40b315b35d20, 0x29cc743001447311, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #29", 0x0c33dffb537dd78a, 0x15bad995520558f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x185b5444302b52d6, 0x69a268617c91d274, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x1153b9b9518e9d20, 0x3ff641df6af4c664, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x2ba0fe425ba6042d, 0x15678f174e43c84f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x0bcedf977aa6dc02, 0x1fb8183d5a0ad5ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x3a3686d1795447dc, 0x0a39e7a0277eb0cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x6f2e80d668e90279, 0x3f1c8e494ddf7fd2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x7e9c5f9964decc78, 0x4f23f2e376e9c189, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x385ca402329182de, 0x48ef1a7c0ad03f94, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x62bcd5b4475853e8, 0x0762120850b7f846, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x18e6f10851144dc1, 0x3bacbeaa74108f6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x2cba51ee620c6ffa, 0x425457bd4487ef4a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x5cb34bfc28ccaca5, 0x1e92c50538893185, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x2220f4811f24709e, 0x6007e25516e9d2cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x080d731733ed4582, 0x64c9529f114f7558, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x18cc11fa5128515e, 0x083936e106a9d2b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x03b9d43c18dc244e, 0x117a12455128b5fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x603478365d8d6cec, 0x21e0ae426676a9f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x2ea1baad1cdb911a, 0x5a87395d791b693e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x7ee801145c361d8d, 0x3da358885b5c0c9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x0502ca3273ed2076, 0x13e53e215b9b4d11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x13119114574e727e, 0x72851fde2723beb4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x0b3bb80040ac6aed, 0x3873340c1b1f042c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x11d4bc4b3342e922, 0x21c8d6dd2407c9fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x4c1f0d7017112e3a, 0x75307ff7158e9087, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x749e9b26568c73d5, 0x7c053a772c5385a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x736804ef6312476d, 0x256eeee4234055d4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x3f4864fa1281a091, 0x7e9c627072500604, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #30", 0x066ec108407072f3, 0x4deb5315444b2f2d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #30", 0x17bee57123e221ed, 0x6b6eede11980521c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #30", 0x648e8cda56682d25, 0x349f564822fa9d72, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x09ab16483c32e764, 0x4702676d76634926, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x5344159e07f71425, 0x0bf1d9ad55ca23b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x5e8387fa278c9843, 0x021da95f47e2b0c5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x0a9edfb069bf6909, 0x6b23069951eb8ce9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x7c41099a1226e602, 0x443b92ed49e744ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x529758f679a161b9, 0x0e3273d802afcaa2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x1d8383a650cf7307, 0x1c301cbf6a563e67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x2737a02d54534346, 0x0d50dbd902121080, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x10862aab04673354, 0x787559a630e2b675, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x0c5e477908ca838c, 0x06acda2d63ca4049, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x30571bd016cff7a7, 0x2bacf10e6ae1cf73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x008f60b00108ef4a, 0x3ccd5c5c3af5fb80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x132fd54c130fb403, 0x04dd402b7cd06a4b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x0cb115bc1bb051ac, 0x7f8034ed65c72e42, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x6c7fc4b45d6e4883, 0x501d6caa2a349962, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x31c18bca24bc0389, 0x2c46a9e313b764e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x292336dd4b46f583, 0x449a1b564247b675, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x5411791051bee7cd, 0x2611f6be35817e56, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x688edf745d30aa26, 0x20634dc9046894e0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x5e399970443bd08c, 0x3f5e9060691e4025, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x574b848f656edf5d, 0x65eeaa7071696ebc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x011f310a274e09a9, 0x57309cff63fc9a4c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x04bc522c3a77dd91, 0x0e3133ae6d9ef5be, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x5f33e11b45f075f5, 0x01565a9f367dddf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x11376b781ed78b2a, 0x78c5946b085717f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x709672f75e3be418, 0x3dd8964f6548e488, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x3b6c8e3e291009c9, 0x69b179685925526b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #29, #31", 0x6d4bda5528323d00, 0x4243929019a627ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #29, #31", 0x0da11c5e6240336a, 0x0b0f966b44975ee4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #29, #31", 0x098e3d1336c52cdf, 0x2893f9300ec04d68, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x713d0a707db59dc5, 0x7c5f43260e4a8f3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x43a613ba3d8e01a1, 0x44c86d365070eb8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x5c658ccb16a099d3, 0x58c8038454dd7f32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x74dc7deb23d7dd23, 0x3a2663bb4cfbffc2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x4ce7e6ec6864e4be, 0x2621522e30490c2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x109721bf54feca43, 0x49ef33d83a33c141, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x373efdad275f1956, 0x7ecb20261e383e1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x5e2446352957ceab, 0x2cf88b8540cd3ac0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x270d6c7013e03736, 0x4f17ca004f6150a6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x516e38d7789a3fb5, 0x1fd23c316ab3802a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x0f3ad98879b76317, 0x3f90ff5c2dd3c5a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x1d8f403b20f11793, 0x7acfc56504175774, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x0955fc527e4f9776, 0x3460639e6a772727, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x534e61ba2376088f, 0x24aae86919ed1e11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x4ad521e5651de7b3, 0x38255c2e0a8d5f67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x0e75b65e1a726428, 0x4b5a9a2828f9681b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x2e529b5e182cf4f2, 0x785ab8c1358322ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x10c734a85fc7a254, 0x2036a2f87fc0d435, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x597f056c28645f3e, 0x2d9499d820020e30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x495576d15879c942, 0x241965a4770e45a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x56c960b906305537, 0x61856cce52ab7323, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x29a65dc624bded62, 0x6c9891342a17c273, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x09dbd5157fffbc02, 0x34a521da747b7fac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x1a72202a15cfa088, 0x1d74e7c718518b73, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x2dfc957a6e0b5139, 0x4dd4ae4148c4bb88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x4dd2f38e761a2996, 0x48858fbe3ec3ca22, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x1e7e88d402df3df7, 0x5ec5d8532751f8fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #0", 0x5b59073a7fe5ab6f, 0x1e603ea167d3ffa6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #0", 0x061600a7271803fe, 0x3a7f72c9322267f3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #0", 0x4bd5f16010df4c40, 0x5c3a2a662fbc5e6d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x10df084341acc5e0, 0x2437de1955b1c676, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x577c66683bd8002b, 0x6e0351e92b51286d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x29e351643c9b73b4, 0x7415e3f60578fbe3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x32b59d4a23029e58, 0x443cc60577b644f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x25e1dc503d687c8d, 0x1f083dec5134261f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x3d4e27fd7387988e, 0x390825c5013ae38a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x1a9f9c8c0f9775e3, 0x335d4b7d436428a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x2076c2231758652b, 0x7320871166758ded, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x59052b0b2a2aa64c, 0x3c2754633155ca66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x6602a67750bcd6ca, 0x5ca6f2d430819174, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x0d584a7e7a37535c, 0x35fa8d570fe5f7dc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x1d39f1b526a47abb, 0x079c3cce400de7c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x640cf7484a4a33ac, 0x11420de7431bce05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x3dd1cc3b77b3fd0c, 0x4456b18f215b1f45, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x074b72ef57dfcefb, 0x64bf47e9587168c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x6f3834267b0e4b17, 0x3ee6f6b427c23512, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x2538f16435bef24d, 0x5917ff79483d5f31, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x067bc9172eb97dfc, 0x78bef0a50b3b97db, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x28f0d15922bdcc86, 0x1b218fb713d41395, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x4962474165240945, 0x53e1fb5d462ac30e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x2f6e3cf14d9d42a2, 0x094691132d6f3e89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x45513fae3389a5b8, 0x4eca5dcf6d40092c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x0b6974b3049868a8, 0x45b171f44c9cb29d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x7fa6b3c04d76e728, 0x745ee7af7aa1a8d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x0335d9753b9df8b0, 0x42df080b24dfa524, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x6a5776ad4b3cccb7, 0x301b3cff09b1a28c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x6dfa993d7167b17f, 0x1d85b62113484806, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #1", 0x568bbac462b99c27, 0x59730b14375ce07e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #1", 0x3056dec933967cd6, 0x64cc1f0705f9f7b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #1", 0x6720228f38eb72d6, 0x733a00e275a81e77, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x3d83db7e36a3b8c3, 0x4244d11472899742, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x041a9fec300a4827, 0x6d2b401c3d2a8f3e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x6ba840d712257162, 0x620a346207507961, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x5d623e192e87d20f, 0x11021bee55ffb784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x1fef838e42bb0a9e, 0x6947ff8a4b5cd756, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x2574a6c56785d6db, 0x02b9b7d4767b3e52, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x1b1c53b26faf36ea, 0x7c75360855cb858e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x289aa9c00db87519, 0x4b73a405023c7641, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x445c2ddd61f14d9f, 0x74c60d83661e853e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x11fb95c6055348df, 0x2349147d4876cdc9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x1778ba4160c96318, 0x4fc7472a7da3d69e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x0f5135283ceb8dad, 0x53a38e2274daf85a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x7fa6984b42f18784, 0x4037cfb02f40b8b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x2a775e6022312d11, 0x25bbf709251b3f11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x11e063fb465a68a5, 0x7ae6c49f4593b212, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x5412ddbe3c9635d6, 0x47d028533a7b0dbb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x1e87837643e2a776, 0x209992f9186f0b9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x4935f05630ad208f, 0x60e5d9643083193c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x117683a701ca7dfd, 0x2e26efda60aeaa97, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x3eb60baa15c172a2, 0x5589a2f220c7b8cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x58b2fa2775c4688f, 0x500871863e5ca3f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x17f595a05e5ea7a6, 0x6377e306032a5887, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x24b9104b108e32ec, 0x48be0a9929d5f99b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x4d2468c204ea9a4f, 0x6451075678cbee09, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x48cd41c67220d309, 0x113af9a56babec38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x22cdf3984a55f54f, 0x1c2f05751203321c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x4c20734c483b7fa5, 0x72b1dcb334447740, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #2", 0x5dfcf2482514a195, 0x550c300f0ad67ef6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #2", 0x1ad90a242cab05f2, 0x493322ec36afec6f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #2", 0x0b09ad9802984f8f, 0x39da44f632ce9fc4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x1326827b40f5a0b5, 0x5ca4995f2fc2bde3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x45e03b0539c9a592, 0x288eabed604aeb3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x2bea789b6825dceb, 0x4bf6d7760ead7ccb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x327bd23a13628b9a, 0x20b0aee74eb86c34, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x5b9e0b4058091383, 0x02fce3747e9c4587, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x7d1db51952a5e769, 0x0972c47d399afd88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x7f50ed5c2a252eed, 0x704ae9f717f6bf3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x2cbd7e7c2769f861, 0x4ac55f020a5a9af4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x685f991762ac04c5, 0x3a1d58d83fe400f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x1c75aa576c25c3aa, 0x202eec342e3fd41c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x544ba0955d9dffce, 0x3ced50e7486022f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x71008b681a15729a, 0x17188f2606c772d0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x721e861e0ed67cd4, 0x0563b8574c9e96a8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x617c643e76847e27, 0x063994306f3c3b37, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x20a9ad1451f85976, 0x0732fa7460cd519a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x796251d825454566, 0x6b27ec8e4d672b90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x07f14a2b2d7a18bc, 0x0d4b2c8761c1eaef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x199fdc664cef0ff2, 0x1001bf0b2466f482, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x2a8d0fc003dfa69b, 0x6cc717756deb7cfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x1df519367a16a823, 0x74b2efcc1b8d9b28, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x08ed24f76e65c601, 0x682c31d110139f54, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x64ea44290682d4ff, 0x7f4fda8b6a698935, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x587b2e76365ec75e, 0x4b36dacf0593f13d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x5ba40cc460464955, 0x52fb1cce51dd804e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x0dc0621143a12a48, 0x339f6b3d639556f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x10903a3a74c362e7, 0x07fc4b7227603e78, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x78a3098309feab40, 0x154bbb743b1d49fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #3", 0x041553633ed716f3, 0x56aae522169822b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #3", 0x2d3cdcf525fb9c98, 0x26abc20d0d02785a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #3", 0x2c7e719742a2dc5f, 0x776c01901227211e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x7901a3bd6ab62f29, 0x17bb125b04f9a00d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x4afc787f0a768b98, 0x56d7205b54a5b082, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x4e17b5e0403752e4, 0x383b077258bcda90, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x34fab5cc1568d47c, 0x001d19085ea7f01a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x1f677fbc70701f37, 0x19c53a142d9dbf4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x2f47362a6ae1a415, 0x4435e208237cd31f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x10dd40ad27eb4d0a, 0x307f4b7a5c84131f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x6a8e296906664699, 0x6eab343d3d5bb244, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x711c75c2192c72ad, 0x42555252638fcd27, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x23a2fe467070851b, 0x38357da93c18ee41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x30a7d7ff14f2e1da, 0x14d5c8d271bab426, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x2a5bb6576a27de55, 0x5062a44165a28dcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x5a97fd8c57762f22, 0x13404d1a49c33613, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x4257d3371dbf54ad, 0x6d40093309df33b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x45aaa1b7550e7b14, 0x666346d6533513e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x5b74c1ad52e6187b, 0x1090c6293038cb20, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x6c128b284bfe15f0, 0x13c898474c91376f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x3c6e9b0b1d7fee83, 0x08aa25b10fb5896e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x3272d05d51d2e1d6, 0x01703d956d16730b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x3bfac02b65f94df1, 0x52b900d65cce86b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x3d6f7d1313d1c5fb, 0x2691bcc81692bdb8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x31911aa806d53845, 0x2071f16f7fc7504b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x5be3b359638d2a58, 0x52fc642f773bbc5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x367342d33b3d1fc7, 0x2774877f37587506, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x073b35b70c93d227, 0x03e9ac762285cdfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x2a13c0aa33ab94ff, 0x323b576a43a9d0c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x057e76d5037944a4, 0x30c043ce5c869107, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #10", 0x697292955fe6d484, 0x395517bc41793701, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #10", 0x73b89a7f787de628, 0x580bf4b926e20fa9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #10", 0x7f531e6d79a5c423, 0x26a95ff42549b527, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x5d32ee7c43f9f905, 0x1c8571865b36d1c7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x7f3718cc1678f343, 0x128f46cd13a6314f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x230cc56a686756b6, 0x362bff4b06724e84, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x1c12ebb57adc6315, 0x4a1c1f474d208614, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x7e55a7b962fc2ed8, 0x29a7171c2191628b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x42e3035c3b168e45, 0x630a998c67c83a4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x3394746d3553a9ec, 0x0eaa49f8369b9ddb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x2ef96e0f786ac488, 0x5be5530232e792da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x3c64bd8d20adab6f, 0x0e1e64a10c2c5c8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x37269eb255fe8d26, 0x1fd28ddb3b9bd65a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x3e65e3dc0c2a4425, 0x420e24de5a33641d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x0706a73a50fb014d, 0x2753ea315a78cf92, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x33f730255f14cba9, 0x7c0a321d055c4ef3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x1a2b59ee7bced33a, 0x6d24894276da3381, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x31227d26095b245e, 0x2d75d15c4dbfce5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x01c5e8e60ec5c5d7, 0x00a76135601beb36, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x2f7371460c1ad59c, 0x6c4847c13e2aa674, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x621962c33bd4a1ac, 0x79c67cce669a0ff8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x47fee5d168215e47, 0x40cd7415207f469f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x391c5f947702484e, 0x7af816314f058d0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x561713f741866541, 0x5461dbfe6d138fba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x3d55387b11639498, 0x63edc33b70426de5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x1abeb8f63ea99d76, 0x3e023c406e77b5a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x4d6f634d3adbe899, 0x4e93a0d81c84a1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x46f6be365475c51f, 0x5aaf48517ce2d493, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x104a66cb244a58a1, 0x637ce48b291020f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x0c6bb6e844877dca, 0x498f679858494c9c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #17", 0x3b89c6187bb0b5a5, 0x274ed9a74588167c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #17", 0x3d371ae616896972, 0x329ba63611a0da10, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #17", 0x27ecfe0a3fe58436, 0x01e347f57a8c5362, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x7e8f21ac3797a9dc, 0x6904090442abb700, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x7273927539dfa12e, 0x5f3058dd4bfe84f9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x0e55664d2c5e3e17, 0x48e1598c396a50ab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x50a896b82c09d93d, 0x627a71a41e9fcd18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x709157071e37f35b, 0x76e919b45d144da0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x19e8a90155380a53, 0x229c641d2c1b1d1f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x6bc173c53f9f3f25, 0x3dbbf72f571fc3e7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x7f84c35b3ab0204d, 0x51ac174913ae71cf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x7247ca29358a81ad, 0x565a28d07e13e507, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x6f6a22dc12f3c38c, 0x4a126a0064bb5c9f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x3f5201a300a01eef, 0x1e25ad4a7dbf8929, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x2ca9f82c13486ff6, 0x1c5f56420ffa985c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x318063520fab4a19, 0x6d0ee5fc1d3b4f33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x64e3546d07126382, 0x49566c524b690c53, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x46b1a2a77434e784, 0x2288d03a50a4c832, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x2ee507d13aad62d2, 0x64533a0246366602, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x7037e47f0e5cb509, 0x444a4b09212cd1fb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x21507895240ddbe4, 0x05e82e9a5fa2075b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x24adfad379c0e6c7, 0x5d61908560a27a38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x0d0956bd5dabf891, 0x709d12945157f2ff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x6d5742aa37e9ae85, 0x6e9342323e89ba0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x3efc12072c7b969d, 0x09f2c662523a9717, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x20b07e210732994c, 0x22df5f4a05adb4ae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x41dffc1e102e65b9, 0x4be41ab04f9585f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x1e8b1ac276aa8687, 0x70c257ed3217e09d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x1ab8626c6f1b787e, 0x11b9e7f93fdb9357, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x68dc5f45111b2024, 0x207e0d8f3f665d3f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #24", 0x6ec718b57f519271, 0x10be503f75e5b602, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #24", 0x373b40f63e623674, 0x346f70125c1e5b5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #24", 0x6addcd11513851c1, 0x2e58f277763752fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x586aeb0d47c9225b, 0x7be507ab0b8e4b32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x57f788144be62912, 0x5b23d1251a4ae72b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x4290af9a5e1cafc1, 0x4c62c7c87682a2d6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x4d38283f56dc43bd, 0x365e362d5d491206, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x67f763e12d6dbf84, 0x1caf6f4536148784, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x2cbf51f66069ad99, 0x2bfa3d8756be7c96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x1ecbe40d6135ca6c, 0x32dcd7f563fa92ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x326e1c2d5616ed95, 0x5a31e5ea09a9b11f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x1de00ff1705bcd76, 0x1537fc510ad9073a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x3c41f6897186b62e, 0x2523ee6575d79805, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x4fa365ef22b87109, 0x6c5a3adc7ed2a623, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x7994b4c678cb276e, 0x5c1bb8291cdb8e2f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x2638e6f37eea533a, 0x52f015b3618c18a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x5f5400d36b276d33, 0x384a953d52f838e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x4c5d379f1124b1bf, 0x36f2cbd57e1fe4e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x673b9f551d019251, 0x07c996007ecb53cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x0d5d5fc82ec8496d, 0x09a45b07051baf46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x204eff9b674d8227, 0x7af3474b499f5651, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x0a05f331248db49d, 0x4871fc746ff2658a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x1d58dc0b5fbe096d, 0x0ccdf3b9039aa7f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x5ea85ca71d7155dc, 0x6526c09f4391c2fe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x0898c30f4d7cc7bd, 0x1689fbe73dfc5d7b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x5ea1797c43e5d85c, 0x3c1c425c54f5faaf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x60e76aad5d65a983, 0x53c14e7c45dd18d1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x0c2df2f045ec0f63, 0x4af8c8176e44ca75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x2d39918a00561d3a, 0x37e420c62c7cf28b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x24e3d1d7293d4bcf, 0x1c6f5816373f84bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #28", 0x08fb553c2000ed52, 0x3ada2cb3423cade3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #28", 0x3d72432e1c586cc9, 0x05ce70e167a3b1e4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #28", 0x69d5348661bc51bb, 0x25a00f5f460b063e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x25a22a176ec24f69, 0x1b0100ed4876ae02, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x4c27f8ec594c8eeb, 0x0e53c6d4068994c4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x1f389e4e2cb28000, 0x74ce5f3a5855ebdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x2d089d3b2142367e, 0x04d2de684c722fd9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x4a7f824e3e8be147, 0x03b1b49451ec6f12, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x5e8cce9919f78dd7, 0x14291cf5537ad78a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x364ffaa060be98cd, 0x3b1e896e1bff11c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x427aea887d0b18f3, 0x620a180620252f26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x6bcd685c76efa3fc, 0x689bdd28681d149f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x503c32e86375089e, 0x6ea6a96437f56148, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x1027889e151e2b8e, 0x104b4d256f74d136, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x3660620c3f98b5a4, 0x3be7010f3d3025d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x7e2496eb2345b1e1, 0x0f1c94ec00dfe45a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x3d3d3fb80f794553, 0x545abbe55cb16585, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x7037de215aba8f53, 0x78b0774d738d3a58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x57c5a8467c4e46a7, 0x13b2697e32b2c8a9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x733deaa3097686ad, 0x1acfdd49439310a2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x6ceb8f4b0bd3bf10, 0x7b8871ea437a1d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x20f1ea9e6ed5efd1, 0x32eeeec27d1317e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x2e6ea575495fd2af, 0x3a433dc357524caa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x6ca584902c8cecea, 0x583231052c933c61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x3c06323d01f51933, 0x0944a1e629e2c449, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x5cafa88631226820, 0x1d6ffea12c3e105e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x2d70aec779c0b651, 0x5ef0d908347550cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x03373cfe7390d358, 0x7808616e20ae996a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x7f6492681717a5b8, 0x6428b6f67022cc49, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x05ed9589277921f5, 0x6d35e43220567d06, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #29", 0x70d8f4a44fdafab6, 0x77a8c9b1345c3aff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #29", 0x7c67e7a06a341946, 0x60ef77605d7e7935, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #29", 0x6c29327924d13c1f, 0x07613d7e386e19dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x55f3a43f439d0344, 0x64ac2a3c48d8daff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x3d5db99575568d39, 0x7d4e2bcb03645306, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x68e76091083ba367, 0x2412ec714094f693, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x1f53491f1deda70e, 0x30b7c2dc684bf2fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x4566c904004b39b1, 0x08a270002540dea8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x502634673a8c9107, 0x599d19a7363fbda8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x24c0aa4d1b1f745b, 0x13be36dd4c8e1c07, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x3ff0b07b69a86021, 0x04fc35e510e9dcc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x2d4563655710e390, 0x59c2b7c515e454ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x4c6770c93d5b9432, 0x1948a7c16aa31cfa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x459737995befd669, 0x2b38138d354ed15b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x79dd7d77263d3455, 0x1d9ac45564ea80b8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x26886e0763c87908, 0x0a2b5f603f44467b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x1e550a0f09423b01, 0x7584042476aea26e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x2461af5d4838f45b, 0x433cbe764315b45d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x31e1547c2dc248e9, 0x53ff912364525fd8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x04d32c79137f5c53, 0x7a36b4925f26b7e1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x50daf0857501e868, 0x49c9d4db513a9d43, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x50f1bed1242432f3, 0x06896e9e1672281e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x4a61674805880837, 0x7b5ca8d64acf3c48, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x6950813f7f9786e8, 0x0a1382c470e9d54f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x08d9c1e92ad53634, 0x679877be07a58b4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x730e2a8f1ebad0cf, 0x4abb3fab2d3b7146, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x4c7d19b80bc485b1, 0x118dd11e24ef7f0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x1f43e2044de00bc7, 0x041636ec51504631, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x42e1f42f29145212, 0x228ae374701ed28a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x4d38850501eda37f, 0x0690faa813d3b300, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #30", 0x0775abb668b6720c, 0x5ea2ef481799ec4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #30", 0x684df8f4701c395b, 0x0883c19d70c62cf5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #30", 0x1af16f8f4326f7ef, 0x786bb8437127bade, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x61e1c8be2ff0fd43, 0x1e632c240dff9a1e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x3bb582f437055015, 0x32ef19292e5ee276, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x04e55bdc223a0c1c, 0x7faf28a75af964f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x4b4e5e2e51a9322b, 0x4b18378247c7500b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x5396d5aa3a3df254, 0x5b9b030b1886e334, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x22f4646038a4911f, 0x3020cf825b0c8160, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x28c0ca7b443e6698, 0x4bd2ae550b425d55, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x07655e871acd4457, 0x7c6a183343b23a0a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x4abe419a04a0ed52, 0x51b1d42969472745, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x3ba63d6817553263, 0x17a609bb0673c48e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x398f3e7f2c856109, 0x616d2987408b9944, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x7e2e933463edec5b, 0x0852e95004dd9cad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x1e2bdeaf4d854f63, 0x1d647fe151c568de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x0629e08378a49893, 0x2cd1ea3e41204310, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x3ce2ff2c48ccb898, 0x4c62a0652eeaaafe, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x6399fcef444eb931, 0x729ce50844485db3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x48efa68445358eb4, 0x2d8f84f92e583e8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x5c8ac11716392c9f, 0x34cc03180495e3ec, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x42be8da94d746680, 0x45217d301619ff96, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x316252dc385c1c25, 0x1af79c4440ed20dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x05e16b893f8473fa, 0x12b289bc4f8e318b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x38290c8e5d111500, 0x10ae749b0c0b4c0c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x25ddcd982d92dc12, 0x3af5f70a750c0bba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x71e1954466e3ee66, 0x3954696d0977ca88, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x2c197d1b6c9c0c2a, 0x37d009123ad13bc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x02d538ca04889ce4, 0x3f671fb408a43e32, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x51fd036539b5da0d, 0x1ebe3dc94593c673, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #30, #31", 0x7211f6321933710c, 0x0680e750035f5641, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #30, #31", 0x58b7e507639bfc68, 0x52ed87cc77f361bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #30, #31", 0x40ad11683ef4a4d1, 0x03feadc710e0f195, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x6c8780e43f4166bc, 0x05ecfd4f668adf01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x2625552327d2b29b, 0x7002a9895e691628, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x146ebec558a171a4, 0x193a51f0523ed23e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x5d2a0e8879a14e39, 0x5ae310701743f78f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x335728466358a553, 0x5cd7be022f2711ed, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x7c8c165f0573effb, 0x3286682e25691e79, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x690fec63215b2dfc, 0x1d5c80345543fb66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x604fd2cd6c11ea4a, 0x6624ecfb29bcfdcb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x2b535107004a8655, 0x1047dccc4cd753b1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x281d38f0447abbc9, 0x2b4069d95178a62a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x1d1c2d6d7e9a88d8, 0x23b778683c8bf7b6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x783bd71230a7ad48, 0x53cfef457a463bf6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x1400529b5bf3b612, 0x296d4de32b92ff58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x6167a60d6e589e06, 0x50fc1dd1108c68fa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x0fb3cc024bf5515c, 0x65d064614a779270, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x38073ba7047c6d08, 0x7434903b70039ecf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x04c6f35d681b5c5a, 0x3cdaf281635a8cae, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x2c961824588aab40, 0x34d332d82ce42c4e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x572534183d401349, 0x6970240449b24591, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x6de7c0916d65cf6b, 0x43f881874f610b2a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x4959857d4bf02854, 0x7af40a8301e8132c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x3a48c65a7844e088, 0x12747c272ac12b8a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x443a31e4696d4e35, 0x7538bdfa49fc925c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x6de9bb3d76db23ad, 0x3a00312c7c416d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x5ef68007146f2d11, 0x5f9bfa3972b0ae9b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x6cf9d8510904feed, 0x1f94dae90b8c982b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x4645123619375f44, 0x553eddbd441f0c6a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #0", 0x069d2eaf0e742217, 0x13801794342cd2c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #0", 0x5a644a6c4889621b, 0x3614e5f44ff6b42c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #0", 0x40ce42a36ff09db0, 0x7ab7dfb614ad10c6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x595debe618a9d44f, 0x5ea9a32305087488, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x0f84f7fc60e5dc4d, 0x0149e2134747a723, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x7555095e598d30a7, 0x39f855be6e7b7803, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x62922f944f46edec, 0x7a08102f624ee1b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x687e4d3039ee05ae, 0x266dee1a28d741cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x486227c61318fa87, 0x5d0414936f1b7be0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x5ba25ca339ca0fc3, 0x3f12300c22c67232, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x29baad73161d261b, 0x377382f81c709f46, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x2ec6fa6a22c2f5e2, 0x217913ce03189959, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x03a8d22f0458963b, 0x4a60407d3e4bf266, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x5de5c6e326cf7a99, 0x2cc76a6a78fddb8d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x7616688501baab57, 0x5b4cbd3d4077f677, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x3ba8b10646534cd5, 0x694f38425e94b5b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x596c475d0cc261a2, 0x4db03195040ad8cc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x468c71655e44cdf6, 0x26d14afe350ea400, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x7461f41272f85715, 0x517f434670471ed8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x15bb4cf73dbff8af, 0x735fb8322328ee7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x42188eea0e3c4b4d, 0x6174e0e319641f26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x350bc5e66daeb7f1, 0x1261fab31ffe55cd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x6f69634849c58487, 0x60764c452b222e6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x1018d15d576715b6, 0x09b6e4202b12144e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x6429775855ee3818, 0x2f1ced1a698518ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x3433060f70130000, 0x1e93bcba2ab5e8bd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x630b57150e5cbfc7, 0x1afd07952894fa21, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x4c1cb8762d32c980, 0x4bbde89d78c6a40c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x3b6f14cd248cbde6, 0x122ac3320e354761, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x123b75d70ea9e973, 0x2e339d2e707adab3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #1", 0x586f6dfb2553ed3f, 0x1b9d091e01a4d91f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #1", 0x7cbb02f55bd3da88, 0x2cb6ed6e68883f58, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #1", 0x31c212a170a114cc, 0x520d581260e47a4d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x60b414cc26976a9f, 0x0b9a630a65f518b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x34f42a675a47fb6e, 0x0e8a12d143bf6be2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x077ac4ef4eb0d321, 0x3c860fee0110e2dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x733d91073d79c76d, 0x0f462a3e42e9d9bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x4c23b0e04f01bd8e, 0x3364b470057906de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x7455aacd33d4cd6b, 0x071ddffd24931edb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x0fa8a7f45f28b645, 0x0d1b5e337110adc2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x4fc9cb115d8f8b19, 0x51f5280f416aba95, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x0426f5b935e9e616, 0x275fd345307ddfde, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x1031e18430c35bae, 0x743d4bc0391b2020, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x7f742ecf49722d3c, 0x3a2c02fd17aca673, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x06ebf4a90dfb34a0, 0x5a96803072b1bfd6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x5cfcf22e7f48a6b2, 0x782ac6b4530fa589, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x331d741d04be2298, 0x77a2c46551529cfc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x63e6d8de145872ce, 0x42634abe42c61c11, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x71e7fde72b90a9eb, 0x0430d6a633b0a3ef, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x617a9001586bcf8d, 0x642e83cd760ef3a0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x092f2b3c695616be, 0x2f2a13c071ac7186, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x32c843fa63ef9829, 0x095917f908a35a0b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x71eaccc9737fe096, 0x7b5519e239b438a3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x72c887480466a291, 0x0cc3de2c4ee7bef8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x0924c52a629da6b2, 0x203a5bf425e5fb66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x76f619806cdcee1e, 0x68ac17776d0b9e08, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x186d980904eac5c5, 0x20bc41f768de1768, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x5d5695520e171ec9, 0x5eed0b0879e8280b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x776d358774edb18a, 0x6b9499916685c08e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x58dd49b46a7e347c, 0x6f291a9a2a357981, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #2", 0x5dfe151270ad9050, 0x63e9b2244ac8167d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #2", 0x751432e239ea3169, 0x19afd57550c69c5b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #2", 0x1c87d81c5f58af38, 0x76ac97c17e38f80c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x4c359d560c00d80b, 0x6b449614137df19c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x10eb9dd05b49140d, 0x7c5c090464a33560, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x696032d64a1ff6fc, 0x5e8b5d6b6e423323, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x3f0da88643f10e4b, 0x54c7f3b160cd685d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x2e6f42c76eec9402, 0x0b02e1de17eaf23a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x5f9a24527c62de2d, 0x62b308b80c6d57da, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x364d0f9753e08bf6, 0x5d33f43554ae5734, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x33393b2e3e2be554, 0x52e74f4052d4e7b3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x4a2cbd6062aee254, 0x6652d94f7f6ed885, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x3df7f661429d6b50, 0x64120de55b185b30, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x0cbd624c1e228205, 0x495a8e5327582937, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x6213905013287372, 0x082591944bcb0ad2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x02150774466905c5, 0x63b5fd0d1082d318, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x42cbe3f27a241f27, 0x1cf02af261af2bc6, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x4e04ab1d0944d23b, 0x365d82fb7918f389, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x4770b7903240b48c, 0x4beddb3c013de64b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x14ef96e064beccb5, 0x00acbed0119d74f0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x275c380536105e74, 0x6cb5d02052e78d41, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x5432e0790265480c, 0x7a3fb67834199a51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x158dbb7e639aa231, 0x7fe4a524364670c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x2a03a7f663b96ed3, 0x46c943e117a2c2f2, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x5ddd8dfa2faf71b3, 0x7951eeb86ccf8be8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x38f443ef31d65aae, 0x65e87f722be23917, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x64170f3a2dccde33, 0x2d201f630064fb7f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x128baae97eb8408f, 0x1202706f7906a61a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x34c89f03462de9d3, 0x4bee335b39e7e2ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x489331df6de62264, 0x6e017d4008fb7f7c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #3", 0x5180c495060b3427, 0x3f41f0465e20ed5d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #3", 0x69c4a2fb6f159f08, 0x75c3b04f7b846c8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #3", 0x1ec510bb4e3c77e5, 0x6853f87347a230f5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x0012d29420a48970, 0x73846a0d57b954aa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x4e7167a36a20c098, 0x581e50296429e1ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x68d90128291ebb44, 0x5d3087e960fd128c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x6f4ca51808e672bb, 0x1ae4f57b1da1a02b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x76cc951f65df0fee, 0x269d1fa837dfd6f7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x6bea44150bc474a4, 0x1600c455484d59b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x7ada13ac2c25beb2, 0x43d1c63f55aee710, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x7a62369810d58213, 0x1d511806199f2468, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x317a0b834976c93c, 0x715879127a75092c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x339789d43bcf72e3, 0x5e9eeafa7feb7326, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x64ee2e287bcd7b2e, 0x60e885b31c708afc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x04b3ede960af4ad0, 0x3a122b28543ad340, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x468e5abe221b6e8c, 0x0c1aaa377b808308, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x2ddfe331079fa2fb, 0x43cddcbc32789ed3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x33c561ad25789dea, 0x082785e428b9f6dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x364e1ffd33b19458, 0x42591b452e279845, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x7d285d94073b8c6c, 0x289ca17167c82b80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x430aff4f489c2459, 0x67b39ea630bfe768, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x44699f8707429d8d, 0x4d30726527f92d77, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x67f1e85d084eaaef, 0x7c3400b7491d8d70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x2a6a197b086bed34, 0x449e10782e80431b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x100b902f692067d2, 0x60f8e1ee5849fcac, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x0e9905bc435d0ecf, 0x0103f38a43d0f1dd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x770ea3271a952b94, 0x71f88a2244e725b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x21d0b8001462efe0, 0x2caf5139743700bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x5cff143972275a89, 0x24f6e82464dbb74f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x7969f8160908e57e, 0x0cd4e4c72168b3c1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #10", 0x1157906d2f2451aa, 0x6a864131615be073, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #10", 0x37903ede70d5057c, 0x0fdc238e3bc1a9e9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #10", 0x59f56d4f150f9a1f, 0x140ba695479bcf0e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x586ca8ef7d654b0d, 0x0b6cc0eb688e730b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x17fa76a15a24e9fe, 0x2d7598c54f7b4c16, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x6e87d9de68a934f6, 0x43b24cd239cb2ea1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x5ad08f7f2b7bcab8, 0x1ea6e5f14b86ee18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x3484b0365775e30a, 0x6cefa1d9543a8795, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x069a34b445728b96, 0x3596680845dc40a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x3647911215a99122, 0x019dea8d3e2a7393, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x2ab92b421133038c, 0x05c642a1103cfe61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x0e984e9926410a32, 0x78cb716d0325d431, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x0065f43016536d19, 0x52a120472692c53b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x7efca20f7f04d9cd, 0x605df3dc6eedce0f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x2a80a48527645e00, 0x3a74bc2759cd318e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x7eda410a639e212b, 0x2e07b9235f0554bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x2910acc1267f7fed, 0x24e19560057475bf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x3c29110f49652bf3, 0x439ee9525f583dd4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x5a982f7f6860ada2, 0x6f953c3566e23c51, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x0ea1b7d43ca930ca, 0x6a08108269307e18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x52fc9de370213730, 0x0fc343530f07ac05, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x6f2610fd386a363b, 0x7df57a1451f93ff3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x5fce943b59ce2aa5, 0x2bc6718119a6b583, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x3d6c4bd01d8d9f9f, 0x78ac0a3f5ea8d545, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x440d1f8c27bc3456, 0x641d4b04667cf892, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x71216049356a729b, 0x45d536660036309b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x1dcb203e51207d6f, 0x67186ced4bb98fc8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x0dc9ae3944ad5134, 0x34ea0de12c6cd812, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x34ce88643969fe2b, 0x3b74841760c64c1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x71d434665e85fd91, 0x32bf8c1023f49962, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #17", 0x3854283636475924, 0x3d9b4ee551a2c8a1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #17", 0x53d4f8c31468e8eb, 0x304b9de775c07407, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #17", 0x3c251d422212a2ff, 0x5c3d6c9917e2184f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x577d159a7f30b5d7, 0x181848ea2d467d8b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x505133472dea1b35, 0x79000d54754835d8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x72976c695d299202, 0x21b50deb5e1ae180, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x1693902e71a0b9ad, 0x3ee12d9d2765f4ce, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x5026b73f08f5dd15, 0x4b5a8e300867c494, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x3f3d36390a562b1d, 0x5a0a8d36087adf75, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x1ebf14085a78c015, 0x7e3b537c13122efc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x7c8b6314430c9035, 0x2af4474b5ae4314a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x423d460d012abc2a, 0x082aaed6540878af, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x2f14d75f6b05bc72, 0x4950ae87128e7954, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x482f4e752f8a8872, 0x70a95ad421ac43c8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x212b421f146cc6c6, 0x491238965ec2dea3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x1d62a3db4135306d, 0x672aa3377151f95e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x4b8b5b8a78082c50, 0x79ccd8d45c9fda14, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x5280ec661aa6505b, 0x6fb209106a4a6f93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x5db2e0914d594fb3, 0x452ea0dd4f0c4f7a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x4e840bdd6c6576b1, 0x2314c8291ff0269e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x576b33232327fac6, 0x327e9ff27d98e33c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x52b2833868575f9b, 0x1f4527051f9a8198, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x7cc4266265880373, 0x7e5d603b73ddc558, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x26bd33e05efc978a, 0x652fbeb61a26ca3d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x5704c3db6678ad62, 0x76c6a45272488f6b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x011efdbe21c19fdb, 0x5c92fefe2985b041, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x6f1aef8f1ba6c7e5, 0x7891ffbb5ed1de4f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x080c3e963140a4df, 0x7ec204ed3d9efb6c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x54689fa55a7d05ae, 0x3b37dea95f7771b9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x42d465497d6f538d, 0x7f11f352271b22de, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #24", 0x62f757000028a6ec, 0x1af8e8363f988bab, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #24", 0x5f253e775085fa3b, 0x59bf55e909b48ae1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #24", 0x36fea79d5890194a, 0x7bfd1a4c362a0252, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x7a51b9255841b24e, 0x5fafb293381da55b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x73e87a3315b18897, 0x16ef83aa696ca8b4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x46f22d76624382ca, 0x270ba4217bf4b8c9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x3cc088785a7e1dd5, 0x5b6c2a831b5acd1c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x57ed71625d6ed830, 0x4275effa7f94edc1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x5d977f1c18eccf56, 0x3f2d796d3ae4c863, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x6972c99140966d90, 0x449953443cbcbd93, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x192686da52967278, 0x72e6bfe52071712e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x2ad824c76f7e9a34, 0x588f168a13783fff, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x053022cc23f08cd5, 0x7ce4e8b41ec09efa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x06340f9f76218247, 0x1ab557c44c225042, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x509fa01c29f30d58, 0x677d1d5e42f49817, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x0761e58801b6ff45, 0x428985d8288d117e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x1aa3ce9b280b2d25, 0x6371d9e164f964a5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x68a19ab5149ce21e, 0x21b622380416982c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x673354967d171fe5, 0x2488095b01c8218f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x6c95ba1912254a43, 0x1540618f120b795d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x3615d7184b81701c, 0x30cc185871c5dce5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x41a2f26325654a86, 0x3de82d283c49e6b7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x4f5857df41c804a6, 0x7f3e7ece1242927f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x437f03ec1e417ddf, 0x3acfa3fd56ba3d67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x464cab045d69c445, 0x3bb3a20c5e22d287, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x7206a66306c1740f, 0x62396ab42eee45ba, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x03d893f445f6c8d8, 0x30b667495939faf9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x581c131b1c118caf, 0x6b457457706e4e0d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x6792fccb201c581b, 0x62342af30e31ea33, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x4581a2a149ba4fb8, 0x4a7bd0ea2935ef2e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #28", 0x0b82545f764825aa, 0x3b7881ad14d9fa80, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #28", 0x1489a3892747d9f4, 0x6b9437e84f01584b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #28", 0x04b19e390f5d9586, 0x2d242ad25ad64e8e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x161f09953a7afb91, 0x09c4944876b8449c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x0071c46a3b37b3ed, 0x4ff23f9619f79d89, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x5749409c6c9a168a, 0x0a65eb97588dd785, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x0cb66ea5313b92a3, 0x66bfc1b93edc3d67, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x7af5e25c238aae42, 0x68122c9552381146, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x19d2d3ec52a643af, 0x67120bc7067836bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x79ee1da3029db9d8, 0x55798f062e5c7776, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x11fb4f5f12f75a4c, 0x0932c6047e9fbbdd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x4d7255dd454a400f, 0x75580079281a58f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x0081f3fc4c77e215, 0x4211f67e4de41a47, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x3911f89f0d31b386, 0x2671f1cd57cb3498, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x3e6d46297eb99e94, 0x16a771ff45c86744, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x22444cd67f128451, 0x1800788a39632885, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x51b8c8001554ee46, 0x3fdb5f403c1720c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x17f2a81f73a65e3d, 0x6a7398394ba6e5a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x069db8893f9ea1fa, 0x4a46a18129edf77e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x04e8e20a141a46f0, 0x5208507254100e66, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x6092290548661a7b, 0x21f428ae056ad606, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x5597ce0173dd7c9e, 0x5d360a9f19a421a4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x72971b33776d0173, 0x5f6c88e81405142a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x767f85c40d439bf0, 0x4d683cb014db6809, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x22988a373b662105, 0x50f288cc48384dc5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x2f0c7f425e25d4ea, 0x13df33693a8b3256, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x1dc476e436817a46, 0x647929d435aa37cb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x4a9bc1372bae6ee0, 0x09ba463222ad58ee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x7414895b054e3994, 0x28182ef52b2dea3c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x792bb632243e94c9, 0x44d20be149ac575c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #29", 0x1bab963c2b19a836, 0x5db16b866bc2d165, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #29", 0x385d44275190c23b, 0x009e396f122b1c01, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #29", 0x0cf6e3416e429d2f, 0x5a6369c65af5ce5e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x4c68721979fa2a88, 0x158100b43c036283, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x307ba4ce7b67e081, 0x71ad9a4f6a2ce8fd, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x27164f6134f270e1, 0x0cda41ec7b176605, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x3a40aa756b175c23, 0x264550421b2ad8bc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x0f55f0ec42889b9e, 0x64d73018336c60a7, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x6da243d51fcd6b7c, 0x1f2f320d2b018729, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x715e2db717900cf0, 0x3d2ca32a25ff87fc, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x05d2aa1f1676570e, 0x00f5565a7e5510f8, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x107081962c060dcb, 0x3a58737c523b1c38, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x276dee4c49424721, 0x3c68053540ec2664, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x7e34b8026248dcac, 0x3c038c6a4e843dad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x4d6038cf4e864681, 0x69af166938756277, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x110ee21f0b10f52c, 0x6be1c31f5cb629bb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x2ade60a844e4540e, 0x07b7b0e47eb125f4, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x5c7460fe25a6044a, 0x24b0adf01c3c8e5f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x3c1c5b5854ea12d4, 0x1a919f5862470b1d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x00f0209f70ea2c8b, 0x348227554c8cdcee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x3a2c73ac497c8fbd, 0x0d790353285e0eeb, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x2bc56c6960916301, 0x76e24c9838612baf, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x2f17a9825cb85145, 0x70d68e267925a538, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x67c946715d937fd8, 0x55dbcef340268ba1, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x2277d3e663885f86, 0x3ed7b19612a7a719, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x092e63d14975d4d1, 0x2ee435797eec34e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x1e5fe7a515b56758, 0x61334002454abf29, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x069f93e31f509f6b, 0x11d79c181f500844, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x68cd2f283e9063c7, 0x47ae172f40cc078f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x1f21c6c86a03c165, 0x792d333e14929b91, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #30", 0x46bc12aa63940fbc, 0x0db840c94e39704a, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #30", 0x41278f944d37ad81, 0x0e5ffbeb2e85591c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #30", 0x30c00d08701135ae, 0x412d0035639f637b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x39870a7f43bed862, 0x628b986039ee70d9, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x59743fba1110cc1a, 0x7f39300257e6f224, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x30616b853ee51197, 0x7736fa686013d39d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x7d75755e1a0d0e6b, 0x20dfdb2d192e9aad, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x0410cfd03b797707, 0x2dc1363e1c973c26, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x1f0d86c47930a85c, 0x6ad0ac704acce27b, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x466855dd3a7f3bcc, 0x79523b9760351658, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x2a90717b26601233, 0x43d479d3772862e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x6a1eea96305003c1, 0x3116d3be64177bfa, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x4160cfdb33356887, 0x3bfe6e1f43932a50, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x721a7a1f4486d91b, 0x23a6fdee71c23b61, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x5e93e78638b20c4d, 0x0af0d60e6f8fef7d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x742b835476f7d814, 0x0c272ba462a4b757, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x7028807026c3d569, 0x2d7199d213390a18, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x6143113537429a44, 0x736e20713690d64e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x5da2ac785ed00cf2, 0x2db939330bd382b0, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x0f2010b32be96cca, 0x6feafeab47c1970e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x5f1ed5512efbbf4c, 0x0b54c15e5080e08e, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x738298674d33f1fe, 0x42431bef51394f70, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x05e5fe4b4cf06a92, 0x40c93eee52167fee, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x43e842a6622cd117, 0x34bb37457a11819f, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x08f0a68000b8ac29, 0x0d4a8bb83410c317, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x37fb466d185ad298, 0x6aa199656a33b7b5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x772adf8a65f23911, 0x76073a66159df2e5, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x11dba5db68b44b52, 0x5d5f89f3064af03d, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x17b00a9e190eecbb, 0x56cbd0cc70fa7b2c, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x6642deb902fd098b, 0x4233ca9d0b32a306, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; ubfm w3, w4, #31, #31", 0x4fed741d12045a39, 0x5d4922f46c28dd04, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; sbfm w3, w4, #31, #31", 0x74312b507384ea5c, 0x663a5ea413d5b6c3, x3, x4, x5, 0); -+TESTINST3("mov x3, x5 ; bfm w3, w4, #31, #31", 0x743d96853288133f, 0x47e679da7d21d1d0, x3, x4, x5, 0); -+ -+#endif /* if TEST_BFM */ -+ -+//////////////////////////////////////////////////////////////// -+printf("EXTR(64)\n"); -+ -+TESTINST3("extr x3, x4, x5, #0", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #0", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #0", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #0", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #0", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #0", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #1", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #1", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #1", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #1", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #1", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #2", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #2", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #2", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #2", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #2", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #2", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #3", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #3", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #3", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #3", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #3", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #3", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #32", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #32", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #32", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #32", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #32", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #32", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #60", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #60", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #60", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #60", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #60", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #60", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #61", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #61", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #61", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #61", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #61", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #61", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #62", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #62", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #62", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #62", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #62", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #62", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr x3, x4, x5, #63", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0xe57b3a514f5207f4, 0x8ef7bac0f0ac903a, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0x9d4a481b12743bf8, 0x9f014e8d2644ee47, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0xefdd33d64e6d6a8b, 0x44e875422d202c19, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0x5c6c9b2a7f109f5b, 0x568ee275e665f075, x3, x4, x5, 0); -+TESTINST3("extr x3, x4, x5, #63", 0x9b14b0a4fbbd2c11, 0x6b5bac44aaa93980, x3, x4, x5, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("EXTR(32)\n"); -+ -+TESTINST3("extr w3, w4, w5, #0", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #0", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #0", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #0", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #0", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #0", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #1", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #1", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #1", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #1", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #1", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #2", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #2", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #2", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #2", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #2", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #2", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #3", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #3", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #3", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #3", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #3", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #3", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #16", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #16", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #16", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #16", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #16", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #16", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #28", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #28", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #28", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #28", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #28", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #28", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #29", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #29", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #29", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #29", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #29", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #29", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #30", 0xdb432311d1e3a1d0, 0xa6325ae016fbd710, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #30", 0x192e7217e1ab63b0, 0xfd370f11bfcd4a4a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #30", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #30", 0xc58586ea2c6954df, 0xe861540945421773, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #30", 0xe51579fec3892795, 0x507865169b052546, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #30", 0x1b834ed5b21de6b5, 0x9a1140d0fd1dbf6c, x3, x4, x5, 0); -+ -+TESTINST3("extr w3, w4, w5, #31", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0xe57b3a514f5207f4, 0x8ef7bac0f0ac903a, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0x9d4a481b12743bf8, 0x9f014e8d2644ee47, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0xefdd33d64e6d6a8b, 0x44e875422d202c19, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0x5c6c9b2a7f109f5b, 0x568ee275e665f075, x3, x4, x5, 0); -+TESTINST3("extr w3, w4, w5, #31", 0x9b14b0a4fbbd2c11, 0x6b5bac44aaa93980, x3, x4, x5, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("ADD/SUB(reg,64)\n"); -+ -+TESTINST3("add x7,x8,x9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,lsl #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,lsl #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("adds x7,x8,x9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsl #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsl #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsl #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("add x7,x8,x9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,lsr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,lsr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("adds x7,x8,x9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,lsr #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("add x7,x8,x9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,asr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("add x7,x8,x9,asr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("adds x7,x8,x9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,asr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,asr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("adds x7,x8,x9,asr #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("sub x7,x8,x9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,lsl #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,lsl #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("subs x7,x8,x9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsl #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsl #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsl #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("sub x7,x8,x9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,lsr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,lsr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("subs x7,x8,x9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,lsr #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("sub x7,x8,x9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,asr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("sub x7,x8,x9,asr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("subs x7,x8,x9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,asr #62", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,asr #63", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,asr #0 ", ALL5s, ALL5s, x7,x8,x9,0); -+TESTINST3("subs x7,x8,x9,asr #0 ", ALLas, ALL5s, x7,x8,x9,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("ADD/SUB(reg,32)\n"); -+ -+TESTINST3("add w7,w8,w9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,lsl #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,lsl #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("adds w7,w8,w9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsl #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsl #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsl #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("add w7,w8,w9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,lsr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,lsr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("adds w7,w8,w9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,lsr #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("add w7,w8,w9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,asr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("add w7,w8,w9,asr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("adds w7,w8,w9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,asr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,asr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("adds w7,w8,w9,asr #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("sub w7,w8,w9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,lsl #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,lsl #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("subs w7,w8,w9,lsl #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsl #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsl #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsl #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsl #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("sub w7,w8,w9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,lsr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,lsr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("subs w7,w8,w9,lsr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,lsr #0 ", 1+ALL5s, ALLas, x7,x8,x9,0); -+ -+TESTINST3("sub w7,w8,w9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,asr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("sub w7,w8,w9,asr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+ -+TESTINST3("subs w7,w8,w9,asr #0", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,asr #1", 0xfc9a9d8be2434f5e, 0x6a13f7db3dfa4a3f, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,asr #30", 0xd98d2022a9b876ab, 0xa7e754e8ff3a554e, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,asr #31", 0x33566e6515990527, 0x3d7e7390195d82e2, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,asr #0 ", ALL5s, ALL5s, x7,x8,x9,0); -+TESTINST3("subs w7,w8,w9,asr #0 ", ALLas, ALL5s, x7,x8,x9,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("LOGIC(reg,64)\n"); -+ -+TESTINST3("and x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("and x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("and x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("and x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("orr x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orr x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orr x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orr x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("eor x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eor x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eor x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eor x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("ands x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("ands x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("ands x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("ands x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+TESTINST3("ands x7,x8,x9,ror #22", ALL5s, ALLas, x7,x8,x9,0); -+ -+ -+TESTINST3("bic x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bic x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bic x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bic x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("orn x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orn x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orn x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orn x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("eon x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eon x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eon x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eon x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("bics x7,x8,x9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,lsl #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,lsl #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bics x7,x8,x9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,lsr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,lsr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bics x7,x8,x9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,asr #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,asr #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bics x7,x8,x9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,ror #62", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics x7,x8,x9,ror #63", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("LOGIC(reg,32)\n"); -+ -+TESTINST3("and w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("and w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("and w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("and w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("and w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("orr w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orr w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orr w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orr w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orr w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("eor w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eor w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eor w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eor w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eor w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("ands w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("ands w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("ands w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("ands w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+TESTINST3("ands w7,w8,w9,ror #22", ALL5s, ALLas, x7,x8,x9,0); -+ -+ -+TESTINST3("bic w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bic w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bic w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bic w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bic w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("orn w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orn w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orn w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("orn w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("orn w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("eon w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eon w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eon w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("eon w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("eon w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+TESTINST3("bics w7,w8,w9,lsl #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,lsl #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,lsl #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,lsl #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bics w7,w8,w9,lsr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,lsr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,lsr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,lsr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bics w7,w8,w9,asr #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,asr #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,asr #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,asr #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+TESTINST3("bics w7,w8,w9,ror #0", 0xdb432311d1e3a1d5, 0xa6325ae016fbd71a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,ror #1", 0xfd79baaee550b488, 0x5bc94f0d3ee4863a, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,ror #30", 0xc58586ea2c6954df, 0xe861540945421773, x7,x8,x9,0); -+TESTINST3("bics w7,w8,w9,ror #31", 0xfb834ed5b21de6b5, 0x9a1140d0fd1dbf6f, x7,x8,x9,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("UMULH/SMULH\n"); -+ -+TESTINST3("umulh x9,x8,x7", 0xefdd33d64e6d6a8b, 0x44e875422d202c19, x9,x8,x7,0); -+TESTINST3("umulh x9,x8,x7", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x9,x8,x7,0); -+TESTINST3("umulh x9,x8,x7", 0xe57b3a514f5207f4, 0x8ef7bac0f0ac903a, x9,x8,x7,0); -+ -+TESTINST3("smulh x9,x8,x7", 0xefdd33d64e6d6a8b, 0x44e875422d202c19, x9,x8,x7,0); -+TESTINST3("smulh x9,x8,x7", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x9,x8,x7,0); -+TESTINST3("smulh x9,x8,x7", 0xe57b3a514f5207f4, 0x8ef7bac0f0ac903a, x9,x8,x7,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("MADD/MSUB\n"); -+ -+TESTINST4("madd x30,x26,x28,x27", -+ 0x7a3847909557e2b4, 0xcbbb98441b9e1029, 0x6a13f7db3dfa4a3f, x30,x26,x28,x27,0); -+TESTINST4("madd x30,x26,x28,x27", -+ 0xe39b12157cf9610f, 0x0eb420e934db9f92, 0x7564a539bf3eb84d, x30,x26,x28,x27,0); -+TESTINST4("madd x30,x26,x28,x27", -+ 0xd7588df1ecb46297, 0x26557c93f44473fa, 0x09fb0ab6a60b34c3, x30,x26,x28,x27,0); -+TESTINST4("madd x30,x26,x28,x27", -+ 0x4f0c54f61ac8f7bd, 0x99b1794bbb4b19cd, 0x52d448b3d56f5369, x30,x26,x28,x27,0); -+TESTINST4("madd x30,x26,x28,x27", -+ 0x5370e6469b1e28ed, 0x0a1925a090f7aaf5, 0xa7e754e8ff3a554e, x30,x26,x28,x27,0); -+ -+TESTINST4("msub x30,x26,x28,x27", -+ 0x7a3847909557e2b4, 0xcbbb98441b9e1029, 0x6a13f7db3dfa4a3f, x30,x26,x28,x27,0); -+TESTINST4("msub x30,x26,x28,x27", -+ 0xe39b12157cf9610f, 0x0eb420e934db9f92, 0x7564a539bf3eb84d, x30,x26,x28,x27,0); -+TESTINST4("msub x30,x26,x28,x27", -+ 0xd7588df1ecb46297, 0x26557c93f44473fa, 0x09fb0ab6a60b34c3, x30,x26,x28,x27,0); -+TESTINST4("msub x30,x26,x28,x27", -+ 0x4f0c54f61ac8f7bd, 0x99b1794bbb4b19cd, 0x52d448b3d56f5369, x30,x26,x28,x27,0); -+TESTINST4("msub x30,x26,x28,x27", -+ 0x5370e6469b1e28ed, 0x0a1925a090f7aaf5, 0xa7e754e8ff3a554e, x30,x26,x28,x27,0); -+ -+TESTINST4("madd w30,w26,w28,w27", -+ 0x7a3847909557e2b4, 0xcbbb98441b9e1029, 0x6a13f7db3dfa4a3f, x30,x26,x28,x27,0); -+TESTINST4("madd w30,w26,w28,w27", -+ 0xe39b12157cf9610f, 0x0eb420e934db9f92, 0x7564a539bf3eb84d, x30,x26,x28,x27,0); -+TESTINST4("madd w30,w26,w28,w27", -+ 0xd7588df1ecb46297, 0x26557c93f44473fa, 0x09fb0ab6a60b34c3, x30,x26,x28,x27,0); -+TESTINST4("madd w30,w26,w28,w27", -+ 0x4f0c54f61ac8f7bd, 0x99b1794bbb4b19cd, 0x52d448b3d56f5369, x30,x26,x28,x27,0); -+TESTINST4("madd w30,w26,w28,w27", -+ 0x5370e6469b1e28ed, 0x0a1925a090f7aaf5, 0xa7e754e8ff3a554e, x30,x26,x28,x27,0); -+ -+TESTINST4("msub w30,w26,w28,w27", -+ 0x7a3847909557e2b4, 0xcbbb98441b9e1029, 0x6a13f7db3dfa4a3f, x30,x26,x28,x27,0); -+TESTINST4("msub w30,w26,w28,w27", -+ 0xe39b12157cf9610f, 0x0eb420e934db9f92, 0x7564a539bf3eb84d, x30,x26,x28,x27,0); -+TESTINST4("msub w30,w26,w28,w27", -+ 0xd7588df1ecb46297, 0x26557c93f44473fa, 0x09fb0ab6a60b34c3, x30,x26,x28,x27,0); -+TESTINST4("msub w30,w26,w28,w27", -+ 0x4f0c54f61ac8f7bd, 0x99b1794bbb4b19cd, 0x52d448b3d56f5369, x30,x26,x28,x27,0); -+TESTINST4("msub w30,w26,w28,w27", -+ 0x5370e6469b1e28ed, 0x0a1925a090f7aaf5, 0xa7e754e8ff3a554e, x30,x26,x28,x27,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("CS{EL,INC,INV,NEG}(64)\n"); -+ -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csel x16,x17,x18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinc x16,x17,x18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csinv x16,x17,x18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp x17,x18 ; csneg x16,x17,x18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("CS{EL,INC,INV,NEG}(32)\n"); -+ -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csel w16,w17,w18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinc w16,w17,w18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csinv w16,w17,w18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,eq", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,ne", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,cc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,cs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,mi", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,pl", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,vc", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+TESTINST3("cmp w17,w18 ; csneg w16,w17,w18,vs", -+ 0xafa6ef803bc9291c, 0x7a6c3d1a51246495, x16,x17,x18,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("ADD/SUB(extended reg)(64)\n"); -+ -+#define NN0 0xa3ca7e66297c469b -+#define NN1 0xa67e09b8e126596c -+#define NN2 0x09fb0ab6a60b34c3 -+#define NN3 0x2584971088d90924 -+#define NN4 0x52d448b3d56f5369 -+#define NN5 0xd98d2022a9b876ab -+#define NN6 0xa7e754e8ff3a554e -+#define NN7 0x7ab2520302849409 -+#define NN8 0x2e10f2a4055bec0e -+#define NN9 0x77f3b8dcc730b96a -+ -+TESTINST3("add x21,x22,x23,uxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("add x21,x22,x23,uxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("add x21,x22,x23,uxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("add x21,x22,x23,uxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,uxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("add x21,x22,x23,sxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("add x21,x22,x23,sxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("add x21,x22,x23,sxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("add x21,x22,x23,sxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("add x21,x22,x23,sxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+ -+TESTINST3("adds x21,x22,x23,uxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("adds x21,x22,x23,uxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("adds x21,x22,x23,uxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("adds x21,x22,x23,uxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,uxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("adds x21,x22,x23,sxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("adds x21,x22,x23,sxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("adds x21,x22,x23,sxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("adds x21,x22,x23,sxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("adds x21,x22,x23,sxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+ -+TESTINST3("sub x21,x22,x23,uxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("sub x21,x22,x23,uxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("sub x21,x22,x23,uxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("sub x21,x22,x23,uxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,uxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("sub x21,x22,x23,sxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("sub x21,x22,x23,sxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("sub x21,x22,x23,sxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("sub x21,x22,x23,sxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("sub x21,x22,x23,sxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+ -+TESTINST3("subs x21,x22,x23,uxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("subs x21,x22,x23,uxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("subs x21,x22,x23,uxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("subs x21,x22,x23,uxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,uxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("subs x21,x22,x23,sxtb #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtb #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtb #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtb #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtb #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("subs x21,x22,x23,sxth #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxth #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxth #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxth #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxth #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("subs x21,x22,x23,sxtw #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtw #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtw #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtw #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtw #4", NN8, NN9, x21,x22,x23,0); -+ -+TESTINST3("subs x21,x22,x23,sxtx #0", NN0, NN1, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtx #1", NN2, NN3, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtx #2", NN4, NN5, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtx #3", NN6, NN7, x21,x22,x23,0); -+TESTINST3("subs x21,x22,x23,sxtx #4", NN8, NN9, x21,x22,x23,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("ADD/SUB(extended reg)(32)\n"); -+ -+TESTINST3("add w21,w22,w23,uxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("add w21,w22,w23,uxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("add w21,w22,w23,uxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("add w21,w22,w23,uxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,uxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("add w21,w22,w23,sxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("add w21,w22,w23,sxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("add w21,w22,w23,sxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("add w21,w22,w23,sxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("add w21,w22,w23,sxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+ -+TESTINST3("adds w21,w22,w23,uxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("adds w21,w22,w23,uxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("adds w21,w22,w23,uxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("adds w21,w22,w23,uxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,uxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("adds w21,w22,w23,sxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("adds w21,w22,w23,sxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("adds w21,w22,w23,sxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("adds w21,w22,w23,sxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("adds w21,w22,w23,sxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+ -+TESTINST3("sub w21,w22,w23,uxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("sub w21,w22,w23,uxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("sub w21,w22,w23,uxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("sub w21,w22,w23,uxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,uxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("sub w21,w22,w23,sxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("sub w21,w22,w23,sxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("sub w21,w22,w23,sxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("sub w21,w22,w23,sxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("sub w21,w22,w23,sxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+ -+TESTINST3("subs w21,w22,w23,uxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("subs w21,w22,w23,uxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("subs w21,w22,w23,uxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("subs w21,w22,w23,uxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,uxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("subs w21,w22,w23,sxtb #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtb #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtb #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtb #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtb #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("subs w21,w22,w23,sxth #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxth #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxth #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxth #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxth #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("subs w21,w22,w23,sxtw #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtw #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtw #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtw #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtw #4", NN8, NN9, x21,x22,x23 ,0); -+ -+TESTINST3("subs w21,w22,w23,sxtx #0", NN0, NN1, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtx #1", NN2, NN3, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtx #2", NN4, NN5, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtx #3", NN6, NN7, x21,x22,x23 ,0); -+TESTINST3("subs w21,w22,w23,sxtx #4", NN8, NN9, x21,x22,x23 ,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("CCMP/CCMN(imm)(64)\n"); -+ -+#define PRE "msr nzcv,x24; " // nzcv = x24 -+#define POST "; mrs x23,nzcv" // x23 = nzcv (overall result) -+ -+#define TEST_CCMP_X_imm(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST3(PRE "ccmp x25,#" #argR_value ",#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, x23,x24,x25 ,0) -+ -+#define TEST_CCMN_X_imm(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST3(PRE "ccmn x25,#" #argR_value ",#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, x23,x24,x25 ,0) -+ -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x0); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x1); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x2); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x4); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x5); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x6); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x7); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x8); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x9); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0xA); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0xB); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0xC); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0xD); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0xE); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x0); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x1); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x2); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x4); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x5); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x6); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x7); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x8); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x9); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0xA); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0xB); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0xC); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0xD); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0xE); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_X_imm(0x1, eq, 17, 17, 0x6); -+TEST_CCMP_X_imm(0x2, eq, 17, 17, 0x5); -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_X_imm(0x8, eq, 17, 17, 0x7); -+TEST_CCMP_X_imm(0x1, lt, 17, 17, 0x6); -+TEST_CCMP_X_imm(0x2, lt, 17, 17, 0x5); -+TEST_CCMP_X_imm(0x4, lt, 17, 17, 0x3); -+TEST_CCMP_X_imm(0x8, lt, 17, 17, 0x7); -+TEST_CCMP_X_imm(0x1, gt, 17, 17, 0x6); -+TEST_CCMP_X_imm(0x2, gt, 17, 17, 0x5); -+TEST_CCMP_X_imm(0x4, gt, 17, 17, 0x3); -+TEST_CCMP_X_imm(0x8, gt, 17, 17, 0x7); -+TEST_CCMP_X_imm(0x1, ne, 17, 17, 0x6); -+TEST_CCMP_X_imm(0x2, ne, 17, 17, 0x5); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_X_imm(0x8, ne, 17, 17, 0x7); -+TEST_CCMP_X_imm(0x1, eq, 17, 18, 0x6); -+TEST_CCMP_X_imm(0x2, eq, 17, 18, 0x5); -+TEST_CCMP_X_imm(0x4, eq, 17, 18, 0x3); -+TEST_CCMP_X_imm(0x8, eq, 17, 18, 0x7); -+TEST_CCMP_X_imm(0x1, lt, 17, 18, 0x6); -+TEST_CCMP_X_imm(0x2, lt, 17, 18, 0x5); -+TEST_CCMP_X_imm(0x4, lt, 17, 18, 0x3); -+TEST_CCMP_X_imm(0x8, lt, 17, 18, 0x7); -+TEST_CCMP_X_imm(0x1, gt, 17, 18, 0x6); -+TEST_CCMP_X_imm(0x2, gt, 17, 18, 0x5); -+TEST_CCMP_X_imm(0x4, gt, 17, 18, 0x3); -+TEST_CCMP_X_imm(0x8, gt, 17, 18, 0x7); -+TEST_CCMP_X_imm(0x1, ne, 17, 18, 0x6); -+TEST_CCMP_X_imm(0x2, ne, 17, 18, 0x5); -+TEST_CCMP_X_imm(0x4, ne, 17, 18, 0x3); -+TEST_CCMP_X_imm(0x8, ne, 17, 18, 0x7); -+ -+ -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x0); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x1); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x2); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x4); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x5); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x6); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x7); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x8); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x9); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0xA); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0xB); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0xC); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0xD); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0xE); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x0); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x1); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x2); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x4); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x5); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x6); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x7); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x8); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x9); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0xA); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0xB); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0xC); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0xD); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0xE); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_X_imm(0x1, eq, -17, 17, 0x6); -+TEST_CCMN_X_imm(0x2, eq, -17, 17, 0x5); -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_X_imm(0x8, eq, -17, 17, 0x7); -+TEST_CCMN_X_imm(0x1, lt, -17, 17, 0x6); -+TEST_CCMN_X_imm(0x2, lt, -17, 17, 0x5); -+TEST_CCMN_X_imm(0x4, lt, -17, 17, 0x3); -+TEST_CCMN_X_imm(0x8, lt, -17, 17, 0x7); -+TEST_CCMN_X_imm(0x1, gt, -17, 17, 0x6); -+TEST_CCMN_X_imm(0x2, gt, -17, 17, 0x5); -+TEST_CCMN_X_imm(0x4, gt, -17, 17, 0x3); -+TEST_CCMN_X_imm(0x8, gt, -17, 17, 0x7); -+TEST_CCMN_X_imm(0x1, ne, -17, 17, 0x6); -+TEST_CCMN_X_imm(0x2, ne, -17, 17, 0x5); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_X_imm(0x8, ne, -17, 17, 0x7); -+TEST_CCMN_X_imm(0x1, eq, -17, 18, 0x6); -+TEST_CCMN_X_imm(0x2, eq, -17, 18, 0x5); -+TEST_CCMN_X_imm(0x4, eq, -17, 18, 0x3); -+TEST_CCMN_X_imm(0x8, eq, -17, 18, 0x7); -+TEST_CCMN_X_imm(0x1, lt, -17, 18, 0x6); -+TEST_CCMN_X_imm(0x2, lt, -17, 18, 0x5); -+TEST_CCMN_X_imm(0x4, lt, -17, 18, 0x3); -+TEST_CCMN_X_imm(0x8, lt, -17, 18, 0x7); -+TEST_CCMN_X_imm(0x1, gt, -17, 18, 0x6); -+TEST_CCMN_X_imm(0x2, gt, -17, 18, 0x5); -+TEST_CCMN_X_imm(0x4, gt, -17, 18, 0x3); -+TEST_CCMN_X_imm(0x8, gt, -17, 18, 0x7); -+TEST_CCMN_X_imm(0x1, ne, -17, 18, 0x6); -+TEST_CCMN_X_imm(0x2, ne, -17, 18, 0x5); -+TEST_CCMN_X_imm(0x4, ne, -17, 18, 0x3); -+TEST_CCMN_X_imm(0x8, ne, -17, 18, 0x7); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("CCMP/CCMN(imm)(32)\n"); -+ -+#define PRE "msr nzcv,x24; " // nzcv = x24 -+#define POST "; mrs x23,nzcv" // x23 = nzcv (overall result) -+ -+#define TEST_CCMP_W_imm(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST3(PRE "ccmp w25,#" #argR_value ",#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, x23,x24,x25 ,0) -+ -+#define TEST_CCMN_W_imm(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST3(PRE "ccmn w25,#" #argR_value ",#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, x23,x24,x25 ,0) -+ -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0xF); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0xF); -+TEST_CCMP_W_imm(0x4, eq, 17+(17ULL<<32), 17, 0xF); -+TEST_CCMP_W_imm(0x4, ne, 17+(17ULL<<32), 17, 0xF); -+ -+TEST_CCMP_X_imm(0x4, eq, 17, 17, 0xF); -+TEST_CCMP_X_imm(0x4, ne, 17, 17, 0xF); -+TEST_CCMP_X_imm(0x4, eq, 17+(17ULL<<32), 17, 0xF); -+TEST_CCMP_X_imm(0x4, ne, 17+(17ULL<<32), 17, 0xF); -+ -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x0); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x1); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x2); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x4); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x5); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x6); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x7); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x8); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x9); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0xA); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0xB); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0xC); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0xD); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0xE); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x0); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x1); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x2); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x4); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x5); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x6); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x7); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x8); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x9); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0xA); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0xB); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0xC); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0xD); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0xE); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_W_imm(0x1, eq, 17, 17, 0x6); -+TEST_CCMP_W_imm(0x2, eq, 17, 17, 0x5); -+TEST_CCMP_W_imm(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_W_imm(0x8, eq, 17, 17, 0x7); -+TEST_CCMP_W_imm(0x1, lt, 17, 17, 0x6); -+TEST_CCMP_W_imm(0x2, lt, 17, 17, 0x5); -+TEST_CCMP_W_imm(0x4, lt, 17, 17, 0x3); -+TEST_CCMP_W_imm(0x8, lt, 17, 17, 0x7); -+TEST_CCMP_W_imm(0x1, gt, 17, 17, 0x6); -+TEST_CCMP_W_imm(0x2, gt, 17, 17, 0x5); -+TEST_CCMP_W_imm(0x4, gt, 17, 17, 0x3); -+TEST_CCMP_W_imm(0x8, gt, 17, 17, 0x7); -+TEST_CCMP_W_imm(0x1, ne, 17, 17, 0x6); -+TEST_CCMP_W_imm(0x2, ne, 17, 17, 0x5); -+TEST_CCMP_W_imm(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_W_imm(0x8, ne, 17, 17, 0x7); -+TEST_CCMP_W_imm(0x1, eq, 17, 18, 0x6); -+TEST_CCMP_W_imm(0x2, eq, 17, 18, 0x5); -+TEST_CCMP_W_imm(0x4, eq, 17, 18, 0x3); -+TEST_CCMP_W_imm(0x8, eq, 17, 18, 0x7); -+TEST_CCMP_W_imm(0x1, lt, 17, 18, 0x6); -+TEST_CCMP_W_imm(0x2, lt, 17, 18, 0x5); -+TEST_CCMP_W_imm(0x4, lt, 17, 18, 0x3); -+TEST_CCMP_W_imm(0x8, lt, 17, 18, 0x7); -+TEST_CCMP_W_imm(0x1, gt, 17, 18, 0x6); -+TEST_CCMP_W_imm(0x2, gt, 17, 18, 0x5); -+TEST_CCMP_W_imm(0x4, gt, 17, 18, 0x3); -+TEST_CCMP_W_imm(0x8, gt, 17, 18, 0x7); -+TEST_CCMP_W_imm(0x1, ne, 17, 18, 0x6); -+TEST_CCMP_W_imm(0x2, ne, 17, 18, 0x5); -+TEST_CCMP_W_imm(0x4, ne, 17, 18, 0x3); -+TEST_CCMP_W_imm(0x8, ne, 17, 18, 0x7); -+ -+ -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0xF); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0xF); -+TEST_CCMN_W_imm(0x4, eq, -(17+(17ULL<<32)), 17, 0xF); -+TEST_CCMN_W_imm(0x4, ne, -(17+(17ULL<<32)), 17, 0xF); -+ -+TEST_CCMN_X_imm(0x4, eq, -17, 17, 0xF); -+TEST_CCMN_X_imm(0x4, ne, -17, 17, 0xF); -+TEST_CCMN_X_imm(0x4, eq, -(17+(17ULL<<32)), 17, 0xF); -+TEST_CCMN_X_imm(0x4, ne, -(17+(17ULL<<32)), 17, 0xF); -+ -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x0); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x1); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x2); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x4); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x5); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x6); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x7); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x8); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x9); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0xA); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0xB); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0xC); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0xD); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0xE); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x0); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x1); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x2); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x4); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x5); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x6); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x7); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x8); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x9); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0xA); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0xB); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0xC); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0xD); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0xE); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_W_imm(0x1, eq, -17, 17, 0x6); -+TEST_CCMN_W_imm(0x2, eq, -17, 17, 0x5); -+TEST_CCMN_W_imm(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_W_imm(0x8, eq, -17, 17, 0x7); -+TEST_CCMN_W_imm(0x1, lt, -17, 17, 0x6); -+TEST_CCMN_W_imm(0x2, lt, -17, 17, 0x5); -+TEST_CCMN_W_imm(0x4, lt, -17, 17, 0x3); -+TEST_CCMN_W_imm(0x8, lt, -17, 17, 0x7); -+TEST_CCMN_W_imm(0x1, gt, -17, 17, 0x6); -+TEST_CCMN_W_imm(0x2, gt, -17, 17, 0x5); -+TEST_CCMN_W_imm(0x4, gt, -17, 17, 0x3); -+TEST_CCMN_W_imm(0x8, gt, -17, 17, 0x7); -+TEST_CCMN_W_imm(0x1, ne, -17, 17, 0x6); -+TEST_CCMN_W_imm(0x2, ne, -17, 17, 0x5); -+TEST_CCMN_W_imm(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_W_imm(0x8, ne, -17, 17, 0x7); -+TEST_CCMN_W_imm(0x1, eq, -17, 18, 0x6); -+TEST_CCMN_W_imm(0x2, eq, -17, 18, 0x5); -+TEST_CCMN_W_imm(0x4, eq, -17, 18, 0x3); -+TEST_CCMN_W_imm(0x8, eq, -17, 18, 0x7); -+TEST_CCMN_W_imm(0x1, lt, -17, 18, 0x6); -+TEST_CCMN_W_imm(0x2, lt, -17, 18, 0x5); -+TEST_CCMN_W_imm(0x4, lt, -17, 18, 0x3); -+TEST_CCMN_W_imm(0x8, lt, -17, 18, 0x7); -+TEST_CCMN_W_imm(0x1, gt, -17, 18, 0x6); -+TEST_CCMN_W_imm(0x2, gt, -17, 18, 0x5); -+TEST_CCMN_W_imm(0x4, gt, -17, 18, 0x3); -+TEST_CCMN_W_imm(0x8, gt, -17, 18, 0x7); -+TEST_CCMN_W_imm(0x1, ne, -17, 18, 0x6); -+TEST_CCMN_W_imm(0x2, ne, -17, 18, 0x5); -+TEST_CCMN_W_imm(0x4, ne, -17, 18, 0x3); -+TEST_CCMN_W_imm(0x8, ne, -17, 18, 0x7); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("CCMP/CCMN(reg)(64)\n"); -+ -+#define PRE "msr nzcv,x24; " // nzcv = x24 -+#define POST "; mrs x23,nzcv" // x23 = nzcv (overall result) -+ -+#define TEST_CCMP_X_reg(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST4(PRE "ccmp x25,x26,#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, argR_value, x23,x24,x25,x26 ,0) -+ -+#define TEST_CCMN_X_reg(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST4(PRE "ccmn x25,x26,#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, argR_value, x23,x24,x25,x26 ,0) -+ -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x0); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x1); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x2); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x4); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x5); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x6); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x7); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x8); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x9); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0xA); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0xB); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0xC); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0xD); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0xE); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x0); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x1); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x2); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x4); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x5); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x6); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x7); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x8); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x9); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0xA); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0xB); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0xC); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0xD); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0xE); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_X_reg(0x1, eq, 17, 17, 0x6); -+TEST_CCMP_X_reg(0x2, eq, 17, 17, 0x5); -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_X_reg(0x8, eq, 17, 17, 0x7); -+TEST_CCMP_X_reg(0x1, lt, 17, 17, 0x6); -+TEST_CCMP_X_reg(0x2, lt, 17, 17, 0x5); -+TEST_CCMP_X_reg(0x4, lt, 17, 17, 0x3); -+TEST_CCMP_X_reg(0x8, lt, 17, 17, 0x7); -+TEST_CCMP_X_reg(0x1, gt, 17, 17, 0x6); -+TEST_CCMP_X_reg(0x2, gt, 17, 17, 0x5); -+TEST_CCMP_X_reg(0x4, gt, 17, 17, 0x3); -+TEST_CCMP_X_reg(0x8, gt, 17, 17, 0x7); -+TEST_CCMP_X_reg(0x1, ne, 17, 17, 0x6); -+TEST_CCMP_X_reg(0x2, ne, 17, 17, 0x5); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_X_reg(0x8, ne, 17, 17, 0x7); -+TEST_CCMP_X_reg(0x1, eq, 17, 18, 0x6); -+TEST_CCMP_X_reg(0x2, eq, 17, 18, 0x5); -+TEST_CCMP_X_reg(0x4, eq, 17, 18, 0x3); -+TEST_CCMP_X_reg(0x8, eq, 17, 18, 0x7); -+TEST_CCMP_X_reg(0x1, lt, 17, 18, 0x6); -+TEST_CCMP_X_reg(0x2, lt, 17, 18, 0x5); -+TEST_CCMP_X_reg(0x4, lt, 17, 18, 0x3); -+TEST_CCMP_X_reg(0x8, lt, 17, 18, 0x7); -+TEST_CCMP_X_reg(0x1, gt, 17, 18, 0x6); -+TEST_CCMP_X_reg(0x2, gt, 17, 18, 0x5); -+TEST_CCMP_X_reg(0x4, gt, 17, 18, 0x3); -+TEST_CCMP_X_reg(0x8, gt, 17, 18, 0x7); -+TEST_CCMP_X_reg(0x1, ne, 17, 18, 0x6); -+TEST_CCMP_X_reg(0x2, ne, 17, 18, 0x5); -+TEST_CCMP_X_reg(0x4, ne, 17, 18, 0x3); -+TEST_CCMP_X_reg(0x8, ne, 17, 18, 0x7); -+ -+ -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x0); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x1); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x2); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x4); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x5); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x6); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x7); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x8); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x9); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0xA); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0xB); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0xC); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0xD); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0xE); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x0); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x1); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x2); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x4); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x5); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x6); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x7); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x8); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x9); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0xA); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0xB); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0xC); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0xD); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0xE); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_X_reg(0x1, eq, -17, 17, 0x6); -+TEST_CCMN_X_reg(0x2, eq, -17, 17, 0x5); -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_X_reg(0x8, eq, -17, 17, 0x7); -+TEST_CCMN_X_reg(0x1, lt, -17, 17, 0x6); -+TEST_CCMN_X_reg(0x2, lt, -17, 17, 0x5); -+TEST_CCMN_X_reg(0x4, lt, -17, 17, 0x3); -+TEST_CCMN_X_reg(0x8, lt, -17, 17, 0x7); -+TEST_CCMN_X_reg(0x1, gt, -17, 17, 0x6); -+TEST_CCMN_X_reg(0x2, gt, -17, 17, 0x5); -+TEST_CCMN_X_reg(0x4, gt, -17, 17, 0x3); -+TEST_CCMN_X_reg(0x8, gt, -17, 17, 0x7); -+TEST_CCMN_X_reg(0x1, ne, -17, 17, 0x6); -+TEST_CCMN_X_reg(0x2, ne, -17, 17, 0x5); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_X_reg(0x8, ne, -17, 17, 0x7); -+TEST_CCMN_X_reg(0x1, eq, -17, 18, 0x6); -+TEST_CCMN_X_reg(0x2, eq, -17, 18, 0x5); -+TEST_CCMN_X_reg(0x4, eq, -17, 18, 0x3); -+TEST_CCMN_X_reg(0x8, eq, -17, 18, 0x7); -+TEST_CCMN_X_reg(0x1, lt, -17, 18, 0x6); -+TEST_CCMN_X_reg(0x2, lt, -17, 18, 0x5); -+TEST_CCMN_X_reg(0x4, lt, -17, 18, 0x3); -+TEST_CCMN_X_reg(0x8, lt, -17, 18, 0x7); -+TEST_CCMN_X_reg(0x1, gt, -17, 18, 0x6); -+TEST_CCMN_X_reg(0x2, gt, -17, 18, 0x5); -+TEST_CCMN_X_reg(0x4, gt, -17, 18, 0x3); -+TEST_CCMN_X_reg(0x8, gt, -17, 18, 0x7); -+TEST_CCMN_X_reg(0x1, ne, -17, 18, 0x6); -+TEST_CCMN_X_reg(0x2, ne, -17, 18, 0x5); -+TEST_CCMN_X_reg(0x4, ne, -17, 18, 0x3); -+TEST_CCMN_X_reg(0x8, ne, -17, 18, 0x7); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("CCMP/CCMN(reg)(32)\n"); -+ -+#define PRE "msr nzcv,x24; " // nzcv = x24 -+#define POST "; mrs x23,nzcv" // x23 = nzcv (overall result) -+ -+#define TEST_CCMP_W_reg(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST4(PRE "ccmp w25,w26,#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, argR_value, x23,x24,x25,x26 ,0) -+ -+#define TEST_CCMN_W_reg(initial_nzcv, cond, argL_value, argR_value, iffalse_nzcv) \ -+ TESTINST4(PRE "ccmn w25,w26,#" #iffalse_nzcv "," #cond POST, \ -+ (initial_nzcv<<28), argL_value, argR_value, x23,x24,x25,x26 ,0) -+ -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0xF); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0xF); -+TEST_CCMP_W_reg(0x4, eq, 17+(17ULL<<32), 17, 0xF); -+TEST_CCMP_W_reg(0x4, ne, 17+(17ULL<<32), 17, 0xF); -+ -+TEST_CCMP_X_reg(0x4, eq, 17, 17, 0xF); -+TEST_CCMP_X_reg(0x4, ne, 17, 17, 0xF); -+TEST_CCMP_X_reg(0x4, eq, 17+(17ULL<<32), 17, 0xF); -+TEST_CCMP_X_reg(0x4, ne, 17+(17ULL<<32), 17, 0xF); -+ -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x0); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x1); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x2); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x4); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x5); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x6); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x7); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x8); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x9); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0xA); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0xB); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0xC); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0xD); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0xE); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x0); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x1); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x2); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x4); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x5); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x6); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x7); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x8); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x9); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0xA); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0xB); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0xC); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0xD); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0xE); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0xF); -+printf("\n"); -+TEST_CCMP_W_reg(0x1, eq, 17, 17, 0x6); -+TEST_CCMP_W_reg(0x2, eq, 17, 17, 0x5); -+TEST_CCMP_W_reg(0x4, eq, 17, 17, 0x3); -+TEST_CCMP_W_reg(0x8, eq, 17, 17, 0x7); -+TEST_CCMP_W_reg(0x1, lt, 17, 17, 0x6); -+TEST_CCMP_W_reg(0x2, lt, 17, 17, 0x5); -+TEST_CCMP_W_reg(0x4, lt, 17, 17, 0x3); -+TEST_CCMP_W_reg(0x8, lt, 17, 17, 0x7); -+TEST_CCMP_W_reg(0x1, gt, 17, 17, 0x6); -+TEST_CCMP_W_reg(0x2, gt, 17, 17, 0x5); -+TEST_CCMP_W_reg(0x4, gt, 17, 17, 0x3); -+TEST_CCMP_W_reg(0x8, gt, 17, 17, 0x7); -+TEST_CCMP_W_reg(0x1, ne, 17, 17, 0x6); -+TEST_CCMP_W_reg(0x2, ne, 17, 17, 0x5); -+TEST_CCMP_W_reg(0x4, ne, 17, 17, 0x3); -+TEST_CCMP_W_reg(0x8, ne, 17, 17, 0x7); -+TEST_CCMP_W_reg(0x1, eq, 17, 18, 0x6); -+TEST_CCMP_W_reg(0x2, eq, 17, 18, 0x5); -+TEST_CCMP_W_reg(0x4, eq, 17, 18, 0x3); -+TEST_CCMP_W_reg(0x8, eq, 17, 18, 0x7); -+TEST_CCMP_W_reg(0x1, lt, 17, 18, 0x6); -+TEST_CCMP_W_reg(0x2, lt, 17, 18, 0x5); -+TEST_CCMP_W_reg(0x4, lt, 17, 18, 0x3); -+TEST_CCMP_W_reg(0x8, lt, 17, 18, 0x7); -+TEST_CCMP_W_reg(0x1, gt, 17, 18, 0x6); -+TEST_CCMP_W_reg(0x2, gt, 17, 18, 0x5); -+TEST_CCMP_W_reg(0x4, gt, 17, 18, 0x3); -+TEST_CCMP_W_reg(0x8, gt, 17, 18, 0x7); -+TEST_CCMP_W_reg(0x1, ne, 17, 18, 0x6); -+TEST_CCMP_W_reg(0x2, ne, 17, 18, 0x5); -+TEST_CCMP_W_reg(0x4, ne, 17, 18, 0x3); -+TEST_CCMP_W_reg(0x8, ne, 17, 18, 0x7); -+ -+ -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0xF); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0xF); -+TEST_CCMN_W_reg(0x4, eq, -(17+(17ULL<<32)), 17, 0xF); -+TEST_CCMN_W_reg(0x4, ne, -(17+(17ULL<<32)), 17, 0xF); -+ -+TEST_CCMN_X_reg(0x4, eq, -17, 17, 0xF); -+TEST_CCMN_X_reg(0x4, ne, -17, 17, 0xF); -+TEST_CCMN_X_reg(0x4, eq, -(17+(17ULL<<32)), 17, 0xF); -+TEST_CCMN_X_reg(0x4, ne, -(17+(17ULL<<32)), 17, 0xF); -+ -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x0); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x1); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x2); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x4); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x5); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x6); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x7); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x8); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x9); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0xA); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0xB); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0xC); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0xD); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0xE); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x0); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x1); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x2); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x4); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x5); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x6); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x7); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x8); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x9); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0xA); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0xB); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0xC); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0xD); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0xE); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0xF); -+printf("\n"); -+TEST_CCMN_W_reg(0x1, eq, -17, 17, 0x6); -+TEST_CCMN_W_reg(0x2, eq, -17, 17, 0x5); -+TEST_CCMN_W_reg(0x4, eq, -17, 17, 0x3); -+TEST_CCMN_W_reg(0x8, eq, -17, 17, 0x7); -+TEST_CCMN_W_reg(0x1, lt, -17, 17, 0x6); -+TEST_CCMN_W_reg(0x2, lt, -17, 17, 0x5); -+TEST_CCMN_W_reg(0x4, lt, -17, 17, 0x3); -+TEST_CCMN_W_reg(0x8, lt, -17, 17, 0x7); -+TEST_CCMN_W_reg(0x1, gt, -17, 17, 0x6); -+TEST_CCMN_W_reg(0x2, gt, -17, 17, 0x5); -+TEST_CCMN_W_reg(0x4, gt, -17, 17, 0x3); -+TEST_CCMN_W_reg(0x8, gt, -17, 17, 0x7); -+TEST_CCMN_W_reg(0x1, ne, -17, 17, 0x6); -+TEST_CCMN_W_reg(0x2, ne, -17, 17, 0x5); -+TEST_CCMN_W_reg(0x4, ne, -17, 17, 0x3); -+TEST_CCMN_W_reg(0x8, ne, -17, 17, 0x7); -+TEST_CCMN_W_reg(0x1, eq, -17, 18, 0x6); -+TEST_CCMN_W_reg(0x2, eq, -17, 18, 0x5); -+TEST_CCMN_W_reg(0x4, eq, -17, 18, 0x3); -+TEST_CCMN_W_reg(0x8, eq, -17, 18, 0x7); -+TEST_CCMN_W_reg(0x1, lt, -17, 18, 0x6); -+TEST_CCMN_W_reg(0x2, lt, -17, 18, 0x5); -+TEST_CCMN_W_reg(0x4, lt, -17, 18, 0x3); -+TEST_CCMN_W_reg(0x8, lt, -17, 18, 0x7); -+TEST_CCMN_W_reg(0x1, gt, -17, 18, 0x6); -+TEST_CCMN_W_reg(0x2, gt, -17, 18, 0x5); -+TEST_CCMN_W_reg(0x4, gt, -17, 18, 0x3); -+TEST_CCMN_W_reg(0x8, gt, -17, 18, 0x7); -+TEST_CCMN_W_reg(0x1, ne, -17, 18, 0x6); -+TEST_CCMN_W_reg(0x2, ne, -17, 18, 0x5); -+TEST_CCMN_W_reg(0x4, ne, -17, 18, 0x3); -+TEST_CCMN_W_reg(0x8, ne, -17, 18, 0x7); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("REV\n"); -+ -+TESTINST2("rev x11,x23", 0xfd79baaee550b488, x11,x23,0); -+TESTINST2("rev x11,x23", 0xe861540945421773, x11,x23,0); -+TESTINST2("rev x11,x23", 0x9a1140d0fd1dbf6c, x11,x23,0); -+ -+TESTINST2("rev w11,w23", 0xfd79baaee550b488, x11,x23,0); -+TESTINST2("rev w11,w23", 0xe861540945421773, x11,x23,0); -+TESTINST2("rev w11,w23", 0x9a1140d0fd1dbf6c, x11,x23,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("RBIT\n"); -+ -+TESTINST2("rbit x11,x23", 0xfd79baaee550b488, x11,x23,0); -+TESTINST2("rbit x11,x23", 0xe861540945421773, x11,x23,0); -+TESTINST2("rbit x11,x23", 0x9a1140d0fd1dbf6c, x11,x23,0); -+ -+TESTINST2("rbit w11,w23", 0xfd79baaee550b488, x11,x23,0); -+TESTINST2("rbit w11,w23", 0xe861540945421773, x11,x23,0); -+TESTINST2("rbit w11,w23", 0x9a1140d0fd1dbf6c, x11,x23,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("REV16\n"); -+ -+TESTINST2("rev16 x11,x23", 0xfd79baaee550b488, x11,x23,0); -+TESTINST2("rev16 x11,x23", 0xe861540945421773, x11,x23,0); -+TESTINST2("rev16 x11,x23", 0x9a1140d0fd1dbf6c, x11,x23,0); -+ -+TESTINST2("rev16 w11,w23", 0xfd79baaee550b488, x11,x23,0); -+TESTINST2("rev16 w11,w23", 0xe861540945421773, x11,x23,0); -+TESTINST2("rev16 w11,w23", 0x9a1140d0fd1dbf6c, x11,x23,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("REV32\n"); -+ -+TESTINST2("rev32 x11,x23", 0xfd79baaee550b488, x11,x23,0); -+TESTINST2("rev32 x11,x23", 0xe861540945421773, x11,x23,0); -+TESTINST2("rev32 x11,x23", 0x9a1140d0fd1dbf6c, x11,x23,0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("CLZ\n"); -+ -+TESTINST2("clz x17, x22", 0xFFFFFFFFFFFFFFFFULL, x17, x22, 0); -+TESTINST2("clz x17, x22", 0ULL, x17, x22, 0); -+TESTINST2("clz x17, x22", 0x0070FFFF01FFFFFFULL, x17, x22, 0); -+ -+TESTINST2("clz w17, w22", 0xFFFFFFFFFFFFFFFFULL, x17, x22, 0); -+TESTINST2("clz w17, w22", 0ULL, x17, x22, 0); -+TESTINST2("clz w17, w22", 0x0070FFFF01FFFFFFULL, x17, x22, 0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("LSLV/LSRV/ASRV\n"); -+ -+TESTINST3("lslv x21,x20,x19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("lslv x21,x20,x19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("lslv x21,x20,x19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("lslv x21,x20,x19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("lslv x21,x20,x19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("lslv x21,x20,x19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("lslv x21,x20,x19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+ -+TESTINST3("lsrv x21,x20,x19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("lsrv x21,x20,x19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("lsrv x21,x20,x19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("lsrv x21,x20,x19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("lsrv x21,x20,x19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("lsrv x21,x20,x19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("lsrv x21,x20,x19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+ -+TESTINST3("asrv x21,x20,x19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("asrv x21,x20,x19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("asrv x21,x20,x19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("asrv x21,x20,x19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("asrv x21,x20,x19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("asrv x21,x20,x19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("asrv x21,x20,x19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+ -+ -+TESTINST3("lslv w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("lslv w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("lslv w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("lslv w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("lslv w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("lslv w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("lslv w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+ -+TESTINST3("lsrv w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("lsrv w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("lsrv w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("lsrv w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("lsrv w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("lsrv w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("lsrv w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+ -+TESTINST3("asrv w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("asrv w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("asrv w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("asrv w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("asrv w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("asrv w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("asrv w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("SDIV/UDIV\n"); -+ -+TESTINST3("sdiv x21,x20,x19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 101, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 100, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 99, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 98, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -101LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -100LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -99LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -98LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 101, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 100, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 99, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 98, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -101LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -100LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -99LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -98LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0LL, 0LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", -1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("sdiv x21,x20,x19", 0x8000000000000000ULL, 0xFFFFFFFFFFFFFFFFULL, x21,x20,x19, 0); -+ -+TESTINST3("sdiv w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 101, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 100, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 99, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 98, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -101LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -100LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -99LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -98LL, 20, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 101, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 100, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 99, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 98, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -101LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -100LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -99LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -98LL, -20LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0LL, 0LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", -1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("sdiv w21,w20,w19", 0x80000000ULL, 0xFFFFFFFFULL, x21,x20,x19, 0); -+ -+TESTINST3("udiv x21,x20,x19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 101, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 100, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 99, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 98, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -101LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -100LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -99LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -98LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 101, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 100, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 99, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 98, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -101LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -100LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -99LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -98LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0LL, 0LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", -1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("udiv x21,x20,x19", 0x8000000000000000ULL, 0xFFFFFFFFFFFFFFFFULL, x21,x20,x19, 0); -+ -+TESTINST3("udiv w21,w20,w19", 0x4b154113f7d32514, 0xcce230caafbf9cc9, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0x33d5d595721d4f13, 0xf4509311f443a7ce, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0x4a3c6de6954cbc17, 0x111b21e39fbd7254, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0xfbb5c64ed1b044c6, 0x33ca4c4fb3960326, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0x2b7c5939d7c0f528, 0xb73870a5a6630162, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0x02fe41918ac5cdba, 0x48e0815289728f05, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0xb60a8f381f187bae, 0x008c208cc413ff72, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 101, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 100, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 99, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 98, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -101LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -100LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -99LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -98LL, 20, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 101, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 100, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 99, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 98, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -101LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -100LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -99LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -98LL, -20LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0LL, 0LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", -1LL, 0LL, x21,x20,x19, 0); -+TESTINST3("udiv w21,w20,w19", 0x80000000ULL, 0xFFFFFFFFULL, x21,x20,x19, 0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("UMADDL/SMADDL/UMSUBL/SMSUBL\n"); -+ -+TESTINST4("umaddl x14,w15,w16,x17", -+ 0x8318f285284c6473, 0xf2deaa8a065b5b97, 0xdb432311d1e3a1d0, x14,x15,x16,x17, 0); -+TESTINST4("umaddl x14,w15,w16,x17", -+ 0xa6325ae016fbd710, 0xf0211fade82d1008, 0x70668d1659e224e8, x14,x15,x16,x17, 0); -+TESTINST4("umaddl x14,w15,w16,x17", -+ 0x1f1dd8017f191501, 0xf69aef71040bfeab, 0x559bc9e2fca45761, x14,x15,x16,x17, 0); -+TESTINST4("umaddl x14,w15,w16,x17", -+ 0x389ce2f3140cec0c, 0x7a3ab866f2dcd171, 0xa5d72d6243684403, x14,x15,x16,x17, 0); -+ -+TESTINST4("smaddl x14,w15,w16,x17", -+ 0x8318f285284c6473, 0xf2deaa8a065b5b97, 0xdb432311d1e3a1d0, x14,x15,x16,x17, 0); -+TESTINST4("smaddl x14,w15,w16,x17", -+ 0xa6325ae016fbd710, 0xf0211fade82d1008, 0x70668d1659e224e8, x14,x15,x16,x17, 0); -+TESTINST4("smaddl x14,w15,w16,x17", -+ 0x1f1dd8017f191501, 0xf69aef71040bfeab, 0x559bc9e2fca45761, x14,x15,x16,x17, 0); -+TESTINST4("smaddl x14,w15,w16,x17", -+ 0x389ce2f3140cec0c, 0x7a3ab866f2dcd171, 0xa5d72d6243684403, x14,x15,x16,x17, 0); -+ -+TESTINST4("umsubl x14,w15,w16,x17", -+ 0x8318f285284c6473, 0xf2deaa8a065b5b97, 0xdb432311d1e3a1d0, x14,x15,x16,x17, 0); -+TESTINST4("umsubl x14,w15,w16,x17", -+ 0xa6325ae016fbd710, 0xf0211fade82d1008, 0x70668d1659e224e8, x14,x15,x16,x17, 0); -+TESTINST4("umsubl x14,w15,w16,x17", -+ 0x1f1dd8017f191501, 0xf69aef71040bfeab, 0x559bc9e2fca45761, x14,x15,x16,x17, 0); -+TESTINST4("umsubl x14,w15,w16,x17", -+ 0x389ce2f3140cec0c, 0x7a3ab866f2dcd171, 0xa5d72d6243684403, x14,x15,x16,x17, 0); -+ -+TESTINST4("smsubl x14,w15,w16,x17", -+ 0x8318f285284c6473, 0xf2deaa8a065b5b97, 0xdb432311d1e3a1d0, x14,x15,x16,x17, 0); -+TESTINST4("smsubl x14,w15,w16,x17", -+ 0xa6325ae016fbd710, 0xf0211fade82d1008, 0x70668d1659e224e8, x14,x15,x16,x17, 0); -+TESTINST4("smsubl x14,w15,w16,x17", -+ 0x1f1dd8017f191501, 0xf69aef71040bfeab, 0x559bc9e2fca45761, x14,x15,x16,x17, 0); -+TESTINST4("smsubl x14,w15,w16,x17", -+ 0x389ce2f3140cec0c, 0x7a3ab866f2dcd171, 0xa5d72d6243684403, x14,x15,x16,x17, 0); -+ -+} /* end of test_arith() */ -+ -+ -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+ -+static __attribute((noinline)) void test_memory ( void ) -+{ -+printf("Integer loads\n"); -+ -+unsigned char area[512]; -+ -+#define RESET \ -+ do { int i; for (i = 0; i < sizeof(area); i++) \ -+ area[i] = i | 0x80; \ -+ } while (0) -+ -+#define AREA_MID (((ULong)(&area[(sizeof(area)/2)-1])) & (~(ULong)0xF)) -+ -+RESET; -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR,STR (immediate, uimm12) (STR cases are MISSING)"); -+TESTINST2_hide2("ldr x21, [x22, #24]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldr w21, [x22, #20]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrh w21, [x22, #44]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrb w21, [x22, #56]", AREA_MID, x21,x22,0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)\n"); -+TESTINST2_hide2("ldr x21, [x22], #-24", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldr x21, [x22, #-40]!", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldr x21, [x22, #-48]", AREA_MID, x21,x22,0); -+printf("LDUR,STUR (immediate, simm9): STR cases are MISSING"); -+ -+//////////////////////////////////////////////////////////////// -+// TESTINST2_hide2 allows use of x28 as scratch -+printf("LDP,STP (immediate, simm7) (STR cases and wb check is MISSING)\n"); -+ -+TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0); -+ -+TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0); -+ -+//////////////////////////////////////////////////////////////// -+// This is a bit tricky. We load the value from just before and -+// just after the actual instruction. Because TESTINSN2_hide2 -+// generates two fixed insns either side of the test insn, these -+// should be constant and hence "safe" to check. -+ -+printf("LDR (literal, int reg)\n"); -+TESTINST2_hide2("xyzzy00: ldr x21, xyzzy00 - 8", AREA_MID, x21,x22,0); -+TESTINST2_hide2("xyzzy01: ldr x21, xyzzy01 + 0", AREA_MID, x21,x22,0); -+TESTINST2_hide2("xyzzy02: ldr x21, xyzzy02 + 8", AREA_MID, x21,x22,0); -+ -+TESTINST2_hide2("xyzzy03: ldr x21, xyzzy03 - 4", AREA_MID, x21,x22,0); -+TESTINST2_hide2("xyzzy04: ldr x21, xyzzy04 + 0", AREA_MID, x21,x22,0); -+TESTINST2_hide2("xyzzy05: ldr x21, xyzzy05 + 4", AREA_MID, x21,x22,0); -+ -+//////////////////////////////////////////////////////////////// -+printf("{LD,ST}R (integer register) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (uimm12)\n"); -+TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh x21, [x22, #20]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh w21, [x22, #44]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb x21, [x22, #88]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb w21, [x22, #56]", AREA_MID, x21,x22,0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n"); -+TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh x21, [x22, #-20]!", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh w21, [x22, #-44]!", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb x21, [x22, #-88]!", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb w21, [x22, #-56]!", AREA_MID, x21,x22,0); -+ -+TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh x21, [x22], #-20", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh w21, [x22], #-44", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb x21, [x22], #-88", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb w21, [x22], #-56", AREA_MID, x21,x22,0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (simm9, noUpd)\n"); -+TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh x21, [x22, #-20]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsh w21, [x22, #-44]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb x21, [x22, #-88]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldrsb w21, [x22, #-56]", AREA_MID, x21,x22,0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("{LD,ST}R (vector register) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (integer register, SX)\n"); -+ -+TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0); -+ -+TESTINST3_hide2and3("ldrsh x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh x21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0); -+ -+TESTINST3_hide2and3("ldrsh w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh w21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0); -+ -+TESTINST3_hide2and3("ldrsb x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb x21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0); -+ -+TESTINST3_hide2and3("ldrsb w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb w21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0); -+TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR (literal, SIMD&FP) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LD1/ST1 (single structure, no offset) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LD1/ST1 (single structure, post index) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LD{,A}X{R,RH,RB} (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("ST{,L}X{R,RH,RB} (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDA{R,RH,RB}\n"); -+TESTINST2_hide2("ldar x21, [x22]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldar w21, [x22]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldarh w21, [x22]", AREA_MID, x21,x22,0); -+TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0); -+ -+//////////////////////////////////////////////////////////////// -+printf("STL{R,RH,RB} (entirely MISSING)\n"); -+ -+} /* end of test_memory() */ -+ -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+ -+static void show_block_xor ( UChar* block1, UChar* block2, Int n ) -+{ -+ Int i; -+ printf(" "); -+ for (i = 0; i < n; i++) { -+ if (i > 0 && 0 == (i & 15)) printf("\n "); -+ if (0 == (i & 15)) printf("[%3d] ", i); -+ UInt diff = 0xFF & (UInt)(block1[i] - block2[i]); -+ if (diff == 0) -+ printf(".. "); -+ else -+ printf("%02x ", diff); -+ } -+ printf("\n"); -+} -+ -+ -+// In: rand: -+// memory area, xferred vec regs, xferred int regs, -+// caller spec: -+// addr reg1, addr reg2 -+// -+// Out: memory area, xferred vec regs, xferred int regs, addr reg1, addr reg2 -+// -+// INSN may mention the following regs as containing load/store data: -+// x13 x23 v17 v18 -+// and -+// x5 as containing the base address -+// x6 as containing an offset, if required -+// A memory area is filled with random data, and x13, x23, v17 and v18 -+// are loaded with random data too. INSN is then executed, with -+// x5 set to the middle of the memory area + AREG1OFF, and x6 set to AREG2VAL. -+// -+// What is printed out: the XOR of the old and new versions of the -+// following: -+// the memory area -+// x13 x23 v17 v18 -+// and the new-old values of these -+// x5 x6 -+// If the insn modifies its base register then the x5 version will -+// be different. -+ -+#define MEM_TEST(INSN, AREG1OFF, AREG2VAL) { \ -+ int i; \ -+ const int N = 256; \ -+ UChar* area = memalign16(N); \ -+ UChar area2[N]; \ -+ for (i = 0; i < N; i++) area[i] = area2[i] = randUChar(); \ -+ ULong block[8]; /* x13 x23 v17.d[0] v17.d[1] v18.d[0] v18.d[1] x5 x6 */ \ -+ for (i = 0; i < 6; i++) block[i] = randULong(); \ -+ block[6] = (ULong)(&area[128]) + (Long)(Int)AREG1OFF; \ -+ block[7] = (Long)AREG2VAL; \ -+ ULong block2[8]; \ -+ for (i = 0; i < 8; i++) block2[i] = block[i]; \ -+ __asm__ __volatile__( \ -+ "ldr x13, [%0, #0] ; " \ -+ "ldr x23, [%0, #8] ; " \ -+ "ldr q17, [%0, #16] ; " \ -+ "ldr q18, [%0, #32] ; " \ -+ "ldr x5, [%0, #48] ; " \ -+ "ldr x6, [%0, #56] ; " \ -+ INSN " ; " \ -+ "str x13, [%0, #0] ; " \ -+ "str x23, [%0, #8] ; " \ -+ "str q17, [%0, #16] ; " \ -+ "str q18, [%0, #32] ; " \ -+ "str x5, [%0, #48] ; " \ -+ "str x6, [%0, #56] ; " \ -+ : : "r"(&block[0]) : "x5", "x6", "x13","x23","v17","v18","memory","cc" \ -+ ); \ -+ printf("%s with x5 = middle_of_block+%lld, x6=%lld\n", \ -+ INSN, (Long)AREG1OFF, (Long)AREG2VAL); \ -+ show_block_xor(&area2[0], area, 256); \ -+ printf(" %016llx x13 (xfer intreg #1)\n", block[0] ^ block2[0]); \ -+ printf(" %016llx x23 (xfer intreg #2)\n", block[1] ^ block2[1]); \ -+ printf(" %016llx v17.d[0] (xfer vecreg #1)\n", block[2] ^ block2[2]); \ -+ printf(" %016llx v17.d[1] (xfer vecreg #1)\n", block[3] ^ block2[3]); \ -+ printf(" %016llx v18.d[0] (xfer vecreg #2)\n", block[4] ^ block2[4]); \ -+ printf(" %016llx v18.d[1] (xfer vecreg #2)\n", block[5] ^ block2[5]); \ -+ printf(" %16lld x5 (base reg)\n", block[6] - block2[6]); \ -+ printf(" %16lld x6 (index reg)\n", block[7] - block2[7]); \ -+ printf("\n"); \ -+ free(area); \ -+ } -+ -+static __attribute__((noinline)) void test_memory2 ( void ) -+{ -+//////////////////////////////////////////////////////////////// -+printf("LDR,STR (immediate, uimm12)"); -+MEM_TEST("ldr x13, [x5, #24]", -1, 0); -+MEM_TEST("ldr w13, [x5, #20]", 1, 0); -+MEM_TEST("ldrh w13, [x5, #44]", 2, 0); -+MEM_TEST("ldrb w13, [x5, #56]", 3, 0); -+MEM_TEST("str x13, [x5, #24]", -3, 0); -+MEM_TEST("str w13, [x5, #20]", 5, 0); -+MEM_TEST("strh w13, [x5, #44]", 6, 0); -+MEM_TEST("strb w13, [x5, #56]", 7, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDUR,STUR (immediate, simm9)\n"); -+MEM_TEST("ldr x13, [x5], #-24", 0, 0); -+MEM_TEST("ldr x13, [x5, #-40]!", 0, 0); -+MEM_TEST("ldr x13, [x5, #-48]", 0, 0); -+MEM_TEST("str x13, [x5], #-24", 0, 0); -+MEM_TEST("str x13, [x5, #-40]!", 0, 0); -+MEM_TEST("str x13, [x5, #-48]", 0, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDP,STP (immediate, simm7)\n"); -+MEM_TEST("ldp x13, x23, [x5], #-24", 0, 0); -+MEM_TEST("ldp x13, x23, [x5, #-40]!", 0, 0); -+MEM_TEST("ldp x13, x23, [x5, #-40]", 0, 0); -+MEM_TEST("stp x13, x23, [x5], #-24", 0, 0); -+MEM_TEST("stp x13, x23, [x5, #-40]!", 0, 0); -+MEM_TEST("stp x13, x23, [x5, #-40]", 0, 0); -+ -+MEM_TEST("ldp w13, w23, [x5], #-24", 0, 0); -+MEM_TEST("ldp w13, w23, [x5, #-40]!", 0, 0); -+MEM_TEST("ldp w13, w23, [x5, #-40]", 0, 0); -+MEM_TEST("stp w13, w23, [x5], #-24", 0, 0); -+MEM_TEST("stp w13, w23, [x5, #-40]!", 0, 0); -+MEM_TEST("stp w13, w23, [x5, #-40]", 0, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR (literal, int reg) (DONE ABOVE)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("{LD,ST}R (integer register) (entirely MISSING)\n"); -+MEM_TEST("str x13, [x5, x6]", 12, -4); -+MEM_TEST("str x13, [x5, x6, lsl #3]", 12, -4); -+MEM_TEST("str x13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("str x13, [x5, w6, uxtw #3]", 12, 4); -+MEM_TEST("str x13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("str x13, [x5, w6, sxtw #3]", 12, -4); -+MEM_TEST("ldr x13, [x5, x6]", 12, -4); -+MEM_TEST("ldr x13, [x5, x6, lsl #3]", 12, -4); -+MEM_TEST("ldr x13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldr x13, [x5, w6, uxtw #3]", 12, 4); -+MEM_TEST("ldr x13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldr x13, [x5, w6, sxtw #3]", 12, -4); -+ -+MEM_TEST("str w13, [x5, x6]", 12, -4); -+MEM_TEST("str w13, [x5, x6, lsl #2]", 12, -4); -+MEM_TEST("str w13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("str w13, [x5, w6, uxtw #2]", 12, 4); -+MEM_TEST("str w13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("str w13, [x5, w6, sxtw #2]", 12, -4); -+MEM_TEST("ldr w13, [x5, x6]", 12, -4); -+MEM_TEST("ldr w13, [x5, x6, lsl #2]", 12, -4); -+MEM_TEST("ldr w13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldr w13, [x5, w6, uxtw #2]", 12, 4); -+MEM_TEST("ldr w13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldr w13, [x5, w6, sxtw #2]", 12, -4); -+ -+MEM_TEST("strh w13, [x5, x6]", 12, -4); -+MEM_TEST("strh w13, [x5, x6, lsl #1]", 12, -4); -+MEM_TEST("strh w13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("strh w13, [x5, w6, uxtw #1]", 12, 4); -+MEM_TEST("strh w13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("strh w13, [x5, w6, sxtw #1]", 12, -4); -+MEM_TEST("ldrh w13, [x5, x6]", 12, -4); -+MEM_TEST("ldrh w13, [x5, x6, lsl #1]", 12, -4); -+MEM_TEST("ldrh w13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldrh w13, [x5, w6, uxtw #1]", 12, 4); -+MEM_TEST("ldrh w13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldrh w13, [x5, w6, sxtw #1]", 12, -4); -+ -+MEM_TEST("strb w13, [x5, x6]", 12, -4); -+MEM_TEST("strb w13, [x5, x6, lsl #0]", 12, -4); -+MEM_TEST("strb w13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("strb w13, [x5, w6, uxtw #0]", 12, 4); -+MEM_TEST("strb w13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("strb w13, [x5, w6, sxtw #0]", 12, -4); -+MEM_TEST("ldrb w13, [x5, x6]", 12, -4); -+MEM_TEST("ldrb w13, [x5, x6, lsl #0]", 12, -4); -+MEM_TEST("ldrb w13, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldrb w13, [x5, w6, uxtw #0]", 12, 4); -+MEM_TEST("ldrb w13, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldrb w13, [x5, w6, sxtw #0]", 12, -4); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (uimm12)\n"); -+MEM_TEST("ldrsw x13, [x5, #24]", -16, 4); -+MEM_TEST("ldrsh x13, [x5, #20]", -16, 4); -+MEM_TEST("ldrsh w13, [x5, #44]", -16, 4); -+MEM_TEST("ldrsb x13, [x5, #72]", -16, 4); -+MEM_TEST("ldrsb w13, [x5, #56]", -16, 4); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n"); -+MEM_TEST("ldrsw x13, [x5, #-24]!", -16, 4); -+MEM_TEST("ldrsh x13, [x5, #-20]!", -16, 4); -+MEM_TEST("ldrsh w13, [x5, #-44]!", -16, 4); -+MEM_TEST("ldrsb x13, [x5, #-72]!", -16, 4); -+MEM_TEST("ldrsb w13, [x5, #-56]!", -16, 4); -+ -+MEM_TEST("ldrsw x13, [x5], #-24", -16, 4); -+MEM_TEST("ldrsh x13, [x5], #-20", -16, 4); -+MEM_TEST("ldrsh w13, [x5], #-44", -16, 4); -+MEM_TEST("ldrsb x13, [x5], #-72", -16, 4); -+MEM_TEST("ldrsb w13, [x5], #-56", -16, 4); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (simm9, noUpd)\n"); -+MEM_TEST("ldrsw x13, [x5, #-24]", -16, 4); -+MEM_TEST("ldrsh x13, [x5, #-20]", -16, 4); -+MEM_TEST("ldrsh w13, [x5, #-44]", -16, 4); -+MEM_TEST("ldrsb x13, [x5, #-72]", -16, 4); -+MEM_TEST("ldrsb w13, [x5, #-56]", -16, 4); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDP,STP (immediate, simm7) (FP&VEC)\n"); -+ -+MEM_TEST("stp q17, q18, [x5, 32]", -16, 4); -+MEM_TEST("stp q17, q18, [x5, 32]!", -16, 4); -+MEM_TEST("stp q17, q18, [x5], 32", -16, 4); -+ -+MEM_TEST("stp d17, d18, [x5, 32]", -16, 4); -+MEM_TEST("stp d17, d18, [x5, 32]!", -16, 4); -+MEM_TEST("stp d17, d18, [x5], 32", -16, 4); -+ -+//MEM_TEST("stp s17, s18, [x5, 32]", -16, 4); -+//MEM_TEST("stp s17, s18, [x5, 32]!", -16, 4); -+//MEM_TEST("stp s17, s18, [x5], 32", -16, 4); -+ -+MEM_TEST("ldp q17, q18, [x5, 32]", -16, 4); -+MEM_TEST("ldp q17, q18, [x5, 32]!", -16, 4); -+MEM_TEST("ldp q17, q18, [x5], 32", -16, 4); -+ -+MEM_TEST("ldp d17, d18, [x5, 32]", -16, 4); -+MEM_TEST("ldp d17, d18, [x5, 32]!", -16, 4); -+MEM_TEST("ldp d17, d18, [x5], 32", -16, 4); -+ -+//MEM_TEST("ldp s17, s18, [x5, 32]", -16, 4); -+//MEM_TEST("ldp s17, s18, [x5, 32]!", -16, 4); -+//MEM_TEST("ldp s17, s18, [x5], 32", -16, 4); -+ -+//////////////////////////////////////////////////////////////// -+printf("{LD,ST}R (vector register)\n"); -+ -+#if 0 -+MEM_TEST("str q17, [x5, x6]", 12, -4); -+MEM_TEST("str q17, [x5, x6, lsl #4]", 12, -4); -+MEM_TEST("str q17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("str q17, [x5, w6, uxtw #4]", 12, 4); -+MEM_TEST("str q17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("str q17, [x5, w6, sxtw #4]", 12, -4); -+MEM_TEST("ldr q17, [x5, x6]", 12, -4); -+MEM_TEST("ldr q17, [x5, x6, lsl #4]", 12, -4); -+MEM_TEST("ldr q17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldr q17, [x5, w6, uxtw #4]", 12, 4); -+MEM_TEST("ldr q17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldr q17, [x5, w6, sxtw #4]", 12, -4); -+#endif -+ -+MEM_TEST("str d17, [x5, x6]", 12, -4); -+MEM_TEST("str d17, [x5, x6, lsl #3]", 12, -4); -+MEM_TEST("str d17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("str d17, [x5, w6, uxtw #3]", 12, 4); -+MEM_TEST("str d17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("str d17, [x5, w6, sxtw #3]", 12, -4); -+MEM_TEST("ldr d17, [x5, x6]", 12, -4); -+MEM_TEST("ldr d17, [x5, x6, lsl #3]", 12, -4); -+MEM_TEST("ldr d17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldr d17, [x5, w6, uxtw #3]", 12, 4); -+MEM_TEST("ldr d17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldr d17, [x5, w6, sxtw #3]", 12, -4); -+ -+MEM_TEST("str s17, [x5, x6]", 12, -4); -+MEM_TEST("str s17, [x5, x6, lsl #2]", 12, -4); -+MEM_TEST("str s17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("str s17, [x5, w6, uxtw #2]", 12, 4); -+MEM_TEST("str s17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("str s17, [x5, w6, sxtw #2]", 12, -4); -+MEM_TEST("ldr s17, [x5, x6]", 12, -4); -+MEM_TEST("ldr s17, [x5, x6, lsl #2]", 12, -4); -+MEM_TEST("ldr s17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldr s17, [x5, w6, uxtw #2]", 12, 4); -+MEM_TEST("ldr s17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldr s17, [x5, w6, sxtw #2]", 12, -4); -+ -+#if 0 -+MEM_TEST("str h17, [x5, x6]", 12, -4); -+MEM_TEST("str h17, [x5, x6, lsl #1]", 12, -4); -+MEM_TEST("str h17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("str h17, [x5, w6, uxtw #1]", 12, 4); -+MEM_TEST("str h17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("str h17, [x5, w6, sxtw #1]", 12, -4); -+MEM_TEST("ldr h17, [x5, x6]", 12, -4); -+MEM_TEST("ldr h17, [x5, x6, lsl #1]", 12, -4); -+MEM_TEST("ldr h17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldr h17, [x5, w6, uxtw #1]", 12, 4); -+MEM_TEST("ldr h17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldr h17, [x5, w6, sxtw #1]", 12, -4); -+ -+MEM_TEST("str b17, [x5, x6]", 12, -4); -+MEM_TEST("str b17, [x5, x6, lsl #0]", 12, -4); -+MEM_TEST("str b17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("str b17, [x5, w6, uxtw #0]", 12, 4); -+MEM_TEST("str b17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("str b17, [x5, w6, sxtw #0]", 12, -4); -+MEM_TEST("ldr b17, [x5, x6]", 12, -4); -+MEM_TEST("ldr b17, [x5, x6, lsl #0]", 12, -4); -+MEM_TEST("ldr b17, [x5, w6, uxtw]", 12, 4); -+MEM_TEST("ldr b17, [x5, w6, uxtw #0]", 12, 4); -+MEM_TEST("ldr b17, [x5, w6, sxtw]", 12, 4); -+MEM_TEST("ldr b17, [x5, w6, sxtw #0]", 12, -4); -+#endif -+ -+//////////////////////////////////////////////////////////////// -+printf("LDRS{B,H,W} (integer register, SX)\n"); -+ -+MEM_TEST("ldrsw x13, [x5,x6]", 12, -4); -+MEM_TEST("ldrsw x13, [x5,x6, lsl #2]", 12, -4); -+MEM_TEST("ldrsw x13, [x5,w6,uxtw #0]", 12, 4); -+MEM_TEST("ldrsw x13, [x5,w6,uxtw #2]", 12, 4); -+MEM_TEST("ldrsw x13, [x5,w6,sxtw #0]", 12, 4); -+MEM_TEST("ldrsw x13, [x5,w6,sxtw #2]", 12, -4); -+ -+MEM_TEST("ldrsh x13, [x5,x6]", 12, -4); -+MEM_TEST("ldrsh x13, [x5,x6, lsl #1]", 12, -4); -+MEM_TEST("ldrsh x13, [x5,w6,uxtw #0]", 12, 4); -+MEM_TEST("ldrsh x13, [x5,w6,uxtw #1]", 12, 4); -+MEM_TEST("ldrsh x13, [x5,w6,sxtw #0]", 12, 4); -+MEM_TEST("ldrsh x13, [x5,w6,sxtw #1]", 12, -4); -+ -+MEM_TEST("ldrsh w13, [x5,x6]", 12, -4); -+MEM_TEST("ldrsh w13, [x5,x6, lsl #1]", 12, -4); -+MEM_TEST("ldrsh w13, [x5,w6,uxtw #0]", 12, 4); -+MEM_TEST("ldrsh w13, [x5,w6,uxtw #1]", 12, 4); -+MEM_TEST("ldrsh w13, [x5,w6,sxtw #0]", 12, 4); -+MEM_TEST("ldrsh w13, [x5,w6,sxtw #1]", 12, -4); -+ -+MEM_TEST("ldrsb x13, [x5,x6]", 12, -4); -+MEM_TEST("ldrsb x13, [x5,x6, lsl #0]", 12, -4); -+MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4); -+MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4); -+MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, 4); -+MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, -4); -+ -+MEM_TEST("ldrsb w13, [x5,x6]", 12, -4); -+MEM_TEST("ldrsb w13, [x5,x6, lsl #0]", 12, -4); -+MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4); -+MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4); -+MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, 4); -+MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, -4); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR/STR (immediate, SIMD&FP, unsigned offset)\n"); -+MEM_TEST("str q17, [x5, #-32]", 16, 0); -+MEM_TEST("str d17, [x5, #-32]", 16, 0); -+MEM_TEST("str s17, [x5, #-32]", 16, 0); -+//MEM_TEST("str h17, [x5, #-32]", 16, 0); -+//MEM_TEST("str b17, [x5, #-32]", 16, 0); -+MEM_TEST("ldr q17, [x5, #-32]", 16, 0); -+MEM_TEST("ldr d17, [x5, #-32]", 16, 0); -+MEM_TEST("ldr s17, [x5, #-32]", 16, 0); -+//MEM_TEST("ldr h17, [x5, #-32]", 16, 0); -+//MEM_TEST("ldr b17, [x5, #-32]", 16, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR/STR (immediate, SIMD&FP, pre/post index)\n"); -+MEM_TEST("str q17, [x5], #-32", 16, 0); -+MEM_TEST("str d17, [x5], #-32", 16, 0); -+MEM_TEST("str s17, [x5], #-32", 16, 0); -+//MEM_TEST("str h17, [x5], #-32", 16, 0); -+//MEM_TEST("str b17, [x5], #-32", 16, 0); -+MEM_TEST("ldr q17, [x5], #-32", 16, 0); -+MEM_TEST("ldr d17, [x5], #-32", 16, 0); -+MEM_TEST("ldr s17, [x5], #-32", 16, 0); -+//MEM_TEST("ldr h17, [x5], #-32", 16, 0); -+//MEM_TEST("ldr b17, [x5], #-32", 16, 0); -+ -+MEM_TEST("str q17, [x5, #-32]!", 16, 0); -+MEM_TEST("str d17, [x5, #-32]!", 16, 0); -+MEM_TEST("str s17, [x5, #-32]!", 16, 0); -+//MEM_TEST("str h17, [x5, #-32]!", 16, 0); -+//MEM_TEST("str b17, [x5, #-32]!", 16, 0); -+MEM_TEST("ldr q17, [x5, #-32]!", 16, 0); -+MEM_TEST("ldr d17, [x5, #-32]!", 16, 0); -+MEM_TEST("ldr s17, [x5, #-32]!", 16, 0); -+//MEM_TEST("ldr h17, [x5, #-32]!", 16, 0); -+//MEM_TEST("ldr b17, [x5, #-32]!", 16, 0); -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("LDUR/STUR (unscaled offset, SIMD&FP)\n"); -+MEM_TEST("str q17, [x5, #-13]", 16, 0); -+MEM_TEST("str d17, [x5, #-13]", 16, 0); -+MEM_TEST("str s17, [x5, #-13]", 16, 0); -+//MEM_TEST("str h17, [x5, #-13]", 16, 0); -+//MEM_TEST("str b17, [x5, #-13]", 16, 0); -+MEM_TEST("ldr q17, [x5, #-13]", 16, 0); -+MEM_TEST("ldr d17, [x5, #-13]", 16, 0); -+MEM_TEST("ldr s17, [x5, #-13]", 16, 0); -+//MEM_TEST("ldr h17, [x5, #-13]", 16, 0); -+//MEM_TEST("ldr b17, [x5, #-13]", 16, 0); -+ -+//////////////////////////////////////////////////////////////// -+printf("LDR (literal, SIMD&FP) (entirely MISSING)\n"); -+ -+//////////////////////////////////////////////////////////////// -+printf("LD1/ST1 (single structure, no offset)\n"); -+MEM_TEST("st1 {v17.2d}, [x5]", 3, 0) -+MEM_TEST("st1 {v17.4s}, [x5]", 5, 0) -+MEM_TEST("st1 {v17.8h}, [x5]", 7, 0) -+MEM_TEST("st1 {v17.16b}, [x5]", 13, 0) -+MEM_TEST("st1 {v17.1d}, [x5]", 3, 0) -+MEM_TEST("st1 {v17.2s}, [x5]", 5, 0) -+MEM_TEST("st1 {v17.4h}, [x5]", 7, 0) -+MEM_TEST("st1 {v17.8b}, [x5]", 13, 0) -+ -+MEM_TEST("ld1 {v17.2d}, [x5]", 3, 0) -+MEM_TEST("ld1 {v17.4s}, [x5]", 5, 0) -+MEM_TEST("ld1 {v17.8h}, [x5]", 7, 0) -+MEM_TEST("ld1 {v17.16b}, [x5]", 13, 0) -+MEM_TEST("ld1 {v17.1d}, [x5]", 3, 0) -+MEM_TEST("ld1 {v17.2s}, [x5]", 5, 0) -+MEM_TEST("ld1 {v17.4h}, [x5]", 7, 0) -+MEM_TEST("ld1 {v17.8b}, [x5]", 13, 0) -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("LD1/ST1 (single structure, post index)\n"); -+MEM_TEST("st1 {v17.2d}, [x5], #16", 3, 0) -+MEM_TEST("st1 {v17.4s}, [x5], #16", 5, 0) -+MEM_TEST("st1 {v17.8h}, [x5], #16", 7, 0) -+MEM_TEST("st1 {v17.16b}, [x5], #16", 13, 0) -+MEM_TEST("st1 {v17.1d}, [x5], #8", 3, 0) -+MEM_TEST("st1 {v17.2s}, [x5], #8", 5, 0) -+MEM_TEST("st1 {v17.4h}, [x5], #8", 7, 0) -+MEM_TEST("st1 {v17.8b}, [x5], #8", 13, 0) -+ -+MEM_TEST("ld1 {v17.2d}, [x5], #16", 3, 0) -+MEM_TEST("ld1 {v17.4s}, [x5], #16", 5, 0) -+MEM_TEST("ld1 {v17.8h}, [x5], #16", 7, 0) -+MEM_TEST("ld1 {v17.16b}, [x5], #16", 13, 0) -+MEM_TEST("ld1 {v17.1d}, [x5], #8", 3, 0) -+MEM_TEST("ld1 {v17.2s}, [x5], #8", 5, 0) -+MEM_TEST("ld1 {v17.4h}, [x5], #8", 7, 0) -+MEM_TEST("ld1 {v17.8b}, [x5], #8", 13, 0) -+ -+//////////////////////////////////////////////////////////////// -+printf("LD2/ST2 (multiple structures, post index) (VERY INCOMPLETE)\n"); -+ -+MEM_TEST("ld2 {v17.2d, v18.2d}, [x5], #32", 3, 0) -+MEM_TEST("st2 {v17.2d, v18.2d}, [x5], #32", 7, 0) -+ -+MEM_TEST("ld2 {v17.4s, v18.4s}, [x5], #32", 13, 0) -+MEM_TEST("st2 {v17.4s, v18.4s}, [x5], #32", 17, 0) -+ -+ -+//////////////////////////////////////////////////////////////// -+printf("LD1/ST1 (multiple structures, no offset) (VERY INCOMPLETE)\n"); -+ -+MEM_TEST("ld1 {v17.16b, v18.16b}, [x5]", 3, 0) -+MEM_TEST("st1 {v17.16b, v18.16b}, [x5]", 7, 0) -+ -+ -+} /* end of test_memory2() */ -+ -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////// -+ -+int main ( void ) -+{ -+ if (1) test_arith(); -+ if (1) test_memory(); -+ if (1) test_memory2(); -+ return 0; -+} -Index: none/tests/cmdline1.stdout.exp -=================================================================== ---- none/tests/cmdline1.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/cmdline1.stdout.exp (.../trunk) (revision 13981) -@@ -21,6 +21,8 @@ - --vgdb-error= invoke gdbserver after errors [999999999] - to get started quickly, use --vgdb-error=0 - and follow the on-screen directions -+ --vgdb-stop-at=event1,event2,... invoke gdbserver for given events [none] -+ where event is one of startup exit valgrindabexit all none - --track-fds=no|yes track open file descriptors? [no] - --time-stamp=no|yes add timestamps to log messages? [no] - --log-fd= log messages to file descriptor [2=stderr] -@@ -90,6 +92,7 @@ - program counters in max frames) [0] - --num-transtab-sectors= size of translated code cache [16] - more sectors may increase performance, but use more memory. -+ --aspace-minaddr=0xPP avoid mapping memory below 0xPP [guessed] - --show-emwarns=no|yes show warnings about emulation limits? [no] - --require-text-symbol=:sonamepattern:symbolpattern abort run if the - stated shared object doesn't have the stated -Index: none/tests/cmdline2.stdout.exp -=================================================================== ---- none/tests/cmdline2.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/cmdline2.stdout.exp (.../trunk) (revision 13981) -@@ -21,6 +21,8 @@ - --vgdb-error= invoke gdbserver after errors [999999999] - to get started quickly, use --vgdb-error=0 - and follow the on-screen directions -+ --vgdb-stop-at=event1,event2,... invoke gdbserver for given events [none] -+ where event is one of startup exit valgrindabexit all none - --track-fds=no|yes track open file descriptors? [no] - --time-stamp=no|yes add timestamps to log messages? [no] - --log-fd= log messages to file descriptor [2=stderr] -@@ -90,6 +92,7 @@ - program counters in max frames) [0] - --num-transtab-sectors= size of translated code cache [16] - more sectors may increase performance, but use more memory. -+ --aspace-minaddr=0xPP avoid mapping memory below 0xPP [guessed] - --show-emwarns=no|yes show warnings about emulation limits? [no] - --require-text-symbol=:sonamepattern:symbolpattern abort run if the - stated shared object doesn't have the stated -Index: none/tests/coolo_sigaction.cpp -=================================================================== ---- none/tests/coolo_sigaction.cpp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/coolo_sigaction.cpp (.../trunk) (revision 13981) -@@ -40,7 +40,6 @@ - - int main() - { -- int i; - char buffer[200]; - setupHandlers(); - FILE *p = popen("echo Hallo World", "r"); -@@ -48,7 +47,6 @@ - int n = fread(buffer, 200, 1, p); - __attribute__((unused)) ssize_t nw = write(2, buffer, n); - } -- fclose(p); -- for (i = 0; i < 1000000; i++) ; -+ pclose(p); - return 0; - } -Index: none/tests/faultstatus.c -=================================================================== ---- none/tests/faultstatus.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/faultstatus.c (.../trunk) (revision 13981) -@@ -18,7 +18,7 @@ - Hence we get a SIGFPE but the SI_CODE is different from that on - x86/amd64-linux. - */ --#if defined(__powerpc__) -+#if defined(__powerpc__) || defined(__aarch64__) - # define DIVISION_BY_ZERO_TRIGGERS_FPE 0 - # define DIVISION_BY_ZERO_SI_CODE SI_TKILL - #elif defined(__arm__) -@@ -41,7 +41,7 @@ - - static int zero(); - --static jmp_buf escape; -+static sigjmp_buf escape; - - #define BADADDR ((int *)0x1234) - -Index: none/tests/mips32 -=================================================================== ---- none/tests/mips32 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32 (.../trunk) (revision 13981) - -Property changes on: none/tests/mips32 -___________________________________________________________________ -Modified: svn:ignore -## -14,3 +14,11 ## - LoadStore - SignalException - bug320057-mips32 -+unaligned_load_store -+mips32_dsp -+mips32_dspr2 -+test_fcsr -+test_math -+round_fpu64 -+fpu_branches -+ -Index: none/tests/mips32/FPUarithmetic.c -=================================================================== ---- none/tests/mips32/FPUarithmetic.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/FPUarithmetic.c (.../trunk) (revision 13981) -@@ -1,4 +1,5 @@ - #include -+#include - - typedef enum { - ABSS=0, ABSD, -@@ -24,40 +25,44 @@ - "rsqrt.s", "rsqrt.d" - }; - -+typedef enum { -+ TO_NEAREST=0, TO_ZERO, TO_PLUS_INFINITY, TO_MINUS_INFINITY } round_mode_t; -+char *round_mode_name[] = { "near", "zero", "+inf", "-inf" }; -+ - const double fs_d[] = { -- 0, 456.2489562, 3, -1, -- 1384.6, -7.2945676, 1000000000, -5786.47, -- 1752, 0.0024575, 0.00000001, -248562.76, -- -45786.476, 456.2489562, 34.00046, 45786.476, -- 1752065, 107, -45667.24, -7.2945676, -- -347856.475, 356047.56, -1.0, 23.04 -+ 0, 456.25, 3, -1, -+ 1384.5, -7.25, 1000000000, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75, -+ 456, -45786.5, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7, -+ -347856.5, 356047.5, -1.0, 23.0625 - }; - - const double ft_d[] = { -- -45786.476, 456.2489562, 34.00046, 45786.476, -- 1752065, 107, -45667.24, -7.2945676, -- -347856.475, 356047.56, -1.0, 23.04, -- 0, 456.2489562, 3, -1, -- 1384.6, -7.2945676, 1000000000, -5786.47, -- 1752, 0.0024575, 0.00000001, -248562.76 -+ -456.25, -45786.5, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7.25, -+ -347856.5, 356047.5, -1.0, 23.0625, -+ 0, 456.25, 3, -1, -+ 1384.5, -7, 1000000000, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75 - }; - - const float fs_f[] = { -- 0, 456.2489562, 3, -1, -- 1384.6, -7.2945676, 1000000000, -5786.47, -- 1752, 0.0024575, 0.00000001, -248562.76, -- -45786.476, 456.2489562, 34.00046, 45786.476, -- 1752065, 107, -45667.24, -7.2945676, -- -347856.475, 356047.56, -1.0, 23.04 -+ 0, 456.25, 3, -1, -+ 1384.5, -7.25, 1000000000, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75, -+ 456, -45786.5, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7, -+ -347856.5, 356047.5, -1.0, 23.0625 - }; - - const float ft_f[] = { -- -45786.476, 456.2489562, 34.00046, 45786.476, -- 1752065, 107, -45667.24, -7.2945676, -- -347856.475, 356047.56, -1.0, 23.04, -- 0, 456.2489562, 3, -1, -- 1384.6, -7.2945676, 1000000000, -5786.47, -- 1752, 0.0024575, 0.00000001, -248562.76 -+ -456.25, -4578.5, 34.03125, 4578.75, -+ 175, 107, -456.25, -7.25, -+ -3478.5, 356.5, -1.0, 23.0625, -+ 0, 456.25, 3, -1, -+ 1384.5, -7, 100, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75 - }; - - #define UNOPdd(op) \ -@@ -84,98 +89,136 @@ - op" %0, %1, %2\n\t" \ - : "=f"(fd_d) : "f"(fs_d[i]) , "f"(ft_d[i])); - --int arithmeticOperations(flt_art_op_t op) -+void set_rounding_mode(round_mode_t mode) - { -+ switch(mode) { -+ case TO_NEAREST: -+ __asm__ volatile("cfc1 $t0, $31\n\t" -+ "srl $t0, 2\n\t" -+ "sll $t0, 2\n\t" -+ "ctc1 $t0, $31\n\t"); -+ break; -+ case TO_ZERO: -+ __asm__ volatile("cfc1 $t0, $31\n\t" -+ "srl $t0, 2\n\t" -+ "sll $t0, 2\n\t" -+ "addiu $t0, 1\n\t" -+ "ctc1 $t0, $31\n\t"); -+ break; -+ case TO_PLUS_INFINITY: -+ __asm__ volatile("cfc1 $t0, $31\n\t" -+ "srl $t0, 2\n\t" -+ "sll $t0, 2\n\t" -+ "addiu $t0, 2\n\t" -+ "ctc1 $t0, $31\n\t"); -+ break; -+ case TO_MINUS_INFINITY: -+ __asm__ volatile("cfc1 $t0, $31\n\t" -+ "srl $t0, 2\n\t" -+ "sll $t0, 2\n\t" -+ "addiu $t0, 3\n\t" -+ "ctc1 $t0, $31\n\t"); -+ break; -+ } -+} -+ -+int arithmeticOperations(flt_art_op_t op) -+{ - double fd_d = 0; - float fd_f = 0; - int i = 0; -- for (i = 0; i < 24; i++) -- { -- switch(op) { -- case ABSS: -- UNOPff("abs.s"); -- printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -- break; -- case ABSD: -- UNOPdd("abs.d"); -- printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -- break; -- case ADDS: -- BINOPf("add.s"); -- printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -- break; -- case ADDD: -- BINOPd("add.d"); -- printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -- break; -- case DIVS: -- BINOPf("div.s"); -- printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -- break; -- case DIVD: -- BINOPd("div.d"); -- printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -- break; -- case MULS: -- BINOPf("mul.s"); -- printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -- break; -- case MULD: -- BINOPd("mul.d"); -- printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -- break; -- case NEGS: -- UNOPff("neg.s"); -- printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -- break; -- case NEGD: -- UNOPdd("neg.d"); -- printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -- break; -- case SQRTS: -- UNOPff("sqrt.s"); -- printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -- break; -- case SQRTD: -- UNOPdd("sqrt.d"); -- printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -- break; -- case SUBS: -- BINOPf("sub.s"); -- printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -- break; -- case SUBD: -- BINOPd("sub.d"); -- printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -- break; -- case RECIPS: -+ round_mode_t rm; -+ for (rm = TO_NEAREST; rm <= TO_MINUS_INFINITY; rm ++) { -+ set_rounding_mode(rm); -+ printf("rounding mode: %s\n", round_mode_name[rm]); -+ for (i = 0; i < 24; i++) -+ { -+ switch(op) { -+ case ABSS: -+ UNOPff("abs.s"); -+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -+ break; -+ case ABSD: -+ UNOPdd("abs.d"); -+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -+ break; -+ case ADDS: -+ BINOPf("add.s"); -+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -+ break; -+ case ADDD: -+ BINOPd("add.d"); -+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -+ break; -+ case DIVS: -+ BINOPf("div.s"); -+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -+ break; -+ case DIVD: -+ BINOPd("div.d"); -+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -+ break; -+ case MULS: -+ BINOPf("mul.s"); -+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -+ break; -+ case MULD: -+ BINOPd("mul.d"); -+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -+ break; -+ case NEGS: -+ UNOPff("neg.s"); -+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -+ break; -+ case NEGD: -+ UNOPdd("neg.d"); -+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -+ break; -+ case SQRTS: -+ UNOPff("sqrt.s"); -+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -+ break; -+ case SQRTD: -+ UNOPdd("sqrt.d"); -+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -+ break; -+ case SUBS: -+ BINOPf("sub.s"); -+ printf("%s %f %f %f\n", flt_art_op_names[op], fd_f, fs_f[i], ft_f[i]); -+ break; -+ case SUBD: -+ BINOPd("sub.d"); -+ printf("%s %lf %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i], ft_d[i]); -+ break; -+ case RECIPS: - #if (__mips==32) && (__mips_isa_rev>=2) -- UNOPff("recip.s"); -- printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -+ UNOPff("recip.s"); -+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); - #endif -- break; -- case RECIPD: -+ break; -+ case RECIPD: - #if (__mips==32) && (__mips_isa_rev>=2) -- UNOPdd("recip.d"); -- printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -+ UNOPdd("recip.d"); -+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); - #endif -- break; -- case RSQRTS: -+ break; -+ case RSQRTS: - #if (__mips==32) && (__mips_isa_rev>=2) -- UNOPff("rsqrt.s"); -- printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); -+ UNOPff("rsqrt.s"); -+ printf("%s %f %f\n", flt_art_op_names[op], fd_f, fs_f[i]); - #endif -- break; -- case RSQRTD: -+ break; -+ case RSQRTD: - #if (__mips==32) && (__mips_isa_rev>=2) -- UNOPdd("rsqrt.d"); -- printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); -+ UNOPdd("rsqrt.d"); -+ printf("%s %lf %lf\n", flt_art_op_names[op], fd_d, fs_d[i]); - #endif -- break; -- default: -- printf("error\n"); -- break; -- } -+ break; -+ default: -+ printf("error\n"); -+ break; -+ } -+ } - } - return 0; - } -Index: none/tests/mips32/FPUarithmetic.stdout.exp -=================================================================== ---- none/tests/mips32/FPUarithmetic.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/FPUarithmetic.stdout.exp (.../trunk) (revision 13981) -@@ -1,385 +1,1601 @@ - -------------------------- test FPU Arithmetic Operations -------------------------- -+rounding mode: near - abs.s 0.000000 0.000000 --abs.s 456.248962 456.248962 -+abs.s 456.250000 456.250000 - abs.s 3.000000 3.000000 - abs.s 1.000000 -1.000000 --abs.s 1384.599976 1384.599976 --abs.s 7.294568 -7.294568 -+abs.s 1384.500000 1384.500000 -+abs.s 7.250000 -7.250000 - abs.s 1000000000.000000 1000000000.000000 --abs.s 5786.470215 -5786.470215 -+abs.s 5786.500000 -5786.500000 - abs.s 1752.000000 1752.000000 --abs.s 0.002457 0.002457 -+abs.s 0.015625 0.015625 -+abs.s 0.031250 0.031250 -+abs.s 248562.750000 -248562.750000 -+abs.s 456.000000 456.000000 -+abs.s 45786.500000 -45786.500000 -+abs.s 34.031250 34.031250 -+abs.s 45786.750000 45786.750000 -+abs.s 1752065.000000 1752065.000000 -+abs.s 107.000000 107.000000 -+abs.s 45667.250000 -45667.250000 -+abs.s 7.000000 -7.000000 -+abs.s 347856.500000 -347856.500000 -+abs.s 356047.500000 356047.500000 -+abs.s 1.000000 -1.000000 -+abs.s 23.062500 23.062500 -+rounding mode: zero - abs.s 0.000000 0.000000 --abs.s 248562.765625 -248562.765625 --abs.s 45786.476562 -45786.476562 --abs.s 456.248962 456.248962 --abs.s 34.000462 34.000462 --abs.s 45786.476562 45786.476562 -+abs.s 456.250000 456.250000 -+abs.s 3.000000 3.000000 -+abs.s 1.000000 -1.000000 -+abs.s 1384.500000 1384.500000 -+abs.s 7.250000 -7.250000 -+abs.s 1000000000.000000 1000000000.000000 -+abs.s 5786.500000 -5786.500000 -+abs.s 1752.000000 1752.000000 -+abs.s 0.015625 0.015625 -+abs.s 0.031250 0.031250 -+abs.s 248562.750000 -248562.750000 -+abs.s 456.000000 456.000000 -+abs.s 45786.500000 -45786.500000 -+abs.s 34.031250 34.031250 -+abs.s 45786.750000 45786.750000 - abs.s 1752065.000000 1752065.000000 - abs.s 107.000000 107.000000 --abs.s 45667.238281 -45667.238281 --abs.s 7.294568 -7.294568 --abs.s 347856.468750 -347856.468750 --abs.s 356047.562500 356047.562500 -+abs.s 45667.250000 -45667.250000 -+abs.s 7.000000 -7.000000 -+abs.s 347856.500000 -347856.500000 -+abs.s 356047.500000 356047.500000 - abs.s 1.000000 -1.000000 --abs.s 23.040001 23.040001 -+abs.s 23.062500 23.062500 -+rounding mode: +inf -+abs.s 0.000000 0.000000 -+abs.s 456.250000 456.250000 -+abs.s 3.000000 3.000000 -+abs.s 1.000000 -1.000000 -+abs.s 1384.500000 1384.500000 -+abs.s 7.250000 -7.250000 -+abs.s 1000000000.000000 1000000000.000000 -+abs.s 5786.500000 -5786.500000 -+abs.s 1752.000000 1752.000000 -+abs.s 0.015625 0.015625 -+abs.s 0.031250 0.031250 -+abs.s 248562.750000 -248562.750000 -+abs.s 456.000000 456.000000 -+abs.s 45786.500000 -45786.500000 -+abs.s 34.031250 34.031250 -+abs.s 45786.750000 45786.750000 -+abs.s 1752065.000000 1752065.000000 -+abs.s 107.000000 107.000000 -+abs.s 45667.250000 -45667.250000 -+abs.s 7.000000 -7.000000 -+abs.s 347856.500000 -347856.500000 -+abs.s 356047.500000 356047.500000 -+abs.s 1.000000 -1.000000 -+abs.s 23.062500 23.062500 -+rounding mode: -inf -+abs.s 0.000000 0.000000 -+abs.s 456.250000 456.250000 -+abs.s 3.000000 3.000000 -+abs.s 1.000000 -1.000000 -+abs.s 1384.500000 1384.500000 -+abs.s 7.250000 -7.250000 -+abs.s 1000000000.000000 1000000000.000000 -+abs.s 5786.500000 -5786.500000 -+abs.s 1752.000000 1752.000000 -+abs.s 0.015625 0.015625 -+abs.s 0.031250 0.031250 -+abs.s 248562.750000 -248562.750000 -+abs.s 456.000000 456.000000 -+abs.s 45786.500000 -45786.500000 -+abs.s 34.031250 34.031250 -+abs.s 45786.750000 45786.750000 -+abs.s 1752065.000000 1752065.000000 -+abs.s 107.000000 107.000000 -+abs.s 45667.250000 -45667.250000 -+abs.s 7.000000 -7.000000 -+abs.s 347856.500000 -347856.500000 -+abs.s 356047.500000 356047.500000 -+abs.s 1.000000 -1.000000 -+abs.s 23.062500 23.062500 -+rounding mode: near - abs.d 0.000000 0.000000 --abs.d 456.248956 456.248956 -+abs.d 456.250000 456.250000 - abs.d 3.000000 3.000000 - abs.d 1.000000 -1.000000 --abs.d 1384.600000 1384.600000 --abs.d 7.294568 -7.294568 -+abs.d 1384.500000 1384.500000 -+abs.d 7.250000 -7.250000 - abs.d 1000000000.000000 1000000000.000000 --abs.d 5786.470000 -5786.470000 -+abs.d 5786.500000 -5786.500000 - abs.d 1752.000000 1752.000000 --abs.d 0.002458 0.002458 -+abs.d 0.015625 0.015625 -+abs.d 0.031250 0.031250 -+abs.d 248562.750000 -248562.750000 -+abs.d 456.000000 456.000000 -+abs.d 45786.500000 -45786.500000 -+abs.d 34.031250 34.031250 -+abs.d 45786.750000 45786.750000 -+abs.d 1752065.000000 1752065.000000 -+abs.d 107.000000 107.000000 -+abs.d 45667.250000 -45667.250000 -+abs.d 7.000000 -7.000000 -+abs.d 347856.500000 -347856.500000 -+abs.d 356047.500000 356047.500000 -+abs.d 1.000000 -1.000000 -+abs.d 23.062500 23.062500 -+rounding mode: zero - abs.d 0.000000 0.000000 --abs.d 248562.760000 -248562.760000 --abs.d 45786.476000 -45786.476000 --abs.d 456.248956 456.248956 --abs.d 34.000460 34.000460 --abs.d 45786.476000 45786.476000 -+abs.d 456.250000 456.250000 -+abs.d 3.000000 3.000000 -+abs.d 1.000000 -1.000000 -+abs.d 1384.500000 1384.500000 -+abs.d 7.250000 -7.250000 -+abs.d 1000000000.000000 1000000000.000000 -+abs.d 5786.500000 -5786.500000 -+abs.d 1752.000000 1752.000000 -+abs.d 0.015625 0.015625 -+abs.d 0.031250 0.031250 -+abs.d 248562.750000 -248562.750000 -+abs.d 456.000000 456.000000 -+abs.d 45786.500000 -45786.500000 -+abs.d 34.031250 34.031250 -+abs.d 45786.750000 45786.750000 - abs.d 1752065.000000 1752065.000000 - abs.d 107.000000 107.000000 --abs.d 45667.240000 -45667.240000 --abs.d 7.294568 -7.294568 --abs.d 347856.475000 -347856.475000 --abs.d 356047.560000 356047.560000 -+abs.d 45667.250000 -45667.250000 -+abs.d 7.000000 -7.000000 -+abs.d 347856.500000 -347856.500000 -+abs.d 356047.500000 356047.500000 - abs.d 1.000000 -1.000000 --abs.d 23.040000 23.040000 --add.s -45786.476562 0.000000 -45786.476562 --add.s 912.497925 456.248962 456.248962 --add.s 37.000462 3.000000 34.000462 --add.s 45785.476562 -1.000000 45786.476562 --add.s 1753449.625000 1384.599976 1752065.000000 --add.s 99.705429 -7.294568 107.000000 --add.s 999954304.000000 1000000000.000000 -45667.238281 --add.s -5793.764648 -5786.470215 -7.294568 --add.s -346104.468750 1752.000000 -347856.468750 --add.s 356047.562500 0.002457 356047.562500 --add.s -1.000000 0.000000 -1.000000 --add.s -248539.718750 -248562.765625 23.040001 --add.s -45786.476562 -45786.476562 0.000000 --add.s 912.497925 456.248962 456.248962 --add.s 37.000462 34.000462 3.000000 --add.s 45785.476562 45786.476562 -1.000000 --add.s 1753449.625000 1752065.000000 1384.599976 --add.s 99.705429 107.000000 -7.294568 --add.s 999954304.000000 -45667.238281 1000000000.000000 --add.s -5793.764648 -7.294568 -5786.470215 --add.s -346104.468750 -347856.468750 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-=================================================================== ---- none/tests/mips32/FPUarithmetic.stdout.exp-mips32 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/FPUarithmetic.stdout.exp-mips32 (.../trunk) (revision 13981) -@@ -1,337 +1,1409 @@ - -------------------------- test FPU Arithmetic Operations -------------------------- -+rounding mode: near - abs.s 0.000000 0.000000 --abs.s 456.248962 456.248962 -+abs.s 456.250000 456.250000 - abs.s 3.000000 3.000000 - abs.s 1.000000 -1.000000 --abs.s 1384.599976 1384.599976 --abs.s 7.294568 -7.294568 -+abs.s 1384.500000 1384.500000 -+abs.s 7.250000 -7.250000 - abs.s 1000000000.000000 1000000000.000000 --abs.s 5786.470215 -5786.470215 -+abs.s 5786.500000 -5786.500000 - abs.s 1752.000000 1752.000000 --abs.s 0.002457 0.002457 -+abs.s 0.015625 0.015625 -+abs.s 0.031250 0.031250 -+abs.s 248562.750000 -248562.750000 -+abs.s 456.000000 456.000000 -+abs.s 45786.500000 -45786.500000 -+abs.s 34.031250 34.031250 -+abs.s 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0.000000 -+sub.d -46242.750000 -45786.500000 456.250000 -+sub.d 31.031250 34.031250 3.000000 -+sub.d 45787.750000 45786.750000 -1.000000 -+sub.d 1750680.500000 1752065.000000 1384.500000 -+sub.d 114.000000 107.000000 -7.000000 -+sub.d -1000045667.250000 -45667.250000 1000000000.000000 -+sub.d 5779.500000 -7.000000 -5786.500000 -+sub.d -349608.500000 -347856.500000 1752.000000 -+sub.d 356047.484375 356047.500000 0.015625 -+sub.d -1.031250 -1.000000 0.031250 -+sub.d 248585.812500 23.062500 -248562.750000 -+rounding mode: -inf -+sub.d 456.250000 0.000000 -456.250000 -+sub.d 46242.750000 456.250000 -45786.500000 -+sub.d -31.031250 3.000000 34.031250 -+sub.d -45787.750000 -1.000000 45786.750000 -+sub.d -1750680.500000 1384.500000 1752065.000000 -+sub.d -114.250000 -7.250000 107.000000 -+sub.d 1000045667.250000 1000000000.000000 -45667.250000 -+sub.d -5779.250000 -5786.500000 -7.250000 -+sub.d 349608.500000 1752.000000 -347856.500000 -+sub.d -356047.484375 0.015625 356047.500000 -+sub.d 1.031250 0.031250 -1.000000 -+sub.d -248585.812500 -248562.750000 23.062500 -+sub.d 456.000000 456.000000 0.000000 -+sub.d -46242.750000 -45786.500000 456.250000 -+sub.d 31.031250 34.031250 3.000000 -+sub.d 45787.750000 45786.750000 -1.000000 -+sub.d 1750680.500000 1752065.000000 1384.500000 -+sub.d 114.000000 107.000000 -7.000000 -+sub.d -1000045667.250000 -45667.250000 1000000000.000000 -+sub.d 5779.500000 -7.000000 -5786.500000 -+sub.d -349608.500000 -347856.500000 1752.000000 -+sub.d 356047.484375 356047.500000 0.015625 -+sub.d -1.031250 -1.000000 0.031250 -+sub.d 248585.812500 23.062500 -248562.750000 -+rounding mode: near -+rounding mode: zero -+rounding mode: +inf -+rounding mode: -inf -+rounding mode: near -+rounding mode: zero -+rounding mode: +inf -+rounding mode: -inf -Index: none/tests/mips32/LoadStore.c -=================================================================== ---- none/tests/mips32/LoadStore.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/LoadStore.c (.../trunk) (revision 13981) -@@ -80,7 +80,7 @@ - m[i+1] = 0; - m[i+2] = 0; - m[i+3] = 0; -- if (i == 2) -+ if (i == 2) - { - m[i] = 0xffffffff; - m[i+1] = 0; -Index: none/tests/mips32/Makefile.am -=================================================================== ---- none/tests/mips32/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/Makefile.am (.../trunk) (revision 13981) -@@ -24,14 +24,17 @@ - SignalException.stderr.exp SignalException.vgtest \ - bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \ - bug320057-mips32.vgtest \ -- mips32_dsp.stdout.exp mips32_dsp.stdout.exp-BE \ -- mips32_dsp.stdout.exp-mips32 mips32_dsp.stderr.exp \ -- mips32_dsp.vgtest \ -+ mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \ -+ mips32_dsp.stderr.exp mips32_dsp.vgtest \ - mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \ -- mips32_dspr2.stdout.exp-mips32 mips32_dspr2.vgtest \ -+ mips32_dspr2.vgtest \ - unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \ - unaligned_load_store.stderr.exp unaligned_load_store.vgtest \ -- test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest -+ test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \ -+ test_math.stdout.exp test_math.stderr.exp test_math.vgtest \ -+ round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \ -+ round_fpu64.stderr.exp round_fpu64.vgtest \ -+ fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest - - check_PROGRAMS = \ - allexec \ -@@ -50,7 +53,10 @@ - mips32_dsp \ - mips32_dspr2 \ - unaligned_load_store \ -- test_fcsr -+ test_fcsr \ -+ test_math \ -+ round_fpu64 \ -+ fpu_branches - - AM_CFLAGS += @FLAG_M32@ - AM_CXXFLAGS += @FLAG_M32@ -@@ -58,3 +64,6 @@ - - allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ - bug320057_mips32_LDFLAGS = -lrt -+ -+# C++ tests -+test_math_SOURCES = test_math.cpp -Index: none/tests/mips32/MemCpyTest.c -=================================================================== ---- none/tests/mips32/MemCpyTest.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/MemCpyTest.c (.../trunk) (revision 13981) -@@ -30,7 +30,7 @@ - - unsigned int mem2[100]; - --int main () -+int main () - { - int i, out; - for (i = 0; i < 100; i++) -Index: none/tests/mips32/MoveIns.c -=================================================================== ---- none/tests/mips32/MoveIns.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/MoveIns.c (.../trunk) (revision 13981) -@@ -168,6 +168,7 @@ - "mtc1 $t1, $f2\n\t" \ - "c.eq.s $f0, $f2\n\t" \ - "move $t0, %2\n\t" \ -+ "lwc1 $" #FD ", 4($t0)\n\t" \ - "lwc1 $" #FS ", "#offset"($t0)\n\t" \ - instruction "\n\t" \ - "mov.s %0, $" #FD"\n\t" \ -@@ -180,6 +181,7 @@ - } - - // movf.d fd, fs -+#if (__mips_fpr==64) - #define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \ - { \ - double out; \ -@@ -187,11 +189,37 @@ - int out2; \ - __asm__ volatile( \ - "li $t0, 1\n\t" \ -+ "mtc1 $t0, $f0\n\t" \ -+ "mtc1 %3, $f2\n\t" \ -+ "move $t0, %4\n\t" \ -+ "ldc1 $f4, 8($t0)\n\t" \ -+ "c.eq.s $f0, $f2\n\t" \ -+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \ -+ instruction "\n\t" \ -+ "mov.d %0, $" #FD"\n\t" \ -+ "mfc1 %1, $f4\n\t" \ -+ "mfhc1 %2, $f4\n\t" \ -+ : "=&f" (out), "=&r" (out1), "=&r" (out2) \ -+ : "r" (cc), "r" (mem) \ -+ : "t0", "t1", "cc", "memory" \ -+ ); \ -+ printf("%s :: out: 0x%x 0x%x, cc: %d\n", \ -+ instruction, out1, out2, cc); \ -+} -+#else -+#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \ -+{ \ -+ double out; \ -+ int out1; \ -+ int out2; \ -+ __asm__ volatile( \ -+ "li $t0, 1\n\t" \ - "move $t1, %3\n\t" \ - "mtc1 $t0, $f0\n\t" \ - "mtc1 $t1, $f2\n\t" \ -+ "move $t0, %4\n\t" \ -+ "ldc1 $f4, 8($t0)\n\t" \ - "c.eq.s $f0, $f2\n\t" \ -- "move $t0, %4\n\t" \ - "ldc1 $" #FS ", "#offset"($t0)\n\t" \ - instruction "\n\t" \ - "mov.d %0, $" #FD"\n\t" \ -@@ -204,6 +232,7 @@ - printf("%s :: out: 0x%x 0x%x, cc: %d\n", \ - instruction, out1, out2, cc); \ - } -+#endif - - // movn.s fd, fs, rt - #define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \ -Index: none/tests/mips32/MoveIns.stdout.exp -=================================================================== ---- none/tests/mips32/MoveIns.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/MoveIns.stdout.exp (.../trunk) (revision 13981) -@@ -128,21 +128,21 @@ - movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 - movf $t0, $t1, $fcc4 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0 - MOVF.S --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 --movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 -+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 - movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0 - movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 - movf.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 0 -@@ -159,21 +159,21 @@ - movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 - movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 - MOVF.D --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0x43e41fde, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 - movf.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 0 - movf.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 0 - movf.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 0 -@@ -256,21 +256,21 @@ - movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 - movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 - movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 - MOVT.D - movt.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 1 - movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1 -@@ -287,21 +287,21 @@ - movt.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 1 - movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1 - movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 1 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0 - MOVZ.S - movz.s $f0, $f2, $t3 :: fs rt 0x0 - movz.s $f0, $f2, $t3 :: fs rt 0x0 -Index: none/tests/mips32/MoveIns.stdout.exp-BE -=================================================================== ---- none/tests/mips32/MoveIns.stdout.exp-BE (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/MoveIns.stdout.exp-BE (.../trunk) (revision 13981) -@@ -159,21 +159,21 @@ - movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 - movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 - MOVF.D --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 --movf.d $f4, $f6, $fcc0 :: out: 0x42080079 0xc732da7a, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 - movf.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 0 - movf.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 0 - movf.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 0 -@@ -256,21 +256,21 @@ - movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1 - movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1 - movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 --movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 -+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0 - MOVT.D - movt.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 1 - movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1 -@@ -287,21 +287,21 @@ - movt.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 1 - movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1 - movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 1 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 --movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 -+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0 - MOVZ.S - movz.s $f0, $f2, $t3 :: fs rt 0x0 - movz.s $f0, $f2, $t3 :: fs rt 0x0 -Index: none/tests/mips32/SignalException.c -=================================================================== ---- none/tests/mips32/SignalException.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/SignalException.c (.../trunk) (revision 13981) -@@ -1,4 +1,4 @@ --/* -+/* - Check that a fault signal handler gets the expected info - */ - #include -Index: none/tests/mips32/branches.c -=================================================================== ---- none/tests/mips32/branches.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/branches.c (.../trunk) (revision 13981) -@@ -241,7 +241,7 @@ - out, RSval); \ - } - --int main() -+int main() - { - printf("b \n"); - TESTINST1(0, v0); -Index: none/tests/mips32/fpu_branches.c -=================================================================== ---- none/tests/mips32/fpu_branches.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/fpu_branches.c (.../trunk) (revision 13981) -@@ -0,0 +1,317 @@ -+#include -+ -+#define MAX_ARR 24 -+ -+const float fs_f[] = { -+ 0, 456.25, 3, -1, -+ 1384.5, -7.25, 1000000000, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75, -+ -45786.5, 456, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7, -+ -347856.5, 356047.5, -1.0, 23.0625 -+}; -+ -+const float ft_f[] = { -+ -4578.5, 456.25, 34.03125, 4578.75, -+ 175, 107, -456.25, -7.25, -+ -3478.5, 356.5, -1.0, 23.0625, -+ 0, 456.25, 3, -1, -+ 1384.5, -7, 100, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75 -+}; -+ -+const double fs_d[] = { -+ 0, 456.25, 3, -1, -+ 1384.5, -7.25, 1000000000, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75, -+ -45786.5, 456, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7, -+ -347856.5, 356047.5, -1.0, 23.0625 -+}; -+ -+const double ft_d[] = { -+ -45786.5, 456.25, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7.25, -+ -347856.5, 356047.5, -1.0, 23.0625, -+ 0, 456.25, 3, -1, -+ 1384.5, -7, 1000000000, -5786.5, -+ 1752, 0.015625, 0.03125, -248562.75 -+}; -+ -+/* Conditional macros.*/ -+#define TESTINST1s(instruction, RDval) \ -+{ \ -+ float outf = 0; \ -+ __asm__ __volatile__( \ -+ ".set noreorder" "\n\t" \ -+ "mov.s $f0, %1" "\n\t" \ -+ "mov.s $f2, %2" "\n\t" \ -+ "c.eq.s $f0, $f2" "\n\t" \ -+ instruction" end"instruction"s"#RDval "\n\t" \ -+ "nop" "\n\t" \ -+ "add.s $f0, $f0, $f2" "\n\t" \ -+ "end"instruction"s"#RDval":" "\n\t" \ -+ "mov.s %0, $f0" "\n\t" \ -+ ".set reorder" "\n\t" \ -+ : "=f" (outf) \ -+ : "f" (fs_f[i]) , "f" (ft_f[i]) \ -+ : "$f0", "$f2" \ -+ ); \ -+ printf("%s, c.eq.s out=%f, fs=%f, ft=%f\n", \ -+ instruction, outf, fs_f[i], ft_f[i]); \ -+} -+ -+#define TESTINST1d(instruction, RDval) \ -+{ \ -+ double outd = 0; \ -+ __asm__ __volatile__( \ -+ ".set noreorder" "\n\t" \ -+ "mov.d $f0, %1" "\n\t" \ -+ "mov.d $f2, %2" "\n\t" \ -+ "c.eq.d $f0, $f2" "\n\t" \ -+ instruction" end"instruction"d"#RDval "\n\t" \ -+ "nop" "\n\t" \ -+ "add.d $f0, $f0, $f2" "\n\t" \ -+ "end"instruction"d"#RDval":" "\n\t" \ -+ "mov.d %0, $f0" "\n\t" \ -+ ".set reorder" "\n\t" \ -+ : "=f" (outd) \ -+ : "f" (fs_d[i]) , "f" (ft_d[i]) \ -+ : "$f0", "$f1", "$f2", "$f3" \ -+ ); \ -+ printf("%s, c.eq.d out=%f, fs=%f, ft=%f\n", \ -+ instruction, outd, fs_d[i], ft_d[i]); \ -+} -+ -+#define TESTINST2s(instruction, RDval) \ -+{ \ -+ float outf = 0; \ -+ __asm__ __volatile__( \ -+ ".set noreorder" "\n\t" \ -+ "mov.s $f0, %1" "\n\t" \ -+ "mov.s $f2, %2" "\n\t" \ -+ "c.eq.s $f0, $f2" "\n\t" \ -+ instruction" end"instruction"s"#RDval "\n\t" \ -+ "add.s $f0, $f0, $f2" "\n\t" \ -+ "end"instruction"s"#RDval":" "\n\t" \ -+ "mov.s %0, $f0" "\n\t" \ -+ ".set reorder" "\n\t" \ -+ : "=f" (outf) \ -+ : "f" (fs_f[i]) , "f" (ft_f[i]) \ -+ : "$f0", "$f2" \ -+ ); \ -+ printf("%s, c.eq.s out=%f, fs=%f, ft=%f\n", \ -+ instruction, outf, fs_f[i], ft_f[i]); \ -+} -+ -+#define TESTINST2d(instruction, RDval) \ -+{ \ -+ double outd = 0; \ -+ __asm__ __volatile__( \ -+ ".set noreorder" "\n\t" \ -+ "mov.d $f0, %1" "\n\t" \ -+ "mov.d $f2, %2" "\n\t" \ -+ "c.eq.d $f0, $f2" "\n\t" \ -+ instruction" end"instruction"d"#RDval "\n\t" \ -+ "add.d $f0, $f0, $f2" "\n\t" \ -+ "end"instruction"d"#RDval":" "\n\t" \ -+ "mov.d %0, $f0" "\n\t" \ -+ ".set reorder" "\n\t" \ -+ : "=f" (outd) \ -+ : "f" (fs_d[i]) , "f" (ft_d[i]) \ -+ : "$f0", "$f1", "$f2", "$f3" \ -+ ); \ -+ printf("%s, c.eq.d out=%f, fs=%f, ft=%f\n", \ -+ instruction, outd, fs_d[i], ft_d[i]); \ -+} -+ -+#define TESTINST_CONDs(instruction, RDval) \ -+{ \ -+ float outf = 0; \ -+ __asm__ __volatile__( \ -+ ".set noreorder" "\n\t" \ -+ "mov.s $f0, %1" "\n\t" \ -+ "mov.s $f2, %2" "\n\t" \ -+ instruction" $f0, $f2" "\n\t" \ -+ "bc1f end"instruction"s"#RDval "\n\t" \ -+ "nop" "\n\t" \ -+ "add.s $f0, $f0, $f2" "\n\t" \ -+ "end"instruction"s"#RDval":" "\n\t" \ -+ "mov.s %0, $f0" "\n\t" \ -+ ".set reorder" "\n\t" \ -+ : "=f" (outf) \ -+ : "f" (fs_f[i]) , "f" (ft_f[i]) \ -+ : "$f0", "$f1", "$f2" \ -+ ); \ -+ printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \ -+ instruction, outf, fs_f[i], ft_f[i]); \ -+} -+ -+#define TESTINST_CONDd(instruction, RDval) \ -+{ \ -+ double outd = 0; \ -+ __asm__ __volatile__( \ -+ ".set noreorder" "\n\t" \ -+ "mov.d $f0, %1" "\n\t" \ -+ "mov.d $f2, %2" "\n\t" \ -+ instruction" $f0, $f2" "\n\t" \ -+ "bc1f end"instruction"d"#RDval "\n\t" \ -+ "nop" "\n\t" \ -+ "add.d $f0, $f0, $f2" "\n\t" \ -+ "end"instruction"d"#RDval":" "\n\t" \ -+ "mov.d %0, $f0" "\n\t" \ -+ ".set reorder" "\n\t" \ -+ : "=f" (outd) \ -+ : "f" (fs_d[i]) , "f" (ft_d[i]) \ -+ : "$f0", "$f1", "$f2", "$f2" \ -+ ); \ -+ printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \ -+ instruction, outd, fs_d[i], ft_d[i]); \ -+} -+ -+int main() -+{ -+ int i = 0; -+ -+ printf("--- BC1F --- if fs != ft then " \ -+ "out = fs else out = fs + ft\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST1s("bc1f", i); -+ TESTINST1d("bc1f", i); -+ } -+ -+ printf("--- BC1T --- if fs == ft then " \ -+ "out = fs else out = fs + ft\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST1s("bc1t", i); -+ TESTINST1d("bc1t", i); -+ } -+ -+ printf("--- BC1FL --- if fs == ft then " \ -+ "out = ft else out = fs + ft\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST2s("bc1fl", i); -+ TESTINST2d("bc1fl", i); -+ } -+ -+ printf("--- BC1TL --- if fs != ft then " \ -+ "out = fs else out = fs + ft\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST2s("bc1tl", i); -+ TESTINST2d("bc1tl", i); -+ } -+ -+ printf("--- C.F.S/D --- if false then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.f.s", i); -+ TESTINST_CONDd("c.f.d", i); -+ } -+ -+ printf("--- C.UN.S/D --- if unordered(fs, ft) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.un.s", i); -+ TESTINST_CONDd("c.un.d", i); -+ } -+ -+ printf("--- C.EQ.S/D --- if fs == ft then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.eq.s", i); -+ TESTINST_CONDd("c.eq.d", i); -+ } -+ -+ printf("--- C.UEQ.S/D --- if (unordered(fs, ft) or (fs == ft)) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.ueq.s", i); -+ TESTINST_CONDd("c.ueq.d", i); -+ } -+ -+ printf("--- C.OLT.S/D --- if (ordered(fs, ft) or (fs < ft)) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.olt.s", i); -+ TESTINST_CONDd("c.olt.d", i); -+ } -+ -+ printf("--- C.ULT.S/D --- if (unordered(fs, ft) or (fs < ft)) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.ult.s", i); -+ TESTINST_CONDd("c.ult.d", i); -+ } -+ -+ printf("--- C.OLE.S/D --- if (ordered(fs, ft) or (fs <= ft)) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.ole.s", i); -+ TESTINST_CONDd("c.ole.d", i); -+ } -+ -+ printf("--- C.ULE.S/D --- if (unordered(fs, ft) or (fs <= ft)) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.ule.s", i); -+ TESTINST_CONDd("c.ule.d", i); -+ } -+ -+ printf("--- C.SF.S/D --- if signaling false then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.sf.s", i); -+ TESTINST_CONDd("c.sf.d", i); -+ } -+ -+ printf("--- C.NGLE.S/D --- if not ((fs > ft) or (fs <= ft)) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.ngle.s", i); -+ TESTINST_CONDd("c.ngle.d", i); -+ } -+ -+ printf("--- C.SEQ.S/D --- if signaling equal then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.seq.s", i); -+ TESTINST_CONDd("c.seq.d", i); -+ } -+ -+ printf("--- C.NGL.S/D --- if not ((fs > ft) or (fs < ft)) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.ngl.s", i); -+ TESTINST_CONDd("c.ngl.d", i); -+ } -+ -+ printf("--- C.LT.S/D --- if fs < ft then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.lt.s", i); -+ TESTINST_CONDd("c.lt.d", i); -+ } -+ -+ printf("--- C.NGE.S/D --- if not (fs >= ft) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.nge.s", i); -+ TESTINST_CONDd("c.nge.d", i); -+ } -+ -+ printf("--- C.LE.S/D --- if fs <= ft then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.le.s", i); -+ TESTINST_CONDd("c.le.d", i); -+ } -+ -+ printf("--- C.NGT.S/D --- if not (fs > ft) then " \ -+ "out = fs + ft else out = fs\n"); -+ for (i = 0; i < MAX_ARR; i++) { -+ TESTINST_CONDs("c.ngt.s", i); -+ TESTINST_CONDd("c.ngt.d", i); -+ } -+ return 0; -+} -+ -Index: none/tests/mips32/fpu_branches.stderr.exp -=================================================================== -Index: none/tests/mips32/fpu_branches.stdout.exp -=================================================================== ---- none/tests/mips32/fpu_branches.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/fpu_branches.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,980 @@ -+--- BC1F --- if fs != ft then out = fs else out = fs + ft -+bc1f, c.eq.s out=0.000000, fs=0.000000, ft=-4578.500000 -+bc1f, c.eq.d out=0.000000, fs=0.000000, ft=-45786.500000 -+bc1f, c.eq.s out=912.500000, fs=456.250000, ft=456.250000 -+bc1f, c.eq.d out=912.500000, fs=456.250000, ft=456.250000 -+bc1f, c.eq.s out=3.000000, fs=3.000000, ft=34.031250 -+bc1f, c.eq.d out=3.000000, fs=3.000000, ft=34.031250 -+bc1f, c.eq.s out=-1.000000, fs=-1.000000, ft=4578.750000 -+bc1f, c.eq.d out=-1.000000, fs=-1.000000, ft=45786.750000 -+bc1f, c.eq.s out=1384.500000, fs=1384.500000, ft=175.000000 -+bc1f, c.eq.d out=1384.500000, fs=1384.500000, ft=1752065.000000 -+bc1f, c.eq.s out=-7.250000, fs=-7.250000, ft=107.000000 -+bc1f, c.eq.d out=-7.250000, fs=-7.250000, ft=107.000000 -+bc1f, c.eq.s out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+bc1f, c.eq.d out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+bc1f, c.eq.s out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+bc1f, c.eq.d out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+bc1f, c.eq.s out=1752.000000, fs=1752.000000, ft=-3478.500000 -+bc1f, c.eq.d out=1752.000000, fs=1752.000000, ft=-347856.500000 -+bc1f, c.eq.s out=0.015625, fs=0.015625, ft=356.500000 -+bc1f, c.eq.d out=0.015625, fs=0.015625, ft=356047.500000 -+bc1f, c.eq.s out=0.031250, fs=0.031250, ft=-1.000000 -+bc1f, c.eq.d out=0.031250, fs=0.031250, ft=-1.000000 -+bc1f, c.eq.s out=-248562.750000, fs=-248562.750000, ft=23.062500 -+bc1f, c.eq.d out=-248562.750000, fs=-248562.750000, ft=23.062500 -+bc1f, c.eq.s out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1f, c.eq.d out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1f, c.eq.s out=456.000000, fs=456.000000, ft=456.250000 -+bc1f, c.eq.d out=456.000000, fs=456.000000, ft=456.250000 -+bc1f, c.eq.s out=34.031250, fs=34.031250, ft=3.000000 -+bc1f, c.eq.d out=34.031250, fs=34.031250, ft=3.000000 -+bc1f, c.eq.s out=45786.750000, fs=45786.750000, ft=-1.000000 -+bc1f, c.eq.d out=45786.750000, fs=45786.750000, ft=-1.000000 -+bc1f, c.eq.s out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+bc1f, c.eq.d out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+bc1f, c.eq.s out=107.000000, fs=107.000000, ft=-7.000000 -+bc1f, c.eq.d out=107.000000, fs=107.000000, ft=-7.000000 -+bc1f, c.eq.s out=-45667.250000, fs=-45667.250000, ft=100.000000 -+bc1f, c.eq.d out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+bc1f, c.eq.s out=-7.000000, fs=-7.000000, ft=-5786.500000 -+bc1f, c.eq.d out=-7.000000, fs=-7.000000, ft=-5786.500000 -+bc1f, c.eq.s out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+bc1f, c.eq.d out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+bc1f, c.eq.s out=356047.500000, fs=356047.500000, ft=0.015625 -+bc1f, c.eq.d out=356047.500000, fs=356047.500000, ft=0.015625 -+bc1f, c.eq.s out=-1.000000, fs=-1.000000, ft=0.031250 -+bc1f, c.eq.d out=-1.000000, fs=-1.000000, ft=0.031250 -+bc1f, c.eq.s out=23.062500, fs=23.062500, ft=-248562.750000 -+bc1f, c.eq.d out=23.062500, fs=23.062500, ft=-248562.750000 -+--- BC1T --- if fs == ft then out = fs else out = fs + ft -+bc1t, c.eq.s out=-4578.500000, fs=0.000000, ft=-4578.500000 -+bc1t, c.eq.d out=-45786.500000, fs=0.000000, ft=-45786.500000 -+bc1t, c.eq.s out=456.250000, fs=456.250000, ft=456.250000 -+bc1t, c.eq.d out=456.250000, fs=456.250000, ft=456.250000 -+bc1t, c.eq.s out=37.031250, fs=3.000000, ft=34.031250 -+bc1t, c.eq.d out=37.031250, fs=3.000000, ft=34.031250 -+bc1t, c.eq.s out=4577.750000, fs=-1.000000, ft=4578.750000 -+bc1t, c.eq.d out=45785.750000, fs=-1.000000, ft=45786.750000 -+bc1t, c.eq.s out=1559.500000, fs=1384.500000, ft=175.000000 -+bc1t, c.eq.d out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+bc1t, c.eq.s out=99.750000, fs=-7.250000, ft=107.000000 -+bc1t, c.eq.d out=99.750000, fs=-7.250000, ft=107.000000 -+bc1t, c.eq.s out=999999552.000000, fs=1000000000.000000, ft=-456.250000 -+bc1t, c.eq.d out=999954332.750000, fs=1000000000.000000, ft=-45667.250000 -+bc1t, c.eq.s out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+bc1t, c.eq.d out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+bc1t, c.eq.s out=-1726.500000, fs=1752.000000, ft=-3478.500000 -+bc1t, c.eq.d out=-346104.500000, fs=1752.000000, ft=-347856.500000 -+bc1t, c.eq.s out=356.515625, fs=0.015625, ft=356.500000 -+bc1t, c.eq.d out=356047.515625, fs=0.015625, ft=356047.500000 -+bc1t, c.eq.s out=-0.968750, fs=0.031250, ft=-1.000000 -+bc1t, c.eq.d out=-0.968750, fs=0.031250, ft=-1.000000 -+bc1t, c.eq.s out=-248539.687500, fs=-248562.750000, ft=23.062500 -+bc1t, c.eq.d out=-248539.687500, fs=-248562.750000, ft=23.062500 -+bc1t, c.eq.s out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1t, c.eq.d out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1t, c.eq.s out=912.250000, fs=456.000000, ft=456.250000 -+bc1t, c.eq.d out=912.250000, fs=456.000000, ft=456.250000 -+bc1t, c.eq.s out=37.031250, fs=34.031250, ft=3.000000 -+bc1t, c.eq.d out=37.031250, fs=34.031250, ft=3.000000 -+bc1t, c.eq.s out=45785.750000, fs=45786.750000, ft=-1.000000 -+bc1t, c.eq.d out=45785.750000, fs=45786.750000, ft=-1.000000 -+bc1t, c.eq.s out=1753449.500000, fs=1752065.000000, ft=1384.500000 -+bc1t, c.eq.d out=1753449.500000, fs=1752065.000000, ft=1384.500000 -+bc1t, c.eq.s out=100.000000, fs=107.000000, ft=-7.000000 -+bc1t, c.eq.d out=100.000000, fs=107.000000, ft=-7.000000 -+bc1t, c.eq.s out=-45567.250000, fs=-45667.250000, ft=100.000000 -+bc1t, c.eq.d out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+bc1t, c.eq.s out=-5793.500000, fs=-7.000000, ft=-5786.500000 -+bc1t, c.eq.d out=-5793.500000, fs=-7.000000, ft=-5786.500000 -+bc1t, c.eq.s out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+bc1t, c.eq.d out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+bc1t, c.eq.s out=356047.500000, fs=356047.500000, ft=0.015625 -+bc1t, c.eq.d out=356047.515625, fs=356047.500000, ft=0.015625 -+bc1t, c.eq.s out=-0.968750, fs=-1.000000, ft=0.031250 -+bc1t, c.eq.d out=-0.968750, fs=-1.000000, ft=0.031250 -+bc1t, c.eq.s out=-248539.687500, fs=23.062500, ft=-248562.750000 -+bc1t, c.eq.d out=-248539.687500, fs=23.062500, ft=-248562.750000 -+--- BC1FL --- if fs == ft then out = ft else out = fs + ft -+bc1fl, c.eq.s out=-4578.500000, fs=0.000000, ft=-4578.500000 -+bc1fl, c.eq.d out=-45786.500000, fs=0.000000, ft=-45786.500000 -+bc1fl, c.eq.s out=456.250000, fs=456.250000, ft=456.250000 -+bc1fl, c.eq.d out=456.250000, fs=456.250000, ft=456.250000 -+bc1fl, c.eq.s out=37.031250, fs=3.000000, ft=34.031250 -+bc1fl, c.eq.d out=37.031250, fs=3.000000, ft=34.031250 -+bc1fl, c.eq.s out=4577.750000, fs=-1.000000, ft=4578.750000 -+bc1fl, c.eq.d out=45785.750000, fs=-1.000000, ft=45786.750000 -+bc1fl, c.eq.s out=1559.500000, fs=1384.500000, ft=175.000000 -+bc1fl, c.eq.d out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+bc1fl, c.eq.s out=99.750000, fs=-7.250000, ft=107.000000 -+bc1fl, c.eq.d out=99.750000, fs=-7.250000, ft=107.000000 -+bc1fl, c.eq.s out=999999552.000000, fs=1000000000.000000, ft=-456.250000 -+bc1fl, c.eq.d out=999954332.750000, fs=1000000000.000000, ft=-45667.250000 -+bc1fl, c.eq.s out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+bc1fl, c.eq.d out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+bc1fl, c.eq.s out=-1726.500000, fs=1752.000000, ft=-3478.500000 -+bc1fl, c.eq.d out=-346104.500000, fs=1752.000000, ft=-347856.500000 -+bc1fl, c.eq.s out=356.515625, fs=0.015625, ft=356.500000 -+bc1fl, c.eq.d out=356047.515625, fs=0.015625, ft=356047.500000 -+bc1fl, c.eq.s out=-0.968750, fs=0.031250, ft=-1.000000 -+bc1fl, c.eq.d out=-0.968750, fs=0.031250, ft=-1.000000 -+bc1fl, c.eq.s out=-248539.687500, fs=-248562.750000, ft=23.062500 -+bc1fl, c.eq.d out=-248539.687500, fs=-248562.750000, ft=23.062500 -+bc1fl, c.eq.s out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1fl, c.eq.d out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1fl, c.eq.s out=912.250000, fs=456.000000, ft=456.250000 -+bc1fl, c.eq.d out=912.250000, fs=456.000000, ft=456.250000 -+bc1fl, c.eq.s out=37.031250, fs=34.031250, ft=3.000000 -+bc1fl, c.eq.d out=37.031250, fs=34.031250, ft=3.000000 -+bc1fl, c.eq.s out=45785.750000, fs=45786.750000, ft=-1.000000 -+bc1fl, c.eq.d out=45785.750000, fs=45786.750000, ft=-1.000000 -+bc1fl, c.eq.s out=1753449.500000, fs=1752065.000000, ft=1384.500000 -+bc1fl, c.eq.d out=1753449.500000, fs=1752065.000000, ft=1384.500000 -+bc1fl, c.eq.s out=100.000000, fs=107.000000, ft=-7.000000 -+bc1fl, c.eq.d out=100.000000, fs=107.000000, ft=-7.000000 -+bc1fl, c.eq.s out=-45567.250000, fs=-45667.250000, ft=100.000000 -+bc1fl, c.eq.d out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+bc1fl, c.eq.s out=-5793.500000, fs=-7.000000, ft=-5786.500000 -+bc1fl, c.eq.d out=-5793.500000, fs=-7.000000, ft=-5786.500000 -+bc1fl, c.eq.s out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+bc1fl, c.eq.d out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+bc1fl, c.eq.s out=356047.500000, fs=356047.500000, ft=0.015625 -+bc1fl, c.eq.d out=356047.515625, fs=356047.500000, ft=0.015625 -+bc1fl, c.eq.s out=-0.968750, fs=-1.000000, ft=0.031250 -+bc1fl, c.eq.d out=-0.968750, fs=-1.000000, ft=0.031250 -+bc1fl, c.eq.s out=-248539.687500, fs=23.062500, ft=-248562.750000 -+bc1fl, c.eq.d out=-248539.687500, fs=23.062500, ft=-248562.750000 -+--- BC1TL --- if fs != ft then out = fs else out = fs + ft -+bc1tl, c.eq.s out=0.000000, fs=0.000000, ft=-4578.500000 -+bc1tl, c.eq.d out=0.000000, fs=0.000000, ft=-45786.500000 -+bc1tl, c.eq.s out=912.500000, fs=456.250000, ft=456.250000 -+bc1tl, c.eq.d out=912.500000, fs=456.250000, ft=456.250000 -+bc1tl, c.eq.s out=3.000000, fs=3.000000, ft=34.031250 -+bc1tl, c.eq.d out=3.000000, fs=3.000000, ft=34.031250 -+bc1tl, c.eq.s out=-1.000000, fs=-1.000000, ft=4578.750000 -+bc1tl, c.eq.d out=-1.000000, fs=-1.000000, ft=45786.750000 -+bc1tl, c.eq.s out=1384.500000, fs=1384.500000, ft=175.000000 -+bc1tl, c.eq.d out=1384.500000, fs=1384.500000, ft=1752065.000000 -+bc1tl, c.eq.s out=-7.250000, fs=-7.250000, ft=107.000000 -+bc1tl, c.eq.d out=-7.250000, fs=-7.250000, ft=107.000000 -+bc1tl, c.eq.s out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+bc1tl, c.eq.d out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+bc1tl, c.eq.s out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+bc1tl, c.eq.d out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+bc1tl, c.eq.s out=1752.000000, fs=1752.000000, ft=-3478.500000 -+bc1tl, c.eq.d out=1752.000000, fs=1752.000000, ft=-347856.500000 -+bc1tl, c.eq.s out=0.015625, fs=0.015625, ft=356.500000 -+bc1tl, c.eq.d out=0.015625, fs=0.015625, ft=356047.500000 -+bc1tl, c.eq.s out=0.031250, fs=0.031250, ft=-1.000000 -+bc1tl, c.eq.d out=0.031250, fs=0.031250, ft=-1.000000 -+bc1tl, c.eq.s out=-248562.750000, fs=-248562.750000, ft=23.062500 -+bc1tl, c.eq.d out=-248562.750000, fs=-248562.750000, ft=23.062500 -+bc1tl, c.eq.s out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1tl, c.eq.d out=-45786.500000, fs=-45786.500000, ft=0.000000 -+bc1tl, c.eq.s out=456.000000, fs=456.000000, ft=456.250000 -+bc1tl, c.eq.d out=456.000000, fs=456.000000, ft=456.250000 -+bc1tl, c.eq.s out=34.031250, fs=34.031250, ft=3.000000 -+bc1tl, c.eq.d out=34.031250, fs=34.031250, ft=3.000000 -+bc1tl, c.eq.s out=45786.750000, fs=45786.750000, ft=-1.000000 -+bc1tl, c.eq.d out=45786.750000, fs=45786.750000, ft=-1.000000 -+bc1tl, c.eq.s out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+bc1tl, c.eq.d out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+bc1tl, c.eq.s out=107.000000, fs=107.000000, ft=-7.000000 -+bc1tl, c.eq.d out=107.000000, fs=107.000000, ft=-7.000000 -+bc1tl, c.eq.s out=-45667.250000, fs=-45667.250000, ft=100.000000 -+bc1tl, c.eq.d out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+bc1tl, c.eq.s out=-7.000000, fs=-7.000000, ft=-5786.500000 -+bc1tl, c.eq.d out=-7.000000, fs=-7.000000, ft=-5786.500000 -+bc1tl, c.eq.s out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+bc1tl, c.eq.d out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+bc1tl, c.eq.s out=356047.500000, fs=356047.500000, ft=0.015625 -+bc1tl, c.eq.d out=356047.500000, fs=356047.500000, ft=0.015625 -+bc1tl, c.eq.s out=-1.000000, fs=-1.000000, ft=0.031250 -+bc1tl, c.eq.d out=-1.000000, fs=-1.000000, ft=0.031250 -+bc1tl, c.eq.s out=23.062500, fs=23.062500, ft=-248562.750000 -+bc1tl, c.eq.d out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.F.S/D --- if false then out = fs + ft else out = fs -+c.f.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.f.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.f.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.f.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.f.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.f.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.f.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.f.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.f.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.f.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.f.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.f.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.f.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.f.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.f.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.f.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.f.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.f.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.f.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.f.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.f.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.f.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.f.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.f.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.f.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.f.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.f.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.f.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.f.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.f.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.f.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.f.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.f.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.f.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.f.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.f.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.f.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.f.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.f.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.f.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.f.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.f.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.f.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.f.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.f.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.f.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.f.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.f.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.UN.S/D --- if unordered(fs, ft) then out = fs + ft else out = fs -+c.un.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.un.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.un.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.un.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.un.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.un.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.un.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.un.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.un.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.un.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.un.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.un.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.un.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.un.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.un.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.un.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.un.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.un.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.un.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.un.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.un.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.un.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.un.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.un.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.un.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.un.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.un.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.un.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.un.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.un.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.un.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.un.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.un.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.un.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.un.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.un.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.un.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.un.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.un.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.un.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.un.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.un.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.un.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.un.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.un.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.un.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.un.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.un.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.EQ.S/D --- if fs == ft then out = fs + ft else out = fs -+c.eq.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.eq.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.eq.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.eq.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.eq.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.eq.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.eq.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.eq.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.eq.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.eq.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.eq.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.eq.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.eq.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.eq.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.eq.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.eq.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.eq.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.eq.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.eq.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.eq.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.eq.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.eq.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.eq.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.eq.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.eq.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.eq.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.eq.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.eq.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.eq.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.eq.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.eq.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.eq.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.eq.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.eq.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.eq.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.eq.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.eq.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.eq.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.eq.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.eq.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.eq.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.eq.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.eq.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.eq.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.eq.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.eq.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.eq.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.eq.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.UEQ.S/D --- if (unordered(fs, ft) or (fs == ft)) then out = fs + ft else out = fs -+c.ueq.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.ueq.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.ueq.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ueq.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ueq.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.ueq.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.ueq.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.ueq.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.ueq.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.ueq.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.ueq.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.ueq.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.ueq.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.ueq.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.ueq.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.ueq.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.ueq.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.ueq.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.ueq.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.ueq.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.ueq.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ueq.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ueq.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.ueq.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.ueq.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ueq.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ueq.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.ueq.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.ueq.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ueq.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ueq.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ueq.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ueq.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ueq.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ueq.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ueq.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ueq.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.ueq.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.ueq.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ueq.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ueq.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.ueq.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.ueq.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ueq.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ueq.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.ueq.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.ueq.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.ueq.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.OLT.S/D --- if (ordered(fs, ft) or (fs < ft)) then out = fs + ft else out = fs -+c.olt.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.olt.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.olt.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.olt.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.olt.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.olt.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.olt.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.olt.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.olt.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.olt.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.olt.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.olt.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.olt.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.olt.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.olt.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.olt.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.olt.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.olt.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.olt.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.olt.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.olt.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.olt.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.olt.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.olt.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.olt.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.olt.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.olt.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.olt.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.olt.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.olt.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.olt.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.olt.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.olt.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.olt.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.olt.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.olt.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.olt.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.olt.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.olt.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.olt.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.olt.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.olt.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.olt.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.olt.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.olt.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.olt.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.olt.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.olt.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.ULT.S/D --- if (unordered(fs, ft) or (fs < ft)) then out = fs + ft else out = fs -+c.ult.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.ult.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.ult.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.ult.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.ult.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ult.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ult.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.ult.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.ult.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.ult.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.ult.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ult.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ult.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.ult.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.ult.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ult.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ult.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.ult.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.ult.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.ult.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.ult.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ult.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ult.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ult.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ult.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ult.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ult.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ult.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ult.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ult.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ult.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ult.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ult.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ult.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ult.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ult.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ult.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.ult.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.ult.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ult.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ult.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ult.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ult.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ult.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ult.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ult.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ult.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.ult.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.OLE.S/D --- if (ordered(fs, ft) or (fs <= ft)) then out = fs + ft else out = fs -+c.ole.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.ole.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.ole.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ole.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ole.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ole.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ole.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.ole.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.ole.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.ole.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.ole.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ole.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ole.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.ole.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.ole.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ole.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ole.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.ole.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.ole.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.ole.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.ole.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ole.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ole.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ole.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ole.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ole.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ole.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ole.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ole.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ole.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ole.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ole.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ole.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ole.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ole.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ole.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ole.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.ole.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.ole.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ole.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ole.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ole.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ole.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ole.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ole.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ole.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ole.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.ole.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.ULE.S/D --- if (unordered(fs, ft) or (fs <= ft)) then out = fs + ft else out = fs -+c.ule.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.ule.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.ule.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ule.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ule.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ule.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ule.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.ule.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.ule.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.ule.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.ule.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ule.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ule.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.ule.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.ule.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ule.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ule.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.ule.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.ule.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.ule.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.ule.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ule.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ule.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ule.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ule.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ule.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ule.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ule.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ule.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ule.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ule.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ule.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ule.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ule.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ule.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ule.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ule.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.ule.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.ule.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ule.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ule.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ule.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ule.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ule.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ule.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ule.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ule.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.ule.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.SF.S/D --- if signaling false then out = fs + ft else out = fs -+c.sf.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.sf.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.sf.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.sf.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.sf.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.sf.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.sf.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.sf.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.sf.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.sf.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.sf.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.sf.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.sf.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.sf.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.sf.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.sf.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.sf.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.sf.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.sf.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.sf.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.sf.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.sf.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.sf.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.sf.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.sf.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.sf.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.sf.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.sf.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.sf.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.sf.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.sf.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.sf.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.sf.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.sf.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.sf.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.sf.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.sf.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.sf.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.sf.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.sf.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.sf.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.sf.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.sf.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.sf.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.sf.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.sf.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.sf.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.sf.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.NGLE.S/D --- if not ((fs > ft) or (fs <= ft)) then out = fs + ft else out = fs -+c.ngle.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.ngle.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.ngle.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.ngle.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.ngle.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.ngle.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.ngle.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.ngle.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.ngle.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.ngle.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.ngle.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.ngle.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.ngle.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.ngle.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.ngle.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.ngle.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.ngle.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.ngle.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.ngle.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.ngle.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.ngle.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ngle.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ngle.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.ngle.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.ngle.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ngle.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ngle.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.ngle.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.ngle.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ngle.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ngle.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ngle.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ngle.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ngle.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ngle.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ngle.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ngle.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.ngle.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.ngle.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ngle.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ngle.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.ngle.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.ngle.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ngle.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ngle.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.ngle.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.ngle.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.ngle.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.SEQ.S/D --- if signaling equal then out = fs + ft else out = fs -+c.seq.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.seq.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.seq.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.seq.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.seq.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.seq.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.seq.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.seq.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.seq.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.seq.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.seq.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.seq.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.seq.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.seq.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.seq.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.seq.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.seq.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.seq.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.seq.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.seq.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.seq.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.seq.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.seq.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.seq.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.seq.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.seq.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.seq.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.seq.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.seq.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.seq.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.seq.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.seq.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.seq.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.seq.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.seq.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.seq.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.seq.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.seq.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.seq.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.seq.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.seq.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.seq.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.seq.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.seq.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.seq.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.seq.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.seq.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.seq.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.NGL.S/D --- if not ((fs > ft) or (fs < ft)) then out = fs + ft else out = fs -+c.ngl.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.ngl.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.ngl.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ngl.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ngl.s, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.ngl.d, bc1f out=3.000000, fs=3.000000, ft=34.031250 -+c.ngl.s, bc1f out=-1.000000, fs=-1.000000, ft=4578.750000 -+c.ngl.d, bc1f out=-1.000000, fs=-1.000000, ft=45786.750000 -+c.ngl.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.ngl.d, bc1f out=1384.500000, fs=1384.500000, ft=1752065.000000 -+c.ngl.s, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.ngl.d, bc1f out=-7.250000, fs=-7.250000, ft=107.000000 -+c.ngl.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.ngl.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.ngl.s, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.ngl.d, bc1f out=-5786.500000, fs=-5786.500000, ft=-7.250000 -+c.ngl.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.ngl.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.ngl.s, bc1f out=0.015625, fs=0.015625, ft=356.500000 -+c.ngl.d, bc1f out=0.015625, fs=0.015625, ft=356047.500000 -+c.ngl.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ngl.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ngl.s, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.ngl.d, bc1f out=-248562.750000, fs=-248562.750000, ft=23.062500 -+c.ngl.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ngl.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ngl.s, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.ngl.d, bc1f out=456.000000, fs=456.000000, ft=456.250000 -+c.ngl.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ngl.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ngl.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ngl.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ngl.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ngl.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ngl.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ngl.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ngl.s, bc1f out=-45667.250000, fs=-45667.250000, ft=100.000000 -+c.ngl.d, bc1f out=-45667.250000, fs=-45667.250000, ft=1000000000.000000 -+c.ngl.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ngl.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ngl.s, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.ngl.d, bc1f out=-347856.500000, fs=-347856.500000, ft=1752.000000 -+c.ngl.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ngl.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ngl.s, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.ngl.d, bc1f out=-1.000000, fs=-1.000000, ft=0.031250 -+c.ngl.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.ngl.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.LT.S/D --- if fs < ft then out = fs + ft else out = fs -+c.lt.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.lt.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.lt.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.lt.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.lt.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.lt.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.lt.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.lt.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.lt.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.lt.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.lt.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.lt.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.lt.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.lt.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.lt.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.lt.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.lt.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.lt.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.lt.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.lt.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.lt.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.lt.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.lt.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.lt.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.lt.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.lt.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.lt.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.lt.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.lt.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.lt.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.lt.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.lt.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.lt.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.lt.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.lt.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.lt.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.lt.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.lt.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.lt.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.lt.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.lt.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.lt.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.lt.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.lt.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.lt.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.lt.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.lt.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.lt.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.NGE.S/D --- if not (fs >= ft) then out = fs + ft else out = fs -+c.nge.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.nge.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.nge.s, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.nge.d, bc1f out=456.250000, fs=456.250000, ft=456.250000 -+c.nge.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.nge.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.nge.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.nge.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.nge.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.nge.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.nge.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.nge.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.nge.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.nge.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.nge.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.nge.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.nge.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.nge.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.nge.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.nge.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.nge.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.nge.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.nge.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.nge.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.nge.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.nge.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.nge.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.nge.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.nge.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.nge.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.nge.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.nge.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.nge.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.nge.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.nge.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.nge.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.nge.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.nge.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.nge.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.nge.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.nge.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.nge.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.nge.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.nge.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.nge.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.nge.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.nge.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.nge.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.LE.S/D --- if fs <= ft then out = fs + ft else out = fs -+c.le.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.le.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.le.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.le.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.le.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.le.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.le.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.le.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.le.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.le.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.le.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.le.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.le.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.le.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.le.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.le.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.le.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.le.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.le.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.le.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.le.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.le.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.le.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.le.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.le.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.le.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.le.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.le.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.le.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.le.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.le.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.le.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.le.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.le.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.le.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.le.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.le.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.le.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.le.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.le.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.le.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.le.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.le.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.le.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.le.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.le.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.le.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.le.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+--- C.NGT.S/D --- if not (fs > ft) then out = fs + ft else out = fs -+c.ngt.s, bc1f out=0.000000, fs=0.000000, ft=-4578.500000 -+c.ngt.d, bc1f out=0.000000, fs=0.000000, ft=-45786.500000 -+c.ngt.s, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ngt.d, bc1f out=912.500000, fs=456.250000, ft=456.250000 -+c.ngt.s, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ngt.d, bc1f out=37.031250, fs=3.000000, ft=34.031250 -+c.ngt.s, bc1f out=4577.750000, fs=-1.000000, ft=4578.750000 -+c.ngt.d, bc1f out=45785.750000, fs=-1.000000, ft=45786.750000 -+c.ngt.s, bc1f out=1384.500000, fs=1384.500000, ft=175.000000 -+c.ngt.d, bc1f out=1753449.500000, fs=1384.500000, ft=1752065.000000 -+c.ngt.s, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ngt.d, bc1f out=99.750000, fs=-7.250000, ft=107.000000 -+c.ngt.s, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-456.250000 -+c.ngt.d, bc1f out=1000000000.000000, fs=1000000000.000000, ft=-45667.250000 -+c.ngt.s, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ngt.d, bc1f out=-5793.750000, fs=-5786.500000, ft=-7.250000 -+c.ngt.s, bc1f out=1752.000000, fs=1752.000000, ft=-3478.500000 -+c.ngt.d, bc1f out=1752.000000, fs=1752.000000, ft=-347856.500000 -+c.ngt.s, bc1f out=356.515625, fs=0.015625, ft=356.500000 -+c.ngt.d, bc1f out=356047.515625, fs=0.015625, ft=356047.500000 -+c.ngt.s, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ngt.d, bc1f out=0.031250, fs=0.031250, ft=-1.000000 -+c.ngt.s, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ngt.d, bc1f out=-248539.687500, fs=-248562.750000, ft=23.062500 -+c.ngt.s, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ngt.d, bc1f out=-45786.500000, fs=-45786.500000, ft=0.000000 -+c.ngt.s, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ngt.d, bc1f out=912.250000, fs=456.000000, ft=456.250000 -+c.ngt.s, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ngt.d, bc1f out=34.031250, fs=34.031250, ft=3.000000 -+c.ngt.s, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ngt.d, bc1f out=45786.750000, fs=45786.750000, ft=-1.000000 -+c.ngt.s, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ngt.d, bc1f out=1752065.000000, fs=1752065.000000, ft=1384.500000 -+c.ngt.s, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ngt.d, bc1f out=107.000000, fs=107.000000, ft=-7.000000 -+c.ngt.s, bc1f out=-45567.250000, fs=-45667.250000, ft=100.000000 -+c.ngt.d, bc1f out=999954332.750000, fs=-45667.250000, ft=1000000000.000000 -+c.ngt.s, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ngt.d, bc1f out=-7.000000, fs=-7.000000, ft=-5786.500000 -+c.ngt.s, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ngt.d, bc1f out=-346104.500000, fs=-347856.500000, ft=1752.000000 -+c.ngt.s, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ngt.d, bc1f out=356047.500000, fs=356047.500000, ft=0.015625 -+c.ngt.s, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ngt.d, bc1f out=-0.968750, fs=-1.000000, ft=0.031250 -+c.ngt.s, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -+c.ngt.d, bc1f out=23.062500, fs=23.062500, ft=-248562.750000 -Index: none/tests/mips32/fpu_branches.vgtest -=================================================================== ---- none/tests/mips32/fpu_branches.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/fpu_branches.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prog: fpu_branches -+vgopts: -q -Index: none/tests/mips32/mips32_dsp.c -=================================================================== ---- none/tests/mips32/mips32_dsp.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/mips32_dsp.c (.../trunk) (revision 13981) -@@ -566,14 +566,14 @@ - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0x0555adec, t2, t3); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0x980b7cde, t4, t1); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0xf973437b, t6, t7); -- TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0x93474bde, t5, t3); -+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0x23c54b6e, t5, t3); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0x55555555, t2, t4); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0xc4dbfe20, t0, t8); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t4", 0x734680bc, t4, t4); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t1", 0x00354565, t0, t1); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t3", 0xbacabaca, t2, t3); -- TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0xdecadeca, t4, t1); -- TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0x00000286, t6, t7); -+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t4, $t1", 0xdba38ec9, t4, t1); -+ TESTDSPINST_RD_RT_DSPC("absq_s.ph $t6, $t7", 0x0b300286, t6, t7); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t5, $t3", 0xabababab, t5, t3); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t2, $t4", 0x00086755, t2, t4); - TESTDSPINST_RD_RT_DSPC("absq_s.ph $t0, $t8", 0x8f8f8f80, t0, t8); -@@ -612,14 +612,14 @@ - TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0x0555adec, t2, t3); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0x980b7cde, t4, t1); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0xf973437b, t6, t7); -- TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0x93474bde, t5, t3); -+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0x23c54b6e, t5, t3); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0x55555555, t2, t4); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0xc4dbfe20, t0, t8); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t4", 0x734680bc, t4, t4); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t1", 0x00354565, t0, t1); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t3", 0xbacabaca, t2, t3); -- TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0xdecadeca, t4, t1); -- TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0x00000286, t6, t7); -+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t4, $t1", 0xdba38ec9, t4, t1); -+ TESTDSPINST_RD_RT_DSPC("absq_s.w $t6, $t7", 0x0b300286, t6, t7); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t5, $t3", 0xabababab, t5, t3); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t2, $t4", 0x00086755, t2, t4); - TESTDSPINST_RD_RT_DSPC("absq_s.w $t0, $t8", 0x8f8f8f80, t0, t8); -@@ -656,11 +656,11 @@ - t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0xf973437b, 0x80000000, - t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xffffffff, -+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xfa3259ff, - t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff, - t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0000c420, 0x00000555, -+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0034c420, 0x00000555, - t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x00000004, 1073741824, - t2, t3, t4); -@@ -668,7 +668,7 @@ - t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t6, $t7, $t3", 0x76548000, 0x73468000, - t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0x80000000, 0x80000000, -+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t5, $t3, $t2", 0x80000000, 0x80620020, - t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t4, $t8", 0x00010001, 0xffffffff, - t2, t4, t8); -@@ -676,7 +676,7 @@ - t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t4, $t6, $t1", 0x0000c420, 0x00000555, - t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0x00000000, 0x00000000, -+ TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t0, $t1, $t2", 0x000a2300, 0x83bc1900, - t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq.ph $t2, $t3, $t4", 0x80000000, 0x80000000, - t2, t3, t4); -@@ -727,494 +727,504 @@ - - printf("-------- ADDQ_S.PH --------\n"); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00045fb2, 0x00000286, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x00002435, 0xffff3421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x07654cb8, 0x734680bc, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xf973437b, 0x80000000, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00000004, 1073741824, -- t2, t3, t4); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x80002435, 0x80003421, -- t4, t1, t5); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x76548000, 0x73468000, -- t6, t7, t3); -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00010001, 0xfa3259ff, -+ t0, t1, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x7fff7322, 0x77ff7fff, -+ t2, t3, t4); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x0034c420, 0x00000555, -+ t4, t1, t5); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x00000004, 1073741824, -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x80002435, 0x80003421, -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x76548000, 0x73468000, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x80000000, 0x80620020, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x00010001, 0xffffffff, -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x7fff7fff, 0x7fff7fff, -+ t2, t3, t4); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x0000c420, 0x00000555, -+ t4, t1, t5); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x000a2300, 0x83bc1900, -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x80000000, 0x80000000, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x80000000, 0x80000000, -- t2, t3, t4); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555, -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0xaaaaaaaa, 0x55555555, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x00000018, 0xffff2435, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xbabababa, 0xabababab, -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0xf0f0f0f0, 0xfc79b4d2, -+ t0, t1, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0xfbde3976, 0x00000000, -+ t2, t3, t4); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x23534870, 0x00354565, -+ t4, t1, t5); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x980b7cde, 0x00086755, -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x00000018, 0x8f8f8f8f, -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x92784656, 0xeeeeeeee, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xcacacaca, 0x1bdbdbdb, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xbacabaca, 0xdecadeca, -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x12fadeb4, 0x93474bde, -+ t0, t1, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x7c000790, 0xfc0007ff, -+ t2, t3, t4); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0xffffffff, 0xffffffff, -+ t4, t1, t5); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0xf2f4df1f, 0xcb4ab48f, -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x435f909a, 0xaf8f7e18, -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x2106ba5f, 0x87df4510, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x246a6376, 0xabf4e8e1, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x1046a1a3, 0xf4c0eeac, -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x638ca515, 0x006a54f2, -+ t0, t1, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0xf63e7a9d, 0x79f74493, -+ t2, t3, t4); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0xbd6845cd, 0x9c09e313, - t4, t1, t5); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x00000018, 0xffff2435, -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x234ba291, 0xbb64981c, - t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xbabababa, 0xabababab, -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x120934de, 0xad2c7601, - t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2, -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0xf5643908, 0xbaff3492, - t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xfbde3976, 0x00000000, -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x88503331, 0xd60e34a2, - t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x23534870, 0x00354565, -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0x7b5309ac, 0xc5487201, - t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0x980b7cde, 0x00086755, -- t0, t1, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f, -- t2, t3, t4); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x92784656, 0xeeeeeeee, -- t4, t1, t5); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb, -- t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0xbacabaca, 0xdecadeca, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x12fadeb4, 0x93474bde, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0x7c000790, 0xfc0007ff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xffffffff, 0xffffffff, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f, -- t0, t1, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18, -- t2, t3, t4); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t1, $t5", 0x2106ba5f, 0x87df4510, -- t4, t1, t5); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1, -- t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t2, $t4, $t8", 0x638ca515, 0x006a54f2, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.ph $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313, -- t4, t6, t1); - - printf("-------- ADDQ_S.W --------\n"); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00045fb2, 0x00000286, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x00002435, 0xffff3421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x07654cb8, 0x734680bc, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xf973437b, 0x80000000, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xfa3259ff, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0034c420, 0x00000555, -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00000004, 1073741824, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x80002435, 0x80003421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x76548000, 0x73468000, -- t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x80000000, 0x80000000, -- t5, t3, t2); -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x80000000, 0x80620020, -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x000a2300, 0x83bc1900, -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x80000000, 0x80000000, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x00000018, 0xffff2435, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xbabababa, 0xabababab, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0xfbde3976, 0x00000000, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0x23534870, 0x00354565, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0x980b7cde, 0x00086755, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x92784656, 0xeeeeeeee, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0xbacabaca, 0xdecadeca, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x12fadeb4, 0x93474bde, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0x7c000790, 0xfc0007ff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0xffffffff, 0xffffffff, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t1, $t5", 0x2106ba5f, 0x87df4510, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t2, $t4, $t8", 0x638ca515, 0x006a54f2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addq_s.w $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313, - t4, t6, t1); - - printf("-------- ADDSC --------\n"); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00045fb2, 0x00000286, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x00002435, 0xffff3421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x07654cb8, 0x734680bc, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0xf973437b, 0x80000000, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xfa3259ff, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0034c420, 0x00000555, -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00000004, 1073741824, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x80002435, 0x80003421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x76548000, 0x73468000, -- t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0x80000000, 0x80000000, -- t5, t3, t2); -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0x80000000, 0x80620020, -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x000a2300, 0x83bc1900, -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x80000000, 0x80000000, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x00000018, 0xffff2435, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0xbabababa, 0xabababab, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0xfbde3976, 0x00000000, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0x23534870, 0x00354565, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0x980b7cde, 0x00086755, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x92784656, 0xeeeeeeee, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0xbacabaca, 0xdecadeca, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x12fadeb4, 0x93474bde, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0x7c000790, 0xfc0007ff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0xffffffff, 0xffffffff, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t1, $t5", 0x2106ba5f, 0x87df4510, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t2, $t4, $t8", 0x638ca515, 0x006a54f2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addsc $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313, - t4, t6, t1); - - printf("-------- ADDU.QB --------\n"); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x00045fb2, 0x00000286, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x00002435, 0xffff3421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x07654cb8, 0x734680bc, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0xf973437b, 0x80000000, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x00010001, 0xfa3259ff, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x0034c420, 0x00000555, -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x00000004, 1073741824, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x80002435, 0x80003421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x76548000, 0x73468000, -- t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0x80000000, 0x80000000, -- t5, t3, t2); -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0x80000000, 0x80620020, -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x000a2300, 0x83bc1900, -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x80000000, 0x80000000, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x00000018, 0xffff2435, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0xbabababa, 0xabababab, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0xfbde3976, 0x00000000, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0x23534870, 0x00354565, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0x980b7cde, 0x00086755, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x92784656, 0xeeeeeeee, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0xbacabaca, 0xdecadeca, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x12fadeb4, 0x93474bde, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0x7c000790, 0xfc0007ff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0xffffffff, 0xffffffff, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t1, $t5", 0x2106ba5f, 0x87df4510, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t2, $t4, $t8", 0x638ca515, 0x006a54f2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu.qb $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313, - t4, t6, t1); - - printf("-------- ADDU_S.QB --------\n"); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t3, $t4", 0x00045fb2, 0x00000286, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t1, $t5", 0x00002435, 0xffff3421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t6, $t7, $t3", 0x07654cb8, 0x734680bc, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t5, $t3, $t2", 0xf973437b, 0x80000000, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t4, $t8", 0x00010001, 0xfa3259ff, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t6, $t1", 0x0034c420, 0x00000555, -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t3, $t4", 0x00000004, 1073741824, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t1, $t5", 0x80002435, 0x80003421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t6, $t7, $t3", 0x76548000, 0x73468000, -- t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t5, $t3, $t2", 0x80000000, 0x80000000, -- t5, t3, t2); -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t5, $t3, $t2", 0x80000000, 0x80620020, -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t1, $t2", 0x000a2300, 0x83bc1900, -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t3, $t4", 0x80000000, 0x80000000, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t6, $t7, $t3", 0x00000018, 0xffff2435, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t5, $t3, $t2", 0xbabababa, 0xabababab, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t8, $t0", 0xfbde3976, 0x00000000, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t6, $t1", 0x23534870, 0x00354565, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t1, $t2", 0x980b7cde, 0x00086755, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t1, $t5", 0x92784656, 0xeeeeeeee, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t5, $t3, $t2", 0xbacabaca, 0xdecadeca, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t4, $t8", 0x12fadeb4, 0x93474bde, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t8, $t0", 0x7c000790, 0xfc0007ff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t6, $t1", 0xffffffff, 0xffffffff, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t1, $t5", 0x2106ba5f, 0x87df4510, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t2, $t4, $t8", 0x638ca515, 0x006a54f2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addu_s.qb $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313, - t4, t6, t1); - - printf("-------- ADDWC --------\n"); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t3, $t4", 0x00045fb2, 0x00000286, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t1, $t5", 0x00002435, 0xffff3421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t6, $t7, $t3", 0x07654cb8, 0x734680bc, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t5, $t3, $t2", 0xf973437b, 0x80000000, -- t5, t3, t2); -- TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -- TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -- TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t4, $t8", 0x00010001, 0xfa3259ff, -+ t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t8, $t0", 0x7fff7322, 0x77ff7fff, -+ t0, t8, t0); -+ TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t6, $t1", 0x0034c420, 0x00000555, -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t3, $t4", 0x00000004, 1073741824, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t1, $t5", 0x80002435, 0x80003421, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t6, $t7, $t3", 0x76548000, 0x73468000, -- t6, t7, t3); -- TESTDSPINST_RD_RS_RT_DSPC("addwc $t5, $t3, $t2", 0x80000000, 0x80000000, -- t5, t3, t2); -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("addwc $t5, $t3, $t2", 0x80000000, 0x80620020, -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t4, $t8", 0x00010001, 0xffffffff, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t8, $t0", 0x7fff7fff, 0x7fff7fff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t6, $t1", 0x0000c420, 0x00000555, -- t4, t6, t1); -- TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t1, $t2", 0x00000000, 0x00000000, -- t0, t1, t2); -+ t4, t6, t1); -+ TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t1, $t2", 0x000a2300, 0x83bc1900, -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t3, $t4", 0x80000000, 0x80000000, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t1, $t5", 0xaaaaaaaa, 0x55555555, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t6, $t7, $t3", 0x00000018, 0xffff2435, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t5, $t3, $t2", 0xbabababa, 0xabababab, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t4, $t8", 0xf0f0f0f0, 0xfc79b4d2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t8, $t0", 0xfbde3976, 0x00000000, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t6, $t1", 0x23534870, 0x00354565, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t1, $t2", 0x980b7cde, 0x00086755, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t3, $t4", 0x00000018, 0x8f8f8f8f, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t1, $t5", 0x92784656, 0xeeeeeeee, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t6, $t7, $t3", 0xcacacaca, 0x1bdbdbdb, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t5, $t3, $t2", 0xbacabaca, 0xdecadeca, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t4, $t8", 0x12fadeb4, 0x93474bde, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t8, $t0", 0x7c000790, 0xfc0007ff, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t6, $t1", 0xffffffff, 0xffffffff, -- t4, t6, t1); -+ t4, t6, t1); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t1, $t2", 0xf2f4df1f, 0xcb4ab48f, -- t0, t1, t2); -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t3, $t4", 0x435f909a, 0xaf8f7e18, -- t2, t3, t4); -+ t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t1, $t5", 0x2106ba5f, 0x87df4510, -- t4, t1, t5); -+ t4, t1, t5); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t6, $t7, $t3", 0x246a6376, 0xabf4e8e1, -- t6, t7, t3); -+ t6, t7, t3); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t5, $t3, $t2", 0x1046a1a3, 0xf4c0eeac, -- t5, t3, t2); -+ t5, t3, t2); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t2, $t4, $t8", 0x638ca515, 0x006a54f2, -- t2, t4, t8); -+ t2, t4, t8); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t0, $t8, $t0", 0xf63e7a9d, 0x79f74493, -- t0, t8, t0); -+ t0, t8, t0); - TESTDSPINST_RD_RS_RT_DSPC("addwc $t4, $t6, $t1", 0xbd6845cd, 0x9c09e313, - t4, t6, t1); - - printf("-------- BITREV --------\n"); -- TESTDSPINST_RD_RT_NODSPC("bitrev $t0, $t1", 0x00000000, t0, t1); -+ TESTDSPINST_RD_RT_NODSPC("bitrev $t0, $t1", 0x09ba4800, t0, t1); - TESTDSPINST_RD_RT_NODSPC("bitrev $t2, $t3", 0x80003286, t2, t3); - TESTDSPINST_RD_RT_NODSPC("bitrev $t4, $t1", 0xfabc2435, t4, t1); - TESTDSPINST_RD_RT_NODSPC("bitrev $t6, $t7", 0x73468000, t6, t7); -- TESTDSPINST_RD_RT_NODSPC("bitrev $t5, $t3", 0x80000000, t5, t3); -- TESTDSPINST_RD_RT_NODSPC("bitrev $t2, $t4", 0xffffffff, t2, t4); -+ TESTDSPINST_RD_RT_NODSPC("bitrev $t5, $t3", 0x803c6900, t5, t3); -+ TESTDSPINST_RD_RT_NODSPC("bitrev $t2, $t4", 0xffad492f, t2, t4); - TESTDSPINST_RD_RT_NODSPC("bitrev $t0, $t8", 0xfff45fff, t0, t8); - TESTDSPINST_RD_RT_NODSPC("bitrev $t2, $t4", 0x00000555, t2, t4); -- TESTDSPINST_RD_RT_NODSPC("bitrev $t0, $t1", 0x00000000, t0, t1); -+ TESTDSPINST_RD_RT_NODSPC("bitrev $t0, $t1", 0x0098f308, t0, t1); - TESTDSPINST_RD_RT_NODSPC("bitrev $t2, $t3", 0x80000000, t2, t3); - TESTDSPINST_RD_RT_NODSPC("bitrev $t4, $t1", 0x55555555, t4, t1); - TESTDSPINST_RD_RT_NODSPC("bitrev $t6, $t7", 0xffff2435, t6, t7); -@@ -1360,7 +1370,7 @@ - TESTDSPINST_RS_RT_DSPC("cmp.le.ph $t4, $t6", 0xbd6845cd, 0x9c09e313, t4, t6); - - printf("-------- CMPGU.EQ.QB --------\n"); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t0, $t1, $t2", 0x00000000, -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t0, $t1, $t2", 0x00672300, - 0x00000000, t0, t1, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t2, $t3, $t4", 0x00045fb2, - 0x00000286, t2, t3, t4); -@@ -1371,11 +1381,11 @@ - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t5, $t3, $t2", 0xf973437b, - 0x80000000, t5, t3, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t2, $t4, $t8", 0x00010001, -- 0xffffffff, t2, t4, t8); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t0, $t8, $t0", 0x7fff7fff, -+ 0xf08b4631, t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t0, $t8, $t0", 0x5cbd891a, - 0x7fff7fff, t0, t8, t0); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t4, $t6, $t1", 0x0000c420, -- 0x00000555, t4, t6, t1); -+ 0x0ab64555, t4, t6, t1); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t2, $t3, $t4", 0x00000004, - 1073741824, t2, t3, t4); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t4, $t1, $t5", 0x80002435, -@@ -1382,7 +1392,7 @@ - 0x80003421, t4, t1, t5); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t6, $t7, $t3", 0x76548000, - 0x73468000, t6, t7, t3); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t5, $t3, $t2", 0x80000000, -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t5, $t3, $t2", 0x8007c560, - 0x80000000, t5, t3, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.eq.qb $t2, $t4, $t8", 0x00010001, - 0xffffffff, t2, t4, t8); -@@ -1440,7 +1450,7 @@ - 0x9c09e313, t4, t6, t1); - - printf("-------- CMPGU.LT.QB --------\n"); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t0, $t1, $t2", 0x00000000, -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t0, $t1, $t2", 0x00672300, - 0x00000000, t0, t1, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t2, $t3, $t4", 0x00045fb2, - 0x00000286, t2, t3, t4); -@@ -1451,11 +1461,11 @@ - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t5, $t3, $t2", 0xf973437b, - 0x80000000, t5, t3, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t2, $t4, $t8", 0x00010001, -- 0xffffffff, t2, t4, t8); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t0, $t8, $t0", 0x7fff7fff, -+ 0xf08b4631, t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t0, $t8, $t0", 0x5cbd891a, - 0x7fff7fff, t0, t8, t0); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t4, $t6, $t1", 0x0000c420, -- 0x00000555, t4, t6, t1); -+ 0x0ab64555, t4, t6, t1); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t2, $t3, $t4", 0x00000004, - 1073741824, t2, t3, t4); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t4, $t1, $t5", 0x80002435, -@@ -1462,7 +1472,7 @@ - 0x80003421, t4, t1, t5); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t6, $t7, $t3", 0x76548000, - 0x73468000, t6, t7, t3); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t5, $t3, $t2", 0x80000000, -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t5, $t3, $t2", 0x8007c560, - 0x80000000, t5, t3, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.lt.qb $t2, $t4, $t8", 0x00010001, - 0xffffffff, t2, t4, t8); -@@ -1520,7 +1530,7 @@ - 0x9c09e313, t4, t6, t1); - - printf("-------- CMPGU.LE.QB --------\n"); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t0, $t1, $t2", 0x00000000, -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t0, $t1, $t2", 0x00672300, - 0x00000000, t0, t1, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t2, $t3, $t4", 0x00045fb2, - 0x00000286, t2, t3, t4); -@@ -1531,11 +1541,11 @@ - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t5, $t3, $t2", 0xf973437b, - 0x80000000, t5, t3, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t2, $t4, $t8", 0x00010001, -- 0xffffffff, t2, t4, t8); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t0, $t8, $t0", 0x7fff7fff, -+ 0xf08b4631, t2, t4, t8); -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t0, $t8, $t0", 0x5cbd891a, - 0x7fff7fff, t0, t8, t0); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t4, $t6, $t1", 0x0000c420, -- 0x00000555, t4, t6, t1); -+ 0x0ab64555, t4, t6, t1); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t2, $t3, $t4", 0x00000004, - 1073741824, t2, t3, t4); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t4, $t1, $t5", 0x80002435, -@@ -1542,7 +1552,7 @@ - 0x80003421, t4, t1, t5); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t6, $t7, $t3", 0x76548000, - 0x73468000, t6, t7, t3); -- TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t5, $t3, $t2", 0x80000000, -+ TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t5, $t3, $t2", 0x8007c560, - 0x80000000, t5, t3, t2); - TESTDSPINST_RD_RS_RT_NODSPC("cmpgu.le.qb $t2, $t4, $t8", 0x00010001, - 0xffffffff, t2, t4, t8); -@@ -2740,6 +2750,16 @@ - t4, 0x1bdbdbdb, 19); - - printf("-------- EXTR_S.H --------\n"); -+ TESTDSPINST_EXT("extr_s.h $t4, $ac3, 0", "ac3", t4, 0x00000000, 0x00000000, -+ 0, 0); -+ TESTDSPINST_EXT("extr_s.h $t5, $ac0, 31", "ac0", t5, 0x7fffffff, 0xcbcdef01, -+ 31, 0); -+ TESTDSPINST_EXT("extr_s.h $t6, $ac1, 31", "ac1", t6, 0x3fffffff, 0x2bcdef01, -+ 31, 0); -+ TESTDSPINST_EXT("extr_s.h $t7, $ac2, 0", "ac2", t7, 0xff34bc6f, 0xffffffff, -+ 0, 0); -+ TESTDSPINST_EXT("extr_s.h $t8, $ac3, 1", "ac3", t8, 0x00000000, 0xfffffffe, -+ 1, 0); - TESTDSPINST_EXT("extr_s.h $t1, $ac0, 31", "ac0", t1, 0x80000000, 0x80000000, - 31, 0); - TESTDSPINST_EXT("extr_s.h $t2, $ac1, 17", "ac1", t2, (1<<31)+1, (1<<31)+2, -@@ -2758,8 +2778,6 @@ - 22, 0); - TESTDSPINST_EXT("extr_s.h $t0, $ac0, 9", "ac0", t0, 0x0000cdfe, 0x0fde3126, - 9, 0); -- TESTDSPINST_EXT("extr_s.h $t1, $ac1, 5", "ac1", t1, 0xaaaaaaaa, 0x55555555, -- 5, 0); - TESTDSPINST_EXT("extr_s.h $t2, $ac2, 14", "ac2", t2, 0x00000018, 0xffff2435, - 14, 0); - TESTDSPINST_EXT("extr_s.h $t1, $ac1, 20", "ac1", t1, 0xaaaaaaaa, 0x55555555, -@@ -2838,6 +2856,16 @@ - 0, 0); - - printf("-------- EXTR.W --------\n"); -+ TESTDSPINST_EXT("extr.w $t4, $ac3, 0", "ac3", t4, 0x00000000, 0x00000000, -+ 0, 0); -+ TESTDSPINST_EXT("extr.w $t5, $ac0, 31", "ac0", t5, 0x7fffffff, 0xcbcdef01, -+ 31, 0); -+ TESTDSPINST_EXT("extr.w $t6, $ac1, 31", "ac1", t6, 0x3fffffff, 0x2bcdef01, -+ 31, 0); -+ TESTDSPINST_EXT("extr.w $t7, $ac2, 0", "ac2", t7, 0xffffffff, 0xffffffff, -+ 0, 0); -+ TESTDSPINST_EXT("extr.w $t8, $ac3, 1", "ac3", t8, 0x00000000, 0xfffffffe, -+ 1, 0); - TESTDSPINST_EXT("extr.w $t1, $ac0, 31", "ac0", t1, 0x80000000, 0x80000000, - 31, 0); - TESTDSPINST_EXT("extr.w $t2, $ac1, 17", "ac1", t2, (1<<31)+1, (1<<31)+2, 17, -@@ -2856,8 +2884,6 @@ - 22, 0); - TESTDSPINST_EXT("extr.w $t0, $ac0, 9", "ac0", t0, 0x0000cdfe, 0xfd0e3126, - 9, 0); -- TESTDSPINST_EXT("extr.w $t1, $ac1, 5", "ac1", t1, 0xaaaaaaaa, 0x55555555, -- 5, 0); - TESTDSPINST_EXT("extr.w $t2, $ac2, 14", "ac2", t2, 0x00000018, 0xffff2435, - 14, 0); - TESTDSPINST_EXT("extr.w $t1, $ac1, 20", "ac1", t1, 0xaaaaaaaa, 0x55555555, -@@ -2936,17 +2962,27 @@ - 0, 0); - - printf("-------- EXTR_R.W --------\n"); -- TESTDSPINST_EXT("extr_r.w $t1, $ac0, 31", "ac0", t1, 0xffffffff, 0x80000000, -+ TESTDSPINST_EXT("extr_r.w $t4, $ac3, 0", "ac3", t4, 0x00000000, 0x00000000, -+ 0, 0); -+ TESTDSPINST_EXT("extr_r.w $t5, $ac0, 31", "ac0", t5, 0x7fffffff, 0xcbcdef01, - 31, 0); -- TESTDSPINST_EXT("extr_r.w $t3, $ac2, 4", "ac2", t3, 0x00000000, 0x00000006, -+ TESTDSPINST_EXT("extr_r.w $t6, $ac1, 31", "ac1", t6, 0x3fffffff, 0x2bcdef01, -+ 31, 0); -+ TESTDSPINST_EXT("extr_r.w $t7, $ac2, 0", "ac2", t7, 0x987b2fff, 0xffffffff, -+ 0, 0); -+ TESTDSPINST_EXT("extr_r.w $t8, $ac3, 1", "ac3", t8, 0x000cd320, 0xfffffffe, -+ 1, 0); -+ TESTDSPINST_EXT("extr_r.w $t1, $ac0, 31", "ac0", t1, 0xfff9b541, 0x80000000, -+ 31, 0); -+ TESTDSPINST_EXT("extr_r.w $t3, $ac2, 4", "ac2", t3, 0x0008b31c, 0x00000006, - 4, 0); -- TESTDSPINST_EXT("extr_r.w $t5, $ac0, 3", "ac0", t5, 0x00000000, 0x7fffffff, -+ TESTDSPINST_EXT("extr_r.w $t5, $ac0, 3", "ac0", t5, 0x0086b3ad, 0x7fffffff, - 3, 0); -- TESTDSPINST_EXT("extr_r.w $t6, $ac1, 8", "ac1", t6, 0x00000000, 0x00000001, -+ TESTDSPINST_EXT("extr_r.w $t6, $ac1, 8", "ac1", t6, 0x00097b51, 0x00000001, - 8, 0); -- TESTDSPINST_EXT("extr_r.w $t7, $ac2, 16", "ac2", t7, 0xffffffff, 0xffffffff, -+ TESTDSPINST_EXT("extr_r.w $t7, $ac2, 16", "ac2", t7, 0xfcde43ff, 0xffffffff, - 16, 0); -- TESTDSPINST_EXT("extr_r.w $t0, $ac0, 9", "ac0", t0, 0xffffffff, 0xfd0e3126, -+ TESTDSPINST_EXT("extr_r.w $t0, $ac0, 9", "ac0", t0, 0xffffca26, 0xfd0e3126, - 9, 0); - TESTDSPINST_EXT("extr_r.w $t1, $ac1, 5", "ac1", t1, 0x00000000, 0x55555555, - 5, 0); -@@ -2968,15 +3004,15 @@ - 19, 0); - TESTDSPINST_EXT("extr_r.w $t6, $ac2, 27", "ac2", t6, 0x00000000, 0x00000000, - 27, 0); -- TESTDSPINST_EXT("extr_r.w $t7, $ac3, 7", "ac3", t7, 0x00000000, 0x12349876, -+ TESTDSPINST_EXT("extr_r.w $t7, $ac3, 7", "ac3", t7, 0x02934b00, 0x12349876, - 7, 0); -- TESTDSPINST_EXT("extr_r.w $t8, $ac0, 11", "ac0", t8, 0x00000000, 0x00354565, -+ TESTDSPINST_EXT("extr_r.w $t8, $ac0, 11", "ac0", t8, 0x0008cad0, 0x00354565, - 11, 0); -- TESTDSPINST_EXT("extr_r.w $t0, $ac1, 26", "ac1", t0, 0xffffffff, 0x80006755, -+ TESTDSPINST_EXT("extr_r.w $t0, $ac1, 26", "ac1", t0, 0xf65c8fff, 0x80006755, - 26, 0); -- TESTDSPINST_EXT("extr_r.w $t1, $ac2, 15", "ac2", t1, 0xffffffff, 0x8f8f8f8f, -+ TESTDSPINST_EXT("extr_r.w $t1, $ac2, 15", "ac2", t1, 0xfffff001, 0x8f8f8f8f, - 15, 0); -- TESTDSPINST_EXT("extr_r.w $t2, $ac3, 2", "ac3", t2, 0xffffffff, 0xeeeeeeee, -+ TESTDSPINST_EXT("extr_r.w $t2, $ac3, 2", "ac3", t2, 0xbad69420, 0xeeeeeeee, - 2, 0); - TESTDSPINST_EXT("extr_r.w $t3, $ac0, 1", "ac0", t3, 0x00000000, 0x1bdbdbdb, - 1, 0); -@@ -3028,98 +3064,118 @@ - 0, 0); - - printf("-------- EXTR_RS.W --------\n"); -- TESTDSPINST_EXT("extr_rs.w $t3, $ac2, 4", "ac2", t3, 0x00000000, 0x00000006, -- 4, 0); -- TESTDSPINST_EXT("extr_rs.w $t5, $ac0, 3", "ac0", t5, 0x00000000, 0x7fffffff, -- 3, 0); -- TESTDSPINST_EXT("extr_rs.w $t6, $ac1, 8", "ac1", t6, 0x00000000, 0x00000001, -- 8, 0); -- TESTDSPINST_EXT("extr_rs.w $t7, $ac2, 16", "ac2", t7, 0xffffffff, 0xffffffff, -- 16, 0); -- TESTDSPINST_EXT("extr_rs.w $t8, $ac3, 22", "ac3", t8, 0xffffffff, 0xffffffff, -- 2, 0); -- TESTDSPINST_EXT("extr_rs.w $t0, $ac0, 9", "ac0", t0, 0xffffffff, 0xfd0e3126, -- 9, 0); -+ TESTDSPINST_EXT("extr_rs.w $t4, $ac3, 0", "ac3", t4, 0x00000000, 0x00000000, -+ 0, 0); -+ TESTDSPINST_EXT("extr_rs.w $t5, $ac0, 31", "ac0", t5, 0x7fffffff, 0xcbcdef01, -+ 31, 0); -+ TESTDSPINST_EXT("extr_rs.w $t6, $ac1, 31", "ac1", t6, 0x3fffffff, 0x2bcdef01, -+ 31, 0); -+ TESTDSPINST_EXT("extr_rs.w $t7, $ac2, 0", "ac2", t7, 0x987b2fff, 0xffffffff, -+ 0, 0); -+ TESTDSPINST_EXT("extr_rs.w $t8, $ac3, 1", "ac3", t8, 0x000cd320, 0xfffffffe, -+ 1, 0); -+ TESTDSPINST_EXT("extr_rs.w $t3, $ac2, 4", "ac2", t3, 0xfff9b541, 0x80000000, -+ 4, 0); -+ TESTDSPINST_EXT("extr_rs.w $t5, $ac0, 3", "ac0", t5, 0x0008b31c, 0x00000006, -+ 3, 0); -+ TESTDSPINST_EXT("extr_rs.w $t6, $ac1, 8", "ac1", t6, 0x0086b3ad, 0x7fffffff, -+ 8, 0); -+ TESTDSPINST_EXT("extr_rs.w $t7, $ac2, 16", "ac2", t7, 0x00097b51, 0x00000001, -+ 16, 0); -+ TESTDSPINST_EXT("extr_rs.w $t8, $ac3, 22", "ac3", t8, 0xfcde43ff, 0xffffffff, -+ 2, 0); -+ TESTDSPINST_EXT("extr_rs.w $t0, $ac0, 9", "ac0", t0, 0xffffca26, 0xfd0e3126, -+ 9, 0); - TESTDSPINST_EXT("extr_rs.w $t1, $ac1, 5", "ac1", t1, 0x00000000, 0x55555555, -- 5, 0); -+ 5, 0); - TESTDSPINST_EXT("extr_rs.w $t2, $ac2, 14", "ac2", t2, 0xffffffff, 0xffff2435, -- 14, 0); -+ 14, 0); - TESTDSPINST_EXT("extr_rs.w $t1, $ac1, 20", "ac1", t1, 0x00000000, 0x55555555, -- 0, 0); -+ 0, 0); - TESTDSPINST_EXT("extr_rs.w $t2, $ac2, 16", "ac2", t2, 0xffffffff, 0xffff2435, -- 16, 0); -+ 16, 0); - TESTDSPINST_EXT("extr_rs.w $t1, $ac1, 5", "ac1", t1, 0x00000000, 0x55555555, -- 5, 0); -+ 5, 0); - TESTDSPINST_EXT("extr_rs.w $t2, $ac2, 22", "ac2", t2, 0xffffffff, 0xffff2435, -- 22, 0); -+ 22, 0); - TESTDSPINST_EXT("extr_rs.w $t3, $ac3, 6", "ac3", t3, 0xffffffff, 0xabababab, -- 6, 0); -+ 6, 0); - TESTDSPINST_EXT("extr_rs.w $t4, $ac0, 13", "ac0", t4, 0xffffffff, 0xfc79b4d2, -- 13, 0); -+ 13, 0); - TESTDSPINST_EXT("extr_rs.w $t5, $ac1, 19", "ac1", t5, 0x00000000, 0x00000000, -- 19, 0); -+ 19, 0); - TESTDSPINST_EXT("extr_rs.w $t6, $ac2, 27", "ac2", t6, 0x00000000, 0x00000000, -- 27, 0); -- TESTDSPINST_EXT("extr_rs.w $t7, $ac3, 7", "ac3", t7, 0x00000000, 0x12349876, -- 7, 0); -- TESTDSPINST_EXT("extr_rs.w $t8, $ac0, 11", "ac0", t8, 0x00000000, 0x00354565, -- 11, 0); -- TESTDSPINST_EXT("extr_rs.w $t0, $ac1, 26", "ac1", t0, 0xffffffff, 0x80006755, -- 26, 0); -- TESTDSPINST_EXT("extr_rs.w $t1, $ac2, 15", "ac2", t1, 0xffffffff, 0x8f8f8f8f, -- 15, 0); -- TESTDSPINST_EXT("extr_rs.w $t2, $ac3, 2", "ac3", t2, 0xffffffff, 0xeeeeeeee, -- 2, 0); -+ 27, 0); -+ TESTDSPINST_EXT("extr_rs.w $t7, $ac3, 7", "ac3", t7, 0x02934b00, 0x12349876, -+ 7, 0); -+ TESTDSPINST_EXT("extr_rs.w $t8, $ac0, 11", "ac0", t8, 0x0008cad0, 0x00354565, -+ 11, 0); -+ TESTDSPINST_EXT("extr_rs.w $t0, $ac1, 26", "ac1", t0, 0xf65c8fff, 0x80006755, -+ 26, 0); -+ TESTDSPINST_EXT("extr_rs.w $t1, $ac2, 15", "ac2", t1, 0xfffff001, 0x8f8f8f8f, -+ 15, 0); -+ TESTDSPINST_EXT("extr_rs.w $t2, $ac3, 2", "ac3", t2, 0xbad69420, 0xeeeeeeee, -+ 2, 0); - TESTDSPINST_EXT("extr_rs.w $t3, $ac0, 1", "ac0", t3, 0x00000000, 0x1bdbdbdb, -- 1, 0); -+ 1, 0); - TESTDSPINST_EXT("extr_rs.w $t4, $ac1, 0", "ac1", t4, 0xffffffff, 0xdecadeca, -- 0, 0); -+ 0, 0); - TESTDSPINST_EXT("extr_rs.w $t5, $ac0, 3", "ac0", t5, 0x00000000, 0x5fc92974, -- 3, 0); -+ 3, 0); - TESTDSPINST_EXT("extr_rs.w $t6, $ac1, 8", "ac1", t6, 0x00000000, 0x7e08184e, -- 8, 0); -+ 8, 0); - TESTDSPINST_EXT("extr_rs.w $t7, $ac2, 16", "ac2", t7, 0x00000000, 0x71c8315f, -- 16, 0); -+ 16, 0); - TESTDSPINST_EXT("extr_rs.w $t8, $ac3, 22", "ac3", t8, 0xffffffff, 0x9493110e, -- 22, 0); -+ 22, 0); - TESTDSPINST_EXT("extr_rs.w $t0, $ac0, 9", "ac0", t0, 0xffffffff, 0xbb246228, -- 9, 0); -+ 9, 0); - TESTDSPINST_EXT("extr_rs.w $t1, $ac1, 5", "ac1", t1, 0x00000000, 0x339d8d88, -- 5, 0); -+ 5, 0); - TESTDSPINST_EXT("extr_rs.w $t2, $ac2, 14", "ac2", t2, 0x00000000, 0x70974249, -- 14, 0); -+ 14, 0); - TESTDSPINST_EXT("extr_rs.w $t1, $ac1, 20", "ac1", t1, 0xffffffff, 0x8a8d4e7d, -- 20, 0); -+ 20, 0); - TESTDSPINST_EXT("extr_rs.w $t2, $ac2, 16", "ac2", t2, 0xffffffff, 0xeb1b4335, -- 16, 0); -+ 16, 0); - TESTDSPINST_EXT("extr_rs.w $t1, $ac1, 5", "ac1", t1, 0x00000000, 0x0cd6b508, -- 5, 0); -+ 5, 0); - TESTDSPINST_EXT("extr_rs.w $t2, $ac2, 22", "ac2", t2, 0x00000000, 0x6731e282, -- 22, 0); -+ 22, 0); - TESTDSPINST_EXT("extr_rs.w $t3, $ac3, 6", "ac3", t3, 0xffffffff, 0xb6edf28f, -- 6, 0); -+ 6, 0); - TESTDSPINST_EXT("extr_rs.w $t4, $ac0, 13", "ac0", t4, 0x00000000, 0x4b4ec9ca, -- 13, 0); -+ 13, 0); - TESTDSPINST_EXT("extr_rs.w $t5, $ac1, 19", "ac1", t5, 0xffffffff, 0xc1037fa4, -- 19, 0); -+ 19, 0); - TESTDSPINST_EXT("extr_rs.w $t6, $ac2, 27", "ac2", t6, 0xffffffff, 0xcb4ab48f, -- 27, 0); -+ 27, 0); - TESTDSPINST_EXT("extr_rs.w $t7, $ac3, 7", "ac3", t7, 0xffffffff, 0xaf8f7e18, -- 7, 0); -+ 7, 0); - TESTDSPINST_EXT("extr_rs.w $t8, $ac0, 11", "ac0", t8, 0xffffffff, 0x87df4510, -- 11, 0); -+ 11, 0); - TESTDSPINST_EXT("extr_rs.w $t0, $ac1, 26", "ac1", t0, 0xffffffff, 0xabf4e8e1, -- 26, 0); -+ 26, 0); - TESTDSPINST_EXT("extr_rs.w $t1, $ac2, 15", "ac2", t1, 0xffffffff, 0xf4c0eeac, -- 15, 0); -+ 15, 0); - TESTDSPINST_EXT("extr_rs.w $t2, $ac3, 2", "ac3", t2, 0x00000000, 0x006a54f2, -- 2, 0); -+ 2, 0); - TESTDSPINST_EXT("extr_rs.w $t3, $ac0, 1", "ac0", t3, 0x00000000, 0x79f74493, -- 1, 0); -+ 1, 0); - TESTDSPINST_EXT("extr_rs.w $t4, $ac1, 0", "ac1", t4, 0xffffffff, 0x9c09e313, - 0, 0); - - printf("-------- EXTRV_S.H --------\n"); -+ TESTDSPINST_EXTV("extrv_s.h $t1, $ac1, $t3", "ac1", t1, 0x00000000, -+ 0x00000000, t3, 0xbababa00, 0); -+ TESTDSPINST_EXTV("extrv_s.h $t2, $ac2, $t4", "ac2", t2, 0x7fffffff, -+ 0xcbcdef01, t4, 0xfbde391f, 0); -+ TESTDSPINST_EXTV("extrv_s.h $t1, $ac1, $t7", "ac1", t1, 0x3fffffff, -+ 0x2bcdef01, t7, 0x5555551f, 0); -+ TESTDSPINST_EXTV("extrv_s.h $t2, $ac2, $t5", "ac2", t2, 0xffffffff, -+ 0xffffffff, t5, 0x0000cd00, 0); -+ TESTDSPINST_EXTV("extrv_s.h $t1, $ac1, $t2", "ac1", t1, 0x00000000, -+ 0xfffffffe, t2, 0x80000001, 0); - TESTDSPINST_EXTV("extrv_s.h $t2, $ac1, $t1", "ac1", t2, (1<<31)+1, (1<<31)+2, - t1, 0x12349876, 0); - TESTDSPINST_EXTV("extrv_s.h $t1, $ac0, $t0", "ac0", t1, 0x80000000, -@@ -3218,11 +3274,21 @@ - 0x9c09e313, t1, 0x6731e282, 0); - - printf("-------- EXTRV.W --------\n"); -- TESTDSPINST_EXTV("extrv.w $t1, $ac1, $t3", "ac1", t1, 0xaaaaaaaa, 0x55555555, -+ TESTDSPINST_EXTV("extrv.w $t1, $ac1, $t3", "ac1", t1, 0x00000000, 0x00000000, -+ t3, 0xbababa00, 0); -+ TESTDSPINST_EXTV("extrv.w $t2, $ac2, $t4", "ac2", t2, 0x7fffffff, 0xcbcdef01, -+ t4, 0xfbde391f, 0); -+ TESTDSPINST_EXTV("extrv.w $t1, $ac1, $t7", "ac1", t1, 0x3fffffff, 0x2bcdef01, -+ t7, 0x5555551f, 0); -+ TESTDSPINST_EXTV("extrv.w $t2, $ac2, $t5", "ac2", t2, 0xffffffff, 0xffffffff, -+ t5, 0x0000cd00, 0); -+ TESTDSPINST_EXTV("extrv.w $t1, $ac1, $t2", "ac1", t1, 0x00000000, 0xfffffffe, -+ t2, 0x80000001, 0); -+ TESTDSPINST_EXTV("extrv.w $t1, $ac1, $t3", "ac1", t1, 0xaaabad3a, 0x55555555, - t3, 0xbababa05, 0); - TESTDSPINST_EXTV("extrv.w $t2, $ac2, $t4", "ac2", t2, 0x00000018, 0xffff2435, - t4, 0xfbde390e, 0); -- TESTDSPINST_EXTV("extrv.w $t1, $ac1, $t7", "ac1", t1, 0xaaaaaaaa, 0x55555555, -+ TESTDSPINST_EXTV("extrv.w $t1, $ac1, $t7", "ac1", t1, 0xaaaaa221, 0x55555555, - t7, 0x55555514, 0); - TESTDSPINST_EXTV("extrv.w $t2, $ac2, $t5", "ac2", t2, 0x00000018, 0xffff2435, - t5, 0x0000cd10, 0); -@@ -3317,6 +3383,16 @@ - - printf("-------- EXTRV_R.W --------\n"); - TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t3", "ac1", t1, 0x00000000, -+ 0x00000000, t3, 0xbababa00, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t4", "ac2", t2, 0x7fffffff, -+ 0xcbcdef01, t4, 0xfbde391f, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t7", "ac1", t1, 0x3fffffff, -+ 0x2bcdef01, t7, 0x5555551f, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t5", "ac2", t2, 0xffffffff, -+ 0xffffffff, t5, 0x0000cd00, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t2", "ac1", t1, 0x00000000, -+ 0xfffffffe, t2, 0x80000001, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t3", "ac1", t1, 0x00000000, - 0x55555555, t3, 0xbababa05, 0); - TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t4", "ac2", t2, 0xffffffff, - 0xffff2435, t4, 0xfbde390e, 0); -@@ -3364,53 +3440,65 @@ - 0x1bdbdbdb, t1, 0xbacabaca, 0); - TESTDSPINST_EXTV("extrv_r.w $t4, $ac1, $t4", "ac1", t4, 0xffffffff, - 0xdecadeca, t4, 0x1bdbdbdb, 0); -- TESTDSPINST_EXTV("extrv_r.w $t5, $ac0, $t8", "ac0", t5, 0x00000000, -- 0x5fc92974, t8, 0xffff2435, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t5, $ac0, $t8", "ac0", t5, 0xf0f0f0f0, -+ 0x5fc92974, t8, 0xffff2435, 0); - TESTDSPINST_EXTV("extrv_r.w $t6, $ac1, $t0", "ac1", t6, 0x00000000, -- 0x7e08184e, t0, 0x55555555, 0); -- TESTDSPINST_EXTV("extrv_r.w $t7, $ac2, $t1", "ac2", t7, 0x00000000, -- 0x71c8315f, t1, 0xffff2435, 0); -- TESTDSPINST_EXTV("extrv_r.w $t8, $ac3, $t2", "ac3", t8, 0xffffffff, -- 0x9493110e, t2, 0x55555555, 0); -- TESTDSPINST_EXTV("extrv_r.w $t0, $ac0, $t3", "ac0", t0, 0xffffffff, -- 0xbb246228, t3, 0xffff2435, 0); -- TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t4", "ac1", t1, 0x00000000, -- 0x339d8d88, t4, 0xabababab, 0); -- TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t5", "ac2", t2, 0x00000000, -- 0x70974249, t5, 0xfc79b4d2, 0); -- TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t6", "ac1", t1, 0xffffffff, -- 0x8a8d4e7d, t6, 0x00000000, 0); -- TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t7", "ac2", t2, 0xffffffff, -- 0xeb1b4335, t7, 0x00000000, 0); -- TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t8", "ac1", t1, 0x00000000, -- 0x0cd6b508, t8, 0x12349876, 0); -+ 0x7e08184e, t0, 0x55555555, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t7, $ac2, $t1", "ac2", t7, 0xfbde3976, -+ 0x71c8315f, t1, 0xffff2435, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t8, $ac3, $t2", "ac3", t8, 0x0bed7654, -+ 0x9493110e, t2, 0x55555555, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t0, $ac0, $t3", "ac0", t0, 0x23534870, -+ 0xbb246228, t3, 0xffff2435, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t4", "ac1", t1, 0x980b7cde, -+ 0x339d8d88, t4, 0xabababab, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t5", "ac2", t2, 0x00000018, -+ 0x70974249, t5, 0xfc79b4d2, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t6", "ac1", t1, 0x92784656, -+ 0x8a8d4e7d, t6, 0x00000000, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t7", "ac2", t2, 0xcacacaca, -+ 0xeb1b4335, t7, 0x00000000, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t1, $ac1, $t8", "ac1", t1, 0xbacabaca, -+ 0x0cd6b508, t8, 0x12349876, 0); - TESTDSPINST_EXTV("extrv_r.w $t2, $ac2, $t0", "ac2", t2, 0x00000000, -- 0x6731e282, t0, 0x00354565, 0); -- TESTDSPINST_EXTV("extrv_r.w $t3, $ac3, $t1", "ac3", t3, 0xffffffff, -- 0xb6edf28f, t1, 0x00086755, 0); -+ 0x6731e282, t0, 0x00354565, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t3, $ac3, $t1", "ac3", t3, 0x00000000, -+ 0xb6edf28f, t1, 0x00086755, 0); - TESTDSPINST_EXTV("extrv_r.w $t4, $ac0, $t2", "ac0", t4, 0x00000000, -- 0x4b4ec9ca, t2, 0x8f8f8f8f, 0); -+ 0x4b4ec9ca, t2, 0x8f8f8f8f, 0); - TESTDSPINST_EXTV("extrv_r.w $t5, $ac1, $t3", "ac1", t5, 0xffffffff, -- 0xc1037fa4, t3, 0xeeeeeeee, 0); -+ 0xc1037fa4, t3, 0xeeeeeeee, 0); - TESTDSPINST_EXTV("extrv_r.w $t6, $ac2, $t3", "ac2", t6, 0xffffffff, -- 0xcb4ab48f, t3, 0x1bdbdbdb, 0); -- TESTDSPINST_EXTV("extrv_r.w $t7, $ac3, $t4", "ac3", t7, 0xffffffff, -- 0xaf8f7e18, t4, 0xbb246228, 0); -- TESTDSPINST_EXTV("extrv_r.w $t8, $ac0, $t5", "ac0", t8, 0xffffffff, -- 0x87df4510, t5, 0x339d8d88, 0); -+ 0xcb4ab48f, t3, 0x1bdbdbdb, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t7, $ac3, $t4", "ac3", t7, 0x00000000, -+ 0xaf8f7e18, t4, 0xbb246228, 0); -+ TESTDSPINST_EXTV("extrv_r.w $t8, $ac0, $t5", "ac0", t8, 0x00000000, -+ 0x87df4510, t5, 0x339d8d88, 0); - TESTDSPINST_EXTV("extrv_r.w $t0, $ac1, $t6", "ac1", t0, 0xffffffff, -- 0xabf4e8e1, t6, 0x70974249, 0); -+ 0xabf4e8e1, t6, 0x70974249, 0); - TESTDSPINST_EXTV("extrv_r.w $t1, $ac2, $t7", "ac2", t1, 0xffffffff, -- 0xf4c0eeac, t7, 0x8a8d4e7d, 0); -+ 0xf4c0eeac, t7, 0x8a8d4e7d, 0); - TESTDSPINST_EXTV("extrv_r.w $t2, $ac3, $t8", "ac3", t2, 0x00000000, -- 0x006a54f2, t8, 0xeb1b4335, 0); -+ 0x006a54f2, t8, 0xeb1b4335, 0); - TESTDSPINST_EXTV("extrv_r.w $t3, $ac0, $t0", "ac0", t3, 0x00000000, -- 0x79f74493, t0, 0x0cd6b508, 0); -+ 0x79f74493, t0, 0x0cd6b508, 0); - TESTDSPINST_EXTV("extrv_r.w $t4, $ac1, $t1", "ac1", t4, 0xffffffff, - 0x9c09e313, t1, 0x6731e282, 0); - - printf("-------- EXTRV_RS.W --------\n"); - TESTDSPINST_EXTV("extrv_rs.w $t1, $ac1, $t3", "ac1", t1, 0x00000000, -+ 0x00000000, t3, 0xbababa00, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t1, $ac1, $t3", "ac1", t1, 0x987b2fff, -+ 0xffffffff, t3, 0xbababa00, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t2, $ac2, $t4", "ac2", t2, 0x7fffffff, -+ 0xcbcdef01, t4, 0xfbde391f, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t1, $ac1, $t7", "ac1", t1, 0x3fffffff, -+ 0x2bcdef01, t7, 0x5555551f, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t2, $ac2, $t5", "ac2", t2, 0xffffffff, -+ 0xffffffff, t5, 0x0000cd00, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t1, $ac1, $t2", "ac1", t1, 0x00000000, -+ 0xfffffffe, t2, 0x80000001, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t1, $ac1, $t3", "ac1", t1, 0x00000000, - 0x55555555, t3, 0xbababa05, 0); - TESTDSPINST_EXTV("extrv_rs.w $t2, $ac2, $t4", "ac2", t2, 0xffffffff, - 0xffff2435, t4, 0xfbde390e, 0); -@@ -3438,25 +3526,25 @@ - 0xffffffff, t9, 0xffff2435, 0); - TESTDSPINST_EXTV("extrv_rs.w $t4, $ac0, $t3", "ac0", t4, 0xffffffff, - 0xfc79b4d2, t3, 0x12349876, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t5, $ac1, $t4", "ac1", t5, 0x00000000, -- 0x00000000, t4, 0x00354565, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t5, $ac1, $t4", "ac1", t5, 0xf0f0f0f0, -+ 0x00000000, t4, 0x00354565, 0); - TESTDSPINST_EXTV("extrv_rs.w $t6, $ac2, $t5", "ac2", t6, 0x00000000, -- 0x00000000, t5, 0x00086755, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t7, $ac3, $t6", "ac3", t7, 0x00000000, -- 0x12349876, t6, 0x00000018, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t8, $ac0, $t7", "ac0", t8, 0x00000000, -- 0x00354565, t7, 0x23534870, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t0, $ac1, $t8", "ac1", t0, 0x00000000, -- 0x00086755, t8, 0x92784656, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t1, $ac2, $t9", "ac2", t1, 0xffffffff, -- 0x8f8f8f8f, t9, 0xeeeeeeee, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t2, $ac3, $t1", "ac3", t2, 0xffffffff, -- 0xeeeeeeee, t1, 0xcacacaca, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t3, $ac0, $t1", "ac0", t3, 0x00000000, -- 0x1bdbdbdb, t1, 0xbacabaca, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t4, $ac1, $t4", "ac1", t4, 0xffffffff, -- 0xdecadeca, t4, 0x1bdbdbdb, 0); -- TESTDSPINST_EXTV("extrv_rs.w $t5, $ac0, $t8", "ac0", t5, 0x00000000, -+ 0x00000000, t5, 0x00086755, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t7, $ac3, $t6", "ac3", t7, 0xfbde3976, -+ 0x12349876, t6, 0x00000018, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t8, $ac0, $t7", "ac0", t8, 0x0bed7654, -+ 0x00354565, t7, 0x23534870, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t0, $ac1, $t8", "ac1", t0, 0x23534870, -+ 0x00086755, t8, 0x92784656, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t1, $ac2, $t9", "ac2", t1, 0x980b7cde, -+ 0x8f8f8f8f, t9, 0xeeeeeeee, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t2, $ac3, $t1", "ac3", t2, 0x00000018, -+ 0xeeeeeeee, t1, 0xcacacaca, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t3, $ac0, $t1", "ac0", t3, 0x92784656, -+ 0x1bdbdbdb, t1, 0xbacabaca, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t4, $ac1, $t4", "ac1", t4, 0xcacacaca, -+ 0xdecadeca, t4, 0x1bdbdbdb, 0); -+ TESTDSPINST_EXTV("extrv_rs.w $t5, $ac0, $t8", "ac0", t5, 0xbacabaca, - 0x5fc92974, t8, 0xffff2435, 0); - TESTDSPINST_EXTV("extrv_rs.w $t6, $ac1, $t0", "ac1", t6, 0x00000000, - 0x7e08184e, t0, 0x55555555, 0); -@@ -7165,6 +7253,16 @@ - printf("-------- SUBQ_S.PH --------\n"); - TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000, - t0, t1, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t2, $t3, $t4", 0x00020002, 0x00010001, -+ t2, t3, t4); -+ TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t4, $t1, $t5", 0x0002fffe, 0x0001ffff, -+ t4, t1, t5); -+ TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t6, $t7, $t3", 0x7fff8000, 0x7fff8000, -+ t6, t7, t3); -+ TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t5, $t3, $t2", 0x7fff8000, 0x7ffe8001, -+ t5, t3, t2); -+ TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t0, $t1, $t2", 0x00000000, 0x00000000, -+ t0, t1, t2); - TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t2, $t3, $t4", 0x045fb232, 0x00028632, - t2, t3, t4); - TESTDSPINST_RD_RS_RT_DSPC("subq_s.ph $t4, $t1, $t5", 0xfabc3435, 0xfabc3421, -Index: none/tests/mips32/mips32_dsp.stdout.exp -=================================================================== ---- none/tests/mips32/mips32_dsp.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/mips32_dsp.stdout.exp (.../trunk) (revision 13981) -@@ -1,4069 +0,0 @@ ---------- ABSQ_S.PH -------- --absq_s.ph $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0 --absq_s.ph $t2, $t3 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 --absq_s.ph $t4, $t1 :: rd 0x05442435 rt 0xfabc2435 DSPControl 0x0 --absq_s.ph $t6, $t7 :: rd 0x73467fff rt 0x73468000 DSPControl 0x100000 --absq_s.ph $t5, $t3 :: rd 0x7fff0000 rt 0x80000000 DSPControl 0x100000 --absq_s.ph $t2, $t4 :: rd 0x00010001 rt 0xffffffff DSPControl 0x0 --absq_s.ph $t0, $t8 :: rd 0x000c5fff rt 0xfff45fff DSPControl 0x0 --absq_s.ph $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0 --absq_s.ph $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0 --absq_s.ph $t2, $t3 :: rd 0x05555214 rt 0x0555adec DSPControl 0x0 --absq_s.ph $t4, $t1 :: rd 0x67f57cde rt 0x980b7cde DSPControl 0x0 --absq_s.ph $t6, $t7 :: rd 0x068d437b rt 0xf973437b DSPControl 0x0 --absq_s.ph $t5, $t3 :: rd 0x6cb94bde rt 0x93474bde DSPControl 0x0 --absq_s.ph $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 --absq_s.ph $t0, $t8 :: rd 0x3b2501e0 rt 0xc4dbfe20 DSPControl 0x0 --absq_s.ph $t4, $t4 :: rd 0x73467f44 rt 0x734680bc DSPControl 0x0 --absq_s.ph $t0, $t1 :: rd 0x00354565 rt 0x00354565 DSPControl 0x0 --absq_s.ph $t2, $t3 :: rd 0x45364536 rt 0xbacabaca DSPControl 0x0 --absq_s.ph $t4, $t1 :: rd 0x21362136 rt 0xdecadeca DSPControl 0x0 --absq_s.ph $t6, $t7 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 --absq_s.ph $t5, $t3 :: rd 0x54555455 rt 0xabababab DSPControl 0x0 --absq_s.ph $t2, $t4 :: rd 0x00086755 rt 0x00086755 DSPControl 0x0 --absq_s.ph $t0, $t8 :: rd 0x70717080 rt 0x8f8f8f80 DSPControl 0x0 --absq_s.ph $t4, $t4 :: rd 0x11121112 rt 0xeeeeeeee DSPControl 0x0 --absq_s.ph $t0, $t1 :: rd 0x1bdb2425 rt 0x1bdbdbdb DSPControl 0x0 --absq_s.ph $t2, $t3 :: rd 0x21362136 rt 0xdecadeca DSPControl 0x0 --absq_s.ph $t4, $t1 :: rd 0x6cb94bde rt 0x93474bde DSPControl 0x0 --absq_s.ph $t6, $t7 :: rd 0x05415406 rt 0xfabfabfa DSPControl 0x0 --absq_s.ph $t5, $t3 :: rd 0x083b3571 rt 0x083b3571 DSPControl 0x0 --absq_s.ph $t2, $t4 :: rd 0x468c3941 rt 0xb9743941 DSPControl 0x0 --absq_s.ph $t0, $t8 :: rd 0x438006dc rt 0xbc80f924 DSPControl 0x0 --absq_s.ph $t4, $t4 :: rd 0x33c4201c rt 0xcc3c201c DSPControl 0x0 --absq_s.ph $t0, $t1 :: rd 0x1eba0772 rt 0x1ebaf88e DSPControl 0x0 --absq_s.ph $t2, $t3 :: rd 0x722d5e20 rt 0x722d5e20 DSPControl 0x0 --absq_s.ph $t4, $t1 :: rd 0x5e2a086f rt 0xa1d6f791 DSPControl 0x0 --absq_s.ph $t6, $t7 :: rd 0x7b114119 rt 0x7b11bee7 DSPControl 0x0 --absq_s.ph $t5, $t3 :: rd 0x5a9d1488 rt 0xa5631488 DSPControl 0x0 --absq_s.ph $t2, $t4 :: rd 0x4ef5339b rt 0xb10bcc65 DSPControl 0x0 --absq_s.ph $t0, $t8 :: rd 0x73f36036 rt 0x73f39fca DSPControl 0x0 --absq_s.ph $t4, $t4 :: rd 0x7fff7fff rt 0x80008000 DSPControl 0x100000 --absq_s.ph $t0, $t1 :: rd 0x00015ba0 rt 0xffffa460 DSPControl 0x0 --absq_s.ph $t2, $t3 :: rd 0x075c70fa rt 0x075c70fa DSPControl 0x0 --absq_s.ph $t4, $t1 :: rd 0x0001000d rt 0xfffffff3 DSPControl 0x0 --absq_s.ph $t6, $t7 :: rd 0x000100ed rt 0xffffff13 DSPControl 0x0 ---------- ABSQ_S.W -------- --absq_s.w $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0 --absq_s.w $t2, $t3 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 --absq_s.w $t4, $t1 :: rd 0x0543dbcb rt 0xfabc2435 DSPControl 0x0 --absq_s.w $t6, $t7 :: rd 0x73468000 rt 0x73468000 DSPControl 0x0 --absq_s.w $t5, $t3 :: rd 0x7fffffff rt 0x80000000 DSPControl 0x100000 --absq_s.w $t2, $t4 :: rd 0x00000001 rt 0xffffffff DSPControl 0x0 --absq_s.w $t0, $t8 :: rd 0x000ba001 rt 0xfff45fff DSPControl 0x0 --absq_s.w $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0 --absq_s.w $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0 --absq_s.w $t2, $t3 :: rd 0x0555adec rt 0x0555adec DSPControl 0x0 --absq_s.w $t4, $t1 :: rd 0x67f48322 rt 0x980b7cde DSPControl 0x0 --absq_s.w $t6, $t7 :: rd 0x068cbc85 rt 0xf973437b DSPControl 0x0 --absq_s.w $t5, $t3 :: rd 0x6cb8b422 rt 0x93474bde DSPControl 0x0 --absq_s.w $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 --absq_s.w $t0, $t8 :: rd 0x3b2401e0 rt 0xc4dbfe20 DSPControl 0x0 --absq_s.w $t4, $t4 :: rd 0x734680bc rt 0x734680bc DSPControl 0x0 --absq_s.w $t0, $t1 :: rd 0x00354565 rt 0x00354565 DSPControl 0x0 --absq_s.w $t2, $t3 :: rd 0x45354536 rt 0xbacabaca DSPControl 0x0 --absq_s.w $t4, $t1 :: rd 0x21352136 rt 0xdecadeca DSPControl 0x0 --absq_s.w $t6, $t7 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 --absq_s.w $t5, $t3 :: rd 0x54545455 rt 0xabababab DSPControl 0x0 --absq_s.w $t2, $t4 :: rd 0x00086755 rt 0x00086755 DSPControl 0x0 --absq_s.w $t0, $t8 :: rd 0x70707080 rt 0x8f8f8f80 DSPControl 0x0 --absq_s.w $t4, $t4 :: rd 0x11111112 rt 0xeeeeeeee DSPControl 0x0 --absq_s.w $t0, $t1 :: rd 0x1bdbdbdb rt 0x1bdbdbdb DSPControl 0x0 --absq_s.w $t2, $t3 :: rd 0x21352136 rt 0xdecadeca DSPControl 0x0 --absq_s.w $t4, $t1 :: rd 0x6cb8b422 rt 0x93474bde DSPControl 0x0 --absq_s.w $t6, $t7 :: rd 0x05405406 rt 0xfabfabfa DSPControl 0x0 --absq_s.w $t5, $t3 :: rd 0x083b3571 rt 0x083b3571 DSPControl 0x0 --absq_s.w $t2, $t4 :: rd 0x468bc6bf rt 0xb9743941 DSPControl 0x0 --absq_s.w $t0, $t8 :: rd 0x437f06dc rt 0xbc80f924 DSPControl 0x0 --absq_s.w $t4, $t4 :: rd 0x33c3dfe4 rt 0xcc3c201c DSPControl 0x0 --absq_s.w $t0, $t1 :: rd 0x1ebaf88e rt 0x1ebaf88e DSPControl 0x0 --absq_s.w $t2, $t3 :: rd 0x722d5e20 rt 0x722d5e20 DSPControl 0x0 --absq_s.w $t4, $t1 :: rd 0x5e29086f rt 0xa1d6f791 DSPControl 0x0 --absq_s.w $t6, $t7 :: rd 0x7b11bee7 rt 0x7b11bee7 DSPControl 0x0 --absq_s.w $t5, $t3 :: rd 0x5a9ceb78 rt 0xa5631488 DSPControl 0x0 --absq_s.w $t2, $t4 :: rd 0x4ef4339b rt 0xb10bcc65 DSPControl 0x0 --absq_s.w $t0, $t8 :: rd 0x73f39fca rt 0x73f39fca DSPControl 0x0 --absq_s.w $t4, $t4 :: rd 0x7fffffff rt 0x80000000 DSPControl 0x100000 --absq_s.w $t0, $t1 :: rd 0x00005ba0 rt 0xffffa460 DSPControl 0x0 --absq_s.w $t2, $t3 :: rd 0x075c70fa rt 0x075c70fa DSPControl 0x0 --absq_s.w $t4, $t1 :: rd 0x0000000d rt 0xfffffff3 DSPControl 0x0 --absq_s.w $t6, $t7 :: rd 0x000000ed rt 0xffffff13 DSPControl 0x0 ---------- ADDQ.PH -------- --addq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addq.ph $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 --addq.ph $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 --addq.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 --addq.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 --addq.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --addq.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 --addq.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq.ph $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addq.ph $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 --addq.ph $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99a0000 DSPCtrl 0x00100000 --addq.ph $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 --addq.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --addq.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 --addq.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addq.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 --addq.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addq.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addq.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x66656665 DSPCtrl 0x00100000 --addq.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed69a5c2 DSPCtrl 0x00000000 --addq.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addq.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00100000 --addq.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00100000 --addq.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addq.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81663544 DSPCtrl 0x00000000 --addq.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a5a6a5 DSPCtrl 0x00000000 --addq.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99949994 DSPCtrl 0x00000000 --addq.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6412a92 DSPCtrl 0x00000000 --addq.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 --addq.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffefffe DSPCtrl 0x00000000 --addq.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3e93ae DSPCtrl 0x00000000 --addq.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00000000 --addq.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addq.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05e4c57 DSPCtrl 0x00000000 --addq.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0506904f DSPCtrl 0x00000000 --addq.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 --addq.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00100000 --addq.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597128e0 DSPCtrl 0x00100000 ---------- ADDQ_S.PH -------- --addq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addq_s.ph $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 --addq_s.ph $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 --addq_s.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 --addq_s.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x8000437b DSPCtrl 0x00100000 --addq_s.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00100000 --addq_s.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq_s.ph $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addq_s.ph $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x80005856 DSPCtrl 0x00100000 --addq_s.ph $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x7fff8000 DSPCtrl 0x00100000 --addq_s.ph $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00100000 --addq_s.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addq_s.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addq_s.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addq_s.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x80008000 DSPCtrl 0x00100000 --addq_s.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed69a5c2 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addq_s.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23887fff DSPCtrl 0x00100000 --addq_s.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98137fff DSPCtrl 0x00100000 --addq_s.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addq_s.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81663544 DSPCtrl 0x00000000 --addq_s.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a5a6a5 DSPCtrl 0x00000000 --addq_s.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99949994 DSPCtrl 0x00000000 --addq_s.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6412a92 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 --addq_s.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffefffe DSPCtrl 0x00000000 --addq_s.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3e93ae DSPCtrl 0x00000000 --addq_s.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00000000 --addq_s.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addq_s.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05e4c57 DSPCtrl 0x00000000 --addq_s.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0506904f DSPCtrl 0x00000000 --addq_s.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x70357fff DSPCtrl 0x00100000 --addq_s.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x800028e0 DSPCtrl 0x00100000 ---------- ADDQ_S.W -------- --addq_s.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addq_s.w $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 --addq_s.w $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 --addq_s.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 --addq_s.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.w $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 --addq_s.w $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fffffff DSPCtrl 0x00100000 --addq_s.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq_s.w $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addq_s.w $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x80000000 DSPCtrl 0x00100000 --addq_s.w $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x7fffffff DSPCtrl 0x00100000 --addq_s.w $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.w $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 --addq_s.w $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fffffff DSPCtrl 0x00100000 --addq_s.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq_s.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addq_s.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addq_s.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addq_s.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x80000000 DSPCtrl 0x00100000 --addq_s.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed6aa5c2 DSPCtrl 0x00000000 --addq_s.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addq_s.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 --addq_s.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00000000 --addq_s.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addq_s.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81673544 DSPCtrl 0x00000000 --addq_s.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a6a6a5 DSPCtrl 0x00000000 --addq_s.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99959994 DSPCtrl 0x00000000 --addq_s.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6422a92 DSPCtrl 0x00000000 --addq_s.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 --addq_s.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 --addq_s.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3f93ae DSPCtrl 0x00000000 --addq_s.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ef0eb2 DSPCtrl 0x00000000 --addq_s.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addq_s.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05f4c57 DSPCtrl 0x00000000 --addq_s.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0507904f DSPCtrl 0x00000000 --addq_s.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 --addq_s.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00000000 --addq_s.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x80000000 DSPCtrl 0x00100000 ---------- ADDSC -------- --addsc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addsc $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 --addsc $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 --addsc $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 --addsc $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00002000 --addsc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00002000 --addsc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00000000 --addsc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addsc $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addsc $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00002000 --addsc $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99b0000 DSPCtrl 0x00000000 --addsc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00002000 --addsc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00002000 --addsc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00000000 --addsc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addsc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addsc $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00002000 --addsc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addsc $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addsc $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x66666665 DSPCtrl 0x00002000 --addsc $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed6aa5c2 DSPCtrl 0x00002000 --addsc $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addsc $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 --addsc $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00000000 --addsc $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addsc $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81673544 DSPCtrl 0x00002000 --addsc $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a6a6a5 DSPCtrl 0x00000000 --addsc $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99959994 DSPCtrl 0x00002000 --addsc $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6422a92 DSPCtrl 0x00000000 --addsc $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00002000 --addsc $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffffffe DSPCtrl 0x00002000 --addsc $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3f93ae DSPCtrl 0x00002000 --addsc $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ef0eb2 DSPCtrl 0x00000000 --addsc $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addsc $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05f4c57 DSPCtrl 0x00000000 --addsc $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0507904f DSPCtrl 0x00002000 --addsc $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 --addsc $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00002000 --addsc $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597228e0 DSPCtrl 0x00002000 ---------- ADDU.QB -------- --addu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addu.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046138 DSPCtrl 0x00100000 --addu.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 --addu.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcc74 DSPCtrl 0x00100000 --addu.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 --addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xff00ff00 DSPCtrl 0x00100000 --addu.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefefefe DSPCtrl 0x00100000 --addu.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addu.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addu.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 --addu.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99a0000 DSPCtrl 0x00100000 --addu.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 --addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xff00ff00 DSPCtrl 0x00100000 --addu.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefefefe DSPCtrl 0x00100000 --addu.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addu.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 --addu.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addu.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addu.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x65656565 DSPCtrl 0x00100000 --addu.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xec69a4c2 DSPCtrl 0x00100000 --addu.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addu.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 --addu.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e333 DSPCtrl 0x00100000 --addu.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addu.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x80663444 DSPCtrl 0x00100000 --addu.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe5a5a5a5 DSPCtrl 0x00100000 --addu.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x98949894 DSPCtrl 0x00100000 --addu.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa5412992 DSPCtrl 0x00100000 --addu.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000e8f DSPCtrl 0x00100000 --addu.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfefefefe DSPCtrl 0x00100000 --addu.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbd3e93ae DSPCtrl 0x00100000 --addu.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00100000 --addu.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addu.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xcf5e4b57 DSPCtrl 0x00100000 --addu.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x04068f4f DSPCtrl 0x00100000 --addu.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6f907 DSPCtrl 0x00100000 --addu.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x6f35be30 DSPCtrl 0x00100000 --addu.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597128e0 DSPCtrl 0x00100000 ---------- ADDU_S.QB -------- --addu_s.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addu_s.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x000461ff DSPCtrl 0x00100000 --addu_s.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 --addu_s.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabccff DSPCtrl 0x00100000 --addu_s.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xff73437b DSPCtrl 0x00100000 --addu_s.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefffeff DSPCtrl 0x00100000 --addu_s.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addu_s.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addu_s.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0xff005856 DSPCtrl 0x00100000 --addu_s.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99aff00 DSPCtrl 0x00100000 --addu_s.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0xff000000 DSPCtrl 0x00100000 --addu_s.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefffeff DSPCtrl 0x00100000 --addu_s.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addu_s.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addu_s.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0xff000000 DSPCtrl 0x00100000 --addu_s.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addu_s.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addu_s.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addu_s.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 --addu_s.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e3ff DSPCtrl 0x00100000 --addu_s.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addu_s.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe5ffffff DSPCtrl 0x00100000 --addu_s.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa5ffffff DSPCtrl 0x00100000 --addu_s.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xff000eff DSPCtrl 0x00100000 --addu_s.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xffffffae DSPCtrl 0x00100000 --addu_s.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2eeffb2 DSPCtrl 0x00100000 --addu_s.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addu_s.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xcfffffff DSPCtrl 0x00100000 --addu_s.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6f9ff DSPCtrl 0x00100000 --addu_s.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xffffbeff DSPCtrl 0x00100000 --addu_s.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xff71ffe0 DSPCtrl 0x00100000 ---------- ADDWC -------- --addwc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addwc $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 --addwc $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 --addwc $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 --addwc $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 --addwc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 --addwc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 --addwc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addwc $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addwc $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 --addwc $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99b0000 DSPCtrl 0x00100000 --addwc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 --addwc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 --addwc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 --addwc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addwc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addwc $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 --addwc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addwc $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addwc $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x66666665 DSPCtrl 0x00100000 --addwc $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed6aa5c2 DSPCtrl 0x00000000 --addwc $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addwc $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 --addwc $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00000000 --addwc $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addwc $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81673544 DSPCtrl 0x00000000 --addwc $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a6a6a5 DSPCtrl 0x00000000 --addwc $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99959994 DSPCtrl 0x00000000 --addwc $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6422a92 DSPCtrl 0x00000000 --addwc $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 --addwc $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 --addwc $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3f93ae DSPCtrl 0x00000000 --addwc $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ef0eb2 DSPCtrl 0x00000000 --addwc $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addwc $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05f4c57 DSPCtrl 0x00000000 --addwc $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0507904f DSPCtrl 0x00000000 --addwc $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 --addwc $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00000000 --addwc $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597228e0 DSPCtrl 0x00100000 ---------- BITREV -------- --bitrev $t0, $t1 :: rd 0x00000000 rt 0x00000000 --bitrev $t2, $t3 :: rd 0x0000614c rt 0x80003286 --bitrev $t4, $t1 :: rd 0x0000ac24 rt 0xfabc2435 --bitrev $t6, $t7 :: rd 0x00000001 rt 0x73468000 --bitrev $t5, $t3 :: rd 0x00000000 rt 0x80000000 --bitrev $t2, $t4 :: rd 0x0000ffff rt 0xffffffff --bitrev $t0, $t8 :: rd 0x0000fffa rt 0xfff45fff --bitrev $t2, $t4 :: rd 0x0000aaa0 rt 0x00000555 --bitrev $t0, $t1 :: rd 0x00000000 rt 0x00000000 --bitrev $t2, $t3 :: rd 0x00000000 rt 0x80000000 --bitrev $t4, $t1 :: rd 0x0000aaaa rt 0x55555555 --bitrev $t6, $t7 :: rd 0x0000ac24 rt 0xffff2435 --bitrev $t5, $t3 :: rd 0x0000d5d5 rt 0xabababab --bitrev $t2, $t4 :: rd 0x00004b2d rt 0xfc79b4d2 --bitrev $t0, $t8 :: rd 0x00000000 rt 0x00000000 --bitrev $t2, $t4 :: rd 0x0000a6a2 rt 0x00354565 --bitrev $t0, $t1 :: rd 0x0000aae6 rt 0x00086755 --bitrev $t2, $t3 :: rd 0x0000f1f1 rt 0x8f8f8f8f --bitrev $t4, $t1 :: rd 0x00007777 rt 0xeeeeeeee --bitrev $t6, $t7 :: rd 0x0000dbdb rt 0x1bdbdbdb --bitrev $t5, $t3 :: rd 0x0000537b rt 0xdecadeca --bitrev $t2, $t4 :: rd 0x00007bd2 rt 0x93474bde --bitrev $t0, $t8 :: rd 0x0000ffe0 rt 0xfc0007ff --bitrev $t2, $t4 :: rd 0x0000ffff rt 0xffffffff --bitrev $t0, $t1 :: rd 0x0000f12d rt 0xcb4ab48f --bitrev $t2, $t3 :: rd 0x0000187e rt 0xaf8f7e18 --bitrev $t4, $t1 :: rd 0x000008a2 rt 0x87df4510 --bitrev $t6, $t7 :: rd 0x00008717 rt 0xabf4e8e1 --bitrev $t5, $t3 :: rd 0x00003577 rt 0xf4c0eeac --bitrev $t2, $t4 :: rd 0x00004f2a rt 0x006a54f2 --bitrev $t0, $t8 :: rd 0x0000c922 rt 0x79f74493 --bitrev $t2, $t4 :: rd 0x0000c8c7 rt 0x9c09e313 ---------- BPOSGE32 -------- --bposge32 :: 6, POSval: 0 --bposge32 :: 7, POSval: 1 --bposge32 :: 3, POSval: 32 --bposge32 :: 9, POSval: 17 --bposge32 :: 10, POSval: 8 --bposge32 :: 6, POSval: 60 --bposge32 :: 12, POSval: 5 --bposge32 :: 8, POSval: -3 --bposge32 :: 9, POSval: 125 --bposge32 :: 15, POSval: 7 --bposge32 :: 11, POSval: 42 --bposge32 :: 12, POSval: 53 --bposge32 :: 13, POSval: 99 --bposge32 :: 19, POSval: 12 --bposge32 :: 20, POSval: 4 --bposge32 :: 21, POSval: 6 ---------- CMP.EQ.PH -------- --cmp.eq.ph $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x00000000 --cmp.eq.ph $t2, $t3 :: rs 0x00045fb2 rt 0x00000286 DSPCtrl 0x00000000 --cmp.eq.ph $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x02000000 --cmp.eq.ph $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x01000000 --cmp.eq.ph $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 --cmp.eq.ph $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 --cmp.eq.ph $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x03000000 --cmp.eq.ph $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x02000000 --cmp.eq.ph $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x03000000 --cmp.eq.ph $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x03000000 --cmp.eq.ph $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 --cmp.eq.ph $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x00000000 --cmp.eq.ph $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 --cmp.eq.ph $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x00000000 --cmp.eq.ph $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 --cmp.eq.ph $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 --cmp.eq.ph $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 --cmp.eq.ph $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 --cmp.eq.ph $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x00000000 --cmp.eq.ph $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x00000000 --cmp.eq.ph $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x00000000 --cmp.eq.ph $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x00000000 --cmp.eq.ph $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x00000000 --cmp.eq.ph $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x03000000 --cmp.eq.ph $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 --cmp.eq.ph $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x00000000 --cmp.eq.ph $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x00000000 --cmp.eq.ph $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 --cmp.eq.ph $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x00000000 --cmp.eq.ph $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x00000000 --cmp.eq.ph $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x00000000 --cmp.eq.ph $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 ---------- CMP.LT.PH -------- --cmp.lt.ph $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x02000000 --cmp.lt.ph $t2, $t3 :: rs 0x00045fb2 rt 0x00000286 DSPCtrl 0x00000000 --cmp.lt.ph $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x01000000 --cmp.lt.ph $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x02000000 --cmp.lt.ph $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 --cmp.lt.ph $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 --cmp.lt.ph $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x00000000 --cmp.lt.ph $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x01000000 --cmp.lt.ph $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x00000000 --cmp.lt.ph $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x00000000 --cmp.lt.ph $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x03000000 --cmp.lt.ph $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x01000000 --cmp.lt.ph $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 --cmp.lt.ph $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x02000000 --cmp.lt.ph $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x02000000 --cmp.lt.ph $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 --cmp.lt.ph $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x02000000 --cmp.lt.ph $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 --cmp.lt.ph $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x02000000 --cmp.lt.ph $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x03000000 --cmp.lt.ph $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x03000000 --cmp.lt.ph $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x01000000 --cmp.lt.ph $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x01000000 --cmp.lt.ph $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x00000000 --cmp.lt.ph $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 --cmp.lt.ph $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x01000000 --cmp.lt.ph $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x01000000 --cmp.lt.ph $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 --cmp.lt.ph $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x01000000 --cmp.lt.ph $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 --cmp.lt.ph $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x02000000 --cmp.lt.ph $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 ---------- CMP.LE.PH -------- --cmp.le.ph $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x02000000 --cmp.le.ph $t2, $t3 :: rs 0x00045fb2 rt 0x00000286 DSPCtrl 0x00000000 --cmp.le.ph $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x03000000 --cmp.le.ph $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x03000000 --cmp.le.ph $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 --cmp.le.ph $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 --cmp.le.ph $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x03000000 --cmp.le.ph $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x03000000 --cmp.le.ph $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x03000000 --cmp.le.ph $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x03000000 --cmp.le.ph $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x03000000 --cmp.le.ph $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x01000000 --cmp.le.ph $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 --cmp.le.ph $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x02000000 --cmp.le.ph $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x02000000 --cmp.le.ph $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 --cmp.le.ph $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x02000000 --cmp.le.ph $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 --cmp.le.ph $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x02000000 --cmp.le.ph $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x03000000 --cmp.le.ph $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x03000000 --cmp.le.ph $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x01000000 --cmp.le.ph $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x01000000 --cmp.le.ph $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x03000000 --cmp.le.ph $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 --cmp.le.ph $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x01000000 --cmp.le.ph $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x01000000 --cmp.le.ph $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 --cmp.le.ph $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x01000000 --cmp.le.ph $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 --cmp.le.ph $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x02000000 --cmp.le.ph $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 ---------- CMPGU.EQ.QB -------- --cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f --cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000008 --cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x00000000 --cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000000 --cmpgu.eq.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 --cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 --cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f --cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000c --cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000006 --cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0000000c --cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000003 --cmpgu.eq.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x0000000f --cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 --cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f --cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000c --cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f --cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x0000000f --cmpgu.eq.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x00000000 --cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 --cmpgu.eq.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 --cmpgu.eq.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000000 --cmpgu.eq.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 --cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x00000000 --cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00000000 --cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 --cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x00000000 --cmpgu.eq.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00000000 --cmpgu.eq.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x00000005 --cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000000 --cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000006 --cmpgu.eq.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x0000000f --cmpgu.eq.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000000 --cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x00000000 --cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x00000000 --cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x00000000 --cmpgu.eq.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x00000000 --cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00000000 --cmpgu.eq.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000000 --cmpgu.eq.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000000 ---------- CMPGU.LT.QB -------- --cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000000 --cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x0000000e --cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0000000b --cmpgu.lt.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 --cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f --cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x00000000 --cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000001 --cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000008 --cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00000002 --cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000000 --cmpgu.lt.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 --cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f --cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x00000000 --cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000001 --cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 --cmpgu.lt.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x00000000 --cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000000f --cmpgu.lt.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 --cmpgu.lt.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000008 --cmpgu.lt.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 --cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x00000000 --cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00000000 --cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000000f --cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0000000f --cmpgu.lt.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00000007 --cmpgu.lt.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x0000000a --cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000009 --cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000009 --cmpgu.lt.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 --cmpgu.lt.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000001 --cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0000000c --cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x0000000c --cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x0000000f --cmpgu.lt.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0000000f --cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00000001 --cmpgu.lt.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000004 --cmpgu.lt.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000002 ---------- CMPGU.LE.QB -------- --cmpgu.le.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f --cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000008 --cmpgu.le.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x0000000e --cmpgu.le.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0000000b --cmpgu.le.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 --cmpgu.le.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f --cmpgu.le.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f --cmpgu.le.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000d --cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x0000000e --cmpgu.le.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0000000e --cmpgu.le.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000003 --cmpgu.le.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x0000000f --cmpgu.le.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f --cmpgu.le.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f --cmpgu.le.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000d --cmpgu.le.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f --cmpgu.le.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x0000000f --cmpgu.le.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x00000000 --cmpgu.le.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000000f --cmpgu.le.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 --cmpgu.le.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000008 --cmpgu.le.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 --cmpgu.le.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x00000000 --cmpgu.le.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00000000 --cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000000f --cmpgu.le.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0000000f --cmpgu.le.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00000007 --cmpgu.le.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x0000000f --cmpgu.le.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000009 --cmpgu.le.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x0000000f --cmpgu.le.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x0000000f --cmpgu.le.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000001 --cmpgu.le.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0000000c --cmpgu.le.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x0000000c --cmpgu.le.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x0000000f --cmpgu.le.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0000000f --cmpgu.le.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00000001 --cmpgu.le.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000004 --cmpgu.le.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000002 ---------- CMPU.EQ.QB -------- --cmpu.eq.qb $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x00000000 --cmpu.eq.qb $t2, $t3 :: rs 0x00005fb2 rt 0x00000286 DSPCtrl 0x0c000000 --cmpu.eq.qb $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x0c000000 --cmpu.eq.qb $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x03000000 --cmpu.eq.qb $t5, $t3 :: rs 0xf973437b rt 0x80734300 DSPCtrl 0x06000000 --cmpu.eq.qb $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 --cmpu.eq.qb $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x0f000000 --cmpu.eq.qb $t4, $t6 :: rs 0x0000c420 rt 0x0000c420 DSPCtrl 0x0f000000 --cmpu.eq.qb $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x0f000000 --cmpu.eq.qb $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x0f000000 --cmpu.eq.qb $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 --cmpu.eq.qb $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x00000000 --cmpu.eq.qb $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 --cmpu.eq.qb $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x00000000 --cmpu.eq.qb $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 --cmpu.eq.qb $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 --cmpu.eq.qb $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 --cmpu.eq.qb $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 --cmpu.eq.qb $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x00000000 --cmpu.eq.qb $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x00000000 --cmpu.eq.qb $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x05000000 --cmpu.eq.qb $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x00000000 --cmpu.eq.qb $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x06000000 --cmpu.eq.qb $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x0f000000 --cmpu.eq.qb $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 --cmpu.eq.qb $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x00000000 --cmpu.eq.qb $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x00000000 --cmpu.eq.qb $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 --cmpu.eq.qb $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x00000000 --cmpu.eq.qb $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x00000000 --cmpu.eq.qb $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x00000000 --cmpu.eq.qb $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 ---------- CMPU.LT.QB -------- --cmpu.lt.qb $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x0f000000 --cmpu.lt.qb $t2, $t3 :: rs 0x00045fb2 rt 0x01080286 DSPCtrl 0x0c000000 --cmpu.lt.qb $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x02000000 --cmpu.lt.qb $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x08000000 --cmpu.lt.qb $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 --cmpu.lt.qb $t2, $t4 :: rs 0xffffffff rt 0x00010001 DSPCtrl 0x00000000 --cmpu.lt.qb $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x00000000 --cmpu.lt.qb $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x01000000 --cmpu.lt.qb $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x00000000 --cmpu.lt.qb $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x00000000 --cmpu.lt.qb $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 --cmpu.lt.qb $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x0f000000 --cmpu.lt.qb $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 --cmpu.lt.qb $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x08000000 --cmpu.lt.qb $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 --cmpu.lt.qb $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 --cmpu.lt.qb $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 --cmpu.lt.qb $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x0f000000 --cmpu.lt.qb $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x0f000000 --cmpu.lt.qb $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x07000000 --cmpu.lt.qb $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x0a000000 --cmpu.lt.qb $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x09000000 --cmpu.lt.qb $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x09000000 --cmpu.lt.qb $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x00000000 --cmpu.lt.qb $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x01000000 --cmpu.lt.qb $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x0c000000 --cmpu.lt.qb $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x0c000000 --cmpu.lt.qb $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x0f000000 --cmpu.lt.qb $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x0f000000 --cmpu.lt.qb $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 --cmpu.lt.qb $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x04000000 --cmpu.lt.qb $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x02000000 ---------- CMPU.LE.QB -------- --cmpu.le.qb $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x0f000000 --cmpu.le.qb $t2, $t3 :: rs 0x00045fb2 rt 0x01040286 DSPCtrl 0x0c000000 --cmpu.le.qb $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x0e000000 --cmpu.le.qb $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x0b000000 --cmpu.le.qb $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 --cmpu.le.qb $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x0f000000 --cmpu.le.qb $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x0f000000 --cmpu.le.qb $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x0d000000 --cmpu.le.qb $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x0f000000 --cmpu.le.qb $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x0f000000 --cmpu.le.qb $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 --cmpu.le.qb $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x0f000000 --cmpu.le.qb $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 --cmpu.le.qb $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x08000000 --cmpu.le.qb $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 --cmpu.le.qb $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 --cmpu.le.qb $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 --cmpu.le.qb $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x0f000000 --cmpu.le.qb $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x0f000000 --cmpu.le.qb $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x07000000 --cmpu.le.qb $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x0f000000 --cmpu.le.qb $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x09000000 --cmpu.le.qb $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x0f000000 --cmpu.le.qb $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x0f000000 --cmpu.le.qb $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x01000000 --cmpu.le.qb $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x0c000000 --cmpu.le.qb $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x0c000000 --cmpu.le.qb $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x0f000000 --cmpu.le.qb $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x0f000000 --cmpu.le.qb $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 --cmpu.le.qb $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x04000000 --cmpu.le.qb $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x02000000 ---------- DPAQ_S.W.PH -------- --dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0xcebedda9 dspCtrl 0x00020000 --dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000001 outLO 0x6a902dee dspCtrl 0x00080000 --dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x80000000 dspCtrl 0x00010000 --dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffb dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0xfffc0003 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0d5fae66 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 --dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x39e41d73 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc807ec2 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x5b47e0f8 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x09430ca0 dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x27896e23 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x64cf7771 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f7a7a5f dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xf42915f6 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1f4dff13 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x00000000 outLO 0x02b51c5a dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x6f6ca6ba dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf7589cda dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3575 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xc98e93f1 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbc416fd6 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xd53ff508 dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xc4465aee dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x0e457e6e dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xb9b99637 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x062e5f3f dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x7b2565dc dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x64c4e377 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x507f754e dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x43774ada dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc2a10106 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0xa97b960e dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7d78c144 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x65b56242 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0xb39e2e69 dspCtrl 0x00040000 --dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x923c5393 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x9a72b449 dspCtrl 0x00000000 --dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x3ae45be0 dspCtrl 0x00000000 --dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x9e955590 dspCtrl 0x00000000 --dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x00000000 outLO 0x36eeba7c dspCtrl 0x00020000 ---------- DPAQ_SA.L.W -------- --dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000002 outLO 0x00000006 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x7fffa7aa outLO 0x4ebeddaa dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x6a91178a outLO 0xffffffff dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x7fffffff outLO 0xffffffff dspCtrl 0x00010000 --dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffdfffd dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x7ffefffe outLO 0x80020001 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x1809ae66 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x7fffffff outLO 0xffff2434 dspCtrl 0x00040000 --dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xc71c71c6 outLO 0x8f39e48f dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc507ec2 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x2da3188e outLO 0xdb65f07c dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x006a26f6 outLO 0x60fcc9c0 dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000eb3a2 outLO 0xc358cdc5 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfff92ccc outLO 0x0403f6c1 dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffea outLO 0x7a7a7a5f dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x0e9aa14a outLO 0x99419ed6 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xf46b6259 outLO 0x9b646d77 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x11f475db outLO 0x6177fd92 dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xefe0f0c1 outLO 0xbcb7040e dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xfc200782 outLO 0x83389cda dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x18b27d05 outLO 0x3b787441 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x0fc95b3b outLO 0x22b18658 dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xf9de25d4 outLO 0xd0fdef8c dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xbd1bf5fa outLO 0x7006d9ee dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xb01464c5 outLO 0x2291ac7e dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x1af47c9f outLO 0x231c51d1 dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xe57e84e1 outLO 0x1a67b5d7 dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xce376894 outLO 0xfb99d898 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xdec79617 outLO 0x57bdd1dd dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xa3ae018c outLO 0x86555c5c dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x0a519844 outLO 0x639570aa dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x0c9f59b9 outLO 0xe5425be6 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x67317b4f outLO 0xaee36470 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffcf5 outLO 0x4384c144 dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x3efc805b outLO 0x9493110e dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xdcdc785f outLO 0x339d3f1e dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00005070 outLO 0xb39d8d88 dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x4f249f4d outLO 0xde80e5a9 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x02506f83 outLO 0x2c89c7a1 dspCtrl 0x00000000 --dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00002c40 outLO 0xdebc2ffc dspCtrl 0x00000000 --dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000801ea outLO 0xa7c3b620 dspCtrl 0x00000000 --dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x000063f6 outLO 0x36edf28f dspCtrl 0x00000000 ---------- DPAU.H.QBL -------- --dpau.h.qbl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --dpau.h.qbl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 --dpau.h.qbl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x40004000 --dpau.h.qbl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x80004bf9 --dpau.h.qbl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00004001 --dpau.h.qbl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x000000fe --dpau.h.qbl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00013d01 --dpau.h.qbl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 --dpau.h.qbl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --dpau.h.qbl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff6435 --dpau.h.qbl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabac1c8f --dpau.h.qbl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 --dpau.h.qbl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x0000f87c --dpau.h.qbl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x00015db0 --dpau.h.qbl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --dpau.h.qbl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x00355694 --dpau.h.qbl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x000867ad --dpau.h.qbl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f --dpau.h.qbl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeefe63a --dpau.h.qbl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bdc9df7 --dpau.h.qbl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdecc1f7a --dpau.h.qbl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x93479b8a --dpau.h.qbl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfac0260a --dpau.h.qbl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083d3173 --dpau.h.qbl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb9747331 --dpau.h.qbl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce6cff4 --dpau.h.qbl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3d1d83 --dpau.h.qbl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1ebb5596 --dpau.h.qbl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722db95e --dpau.h.qbl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d7f9b0 --dpau.h.qbl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b11ec66 --dpau.h.qbl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa5638376 --dpau.h.qbl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10c4e92 --dpau.h.qbl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f42c2b --dpau.h.qbl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x5649aa98 --dpau.h.qbl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc5503452 --dpau.h.qbl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fc98d5c --dpau.h.qbl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e --dpau.h.qbl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --dpau.h.qbl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493718e --dpau.h.qbl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb24be21 --dpau.h.qbl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339eca4a --dpau.h.qbl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x7098316b --dpau.h.qbl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8e6a25 --dpau.h.qbl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --dpau.h.qbl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd6cafa --dpau.h.qbl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x6731ea3a --dpau.h.qbl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6ee96ea ---------- DPAU.H.QBR -------- --dpau.h.qbr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --dpau.h.qbr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 --dpau.h.qbr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x40000e25 --dpau.h.qbr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x80003fff --dpau.h.qbr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 --dpau.h.qbr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x000000fe --dpau.h.qbr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00013d01 --dpau.h.qbr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3f9a --dpau.h.qbr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --dpau.h.qbr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 --dpau.h.qbr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabac1c8f --dpau.h.qbr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b9ca --dpau.h.qbr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x0000f87c --dpau.h.qbr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x00016da0 --dpau.h.qbr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --dpau.h.qbr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x003584fd --dpau.h.qbr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0008e2ef --dpau.h.qbr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f9cf7 --dpau.h.qbr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeef7ff6 --dpau.h.qbr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bdd3577 --dpau.h.qbr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdecc1f7a --dpau.h.qbr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x93482900 --dpau.h.qbr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfac03b9b --dpau.h.qbr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083d3173 --dpau.h.qbr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb974656e --dpau.h.qbr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce7153c --dpau.h.qbr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3c8132 --dpau.h.qbr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1ebb4b86 --dpau.h.qbr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722d975b --dpau.h.qbr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d71419 --dpau.h.qbr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b11f933 --dpau.h.qbr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa563e99b --dpau.h.qbr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10c3779 --dpau.h.qbr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f4181b --dpau.h.qbr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x5649344d --dpau.h.qbr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc54f8d48 --dpau.h.qbr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fca1b10 --dpau.h.qbr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e084c83 --dpau.h.qbr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --dpau.h.qbr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e --dpau.h.qbr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb24cd67 --dpau.h.qbr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339dcd88 --dpau.h.qbr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x70977b10 --dpau.h.qbr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8eaa2f --dpau.h.qbr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --dpau.h.qbr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd72b26 --dpau.h.qbr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x67322ead --dpau.h.qbr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6ee328f ---------- DPSQ_S.W.PH -------- --dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0xffffffff outLO 0xb1412257 dspCtrl 0x00020000 --dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0xffffffff outLO 0x956fd210 dspCtrl 0x00080000 --dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xffffffff outLO 0x80000002 dspCtrl 0x00010000 --dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00000003 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0x0003fffb dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x125cb3e6 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0x7fff2436 dspCtrl 0x00040000 --dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x00000000 outLO 0x1d7339e3 dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc72eae2 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xa4b81f08 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xf6bcf360 dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xffffffff outLO 0xd8e11ca7 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xffffffff outLO 0x9b415739 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8fa4a4bf dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xe9b4c7e6 dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1869b8a3 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xbae0a13a dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0xb721f102 dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfe26bb1a dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b356d dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xa959de91 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbd8a8272 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xc3384b30 dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x792f962e dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0xd6153dd2 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0x89f458eb dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0xeff51e8f dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xcfa0c334 dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xfd52b553 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x9767ca46 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x691a7fa6 dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc7fdf2c6 dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x1616bcda dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e976f58 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x5596110e dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x00000000 outLO 0x1093620e dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffffff outLO 0xb39ceca7 dspCtrl 0x00040000 --dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x4ef230ff dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x7aa7e8b1 dspCtrl 0x00000000 --dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffffff outLO 0xdec90e30 dspCtrl 0x00000000 --dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x2fce6f74 dspCtrl 0x00000000 --dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0x36ed2aa2 dspCtrl 0x00020000 ---------- DPSQ_SA.L.W -------- --dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0xfffffffe outLO 0x00000006 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x80005856 outLO 0x31412256 dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x956ee875 outLO 0xffffffff dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x80000000 outLO 0x00000002 dspCtrl 0x00010000 --dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00020001 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x80010001 outLO 0x7ffdfffd dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x07b2b3e6 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x80000000 outLO 0x00000000 dspCtrl 0x00040000 --dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x38e38e38 outLO 0xc81d72c7 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfca2eae2 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xd25ce771 outLO 0x249a0f84 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xff95d909 outLO 0x9f033640 dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xfff14c5d outLO 0x3d11bd05 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x0006d333 outLO 0xfc0cd7e9 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x00000014 outLO 0xa4a4a4bf dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xf1655eb5 outLO 0x449c3f06 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x0b949da6 outLO 0x9c534a3f dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xee0b8a24 outLO 0x5c1dc002 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x101f0f3d outLO 0x69d793ae dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x03dff87d outLO 0x7246bb1a dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b356f dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xe74d82fa outLO 0x376ffe41 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xf036a4c4 outLO 0x571a6bf0 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x0621da2a outLO 0xc77a50ac dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x42e40a05 outLO 0xcd6f172e dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x4feb9b3b outLO 0xc1c90fc2 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xe50b8360 outLO 0x20919d51 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x1a817b1f outLO 0xdbbbc7f7 dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x31c8976a outLO 0x4f2c5078 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x213869e8 outLO 0x0a59c6ed dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x5c51fe74 outLO 0x6191e338 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xf5ae67bc outLO 0x48fc59d6 dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xf360a645 outLO 0xa55c97e6 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x98ce84b1 outLO 0x10aeee78 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x0000030b outLO 0xb88b6f58 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xc1037fa3 outLO 0x9493110e dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x232387a0 outLO 0x42ab8532 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffaf8f outLO 0xb39d8d88 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0xb0db60b3 outLO 0x02ad9ee9 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xfdaf907b outLO 0xe890d559 dspCtrl 0x00000000 --dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffd3bf outLO 0x3af13a14 dspCtrl 0x00000000 --dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0xfff7fe16 outLO 0x26a00ee4 dspCtrl 0x00000000 --dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffff9c09 outLO 0x36edf28f dspCtrl 0x00000000 ---------- DPSU.H.QBL -------- --dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 --dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x3fffc000 --dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffb405 --dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xffffffff outLO 0xffffc001 --dpsu.h.qbl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffff00 --dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffec2fd --dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 --dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --dpsu.h.qbl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xfffee435 --dpsu.h.qbl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabab3ac7 --dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 --dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xffff0784 --dpsu.h.qbl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xfffea250 --dpsu.h.qbl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x00353436 --dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x000866fd --dpsu.h.qbl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f --dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeedf7a2 --dpsu.h.qbl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bdb19bf --dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdec99e1a --dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x9346fc32 --dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfabf31ea --dpsu.h.qbl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x0839396f --dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb973ff51 --dpsu.h.qbl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce52254 --dpsu.h.qbl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3b22b5 --dpsu.h.qbl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1eba9b86 --dpsu.h.qbl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722d02e2 --dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d5f572 --dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b119168 --dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa562a59a --dpsu.h.qbl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10b4a38 --dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f31369 --dpsu.h.qbl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x56481fe8 --dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc54ebf7a --dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fc8c58c --dpsu.h.qbl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e --dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9492b08e --dpsu.h.qbl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb24062f --dpsu.h.qbl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339c50c6 --dpsu.h.qbl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x70965327 --dpsu.h.qbl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8c32d5 --dpsu.h.qbl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd69f16 --dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x6731daca --dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6ed4e34 ---------- DPSU.H.QBR -------- --dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 --dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x3ffff1db --dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffbfff --dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 --dpsu.h.qbr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffff00 --dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffec2fd --dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde22b2 --dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --dpsu.h.qbr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 --dpsu.h.qbr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabab3ac7 --dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79afda --dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xffff0784 --dpsu.h.qbr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xfffe9260 --dpsu.h.qbr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x003505cd --dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0007ebbb --dpsu.h.qbr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8227 --dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeee5de6 --dpsu.h.qbr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bda823f --dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdec99e1a --dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x93466ebc --dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfabf1c59 --dpsu.h.qbr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x0839396f --dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb9740d14 --dpsu.h.qbr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce4dd0c --dpsu.h.qbr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3bbf06 --dpsu.h.qbr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1ebaa596 --dpsu.h.qbr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722d24e5 --dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d6db09 --dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b11849b --dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa5623f75 --dpsu.h.qbr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10b6151 --dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f32779 --dpsu.h.qbr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x56489633 --dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc54f6684 --dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fc837d8 --dpsu.h.qbr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e07e419 --dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e --dpsu.h.qbr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb23f6e9 --dpsu.h.qbr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339d4d88 --dpsu.h.qbr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x70970982 --dpsu.h.qbr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8bf2cb --dpsu.h.qbr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd63eea --dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x67319657 --dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6edb28f ---------- EXTP -------- --extp $t1, $ac0, 31 :: rt 0x00100000 ac0 0x8000000080000000 size 31 DSPCtrl 0x0000002a --extp $t2, $ac1, 17 :: rt 0x00020000 ac1 0x8000000180000002 size 17 DSPCtrl 0x0000001f --extp $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000037 --extp $t4, $ac3, 12 :: rt 0x00000000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000016 --extp $t5, $ac0, 3 :: rt 0x00000007 ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x0000003f --extp $t6, $ac1, 8 :: rt 0x00000000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x0000000d --extp $t7, $ac2, 16 :: rt 0x00000000 ac2 0x00000001ffffffff size 16 DSPCtrl 0x0000003c --extp $t8, $ac3, 22 :: rt 0x007fffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000016 --extp $t0, $ac0, 9 :: rt 0x00000318 ac0 0x0000cdfe0fde3126 size 9 DSPCtrl 0x00000012 --extp $t2, $ac2, 16 :: rt 0x0001fffc ac2 0x00000018ffff2435 size 16 DSPCtrl 0x0000001e --extp $t3, $ac3, 6 :: rt 0x00000075 ac3 0xbabababaabababab size 6 DSPCtrl 0x00000011 --extp $t4, $ac0, 13 :: rt 0x00001f8f ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00000020 --extp $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000014 --extp $t6, $ac2, 27 :: rt 0x00000000 ac2 0xfbde397600000000 size 27 DSPCtrl 0x0000001e --extp $t7, $ac3, 7 :: rt 0x00000009 ac3 0xb0ed765412349876 size 7 DSPCtrl 0x00000020 --extp $t8, $ac0, 11 :: rt 0x00000c0d ac0 0x2353487035004565 size 11 DSPCtrl 0x00000025 --extp $t0, $ac1, 26 :: rt 0x03016f9b ac1 0x980b7cde86700055 size 26 DSPCtrl 0x0000003d --extp $t1, $ac2, 15 :: rt 0x00007c7c ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x0000001c --extp $t2, $ac3, 2 :: rt 0x00000006 ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x0000000e --extp $t3, $ac0, 1 :: rt 0x00000001 ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x0000003a --extp $t4, $ac1, 0 :: rt 0x00000001 ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00000013 ---------- EXTPDP -------- --extpdp $t1, $ac0, 31 :: rt 0x00100000 ac0 0x8000000080000000 size 31 DSPCtrl 0x0000000a --extpdp $t2, $ac1, 17 :: rt 0x00020000 ac1 0x8000000180000002 size 17 DSPCtrl 0x0000000d --extpdp $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000032 --extpdp $t4, $ac3, 12 :: rt 0x00000000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000009 --extpdp $t5, $ac0, 3 :: rt 0x00000007 ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x0000003b --extpdp $t6, $ac1, 8 :: rt 0x00000000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x00000004 --extpdp $t7, $ac2, 16 :: rt 0x00000000 ac2 0x00000001ffffffff size 16 DSPCtrl 0x0000002b --extpdp $t8, $ac3, 22 :: rt 0x007fffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x0000003f --extpdp $t0, $ac0, 9 :: rt 0x00000318 ac0 0x0000cdfe0fde3126 size 9 DSPCtrl 0x00000008 --extpdp $t3, $ac3, 6 :: rt 0x00000075 ac3 0xbabababaabababab size 6 DSPCtrl 0x0000000a --extpdp $t4, $ac0, 13 :: rt 0x00001f8f ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00000012 --extpdp $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 --extpdp $t6, $ac2, 27 :: rt 0x00000000 ac2 0xfbde397600000000 size 27 DSPCtrl 0x00000002 --extpdp $t7, $ac3, 7 :: rt 0x00000009 ac3 0x0bed765412349876 size 7 DSPCtrl 0x00000018 --extpdp $t8, $ac0, 11 :: rt 0x00000c00 ac0 0x2353487000354565 size 11 DSPCtrl 0x00000019 --extpdp $t0, $ac1, 26 :: rt 0x03016f9b ac1 0x980b7cde00086755 size 26 DSPCtrl 0x00000022 --extpdp $t1, $ac2, 15 :: rt 0x00007c7c ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x0000000c --extpdp $t2, $ac3, 2 :: rt 0x00000006 ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x0000000b --extpdp $t3, $ac0, 1 :: rt 0x00000001 ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x00000038 --extpdp $t4, $ac1, 0 :: rt 0x00000001 ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00000012 ---------- EXTPDPV -------- --extpdpv $t1, $ac0, $t2 :: rt 0x00000000 ac0 0x8000000080000000 rs 0x80000000 DSPCtrl 0x00000029 --extpdpv $t2, $ac1, $t3 :: rt 0x00000040 ac1 0x8000000180000002 rs 0x00000006 DSPCtrl 0x00000018 --extpdpv $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000017 --extpdpv $t5, $ac0, $t6 :: rt 0x0000003f ac0 0x7fffffff7fffffff rs 0x0fde3126 DSPCtrl 0x00000038 --extpdpv $t7, $ac2, $t8 :: rt 0x00000000 ac2 0x00000001ffffffff rs 0xaaaaaaaa DSPCtrl 0x00000031 --extpdpv $t8, $ac3, $t9 :: rt 0x003fffff ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 --extpdpv $t4, $ac0, $t3 :: rt 0x003f1e6d ac0 0xf0f0f0f0fc79b4d2 rs 0x12349876 DSPCtrl 0x00000009 --extpdpv $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x0000000e --extpdpv $t6, $ac2, $t5 :: rt 0x00000000 ac2 0xfbde397600000000 rs 0x00086755 DSPCtrl 0x00000008 --extpdpv $t7, $ac3, $t6 :: rt 0x00123498 ac3 0x0bed765412349876 rs 0x00000018 DSPCtrl 0x00000007 --extpdpv $t8, $ac0, $t7 :: rt 0x00018001 ac0 0x2353487000354565 rs 0x23534870 DSPCtrl 0x00000014 --extpdpv $t0, $ac1, $t8 :: rt 0x003016f9 ac1 0x980b7cde00086755 rs 0x92784656 DSPCtrl 0x00000026 --extpdpv $t1, $ac2, $t9 :: rt 0x00003e3e ac2 0x000000188f8f8f8f rs 0xeeeeeeee DSPCtrl 0x0000000d --extpdpv $t2, $ac3, $t1 :: rt 0x000006ee ac3 0x92784656eeeeeeee rs 0xcacacaca DSPCtrl 0x00000003 --extpdpv $t3, $ac0, $t1 :: rt 0x000002ca ac0 0xcacacaca1bdbdbdb rs 0xbacabaca DSPCtrl 0x0000002f --extpdpv $t4, $ac1, $t4 :: rt 0x0000056f ac1 0xbacabacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00000008 ---------- EXTPV -------- --extpv $t1, $ac0, $t2 :: rt 0x00000000 ac0 0x8000000080000000 rs 0x80000000 DSPCtrl 0x0000002a --extpv $t2, $ac1, $t3 :: rt 0x00000040 ac1 0x8000000180000002 rs 0x00000006 DSPCtrl 0x0000001f --extpv $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000037 --extpv $t5, $ac0, $t6 :: rt 0x0000003f ac0 0x7fffffff7fffffff rs 0x0fde3126 DSPCtrl 0x0000003f --extpv $t7, $ac2, $t8 :: rt 0x00000000 ac2 0x00000001ffffffff rs 0xaaaaaaaa DSPCtrl 0x0000003c --extpv $t8, $ac3, $t9 :: rt 0x003fffff ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000016 --extpv $t4, $ac0, $t3 :: rt 0x003f1e6d ac0 0xf0f0f0f0fc79b4d2 rs 0x12349876 DSPCtrl 0x00000020 --extpv $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000014 --extpv $t6, $ac2, $t5 :: rt 0x00000000 ac2 0xfbde397600000000 rs 0x00086755 DSPCtrl 0x0000001e --extpv $t7, $ac3, $t6 :: rt 0x00123498 ac3 0x0bed765412349876 rs 0x00000018 DSPCtrl 0x00000020 --extpv $t8, $ac0, $t7 :: rt 0x00018001 ac0 0x2353487000354565 rs 0x23534870 DSPCtrl 0x00000025 --extpv $t0, $ac1, $t8 :: rt 0x003016f9 ac1 0x980b7cde00086755 rs 0x92784656 DSPCtrl 0x0000003d --extpv $t1, $ac2, $t9 :: rt 0x00003e3e ac2 0x000000188f8f8f8f rs 0xeeeeeeee DSPCtrl 0x0000001c --extpv $t2, $ac3, $t1 :: rt 0x000006ee ac3 0x92784656eeeeeeee rs 0xcacacaca DSPCtrl 0x0000000e --extpv $t3, $ac0, $t1 :: rt 0x000002ca ac0 0xcacacaca1bdbdbdb rs 0xbacabaca DSPCtrl 0x0000003a --extpv $t4, $ac1, $t4 :: rt 0x0000056f ac1 0xbacabacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00000013 ---------- EXTR_S.H -------- --extr_s.h $t1, $ac0, 31 :: rt 0xffff8000 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000 --extr_s.h $t2, $ac1, 17 :: rt 0xffff8000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000 --extr_s.h $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 --extr_s.h $t4, $ac3, 12 :: rt 0x00007fff ac3 0x0000000440000000 size 12 DSPCtrl 0x00800000 --extr_s.h $t5, $ac0, 3 :: rt 0x00007fff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000 --extr_s.h $t6, $ac1, 8 :: rt 0xffff8000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x00800000 --extr_s.h $t7, $ac2, 16 :: rt 0x00007fff ac2 0x00000001ffffffff size 16 DSPCtrl 0x00800000 --extr_s.h $t8, $ac3, 22 :: rt 0xffffffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000000 --extr_s.h $t0, $ac0, 9 :: rt 0x00007fff ac0 0x0000cdfe0fde3126 size 9 DSPCtrl 0x00800000 --extr_s.h $t1, $ac1, 5 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 --extr_s.h $t2, $ac2, 14 :: rt 0x00007fff ac2 0x00000018ffff2435 size 14 DSPCtrl 0x00800000 --extr_s.h $t1, $ac1, 20 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 size 20 DSPCtrl 0x00800000 --extr_s.h $t2, $ac2, 16 :: rt 0x00007fff ac2 0x00000018ffff2435 size 16 DSPCtrl 0x00800000 --extr_s.h $t1, $ac1, 5 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 --extr_s.h $t2, $ac2, 22 :: rt 0x000063ff ac2 0x00000018ffff2435 size 22 DSPCtrl 0x00000000 --extr_s.h $t3, $ac3, 6 :: rt 0xffff8000 ac3 0xbabababaabababab size 6 DSPCtrl 0x00800000 --extr_s.h $t4, $ac0, 13 :: rt 0xffff8000 ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00800000 --extr_s.h $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 --extr_s.h $t6, $ac2, 27 :: rt 0xffff8000 ac2 0xfbde397600000000 size 27 DSPCtrl 0x00800000 --extr_s.h $t7, $ac3, 7 :: rt 0x00007fff ac3 0x0bed765412349876 size 7 DSPCtrl 0x00800000 --extr_s.h $t8, $ac0, 11 :: rt 0x00007fff ac0 0x2353487000354565 size 11 DSPCtrl 0x00800000 --extr_s.h $t0, $ac1, 26 :: rt 0xffff8000 ac1 0x980b7cde00086755 size 26 DSPCtrl 0x00800000 --extr_s.h $t1, $ac2, 15 :: rt 0x00007fff ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x00800000 --extr_s.h $t2, $ac3, 2 :: rt 0xffff8000 ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x00800000 --extr_s.h $t3, $ac0, 1 :: rt 0xffff8000 ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x00800000 --extr_s.h $t4, $ac1, 0 :: rt 0xffff8000 ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00800000 --extr_s.h $t5, $ac0, 3 :: rt 0x00007fff ac0 0x000000005fc92974 size 3 DSPCtrl 0x00800000 --extr_s.h $t6, $ac1, 8 :: rt 0x00007fff ac1 0x000000007e08184e size 8 DSPCtrl 0x00800000 --extr_s.h $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 --extr_s.h $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 --extr_s.h $t0, $ac0, 9 :: rt 0xffff8000 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00800000 --extr_s.h $t1, $ac1, 5 :: rt 0x00007fff ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00800000 --extr_s.h $t2, $ac2, 14 :: rt 0x00007fff ac2 0x0000000070974249 size 14 DSPCtrl 0x00800000 --extr_s.h $t1, $ac1, 20 :: rt 0xfffff8a8 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 --extr_s.h $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 --extr_s.h $t1, $ac1, 5 :: rt 0x00007fff ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00800000 --extr_s.h $t2, $ac2, 22 :: rt 0x0000019c ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 --extr_s.h $t3, $ac3, 6 :: rt 0xffff8000 ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00800000 --extr_s.h $t4, $ac0, 13 :: rt 0x00007fff ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00800000 --extr_s.h $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 --extr_s.h $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 --extr_s.h $t7, $ac3, 7 :: rt 0xffff8000 ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00800000 --extr_s.h $t8, $ac0, 11 :: rt 0xffff8000 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00800000 --extr_s.h $t0, $ac1, 26 :: rt 0xffffffea ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 --extr_s.h $t1, $ac2, 15 :: rt 0xffffe981 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 --extr_s.h $t2, $ac3, 2 :: rt 0x00007fff ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00800000 --extr_s.h $t3, $ac0, 1 :: rt 0x00007fff ac0 0x0000000079f74493 size 1 DSPCtrl 0x00800000 --extr_s.h $t4, $ac1, 0 :: rt 0xffff8000 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00800000 ---------- EXTR.W -------- --extr.w $t1, $ac0, 31 :: rt 0x00000001 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000 --extr.w $t2, $ac1, 17 :: rt 0x0000c000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000 --extr.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 --extr.w $t4, $ac3, 12 :: rt 0x00440000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000000 --extr.w $t5, $ac0, 3 :: rt 0xefffffff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000 --extr.w $t6, $ac1, 8 :: rt 0xff000000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x00000000 --extr.w $t7, $ac2, 16 :: rt 0x0001ffff ac2 0x00000001ffffffff size 16 DSPCtrl 0x00000000 --extr.w $t8, $ac3, 22 :: rt 0xffffffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000000 --extr.w $t0, $ac0, 9 :: rt 0xff7e8718 ac0 0x0000cdfefd0e3126 size 9 DSPCtrl 0x00800000 --extr.w $t1, $ac1, 5 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 --extr.w $t2, $ac2, 14 :: rt 0x0063fffc ac2 0x00000018ffff2435 size 14 DSPCtrl 0x00000000 --extr.w $t1, $ac1, 20 :: rt 0xaaaaa555 ac1 0xaaaaaaaa55555555 size 20 DSPCtrl 0x00800000 --extr.w $t2, $ac2, 16 :: rt 0x0018ffff ac2 0x00000018ffff2435 size 16 DSPCtrl 0x00000000 --extr.w $t1, $ac1, 5 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 --extr.w $t2, $ac2, 22 :: rt 0x000063ff ac2 0x00000018ffff2435 size 22 DSPCtrl 0x00000000 --extr.w $t3, $ac3, 6 :: rt 0xeaaeaeae ac3 0xbabababaabababab size 6 DSPCtrl 0x00800000 --extr.w $t4, $ac0, 13 :: rt 0x8787e3cd ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00800000 --extr.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 --extr.w $t6, $ac2, 27 :: rt 0x7bc72ec0 ac2 0xfbde397600000000 size 27 DSPCtrl 0x00800000 --extr.w $t7, $ac3, 7 :: rt 0xa8246930 ac3 0x0bed765412349876 size 7 DSPCtrl 0x00800000 --extr.w $t8, $ac0, 11 :: rt 0x0e0006a8 ac0 0x2353487000354565 size 11 DSPCtrl 0x00800000 --extr.w $t0, $ac1, 26 :: rt 0x02df37a0 ac1 0x980b7cde80006755 size 26 DSPCtrl 0x00800000 --extr.w $t1, $ac2, 15 :: rt 0x00311f1f ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x00000000 --extr.w $t2, $ac3, 2 :: rt 0xbbbbbbbb ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x00800000 --extr.w $t3, $ac0, 1 :: rt 0x0dededed ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x00800000 --extr.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00800000 --extr.w $t5, $ac0, 3 :: rt 0x0bf9252e ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 --extr.w $t6, $ac1, 8 :: rt 0x007e0818 ac1 0x000000007e08184e size 8 DSPCtrl 0x00000000 --extr.w $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 --extr.w $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 --extr.w $t0, $ac0, 9 :: rt 0xffdd9231 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00000000 --extr.w $t1, $ac1, 5 :: rt 0x019cec6c ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00000000 --extr.w $t2, $ac2, 14 :: rt 0x0001c25d ac2 0x0000000070974249 size 14 DSPCtrl 0x00000000 --extr.w $t1, $ac1, 20 :: rt 0xfffff8a8 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 --extr.w $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 --extr.w $t1, $ac1, 5 :: rt 0x0066b5a8 ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00000000 --extr.w $t2, $ac2, 22 :: rt 0x0000019c ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 --extr.w $t3, $ac3, 6 :: rt 0xfedbb7ca ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00000000 --extr.w $t4, $ac0, 13 :: rt 0x00025a76 ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00000000 --extr.w $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 --extr.w $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 --extr.w $t7, $ac3, 7 :: rt 0xff5f1efc ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00000000 --extr.w $t8, $ac0, 11 :: rt 0xfff0fbe8 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00000000 --extr.w $t0, $ac1, 26 :: rt 0xffffffea ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 --extr.w $t1, $ac2, 15 :: rt 0xffffe981 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 --extr.w $t2, $ac3, 2 :: rt 0x001a953c ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00000000 --extr.w $t3, $ac0, 1 :: rt 0x3cfba249 ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 --extr.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 ---------- EXTR_R.W -------- --extr_r.w $t1, $ac0, 31 :: rt 0xffffffff ac0 0xffffffff80000000 size 31 DSPCtrl 0x00000000 --extr_r.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 --extr_r.w $t5, $ac0, 3 :: rt 0x10000000 ac0 0x000000007fffffff size 3 DSPCtrl 0x00000000 --extr_r.w $t6, $ac1, 8 :: rt 0x00000000 ac1 0x0000000000000001 size 8 DSPCtrl 0x00000000 --extr_r.w $t7, $ac2, 16 :: rt 0x00000000 ac2 0xffffffffffffffff size 16 DSPCtrl 0x00000000 --extr_r.w $t0, $ac0, 9 :: rt 0xfffe8719 ac0 0xfffffffffd0e3126 size 9 DSPCtrl 0x00000000 --extr_r.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 --extr_r.w $t2, $ac2, 14 :: rt 0xfffffffd ac2 0xffffffffffff2435 size 14 DSPCtrl 0x00000000 --extr_r.w $t1, $ac1, 20 :: rt 0x00000555 ac1 0x0000000055555555 size 20 DSPCtrl 0x00000000 --extr_r.w $t2, $ac2, 16 :: rt 0xffffffff ac2 0xffffffffffff2435 size 16 DSPCtrl 0x00000000 --extr_r.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 --extr_r.w $t2, $ac2, 22 :: rt 0x00000000 ac2 0xffffffffffff2435 size 22 DSPCtrl 0x00000000 --extr_r.w $t3, $ac3, 6 :: rt 0xfeaeaeaf ac3 0xffffffffabababab size 6 DSPCtrl 0x00000000 --extr_r.w $t4, $ac0, 13 :: rt 0xffffe3ce ac0 0xfffffffffc79b4d2 size 13 DSPCtrl 0x00000000 --extr_r.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 --extr_r.w $t6, $ac2, 27 :: rt 0x00000000 ac2 0x0000000000000000 size 27 DSPCtrl 0x00000000 --extr_r.w $t7, $ac3, 7 :: rt 0x00246931 ac3 0x0000000012349876 size 7 DSPCtrl 0x00000000 --extr_r.w $t8, $ac0, 11 :: rt 0x000006a9 ac0 0x0000000000354565 size 11 DSPCtrl 0x00000000 --extr_r.w $t0, $ac1, 26 :: rt 0xffffffe0 ac1 0xffffffff80006755 size 26 DSPCtrl 0x00000000 --extr_r.w $t1, $ac2, 15 :: rt 0xffff1f1f ac2 0xffffffff8f8f8f8f size 15 DSPCtrl 0x00000000 --extr_r.w $t2, $ac3, 2 :: rt 0xfbbbbbbc ac3 0xffffffffeeeeeeee size 2 DSPCtrl 0x00000000 --extr_r.w $t3, $ac0, 1 :: rt 0x0dededee ac0 0x000000001bdbdbdb size 1 DSPCtrl 0x00000000 --extr_r.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xffffffffdecadeca size 0 DSPCtrl 0x00000000 --extr_r.w $t5, $ac0, 3 :: rt 0x0bf9252f ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 --extr_r.w $t6, $ac1, 8 :: rt 0x007e0818 ac1 0x000000007e08184e size 8 DSPCtrl 0x00000000 --extr_r.w $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 --extr_r.w $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 --extr_r.w $t0, $ac0, 9 :: rt 0xffdd9231 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00000000 --extr_r.w $t1, $ac1, 5 :: rt 0x019cec6c ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00000000 --extr_r.w $t2, $ac2, 14 :: rt 0x0001c25d ac2 0x0000000070974249 size 14 DSPCtrl 0x00000000 --extr_r.w $t1, $ac1, 20 :: rt 0xfffff8a9 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 --extr_r.w $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 --extr_r.w $t1, $ac1, 5 :: rt 0x0066b5a8 ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00000000 --extr_r.w $t2, $ac2, 22 :: rt 0x0000019d ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 --extr_r.w $t3, $ac3, 6 :: rt 0xfedbb7ca ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00000000 --extr_r.w $t4, $ac0, 13 :: rt 0x00025a76 ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00000000 --extr_r.w $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 --extr_r.w $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 --extr_r.w $t7, $ac3, 7 :: rt 0xff5f1efc ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00000000 --extr_r.w $t8, $ac0, 11 :: rt 0xfff0fbe9 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00000000 --extr_r.w $t0, $ac1, 26 :: rt 0xffffffeb ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 --extr_r.w $t1, $ac2, 15 :: rt 0xffffe982 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 --extr_r.w $t2, $ac3, 2 :: rt 0x001a953d ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00000000 --extr_r.w $t3, $ac0, 1 :: rt 0x3cfba24a ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 --extr_r.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 ---------- EXTR_RS.W -------- --extr_rs.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 --extr_rs.w $t5, $ac0, 3 :: rt 0x10000000 ac0 0x000000007fffffff size 3 DSPCtrl 0x00000000 --extr_rs.w $t6, $ac1, 8 :: rt 0x00000000 ac1 0x0000000000000001 size 8 DSPCtrl 0x00000000 --extr_rs.w $t7, $ac2, 16 :: rt 0x00000000 ac2 0xffffffffffffffff size 16 DSPCtrl 0x00000000 --extr_rs.w $t8, $ac3, 22 :: rt 0x00000000 ac3 0xffffffffffffffff size 2 DSPCtrl 0x00000000 --extr_rs.w $t0, $ac0, 9 :: rt 0xfffe8719 ac0 0xfffffffffd0e3126 size 9 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac2, 14 :: rt 0xfffffffd ac2 0xffffffffffff2435 size 14 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac1, 20 :: rt 0x00000555 ac1 0x0000000055555555 size 0 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac2, 16 :: rt 0xffffffff ac2 0xffffffffffff2435 size 16 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac2, 22 :: rt 0x00000000 ac2 0xffffffffffff2435 size 22 DSPCtrl 0x00000000 --extr_rs.w $t3, $ac3, 6 :: rt 0xfeaeaeaf ac3 0xffffffffabababab size 6 DSPCtrl 0x00000000 --extr_rs.w $t4, $ac0, 13 :: rt 0xffffe3ce ac0 0xfffffffffc79b4d2 size 13 DSPCtrl 0x00000000 --extr_rs.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 --extr_rs.w $t6, $ac2, 27 :: rt 0x00000000 ac2 0x0000000000000000 size 27 DSPCtrl 0x00000000 --extr_rs.w $t7, $ac3, 7 :: rt 0x00246931 ac3 0x0000000012349876 size 7 DSPCtrl 0x00000000 --extr_rs.w $t8, $ac0, 11 :: rt 0x000006a9 ac0 0x0000000000354565 size 11 DSPCtrl 0x00000000 --extr_rs.w $t0, $ac1, 26 :: rt 0xffffffe0 ac1 0xffffffff80006755 size 26 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac2, 15 :: rt 0xffff1f1f ac2 0xffffffff8f8f8f8f size 15 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac3, 2 :: rt 0xfbbbbbbc ac3 0xffffffffeeeeeeee size 2 DSPCtrl 0x00000000 --extr_rs.w $t3, $ac0, 1 :: rt 0x0dededee ac0 0x000000001bdbdbdb size 1 DSPCtrl 0x00000000 --extr_rs.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xffffffffdecadeca size 0 DSPCtrl 0x00000000 --extr_rs.w $t5, $ac0, 3 :: rt 0x0bf9252f ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 --extr_rs.w $t6, $ac1, 8 :: rt 0x007e0818 ac1 0x000000007e08184e size 8 DSPCtrl 0x00000000 --extr_rs.w $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 --extr_rs.w $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 --extr_rs.w $t0, $ac0, 9 :: rt 0xffdd9231 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac1, 5 :: rt 0x019cec6c ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac2, 14 :: rt 0x0001c25d ac2 0x0000000070974249 size 14 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac1, 20 :: rt 0xfffff8a9 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac1, 5 :: rt 0x0066b5a8 ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac2, 22 :: rt 0x0000019d ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 --extr_rs.w $t3, $ac3, 6 :: rt 0xfedbb7ca ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00000000 --extr_rs.w $t4, $ac0, 13 :: rt 0x00025a76 ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00000000 --extr_rs.w $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 --extr_rs.w $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 --extr_rs.w $t7, $ac3, 7 :: rt 0xff5f1efc ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00000000 --extr_rs.w $t8, $ac0, 11 :: rt 0xfff0fbe9 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00000000 --extr_rs.w $t0, $ac1, 26 :: rt 0xffffffeb ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac2, 15 :: rt 0xffffe982 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac3, 2 :: rt 0x001a953d ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00000000 --extr_rs.w $t3, $ac0, 1 :: rt 0x3cfba24a ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 --extr_rs.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 ---------- EXTRV_S.H -------- --extrv_s.h $t2, $ac1, $t1 :: rt 0xffff8000 ac1 0x8000000180000002 rs 0x12349876 DSPCtrl 0x00800000 --extrv_s.h $t1, $ac0, $t0 :: rt 0xffff8000 ac0 0x8000000080000000 rs 0x12349876 DSPCtrl 0x00800000 --extrv_s.h $t3, $ac2, $t2 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x00354565 DSPCtrl 0x00000000 --extrv_s.h $t4, $ac3, $t3 :: rt 0x00002200 ac3 0x0000000440000000 rs 0x00086755 DSPCtrl 0x00000000 --extrv_s.h $t5, $ac0, $t4 :: rt 0x00007fff ac0 0x7fffffff7fffffff rs 0x00000018 DSPCtrl 0x00800000 --extrv_s.h $t6, $ac1, $t5 :: rt 0xffff8000 ac1 0xffffffff00000001 rs 0x23534870 DSPCtrl 0x00800000 --extrv_s.h $t7, $ac2, $t6 :: rt 0x000007ff ac2 0x00000001ffffffff rs 0x92784656 DSPCtrl 0x00000000 --extrv_s.h $t8, $ac3, $t7 :: rt 0xffffffff ac3 0xffffffffffffffff rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv_s.h $t0, $ac0, $t8 :: rt 0x00007fff ac0 0x0000cdfe0fde3126 rs 0xcacacaca DSPCtrl 0x00800000 --extrv_s.h $t1, $ac1, $t0 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 rs 0xbacabaca DSPCtrl 0x00800000 --extrv_s.h $t2, $ac2, $t1 :: rt 0x0000031f ac2 0x00000018ffff2435 rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_s.h $t1, $ac1, $t2 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 rs 0x0cd6b508 DSPCtrl 0x00800000 --extrv_s.h $t2, $ac2, $t3 :: rt 0x00007fff ac2 0x00000018ffff2435 rs 0x6731e282 DSPCtrl 0x00800000 --extrv_s.h $t1, $ac1, $t4 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 rs 0xb6edf28f DSPCtrl 0x00800000 --extrv_s.h $t2, $ac2, $t5 :: rt 0x00007fff ac2 0x00000018ffff2435 rs 0x4b4ec9ca DSPCtrl 0x00800000 --extrv_s.h $t3, $ac3, $t6 :: rt 0xffff8000 ac3 0xbabababaabababab rs 0xc1037fa4 DSPCtrl 0x00800000 --extrv_s.h $t4, $ac0, $t7 :: rt 0xffff8000 ac0 0xf0f0f0f0fc79b4d2 rs 0xcb4ab48f DSPCtrl 0x00800000 --extrv_s.h $t5, $ac1, $t8 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xaf8f7e18 DSPCtrl 0x00000000 --extrv_s.h $t6, $ac2, $t0 :: rt 0xffff8000 ac2 0xfbde397600000000 rs 0x87df4510 DSPCtrl 0x00800000 --extrv_s.h $t7, $ac3, $t1 :: rt 0x00007fff ac3 0x0bed765412349876 rs 0xabf4e8e1 DSPCtrl 0x00800000 --extrv_s.h $t8, $ac0, $t2 :: rt 0x00007fff ac0 0x2353487000354565 rs 0xf4c0eeac DSPCtrl 0x00800000 --extrv_s.h $t0, $ac1, $t3 :: rt 0xffff8000 ac1 0x980b7cde00086755 rs 0x006a54f2 DSPCtrl 0x00800000 --extrv_s.h $t1, $ac2, $t4 :: rt 0x00007fff ac2 0x000000188f8f8f8f rs 0x79f74493 DSPCtrl 0x00800000 --extrv_s.h $t2, $ac3, $t5 :: rt 0xffff8000 ac3 0x92784656eeeeeeee rs 0x9c09e313 DSPCtrl 0x00800000 --extrv_s.h $t3, $ac0, $t6 :: rt 0xffff8000 ac0 0xcacacaca1bdbdbdb rs 0x0fde3126 DSPCtrl 0x00800000 --extrv_s.h $t4, $ac1, $t7 :: rt 0xffff8000 ac1 0xbacabacadecadeca rs 0x55555555 DSPCtrl 0x00800000 --extrv_s.h $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 --extrv_s.h $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 --extrv_s.h $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 --extrv_s.h $t8, $ac3, $t2 :: rt 0xfffffca4 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 --extrv_s.h $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 --extrv_s.h $t1, $ac1, $t4 :: rt 0x00007fff ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00800000 --extrv_s.h $t2, $ac2, $t5 :: rt 0x00001c25 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 --extrv_s.h $t1, $ac1, $t6 :: rt 0xffff8000 ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00800000 --extrv_s.h $t2, $ac2, $t7 :: rt 0xffff8000 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00800000 --extrv_s.h $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 --extrv_s.h $t2, $ac2, $t0 :: rt 0x00007fff ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00800000 --extrv_s.h $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 --extrv_s.h $t4, $ac0, $t2 :: rt 0x00007fff ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00800000 --extrv_s.h $t5, $ac1, $t3 :: rt 0xffff8000 ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00800000 --extrv_s.h $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_s.h $t7, $ac3, $t4 :: rt 0xffff8000 ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00800000 --extrv_s.h $t8, $ac0, $t5 :: rt 0xffff8000 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00800000 --extrv_s.h $t0, $ac1, $t6 :: rt 0xffff8000 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00800000 --extrv_s.h $t1, $ac2, $t7 :: rt 0xffffffff ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 --extrv_s.h $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 --extrv_s.h $t3, $ac0, $t0 :: rt 0x00007fff ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00800000 --extrv_s.h $t4, $ac1, $t1 :: rt 0xffff8000 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00800000 ---------- EXTRV.W -------- --extrv.w $t1, $ac1, $t3 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 rs 0xbababa05 DSPCtrl 0x00800000 --extrv.w $t2, $ac2, $t4 :: rt 0x0063fffc ac2 0x00000018ffff2435 rs 0xfbde390e DSPCtrl 0x00000000 --extrv.w $t1, $ac1, $t7 :: rt 0xaaaaa555 ac1 0xaaaaaaaa55555555 rs 0x55555514 DSPCtrl 0x00800000 --extrv.w $t2, $ac2, $t5 :: rt 0x0018ffff ac2 0x00000018ffff2435 rs 0x0000cd10 DSPCtrl 0x00000000 --extrv.w $t1, $ac1, $t2 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 rs 0x80000005 DSPCtrl 0x00800000 --extrv.w $t2, $ac2, $t3 :: rt 0x000063ff ac2 0x00000018ffff2435 rs 0x7fffff16 DSPCtrl 0x00000000 --extrv.w $t0, $ac0, $t1 :: rt 0x00337f83 ac0 0x0000cdfe0fde3126 rs 0xbabababa DSPCtrl 0x00000000 --extrv.w $t3, $ac3, $t2 :: rt 0xeaeaeaae ac3 0xbabababaabababab rs 0xfbde3976 DSPCtrl 0x00800000 --extrv.w $t6, $ac1, $t7 :: rt 0xfffff800 ac1 0xffffffff00000001 rs 0x55555555 DSPCtrl 0x00000000 --extrv.w $t4, $ac3, $t5 :: rt 0x00000011 ac3 0x0000000440000000 rs 0x0000cdfe DSPCtrl 0x00000000 --extrv.w $t1, $ac0, $t2 :: rt 0x80000000 ac0 0x8000000080000000 rs 0x80000000 DSPCtrl 0x00800000 --extrv.w $t2, $ac1, $t3 :: rt 0x06000000 ac1 0x8000000180000002 rs 0x00000006 DSPCtrl 0x00800000 --extrv.w $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000000 --extrv.w $t5, $ac0, $t6 :: rt 0xfdffffff ac0 0x7fffffff7fffffff rs 0x0fde3126 DSPCtrl 0x00800000 --extrv.w $t7, $ac2, $t8 :: rt 0x007fffff ac2 0x00000001ffffffff rs 0xaaaaaaaa DSPCtrl 0x00000000 --extrv.w $t8, $ac3, $t9 :: rt 0xffffffff ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 --extrv.w $t4, $ac0, $t3 :: rt 0xc3c3c3f1 ac0 0xf0f0f0f0fc79b4d2 rs 0x12349876 DSPCtrl 0x00800000 --extrv.w $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000000 --extrv.w $t6, $ac2, $t5 :: rt 0xf1cbb000 ac2 0xfbde397600000000 rs 0x00086755 DSPCtrl 0x00800000 --extrv.w $t7, $ac3, $t6 :: rt 0xed765412 ac3 0x0bed765412349876 rs 0x00000018 DSPCtrl 0x00800000 --extrv.w $t8, $ac0, $t7 :: rt 0x48700035 ac0 0x2353487000354565 rs 0x23534870 DSPCtrl 0x00800000 --extrv.w $t0, $ac1, $t8 :: rt 0x2df37800 ac1 0x980b7cde00086755 rs 0x92784656 DSPCtrl 0x00800000 --extrv.w $t1, $ac2, $t9 :: rt 0x00623e3e ac2 0x000000188f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv.w $t2, $ac3, $t1 :: rt 0x95bbbbbb ac3 0x92784656eeeeeeee rs 0xcacacaca DSPCtrl 0x00800000 --extrv.w $t3, $ac0, $t1 :: rt 0xb286f6f6 ac0 0xcacacaca1bdbdbdb rs 0xbacabaca DSPCtrl 0x00800000 --extrv.w $t4, $ac1, $t4 :: rt 0xb2b7b2b7 ac1 0xbacabacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00800000 --extrv.w $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 --extrv.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 --extrv.w $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 --extrv.w $t8, $ac3, $t2 :: rt 0xfffffca4 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 --extrv.w $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 --extrv.w $t1, $ac1, $t4 :: rt 0x000673b1 ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00000000 --extrv.w $t2, $ac2, $t5 :: rt 0x00001c25 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 --extrv.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00000000 --extrv.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00000000 --extrv.w $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 --extrv.w $t2, $ac2, $t0 :: rt 0x03398f14 ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00000000 --extrv.w $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 --extrv.w $t4, $ac0, $t2 :: rt 0x0000969d ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00000000 --extrv.w $t5, $ac1, $t3 :: rt 0xffff040d ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv.w $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv.w $t7, $ac3, $t4 :: rt 0xffaf8f7e ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 --extrv.w $t8, $ac0, $t5 :: rt 0xff87df45 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00000000 --extrv.w $t0, $ac1, $t6 :: rt 0xffd5fa74 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00000000 --extrv.w $t1, $ac2, $t7 :: rt 0xffffffff ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 --extrv.w $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 --extrv.w $t3, $ac0, $t0 :: rt 0x0079f744 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 --extrv.w $t4, $ac1, $t1 :: rt 0xe70278c4 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 ---------- EXTRV_R.W -------- --extrv_r.w $t1, $ac1, $t3 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0xbababa05 DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t4 :: rt 0xfffffffd ac2 0xffffffffffff2435 rs 0xfbde390e DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t7 :: rt 0x00000555 ac1 0x0000000055555555 rs 0x55555514 DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffff2435 rs 0x0000cd10 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t2 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0x80000005 DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t3 :: rt 0x00000000 ac2 0xffffffffffff2435 rs 0x7fffff16 DSPCtrl 0x00000000 --extrv_r.w $t0, $ac0, $t1 :: rt 0x00000004 ac0 0x000000000fde3126 rs 0xbabababa DSPCtrl 0x00000000 --extrv_r.w $t3, $ac3, $t2 :: rt 0xfffffeaf ac3 0xffffffffabababab rs 0xfbde3976 DSPCtrl 0x00000000 --extrv_r.w $t6, $ac1, $t7 :: rt 0x00000000 ac1 0x0000000000000001 rs 0x55555555 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac0, $t2 :: rt 0x80000000 ac0 0xffffffff80000000 rs 0x80000000 DSPCtrl 0x00000000 --extrv_r.w $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000000 --extrv_r.w $t5, $ac0, $t6 :: rt 0x02000000 ac0 0x000000007fffffff rs 0x0fde3126 DSPCtrl 0x00000000 --extrv_r.w $t7, $ac2, $t8 :: rt 0x00000000 ac2 0xffffffffffffffff rs 0xaaaaaaaa DSPCtrl 0x00000000 --extrv_r.w $t8, $ac3, $t9 :: rt 0x00000000 ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 --extrv_r.w $t4, $ac0, $t3 :: rt 0xfffffff2 ac0 0xfffffffffc79b4d2 rs 0x12349876 DSPCtrl 0x00000000 --extrv_r.w $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000000 --extrv_r.w $t6, $ac2, $t5 :: rt 0x00000000 ac2 0x0000000000000000 rs 0x00086755 DSPCtrl 0x00000000 --extrv_r.w $t7, $ac3, $t6 :: rt 0x00000012 ac3 0x0000000012349876 rs 0x00000018 DSPCtrl 0x00000000 --extrv_r.w $t8, $ac0, $t7 :: rt 0x00000035 ac0 0x0000000000354565 rs 0x23534870 DSPCtrl 0x00000000 --extrv_r.w $t0, $ac1, $t8 :: rt 0x00000000 ac1 0x0000000000086755 rs 0x92784656 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac2, $t9 :: rt 0xfffe3e3e ac2 0xffffffff8f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv_r.w $t2, $ac3, $t1 :: rt 0xfffbbbbc ac3 0xffffffffeeeeeeee rs 0xcacacaca DSPCtrl 0x00000000 --extrv_r.w $t3, $ac0, $t1 :: rt 0x0006f6f7 ac0 0x000000001bdbdbdb rs 0xbacabaca DSPCtrl 0x00000000 --extrv_r.w $t4, $ac1, $t4 :: rt 0xfff7b2b8 ac1 0xffffffffdecadeca rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_r.w $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 --extrv_r.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 --extrv_r.w $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 --extrv_r.w $t8, $ac3, $t2 :: rt 0xfffffca5 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 --extrv_r.w $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t4 :: rt 0x000673b2 ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t5 :: rt 0x00001c26 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t0 :: rt 0x03398f14 ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00000000 --extrv_r.w $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 --extrv_r.w $t4, $ac0, $t2 :: rt 0x0000969e ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00000000 --extrv_r.w $t5, $ac1, $t3 :: rt 0xffff040e ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv_r.w $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_r.w $t7, $ac3, $t4 :: rt 0xffaf8f7e ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 --extrv_r.w $t8, $ac0, $t5 :: rt 0xff87df45 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00000000 --extrv_r.w $t0, $ac1, $t6 :: rt 0xffd5fa74 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac2, $t7 :: rt 0x00000000 ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 --extrv_r.w $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 --extrv_r.w $t3, $ac0, $t0 :: rt 0x0079f745 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 --extrv_r.w $t4, $ac1, $t1 :: rt 0xe70278c5 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 ---------- EXTRV_RS.W -------- --extrv_rs.w $t1, $ac1, $t3 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0xbababa05 DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac2, $t4 :: rt 0xfffffffd ac2 0xffffffffffff2435 rs 0xfbde390e DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac1, $t7 :: rt 0x00000555 ac1 0x0000000055555555 rs 0x55555514 DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffff2435 rs 0x0000cd10 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac1, $t2 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0x80000005 DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac2, $t3 :: rt 0x00000000 ac2 0xffffffffffff2435 rs 0x7fffff16 DSPCtrl 0x00000000 --extrv_rs.w $t0, $ac0, $t1 :: rt 0x00000004 ac0 0x000000000fde3126 rs 0xbabababa DSPCtrl 0x00000000 --extrv_rs.w $t3, $ac3, $t2 :: rt 0xfffffeaf ac3 0xffffffffabababab rs 0xfbde3976 DSPCtrl 0x00000000 --extrv_rs.w $t6, $ac1, $t7 :: rt 0x00000000 ac1 0x0000000000000001 rs 0x55555555 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac0, $t2 :: rt 0x80000000 ac0 0xffffffff80000000 rs 0x80000000 DSPCtrl 0x00000000 --extrv_rs.w $t5, $ac0, $t6 :: rt 0x02000000 ac0 0x000000007fffffff rs 0x0fde3126 DSPCtrl 0x00000000 --extrv_rs.w $t7, $ac2, $t8 :: rt 0x00000000 ac2 0xffffffffffffffff rs 0xaaaaaaaa DSPCtrl 0x00000000 --extrv_rs.w $t8, $ac3, $t9 :: rt 0x00000000 ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 --extrv_rs.w $t4, $ac0, $t3 :: rt 0xfffffff2 ac0 0xfffffffffc79b4d2 rs 0x12349876 DSPCtrl 0x00000000 --extrv_rs.w $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000000 --extrv_rs.w $t6, $ac2, $t5 :: rt 0x00000000 ac2 0x0000000000000000 rs 0x00086755 DSPCtrl 0x00000000 --extrv_rs.w $t7, $ac3, $t6 :: rt 0x00000012 ac3 0x0000000012349876 rs 0x00000018 DSPCtrl 0x00000000 --extrv_rs.w $t8, $ac0, $t7 :: rt 0x00000035 ac0 0x0000000000354565 rs 0x23534870 DSPCtrl 0x00000000 --extrv_rs.w $t0, $ac1, $t8 :: rt 0x00000000 ac1 0x0000000000086755 rs 0x92784656 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac2, $t9 :: rt 0xfffe3e3e ac2 0xffffffff8f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac3, $t1 :: rt 0xfffbbbbc ac3 0xffffffffeeeeeeee rs 0xcacacaca DSPCtrl 0x00000000 --extrv_rs.w $t3, $ac0, $t1 :: rt 0x0006f6f7 ac0 0x000000001bdbdbdb rs 0xbacabaca DSPCtrl 0x00000000 --extrv_rs.w $t4, $ac1, $t4 :: rt 0xfff7b2b8 ac1 0xffffffffdecadeca rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_rs.w $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 --extrv_rs.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 --extrv_rs.w $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 --extrv_rs.w $t8, $ac3, $t2 :: rt 0xfffffca5 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 --extrv_rs.w $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac1, $t4 :: rt 0x000673b2 ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac2, $t5 :: rt 0x00001c26 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac2, $t0 :: rt 0x03398f14 ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00000000 --extrv_rs.w $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 --extrv_rs.w $t4, $ac0, $t2 :: rt 0x0000969e ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00000000 --extrv_rs.w $t5, $ac1, $t3 :: rt 0xffff040e ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv_rs.w $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_rs.w $t7, $ac3, $t4 :: rt 0xffaf8f7e ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 --extrv_rs.w $t8, $ac0, $t5 :: rt 0xff87df45 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00000000 --extrv_rs.w $t0, $ac1, $t6 :: rt 0xffd5fa74 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac2, $t7 :: rt 0x00000000 ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 --extrv_rs.w $t3, $ac0, $t0 :: rt 0x0079f745 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 --extrv_rs.w $t4, $ac1, $t1 :: rt 0xe70278c5 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 ---------- INSV -------- --insv :: out: 0xffffff7f rtIN 0xffffffff rsIN 0x00000000 posI 7 sizeI 1 --insv :: out: 0x004c9f31 rtIN 0x004dfbe5 rsIN 0xe87927cc posI 2 sizeI 15 --insv :: out: 0xf6a3fa1c rtIN 0xf6a3fa3c rsIN 0x083b3571 posI 4 sizeI 2 --insv :: out: 0xbf17fb9a rtIN 0xbf17fb9a rsIN 0xb9743941 posI 13 sizeI 0 --insv :: out: 0x2c0bd084 rtIN 0x2c0bd024 rsIN 0xbce5f924 posI 5 sizeI 5 --insv :: out: 0x088593c0 rtIN 0x288593c0 rsIN 0x722d5e20 posI 28 sizeI 4 --insv :: out: 0xa1d6f791 rtIN 0x4d7ff5b4 rsIN 0xa1d6f791 posI 0 sizeI 32 --insv :: out: 0x3ee7be13 rtIN 0x4557be13 rsIN 0x7b11bee7 posI 16 sizeI 15 --insv :: out: 0xadc45772 rtIN 0xadcf5772 rsIN 0xa5631488 posI 15 sizeI 7 --insv :: out: 0x9b2a7235 rtIN 0x989a7235 rsIN 0xb10bcc65 posI 19 sizeI 8 --insv :: out: 0x0d6f393a rtIN 0x4d6f393a rsIN 0x73f39fca posI 30 sizeI 1 --insv :: out: 0x2c91ca80 rtIN 0x24a3291e rsIN 0x5648e540 posI 1 sizeI 28 --insv :: out: 0xdd8deebf rtIN 0xdd91eebf rsIN 0xc54f79e6 posI 17 sizeI 5 --insv :: out: 0xf3ce2ec6 rtIN 0xf7ce2ec6 rsIN 0x5fc92974 posI 26 sizeI 2 --insv :: out: 0xbe1383e8 rtIN 0xbc1083e8 rsIN 0x7e08184e posI 14 sizeI 13 --insv :: out: 0xa6315f31 rtIN 0xa617cc31 rsIN 0x71c8315f posI 8 sizeI 17 --insv :: out: 0xdfe21cf0 rtIN 0xdfe1e8f0 rsIN 0x9493110e posI 9 sizeI 11 --insv :: out: 0x14458a23 rtIN 0x31458a23 rsIN 0xbb246228 posI 23 sizeI 9 --insv :: out: 0x85636211 rtIN 0x848af791 rsIN 0x339d8d88 posI 6 sizeI 19 --insv :: out: 0xda4bacdc rtIN 0xda3bacdc rsIN 0x70974249 posI 19 sizeI 8 --insv :: out: 0x2ff00080 rtIN 0x2fff0000 rsIN 0x00000001 posI 7 sizeI 13 --insv :: out: 0x2fd06008 rtIN 0x2fff0000 rsIN 0x73741802 posI 2 sizeI 23 --insv :: out: 0x00034030 rtIN 0x2fff0000 rsIN 0x80003403 posI 4 sizeI 28 --insv :: out: 0xab800000 rtIN 0xabababab rsIN 0x00000000 posI 0 sizeI 22 --insv :: out: 0xdecadeca rtIN 0xdecadeca rsIN 0x80000000 posI 26 sizeI 0 --insv :: out: 0xbacadaca rtIN 0xbacabaca rsIN 0x55555555 posI 12 sizeI 3 --insv :: out: 0x35fe4868 rtIN 0x3545ff80 rsIN 0xffff2434 posI 1 sizeI 23 --insv :: out: 0xc4de9620 rtIN 0xc4dbfe20 rsIN 0xfc79b4d2 posI 11 sizeI 8 --insv :: out: 0x00000000 rtIN 0x00000000 rsIN 0x00000000 posI 16 sizeI 9 --insv :: out: 0x8ceabce4 rtIN 0xad80bce4 rsIN 0x00086755 posI 13 sizeI 17 --insv :: out: 0x7f8f8f45 rtIN 0x7f003245 rsIN 0x8f8f8f8f posI 8 sizeI 18 --insv :: out: 0x980decae rtIN 0x980b7cde rsIN 0xdecadeca posI 4 sizeI 15 --DSP LWX --MEM: --0x121f1e1f, 0x00000000, 0x00000003, 0xffffffff --0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a --0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a --0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c --lwx :: out: 0x121f1e1f mem[0] --lwx :: out: 0x00000000 mem[4] --lwx :: out: 0x00000003 mem[8] --lwx :: out: 0xffffffff mem[12] --lwx :: out: 0x232f2e2f mem[16] --lwx :: out: 0x242c2b2b mem[20] --lwx :: out: 0x252a2e2b mem[24] --lwx :: out: 0x262d2d2a mem[28] --lwx :: out: 0x3f343f3e mem[32] --lwx :: out: 0x3e353d3c mem[36] --lwx :: out: 0x363a3c3b mem[40] --lwx :: out: 0x3b373b3a mem[44] --lwx :: out: 0x454f4e45 mem[48] --lwx :: out: 0x4e464d46 mem[52] --lwx :: out: 0x474d474c mem[56] --lwx :: out: 0x4a484a4c mem[60] --DSP LHX --MEM: --0x121f1e1f, 0x00000000, 0x00000003, 0xffffffff --0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a --0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a --0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c --lhx :: out: 0x00001e1f mem[0] --lhx :: out: 0x0000121f mem[2] --lhx :: out: 0x00000000 mem[4] --lhx :: out: 0x00000000 mem[6] --lhx :: out: 0x00000003 mem[8] --lhx :: out: 0x00000000 mem[10] --lhx :: out: 0xffffffff mem[12] --lhx :: out: 0xffffffff mem[14] --lhx :: out: 0x00002e2f mem[16] --lhx :: out: 0x0000232f mem[18] --lhx :: out: 0x00002b2b mem[20] --lhx :: out: 0x0000242c mem[22] --lhx :: out: 0x00002e2b mem[24] --lhx :: out: 0x0000252a mem[26] --lhx :: out: 0x00002d2a mem[28] --lhx :: out: 0x0000262d mem[30] --lhx :: out: 0x00003f3e mem[32] --lhx :: out: 0x00003f34 mem[34] --lhx :: out: 0x00003d3c mem[36] --lhx :: out: 0x00003e35 mem[38] --lhx :: out: 0x00003c3b mem[40] --lhx :: out: 0x0000363a mem[42] --lhx :: out: 0x00003b3a mem[44] --lhx :: out: 0x00003b37 mem[46] --lhx :: out: 0x00004e45 mem[48] --lhx :: out: 0x0000454f mem[50] --lhx :: out: 0x00004d46 mem[52] --lhx :: out: 0x00004e46 mem[54] --lhx :: out: 0x0000474c mem[56] --lhx :: out: 0x0000474d mem[58] --lhx :: out: 0x00004a4c mem[60] --lhx :: out: 0x00004a48 mem[62] --DSP LBUX --MEM: --0x121f1e1f, 0x00000000, 0x00000003, 0xffffffff --0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a --0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a --0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c --lbux :: out: 0x0000001f mem[0] --lbux :: out: 0x0000001e mem[1] --lbux :: out: 0x0000001f mem[2] --lbux :: out: 0x00000012 mem[3] --lbux :: out: 0x00000000 mem[4] --lbux :: out: 0x00000000 mem[5] --lbux :: out: 0x00000000 mem[6] --lbux :: out: 0x00000000 mem[7] --lbux :: out: 0x00000003 mem[8] --lbux :: out: 0x00000000 mem[9] --lbux :: out: 0x00000000 mem[10] --lbux :: out: 0x00000000 mem[11] --lbux :: out: 0x000000ff mem[12] --lbux :: out: 0x000000ff mem[13] --lbux :: out: 0x000000ff mem[14] --lbux :: out: 0x000000ff mem[15] --lbux :: out: 0x0000002f mem[16] --lbux :: out: 0x0000002e mem[17] --lbux :: out: 0x0000002f mem[18] --lbux :: out: 0x00000023 mem[19] --lbux :: out: 0x0000002b mem[20] --lbux :: out: 0x0000002b mem[21] --lbux :: out: 0x0000002c mem[22] --lbux :: out: 0x00000024 mem[23] --lbux :: out: 0x0000002b mem[24] --lbux :: out: 0x0000002e mem[25] --lbux :: out: 0x0000002a mem[26] --lbux :: out: 0x00000025 mem[27] --lbux :: out: 0x0000002a mem[28] --lbux :: out: 0x0000002d mem[29] --lbux :: out: 0x0000002d mem[30] --lbux :: out: 0x00000026 mem[31] --lbux :: out: 0x0000003e mem[32] --lbux :: out: 0x0000003f mem[33] --lbux :: out: 0x00000034 mem[34] --lbux :: out: 0x0000003f mem[35] --lbux :: out: 0x0000003c mem[36] --lbux :: out: 0x0000003d mem[37] --lbux :: out: 0x00000035 mem[38] --lbux :: out: 0x0000003e mem[39] --lbux :: out: 0x0000003b mem[40] --lbux :: out: 0x0000003c mem[41] --lbux :: out: 0x0000003a mem[42] --lbux :: out: 0x00000036 mem[43] --lbux :: out: 0x0000003a mem[44] --lbux :: out: 0x0000003b mem[45] --lbux :: out: 0x00000037 mem[46] --lbux :: out: 0x0000003b mem[47] --lbux :: out: 0x00000045 mem[48] --lbux :: out: 0x0000004e mem[49] --lbux :: out: 0x0000004f mem[50] --lbux :: out: 0x00000045 mem[51] --lbux :: out: 0x00000046 mem[52] --lbux :: out: 0x0000004d mem[53] --lbux :: out: 0x00000046 mem[54] --lbux :: out: 0x0000004e mem[55] --lbux :: out: 0x0000004c mem[56] --lbux :: out: 0x00000047 mem[57] --lbux :: out: 0x0000004d mem[58] --lbux :: out: 0x00000047 mem[59] --lbux :: out: 0x0000004c mem[60] --lbux :: out: 0x0000004a mem[61] --lbux :: out: 0x00000048 mem[62] --lbux :: out: 0x0000004a mem[63] ---------- MADD -------- --madd $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --madd $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000006 --madd $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x3fffd3d5 outLO 0x475f6ed5 --madd $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0xbfffffff --madd $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000001 --madd $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffefffe --madd $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010000 --madd $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x13f3efc6 --madd $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --madd $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x3fffffff outLO 0xffff2435 --madd $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xe38e38e3 outLO 0x1d72c81d --madd $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc6519ca --madd $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x16d18c47 outLO 0x6db2f83e --madd $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x0035137b outLO 0x307e64e0 --madd $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --madd $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x61c70995 --madd $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfffc9666 outLO 0x02062f0b --madd $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xfffffff5 outLO 0x050504f7 --madd $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x074d50a5 outLO 0x441846e2 --madd $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xfa35b12c outLO 0xdba024a9 --madd $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x08fa3aed outLO 0xa0216e2e --madd $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xf7f07860 outLO 0xa7ff27f6 --madd $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xfe1003c1 outLO 0x3efc246a --madd $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3572 --madd $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0x7a7656c1 --madd $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x07e4ad9d outLO 0x6fcbbfbe --madd $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xfcef12ea outLO 0x4e9d07d4 --madd $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xde8dfafd outLO 0x4760e93e --madd $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xd80a3262 outLO 0xca5f854f --madd $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x0d7a3e4f outLO 0x6279a4b1 --madd $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xf2bf4270 outLO 0xcabcba5f --madd $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xe71bb44a outLO 0x507e7690 --madd $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xef63cb0b outLO 0x8464cf21 --madd $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xd1d700c6 outLO 0x7d247e13 --madd $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x0528cc22 outLO 0x5cef2af5 --madd $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdc outLO 0xd548eae6 --madd $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda8 outLO 0x075646f2 --madd $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffe7a outLO 0xe0c66cc9 --madd $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --madd $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x1f7e402d outLO 0x9493110e --madd $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xee6e3c2f outLO 0x7760d0a3 --madd $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00002838 outLO 0x739d8d88 --madd $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x27924fa7 outLO 0x278c13f9 --madd $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x012837c1 outLO 0x5b8b8b0f --madd $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --madd $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x75c97282 --madd $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x877acc51 --madd $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x000031fa outLO 0xf6edf28f ---------- MADDU -------- --maddu $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --maddu $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000006 --maddu $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x40002c2b outLO 0x475f6ed5 --maddu $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0xbfffffff --maddu $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000001 --maddu $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00010000 outLO 0xfffefffe --maddu $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010000 --maddu $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x13f3efc6 --maddu $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --maddu $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x3fffffff outLO 0xffff2435 --maddu $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x38e38e38 outLO 0x1d72c81d --maddu $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0x00000017 outLO 0xfc6519ca --maddu $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x7d37f2ac outLO 0x6db2f83e --maddu $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xed9fb93d outLO 0x307e64e0 --maddu $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --maddu $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x61c70995 --maddu $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x0004fdbb outLO 0x02062f0b --maddu $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x0000000d outLO 0x050504f7 --maddu $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x88b485e9 outLO 0x441846e2 --maddu $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x16118d07 outLO 0xdba024a9 --maddu $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xa28fd481 outLO 0xa0216e2e --maddu $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x0aeb5714 outLO 0xa7ff27f6 --maddu $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x7a100b51 outLO 0x3efc246a --maddu $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0xfffffffe outLO 0x083b3572 --maddu $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0x7a7656c1 --maddu $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xaac61642 outLO 0x6fcbbfbe --maddu $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x5cb83c5e outLO 0x4e9d07d4 --maddu $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x5c96134b outLO 0x4760e93e --maddu $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x49d263c1 outLO 0xca5f854f --maddu $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x81ef384d outLO 0x6279a4b1 --maddu $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x2404cc93 outLO 0xcabcba5f --maddu $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x1ab941d2 outLO 0x507e7690 --maddu $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x5ffb0d54 outLO 0x8464cf21 --maddu $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x36745d83 outLO 0x7d247e13 --maddu $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xb10cd7d8 outLO 0x5cef2af5 --maddu $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdc outLO 0xd548eae6 --maddu $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda8 outLO 0x075646f2 --maddu $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x000003cf outLO 0xe0c66cc9 --maddu $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --maddu $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x6081bfd1 outLO 0x9493110e --maddu $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x43c39184 outLO 0x7760d0a3 --maddu $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xaf8f2838 outLO 0x739d8d88 --maddu $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x5b1d4062 outLO 0x278c13f9 --maddu $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xa996d574 outLO 0x5b8b8b0f --maddu $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --maddu $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x75c97282 --maddu $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x877acc51 --maddu $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x9c0931fa outLO 0xf6edf28f ---------- MSUB -------- --msub $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --msub $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0xffffffff outLO 0x00000006 --msub $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0xc0002c2b outLO 0x38a0912b --msub $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0xcab7743b outLO 0x3fffffff --msub $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xc0000000 outLO 0x00000001 --msub $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00010000 --msub $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xc0008000 outLO 0xbffefffe --msub $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0bc87286 --msub $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --msub $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xbfffffff outLO 0xffff2435 --msub $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x1c71c71c outLO 0x39e48f39 --msub $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc8e4fda --msub $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xe92e73b8 outLO 0x924d07c2 --msub $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffcaec84 outLO 0xcf819b20 --msub $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --msub $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xfff8a62e outLO 0x9ea38135 --msub $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00036999 outLO 0xfe0a9f9f --msub $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x0000000a outLO 0x1a1a1a27 --msub $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xf8b2af5a outLO 0x99c596fa --msub $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x05ca4ed3 outLO 0x5c17930d --msub $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xf705c512 outLO 0x1d744f66 --msub $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x080f879e outLO 0x7e8f6fc6 --msub $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x01effc3e outLO 0xb683338a --msub $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3570 --msub $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xf3a6c17c outLO 0xf8721bc1 --msub $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xf81b5262 outLO 0x0a00328a --msub $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x0310ed15 outLO 0x49db3864 --msub $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x21720502 outLO 0xf61507de --msub $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x27f5cd9e outLO 0x19fb36f1 --msub $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xf285c1af outLO 0xe1344a71 --msub $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x0d40bd90 outLO 0x2b66c36f --msub $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x18e44bb4 outLO 0xfa47b280 --msub $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x109c34f3 outLO 0xddb2c9a9 --msub $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x2e28ff3a outLO 0x6ac2c181 --msub $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xfad733de outLO 0x4fa29f8b --msub $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xf9b05322 outLO 0xb55608e6 --msub $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0xcc674258 outLO 0xb83c0bf6 --msub $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000186 outLO 0x1b49c3d3 --msub $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --msub $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xe081bfd1 outLO 0x9493110e --msub $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x1191c3cf outLO 0xfee7f3ad --msub $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffd7c7 outLO 0xf39d8d88 --msub $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0xd86db059 outLO 0xb9a27099 --msub $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xfed7c83d outLO 0xb98f11eb --msub $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --msub $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffe9df outLO 0xa3e3f78e --msub $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0xfffbff0b outLO 0x46e8f8b3 --msub $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffce04 outLO 0x76edf28f ---------- MSUBU -------- --msubu $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 --msubu $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0xffffffff outLO 0x00000006 --msubu $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0xbfffd3d5 outLO 0x38a0912b --msubu $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0xcab7743b outLO 0x3fffffff --msubu $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xc0000000 outLO 0x00000001 --msubu $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xfffeffff outLO 0x00010000 --msubu $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xc0008000 outLO 0xbffefffe --msubu $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0bc87286 --msubu $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 --msubu $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xbfffffff outLO 0xffff2435 --msubu $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xc71c71c7 outLO 0x39e48f39 --msubu $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffe7 outLO 0xfc8e4fda --msubu $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x82c80d53 outLO 0x924d07c2 --msubu $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x126046c2 outLO 0xcf819b20 --msubu $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 --msubu $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xfff8a62e outLO 0x9ea38135 --msubu $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfffb0244 outLO 0xfe0a9f9f --msubu $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xfffffff2 outLO 0x1a1a1a27 --msubu $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x774b7a16 outLO 0x99c596fa --msubu $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xe9ee72f8 outLO 0x5c17930d --msubu $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x5d702b7e outLO 0x1d744f66 --msubu $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xf514a8ea outLO 0x7e8f6fc6 --msubu $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x85eff4ae outLO 0xb683338a --msubu $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000002 outLO 0x083b3570 --msubu $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xf3a6c17c outLO 0xf8721bc1 --msubu $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x5539e9bd outLO 0x0a00328a --msubu $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xa347c3a1 outLO 0x49db3864 --msubu $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xa369ecb4 outLO 0xf61507de --msubu $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xb62d9c3f outLO 0x19fb36f1 --msubu $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x7e10c7b1 outLO 0xe1344a71 --msubu $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xdbfb336d outLO 0x2b66c36f --msubu $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xe546be2c outLO 0xfa47b280 --msubu $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xa004f2aa outLO 0xddb2c9a9 --msubu $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xc98ba27d outLO 0x6ac2c181 --msubu $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x4ef32828 outLO 0x4fa29f8b --msubu $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xf9b05322 outLO 0xb55608e6 --msubu $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0xcc674258 outLO 0xb83c0bf6 --msubu $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffc31 outLO 0x1b49c3d3 --msubu $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f --msubu $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x9f7e402d outLO 0x9493110e --msubu $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xbc3c6e7a outLO 0xfee7f3ad --msubu $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x5070d7c7 outLO 0xf39d8d88 --msubu $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0xa4e2bf9e outLO 0xb9a27099 --msubu $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x56692a8a outLO 0xb98f11eb --msubu $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 --msubu $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffe9df outLO 0xa3e3f78e --msubu $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0xfffbff0b outLO 0x46e8f8b3 --msubu $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x63f6ce04 outLO 0x76edf28f ---------- MAQ_S.W.PHR -------- --maq_s.w.phr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x4ebeddaa dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0xfffffffe dspCtrl 0x00080000 --maq_s.w.phr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0d5fae66 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x72c7e48f dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc807ec2 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x08d8c9c0 dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x277acdc5 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x64d5f6c1 dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f7a7a5f dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xe58d9ed6 dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x2ae26d77 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x7f8b040e dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfb389cda dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb0dc7441 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xac778658 dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xdb61ef8c dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x072ad9ee dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x5e31ac7e dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0x9ec451d1 dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x20afb5d7 dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xacedd898 dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x85fdd1dd dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0xacd15c5c dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x392570aa dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xb6025be6 dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x424b6470 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7d78c144 dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x88d93f1e dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0xb39d8d87 dspCtrl 0x00040000 --maq_s.w.phr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x4316e5a9 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x9821c7a1 dspCtrl 0x00000000 --maq_s.w.phr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --maq_s.w.phr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x3ae42ffc dspCtrl 0x00000000 --maq_s.w.phr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x9e8db620 dspCtrl 0x00000000 --maq_s.w.phr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x00000000 outLO 0x36edf28e dspCtrl 0x00020000 ---------- MAQ_SA.W.PHR -------- --maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x4ebeddaa dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00080000 --maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0d5fae66 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00080000 --maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc807ec2 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x08d8c9c0 dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x277acdc5 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x64d5f6c1 dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f7a7a5f dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xe58d9ed6 dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x2ae26d77 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00040000 --maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfb389cda dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb0dc7441 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xac778658 dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xdb61ef8c dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x072ad9ee dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x5e31ac7e dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0x9ec451d1 dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x20afb5d7 dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xacedd898 dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x85fdd1dd dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00020000 --maq_sa.w.phr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x392570aa dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xb6025be6 dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x424b6470 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7d78c144 dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x88d93f1e dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00040000 --maq_sa.w.phr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x4316e5a9 dspCtrl 0x00000000 --maq_sa.w.phr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x9821c7a1 dspCtrl 0x00000000 --maq_sa.w.phr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x3ae42ffc dspCtrl 0x00000000 --maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 --maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x00000000 outLO 0x36edf28e dspCtrl 0x00020000 ---------- MAQ_S.W.PHL -------- --maq_s.w.phl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0xbfffffff dspCtrl 0x00020000 --maq_s.w.phl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0xea902def dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x80000000 dspCtrl 0x00010000 --maq_s.w.phl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 --maq_s.w.phl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x72c7e48f dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x006a42e0 dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x0043e5c3 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0001e805 dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xfd8a660e dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x10476d77 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x8328ee8a dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf6dfabfa dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xd22658f1 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xccafe2a2 dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xc61a2598 dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xdbd6798e dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x22413010 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xbccc3bf7 dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x6090684f dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x739aa1cc dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x8fd2ddff dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x17a1b8bc dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x609abf70 dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xd1ee1f06 dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0xc6f95b12 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x9800854c dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339e2e6a dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0xbfbcb033 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8cde3b25 dspCtrl 0x00000000 --maq_s.w.phl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --maq_s.w.phl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd6e0ec dspCtrl 0x00000000 --maq_s.w.phl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x673981f2 dspCtrl 0x00000000 --maq_s.w.phl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6eeba7d dspCtrl 0x00000000 ---------- MAQ_SA.W.PHL -------- --maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00020000 --maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00080000 --maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 --maq_sa.w.phl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 --maq_sa.w.phl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00080000 --maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x006a42e0 dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x0043e5c3 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0001e805 dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xfd8a660e dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x10476d77 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x8328ee8a dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf6dfabfa dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xd22658f1 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xccafe2a2 dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xc61a2598 dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xdbd6798e dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x22413010 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xbccc3bf7 dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x6090684f dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00080000 --maq_sa.w.phl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x8fd2ddff dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x17a1b8bc dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x609abf70 dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xd1ee1f06 dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 --maq_sa.w.phl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x9800854c dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339e2e6a dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 --maq_sa.w.phl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8cde3b25 dspCtrl 0x00000000 --maq_sa.w.phl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd6e0ec dspCtrl 0x00000000 --maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x673981f2 dspCtrl 0x00000000 --maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6eeba7d dspCtrl 0x00000000 ---------- MTHI, MTLO, MFHI, MFLO -------- --rs_hi: 0x00000000 rs_lo: 0x00000006 ac0 out HI: 0x00000000, out LO: 0x00000006 --rs_hi: 0x00000055 rs_lo: 0x00000286 ac1 out HI: 0x00000055, out LO: 0x00000286 --rs_hi: 0x00000018 rs_lo: 0x00000fff ac2 out HI: 0x00000018, out LO: 0x00000fff --rs_hi: 0x7fffffff rs_lo: 0x7fffffff ac3 out HI: 0x7fffffff, out LO: 0x7fffffff --rs_hi: 0xffffffff rs_lo: 0x00000001 ac0 out HI: 0xffffffff, out LO: 0x00000001 --rs_hi: 0x00000001 rs_lo: 0xffffffff ac1 out HI: 0x00000001, out LO: 0xffffffff --rs_hi: 0x00000002 rs_lo: 0x00000006 ac2 out HI: 0x00000002, out LO: 0x00000006 --rs_hi: 0x00000356 rs_lo: 0x00000555 ac3 out HI: 0x00000356, out LO: 0x00000555 ---------- MODSUB -------- --modsub $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --modsub $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00045f2c --modsub $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x00002414 --modsub $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x07654bfc --modsub $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b --modsub $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ff02 --modsub $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7f00 --modsub $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c3cb --modsub $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000004 --modsub $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x80002414 --modsub $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x76548000 --modsub $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x80000000 --modsub $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ff02 --modsub $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7f00 --modsub $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c3cb --modsub $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --modsub $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 --modsub $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaaaa55 --modsub $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffffffe3 --modsub $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbababa0f --modsub $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0f01e --modsub $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 --modsub $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x2353480b --modsub $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x980b7c89 --modsub $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0xffffff89 --modsub $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x92784568 --modsub $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcacac9ef --modsub $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacaba00 --modsub $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12faddd6 --modsub $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7c000691 --modsub $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffff00 --modsub $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2f4de90 --modsub $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x435f9082 --modsub $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x2106ba4f --modsub $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x246a6295 --modsub $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1046a0f7 --modsub $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x638ca423 --modsub $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf63e7a0a --modsub $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd6845ba ---------- MTHLIP -------- --mthlip :: acIn: 0xda3bacdc70974249 rsIn 0x00000000 posIn 0x00000007 acOut 0x7097424900000000 posOut 0x00000027 --mthlip :: acIn: 0x2fff000000000001 rsIn 0xe87927cc posIn 0x00000002 acOut 0x00000001e87927cc posOut 0x00000022 --mthlip :: acIn: 0x2fff000073741802 rsIn 0x083b3571 posIn 0x00000004 acOut 0x73741802083b3571 posOut 0x00000024 --mthlip :: acIn: 0x2fff000080003403 rsIn 0xb9743941 posIn 0x0000000d acOut 0x80003403b9743941 posOut 0x0000002d --mthlip :: acIn: 0xff46000073468004 rsIn 0xbce5f924 posIn 0x00000005 acOut 0x73468004bce5f924 posOut 0x00000025 --mthlip :: acIn: 0x0000800080000000 rsIn 0xcc3c201c posIn 0x00000016 acOut 0x80000000cc3c201c posOut 0x00000036 --mthlip :: acIn: 0x00010001ffffff07 rsIn 0x1ebaf88e posIn 0x0000001f acOut 0xffffff071ebaf88e posOut 0x0000003f --mthlip :: acIn: 0x7fff7fff7fff7f07 rsIn 0x722d5e20 posIn 0x0000001c acOut 0x7fff7f07722d5e20 posOut 0x0000003c --mthlip :: acIn: 0xffffffff00000505 rsIn 0xa1d6f791 posIn 0x00000000 acOut 0x00000505a1d6f791 posOut 0x00000020 --mthlip :: acIn: 0xabababab00000000 rsIn 0x7b11bee7 posIn 0x0000001a acOut 0x000000007b11bee7 posOut 0x0000003a --mthlip :: acIn: 0xdecadeca80000000 rsIn 0xa5631488 posIn 0x0000000c acOut 0x80000000a5631488 posOut 0x0000002c --mthlip :: acIn: 0xbacabaca55555555 rsIn 0xb10bcc65 posIn 0x00000001 acOut 0x55555555b10bcc65 posOut 0x00000021 --mthlip :: acIn: 0x3545ff80ffff2434 rsIn 0x73f39fca posIn 0x0000001f acOut 0xffff243473f39fca posOut 0x0000003f --mthlip :: acIn: 0x734680bcabababa3 rsIn 0x5648e540 posIn 0x0000000b acOut 0xabababa35648e540 posOut 0x0000002b --mthlip :: acIn: 0xc4dbfe20fc79b4d2 rsIn 0xc54f79e6 posIn 0x00000010 acOut 0xfc79b4d2c54f79e6 posOut 0x00000030 --mthlip :: acIn: 0x0000000000000000 rsIn 0x5fc92974 posIn 0x0000001d acOut 0x000000005fc92974 posOut 0x0000003d --mthlip :: acIn: 0x5555555500354561 rsIn 0x7e08184e posIn 0x0000000d acOut 0x003545617e08184e posOut 0x0000002d --mthlip :: acIn: 0xad80bce400086755 rsIn 0x71c8315f posIn 0x00000008 acOut 0x0008675571c8315f posOut 0x00000028 --mthlip :: acIn: 0x7f0032458f8f8f8f rsIn 0x9493110e posIn 0x00000007 acOut 0x8f8f8f8f9493110e posOut 0x00000027 --mthlip :: acIn: 0x93474bdeeeeeeeee rsIn 0xbb246228 posIn 0x00000015 acOut 0xeeeeeeeebb246228 posOut 0x00000035 --mthlip :: acIn: 0xf97343ff1bdbdbdb rsIn 0x339d8d88 posIn 0x00000004 acOut 0x1bdbdbdb339d8d88 posOut 0x00000024 --mthlip :: acIn: 0x980b7cdedecadeca rsIn 0x70974249 posIn 0x00000020 acOut 0xdecadeca70974249 posOut 0x00000000 --mthlip :: acIn: 0x0555adec93474bde rsIn 0x339d8d88 posIn 0x00000021 acOut 0x93474bde339d8d88 posOut 0x00000001 --mthlip :: acIn: 0x000000000cd6b508 rsIn 0x12349876 posIn 0x0000000c acOut 0x0cd6b50812349876 posOut 0x0000002c --mthlip :: acIn: 0x000000006731e282 rsIn 0x00354565 posIn 0x00000001 acOut 0x6731e28200354565 posOut 0x00000021 --mthlip :: acIn: 0xffffffffb6edf28f rsIn 0x00086755 posIn 0x0000001f acOut 0xb6edf28f00086755 posOut 0x0000003f --mthlip :: acIn: 0x000000004b4ec9ca rsIn 0x8f8f8f8f posIn 0x0000000b acOut 0x4b4ec9ca8f8f8f8f posOut 0x0000002b --mthlip :: acIn: 0xffffffffc1037fa4 rsIn 0xeeeeeeee posIn 0x00000010 acOut 0xc1037fa4eeeeeeee posOut 0x00000030 --mthlip :: acIn: 0xffffffffcb4ab48f rsIn 0x1bdbdbdb posIn 0x0000001d acOut 0xcb4ab48f1bdbdbdb posOut 0x0000003d --mthlip :: acIn: 0xffffffffaf8f7e18 rsIn 0xbb246228 posIn 0x0000000d acOut 0xaf8f7e18bb246228 posOut 0x0000002d --mthlip :: acIn: 0xffffffff87df4510 rsIn 0x339d8d88 posIn 0x00000008 acOut 0x87df4510339d8d88 posOut 0x00000028 --mthlip :: acIn: 0xffffffffabf4e8e1 rsIn 0x70974249 posIn 0x00000007 acOut 0xabf4e8e170974249 posOut 0x00000027 --mthlip :: acIn: 0xfffffffff4c0eeac rsIn 0x8a8d4e7d posIn 0x00000015 acOut 0xf4c0eeac8a8d4e7d posOut 0x00000035 --mthlip :: acIn: 0x00000000006a54f2 rsIn 0xeb1b4335 posIn 0x00000004 acOut 0x006a54f2eb1b4335 posOut 0x00000024 --mthlip :: acIn: 0x0000000079f74493 rsIn 0x0cd6b508 posIn 0x00000020 acOut 0x79f744930cd6b508 posOut 0x00000000 --mthlip :: acIn: 0xffffffff9c09e313 rsIn 0x6731e282 posIn 0x00000021 acOut 0x9c09e3136731e282 posOut 0x00000001 ---------- MULEQ_S.W.PHL -------- --muleq_s.w.phl $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phl $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x7fffffff DSPCtrl 0x00200000 --muleq_s.w.phl $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x06a8c93c DSPCtrl 0x00000000 --muleq_s.w.phl $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x068d0000 DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 --muleq_s.w.phl $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7ffe0002 DSPCtrl 0x00000000 --muleq_s.w.phl $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x7fffffff DSPCtrl 0x00200000 --muleq_s.w.phl $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xc71c38e4 DSPCtrl 0x00000000 --muleq_s.w.phl $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phl $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x2da3f07c DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x006a42e0 DSPCtrl 0x00000000 --muleq_s.w.phl $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phl $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x000ea05e DSPCtrl 0x00000000 --muleq_s.w.phl $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfff980b0 DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phl $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0e9b7720 DSPCtrl 0x00000000 --muleq_s.w.phl $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xf46b919c DSPCtrl 0x00000000 --muleq_s.w.phl $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x11f51ec8 DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xefe1a2ac DSPCtrl 0x00000000 --muleq_s.w.phl $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xfc200000 DSPCtrl 0x00000000 --muleq_s.w.phl $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000002 DSPCtrl 0x00000000 --muleq_s.w.phl $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x055f6d10 DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xd5a92622 DSPCtrl 0x00000000 --muleq_s.w.phl $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xe101dc74 DSPCtrl 0x00000000 --muleq_s.w.phl $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xe8170610 DSPCtrl 0x00000000 --muleq_s.w.phl $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xfe91d900 DSPCtrl 0x00000000 --muleq_s.w.phl $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00526ff0 DSPCtrl 0x00000000 --muleq_s.w.phl $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf6b3c7a4 DSPCtrl 0x00000000 --muleq_s.w.phl $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x34021150 DSPCtrl 0x00000000 ---------- MULEQ_S.W.PHR -------- --muleq_s.w.phr $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x01e2f658 DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0ebeddaa DSPCtrl 0x00000000 --muleq_s.w.phr $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0xb3b8ae40 DSPCtrl 0x00000000 --muleq_s.w.phr $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 --muleq_s.w.phr $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7ffe0002 DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0xfd817d40 DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xc71c38e4 DSPCtrl 0x00000000 --muleq_s.w.phr $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0006c9f0 DSPCtrl 0x00000000 --muleq_s.w.phr $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x2da3f07c DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x08d8c9c0 DSPCtrl 0x00000000 --muleq_s.w.phr $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x27458860 DSPCtrl 0x00000000 --muleq_s.w.phr $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x64cd8f6c DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0xffeaead0 DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xf69eafe8 DSPCtrl 0x00000000 --muleq_s.w.phr $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x0f06919c DSPCtrl 0x00000000 --muleq_s.w.phr $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x11f51ec8 DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xec43b830 DSPCtrl 0x00000000 --muleq_s.w.phr $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x0078f0e0 DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000002 DSPCtrl 0x00000000 --muleq_s.w.phr $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x1360dca2 DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x9242b4e0 DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xda6e81e0 DSPCtrl 0x00000000 --muleq_s.w.phr $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xee08b56c DSPCtrl 0x00000000 --muleq_s.w.phr $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0cc64708 DSPCtrl 0x00000000 --muleq_s.w.phr $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0xc3a9e3b4 DSPCtrl 0x00000000 --muleq_s.w.phr $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x41b0384e DSPCtrl 0x00000000 --muleq_s.w.phr $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xf039ea6e DSPCtrl 0x00000000 ---------- MULEU_S.PH.QBL -------- --muleu_s.ph.qbl $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000a18 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0xffff0000 DSPCtrl 0x00200000 --muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xffff0000 DSPCtrl 0x00200000 --muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ffff DSPCtrl 0x00000000 --muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0xffff0000 DSPCtrl 0x00200000 --muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0xaaaa8000 rt 0x55558000 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x073fffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x04c0ffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xffff0000 DSPCtrl 0x00200000 --muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t0, $t1, $t2 :: rs 0xffffffff rt 0xcb4ab48f out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0xffffffff rt 0xaf8f7e18 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0xffffffff rt 0x87df4510 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0xffffffff rt 0xabf4e8e1 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xffffffff rt 0xf4c0eeac out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0x00000000 rt 0x006a54f2 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0x00000000 rt 0x79f74493 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0xffffffff rt 0x9c09e313 out 0xffffffff DSPCtrl 0x00200000 ---------- MULEU_S.PH.QBR -------- --muleu_s.ph.qbr $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x0000ffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xffff0000 DSPCtrl 0x00200000 --muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ffff DSPCtrl 0x00000000 --muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000aaa0 DSPCtrl 0x00000000 --muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0xaaaa8000 rt 0x55558000 out 0xffff0000 DSPCtrl 0x00200000 --muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x0ee8ffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x03e0ffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000ffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t0, $t1, $t2 :: rs 0xffffffff rt 0xcb4ab48f out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0xffffffff rt 0xaf8f7e18 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0xffffffff rt 0x87df4510 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0xffffffff rt 0xabf4e8e1 out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xffffffff rt 0xf4c0eeac out 0xffffffff DSPCtrl 0x00200000 --muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0x00000000 rt 0x006a54f2 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0x00000000 rt 0x79f74493 out 0x00000000 DSPCtrl 0x00000000 --muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0xffffffff rt 0x9c09e313 out 0xffffffff DSPCtrl 0x00200000 ---------- MULQ_RS.PH -------- --mulq_rs.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x000001e3 DSPCtrl 0x00000000 --mulq_rs.ph $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x7fff0ebf DSPCtrl 0x00200000 --mulq_rs.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x06a9b3b9 DSPCtrl 0x00000000 --mulq_rs.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x068d0000 DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --mulq_rs.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7ffe7ffe DSPCtrl 0x00000000 --mulq_rs.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000fd81 DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x7fff0000 DSPCtrl 0x00200000 --mulq_rs.ph $t4, $t1, $t5 :: rs 0xaaaa8000 rt 0x55558000 out 0xc71c7fff DSPCtrl 0x00200000 --mulq_rs.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000007 DSPCtrl 0x00000000 --mulq_rs.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x2da42da4 DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x006a08d9 DSPCtrl 0x00000000 --mulq_rs.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --mulq_rs.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x000f2746 DSPCtrl 0x00000000 --mulq_rs.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfffa64ce DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000ffeb DSPCtrl 0x00000000 --mulq_rs.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0e9bf69f DSPCtrl 0x00000000 --mulq_rs.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xf46c0f07 DSPCtrl 0x00000000 --mulq_rs.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x11f511f5 DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xefe2ec44 DSPCtrl 0x00000000 --mulq_rs.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xfc200079 DSPCtrl 0x00000000 --mulq_rs.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --mulq_rs.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x055f1361 DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xd5a99243 DSPCtrl 0x00000000 --mulq_rs.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xe102da6f DSPCtrl 0x00000000 --mulq_rs.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xe817ee09 DSPCtrl 0x00000000 --mulq_rs.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xfe920cc6 DSPCtrl 0x00000000 --mulq_rs.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x0052c3aa DSPCtrl 0x00000000 --mulq_rs.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf6b441b0 DSPCtrl 0x00000000 --mulq_rs.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x3402f03a DSPCtrl 0x00000000 ---------- MULSAQ_S.W.PH -------- --mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0xb1412255 dspCtrl 0x00020000 --mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x6a902df0 dspCtrl 0x00080000 --mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x80000000 dspCtrl 0x00010000 --mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffffff dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffffff dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x125cb3e6 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 --mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabababab dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc72eae2 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x00000000 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xf7917920 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xffffffff outLO 0xd8fe5d63 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xffffffff outLO 0x9b345899 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8fa4a4bf dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x00000000 outLO 0x06ebb626 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x0140dbdb dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdecadeca dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x96e5365a dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf666bb1a dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3571 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xdabe1df1 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xdd1e556e dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xb6f45628 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xf366982e dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x363ce1b2 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xbfdee1b7 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0xbaf2715f dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x6c0fddbc dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xbae0d887 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xffffffff outLO 0xdec3fc2a dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x7dbe3406 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xe13b3d06 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0xe4772016 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e976f58 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xca4ba856 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffffff outLO 0xb39e2e6b dspCtrl 0x00040000 --mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0xed3d0cd3 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x7f49c201 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffffff outLO 0xdec965f8 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x2fddae54 dspCtrl 0x00000000 --mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0x36eeba7e dspCtrl 0x00020000 ---------- MULT -------- --mult $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0x00000000 outLO 0x00000000 --mult $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000000 --mult $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x3fffd3d5 outLO 0x075f6ed5 --mult $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0x40000000 --mult $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000000 --mult $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffeffff --mult $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010001 --mult $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0415bea0 --mult $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x00000000 --mult $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x40000000 outLO 0x00000000 --mult $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xe38e38e3 outLO 0x71c71c72 --mult $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xffeb64f8 --mult $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x16d18c47 outLO 0x6db2f83e --mult $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x0035137b outLO 0x307e64e0 --mult $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x00000000 --mult $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x6191c430 --mult $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfffc9666 outLO 0x01fdc7b6 --mult $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xfffffff5 outLO 0x75757568 --mult $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x074d50a5 outLO 0x552957f4 --mult $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xfa35b12c outLO 0xbfc448ce --mult $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x08fa3aed outLO 0xc1568f64 --mult $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xf7f07861 outLO 0x14b7dc18 --mult $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xfe1003c1 outLO 0x443c7870 --mult $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x00000001 --mult $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0xc1021d80 --mult $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x07e4ad9d outLO 0xb2e5c69a --mult $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xfcef12ea outLO 0x8260e7b8 --mult $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xde8dfafd outLO 0x28a5f0b0 --mult $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xd80a3262 outLO 0x5832272f --mult $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x0d7a3e4f outLO 0xc0a2ad20 --mult $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xf2bf4270 outLO 0x4faafb78 --mult $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xe71bb44a outLO 0xab1b6208 --mult $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xef63cb0b outLO 0xd35902bc --mult $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xd1d700c6 outLO 0x0930de49 --mult $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x0528cc22 outLO 0x06a645b5 --mult $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdd outLO 0x0ff97100 --mult $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda7 outLO 0xa78d1d7e --mult $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffe7a outLO 0x62be547b --mult $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x00000000 --mult $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x1f7e402e outLO 0x00000000 --mult $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xee6e3c2f outLO 0xbc3c6e7b --mult $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00002838 outLO 0x40000000 --mult $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x27924fa6 outLO 0xb6f4d1b0 --mult $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x012837c1 outLO 0xd0fe3c92 --mult $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0x00000000 outLO 0x00000000 --mult $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x68f2bd7a --mult $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x2048e9cf --mult $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x000031fb outLO 0x40000000 ---------- MULTU -------- --multu $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0x00000000 outLO 0x00000000 --multu $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000000 --multu $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x40002c2b outLO 0x075f6ed5 --multu $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0x40000000 --multu $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000000 --multu $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00010000 outLO 0xfffeffff --multu $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010001 --multu $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0415bea0 --multu $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x00000000 --multu $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x40000000 outLO 0x00000000 --multu $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x38e38e38 outLO 0x71c71c72 --multu $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0x00000017 outLO 0xffeb64f8 --multu $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x7d37f2ac outLO 0x6db2f83e --multu $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xed9fb93d outLO 0x307e64e0 --multu $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x00000000 --multu $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x6191c430 --multu $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x0004fdbb outLO 0x01fdc7b6 --multu $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x0000000d outLO 0x75757568 --multu $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x88b485e9 outLO 0x552957f4 --multu $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x16118d07 outLO 0xbfc448ce --multu $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xa28fd481 outLO 0xc1568f64 --multu $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x0aeb5715 outLO 0x14b7dc18 --multu $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x7a100b51 outLO 0x443c7870 --multu $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0xfffffffe outLO 0x00000001 --multu $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0xc1021d80 --multu $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xaac61642 outLO 0xb2e5c69a --multu $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x5cb83c5e outLO 0x8260e7b8 --multu $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x5c96134b outLO 0x28a5f0b0 --multu $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x49d263c1 outLO 0x5832272f --multu $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x81ef384d outLO 0xc0a2ad20 --multu $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x2404cc93 outLO 0x4faafb78 --multu $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x1ab941d2 outLO 0xab1b6208 --multu $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x5ffb0d54 outLO 0xd35902bc --multu $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x36745d83 outLO 0x0930de49 --multu $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xb10cd7d8 outLO 0x06a645b5 --multu $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdd outLO 0x0ff97100 --multu $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda7 outLO 0xa78d1d7e --multu $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x000003cf outLO 0x62be547b --multu $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x00000000 --multu $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x6081bfd2 outLO 0x00000000 --multu $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x43c39184 outLO 0xbc3c6e7b --multu $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xaf8f2838 outLO 0x40000000 --multu $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x5b1d4061 outLO 0xb6f4d1b0 --multu $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xa996d574 outLO 0xd0fe3c92 --multu $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0x00000000 outLO 0x00000000 --multu $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x68f2bd7a --multu $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x2048e9cf --multu $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x9c0931fb outLO 0x40000000 ---------- PACKRL.PH -------- --packrl.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --packrl.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0xb2320002 --packrl.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x3435fabc --packrl.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x4cb87346 --packrl.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x437b8000 --packrl.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x0001ff01 --packrl.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff --packrl.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0xc4200000 --packrl.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --packrl.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00008000 --packrl.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaa5555 --packrl.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0018ffff --packrl.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabaabab --packrl.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0fc79 --packrl.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x39760000 --packrl.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x48700035 --packrl.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x7cde0008 --packrl.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00188f8f --packrl.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x4656eeee --packrl.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcaca1bdb --packrl.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacadeca --packrl.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xdeb49347 --packrl.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x0790fc00 --packrl.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff --packrl.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xdf1fcb4a --packrl.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x909aaf8f --packrl.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xba5f87df --packrl.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x6376abf4 --packrl.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xa1a3f4c0 --packrl.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0xa515006a --packrl.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7a9d79f7 --packrl.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x45cd9c09 ---------- PICK.QB -------- --pick.qb $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0xf973437b rt 0x807343bc out 0x807343bc DSPCtrl1 0x0 --pick.qb $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x00ff0001 rt 0x00ff0001 out 0x00ff0001 DSPCtrl1 0x3000000 --pick.qb $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 --pick.qb $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x0000c420 rt 0x00000555 out 0x0000c455 DSPCtrl1 0x2000000 --pick.qb $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 --pick.qb $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 --pick.qb $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x0 --pick.qb $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x00000520 DSPCtrl1 0x1000000 --pick.qb $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 --pick.qb $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 --pick.qb $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 --pick.qb $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x0000c420 DSPCtrl1 0x3000000 --pick.qb $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eeac DSPCtrl1 0x0 --pick.qb $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x638ca515 rt 0x006a54f2 out 0x006a54f2 DSPCtrl1 0x0 --pick.qb $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xf63e7a9d rt 0x79f74493 out 0x79f74493 DSPCtrl1 0x0 --pick.qb $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 --pick.qb $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eea3 DSPCtrl1 0x1000000 --pick.qb $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006a5415 DSPCtrl1 0x1000000 --pick.qb $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0x79f77a93 DSPCtrl1 0x2000000 --pick.qb $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 --pick.qb $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eea3 DSPCtrl1 0x1000000 --pick.qb $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006a5415 DSPCtrl1 0x1000000 --pick.qb $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0x79f77a93 DSPCtrl1 0x2000000 --pick.qb $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 --pick.qb $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x92784656 rt 0xeeeeeeee out 0xeeeeeeee DSPCtrl1 0x0 --pick.qb $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbdbdb DSPCtrl1 0x0 --pick.qb $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xbacabaca rt 0xdecadeca out 0xdecadeca DSPCtrl1 0x0 --pick.qb $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x12fadeb4 rt 0x93474bde out 0x93474bde DSPCtrl1 0x0 --pick.qb $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0xeeee46ee DSPCtrl1 0x2000000 --pick.qb $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbcaca DSPCtrl1 0x3000000 --pick.qb $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xdecabaca DSPCtrl1 0x3000000 --pick.qb $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x93474bb4 DSPCtrl1 0x1000000 --pick.qb $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0xeeee46ee DSPCtrl1 0x2000000 --pick.qb $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbcaca DSPCtrl1 0x3000000 --pick.qb $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xdecabaca DSPCtrl1 0x3000000 --pick.qb $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x93474bb4 DSPCtrl1 0x1000000 ---------- PRECEQ.W.PHL -------- --preceq.w.phl $t0, $t1 :: rd 0x00000000 rt 0x00000000 --preceq.w.phl $t2, $t3 :: rd 0x80000000 rt 0x80003286 --preceq.w.phl $t4, $t1 :: rd 0xfabc0000 rt 0xfabc2435 --preceq.w.phl $t6, $t7 :: rd 0x73460000 rt 0x73468000 --preceq.w.phl $t5, $t3 :: rd 0x80000000 rt 0x80000000 --preceq.w.phl $t2, $t4 :: rd 0xffff0000 rt 0xffffffff --preceq.w.phl $t0, $t8 :: rd 0xfff40000 rt 0xfff45fff --preceq.w.phl $t4, $t4 :: rd 0x00000000 rt 0x00000555 --preceq.w.phl $t0, $t1 :: rd 0x00000000 rt 0x00005340 --preceq.w.phl $t2, $t3 :: rd 0x80000000 rt 0x80000000 --preceq.w.phl $t4, $t1 :: rd 0x55550000 rt 0x55555555 --preceq.w.phl $t6, $t7 :: rd 0xffff0000 rt 0xffff2435 --preceq.w.phl $t5, $t3 :: rd 0xabab0000 rt 0xabababab --preceq.w.phl $t2, $t4 :: rd 0xfc790000 rt 0xfc79b4d2 --preceq.w.phl $t0, $t8 :: rd 0x00000000 rt 0x00000000 --preceq.w.phl $t4, $t4 :: rd 0x00350000 rt 0x00354565 --preceq.w.phl $t0, $t1 :: rd 0x00080000 rt 0x00086755 --preceq.w.phl $t2, $t3 :: rd 0x8f8f0000 rt 0x8f8f8f8f --preceq.w.phl $t4, $t1 :: rd 0xeeee0000 rt 0xeeeeeeee --preceq.w.phl $t6, $t7 :: rd 0x1bdb0000 rt 0x1bdbdbdb --preceq.w.phl $t5, $t3 :: rd 0xdeca0000 rt 0xdecadeca --preceq.w.phl $t2, $t4 :: rd 0x93470000 rt 0x93474bde --preceq.w.phl $t0, $t8 :: rd 0xfc000000 rt 0xfc0007ff --preceq.w.phl $t4, $t4 :: rd 0xffff0000 rt 0xffffffff --preceq.w.phl $t0, $t1 :: rd 0xcb4a0000 rt 0xcb4ab48f --preceq.w.phl $t2, $t3 :: rd 0xaf8f0000 rt 0xaf8f7e18 --preceq.w.phl $t4, $t1 :: rd 0x87df0000 rt 0x87df4510 --preceq.w.phl $t6, $t7 :: rd 0xabf40000 rt 0xabf4e8e1 --preceq.w.phl $t5, $t3 :: rd 0xf4c00000 rt 0xf4c0eeac --preceq.w.phl $t2, $t4 :: rd 0x006a0000 rt 0x006a54f2 --preceq.w.phl $t0, $t8 :: rd 0x79f70000 rt 0x79f74493 --preceq.w.phl $t4, $t4 :: rd 0x9c090000 rt 0x9c09e313 ---------- PICK.PH -------- --pick.ph $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0xf973437b rt 0x807343bc out 0x807343bc DSPCtrl1 0x0 --pick.ph $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x00ff0001 rt 0x00ff0001 out 0x00ff0001 DSPCtrl1 0x3000000 --pick.ph $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 --pick.ph $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x0000c420 rt 0x00000555 out 0x00000555 DSPCtrl1 0x2000000 --pick.ph $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 --pick.ph $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 --pick.ph $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x0 --pick.ph $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x0000c420 DSPCtrl1 0x1000000 --pick.ph $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 --pick.ph $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 --pick.ph $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 --pick.ph $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x0000c420 DSPCtrl1 0x3000000 --pick.ph $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eeac DSPCtrl1 0x0 --pick.ph $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x638ca515 rt 0x006a54f2 out 0x006a54f2 DSPCtrl1 0x0 --pick.ph $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xf63e7a9d rt 0x79f74493 out 0x79f74493 DSPCtrl1 0x0 --pick.ph $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 --pick.ph $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0a1a3 DSPCtrl1 0x1000000 --pick.ph $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006aa515 DSPCtrl1 0x1000000 --pick.ph $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0xf63e4493 DSPCtrl1 0x2000000 --pick.ph $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 --pick.ph $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0a1a3 DSPCtrl1 0x1000000 --pick.ph $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006aa515 DSPCtrl1 0x1000000 --pick.ph $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0xf63e4493 DSPCtrl1 0x2000000 --pick.ph $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 --pick.ph $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x92784656 rt 0xeeeeeeee out 0xeeeeeeee DSPCtrl1 0x0 --pick.ph $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbdbdb DSPCtrl1 0x0 --pick.ph $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xbacabaca rt 0xdecadeca out 0xdecadeca DSPCtrl1 0x0 --pick.ph $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x12fadeb4 rt 0x93474bde out 0x93474bde DSPCtrl1 0x0 --pick.ph $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0x9278eeee DSPCtrl1 0x2000000 --pick.ph $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0xcacacaca DSPCtrl1 0x3000000 --pick.ph $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xbacabaca DSPCtrl1 0x3000000 --pick.ph $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x9347deb4 DSPCtrl1 0x1000000 --pick.ph $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0x9278eeee DSPCtrl1 0x2000000 --pick.ph $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0xcacacaca DSPCtrl1 0x3000000 --pick.ph $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xbacabaca DSPCtrl1 0x3000000 --pick.ph $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x9347deb4 DSPCtrl1 0x1000000 ---------- PRECEQ.W.PHR -------- --preceq.w.phr $t0, $t1 :: rd 0x00000000 rt 0x00000000 --preceq.w.phr $t2, $t3 :: rd 0x32860000 rt 0x80003286 --preceq.w.phr $t4, $t1 :: rd 0x24350000 rt 0xfabc2435 --preceq.w.phr $t6, $t7 :: rd 0x80000000 rt 0x73468000 --preceq.w.phr $t5, $t3 :: rd 0x00000000 rt 0x80000000 --preceq.w.phr $t2, $t4 :: rd 0xffff0000 rt 0xffffffff --preceq.w.phr $t0, $t8 :: rd 0x5fff0000 rt 0xfff45fff --preceq.w.phr $t4, $t4 :: rd 0x05550000 rt 0x00000555 --preceq.w.phr $t0, $t1 :: rd 0x53400000 rt 0x00005340 --preceq.w.phr $t2, $t3 :: rd 0x00000000 rt 0x80000000 --preceq.w.phr $t4, $t1 :: rd 0x55550000 rt 0x55555555 --preceq.w.phr $t6, $t7 :: rd 0x24350000 rt 0xffff2435 --preceq.w.phr $t5, $t3 :: rd 0xabab0000 rt 0xabababab --preceq.w.phr $t2, $t4 :: rd 0xb4d20000 rt 0xfc79b4d2 --preceq.w.phr $t0, $t8 :: rd 0x00000000 rt 0x00000000 --preceq.w.phr $t4, $t4 :: rd 0x45650000 rt 0x00354565 --preceq.w.phr $t0, $t1 :: rd 0x67550000 rt 0x00086755 --preceq.w.phr $t2, $t3 :: rd 0x8f8f0000 rt 0x8f8f8f8f --preceq.w.phr $t4, $t1 :: rd 0xeeee0000 rt 0xeeeeeeee --preceq.w.phr $t6, $t7 :: rd 0xdbdb0000 rt 0x1bdbdbdb --preceq.w.phr $t5, $t3 :: rd 0xdeca0000 rt 0xdecadeca --preceq.w.phr $t2, $t4 :: rd 0x4bde0000 rt 0x93474bde --preceq.w.phr $t0, $t8 :: rd 0x07ff0000 rt 0xfc0007ff --preceq.w.phr $t4, $t4 :: rd 0xffff0000 rt 0xffffffff --preceq.w.phr $t0, $t1 :: rd 0xb48f0000 rt 0xcb4ab48f --preceq.w.phr $t2, $t3 :: rd 0x7e180000 rt 0xaf8f7e18 --preceq.w.phr $t4, $t1 :: rd 0x45100000 rt 0x87df4510 --preceq.w.phr $t6, $t7 :: rd 0xe8e10000 rt 0xabf4e8e1 --preceq.w.phr $t5, $t3 :: rd 0xeeac0000 rt 0xf4c0eeac --preceq.w.phr $t2, $t4 :: rd 0x54f20000 rt 0x006a54f2 --preceq.w.phr $t0, $t8 :: rd 0x44930000 rt 0x79f74493 --preceq.w.phr $t4, $t4 :: rd 0xe3130000 rt 0x9c09e313 ---------- PRECEQU.PH.QBL -------- --precequ.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbl $t2, $t3 :: rd 0x40000000 rt 0x80003286 --precequ.ph.qbl $t4, $t1 :: rd 0x7d005e00 rt 0xfabc2435 --precequ.ph.qbl $t6, $t7 :: rd 0x39802300 rt 0x73468000 --precequ.ph.qbl $t5, $t3 :: rd 0x40000000 rt 0x80000000 --precequ.ph.qbl $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbl $t0, $t8 :: rd 0x7f807a00 rt 0xfff45fff --precequ.ph.qbl $t4, $t4 :: rd 0x00000000 rt 0x00000555 --precequ.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00005340 --precequ.ph.qbl $t2, $t3 :: rd 0x40000000 rt 0x80000000 --precequ.ph.qbl $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 --precequ.ph.qbl $t6, $t7 :: rd 0x7f807f80 rt 0xffff2435 --precequ.ph.qbl $t5, $t3 :: rd 0x55805580 rt 0xabababab --precequ.ph.qbl $t2, $t4 :: rd 0x7e003c80 rt 0xfc79b4d2 --precequ.ph.qbl $t0, $t8 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbl $t4, $t4 :: rd 0x00001a80 rt 0x00354565 --precequ.ph.qbl $t0, $t1 :: rd 0x00000400 rt 0x00086755 --precequ.ph.qbl $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f --precequ.ph.qbl $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee --precequ.ph.qbl $t6, $t7 :: rd 0x0d806d80 rt 0x1bdbdbdb --precequ.ph.qbl $t5, $t3 :: rd 0x6f006500 rt 0xdecadeca --precequ.ph.qbl $t2, $t4 :: rd 0x49802380 rt 0x93474bde --precequ.ph.qbl $t0, $t8 :: rd 0x7e000000 rt 0xfc0007ff --precequ.ph.qbl $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbl $t0, $t1 :: rd 0x65802500 rt 0xcb4ab48f --precequ.ph.qbl $t2, $t3 :: rd 0x57804780 rt 0xaf8f7e18 --precequ.ph.qbl $t4, $t1 :: rd 0x43806f80 rt 0x87df4510 --precequ.ph.qbl $t6, $t7 :: rd 0x55807a00 rt 0xabf4e8e1 --precequ.ph.qbl $t5, $t3 :: rd 0x7a006000 rt 0xf4c0eeac --precequ.ph.qbl $t2, $t4 :: rd 0x00003500 rt 0x006a54f2 --precequ.ph.qbl $t0, $t8 :: rd 0x3c807b80 rt 0x79f74493 --precequ.ph.qbl $t4, $t4 :: rd 0x4e000480 rt 0x9c09e313 ---------- PRECEQU.PH.QBLA -------- --precequ.ph.qbla $t0, $t1 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbla $t2, $t3 :: rd 0x40001900 rt 0x80003286 --precequ.ph.qbla $t4, $t1 :: rd 0x7d001200 rt 0xfabc2435 --precequ.ph.qbla $t6, $t7 :: rd 0x39804000 rt 0x73468000 --precequ.ph.qbla $t5, $t3 :: rd 0x40000000 rt 0x80000000 --precequ.ph.qbla $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbla $t0, $t8 :: rd 0x7f802f80 rt 0xfff45fff --precequ.ph.qbla $t4, $t4 :: rd 0x00000280 rt 0x00000555 --precequ.ph.qbla $t0, $t1 :: rd 0x00002980 rt 0x00005340 --precequ.ph.qbla $t2, $t3 :: rd 0x40000000 rt 0x80000000 --precequ.ph.qbla $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 --precequ.ph.qbla $t6, $t7 :: rd 0x7f801200 rt 0xffff2435 --precequ.ph.qbla $t5, $t3 :: rd 0x55805580 rt 0xabababab --precequ.ph.qbla $t2, $t4 :: rd 0x7e005a00 rt 0xfc79b4d2 --precequ.ph.qbla $t0, $t8 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbla $t4, $t4 :: rd 0x00002280 rt 0x00354565 --precequ.ph.qbla $t0, $t1 :: rd 0x00003380 rt 0x00086755 --precequ.ph.qbla $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f --precequ.ph.qbla $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee --precequ.ph.qbla $t6, $t7 :: rd 0x0d806d80 rt 0x1bdbdbdb --precequ.ph.qbla $t5, $t3 :: rd 0x6f006f00 rt 0xdecadeca --precequ.ph.qbla $t2, $t4 :: rd 0x49802580 rt 0x93474bde --precequ.ph.qbla $t0, $t8 :: rd 0x7e000380 rt 0xfc0007ff --precequ.ph.qbla $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbla $t0, $t1 :: rd 0x65805a00 rt 0xcb4ab48f --precequ.ph.qbla $t2, $t3 :: rd 0x57803f00 rt 0xaf8f7e18 --precequ.ph.qbla $t4, $t1 :: rd 0x43802280 rt 0x87df4510 --precequ.ph.qbla $t6, $t7 :: rd 0x55807400 rt 0xabf4e8e1 --precequ.ph.qbla $t5, $t3 :: rd 0x7a007700 rt 0xf4c0eeac --precequ.ph.qbla $t2, $t4 :: rd 0x00002a00 rt 0x006a54f2 --precequ.ph.qbla $t0, $t8 :: rd 0x3c802200 rt 0x79f74493 --precequ.ph.qbla $t4, $t4 :: rd 0x4e007180 rt 0x9c09e313 ---------- PRECEQU.PH.QBR -------- --precequ.ph.qbr $t0, $t1 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbr $t2, $t3 :: rd 0x19004300 rt 0x80003286 --precequ.ph.qbr $t4, $t1 :: rd 0x12001a80 rt 0xfabc2435 --precequ.ph.qbr $t6, $t7 :: rd 0x40000000 rt 0x73468000 --precequ.ph.qbr $t5, $t3 :: rd 0x00000000 rt 0x80000000 --precequ.ph.qbr $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbr $t0, $t8 :: rd 0x2f807f80 rt 0xfff45fff --precequ.ph.qbr $t4, $t4 :: rd 0x02802a80 rt 0x00000555 --precequ.ph.qbr $t0, $t1 :: rd 0x29802000 rt 0x00005340 --precequ.ph.qbr $t2, $t3 :: rd 0x00000000 rt 0x80000000 --precequ.ph.qbr $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 --precequ.ph.qbr $t6, $t7 :: rd 0x12001a80 rt 0xffff2435 --precequ.ph.qbr $t5, $t3 :: rd 0x55805580 rt 0xabababab --precequ.ph.qbr $t2, $t4 :: rd 0x5a006900 rt 0xfc79b4d2 --precequ.ph.qbr $t0, $t8 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbr $t4, $t4 :: rd 0x22803280 rt 0x00354565 --precequ.ph.qbr $t0, $t1 :: rd 0x33802a80 rt 0x00086755 --precequ.ph.qbr $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f --precequ.ph.qbr $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee --precequ.ph.qbr $t6, $t7 :: rd 0x6d806d80 rt 0x1bdbdbdb --precequ.ph.qbr $t5, $t3 :: rd 0x6f006500 rt 0xdecadeca --precequ.ph.qbr $t2, $t4 :: rd 0x25806f00 rt 0x93474bde --precequ.ph.qbr $t0, $t8 :: rd 0x03807f80 rt 0xfc0007ff --precequ.ph.qbr $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbr $t0, $t1 :: rd 0x5a004780 rt 0xcb4ab48f --precequ.ph.qbr $t2, $t3 :: rd 0x3f000c00 rt 0xaf8f7e18 --precequ.ph.qbr $t4, $t1 :: rd 0x22800800 rt 0x87df4510 --precequ.ph.qbr $t6, $t7 :: rd 0x74007080 rt 0xabf4e8e1 --precequ.ph.qbr $t5, $t3 :: rd 0x77005600 rt 0xf4c0eeac --precequ.ph.qbr $t2, $t4 :: rd 0x2a007900 rt 0x006a54f2 --precequ.ph.qbr $t0, $t8 :: rd 0x22004980 rt 0x79f74493 --precequ.ph.qbr $t4, $t4 :: rd 0x71800980 rt 0x9c09e313 ---------- PRECEQU.PH.QBRA -------- --precequ.ph.qbra $t0, $t1 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbra $t2, $t3 :: rd 0x00004300 rt 0x80003286 --precequ.ph.qbra $t4, $t1 :: rd 0x5e001a80 rt 0xfabc2435 --precequ.ph.qbra $t6, $t7 :: rd 0x23000000 rt 0x73468000 --precequ.ph.qbra $t5, $t3 :: rd 0x00000000 rt 0x80000000 --precequ.ph.qbra $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbra $t0, $t8 :: rd 0x7a007f80 rt 0xfff45fff --precequ.ph.qbra $t4, $t4 :: rd 0x00002a80 rt 0x00000555 --precequ.ph.qbra $t0, $t1 :: rd 0x00002000 rt 0x00005340 --precequ.ph.qbra $t2, $t3 :: rd 0x00000000 rt 0x80000000 --precequ.ph.qbra $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 --precequ.ph.qbra $t6, $t7 :: rd 0x7f801a80 rt 0xffff2435 --precequ.ph.qbra $t5, $t3 :: rd 0x55805580 rt 0xabababab --precequ.ph.qbra $t2, $t4 :: rd 0x3c806900 rt 0xfc79b4d2 --precequ.ph.qbra $t0, $t8 :: rd 0x00000000 rt 0x00000000 --precequ.ph.qbra $t4, $t4 :: rd 0x1a803280 rt 0x00354565 --precequ.ph.qbra $t0, $t1 :: rd 0x04002a80 rt 0x00086755 --precequ.ph.qbra $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f --precequ.ph.qbra $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee --precequ.ph.qbra $t6, $t7 :: rd 0x6d806d80 rt 0x1bdbdbdb --precequ.ph.qbra $t5, $t3 :: rd 0x65006500 rt 0xdecadeca --precequ.ph.qbra $t2, $t4 :: rd 0x23806f00 rt 0x93474bde --precequ.ph.qbra $t0, $t8 :: rd 0x00007f80 rt 0xfc0007ff --precequ.ph.qbra $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff --precequ.ph.qbra $t0, $t1 :: rd 0x25004780 rt 0xcb4ab48f --precequ.ph.qbra $t2, $t3 :: rd 0x47800c00 rt 0xaf8f7e18 --precequ.ph.qbra $t4, $t1 :: rd 0x6f800800 rt 0x87df4510 --precequ.ph.qbra $t6, $t7 :: rd 0x7a007080 rt 0xabf4e8e1 --precequ.ph.qbra $t5, $t3 :: rd 0x60005600 rt 0xf4c0eeac --precequ.ph.qbra $t2, $t4 :: rd 0x35007900 rt 0x006a54f2 --precequ.ph.qbra $t0, $t8 :: rd 0x7b804980 rt 0x79f74493 --precequ.ph.qbra $t4, $t4 :: rd 0x04800980 rt 0x9c09e313 ---------- PRECEU.PH.QBL -------- --preceu.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbl $t2, $t3 :: rd 0x00800000 rt 0x80003286 --preceu.ph.qbl $t4, $t1 :: rd 0x00fa00bc rt 0xfabc2435 --preceu.ph.qbl $t6, $t7 :: rd 0x00730046 rt 0x73468000 --preceu.ph.qbl $t5, $t3 :: rd 0x00800000 rt 0x80000000 --preceu.ph.qbl $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbl $t0, $t8 :: rd 0x00ff00f4 rt 0xfff45fff --preceu.ph.qbl $t4, $t4 :: rd 0x00000000 rt 0x00000555 --preceu.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00005340 --preceu.ph.qbl $t2, $t3 :: rd 0x00800000 rt 0x80000000 --preceu.ph.qbl $t4, $t1 :: rd 0x00550055 rt 0x55555555 --preceu.ph.qbl $t6, $t7 :: rd 0x00ff00ff rt 0xffff2435 --preceu.ph.qbl $t5, $t3 :: rd 0x00ab00ab rt 0xabababab --preceu.ph.qbl $t2, $t4 :: rd 0x00fc0079 rt 0xfc79b4d2 --preceu.ph.qbl $t0, $t8 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbl $t4, $t4 :: rd 0x00000035 rt 0x00354565 --preceu.ph.qbl $t0, $t1 :: rd 0x00000008 rt 0x00086755 --preceu.ph.qbl $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f --preceu.ph.qbl $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee --preceu.ph.qbl $t6, $t7 :: rd 0x001b00db rt 0x1bdbdbdb --preceu.ph.qbl $t5, $t3 :: rd 0x00de00ca rt 0xdecadeca --preceu.ph.qbl $t2, $t4 :: rd 0x00930047 rt 0x93474bde --preceu.ph.qbl $t0, $t8 :: rd 0x00fc0000 rt 0xfc0007ff --preceu.ph.qbl $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbl $t0, $t1 :: rd 0x00cb004a rt 0xcb4ab48f --preceu.ph.qbl $t2, $t3 :: rd 0x00af008f rt 0xaf8f7e18 --preceu.ph.qbl $t4, $t1 :: rd 0x008700df rt 0x87df4510 --preceu.ph.qbl $t6, $t7 :: rd 0x00ab00f4 rt 0xabf4e8e1 --preceu.ph.qbl $t5, $t3 :: rd 0x00f400c0 rt 0xf4c0eeac --preceu.ph.qbl $t2, $t4 :: rd 0x0000006a rt 0x006a54f2 --preceu.ph.qbl $t0, $t8 :: rd 0x007900f7 rt 0x79f74493 --preceu.ph.qbl $t4, $t4 :: rd 0x009c0009 rt 0x9c09e313 ---------- PRECEU.PH.QBLA -------- --preceu.ph.qbla $t0, $t1 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbla $t2, $t3 :: rd 0x00800032 rt 0x80003286 --preceu.ph.qbla $t4, $t1 :: rd 0x00fa0024 rt 0xfabc2435 --preceu.ph.qbla $t6, $t7 :: rd 0x00730080 rt 0x73468000 --preceu.ph.qbla $t5, $t3 :: rd 0x00800000 rt 0x80000000 --preceu.ph.qbla $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbla $t0, $t8 :: rd 0x00ff005f rt 0xfff45fff --preceu.ph.qbla $t4, $t4 :: rd 0x00000005 rt 0x00000555 --preceu.ph.qbla $t0, $t1 :: rd 0x00000053 rt 0x00005340 --preceu.ph.qbla $t2, $t3 :: rd 0x00800000 rt 0x80000000 --preceu.ph.qbla $t4, $t1 :: rd 0x00550055 rt 0x55555555 --preceu.ph.qbla $t6, $t7 :: rd 0x00ff0024 rt 0xffff2435 --preceu.ph.qbla $t5, $t3 :: rd 0x00ab00ab rt 0xabababab --preceu.ph.qbla $t2, $t4 :: rd 0x00fc00b4 rt 0xfc79b4d2 --preceu.ph.qbla $t0, $t8 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbla $t4, $t4 :: rd 0x00000045 rt 0x00354565 --preceu.ph.qbla $t0, $t1 :: rd 0x00000067 rt 0x00086755 --preceu.ph.qbla $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f --preceu.ph.qbla $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee --preceu.ph.qbla $t6, $t7 :: rd 0x001b00db rt 0x1bdbdbdb --preceu.ph.qbla $t5, $t3 :: rd 0x00de00de rt 0xdecadeca --preceu.ph.qbla $t2, $t4 :: rd 0x0093004b rt 0x93474bde --preceu.ph.qbla $t0, $t8 :: rd 0x00fc0007 rt 0xfc0007ff --preceu.ph.qbla $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbla $t0, $t1 :: rd 0x00cb00b4 rt 0xcb4ab48f --preceu.ph.qbla $t2, $t3 :: rd 0x00af007e rt 0xaf8f7e18 --preceu.ph.qbla $t4, $t1 :: rd 0x00870045 rt 0x87df4510 --preceu.ph.qbla $t6, $t7 :: rd 0x00ab00e8 rt 0xabf4e8e1 --preceu.ph.qbla $t5, $t3 :: rd 0x00f400ee rt 0xf4c0eeac --preceu.ph.qbla $t2, $t4 :: rd 0x00000054 rt 0x006a54f2 --preceu.ph.qbla $t0, $t8 :: rd 0x00790044 rt 0x79f74493 --preceu.ph.qbla $t4, $t4 :: rd 0x009c00e3 rt 0x9c09e313 ---------- PRECEU.PH.QBR -------- --preceu.ph.qbr $t0, $t1 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbr $t2, $t3 :: rd 0x00320086 rt 0x80003286 --preceu.ph.qbr $t4, $t1 :: rd 0x00240035 rt 0xfabc2435 --preceu.ph.qbr $t6, $t7 :: rd 0x00800000 rt 0x73468000 --preceu.ph.qbr $t5, $t3 :: rd 0x00000000 rt 0x80000000 --preceu.ph.qbr $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbr $t0, $t8 :: rd 0x005f00ff rt 0xfff45fff --preceu.ph.qbr $t4, $t4 :: rd 0x00050055 rt 0x00000555 --preceu.ph.qbr $t0, $t1 :: rd 0x00530040 rt 0x00005340 --preceu.ph.qbr $t2, $t3 :: rd 0x00000000 rt 0x80000000 --preceu.ph.qbr $t4, $t1 :: rd 0x00550055 rt 0x55555555 --preceu.ph.qbr $t6, $t7 :: rd 0x00240035 rt 0xffff2435 --preceu.ph.qbr $t5, $t3 :: rd 0x00ab00ab rt 0xabababab --preceu.ph.qbr $t2, $t4 :: rd 0x00b400d2 rt 0xfc79b4d2 --preceu.ph.qbr $t0, $t8 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbr $t4, $t4 :: rd 0x00450065 rt 0x00354565 --preceu.ph.qbr $t0, $t1 :: rd 0x00670055 rt 0x00086755 --preceu.ph.qbr $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f --preceu.ph.qbr $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee --preceu.ph.qbr $t6, $t7 :: rd 0x00db00db rt 0x1bdbdbdb --preceu.ph.qbr $t5, $t3 :: rd 0x00de00ca rt 0xdecadeca --preceu.ph.qbr $t2, $t4 :: rd 0x004b00de rt 0x93474bde --preceu.ph.qbr $t0, $t8 :: rd 0x000700ff rt 0xfc0007ff --preceu.ph.qbr $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbr $t0, $t1 :: rd 0x00b4008f rt 0xcb4ab48f --preceu.ph.qbr $t2, $t3 :: rd 0x007e0018 rt 0xaf8f7e18 --preceu.ph.qbr $t4, $t1 :: rd 0x00450010 rt 0x87df4510 --preceu.ph.qbr $t6, $t7 :: rd 0x00e800e1 rt 0xabf4e8e1 --preceu.ph.qbr $t5, $t3 :: rd 0x00ee00ac rt 0xf4c0eeac --preceu.ph.qbr $t2, $t4 :: rd 0x005400f2 rt 0x006a54f2 --preceu.ph.qbr $t0, $t8 :: rd 0x00440093 rt 0x79f74493 --preceu.ph.qbr $t4, $t4 :: rd 0x00e30013 rt 0x9c09e313 ---------- PRECEU.PH.QBRA -------- --preceu.ph.qbra $t0, $t1 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbra $t2, $t3 :: rd 0x00000086 rt 0x80003286 --preceu.ph.qbra $t4, $t1 :: rd 0x00bc0035 rt 0xfabc2435 --preceu.ph.qbra $t6, $t7 :: rd 0x00460000 rt 0x73468000 --preceu.ph.qbra $t5, $t3 :: rd 0x00000000 rt 0x80000000 --preceu.ph.qbra $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbra $t0, $t8 :: rd 0x00f400ff rt 0xfff45fff --preceu.ph.qbra $t4, $t4 :: rd 0x00000055 rt 0x00000555 --preceu.ph.qbra $t0, $t1 :: rd 0x00000040 rt 0x00005340 --preceu.ph.qbra $t2, $t3 :: rd 0x00000000 rt 0x80000000 --preceu.ph.qbra $t4, $t1 :: rd 0x00550055 rt 0x55555555 --preceu.ph.qbra $t6, $t7 :: rd 0x00ff0035 rt 0xffff2435 --preceu.ph.qbra $t5, $t3 :: rd 0x00ab00ab rt 0xabababab --preceu.ph.qbra $t2, $t4 :: rd 0x007900d2 rt 0xfc79b4d2 --preceu.ph.qbra $t0, $t8 :: rd 0x00000000 rt 0x00000000 --preceu.ph.qbra $t4, $t4 :: rd 0x00350065 rt 0x00354565 --preceu.ph.qbra $t0, $t1 :: rd 0x00080055 rt 0x00086755 --preceu.ph.qbra $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f --preceu.ph.qbra $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee --preceu.ph.qbra $t6, $t7 :: rd 0x00db00db rt 0x1bdbdbdb --preceu.ph.qbra $t5, $t3 :: rd 0x00ca00ca rt 0xdecadeca --preceu.ph.qbra $t2, $t4 :: rd 0x004700de rt 0x93474bde --preceu.ph.qbra $t0, $t8 :: rd 0x000000ff rt 0xfc0007ff --preceu.ph.qbra $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff --preceu.ph.qbra $t0, $t1 :: rd 0x004a008f rt 0xcb4ab48f --preceu.ph.qbra $t2, $t3 :: rd 0x008f0018 rt 0xaf8f7e18 --preceu.ph.qbra $t4, $t1 :: rd 0x00df0010 rt 0x87df4510 --preceu.ph.qbra $t6, $t7 :: rd 0x00f400e1 rt 0xabf4e8e1 --preceu.ph.qbra $t5, $t3 :: rd 0x00c000ac rt 0xf4c0eeac --preceu.ph.qbra $t2, $t4 :: rd 0x006a00f2 rt 0x006a54f2 --preceu.ph.qbra $t0, $t8 :: rd 0x00f70093 rt 0x79f74493 --preceu.ph.qbra $t4, $t4 :: rd 0x00090013 rt 0x9c09e313 ---------- PRECRQ.QB.PH -------- --precrq.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --precrq.qb.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x04b20086 --precrq.qb.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfa34fa34 --precrq.qb.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x074c7380 --precrq.qb.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf9438000 --precrq.qb.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x0000ffff --precrq.qb.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7f7f7f7f --precrq.qb.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00c40005 --precrq.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --precrq.qb.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80008000 --precrq.qb.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaa5555 --precrq.qb.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ff24 --precrq.qb.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabaabab --precrq.qb.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0fcb4 --precrq.qb.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfb390000 --precrq.qb.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23480045 --precrq.qb.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x987c0067 --precrq.qb.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00008f8f --precrq.qb.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x9246eeee --precrq.qb.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcaca1bdb --precrq.qb.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbabadede --precrq.qb.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12de934b --precrq.qb.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7c07fc07 --precrq.qb.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff --precrq.qb.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2dfcbb4 --precrq.qb.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x4390af7e --precrq.qb.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x21ba8745 --precrq.qb.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x2463abe8 --precrq.qb.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x10a1f4ee --precrq.qb.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63a50054 --precrq.qb.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf67a7944 --precrq.qb.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd459ce3 ---------- PRECRQ.PH.W -------- --precrq.ph.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --precrq.ph.w $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x045f0002 --precrq.ph.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfabcfabc --precrq.ph.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x07657346 --precrq.ph.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf9738000 --precrq.ph.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00ffff01 --precrq.ph.w $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff --precrq.ph.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 --precrq.ph.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --precrq.ph.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80008000 --precrq.ph.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaa5555 --precrq.ph.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ffff --precrq.ph.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabaabab --precrq.ph.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0fc79 --precrq.ph.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde0000 --precrq.ph.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23530035 --precrq.ph.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x980b0008 --precrq.ph.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00008f8f --precrq.ph.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x9278eeee --precrq.ph.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcaca1bdb --precrq.ph.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacadeca --precrq.ph.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12fa9347 --precrq.ph.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7c00fc00 --precrq.ph.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff --precrq.ph.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2f4cb4a --precrq.ph.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x435faf8f --precrq.ph.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x210687df --precrq.ph.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x246aabf4 --precrq.ph.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1046f4c0 --precrq.ph.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x638c006a --precrq.ph.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf63e79f7 --precrq.ph.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd689c09 ---------- PRECRQ_RS.PH.W -------- --precrq_rs.ph.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x04600003 DSPCtrl 0x00000000 --precrq_rs.ph.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfabcfabc DSPCtrl 0x00000000 --precrq_rs.ph.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x07657347 DSPCtrl 0x00000000 --precrq_rs.ph.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf9738000 DSPCtrl 0x00000000 --precrq_rs.ph.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00ffff02 DSPCtrl 0x00000000 --precrq_rs.ph.w $t0, $t8, $t0 :: rs 0x7fffd004 rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00400000 --precrq_rs.ph.w $t0, $t8, $t0 :: rs 0x7fffd004 rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00400000 --precrq_rs.ph.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00010000 DSPCtrl 0x00000000 --precrq_rs.ph.w $t0, $t1, $t2 :: rs 0x7fff8000 rt 0xffff8000 out 0x7fff0000 DSPCtrl 0x00400000 --precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80008000 DSPCtrl 0x00000000 --precrq_rs.ph.w $t4, $t1, $t5 :: rs 0x7fffaaaa rt 0x55555555 out 0x7fff5555 DSPCtrl 0x00400000 --precrq_rs.ph.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ffff DSPCtrl 0x00000000 --precrq_rs.ph.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabbabac DSPCtrl 0x00000000 --precrq_rs.ph.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f1fc7a DSPCtrl 0x00000000 --precrq_rs.ph.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde0000 DSPCtrl 0x00000000 --precrq_rs.ph.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23530035 DSPCtrl 0x00000000 --precrq_rs.ph.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x980b0008 DSPCtrl 0x00000000 --precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00008f90 DSPCtrl 0x00000000 --precrq_rs.ph.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x9278eeef DSPCtrl 0x00000000 --precrq_rs.ph.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcacb1bdc DSPCtrl 0x00000000 --precrq_rs.ph.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacbdecb DSPCtrl 0x00000000 --precrq_rs.ph.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12fb9347 DSPCtrl 0x00000000 --precrq_rs.ph.w $t0, $t8, $t0 :: rs 0x7fffffff rt 0xfc0007ff out 0x7ffffc00 DSPCtrl 0x00400000 --precrq_rs.ph.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --precrq_rs.ph.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2f5cb4b DSPCtrl 0x00000000 --precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x4360af8f DSPCtrl 0x00000000 --precrq_rs.ph.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x210787df DSPCtrl 0x00000000 --precrq_rs.ph.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x246aabf5 DSPCtrl 0x00000000 --precrq_rs.ph.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1047f4c1 DSPCtrl 0x00000000 --precrq_rs.ph.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x638d006a DSPCtrl 0x00000000 --precrq_rs.ph.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf63e79f7 DSPCtrl 0x00000000 --precrq_rs.ph.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd689c0a DSPCtrl 0x00000000 ---------- PRECRQU_S.QB.PH -------- --precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x08000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00680068 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0e99e600 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00860000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0xffe0ffff DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000a DSPCtrl 0x00400000 --precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x0000aaaa DSPCtrl 0x00400000 --precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000048 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00720000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x4690008a DSPCtrl 0x00000000 --precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00f900ce DSPCtrl 0x00400000 --precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x008c0000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00003700 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x00000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x25000097 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xf80f000f DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x860000fc DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x4200008a DSPCtrl 0x00400000 --precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x48c60000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x20000000 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0xc70000a9 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00f5f389 DSPCtrl 0x00400000 --precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x008b0000 DSPCtrl 0x00400000 ---------- RADDU.W.QB -------- --raddu.w.qb $t3, $t2 :: out 0x00000154 rs 0x55555555 --raddu.w.qb $t4, $t1 :: out 0x00000257 rs 0xffff2435 --raddu.w.qb $t7, $t2 :: out 0x00000154 rs 0x55555555 --raddu.w.qb $t5, $t1 :: out 0x00000257 rs 0xffff2435 --raddu.w.qb $t2, $t2 :: out 0x00000144 rs 0x55435755 --raddu.w.qb $t3, $t1 :: out 0x00000257 rs 0xffff2435 --raddu.w.qb $t1, $t2 :: out 0x00000144 rs 0x0fde3126 --raddu.w.qb $t2, $t0 :: out 0x000002ac rs 0xabababab --raddu.w.qb $t7, $t3 :: out 0x00000001 rs 0x00000001 --raddu.w.qb $t5, $t6 :: out 0x00000040 rs 0x40000000 --raddu.w.qb $t2, $t4 :: out 0x00000080 rs 0x80000000 --raddu.w.qb $t6, $t1 :: out 0x0000037c rs 0x7fffffff --raddu.w.qb $t8, $t5 :: out 0x0000012e rs 0x23534870 --raddu.w.qb $t9, $t7 :: out 0x000003fc rs 0xffffffff --raddu.w.qb $t3, $t8 :: out 0x000002fb rs 0xfc79b4d2 --raddu.w.qb $t4, $t4 :: out 0x00000000 rs 0x00000000 --raddu.w.qb $t5, $t5 :: out 0x00000000 rs 0x00000000 --raddu.w.qb $t6, $t6 :: out 0x00000154 rs 0x12349876 --raddu.w.qb $t7, $t7 :: out 0x000000df rs 0x00354565 --raddu.w.qb $t8, $t8 :: out 0x000000c4 rs 0x00086755 --raddu.w.qb $t9, $t0 :: out 0x0000023c rs 0x8f8f8f8f --raddu.w.qb $t1, $t1 :: out 0x000003b8 rs 0xeeeeeeee --raddu.w.qb $t1, $t2 :: out 0x000002ac rs 0x1bdbdbdb --raddu.w.qb $t4, $t3 :: out 0x00000350 rs 0xdecadeca --raddu.w.qb $t8, $t4 :: out 0x000001c5 rs 0x5fc92974 --raddu.w.qb $t0, $t5 :: out 0x000000ec rs 0x7e08184e --raddu.w.qb $t1, $t6 :: out 0x000001c9 rs 0x71c8315f --raddu.w.qb $t2, $t7 :: out 0x00000146 rs 0x9493110e --raddu.w.qb $t3, $t8 :: out 0x00000169 rs 0xbb246228 --raddu.w.qb $t4, $t0 :: out 0x000001e5 rs 0x339d8d88 --raddu.w.qb $t5, $t1 :: out 0x00000192 rs 0x70974249 --raddu.w.qb $t6, $t2 :: out 0x000001e2 rs 0x8a8d4e7d --raddu.w.qb $t7, $t1 :: out 0x0000017e rs 0xeb1b4335 --raddu.w.qb $t8, $t2 :: out 0x0000019f rs 0x0cd6b508 --raddu.w.qb $t0, $t1 :: out 0x000001fc rs 0x6731e282 --raddu.w.qb $t1, $t2 :: out 0x00000324 rs 0xb6edf28f --raddu.w.qb $t2, $t3 :: out 0x0000022c rs 0x4b4ec9ca --raddu.w.qb $t3, $t4 :: out 0x000001e7 rs 0xc1037fa4 --raddu.w.qb $t3, $t5 :: out 0x00000258 rs 0xcb4ab48f --raddu.w.qb $t4, $t6 :: out 0x000001d4 rs 0xaf8f7e18 --raddu.w.qb $t4, $t6 :: out 0x000001d4 rs 0xaf8f7e18 ---------- RDDSP/WRDSP -------- --outVal 0x05051512 inVal 0x35055512 mask 0x0000001f --outVal 0x00000000 inVal 0x00000000 mask 0x00000002 --outVal 0x00002000 inVal 0x80003286 mask 0x00000004 --outVal 0x00bc0000 inVal 0xfabc2435 mask 0x00000008 --outVal 0x03000000 inVal 0x73468000 mask 0x00000016 --outVal 0x00000000 inVal 0x80000000 mask 0x00000020 --outVal 0x00005f80 inVal 0xffffffff mask 0x00000022 --outVal 0x0ff45fbf inVal 0xfff45fff mask 0x0000003f --outVal 0x00000515 inVal 0x00000555 mask 0x00000013 --outVal 0x03000000 inVal 0x23534870 mask 0x00000014 --outVal 0x05000000 inVal 0x0555adec mask 0x00000010 --outVal 0x0800201e inVal 0x980b7cde mask 0x00000015 --outVal 0x0900003b inVal 0xf973437b mask 0x00000011 --outVal 0x00000b9e inVal 0x93474bde mask 0x00000007 --outVal 0x00550015 inVal 0x55555555 mask 0x00000009 --outVal 0x00003e00 inVal 0xc4dbfe20 mask 0x00000006 --outVal 0x00000000 inVal 0x734680bc mask 0x00000000 --outVal 0x00000525 inVal 0x00354565 mask 0x00000003 --outVal 0x0000000a inVal 0xbacabaca mask 0x00000021 --outVal 0x0e001e80 inVal 0xdecadeca mask 0x00000016 --outVal 0x00000006 inVal 0x00000286 mask 0x00000001 --outVal 0x00002b80 inVal 0xabababab mask 0x00000026 ---------- REPL.PH -------- --repl.ph $t0, 0 :: rd 0x00000000 imm 0x00000000 --repl.ph $t1, 1 :: rd 0x00010001 imm 0x00000001 --repl.ph $t2, -1 :: rd 0xffffffff imm 0xffffffff --repl.ph $t3, -129 :: rd 0xff7fff7f imm 0xffffff7f --repl.ph $t4, -2 :: rd 0xfffefffe imm 0xfffffffe --repl.ph $t0, 0x123 :: rd 0x01230123 imm 0x00000123 --repl.ph $t1, 0x07b :: rd 0x007b007b imm 0x0000007b --repl.ph $t2, 0x1c8 :: rd 0x01c801c8 imm 0x000001c8 --repl.ph $t3, 0x080 :: rd 0x00800080 imm 0x00000080 --repl.ph $t4, 0x07f :: rd 0x007f007f imm 0x0000007f --repl.ph $t5, 0x1ff :: rd 0x01ff01ff imm 0x000001ff --repl.ph $t6, 0x000 :: rd 0x00000000 imm 0x00000000 --repl.ph $t7, 0x177 :: rd 0x01770177 imm 0x00000177 --repl.ph $t0, 0x1de :: rd 0x01de01de imm 0x000001de --repl.ph $t1, 0x018 :: rd 0x00180018 imm 0x00000018 --repl.ph $t2, 0x056 :: rd 0x00560056 imm 0x00000056 --repl.ph $t3, 0x1ca :: rd 0x01ca01ca imm 0x000001ca --repl.ph $t4, 0x1ab :: rd 0x01ab01ab imm 0x000001ab --repl.ph $t5, 0x1d2 :: rd 0x01d201d2 imm 0x000001d2 --repl.ph $t6, 0x000 :: rd 0x00000000 imm 0x00000000 --repl.ph $t7, 0x065 :: rd 0x00650065 imm 0x00000065 --repl.ph $t0, 0x055 :: rd 0x00550055 imm 0x00000055 --repl.ph $t1, 0x08f :: rd 0x008f008f imm 0x0000008f --repl.ph $t2, 0x0ee :: rd 0x00ee00ee imm 0x000000ee --repl.ph $t3, 0x1db :: rd 0x01db01db imm 0x000001db --repl.ph $t4, 0x1ca :: rd 0x01ca01ca imm 0x000001ca --repl.ph $t5, 0x1de :: rd 0x01de01de imm 0x000001de --repl.ph $t6, 0x0ff :: rd 0x00ff00ff imm 0x000000ff --repl.ph $t7, 0x0ff :: rd 0x00ff00ff imm 0x000000ff --repl.ph $t0, 0x08f :: rd 0x008f008f imm 0x0000008f --repl.ph $t1, 0x118 :: rd 0x01180118 imm 0x00000118 --repl.ph $t2, 0x110 :: rd 0x01100110 imm 0x00000110 --repl.ph $t3, 0x1e1 :: rd 0x01e101e1 imm 0x000001e1 --repl.ph $t4, 0x1ac :: rd 0x01ac01ac imm 0x000001ac --repl.ph $t5, 0x0f2 :: rd 0x00f200f2 imm 0x000000f2 --repl.ph $t6, 0x093 :: rd 0x00930093 imm 0x00000093 --repl.ph $t7, 0x013 :: rd 0x00130013 imm 0x00000013 ---------- REPL.QB -------- --repl.qb $t0, 0x23 :: rd 0x23232323 imm 0x00000023 --repl.qb $t1, 0x7b :: rd 0x7b7b7b7b imm 0x0000007b --repl.qb $t2, 0xc8 :: rd 0xc8c8c8c8 imm 0x000000c8 --repl.qb $t3, 0x80 :: rd 0x80808080 imm 0x00000080 --repl.qb $t4, 0x7f :: rd 0x7f7f7f7f imm 0x0000007f --repl.qb $t5, 0xff :: rd 0xffffffff imm 0x000000ff --repl.qb $t6, 0x00 :: rd 0x00000000 imm 0x00000000 --repl.qb $t7, 0x77 :: rd 0x77777777 imm 0x00000077 --repl.qb $t0, 0xde :: rd 0xdededede imm 0x000000de --repl.qb $t1, 0x18 :: rd 0x18181818 imm 0x00000018 --repl.qb $t2, 0x56 :: rd 0x56565656 imm 0x00000056 --repl.qb $t3, 0xca :: rd 0xcacacaca imm 0x000000ca --repl.qb $t4, 0xab :: rd 0xabababab imm 0x000000ab --repl.qb $t5, 0xd2 :: rd 0xd2d2d2d2 imm 0x000000d2 --repl.qb $t6, 0x00 :: rd 0x00000000 imm 0x00000000 --repl.qb $t7, 0x65 :: rd 0x65656565 imm 0x00000065 --repl.qb $t0, 0x55 :: rd 0x55555555 imm 0x00000055 --repl.qb $t1, 0x8f :: rd 0x8f8f8f8f imm 0x0000008f --repl.qb $t2, 0xee :: rd 0xeeeeeeee imm 0x000000ee --repl.qb $t3, 0xdb :: rd 0xdbdbdbdb imm 0x000000db --repl.qb $t4, 0xca :: rd 0xcacacaca imm 0x000000ca --repl.qb $t5, 0xde :: rd 0xdededede imm 0x000000de --repl.qb $t6, 0xff :: rd 0xffffffff imm 0x000000ff --repl.qb $t7, 0xff :: rd 0xffffffff imm 0x000000ff --repl.qb $t0, 0x8f :: rd 0x8f8f8f8f imm 0x0000008f --repl.qb $t1, 0x18 :: rd 0x18181818 imm 0x00000018 --repl.qb $t2, 0x10 :: rd 0x10101010 imm 0x00000010 --repl.qb $t3, 0xe1 :: rd 0xe1e1e1e1 imm 0x000000e1 --repl.qb $t4, 0xac :: rd 0xacacacac imm 0x000000ac --repl.qb $t5, 0xf2 :: rd 0xf2f2f2f2 imm 0x000000f2 --repl.qb $t6, 0x93 :: rd 0x93939393 imm 0x00000093 --repl.qb $t7, 0x13 :: rd 0x13131313 imm 0x00000013 ---------- REPLV.PH -------- --replv.ph $t0, $t1 :: rd 0x00000000 rt 0x00000000 --replv.ph $t2, $t3 :: rd 0x32863286 rt 0x80003286 --replv.ph $t4, $t1 :: rd 0x24352435 rt 0xfabc2435 --replv.ph $t6, $t7 :: rd 0x80008000 rt 0x73468000 --replv.ph $t5, $t3 :: rd 0x00000000 rt 0x80000000 --replv.ph $t2, $t4 :: rd 0xffffffff rt 0xffffffff --replv.ph $t0, $t8 :: rd 0x5fff5fff rt 0xfff45fff --replv.ph $t4, $t4 :: rd 0x05550555 rt 0x00000555 --replv.ph $t0, $t1 :: rd 0x53405340 rt 0x00005340 --replv.ph $t2, $t3 :: rd 0x00000000 rt 0x80000000 --replv.ph $t4, $t1 :: rd 0x55555555 rt 0x55555555 --replv.ph $t6, $t7 :: rd 0x24352435 rt 0xffff2435 --replv.ph $t5, $t3 :: rd 0xabababab rt 0xabababab --replv.ph $t2, $t4 :: rd 0xb4d2b4d2 rt 0xfc79b4d2 --replv.ph $t0, $t8 :: rd 0x00000000 rt 0x00000000 --replv.ph $t4, $t4 :: rd 0x45654565 rt 0x00354565 --replv.ph $t0, $t1 :: rd 0x67556755 rt 0x00086755 --replv.ph $t2, $t3 :: rd 0x8f8f8f8f rt 0x8f8f8f8f --replv.ph $t4, $t1 :: rd 0xeeeeeeee rt 0xeeeeeeee --replv.ph $t6, $t7 :: rd 0xdbdbdbdb rt 0x1bdbdbdb --replv.ph $t5, $t3 :: rd 0xdecadeca rt 0xdecadeca --replv.ph $t2, $t4 :: rd 0x4bde4bde rt 0x93474bde --replv.ph $t0, $t8 :: rd 0x07ff07ff rt 0xfc0007ff --replv.ph $t4, $t4 :: rd 0xffffffff rt 0xffffffff --replv.ph $t0, $t1 :: rd 0xb48fb48f rt 0xcb4ab48f --replv.ph $t2, $t3 :: rd 0x7e187e18 rt 0xaf8f7e18 --replv.ph $t4, $t1 :: rd 0x45104510 rt 0x87df4510 --replv.ph $t6, $t7 :: rd 0xe8e1e8e1 rt 0xabf4e8e1 --replv.ph $t5, $t3 :: rd 0xeeaceeac rt 0xf4c0eeac --replv.ph $t2, $t4 :: rd 0x54f254f2 rt 0x006a54f2 --replv.ph $t0, $t8 :: rd 0x44934493 rt 0x79f74493 --replv.ph $t4, $t4 :: rd 0xe313e313 rt 0x9c09e313 ---------- REPLV.QB -------- --replv.qb $t0, $t1 :: rd 0x00000000 rt 0x00000000 --replv.qb $t2, $t3 :: rd 0x86868686 rt 0x80003286 --replv.qb $t4, $t1 :: rd 0x35353535 rt 0xfabc2435 --replv.qb $t6, $t7 :: rd 0x00000000 rt 0x73468000 --replv.qb $t5, $t3 :: rd 0x00000000 rt 0x80000000 --replv.qb $t2, $t4 :: rd 0xffffffff rt 0xffffffff --replv.qb $t0, $t8 :: rd 0xffffffff rt 0xfff45fff --replv.qb $t4, $t4 :: rd 0x55555555 rt 0x00000555 --replv.qb $t0, $t1 :: rd 0x40404040 rt 0x00005340 --replv.qb $t2, $t3 :: rd 0x00000000 rt 0x80000000 --replv.qb $t4, $t1 :: rd 0x55555555 rt 0x55555555 --replv.qb $t6, $t7 :: rd 0x35353535 rt 0xffff2435 --replv.qb $t5, $t3 :: rd 0xabababab rt 0xabababab --replv.qb $t2, $t4 :: rd 0xd2d2d2d2 rt 0xfc79b4d2 --replv.qb $t0, $t8 :: rd 0x00000000 rt 0x00000000 --replv.qb $t4, $t4 :: rd 0x65656565 rt 0x00354565 --replv.qb $t0, $t1 :: rd 0x55555555 rt 0x00086755 --replv.qb $t2, $t3 :: rd 0x8f8f8f8f rt 0x8f8f8f8f --replv.qb $t4, $t1 :: rd 0xeeeeeeee rt 0xeeeeeeee --replv.qb $t6, $t7 :: rd 0xdbdbdbdb rt 0x1bdbdbdb --replv.qb $t5, $t3 :: rd 0xcacacaca rt 0xdecadeca --replv.qb $t2, $t4 :: rd 0xdededede rt 0x93474bde --replv.qb $t0, $t8 :: rd 0xffffffff rt 0xfc0007ff --replv.qb $t4, $t4 :: rd 0xffffffff rt 0xffffffff --replv.qb $t0, $t1 :: rd 0x8f8f8f8f rt 0xcb4ab48f --replv.qb $t2, $t3 :: rd 0x18181818 rt 0xaf8f7e18 --replv.qb $t4, $t1 :: rd 0x10101010 rt 0x87df4510 --replv.qb $t6, $t7 :: rd 0xe1e1e1e1 rt 0xabf4e8e1 --replv.qb $t5, $t3 :: rd 0xacacacac rt 0xf4c0eeac --replv.qb $t2, $t4 :: rd 0xf2f2f2f2 rt 0x006a54f2 --replv.qb $t0, $t8 :: rd 0x93939393 rt 0x79f74493 --replv.qb $t4, $t4 :: rd 0x13131313 rt 0x9c09e313 ---------- SHILO -------- --shilo ac3, -5 inAcc = 0x980b7cde0243ade5 outAcc = 0x016f9bc04875bca0 --shilo ac0, 12 inAcc = 0x8000328600002340 outAcc = 0x0008000328600002 --shilo ac1, 7 inAcc = 0x235348700bca3470 outAcc = 0x0046a690e0179468 --shilo ac2, 3 inAcc = 0x0555adec1245bef6 outAcc = 0x00aab5bd8248b7de --shilo ac3, -5 inAcc = 0x980b7cde0243ade5 outAcc = 0x016f9bc04875bca0 --shilo ac0, -13 inAcc = 0xf97343ff0bce2434 outAcc = 0x687fe179c4868000 --shilo ac1, 31 inAcc = 0x93474bde0bcde433 outAcc = 0x00000001268e97bc --shilo ac2, -32 inAcc = 0x7f003245000432fe outAcc = 0x000432fe00000000 --shilo ac3, 8 inAcc = 0xad80bce40241bce0 outAcc = 0x00ad80bce40241bc --shilo ac0, 20 inAcc = 0x55555555bcdea87a outAcc = 0x0000055555555bcd --shilo ac1, 22 inAcc = 0x0000000000000007 outAcc = 0x0000000000000000 --shilo ac2, -19 inAcc = 0xc4dbfe20000023b6 outAcc = 0xf10000011db00000 --shilo ac3, 16 inAcc = 0x734680bc000deab5 outAcc = 0x0000734680bc000d --shilo ac0, -2 inAcc = 0x3545ff8000000004 outAcc = 0xd517fe0000000010 --shilo ac1, -4 inAcc = 0xbacabaca00000003 outAcc = 0xacabaca000000030 --shilo ac2, -18 inAcc = 0xdecadeca00000002 outAcc = 0x7b28000000080000 --shilo ac3, 0 inAcc = 0xabababab00000001 outAcc = 0xabababab00000001 --shilo ac0, 1 inAcc = 0xffffffff00000000 outAcc = 0x7fffffff80000000 --shilo ac1, 30 inAcc = 0x7fff7fff0bce3457 outAcc = 0x00000001fffdfffc --shilo ac2, -30 inAcc = 0x0001000100ca6ced outAcc = 0x40329b3b40000000 --shilo ac3, -24 inAcc = 0x000000805bc34109 outAcc = 0x805bc34109000000 --shilo ac0, 5 inAcc = 0xff4600004bacd342 outAcc = 0x07fa3000025d669a --shilo ac1, 9 inAcc = 0x2fff000003bcde24 outAcc = 0x0017ff800001de6f --shilo ac2, 16 inAcc = 0x2fff000002234379 outAcc = 0x00002fff00000223 --shilo ac3, -12 inAcc = 0x2fff000001098789 outAcc = 0xf000001098789000 ---------- SHILOV -------- --shilov ac3, rs 0x01098789 inAcc = 0x980b7cde0243ade5 outAcc = 0x004c05be6f0121d6 --shilov ac0, rs 0x0241bce0 inAcc = 0x8000328600002340 outAcc = 0x0000234000000000 --shilov ac1, rs 0xc4dbfe20 inAcc = 0x235348700bca3470 outAcc = 0x0bca347000000000 --shilov ac2, rs 0x93474bde inAcc = 0x0555adec1245bef6 outAcc = 0x000000001556b7b0 --shilov ac3, rs 0x7f003245 inAcc = 0x980b7cde0243ade5 outAcc = 0x04c05be6f0121d6f --shilov ac0, rs 0x0241bce0 inAcc = 0xf97343ff0bce2434 outAcc = 0x0bce243400000000 --shilov ac1, rs 0x0bce3457 inAcc = 0x93474bde0bcde433 outAcc = 0x000001268e97bc17 --shilov ac2, rs 0xbacabaca inAcc = 0x7f003245000432fe outAcc = 0x001fc00c9140010c --shilov ac3, rs 0x734680bc inAcc = 0xad80bce40241bce0 outAcc = 0xd80bce40241bce00 --shilov ac0, rs 0x3545ff80 inAcc = 0x55555555bcdea87a outAcc = 0x55555555bcdea87a --shilov ac1, rs 0x7fff7fff inAcc = 0x0000000000000007 outAcc = 0x000000000000000e --shilov ac2, rs 0xc4dbfe20 inAcc = 0xc4dbfe20000023b6 outAcc = 0x000023b600000000 --shilov ac3, rs 0x00000010 inAcc = 0x734680bc000deab5 outAcc = 0x0000734680bc000d --shilov ac0, rs 0xfffffffe inAcc = 0x3545ff8000000004 outAcc = 0xd517fe0000000010 --shilov ac1, rs 0xfffffffc inAcc = 0xbacabaca00000003 outAcc = 0xacabaca000000030 --shilov ac2, rs 0xffffffee inAcc = 0xdecadeca00000002 outAcc = 0x7b28000000080000 --shilov ac3, rs 0x00000000 inAcc = 0xabababab00000001 outAcc = 0xabababab00000001 --shilov ac0, rs 0x00000001 inAcc = 0xffffffff00000000 outAcc = 0x7fffffff80000000 --shilov ac1, rs 0x0000001e inAcc = 0x7fff7fff0bce3457 outAcc = 0x00000001fffdfffc --shilov ac2, rs 0xffffffe2 inAcc = 0x0001000100ca6ced outAcc = 0x40329b3b40000000 --shilov ac3, rs 0xffffffe8 inAcc = 0x000000805bc34109 outAcc = 0x805bc34109000000 --shilov ac0, rs 0xffffffe0 inAcc = 0xff4600004bacd342 outAcc = 0x4bacd34200000000 --shilov ac1, rs 0x0000001f inAcc = 0x2fff000003bcde24 outAcc = 0x000000005ffe0000 --shilov ac2, rs 0x00000010 inAcc = 0x2fff000002234379 outAcc = 0x00002fff00000223 --shilov ac3, rs 0xfffffff4 inAcc = 0x2fff000001098789 outAcc = 0xf000001098789000 ---------- SHLL.PH -------- --shll.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 DSPCtrl 0x00000000 --shll.ph $t2, $t3, 1 :: rd 0x5ffe0000 rt 0x2fff0000 sa 1 DSPCtrl 0x00000000 --shll.ph $t4, $t1, 2 :: rd 0xbffc0000 rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 --shll.ph $t6, $t7, 3 :: rd 0x7ff80000 rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 --shll.ph $t5, $t3, 4 :: rd 0x00000000 rt 0x80000000 sa 4 DSPCtrl 0x00400000 --shll.ph $t2, $t4, 5 :: rd 0xe020ffe0 rt 0xff01ffff sa 5 DSPCtrl 0x00000000 --shll.ph $t0, $t8, 6 :: rd 0xffc0ffc0 rt 0x7fff7fff sa 6 DSPCtrl 0x00400000 --shll.ph $t4, $t6, 7 :: rd 0x0000aa80 rt 0x00000555 sa 7 DSPCtrl 0x00400000 --shll.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 DSPCtrl 0x00000000 --shll.ph $t2, $t3, 9 :: rd 0x00000000 rt 0x80000000 sa 9 DSPCtrl 0x00400000 --shll.ph $t4, $t1, 10 :: rd 0x54005400 rt 0x55555555 sa 10 DSPCtrl 0x00400000 --shll.ph $t6, $t7, 11 :: rd 0xf800a800 rt 0xffff2435 sa 11 DSPCtrl 0x00400000 --shll.ph $t5, $t3, 12 :: rd 0xb000b000 rt 0xabababab sa 12 DSPCtrl 0x00400000 --shll.ph $t2, $t4, 13 :: rd 0x20004000 rt 0xfc79b4d2 sa 13 DSPCtrl 0x00400000 --shll.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 DSPCtrl 0x00000000 --shll.ph $t4, $t6, 15 :: rd 0x80008000 rt 0x00354565 sa 15 DSPCtrl 0x00400000 --shll.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 DSPCtrl 0x00000000 --shll.ph $t2, $t3, 1 :: rd 0x1f1e1f1e rt 0x8f8f8f8f sa 1 DSPCtrl 0x00400000 --shll.ph $t4, $t1, 2 :: rd 0xbbb8bbb8 rt 0xeeeeeeee sa 2 DSPCtrl 0x00000000 --shll.ph $t6, $t7, 3 :: rd 0xded8ded8 rt 0x1bdbdbdb sa 3 DSPCtrl 0x00400000 --shll.ph $t5, $t3, 4 :: rd 0xeca0eca0 rt 0xdecadeca sa 4 DSPCtrl 0x00400000 --shll.ph $t2, $t4, 5 :: rd 0x68e07bc0 rt 0x93474bde sa 5 DSPCtrl 0x00400000 --shll.ph $t0, $t8, 6 :: rd 0x0000ffc0 rt 0xfc0007ff sa 6 DSPCtrl 0x00400000 --shll.ph $t4, $t6, 7 :: rd 0xff80ff80 rt 0xffffffff sa 7 DSPCtrl 0x00000000 --shll.ph $t0, $t1, 8 :: rd 0x4a008f00 rt 0xcb4ab48f sa 8 DSPCtrl 0x00400000 --shll.ph $t2, $t3, 9 :: rd 0x1e003000 rt 0xaf8f7e18 sa 9 DSPCtrl 0x00400000 --shll.ph $t4, $t1, 10 :: rd 0x7c004000 rt 0x87df4510 sa 10 DSPCtrl 0x00400000 --shll.ph $t6, $t7, 11 :: rd 0xa0000800 rt 0xabf4e8e1 sa 11 DSPCtrl 0x00400000 --shll.ph $t5, $t3, 12 :: rd 0x0000c000 rt 0xf4c0eeac sa 12 DSPCtrl 0x00400000 --shll.ph $t2, $t4, 13 :: rd 0x40004000 rt 0x006a54f2 sa 13 DSPCtrl 0x00400000 --shll.ph $t0, $t8, 14 :: rd 0xc000c000 rt 0x79f74493 sa 14 DSPCtrl 0x00400000 --shll.ph $t4, $t6, 15 :: rd 0x80008000 rt 0x9c09e313 sa 15 DSPCtrl 0x00400000 ---------- SHLL_S.PH -------- --shll_s.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 DSPCtrl 0x00000000 --shll_s.ph $t2, $t3, 1 :: rd 0x5ffe0000 rt 0x2fff0000 sa 1 DSPCtrl 0x00000000 --shll_s.ph $t4, $t1, 2 :: rd 0x7fff0000 rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 --shll_s.ph $t6, $t7, 3 :: rd 0x7fff0000 rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 --shll_s.ph $t5, $t3, 4 :: rd 0x80000000 rt 0x80000000 sa 4 DSPCtrl 0x00400000 --shll_s.ph $t2, $t4, 5 :: rd 0xe020ffe0 rt 0xff01ffff sa 5 DSPCtrl 0x00000000 --shll_s.ph $t0, $t8, 6 :: rd 0x7fff7fff rt 0x7fff7fff sa 6 DSPCtrl 0x00400000 --shll_s.ph $t4, $t6, 7 :: rd 0x00007fff rt 0x00000555 sa 7 DSPCtrl 0x00400000 --shll_s.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 DSPCtrl 0x00000000 --shll_s.ph $t2, $t3, 9 :: rd 0x80000000 rt 0x80000000 sa 9 DSPCtrl 0x00400000 --shll_s.ph $t4, $t1, 10 :: rd 0x7fff7fff rt 0x55555555 sa 10 DSPCtrl 0x00400000 --shll_s.ph $t6, $t7, 11 :: rd 0xf8007fff rt 0xffff2435 sa 11 DSPCtrl 0x00400000 --shll_s.ph $t5, $t3, 12 :: rd 0x80008000 rt 0xabababab sa 12 DSPCtrl 0x00400000 --shll_s.ph $t2, $t4, 13 :: rd 0x80008000 rt 0xfc79b4d2 sa 13 DSPCtrl 0x00400000 --shll_s.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 DSPCtrl 0x00000000 --shll_s.ph $t4, $t6, 15 :: rd 0x7fff7fff rt 0x00354565 sa 15 DSPCtrl 0x00400000 --shll_s.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 DSPCtrl 0x00000000 --shll_s.ph $t2, $t3, 1 :: rd 0x80008000 rt 0x8f8f8f8f sa 1 DSPCtrl 0x00400000 --shll_s.ph $t4, $t1, 2 :: rd 0xbbb8bbb8 rt 0xeeeeeeee sa 2 DSPCtrl 0x00000000 --shll_s.ph $t6, $t7, 3 :: rd 0x7fff8000 rt 0x1bdbdbdb sa 3 DSPCtrl 0x00400000 --shll_s.ph $t5, $t3, 4 :: rd 0x80008000 rt 0xdecadeca sa 4 DSPCtrl 0x00400000 --shll_s.ph $t2, $t4, 5 :: rd 0x80007fff rt 0x93474bde sa 5 DSPCtrl 0x00400000 --shll_s.ph $t0, $t8, 6 :: rd 0x80007fff rt 0xfc0007ff sa 6 DSPCtrl 0x00400000 --shll_s.ph $t4, $t6, 7 :: rd 0xff80ff80 rt 0xffffffff sa 7 DSPCtrl 0x00000000 --shll_s.ph $t0, $t1, 8 :: rd 0x80008000 rt 0xcb4ab48f sa 8 DSPCtrl 0x00400000 --shll_s.ph $t2, $t3, 9 :: rd 0x80007fff rt 0xaf8f7e18 sa 9 DSPCtrl 0x00400000 --shll_s.ph $t4, $t1, 10 :: rd 0x80007fff rt 0x87df4510 sa 10 DSPCtrl 0x00400000 --shll_s.ph $t6, $t7, 11 :: rd 0x80008000 rt 0xabf4e8e1 sa 11 DSPCtrl 0x00400000 --shll_s.ph $t5, $t3, 12 :: rd 0x80008000 rt 0xf4c0eeac sa 12 DSPCtrl 0x00400000 --shll_s.ph $t2, $t4, 13 :: rd 0x7fff7fff rt 0x006a54f2 sa 13 DSPCtrl 0x00400000 --shll_s.ph $t0, $t8, 14 :: rd 0x7fff7fff rt 0x79f74493 sa 14 DSPCtrl 0x00400000 --shll_s.ph $t4, $t6, 15 :: rd 0x80008000 rt 0x9c09e313 sa 15 DSPCtrl 0x00400000 ---------- SHLL.QB -------- --shll.qb $t0, $t1, 1 :: rd 0x00000000 rt 0x00000000 sa 1 DSPCtrl 0x00000000 --shll.qb $t2, $t3, 2 :: rd 0xbcfc0000 rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 --shll.qb $t4, $t1, 3 :: rd 0x78f80000 rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 --shll.qb $t6, $t7, 4 :: rd 0xf0f00000 rt 0x2fff0000 sa 4 DSPCtrl 0x00400000 --shll.qb $t5, $t3, 0 :: rd 0x80000000 rt 0x80000000 sa 0 DSPCtrl 0x00000000 --shll.qb $t2, $t4, 7 :: rd 0x80808080 rt 0xff01ffff sa 7 DSPCtrl 0x00400000 --shll.qb $t0, $t8, 7 :: rd 0x80808080 rt 0x7fff7fff sa 7 DSPCtrl 0x00400000 --shll.qb $t4, $t6, 0 :: rd 0x00000555 rt 0x00000555 sa 0 DSPCtrl 0x00000000 --shll.qb $t0, $t1, 1 :: rd 0x00000000 rt 0x00000000 sa 1 DSPCtrl 0x00000000 --shll.qb $t2, $t3, 2 :: rd 0x00000000 rt 0x80000000 sa 2 DSPCtrl 0x00400000 --shll.qb $t4, $t1, 3 :: rd 0xa8a8a8a8 rt 0x55555555 sa 3 DSPCtrl 0x00400000 --shll.qb $t6, $t7, 4 :: rd 0xf0f04050 rt 0xffff2435 sa 4 DSPCtrl 0x00400000 --shll.qb $t5, $t3, 5 :: rd 0x60606060 rt 0xabababab sa 5 DSPCtrl 0x00400000 --shll.qb $t2, $t4, 6 :: rd 0x00400080 rt 0xfc79b4d2 sa 6 DSPCtrl 0x00400000 --shll.qb $t0, $t8, 7 :: rd 0x00000000 rt 0x00000000 sa 7 DSPCtrl 0x00000000 --shll.qb $t4, $t6, 0 :: rd 0x00354565 rt 0x00354565 sa 0 DSPCtrl 0x00000000 --shll.qb $t0, $t1, 1 :: rd 0x0010ceaa rt 0x00086755 sa 1 DSPCtrl 0x00000000 --shll.qb $t2, $t3, 2 :: rd 0x3c3c3c3c rt 0x8f8f8f8f sa 2 DSPCtrl 0x00400000 --shll.qb $t4, $t1, 3 :: rd 0x70707070 rt 0xeeeeeeee sa 3 DSPCtrl 0x00400000 --shll.qb $t6, $t7, 4 :: rd 0xb0b0b0b0 rt 0x1bdbdbdb sa 4 DSPCtrl 0x00400000 --shll.qb $t5, $t3, 5 :: rd 0xc040c040 rt 0xdecadeca sa 5 DSPCtrl 0x00400000 --shll.qb $t2, $t4, 6 :: rd 0xc0c0c080 rt 0x93474bde sa 6 DSPCtrl 0x00400000 --shll.qb $t0, $t8, 7 :: rd 0x00008080 rt 0xfc0007ff sa 7 DSPCtrl 0x00400000 --shll.qb $t4, $t6, 0 :: rd 0xffffffff rt 0xffffffff sa 0 DSPCtrl 0x00000000 --shll.qb $t0, $t1, 3 :: rd 0x5850a078 rt 0xcb4ab48f sa 3 DSPCtrl 0x00400000 --shll.qb $t2, $t3, 4 :: rd 0xf0f0e080 rt 0xaf8f7e18 sa 4 DSPCtrl 0x00400000 --shll.qb $t4, $t1, 0 :: rd 0x87df4510 rt 0x87df4510 sa 0 DSPCtrl 0x00000000 --shll.qb $t6, $t7, 7 :: rd 0x80000080 rt 0xabf4e8e1 sa 7 DSPCtrl 0x00400000 --shll.qb $t5, $t3, 7 :: rd 0x00000000 rt 0xf4c0eeac sa 7 DSPCtrl 0x00400000 --shll.qb $t2, $t4, 5 :: rd 0x00408040 rt 0x006a54f2 sa 5 DSPCtrl 0x00400000 --shll.qb $t0, $t8, 1 :: rd 0xf2ee8826 rt 0x79f74493 sa 1 DSPCtrl 0x00400000 --shll.qb $t4, $t6, 2 :: rd 0x70248c4c rt 0x9c09e313 sa 2 DSPCtrl 0x00400000 ---------- SHLL_S.W -------- --shll_s.w $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 DSPCtrl 0x00000000 --shll_s.w $t2, $t3, 1 :: rd 0x5ffe0000 rt 0x2fff0000 sa 1 DSPCtrl 0x00000000 --shll_s.w $t4, $t1, 2 :: rd 0x7fffffff rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 --shll_s.w $t6, $t7, 3 :: rd 0x7fffffff rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 --shll_s.w $t5, $t3, 4 :: rd 0x80000000 rt 0x80000000 sa 4 DSPCtrl 0x00400000 --shll_s.w $t2, $t4, 5 :: rd 0xe03fffe0 rt 0xff01ffff sa 5 DSPCtrl 0x00000000 --shll_s.w $t0, $t8, 6 :: rd 0x7fffffff rt 0x7fff7fff sa 6 DSPCtrl 0x00400000 --shll_s.w $t4, $t6, 7 :: rd 0x0002aa80 rt 0x00000555 sa 7 DSPCtrl 0x00000000 --shll_s.w $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 DSPCtrl 0x00000000 --shll_s.w $t2, $t3, 9 :: rd 0x80000000 rt 0x80000000 sa 9 DSPCtrl 0x00400000 --shll_s.w $t4, $t1, 10 :: rd 0x7fffffff rt 0x55555555 sa 10 DSPCtrl 0x00400000 --shll_s.w $t6, $t7, 11 :: rd 0xf921a800 rt 0xffff2435 sa 11 DSPCtrl 0x00000000 --shll_s.w $t5, $t3, 12 :: rd 0x80000000 rt 0xabababab sa 12 DSPCtrl 0x00400000 --shll_s.w $t2, $t4, 13 :: rd 0x80000000 rt 0xfc79b4d2 sa 13 DSPCtrl 0x00400000 --shll_s.w $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 DSPCtrl 0x00000000 --shll_s.w $t4, $t6, 15 :: rd 0x7fffffff rt 0x00354565 sa 15 DSPCtrl 0x00400000 --shll_s.w $t0, $t1, 16 :: rd 0x7fffffff rt 0x00086755 sa 0 DSPCtrl 0x00400000 --shll_s.w $t2, $t3, 17 :: rd 0x80000000 rt 0x8f8f8f8f sa 1 DSPCtrl 0x00400000 --shll_s.w $t4, $t1, 18 :: rd 0x80000000 rt 0xeeeeeeee sa 2 DSPCtrl 0x00400000 --shll_s.w $t6, $t7, 19 :: rd 0x7fffffff rt 0x1bdbdbdb sa 3 DSPCtrl 0x00400000 --shll_s.w $t5, $t3, 20 :: rd 0x80000000 rt 0xdecadeca sa 4 DSPCtrl 0x00400000 --shll_s.w $t2, $t4, 21 :: rd 0x80000000 rt 0x93474bde sa 5 DSPCtrl 0x00400000 --shll_s.w $t0, $t8, 22 :: rd 0x80000000 rt 0xfc0007ff sa 6 DSPCtrl 0x00400000 --shll_s.w $t4, $t6, 23 :: rd 0xff800000 rt 0xffffffff sa 7 DSPCtrl 0x00000000 --shll_s.w $t0, $t1, 24 :: rd 0x80000000 rt 0xcb4ab48f sa 8 DSPCtrl 0x00400000 --shll_s.w $t2, $t3, 25 :: rd 0x80000000 rt 0xaf8f7e18 sa 9 DSPCtrl 0x00400000 --shll_s.w $t4, $t1, 26 :: rd 0x80000000 rt 0x87df4510 sa 10 DSPCtrl 0x00400000 --shll_s.w $t6, $t7, 27 :: rd 0x80000000 rt 0xabf4e8e1 sa 11 DSPCtrl 0x00400000 --shll_s.w $t5, $t3, 28 :: rd 0x80000000 rt 0xf4c0eeac sa 12 DSPCtrl 0x00400000 --shll_s.w $t2, $t4, 29 :: rd 0x7fffffff rt 0x006a54f2 sa 13 DSPCtrl 0x00400000 --shll_s.w $t0, $t8, 30 :: rd 0x7fffffff rt 0x79f74493 sa 14 DSPCtrl 0x00400000 --shll_s.w $t4, $t6, 31 :: rd 0x80000000 rt 0x9c09e313 sa 15 DSPCtrl 0x00400000 ---------- SHLLV.PH -------- --shllv.ph $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 --shllv.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 --shllv.ph $t4, $t1, $t5 :: rd 0x5ffe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00000000 --shllv.ph $t6, $t7, $t3 :: rd 0xbffc0000 rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 --shllv.ph $t5, $t3, $t2 :: rd 0x7ff80000 rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 --shllv.ph $t2, $t4, $t8 :: rd 0x80008000 rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 --shllv.ph $t0, $t8, $t0 :: rd 0x80000000 rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 --shllv.ph $t4, $t6, $t1 :: rd 0x00008400 rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 --shllv.ph $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 DSPCtrl 0x00000000 --shllv.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 DSPCtrl 0x00000000 --shllv.ph $t4, $t1, $t5 :: rd 0x55405540 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 --shllv.ph $t6, $t7, $t3 :: rd 0x00000300 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00000000 --shllv.ph $t5, $t3, $t2 :: rd 0xd000d000 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 --shllv.ph $t2, $t4, $t8 :: rd 0xc3c0c3c0 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00000000 --shllv.ph $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 --shllv.ph $t4, $t6, $t1 :: rd 0x6a600e00 rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 --shllv.ph $t0, $t1, $t2 :: rd 0x01609bc0 rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 --shllv.ph $t2, $t3, $t4 :: rd 0x00000000 rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00400000 --shllv.ph $t4, $t1, $t5 :: rd 0x00008000 rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 --shllv.ph $t6, $t7, $t3 :: rd 0x50005000 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 --shllv.ph $t5, $t3, $t2 :: rd 0x28002800 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 --shllv.ph $t2, $t4, $t8 :: rd 0x80000000 rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 --shllv.ph $t0, $t8, $t0 :: rd 0x00000000 rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 --shllv.ph $t4, $t6, $t1 :: rd 0x80008000 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00000000 --shllv.ph $t0, $t1, $t2 :: rd 0x00008000 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 --shllv.ph $t2, $t3, $t4 :: rd 0x5f009a00 rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00400000 --shllv.ph $t4, $t1, $t5 :: rd 0x2106ba5f rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00000000 --shllv.ph $t6, $t7, $t3 :: rd 0x48d4c6ec rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00400000 --shllv.ph $t5, $t3, $t2 :: rd 0x60003000 rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 --shllv.ph $t2, $t4, $t8 :: rd 0x8e309454 rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 --shllv.ph $t0, $t8, $t0 :: rd 0xb1f0d4e8 rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 --shllv.ph $t4, $t6, $t1 :: rd 0xeb402e68 rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 ---------- SHLLV_S.PH -------- --shllv_s.ph $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.ph $t4, $t1, $t5 :: rd 0x5ffe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00000000 --shllv_s.ph $t6, $t7, $t3 :: rd 0x7fff0000 rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 --shllv_s.ph $t5, $t3, $t2 :: rd 0x7fff0000 rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 --shllv_s.ph $t2, $t4, $t8 :: rd 0x7fff7fff rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 --shllv_s.ph $t0, $t8, $t0 :: rd 0x7fff7fff rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 --shllv_s.ph $t4, $t6, $t1 :: rd 0x00008000 rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 --shllv_s.ph $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 DSPCtrl 0x00000000 --shllv_s.ph $t4, $t1, $t5 :: rd 0x80008000 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 --shllv_s.ph $t6, $t7, $t3 :: rd 0x00000300 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00000000 --shllv_s.ph $t5, $t3, $t2 :: rd 0x80008000 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 --shllv_s.ph $t2, $t4, $t8 :: rd 0xc3c0c3c0 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00000000 --shllv_s.ph $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.ph $t4, $t6, $t1 :: rd 0x7fff7fff rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 --shllv_s.ph $t0, $t1, $t2 :: rd 0x80007fff rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 --shllv_s.ph $t2, $t3, $t4 :: rd 0x00007fff rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00400000 --shllv_s.ph $t4, $t1, $t5 :: rd 0x80007fff rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 --shllv_s.ph $t6, $t7, $t3 :: rd 0x80008000 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 --shllv_s.ph $t5, $t3, $t2 :: rd 0x80008000 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 --shllv_s.ph $t2, $t4, $t8 :: rd 0x7fff8000 rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 --shllv_s.ph $t0, $t8, $t0 :: rd 0x7fff7fff rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 --shllv_s.ph $t4, $t6, $t1 :: rd 0x80008000 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00000000 --shllv_s.ph $t0, $t1, $t2 :: rd 0x80008000 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 --shllv_s.ph $t2, $t3, $t4 :: rd 0x7fff8000 rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00400000 --shllv_s.ph $t4, $t1, $t5 :: rd 0x2106ba5f rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00000000 --shllv_s.ph $t6, $t7, $t3 :: rd 0x48d47fff rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00400000 --shllv_s.ph $t5, $t3, $t2 :: rd 0x7fff8000 rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 --shllv_s.ph $t2, $t4, $t8 :: rd 0x7fff8000 rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 --shllv_s.ph $t0, $t8, $t0 :: rd 0xb1f07fff rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 --shllv_s.ph $t4, $t6, $t1 :: rd 0x80007fff rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 ---------- SHLLV.QB -------- --shllv.qb $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 --shllv.qb $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 --shllv.qb $t4, $t1, $t5 :: rd 0x5efe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00400000 --shllv.qb $t6, $t7, $t3 :: rd 0xbcfc0000 rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 --shllv.qb $t5, $t3, $t2 :: rd 0x78f80000 rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 --shllv.qb $t2, $t4, $t8 :: rd 0x00800080 rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 --shllv.qb $t0, $t8, $t0 :: rd 0x80800000 rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 --shllv.qb $t4, $t6, $t1 :: rd 0x00008000 rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 --shllv.qb $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x9348572b DSPCtrl 0x00000000 --shllv.qb $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80023450 DSPCtrl 0x00000000 --shllv.qb $t4, $t1, $t5 :: rd 0x40404040 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 --shllv.qb $t6, $t7, $t3 :: rd 0x00000000 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00400000 --shllv.qb $t5, $t3, $t2 :: rd 0xd0d0d0d0 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 --shllv.qb $t2, $t4, $t8 :: rd 0xc0c0c0c0 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00400000 --shllv.qb $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 --shllv.qb $t4, $t6, $t1 :: rd 0x60600000 rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 --shllv.qb $t0, $t1, $t2 :: rd 0x006080c0 rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 --shllv.qb $t2, $t3, $t4 :: rd 0x00000000 rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00400000 --shllv.qb $t4, $t1, $t5 :: rd 0x80008080 rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 --shllv.qb $t6, $t7, $t3 :: rd 0x50505050 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 --shllv.qb $t5, $t3, $t2 :: rd 0xe828e828 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 --shllv.qb $t2, $t4, $t8 :: rd 0x80808000 rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 --shllv.qb $t0, $t8, $t0 :: rd 0x00008000 rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 --shllv.qb $t4, $t6, $t1 :: rd 0x80808080 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00400000 --shllv.qb $t0, $t1, $t2 :: rd 0x00008080 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 --shllv.qb $t2, $t3, $t4 :: rd 0x435f909a rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00000000 --shllv.qb $t4, $t1, $t5 :: rd 0x2106ba5f rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00000000 --shllv.qb $t6, $t7, $t3 :: rd 0x48d4c6ec rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00000000 --shllv.qb $t5, $t3, $t2 :: rd 0x00601030 rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 --shllv.qb $t2, $t4, $t8 :: rd 0x8c309454 rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 --shllv.qb $t0, $t8, $t0 :: rd 0xb0f0d0e8 rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 --shllv.qb $t4, $t6, $t1 :: rd 0xe8402868 rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 ---------- SHLLV_S.W -------- --shllv_s.w $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.w $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.w $t4, $t1, $t5 :: rd 0x5ffe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00000000 --shllv_s.w $t6, $t7, $t3 :: rd 0x7fffffff rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 --shllv_s.w $t5, $t3, $t2 :: rd 0x7fffffff rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 --shllv_s.w $t2, $t4, $t8 :: rd 0x7fffffff rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 --shllv_s.w $t0, $t8, $t0 :: rd 0x7fffffff rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 --shllv_s.w $t4, $t6, $t1 :: rd 0x7fffffff rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 --shllv_s.w $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.w $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 DSPCtrl 0x00000000 --shllv_s.w $t4, $t1, $t5 :: rd 0x80000000 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 --shllv_s.w $t6, $t7, $t3 :: rd 0x03000000 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00000000 --shllv_s.w $t5, $t3, $t2 :: rd 0x80000000 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 --shllv_s.w $t2, $t4, $t8 :: rd 0x80000000 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00400000 --shllv_s.w $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 --shllv_s.w $t4, $t6, $t1 :: rd 0x7fffffff rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 --shllv_s.w $t0, $t1, $t2 :: rd 0x80000000 rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 --shllv_s.w $t2, $t3, $t4 :: rd 0x000c0000 rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00000000 --shllv_s.w $t4, $t1, $t5 :: rd 0x80000000 rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 --shllv_s.w $t6, $t7, $t3 :: rd 0x80000000 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 --shllv_s.w $t5, $t3, $t2 :: rd 0x80000000 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 --shllv_s.w $t2, $t4, $t8 :: rd 0x7fffffff rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 --shllv_s.w $t0, $t8, $t0 :: rd 0x7fffffff rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 --shllv_s.w $t4, $t6, $t1 :: rd 0x80000000 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00000000 --shllv_s.w $t0, $t1, $t2 :: rd 0x80000000 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 --shllv_s.w $t2, $t3, $t4 :: rd 0x7fffffff rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00400000 --shllv_s.w $t4, $t1, $t5 :: rd 0x7fffffff rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00400000 --shllv_s.w $t6, $t7, $t3 :: rd 0x48d4c6ec rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00000000 --shllv_s.w $t5, $t3, $t2 :: rd 0x7fffffff rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 --shllv_s.w $t2, $t4, $t8 :: rd 0x7fffffff rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 --shllv_s.w $t0, $t8, $t0 :: rd 0x80000000 rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 --shllv_s.w $t4, $t6, $t1 :: rd 0x80000000 rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 ---------- SHRA.PH -------- --shra.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 --shra.ph $t2, $t3, 1 :: rd 0x0001c319 rt 0x00028632 sa 1 --shra.ph $t4, $t1, 2 :: rd 0xfeaf0d08 rt 0xfabc3421 sa 2 --shra.ph $t6, $t7, 3 :: rd 0x0e68f017 rt 0x734680bc sa 3 --shra.ph $t5, $t3, 4 :: rd 0xf8000000 rt 0x80000000 sa 4 --shra.ph $t2, $t4, 5 :: rd 0xfff8ffff rt 0xff01ffff sa 5 --shra.ph $t0, $t8, 6 :: rd 0x01ff01ff rt 0x7fff7fff sa 6 --shra.ph $t4, $t6, 7 :: rd 0x0000000a rt 0x00000555 sa 7 --shra.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 --shra.ph $t2, $t3, 9 :: rd 0xffc00000 rt 0x80000000 sa 9 --shra.ph $t4, $t1, 10 :: rd 0x00150015 rt 0x55555555 sa 10 --shra.ph $t6, $t7, 11 :: rd 0xffff0004 rt 0xffff2435 sa 11 --shra.ph $t5, $t3, 12 :: rd 0xfffafffa rt 0xabababab sa 12 --shra.ph $t2, $t4, 13 :: rd 0xfffffffd rt 0xfc79b4d2 sa 13 --shra.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 --shra.ph $t4, $t6, 15 :: rd 0x00000000 rt 0x00354565 sa 15 --shra.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 --shra.ph $t2, $t3, 1 :: rd 0xc7c7c7c7 rt 0x8f8f8f8f sa 1 --shra.ph $t4, $t1, 2 :: rd 0xfbbbfbbb rt 0xeeeeeeee sa 2 --shra.ph $t6, $t7, 3 :: rd 0x037bfb7b rt 0x1bdbdbdb sa 3 --shra.ph $t5, $t3, 4 :: rd 0xfdecfdec rt 0xdecadeca sa 4 --shra.ph $t2, $t4, 5 :: rd 0xfc9a025e rt 0x93474bde sa 5 --shra.ph $t0, $t8, 6 :: rd 0xfff0001f rt 0xfc0007ff sa 6 --shra.ph $t4, $t6, 7 :: rd 0xffffffff rt 0xffffffff sa 7 --shra.ph $t0, $t1, 8 :: rd 0xffcbffb4 rt 0xcb4ab48f sa 8 --shra.ph $t2, $t3, 9 :: rd 0xffd7003f rt 0xaf8f7e18 sa 9 --shra.ph $t4, $t1, 10 :: rd 0xffe10011 rt 0x87df4510 sa 10 --shra.ph $t6, $t7, 11 :: rd 0xfff5fffd rt 0xabf4e8e1 sa 11 --shra.ph $t5, $t3, 12 :: rd 0xfffffffe rt 0xf4c0eeac sa 12 --shra.ph $t2, $t4, 13 :: rd 0x00000002 rt 0x006a54f2 sa 13 --shra.ph $t0, $t8, 14 :: rd 0x00010001 rt 0x79f74493 sa 14 --shra.ph $t4, $t6, 15 :: rd 0xffffffff rt 0x9c09e313 sa 15 ---------- SHRA_R.PH -------- --shra_r.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 --shra_r.ph $t2, $t3, 1 :: rd 0x0001c319 rt 0x00028632 sa 1 --shra_r.ph $t4, $t1, 2 :: rd 0xfeaf0d08 rt 0xfabc3421 sa 2 --shra_r.ph $t6, $t7, 3 :: rd 0x0e69f018 rt 0x734680bc sa 3 --shra_r.ph $t5, $t3, 4 :: rd 0xf8000000 rt 0x80000000 sa 4 --shra_r.ph $t2, $t4, 5 :: rd 0xfff80000 rt 0xff01ffff sa 5 --shra_r.ph $t0, $t8, 6 :: rd 0x02000200 rt 0x7fff7fff sa 6 --shra_r.ph $t4, $t6, 7 :: rd 0x0000000b rt 0x00000555 sa 7 --shra_r.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 --shra_r.ph $t2, $t3, 9 :: rd 0xffc00000 rt 0x80000000 sa 9 --shra_r.ph $t4, $t1, 10 :: rd 0x00150015 rt 0x55555555 sa 10 --shra_r.ph $t6, $t7, 11 :: rd 0x00000005 rt 0xffff2435 sa 11 --shra_r.ph $t5, $t3, 12 :: rd 0xfffbfffb rt 0xabababab sa 12 --shra_r.ph $t2, $t4, 13 :: rd 0x0000fffe rt 0xfc79b4d2 sa 13 --shra_r.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 --shra_r.ph $t4, $t6, 15 :: rd 0x00000001 rt 0x00354565 sa 15 --shra_r.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 --shra_r.ph $t2, $t3, 1 :: rd 0xc7c8c7c8 rt 0x8f8f8f8f sa 1 --shra_r.ph $t4, $t1, 2 :: rd 0xfbbcfbbc rt 0xeeeeeeee sa 2 --shra_r.ph $t6, $t7, 3 :: rd 0x037bfb7b rt 0x1bdbdbdb sa 3 --shra_r.ph $t5, $t3, 4 :: rd 0xfdedfded rt 0xdecadeca sa 4 --shra_r.ph $t2, $t4, 5 :: rd 0xfc9a025f rt 0x93474bde sa 5 --shra_r.ph $t0, $t8, 6 :: rd 0xfff00020 rt 0xfc0007ff sa 6 --shra_r.ph $t4, $t6, 7 :: rd 0x00000000 rt 0xffffffff sa 7 --shra_r.ph $t0, $t1, 8 :: rd 0xffcbffb5 rt 0xcb4ab48f sa 8 --shra_r.ph $t2, $t3, 9 :: rd 0xffd8003f rt 0xaf8f7e18 sa 9 --shra_r.ph $t4, $t1, 10 :: rd 0xffe20011 rt 0x87df4510 sa 10 --shra_r.ph $t6, $t7, 11 :: rd 0xfff5fffd rt 0xabf4e8e1 sa 11 --shra_r.ph $t5, $t3, 12 :: rd 0xffffffff rt 0xf4c0eeac sa 12 --shra_r.ph $t2, $t4, 13 :: rd 0x00000003 rt 0x006a54f2 sa 13 --shra_r.ph $t0, $t8, 14 :: rd 0x00020001 rt 0x79f74493 sa 14 --shra_r.ph $t4, $t6, 15 :: rd 0xffff0000 rt 0x9c09e313 sa 15 ---------- SHRA_R.W -------- --shra_r.w $t2, $t3, 1 :: rd 0x00000001 rt 0x00000002 sa 1 --shra_r.w $t2, $t3, 16 :: rd 0xffff8000 rt 0x80000000 sa 16 --shra_r.w $t2, $t3, 1 :: rd 0x00008001 rt 0x00010001 sa 1 --shra_r.w $t2, $t3, 17 :: rd 0x00000001 rt 0x00010001 sa 17 --shra_r.w $t2, $t3, 17 :: rd 0xffffc001 rt 0x80010001 sa 17 --shra_r.w $t2, $t3, 0 :: rd 0x7fffffff rt 0x7fffffff sa 0 --shra_r.w $t2, $t3, 1 :: rd 0x40000000 rt 0x7fffffff sa 1 --shra_r.w $t2, $t3, 2 :: rd 0x20000000 rt 0x7ffffffe sa 2 --shra_r.w $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 --shra_r.w $t4, $t1, 4 :: rd 0xffabc343 rt 0xfabc3435 sa 4 --shra_r.w $t6, $t7, 17 :: rd 0x000003b3 rt 0x07654cb8 sa 17 --shra_r.w $t5, $t3, 31 :: rd 0x00000000 rt 0xf973437b sa 31 --shra_r.w $t2, $t4, 8 :: rd 0x0000ff00 rt 0x00ff0001 sa 8 --shra_r.w $t0, $t8, 11 :: rd 0x000ffff0 rt 0x7fff7fff sa 11 --shra_r.w $t4, $t6, 13 :: rd 0x00000006 rt 0x0000c420 sa 13 --shra_r.w $t0, $t1, 2 :: rd 0x00000000 rt 0x00000000 sa 2 --shra_r.w $t2, $t3, 6 :: rd 0xfe000000 rt 0x80000000 sa 6 --shra_r.w $t4, $t1, 7 :: rd 0xff555555 rt 0xaaaaaaaa sa 7 --shra_r.w $t6, $t7, 19 :: rd 0x00000000 rt 0x00000018 sa 19 --shra_r.w $t5, $t3, 31 :: rd 0xffffffff rt 0xbabababa sa 31 --shra_r.w $t2, $t4, 4 :: rd 0xff0f0f0f rt 0xf0f0f0f0 sa 4 --shra_r.w $t0, $t8, 12 :: rd 0xffffbde4 rt 0xfbde3976 sa 12 --shra_r.w $t4, $t6, 10 :: rd 0x0008d4d2 rt 0x23534870 sa 10 --shra_r.w $t0, $t1, 20 :: rd 0xfffff981 rt 0x980b7cde sa 20 --shra_r.w $t2, $t3, 21 :: rd 0x00000000 rt 0x00000018 sa 21 --shra_r.w $t4, $t1, 24 :: rd 0xffffff92 rt 0x92784656 sa 24 --shra_r.w $t6, $t7, 27 :: rd 0xfffffff9 rt 0xcacacaca sa 27 --shra_r.w $t5, $t3, 1 :: rd 0xdd655d65 rt 0xbacabaca sa 1 --shra_r.w $t2, $t4, 18 :: rd 0x000004bf rt 0x12fadeb4 sa 18 --shra_r.w $t0, $t8, 10 :: rd 0x001f0002 rt 0x7c000790 sa 10 --shra_r.w $t4, $t6, 16 :: rd 0x00000000 rt 0xffffffff sa 16 --shra_r.w $t0, $t1, 0 :: rd 0xf2f4df1f rt 0xf2f4df1f sa 0 --shra_r.w $t2, $t3, 14 :: rd 0x00010d7e rt 0x435f909a sa 14 --shra_r.w $t4, $t1, 5 :: rd 0x010835d3 rt 0x2106ba5f sa 5 --shra_r.w $t6, $t7, 7 :: rd 0x0048d4c7 rt 0x246a6376 sa 7 --shra_r.w $t5, $t3, 9 :: rd 0x00082351 rt 0x1046a1a3 sa 9 --shra_r.w $t2, $t4, 3 :: rd 0x0c7194a3 rt 0x638ca515 sa 3 --shra_r.w $t0, $t8, 15 :: rd 0xffffec7d rt 0xf63e7a9d sa 15 --shra_r.w $t4, $t6, 11 :: rd 0xfff7ad09 rt 0xbd6845cd sa 11 ---------- SHRAV.PH -------- --shrav.ph $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff --shrav.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 --shrav.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfd5e1a1a --shrav.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000004 --shrav.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b --shrav.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00000000 --shrav.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00000000 --shrav.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000fe21 --shrav.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --shrav.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 --shrav.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xfd55fd55 --shrav.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 --shrav.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xfff7fff7 --shrav.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xfc3cfc3c --shrav.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 --shrav.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x011a0243 --shrav.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfcc003e6 --shrav.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 --shrav.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xfffe0001 --shrav.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xfff9fff9 --shrav.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffeeffee --shrav.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x0000ffff --shrav.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000000 --shrav.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff --shrav.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xffffffff --shrav.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0043ff90 --shrav.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x2106ba5f --shrav.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x123531bb --shrav.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0001fffa --shrav.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x18e3e945 --shrav.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xfec70f53 --shrav.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xf7ad08b9 ---------- SHRAV_R.PH -------- --shrav_r.ph $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff --shrav_r.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 --shrav_r.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfd5e1a1b --shrav_r.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000005 --shrav_r.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b --shrav_r.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00000000 --shrav_r.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00010001 --shrav_r.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000fe21 --shrav_r.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --shrav_r.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 --shrav_r.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xfd55fd55 --shrav_r.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000001 --shrav_r.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xfff7fff7 --shrav_r.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xfc3cfc3c --shrav_r.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 --shrav_r.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x011b0244 --shrav_r.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfcc003e7 --shrav_r.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 --shrav_r.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xfffe0001 --shrav_r.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xfff9fff9 --shrav_r.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffefffef --shrav_r.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x0000ffff --shrav_r.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00010000 --shrav_r.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 --shrav_r.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000000 --shrav_r.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0043ff91 --shrav_r.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x2106ba5f --shrav_r.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x123531bb --shrav_r.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0001fffa --shrav_r.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x18e3e945 --shrav_r.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xfec80f54 --shrav_r.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xf7ad08ba ---------- SHRAV_R.W -------- --shrav_r.w $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff --shrav_r.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 --shrav_r.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfd5e1a1b --shrav_r.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000000 --shrav_r.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b --shrav_r.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00000000 --shrav_r.w $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00000001 --shrav_r.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 --shrav_r.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 --shrav_r.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 --shrav_r.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xfffffd55 --shrav_r.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 --shrav_r.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xfff75757 --shrav_r.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xfffffc3c --shrav_r.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 --shrav_r.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x011a9a44 --shrav_r.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfffffcc0 --shrav_r.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 --shrav_r.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xfffe49e1 --shrav_r.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xfffffff9 --shrav_r.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffeeb2af --shrav_r.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000000 --shrav_r.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000001 --shrav_r.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 --shrav_r.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xffffe5ea --shrav_r.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x00000043 --shrav_r.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x00002107 --shrav_r.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x123531bb --shrav_r.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0001046a --shrav_r.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x000018e3 --shrav_r.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xfffffec8 --shrav_r.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xfffff7ad ---------- SHRL.QB -------- --shrl.qb $t0, $t1, 1 :: rd 0x177f0000 rt 0x2fff0000 sa 1 --shrl.qb $t2, $t3, 2 :: rd 0x0b3f0000 rt 0x2fff0000 sa 2 --shrl.qb $t4, $t1, 3 :: rd 0x051f0000 rt 0x2fff0000 sa 3 --shrl.qb $t6, $t7, 4 :: rd 0x0f040000 rt 0xff460000 sa 4 --shrl.qb $t5, $t3, 0 :: rd 0x80000000 rt 0x80000000 sa 0 --shrl.qb $t2, $t4, 7 :: rd 0x01000101 rt 0xff01ffff sa 7 --shrl.qb $t0, $t8, 7 :: rd 0x00010001 rt 0x7fff7fff sa 7 --shrl.qb $t4, $t6, 0 :: rd 0x00000555 rt 0x00000555 sa 0 --shrl.qb $t0, $t1, 1 :: rd 0x00000000 rt 0x00000000 sa 1 --shrl.qb $t2, $t3, 2 :: rd 0x20000000 rt 0x80000000 sa 2 --shrl.qb $t4, $t1, 3 :: rd 0x0a0a0a0a rt 0x55555555 sa 3 --shrl.qb $t6, $t7, 4 :: rd 0x0f0f0203 rt 0xffff2435 sa 4 --shrl.qb $t5, $t3, 5 :: rd 0x05050505 rt 0xabababab sa 5 --shrl.qb $t2, $t4, 6 :: rd 0x03010203 rt 0xfc79b4d2 sa 6 --shrl.qb $t0, $t8, 7 :: rd 0x00000000 rt 0x00000000 sa 7 --shrl.qb $t4, $t6, 0 :: rd 0x00354565 rt 0x00354565 sa 0 --shrl.qb $t0, $t1, 1 :: rd 0x0004332a rt 0x00086755 sa 1 --shrl.qb $t2, $t3, 2 :: rd 0x23232323 rt 0x8f8f8f8f sa 2 --shrl.qb $t4, $t1, 3 :: rd 0x1d1d1d1d rt 0xeeeeeeee sa 3 --shrl.qb $t6, $t7, 4 :: rd 0x010d0d0d rt 0x1bdbdbdb sa 4 --shrl.qb $t5, $t3, 5 :: rd 0x06060606 rt 0xdecadeca sa 5 --shrl.qb $t2, $t4, 6 :: rd 0x02010103 rt 0x93474bde sa 6 --shrl.qb $t0, $t8, 7 :: rd 0x01000001 rt 0xfc0007ff sa 7 --shrl.qb $t4, $t6, 0 :: rd 0xffffffff rt 0xffffffff sa 0 --shrl.qb $t0, $t1, 3 :: rd 0x19091611 rt 0xcb4ab48f sa 3 --shrl.qb $t2, $t3, 4 :: rd 0x0a080701 rt 0xaf8f7e18 sa 4 --shrl.qb $t4, $t1, 0 :: rd 0x87df4510 rt 0x87df4510 sa 0 --shrl.qb $t6, $t7, 7 :: rd 0x01010101 rt 0xabf4e8e1 sa 7 --shrl.qb $t5, $t3, 7 :: rd 0x01010101 rt 0xf4c0eeac sa 7 --shrl.qb $t2, $t4, 5 :: rd 0x00030207 rt 0x006a54f2 sa 5 --shrl.qb $t0, $t8, 1 :: rd 0x3c7b2249 rt 0x79f74493 sa 1 --shrl.qb $t4, $t6, 2 :: rd 0x27023804 rt 0x9c09e313 sa 2 ---------- SHRLV.QB -------- --shrlv.qb $t0, $t1, $t2 :: rd 0x177f0000 rt 0x2fff0000 rs 0x00000001 --shrlv.qb $t2, $t3, $t4 :: rd 0x0b3f0000 rt 0x2fff0000 rs 0x73741802 --shrlv.qb $t4, $t1, $t5 :: rd 0x051f0000 rt 0x2fff0000 rs 0x80003403 --shrlv.qb $t6, $t7, $t3 :: rd 0x0f040000 rt 0xff460000 rs 0x73468004 --shrlv.qb $t5, $t3, $t2 :: rd 0x00008000 rt 0x00008000 rs 0x80000000 --shrlv.qb $t2, $t4, $t8 :: rd 0x00000000 rt 0x00010001 rs 0xffffff07 --shrlv.qb $t0, $t8, $t0 :: rd 0x00010001 rt 0x7fff7fff rs 0x7fff7f07 --shrlv.qb $t4, $t6, $t1 :: rd 0x07070707 rt 0xffffffff rs 0x00000505 --shrlv.qb $t0, $t1, $t2 :: rd 0xabababab rt 0xabababab rs 0x00000000 --shrlv.qb $t2, $t3, $t4 :: rd 0xdecadeca rt 0xdecadeca rs 0x80000000 --shrlv.qb $t4, $t1, $t5 :: rd 0x05060506 rt 0xbacabaca rs 0x55555555 --shrlv.qb $t6, $t7, $t3 :: rd 0x03040f08 rt 0x3545ff80 rs 0xffff2434 --shrlv.qb $t5, $t3, $t2 :: rd 0x0e081017 rt 0x734680bc rs 0xabababa3 --shrlv.qb $t2, $t4, $t8 :: rd 0x31363f08 rt 0xc4dbfe20 rs 0xfc79b4d2 --shrlv.qb $t0, $t8, $t0 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 --shrlv.qb $t4, $t3, $t1 :: rd 0x2a2a2a2a rt 0x55555555 rs 0x00354561 --shrlv.qb $t0, $t1, $t2 :: rd 0x05040507 rt 0xad80bce4 rs 0x00086755 --shrlv.qb $t2, $t3, $t4 :: rd 0x00000000 rt 0x7f003245 rs 0x8f8f8f8f --shrlv.qb $t4, $t1, $t5 :: rd 0x02010103 rt 0x93474bde rs 0xeeeeeeee --shrlv.qb $t6, $t7, $t3 :: rd 0x1f0e081f rt 0xf97343ff rs 0x1bdbdbdb --shrlv.qb $t5, $t3, $t2 :: rd 0x26021f37 rt 0x980b7cde rs 0xdecadeca --shrlv.qb $t2, $t4, $t8 :: rd 0x00010203 rt 0x0555adec rs 0x93474bde --shrlv.qb $t0, $t8, $t0 :: rd 0x00000000 rt 0x23534870 rs 0xfc0007ff --shrlv.qb $t4, $t3, $t1 :: rd 0x01000001 rt 0x80003286 rs 0xffffffff --shrlv.qb $t4, $t6, $t1 :: rd 0x10213f3f rt 0x4387ffff rs 0xdecadeca --shrlv.qb $t0, $t1, $t2 :: rd 0x03352d02 rt 0x0cd6b508 rs 0xbacabaca --shrlv.qb $t2, $t3, $t4 :: rd 0x6731e282 rt 0x6731e282 rs 0x3545ff80 --shrlv.qb $t4, $t1, $t5 :: rd 0x020e0f08 rt 0x26edf28f rs 0x734680bc --shrlv.qb $t6, $t7, $t3 :: rd 0x4b4ec9ca rt 0x4b4ec9ca rs 0xc4dbfe20 --shrlv.qb $t5, $t3, $t2 :: rd 0xc1037fa4 rt 0xc1037fa4 rs 0x00000000 --shrlv.qb $t2, $t4, $t8 :: rd 0x06020504 rt 0xcb4ab48f rs 0x55555555 --shrlv.qb $t0, $t8, $t0 :: rd 0x0a080701 rt 0xaf8f7e18 rs 0xad80bce4 --shrlv.qb $t4, $t3, $t1 :: rd 0x04060200 rt 0x87df4510 rs 0x7f003245 --shrlv.qb $t0, $t1, $t2 :: rd 0x02030303 rt 0xabf4e8e1 rs 0x93474bde --shrlv.qb $t2, $t3, $t4 :: rd 0x01010101 rt 0xf4c0eeac rs 0xf97343ff --shrlv.qb $t4, $t1, $t5 :: rd 0x00010103 rt 0x006a54f2 rs 0x980b7cde --shrlv.qb $t6, $t7, $t3 :: rd 0x070f0409 rt 0x79f74493 rs 0x0555adec --shrlv.qb $t5, $t3, $t2 :: rd 0x9c09e313 rt 0x9c09e313 rs 0x23534870 --shrlv.qb $t2, $t4, $t8 :: rd 0x13011c02 rt 0x9c09e313 rs 0x9c09e313 --shrlv.qb $t0, $t8, $t0 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 --shrlv.qb $t4, $t3, $t1 :: rd 0x004d8000 rt 0x004d8000 rs 0x004d8000 ---------- SUBQ.PH -------- --subq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --subq.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x045d2c00 DSPCtrl 0x00000000 --subq.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 --subq.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941fcbfc DSPCtrl 0x00100000 --subq.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 --subq.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fe0002 DSPCtrl 0x00000000 --subq.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x0000f005 DSPCtrl 0x00000000 --subq.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000becb DSPCtrl 0x00000000 --subq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --subq.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --subq.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x55555555 DSPCtrl 0x00100000 --subq.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0001dbe3 DSPCtrl 0x00000000 --subq.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 --subq.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00000000 --subq.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --subq.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 --subq.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 --subq.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x70717089 DSPCtrl 0x00000000 --subq.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa38a5768 DSPCtrl 0x00000000 --subq.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaeefeeef DSPCtrl 0x00000000 --subq.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdc00dc00 DSPCtrl 0x00000000 --subq.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb392d6 DSPCtrl 0x00000000 --subq.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x8000ff91 DSPCtrl 0x00100000 --subq.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --subq.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2a90 DSPCtrl 0x00000000 --subq.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x93d01282 DSPCtrl 0x00100000 --subq.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x9927754f DSPCtrl 0x00100000 --subq.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x78767a95 DSPCtrl 0x00000000 --subq.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1b86b2f7 DSPCtrl 0x00000000 --subq.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225023 DSPCtrl 0x00100000 --subq.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7c47360a DSPCtrl 0x00100000 --subq.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f62ba DSPCtrl 0x00000000 ---------- SUBQ_S.PH -------- --subq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --subq_s.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x045d2c00 DSPCtrl 0x00000000 --subq_s.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 --subq_s.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941f7fff DSPCtrl 0x00100000 --subq_s.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 --subq_s.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fe0002 DSPCtrl 0x00000000 --subq_s.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x0000f005 DSPCtrl 0x00000000 --subq_s.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000becb DSPCtrl 0x00000000 --subq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --subq_s.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --subq_s.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x80008000 DSPCtrl 0x00100000 --subq_s.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0001dbe3 DSPCtrl 0x00000000 --subq_s.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 --subq_s.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00000000 --subq_s.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --subq_s.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 --subq_s.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 --subq_s.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x70717089 DSPCtrl 0x00000000 --subq_s.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa38a5768 DSPCtrl 0x00000000 --subq_s.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaeefeeef DSPCtrl 0x00000000 --subq_s.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdc00dc00 DSPCtrl 0x00000000 --subq_s.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb392d6 DSPCtrl 0x00000000 --subq_s.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7fffff91 DSPCtrl 0x00100000 --subq_s.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --subq_s.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2a90 DSPCtrl 0x00000000 --subq_s.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x7fff8000 DSPCtrl 0x00100000 --subq_s.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x7fff8000 DSPCtrl 0x00100000 --subq_s.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x78767a95 DSPCtrl 0x00000000 --subq_s.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1b86b2f7 DSPCtrl 0x00000000 --subq_s.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63228000 DSPCtrl 0x00100000 --subq_s.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x8000360a DSPCtrl 0x00100000 --subq_s.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f62ba DSPCtrl 0x00000000 ---------- SUBQ_S.W -------- --subq_s.w $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff DSPCtrl 0x00000000 --subq_s.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 DSPCtrl 0x00000000 --subq_s.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 --subq_s.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941ecbfc DSPCtrl 0x00000000 --subq_s.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 --subq_s.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fd0002 DSPCtrl 0x00000000 --subq_s.w $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0xfffff005 DSPCtrl 0x00000000 --subq_s.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000becb DSPCtrl 0x00000000 --subq_s.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --subq_s.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --subq_s.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x80000000 DSPCtrl 0x00100000 --subq_s.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000dbe3 DSPCtrl 0x00000000 --subq_s.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 --subq_s.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00000000 --subq_s.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --subq_s.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 --subq_s.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 --subq_s.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x70707089 DSPCtrl 0x00000000 --subq_s.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa3895768 DSPCtrl 0x00000000 --subq_s.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaeeeeeef DSPCtrl 0x00000000 --subq_s.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdbffdc00 DSPCtrl 0x00000000 --subq_s.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb392d6 DSPCtrl 0x00000000 --subq_s.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7fffff91 DSPCtrl 0x00000000 --subq_s.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --subq_s.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2a90 DSPCtrl 0x00000000 --subq_s.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x7fffffff DSPCtrl 0x00100000 --subq_s.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x7fffffff DSPCtrl 0x00100000 --subq_s.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x78757a95 DSPCtrl 0x00000000 --subq_s.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1b85b2f7 DSPCtrl 0x00000000 --subq_s.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225023 DSPCtrl 0x00000000 --subq_s.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x80000000 DSPCtrl 0x00100000 --subq_s.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215e62ba DSPCtrl 0x00000000 ---------- SUBU.QB -------- --subu.qb $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff DSPCtrl 0x00000000 --subu.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 DSPCtrl 0x00000000 --subu.qb $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 --subu.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941fccfc DSPCtrl 0x00100000 --subu.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 --subu.qb $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fe0102 DSPCtrl 0x00100000 --subu.qb $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x0000f105 DSPCtrl 0x00100000 --subu.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000bfcb DSPCtrl 0x00100000 --subu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --subu.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --subu.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x55555555 DSPCtrl 0x00000000 --subu.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0101dce3 DSPCtrl 0x00100000 --subu.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 --subu.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00100000 --subu.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --subu.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 --subu.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 --subu.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x71717189 DSPCtrl 0x00100000 --subu.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa48a5868 DSPCtrl 0x00100000 --subu.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xafefefef DSPCtrl 0x00100000 --subu.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdc00dc00 DSPCtrl 0x00100000 --subu.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb393d6 DSPCtrl 0x00100000 --subu.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x80000091 DSPCtrl 0x00100000 --subu.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --subu.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2b90 DSPCtrl 0x00100000 --subu.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x94d01282 DSPCtrl 0x00100000 --subu.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x9a27754f DSPCtrl 0x00100000 --subu.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x79767b95 DSPCtrl 0x00100000 --subu.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1c86b3f7 DSPCtrl 0x00100000 --subu.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225123 DSPCtrl 0x00100000 --subu.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7d47360a DSPCtrl 0x00100000 --subu.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f62ba DSPCtrl 0x00100000 ---------- SUBU_S.QB -------- --subu_s.qb $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff DSPCtrl 0x00000000 --subu_s.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 DSPCtrl 0x00000000 --subu_s.qb $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 --subu_s.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x001f0000 DSPCtrl 0x00100000 --subu_s.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 --subu_s.qb $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00fe0000 DSPCtrl 0x00100000 --subu_s.qb $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000bf00 DSPCtrl 0x00100000 --subu_s.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --subu_s.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 --subu_s.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x55555555 DSPCtrl 0x00000000 --subu_s.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 --subu_s.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00773c1e DSPCtrl 0x00100000 --subu_s.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --subu_s.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 --subu_s.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 --subu_s.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaf000000 DSPCtrl 0x00100000 --subu_s.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00b39300 DSPCtrl 0x00100000 --subu_s.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --subu_s.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2b00 DSPCtrl 0x00100000 --subu_s.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x00001282 DSPCtrl 0x00100000 --subu_s.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x0000754f DSPCtrl 0x00100000 --subu_s.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x00000000 DSPCtrl 0x00100000 --subu_s.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225100 DSPCtrl 0x00100000 --subu_s.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7d00360a DSPCtrl 0x00100000 --subu_s.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f00ba DSPCtrl 0x00100000 -Index: none/tests/mips32/mips32_dsp.stdout.exp-BE -=================================================================== ---- none/tests/mips32/mips32_dsp.stdout.exp-BE (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/mips32_dsp.stdout.exp-BE (.../trunk) (revision 13981) -@@ -11,14 +11,14 @@ - absq_s.ph $t2, $t3 :: rd 0x05555214 rt 0x0555adec DSPControl 0x0 - absq_s.ph $t4, $t1 :: rd 0x67f57cde rt 0x980b7cde DSPControl 0x0 - absq_s.ph $t6, $t7 :: rd 0x068d437b rt 0xf973437b DSPControl 0x0 --absq_s.ph $t5, $t3 :: rd 0x6cb94bde rt 0x93474bde DSPControl 0x0 -+absq_s.ph $t5, $t3 :: rd 0x23c54b6e rt 0x23c54b6e DSPControl 0x0 - absq_s.ph $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 - absq_s.ph $t0, $t8 :: rd 0x3b2501e0 rt 0xc4dbfe20 DSPControl 0x0 - absq_s.ph $t4, $t4 :: rd 0x73467f44 rt 0x734680bc DSPControl 0x0 - absq_s.ph $t0, $t1 :: rd 0x00354565 rt 0x00354565 DSPControl 0x0 - absq_s.ph $t2, $t3 :: rd 0x45364536 rt 0xbacabaca DSPControl 0x0 --absq_s.ph $t4, $t1 :: rd 0x21362136 rt 0xdecadeca DSPControl 0x0 --absq_s.ph $t6, $t7 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 -+absq_s.ph $t4, $t1 :: rd 0x245d7137 rt 0xdba38ec9 DSPControl 0x0 -+absq_s.ph $t6, $t7 :: rd 0x0b300286 rt 0x0b300286 DSPControl 0x0 - absq_s.ph $t5, $t3 :: rd 0x54555455 rt 0xabababab DSPControl 0x0 - absq_s.ph $t2, $t4 :: rd 0x00086755 rt 0x00086755 DSPControl 0x0 - absq_s.ph $t0, $t8 :: rd 0x70717080 rt 0x8f8f8f80 DSPControl 0x0 -@@ -56,14 +56,14 @@ - absq_s.w $t2, $t3 :: rd 0x0555adec rt 0x0555adec DSPControl 0x0 - absq_s.w $t4, $t1 :: rd 0x67f48322 rt 0x980b7cde DSPControl 0x0 - absq_s.w $t6, $t7 :: rd 0x068cbc85 rt 0xf973437b DSPControl 0x0 --absq_s.w $t5, $t3 :: rd 0x6cb8b422 rt 0x93474bde DSPControl 0x0 -+absq_s.w $t5, $t3 :: rd 0x23c54b6e rt 0x23c54b6e DSPControl 0x0 - absq_s.w $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 - absq_s.w $t0, $t8 :: rd 0x3b2401e0 rt 0xc4dbfe20 DSPControl 0x0 - absq_s.w $t4, $t4 :: rd 0x734680bc rt 0x734680bc DSPControl 0x0 - absq_s.w $t0, $t1 :: rd 0x00354565 rt 0x00354565 DSPControl 0x0 - absq_s.w $t2, $t3 :: rd 0x45354536 rt 0xbacabaca DSPControl 0x0 --absq_s.w $t4, $t1 :: rd 0x21352136 rt 0xdecadeca DSPControl 0x0 --absq_s.w $t6, $t7 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 -+absq_s.w $t4, $t1 :: rd 0x245c7137 rt 0xdba38ec9 DSPControl 0x0 -+absq_s.w $t6, $t7 :: rd 0x0b300286 rt 0x0b300286 DSPControl 0x0 - absq_s.w $t5, $t3 :: rd 0x54545455 rt 0xabababab DSPControl 0x0 - absq_s.w $t2, $t4 :: rd 0x00086755 rt 0x00086755 DSPControl 0x0 - absq_s.w $t0, $t8 :: rd 0x70707080 rt 0x8f8f8f80 DSPControl 0x0 -@@ -94,17 +94,17 @@ - addq.ph $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 - addq.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 - addq.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 --addq.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --addq.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 --addq.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addq.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addq.ph $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf7fef321 DSPCtrl 0x00100000 -+addq.ph $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 - addq.ph $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 - addq.ph $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 - addq.ph $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99a0000 DSPCtrl 0x00100000 --addq.ph $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 -+addq.ph $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00100000 - addq.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 - addq.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 - addq.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addq.ph $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 - addq.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 - addq.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 - addq.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -@@ -134,40 +134,45 @@ - addq_s.ph $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 - addq_s.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 - addq_s.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x8000437b DSPCtrl 0x00100000 --addq_s.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00100000 --addq_s.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq_s.ph $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 --addq_s.ph $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x80005856 DSPCtrl 0x00100000 --addq_s.ph $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x7fff8000 DSPCtrl 0x00100000 -+addq_s.ph $t0, $t1, $t2 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0x7fff7322 rt 0x77ff7fff out 0x7fff7fff DSPCtrl 0x00100000 -+addq_s.ph $t4, $t1, $t5 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x80002435 rt 0x80003421 out 0x80005856 DSPCtrl 0x00100000 -+addq_s.ph $t2, $t4, $t8 :: rs 0x76548000 rt 0x73468000 out 0x7fff8000 DSPCtrl 0x00100000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x80000000 rt 0x80620020 out 0x80000020 DSPCtrl 0x00100000 -+addq_s.ph $t4, $t6, $t1 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00100000 -+addq_s.ph $t4, $t1, $t5 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 - addq_s.ph $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00100000 --addq_s.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 --addq_s.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 --addq_s.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 --addq_s.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x80008000 DSPCtrl 0x00100000 --addq_s.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed69a5c2 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 --addq_s.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23887fff DSPCtrl 0x00100000 --addq_s.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98137fff DSPCtrl 0x00100000 --addq_s.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 --addq_s.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81663544 DSPCtrl 0x00000000 --addq_s.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a5a6a5 DSPCtrl 0x00000000 --addq_s.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99949994 DSPCtrl 0x00000000 --addq_s.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6412a92 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 --addq_s.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffefffe DSPCtrl 0x00000000 --addq_s.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3e93ae DSPCtrl 0x00000000 --addq_s.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00000000 --addq_s.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 --addq_s.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05e4c57 DSPCtrl 0x00000000 --addq_s.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0506904f DSPCtrl 0x00000000 --addq_s.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 --addq_s.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x70357fff DSPCtrl 0x00100000 --addq_s.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x800028e0 DSPCtrl 0x00100000 -+addq_s.ph $t2, $t4, $t8 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addq_s.ph $t4, $t6, $t1 :: rs 0xbabababa rt 0xabababab out 0x80008000 DSPCtrl 0x00100000 -+addq_s.ph $t0, $t1, $t2 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed69a5c2 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addq_s.ph $t4, $t1, $t5 :: rs 0x23534870 rt 0x00354565 out 0x23887fff DSPCtrl 0x00100000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x980b7cde rt 0x00086755 out 0x98137fff DSPCtrl 0x00100000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t4, $t8 :: rs 0x92784656 rt 0xeeeeeeee out 0x81663544 DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a5a6a5 DSPCtrl 0x00000000 -+addq_s.ph $t4, $t6, $t1 :: rs 0xbacabaca rt 0xdecadeca out 0x99949994 DSPCtrl 0x00000000 -+addq_s.ph $t0, $t1, $t2 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6412a92 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 -+addq_s.ph $t4, $t1, $t5 :: rs 0xffffffff rt 0xffffffff out 0xfffefffe DSPCtrl 0x00000000 -+addq_s.ph $t6, $t7, $t3 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3e93ae DSPCtrl 0x00000000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t4, $t8 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05e4c57 DSPCtrl 0x00000000 -+addq_s.ph $t4, $t6, $t1 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0506904f DSPCtrl 0x00000000 -+addq_s.ph $t0, $t1, $t2 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0xf63e7a9d rt 0x79f74493 out 0x70357fff DSPCtrl 0x00100000 -+addq_s.ph $t4, $t1, $t5 :: rs 0xbd6845cd rt 0x9c09e313 out 0x800028e0 DSPCtrl 0x00100000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x234ba291 rt 0xbb64981c out 0xdeaf8000 DSPCtrl 0x00100000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x120934de rt 0xad2c7601 out 0xbf357fff DSPCtrl 0x00100000 -+addq_s.ph $t2, $t4, $t8 :: rs 0xf5643908 rt 0xbaff3492 out 0xb0636d9a DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x88503331 rt 0xd60e34a2 out 0x800067d3 DSPCtrl 0x00100000 -+addq_s.ph $t4, $t6, $t1 :: rs 0x7b5309ac rt 0xc5487201 out 0x409b7bad DSPCtrl 0x00000000 - -------- ADDQ_S.W -------- - addq_s.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 - addq_s.w $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 -@@ -174,17 +179,17 @@ - addq_s.w $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 - addq_s.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 - addq_s.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 --addq_s.w $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 --addq_s.w $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fffffff DSPCtrl 0x00100000 --addq_s.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addq_s.w $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addq_s.w $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0x7fffffff DSPCtrl 0x00100000 -+addq_s.w $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 - addq_s.w $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 - addq_s.w $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x80000000 DSPCtrl 0x00100000 - addq_s.w $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x7fffffff DSPCtrl 0x00100000 --addq_s.w $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 -+addq_s.w $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x80000000 DSPCtrl 0x00100000 - addq_s.w $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 - addq_s.w $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fffffff DSPCtrl 0x00100000 - addq_s.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addq_s.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addq_s.w $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 - addq_s.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 - addq_s.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 - addq_s.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -@@ -214,17 +219,17 @@ - addsc $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 - addsc $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 - addsc $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00002000 --addsc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00002000 --addsc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00000000 --addsc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addsc $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addsc $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf7fef321 DSPCtrl 0x00000000 -+addsc $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 - addsc $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 - addsc $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00002000 - addsc $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99b0000 DSPCtrl 0x00000000 --addsc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00002000 -+addsc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00002000 - addsc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00002000 - addsc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00000000 - addsc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addsc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addsc $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 - addsc $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00002000 - addsc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 - addsc $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -@@ -254,17 +259,17 @@ - addu.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 - addu.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcc74 DSPCtrl 0x00100000 - addu.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 --addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xff00ff00 DSPCtrl 0x00100000 --addu.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefefefe DSPCtrl 0x00100000 --addu.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335900 DSPCtrl 0x00100000 -+addu.qb $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf6fef221 DSPCtrl 0x00100000 -+addu.qb $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 - addu.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 - addu.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 - addu.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99a0000 DSPCtrl 0x00100000 --addu.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 -+addu.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00100000 - addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xff00ff00 DSPCtrl 0x00100000 - addu.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefefefe DSPCtrl 0x00100000 - addu.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addu.qb $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 - addu.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 - addu.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 - addu.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -@@ -294,17 +299,17 @@ - addu_s.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 - addu_s.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabccff DSPCtrl 0x00100000 - addu_s.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xff73437b DSPCtrl 0x00100000 --addu_s.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xffffffff DSPCtrl 0x00100000 --addu_s.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefffeff DSPCtrl 0x00100000 --addu_s.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addu_s.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa3359ff DSPCtrl 0x00100000 -+addu_s.qb $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf6fff2ff DSPCtrl 0x00100000 -+addu_s.qb $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 - addu_s.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 - addu_s.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0xff005856 DSPCtrl 0x00100000 - addu_s.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99aff00 DSPCtrl 0x00100000 --addu_s.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0xff000000 DSPCtrl 0x00100000 -+addu_s.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0xff620020 DSPCtrl 0x00100000 - addu_s.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xffffffff DSPCtrl 0x00100000 - addu_s.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefffeff DSPCtrl 0x00100000 - addu_s.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addu_s.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addu_s.qb $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 - addu_s.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0xff000000 DSPCtrl 0x00100000 - addu_s.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 - addu_s.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -@@ -334,17 +339,17 @@ - addwc $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 - addwc $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 - addwc $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 --addwc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 --addwc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 --addwc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addwc $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addwc $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf7fef321 DSPCtrl 0x00100000 -+addwc $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 - addwc $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 - addwc $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 - addwc $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99b0000 DSPCtrl 0x00100000 --addwc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 -+addwc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00100000 - addwc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 - addwc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 - addwc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 --addwc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addwc $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 - addwc $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 - addwc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 - addwc $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -@@ -369,15 +374,15 @@ - addwc $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00000000 - addwc $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597228e0 DSPCtrl 0x00100000 - -------- BITREV -------- --bitrev $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+bitrev $t0, $t1 :: rd 0x00000012 rt 0x09ba4800 - bitrev $t2, $t3 :: rd 0x0000614c rt 0x80003286 - bitrev $t4, $t1 :: rd 0x0000ac24 rt 0xfabc2435 - bitrev $t6, $t7 :: rd 0x00000001 rt 0x73468000 --bitrev $t5, $t3 :: rd 0x00000000 rt 0x80000000 --bitrev $t2, $t4 :: rd 0x0000ffff rt 0xffffffff -+bitrev $t5, $t3 :: rd 0x00000096 rt 0x803c6900 -+bitrev $t2, $t4 :: rd 0x0000f492 rt 0xffad492f - bitrev $t0, $t8 :: rd 0x0000fffa rt 0xfff45fff - bitrev $t2, $t4 :: rd 0x0000aaa0 rt 0x00000555 --bitrev $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+bitrev $t0, $t1 :: rd 0x000010cf rt 0x0098f308 - bitrev $t2, $t3 :: rd 0x00000000 rt 0x80000000 - bitrev $t4, $t1 :: rd 0x0000aaaa rt 0x55555555 - bitrev $t6, $t7 :: rd 0x0000ac24 rt 0xffff2435 -@@ -518,18 +523,18 @@ - cmp.le.ph $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x02000000 - cmp.le.ph $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 - -------- CMPGU.EQ.QB -------- --cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f -+cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x00672300 rt 0x00000000 out 0x00000009 - cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000008 - cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x00000000 - cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000000 - cmpgu.eq.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 --cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 --cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f --cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000c -+cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xf08b4631 out 0x00000000 -+cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x5cbd891a rt 0x7fff7fff out 0x00000000 -+cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x0ab64555 out 0x00000000 - cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000006 - cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0000000c - cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000003 --cmpgu.eq.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x0000000f -+cmpgu.eq.qb $t5, $t3, $t2 :: rs 0x8007c560 rt 0x80000000 out 0x00000008 - cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 - cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f - cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000c -@@ -558,18 +563,18 @@ - cmpgu.eq.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000000 - cmpgu.eq.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000000 - -------- CMPGU.LT.QB -------- --cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x00672300 rt 0x00000000 out 0x00000000 - cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000000 - cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x0000000e - cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0000000b - cmpgu.lt.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 --cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f --cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x00000000 --cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000001 -+cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xf08b4631 out 0x0000000f -+cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x5cbd891a rt 0x7fff7fff out 0x0000000d -+cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x0ab64555 out 0x0000000d - cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000008 - cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00000002 - cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000000 --cmpgu.lt.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x00000000 -+cmpgu.lt.qb $t5, $t3, $t2 :: rs 0x8007c560 rt 0x80000000 out 0x00000000 - cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f - cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x00000000 - cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000001 -@@ -598,18 +603,18 @@ - cmpgu.lt.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000004 - cmpgu.lt.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000002 - -------- CMPGU.LE.QB -------- --cmpgu.le.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f -+cmpgu.le.qb $t0, $t1, $t2 :: rs 0x00672300 rt 0x00000000 out 0x00000009 - cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000008 - cmpgu.le.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x0000000e - cmpgu.le.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0000000b - cmpgu.le.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 --cmpgu.le.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f --cmpgu.le.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f --cmpgu.le.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000d -+cmpgu.le.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xf08b4631 out 0x0000000f -+cmpgu.le.qb $t0, $t8, $t0 :: rs 0x5cbd891a rt 0x7fff7fff out 0x0000000d -+cmpgu.le.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x0ab64555 out 0x0000000d - cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x0000000e - cmpgu.le.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0000000e - cmpgu.le.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000003 --cmpgu.le.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x0000000f -+cmpgu.le.qb $t5, $t3, $t2 :: rs 0x8007c560 rt 0x80000000 out 0x00000008 - cmpgu.le.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f - cmpgu.le.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f - cmpgu.le.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000d -@@ -1206,6 +1211,11 @@ - extpv $t3, $ac0, $t1 :: rt 0x000002ca ac0 0xcacacaca1bdbdbdb rs 0xbacabaca DSPCtrl 0x0000003a - extpv $t4, $ac1, $t4 :: rt 0x0000056f ac1 0xbacabacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00000013 - -------- EXTR_S.H -------- -+extr_s.h $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr_s.h $t5, $ac0, 31 :: rt 0x00007fff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr_s.h $t6, $ac1, 31 :: rt 0x00007fff ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00800000 -+extr_s.h $t7, $ac2, 0 :: rt 0xffff8000 ac2 0xff34bc6fffffffff size 0 DSPCtrl 0x00800000 -+extr_s.h $t8, $ac3, 1 :: rt 0x00007fff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00800000 - extr_s.h $t1, $ac0, 31 :: rt 0xffff8000 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000 - extr_s.h $t2, $ac1, 17 :: rt 0xffff8000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000 - extr_s.h $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 -@@ -1215,7 +1225,6 @@ - extr_s.h $t7, $ac2, 16 :: rt 0x00007fff ac2 0x00000001ffffffff size 16 DSPCtrl 0x00800000 - extr_s.h $t8, $ac3, 22 :: rt 0xffffffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000000 - extr_s.h $t0, $ac0, 9 :: rt 0x00007fff ac0 0x0000cdfe0fde3126 size 9 DSPCtrl 0x00800000 --extr_s.h $t1, $ac1, 5 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 - extr_s.h $t2, $ac2, 14 :: rt 0x00007fff ac2 0x00000018ffff2435 size 14 DSPCtrl 0x00800000 - extr_s.h $t1, $ac1, 20 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 size 20 DSPCtrl 0x00800000 - extr_s.h $t2, $ac2, 16 :: rt 0x00007fff ac2 0x00000018ffff2435 size 16 DSPCtrl 0x00800000 -@@ -1255,6 +1264,11 @@ - extr_s.h $t3, $ac0, 1 :: rt 0x00007fff ac0 0x0000000079f74493 size 1 DSPCtrl 0x00800000 - extr_s.h $t4, $ac1, 0 :: rt 0xffff8000 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00800000 - -------- EXTR.W -------- -+extr.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr.w $t5, $ac0, 31 :: rt 0xffffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000 -+extr.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0xffffffffffffffff size 0 DSPCtrl 0x00000000 -+extr.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00000000 - extr.w $t1, $ac0, 31 :: rt 0x00000001 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000 - extr.w $t2, $ac1, 17 :: rt 0x0000c000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000 - extr.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 -@@ -1264,7 +1278,6 @@ - extr.w $t7, $ac2, 16 :: rt 0x0001ffff ac2 0x00000001ffffffff size 16 DSPCtrl 0x00000000 - extr.w $t8, $ac3, 22 :: rt 0xffffffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000000 - extr.w $t0, $ac0, 9 :: rt 0xff7e8718 ac0 0x0000cdfefd0e3126 size 9 DSPCtrl 0x00800000 --extr.w $t1, $ac1, 5 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 - extr.w $t2, $ac2, 14 :: rt 0x0063fffc ac2 0x00000018ffff2435 size 14 DSPCtrl 0x00000000 - extr.w $t1, $ac1, 20 :: rt 0xaaaaa555 ac1 0xaaaaaaaa55555555 size 20 DSPCtrl 0x00800000 - extr.w $t2, $ac2, 16 :: rt 0x0018ffff ac2 0x00000018ffff2435 size 16 DSPCtrl 0x00000000 -@@ -1304,12 +1317,17 @@ - extr.w $t3, $ac0, 1 :: rt 0x3cfba249 ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 - extr.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 - -------- EXTR_R.W -------- --extr_r.w $t1, $ac0, 31 :: rt 0xffffffff ac0 0xffffffff80000000 size 31 DSPCtrl 0x00000000 --extr_r.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 --extr_r.w $t5, $ac0, 3 :: rt 0x10000000 ac0 0x000000007fffffff size 3 DSPCtrl 0x00000000 --extr_r.w $t6, $ac1, 8 :: rt 0x00000000 ac1 0x0000000000000001 size 8 DSPCtrl 0x00000000 --extr_r.w $t7, $ac2, 16 :: rt 0x00000000 ac2 0xffffffffffffffff size 16 DSPCtrl 0x00000000 --extr_r.w $t0, $ac0, 9 :: rt 0xfffe8719 ac0 0xfffffffffd0e3126 size 9 DSPCtrl 0x00000000 -+extr_r.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr_r.w $t5, $ac0, 31 :: rt 0x00000000 ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr_r.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000 -+extr_r.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0x987b2fffffffffff size 0 DSPCtrl 0x00800000 -+extr_r.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x000cd320fffffffe size 1 DSPCtrl 0x00800000 -+extr_r.w $t1, $ac0, 31 :: rt 0xfff36a83 ac0 0xfff9b54180000000 size 31 DSPCtrl 0x00000000 -+extr_r.w $t3, $ac2, 4 :: rt 0xc0000000 ac2 0x0008b31c00000006 size 4 DSPCtrl 0x00800000 -+extr_r.w $t5, $ac0, 3 :: rt 0xb0000000 ac0 0x0086b3ad7fffffff size 3 DSPCtrl 0x00800000 -+extr_r.w $t6, $ac1, 8 :: rt 0x51000000 ac1 0x00097b5100000001 size 8 DSPCtrl 0x00800000 -+extr_r.w $t7, $ac2, 16 :: rt 0x44000000 ac2 0xfcde43ffffffffff size 16 DSPCtrl 0x00800000 -+extr_r.w $t0, $ac0, 9 :: rt 0x137e8719 ac0 0xffffca26fd0e3126 size 9 DSPCtrl 0x00800000 - extr_r.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 - extr_r.w $t2, $ac2, 14 :: rt 0xfffffffd ac2 0xffffffffffff2435 size 14 DSPCtrl 0x00000000 - extr_r.w $t1, $ac1, 20 :: rt 0x00000555 ac1 0x0000000055555555 size 20 DSPCtrl 0x00000000 -@@ -1320,11 +1338,11 @@ - extr_r.w $t4, $ac0, 13 :: rt 0xffffe3ce ac0 0xfffffffffc79b4d2 size 13 DSPCtrl 0x00000000 - extr_r.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 - extr_r.w $t6, $ac2, 27 :: rt 0x00000000 ac2 0x0000000000000000 size 27 DSPCtrl 0x00000000 --extr_r.w $t7, $ac3, 7 :: rt 0x00246931 ac3 0x0000000012349876 size 7 DSPCtrl 0x00000000 --extr_r.w $t8, $ac0, 11 :: rt 0x000006a9 ac0 0x0000000000354565 size 11 DSPCtrl 0x00000000 --extr_r.w $t0, $ac1, 26 :: rt 0xffffffe0 ac1 0xffffffff80006755 size 26 DSPCtrl 0x00000000 --extr_r.w $t1, $ac2, 15 :: rt 0xffff1f1f ac2 0xffffffff8f8f8f8f size 15 DSPCtrl 0x00000000 --extr_r.w $t2, $ac3, 2 :: rt 0xfbbbbbbc ac3 0xffffffffeeeeeeee size 2 DSPCtrl 0x00000000 -+extr_r.w $t7, $ac3, 7 :: rt 0x00246931 ac3 0x02934b0012349876 size 7 DSPCtrl 0x00800000 -+extr_r.w $t8, $ac0, 11 :: rt 0x5a0006a9 ac0 0x0008cad000354565 size 11 DSPCtrl 0x00800000 -+extr_r.w $t0, $ac1, 26 :: rt 0x9723ffe0 ac1 0xf65c8fff80006755 size 26 DSPCtrl 0x00800000 -+extr_r.w $t1, $ac2, 15 :: rt 0xe0031f1f ac2 0xfffff0018f8f8f8f size 15 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac3, 2 :: rt 0x3bbbbbbc ac3 0xbad69420eeeeeeee size 2 DSPCtrl 0x00800000 - extr_r.w $t3, $ac0, 1 :: rt 0x0dededee ac0 0x000000001bdbdbdb size 1 DSPCtrl 0x00000000 - extr_r.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xffffffffdecadeca size 0 DSPCtrl 0x00000000 - extr_r.w $t5, $ac0, 3 :: rt 0x0bf9252f ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 -@@ -1350,12 +1368,17 @@ - extr_r.w $t3, $ac0, 1 :: rt 0x3cfba24a ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 - extr_r.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 - -------- EXTR_RS.W -------- --extr_rs.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 --extr_rs.w $t5, $ac0, 3 :: rt 0x10000000 ac0 0x000000007fffffff size 3 DSPCtrl 0x00000000 --extr_rs.w $t6, $ac1, 8 :: rt 0x00000000 ac1 0x0000000000000001 size 8 DSPCtrl 0x00000000 --extr_rs.w $t7, $ac2, 16 :: rt 0x00000000 ac2 0xffffffffffffffff size 16 DSPCtrl 0x00000000 --extr_rs.w $t8, $ac3, 22 :: rt 0x00000000 ac3 0xffffffffffffffff size 2 DSPCtrl 0x00000000 --extr_rs.w $t0, $ac0, 9 :: rt 0xfffe8719 ac0 0xfffffffffd0e3126 size 9 DSPCtrl 0x00000000 -+extr_rs.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr_rs.w $t5, $ac0, 31 :: rt 0x7fffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr_rs.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000 -+extr_rs.w $t7, $ac2, 0 :: rt 0x80000000 ac2 0x987b2fffffffffff size 0 DSPCtrl 0x00800000 -+extr_rs.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x000cd320fffffffe size 1 DSPCtrl 0x00800000 -+extr_rs.w $t3, $ac2, 4 :: rt 0x80000000 ac2 0xfff9b54180000000 size 4 DSPCtrl 0x00800000 -+extr_rs.w $t5, $ac0, 3 :: rt 0x7fffffff ac0 0x0008b31c00000006 size 3 DSPCtrl 0x00800000 -+extr_rs.w $t6, $ac1, 8 :: rt 0x7fffffff ac1 0x0086b3ad7fffffff size 8 DSPCtrl 0x00800000 -+extr_rs.w $t7, $ac2, 16 :: rt 0x7fffffff ac2 0x00097b5100000001 size 16 DSPCtrl 0x00800000 -+extr_rs.w $t8, $ac3, 22 :: rt 0x80000000 ac3 0xfcde43ffffffffff size 2 DSPCtrl 0x00800000 -+extr_rs.w $t0, $ac0, 9 :: rt 0x80000000 ac0 0xffffca26fd0e3126 size 9 DSPCtrl 0x00800000 - extr_rs.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 - extr_rs.w $t2, $ac2, 14 :: rt 0xfffffffd ac2 0xffffffffffff2435 size 14 DSPCtrl 0x00000000 - extr_rs.w $t1, $ac1, 20 :: rt 0x00000555 ac1 0x0000000055555555 size 0 DSPCtrl 0x00000000 -@@ -1366,11 +1389,11 @@ - extr_rs.w $t4, $ac0, 13 :: rt 0xffffe3ce ac0 0xfffffffffc79b4d2 size 13 DSPCtrl 0x00000000 - extr_rs.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 - extr_rs.w $t6, $ac2, 27 :: rt 0x00000000 ac2 0x0000000000000000 size 27 DSPCtrl 0x00000000 --extr_rs.w $t7, $ac3, 7 :: rt 0x00246931 ac3 0x0000000012349876 size 7 DSPCtrl 0x00000000 --extr_rs.w $t8, $ac0, 11 :: rt 0x000006a9 ac0 0x0000000000354565 size 11 DSPCtrl 0x00000000 --extr_rs.w $t0, $ac1, 26 :: rt 0xffffffe0 ac1 0xffffffff80006755 size 26 DSPCtrl 0x00000000 --extr_rs.w $t1, $ac2, 15 :: rt 0xffff1f1f ac2 0xffffffff8f8f8f8f size 15 DSPCtrl 0x00000000 --extr_rs.w $t2, $ac3, 2 :: rt 0xfbbbbbbc ac3 0xffffffffeeeeeeee size 2 DSPCtrl 0x00000000 -+extr_rs.w $t7, $ac3, 7 :: rt 0x7fffffff ac3 0x02934b0012349876 size 7 DSPCtrl 0x00800000 -+extr_rs.w $t8, $ac0, 11 :: rt 0x7fffffff ac0 0x0008cad000354565 size 11 DSPCtrl 0x00800000 -+extr_rs.w $t0, $ac1, 26 :: rt 0x80000000 ac1 0xf65c8fff80006755 size 26 DSPCtrl 0x00800000 -+extr_rs.w $t1, $ac2, 15 :: rt 0xe0031f1f ac2 0xfffff0018f8f8f8f size 15 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac3, 2 :: rt 0x80000000 ac3 0xbad69420eeeeeeee size 2 DSPCtrl 0x00800000 - extr_rs.w $t3, $ac0, 1 :: rt 0x0dededee ac0 0x000000001bdbdbdb size 1 DSPCtrl 0x00000000 - extr_rs.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xffffffffdecadeca size 0 DSPCtrl 0x00000000 - extr_rs.w $t5, $ac0, 3 :: rt 0x0bf9252f ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 -@@ -1396,6 +1419,11 @@ - extr_rs.w $t3, $ac0, 1 :: rt 0x3cfba24a ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 - extr_rs.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 - -------- EXTRV_S.H -------- -+extrv_s.h $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv_s.h $t2, $ac2, $t4 :: rt 0x00007fff ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac1, $t7 :: rt 0x00007fff ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv_s.h $t1, $ac1, $t2 :: rt 0x00007fff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00800000 - extrv_s.h $t2, $ac1, $t1 :: rt 0xffff8000 ac1 0x8000000180000002 rs 0x12349876 DSPCtrl 0x00800000 - extrv_s.h $t1, $ac0, $t0 :: rt 0xffff8000 ac0 0x8000000080000000 rs 0x12349876 DSPCtrl 0x00800000 - extrv_s.h $t3, $ac2, $t2 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x00354565 DSPCtrl 0x00000000 -@@ -1445,9 +1473,14 @@ - extrv_s.h $t3, $ac0, $t0 :: rt 0x00007fff ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00800000 - extrv_s.h $t4, $ac1, $t1 :: rt 0xffff8000 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00800000 - -------- EXTRV.W -------- --extrv.w $t1, $ac1, $t3 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 rs 0xbababa05 DSPCtrl 0x00800000 -+extrv.w $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv.w $t2, $ac2, $t4 :: rt 0xffffffff ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv.w $t1, $ac1, $t7 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00000000 -+extrv.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t2 :: rt 0x7fffffff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t3 :: rt 0xd2aaaaaa ac1 0xaaabad3a55555555 rs 0xbababa05 DSPCtrl 0x00800000 - extrv.w $t2, $ac2, $t4 :: rt 0x0063fffc ac2 0x00000018ffff2435 rs 0xfbde390e DSPCtrl 0x00000000 --extrv.w $t1, $ac1, $t7 :: rt 0xaaaaa555 ac1 0xaaaaaaaa55555555 rs 0x55555514 DSPCtrl 0x00800000 -+extrv.w $t1, $ac1, $t7 :: rt 0xaa221555 ac1 0xaaaaa22155555555 rs 0x55555514 DSPCtrl 0x00800000 - extrv.w $t2, $ac2, $t5 :: rt 0x0018ffff ac2 0x00000018ffff2435 rs 0x0000cd10 DSPCtrl 0x00000000 - extrv.w $t1, $ac1, $t2 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 rs 0x80000005 DSPCtrl 0x00800000 - extrv.w $t2, $ac2, $t3 :: rt 0x000063ff ac2 0x00000018ffff2435 rs 0x7fffff16 DSPCtrl 0x00000000 -@@ -1494,6 +1527,11 @@ - extrv.w $t3, $ac0, $t0 :: rt 0x0079f744 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 - extrv.w $t4, $ac1, $t1 :: rt 0xe70278c4 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 - -------- EXTRV_R.W -------- -+extrv_r.w $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac2, $t4 :: rt 0x00000000 ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv_r.w $t1, $ac1, $t7 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac1, $t2 :: rt 0x7fffffff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00000000 - extrv_r.w $t1, $ac1, $t3 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0xbababa05 DSPCtrl 0x00000000 - extrv_r.w $t2, $ac2, $t4 :: rt 0xfffffffd ac2 0xffffffffffff2435 rs 0xfbde390e DSPCtrl 0x00000000 - extrv_r.w $t1, $ac1, $t7 :: rt 0x00000555 ac1 0x0000000055555555 rs 0x55555514 DSPCtrl 0x00000000 -@@ -1518,23 +1556,23 @@ - extrv_r.w $t2, $ac3, $t1 :: rt 0xfffbbbbc ac3 0xffffffffeeeeeeee rs 0xcacacaca DSPCtrl 0x00000000 - extrv_r.w $t3, $ac0, $t1 :: rt 0x0006f6f7 ac0 0x000000001bdbdbdb rs 0xbacabaca DSPCtrl 0x00000000 - extrv_r.w $t4, $ac1, $t4 :: rt 0xfff7b2b8 ac1 0xffffffffdecadeca rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_r.w $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_r.w $t5, $ac0, $t8 :: rt 0x878782fe ac0 0xf0f0f0f05fc92974 rs 0xffff2435 DSPCtrl 0x00800000 - extrv_r.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 --extrv_r.w $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 --extrv_r.w $t8, $ac3, $t2 :: rt 0xfffffca5 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 --extrv_r.w $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t4 :: rt 0x000673b2 ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t5 :: rt 0x00001c26 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00000000 --extrv_r.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00000000 --extrv_r.w $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 -+extrv_r.w $t7, $ac2, $t1 :: rt 0xf1cbb38e ac2 0xfbde397671c8315f rs 0xffff2435 DSPCtrl 0x00800000 -+extrv_r.w $t8, $ac3, $t2 :: rt 0x6bb2a4a5 ac3 0x0bed76549493110e rs 0x55555555 DSPCtrl 0x00800000 -+extrv_r.w $t0, $ac0, $t3 :: rt 0x9a4385d9 ac0 0x23534870bb246228 rs 0xffff2435 DSPCtrl 0x00800000 -+extrv_r.w $t1, $ac1, $t4 :: rt 0x9bc673b2 ac1 0x980b7cde339d8d88 rs 0xabababab DSPCtrl 0x00800000 -+extrv_r.w $t2, $ac2, $t5 :: rt 0x00061c26 ac2 0x0000001870974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0x927846568a8d4e7d rs 0x00000000 DSPCtrl 0x00800000 -+extrv_r.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xcacacacaeb1b4335 rs 0x00000000 DSPCtrl 0x00800000 -+extrv_r.w $t1, $ac1, $t8 :: rt 0x2aeb2833 ac1 0xbacabaca0cd6b508 rs 0x12349876 DSPCtrl 0x00800000 - extrv_r.w $t2, $ac2, $t0 :: rt 0x03398f14 ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00000000 --extrv_r.w $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 -+extrv_r.w $t3, $ac3, $t1 :: rt 0x000005b7 ac3 0x00000000b6edf28f rs 0x00086755 DSPCtrl 0x00000000 - extrv_r.w $t4, $ac0, $t2 :: rt 0x0000969e ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00000000 - extrv_r.w $t5, $ac1, $t3 :: rt 0xffff040e ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00000000 - extrv_r.w $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_r.w $t7, $ac3, $t4 :: rt 0xffaf8f7e ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 --extrv_r.w $t8, $ac0, $t5 :: rt 0xff87df45 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00000000 -+extrv_r.w $t7, $ac3, $t4 :: rt 0x00af8f7e ac3 0x00000000af8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 -+extrv_r.w $t8, $ac0, $t5 :: rt 0x0087df45 ac0 0x0000000087df4510 rs 0x339d8d88 DSPCtrl 0x00000000 - extrv_r.w $t0, $ac1, $t6 :: rt 0xffd5fa74 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00000000 - extrv_r.w $t1, $ac2, $t7 :: rt 0x00000000 ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 - extrv_r.w $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 -@@ -1541,6 +1579,12 @@ - extrv_r.w $t3, $ac0, $t0 :: rt 0x0079f745 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 - extrv_r.w $t4, $ac1, $t1 :: rt 0xe70278c5 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 - -------- EXTRV_RS.W -------- -+extrv_rs.w $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t3 :: rt 0x80000000 ac1 0x987b2fffffffffff rs 0xbababa00 DSPCtrl 0x00800000 -+extrv_rs.w $t2, $ac2, $t4 :: rt 0x7fffffff ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv_rs.w $t1, $ac1, $t7 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t2 :: rt 0x7fffffff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00000000 - extrv_rs.w $t1, $ac1, $t3 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0xbababa05 DSPCtrl 0x00000000 - extrv_rs.w $t2, $ac2, $t4 :: rt 0xfffffffd ac2 0xffffffffffff2435 rs 0xfbde390e DSPCtrl 0x00000000 - extrv_rs.w $t1, $ac1, $t7 :: rt 0x00000555 ac1 0x0000000055555555 rs 0x55555514 DSPCtrl 0x00000000 -@@ -1555,16 +1599,16 @@ - extrv_rs.w $t7, $ac2, $t8 :: rt 0x00000000 ac2 0xffffffffffffffff rs 0xaaaaaaaa DSPCtrl 0x00000000 - extrv_rs.w $t8, $ac3, $t9 :: rt 0x00000000 ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 - extrv_rs.w $t4, $ac0, $t3 :: rt 0xfffffff2 ac0 0xfffffffffc79b4d2 rs 0x12349876 DSPCtrl 0x00000000 --extrv_rs.w $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000000 -+extrv_rs.w $t5, $ac1, $t4 :: rt 0x80000000 ac1 0xf0f0f0f000000000 rs 0x00354565 DSPCtrl 0x00800000 - extrv_rs.w $t6, $ac2, $t5 :: rt 0x00000000 ac2 0x0000000000000000 rs 0x00086755 DSPCtrl 0x00000000 --extrv_rs.w $t7, $ac3, $t6 :: rt 0x00000012 ac3 0x0000000012349876 rs 0x00000018 DSPCtrl 0x00000000 --extrv_rs.w $t8, $ac0, $t7 :: rt 0x00000035 ac0 0x0000000000354565 rs 0x23534870 DSPCtrl 0x00000000 --extrv_rs.w $t0, $ac1, $t8 :: rt 0x00000000 ac1 0x0000000000086755 rs 0x92784656 DSPCtrl 0x00000000 --extrv_rs.w $t1, $ac2, $t9 :: rt 0xfffe3e3e ac2 0xffffffff8f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00000000 --extrv_rs.w $t2, $ac3, $t1 :: rt 0xfffbbbbc ac3 0xffffffffeeeeeeee rs 0xcacacaca DSPCtrl 0x00000000 --extrv_rs.w $t3, $ac0, $t1 :: rt 0x0006f6f7 ac0 0x000000001bdbdbdb rs 0xbacabaca DSPCtrl 0x00000000 --extrv_rs.w $t4, $ac1, $t4 :: rt 0xfff7b2b8 ac1 0xffffffffdecadeca rs 0x1bdbdbdb DSPCtrl 0x00000000 --extrv_rs.w $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_rs.w $t7, $ac3, $t6 :: rt 0x80000000 ac3 0xfbde397612349876 rs 0x00000018 DSPCtrl 0x00800000 -+extrv_rs.w $t8, $ac0, $t7 :: rt 0x7fffffff ac0 0x0bed765400354565 rs 0x23534870 DSPCtrl 0x00800000 -+extrv_rs.w $t0, $ac1, $t8 :: rt 0x7fffffff ac1 0x2353487000086755 rs 0x92784656 DSPCtrl 0x00800000 -+extrv_rs.w $t1, $ac2, $t9 :: rt 0x80000000 ac2 0x980b7cde8f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00800000 -+extrv_rs.w $t2, $ac3, $t1 :: rt 0x063bbbbc ac3 0x00000018eeeeeeee rs 0xcacacaca DSPCtrl 0x00000000 -+extrv_rs.w $t3, $ac0, $t1 :: rt 0x80000000 ac0 0x927846561bdbdbdb rs 0xbacabaca DSPCtrl 0x00800000 -+extrv_rs.w $t4, $ac1, $t4 :: rt 0x80000000 ac1 0xcacacacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00800000 -+extrv_rs.w $t5, $ac0, $t8 :: rt 0x80000000 ac0 0xbacabaca5fc92974 rs 0xffff2435 DSPCtrl 0x00800000 - extrv_rs.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 - extrv_rs.w $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 - extrv_rs.w $t8, $ac3, $t2 :: rt 0xfffffca5 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 -@@ -3937,6 +3981,11 @@ - subq.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f62ba DSPCtrl 0x00000000 - -------- SUBQ_S.PH -------- - subq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t3, $t4 :: rs 0x00020002 rt 0x00010001 out 0x00010001 DSPCtrl 0x00000000 -+subq_s.ph $t4, $t1, $t5 :: rs 0x0002fffe rt 0x0001ffff out 0x0001ffff DSPCtrl 0x00000000 -+subq_s.ph $t6, $t7, $t3 :: rs 0x7fff8000 rt 0x7fff8000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t5, $t3, $t2 :: rs 0x7fff8000 rt 0x7ffe8001 out 0x0001ffff DSPCtrl 0x00000000 -+subq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 - subq_s.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x045d2c00 DSPCtrl 0x00000000 - subq_s.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 - subq_s.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941f7fff DSPCtrl 0x00100000 -Index: none/tests/mips32/mips32_dsp.stdout.exp-LE -=================================================================== ---- none/tests/mips32/mips32_dsp.stdout.exp-LE (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/mips32_dsp.stdout.exp-LE (.../trunk) (revision 13981) -@@ -0,0 +1,4118 @@ -+-------- ABSQ_S.PH -------- -+absq_s.ph $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0 -+absq_s.ph $t2, $t3 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 -+absq_s.ph $t4, $t1 :: rd 0x05442435 rt 0xfabc2435 DSPControl 0x0 -+absq_s.ph $t6, $t7 :: rd 0x73467fff rt 0x73468000 DSPControl 0x100000 -+absq_s.ph $t5, $t3 :: rd 0x7fff0000 rt 0x80000000 DSPControl 0x100000 -+absq_s.ph $t2, $t4 :: rd 0x00010001 rt 0xffffffff DSPControl 0x0 -+absq_s.ph $t0, $t8 :: rd 0x000c5fff rt 0xfff45fff DSPControl 0x0 -+absq_s.ph $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0 -+absq_s.ph $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0 -+absq_s.ph $t2, $t3 :: rd 0x05555214 rt 0x0555adec DSPControl 0x0 -+absq_s.ph $t4, $t1 :: rd 0x67f57cde rt 0x980b7cde DSPControl 0x0 -+absq_s.ph $t6, $t7 :: rd 0x068d437b rt 0xf973437b DSPControl 0x0 -+absq_s.ph $t5, $t3 :: rd 0x23c54b6e rt 0x23c54b6e DSPControl 0x0 -+absq_s.ph $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 -+absq_s.ph $t0, $t8 :: rd 0x3b2501e0 rt 0xc4dbfe20 DSPControl 0x0 -+absq_s.ph $t4, $t4 :: rd 0x73467f44 rt 0x734680bc DSPControl 0x0 -+absq_s.ph $t0, $t1 :: rd 0x00354565 rt 0x00354565 DSPControl 0x0 -+absq_s.ph $t2, $t3 :: rd 0x45364536 rt 0xbacabaca DSPControl 0x0 -+absq_s.ph $t4, $t1 :: rd 0x245d7137 rt 0xdba38ec9 DSPControl 0x0 -+absq_s.ph $t6, $t7 :: rd 0x0b300286 rt 0x0b300286 DSPControl 0x0 -+absq_s.ph $t5, $t3 :: rd 0x54555455 rt 0xabababab DSPControl 0x0 -+absq_s.ph $t2, $t4 :: rd 0x00086755 rt 0x00086755 DSPControl 0x0 -+absq_s.ph $t0, $t8 :: rd 0x70717080 rt 0x8f8f8f80 DSPControl 0x0 -+absq_s.ph $t4, $t4 :: rd 0x11121112 rt 0xeeeeeeee DSPControl 0x0 -+absq_s.ph $t0, $t1 :: rd 0x1bdb2425 rt 0x1bdbdbdb DSPControl 0x0 -+absq_s.ph $t2, $t3 :: rd 0x21362136 rt 0xdecadeca DSPControl 0x0 -+absq_s.ph $t4, $t1 :: rd 0x6cb94bde rt 0x93474bde DSPControl 0x0 -+absq_s.ph $t6, $t7 :: rd 0x05415406 rt 0xfabfabfa DSPControl 0x0 -+absq_s.ph $t5, $t3 :: rd 0x083b3571 rt 0x083b3571 DSPControl 0x0 -+absq_s.ph $t2, $t4 :: rd 0x468c3941 rt 0xb9743941 DSPControl 0x0 -+absq_s.ph $t0, $t8 :: rd 0x438006dc rt 0xbc80f924 DSPControl 0x0 -+absq_s.ph $t4, $t4 :: rd 0x33c4201c rt 0xcc3c201c DSPControl 0x0 -+absq_s.ph $t0, $t1 :: rd 0x1eba0772 rt 0x1ebaf88e DSPControl 0x0 -+absq_s.ph $t2, $t3 :: rd 0x722d5e20 rt 0x722d5e20 DSPControl 0x0 -+absq_s.ph $t4, $t1 :: rd 0x5e2a086f rt 0xa1d6f791 DSPControl 0x0 -+absq_s.ph $t6, $t7 :: rd 0x7b114119 rt 0x7b11bee7 DSPControl 0x0 -+absq_s.ph $t5, $t3 :: rd 0x5a9d1488 rt 0xa5631488 DSPControl 0x0 -+absq_s.ph $t2, $t4 :: rd 0x4ef5339b rt 0xb10bcc65 DSPControl 0x0 -+absq_s.ph $t0, $t8 :: rd 0x73f36036 rt 0x73f39fca DSPControl 0x0 -+absq_s.ph $t4, $t4 :: rd 0x7fff7fff rt 0x80008000 DSPControl 0x100000 -+absq_s.ph $t0, $t1 :: rd 0x00015ba0 rt 0xffffa460 DSPControl 0x0 -+absq_s.ph $t2, $t3 :: rd 0x075c70fa rt 0x075c70fa DSPControl 0x0 -+absq_s.ph $t4, $t1 :: rd 0x0001000d rt 0xfffffff3 DSPControl 0x0 -+absq_s.ph $t6, $t7 :: rd 0x000100ed rt 0xffffff13 DSPControl 0x0 -+-------- ABSQ_S.W -------- -+absq_s.w $t0, $t1 :: rd 0x00000000 rt 0x00000000 DSPControl 0x0 -+absq_s.w $t2, $t3 :: rd 0x00000286 rt 0x00000286 DSPControl 0x0 -+absq_s.w $t4, $t1 :: rd 0x0543dbcb rt 0xfabc2435 DSPControl 0x0 -+absq_s.w $t6, $t7 :: rd 0x73468000 rt 0x73468000 DSPControl 0x0 -+absq_s.w $t5, $t3 :: rd 0x7fffffff rt 0x80000000 DSPControl 0x100000 -+absq_s.w $t2, $t4 :: rd 0x00000001 rt 0xffffffff DSPControl 0x0 -+absq_s.w $t0, $t8 :: rd 0x000ba001 rt 0xfff45fff DSPControl 0x0 -+absq_s.w $t4, $t4 :: rd 0x00000555 rt 0x00000555 DSPControl 0x0 -+absq_s.w $t0, $t1 :: rd 0x23534870 rt 0x23534870 DSPControl 0x0 -+absq_s.w $t2, $t3 :: rd 0x0555adec rt 0x0555adec DSPControl 0x0 -+absq_s.w $t4, $t1 :: rd 0x67f48322 rt 0x980b7cde DSPControl 0x0 -+absq_s.w $t6, $t7 :: rd 0x068cbc85 rt 0xf973437b DSPControl 0x0 -+absq_s.w $t5, $t3 :: rd 0x23c54b6e rt 0x23c54b6e DSPControl 0x0 -+absq_s.w $t2, $t4 :: rd 0x55555555 rt 0x55555555 DSPControl 0x0 -+absq_s.w $t0, $t8 :: rd 0x3b2401e0 rt 0xc4dbfe20 DSPControl 0x0 -+absq_s.w $t4, $t4 :: rd 0x734680bc rt 0x734680bc DSPControl 0x0 -+absq_s.w $t0, $t1 :: rd 0x00354565 rt 0x00354565 DSPControl 0x0 -+absq_s.w $t2, $t3 :: rd 0x45354536 rt 0xbacabaca DSPControl 0x0 -+absq_s.w $t4, $t1 :: rd 0x245c7137 rt 0xdba38ec9 DSPControl 0x0 -+absq_s.w $t6, $t7 :: rd 0x0b300286 rt 0x0b300286 DSPControl 0x0 -+absq_s.w $t5, $t3 :: rd 0x54545455 rt 0xabababab DSPControl 0x0 -+absq_s.w $t2, $t4 :: rd 0x00086755 rt 0x00086755 DSPControl 0x0 -+absq_s.w $t0, $t8 :: rd 0x70707080 rt 0x8f8f8f80 DSPControl 0x0 -+absq_s.w $t4, $t4 :: rd 0x11111112 rt 0xeeeeeeee DSPControl 0x0 -+absq_s.w $t0, $t1 :: rd 0x1bdbdbdb rt 0x1bdbdbdb DSPControl 0x0 -+absq_s.w $t2, $t3 :: rd 0x21352136 rt 0xdecadeca DSPControl 0x0 -+absq_s.w $t4, $t1 :: rd 0x6cb8b422 rt 0x93474bde DSPControl 0x0 -+absq_s.w $t6, $t7 :: rd 0x05405406 rt 0xfabfabfa DSPControl 0x0 -+absq_s.w $t5, $t3 :: rd 0x083b3571 rt 0x083b3571 DSPControl 0x0 -+absq_s.w $t2, $t4 :: rd 0x468bc6bf rt 0xb9743941 DSPControl 0x0 -+absq_s.w $t0, $t8 :: rd 0x437f06dc rt 0xbc80f924 DSPControl 0x0 -+absq_s.w $t4, $t4 :: rd 0x33c3dfe4 rt 0xcc3c201c DSPControl 0x0 -+absq_s.w $t0, $t1 :: rd 0x1ebaf88e rt 0x1ebaf88e DSPControl 0x0 -+absq_s.w $t2, $t3 :: rd 0x722d5e20 rt 0x722d5e20 DSPControl 0x0 -+absq_s.w $t4, $t1 :: rd 0x5e29086f rt 0xa1d6f791 DSPControl 0x0 -+absq_s.w $t6, $t7 :: rd 0x7b11bee7 rt 0x7b11bee7 DSPControl 0x0 -+absq_s.w $t5, $t3 :: rd 0x5a9ceb78 rt 0xa5631488 DSPControl 0x0 -+absq_s.w $t2, $t4 :: rd 0x4ef4339b rt 0xb10bcc65 DSPControl 0x0 -+absq_s.w $t0, $t8 :: rd 0x73f39fca rt 0x73f39fca DSPControl 0x0 -+absq_s.w $t4, $t4 :: rd 0x7fffffff rt 0x80000000 DSPControl 0x100000 -+absq_s.w $t0, $t1 :: rd 0x00005ba0 rt 0xffffa460 DSPControl 0x0 -+absq_s.w $t2, $t3 :: rd 0x075c70fa rt 0x075c70fa DSPControl 0x0 -+absq_s.w $t4, $t1 :: rd 0x0000000d rt 0xfffffff3 DSPControl 0x0 -+absq_s.w $t6, $t7 :: rd 0x000000ed rt 0xffffff13 DSPControl 0x0 -+-------- ADDQ.PH -------- -+addq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addq.ph $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 -+addq.ph $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 -+addq.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 -+addq.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 -+addq.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addq.ph $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf7fef321 DSPCtrl 0x00100000 -+addq.ph $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addq.ph $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addq.ph $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 -+addq.ph $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99a0000 DSPCtrl 0x00100000 -+addq.ph $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00100000 -+addq.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+addq.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 -+addq.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addq.ph $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 -+addq.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 -+addq.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addq.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addq.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x66656665 DSPCtrl 0x00100000 -+addq.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed69a5c2 DSPCtrl 0x00000000 -+addq.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addq.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00100000 -+addq.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00100000 -+addq.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addq.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81663544 DSPCtrl 0x00000000 -+addq.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a5a6a5 DSPCtrl 0x00000000 -+addq.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99949994 DSPCtrl 0x00000000 -+addq.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6412a92 DSPCtrl 0x00000000 -+addq.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 -+addq.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffefffe DSPCtrl 0x00000000 -+addq.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3e93ae DSPCtrl 0x00000000 -+addq.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00000000 -+addq.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addq.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05e4c57 DSPCtrl 0x00000000 -+addq.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0506904f DSPCtrl 0x00000000 -+addq.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 -+addq.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00100000 -+addq.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597128e0 DSPCtrl 0x00100000 -+-------- ADDQ_S.PH -------- -+addq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 -+addq_s.ph $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 -+addq_s.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x8000437b DSPCtrl 0x00100000 -+addq_s.ph $t0, $t1, $t2 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0x7fff7322 rt 0x77ff7fff out 0x7fff7fff DSPCtrl 0x00100000 -+addq_s.ph $t4, $t1, $t5 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x80002435 rt 0x80003421 out 0x80005856 DSPCtrl 0x00100000 -+addq_s.ph $t2, $t4, $t8 :: rs 0x76548000 rt 0x73468000 out 0x7fff8000 DSPCtrl 0x00100000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x80000000 rt 0x80620020 out 0x80000020 DSPCtrl 0x00100000 -+addq_s.ph $t4, $t6, $t1 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00100000 -+addq_s.ph $t4, $t1, $t5 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 -+addq_s.ph $t2, $t4, $t8 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addq_s.ph $t4, $t6, $t1 :: rs 0xbabababa rt 0xabababab out 0x80008000 DSPCtrl 0x00100000 -+addq_s.ph $t0, $t1, $t2 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed69a5c2 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addq_s.ph $t4, $t1, $t5 :: rs 0x23534870 rt 0x00354565 out 0x23887fff DSPCtrl 0x00100000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x980b7cde rt 0x00086755 out 0x98137fff DSPCtrl 0x00100000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t4, $t8 :: rs 0x92784656 rt 0xeeeeeeee out 0x81663544 DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a5a6a5 DSPCtrl 0x00000000 -+addq_s.ph $t4, $t6, $t1 :: rs 0xbacabaca rt 0xdecadeca out 0x99949994 DSPCtrl 0x00000000 -+addq_s.ph $t0, $t1, $t2 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6412a92 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 -+addq_s.ph $t4, $t1, $t5 :: rs 0xffffffff rt 0xffffffff out 0xfffefffe DSPCtrl 0x00000000 -+addq_s.ph $t6, $t7, $t3 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3e93ae DSPCtrl 0x00000000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t4, $t8 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05e4c57 DSPCtrl 0x00000000 -+addq_s.ph $t4, $t6, $t1 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0506904f DSPCtrl 0x00000000 -+addq_s.ph $t0, $t1, $t2 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 -+addq_s.ph $t2, $t3, $t4 :: rs 0xf63e7a9d rt 0x79f74493 out 0x70357fff DSPCtrl 0x00100000 -+addq_s.ph $t4, $t1, $t5 :: rs 0xbd6845cd rt 0x9c09e313 out 0x800028e0 DSPCtrl 0x00100000 -+addq_s.ph $t6, $t7, $t3 :: rs 0x234ba291 rt 0xbb64981c out 0xdeaf8000 DSPCtrl 0x00100000 -+addq_s.ph $t5, $t3, $t2 :: rs 0x120934de rt 0xad2c7601 out 0xbf357fff DSPCtrl 0x00100000 -+addq_s.ph $t2, $t4, $t8 :: rs 0xf5643908 rt 0xbaff3492 out 0xb0636d9a DSPCtrl 0x00000000 -+addq_s.ph $t0, $t8, $t0 :: rs 0x88503331 rt 0xd60e34a2 out 0x800067d3 DSPCtrl 0x00100000 -+addq_s.ph $t4, $t6, $t1 :: rs 0x7b5309ac rt 0xc5487201 out 0x409b7bad DSPCtrl 0x00000000 -+-------- ADDQ_S.W -------- -+addq_s.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addq_s.w $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 -+addq_s.w $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 -+addq_s.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 -+addq_s.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 -+addq_s.w $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addq_s.w $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0x7fffffff DSPCtrl 0x00100000 -+addq_s.w $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addq_s.w $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addq_s.w $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x80000000 DSPCtrl 0x00100000 -+addq_s.w $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x7fffffff DSPCtrl 0x00100000 -+addq_s.w $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x80000000 DSPCtrl 0x00100000 -+addq_s.w $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 -+addq_s.w $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fffffff DSPCtrl 0x00100000 -+addq_s.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addq_s.w $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 -+addq_s.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 DSPCtrl 0x00100000 -+addq_s.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addq_s.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addq_s.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x80000000 DSPCtrl 0x00100000 -+addq_s.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed6aa5c2 DSPCtrl 0x00000000 -+addq_s.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addq_s.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 -+addq_s.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00000000 -+addq_s.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addq_s.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81673544 DSPCtrl 0x00000000 -+addq_s.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a6a6a5 DSPCtrl 0x00000000 -+addq_s.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99959994 DSPCtrl 0x00000000 -+addq_s.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6422a92 DSPCtrl 0x00000000 -+addq_s.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 -+addq_s.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 -+addq_s.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3f93ae DSPCtrl 0x00000000 -+addq_s.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ef0eb2 DSPCtrl 0x00000000 -+addq_s.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addq_s.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05f4c57 DSPCtrl 0x00000000 -+addq_s.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0507904f DSPCtrl 0x00000000 -+addq_s.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 -+addq_s.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00000000 -+addq_s.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x80000000 DSPCtrl 0x00100000 -+-------- ADDSC -------- -+addsc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addsc $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 -+addsc $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 -+addsc $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 -+addsc $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00002000 -+addsc $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addsc $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf7fef321 DSPCtrl 0x00000000 -+addsc $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addsc $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addsc $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00002000 -+addsc $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99b0000 DSPCtrl 0x00000000 -+addsc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00002000 -+addsc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00002000 -+addsc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00000000 -+addsc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addsc $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 -+addsc $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00002000 -+addsc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addsc $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addsc $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x66666665 DSPCtrl 0x00002000 -+addsc $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed6aa5c2 DSPCtrl 0x00002000 -+addsc $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addsc $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 -+addsc $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00000000 -+addsc $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addsc $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81673544 DSPCtrl 0x00002000 -+addsc $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a6a6a5 DSPCtrl 0x00000000 -+addsc $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99959994 DSPCtrl 0x00002000 -+addsc $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6422a92 DSPCtrl 0x00000000 -+addsc $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00002000 -+addsc $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffffffe DSPCtrl 0x00002000 -+addsc $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3f93ae DSPCtrl 0x00002000 -+addsc $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ef0eb2 DSPCtrl 0x00000000 -+addsc $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addsc $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05f4c57 DSPCtrl 0x00000000 -+addsc $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0507904f DSPCtrl 0x00002000 -+addsc $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 -+addsc $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00002000 -+addsc $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597228e0 DSPCtrl 0x00002000 -+-------- ADDU.QB -------- -+addu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addu.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046138 DSPCtrl 0x00100000 -+addu.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 -+addu.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcc74 DSPCtrl 0x00100000 -+addu.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 -+addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335900 DSPCtrl 0x00100000 -+addu.qb $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf6fef221 DSPCtrl 0x00100000 -+addu.qb $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addu.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addu.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 -+addu.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99a0000 DSPCtrl 0x00100000 -+addu.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00100000 -+addu.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xff00ff00 DSPCtrl 0x00100000 -+addu.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefefefe DSPCtrl 0x00100000 -+addu.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addu.qb $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 -+addu.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 -+addu.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addu.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addu.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x65656565 DSPCtrl 0x00100000 -+addu.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xec69a4c2 DSPCtrl 0x00100000 -+addu.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addu.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 -+addu.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e333 DSPCtrl 0x00100000 -+addu.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addu.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x80663444 DSPCtrl 0x00100000 -+addu.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe5a5a5a5 DSPCtrl 0x00100000 -+addu.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x98949894 DSPCtrl 0x00100000 -+addu.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa5412992 DSPCtrl 0x00100000 -+addu.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000e8f DSPCtrl 0x00100000 -+addu.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfefefefe DSPCtrl 0x00100000 -+addu.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbd3e93ae DSPCtrl 0x00100000 -+addu.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ee0eb2 DSPCtrl 0x00100000 -+addu.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addu.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xcf5e4b57 DSPCtrl 0x00100000 -+addu.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x04068f4f DSPCtrl 0x00100000 -+addu.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6f907 DSPCtrl 0x00100000 -+addu.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x6f35be30 DSPCtrl 0x00100000 -+addu.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597128e0 DSPCtrl 0x00100000 -+-------- ADDU_S.QB -------- -+addu_s.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addu_s.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x000461ff DSPCtrl 0x00100000 -+addu_s.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 -+addu_s.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabccff DSPCtrl 0x00100000 -+addu_s.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xff73437b DSPCtrl 0x00100000 -+addu_s.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa3359ff DSPCtrl 0x00100000 -+addu_s.qb $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf6fff2ff DSPCtrl 0x00100000 -+addu_s.qb $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addu_s.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addu_s.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0xff005856 DSPCtrl 0x00100000 -+addu_s.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99aff00 DSPCtrl 0x00100000 -+addu_s.qb $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0xff620020 DSPCtrl 0x00100000 -+addu_s.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xffffffff DSPCtrl 0x00100000 -+addu_s.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfefffeff DSPCtrl 0x00100000 -+addu_s.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addu_s.qb $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 -+addu_s.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0xff000000 DSPCtrl 0x00100000 -+addu_s.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addu_s.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addu_s.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xffffffff DSPCtrl 0x00100000 -+addu_s.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xffffffff DSPCtrl 0x00100000 -+addu_s.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addu_s.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 -+addu_s.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e3ff DSPCtrl 0x00100000 -+addu_s.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addu_s.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xffffffff DSPCtrl 0x00100000 -+addu_s.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe5ffffff DSPCtrl 0x00100000 -+addu_s.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffffffff DSPCtrl 0x00100000 -+addu_s.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa5ffffff DSPCtrl 0x00100000 -+addu_s.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xff000eff DSPCtrl 0x00100000 -+addu_s.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff DSPCtrl 0x00100000 -+addu_s.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xffffffae DSPCtrl 0x00100000 -+addu_s.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2eeffb2 DSPCtrl 0x00100000 -+addu_s.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addu_s.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xcfffffff DSPCtrl 0x00100000 -+addu_s.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xffffffff DSPCtrl 0x00100000 -+addu_s.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6f9ff DSPCtrl 0x00100000 -+addu_s.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xffffbeff DSPCtrl 0x00100000 -+addu_s.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xff71ffe0 DSPCtrl 0x00100000 -+-------- ADDWC -------- -+addwc $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+addwc $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00046238 DSPCtrl 0x00000000 -+addwc $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0xffff5856 DSPCtrl 0x00000000 -+addwc $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x7aabcd74 DSPCtrl 0x00000000 -+addwc $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00100000 -+addwc $t2, $t4, $t8 :: rs 0x00010001 rt 0xfa3259ff out 0xfa335a00 DSPCtrl 0x00000000 -+addwc $t0, $t8, $t0 :: rs 0x7fff7322 rt 0x77ff7fff out 0xf7fef321 DSPCtrl 0x00100000 -+addwc $t4, $t6, $t1 :: rs 0x0034c420 rt 0x00000555 out 0x0034c975 DSPCtrl 0x00000000 -+addwc $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x40000004 DSPCtrl 0x00000000 -+addwc $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00005856 DSPCtrl 0x00100000 -+addwc $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0xe99b0000 DSPCtrl 0x00100000 -+addwc $t5, $t3, $t2 :: rs 0x80000000 rt 0x80620020 out 0x00620020 DSPCtrl 0x00100000 -+addwc $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00010000 DSPCtrl 0x00000000 -+addwc $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xfffefffe DSPCtrl 0x00100000 -+addwc $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c975 DSPCtrl 0x00000000 -+addwc $t0, $t1, $t2 :: rs 0x000a2300 rt 0x83bc1900 out 0x83c63c00 DSPCtrl 0x00000000 -+addwc $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00100000 -+addwc $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xffffffff DSPCtrl 0x00000000 -+addwc $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffff244d DSPCtrl 0x00000000 -+addwc $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x66666665 DSPCtrl 0x00100000 -+addwc $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xed6aa5c2 DSPCtrl 0x00000000 -+addwc $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+addwc $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23888dd5 DSPCtrl 0x00000000 -+addwc $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x9813e433 DSPCtrl 0x00000000 -+addwc $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x8f8f8fa7 DSPCtrl 0x00000000 -+addwc $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x81673544 DSPCtrl 0x00000000 -+addwc $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xe6a6a6a5 DSPCtrl 0x00000000 -+addwc $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x99959994 DSPCtrl 0x00000000 -+addwc $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xa6422a92 DSPCtrl 0x00000000 -+addwc $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x78000f8f DSPCtrl 0x00000000 -+addwc $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 -+addwc $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xbe3f93ae DSPCtrl 0x00000000 -+addwc $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xf2ef0eb2 DSPCtrl 0x00000000 -+addwc $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xa8e5ff6f DSPCtrl 0x00000000 -+addwc $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xd05f4c57 DSPCtrl 0x00000000 -+addwc $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0507904f DSPCtrl 0x00000000 -+addwc $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63f6fa07 DSPCtrl 0x00000000 -+addwc $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7035bf30 DSPCtrl 0x00000000 -+addwc $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x597228e0 DSPCtrl 0x00100000 -+-------- BITREV -------- -+bitrev $t0, $t1 :: rd 0x00000012 rt 0x09ba4800 -+bitrev $t2, $t3 :: rd 0x0000614c rt 0x80003286 -+bitrev $t4, $t1 :: rd 0x0000ac24 rt 0xfabc2435 -+bitrev $t6, $t7 :: rd 0x00000001 rt 0x73468000 -+bitrev $t5, $t3 :: rd 0x00000096 rt 0x803c6900 -+bitrev $t2, $t4 :: rd 0x0000f492 rt 0xffad492f -+bitrev $t0, $t8 :: rd 0x0000fffa rt 0xfff45fff -+bitrev $t2, $t4 :: rd 0x0000aaa0 rt 0x00000555 -+bitrev $t0, $t1 :: rd 0x000010cf rt 0x0098f308 -+bitrev $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+bitrev $t4, $t1 :: rd 0x0000aaaa rt 0x55555555 -+bitrev $t6, $t7 :: rd 0x0000ac24 rt 0xffff2435 -+bitrev $t5, $t3 :: rd 0x0000d5d5 rt 0xabababab -+bitrev $t2, $t4 :: rd 0x00004b2d rt 0xfc79b4d2 -+bitrev $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+bitrev $t2, $t4 :: rd 0x0000a6a2 rt 0x00354565 -+bitrev $t0, $t1 :: rd 0x0000aae6 rt 0x00086755 -+bitrev $t2, $t3 :: rd 0x0000f1f1 rt 0x8f8f8f8f -+bitrev $t4, $t1 :: rd 0x00007777 rt 0xeeeeeeee -+bitrev $t6, $t7 :: rd 0x0000dbdb rt 0x1bdbdbdb -+bitrev $t5, $t3 :: rd 0x0000537b rt 0xdecadeca -+bitrev $t2, $t4 :: rd 0x00007bd2 rt 0x93474bde -+bitrev $t0, $t8 :: rd 0x0000ffe0 rt 0xfc0007ff -+bitrev $t2, $t4 :: rd 0x0000ffff rt 0xffffffff -+bitrev $t0, $t1 :: rd 0x0000f12d rt 0xcb4ab48f -+bitrev $t2, $t3 :: rd 0x0000187e rt 0xaf8f7e18 -+bitrev $t4, $t1 :: rd 0x000008a2 rt 0x87df4510 -+bitrev $t6, $t7 :: rd 0x00008717 rt 0xabf4e8e1 -+bitrev $t5, $t3 :: rd 0x00003577 rt 0xf4c0eeac -+bitrev $t2, $t4 :: rd 0x00004f2a rt 0x006a54f2 -+bitrev $t0, $t8 :: rd 0x0000c922 rt 0x79f74493 -+bitrev $t2, $t4 :: rd 0x0000c8c7 rt 0x9c09e313 -+-------- BPOSGE32 -------- -+bposge32 :: 6, POSval: 0 -+bposge32 :: 7, POSval: 1 -+bposge32 :: 3, POSval: 32 -+bposge32 :: 9, POSval: 17 -+bposge32 :: 10, POSval: 8 -+bposge32 :: 6, POSval: 60 -+bposge32 :: 12, POSval: 5 -+bposge32 :: 8, POSval: -3 -+bposge32 :: 9, POSval: 125 -+bposge32 :: 15, POSval: 7 -+bposge32 :: 11, POSval: 42 -+bposge32 :: 12, POSval: 53 -+bposge32 :: 13, POSval: 99 -+bposge32 :: 19, POSval: 12 -+bposge32 :: 20, POSval: 4 -+bposge32 :: 21, POSval: 6 -+-------- CMP.EQ.PH -------- -+cmp.eq.ph $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x00000000 -+cmp.eq.ph $t2, $t3 :: rs 0x00045fb2 rt 0x00000286 DSPCtrl 0x00000000 -+cmp.eq.ph $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x02000000 -+cmp.eq.ph $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x01000000 -+cmp.eq.ph $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 -+cmp.eq.ph $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 -+cmp.eq.ph $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x03000000 -+cmp.eq.ph $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x02000000 -+cmp.eq.ph $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x03000000 -+cmp.eq.ph $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x03000000 -+cmp.eq.ph $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 -+cmp.eq.ph $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x00000000 -+cmp.eq.ph $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 -+cmp.eq.ph $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x00000000 -+cmp.eq.ph $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 -+cmp.eq.ph $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 -+cmp.eq.ph $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 -+cmp.eq.ph $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 -+cmp.eq.ph $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x00000000 -+cmp.eq.ph $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x00000000 -+cmp.eq.ph $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x00000000 -+cmp.eq.ph $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x00000000 -+cmp.eq.ph $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x00000000 -+cmp.eq.ph $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x03000000 -+cmp.eq.ph $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 -+cmp.eq.ph $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x00000000 -+cmp.eq.ph $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x00000000 -+cmp.eq.ph $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 -+cmp.eq.ph $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x00000000 -+cmp.eq.ph $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x00000000 -+cmp.eq.ph $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x00000000 -+cmp.eq.ph $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 -+-------- CMP.LT.PH -------- -+cmp.lt.ph $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x02000000 -+cmp.lt.ph $t2, $t3 :: rs 0x00045fb2 rt 0x00000286 DSPCtrl 0x00000000 -+cmp.lt.ph $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x01000000 -+cmp.lt.ph $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x02000000 -+cmp.lt.ph $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 -+cmp.lt.ph $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 -+cmp.lt.ph $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x00000000 -+cmp.lt.ph $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x01000000 -+cmp.lt.ph $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x00000000 -+cmp.lt.ph $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x00000000 -+cmp.lt.ph $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x03000000 -+cmp.lt.ph $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x01000000 -+cmp.lt.ph $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 -+cmp.lt.ph $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x02000000 -+cmp.lt.ph $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x02000000 -+cmp.lt.ph $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 -+cmp.lt.ph $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x02000000 -+cmp.lt.ph $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 -+cmp.lt.ph $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x02000000 -+cmp.lt.ph $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x03000000 -+cmp.lt.ph $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x03000000 -+cmp.lt.ph $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x01000000 -+cmp.lt.ph $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x01000000 -+cmp.lt.ph $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x00000000 -+cmp.lt.ph $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 -+cmp.lt.ph $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x01000000 -+cmp.lt.ph $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x01000000 -+cmp.lt.ph $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 -+cmp.lt.ph $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x01000000 -+cmp.lt.ph $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 -+cmp.lt.ph $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x02000000 -+cmp.lt.ph $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 -+-------- CMP.LE.PH -------- -+cmp.le.ph $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x02000000 -+cmp.le.ph $t2, $t3 :: rs 0x00045fb2 rt 0x00000286 DSPCtrl 0x00000000 -+cmp.le.ph $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x03000000 -+cmp.le.ph $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x03000000 -+cmp.le.ph $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 -+cmp.le.ph $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 -+cmp.le.ph $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x03000000 -+cmp.le.ph $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x03000000 -+cmp.le.ph $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x03000000 -+cmp.le.ph $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x03000000 -+cmp.le.ph $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x03000000 -+cmp.le.ph $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x01000000 -+cmp.le.ph $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 -+cmp.le.ph $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x02000000 -+cmp.le.ph $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x02000000 -+cmp.le.ph $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 -+cmp.le.ph $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x02000000 -+cmp.le.ph $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 -+cmp.le.ph $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x02000000 -+cmp.le.ph $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x03000000 -+cmp.le.ph $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x03000000 -+cmp.le.ph $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x01000000 -+cmp.le.ph $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x01000000 -+cmp.le.ph $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x03000000 -+cmp.le.ph $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 -+cmp.le.ph $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x01000000 -+cmp.le.ph $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x01000000 -+cmp.le.ph $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 -+cmp.le.ph $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x01000000 -+cmp.le.ph $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 -+cmp.le.ph $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x02000000 -+cmp.le.ph $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 -+-------- CMPGU.EQ.QB -------- -+cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x00672300 rt 0x00000000 out 0x00000009 -+cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000008 -+cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x00000000 -+cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000000 -+cmpgu.eq.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 -+cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xf08b4631 out 0x00000000 -+cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x5cbd891a rt 0x7fff7fff out 0x00000000 -+cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x0ab64555 out 0x00000000 -+cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000006 -+cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0000000c -+cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000003 -+cmpgu.eq.qb $t5, $t3, $t2 :: rs 0x8007c560 rt 0x80000000 out 0x00000008 -+cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 -+cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f -+cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000c -+cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f -+cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x0000000f -+cmpgu.eq.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x00000000 -+cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 -+cmpgu.eq.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 -+cmpgu.eq.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000000 -+cmpgu.eq.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 -+cmpgu.eq.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x00000000 -+cmpgu.eq.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00000000 -+cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 -+cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x00000000 -+cmpgu.eq.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00000000 -+cmpgu.eq.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x00000005 -+cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000000 -+cmpgu.eq.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000006 -+cmpgu.eq.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x0000000f -+cmpgu.eq.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000000 -+cmpgu.eq.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x00000000 -+cmpgu.eq.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x00000000 -+cmpgu.eq.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x00000000 -+cmpgu.eq.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x00000000 -+cmpgu.eq.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00000000 -+cmpgu.eq.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000000 -+cmpgu.eq.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000000 -+-------- CMPGU.LT.QB -------- -+cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x00672300 rt 0x00000000 out 0x00000000 -+cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000000 -+cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x0000000e -+cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0000000b -+cmpgu.lt.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 -+cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xf08b4631 out 0x0000000f -+cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x5cbd891a rt 0x7fff7fff out 0x0000000d -+cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x0ab64555 out 0x0000000d -+cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000008 -+cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x00000002 -+cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000000 -+cmpgu.lt.qb $t5, $t3, $t2 :: rs 0x8007c560 rt 0x80000000 out 0x00000000 -+cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f -+cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x00000000 -+cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000001 -+cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 -+cmpgu.lt.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x00000000 -+cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000000f -+cmpgu.lt.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 -+cmpgu.lt.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000008 -+cmpgu.lt.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 -+cmpgu.lt.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x00000000 -+cmpgu.lt.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00000000 -+cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000000f -+cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0000000f -+cmpgu.lt.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00000007 -+cmpgu.lt.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x0000000a -+cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000009 -+cmpgu.lt.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000009 -+cmpgu.lt.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 -+cmpgu.lt.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000001 -+cmpgu.lt.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0000000c -+cmpgu.lt.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x0000000c -+cmpgu.lt.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x0000000f -+cmpgu.lt.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0000000f -+cmpgu.lt.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00000001 -+cmpgu.lt.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000004 -+cmpgu.lt.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000002 -+-------- CMPGU.LE.QB -------- -+cmpgu.le.qb $t0, $t1, $t2 :: rs 0x00672300 rt 0x00000000 out 0x00000009 -+cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000008 -+cmpgu.le.qb $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x0000000e -+cmpgu.le.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0000000b -+cmpgu.le.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 -+cmpgu.le.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xf08b4631 out 0x0000000f -+cmpgu.le.qb $t0, $t8, $t0 :: rs 0x5cbd891a rt 0x7fff7fff out 0x0000000d -+cmpgu.le.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x0ab64555 out 0x0000000d -+cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x0000000e -+cmpgu.le.qb $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0000000e -+cmpgu.le.qb $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x00000003 -+cmpgu.le.qb $t5, $t3, $t2 :: rs 0x8007c560 rt 0x80000000 out 0x00000008 -+cmpgu.le.qb $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000000f -+cmpgu.le.qb $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x0000000f -+cmpgu.le.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000d -+cmpgu.le.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x0000000f -+cmpgu.le.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x0000000f -+cmpgu.le.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x00000000 -+cmpgu.le.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000000f -+cmpgu.le.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 -+cmpgu.le.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000008 -+cmpgu.le.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 -+cmpgu.le.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x00000000 -+cmpgu.le.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00000000 -+cmpgu.le.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000000f -+cmpgu.le.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0000000f -+cmpgu.le.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00000007 -+cmpgu.le.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x0000000f -+cmpgu.le.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000009 -+cmpgu.le.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x0000000f -+cmpgu.le.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x0000000f -+cmpgu.le.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000001 -+cmpgu.le.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0000000c -+cmpgu.le.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x0000000c -+cmpgu.le.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x0000000f -+cmpgu.le.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0000000f -+cmpgu.le.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00000001 -+cmpgu.le.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00000004 -+cmpgu.le.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x00000002 -+-------- CMPU.EQ.QB -------- -+cmpu.eq.qb $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x00000000 -+cmpu.eq.qb $t2, $t3 :: rs 0x00005fb2 rt 0x00000286 DSPCtrl 0x0c000000 -+cmpu.eq.qb $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x0c000000 -+cmpu.eq.qb $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x03000000 -+cmpu.eq.qb $t5, $t3 :: rs 0xf973437b rt 0x80734300 DSPCtrl 0x06000000 -+cmpu.eq.qb $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x00000000 -+cmpu.eq.qb $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x0f000000 -+cmpu.eq.qb $t4, $t6 :: rs 0x0000c420 rt 0x0000c420 DSPCtrl 0x0f000000 -+cmpu.eq.qb $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x0f000000 -+cmpu.eq.qb $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x0f000000 -+cmpu.eq.qb $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 -+cmpu.eq.qb $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x00000000 -+cmpu.eq.qb $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 -+cmpu.eq.qb $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x00000000 -+cmpu.eq.qb $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 -+cmpu.eq.qb $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 -+cmpu.eq.qb $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 -+cmpu.eq.qb $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x00000000 -+cmpu.eq.qb $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x00000000 -+cmpu.eq.qb $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x00000000 -+cmpu.eq.qb $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x05000000 -+cmpu.eq.qb $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x00000000 -+cmpu.eq.qb $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x06000000 -+cmpu.eq.qb $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x0f000000 -+cmpu.eq.qb $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x00000000 -+cmpu.eq.qb $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x00000000 -+cmpu.eq.qb $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x00000000 -+cmpu.eq.qb $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x00000000 -+cmpu.eq.qb $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x00000000 -+cmpu.eq.qb $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x00000000 -+cmpu.eq.qb $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x00000000 -+cmpu.eq.qb $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x00000000 -+-------- CMPU.LT.QB -------- -+cmpu.lt.qb $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x0f000000 -+cmpu.lt.qb $t2, $t3 :: rs 0x00045fb2 rt 0x01080286 DSPCtrl 0x0c000000 -+cmpu.lt.qb $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x02000000 -+cmpu.lt.qb $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x08000000 -+cmpu.lt.qb $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 -+cmpu.lt.qb $t2, $t4 :: rs 0xffffffff rt 0x00010001 DSPCtrl 0x00000000 -+cmpu.lt.qb $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x00000000 -+cmpu.lt.qb $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x01000000 -+cmpu.lt.qb $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x00000000 -+cmpu.lt.qb $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x00000000 -+cmpu.lt.qb $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 -+cmpu.lt.qb $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x0f000000 -+cmpu.lt.qb $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 -+cmpu.lt.qb $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x08000000 -+cmpu.lt.qb $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 -+cmpu.lt.qb $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 -+cmpu.lt.qb $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 -+cmpu.lt.qb $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x0f000000 -+cmpu.lt.qb $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x0f000000 -+cmpu.lt.qb $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x07000000 -+cmpu.lt.qb $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x0a000000 -+cmpu.lt.qb $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x09000000 -+cmpu.lt.qb $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x09000000 -+cmpu.lt.qb $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x00000000 -+cmpu.lt.qb $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x01000000 -+cmpu.lt.qb $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x0c000000 -+cmpu.lt.qb $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x0c000000 -+cmpu.lt.qb $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x0f000000 -+cmpu.lt.qb $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x0f000000 -+cmpu.lt.qb $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 -+cmpu.lt.qb $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x04000000 -+cmpu.lt.qb $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x02000000 -+-------- CMPU.LE.QB -------- -+cmpu.le.qb $t0, $t1 :: rs 0x00000000 rt 0x0fffffff DSPCtrl 0x0f000000 -+cmpu.le.qb $t2, $t3 :: rs 0x00045fb2 rt 0x01040286 DSPCtrl 0x0c000000 -+cmpu.le.qb $t4, $t1 :: rs 0xfabc2435 rt 0xfabc3421 DSPCtrl 0x0e000000 -+cmpu.le.qb $t6, $t7 :: rs 0x07654cb8 rt 0x73464cb8 DSPCtrl 0x0b000000 -+cmpu.le.qb $t5, $t3 :: rs 0xf973437b rt 0x80000000 DSPCtrl 0x00000000 -+cmpu.le.qb $t2, $t4 :: rs 0x00010001 rt 0xffffffff DSPCtrl 0x0f000000 -+cmpu.le.qb $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff DSPCtrl 0x0f000000 -+cmpu.le.qb $t4, $t6 :: rs 0x0000c420 rt 0x00000555 DSPCtrl 0x0d000000 -+cmpu.le.qb $t0, $t1 :: rs 0x00000000 rt 0x00000000 DSPCtrl 0x0f000000 -+cmpu.le.qb $t2, $t3 :: rs 0x80000000 rt 0x80000000 DSPCtrl 0x0f000000 -+cmpu.le.qb $t4, $t1 :: rs 0xaaaaaaaa rt 0x55555555 DSPCtrl 0x00000000 -+cmpu.le.qb $t6, $t7 :: rs 0x00000018 rt 0xffff2435 DSPCtrl 0x0f000000 -+cmpu.le.qb $t5, $t3 :: rs 0xbabababa rt 0xabababab DSPCtrl 0x00000000 -+cmpu.le.qb $t2, $t4 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 DSPCtrl 0x08000000 -+cmpu.le.qb $t0, $t8 :: rs 0xfbde3976 rt 0x00000000 DSPCtrl 0x00000000 -+cmpu.le.qb $t4, $t6 :: rs 0x23534870 rt 0x00354565 DSPCtrl 0x00000000 -+cmpu.le.qb $t0, $t1 :: rs 0x980b7cde rt 0x00086755 DSPCtrl 0x00000000 -+cmpu.le.qb $t2, $t3 :: rs 0x00000018 rt 0x8f8f8f8f DSPCtrl 0x0f000000 -+cmpu.le.qb $t4, $t1 :: rs 0x92784656 rt 0xeeeeeeee DSPCtrl 0x0f000000 -+cmpu.le.qb $t6, $t7 :: rs 0xcacacaca rt 0x1bdbdbdb DSPCtrl 0x07000000 -+cmpu.le.qb $t5, $t3 :: rs 0xbacabaca rt 0xdecadeca DSPCtrl 0x0f000000 -+cmpu.le.qb $t2, $t4 :: rs 0x12fadeb4 rt 0x93474bde DSPCtrl 0x09000000 -+cmpu.le.qb $t0, $t8 :: rs 0x7c000790 rt 0xfc0007ff DSPCtrl 0x0f000000 -+cmpu.le.qb $t4, $t6 :: rs 0xffffffff rt 0xffffffff DSPCtrl 0x0f000000 -+cmpu.le.qb $t0, $t1 :: rs 0xf2f4df1f rt 0xcb4ab48f DSPCtrl 0x01000000 -+cmpu.le.qb $t2, $t3 :: rs 0x435f909a rt 0xaf8f7e18 DSPCtrl 0x0c000000 -+cmpu.le.qb $t4, $t1 :: rs 0x2106ba5f rt 0x87df4510 DSPCtrl 0x0c000000 -+cmpu.le.qb $t6, $t7 :: rs 0x246a6376 rt 0xabf4e8e1 DSPCtrl 0x0f000000 -+cmpu.le.qb $t5, $t3 :: rs 0x1046a1a3 rt 0xf4c0eeac DSPCtrl 0x0f000000 -+cmpu.le.qb $t2, $t4 :: rs 0x638ca515 rt 0x006a54f2 DSPCtrl 0x01000000 -+cmpu.le.qb $t0, $t8 :: rs 0xf63e7a9d rt 0x79f74493 DSPCtrl 0x04000000 -+cmpu.le.qb $t4, $t6 :: rs 0xbd6845cd rt 0x9c09e313 DSPCtrl 0x02000000 -+-------- DPAQ_S.W.PH -------- -+dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0xcebedda9 dspCtrl 0x00020000 -+dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000001 outLO 0x6a902dee dspCtrl 0x00080000 -+dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x80000000 dspCtrl 0x00010000 -+dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffb dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0xfffc0003 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0d5fae66 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 -+dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x39e41d73 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc807ec2 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x5b47e0f8 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x09430ca0 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x27896e23 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x64cf7771 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f7a7a5f dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xf42915f6 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1f4dff13 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x00000000 outLO 0x02b51c5a dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x6f6ca6ba dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf7589cda dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3575 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xc98e93f1 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbc416fd6 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xd53ff508 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xc4465aee dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x0e457e6e dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xb9b99637 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x062e5f3f dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x7b2565dc dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x64c4e377 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x507f754e dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x43774ada dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc2a10106 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0xa97b960e dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7d78c144 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x65b56242 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0xb39e2e69 dspCtrl 0x00040000 -+dpaq_s.w.ph $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x923c5393 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x9a72b449 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x3ae45be0 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x9e955590 dspCtrl 0x00000000 -+dpaq_s.w.ph $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x00000000 outLO 0x36eeba7c dspCtrl 0x00020000 -+-------- DPAQ_SA.L.W -------- -+dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000002 outLO 0x00000006 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x7fffa7aa outLO 0x4ebeddaa dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x6a91178a outLO 0xffffffff dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x7fffffff outLO 0xffffffff dspCtrl 0x00010000 -+dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffdfffd dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x7ffefffe outLO 0x80020001 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x1809ae66 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x7fffffff outLO 0xffff2434 dspCtrl 0x00040000 -+dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xc71c71c6 outLO 0x8f39e48f dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc507ec2 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x2da3188e outLO 0xdb65f07c dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x006a26f6 outLO 0x60fcc9c0 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000eb3a2 outLO 0xc358cdc5 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfff92ccc outLO 0x0403f6c1 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffea outLO 0x7a7a7a5f dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x0e9aa14a outLO 0x99419ed6 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xf46b6259 outLO 0x9b646d77 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x11f475db outLO 0x6177fd92 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xefe0f0c1 outLO 0xbcb7040e dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xfc200782 outLO 0x83389cda dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x18b27d05 outLO 0x3b787441 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x0fc95b3b outLO 0x22b18658 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xf9de25d4 outLO 0xd0fdef8c dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xbd1bf5fa outLO 0x7006d9ee dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xb01464c5 outLO 0x2291ac7e dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x1af47c9f outLO 0x231c51d1 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xe57e84e1 outLO 0x1a67b5d7 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xce376894 outLO 0xfb99d898 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xdec79617 outLO 0x57bdd1dd dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xa3ae018c outLO 0x86555c5c dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x0a519844 outLO 0x639570aa dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x0c9f59b9 outLO 0xe5425be6 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x67317b4f outLO 0xaee36470 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffcf5 outLO 0x4384c144 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x3efc805b outLO 0x9493110e dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xdcdc785f outLO 0x339d3f1e dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00005070 outLO 0xb39d8d88 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x4f249f4d outLO 0xde80e5a9 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x02506f83 outLO 0x2c89c7a1 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00002c40 outLO 0xdebc2ffc dspCtrl 0x00000000 -+dpaq_sa.l.w $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000801ea outLO 0xa7c3b620 dspCtrl 0x00000000 -+dpaq_sa.l.w $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x000063f6 outLO 0x36edf28f dspCtrl 0x00000000 -+-------- DPAU.H.QBL -------- -+dpau.h.qbl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+dpau.h.qbl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 -+dpau.h.qbl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x40004000 -+dpau.h.qbl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x80004bf9 -+dpau.h.qbl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00004001 -+dpau.h.qbl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x000000fe -+dpau.h.qbl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00013d01 -+dpau.h.qbl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 -+dpau.h.qbl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+dpau.h.qbl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff6435 -+dpau.h.qbl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabac1c8f -+dpau.h.qbl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 -+dpau.h.qbl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x0000f87c -+dpau.h.qbl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x00015db0 -+dpau.h.qbl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+dpau.h.qbl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x00355694 -+dpau.h.qbl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x000867ad -+dpau.h.qbl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f -+dpau.h.qbl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeefe63a -+dpau.h.qbl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bdc9df7 -+dpau.h.qbl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdecc1f7a -+dpau.h.qbl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x93479b8a -+dpau.h.qbl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfac0260a -+dpau.h.qbl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083d3173 -+dpau.h.qbl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb9747331 -+dpau.h.qbl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce6cff4 -+dpau.h.qbl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3d1d83 -+dpau.h.qbl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1ebb5596 -+dpau.h.qbl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722db95e -+dpau.h.qbl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d7f9b0 -+dpau.h.qbl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b11ec66 -+dpau.h.qbl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa5638376 -+dpau.h.qbl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10c4e92 -+dpau.h.qbl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f42c2b -+dpau.h.qbl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x5649aa98 -+dpau.h.qbl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc5503452 -+dpau.h.qbl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fc98d5c -+dpau.h.qbl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e -+dpau.h.qbl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+dpau.h.qbl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493718e -+dpau.h.qbl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb24be21 -+dpau.h.qbl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339eca4a -+dpau.h.qbl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x7098316b -+dpau.h.qbl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8e6a25 -+dpau.h.qbl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+dpau.h.qbl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd6cafa -+dpau.h.qbl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x6731ea3a -+dpau.h.qbl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6ee96ea -+-------- DPAU.H.QBR -------- -+dpau.h.qbr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+dpau.h.qbr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 -+dpau.h.qbr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x40000e25 -+dpau.h.qbr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x80003fff -+dpau.h.qbr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 -+dpau.h.qbr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x000000fe -+dpau.h.qbr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00013d01 -+dpau.h.qbr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3f9a -+dpau.h.qbr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+dpau.h.qbr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 -+dpau.h.qbr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabac1c8f -+dpau.h.qbr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b9ca -+dpau.h.qbr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x0000f87c -+dpau.h.qbr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x00016da0 -+dpau.h.qbr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+dpau.h.qbr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x003584fd -+dpau.h.qbr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0008e2ef -+dpau.h.qbr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f9cf7 -+dpau.h.qbr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeef7ff6 -+dpau.h.qbr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bdd3577 -+dpau.h.qbr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdecc1f7a -+dpau.h.qbr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x93482900 -+dpau.h.qbr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfac03b9b -+dpau.h.qbr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083d3173 -+dpau.h.qbr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb974656e -+dpau.h.qbr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce7153c -+dpau.h.qbr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3c8132 -+dpau.h.qbr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1ebb4b86 -+dpau.h.qbr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722d975b -+dpau.h.qbr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d71419 -+dpau.h.qbr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b11f933 -+dpau.h.qbr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa563e99b -+dpau.h.qbr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10c3779 -+dpau.h.qbr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f4181b -+dpau.h.qbr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x5649344d -+dpau.h.qbr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc54f8d48 -+dpau.h.qbr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fca1b10 -+dpau.h.qbr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e084c83 -+dpau.h.qbr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+dpau.h.qbr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e -+dpau.h.qbr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb24cd67 -+dpau.h.qbr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339dcd88 -+dpau.h.qbr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x70977b10 -+dpau.h.qbr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8eaa2f -+dpau.h.qbr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+dpau.h.qbr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd72b26 -+dpau.h.qbr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x67322ead -+dpau.h.qbr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6ee328f -+-------- DPSQ_S.W.PH -------- -+dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0xffffffff outLO 0xb1412257 dspCtrl 0x00020000 -+dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0xffffffff outLO 0x956fd210 dspCtrl 0x00080000 -+dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xffffffff outLO 0x80000002 dspCtrl 0x00010000 -+dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00000003 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0x0003fffb dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x125cb3e6 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0x7fff2436 dspCtrl 0x00040000 -+dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x00000000 outLO 0x1d7339e3 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc72eae2 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xa4b81f08 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xf6bcf360 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xffffffff outLO 0xd8e11ca7 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xffffffff outLO 0x9b415739 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8fa4a4bf dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xe9b4c7e6 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1869b8a3 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xbae0a13a dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0xb721f102 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfe26bb1a dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b356d dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xa959de91 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbd8a8272 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xc3384b30 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x792f962e dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0xd6153dd2 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0x89f458eb dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0xeff51e8f dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xcfa0c334 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xfd52b553 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x9767ca46 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x691a7fa6 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc7fdf2c6 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x1616bcda dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e976f58 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x5596110e dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x00000000 outLO 0x1093620e dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffffff outLO 0xb39ceca7 dspCtrl 0x00040000 -+dpsq_s.w.ph $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x4ef230ff dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x7aa7e8b1 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffffff outLO 0xdec90e30 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x2fce6f74 dspCtrl 0x00000000 -+dpsq_s.w.ph $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0x36ed2aa2 dspCtrl 0x00020000 -+-------- DPSQ_SA.L.W -------- -+dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0xfffffffe outLO 0x00000006 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x80005856 outLO 0x31412256 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x956ee875 outLO 0xffffffff dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x80000000 outLO 0x00000002 dspCtrl 0x00010000 -+dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00020001 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x80010001 outLO 0x7ffdfffd dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x07b2b3e6 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x80000000 outLO 0x00000000 dspCtrl 0x00040000 -+dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x38e38e38 outLO 0xc81d72c7 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfca2eae2 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xd25ce771 outLO 0x249a0f84 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xff95d909 outLO 0x9f033640 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xfff14c5d outLO 0x3d11bd05 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x0006d333 outLO 0xfc0cd7e9 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x00000014 outLO 0xa4a4a4bf dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xf1655eb5 outLO 0x449c3f06 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x0b949da6 outLO 0x9c534a3f dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xee0b8a24 outLO 0x5c1dc002 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x101f0f3d outLO 0x69d793ae dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x03dff87d outLO 0x7246bb1a dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b356f dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xe74d82fa outLO 0x376ffe41 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xf036a4c4 outLO 0x571a6bf0 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x0621da2a outLO 0xc77a50ac dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x42e40a05 outLO 0xcd6f172e dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x4feb9b3b outLO 0xc1c90fc2 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xe50b8360 outLO 0x20919d51 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x1a817b1f outLO 0xdbbbc7f7 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x31c8976a outLO 0x4f2c5078 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x213869e8 outLO 0x0a59c6ed dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x5c51fe74 outLO 0x6191e338 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xf5ae67bc outLO 0x48fc59d6 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xf360a645 outLO 0xa55c97e6 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x98ce84b1 outLO 0x10aeee78 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x0000030b outLO 0xb88b6f58 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xc1037fa3 outLO 0x9493110e dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x232387a0 outLO 0x42ab8532 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffaf8f outLO 0xb39d8d88 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0xb0db60b3 outLO 0x02ad9ee9 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xfdaf907b outLO 0xe890d559 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffd3bf outLO 0x3af13a14 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0xfff7fe16 outLO 0x26a00ee4 dspCtrl 0x00000000 -+dpsq_sa.l.w $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffff9c09 outLO 0x36edf28f dspCtrl 0x00000000 -+-------- DPSU.H.QBL -------- -+dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 -+dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x3fffc000 -+dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffb405 -+dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xffffffff outLO 0xffffc001 -+dpsu.h.qbl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffff00 -+dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffec2fd -+dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 -+dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+dpsu.h.qbl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xfffee435 -+dpsu.h.qbl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabab3ac7 -+dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 -+dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xffff0784 -+dpsu.h.qbl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xfffea250 -+dpsu.h.qbl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x00353436 -+dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x000866fd -+dpsu.h.qbl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f -+dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeedf7a2 -+dpsu.h.qbl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bdb19bf -+dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdec99e1a -+dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x9346fc32 -+dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfabf31ea -+dpsu.h.qbl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x0839396f -+dpsu.h.qbl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb973ff51 -+dpsu.h.qbl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce52254 -+dpsu.h.qbl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3b22b5 -+dpsu.h.qbl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1eba9b86 -+dpsu.h.qbl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722d02e2 -+dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d5f572 -+dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b119168 -+dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa562a59a -+dpsu.h.qbl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10b4a38 -+dpsu.h.qbl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f31369 -+dpsu.h.qbl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x56481fe8 -+dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc54ebf7a -+dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fc8c58c -+dpsu.h.qbl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e -+dpsu.h.qbl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+dpsu.h.qbl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9492b08e -+dpsu.h.qbl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb24062f -+dpsu.h.qbl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339c50c6 -+dpsu.h.qbl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x70965327 -+dpsu.h.qbl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8c32d5 -+dpsu.h.qbl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+dpsu.h.qbl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd69f16 -+dpsu.h.qbl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x6731daca -+dpsu.h.qbl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6ed4e34 -+-------- DPSU.H.QBR -------- -+dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 -+dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x3ffff1db -+dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffbfff -+dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 -+dpsu.h.qbr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffff00 -+dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffec2fd -+dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde22b2 -+dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+dpsu.h.qbr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 -+dpsu.h.qbr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabab3ac7 -+dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79afda -+dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xffff0784 -+dpsu.h.qbr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xfffe9260 -+dpsu.h.qbr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x003505cd -+dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0007ebbb -+dpsu.h.qbr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8227 -+dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xeeee5de6 -+dpsu.h.qbr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x1bda823f -+dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdec99e1a -+dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x93466ebc -+dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfabf1c59 -+dpsu.h.qbr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x0839396f -+dpsu.h.qbr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb9740d14 -+dpsu.h.qbr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xbce4dd0c -+dpsu.h.qbr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xcc3bbf06 -+dpsu.h.qbr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x1ebaa596 -+dpsu.h.qbr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x722d24e5 -+dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xa1d6db09 -+dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x7b11849b -+dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xa5623f75 -+dpsu.h.qbr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xb10b6151 -+dpsu.h.qbr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x73f32779 -+dpsu.h.qbr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x56489633 -+dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xc54f6684 -+dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x5fc837d8 -+dpsu.h.qbr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e07e419 -+dpsu.h.qbr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+dpsu.h.qbr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e -+dpsu.h.qbr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xbb23f6e9 -+dpsu.h.qbr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339d4d88 -+dpsu.h.qbr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x70970982 -+dpsu.h.qbr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8a8bf2cb -+dpsu.h.qbr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+dpsu.h.qbr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd63eea -+dpsu.h.qbr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x67319657 -+dpsu.h.qbr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6edb28f -+-------- EXTP -------- -+extp $t1, $ac0, 31 :: rt 0x00100000 ac0 0x8000000080000000 size 31 DSPCtrl 0x0000002a -+extp $t2, $ac1, 17 :: rt 0x00020000 ac1 0x8000000180000002 size 17 DSPCtrl 0x0000001f -+extp $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000037 -+extp $t4, $ac3, 12 :: rt 0x00000000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000016 -+extp $t5, $ac0, 3 :: rt 0x00000007 ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x0000003f -+extp $t6, $ac1, 8 :: rt 0x00000000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x0000000d -+extp $t7, $ac2, 16 :: rt 0x00000000 ac2 0x00000001ffffffff size 16 DSPCtrl 0x0000003c -+extp $t8, $ac3, 22 :: rt 0x007fffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000016 -+extp $t0, $ac0, 9 :: rt 0x00000318 ac0 0x0000cdfe0fde3126 size 9 DSPCtrl 0x00000012 -+extp $t2, $ac2, 16 :: rt 0x0001fffc ac2 0x00000018ffff2435 size 16 DSPCtrl 0x0000001e -+extp $t3, $ac3, 6 :: rt 0x00000075 ac3 0xbabababaabababab size 6 DSPCtrl 0x00000011 -+extp $t4, $ac0, 13 :: rt 0x00001f8f ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00000020 -+extp $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000014 -+extp $t6, $ac2, 27 :: rt 0x00000000 ac2 0xfbde397600000000 size 27 DSPCtrl 0x0000001e -+extp $t7, $ac3, 7 :: rt 0x00000009 ac3 0xb0ed765412349876 size 7 DSPCtrl 0x00000020 -+extp $t8, $ac0, 11 :: rt 0x00000c0d ac0 0x2353487035004565 size 11 DSPCtrl 0x00000025 -+extp $t0, $ac1, 26 :: rt 0x03016f9b ac1 0x980b7cde86700055 size 26 DSPCtrl 0x0000003d -+extp $t1, $ac2, 15 :: rt 0x00007c7c ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x0000001c -+extp $t2, $ac3, 2 :: rt 0x00000006 ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x0000000e -+extp $t3, $ac0, 1 :: rt 0x00000001 ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x0000003a -+extp $t4, $ac1, 0 :: rt 0x00000001 ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00000013 -+-------- EXTPDP -------- -+extpdp $t1, $ac0, 31 :: rt 0x00100000 ac0 0x8000000080000000 size 31 DSPCtrl 0x0000000a -+extpdp $t2, $ac1, 17 :: rt 0x00020000 ac1 0x8000000180000002 size 17 DSPCtrl 0x0000000d -+extpdp $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000032 -+extpdp $t4, $ac3, 12 :: rt 0x00000000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000009 -+extpdp $t5, $ac0, 3 :: rt 0x00000007 ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x0000003b -+extpdp $t6, $ac1, 8 :: rt 0x00000000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x00000004 -+extpdp $t7, $ac2, 16 :: rt 0x00000000 ac2 0x00000001ffffffff size 16 DSPCtrl 0x0000002b -+extpdp $t8, $ac3, 22 :: rt 0x007fffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x0000003f -+extpdp $t0, $ac0, 9 :: rt 0x00000318 ac0 0x0000cdfe0fde3126 size 9 DSPCtrl 0x00000008 -+extpdp $t3, $ac3, 6 :: rt 0x00000075 ac3 0xbabababaabababab size 6 DSPCtrl 0x0000000a -+extpdp $t4, $ac0, 13 :: rt 0x00001f8f ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00000012 -+extpdp $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 -+extpdp $t6, $ac2, 27 :: rt 0x00000000 ac2 0xfbde397600000000 size 27 DSPCtrl 0x00000002 -+extpdp $t7, $ac3, 7 :: rt 0x00000009 ac3 0x0bed765412349876 size 7 DSPCtrl 0x00000018 -+extpdp $t8, $ac0, 11 :: rt 0x00000c00 ac0 0x2353487000354565 size 11 DSPCtrl 0x00000019 -+extpdp $t0, $ac1, 26 :: rt 0x03016f9b ac1 0x980b7cde00086755 size 26 DSPCtrl 0x00000022 -+extpdp $t1, $ac2, 15 :: rt 0x00007c7c ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x0000000c -+extpdp $t2, $ac3, 2 :: rt 0x00000006 ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x0000000b -+extpdp $t3, $ac0, 1 :: rt 0x00000001 ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x00000038 -+extpdp $t4, $ac1, 0 :: rt 0x00000001 ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00000012 -+-------- EXTPDPV -------- -+extpdpv $t1, $ac0, $t2 :: rt 0x00000000 ac0 0x8000000080000000 rs 0x80000000 DSPCtrl 0x00000029 -+extpdpv $t2, $ac1, $t3 :: rt 0x00000040 ac1 0x8000000180000002 rs 0x00000006 DSPCtrl 0x00000018 -+extpdpv $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000017 -+extpdpv $t5, $ac0, $t6 :: rt 0x0000003f ac0 0x7fffffff7fffffff rs 0x0fde3126 DSPCtrl 0x00000038 -+extpdpv $t7, $ac2, $t8 :: rt 0x00000000 ac2 0x00000001ffffffff rs 0xaaaaaaaa DSPCtrl 0x00000031 -+extpdpv $t8, $ac3, $t9 :: rt 0x003fffff ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 -+extpdpv $t4, $ac0, $t3 :: rt 0x003f1e6d ac0 0xf0f0f0f0fc79b4d2 rs 0x12349876 DSPCtrl 0x00000009 -+extpdpv $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x0000000e -+extpdpv $t6, $ac2, $t5 :: rt 0x00000000 ac2 0xfbde397600000000 rs 0x00086755 DSPCtrl 0x00000008 -+extpdpv $t7, $ac3, $t6 :: rt 0x00123498 ac3 0x0bed765412349876 rs 0x00000018 DSPCtrl 0x00000007 -+extpdpv $t8, $ac0, $t7 :: rt 0x00018001 ac0 0x2353487000354565 rs 0x23534870 DSPCtrl 0x00000014 -+extpdpv $t0, $ac1, $t8 :: rt 0x003016f9 ac1 0x980b7cde00086755 rs 0x92784656 DSPCtrl 0x00000026 -+extpdpv $t1, $ac2, $t9 :: rt 0x00003e3e ac2 0x000000188f8f8f8f rs 0xeeeeeeee DSPCtrl 0x0000000d -+extpdpv $t2, $ac3, $t1 :: rt 0x000006ee ac3 0x92784656eeeeeeee rs 0xcacacaca DSPCtrl 0x00000003 -+extpdpv $t3, $ac0, $t1 :: rt 0x000002ca ac0 0xcacacaca1bdbdbdb rs 0xbacabaca DSPCtrl 0x0000002f -+extpdpv $t4, $ac1, $t4 :: rt 0x0000056f ac1 0xbacabacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00000008 -+-------- EXTPV -------- -+extpv $t1, $ac0, $t2 :: rt 0x00000000 ac0 0x8000000080000000 rs 0x80000000 DSPCtrl 0x0000002a -+extpv $t2, $ac1, $t3 :: rt 0x00000040 ac1 0x8000000180000002 rs 0x00000006 DSPCtrl 0x0000001f -+extpv $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000037 -+extpv $t5, $ac0, $t6 :: rt 0x0000003f ac0 0x7fffffff7fffffff rs 0x0fde3126 DSPCtrl 0x0000003f -+extpv $t7, $ac2, $t8 :: rt 0x00000000 ac2 0x00000001ffffffff rs 0xaaaaaaaa DSPCtrl 0x0000003c -+extpv $t8, $ac3, $t9 :: rt 0x003fffff ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000016 -+extpv $t4, $ac0, $t3 :: rt 0x003f1e6d ac0 0xf0f0f0f0fc79b4d2 rs 0x12349876 DSPCtrl 0x00000020 -+extpv $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000014 -+extpv $t6, $ac2, $t5 :: rt 0x00000000 ac2 0xfbde397600000000 rs 0x00086755 DSPCtrl 0x0000001e -+extpv $t7, $ac3, $t6 :: rt 0x00123498 ac3 0x0bed765412349876 rs 0x00000018 DSPCtrl 0x00000020 -+extpv $t8, $ac0, $t7 :: rt 0x00018001 ac0 0x2353487000354565 rs 0x23534870 DSPCtrl 0x00000025 -+extpv $t0, $ac1, $t8 :: rt 0x003016f9 ac1 0x980b7cde00086755 rs 0x92784656 DSPCtrl 0x0000003d -+extpv $t1, $ac2, $t9 :: rt 0x00003e3e ac2 0x000000188f8f8f8f rs 0xeeeeeeee DSPCtrl 0x0000001c -+extpv $t2, $ac3, $t1 :: rt 0x000006ee ac3 0x92784656eeeeeeee rs 0xcacacaca DSPCtrl 0x0000000e -+extpv $t3, $ac0, $t1 :: rt 0x000002ca ac0 0xcacacaca1bdbdbdb rs 0xbacabaca DSPCtrl 0x0000003a -+extpv $t4, $ac1, $t4 :: rt 0x0000056f ac1 0xbacabacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00000013 -+-------- EXTR_S.H -------- -+extr_s.h $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr_s.h $t5, $ac0, 31 :: rt 0x00007fff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr_s.h $t6, $ac1, 31 :: rt 0x00007fff ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00800000 -+extr_s.h $t7, $ac2, 0 :: rt 0xffff8000 ac2 0xff34bc6fffffffff size 0 DSPCtrl 0x00800000 -+extr_s.h $t8, $ac3, 1 :: rt 0x00007fff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00800000 -+extr_s.h $t1, $ac0, 31 :: rt 0xffff8000 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000 -+extr_s.h $t2, $ac1, 17 :: rt 0xffff8000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000 -+extr_s.h $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 -+extr_s.h $t4, $ac3, 12 :: rt 0x00007fff ac3 0x0000000440000000 size 12 DSPCtrl 0x00800000 -+extr_s.h $t5, $ac0, 3 :: rt 0x00007fff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000 -+extr_s.h $t6, $ac1, 8 :: rt 0xffff8000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x00800000 -+extr_s.h $t7, $ac2, 16 :: rt 0x00007fff ac2 0x00000001ffffffff size 16 DSPCtrl 0x00800000 -+extr_s.h $t8, $ac3, 22 :: rt 0xffffffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000000 -+extr_s.h $t0, $ac0, 9 :: rt 0x00007fff ac0 0x0000cdfe0fde3126 size 9 DSPCtrl 0x00800000 -+extr_s.h $t2, $ac2, 14 :: rt 0x00007fff ac2 0x00000018ffff2435 size 14 DSPCtrl 0x00800000 -+extr_s.h $t1, $ac1, 20 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 size 20 DSPCtrl 0x00800000 -+extr_s.h $t2, $ac2, 16 :: rt 0x00007fff ac2 0x00000018ffff2435 size 16 DSPCtrl 0x00800000 -+extr_s.h $t1, $ac1, 5 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 -+extr_s.h $t2, $ac2, 22 :: rt 0x000063ff ac2 0x00000018ffff2435 size 22 DSPCtrl 0x00000000 -+extr_s.h $t3, $ac3, 6 :: rt 0xffff8000 ac3 0xbabababaabababab size 6 DSPCtrl 0x00800000 -+extr_s.h $t4, $ac0, 13 :: rt 0xffff8000 ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00800000 -+extr_s.h $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 -+extr_s.h $t6, $ac2, 27 :: rt 0xffff8000 ac2 0xfbde397600000000 size 27 DSPCtrl 0x00800000 -+extr_s.h $t7, $ac3, 7 :: rt 0x00007fff ac3 0x0bed765412349876 size 7 DSPCtrl 0x00800000 -+extr_s.h $t8, $ac0, 11 :: rt 0x00007fff ac0 0x2353487000354565 size 11 DSPCtrl 0x00800000 -+extr_s.h $t0, $ac1, 26 :: rt 0xffff8000 ac1 0x980b7cde00086755 size 26 DSPCtrl 0x00800000 -+extr_s.h $t1, $ac2, 15 :: rt 0x00007fff ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x00800000 -+extr_s.h $t2, $ac3, 2 :: rt 0xffff8000 ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x00800000 -+extr_s.h $t3, $ac0, 1 :: rt 0xffff8000 ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x00800000 -+extr_s.h $t4, $ac1, 0 :: rt 0xffff8000 ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00800000 -+extr_s.h $t5, $ac0, 3 :: rt 0x00007fff ac0 0x000000005fc92974 size 3 DSPCtrl 0x00800000 -+extr_s.h $t6, $ac1, 8 :: rt 0x00007fff ac1 0x000000007e08184e size 8 DSPCtrl 0x00800000 -+extr_s.h $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 -+extr_s.h $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 -+extr_s.h $t0, $ac0, 9 :: rt 0xffff8000 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00800000 -+extr_s.h $t1, $ac1, 5 :: rt 0x00007fff ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00800000 -+extr_s.h $t2, $ac2, 14 :: rt 0x00007fff ac2 0x0000000070974249 size 14 DSPCtrl 0x00800000 -+extr_s.h $t1, $ac1, 20 :: rt 0xfffff8a8 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 -+extr_s.h $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 -+extr_s.h $t1, $ac1, 5 :: rt 0x00007fff ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00800000 -+extr_s.h $t2, $ac2, 22 :: rt 0x0000019c ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 -+extr_s.h $t3, $ac3, 6 :: rt 0xffff8000 ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00800000 -+extr_s.h $t4, $ac0, 13 :: rt 0x00007fff ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00800000 -+extr_s.h $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 -+extr_s.h $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 -+extr_s.h $t7, $ac3, 7 :: rt 0xffff8000 ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00800000 -+extr_s.h $t8, $ac0, 11 :: rt 0xffff8000 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00800000 -+extr_s.h $t0, $ac1, 26 :: rt 0xffffffea ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 -+extr_s.h $t1, $ac2, 15 :: rt 0xffffe981 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 -+extr_s.h $t2, $ac3, 2 :: rt 0x00007fff ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00800000 -+extr_s.h $t3, $ac0, 1 :: rt 0x00007fff ac0 0x0000000079f74493 size 1 DSPCtrl 0x00800000 -+extr_s.h $t4, $ac1, 0 :: rt 0xffff8000 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00800000 -+-------- EXTR.W -------- -+extr.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr.w $t5, $ac0, 31 :: rt 0xffffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000 -+extr.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0xffffffffffffffff size 0 DSPCtrl 0x00000000 -+extr.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x00000000fffffffe size 1 DSPCtrl 0x00000000 -+extr.w $t1, $ac0, 31 :: rt 0x00000001 ac0 0x8000000080000000 size 31 DSPCtrl 0x00800000 -+extr.w $t2, $ac1, 17 :: rt 0x0000c000 ac1 0x8000000180000002 size 17 DSPCtrl 0x00800000 -+extr.w $t3, $ac2, 4 :: rt 0x00000000 ac2 0x0000000000000006 size 4 DSPCtrl 0x00000000 -+extr.w $t4, $ac3, 12 :: rt 0x00440000 ac3 0x0000000440000000 size 12 DSPCtrl 0x00000000 -+extr.w $t5, $ac0, 3 :: rt 0xefffffff ac0 0x7fffffff7fffffff size 3 DSPCtrl 0x00800000 -+extr.w $t6, $ac1, 8 :: rt 0xff000000 ac1 0xffffffff00000001 size 8 DSPCtrl 0x00000000 -+extr.w $t7, $ac2, 16 :: rt 0x0001ffff ac2 0x00000001ffffffff size 16 DSPCtrl 0x00000000 -+extr.w $t8, $ac3, 22 :: rt 0xffffffff ac3 0xffffffffffffffff size 22 DSPCtrl 0x00000000 -+extr.w $t0, $ac0, 9 :: rt 0xff7e8718 ac0 0x0000cdfefd0e3126 size 9 DSPCtrl 0x00800000 -+extr.w $t2, $ac2, 14 :: rt 0x0063fffc ac2 0x00000018ffff2435 size 14 DSPCtrl 0x00000000 -+extr.w $t1, $ac1, 20 :: rt 0xaaaaa555 ac1 0xaaaaaaaa55555555 size 20 DSPCtrl 0x00800000 -+extr.w $t2, $ac2, 16 :: rt 0x0018ffff ac2 0x00000018ffff2435 size 16 DSPCtrl 0x00000000 -+extr.w $t1, $ac1, 5 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 size 5 DSPCtrl 0x00800000 -+extr.w $t2, $ac2, 22 :: rt 0x000063ff ac2 0x00000018ffff2435 size 22 DSPCtrl 0x00000000 -+extr.w $t3, $ac3, 6 :: rt 0xeaaeaeae ac3 0xbabababaabababab size 6 DSPCtrl 0x00800000 -+extr.w $t4, $ac0, 13 :: rt 0x8787e3cd ac0 0xf0f0f0f0fc79b4d2 size 13 DSPCtrl 0x00800000 -+extr.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 -+extr.w $t6, $ac2, 27 :: rt 0x7bc72ec0 ac2 0xfbde397600000000 size 27 DSPCtrl 0x00800000 -+extr.w $t7, $ac3, 7 :: rt 0xa8246930 ac3 0x0bed765412349876 size 7 DSPCtrl 0x00800000 -+extr.w $t8, $ac0, 11 :: rt 0x0e0006a8 ac0 0x2353487000354565 size 11 DSPCtrl 0x00800000 -+extr.w $t0, $ac1, 26 :: rt 0x02df37a0 ac1 0x980b7cde80006755 size 26 DSPCtrl 0x00800000 -+extr.w $t1, $ac2, 15 :: rt 0x00311f1f ac2 0x000000188f8f8f8f size 15 DSPCtrl 0x00000000 -+extr.w $t2, $ac3, 2 :: rt 0xbbbbbbbb ac3 0x92784656eeeeeeee size 2 DSPCtrl 0x00800000 -+extr.w $t3, $ac0, 1 :: rt 0x0dededed ac0 0xcacacaca1bdbdbdb size 1 DSPCtrl 0x00800000 -+extr.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xbacabacadecadeca size 0 DSPCtrl 0x00800000 -+extr.w $t5, $ac0, 3 :: rt 0x0bf9252e ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 -+extr.w $t6, $ac1, 8 :: rt 0x007e0818 ac1 0x000000007e08184e size 8 DSPCtrl 0x00000000 -+extr.w $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 -+extr.w $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 -+extr.w $t0, $ac0, 9 :: rt 0xffdd9231 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00000000 -+extr.w $t1, $ac1, 5 :: rt 0x019cec6c ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00000000 -+extr.w $t2, $ac2, 14 :: rt 0x0001c25d ac2 0x0000000070974249 size 14 DSPCtrl 0x00000000 -+extr.w $t1, $ac1, 20 :: rt 0xfffff8a8 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 -+extr.w $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 -+extr.w $t1, $ac1, 5 :: rt 0x0066b5a8 ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00000000 -+extr.w $t2, $ac2, 22 :: rt 0x0000019c ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 -+extr.w $t3, $ac3, 6 :: rt 0xfedbb7ca ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00000000 -+extr.w $t4, $ac0, 13 :: rt 0x00025a76 ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00000000 -+extr.w $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 -+extr.w $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 -+extr.w $t7, $ac3, 7 :: rt 0xff5f1efc ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00000000 -+extr.w $t8, $ac0, 11 :: rt 0xfff0fbe8 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00000000 -+extr.w $t0, $ac1, 26 :: rt 0xffffffea ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 -+extr.w $t1, $ac2, 15 :: rt 0xffffe981 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 -+extr.w $t2, $ac3, 2 :: rt 0x001a953c ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00000000 -+extr.w $t3, $ac0, 1 :: rt 0x3cfba249 ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 -+extr.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 -+-------- EXTR_R.W -------- -+extr_r.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr_r.w $t5, $ac0, 31 :: rt 0x00000000 ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr_r.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000 -+extr_r.w $t7, $ac2, 0 :: rt 0xffffffff ac2 0x987b2fffffffffff size 0 DSPCtrl 0x00800000 -+extr_r.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x000cd320fffffffe size 1 DSPCtrl 0x00800000 -+extr_r.w $t1, $ac0, 31 :: rt 0xfff36a83 ac0 0xfff9b54180000000 size 31 DSPCtrl 0x00000000 -+extr_r.w $t3, $ac2, 4 :: rt 0xc0000000 ac2 0x0008b31c00000006 size 4 DSPCtrl 0x00800000 -+extr_r.w $t5, $ac0, 3 :: rt 0xb0000000 ac0 0x0086b3ad7fffffff size 3 DSPCtrl 0x00800000 -+extr_r.w $t6, $ac1, 8 :: rt 0x51000000 ac1 0x00097b5100000001 size 8 DSPCtrl 0x00800000 -+extr_r.w $t7, $ac2, 16 :: rt 0x44000000 ac2 0xfcde43ffffffffff size 16 DSPCtrl 0x00800000 -+extr_r.w $t0, $ac0, 9 :: rt 0x137e8719 ac0 0xffffca26fd0e3126 size 9 DSPCtrl 0x00800000 -+extr_r.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac2, 14 :: rt 0xfffffffd ac2 0xffffffffffff2435 size 14 DSPCtrl 0x00000000 -+extr_r.w $t1, $ac1, 20 :: rt 0x00000555 ac1 0x0000000055555555 size 20 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac2, 16 :: rt 0xffffffff ac2 0xffffffffffff2435 size 16 DSPCtrl 0x00000000 -+extr_r.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac2, 22 :: rt 0x00000000 ac2 0xffffffffffff2435 size 22 DSPCtrl 0x00000000 -+extr_r.w $t3, $ac3, 6 :: rt 0xfeaeaeaf ac3 0xffffffffabababab size 6 DSPCtrl 0x00000000 -+extr_r.w $t4, $ac0, 13 :: rt 0xffffe3ce ac0 0xfffffffffc79b4d2 size 13 DSPCtrl 0x00000000 -+extr_r.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 -+extr_r.w $t6, $ac2, 27 :: rt 0x00000000 ac2 0x0000000000000000 size 27 DSPCtrl 0x00000000 -+extr_r.w $t7, $ac3, 7 :: rt 0x00246931 ac3 0x02934b0012349876 size 7 DSPCtrl 0x00800000 -+extr_r.w $t8, $ac0, 11 :: rt 0x5a0006a9 ac0 0x0008cad000354565 size 11 DSPCtrl 0x00800000 -+extr_r.w $t0, $ac1, 26 :: rt 0x9723ffe0 ac1 0xf65c8fff80006755 size 26 DSPCtrl 0x00800000 -+extr_r.w $t1, $ac2, 15 :: rt 0xe0031f1f ac2 0xfffff0018f8f8f8f size 15 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac3, 2 :: rt 0x3bbbbbbc ac3 0xbad69420eeeeeeee size 2 DSPCtrl 0x00800000 -+extr_r.w $t3, $ac0, 1 :: rt 0x0dededee ac0 0x000000001bdbdbdb size 1 DSPCtrl 0x00000000 -+extr_r.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xffffffffdecadeca size 0 DSPCtrl 0x00000000 -+extr_r.w $t5, $ac0, 3 :: rt 0x0bf9252f ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 -+extr_r.w $t6, $ac1, 8 :: rt 0x007e0818 ac1 0x000000007e08184e size 8 DSPCtrl 0x00000000 -+extr_r.w $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 -+extr_r.w $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 -+extr_r.w $t0, $ac0, 9 :: rt 0xffdd9231 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00000000 -+extr_r.w $t1, $ac1, 5 :: rt 0x019cec6c ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac2, 14 :: rt 0x0001c25d ac2 0x0000000070974249 size 14 DSPCtrl 0x00000000 -+extr_r.w $t1, $ac1, 20 :: rt 0xfffff8a9 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 -+extr_r.w $t1, $ac1, 5 :: rt 0x0066b5a8 ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac2, 22 :: rt 0x0000019d ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 -+extr_r.w $t3, $ac3, 6 :: rt 0xfedbb7ca ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00000000 -+extr_r.w $t4, $ac0, 13 :: rt 0x00025a76 ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00000000 -+extr_r.w $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 -+extr_r.w $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 -+extr_r.w $t7, $ac3, 7 :: rt 0xff5f1efc ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00000000 -+extr_r.w $t8, $ac0, 11 :: rt 0xfff0fbe9 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00000000 -+extr_r.w $t0, $ac1, 26 :: rt 0xffffffeb ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 -+extr_r.w $t1, $ac2, 15 :: rt 0xffffe982 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 -+extr_r.w $t2, $ac3, 2 :: rt 0x001a953d ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00000000 -+extr_r.w $t3, $ac0, 1 :: rt 0x3cfba24a ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 -+extr_r.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 -+-------- EXTR_RS.W -------- -+extr_rs.w $t4, $ac3, 0 :: rt 0x00000000 ac3 0x0000000000000000 size 0 DSPCtrl 0x00000000 -+extr_rs.w $t5, $ac0, 31 :: rt 0x7fffffff ac0 0x7fffffffcbcdef01 size 31 DSPCtrl 0x00800000 -+extr_rs.w $t6, $ac1, 31 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 size 31 DSPCtrl 0x00000000 -+extr_rs.w $t7, $ac2, 0 :: rt 0x80000000 ac2 0x987b2fffffffffff size 0 DSPCtrl 0x00800000 -+extr_rs.w $t8, $ac3, 1 :: rt 0x7fffffff ac3 0x000cd320fffffffe size 1 DSPCtrl 0x00800000 -+extr_rs.w $t3, $ac2, 4 :: rt 0x80000000 ac2 0xfff9b54180000000 size 4 DSPCtrl 0x00800000 -+extr_rs.w $t5, $ac0, 3 :: rt 0x7fffffff ac0 0x0008b31c00000006 size 3 DSPCtrl 0x00800000 -+extr_rs.w $t6, $ac1, 8 :: rt 0x7fffffff ac1 0x0086b3ad7fffffff size 8 DSPCtrl 0x00800000 -+extr_rs.w $t7, $ac2, 16 :: rt 0x7fffffff ac2 0x00097b5100000001 size 16 DSPCtrl 0x00800000 -+extr_rs.w $t8, $ac3, 22 :: rt 0x80000000 ac3 0xfcde43ffffffffff size 2 DSPCtrl 0x00800000 -+extr_rs.w $t0, $ac0, 9 :: rt 0x80000000 ac0 0xffffca26fd0e3126 size 9 DSPCtrl 0x00800000 -+extr_rs.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac2, 14 :: rt 0xfffffffd ac2 0xffffffffffff2435 size 14 DSPCtrl 0x00000000 -+extr_rs.w $t1, $ac1, 20 :: rt 0x00000555 ac1 0x0000000055555555 size 0 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac2, 16 :: rt 0xffffffff ac2 0xffffffffffff2435 size 16 DSPCtrl 0x00000000 -+extr_rs.w $t1, $ac1, 5 :: rt 0x02aaaaab ac1 0x0000000055555555 size 5 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac2, 22 :: rt 0x00000000 ac2 0xffffffffffff2435 size 22 DSPCtrl 0x00000000 -+extr_rs.w $t3, $ac3, 6 :: rt 0xfeaeaeaf ac3 0xffffffffabababab size 6 DSPCtrl 0x00000000 -+extr_rs.w $t4, $ac0, 13 :: rt 0xffffe3ce ac0 0xfffffffffc79b4d2 size 13 DSPCtrl 0x00000000 -+extr_rs.w $t5, $ac1, 19 :: rt 0x00000000 ac1 0x0000000000000000 size 19 DSPCtrl 0x00000000 -+extr_rs.w $t6, $ac2, 27 :: rt 0x00000000 ac2 0x0000000000000000 size 27 DSPCtrl 0x00000000 -+extr_rs.w $t7, $ac3, 7 :: rt 0x7fffffff ac3 0x02934b0012349876 size 7 DSPCtrl 0x00800000 -+extr_rs.w $t8, $ac0, 11 :: rt 0x7fffffff ac0 0x0008cad000354565 size 11 DSPCtrl 0x00800000 -+extr_rs.w $t0, $ac1, 26 :: rt 0x80000000 ac1 0xf65c8fff80006755 size 26 DSPCtrl 0x00800000 -+extr_rs.w $t1, $ac2, 15 :: rt 0xe0031f1f ac2 0xfffff0018f8f8f8f size 15 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac3, 2 :: rt 0x80000000 ac3 0xbad69420eeeeeeee size 2 DSPCtrl 0x00800000 -+extr_rs.w $t3, $ac0, 1 :: rt 0x0dededee ac0 0x000000001bdbdbdb size 1 DSPCtrl 0x00000000 -+extr_rs.w $t4, $ac1, 0 :: rt 0xdecadeca ac1 0xffffffffdecadeca size 0 DSPCtrl 0x00000000 -+extr_rs.w $t5, $ac0, 3 :: rt 0x0bf9252f ac0 0x000000005fc92974 size 3 DSPCtrl 0x00000000 -+extr_rs.w $t6, $ac1, 8 :: rt 0x007e0818 ac1 0x000000007e08184e size 8 DSPCtrl 0x00000000 -+extr_rs.w $t7, $ac2, 16 :: rt 0x000071c8 ac2 0x0000000071c8315f size 16 DSPCtrl 0x00000000 -+extr_rs.w $t8, $ac3, 22 :: rt 0xfffffe52 ac3 0xffffffff9493110e size 22 DSPCtrl 0x00000000 -+extr_rs.w $t0, $ac0, 9 :: rt 0xffdd9231 ac0 0xffffffffbb246228 size 9 DSPCtrl 0x00000000 -+extr_rs.w $t1, $ac1, 5 :: rt 0x019cec6c ac1 0x00000000339d8d88 size 5 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac2, 14 :: rt 0x0001c25d ac2 0x0000000070974249 size 14 DSPCtrl 0x00000000 -+extr_rs.w $t1, $ac1, 20 :: rt 0xfffff8a9 ac1 0xffffffff8a8d4e7d size 20 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac2, 16 :: rt 0xffffeb1b ac2 0xffffffffeb1b4335 size 16 DSPCtrl 0x00000000 -+extr_rs.w $t1, $ac1, 5 :: rt 0x0066b5a8 ac1 0x000000000cd6b508 size 5 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac2, 22 :: rt 0x0000019d ac2 0x000000006731e282 size 22 DSPCtrl 0x00000000 -+extr_rs.w $t3, $ac3, 6 :: rt 0xfedbb7ca ac3 0xffffffffb6edf28f size 6 DSPCtrl 0x00000000 -+extr_rs.w $t4, $ac0, 13 :: rt 0x00025a76 ac0 0x000000004b4ec9ca size 13 DSPCtrl 0x00000000 -+extr_rs.w $t5, $ac1, 19 :: rt 0xfffff820 ac1 0xffffffffc1037fa4 size 19 DSPCtrl 0x00000000 -+extr_rs.w $t6, $ac2, 27 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f size 27 DSPCtrl 0x00000000 -+extr_rs.w $t7, $ac3, 7 :: rt 0xff5f1efc ac3 0xffffffffaf8f7e18 size 7 DSPCtrl 0x00000000 -+extr_rs.w $t8, $ac0, 11 :: rt 0xfff0fbe9 ac0 0xffffffff87df4510 size 11 DSPCtrl 0x00000000 -+extr_rs.w $t0, $ac1, 26 :: rt 0xffffffeb ac1 0xffffffffabf4e8e1 size 26 DSPCtrl 0x00000000 -+extr_rs.w $t1, $ac2, 15 :: rt 0xffffe982 ac2 0xfffffffff4c0eeac size 15 DSPCtrl 0x00000000 -+extr_rs.w $t2, $ac3, 2 :: rt 0x001a953d ac3 0x00000000006a54f2 size 2 DSPCtrl 0x00000000 -+extr_rs.w $t3, $ac0, 1 :: rt 0x3cfba24a ac0 0x0000000079f74493 size 1 DSPCtrl 0x00000000 -+extr_rs.w $t4, $ac1, 0 :: rt 0x9c09e313 ac1 0xffffffff9c09e313 size 0 DSPCtrl 0x00000000 -+-------- EXTRV_S.H -------- -+extrv_s.h $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv_s.h $t2, $ac2, $t4 :: rt 0x00007fff ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac1, $t7 :: rt 0x00007fff ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv_s.h $t1, $ac1, $t2 :: rt 0x00007fff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac1, $t1 :: rt 0xffff8000 ac1 0x8000000180000002 rs 0x12349876 DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac0, $t0 :: rt 0xffff8000 ac0 0x8000000080000000 rs 0x12349876 DSPCtrl 0x00800000 -+extrv_s.h $t3, $ac2, $t2 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x00354565 DSPCtrl 0x00000000 -+extrv_s.h $t4, $ac3, $t3 :: rt 0x00002200 ac3 0x0000000440000000 rs 0x00086755 DSPCtrl 0x00000000 -+extrv_s.h $t5, $ac0, $t4 :: rt 0x00007fff ac0 0x7fffffff7fffffff rs 0x00000018 DSPCtrl 0x00800000 -+extrv_s.h $t6, $ac1, $t5 :: rt 0xffff8000 ac1 0xffffffff00000001 rs 0x23534870 DSPCtrl 0x00800000 -+extrv_s.h $t7, $ac2, $t6 :: rt 0x000007ff ac2 0x00000001ffffffff rs 0x92784656 DSPCtrl 0x00000000 -+extrv_s.h $t8, $ac3, $t7 :: rt 0xffffffff ac3 0xffffffffffffffff rs 0xeeeeeeee DSPCtrl 0x00000000 -+extrv_s.h $t0, $ac0, $t8 :: rt 0x00007fff ac0 0x0000cdfe0fde3126 rs 0xcacacaca DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac1, $t0 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 rs 0xbacabaca DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac2, $t1 :: rt 0x0000031f ac2 0x00000018ffff2435 rs 0x1bdbdbdb DSPCtrl 0x00000000 -+extrv_s.h $t1, $ac1, $t2 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 rs 0x0cd6b508 DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac2, $t3 :: rt 0x00007fff ac2 0x00000018ffff2435 rs 0x6731e282 DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac1, $t4 :: rt 0xffff8000 ac1 0xaaaaaaaa55555555 rs 0xb6edf28f DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac2, $t5 :: rt 0x00007fff ac2 0x00000018ffff2435 rs 0x4b4ec9ca DSPCtrl 0x00800000 -+extrv_s.h $t3, $ac3, $t6 :: rt 0xffff8000 ac3 0xbabababaabababab rs 0xc1037fa4 DSPCtrl 0x00800000 -+extrv_s.h $t4, $ac0, $t7 :: rt 0xffff8000 ac0 0xf0f0f0f0fc79b4d2 rs 0xcb4ab48f DSPCtrl 0x00800000 -+extrv_s.h $t5, $ac1, $t8 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xaf8f7e18 DSPCtrl 0x00000000 -+extrv_s.h $t6, $ac2, $t0 :: rt 0xffff8000 ac2 0xfbde397600000000 rs 0x87df4510 DSPCtrl 0x00800000 -+extrv_s.h $t7, $ac3, $t1 :: rt 0x00007fff ac3 0x0bed765412349876 rs 0xabf4e8e1 DSPCtrl 0x00800000 -+extrv_s.h $t8, $ac0, $t2 :: rt 0x00007fff ac0 0x2353487000354565 rs 0xf4c0eeac DSPCtrl 0x00800000 -+extrv_s.h $t0, $ac1, $t3 :: rt 0xffff8000 ac1 0x980b7cde00086755 rs 0x006a54f2 DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac2, $t4 :: rt 0x00007fff ac2 0x000000188f8f8f8f rs 0x79f74493 DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac3, $t5 :: rt 0xffff8000 ac3 0x92784656eeeeeeee rs 0x9c09e313 DSPCtrl 0x00800000 -+extrv_s.h $t3, $ac0, $t6 :: rt 0xffff8000 ac0 0xcacacaca1bdbdbdb rs 0x0fde3126 DSPCtrl 0x00800000 -+extrv_s.h $t4, $ac1, $t7 :: rt 0xffff8000 ac1 0xbacabacadecadeca rs 0x55555555 DSPCtrl 0x00800000 -+extrv_s.h $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_s.h $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 -+extrv_s.h $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_s.h $t8, $ac3, $t2 :: rt 0xfffffca4 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 -+extrv_s.h $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_s.h $t1, $ac1, $t4 :: rt 0x00007fff ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac2, $t5 :: rt 0x00001c25 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 -+extrv_s.h $t1, $ac1, $t6 :: rt 0xffff8000 ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00800000 -+extrv_s.h $t2, $ac2, $t7 :: rt 0xffff8000 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 -+extrv_s.h $t2, $ac2, $t0 :: rt 0x00007fff ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00800000 -+extrv_s.h $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 -+extrv_s.h $t4, $ac0, $t2 :: rt 0x00007fff ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00800000 -+extrv_s.h $t5, $ac1, $t3 :: rt 0xffff8000 ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00800000 -+extrv_s.h $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 -+extrv_s.h $t7, $ac3, $t4 :: rt 0xffff8000 ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00800000 -+extrv_s.h $t8, $ac0, $t5 :: rt 0xffff8000 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00800000 -+extrv_s.h $t0, $ac1, $t6 :: rt 0xffff8000 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00800000 -+extrv_s.h $t1, $ac2, $t7 :: rt 0xffffffff ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 -+extrv_s.h $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 -+extrv_s.h $t3, $ac0, $t0 :: rt 0x00007fff ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00800000 -+extrv_s.h $t4, $ac1, $t1 :: rt 0xffff8000 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00800000 -+-------- EXTRV.W -------- -+extrv.w $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv.w $t2, $ac2, $t4 :: rt 0xffffffff ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv.w $t1, $ac1, $t7 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00000000 -+extrv.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t2 :: rt 0x7fffffff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t3 :: rt 0xd2aaaaaa ac1 0xaaabad3a55555555 rs 0xbababa05 DSPCtrl 0x00800000 -+extrv.w $t2, $ac2, $t4 :: rt 0x0063fffc ac2 0x00000018ffff2435 rs 0xfbde390e DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t7 :: rt 0xaa221555 ac1 0xaaaaa22155555555 rs 0x55555514 DSPCtrl 0x00800000 -+extrv.w $t2, $ac2, $t5 :: rt 0x0018ffff ac2 0x00000018ffff2435 rs 0x0000cd10 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t2 :: rt 0x52aaaaaa ac1 0xaaaaaaaa55555555 rs 0x80000005 DSPCtrl 0x00800000 -+extrv.w $t2, $ac2, $t3 :: rt 0x000063ff ac2 0x00000018ffff2435 rs 0x7fffff16 DSPCtrl 0x00000000 -+extrv.w $t0, $ac0, $t1 :: rt 0x00337f83 ac0 0x0000cdfe0fde3126 rs 0xbabababa DSPCtrl 0x00000000 -+extrv.w $t3, $ac3, $t2 :: rt 0xeaeaeaae ac3 0xbabababaabababab rs 0xfbde3976 DSPCtrl 0x00800000 -+extrv.w $t6, $ac1, $t7 :: rt 0xfffff800 ac1 0xffffffff00000001 rs 0x55555555 DSPCtrl 0x00000000 -+extrv.w $t4, $ac3, $t5 :: rt 0x00000011 ac3 0x0000000440000000 rs 0x0000cdfe DSPCtrl 0x00000000 -+extrv.w $t1, $ac0, $t2 :: rt 0x80000000 ac0 0x8000000080000000 rs 0x80000000 DSPCtrl 0x00800000 -+extrv.w $t2, $ac1, $t3 :: rt 0x06000000 ac1 0x8000000180000002 rs 0x00000006 DSPCtrl 0x00800000 -+extrv.w $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000000 -+extrv.w $t5, $ac0, $t6 :: rt 0xfdffffff ac0 0x7fffffff7fffffff rs 0x0fde3126 DSPCtrl 0x00800000 -+extrv.w $t7, $ac2, $t8 :: rt 0x007fffff ac2 0x00000001ffffffff rs 0xaaaaaaaa DSPCtrl 0x00000000 -+extrv.w $t8, $ac3, $t9 :: rt 0xffffffff ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 -+extrv.w $t4, $ac0, $t3 :: rt 0xc3c3c3f1 ac0 0xf0f0f0f0fc79b4d2 rs 0x12349876 DSPCtrl 0x00800000 -+extrv.w $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000000 -+extrv.w $t6, $ac2, $t5 :: rt 0xf1cbb000 ac2 0xfbde397600000000 rs 0x00086755 DSPCtrl 0x00800000 -+extrv.w $t7, $ac3, $t6 :: rt 0xed765412 ac3 0x0bed765412349876 rs 0x00000018 DSPCtrl 0x00800000 -+extrv.w $t8, $ac0, $t7 :: rt 0x48700035 ac0 0x2353487000354565 rs 0x23534870 DSPCtrl 0x00800000 -+extrv.w $t0, $ac1, $t8 :: rt 0x2df37800 ac1 0x980b7cde00086755 rs 0x92784656 DSPCtrl 0x00800000 -+extrv.w $t1, $ac2, $t9 :: rt 0x00623e3e ac2 0x000000188f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00000000 -+extrv.w $t2, $ac3, $t1 :: rt 0x95bbbbbb ac3 0x92784656eeeeeeee rs 0xcacacaca DSPCtrl 0x00800000 -+extrv.w $t3, $ac0, $t1 :: rt 0xb286f6f6 ac0 0xcacacaca1bdbdbdb rs 0xbacabaca DSPCtrl 0x00800000 -+extrv.w $t4, $ac1, $t4 :: rt 0xb2b7b2b7 ac1 0xbacabacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00800000 -+extrv.w $t5, $ac0, $t8 :: rt 0x000002fe ac0 0x000000005fc92974 rs 0xffff2435 DSPCtrl 0x00000000 -+extrv.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 -+extrv.w $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 -+extrv.w $t8, $ac3, $t2 :: rt 0xfffffca4 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 -+extrv.w $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t4 :: rt 0x000673b1 ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00000000 -+extrv.w $t2, $ac2, $t5 :: rt 0x00001c25 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00000000 -+extrv.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00000000 -+extrv.w $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 -+extrv.w $t2, $ac2, $t0 :: rt 0x03398f14 ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00000000 -+extrv.w $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 -+extrv.w $t4, $ac0, $t2 :: rt 0x0000969d ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00000000 -+extrv.w $t5, $ac1, $t3 :: rt 0xffff040d ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00000000 -+extrv.w $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 -+extrv.w $t7, $ac3, $t4 :: rt 0xffaf8f7e ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 -+extrv.w $t8, $ac0, $t5 :: rt 0xff87df45 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00000000 -+extrv.w $t0, $ac1, $t6 :: rt 0xffd5fa74 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00000000 -+extrv.w $t1, $ac2, $t7 :: rt 0xffffffff ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 -+extrv.w $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 -+extrv.w $t3, $ac0, $t0 :: rt 0x0079f744 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 -+extrv.w $t4, $ac1, $t1 :: rt 0xe70278c4 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 -+-------- EXTRV_R.W -------- -+extrv_r.w $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac2, $t4 :: rt 0x00000000 ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv_r.w $t1, $ac1, $t7 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac1, $t2 :: rt 0x7fffffff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac1, $t3 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0xbababa05 DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac2, $t4 :: rt 0xfffffffd ac2 0xffffffffffff2435 rs 0xfbde390e DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac1, $t7 :: rt 0x00000555 ac1 0x0000000055555555 rs 0x55555514 DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffff2435 rs 0x0000cd10 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac1, $t2 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0x80000005 DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac2, $t3 :: rt 0x00000000 ac2 0xffffffffffff2435 rs 0x7fffff16 DSPCtrl 0x00000000 -+extrv_r.w $t0, $ac0, $t1 :: rt 0x00000004 ac0 0x000000000fde3126 rs 0xbabababa DSPCtrl 0x00000000 -+extrv_r.w $t3, $ac3, $t2 :: rt 0xfffffeaf ac3 0xffffffffabababab rs 0xfbde3976 DSPCtrl 0x00000000 -+extrv_r.w $t6, $ac1, $t7 :: rt 0x00000000 ac1 0x0000000000000001 rs 0x55555555 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac0, $t2 :: rt 0x80000000 ac0 0xffffffff80000000 rs 0x80000000 DSPCtrl 0x00000000 -+extrv_r.w $t3, $ac2, $t4 :: rt 0x00000000 ac2 0x0000000000000006 rs 0x7fffffff DSPCtrl 0x00000000 -+extrv_r.w $t5, $ac0, $t6 :: rt 0x02000000 ac0 0x000000007fffffff rs 0x0fde3126 DSPCtrl 0x00000000 -+extrv_r.w $t7, $ac2, $t8 :: rt 0x00000000 ac2 0xffffffffffffffff rs 0xaaaaaaaa DSPCtrl 0x00000000 -+extrv_r.w $t8, $ac3, $t9 :: rt 0x00000000 ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_r.w $t4, $ac0, $t3 :: rt 0xfffffff2 ac0 0xfffffffffc79b4d2 rs 0x12349876 DSPCtrl 0x00000000 -+extrv_r.w $t5, $ac1, $t4 :: rt 0x00000000 ac1 0x0000000000000000 rs 0x00354565 DSPCtrl 0x00000000 -+extrv_r.w $t6, $ac2, $t5 :: rt 0x00000000 ac2 0x0000000000000000 rs 0x00086755 DSPCtrl 0x00000000 -+extrv_r.w $t7, $ac3, $t6 :: rt 0x00000012 ac3 0x0000000012349876 rs 0x00000018 DSPCtrl 0x00000000 -+extrv_r.w $t8, $ac0, $t7 :: rt 0x00000035 ac0 0x0000000000354565 rs 0x23534870 DSPCtrl 0x00000000 -+extrv_r.w $t0, $ac1, $t8 :: rt 0x00000000 ac1 0x0000000000086755 rs 0x92784656 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac2, $t9 :: rt 0xfffe3e3e ac2 0xffffffff8f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac3, $t1 :: rt 0xfffbbbbc ac3 0xffffffffeeeeeeee rs 0xcacacaca DSPCtrl 0x00000000 -+extrv_r.w $t3, $ac0, $t1 :: rt 0x0006f6f7 ac0 0x000000001bdbdbdb rs 0xbacabaca DSPCtrl 0x00000000 -+extrv_r.w $t4, $ac1, $t4 :: rt 0xfff7b2b8 ac1 0xffffffffdecadeca rs 0x1bdbdbdb DSPCtrl 0x00000000 -+extrv_r.w $t5, $ac0, $t8 :: rt 0x878782fe ac0 0xf0f0f0f05fc92974 rs 0xffff2435 DSPCtrl 0x00800000 -+extrv_r.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 -+extrv_r.w $t7, $ac2, $t1 :: rt 0xf1cbb38e ac2 0xfbde397671c8315f rs 0xffff2435 DSPCtrl 0x00800000 -+extrv_r.w $t8, $ac3, $t2 :: rt 0x6bb2a4a5 ac3 0x0bed76549493110e rs 0x55555555 DSPCtrl 0x00800000 -+extrv_r.w $t0, $ac0, $t3 :: rt 0x9a4385d9 ac0 0x23534870bb246228 rs 0xffff2435 DSPCtrl 0x00800000 -+extrv_r.w $t1, $ac1, $t4 :: rt 0x9bc673b2 ac1 0x980b7cde339d8d88 rs 0xabababab DSPCtrl 0x00800000 -+extrv_r.w $t2, $ac2, $t5 :: rt 0x00061c26 ac2 0x0000001870974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0x927846568a8d4e7d rs 0x00000000 DSPCtrl 0x00800000 -+extrv_r.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xcacacacaeb1b4335 rs 0x00000000 DSPCtrl 0x00800000 -+extrv_r.w $t1, $ac1, $t8 :: rt 0x2aeb2833 ac1 0xbacabaca0cd6b508 rs 0x12349876 DSPCtrl 0x00800000 -+extrv_r.w $t2, $ac2, $t0 :: rt 0x03398f14 ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00000000 -+extrv_r.w $t3, $ac3, $t1 :: rt 0x000005b7 ac3 0x00000000b6edf28f rs 0x00086755 DSPCtrl 0x00000000 -+extrv_r.w $t4, $ac0, $t2 :: rt 0x0000969e ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00000000 -+extrv_r.w $t5, $ac1, $t3 :: rt 0xffff040e ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00000000 -+extrv_r.w $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 -+extrv_r.w $t7, $ac3, $t4 :: rt 0x00af8f7e ac3 0x00000000af8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 -+extrv_r.w $t8, $ac0, $t5 :: rt 0x0087df45 ac0 0x0000000087df4510 rs 0x339d8d88 DSPCtrl 0x00000000 -+extrv_r.w $t0, $ac1, $t6 :: rt 0xffd5fa74 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00000000 -+extrv_r.w $t1, $ac2, $t7 :: rt 0x00000000 ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 -+extrv_r.w $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 -+extrv_r.w $t3, $ac0, $t0 :: rt 0x0079f745 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 -+extrv_r.w $t4, $ac1, $t1 :: rt 0xe70278c5 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 -+-------- EXTRV_RS.W -------- -+extrv_rs.w $t1, $ac1, $t3 :: rt 0x00000000 ac1 0x0000000000000000 rs 0xbababa00 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t3 :: rt 0x80000000 ac1 0x987b2fffffffffff rs 0xbababa00 DSPCtrl 0x00800000 -+extrv_rs.w $t2, $ac2, $t4 :: rt 0x7fffffff ac2 0x7fffffffcbcdef01 rs 0xfbde391f DSPCtrl 0x00800000 -+extrv_rs.w $t1, $ac1, $t7 :: rt 0x7ffffffe ac1 0x3fffffff2bcdef01 rs 0x5555551f DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffffffff rs 0x0000cd00 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t2 :: rt 0x7fffffff ac1 0x00000000fffffffe rs 0x80000001 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t3 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0xbababa05 DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t4 :: rt 0xfffffffd ac2 0xffffffffffff2435 rs 0xfbde390e DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t7 :: rt 0x00000555 ac1 0x0000000055555555 rs 0x55555514 DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t5 :: rt 0xffffffff ac2 0xffffffffffff2435 rs 0x0000cd10 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t2 :: rt 0x02aaaaab ac1 0x0000000055555555 rs 0x80000005 DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t3 :: rt 0x00000000 ac2 0xffffffffffff2435 rs 0x7fffff16 DSPCtrl 0x00000000 -+extrv_rs.w $t0, $ac0, $t1 :: rt 0x00000004 ac0 0x000000000fde3126 rs 0xbabababa DSPCtrl 0x00000000 -+extrv_rs.w $t3, $ac3, $t2 :: rt 0xfffffeaf ac3 0xffffffffabababab rs 0xfbde3976 DSPCtrl 0x00000000 -+extrv_rs.w $t6, $ac1, $t7 :: rt 0x00000000 ac1 0x0000000000000001 rs 0x55555555 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac0, $t2 :: rt 0x80000000 ac0 0xffffffff80000000 rs 0x80000000 DSPCtrl 0x00000000 -+extrv_rs.w $t5, $ac0, $t6 :: rt 0x02000000 ac0 0x000000007fffffff rs 0x0fde3126 DSPCtrl 0x00000000 -+extrv_rs.w $t7, $ac2, $t8 :: rt 0x00000000 ac2 0xffffffffffffffff rs 0xaaaaaaaa DSPCtrl 0x00000000 -+extrv_rs.w $t8, $ac3, $t9 :: rt 0x00000000 ac3 0xffffffffffffffff rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_rs.w $t4, $ac0, $t3 :: rt 0xfffffff2 ac0 0xfffffffffc79b4d2 rs 0x12349876 DSPCtrl 0x00000000 -+extrv_rs.w $t5, $ac1, $t4 :: rt 0x80000000 ac1 0xf0f0f0f000000000 rs 0x00354565 DSPCtrl 0x00800000 -+extrv_rs.w $t6, $ac2, $t5 :: rt 0x00000000 ac2 0x0000000000000000 rs 0x00086755 DSPCtrl 0x00000000 -+extrv_rs.w $t7, $ac3, $t6 :: rt 0x80000000 ac3 0xfbde397612349876 rs 0x00000018 DSPCtrl 0x00800000 -+extrv_rs.w $t8, $ac0, $t7 :: rt 0x7fffffff ac0 0x0bed765400354565 rs 0x23534870 DSPCtrl 0x00800000 -+extrv_rs.w $t0, $ac1, $t8 :: rt 0x7fffffff ac1 0x2353487000086755 rs 0x92784656 DSPCtrl 0x00800000 -+extrv_rs.w $t1, $ac2, $t9 :: rt 0x80000000 ac2 0x980b7cde8f8f8f8f rs 0xeeeeeeee DSPCtrl 0x00800000 -+extrv_rs.w $t2, $ac3, $t1 :: rt 0x063bbbbc ac3 0x00000018eeeeeeee rs 0xcacacaca DSPCtrl 0x00000000 -+extrv_rs.w $t3, $ac0, $t1 :: rt 0x80000000 ac0 0x927846561bdbdbdb rs 0xbacabaca DSPCtrl 0x00800000 -+extrv_rs.w $t4, $ac1, $t4 :: rt 0x80000000 ac1 0xcacacacadecadeca rs 0x1bdbdbdb DSPCtrl 0x00800000 -+extrv_rs.w $t5, $ac0, $t8 :: rt 0x80000000 ac0 0xbacabaca5fc92974 rs 0xffff2435 DSPCtrl 0x00800000 -+extrv_rs.w $t6, $ac1, $t0 :: rt 0x000003f0 ac1 0x000000007e08184e rs 0x55555555 DSPCtrl 0x00000000 -+extrv_rs.w $t7, $ac2, $t1 :: rt 0x0000038e ac2 0x0000000071c8315f rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_rs.w $t8, $ac3, $t2 :: rt 0xfffffca5 ac3 0xffffffff9493110e rs 0x55555555 DSPCtrl 0x00000000 -+extrv_rs.w $t0, $ac0, $t3 :: rt 0xfffffdd9 ac0 0xffffffffbb246228 rs 0xffff2435 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t4 :: rt 0x000673b2 ac1 0x00000000339d8d88 rs 0xabababab DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t5 :: rt 0x00001c26 ac2 0x0000000070974249 rs 0xfc79b4d2 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t6 :: rt 0x8a8d4e7d ac1 0xffffffff8a8d4e7d rs 0x00000000 DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t7 :: rt 0xeb1b4335 ac2 0xffffffffeb1b4335 rs 0x00000000 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac1, $t8 :: rt 0x00000033 ac1 0x000000000cd6b508 rs 0x12349876 DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac2, $t0 :: rt 0x03398f14 ac2 0x000000006731e282 rs 0x00354565 DSPCtrl 0x00000000 -+extrv_rs.w $t3, $ac3, $t1 :: rt 0xfffffdb7 ac3 0xffffffffb6edf28f rs 0x00086755 DSPCtrl 0x00000000 -+extrv_rs.w $t4, $ac0, $t2 :: rt 0x0000969e ac0 0x000000004b4ec9ca rs 0x8f8f8f8f DSPCtrl 0x00000000 -+extrv_rs.w $t5, $ac1, $t3 :: rt 0xffff040e ac1 0xffffffffc1037fa4 rs 0xeeeeeeee DSPCtrl 0x00000000 -+extrv_rs.w $t6, $ac2, $t3 :: rt 0xfffffff9 ac2 0xffffffffcb4ab48f rs 0x1bdbdbdb DSPCtrl 0x00000000 -+extrv_rs.w $t7, $ac3, $t4 :: rt 0xffaf8f7e ac3 0xffffffffaf8f7e18 rs 0xbb246228 DSPCtrl 0x00000000 -+extrv_rs.w $t8, $ac0, $t5 :: rt 0xff87df45 ac0 0xffffffff87df4510 rs 0x339d8d88 DSPCtrl 0x00000000 -+extrv_rs.w $t0, $ac1, $t6 :: rt 0xffd5fa74 ac1 0xffffffffabf4e8e1 rs 0x70974249 DSPCtrl 0x00000000 -+extrv_rs.w $t1, $ac2, $t7 :: rt 0x00000000 ac2 0xfffffffff4c0eeac rs 0x8a8d4e7d DSPCtrl 0x00000000 -+extrv_rs.w $t2, $ac3, $t8 :: rt 0x00000003 ac3 0x00000000006a54f2 rs 0xeb1b4335 DSPCtrl 0x00000000 -+extrv_rs.w $t3, $ac0, $t0 :: rt 0x0079f745 ac0 0x0000000079f74493 rs 0x0cd6b508 DSPCtrl 0x00000000 -+extrv_rs.w $t4, $ac1, $t1 :: rt 0xe70278c5 ac1 0xffffffff9c09e313 rs 0x6731e282 DSPCtrl 0x00000000 -+-------- INSV -------- -+insv :: out: 0xffffff7f rtIN 0xffffffff rsIN 0x00000000 posI 7 sizeI 1 -+insv :: out: 0x004c9f31 rtIN 0x004dfbe5 rsIN 0xe87927cc posI 2 sizeI 15 -+insv :: out: 0xf6a3fa1c rtIN 0xf6a3fa3c rsIN 0x083b3571 posI 4 sizeI 2 -+insv :: out: 0xbf17fb9a rtIN 0xbf17fb9a rsIN 0xb9743941 posI 13 sizeI 0 -+insv :: out: 0x2c0bd084 rtIN 0x2c0bd024 rsIN 0xbce5f924 posI 5 sizeI 5 -+insv :: out: 0x088593c0 rtIN 0x288593c0 rsIN 0x722d5e20 posI 28 sizeI 4 -+insv :: out: 0xa1d6f791 rtIN 0x4d7ff5b4 rsIN 0xa1d6f791 posI 0 sizeI 32 -+insv :: out: 0x3ee7be13 rtIN 0x4557be13 rsIN 0x7b11bee7 posI 16 sizeI 15 -+insv :: out: 0xadc45772 rtIN 0xadcf5772 rsIN 0xa5631488 posI 15 sizeI 7 -+insv :: out: 0x9b2a7235 rtIN 0x989a7235 rsIN 0xb10bcc65 posI 19 sizeI 8 -+insv :: out: 0x0d6f393a rtIN 0x4d6f393a rsIN 0x73f39fca posI 30 sizeI 1 -+insv :: out: 0x2c91ca80 rtIN 0x24a3291e rsIN 0x5648e540 posI 1 sizeI 28 -+insv :: out: 0xdd8deebf rtIN 0xdd91eebf rsIN 0xc54f79e6 posI 17 sizeI 5 -+insv :: out: 0xf3ce2ec6 rtIN 0xf7ce2ec6 rsIN 0x5fc92974 posI 26 sizeI 2 -+insv :: out: 0xbe1383e8 rtIN 0xbc1083e8 rsIN 0x7e08184e posI 14 sizeI 13 -+insv :: out: 0xa6315f31 rtIN 0xa617cc31 rsIN 0x71c8315f posI 8 sizeI 17 -+insv :: out: 0xdfe21cf0 rtIN 0xdfe1e8f0 rsIN 0x9493110e posI 9 sizeI 11 -+insv :: out: 0x14458a23 rtIN 0x31458a23 rsIN 0xbb246228 posI 23 sizeI 9 -+insv :: out: 0x85636211 rtIN 0x848af791 rsIN 0x339d8d88 posI 6 sizeI 19 -+insv :: out: 0xda4bacdc rtIN 0xda3bacdc rsIN 0x70974249 posI 19 sizeI 8 -+insv :: out: 0x2ff00080 rtIN 0x2fff0000 rsIN 0x00000001 posI 7 sizeI 13 -+insv :: out: 0x2fd06008 rtIN 0x2fff0000 rsIN 0x73741802 posI 2 sizeI 23 -+insv :: out: 0x00034030 rtIN 0x2fff0000 rsIN 0x80003403 posI 4 sizeI 28 -+insv :: out: 0xab800000 rtIN 0xabababab rsIN 0x00000000 posI 0 sizeI 22 -+insv :: out: 0xdecadeca rtIN 0xdecadeca rsIN 0x80000000 posI 26 sizeI 0 -+insv :: out: 0xbacadaca rtIN 0xbacabaca rsIN 0x55555555 posI 12 sizeI 3 -+insv :: out: 0x35fe4868 rtIN 0x3545ff80 rsIN 0xffff2434 posI 1 sizeI 23 -+insv :: out: 0xc4de9620 rtIN 0xc4dbfe20 rsIN 0xfc79b4d2 posI 11 sizeI 8 -+insv :: out: 0x00000000 rtIN 0x00000000 rsIN 0x00000000 posI 16 sizeI 9 -+insv :: out: 0x8ceabce4 rtIN 0xad80bce4 rsIN 0x00086755 posI 13 sizeI 17 -+insv :: out: 0x7f8f8f45 rtIN 0x7f003245 rsIN 0x8f8f8f8f posI 8 sizeI 18 -+insv :: out: 0x980decae rtIN 0x980b7cde rsIN 0xdecadeca posI 4 sizeI 15 -+DSP LWX -+MEM: -+0x121f1e1f, 0x00000000, 0x00000003, 0xffffffff -+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a -+0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a -+0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c -+lwx :: out: 0x121f1e1f mem[0] -+lwx :: out: 0x00000000 mem[4] -+lwx :: out: 0x00000003 mem[8] -+lwx :: out: 0xffffffff mem[12] -+lwx :: out: 0x232f2e2f mem[16] -+lwx :: out: 0x242c2b2b mem[20] -+lwx :: out: 0x252a2e2b mem[24] -+lwx :: out: 0x262d2d2a mem[28] -+lwx :: out: 0x3f343f3e mem[32] -+lwx :: out: 0x3e353d3c mem[36] -+lwx :: out: 0x363a3c3b mem[40] -+lwx :: out: 0x3b373b3a mem[44] -+lwx :: out: 0x454f4e45 mem[48] -+lwx :: out: 0x4e464d46 mem[52] -+lwx :: out: 0x474d474c mem[56] -+lwx :: out: 0x4a484a4c mem[60] -+DSP LHX -+MEM: -+0x121f1e1f, 0x00000000, 0x00000003, 0xffffffff -+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a -+0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a -+0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c -+lhx :: out: 0x00001e1f mem[0] -+lhx :: out: 0x0000121f mem[2] -+lhx :: out: 0x00000000 mem[4] -+lhx :: out: 0x00000000 mem[6] -+lhx :: out: 0x00000003 mem[8] -+lhx :: out: 0x00000000 mem[10] -+lhx :: out: 0xffffffff mem[12] -+lhx :: out: 0xffffffff mem[14] -+lhx :: out: 0x00002e2f mem[16] -+lhx :: out: 0x0000232f mem[18] -+lhx :: out: 0x00002b2b mem[20] -+lhx :: out: 0x0000242c mem[22] -+lhx :: out: 0x00002e2b mem[24] -+lhx :: out: 0x0000252a mem[26] -+lhx :: out: 0x00002d2a mem[28] -+lhx :: out: 0x0000262d mem[30] -+lhx :: out: 0x00003f3e mem[32] -+lhx :: out: 0x00003f34 mem[34] -+lhx :: out: 0x00003d3c mem[36] -+lhx :: out: 0x00003e35 mem[38] -+lhx :: out: 0x00003c3b mem[40] -+lhx :: out: 0x0000363a mem[42] -+lhx :: out: 0x00003b3a mem[44] -+lhx :: out: 0x00003b37 mem[46] -+lhx :: out: 0x00004e45 mem[48] -+lhx :: out: 0x0000454f mem[50] -+lhx :: out: 0x00004d46 mem[52] -+lhx :: out: 0x00004e46 mem[54] -+lhx :: out: 0x0000474c mem[56] -+lhx :: out: 0x0000474d mem[58] -+lhx :: out: 0x00004a4c mem[60] -+lhx :: out: 0x00004a48 mem[62] -+DSP LBUX -+MEM: -+0x121f1e1f, 0x00000000, 0x00000003, 0xffffffff -+0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a -+0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a -+0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c -+lbux :: out: 0x0000001f mem[0] -+lbux :: out: 0x0000001e mem[1] -+lbux :: out: 0x0000001f mem[2] -+lbux :: out: 0x00000012 mem[3] -+lbux :: out: 0x00000000 mem[4] -+lbux :: out: 0x00000000 mem[5] -+lbux :: out: 0x00000000 mem[6] -+lbux :: out: 0x00000000 mem[7] -+lbux :: out: 0x00000003 mem[8] -+lbux :: out: 0x00000000 mem[9] -+lbux :: out: 0x00000000 mem[10] -+lbux :: out: 0x00000000 mem[11] -+lbux :: out: 0x000000ff mem[12] -+lbux :: out: 0x000000ff mem[13] -+lbux :: out: 0x000000ff mem[14] -+lbux :: out: 0x000000ff mem[15] -+lbux :: out: 0x0000002f mem[16] -+lbux :: out: 0x0000002e mem[17] -+lbux :: out: 0x0000002f mem[18] -+lbux :: out: 0x00000023 mem[19] -+lbux :: out: 0x0000002b mem[20] -+lbux :: out: 0x0000002b mem[21] -+lbux :: out: 0x0000002c mem[22] -+lbux :: out: 0x00000024 mem[23] -+lbux :: out: 0x0000002b mem[24] -+lbux :: out: 0x0000002e mem[25] -+lbux :: out: 0x0000002a mem[26] -+lbux :: out: 0x00000025 mem[27] -+lbux :: out: 0x0000002a mem[28] -+lbux :: out: 0x0000002d mem[29] -+lbux :: out: 0x0000002d mem[30] -+lbux :: out: 0x00000026 mem[31] -+lbux :: out: 0x0000003e mem[32] -+lbux :: out: 0x0000003f mem[33] -+lbux :: out: 0x00000034 mem[34] -+lbux :: out: 0x0000003f mem[35] -+lbux :: out: 0x0000003c mem[36] -+lbux :: out: 0x0000003d mem[37] -+lbux :: out: 0x00000035 mem[38] -+lbux :: out: 0x0000003e mem[39] -+lbux :: out: 0x0000003b mem[40] -+lbux :: out: 0x0000003c mem[41] -+lbux :: out: 0x0000003a mem[42] -+lbux :: out: 0x00000036 mem[43] -+lbux :: out: 0x0000003a mem[44] -+lbux :: out: 0x0000003b mem[45] -+lbux :: out: 0x00000037 mem[46] -+lbux :: out: 0x0000003b mem[47] -+lbux :: out: 0x00000045 mem[48] -+lbux :: out: 0x0000004e mem[49] -+lbux :: out: 0x0000004f mem[50] -+lbux :: out: 0x00000045 mem[51] -+lbux :: out: 0x00000046 mem[52] -+lbux :: out: 0x0000004d mem[53] -+lbux :: out: 0x00000046 mem[54] -+lbux :: out: 0x0000004e mem[55] -+lbux :: out: 0x0000004c mem[56] -+lbux :: out: 0x00000047 mem[57] -+lbux :: out: 0x0000004d mem[58] -+lbux :: out: 0x00000047 mem[59] -+lbux :: out: 0x0000004c mem[60] -+lbux :: out: 0x0000004a mem[61] -+lbux :: out: 0x00000048 mem[62] -+lbux :: out: 0x0000004a mem[63] -+-------- MADD -------- -+madd $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+madd $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000006 -+madd $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x3fffd3d5 outLO 0x475f6ed5 -+madd $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0xbfffffff -+madd $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000001 -+madd $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffefffe -+madd $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010000 -+madd $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x13f3efc6 -+madd $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+madd $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x3fffffff outLO 0xffff2435 -+madd $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xe38e38e3 outLO 0x1d72c81d -+madd $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc6519ca -+madd $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x16d18c47 outLO 0x6db2f83e -+madd $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x0035137b outLO 0x307e64e0 -+madd $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+madd $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x61c70995 -+madd $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfffc9666 outLO 0x02062f0b -+madd $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xfffffff5 outLO 0x050504f7 -+madd $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x074d50a5 outLO 0x441846e2 -+madd $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xfa35b12c outLO 0xdba024a9 -+madd $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x08fa3aed outLO 0xa0216e2e -+madd $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xf7f07860 outLO 0xa7ff27f6 -+madd $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xfe1003c1 outLO 0x3efc246a -+madd $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3572 -+madd $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0x7a7656c1 -+madd $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x07e4ad9d outLO 0x6fcbbfbe -+madd $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xfcef12ea outLO 0x4e9d07d4 -+madd $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xde8dfafd outLO 0x4760e93e -+madd $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xd80a3262 outLO 0xca5f854f -+madd $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x0d7a3e4f outLO 0x6279a4b1 -+madd $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xf2bf4270 outLO 0xcabcba5f -+madd $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xe71bb44a outLO 0x507e7690 -+madd $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xef63cb0b outLO 0x8464cf21 -+madd $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xd1d700c6 outLO 0x7d247e13 -+madd $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x0528cc22 outLO 0x5cef2af5 -+madd $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdc outLO 0xd548eae6 -+madd $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda8 outLO 0x075646f2 -+madd $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffe7a outLO 0xe0c66cc9 -+madd $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+madd $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x1f7e402d outLO 0x9493110e -+madd $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xee6e3c2f outLO 0x7760d0a3 -+madd $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00002838 outLO 0x739d8d88 -+madd $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x27924fa7 outLO 0x278c13f9 -+madd $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x012837c1 outLO 0x5b8b8b0f -+madd $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+madd $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x75c97282 -+madd $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x877acc51 -+madd $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x000031fa outLO 0xf6edf28f -+-------- MADDU -------- -+maddu $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+maddu $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000006 -+maddu $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x40002c2b outLO 0x475f6ed5 -+maddu $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0xbfffffff -+maddu $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000001 -+maddu $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00010000 outLO 0xfffefffe -+maddu $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010000 -+maddu $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x13f3efc6 -+maddu $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+maddu $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x3fffffff outLO 0xffff2435 -+maddu $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x38e38e38 outLO 0x1d72c81d -+maddu $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0x00000017 outLO 0xfc6519ca -+maddu $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x7d37f2ac outLO 0x6db2f83e -+maddu $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xed9fb93d outLO 0x307e64e0 -+maddu $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+maddu $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x61c70995 -+maddu $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x0004fdbb outLO 0x02062f0b -+maddu $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x0000000d outLO 0x050504f7 -+maddu $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x88b485e9 outLO 0x441846e2 -+maddu $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x16118d07 outLO 0xdba024a9 -+maddu $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xa28fd481 outLO 0xa0216e2e -+maddu $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x0aeb5714 outLO 0xa7ff27f6 -+maddu $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x7a100b51 outLO 0x3efc246a -+maddu $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0xfffffffe outLO 0x083b3572 -+maddu $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0x7a7656c1 -+maddu $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xaac61642 outLO 0x6fcbbfbe -+maddu $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x5cb83c5e outLO 0x4e9d07d4 -+maddu $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x5c96134b outLO 0x4760e93e -+maddu $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x49d263c1 outLO 0xca5f854f -+maddu $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x81ef384d outLO 0x6279a4b1 -+maddu $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x2404cc93 outLO 0xcabcba5f -+maddu $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x1ab941d2 outLO 0x507e7690 -+maddu $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x5ffb0d54 outLO 0x8464cf21 -+maddu $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x36745d83 outLO 0x7d247e13 -+maddu $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xb10cd7d8 outLO 0x5cef2af5 -+maddu $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdc outLO 0xd548eae6 -+maddu $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda8 outLO 0x075646f2 -+maddu $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x000003cf outLO 0xe0c66cc9 -+maddu $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+maddu $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x6081bfd1 outLO 0x9493110e -+maddu $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x43c39184 outLO 0x7760d0a3 -+maddu $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xaf8f2838 outLO 0x739d8d88 -+maddu $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x5b1d4062 outLO 0x278c13f9 -+maddu $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xa996d574 outLO 0x5b8b8b0f -+maddu $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+maddu $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x75c97282 -+maddu $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x877acc51 -+maddu $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x9c0931fa outLO 0xf6edf28f -+-------- MSUB -------- -+msub $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+msub $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0xffffffff outLO 0x00000006 -+msub $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0xc0002c2b outLO 0x38a0912b -+msub $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0xcab7743b outLO 0x3fffffff -+msub $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xc0000000 outLO 0x00000001 -+msub $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00010000 -+msub $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xc0008000 outLO 0xbffefffe -+msub $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0bc87286 -+msub $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+msub $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xbfffffff outLO 0xffff2435 -+msub $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x1c71c71c outLO 0x39e48f39 -+msub $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc8e4fda -+msub $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xe92e73b8 outLO 0x924d07c2 -+msub $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffcaec84 outLO 0xcf819b20 -+msub $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+msub $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xfff8a62e outLO 0x9ea38135 -+msub $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00036999 outLO 0xfe0a9f9f -+msub $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x0000000a outLO 0x1a1a1a27 -+msub $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xf8b2af5a outLO 0x99c596fa -+msub $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x05ca4ed3 outLO 0x5c17930d -+msub $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xf705c512 outLO 0x1d744f66 -+msub $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x080f879e outLO 0x7e8f6fc6 -+msub $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x01effc3e outLO 0xb683338a -+msub $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3570 -+msub $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xf3a6c17c outLO 0xf8721bc1 -+msub $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xf81b5262 outLO 0x0a00328a -+msub $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x0310ed15 outLO 0x49db3864 -+msub $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x21720502 outLO 0xf61507de -+msub $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x27f5cd9e outLO 0x19fb36f1 -+msub $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xf285c1af outLO 0xe1344a71 -+msub $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x0d40bd90 outLO 0x2b66c36f -+msub $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x18e44bb4 outLO 0xfa47b280 -+msub $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x109c34f3 outLO 0xddb2c9a9 -+msub $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x2e28ff3a outLO 0x6ac2c181 -+msub $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xfad733de outLO 0x4fa29f8b -+msub $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xf9b05322 outLO 0xb55608e6 -+msub $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0xcc674258 outLO 0xb83c0bf6 -+msub $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000186 outLO 0x1b49c3d3 -+msub $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+msub $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xe081bfd1 outLO 0x9493110e -+msub $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x1191c3cf outLO 0xfee7f3ad -+msub $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffd7c7 outLO 0xf39d8d88 -+msub $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0xd86db059 outLO 0xb9a27099 -+msub $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xfed7c83d outLO 0xb98f11eb -+msub $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+msub $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffe9df outLO 0xa3e3f78e -+msub $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0xfffbff0b outLO 0x46e8f8b3 -+msub $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffce04 outLO 0x76edf28f -+-------- MSUBU -------- -+msubu $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 -+msubu $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0xffffffff outLO 0x00000006 -+msubu $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0xbfffd3d5 outLO 0x38a0912b -+msubu $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0xcab7743b outLO 0x3fffffff -+msubu $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0xc0000000 outLO 0x00000001 -+msubu $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xfffeffff outLO 0x00010000 -+msubu $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xc0008000 outLO 0xbffefffe -+msubu $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0bc87286 -+msubu $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 -+msubu $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xbfffffff outLO 0xffff2435 -+msubu $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xc71c71c7 outLO 0x39e48f39 -+msubu $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffe7 outLO 0xfc8e4fda -+msubu $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x82c80d53 outLO 0x924d07c2 -+msubu $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x126046c2 outLO 0xcf819b20 -+msubu $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 -+msubu $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xfff8a62e outLO 0x9ea38135 -+msubu $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfffb0244 outLO 0xfe0a9f9f -+msubu $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xfffffff2 outLO 0x1a1a1a27 -+msubu $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x774b7a16 outLO 0x99c596fa -+msubu $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xe9ee72f8 outLO 0x5c17930d -+msubu $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x5d702b7e outLO 0x1d744f66 -+msubu $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xf514a8ea outLO 0x7e8f6fc6 -+msubu $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x85eff4ae outLO 0xb683338a -+msubu $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000002 outLO 0x083b3570 -+msubu $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xf3a6c17c outLO 0xf8721bc1 -+msubu $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x5539e9bd outLO 0x0a00328a -+msubu $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xa347c3a1 outLO 0x49db3864 -+msubu $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xa369ecb4 outLO 0xf61507de -+msubu $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xb62d9c3f outLO 0x19fb36f1 -+msubu $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x7e10c7b1 outLO 0xe1344a71 -+msubu $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xdbfb336d outLO 0x2b66c36f -+msubu $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xe546be2c outLO 0xfa47b280 -+msubu $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xa004f2aa outLO 0xddb2c9a9 -+msubu $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xc98ba27d outLO 0x6ac2c181 -+msubu $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x4ef32828 outLO 0x4fa29f8b -+msubu $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xf9b05322 outLO 0xb55608e6 -+msubu $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0xcc674258 outLO 0xb83c0bf6 -+msubu $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffc31 outLO 0x1b49c3d3 -+msubu $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f -+msubu $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x9f7e402d outLO 0x9493110e -+msubu $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xbc3c6e7a outLO 0xfee7f3ad -+msubu $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x5070d7c7 outLO 0xf39d8d88 -+msubu $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0xa4e2bf9e outLO 0xb9a27099 -+msubu $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x56692a8a outLO 0xb98f11eb -+msubu $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 -+msubu $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffe9df outLO 0xa3e3f78e -+msubu $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0xfffbff0b outLO 0x46e8f8b3 -+msubu $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x63f6ce04 outLO 0x76edf28f -+-------- MAQ_S.W.PHR -------- -+maq_s.w.phr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x4ebeddaa dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0xfffffffe dspCtrl 0x00080000 -+maq_s.w.phr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0d5fae66 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x72c7e48f dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc807ec2 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x08d8c9c0 dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x277acdc5 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x64d5f6c1 dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f7a7a5f dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xe58d9ed6 dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x2ae26d77 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x7f8b040e dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfb389cda dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb0dc7441 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xac778658 dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xdb61ef8c dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x072ad9ee dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x5e31ac7e dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0x9ec451d1 dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x20afb5d7 dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xacedd898 dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x85fdd1dd dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0xacd15c5c dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x392570aa dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xb6025be6 dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x424b6470 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7d78c144 dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x88d93f1e dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0xb39d8d87 dspCtrl 0x00040000 -+maq_s.w.phr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x4316e5a9 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x9821c7a1 dspCtrl 0x00000000 -+maq_s.w.phr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+maq_s.w.phr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x3ae42ffc dspCtrl 0x00000000 -+maq_s.w.phr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x9e8db620 dspCtrl 0x00000000 -+maq_s.w.phr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x00000000 outLO 0x36edf28e dspCtrl 0x00020000 -+-------- MAQ_SA.W.PHR -------- -+maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x4ebeddaa dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00080000 -+maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0d5fae66 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00080000 -+maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc807ec2 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x08d8c9c0 dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x277acdc5 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x64d5f6c1 dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f7a7a5f dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xe58d9ed6 dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x2ae26d77 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00040000 -+maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xfb389cda dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xb0dc7441 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xac778658 dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xdb61ef8c dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x00000000 outLO 0x072ad9ee dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x5e31ac7e dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0x9ec451d1 dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x20afb5d7 dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0xacedd898 dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x85fdd1dd dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00020000 -+maq_sa.w.phr $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x392570aa dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xb6025be6 dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x424b6470 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7d78c144 dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0x9493110e dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x88d93f1e dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00040000 -+maq_sa.w.phr $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x4316e5a9 dspCtrl 0x00000000 -+maq_sa.w.phr $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x9821c7a1 dspCtrl 0x00000000 -+maq_sa.w.phr $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+maq_sa.w.phr $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x3ae42ffc dspCtrl 0x00000000 -+maq_sa.w.phr $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 -+maq_sa.w.phr $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x00000000 outLO 0x36edf28e dspCtrl 0x00020000 -+-------- MAQ_S.W.PHL -------- -+maq_s.w.phl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0xbfffffff dspCtrl 0x00020000 -+maq_s.w.phl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0xea902def dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x80000000 dspCtrl 0x00010000 -+maq_s.w.phl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 -+maq_s.w.phl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x72c7e48f dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x006a42e0 dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x0043e5c3 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0001e805 dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xfd8a660e dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x10476d77 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x8328ee8a dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf6dfabfa dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xd22658f1 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xccafe2a2 dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xc61a2598 dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xdbd6798e dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x22413010 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xbccc3bf7 dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x6090684f dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x739aa1cc dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x8fd2ddff dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x17a1b8bc dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x609abf70 dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xd1ee1f06 dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0xc6f95b12 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x9800854c dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339e2e6a dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0xbfbcb033 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8cde3b25 dspCtrl 0x00000000 -+maq_s.w.phl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+maq_s.w.phl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd6e0ec dspCtrl 0x00000000 -+maq_s.w.phl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x673981f2 dspCtrl 0x00000000 -+maq_s.w.phl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6eeba7d dspCtrl 0x00000000 -+-------- MAQ_SA.W.PHL -------- -+maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00020000 -+maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00080000 -+maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 -+maq_sa.w.phl $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffffffd dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x7ffe0001 dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 -+maq_sa.w.phl $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00080000 -+maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b4d2 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x2da3f07c dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x006a42e0 dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x00000000 outLO 0x0043e5c3 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x00000000 outLO 0x0001e805 dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8f8f8f8f dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0xffffffff outLO 0xfd8a660e dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x10476d77 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xf0bffd92 dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x8328ee8a dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf6dfabfa dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3573 dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xd22658f1 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xccafe2a2 dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xc61a2598 dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xdbd6798e dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x22413010 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xbccc3bf7 dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0x6090684f dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00080000 -+maq_sa.w.phl $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0x8fd2ddff dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x00000000 outLO 0x17a1b8bc dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x609abf70 dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xd1ee1f06 dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 -+maq_sa.w.phl $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e08184e dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0x9800854c dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00000000 outLO 0x339e2e6a dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00010000 -+maq_sa.w.phl $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x8cde3b25 dspCtrl 0x00000000 -+maq_sa.w.phl $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+maq_sa.w.phl $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0cd6e0ec dspCtrl 0x00000000 -+maq_sa.w.phl $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x673981f2 dspCtrl 0x00000000 -+maq_sa.w.phl $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0xb6eeba7d dspCtrl 0x00000000 -+-------- MTHI, MTLO, MFHI, MFLO -------- -+rs_hi: 0x00000000 rs_lo: 0x00000006 ac0 out HI: 0x00000000, out LO: 0x00000006 -+rs_hi: 0x00000055 rs_lo: 0x00000286 ac1 out HI: 0x00000055, out LO: 0x00000286 -+rs_hi: 0x00000018 rs_lo: 0x00000fff ac2 out HI: 0x00000018, out LO: 0x00000fff -+rs_hi: 0x7fffffff rs_lo: 0x7fffffff ac3 out HI: 0x7fffffff, out LO: 0x7fffffff -+rs_hi: 0xffffffff rs_lo: 0x00000001 ac0 out HI: 0xffffffff, out LO: 0x00000001 -+rs_hi: 0x00000001 rs_lo: 0xffffffff ac1 out HI: 0x00000001, out LO: 0xffffffff -+rs_hi: 0x00000002 rs_lo: 0x00000006 ac2 out HI: 0x00000002, out LO: 0x00000006 -+rs_hi: 0x00000356 rs_lo: 0x00000555 ac3 out HI: 0x00000356, out LO: 0x00000555 -+-------- MODSUB -------- -+modsub $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+modsub $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00045f2c -+modsub $t4, $t1, $t5 :: rs 0x00002435 rt 0xffff3421 out 0x00002414 -+modsub $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x07654bfc -+modsub $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b -+modsub $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ff02 -+modsub $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7f00 -+modsub $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c3cb -+modsub $t2, $t3, $t4 :: rs 0x00000004 rt 0x40000000 out 0x00000004 -+modsub $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x80002414 -+modsub $t6, $t7, $t3 :: rs 0x76548000 rt 0x73468000 out 0x76548000 -+modsub $t5, $t3, $t2 :: rs 0x80000000 rt 0x80000000 out 0x80000000 -+modsub $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ff02 -+modsub $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7f00 -+modsub $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000c3cb -+modsub $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+modsub $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 -+modsub $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaaaa55 -+modsub $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0xffffffe3 -+modsub $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbababa0f -+modsub $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0f01e -+modsub $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 -+modsub $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x2353480b -+modsub $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x980b7c89 -+modsub $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0xffffff89 -+modsub $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x92784568 -+modsub $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcacac9ef -+modsub $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacaba00 -+modsub $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12faddd6 -+modsub $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7c000691 -+modsub $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffff00 -+modsub $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2f4de90 -+modsub $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x435f9082 -+modsub $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x2106ba4f -+modsub $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x246a6295 -+modsub $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1046a0f7 -+modsub $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x638ca423 -+modsub $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf63e7a0a -+modsub $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd6845ba -+-------- MTHLIP -------- -+mthlip :: acIn: 0xda3bacdc70974249 rsIn 0x00000000 posIn 0x00000007 acOut 0x7097424900000000 posOut 0x00000027 -+mthlip :: acIn: 0x2fff000000000001 rsIn 0xe87927cc posIn 0x00000002 acOut 0x00000001e87927cc posOut 0x00000022 -+mthlip :: acIn: 0x2fff000073741802 rsIn 0x083b3571 posIn 0x00000004 acOut 0x73741802083b3571 posOut 0x00000024 -+mthlip :: acIn: 0x2fff000080003403 rsIn 0xb9743941 posIn 0x0000000d acOut 0x80003403b9743941 posOut 0x0000002d -+mthlip :: acIn: 0xff46000073468004 rsIn 0xbce5f924 posIn 0x00000005 acOut 0x73468004bce5f924 posOut 0x00000025 -+mthlip :: acIn: 0x0000800080000000 rsIn 0xcc3c201c posIn 0x00000016 acOut 0x80000000cc3c201c posOut 0x00000036 -+mthlip :: acIn: 0x00010001ffffff07 rsIn 0x1ebaf88e posIn 0x0000001f acOut 0xffffff071ebaf88e posOut 0x0000003f -+mthlip :: acIn: 0x7fff7fff7fff7f07 rsIn 0x722d5e20 posIn 0x0000001c acOut 0x7fff7f07722d5e20 posOut 0x0000003c -+mthlip :: acIn: 0xffffffff00000505 rsIn 0xa1d6f791 posIn 0x00000000 acOut 0x00000505a1d6f791 posOut 0x00000020 -+mthlip :: acIn: 0xabababab00000000 rsIn 0x7b11bee7 posIn 0x0000001a acOut 0x000000007b11bee7 posOut 0x0000003a -+mthlip :: acIn: 0xdecadeca80000000 rsIn 0xa5631488 posIn 0x0000000c acOut 0x80000000a5631488 posOut 0x0000002c -+mthlip :: acIn: 0xbacabaca55555555 rsIn 0xb10bcc65 posIn 0x00000001 acOut 0x55555555b10bcc65 posOut 0x00000021 -+mthlip :: acIn: 0x3545ff80ffff2434 rsIn 0x73f39fca posIn 0x0000001f acOut 0xffff243473f39fca posOut 0x0000003f -+mthlip :: acIn: 0x734680bcabababa3 rsIn 0x5648e540 posIn 0x0000000b acOut 0xabababa35648e540 posOut 0x0000002b -+mthlip :: acIn: 0xc4dbfe20fc79b4d2 rsIn 0xc54f79e6 posIn 0x00000010 acOut 0xfc79b4d2c54f79e6 posOut 0x00000030 -+mthlip :: acIn: 0x0000000000000000 rsIn 0x5fc92974 posIn 0x0000001d acOut 0x000000005fc92974 posOut 0x0000003d -+mthlip :: acIn: 0x5555555500354561 rsIn 0x7e08184e posIn 0x0000000d acOut 0x003545617e08184e posOut 0x0000002d -+mthlip :: acIn: 0xad80bce400086755 rsIn 0x71c8315f posIn 0x00000008 acOut 0x0008675571c8315f posOut 0x00000028 -+mthlip :: acIn: 0x7f0032458f8f8f8f rsIn 0x9493110e posIn 0x00000007 acOut 0x8f8f8f8f9493110e posOut 0x00000027 -+mthlip :: acIn: 0x93474bdeeeeeeeee rsIn 0xbb246228 posIn 0x00000015 acOut 0xeeeeeeeebb246228 posOut 0x00000035 -+mthlip :: acIn: 0xf97343ff1bdbdbdb rsIn 0x339d8d88 posIn 0x00000004 acOut 0x1bdbdbdb339d8d88 posOut 0x00000024 -+mthlip :: acIn: 0x980b7cdedecadeca rsIn 0x70974249 posIn 0x00000020 acOut 0xdecadeca70974249 posOut 0x00000000 -+mthlip :: acIn: 0x0555adec93474bde rsIn 0x339d8d88 posIn 0x00000021 acOut 0x93474bde339d8d88 posOut 0x00000001 -+mthlip :: acIn: 0x000000000cd6b508 rsIn 0x12349876 posIn 0x0000000c acOut 0x0cd6b50812349876 posOut 0x0000002c -+mthlip :: acIn: 0x000000006731e282 rsIn 0x00354565 posIn 0x00000001 acOut 0x6731e28200354565 posOut 0x00000021 -+mthlip :: acIn: 0xffffffffb6edf28f rsIn 0x00086755 posIn 0x0000001f acOut 0xb6edf28f00086755 posOut 0x0000003f -+mthlip :: acIn: 0x000000004b4ec9ca rsIn 0x8f8f8f8f posIn 0x0000000b acOut 0x4b4ec9ca8f8f8f8f posOut 0x0000002b -+mthlip :: acIn: 0xffffffffc1037fa4 rsIn 0xeeeeeeee posIn 0x00000010 acOut 0xc1037fa4eeeeeeee posOut 0x00000030 -+mthlip :: acIn: 0xffffffffcb4ab48f rsIn 0x1bdbdbdb posIn 0x0000001d acOut 0xcb4ab48f1bdbdbdb posOut 0x0000003d -+mthlip :: acIn: 0xffffffffaf8f7e18 rsIn 0xbb246228 posIn 0x0000000d acOut 0xaf8f7e18bb246228 posOut 0x0000002d -+mthlip :: acIn: 0xffffffff87df4510 rsIn 0x339d8d88 posIn 0x00000008 acOut 0x87df4510339d8d88 posOut 0x00000028 -+mthlip :: acIn: 0xffffffffabf4e8e1 rsIn 0x70974249 posIn 0x00000007 acOut 0xabf4e8e170974249 posOut 0x00000027 -+mthlip :: acIn: 0xfffffffff4c0eeac rsIn 0x8a8d4e7d posIn 0x00000015 acOut 0xf4c0eeac8a8d4e7d posOut 0x00000035 -+mthlip :: acIn: 0x00000000006a54f2 rsIn 0xeb1b4335 posIn 0x00000004 acOut 0x006a54f2eb1b4335 posOut 0x00000024 -+mthlip :: acIn: 0x0000000079f74493 rsIn 0x0cd6b508 posIn 0x00000020 acOut 0x79f744930cd6b508 posOut 0x00000000 -+mthlip :: acIn: 0xffffffff9c09e313 rsIn 0x6731e282 posIn 0x00000021 acOut 0x9c09e3136731e282 posOut 0x00000001 -+-------- MULEQ_S.W.PHL -------- -+muleq_s.w.phl $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x7fffffff DSPCtrl 0x00200000 -+muleq_s.w.phl $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x06a8c93c DSPCtrl 0x00000000 -+muleq_s.w.phl $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x068d0000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 -+muleq_s.w.phl $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7ffe0002 DSPCtrl 0x00000000 -+muleq_s.w.phl $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x7fffffff DSPCtrl 0x00200000 -+muleq_s.w.phl $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xc71c38e4 DSPCtrl 0x00000000 -+muleq_s.w.phl $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x2da3f07c DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x006a42e0 DSPCtrl 0x00000000 -+muleq_s.w.phl $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x000ea05e DSPCtrl 0x00000000 -+muleq_s.w.phl $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfff980b0 DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0e9b7720 DSPCtrl 0x00000000 -+muleq_s.w.phl $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xf46b919c DSPCtrl 0x00000000 -+muleq_s.w.phl $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x11f51ec8 DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xefe1a2ac DSPCtrl 0x00000000 -+muleq_s.w.phl $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xfc200000 DSPCtrl 0x00000000 -+muleq_s.w.phl $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000002 DSPCtrl 0x00000000 -+muleq_s.w.phl $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x055f6d10 DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xd5a92622 DSPCtrl 0x00000000 -+muleq_s.w.phl $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xe101dc74 DSPCtrl 0x00000000 -+muleq_s.w.phl $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xe8170610 DSPCtrl 0x00000000 -+muleq_s.w.phl $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xfe91d900 DSPCtrl 0x00000000 -+muleq_s.w.phl $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x00526ff0 DSPCtrl 0x00000000 -+muleq_s.w.phl $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf6b3c7a4 DSPCtrl 0x00000000 -+muleq_s.w.phl $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x34021150 DSPCtrl 0x00000000 -+-------- MULEQ_S.W.PHR -------- -+muleq_s.w.phr $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x01e2f658 DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x0ebeddaa DSPCtrl 0x00000000 -+muleq_s.w.phr $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0xb3b8ae40 DSPCtrl 0x00000000 -+muleq_s.w.phr $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0xfffffffe DSPCtrl 0x00000000 -+muleq_s.w.phr $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7ffe0002 DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0xfd817d40 DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xc71c38e4 DSPCtrl 0x00000000 -+muleq_s.w.phr $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0006c9f0 DSPCtrl 0x00000000 -+muleq_s.w.phr $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x2da3f07c DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x08d8c9c0 DSPCtrl 0x00000000 -+muleq_s.w.phr $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x27458860 DSPCtrl 0x00000000 -+muleq_s.w.phr $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x64cd8f6c DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0xffeaead0 DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xf69eafe8 DSPCtrl 0x00000000 -+muleq_s.w.phr $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x0f06919c DSPCtrl 0x00000000 -+muleq_s.w.phr $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x11f51ec8 DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xec43b830 DSPCtrl 0x00000000 -+muleq_s.w.phr $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x0078f0e0 DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000002 DSPCtrl 0x00000000 -+muleq_s.w.phr $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x1360dca2 DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x9242b4e0 DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xda6e81e0 DSPCtrl 0x00000000 -+muleq_s.w.phr $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xee08b56c DSPCtrl 0x00000000 -+muleq_s.w.phr $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0cc64708 DSPCtrl 0x00000000 -+muleq_s.w.phr $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0xc3a9e3b4 DSPCtrl 0x00000000 -+muleq_s.w.phr $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x41b0384e DSPCtrl 0x00000000 -+muleq_s.w.phr $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xf039ea6e DSPCtrl 0x00000000 -+-------- MULEU_S.PH.QBL -------- -+muleu_s.ph.qbl $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x00000a18 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0xffff0000 DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xffff0000 DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ffff DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0xffff0000 DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0xaaaa8000 rt 0x55558000 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x073fffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x04c0ffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xffff0000 DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t0, $t1, $t2 :: rs 0xffffffff rt 0xcb4ab48f out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t2, $t3, $t4 :: rs 0xffffffff rt 0xaf8f7e18 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t4, $t1, $t5 :: rs 0xffffffff rt 0x87df4510 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t6, $t7, $t3 :: rs 0xffffffff rt 0xabf4e8e1 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t5, $t3, $t2 :: rs 0xffffffff rt 0xf4c0eeac out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbl $t2, $t4, $t8 :: rs 0x00000000 rt 0x006a54f2 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t0, $t8, $t0 :: rs 0x00000000 rt 0x79f74493 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbl $t4, $t6, $t1 :: rs 0xffffffff rt 0x9c09e313 out 0xffffffff DSPCtrl 0x00200000 -+-------- MULEU_S.PH.QBR -------- -+muleu_s.ph.qbr $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x0000ffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xffff0000 DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x0000ffff DSPCtrl 0x00000000 -+muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000aaa0 DSPCtrl 0x00000000 -+muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0xaaaa8000 rt 0x55558000 out 0xffff0000 DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x0ee8ffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x03e0ffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000ffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t0, $t1, $t2 :: rs 0xffffffff rt 0xcb4ab48f out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t2, $t3, $t4 :: rs 0xffffffff rt 0xaf8f7e18 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t4, $t1, $t5 :: rs 0xffffffff rt 0x87df4510 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t6, $t7, $t3 :: rs 0xffffffff rt 0xabf4e8e1 out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t5, $t3, $t2 :: rs 0xffffffff rt 0xf4c0eeac out 0xffffffff DSPCtrl 0x00200000 -+muleu_s.ph.qbr $t2, $t4, $t8 :: rs 0x00000000 rt 0x006a54f2 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbr $t0, $t8, $t0 :: rs 0x00000000 rt 0x79f74493 out 0x00000000 DSPCtrl 0x00000000 -+muleu_s.ph.qbr $t4, $t6, $t1 :: rs 0xffffffff rt 0x9c09e313 out 0xffffffff DSPCtrl 0x00200000 -+-------- MULQ_RS.PH -------- -+mulq_rs.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t3, $t4 :: rs 0x00045fb2 rt 0x00000286 out 0x000001e3 DSPCtrl 0x00000000 -+mulq_rs.ph $t4, $t1, $t5 :: rs 0x80002435 rt 0x80003421 out 0x7fff0ebf DSPCtrl 0x00200000 -+mulq_rs.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x06a9b3b9 DSPCtrl 0x00000000 -+mulq_rs.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x068d0000 DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t4, $t8 :: rs 0x00010001 rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+mulq_rs.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7ffe7ffe DSPCtrl 0x00000000 -+mulq_rs.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000fd81 DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x7fff0000 DSPCtrl 0x00200000 -+mulq_rs.ph $t4, $t1, $t5 :: rs 0xaaaa8000 rt 0x55558000 out 0xc71c7fff DSPCtrl 0x00200000 -+mulq_rs.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000007 DSPCtrl 0x00000000 -+mulq_rs.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x2da42da4 DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x006a08d9 DSPCtrl 0x00000000 -+mulq_rs.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+mulq_rs.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x000f2746 DSPCtrl 0x00000000 -+mulq_rs.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfffa64ce DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x0000ffeb DSPCtrl 0x00000000 -+mulq_rs.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x0e9bf69f DSPCtrl 0x00000000 -+mulq_rs.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xf46c0f07 DSPCtrl 0x00000000 -+mulq_rs.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x11f511f5 DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xefe2ec44 DSPCtrl 0x00000000 -+mulq_rs.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xfc200079 DSPCtrl 0x00000000 -+mulq_rs.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+mulq_rs.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x055f1361 DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0xd5a99243 DSPCtrl 0x00000000 -+mulq_rs.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xe102da6f DSPCtrl 0x00000000 -+mulq_rs.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0xe817ee09 DSPCtrl 0x00000000 -+mulq_rs.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xfe920cc6 DSPCtrl 0x00000000 -+mulq_rs.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x0052c3aa DSPCtrl 0x00000000 -+mulq_rs.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf6b441b0 DSPCtrl 0x00000000 -+mulq_rs.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x3402f03a DSPCtrl 0x00000000 -+-------- MULSAQ_S.W.PH -------- -+mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000000 outLO 0x00000006 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0xb1412255 dspCtrl 0x00020000 -+mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x6a902df0 dspCtrl 0x00080000 -+mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x80000000 dspCtrl 0x00010000 -+mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffffff dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xffffffff dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x125cb3e6 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x00000000 outLO 0x7fff2434 dspCtrl 0x00040000 -+mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xffffffff outLO 0xabababab dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc72eae2 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x00000000 outLO 0x00000000 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xf7917920 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0xffffffff outLO 0xd8fe5d63 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xffffffff outLO 0x9b345899 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xffffffff outLO 0x8fa4a4bf dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x00000000 outLO 0x06ebb626 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x00000000 outLO 0x0140dbdb dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xdecadeca dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x96e5365a dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf666bb1a dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b3571 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xdabe1df1 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xdd1e556e dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xb6f45628 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xffffffff outLO 0xf366982e dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x00000000 outLO 0x363ce1b2 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0xffffffff outLO 0xbfdee1b7 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x00000000 outLO 0xbaf2715f dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xffffffff outLO 0x6c0fddbc dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xffffffff outLO 0xbae0d887 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xffffffff outLO 0xdec3fc2a dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x00000000 outLO 0x7dbe3406 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0xffffffff outLO 0xe13b3d06 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x00000000 outLO 0xe4772016 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x00000000 outLO 0x7e976f58 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0xffffffff outLO 0xd390110e dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xffffffff outLO 0xca4ba856 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffffff outLO 0xb39e2e6b dspCtrl 0x00040000 -+mulsaq_s.w.ph $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0xed3d0cd3 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x7f49c201 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0xffffffff outLO 0xdec965f8 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x2fddae54 dspCtrl 0x00000000 -+mulsaq_s.w.ph $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0x36eeba7e dspCtrl 0x00020000 -+-------- MULT -------- -+mult $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0x00000000 outLO 0x00000000 -+mult $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000000 -+mult $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x3fffd3d5 outLO 0x075f6ed5 -+mult $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0x40000000 -+mult $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000000 -+mult $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0xfffeffff -+mult $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010001 -+mult $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0415bea0 -+mult $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x00000000 -+mult $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x40000000 outLO 0x00000000 -+mult $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0xe38e38e3 outLO 0x71c71c72 -+mult $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xffeb64f8 -+mult $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x16d18c47 outLO 0x6db2f83e -+mult $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0x0035137b outLO 0x307e64e0 -+mult $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x00000000 -+mult $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x6191c430 -+mult $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0xfffc9666 outLO 0x01fdc7b6 -+mult $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0xfffffff5 outLO 0x75757568 -+mult $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x074d50a5 outLO 0x552957f4 -+mult $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0xfa35b12c outLO 0xbfc448ce -+mult $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0x08fa3aed outLO 0xc1568f64 -+mult $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xf7f07861 outLO 0x14b7dc18 -+mult $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xfe1003c1 outLO 0x443c7870 -+mult $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x00000001 -+mult $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0xc1021d80 -+mult $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0x07e4ad9d outLO 0xb2e5c69a -+mult $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xfcef12ea outLO 0x8260e7b8 -+mult $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0xde8dfafd outLO 0x28a5f0b0 -+mult $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0xd80a3262 outLO 0x5832272f -+mult $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x0d7a3e4f outLO 0xc0a2ad20 -+mult $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0xf2bf4270 outLO 0x4faafb78 -+mult $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0xe71bb44a outLO 0xab1b6208 -+mult $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0xef63cb0b outLO 0xd35902bc -+mult $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0xd1d700c6 outLO 0x0930de49 -+mult $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0x0528cc22 outLO 0x06a645b5 -+mult $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdd outLO 0x0ff97100 -+mult $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda7 outLO 0xa78d1d7e -+mult $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0xfffffe7a outLO 0x62be547b -+mult $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x00000000 -+mult $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x1f7e402e outLO 0x00000000 -+mult $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0xee6e3c2f outLO 0xbc3c6e7b -+mult $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0x00002838 outLO 0x40000000 -+mult $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x27924fa6 outLO 0xb6f4d1b0 -+mult $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0x012837c1 outLO 0xd0fe3c92 -+mult $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0x00000000 outLO 0x00000000 -+mult $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x68f2bd7a -+mult $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x2048e9cf -+mult $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x000031fb outLO 0x40000000 -+-------- MULTU -------- -+multu $ac3, $t4, $t5 :: rs 0x00000000 rt 0x00000000 inHI 0xffffffff inLO 0x80000000 outHI 0x00000000 outLO 0x00000000 -+multu $ac0, $t0, $t1 :: rs 0x00000004 rt 0x40000000 inHI 0x00000000 inLO 0x00000006 outHI 0x00000001 outLO 0x00000000 -+multu $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x40002c2b outLO 0x075f6ed5 -+multu $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x35488bc5 outLO 0x40000000 -+multu $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x40000000 outLO 0x00000000 -+multu $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00010000 outLO 0xfffeffff -+multu $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0x3fff7fff outLO 0x40010001 -+multu $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0415bea0 -+multu $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x00000000 -+multu $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0x40000000 outLO 0x00000000 -+multu $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x38e38e38 outLO 0x71c71c72 -+multu $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0x00000017 outLO 0xffeb64f8 -+multu $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0x7d37f2ac outLO 0x6db2f83e -+multu $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xed9fb93d outLO 0x307e64e0 -+multu $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x00000000 -+multu $ac0, $t0, $t1 :: rs 0x23534870 rt 0x00354565 inHI 0x00000000 inLO 0x00354565 outHI 0x000759d1 outLO 0x6191c430 -+multu $ac1, $t2, $t3 :: rs 0x980b7cde rt 0x00086755 inHI 0x00000000 inLO 0x00086755 outHI 0x0004fdbb outLO 0x01fdc7b6 -+multu $ac2, $t4, $t1 :: rs 0x00000018 rt 0x8f8f8f8f inHI 0xffffffff inLO 0x8f8f8f8f outHI 0x0000000d outLO 0x75757568 -+multu $ac3, $t6, $t7 :: rs 0x92784656 rt 0xeeeeeeee inHI 0xffffffff inLO 0xeeeeeeee outHI 0x88b485e9 outLO 0x552957f4 -+multu $ac0, $t5, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb inHI 0x00000000 inLO 0x1bdbdbdb outHI 0x16118d07 outLO 0xbfc448ce -+multu $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xa28fd481 outLO 0xc1568f64 -+multu $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0x0aeb5715 outLO 0x14b7dc18 -+multu $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0x7a100b51 outLO 0x443c7870 -+multu $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0xfffffffe outLO 0x00000001 -+multu $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0x0c593e82 outLO 0xc1021d80 -+multu $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xaac61642 outLO 0xb2e5c69a -+multu $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0x5cb83c5e outLO 0x8260e7b8 -+multu $ac3, $t6, $t7 :: rs 0xbc1083e8 rt 0x7e08184e inHI 0x00000000 inLO 0x1ebaf88e outHI 0x5c96134b outLO 0x28a5f0b0 -+multu $ac0, $t5, $t3 :: rs 0xa617cc31 rt 0x71c8315f inHI 0x00000000 inLO 0x722d5e20 outHI 0x49d263c1 outLO 0x5832272f -+multu $ac1, $t2, $t4 :: rs 0xdfe1e8f0 rt 0x9493110e inHI 0xffffffff inLO 0xa1d6f791 outHI 0x81ef384d outLO 0xc0a2ad20 -+multu $ac2, $t0, $t8 :: rs 0x31458a23 rt 0xbb246228 inHI 0x00000000 inLO 0x7b11bee7 outHI 0x2404cc93 outLO 0x4faafb78 -+multu $ac3, $t4, $t5 :: rs 0x848af791 rt 0x339d8d88 inHI 0xffffffff inLO 0xa5631488 outHI 0x1ab941d2 outLO 0xab1b6208 -+multu $ac0, $t0, $t1 :: rs 0xda3bacdc rt 0x70974249 inHI 0xffffffff inLO 0xb10bcc65 outHI 0x5ffb0d54 outLO 0xd35902bc -+multu $ac1, $t2, $t3 :: rs 0x649d5cbd rt 0x8a8d4e7d inHI 0x00000000 inLO 0x73f39fca outHI 0x36745d83 outLO 0x0930de49 -+multu $ac2, $t4, $t1 :: rs 0xc0c8c881 rt 0xeb1b4335 inHI 0x00000000 inLO 0x5648e540 outHI 0xb10cd7d8 outLO 0x06a645b5 -+multu $ac3, $t6, $t7 :: rs 0x7dd81a20 rt 0x0cd6b508 inHI 0xffffffff inLO 0xc54f79e6 outHI 0x064facdd outLO 0x0ff97100 -+multu $ac0, $t5, $t3 :: rs 0x7fff7fff rt 0x6731e282 inHI 0x00000000 inLO 0x5fc92974 outHI 0x3398bda7 outLO 0xa78d1d7e -+multu $ac1, $t2, $t4 :: rs 0x00000555 rt 0xb6edf28f inHI 0x00000000 inLO 0x7e08184e outHI 0x000003cf outLO 0x62be547b -+multu $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x00000000 -+multu $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x6081bfd2 outLO 0x00000000 -+multu $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x43c39184 outLO 0xbc3c6e7b -+multu $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xaf8f2838 outLO 0x40000000 -+multu $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x5b1d4061 outLO 0xb6f4d1b0 -+multu $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xa996d574 outLO 0xd0fe3c92 -+multu $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0x00000000 outLO 0x00000000 -+multu $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00001620 outLO 0x68f2bd7a -+multu $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x000400f5 outLO 0x2048e9cf -+multu $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0x9c0931fb outLO 0x40000000 -+-------- PACKRL.PH -------- -+packrl.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+packrl.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0xb2320002 -+packrl.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x3435fabc -+packrl.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x4cb87346 -+packrl.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x437b8000 -+packrl.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x0001ff01 -+packrl.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff -+packrl.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0xc4200000 -+packrl.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+packrl.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00008000 -+packrl.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaa5555 -+packrl.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0018ffff -+packrl.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabaabab -+packrl.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0fc79 -+packrl.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x39760000 -+packrl.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x48700035 -+packrl.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x7cde0008 -+packrl.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00188f8f -+packrl.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x4656eeee -+packrl.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcaca1bdb -+packrl.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacadeca -+packrl.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0xdeb49347 -+packrl.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x0790fc00 -+packrl.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff -+packrl.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xdf1fcb4a -+packrl.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x909aaf8f -+packrl.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0xba5f87df -+packrl.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x6376abf4 -+packrl.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0xa1a3f4c0 -+packrl.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0xa515006a -+packrl.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7a9d79f7 -+packrl.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x45cd9c09 -+-------- PICK.QB -------- -+pick.qb $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0xf973437b rt 0x807343bc out 0x807343bc DSPCtrl1 0x0 -+pick.qb $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x00ff0001 rt 0x00ff0001 out 0x00ff0001 DSPCtrl1 0x3000000 -+pick.qb $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 -+pick.qb $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x0000c420 rt 0x00000555 out 0x0000c455 DSPCtrl1 0x2000000 -+pick.qb $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 -+pick.qb $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 -+pick.qb $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x0 -+pick.qb $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x00000520 DSPCtrl1 0x1000000 -+pick.qb $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 -+pick.qb $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 -+pick.qb $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 -+pick.qb $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x0000c420 DSPCtrl1 0x3000000 -+pick.qb $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eeac DSPCtrl1 0x0 -+pick.qb $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x638ca515 rt 0x006a54f2 out 0x006a54f2 DSPCtrl1 0x0 -+pick.qb $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xf63e7a9d rt 0x79f74493 out 0x79f74493 DSPCtrl1 0x0 -+pick.qb $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 -+pick.qb $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eea3 DSPCtrl1 0x1000000 -+pick.qb $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006a5415 DSPCtrl1 0x1000000 -+pick.qb $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0x79f77a93 DSPCtrl1 0x2000000 -+pick.qb $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 -+pick.qb $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eea3 DSPCtrl1 0x1000000 -+pick.qb $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006a5415 DSPCtrl1 0x1000000 -+pick.qb $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0x79f77a93 DSPCtrl1 0x2000000 -+pick.qb $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 -+pick.qb $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x92784656 rt 0xeeeeeeee out 0xeeeeeeee DSPCtrl1 0x0 -+pick.qb $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbdbdb DSPCtrl1 0x0 -+pick.qb $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xbacabaca rt 0xdecadeca out 0xdecadeca DSPCtrl1 0x0 -+pick.qb $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x12fadeb4 rt 0x93474bde out 0x93474bde DSPCtrl1 0x0 -+pick.qb $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0xeeee46ee DSPCtrl1 0x2000000 -+pick.qb $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbcaca DSPCtrl1 0x3000000 -+pick.qb $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xdecabaca DSPCtrl1 0x3000000 -+pick.qb $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x93474bb4 DSPCtrl1 0x1000000 -+pick.qb $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0xeeee46ee DSPCtrl1 0x2000000 -+pick.qb $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbcaca DSPCtrl1 0x3000000 -+pick.qb $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xdecabaca DSPCtrl1 0x3000000 -+pick.qb $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x93474bb4 DSPCtrl1 0x1000000 -+-------- PRECEQ.W.PHL -------- -+preceq.w.phl $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+preceq.w.phl $t2, $t3 :: rd 0x80000000 rt 0x80003286 -+preceq.w.phl $t4, $t1 :: rd 0xfabc0000 rt 0xfabc2435 -+preceq.w.phl $t6, $t7 :: rd 0x73460000 rt 0x73468000 -+preceq.w.phl $t5, $t3 :: rd 0x80000000 rt 0x80000000 -+preceq.w.phl $t2, $t4 :: rd 0xffff0000 rt 0xffffffff -+preceq.w.phl $t0, $t8 :: rd 0xfff40000 rt 0xfff45fff -+preceq.w.phl $t4, $t4 :: rd 0x00000000 rt 0x00000555 -+preceq.w.phl $t0, $t1 :: rd 0x00000000 rt 0x00005340 -+preceq.w.phl $t2, $t3 :: rd 0x80000000 rt 0x80000000 -+preceq.w.phl $t4, $t1 :: rd 0x55550000 rt 0x55555555 -+preceq.w.phl $t6, $t7 :: rd 0xffff0000 rt 0xffff2435 -+preceq.w.phl $t5, $t3 :: rd 0xabab0000 rt 0xabababab -+preceq.w.phl $t2, $t4 :: rd 0xfc790000 rt 0xfc79b4d2 -+preceq.w.phl $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+preceq.w.phl $t4, $t4 :: rd 0x00350000 rt 0x00354565 -+preceq.w.phl $t0, $t1 :: rd 0x00080000 rt 0x00086755 -+preceq.w.phl $t2, $t3 :: rd 0x8f8f0000 rt 0x8f8f8f8f -+preceq.w.phl $t4, $t1 :: rd 0xeeee0000 rt 0xeeeeeeee -+preceq.w.phl $t6, $t7 :: rd 0x1bdb0000 rt 0x1bdbdbdb -+preceq.w.phl $t5, $t3 :: rd 0xdeca0000 rt 0xdecadeca -+preceq.w.phl $t2, $t4 :: rd 0x93470000 rt 0x93474bde -+preceq.w.phl $t0, $t8 :: rd 0xfc000000 rt 0xfc0007ff -+preceq.w.phl $t4, $t4 :: rd 0xffff0000 rt 0xffffffff -+preceq.w.phl $t0, $t1 :: rd 0xcb4a0000 rt 0xcb4ab48f -+preceq.w.phl $t2, $t3 :: rd 0xaf8f0000 rt 0xaf8f7e18 -+preceq.w.phl $t4, $t1 :: rd 0x87df0000 rt 0x87df4510 -+preceq.w.phl $t6, $t7 :: rd 0xabf40000 rt 0xabf4e8e1 -+preceq.w.phl $t5, $t3 :: rd 0xf4c00000 rt 0xf4c0eeac -+preceq.w.phl $t2, $t4 :: rd 0x006a0000 rt 0x006a54f2 -+preceq.w.phl $t0, $t8 :: rd 0x79f70000 rt 0x79f74493 -+preceq.w.phl $t4, $t4 :: rd 0x9c090000 rt 0x9c09e313 -+-------- PICK.PH -------- -+pick.ph $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0xf973437b rt 0x807343bc out 0x807343bc DSPCtrl1 0x0 -+pick.ph $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x00ff0001 rt 0x00ff0001 out 0x00ff0001 DSPCtrl1 0x3000000 -+pick.ph $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 -+pick.ph $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x0000c420 rt 0x00000555 out 0x00000555 DSPCtrl1 0x2000000 -+pick.ph $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 -+pick.ph $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 -+pick.ph $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x0 -+pick.ph $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x0000c420 DSPCtrl1 0x1000000 -+pick.ph $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0xf973437b rt 0x807342bc out 0x807342bc DSPCtrl1 0x0 -+pick.ph $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x00ff0001 rt 0xff0100ff out 0xff010001 DSPCtrl1 0x1000000 -+pick.ph $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff DSPCtrl1 0x3000000 -+pick.ph $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x0000c420 rt 0x00000555 out 0x0000c420 DSPCtrl1 0x3000000 -+pick.ph $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0eeac DSPCtrl1 0x0 -+pick.ph $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0x638ca515 rt 0x006a54f2 out 0x006a54f2 DSPCtrl1 0x0 -+pick.ph $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xf63e7a9d rt 0x79f74493 out 0x79f74493 DSPCtrl1 0x0 -+pick.ph $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 -+pick.ph $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0a1a3 DSPCtrl1 0x1000000 -+pick.ph $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006aa515 DSPCtrl1 0x1000000 -+pick.ph $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0xf63e4493 DSPCtrl1 0x2000000 -+pick.ph $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 -+pick.ph $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x1046a1a3 rt 0xf4c0eeac out 0xf4c0a1a3 DSPCtrl1 0x1000000 -+pick.ph $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0x638ca515 rt 0x006a54f2 out 0x006aa515 DSPCtrl1 0x1000000 -+pick.ph $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xf63e7a9d rt 0x79f74493 out 0xf63e4493 DSPCtrl1 0x2000000 -+pick.ph $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0xbd6845cd rt 0x9c09e313 out 0x9c09e313 DSPCtrl1 0x0 -+pick.ph $t5, $t3, $t2 :: cmp.eq.ph $t3, $t2 rs 0x92784656 rt 0xeeeeeeee out 0xeeeeeeee DSPCtrl1 0x0 -+pick.ph $t2, $t4, $t8 :: cmp.eq.ph $t4, $t8 rs 0xcacacaca rt 0x1bdbdbdb out 0x1bdbdbdb DSPCtrl1 0x0 -+pick.ph $t3, $t8, $t0 :: cmp.eq.ph $t8, $t0 rs 0xbacabaca rt 0xdecadeca out 0xdecadeca DSPCtrl1 0x0 -+pick.ph $t4, $t6, $t1 :: cmp.eq.ph $t6, $t1 rs 0x12fadeb4 rt 0x93474bde out 0x93474bde DSPCtrl1 0x0 -+pick.ph $t2, $t3, $t4 :: cmp.lt.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0x9278eeee DSPCtrl1 0x2000000 -+pick.ph $t4, $t1, $t5 :: cmp.lt.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0xcacacaca DSPCtrl1 0x3000000 -+pick.ph $t6, $t7, $t3 :: cmp.lt.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xbacabaca DSPCtrl1 0x3000000 -+pick.ph $t0, $t1, $t2 :: cmp.lt.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x9347deb4 DSPCtrl1 0x1000000 -+pick.ph $t2, $t3, $t4 :: cmp.le.ph $t3, $t4 rs 0x92784656 rt 0xeeeeeeee out 0x9278eeee DSPCtrl1 0x2000000 -+pick.ph $t4, $t1, $t5 :: cmp.le.ph $t1, $t5 rs 0xcacacaca rt 0x1bdbdbdb out 0xcacacaca DSPCtrl1 0x3000000 -+pick.ph $t6, $t7, $t3 :: cmp.le.ph $t7, $t3 rs 0xbacabaca rt 0xdecadeca out 0xbacabaca DSPCtrl1 0x3000000 -+pick.ph $t0, $t1, $t2 :: cmp.le.ph $t1, $t2 rs 0x12fadeb4 rt 0x93474bde out 0x9347deb4 DSPCtrl1 0x1000000 -+-------- PRECEQ.W.PHR -------- -+preceq.w.phr $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+preceq.w.phr $t2, $t3 :: rd 0x32860000 rt 0x80003286 -+preceq.w.phr $t4, $t1 :: rd 0x24350000 rt 0xfabc2435 -+preceq.w.phr $t6, $t7 :: rd 0x80000000 rt 0x73468000 -+preceq.w.phr $t5, $t3 :: rd 0x00000000 rt 0x80000000 -+preceq.w.phr $t2, $t4 :: rd 0xffff0000 rt 0xffffffff -+preceq.w.phr $t0, $t8 :: rd 0x5fff0000 rt 0xfff45fff -+preceq.w.phr $t4, $t4 :: rd 0x05550000 rt 0x00000555 -+preceq.w.phr $t0, $t1 :: rd 0x53400000 rt 0x00005340 -+preceq.w.phr $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+preceq.w.phr $t4, $t1 :: rd 0x55550000 rt 0x55555555 -+preceq.w.phr $t6, $t7 :: rd 0x24350000 rt 0xffff2435 -+preceq.w.phr $t5, $t3 :: rd 0xabab0000 rt 0xabababab -+preceq.w.phr $t2, $t4 :: rd 0xb4d20000 rt 0xfc79b4d2 -+preceq.w.phr $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+preceq.w.phr $t4, $t4 :: rd 0x45650000 rt 0x00354565 -+preceq.w.phr $t0, $t1 :: rd 0x67550000 rt 0x00086755 -+preceq.w.phr $t2, $t3 :: rd 0x8f8f0000 rt 0x8f8f8f8f -+preceq.w.phr $t4, $t1 :: rd 0xeeee0000 rt 0xeeeeeeee -+preceq.w.phr $t6, $t7 :: rd 0xdbdb0000 rt 0x1bdbdbdb -+preceq.w.phr $t5, $t3 :: rd 0xdeca0000 rt 0xdecadeca -+preceq.w.phr $t2, $t4 :: rd 0x4bde0000 rt 0x93474bde -+preceq.w.phr $t0, $t8 :: rd 0x07ff0000 rt 0xfc0007ff -+preceq.w.phr $t4, $t4 :: rd 0xffff0000 rt 0xffffffff -+preceq.w.phr $t0, $t1 :: rd 0xb48f0000 rt 0xcb4ab48f -+preceq.w.phr $t2, $t3 :: rd 0x7e180000 rt 0xaf8f7e18 -+preceq.w.phr $t4, $t1 :: rd 0x45100000 rt 0x87df4510 -+preceq.w.phr $t6, $t7 :: rd 0xe8e10000 rt 0xabf4e8e1 -+preceq.w.phr $t5, $t3 :: rd 0xeeac0000 rt 0xf4c0eeac -+preceq.w.phr $t2, $t4 :: rd 0x54f20000 rt 0x006a54f2 -+preceq.w.phr $t0, $t8 :: rd 0x44930000 rt 0x79f74493 -+preceq.w.phr $t4, $t4 :: rd 0xe3130000 rt 0x9c09e313 -+-------- PRECEQU.PH.QBL -------- -+precequ.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbl $t2, $t3 :: rd 0x40000000 rt 0x80003286 -+precequ.ph.qbl $t4, $t1 :: rd 0x7d005e00 rt 0xfabc2435 -+precequ.ph.qbl $t6, $t7 :: rd 0x39802300 rt 0x73468000 -+precequ.ph.qbl $t5, $t3 :: rd 0x40000000 rt 0x80000000 -+precequ.ph.qbl $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbl $t0, $t8 :: rd 0x7f807a00 rt 0xfff45fff -+precequ.ph.qbl $t4, $t4 :: rd 0x00000000 rt 0x00000555 -+precequ.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00005340 -+precequ.ph.qbl $t2, $t3 :: rd 0x40000000 rt 0x80000000 -+precequ.ph.qbl $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 -+precequ.ph.qbl $t6, $t7 :: rd 0x7f807f80 rt 0xffff2435 -+precequ.ph.qbl $t5, $t3 :: rd 0x55805580 rt 0xabababab -+precequ.ph.qbl $t2, $t4 :: rd 0x7e003c80 rt 0xfc79b4d2 -+precequ.ph.qbl $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbl $t4, $t4 :: rd 0x00001a80 rt 0x00354565 -+precequ.ph.qbl $t0, $t1 :: rd 0x00000400 rt 0x00086755 -+precequ.ph.qbl $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f -+precequ.ph.qbl $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee -+precequ.ph.qbl $t6, $t7 :: rd 0x0d806d80 rt 0x1bdbdbdb -+precequ.ph.qbl $t5, $t3 :: rd 0x6f006500 rt 0xdecadeca -+precequ.ph.qbl $t2, $t4 :: rd 0x49802380 rt 0x93474bde -+precequ.ph.qbl $t0, $t8 :: rd 0x7e000000 rt 0xfc0007ff -+precequ.ph.qbl $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbl $t0, $t1 :: rd 0x65802500 rt 0xcb4ab48f -+precequ.ph.qbl $t2, $t3 :: rd 0x57804780 rt 0xaf8f7e18 -+precequ.ph.qbl $t4, $t1 :: rd 0x43806f80 rt 0x87df4510 -+precequ.ph.qbl $t6, $t7 :: rd 0x55807a00 rt 0xabf4e8e1 -+precequ.ph.qbl $t5, $t3 :: rd 0x7a006000 rt 0xf4c0eeac -+precequ.ph.qbl $t2, $t4 :: rd 0x00003500 rt 0x006a54f2 -+precequ.ph.qbl $t0, $t8 :: rd 0x3c807b80 rt 0x79f74493 -+precequ.ph.qbl $t4, $t4 :: rd 0x4e000480 rt 0x9c09e313 -+-------- PRECEQU.PH.QBLA -------- -+precequ.ph.qbla $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbla $t2, $t3 :: rd 0x40001900 rt 0x80003286 -+precequ.ph.qbla $t4, $t1 :: rd 0x7d001200 rt 0xfabc2435 -+precequ.ph.qbla $t6, $t7 :: rd 0x39804000 rt 0x73468000 -+precequ.ph.qbla $t5, $t3 :: rd 0x40000000 rt 0x80000000 -+precequ.ph.qbla $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbla $t0, $t8 :: rd 0x7f802f80 rt 0xfff45fff -+precequ.ph.qbla $t4, $t4 :: rd 0x00000280 rt 0x00000555 -+precequ.ph.qbla $t0, $t1 :: rd 0x00002980 rt 0x00005340 -+precequ.ph.qbla $t2, $t3 :: rd 0x40000000 rt 0x80000000 -+precequ.ph.qbla $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 -+precequ.ph.qbla $t6, $t7 :: rd 0x7f801200 rt 0xffff2435 -+precequ.ph.qbla $t5, $t3 :: rd 0x55805580 rt 0xabababab -+precequ.ph.qbla $t2, $t4 :: rd 0x7e005a00 rt 0xfc79b4d2 -+precequ.ph.qbla $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbla $t4, $t4 :: rd 0x00002280 rt 0x00354565 -+precequ.ph.qbla $t0, $t1 :: rd 0x00003380 rt 0x00086755 -+precequ.ph.qbla $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f -+precequ.ph.qbla $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee -+precequ.ph.qbla $t6, $t7 :: rd 0x0d806d80 rt 0x1bdbdbdb -+precequ.ph.qbla $t5, $t3 :: rd 0x6f006f00 rt 0xdecadeca -+precequ.ph.qbla $t2, $t4 :: rd 0x49802580 rt 0x93474bde -+precequ.ph.qbla $t0, $t8 :: rd 0x7e000380 rt 0xfc0007ff -+precequ.ph.qbla $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbla $t0, $t1 :: rd 0x65805a00 rt 0xcb4ab48f -+precequ.ph.qbla $t2, $t3 :: rd 0x57803f00 rt 0xaf8f7e18 -+precequ.ph.qbla $t4, $t1 :: rd 0x43802280 rt 0x87df4510 -+precequ.ph.qbla $t6, $t7 :: rd 0x55807400 rt 0xabf4e8e1 -+precequ.ph.qbla $t5, $t3 :: rd 0x7a007700 rt 0xf4c0eeac -+precequ.ph.qbla $t2, $t4 :: rd 0x00002a00 rt 0x006a54f2 -+precequ.ph.qbla $t0, $t8 :: rd 0x3c802200 rt 0x79f74493 -+precequ.ph.qbla $t4, $t4 :: rd 0x4e007180 rt 0x9c09e313 -+-------- PRECEQU.PH.QBR -------- -+precequ.ph.qbr $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbr $t2, $t3 :: rd 0x19004300 rt 0x80003286 -+precequ.ph.qbr $t4, $t1 :: rd 0x12001a80 rt 0xfabc2435 -+precequ.ph.qbr $t6, $t7 :: rd 0x40000000 rt 0x73468000 -+precequ.ph.qbr $t5, $t3 :: rd 0x00000000 rt 0x80000000 -+precequ.ph.qbr $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbr $t0, $t8 :: rd 0x2f807f80 rt 0xfff45fff -+precequ.ph.qbr $t4, $t4 :: rd 0x02802a80 rt 0x00000555 -+precequ.ph.qbr $t0, $t1 :: rd 0x29802000 rt 0x00005340 -+precequ.ph.qbr $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+precequ.ph.qbr $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 -+precequ.ph.qbr $t6, $t7 :: rd 0x12001a80 rt 0xffff2435 -+precequ.ph.qbr $t5, $t3 :: rd 0x55805580 rt 0xabababab -+precequ.ph.qbr $t2, $t4 :: rd 0x5a006900 rt 0xfc79b4d2 -+precequ.ph.qbr $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbr $t4, $t4 :: rd 0x22803280 rt 0x00354565 -+precequ.ph.qbr $t0, $t1 :: rd 0x33802a80 rt 0x00086755 -+precequ.ph.qbr $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f -+precequ.ph.qbr $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee -+precequ.ph.qbr $t6, $t7 :: rd 0x6d806d80 rt 0x1bdbdbdb -+precequ.ph.qbr $t5, $t3 :: rd 0x6f006500 rt 0xdecadeca -+precequ.ph.qbr $t2, $t4 :: rd 0x25806f00 rt 0x93474bde -+precequ.ph.qbr $t0, $t8 :: rd 0x03807f80 rt 0xfc0007ff -+precequ.ph.qbr $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbr $t0, $t1 :: rd 0x5a004780 rt 0xcb4ab48f -+precequ.ph.qbr $t2, $t3 :: rd 0x3f000c00 rt 0xaf8f7e18 -+precequ.ph.qbr $t4, $t1 :: rd 0x22800800 rt 0x87df4510 -+precequ.ph.qbr $t6, $t7 :: rd 0x74007080 rt 0xabf4e8e1 -+precequ.ph.qbr $t5, $t3 :: rd 0x77005600 rt 0xf4c0eeac -+precequ.ph.qbr $t2, $t4 :: rd 0x2a007900 rt 0x006a54f2 -+precequ.ph.qbr $t0, $t8 :: rd 0x22004980 rt 0x79f74493 -+precequ.ph.qbr $t4, $t4 :: rd 0x71800980 rt 0x9c09e313 -+-------- PRECEQU.PH.QBRA -------- -+precequ.ph.qbra $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbra $t2, $t3 :: rd 0x00004300 rt 0x80003286 -+precequ.ph.qbra $t4, $t1 :: rd 0x5e001a80 rt 0xfabc2435 -+precequ.ph.qbra $t6, $t7 :: rd 0x23000000 rt 0x73468000 -+precequ.ph.qbra $t5, $t3 :: rd 0x00000000 rt 0x80000000 -+precequ.ph.qbra $t2, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbra $t0, $t8 :: rd 0x7a007f80 rt 0xfff45fff -+precequ.ph.qbra $t4, $t4 :: rd 0x00002a80 rt 0x00000555 -+precequ.ph.qbra $t0, $t1 :: rd 0x00002000 rt 0x00005340 -+precequ.ph.qbra $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+precequ.ph.qbra $t4, $t1 :: rd 0x2a802a80 rt 0x55555555 -+precequ.ph.qbra $t6, $t7 :: rd 0x7f801a80 rt 0xffff2435 -+precequ.ph.qbra $t5, $t3 :: rd 0x55805580 rt 0xabababab -+precequ.ph.qbra $t2, $t4 :: rd 0x3c806900 rt 0xfc79b4d2 -+precequ.ph.qbra $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+precequ.ph.qbra $t4, $t4 :: rd 0x1a803280 rt 0x00354565 -+precequ.ph.qbra $t0, $t1 :: rd 0x04002a80 rt 0x00086755 -+precequ.ph.qbra $t2, $t3 :: rd 0x47804780 rt 0x8f8f8f8f -+precequ.ph.qbra $t4, $t1 :: rd 0x77007700 rt 0xeeeeeeee -+precequ.ph.qbra $t6, $t7 :: rd 0x6d806d80 rt 0x1bdbdbdb -+precequ.ph.qbra $t5, $t3 :: rd 0x65006500 rt 0xdecadeca -+precequ.ph.qbra $t2, $t4 :: rd 0x23806f00 rt 0x93474bde -+precequ.ph.qbra $t0, $t8 :: rd 0x00007f80 rt 0xfc0007ff -+precequ.ph.qbra $t4, $t4 :: rd 0x7f807f80 rt 0xffffffff -+precequ.ph.qbra $t0, $t1 :: rd 0x25004780 rt 0xcb4ab48f -+precequ.ph.qbra $t2, $t3 :: rd 0x47800c00 rt 0xaf8f7e18 -+precequ.ph.qbra $t4, $t1 :: rd 0x6f800800 rt 0x87df4510 -+precequ.ph.qbra $t6, $t7 :: rd 0x7a007080 rt 0xabf4e8e1 -+precequ.ph.qbra $t5, $t3 :: rd 0x60005600 rt 0xf4c0eeac -+precequ.ph.qbra $t2, $t4 :: rd 0x35007900 rt 0x006a54f2 -+precequ.ph.qbra $t0, $t8 :: rd 0x7b804980 rt 0x79f74493 -+precequ.ph.qbra $t4, $t4 :: rd 0x04800980 rt 0x9c09e313 -+-------- PRECEU.PH.QBL -------- -+preceu.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbl $t2, $t3 :: rd 0x00800000 rt 0x80003286 -+preceu.ph.qbl $t4, $t1 :: rd 0x00fa00bc rt 0xfabc2435 -+preceu.ph.qbl $t6, $t7 :: rd 0x00730046 rt 0x73468000 -+preceu.ph.qbl $t5, $t3 :: rd 0x00800000 rt 0x80000000 -+preceu.ph.qbl $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbl $t0, $t8 :: rd 0x00ff00f4 rt 0xfff45fff -+preceu.ph.qbl $t4, $t4 :: rd 0x00000000 rt 0x00000555 -+preceu.ph.qbl $t0, $t1 :: rd 0x00000000 rt 0x00005340 -+preceu.ph.qbl $t2, $t3 :: rd 0x00800000 rt 0x80000000 -+preceu.ph.qbl $t4, $t1 :: rd 0x00550055 rt 0x55555555 -+preceu.ph.qbl $t6, $t7 :: rd 0x00ff00ff rt 0xffff2435 -+preceu.ph.qbl $t5, $t3 :: rd 0x00ab00ab rt 0xabababab -+preceu.ph.qbl $t2, $t4 :: rd 0x00fc0079 rt 0xfc79b4d2 -+preceu.ph.qbl $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbl $t4, $t4 :: rd 0x00000035 rt 0x00354565 -+preceu.ph.qbl $t0, $t1 :: rd 0x00000008 rt 0x00086755 -+preceu.ph.qbl $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f -+preceu.ph.qbl $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee -+preceu.ph.qbl $t6, $t7 :: rd 0x001b00db rt 0x1bdbdbdb -+preceu.ph.qbl $t5, $t3 :: rd 0x00de00ca rt 0xdecadeca -+preceu.ph.qbl $t2, $t4 :: rd 0x00930047 rt 0x93474bde -+preceu.ph.qbl $t0, $t8 :: rd 0x00fc0000 rt 0xfc0007ff -+preceu.ph.qbl $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbl $t0, $t1 :: rd 0x00cb004a rt 0xcb4ab48f -+preceu.ph.qbl $t2, $t3 :: rd 0x00af008f rt 0xaf8f7e18 -+preceu.ph.qbl $t4, $t1 :: rd 0x008700df rt 0x87df4510 -+preceu.ph.qbl $t6, $t7 :: rd 0x00ab00f4 rt 0xabf4e8e1 -+preceu.ph.qbl $t5, $t3 :: rd 0x00f400c0 rt 0xf4c0eeac -+preceu.ph.qbl $t2, $t4 :: rd 0x0000006a rt 0x006a54f2 -+preceu.ph.qbl $t0, $t8 :: rd 0x007900f7 rt 0x79f74493 -+preceu.ph.qbl $t4, $t4 :: rd 0x009c0009 rt 0x9c09e313 -+-------- PRECEU.PH.QBLA -------- -+preceu.ph.qbla $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbla $t2, $t3 :: rd 0x00800032 rt 0x80003286 -+preceu.ph.qbla $t4, $t1 :: rd 0x00fa0024 rt 0xfabc2435 -+preceu.ph.qbla $t6, $t7 :: rd 0x00730080 rt 0x73468000 -+preceu.ph.qbla $t5, $t3 :: rd 0x00800000 rt 0x80000000 -+preceu.ph.qbla $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbla $t0, $t8 :: rd 0x00ff005f rt 0xfff45fff -+preceu.ph.qbla $t4, $t4 :: rd 0x00000005 rt 0x00000555 -+preceu.ph.qbla $t0, $t1 :: rd 0x00000053 rt 0x00005340 -+preceu.ph.qbla $t2, $t3 :: rd 0x00800000 rt 0x80000000 -+preceu.ph.qbla $t4, $t1 :: rd 0x00550055 rt 0x55555555 -+preceu.ph.qbla $t6, $t7 :: rd 0x00ff0024 rt 0xffff2435 -+preceu.ph.qbla $t5, $t3 :: rd 0x00ab00ab rt 0xabababab -+preceu.ph.qbla $t2, $t4 :: rd 0x00fc00b4 rt 0xfc79b4d2 -+preceu.ph.qbla $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbla $t4, $t4 :: rd 0x00000045 rt 0x00354565 -+preceu.ph.qbla $t0, $t1 :: rd 0x00000067 rt 0x00086755 -+preceu.ph.qbla $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f -+preceu.ph.qbla $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee -+preceu.ph.qbla $t6, $t7 :: rd 0x001b00db rt 0x1bdbdbdb -+preceu.ph.qbla $t5, $t3 :: rd 0x00de00de rt 0xdecadeca -+preceu.ph.qbla $t2, $t4 :: rd 0x0093004b rt 0x93474bde -+preceu.ph.qbla $t0, $t8 :: rd 0x00fc0007 rt 0xfc0007ff -+preceu.ph.qbla $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbla $t0, $t1 :: rd 0x00cb00b4 rt 0xcb4ab48f -+preceu.ph.qbla $t2, $t3 :: rd 0x00af007e rt 0xaf8f7e18 -+preceu.ph.qbla $t4, $t1 :: rd 0x00870045 rt 0x87df4510 -+preceu.ph.qbla $t6, $t7 :: rd 0x00ab00e8 rt 0xabf4e8e1 -+preceu.ph.qbla $t5, $t3 :: rd 0x00f400ee rt 0xf4c0eeac -+preceu.ph.qbla $t2, $t4 :: rd 0x00000054 rt 0x006a54f2 -+preceu.ph.qbla $t0, $t8 :: rd 0x00790044 rt 0x79f74493 -+preceu.ph.qbla $t4, $t4 :: rd 0x009c00e3 rt 0x9c09e313 -+-------- PRECEU.PH.QBR -------- -+preceu.ph.qbr $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbr $t2, $t3 :: rd 0x00320086 rt 0x80003286 -+preceu.ph.qbr $t4, $t1 :: rd 0x00240035 rt 0xfabc2435 -+preceu.ph.qbr $t6, $t7 :: rd 0x00800000 rt 0x73468000 -+preceu.ph.qbr $t5, $t3 :: rd 0x00000000 rt 0x80000000 -+preceu.ph.qbr $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbr $t0, $t8 :: rd 0x005f00ff rt 0xfff45fff -+preceu.ph.qbr $t4, $t4 :: rd 0x00050055 rt 0x00000555 -+preceu.ph.qbr $t0, $t1 :: rd 0x00530040 rt 0x00005340 -+preceu.ph.qbr $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+preceu.ph.qbr $t4, $t1 :: rd 0x00550055 rt 0x55555555 -+preceu.ph.qbr $t6, $t7 :: rd 0x00240035 rt 0xffff2435 -+preceu.ph.qbr $t5, $t3 :: rd 0x00ab00ab rt 0xabababab -+preceu.ph.qbr $t2, $t4 :: rd 0x00b400d2 rt 0xfc79b4d2 -+preceu.ph.qbr $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbr $t4, $t4 :: rd 0x00450065 rt 0x00354565 -+preceu.ph.qbr $t0, $t1 :: rd 0x00670055 rt 0x00086755 -+preceu.ph.qbr $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f -+preceu.ph.qbr $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee -+preceu.ph.qbr $t6, $t7 :: rd 0x00db00db rt 0x1bdbdbdb -+preceu.ph.qbr $t5, $t3 :: rd 0x00de00ca rt 0xdecadeca -+preceu.ph.qbr $t2, $t4 :: rd 0x004b00de rt 0x93474bde -+preceu.ph.qbr $t0, $t8 :: rd 0x000700ff rt 0xfc0007ff -+preceu.ph.qbr $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbr $t0, $t1 :: rd 0x00b4008f rt 0xcb4ab48f -+preceu.ph.qbr $t2, $t3 :: rd 0x007e0018 rt 0xaf8f7e18 -+preceu.ph.qbr $t4, $t1 :: rd 0x00450010 rt 0x87df4510 -+preceu.ph.qbr $t6, $t7 :: rd 0x00e800e1 rt 0xabf4e8e1 -+preceu.ph.qbr $t5, $t3 :: rd 0x00ee00ac rt 0xf4c0eeac -+preceu.ph.qbr $t2, $t4 :: rd 0x005400f2 rt 0x006a54f2 -+preceu.ph.qbr $t0, $t8 :: rd 0x00440093 rt 0x79f74493 -+preceu.ph.qbr $t4, $t4 :: rd 0x00e30013 rt 0x9c09e313 -+-------- PRECEU.PH.QBRA -------- -+preceu.ph.qbra $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbra $t2, $t3 :: rd 0x00000086 rt 0x80003286 -+preceu.ph.qbra $t4, $t1 :: rd 0x00bc0035 rt 0xfabc2435 -+preceu.ph.qbra $t6, $t7 :: rd 0x00460000 rt 0x73468000 -+preceu.ph.qbra $t5, $t3 :: rd 0x00000000 rt 0x80000000 -+preceu.ph.qbra $t2, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbra $t0, $t8 :: rd 0x00f400ff rt 0xfff45fff -+preceu.ph.qbra $t4, $t4 :: rd 0x00000055 rt 0x00000555 -+preceu.ph.qbra $t0, $t1 :: rd 0x00000040 rt 0x00005340 -+preceu.ph.qbra $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+preceu.ph.qbra $t4, $t1 :: rd 0x00550055 rt 0x55555555 -+preceu.ph.qbra $t6, $t7 :: rd 0x00ff0035 rt 0xffff2435 -+preceu.ph.qbra $t5, $t3 :: rd 0x00ab00ab rt 0xabababab -+preceu.ph.qbra $t2, $t4 :: rd 0x007900d2 rt 0xfc79b4d2 -+preceu.ph.qbra $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+preceu.ph.qbra $t4, $t4 :: rd 0x00350065 rt 0x00354565 -+preceu.ph.qbra $t0, $t1 :: rd 0x00080055 rt 0x00086755 -+preceu.ph.qbra $t2, $t3 :: rd 0x008f008f rt 0x8f8f8f8f -+preceu.ph.qbra $t4, $t1 :: rd 0x00ee00ee rt 0xeeeeeeee -+preceu.ph.qbra $t6, $t7 :: rd 0x00db00db rt 0x1bdbdbdb -+preceu.ph.qbra $t5, $t3 :: rd 0x00ca00ca rt 0xdecadeca -+preceu.ph.qbra $t2, $t4 :: rd 0x004700de rt 0x93474bde -+preceu.ph.qbra $t0, $t8 :: rd 0x000000ff rt 0xfc0007ff -+preceu.ph.qbra $t4, $t4 :: rd 0x00ff00ff rt 0xffffffff -+preceu.ph.qbra $t0, $t1 :: rd 0x004a008f rt 0xcb4ab48f -+preceu.ph.qbra $t2, $t3 :: rd 0x008f0018 rt 0xaf8f7e18 -+preceu.ph.qbra $t4, $t1 :: rd 0x00df0010 rt 0x87df4510 -+preceu.ph.qbra $t6, $t7 :: rd 0x00f400e1 rt 0xabf4e8e1 -+preceu.ph.qbra $t5, $t3 :: rd 0x00c000ac rt 0xf4c0eeac -+preceu.ph.qbra $t2, $t4 :: rd 0x006a00f2 rt 0x006a54f2 -+preceu.ph.qbra $t0, $t8 :: rd 0x00f70093 rt 0x79f74493 -+preceu.ph.qbra $t4, $t4 :: rd 0x00090013 rt 0x9c09e313 -+-------- PRECRQ.QB.PH -------- -+precrq.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+precrq.qb.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x04b20086 -+precrq.qb.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfa34fa34 -+precrq.qb.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x074c7380 -+precrq.qb.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf9438000 -+precrq.qb.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x0000ffff -+precrq.qb.ph $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7f7f7f7f -+precrq.qb.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00c40005 -+precrq.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+precrq.qb.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80008000 -+precrq.qb.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaa5555 -+precrq.qb.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ff24 -+precrq.qb.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabaabab -+precrq.qb.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0fcb4 -+precrq.qb.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfb390000 -+precrq.qb.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23480045 -+precrq.qb.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x987c0067 -+precrq.qb.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00008f8f -+precrq.qb.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x9246eeee -+precrq.qb.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcaca1bdb -+precrq.qb.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbabadede -+precrq.qb.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12de934b -+precrq.qb.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7c07fc07 -+precrq.qb.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff -+precrq.qb.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2dfcbb4 -+precrq.qb.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x4390af7e -+precrq.qb.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x21ba8745 -+precrq.qb.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x2463abe8 -+precrq.qb.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x10a1f4ee -+precrq.qb.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63a50054 -+precrq.qb.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf67a7944 -+precrq.qb.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd459ce3 -+-------- PRECRQ.PH.W -------- -+precrq.ph.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+precrq.ph.w $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x045f0002 -+precrq.ph.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfabcfabc -+precrq.ph.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x07657346 -+precrq.ph.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf9738000 -+precrq.ph.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00ffff01 -+precrq.ph.w $t0, $t8, $t0 :: rs 0x7fff7fff rt 0x7fff7fff out 0x7fff7fff -+precrq.ph.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 -+precrq.ph.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+precrq.ph.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80008000 -+precrq.ph.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xaaaa5555 -+precrq.ph.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ffff -+precrq.ph.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabaabab -+precrq.ph.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f0fc79 -+precrq.ph.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde0000 -+precrq.ph.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23530035 -+precrq.ph.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x980b0008 -+precrq.ph.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00008f8f -+precrq.ph.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x9278eeee -+precrq.ph.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcaca1bdb -+precrq.ph.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacadeca -+precrq.ph.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12fa9347 -+precrq.ph.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7c00fc00 -+precrq.ph.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff -+precrq.ph.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2f4cb4a -+precrq.ph.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x435faf8f -+precrq.ph.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x210687df -+precrq.ph.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x246aabf4 -+precrq.ph.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1046f4c0 -+precrq.ph.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x638c006a -+precrq.ph.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf63e79f7 -+precrq.ph.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd689c09 -+-------- PRECRQ_RS.PH.W -------- -+precrq_rs.ph.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x04600003 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfabcfabc DSPCtrl 0x00000000 -+precrq_rs.ph.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x07657347 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf9738000 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00ffff02 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t0, $t8, $t0 :: rs 0x7fffd004 rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00400000 -+precrq_rs.ph.w $t0, $t8, $t0 :: rs 0x7fffd004 rt 0x7fff7fff out 0x7fff7fff DSPCtrl 0x00400000 -+precrq_rs.ph.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00010000 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t0, $t1, $t2 :: rs 0x7fff8000 rt 0xffff8000 out 0x7fff0000 DSPCtrl 0x00400000 -+precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80008000 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t4, $t1, $t5 :: rs 0x7fffaaaa rt 0x55555555 out 0x7fff5555 DSPCtrl 0x00400000 -+precrq_rs.ph.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000ffff DSPCtrl 0x00000000 -+precrq_rs.ph.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xbabbabac DSPCtrl 0x00000000 -+precrq_rs.ph.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf0f1fc7a DSPCtrl 0x00000000 -+precrq_rs.ph.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde0000 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x23530035 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x980b0008 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00008f90 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x9278eeef DSPCtrl 0x00000000 -+precrq_rs.ph.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xcacb1bdc DSPCtrl 0x00000000 -+precrq_rs.ph.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xbacbdecb DSPCtrl 0x00000000 -+precrq_rs.ph.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x12fb9347 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t0, $t8, $t0 :: rs 0x7fffffff rt 0xfc0007ff out 0x7ffffc00 DSPCtrl 0x00400000 -+precrq_rs.ph.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xf2f5cb4b DSPCtrl 0x00000000 -+precrq_rs.ph.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x4360af8f DSPCtrl 0x00000000 -+precrq_rs.ph.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x210787df DSPCtrl 0x00000000 -+precrq_rs.ph.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x246aabf5 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1047f4c1 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x638d006a DSPCtrl 0x00000000 -+precrq_rs.ph.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xf63e79f7 DSPCtrl 0x00000000 -+precrq_rs.ph.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xbd689c0a DSPCtrl 0x00000000 -+-------- PRECRQU_S.QB.PH -------- -+precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x08000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00680068 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x0e99e600 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x00860000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0xffe0ffff DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000000a DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x0000aaaa DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000048 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x00000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0x00720000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x4690008a DSPCtrl 0x00000000 -+precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x00f900ce DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x008c0000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0x00003700 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x00000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x25000097 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0xf80f000f DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x860000fc DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x4200008a DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x48c60000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x20000000 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0xc70000a9 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x00f5f389 DSPCtrl 0x00400000 -+precrqu_s.qb.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x008b0000 DSPCtrl 0x00400000 -+-------- RADDU.W.QB -------- -+raddu.w.qb $t3, $t2 :: out 0x00000154 rs 0x55555555 -+raddu.w.qb $t4, $t1 :: out 0x00000257 rs 0xffff2435 -+raddu.w.qb $t7, $t2 :: out 0x00000154 rs 0x55555555 -+raddu.w.qb $t5, $t1 :: out 0x00000257 rs 0xffff2435 -+raddu.w.qb $t2, $t2 :: out 0x00000144 rs 0x55435755 -+raddu.w.qb $t3, $t1 :: out 0x00000257 rs 0xffff2435 -+raddu.w.qb $t1, $t2 :: out 0x00000144 rs 0x0fde3126 -+raddu.w.qb $t2, $t0 :: out 0x000002ac rs 0xabababab -+raddu.w.qb $t7, $t3 :: out 0x00000001 rs 0x00000001 -+raddu.w.qb $t5, $t6 :: out 0x00000040 rs 0x40000000 -+raddu.w.qb $t2, $t4 :: out 0x00000080 rs 0x80000000 -+raddu.w.qb $t6, $t1 :: out 0x0000037c rs 0x7fffffff -+raddu.w.qb $t8, $t5 :: out 0x0000012e rs 0x23534870 -+raddu.w.qb $t9, $t7 :: out 0x000003fc rs 0xffffffff -+raddu.w.qb $t3, $t8 :: out 0x000002fb rs 0xfc79b4d2 -+raddu.w.qb $t4, $t4 :: out 0x00000000 rs 0x00000000 -+raddu.w.qb $t5, $t5 :: out 0x00000000 rs 0x00000000 -+raddu.w.qb $t6, $t6 :: out 0x00000154 rs 0x12349876 -+raddu.w.qb $t7, $t7 :: out 0x000000df rs 0x00354565 -+raddu.w.qb $t8, $t8 :: out 0x000000c4 rs 0x00086755 -+raddu.w.qb $t9, $t0 :: out 0x0000023c rs 0x8f8f8f8f -+raddu.w.qb $t1, $t1 :: out 0x000003b8 rs 0xeeeeeeee -+raddu.w.qb $t1, $t2 :: out 0x000002ac rs 0x1bdbdbdb -+raddu.w.qb $t4, $t3 :: out 0x00000350 rs 0xdecadeca -+raddu.w.qb $t8, $t4 :: out 0x000001c5 rs 0x5fc92974 -+raddu.w.qb $t0, $t5 :: out 0x000000ec rs 0x7e08184e -+raddu.w.qb $t1, $t6 :: out 0x000001c9 rs 0x71c8315f -+raddu.w.qb $t2, $t7 :: out 0x00000146 rs 0x9493110e -+raddu.w.qb $t3, $t8 :: out 0x00000169 rs 0xbb246228 -+raddu.w.qb $t4, $t0 :: out 0x000001e5 rs 0x339d8d88 -+raddu.w.qb $t5, $t1 :: out 0x00000192 rs 0x70974249 -+raddu.w.qb $t6, $t2 :: out 0x000001e2 rs 0x8a8d4e7d -+raddu.w.qb $t7, $t1 :: out 0x0000017e rs 0xeb1b4335 -+raddu.w.qb $t8, $t2 :: out 0x0000019f rs 0x0cd6b508 -+raddu.w.qb $t0, $t1 :: out 0x000001fc rs 0x6731e282 -+raddu.w.qb $t1, $t2 :: out 0x00000324 rs 0xb6edf28f -+raddu.w.qb $t2, $t3 :: out 0x0000022c rs 0x4b4ec9ca -+raddu.w.qb $t3, $t4 :: out 0x000001e7 rs 0xc1037fa4 -+raddu.w.qb $t3, $t5 :: out 0x00000258 rs 0xcb4ab48f -+raddu.w.qb $t4, $t6 :: out 0x000001d4 rs 0xaf8f7e18 -+raddu.w.qb $t4, $t6 :: out 0x000001d4 rs 0xaf8f7e18 -+-------- RDDSP/WRDSP -------- -+outVal 0x05051512 inVal 0x35055512 mask 0x0000001f -+outVal 0x00000000 inVal 0x00000000 mask 0x00000002 -+outVal 0x00002000 inVal 0x80003286 mask 0x00000004 -+outVal 0x00bc0000 inVal 0xfabc2435 mask 0x00000008 -+outVal 0x03000000 inVal 0x73468000 mask 0x00000016 -+outVal 0x00000000 inVal 0x80000000 mask 0x00000020 -+outVal 0x00005f80 inVal 0xffffffff mask 0x00000022 -+outVal 0x0ff45fbf inVal 0xfff45fff mask 0x0000003f -+outVal 0x00000515 inVal 0x00000555 mask 0x00000013 -+outVal 0x03000000 inVal 0x23534870 mask 0x00000014 -+outVal 0x05000000 inVal 0x0555adec mask 0x00000010 -+outVal 0x0800201e inVal 0x980b7cde mask 0x00000015 -+outVal 0x0900003b inVal 0xf973437b mask 0x00000011 -+outVal 0x00000b9e inVal 0x93474bde mask 0x00000007 -+outVal 0x00550015 inVal 0x55555555 mask 0x00000009 -+outVal 0x00003e00 inVal 0xc4dbfe20 mask 0x00000006 -+outVal 0x00000000 inVal 0x734680bc mask 0x00000000 -+outVal 0x00000525 inVal 0x00354565 mask 0x00000003 -+outVal 0x0000000a inVal 0xbacabaca mask 0x00000021 -+outVal 0x0e001e80 inVal 0xdecadeca mask 0x00000016 -+outVal 0x00000006 inVal 0x00000286 mask 0x00000001 -+outVal 0x00002b80 inVal 0xabababab mask 0x00000026 -+-------- REPL.PH -------- -+repl.ph $t0, 0 :: rd 0x00000000 imm 0x00000000 -+repl.ph $t1, 1 :: rd 0x00010001 imm 0x00000001 -+repl.ph $t2, -1 :: rd 0xffffffff imm 0xffffffff -+repl.ph $t3, -129 :: rd 0xff7fff7f imm 0xffffff7f -+repl.ph $t4, -2 :: rd 0xfffefffe imm 0xfffffffe -+repl.ph $t0, 0x123 :: rd 0x01230123 imm 0x00000123 -+repl.ph $t1, 0x07b :: rd 0x007b007b imm 0x0000007b -+repl.ph $t2, 0x1c8 :: rd 0x01c801c8 imm 0x000001c8 -+repl.ph $t3, 0x080 :: rd 0x00800080 imm 0x00000080 -+repl.ph $t4, 0x07f :: rd 0x007f007f imm 0x0000007f -+repl.ph $t5, 0x1ff :: rd 0x01ff01ff imm 0x000001ff -+repl.ph $t6, 0x000 :: rd 0x00000000 imm 0x00000000 -+repl.ph $t7, 0x177 :: rd 0x01770177 imm 0x00000177 -+repl.ph $t0, 0x1de :: rd 0x01de01de imm 0x000001de -+repl.ph $t1, 0x018 :: rd 0x00180018 imm 0x00000018 -+repl.ph $t2, 0x056 :: rd 0x00560056 imm 0x00000056 -+repl.ph $t3, 0x1ca :: rd 0x01ca01ca imm 0x000001ca -+repl.ph $t4, 0x1ab :: rd 0x01ab01ab imm 0x000001ab -+repl.ph $t5, 0x1d2 :: rd 0x01d201d2 imm 0x000001d2 -+repl.ph $t6, 0x000 :: rd 0x00000000 imm 0x00000000 -+repl.ph $t7, 0x065 :: rd 0x00650065 imm 0x00000065 -+repl.ph $t0, 0x055 :: rd 0x00550055 imm 0x00000055 -+repl.ph $t1, 0x08f :: rd 0x008f008f imm 0x0000008f -+repl.ph $t2, 0x0ee :: rd 0x00ee00ee imm 0x000000ee -+repl.ph $t3, 0x1db :: rd 0x01db01db imm 0x000001db -+repl.ph $t4, 0x1ca :: rd 0x01ca01ca imm 0x000001ca -+repl.ph $t5, 0x1de :: rd 0x01de01de imm 0x000001de -+repl.ph $t6, 0x0ff :: rd 0x00ff00ff imm 0x000000ff -+repl.ph $t7, 0x0ff :: rd 0x00ff00ff imm 0x000000ff -+repl.ph $t0, 0x08f :: rd 0x008f008f imm 0x0000008f -+repl.ph $t1, 0x118 :: rd 0x01180118 imm 0x00000118 -+repl.ph $t2, 0x110 :: rd 0x01100110 imm 0x00000110 -+repl.ph $t3, 0x1e1 :: rd 0x01e101e1 imm 0x000001e1 -+repl.ph $t4, 0x1ac :: rd 0x01ac01ac imm 0x000001ac -+repl.ph $t5, 0x0f2 :: rd 0x00f200f2 imm 0x000000f2 -+repl.ph $t6, 0x093 :: rd 0x00930093 imm 0x00000093 -+repl.ph $t7, 0x013 :: rd 0x00130013 imm 0x00000013 -+-------- REPL.QB -------- -+repl.qb $t0, 0x23 :: rd 0x23232323 imm 0x00000023 -+repl.qb $t1, 0x7b :: rd 0x7b7b7b7b imm 0x0000007b -+repl.qb $t2, 0xc8 :: rd 0xc8c8c8c8 imm 0x000000c8 -+repl.qb $t3, 0x80 :: rd 0x80808080 imm 0x00000080 -+repl.qb $t4, 0x7f :: rd 0x7f7f7f7f imm 0x0000007f -+repl.qb $t5, 0xff :: rd 0xffffffff imm 0x000000ff -+repl.qb $t6, 0x00 :: rd 0x00000000 imm 0x00000000 -+repl.qb $t7, 0x77 :: rd 0x77777777 imm 0x00000077 -+repl.qb $t0, 0xde :: rd 0xdededede imm 0x000000de -+repl.qb $t1, 0x18 :: rd 0x18181818 imm 0x00000018 -+repl.qb $t2, 0x56 :: rd 0x56565656 imm 0x00000056 -+repl.qb $t3, 0xca :: rd 0xcacacaca imm 0x000000ca -+repl.qb $t4, 0xab :: rd 0xabababab imm 0x000000ab -+repl.qb $t5, 0xd2 :: rd 0xd2d2d2d2 imm 0x000000d2 -+repl.qb $t6, 0x00 :: rd 0x00000000 imm 0x00000000 -+repl.qb $t7, 0x65 :: rd 0x65656565 imm 0x00000065 -+repl.qb $t0, 0x55 :: rd 0x55555555 imm 0x00000055 -+repl.qb $t1, 0x8f :: rd 0x8f8f8f8f imm 0x0000008f -+repl.qb $t2, 0xee :: rd 0xeeeeeeee imm 0x000000ee -+repl.qb $t3, 0xdb :: rd 0xdbdbdbdb imm 0x000000db -+repl.qb $t4, 0xca :: rd 0xcacacaca imm 0x000000ca -+repl.qb $t5, 0xde :: rd 0xdededede imm 0x000000de -+repl.qb $t6, 0xff :: rd 0xffffffff imm 0x000000ff -+repl.qb $t7, 0xff :: rd 0xffffffff imm 0x000000ff -+repl.qb $t0, 0x8f :: rd 0x8f8f8f8f imm 0x0000008f -+repl.qb $t1, 0x18 :: rd 0x18181818 imm 0x00000018 -+repl.qb $t2, 0x10 :: rd 0x10101010 imm 0x00000010 -+repl.qb $t3, 0xe1 :: rd 0xe1e1e1e1 imm 0x000000e1 -+repl.qb $t4, 0xac :: rd 0xacacacac imm 0x000000ac -+repl.qb $t5, 0xf2 :: rd 0xf2f2f2f2 imm 0x000000f2 -+repl.qb $t6, 0x93 :: rd 0x93939393 imm 0x00000093 -+repl.qb $t7, 0x13 :: rd 0x13131313 imm 0x00000013 -+-------- REPLV.PH -------- -+replv.ph $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+replv.ph $t2, $t3 :: rd 0x32863286 rt 0x80003286 -+replv.ph $t4, $t1 :: rd 0x24352435 rt 0xfabc2435 -+replv.ph $t6, $t7 :: rd 0x80008000 rt 0x73468000 -+replv.ph $t5, $t3 :: rd 0x00000000 rt 0x80000000 -+replv.ph $t2, $t4 :: rd 0xffffffff rt 0xffffffff -+replv.ph $t0, $t8 :: rd 0x5fff5fff rt 0xfff45fff -+replv.ph $t4, $t4 :: rd 0x05550555 rt 0x00000555 -+replv.ph $t0, $t1 :: rd 0x53405340 rt 0x00005340 -+replv.ph $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+replv.ph $t4, $t1 :: rd 0x55555555 rt 0x55555555 -+replv.ph $t6, $t7 :: rd 0x24352435 rt 0xffff2435 -+replv.ph $t5, $t3 :: rd 0xabababab rt 0xabababab -+replv.ph $t2, $t4 :: rd 0xb4d2b4d2 rt 0xfc79b4d2 -+replv.ph $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+replv.ph $t4, $t4 :: rd 0x45654565 rt 0x00354565 -+replv.ph $t0, $t1 :: rd 0x67556755 rt 0x00086755 -+replv.ph $t2, $t3 :: rd 0x8f8f8f8f rt 0x8f8f8f8f -+replv.ph $t4, $t1 :: rd 0xeeeeeeee rt 0xeeeeeeee -+replv.ph $t6, $t7 :: rd 0xdbdbdbdb rt 0x1bdbdbdb -+replv.ph $t5, $t3 :: rd 0xdecadeca rt 0xdecadeca -+replv.ph $t2, $t4 :: rd 0x4bde4bde rt 0x93474bde -+replv.ph $t0, $t8 :: rd 0x07ff07ff rt 0xfc0007ff -+replv.ph $t4, $t4 :: rd 0xffffffff rt 0xffffffff -+replv.ph $t0, $t1 :: rd 0xb48fb48f rt 0xcb4ab48f -+replv.ph $t2, $t3 :: rd 0x7e187e18 rt 0xaf8f7e18 -+replv.ph $t4, $t1 :: rd 0x45104510 rt 0x87df4510 -+replv.ph $t6, $t7 :: rd 0xe8e1e8e1 rt 0xabf4e8e1 -+replv.ph $t5, $t3 :: rd 0xeeaceeac rt 0xf4c0eeac -+replv.ph $t2, $t4 :: rd 0x54f254f2 rt 0x006a54f2 -+replv.ph $t0, $t8 :: rd 0x44934493 rt 0x79f74493 -+replv.ph $t4, $t4 :: rd 0xe313e313 rt 0x9c09e313 -+-------- REPLV.QB -------- -+replv.qb $t0, $t1 :: rd 0x00000000 rt 0x00000000 -+replv.qb $t2, $t3 :: rd 0x86868686 rt 0x80003286 -+replv.qb $t4, $t1 :: rd 0x35353535 rt 0xfabc2435 -+replv.qb $t6, $t7 :: rd 0x00000000 rt 0x73468000 -+replv.qb $t5, $t3 :: rd 0x00000000 rt 0x80000000 -+replv.qb $t2, $t4 :: rd 0xffffffff rt 0xffffffff -+replv.qb $t0, $t8 :: rd 0xffffffff rt 0xfff45fff -+replv.qb $t4, $t4 :: rd 0x55555555 rt 0x00000555 -+replv.qb $t0, $t1 :: rd 0x40404040 rt 0x00005340 -+replv.qb $t2, $t3 :: rd 0x00000000 rt 0x80000000 -+replv.qb $t4, $t1 :: rd 0x55555555 rt 0x55555555 -+replv.qb $t6, $t7 :: rd 0x35353535 rt 0xffff2435 -+replv.qb $t5, $t3 :: rd 0xabababab rt 0xabababab -+replv.qb $t2, $t4 :: rd 0xd2d2d2d2 rt 0xfc79b4d2 -+replv.qb $t0, $t8 :: rd 0x00000000 rt 0x00000000 -+replv.qb $t4, $t4 :: rd 0x65656565 rt 0x00354565 -+replv.qb $t0, $t1 :: rd 0x55555555 rt 0x00086755 -+replv.qb $t2, $t3 :: rd 0x8f8f8f8f rt 0x8f8f8f8f -+replv.qb $t4, $t1 :: rd 0xeeeeeeee rt 0xeeeeeeee -+replv.qb $t6, $t7 :: rd 0xdbdbdbdb rt 0x1bdbdbdb -+replv.qb $t5, $t3 :: rd 0xcacacaca rt 0xdecadeca -+replv.qb $t2, $t4 :: rd 0xdededede rt 0x93474bde -+replv.qb $t0, $t8 :: rd 0xffffffff rt 0xfc0007ff -+replv.qb $t4, $t4 :: rd 0xffffffff rt 0xffffffff -+replv.qb $t0, $t1 :: rd 0x8f8f8f8f rt 0xcb4ab48f -+replv.qb $t2, $t3 :: rd 0x18181818 rt 0xaf8f7e18 -+replv.qb $t4, $t1 :: rd 0x10101010 rt 0x87df4510 -+replv.qb $t6, $t7 :: rd 0xe1e1e1e1 rt 0xabf4e8e1 -+replv.qb $t5, $t3 :: rd 0xacacacac rt 0xf4c0eeac -+replv.qb $t2, $t4 :: rd 0xf2f2f2f2 rt 0x006a54f2 -+replv.qb $t0, $t8 :: rd 0x93939393 rt 0x79f74493 -+replv.qb $t4, $t4 :: rd 0x13131313 rt 0x9c09e313 -+-------- SHILO -------- -+shilo ac3, -5 inAcc = 0x980b7cde0243ade5 outAcc = 0x016f9bc04875bca0 -+shilo ac0, 12 inAcc = 0x8000328600002340 outAcc = 0x0008000328600002 -+shilo ac1, 7 inAcc = 0x235348700bca3470 outAcc = 0x0046a690e0179468 -+shilo ac2, 3 inAcc = 0x0555adec1245bef6 outAcc = 0x00aab5bd8248b7de -+shilo ac3, -5 inAcc = 0x980b7cde0243ade5 outAcc = 0x016f9bc04875bca0 -+shilo ac0, -13 inAcc = 0xf97343ff0bce2434 outAcc = 0x687fe179c4868000 -+shilo ac1, 31 inAcc = 0x93474bde0bcde433 outAcc = 0x00000001268e97bc -+shilo ac2, -32 inAcc = 0x7f003245000432fe outAcc = 0x000432fe00000000 -+shilo ac3, 8 inAcc = 0xad80bce40241bce0 outAcc = 0x00ad80bce40241bc -+shilo ac0, 20 inAcc = 0x55555555bcdea87a outAcc = 0x0000055555555bcd -+shilo ac1, 22 inAcc = 0x0000000000000007 outAcc = 0x0000000000000000 -+shilo ac2, -19 inAcc = 0xc4dbfe20000023b6 outAcc = 0xf10000011db00000 -+shilo ac3, 16 inAcc = 0x734680bc000deab5 outAcc = 0x0000734680bc000d -+shilo ac0, -2 inAcc = 0x3545ff8000000004 outAcc = 0xd517fe0000000010 -+shilo ac1, -4 inAcc = 0xbacabaca00000003 outAcc = 0xacabaca000000030 -+shilo ac2, -18 inAcc = 0xdecadeca00000002 outAcc = 0x7b28000000080000 -+shilo ac3, 0 inAcc = 0xabababab00000001 outAcc = 0xabababab00000001 -+shilo ac0, 1 inAcc = 0xffffffff00000000 outAcc = 0x7fffffff80000000 -+shilo ac1, 30 inAcc = 0x7fff7fff0bce3457 outAcc = 0x00000001fffdfffc -+shilo ac2, -30 inAcc = 0x0001000100ca6ced outAcc = 0x40329b3b40000000 -+shilo ac3, -24 inAcc = 0x000000805bc34109 outAcc = 0x805bc34109000000 -+shilo ac0, 5 inAcc = 0xff4600004bacd342 outAcc = 0x07fa3000025d669a -+shilo ac1, 9 inAcc = 0x2fff000003bcde24 outAcc = 0x0017ff800001de6f -+shilo ac2, 16 inAcc = 0x2fff000002234379 outAcc = 0x00002fff00000223 -+shilo ac3, -12 inAcc = 0x2fff000001098789 outAcc = 0xf000001098789000 -+-------- SHILOV -------- -+shilov ac3, rs 0x01098789 inAcc = 0x980b7cde0243ade5 outAcc = 0x004c05be6f0121d6 -+shilov ac0, rs 0x0241bce0 inAcc = 0x8000328600002340 outAcc = 0x0000234000000000 -+shilov ac1, rs 0xc4dbfe20 inAcc = 0x235348700bca3470 outAcc = 0x0bca347000000000 -+shilov ac2, rs 0x93474bde inAcc = 0x0555adec1245bef6 outAcc = 0x000000001556b7b0 -+shilov ac3, rs 0x7f003245 inAcc = 0x980b7cde0243ade5 outAcc = 0x04c05be6f0121d6f -+shilov ac0, rs 0x0241bce0 inAcc = 0xf97343ff0bce2434 outAcc = 0x0bce243400000000 -+shilov ac1, rs 0x0bce3457 inAcc = 0x93474bde0bcde433 outAcc = 0x000001268e97bc17 -+shilov ac2, rs 0xbacabaca inAcc = 0x7f003245000432fe outAcc = 0x001fc00c9140010c -+shilov ac3, rs 0x734680bc inAcc = 0xad80bce40241bce0 outAcc = 0xd80bce40241bce00 -+shilov ac0, rs 0x3545ff80 inAcc = 0x55555555bcdea87a outAcc = 0x55555555bcdea87a -+shilov ac1, rs 0x7fff7fff inAcc = 0x0000000000000007 outAcc = 0x000000000000000e -+shilov ac2, rs 0xc4dbfe20 inAcc = 0xc4dbfe20000023b6 outAcc = 0x000023b600000000 -+shilov ac3, rs 0x00000010 inAcc = 0x734680bc000deab5 outAcc = 0x0000734680bc000d -+shilov ac0, rs 0xfffffffe inAcc = 0x3545ff8000000004 outAcc = 0xd517fe0000000010 -+shilov ac1, rs 0xfffffffc inAcc = 0xbacabaca00000003 outAcc = 0xacabaca000000030 -+shilov ac2, rs 0xffffffee inAcc = 0xdecadeca00000002 outAcc = 0x7b28000000080000 -+shilov ac3, rs 0x00000000 inAcc = 0xabababab00000001 outAcc = 0xabababab00000001 -+shilov ac0, rs 0x00000001 inAcc = 0xffffffff00000000 outAcc = 0x7fffffff80000000 -+shilov ac1, rs 0x0000001e inAcc = 0x7fff7fff0bce3457 outAcc = 0x00000001fffdfffc -+shilov ac2, rs 0xffffffe2 inAcc = 0x0001000100ca6ced outAcc = 0x40329b3b40000000 -+shilov ac3, rs 0xffffffe8 inAcc = 0x000000805bc34109 outAcc = 0x805bc34109000000 -+shilov ac0, rs 0xffffffe0 inAcc = 0xff4600004bacd342 outAcc = 0x4bacd34200000000 -+shilov ac1, rs 0x0000001f inAcc = 0x2fff000003bcde24 outAcc = 0x000000005ffe0000 -+shilov ac2, rs 0x00000010 inAcc = 0x2fff000002234379 outAcc = 0x00002fff00000223 -+shilov ac3, rs 0xfffffff4 inAcc = 0x2fff000001098789 outAcc = 0xf000001098789000 -+-------- SHLL.PH -------- -+shll.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 DSPCtrl 0x00000000 -+shll.ph $t2, $t3, 1 :: rd 0x5ffe0000 rt 0x2fff0000 sa 1 DSPCtrl 0x00000000 -+shll.ph $t4, $t1, 2 :: rd 0xbffc0000 rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 -+shll.ph $t6, $t7, 3 :: rd 0x7ff80000 rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 -+shll.ph $t5, $t3, 4 :: rd 0x00000000 rt 0x80000000 sa 4 DSPCtrl 0x00400000 -+shll.ph $t2, $t4, 5 :: rd 0xe020ffe0 rt 0xff01ffff sa 5 DSPCtrl 0x00000000 -+shll.ph $t0, $t8, 6 :: rd 0xffc0ffc0 rt 0x7fff7fff sa 6 DSPCtrl 0x00400000 -+shll.ph $t4, $t6, 7 :: rd 0x0000aa80 rt 0x00000555 sa 7 DSPCtrl 0x00400000 -+shll.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 DSPCtrl 0x00000000 -+shll.ph $t2, $t3, 9 :: rd 0x00000000 rt 0x80000000 sa 9 DSPCtrl 0x00400000 -+shll.ph $t4, $t1, 10 :: rd 0x54005400 rt 0x55555555 sa 10 DSPCtrl 0x00400000 -+shll.ph $t6, $t7, 11 :: rd 0xf800a800 rt 0xffff2435 sa 11 DSPCtrl 0x00400000 -+shll.ph $t5, $t3, 12 :: rd 0xb000b000 rt 0xabababab sa 12 DSPCtrl 0x00400000 -+shll.ph $t2, $t4, 13 :: rd 0x20004000 rt 0xfc79b4d2 sa 13 DSPCtrl 0x00400000 -+shll.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 DSPCtrl 0x00000000 -+shll.ph $t4, $t6, 15 :: rd 0x80008000 rt 0x00354565 sa 15 DSPCtrl 0x00400000 -+shll.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 DSPCtrl 0x00000000 -+shll.ph $t2, $t3, 1 :: rd 0x1f1e1f1e rt 0x8f8f8f8f sa 1 DSPCtrl 0x00400000 -+shll.ph $t4, $t1, 2 :: rd 0xbbb8bbb8 rt 0xeeeeeeee sa 2 DSPCtrl 0x00000000 -+shll.ph $t6, $t7, 3 :: rd 0xded8ded8 rt 0x1bdbdbdb sa 3 DSPCtrl 0x00400000 -+shll.ph $t5, $t3, 4 :: rd 0xeca0eca0 rt 0xdecadeca sa 4 DSPCtrl 0x00400000 -+shll.ph $t2, $t4, 5 :: rd 0x68e07bc0 rt 0x93474bde sa 5 DSPCtrl 0x00400000 -+shll.ph $t0, $t8, 6 :: rd 0x0000ffc0 rt 0xfc0007ff sa 6 DSPCtrl 0x00400000 -+shll.ph $t4, $t6, 7 :: rd 0xff80ff80 rt 0xffffffff sa 7 DSPCtrl 0x00000000 -+shll.ph $t0, $t1, 8 :: rd 0x4a008f00 rt 0xcb4ab48f sa 8 DSPCtrl 0x00400000 -+shll.ph $t2, $t3, 9 :: rd 0x1e003000 rt 0xaf8f7e18 sa 9 DSPCtrl 0x00400000 -+shll.ph $t4, $t1, 10 :: rd 0x7c004000 rt 0x87df4510 sa 10 DSPCtrl 0x00400000 -+shll.ph $t6, $t7, 11 :: rd 0xa0000800 rt 0xabf4e8e1 sa 11 DSPCtrl 0x00400000 -+shll.ph $t5, $t3, 12 :: rd 0x0000c000 rt 0xf4c0eeac sa 12 DSPCtrl 0x00400000 -+shll.ph $t2, $t4, 13 :: rd 0x40004000 rt 0x006a54f2 sa 13 DSPCtrl 0x00400000 -+shll.ph $t0, $t8, 14 :: rd 0xc000c000 rt 0x79f74493 sa 14 DSPCtrl 0x00400000 -+shll.ph $t4, $t6, 15 :: rd 0x80008000 rt 0x9c09e313 sa 15 DSPCtrl 0x00400000 -+-------- SHLL_S.PH -------- -+shll_s.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 DSPCtrl 0x00000000 -+shll_s.ph $t2, $t3, 1 :: rd 0x5ffe0000 rt 0x2fff0000 sa 1 DSPCtrl 0x00000000 -+shll_s.ph $t4, $t1, 2 :: rd 0x7fff0000 rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 -+shll_s.ph $t6, $t7, 3 :: rd 0x7fff0000 rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 -+shll_s.ph $t5, $t3, 4 :: rd 0x80000000 rt 0x80000000 sa 4 DSPCtrl 0x00400000 -+shll_s.ph $t2, $t4, 5 :: rd 0xe020ffe0 rt 0xff01ffff sa 5 DSPCtrl 0x00000000 -+shll_s.ph $t0, $t8, 6 :: rd 0x7fff7fff rt 0x7fff7fff sa 6 DSPCtrl 0x00400000 -+shll_s.ph $t4, $t6, 7 :: rd 0x00007fff rt 0x00000555 sa 7 DSPCtrl 0x00400000 -+shll_s.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 DSPCtrl 0x00000000 -+shll_s.ph $t2, $t3, 9 :: rd 0x80000000 rt 0x80000000 sa 9 DSPCtrl 0x00400000 -+shll_s.ph $t4, $t1, 10 :: rd 0x7fff7fff rt 0x55555555 sa 10 DSPCtrl 0x00400000 -+shll_s.ph $t6, $t7, 11 :: rd 0xf8007fff rt 0xffff2435 sa 11 DSPCtrl 0x00400000 -+shll_s.ph $t5, $t3, 12 :: rd 0x80008000 rt 0xabababab sa 12 DSPCtrl 0x00400000 -+shll_s.ph $t2, $t4, 13 :: rd 0x80008000 rt 0xfc79b4d2 sa 13 DSPCtrl 0x00400000 -+shll_s.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 DSPCtrl 0x00000000 -+shll_s.ph $t4, $t6, 15 :: rd 0x7fff7fff rt 0x00354565 sa 15 DSPCtrl 0x00400000 -+shll_s.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 DSPCtrl 0x00000000 -+shll_s.ph $t2, $t3, 1 :: rd 0x80008000 rt 0x8f8f8f8f sa 1 DSPCtrl 0x00400000 -+shll_s.ph $t4, $t1, 2 :: rd 0xbbb8bbb8 rt 0xeeeeeeee sa 2 DSPCtrl 0x00000000 -+shll_s.ph $t6, $t7, 3 :: rd 0x7fff8000 rt 0x1bdbdbdb sa 3 DSPCtrl 0x00400000 -+shll_s.ph $t5, $t3, 4 :: rd 0x80008000 rt 0xdecadeca sa 4 DSPCtrl 0x00400000 -+shll_s.ph $t2, $t4, 5 :: rd 0x80007fff rt 0x93474bde sa 5 DSPCtrl 0x00400000 -+shll_s.ph $t0, $t8, 6 :: rd 0x80007fff rt 0xfc0007ff sa 6 DSPCtrl 0x00400000 -+shll_s.ph $t4, $t6, 7 :: rd 0xff80ff80 rt 0xffffffff sa 7 DSPCtrl 0x00000000 -+shll_s.ph $t0, $t1, 8 :: rd 0x80008000 rt 0xcb4ab48f sa 8 DSPCtrl 0x00400000 -+shll_s.ph $t2, $t3, 9 :: rd 0x80007fff rt 0xaf8f7e18 sa 9 DSPCtrl 0x00400000 -+shll_s.ph $t4, $t1, 10 :: rd 0x80007fff rt 0x87df4510 sa 10 DSPCtrl 0x00400000 -+shll_s.ph $t6, $t7, 11 :: rd 0x80008000 rt 0xabf4e8e1 sa 11 DSPCtrl 0x00400000 -+shll_s.ph $t5, $t3, 12 :: rd 0x80008000 rt 0xf4c0eeac sa 12 DSPCtrl 0x00400000 -+shll_s.ph $t2, $t4, 13 :: rd 0x7fff7fff rt 0x006a54f2 sa 13 DSPCtrl 0x00400000 -+shll_s.ph $t0, $t8, 14 :: rd 0x7fff7fff rt 0x79f74493 sa 14 DSPCtrl 0x00400000 -+shll_s.ph $t4, $t6, 15 :: rd 0x80008000 rt 0x9c09e313 sa 15 DSPCtrl 0x00400000 -+-------- SHLL.QB -------- -+shll.qb $t0, $t1, 1 :: rd 0x00000000 rt 0x00000000 sa 1 DSPCtrl 0x00000000 -+shll.qb $t2, $t3, 2 :: rd 0xbcfc0000 rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 -+shll.qb $t4, $t1, 3 :: rd 0x78f80000 rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 -+shll.qb $t6, $t7, 4 :: rd 0xf0f00000 rt 0x2fff0000 sa 4 DSPCtrl 0x00400000 -+shll.qb $t5, $t3, 0 :: rd 0x80000000 rt 0x80000000 sa 0 DSPCtrl 0x00000000 -+shll.qb $t2, $t4, 7 :: rd 0x80808080 rt 0xff01ffff sa 7 DSPCtrl 0x00400000 -+shll.qb $t0, $t8, 7 :: rd 0x80808080 rt 0x7fff7fff sa 7 DSPCtrl 0x00400000 -+shll.qb $t4, $t6, 0 :: rd 0x00000555 rt 0x00000555 sa 0 DSPCtrl 0x00000000 -+shll.qb $t0, $t1, 1 :: rd 0x00000000 rt 0x00000000 sa 1 DSPCtrl 0x00000000 -+shll.qb $t2, $t3, 2 :: rd 0x00000000 rt 0x80000000 sa 2 DSPCtrl 0x00400000 -+shll.qb $t4, $t1, 3 :: rd 0xa8a8a8a8 rt 0x55555555 sa 3 DSPCtrl 0x00400000 -+shll.qb $t6, $t7, 4 :: rd 0xf0f04050 rt 0xffff2435 sa 4 DSPCtrl 0x00400000 -+shll.qb $t5, $t3, 5 :: rd 0x60606060 rt 0xabababab sa 5 DSPCtrl 0x00400000 -+shll.qb $t2, $t4, 6 :: rd 0x00400080 rt 0xfc79b4d2 sa 6 DSPCtrl 0x00400000 -+shll.qb $t0, $t8, 7 :: rd 0x00000000 rt 0x00000000 sa 7 DSPCtrl 0x00000000 -+shll.qb $t4, $t6, 0 :: rd 0x00354565 rt 0x00354565 sa 0 DSPCtrl 0x00000000 -+shll.qb $t0, $t1, 1 :: rd 0x0010ceaa rt 0x00086755 sa 1 DSPCtrl 0x00000000 -+shll.qb $t2, $t3, 2 :: rd 0x3c3c3c3c rt 0x8f8f8f8f sa 2 DSPCtrl 0x00400000 -+shll.qb $t4, $t1, 3 :: rd 0x70707070 rt 0xeeeeeeee sa 3 DSPCtrl 0x00400000 -+shll.qb $t6, $t7, 4 :: rd 0xb0b0b0b0 rt 0x1bdbdbdb sa 4 DSPCtrl 0x00400000 -+shll.qb $t5, $t3, 5 :: rd 0xc040c040 rt 0xdecadeca sa 5 DSPCtrl 0x00400000 -+shll.qb $t2, $t4, 6 :: rd 0xc0c0c080 rt 0x93474bde sa 6 DSPCtrl 0x00400000 -+shll.qb $t0, $t8, 7 :: rd 0x00008080 rt 0xfc0007ff sa 7 DSPCtrl 0x00400000 -+shll.qb $t4, $t6, 0 :: rd 0xffffffff rt 0xffffffff sa 0 DSPCtrl 0x00000000 -+shll.qb $t0, $t1, 3 :: rd 0x5850a078 rt 0xcb4ab48f sa 3 DSPCtrl 0x00400000 -+shll.qb $t2, $t3, 4 :: rd 0xf0f0e080 rt 0xaf8f7e18 sa 4 DSPCtrl 0x00400000 -+shll.qb $t4, $t1, 0 :: rd 0x87df4510 rt 0x87df4510 sa 0 DSPCtrl 0x00000000 -+shll.qb $t6, $t7, 7 :: rd 0x80000080 rt 0xabf4e8e1 sa 7 DSPCtrl 0x00400000 -+shll.qb $t5, $t3, 7 :: rd 0x00000000 rt 0xf4c0eeac sa 7 DSPCtrl 0x00400000 -+shll.qb $t2, $t4, 5 :: rd 0x00408040 rt 0x006a54f2 sa 5 DSPCtrl 0x00400000 -+shll.qb $t0, $t8, 1 :: rd 0xf2ee8826 rt 0x79f74493 sa 1 DSPCtrl 0x00400000 -+shll.qb $t4, $t6, 2 :: rd 0x70248c4c rt 0x9c09e313 sa 2 DSPCtrl 0x00400000 -+-------- SHLL_S.W -------- -+shll_s.w $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 DSPCtrl 0x00000000 -+shll_s.w $t2, $t3, 1 :: rd 0x5ffe0000 rt 0x2fff0000 sa 1 DSPCtrl 0x00000000 -+shll_s.w $t4, $t1, 2 :: rd 0x7fffffff rt 0x2fff0000 sa 2 DSPCtrl 0x00400000 -+shll_s.w $t6, $t7, 3 :: rd 0x7fffffff rt 0x2fff0000 sa 3 DSPCtrl 0x00400000 -+shll_s.w $t5, $t3, 4 :: rd 0x80000000 rt 0x80000000 sa 4 DSPCtrl 0x00400000 -+shll_s.w $t2, $t4, 5 :: rd 0xe03fffe0 rt 0xff01ffff sa 5 DSPCtrl 0x00000000 -+shll_s.w $t0, $t8, 6 :: rd 0x7fffffff rt 0x7fff7fff sa 6 DSPCtrl 0x00400000 -+shll_s.w $t4, $t6, 7 :: rd 0x0002aa80 rt 0x00000555 sa 7 DSPCtrl 0x00000000 -+shll_s.w $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 DSPCtrl 0x00000000 -+shll_s.w $t2, $t3, 9 :: rd 0x80000000 rt 0x80000000 sa 9 DSPCtrl 0x00400000 -+shll_s.w $t4, $t1, 10 :: rd 0x7fffffff rt 0x55555555 sa 10 DSPCtrl 0x00400000 -+shll_s.w $t6, $t7, 11 :: rd 0xf921a800 rt 0xffff2435 sa 11 DSPCtrl 0x00000000 -+shll_s.w $t5, $t3, 12 :: rd 0x80000000 rt 0xabababab sa 12 DSPCtrl 0x00400000 -+shll_s.w $t2, $t4, 13 :: rd 0x80000000 rt 0xfc79b4d2 sa 13 DSPCtrl 0x00400000 -+shll_s.w $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 DSPCtrl 0x00000000 -+shll_s.w $t4, $t6, 15 :: rd 0x7fffffff rt 0x00354565 sa 15 DSPCtrl 0x00400000 -+shll_s.w $t0, $t1, 16 :: rd 0x7fffffff rt 0x00086755 sa 0 DSPCtrl 0x00400000 -+shll_s.w $t2, $t3, 17 :: rd 0x80000000 rt 0x8f8f8f8f sa 1 DSPCtrl 0x00400000 -+shll_s.w $t4, $t1, 18 :: rd 0x80000000 rt 0xeeeeeeee sa 2 DSPCtrl 0x00400000 -+shll_s.w $t6, $t7, 19 :: rd 0x7fffffff rt 0x1bdbdbdb sa 3 DSPCtrl 0x00400000 -+shll_s.w $t5, $t3, 20 :: rd 0x80000000 rt 0xdecadeca sa 4 DSPCtrl 0x00400000 -+shll_s.w $t2, $t4, 21 :: rd 0x80000000 rt 0x93474bde sa 5 DSPCtrl 0x00400000 -+shll_s.w $t0, $t8, 22 :: rd 0x80000000 rt 0xfc0007ff sa 6 DSPCtrl 0x00400000 -+shll_s.w $t4, $t6, 23 :: rd 0xff800000 rt 0xffffffff sa 7 DSPCtrl 0x00000000 -+shll_s.w $t0, $t1, 24 :: rd 0x80000000 rt 0xcb4ab48f sa 8 DSPCtrl 0x00400000 -+shll_s.w $t2, $t3, 25 :: rd 0x80000000 rt 0xaf8f7e18 sa 9 DSPCtrl 0x00400000 -+shll_s.w $t4, $t1, 26 :: rd 0x80000000 rt 0x87df4510 sa 10 DSPCtrl 0x00400000 -+shll_s.w $t6, $t7, 27 :: rd 0x80000000 rt 0xabf4e8e1 sa 11 DSPCtrl 0x00400000 -+shll_s.w $t5, $t3, 28 :: rd 0x80000000 rt 0xf4c0eeac sa 12 DSPCtrl 0x00400000 -+shll_s.w $t2, $t4, 29 :: rd 0x7fffffff rt 0x006a54f2 sa 13 DSPCtrl 0x00400000 -+shll_s.w $t0, $t8, 30 :: rd 0x7fffffff rt 0x79f74493 sa 14 DSPCtrl 0x00400000 -+shll_s.w $t4, $t6, 31 :: rd 0x80000000 rt 0x9c09e313 sa 15 DSPCtrl 0x00400000 -+-------- SHLLV.PH -------- -+shllv.ph $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 -+shllv.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 -+shllv.ph $t4, $t1, $t5 :: rd 0x5ffe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00000000 -+shllv.ph $t6, $t7, $t3 :: rd 0xbffc0000 rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 -+shllv.ph $t5, $t3, $t2 :: rd 0x7ff80000 rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 -+shllv.ph $t2, $t4, $t8 :: rd 0x80008000 rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 -+shllv.ph $t0, $t8, $t0 :: rd 0x80000000 rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 -+shllv.ph $t4, $t6, $t1 :: rd 0x00008400 rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 -+shllv.ph $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 DSPCtrl 0x00000000 -+shllv.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 DSPCtrl 0x00000000 -+shllv.ph $t4, $t1, $t5 :: rd 0x55405540 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 -+shllv.ph $t6, $t7, $t3 :: rd 0x00000300 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00000000 -+shllv.ph $t5, $t3, $t2 :: rd 0xd000d000 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 -+shllv.ph $t2, $t4, $t8 :: rd 0xc3c0c3c0 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00000000 -+shllv.ph $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 -+shllv.ph $t4, $t6, $t1 :: rd 0x6a600e00 rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 -+shllv.ph $t0, $t1, $t2 :: rd 0x01609bc0 rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 -+shllv.ph $t2, $t3, $t4 :: rd 0x00000000 rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00400000 -+shllv.ph $t4, $t1, $t5 :: rd 0x00008000 rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 -+shllv.ph $t6, $t7, $t3 :: rd 0x50005000 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 -+shllv.ph $t5, $t3, $t2 :: rd 0x28002800 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 -+shllv.ph $t2, $t4, $t8 :: rd 0x80000000 rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 -+shllv.ph $t0, $t8, $t0 :: rd 0x00000000 rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 -+shllv.ph $t4, $t6, $t1 :: rd 0x80008000 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00000000 -+shllv.ph $t0, $t1, $t2 :: rd 0x00008000 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 -+shllv.ph $t2, $t3, $t4 :: rd 0x5f009a00 rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00400000 -+shllv.ph $t4, $t1, $t5 :: rd 0x2106ba5f rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00000000 -+shllv.ph $t6, $t7, $t3 :: rd 0x48d4c6ec rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00400000 -+shllv.ph $t5, $t3, $t2 :: rd 0x60003000 rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 -+shllv.ph $t2, $t4, $t8 :: rd 0x8e309454 rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 -+shllv.ph $t0, $t8, $t0 :: rd 0xb1f0d4e8 rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 -+shllv.ph $t4, $t6, $t1 :: rd 0xeb402e68 rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 -+-------- SHLLV_S.PH -------- -+shllv_s.ph $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.ph $t4, $t1, $t5 :: rd 0x5ffe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00000000 -+shllv_s.ph $t6, $t7, $t3 :: rd 0x7fff0000 rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 -+shllv_s.ph $t5, $t3, $t2 :: rd 0x7fff0000 rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 -+shllv_s.ph $t2, $t4, $t8 :: rd 0x7fff7fff rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 -+shllv_s.ph $t0, $t8, $t0 :: rd 0x7fff7fff rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 -+shllv_s.ph $t4, $t6, $t1 :: rd 0x00008000 rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 -+shllv_s.ph $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.ph $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 DSPCtrl 0x00000000 -+shllv_s.ph $t4, $t1, $t5 :: rd 0x80008000 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 -+shllv_s.ph $t6, $t7, $t3 :: rd 0x00000300 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00000000 -+shllv_s.ph $t5, $t3, $t2 :: rd 0x80008000 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 -+shllv_s.ph $t2, $t4, $t8 :: rd 0xc3c0c3c0 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00000000 -+shllv_s.ph $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.ph $t4, $t6, $t1 :: rd 0x7fff7fff rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 -+shllv_s.ph $t0, $t1, $t2 :: rd 0x80007fff rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 -+shllv_s.ph $t2, $t3, $t4 :: rd 0x00007fff rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00400000 -+shllv_s.ph $t4, $t1, $t5 :: rd 0x80007fff rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 -+shllv_s.ph $t6, $t7, $t3 :: rd 0x80008000 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 -+shllv_s.ph $t5, $t3, $t2 :: rd 0x80008000 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 -+shllv_s.ph $t2, $t4, $t8 :: rd 0x7fff8000 rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 -+shllv_s.ph $t0, $t8, $t0 :: rd 0x7fff7fff rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 -+shllv_s.ph $t4, $t6, $t1 :: rd 0x80008000 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00000000 -+shllv_s.ph $t0, $t1, $t2 :: rd 0x80008000 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 -+shllv_s.ph $t2, $t3, $t4 :: rd 0x7fff8000 rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00400000 -+shllv_s.ph $t4, $t1, $t5 :: rd 0x2106ba5f rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00000000 -+shllv_s.ph $t6, $t7, $t3 :: rd 0x48d47fff rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00400000 -+shllv_s.ph $t5, $t3, $t2 :: rd 0x7fff8000 rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 -+shllv_s.ph $t2, $t4, $t8 :: rd 0x7fff8000 rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 -+shllv_s.ph $t0, $t8, $t0 :: rd 0xb1f07fff rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 -+shllv_s.ph $t4, $t6, $t1 :: rd 0x80007fff rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 -+-------- SHLLV.QB -------- -+shllv.qb $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 -+shllv.qb $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 -+shllv.qb $t4, $t1, $t5 :: rd 0x5efe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00400000 -+shllv.qb $t6, $t7, $t3 :: rd 0xbcfc0000 rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 -+shllv.qb $t5, $t3, $t2 :: rd 0x78f80000 rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 -+shllv.qb $t2, $t4, $t8 :: rd 0x00800080 rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 -+shllv.qb $t0, $t8, $t0 :: rd 0x80800000 rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 -+shllv.qb $t4, $t6, $t1 :: rd 0x00008000 rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 -+shllv.qb $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x9348572b DSPCtrl 0x00000000 -+shllv.qb $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80023450 DSPCtrl 0x00000000 -+shllv.qb $t4, $t1, $t5 :: rd 0x40404040 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 -+shllv.qb $t6, $t7, $t3 :: rd 0x00000000 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00400000 -+shllv.qb $t5, $t3, $t2 :: rd 0xd0d0d0d0 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 -+shllv.qb $t2, $t4, $t8 :: rd 0xc0c0c0c0 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00400000 -+shllv.qb $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 -+shllv.qb $t4, $t6, $t1 :: rd 0x60600000 rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 -+shllv.qb $t0, $t1, $t2 :: rd 0x006080c0 rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 -+shllv.qb $t2, $t3, $t4 :: rd 0x00000000 rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00400000 -+shllv.qb $t4, $t1, $t5 :: rd 0x80008080 rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 -+shllv.qb $t6, $t7, $t3 :: rd 0x50505050 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 -+shllv.qb $t5, $t3, $t2 :: rd 0xe828e828 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 -+shllv.qb $t2, $t4, $t8 :: rd 0x80808000 rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 -+shllv.qb $t0, $t8, $t0 :: rd 0x00008000 rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 -+shllv.qb $t4, $t6, $t1 :: rd 0x80808080 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00400000 -+shllv.qb $t0, $t1, $t2 :: rd 0x00008080 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 -+shllv.qb $t2, $t3, $t4 :: rd 0x435f909a rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00000000 -+shllv.qb $t4, $t1, $t5 :: rd 0x2106ba5f rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00000000 -+shllv.qb $t6, $t7, $t3 :: rd 0x48d4c6ec rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00000000 -+shllv.qb $t5, $t3, $t2 :: rd 0x00601030 rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 -+shllv.qb $t2, $t4, $t8 :: rd 0x8c309454 rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 -+shllv.qb $t0, $t8, $t0 :: rd 0xb0f0d0e8 rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 -+shllv.qb $t4, $t6, $t1 :: rd 0xe8402868 rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 -+-------- SHLLV_S.W -------- -+shllv_s.w $t0, $t1, $t2 :: rd 0x7fffffff rt 0x7fffffff rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.w $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.w $t4, $t1, $t5 :: rd 0x5ffe0000 rt 0x2fff0000 rs 0xfabc3401 DSPCtrl 0x00000000 -+shllv_s.w $t6, $t7, $t3 :: rd 0x7fffffff rt 0x2fff0000 rs 0x73468002 DSPCtrl 0x00400000 -+shllv_s.w $t5, $t3, $t2 :: rd 0x7fffffff rt 0x2fff0000 rs 0x80000003 DSPCtrl 0x00400000 -+shllv_s.w $t2, $t4, $t8 :: rd 0x7fffffff rt 0x00ff0001 rs 0xff01ffff DSPCtrl 0x00400000 -+shllv_s.w $t0, $t8, $t0 :: rd 0x7fffffff rt 0x7fff7004 rs 0x7fff7fff DSPCtrl 0x00400000 -+shllv_s.w $t4, $t6, $t1 :: rd 0x7fffffff rt 0x0000c420 rs 0x00000555 DSPCtrl 0x00400000 -+shllv_s.w $t0, $t1, $t2 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.w $t2, $t3, $t4 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 DSPCtrl 0x00000000 -+shllv_s.w $t4, $t1, $t5 :: rd 0x80000000 rt 0xaaaaaaaa rs 0x55555555 DSPCtrl 0x00400000 -+shllv_s.w $t6, $t7, $t3 :: rd 0x03000000 rt 0x00000018 rs 0xffff2435 DSPCtrl 0x00000000 -+shllv_s.w $t5, $t3, $t2 :: rd 0x80000000 rt 0xbabababa rs 0xabababab DSPCtrl 0x00400000 -+shllv_s.w $t2, $t4, $t8 :: rd 0x80000000 rt 0xf0f0f0f0 rs 0xfc79b4d2 DSPCtrl 0x00400000 -+shllv_s.w $t0, $t8, $t0 :: rd 0xfbde3976 rt 0xfbde3976 rs 0x00000000 DSPCtrl 0x00000000 -+shllv_s.w $t4, $t6, $t1 :: rd 0x7fffffff rt 0x23534870 rs 0x00354565 DSPCtrl 0x00400000 -+shllv_s.w $t0, $t1, $t2 :: rd 0x80000000 rt 0x980b7cde rs 0x00086755 DSPCtrl 0x00400000 -+shllv_s.w $t2, $t3, $t4 :: rd 0x000c0000 rt 0x00000018 rs 0x8f8f8f8f DSPCtrl 0x00000000 -+shllv_s.w $t4, $t1, $t5 :: rd 0x80000000 rt 0x92784656 rs 0xeeeeeeee DSPCtrl 0x00400000 -+shllv_s.w $t6, $t7, $t3 :: rd 0x80000000 rt 0xcacacaca rs 0x1bdbdbdb DSPCtrl 0x00400000 -+shllv_s.w $t5, $t3, $t2 :: rd 0x80000000 rt 0xbacabaca rs 0xdecadeca DSPCtrl 0x00400000 -+shllv_s.w $t2, $t4, $t8 :: rd 0x7fffffff rt 0x12fadeb4 rs 0x93474bde DSPCtrl 0x00400000 -+shllv_s.w $t0, $t8, $t0 :: rd 0x7fffffff rt 0x7c000790 rs 0xfc0007ff DSPCtrl 0x00400000 -+shllv_s.w $t4, $t6, $t1 :: rd 0x80000000 rt 0xffffffff rs 0xffffffff DSPCtrl 0x00000000 -+shllv_s.w $t0, $t1, $t2 :: rd 0x80000000 rt 0xf2f4df1f rs 0xcb4ab48f DSPCtrl 0x00400000 -+shllv_s.w $t2, $t3, $t4 :: rd 0x7fffffff rt 0x435f909a rs 0xaf8f7e18 DSPCtrl 0x00400000 -+shllv_s.w $t4, $t1, $t5 :: rd 0x7fffffff rt 0x2106ba5f rs 0x87df4510 DSPCtrl 0x00400000 -+shllv_s.w $t6, $t7, $t3 :: rd 0x48d4c6ec rt 0x246a6376 rs 0xabf4e8e1 DSPCtrl 0x00000000 -+shllv_s.w $t5, $t3, $t2 :: rd 0x7fffffff rt 0x1046a1a3 rs 0xf4c0eeac DSPCtrl 0x00400000 -+shllv_s.w $t2, $t4, $t8 :: rd 0x7fffffff rt 0x638ca515 rs 0x006a54f2 DSPCtrl 0x00400000 -+shllv_s.w $t0, $t8, $t0 :: rd 0x80000000 rt 0xf63e7a9d rs 0x79f74493 DSPCtrl 0x00400000 -+shllv_s.w $t4, $t6, $t1 :: rd 0x80000000 rt 0xbd6845cd rs 0x9c09e313 DSPCtrl 0x00400000 -+-------- SHRA.PH -------- -+shra.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 -+shra.ph $t2, $t3, 1 :: rd 0x0001c319 rt 0x00028632 sa 1 -+shra.ph $t4, $t1, 2 :: rd 0xfeaf0d08 rt 0xfabc3421 sa 2 -+shra.ph $t6, $t7, 3 :: rd 0x0e68f017 rt 0x734680bc sa 3 -+shra.ph $t5, $t3, 4 :: rd 0xf8000000 rt 0x80000000 sa 4 -+shra.ph $t2, $t4, 5 :: rd 0xfff8ffff rt 0xff01ffff sa 5 -+shra.ph $t0, $t8, 6 :: rd 0x01ff01ff rt 0x7fff7fff sa 6 -+shra.ph $t4, $t6, 7 :: rd 0x0000000a rt 0x00000555 sa 7 -+shra.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 -+shra.ph $t2, $t3, 9 :: rd 0xffc00000 rt 0x80000000 sa 9 -+shra.ph $t4, $t1, 10 :: rd 0x00150015 rt 0x55555555 sa 10 -+shra.ph $t6, $t7, 11 :: rd 0xffff0004 rt 0xffff2435 sa 11 -+shra.ph $t5, $t3, 12 :: rd 0xfffafffa rt 0xabababab sa 12 -+shra.ph $t2, $t4, 13 :: rd 0xfffffffd rt 0xfc79b4d2 sa 13 -+shra.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 -+shra.ph $t4, $t6, 15 :: rd 0x00000000 rt 0x00354565 sa 15 -+shra.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 -+shra.ph $t2, $t3, 1 :: rd 0xc7c7c7c7 rt 0x8f8f8f8f sa 1 -+shra.ph $t4, $t1, 2 :: rd 0xfbbbfbbb rt 0xeeeeeeee sa 2 -+shra.ph $t6, $t7, 3 :: rd 0x037bfb7b rt 0x1bdbdbdb sa 3 -+shra.ph $t5, $t3, 4 :: rd 0xfdecfdec rt 0xdecadeca sa 4 -+shra.ph $t2, $t4, 5 :: rd 0xfc9a025e rt 0x93474bde sa 5 -+shra.ph $t0, $t8, 6 :: rd 0xfff0001f rt 0xfc0007ff sa 6 -+shra.ph $t4, $t6, 7 :: rd 0xffffffff rt 0xffffffff sa 7 -+shra.ph $t0, $t1, 8 :: rd 0xffcbffb4 rt 0xcb4ab48f sa 8 -+shra.ph $t2, $t3, 9 :: rd 0xffd7003f rt 0xaf8f7e18 sa 9 -+shra.ph $t4, $t1, 10 :: rd 0xffe10011 rt 0x87df4510 sa 10 -+shra.ph $t6, $t7, 11 :: rd 0xfff5fffd rt 0xabf4e8e1 sa 11 -+shra.ph $t5, $t3, 12 :: rd 0xfffffffe rt 0xf4c0eeac sa 12 -+shra.ph $t2, $t4, 13 :: rd 0x00000002 rt 0x006a54f2 sa 13 -+shra.ph $t0, $t8, 14 :: rd 0x00010001 rt 0x79f74493 sa 14 -+shra.ph $t4, $t6, 15 :: rd 0xffffffff rt 0x9c09e313 sa 15 -+-------- SHRA_R.PH -------- -+shra_r.ph $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 -+shra_r.ph $t2, $t3, 1 :: rd 0x0001c319 rt 0x00028632 sa 1 -+shra_r.ph $t4, $t1, 2 :: rd 0xfeaf0d08 rt 0xfabc3421 sa 2 -+shra_r.ph $t6, $t7, 3 :: rd 0x0e69f018 rt 0x734680bc sa 3 -+shra_r.ph $t5, $t3, 4 :: rd 0xf8000000 rt 0x80000000 sa 4 -+shra_r.ph $t2, $t4, 5 :: rd 0xfff80000 rt 0xff01ffff sa 5 -+shra_r.ph $t0, $t8, 6 :: rd 0x02000200 rt 0x7fff7fff sa 6 -+shra_r.ph $t4, $t6, 7 :: rd 0x0000000b rt 0x00000555 sa 7 -+shra_r.ph $t0, $t1, 8 :: rd 0x00000000 rt 0x00000000 sa 8 -+shra_r.ph $t2, $t3, 9 :: rd 0xffc00000 rt 0x80000000 sa 9 -+shra_r.ph $t4, $t1, 10 :: rd 0x00150015 rt 0x55555555 sa 10 -+shra_r.ph $t6, $t7, 11 :: rd 0x00000005 rt 0xffff2435 sa 11 -+shra_r.ph $t5, $t3, 12 :: rd 0xfffbfffb rt 0xabababab sa 12 -+shra_r.ph $t2, $t4, 13 :: rd 0x0000fffe rt 0xfc79b4d2 sa 13 -+shra_r.ph $t0, $t8, 14 :: rd 0x00000000 rt 0x00000000 sa 14 -+shra_r.ph $t4, $t6, 15 :: rd 0x00000001 rt 0x00354565 sa 15 -+shra_r.ph $t0, $t1, 0 :: rd 0x00086755 rt 0x00086755 sa 0 -+shra_r.ph $t2, $t3, 1 :: rd 0xc7c8c7c8 rt 0x8f8f8f8f sa 1 -+shra_r.ph $t4, $t1, 2 :: rd 0xfbbcfbbc rt 0xeeeeeeee sa 2 -+shra_r.ph $t6, $t7, 3 :: rd 0x037bfb7b rt 0x1bdbdbdb sa 3 -+shra_r.ph $t5, $t3, 4 :: rd 0xfdedfded rt 0xdecadeca sa 4 -+shra_r.ph $t2, $t4, 5 :: rd 0xfc9a025f rt 0x93474bde sa 5 -+shra_r.ph $t0, $t8, 6 :: rd 0xfff00020 rt 0xfc0007ff sa 6 -+shra_r.ph $t4, $t6, 7 :: rd 0x00000000 rt 0xffffffff sa 7 -+shra_r.ph $t0, $t1, 8 :: rd 0xffcbffb5 rt 0xcb4ab48f sa 8 -+shra_r.ph $t2, $t3, 9 :: rd 0xffd8003f rt 0xaf8f7e18 sa 9 -+shra_r.ph $t4, $t1, 10 :: rd 0xffe20011 rt 0x87df4510 sa 10 -+shra_r.ph $t6, $t7, 11 :: rd 0xfff5fffd rt 0xabf4e8e1 sa 11 -+shra_r.ph $t5, $t3, 12 :: rd 0xffffffff rt 0xf4c0eeac sa 12 -+shra_r.ph $t2, $t4, 13 :: rd 0x00000003 rt 0x006a54f2 sa 13 -+shra_r.ph $t0, $t8, 14 :: rd 0x00020001 rt 0x79f74493 sa 14 -+shra_r.ph $t4, $t6, 15 :: rd 0xffff0000 rt 0x9c09e313 sa 15 -+-------- SHRA_R.W -------- -+shra_r.w $t2, $t3, 1 :: rd 0x00000001 rt 0x00000002 sa 1 -+shra_r.w $t2, $t3, 16 :: rd 0xffff8000 rt 0x80000000 sa 16 -+shra_r.w $t2, $t3, 1 :: rd 0x00008001 rt 0x00010001 sa 1 -+shra_r.w $t2, $t3, 17 :: rd 0x00000001 rt 0x00010001 sa 17 -+shra_r.w $t2, $t3, 17 :: rd 0xffffc001 rt 0x80010001 sa 17 -+shra_r.w $t2, $t3, 0 :: rd 0x7fffffff rt 0x7fffffff sa 0 -+shra_r.w $t2, $t3, 1 :: rd 0x40000000 rt 0x7fffffff sa 1 -+shra_r.w $t2, $t3, 2 :: rd 0x20000000 rt 0x7ffffffe sa 2 -+shra_r.w $t0, $t1, 0 :: rd 0x00000000 rt 0x00000000 sa 0 -+shra_r.w $t4, $t1, 4 :: rd 0xffabc343 rt 0xfabc3435 sa 4 -+shra_r.w $t6, $t7, 17 :: rd 0x000003b3 rt 0x07654cb8 sa 17 -+shra_r.w $t5, $t3, 31 :: rd 0x00000000 rt 0xf973437b sa 31 -+shra_r.w $t2, $t4, 8 :: rd 0x0000ff00 rt 0x00ff0001 sa 8 -+shra_r.w $t0, $t8, 11 :: rd 0x000ffff0 rt 0x7fff7fff sa 11 -+shra_r.w $t4, $t6, 13 :: rd 0x00000006 rt 0x0000c420 sa 13 -+shra_r.w $t0, $t1, 2 :: rd 0x00000000 rt 0x00000000 sa 2 -+shra_r.w $t2, $t3, 6 :: rd 0xfe000000 rt 0x80000000 sa 6 -+shra_r.w $t4, $t1, 7 :: rd 0xff555555 rt 0xaaaaaaaa sa 7 -+shra_r.w $t6, $t7, 19 :: rd 0x00000000 rt 0x00000018 sa 19 -+shra_r.w $t5, $t3, 31 :: rd 0xffffffff rt 0xbabababa sa 31 -+shra_r.w $t2, $t4, 4 :: rd 0xff0f0f0f rt 0xf0f0f0f0 sa 4 -+shra_r.w $t0, $t8, 12 :: rd 0xffffbde4 rt 0xfbde3976 sa 12 -+shra_r.w $t4, $t6, 10 :: rd 0x0008d4d2 rt 0x23534870 sa 10 -+shra_r.w $t0, $t1, 20 :: rd 0xfffff981 rt 0x980b7cde sa 20 -+shra_r.w $t2, $t3, 21 :: rd 0x00000000 rt 0x00000018 sa 21 -+shra_r.w $t4, $t1, 24 :: rd 0xffffff92 rt 0x92784656 sa 24 -+shra_r.w $t6, $t7, 27 :: rd 0xfffffff9 rt 0xcacacaca sa 27 -+shra_r.w $t5, $t3, 1 :: rd 0xdd655d65 rt 0xbacabaca sa 1 -+shra_r.w $t2, $t4, 18 :: rd 0x000004bf rt 0x12fadeb4 sa 18 -+shra_r.w $t0, $t8, 10 :: rd 0x001f0002 rt 0x7c000790 sa 10 -+shra_r.w $t4, $t6, 16 :: rd 0x00000000 rt 0xffffffff sa 16 -+shra_r.w $t0, $t1, 0 :: rd 0xf2f4df1f rt 0xf2f4df1f sa 0 -+shra_r.w $t2, $t3, 14 :: rd 0x00010d7e rt 0x435f909a sa 14 -+shra_r.w $t4, $t1, 5 :: rd 0x010835d3 rt 0x2106ba5f sa 5 -+shra_r.w $t6, $t7, 7 :: rd 0x0048d4c7 rt 0x246a6376 sa 7 -+shra_r.w $t5, $t3, 9 :: rd 0x00082351 rt 0x1046a1a3 sa 9 -+shra_r.w $t2, $t4, 3 :: rd 0x0c7194a3 rt 0x638ca515 sa 3 -+shra_r.w $t0, $t8, 15 :: rd 0xffffec7d rt 0xf63e7a9d sa 15 -+shra_r.w $t4, $t6, 11 :: rd 0xfff7ad09 rt 0xbd6845cd sa 11 -+-------- SHRAV.PH -------- -+shrav.ph $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff -+shrav.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 -+shrav.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfd5e1a1a -+shrav.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000004 -+shrav.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b -+shrav.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00000000 -+shrav.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00000000 -+shrav.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000fe21 -+shrav.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+shrav.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 -+shrav.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xfd55fd55 -+shrav.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 -+shrav.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xfff7fff7 -+shrav.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xfc3cfc3c -+shrav.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 -+shrav.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x011a0243 -+shrav.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfcc003e6 -+shrav.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 -+shrav.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xfffe0001 -+shrav.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xfff9fff9 -+shrav.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffeeffee -+shrav.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x0000ffff -+shrav.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000000 -+shrav.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0xffffffff -+shrav.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xffffffff -+shrav.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0043ff90 -+shrav.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x2106ba5f -+shrav.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x123531bb -+shrav.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0001fffa -+shrav.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x18e3e945 -+shrav.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xfec70f53 -+shrav.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xf7ad08b9 -+-------- SHRAV_R.PH -------- -+shrav_r.ph $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff -+shrav_r.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 -+shrav_r.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfd5e1a1b -+shrav_r.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000005 -+shrav_r.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b -+shrav_r.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00000000 -+shrav_r.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00010001 -+shrav_r.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000fe21 -+shrav_r.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+shrav_r.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 -+shrav_r.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xfd55fd55 -+shrav_r.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000001 -+shrav_r.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xfff7fff7 -+shrav_r.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xfc3cfc3c -+shrav_r.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 -+shrav_r.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x011b0244 -+shrav_r.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfcc003e7 -+shrav_r.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 -+shrav_r.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xfffe0001 -+shrav_r.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xfff9fff9 -+shrav_r.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffefffef -+shrav_r.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x0000ffff -+shrav_r.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00010000 -+shrav_r.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 -+shrav_r.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x00000000 -+shrav_r.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x0043ff91 -+shrav_r.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x2106ba5f -+shrav_r.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x123531bb -+shrav_r.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0001fffa -+shrav_r.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x18e3e945 -+shrav_r.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xfec80f54 -+shrav_r.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xf7ad08ba -+-------- SHRAV_R.W -------- -+shrav_r.w $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff -+shrav_r.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 -+shrav_r.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0xfd5e1a1b -+shrav_r.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x00000000 -+shrav_r.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0xf973437b -+shrav_r.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00000000 -+shrav_r.w $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00000001 -+shrav_r.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x00000000 -+shrav_r.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 -+shrav_r.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x80000000 -+shrav_r.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0xfffffd55 -+shrav_r.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 -+shrav_r.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0xfff75757 -+shrav_r.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xfffffc3c -+shrav_r.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 -+shrav_r.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x011a9a44 -+shrav_r.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0xfffffcc0 -+shrav_r.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 -+shrav_r.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xfffe49e1 -+shrav_r.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xfffffff9 -+shrav_r.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xffeeb2af -+shrav_r.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00000000 -+shrav_r.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000001 -+shrav_r.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 -+shrav_r.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0xffffe5ea -+shrav_r.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x00000043 -+shrav_r.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x00002107 -+shrav_r.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x123531bb -+shrav_r.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x0001046a -+shrav_r.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x000018e3 -+shrav_r.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0xfffffec8 -+shrav_r.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0xfffff7ad -+-------- SHRL.QB -------- -+shrl.qb $t0, $t1, 1 :: rd 0x177f0000 rt 0x2fff0000 sa 1 -+shrl.qb $t2, $t3, 2 :: rd 0x0b3f0000 rt 0x2fff0000 sa 2 -+shrl.qb $t4, $t1, 3 :: rd 0x051f0000 rt 0x2fff0000 sa 3 -+shrl.qb $t6, $t7, 4 :: rd 0x0f040000 rt 0xff460000 sa 4 -+shrl.qb $t5, $t3, 0 :: rd 0x80000000 rt 0x80000000 sa 0 -+shrl.qb $t2, $t4, 7 :: rd 0x01000101 rt 0xff01ffff sa 7 -+shrl.qb $t0, $t8, 7 :: rd 0x00010001 rt 0x7fff7fff sa 7 -+shrl.qb $t4, $t6, 0 :: rd 0x00000555 rt 0x00000555 sa 0 -+shrl.qb $t0, $t1, 1 :: rd 0x00000000 rt 0x00000000 sa 1 -+shrl.qb $t2, $t3, 2 :: rd 0x20000000 rt 0x80000000 sa 2 -+shrl.qb $t4, $t1, 3 :: rd 0x0a0a0a0a rt 0x55555555 sa 3 -+shrl.qb $t6, $t7, 4 :: rd 0x0f0f0203 rt 0xffff2435 sa 4 -+shrl.qb $t5, $t3, 5 :: rd 0x05050505 rt 0xabababab sa 5 -+shrl.qb $t2, $t4, 6 :: rd 0x03010203 rt 0xfc79b4d2 sa 6 -+shrl.qb $t0, $t8, 7 :: rd 0x00000000 rt 0x00000000 sa 7 -+shrl.qb $t4, $t6, 0 :: rd 0x00354565 rt 0x00354565 sa 0 -+shrl.qb $t0, $t1, 1 :: rd 0x0004332a rt 0x00086755 sa 1 -+shrl.qb $t2, $t3, 2 :: rd 0x23232323 rt 0x8f8f8f8f sa 2 -+shrl.qb $t4, $t1, 3 :: rd 0x1d1d1d1d rt 0xeeeeeeee sa 3 -+shrl.qb $t6, $t7, 4 :: rd 0x010d0d0d rt 0x1bdbdbdb sa 4 -+shrl.qb $t5, $t3, 5 :: rd 0x06060606 rt 0xdecadeca sa 5 -+shrl.qb $t2, $t4, 6 :: rd 0x02010103 rt 0x93474bde sa 6 -+shrl.qb $t0, $t8, 7 :: rd 0x01000001 rt 0xfc0007ff sa 7 -+shrl.qb $t4, $t6, 0 :: rd 0xffffffff rt 0xffffffff sa 0 -+shrl.qb $t0, $t1, 3 :: rd 0x19091611 rt 0xcb4ab48f sa 3 -+shrl.qb $t2, $t3, 4 :: rd 0x0a080701 rt 0xaf8f7e18 sa 4 -+shrl.qb $t4, $t1, 0 :: rd 0x87df4510 rt 0x87df4510 sa 0 -+shrl.qb $t6, $t7, 7 :: rd 0x01010101 rt 0xabf4e8e1 sa 7 -+shrl.qb $t5, $t3, 7 :: rd 0x01010101 rt 0xf4c0eeac sa 7 -+shrl.qb $t2, $t4, 5 :: rd 0x00030207 rt 0x006a54f2 sa 5 -+shrl.qb $t0, $t8, 1 :: rd 0x3c7b2249 rt 0x79f74493 sa 1 -+shrl.qb $t4, $t6, 2 :: rd 0x27023804 rt 0x9c09e313 sa 2 -+-------- SHRLV.QB -------- -+shrlv.qb $t0, $t1, $t2 :: rd 0x177f0000 rt 0x2fff0000 rs 0x00000001 -+shrlv.qb $t2, $t3, $t4 :: rd 0x0b3f0000 rt 0x2fff0000 rs 0x73741802 -+shrlv.qb $t4, $t1, $t5 :: rd 0x051f0000 rt 0x2fff0000 rs 0x80003403 -+shrlv.qb $t6, $t7, $t3 :: rd 0x0f040000 rt 0xff460000 rs 0x73468004 -+shrlv.qb $t5, $t3, $t2 :: rd 0x00008000 rt 0x00008000 rs 0x80000000 -+shrlv.qb $t2, $t4, $t8 :: rd 0x00000000 rt 0x00010001 rs 0xffffff07 -+shrlv.qb $t0, $t8, $t0 :: rd 0x00010001 rt 0x7fff7fff rs 0x7fff7f07 -+shrlv.qb $t4, $t6, $t1 :: rd 0x07070707 rt 0xffffffff rs 0x00000505 -+shrlv.qb $t0, $t1, $t2 :: rd 0xabababab rt 0xabababab rs 0x00000000 -+shrlv.qb $t2, $t3, $t4 :: rd 0xdecadeca rt 0xdecadeca rs 0x80000000 -+shrlv.qb $t4, $t1, $t5 :: rd 0x05060506 rt 0xbacabaca rs 0x55555555 -+shrlv.qb $t6, $t7, $t3 :: rd 0x03040f08 rt 0x3545ff80 rs 0xffff2434 -+shrlv.qb $t5, $t3, $t2 :: rd 0x0e081017 rt 0x734680bc rs 0xabababa3 -+shrlv.qb $t2, $t4, $t8 :: rd 0x31363f08 rt 0xc4dbfe20 rs 0xfc79b4d2 -+shrlv.qb $t0, $t8, $t0 :: rd 0x00000000 rt 0x00000000 rs 0x00000000 -+shrlv.qb $t4, $t3, $t1 :: rd 0x2a2a2a2a rt 0x55555555 rs 0x00354561 -+shrlv.qb $t0, $t1, $t2 :: rd 0x05040507 rt 0xad80bce4 rs 0x00086755 -+shrlv.qb $t2, $t3, $t4 :: rd 0x00000000 rt 0x7f003245 rs 0x8f8f8f8f -+shrlv.qb $t4, $t1, $t5 :: rd 0x02010103 rt 0x93474bde rs 0xeeeeeeee -+shrlv.qb $t6, $t7, $t3 :: rd 0x1f0e081f rt 0xf97343ff rs 0x1bdbdbdb -+shrlv.qb $t5, $t3, $t2 :: rd 0x26021f37 rt 0x980b7cde rs 0xdecadeca -+shrlv.qb $t2, $t4, $t8 :: rd 0x00010203 rt 0x0555adec rs 0x93474bde -+shrlv.qb $t0, $t8, $t0 :: rd 0x00000000 rt 0x23534870 rs 0xfc0007ff -+shrlv.qb $t4, $t3, $t1 :: rd 0x01000001 rt 0x80003286 rs 0xffffffff -+shrlv.qb $t4, $t6, $t1 :: rd 0x10213f3f rt 0x4387ffff rs 0xdecadeca -+shrlv.qb $t0, $t1, $t2 :: rd 0x03352d02 rt 0x0cd6b508 rs 0xbacabaca -+shrlv.qb $t2, $t3, $t4 :: rd 0x6731e282 rt 0x6731e282 rs 0x3545ff80 -+shrlv.qb $t4, $t1, $t5 :: rd 0x020e0f08 rt 0x26edf28f rs 0x734680bc -+shrlv.qb $t6, $t7, $t3 :: rd 0x4b4ec9ca rt 0x4b4ec9ca rs 0xc4dbfe20 -+shrlv.qb $t5, $t3, $t2 :: rd 0xc1037fa4 rt 0xc1037fa4 rs 0x00000000 -+shrlv.qb $t2, $t4, $t8 :: rd 0x06020504 rt 0xcb4ab48f rs 0x55555555 -+shrlv.qb $t0, $t8, $t0 :: rd 0x0a080701 rt 0xaf8f7e18 rs 0xad80bce4 -+shrlv.qb $t4, $t3, $t1 :: rd 0x04060200 rt 0x87df4510 rs 0x7f003245 -+shrlv.qb $t0, $t1, $t2 :: rd 0x02030303 rt 0xabf4e8e1 rs 0x93474bde -+shrlv.qb $t2, $t3, $t4 :: rd 0x01010101 rt 0xf4c0eeac rs 0xf97343ff -+shrlv.qb $t4, $t1, $t5 :: rd 0x00010103 rt 0x006a54f2 rs 0x980b7cde -+shrlv.qb $t6, $t7, $t3 :: rd 0x070f0409 rt 0x79f74493 rs 0x0555adec -+shrlv.qb $t5, $t3, $t2 :: rd 0x9c09e313 rt 0x9c09e313 rs 0x23534870 -+shrlv.qb $t2, $t4, $t8 :: rd 0x13011c02 rt 0x9c09e313 rs 0x9c09e313 -+shrlv.qb $t0, $t8, $t0 :: rd 0x80000000 rt 0x80000000 rs 0x80000000 -+shrlv.qb $t4, $t3, $t1 :: rd 0x004d8000 rt 0x004d8000 rs 0x004d8000 -+-------- SUBQ.PH -------- -+subq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subq.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x045d2c00 DSPCtrl 0x00000000 -+subq.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 -+subq.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941fcbfc DSPCtrl 0x00100000 -+subq.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 -+subq.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fe0002 DSPCtrl 0x00000000 -+subq.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x0000f005 DSPCtrl 0x00000000 -+subq.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000becb DSPCtrl 0x00000000 -+subq.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subq.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+subq.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x55555555 DSPCtrl 0x00100000 -+subq.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0001dbe3 DSPCtrl 0x00000000 -+subq.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 -+subq.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00000000 -+subq.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+subq.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 -+subq.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 -+subq.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x70717089 DSPCtrl 0x00000000 -+subq.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa38a5768 DSPCtrl 0x00000000 -+subq.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaeefeeef DSPCtrl 0x00000000 -+subq.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdc00dc00 DSPCtrl 0x00000000 -+subq.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb392d6 DSPCtrl 0x00000000 -+subq.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x8000ff91 DSPCtrl 0x00100000 -+subq.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+subq.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2a90 DSPCtrl 0x00000000 -+subq.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x93d01282 DSPCtrl 0x00100000 -+subq.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x9927754f DSPCtrl 0x00100000 -+subq.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x78767a95 DSPCtrl 0x00000000 -+subq.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1b86b2f7 DSPCtrl 0x00000000 -+subq.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225023 DSPCtrl 0x00100000 -+subq.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7c47360a DSPCtrl 0x00100000 -+subq.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f62ba DSPCtrl 0x00000000 -+-------- SUBQ_S.PH -------- -+subq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t3, $t4 :: rs 0x00020002 rt 0x00010001 out 0x00010001 DSPCtrl 0x00000000 -+subq_s.ph $t4, $t1, $t5 :: rs 0x0002fffe rt 0x0001ffff out 0x0001ffff DSPCtrl 0x00000000 -+subq_s.ph $t6, $t7, $t3 :: rs 0x7fff8000 rt 0x7fff8000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t5, $t3, $t2 :: rs 0x7fff8000 rt 0x7ffe8001 out 0x0001ffff DSPCtrl 0x00000000 -+subq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t3, $t4 :: rs 0x045fb232 rt 0x00028632 out 0x045d2c00 DSPCtrl 0x00000000 -+subq_s.ph $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 -+subq_s.ph $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941f7fff DSPCtrl 0x00100000 -+subq_s.ph $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 -+subq_s.ph $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fe0002 DSPCtrl 0x00000000 -+subq_s.ph $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x0000f005 DSPCtrl 0x00000000 -+subq_s.ph $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000becb DSPCtrl 0x00000000 -+subq_s.ph $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x80008000 DSPCtrl 0x00100000 -+subq_s.ph $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0001dbe3 DSPCtrl 0x00000000 -+subq_s.ph $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 -+subq_s.ph $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00000000 -+subq_s.ph $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+subq_s.ph $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 -+subq_s.ph $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x70717089 DSPCtrl 0x00000000 -+subq_s.ph $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa38a5768 DSPCtrl 0x00000000 -+subq_s.ph $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaeefeeef DSPCtrl 0x00000000 -+subq_s.ph $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdc00dc00 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb392d6 DSPCtrl 0x00000000 -+subq_s.ph $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7fffff91 DSPCtrl 0x00100000 -+subq_s.ph $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+subq_s.ph $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2a90 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x7fff8000 DSPCtrl 0x00100000 -+subq_s.ph $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x7fff8000 DSPCtrl 0x00100000 -+subq_s.ph $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x78767a95 DSPCtrl 0x00000000 -+subq_s.ph $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1b86b2f7 DSPCtrl 0x00000000 -+subq_s.ph $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63228000 DSPCtrl 0x00100000 -+subq_s.ph $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x8000360a DSPCtrl 0x00100000 -+subq_s.ph $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f62ba DSPCtrl 0x00000000 -+-------- SUBQ_S.W -------- -+subq_s.w $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff DSPCtrl 0x00000000 -+subq_s.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 DSPCtrl 0x00000000 -+subq_s.w $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 -+subq_s.w $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941ecbfc DSPCtrl 0x00000000 -+subq_s.w $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 -+subq_s.w $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fd0002 DSPCtrl 0x00000000 -+subq_s.w $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0xfffff005 DSPCtrl 0x00000000 -+subq_s.w $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000becb DSPCtrl 0x00000000 -+subq_s.w $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.w $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+subq_s.w $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x80000000 DSPCtrl 0x00100000 -+subq_s.w $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0000dbe3 DSPCtrl 0x00000000 -+subq_s.w $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 -+subq_s.w $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00000000 -+subq_s.w $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+subq_s.w $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 -+subq_s.w $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 -+subq_s.w $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x70707089 DSPCtrl 0x00000000 -+subq_s.w $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa3895768 DSPCtrl 0x00000000 -+subq_s.w $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaeeeeeef DSPCtrl 0x00000000 -+subq_s.w $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdbffdc00 DSPCtrl 0x00000000 -+subq_s.w $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb392d6 DSPCtrl 0x00000000 -+subq_s.w $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x7fffff91 DSPCtrl 0x00000000 -+subq_s.w $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+subq_s.w $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2a90 DSPCtrl 0x00000000 -+subq_s.w $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x7fffffff DSPCtrl 0x00100000 -+subq_s.w $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x7fffffff DSPCtrl 0x00100000 -+subq_s.w $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x78757a95 DSPCtrl 0x00000000 -+subq_s.w $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1b85b2f7 DSPCtrl 0x00000000 -+subq_s.w $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225023 DSPCtrl 0x00000000 -+subq_s.w $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x80000000 DSPCtrl 0x00100000 -+subq_s.w $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215e62ba DSPCtrl 0x00000000 -+-------- SUBU.QB -------- -+subu.qb $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff DSPCtrl 0x00000000 -+subu.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 DSPCtrl 0x00000000 -+subu.qb $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 -+subu.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x941fccfc DSPCtrl 0x00100000 -+subu.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 -+subu.qb $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x01fe0102 DSPCtrl 0x00100000 -+subu.qb $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x0000f105 DSPCtrl 0x00100000 -+subu.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000bfcb DSPCtrl 0x00100000 -+subu.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subu.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+subu.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x55555555 DSPCtrl 0x00000000 -+subu.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x0101dce3 DSPCtrl 0x00100000 -+subu.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 -+subu.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0xf4773c1e DSPCtrl 0x00100000 -+subu.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+subu.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 -+subu.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 -+subu.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x71717189 DSPCtrl 0x00100000 -+subu.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0xa48a5868 DSPCtrl 0x00100000 -+subu.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xafefefef DSPCtrl 0x00100000 -+subu.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0xdc00dc00 DSPCtrl 0x00100000 -+subu.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x7fb393d6 DSPCtrl 0x00100000 -+subu.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x80000091 DSPCtrl 0x00100000 -+subu.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+subu.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2b90 DSPCtrl 0x00100000 -+subu.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x94d01282 DSPCtrl 0x00100000 -+subu.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x9a27754f DSPCtrl 0x00100000 -+subu.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x79767b95 DSPCtrl 0x00100000 -+subu.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x1c86b3f7 DSPCtrl 0x00100000 -+subu.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225123 DSPCtrl 0x00100000 -+subu.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7d47360a DSPCtrl 0x00100000 -+subu.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f62ba DSPCtrl 0x00100000 -+-------- SUBU_S.QB -------- -+subu_s.qb $t0, $t1, $t2 :: rs 0x7fffffff rt 0x00000000 out 0x7fffffff DSPCtrl 0x00000000 -+subu_s.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x00000000 out 0x80000000 DSPCtrl 0x00000000 -+subu_s.qb $t4, $t1, $t5 :: rs 0xfabc3435 rt 0xfabc3421 out 0x00000014 DSPCtrl 0x00000000 -+subu_s.qb $t6, $t7, $t3 :: rs 0x07654cb8 rt 0x734680bc out 0x001f0000 DSPCtrl 0x00100000 -+subu_s.qb $t5, $t3, $t2 :: rs 0xf973437b rt 0x80000000 out 0x7973437b DSPCtrl 0x00000000 -+subu_s.qb $t2, $t4, $t8 :: rs 0x00ff0001 rt 0xff01ffff out 0x00fe0000 DSPCtrl 0x00100000 -+subu_s.qb $t0, $t8, $t0 :: rs 0x7fff7004 rt 0x7fff7fff out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t4, $t6, $t1 :: rs 0x0000c420 rt 0x00000555 out 0x0000bf00 DSPCtrl 0x00100000 -+subu_s.qb $t0, $t1, $t2 :: rs 0x00000000 rt 0x00000000 out 0x00000000 DSPCtrl 0x00000000 -+subu_s.qb $t2, $t3, $t4 :: rs 0x80000000 rt 0x80000000 out 0x00000000 DSPCtrl 0x00000000 -+subu_s.qb $t4, $t1, $t5 :: rs 0xaaaaaaaa rt 0x55555555 out 0x55555555 DSPCtrl 0x00000000 -+subu_s.qb $t6, $t7, $t3 :: rs 0x00000018 rt 0xffff2435 out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t5, $t3, $t2 :: rs 0xbabababa rt 0xabababab out 0x0f0f0f0f DSPCtrl 0x00000000 -+subu_s.qb $t2, $t4, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 out 0x00773c1e DSPCtrl 0x00100000 -+subu_s.qb $t0, $t8, $t0 :: rs 0xfbde3976 rt 0x00000000 out 0xfbde3976 DSPCtrl 0x00000000 -+subu_s.qb $t4, $t6, $t1 :: rs 0x23534870 rt 0x00354565 out 0x231e030b DSPCtrl 0x00000000 -+subu_s.qb $t0, $t1, $t2 :: rs 0x980b7cde rt 0x00086755 out 0x98031589 DSPCtrl 0x00000000 -+subu_s.qb $t2, $t3, $t4 :: rs 0x00000018 rt 0x8f8f8f8f out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t4, $t1, $t5 :: rs 0x92784656 rt 0xeeeeeeee out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t6, $t7, $t3 :: rs 0xcacacaca rt 0x1bdbdbdb out 0xaf000000 DSPCtrl 0x00100000 -+subu_s.qb $t5, $t3, $t2 :: rs 0xbacabaca rt 0xdecadeca out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t2, $t4, $t8 :: rs 0x12fadeb4 rt 0x93474bde out 0x00b39300 DSPCtrl 0x00100000 -+subu_s.qb $t0, $t8, $t0 :: rs 0x7c000790 rt 0xfc0007ff out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t4, $t6, $t1 :: rs 0xffffffff rt 0xffffffff out 0x00000000 DSPCtrl 0x00000000 -+subu_s.qb $t0, $t1, $t2 :: rs 0xf2f4df1f rt 0xcb4ab48f out 0x27aa2b00 DSPCtrl 0x00100000 -+subu_s.qb $t2, $t3, $t4 :: rs 0x435f909a rt 0xaf8f7e18 out 0x00001282 DSPCtrl 0x00100000 -+subu_s.qb $t4, $t1, $t5 :: rs 0x2106ba5f rt 0x87df4510 out 0x0000754f DSPCtrl 0x00100000 -+subu_s.qb $t6, $t7, $t3 :: rs 0x246a6376 rt 0xabf4e8e1 out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t5, $t3, $t2 :: rs 0x1046a1a3 rt 0xf4c0eeac out 0x00000000 DSPCtrl 0x00100000 -+subu_s.qb $t2, $t4, $t8 :: rs 0x638ca515 rt 0x006a54f2 out 0x63225100 DSPCtrl 0x00100000 -+subu_s.qb $t0, $t8, $t0 :: rs 0xf63e7a9d rt 0x79f74493 out 0x7d00360a DSPCtrl 0x00100000 -+subu_s.qb $t4, $t6, $t1 :: rs 0xbd6845cd rt 0x9c09e313 out 0x215f00ba DSPCtrl 0x00100000 -Index: none/tests/mips32/mips32_dspr2.c -=================================================================== ---- none/tests/mips32/mips32_dspr2.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/mips32_dspr2.c (.../trunk) (revision 13981) -@@ -2328,7 +2328,7 @@ - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac0, $t5, $t3", "ac0", 0x80000000, - 0x80000000, 0x00000000, 0x00000001, t5, t3); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac1, $t2, $t4", "ac1", 0x00010001, -- 0xffffffff, 0xffffffff, 0xffffffff, t2, t4); -+ 0xcfffefff, 0xffffffff, 0xffffffff, t2, t4); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac2, $t0, $t8", "ac2", 0x7fff7fff, - 0x7fff7fff, 0xffffffff, 0xffffffff, t0, t8); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac0, $t0, $t1", "ac0", 0x0000c420, -@@ -2340,7 +2340,7 @@ - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac3, $t6, $t7", "ac3", 0xaaaaaaaa, - 0x55555555, 0xffffffff, 0xabababab, t6, t7); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac0, $t5, $t3", "ac0", 0x00000018, -- 0xffff2435, 0xffffffff, 0xfc79b4d2, t5, t3); -+ 0xfbff2435, 0xffffffff, 0xfc79b4d2, t5, t3); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac1, $t2, $t4", "ac1", 0xbabababa, - 0xabababab, 0x00000000, 0x00000000, t2, t4); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac2, $t0, $t8", "ac2", 0xf0f0f0f0, -@@ -2363,8 +2363,8 @@ - 0x93474bde, 0xffffffff, 0x93474bde, t0, t8); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac3, $t4, $t5", "ac3", 0x7c000790, - 0xfc0007ff, 0xffffffff, 0xfabfabfa, t4, t5); -- TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac2, $t0, $t8", "ac2", 0xffffffff, -- 0xffffffff, 0x00000000, 0x083b3571, t0, t8); -+ TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac2, $t0, $t8", "ac2", 0xbfff54ff, -+ 0xfb32ff01, 0x00000000, 0x083b3571, t0, t8); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac0, $t0, $t1", "ac0", 0x24a3291e, - 0x5648e540, 0xffffffff, 0xb9743941, t0, t1); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac1, $t2, $t3", "ac1", 0xdd91eebf, -@@ -2399,7 +2399,7 @@ - 0xc1037fa4, 0xffffffff, 0x9493110e, t4, t5); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac1, $t2, $t4", "ac1", 0x55555555, - 0xcb4ab48f, 0xffffffff, 0xbb246228, t2, t4); -- TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac2, $t0, $t8", "ac2", 0xffff8000, -+ TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac2, $t0, $t8", "ac2", 0x0fff8000, - 0xaf8f8000, 0x00000000, 0x339d8d88, t0, t8); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac0, $t0, $t1", "ac0", 0xabababab, - 0x87df4510, 0x00000000, 0x70974249, t0, t1); -@@ -2411,7 +2411,7 @@ - 0x006a54f2, 0x00000000, 0x0cd6b508, t6, t7); - TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac0, $t5, $t3", "ac0", 0x00086755, - 0x79f74493, 0x00000000, 0x6731e282, t5, t3); -- TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac1, $t2, $t4", "ac1", 0xffff8000, -+ TESTDSPINST_AC_RS_RT_DSPC("dpsqx_sa.w.ph $ac1, $t2, $t4", "ac1", 0x98548000, - 0x9c098000, 0xffffffff, 0xb6edf28f, t2, t4); - - printf("-------- DPSX.W.PH --------\n"); -Index: none/tests/mips32/mips32_dspr2.stdout.exp -=================================================================== ---- none/tests/mips32/mips32_dspr2.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/mips32_dspr2.stdout.exp (.../trunk) (revision 13981) -@@ -912,13 +912,13 @@ - dpsqx_sa.w.ph $ac1, $t2, $t3 :: rs 0x80002435 rt 0x80003421 inHI 0x00000000 inLO 0x40000000 outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00020000 - dpsqx_sa.w.ph $ac3, $t6, $t7 :: rs 0x76548000 rt 0x73468000 inHI 0x00000000 inLO 0x7fffffff outHI 0x00000000 outLO 0x7fffffff dspCtrl 0x00080000 - dpsqx_sa.w.ph $ac0, $t5, $t3 :: rs 0x80000000 rt 0x80000000 inHI 0x00000000 inLO 0x00000001 outHI 0x00000000 outLO 0x00000001 dspCtrl 0x00000000 --dpsqx_sa.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xffffffff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00000003 dspCtrl 0x00000000 -+dpsqx_sa.w.ph $ac1, $t2, $t4 :: rs 0x00010001 rt 0xcfffefff inHI 0xffffffff inLO 0xffffffff outHI 0x00000000 outLO 0x00008003 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0x7fff7fff rt 0x7fff7fff inHI 0xffffffff inLO 0xffffffff outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00040000 - dpsqx_sa.w.ph $ac0, $t0, $t1 :: rs 0x0000c420 rt 0x00000555 inHI 0x00000000 inLO 0x0fde3126 outHI 0x00000000 outLO 0x0fde3126 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac1, $t2, $t3 :: rs 0x00000000 rt 0x00000000 inHI 0x00000000 inLO 0x55555555 outHI 0x00000000 outLO 0x55555555 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac2, $t4, $t1 :: rs 0x80000000 rt 0x80000000 inHI 0xffffffff inLO 0xffff2435 outHI 0xffffffff outLO 0xffff2435 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac3, $t6, $t7 :: rs 0xaaaaaaaa rt 0x55555555 inHI 0xffffffff inLO 0xabababab outHI 0x00000000 outLO 0x1d7339e3 dspCtrl 0x00000000 --dpsqx_sa.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xffff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc79b502 dspCtrl 0x00000000 -+dpsqx_sa.w.ph $ac0, $t5, $t3 :: rs 0x00000018 rt 0xfbff2435 inHI 0xffffffff inLO 0xfc79b4d2 outHI 0xffffffff outLO 0xfc7a7502 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac1, $t2, $t4 :: rs 0xbabababa rt 0xabababab inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xa4b81f08 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0xf0f0f0f0 rt 0xfc79b4d2 inHI 0x00000000 inLO 0x00000000 outHI 0xffffffff outLO 0xf6bcf360 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac3, $t4, $t5 :: rs 0xfbde3976 rt 0x00000000 inHI 0x00000000 inLO 0x12349876 outHI 0x00000000 outLO 0x12349876 dspCtrl 0x00000000 -@@ -930,7 +930,7 @@ - dpsqx_sa.w.ph $ac1, $t2, $t4 :: rs 0xbacabaca rt 0xdecadeca inHI 0xffffffff inLO 0xdecadeca outHI 0xffffffff outLO 0xbae0a13a dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0x12fadeb4 rt 0x93474bde inHI 0xffffffff inLO 0x93474bde outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00040000 - dpsqx_sa.w.ph $ac3, $t4, $t5 :: rs 0x7c000790 rt 0xfc0007ff inHI 0xffffffff inLO 0xfabfabfa outHI 0xffffffff outLO 0xf33d23fa dspCtrl 0x00000000 --dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0xffffffff rt 0xffffffff inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x083b356d dspCtrl 0x00000000 -+dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0xbfff54ff rt 0xfb32ff01 inHI 0x00000000 inLO 0x083b3571 outHI 0x00000000 outLO 0x0aec75d7 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac0, $t0, $t1 :: rs 0x24a3291e rt 0x5648e540 inHI 0xffffffff inLO 0xb9743941 outHI 0xffffffff outLO 0xa56500e1 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac1, $t2, $t3 :: rs 0xdd91eebf rt 0xc54f79e6 inHI 0xffffffff inLO 0xbce5f924 outHI 0xffffffff outLO 0xd5c776b6 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac2, $t4, $t1 :: rs 0xf7ce2ec6 rt 0x5fc92974 inHI 0xffffffff inLO 0xcc3c201c outHI 0xffffffff outLO 0xabe32a80 dspCtrl 0x00000000 -@@ -948,13 +948,13 @@ - dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0x00000000 rt 0x4b4ec9ca inHI 0x00000000 inLO 0x71c8315f outHI 0x00000000 outLO 0x71c8315f dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac3, $t4, $t5 :: rs 0x80000000 rt 0xc1037fa4 inHI 0xffffffff inLO 0x9493110e outHI 0x00000000 outLO 0x1437110e dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac1, $t2, $t4 :: rs 0x55555555 rt 0xcb4ab48f inHI 0xffffffff inLO 0xbb246228 outHI 0x00000000 outLO 0x1093620e dspCtrl 0x00000000 --dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0xffff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffffff outLO 0xe32b8d88 dspCtrl 0x00000000 -+dpsqx_sa.w.ph $ac2, $t0, $t8 :: rs 0x0fff8000 rt 0xaf8f8000 inHI 0x00000000 inLO 0x339d8d88 outHI 0xffffffff outLO 0xf32b8d88 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac0, $t0, $t1 :: rs 0xabababab rt 0x87df4510 inHI 0x00000000 inLO 0x70974249 outHI 0x00000000 outLO 0x4ef230ff dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac1, $t2, $t3 :: rs 0xfc79b4d2 rt 0xabf4e8e1 inHI 0xffffffff inLO 0x8a8d4e7d outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00020000 - dpsqx_sa.w.ph $ac2, $t4, $t1 :: rs 0x00000000 rt 0xf4c0eeac inHI 0xffffffff inLO 0xeb1b4335 outHI 0xffffffff outLO 0xeb1b4335 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac3, $t6, $t7 :: rs 0x00354565 rt 0x006a54f2 inHI 0x00000000 inLO 0x0cd6b508 outHI 0x00000000 outLO 0x0c7a1130 dspCtrl 0x00000000 - dpsqx_sa.w.ph $ac0, $t5, $t3 :: rs 0x00086755 rt 0x79f74493 inHI 0x00000000 inLO 0x6731e282 outHI 0x00000000 outLO 0x04b7d94c dspCtrl 0x00000000 --dpsqx_sa.w.ph $ac1, $t2, $t4 :: rs 0xffff8000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00020000 -+dpsqx_sa.w.ph $ac1, $t2, $t4 :: rs 0x98548000 rt 0x9c098000 inHI 0xffffffff inLO 0xb6edf28f outHI 0xffffffff outLO 0x80000000 dspCtrl 0x00020000 - -------- DPSX.W.PH -------- - dpsx.w.ph HIout=0xffffffff, LOout=0x000075fe, HIin=0xffffffff, LOin=0x00000000, RSval=0x3277ffff, RTval=0x4387ffff - dpsx.w.ph HIout=0x00000000, LOout=0x00000000, HIin=0x00000000, LOin=0x00000000, RSval=0x00000004, RTval=0x00000005 -Index: none/tests/mips32/round.c -=================================================================== ---- none/tests/mips32/round.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/round.c (.../trunk) (revision 13981) -@@ -32,11 +32,11 @@ - }; - - const double fs_d[] = { -- 0, 456.25, 3, -1, -- 1384.5, -7.25, 1000000000, -5786.25, -- 1752, 0.015625, 0.03125, -248562.75, -- -45786.5, 456, 34.03125, 45786.75, -- 1752065, 107, -45667.25, -7, -+ 0, 456.25, 3, -1, -+ 1384.5, -7.25, 1000000000, -5786.25, -+ 1752, 0.015625, 0.03125, -248562.75, -+ -45786.5, 456, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7, - -347856.5, 356047, -1.25, 23.0625 - }; - -@@ -132,31 +132,19 @@ - { - switch(mode) { - case TO_NEAREST: -- __asm__ volatile("cfc1 $t0, $31\n\t" -- "srl $t0, 2\n\t" -- "sll $t0, 2\n\t" -- "ctc1 $t0, $31\n\t"); -+ __asm__ volatile("ctc1 $zero, $31" "\n\t"); - break; - case TO_ZERO: -- __asm__ volatile("cfc1 $t0, $31\n\t" -- "srl $t0, 2\n\t" -- "sll $t0, 2\n\t" -- "addiu $t0, 1\n\t" -- "ctc1 $t0, $31\n\t"); -+ __asm__ volatile("li $t0, 0x1" "\n\t" -+ "ctc1 $t0, $31" "\n\t"); - break; - case TO_PLUS_INFINITY: -- __asm__ volatile("cfc1 $t0, $31\n\t" -- "srl $t0, 2\n\t" -- "sll $t0, 2\n\t" -- "addiu $t0, 2\n\t" -- "ctc1 $t0, $31\n\t"); -+ __asm__ volatile("li $t0, 0x2" "\n\t" -+ "ctc1 $t0, $31" "\n\t"); - break; - case TO_MINUS_INFINITY: -- __asm__ volatile("cfc1 $t0, $31\n\t" -- "srl $t0, 2\n\t" -- "sll $t0, 2\n\t" -- "addiu $t0, 3\n\t" -- "ctc1 $t0, $31\n\t"); -+ __asm__ volatile("li $t0, 0x3" "\n\t" -+ "ctc1 $t0, $31" "\n\t"); - break; - } - } -@@ -165,7 +153,9 @@ - int fd_w = 0; - int i; - int fcsr = 0; -+ round_mode_t rm = TO_NEAREST; - for (i = 0; i < 24; i++) { -+ set_rounding_mode(rm); - switch(op) { - case CEILWS: - UNOPfw("ceil.w.s"); -@@ -215,7 +205,7 @@ - return 0; - } - --int FCSRRoundingMode(flt_round_op_t op1) -+int FCSRRoundingMode(flt_round_op_t op1) - { - double fd_d = 0; - float fd_f = 0; -@@ -223,7 +213,7 @@ - int i; - int fcsr = 0; - round_mode_t rm; -- for (rm = TO_NEAREST; rm <= TO_MINUS_INFINITY; rm ++) { -+ for (rm = TO_NEAREST; rm <= TO_MINUS_INFINITY; rm ++) { - set_rounding_mode(rm); - printf("roundig mode: %s\n", round_mode_name[rm]); - for (i = 0; i < 24; i++) { -@@ -278,7 +268,7 @@ - for (op = CEILWS; op <= TRUNCWD; op++) { - directedRoundingMode(op); - } -- -+ - printf("-------------------------- %s --------------------------\n", - "test FPU Conversion Operations Using the FCSR Rounding Mode"); - for (op1 = CVTDS; op1 <= CVTWD; op1++) { -Index: none/tests/mips32/round.stdout.exp -=================================================================== ---- none/tests/mips32/round.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/round.stdout.exp (.../trunk) (revision 13981) -@@ -4,19 +4,19 @@ - ceil.w.s 457 456.250000 - fcsr: 0x1004 - ceil.w.s 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s 1385 1384.500000 - fcsr: 0x1004 - ceil.w.s -7 -7.250000 - fcsr: 0x1004 - ceil.w.s 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s -5786 -5786.250000 - fcsr: 0x1004 - ceil.w.s 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s 1 0.015625 - fcsr: 0x1004 - ceil.w.s 1 0.031250 -@@ -26,45 +26,45 @@ - ceil.w.s -45786 -45786.500000 - fcsr: 0x1004 - ceil.w.s 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s 35 34.031250 - fcsr: 0x1004 - ceil.w.s 45787 45786.750000 - fcsr: 0x1004 - ceil.w.s 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s -45667 -45667.250000 - fcsr: 0x1004 - ceil.w.s -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s -347856 -347856.500000 - fcsr: 0x1004 - ceil.w.s 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.s -1 -1.250000 - fcsr: 0x1004 - ceil.w.s 24 23.062500 - fcsr: 0x1004 - ceil.w.d 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d 457 456.250000 - fcsr: 0x1004 - ceil.w.d 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d 1385 1384.500000 - fcsr: 0x1004 - ceil.w.d -7 -7.250000 - fcsr: 0x1004 - ceil.w.d 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d -5786 -5786.250000 - fcsr: 0x1004 - ceil.w.d 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d 1 0.015625 - fcsr: 0x1004 - ceil.w.d 1 0.031250 -@@ -74,45 +74,45 @@ - ceil.w.d -45786 -45786.500000 - fcsr: 0x1004 - ceil.w.d 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d 35 34.031250 - fcsr: 0x1004 - ceil.w.d 45787 45786.750000 - fcsr: 0x1004 - ceil.w.d 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d -45667 -45667.250000 - fcsr: 0x1004 - ceil.w.d -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d -347856 -347856.500000 - fcsr: 0x1004 - ceil.w.d 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - ceil.w.d -1 -1.250000 - fcsr: 0x1004 - ceil.w.d 24 23.062500 - fcsr: 0x1004 - floor.w.s 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s 456 456.250000 - fcsr: 0x1004 - floor.w.s 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s 1384 1384.500000 - fcsr: 0x1004 - floor.w.s -8 -7.250000 - fcsr: 0x1004 - floor.w.s 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s -5787 -5786.250000 - fcsr: 0x1004 - floor.w.s 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s 0 0.015625 - fcsr: 0x1004 - floor.w.s 0 0.031250 -@@ -122,45 +122,45 @@ - floor.w.s -45787 -45786.500000 - fcsr: 0x1004 - floor.w.s 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s 34 34.031250 - fcsr: 0x1004 - floor.w.s 45786 45786.750000 - fcsr: 0x1004 - floor.w.s 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s -45668 -45667.250000 - fcsr: 0x1004 - floor.w.s -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s -347857 -347856.500000 - fcsr: 0x1004 - floor.w.s 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.s -2 -1.250000 - fcsr: 0x1004 - floor.w.s 23 23.062500 - fcsr: 0x1004 - floor.w.d 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d 456 456.250000 - fcsr: 0x1004 - floor.w.d 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d 1384 1384.500000 - fcsr: 0x1004 - floor.w.d -8 -7.250000 - fcsr: 0x1004 - floor.w.d 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d -5787 -5786.250000 - fcsr: 0x1004 - floor.w.d 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d 0 0.015625 - fcsr: 0x1004 - floor.w.d 0 0.031250 -@@ -170,45 +170,45 @@ - floor.w.d -45787 -45786.500000 - fcsr: 0x1004 - floor.w.d 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d 34 34.031250 - fcsr: 0x1004 - floor.w.d 45786 45786.750000 - fcsr: 0x1004 - floor.w.d 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d -45668 -45667.250000 - fcsr: 0x1004 - floor.w.d -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d -347857 -347856.500000 - fcsr: 0x1004 - floor.w.d 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - floor.w.d -2 -1.250000 - fcsr: 0x1004 - floor.w.d 23 23.062500 - fcsr: 0x1004 - round.w.s 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s 456 456.250000 - fcsr: 0x1004 - round.w.s 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s 1384 1384.500000 - fcsr: 0x1004 - round.w.s -7 -7.250000 - fcsr: 0x1004 - round.w.s 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s -5786 -5786.250000 - fcsr: 0x1004 - round.w.s 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s 0 0.015625 - fcsr: 0x1004 - round.w.s 0 0.031250 -@@ -218,45 +218,45 @@ - round.w.s -45786 -45786.500000 - fcsr: 0x1004 - round.w.s 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s 34 34.031250 - fcsr: 0x1004 - round.w.s 45787 45786.750000 - fcsr: 0x1004 - round.w.s 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s -45667 -45667.250000 - fcsr: 0x1004 - round.w.s -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s -347856 -347856.500000 - fcsr: 0x1004 - round.w.s 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.s -1 -1.250000 - fcsr: 0x1004 - round.w.s 23 23.062500 - fcsr: 0x1004 - round.w.d 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d 456 456.250000 - fcsr: 0x1004 - round.w.d 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d 1384 1384.500000 - fcsr: 0x1004 - round.w.d -7 -7.250000 - fcsr: 0x1004 - round.w.d 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d -5786 -5786.250000 - fcsr: 0x1004 - round.w.d 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d 0 0.015625 - fcsr: 0x1004 - round.w.d 0 0.031250 -@@ -266,45 +266,45 @@ - round.w.d -45786 -45786.500000 - fcsr: 0x1004 - round.w.d 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d 34 34.031250 - fcsr: 0x1004 - round.w.d 45787 45786.750000 - fcsr: 0x1004 - round.w.d 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d -45667 -45667.250000 - fcsr: 0x1004 - round.w.d -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d -347856 -347856.500000 - fcsr: 0x1004 - round.w.d 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - round.w.d -1 -1.250000 - fcsr: 0x1004 - round.w.d 23 23.062500 - fcsr: 0x1004 - trunc.w.s 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s 456 456.250000 - fcsr: 0x1004 - trunc.w.s 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s 1384 1384.500000 - fcsr: 0x1004 - trunc.w.s -7 -7.250000 - fcsr: 0x1004 - trunc.w.s 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s -5786 -5786.250000 - fcsr: 0x1004 - trunc.w.s 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s 0 0.015625 - fcsr: 0x1004 - trunc.w.s 0 0.031250 -@@ -314,45 +314,45 @@ - trunc.w.s -45786 -45786.500000 - fcsr: 0x1004 - trunc.w.s 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s 34 34.031250 - fcsr: 0x1004 - trunc.w.s 45786 45786.750000 - fcsr: 0x1004 - trunc.w.s 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s -45667 -45667.250000 - fcsr: 0x1004 - trunc.w.s -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s -347856 -347856.500000 - fcsr: 0x1004 - trunc.w.s 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.s -1 -1.250000 - fcsr: 0x1004 - trunc.w.s 23 23.062500 - fcsr: 0x1004 - trunc.w.d 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d 456 456.250000 - fcsr: 0x1004 - trunc.w.d 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d 1384 1384.500000 - fcsr: 0x1004 - trunc.w.d -7 -7.250000 - fcsr: 0x1004 - trunc.w.d 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d -5786 -5786.250000 - fcsr: 0x1004 - trunc.w.d 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d 0 0.015625 - fcsr: 0x1004 - trunc.w.d 0 0.031250 -@@ -362,23 +362,23 @@ - trunc.w.d -45786 -45786.500000 - fcsr: 0x1004 - trunc.w.d 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d 34 34.031250 - fcsr: 0x1004 - trunc.w.d 45786 45786.750000 - fcsr: 0x1004 - trunc.w.d 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d -45667 -45667.250000 - fcsr: 0x1004 - trunc.w.d -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d -347856 -347856.500000 - fcsr: 0x1004 - trunc.w.d 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - trunc.w.d -1 -1.250000 - fcsr: 0x1004 - trunc.w.d 23 23.062500 -@@ -386,807 +386,807 @@ - -------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode -------------------------- - roundig mode: near - cvt.d.s 0.000000 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 456.250000 456.250000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 3.000000 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -1.000000 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 1384.500000 1384.500000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -7.250000 -7.250000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 1000000000.000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -5786.250000 -5786.250000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 1752.000000 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 0.015625 0.015625 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 0.031250 0.031250 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -248562.750000 -248562.750000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -45786.500000 -45786.500000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 456.000000 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 34.031250 34.031250 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 45786.750000 45786.750000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 1752065.000000 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 107.000000 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -45667.250000 -45667.250000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -7.000000 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -347856.500000 -347856.500000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 356047.000000 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s -1.250000 -1.250000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.s 23.062500 23.062500 --fcsr: 0x4 -+fcsr: 0x0 - roundig mode: zero - cvt.d.s 0.000000 0.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 456.250000 456.250000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 3.000000 3.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -1.000000 -1.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 1384.500000 1384.500000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -7.250000 -7.250000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 1000000000.000000 1000000000.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -5786.250000 -5786.250000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 1752.000000 1752.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 0.015625 0.015625 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 0.031250 0.031250 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -248562.750000 -248562.750000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -45786.500000 -45786.500000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 456.000000 456.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 34.031250 34.031250 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 45786.750000 45786.750000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 1752065.000000 1752065.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 107.000000 107.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -45667.250000 -45667.250000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -7.000000 -7.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -347856.500000 -347856.500000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 356047.000000 356047.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s -1.250000 -1.250000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.s 23.062500 23.062500 --fcsr: 0x5 -+fcsr: 0x1 - roundig mode: +inf - cvt.d.s 0.000000 0.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 456.250000 456.250000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 3.000000 3.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -1.000000 -1.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 1384.500000 1384.500000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -7.250000 -7.250000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 1000000000.000000 1000000000.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -5786.250000 -5786.250000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 1752.000000 1752.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 0.015625 0.015625 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 0.031250 0.031250 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -248562.750000 -248562.750000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -45786.500000 -45786.500000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 456.000000 456.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 34.031250 34.031250 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 45786.750000 45786.750000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 1752065.000000 1752065.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 107.000000 107.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -45667.250000 -45667.250000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -7.000000 -7.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -347856.500000 -347856.500000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 356047.000000 356047.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s -1.250000 -1.250000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.s 23.062500 23.062500 --fcsr: 0x6 -+fcsr: 0x2 - roundig mode: -inf - cvt.d.s 0.000000 0.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 456.250000 456.250000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 3.000000 3.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -1.000000 -1.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 1384.500000 1384.500000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -7.250000 -7.250000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 1000000000.000000 1000000000.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -5786.250000 -5786.250000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 1752.000000 1752.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 0.015625 0.015625 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 0.031250 0.031250 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -248562.750000 -248562.750000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -45786.500000 -45786.500000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 456.000000 456.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 34.031250 34.031250 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 45786.750000 45786.750000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 1752065.000000 1752065.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 107.000000 107.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -45667.250000 -45667.250000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -7.000000 -7.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -347856.500000 -347856.500000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 356047.000000 356047.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s -1.250000 -1.250000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.d.s 23.062500 23.062500 --fcsr: 0x7 -+fcsr: 0x3 - roundig mode: near - cvt.d.w 0.000000 0 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 456.000000 456 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 3.000000 3 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -1.000000 -1 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -1.000000 -1 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 356.000000 356 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 1000000000.000000 1000000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -5786.000000 -5786 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 1752.000000 1752 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 24575.000000 24575 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 10.000000 10 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -248562.000000 -248562 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -45786.000000 -45786 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 456.000000 456 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 34.000000 34 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 45786.000000 45786 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 1752065.000000 1752065 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 107.000000 107 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -45667.000000 -45667 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -7.000000 -7 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -347856.000000 -347856 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w -2147483648.000000 -2147483648 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 268435455.000000 268435455 --fcsr: 0x4 -+fcsr: 0x0 - cvt.d.w 23.000000 23 --fcsr: 0x4 -+fcsr: 0x0 - roundig mode: zero - cvt.d.w 0.000000 0 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 456.000000 456 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 3.000000 3 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -1.000000 -1 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -1.000000 -1 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 356.000000 356 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 1000000000.000000 1000000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -5786.000000 -5786 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 1752.000000 1752 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 24575.000000 24575 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 10.000000 10 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -248562.000000 -248562 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -45786.000000 -45786 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 456.000000 456 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 34.000000 34 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 45786.000000 45786 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 1752065.000000 1752065 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 107.000000 107 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -45667.000000 -45667 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -7.000000 -7 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -347856.000000 -347856 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w -2147483648.000000 -2147483648 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 268435455.000000 268435455 --fcsr: 0x5 -+fcsr: 0x1 - cvt.d.w 23.000000 23 --fcsr: 0x5 -+fcsr: 0x1 - roundig mode: +inf - cvt.d.w 0.000000 0 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w 456.000000 456 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w 3.000000 3 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w -1.000000 -1 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w -1.000000 -1 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w 356.000000 356 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w 1000000000.000000 1000000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w -5786.000000 -5786 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w 1752.000000 1752 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w 24575.000000 24575 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w 10.000000 10 --fcsr: 0x6 -+fcsr: 0x2 - cvt.d.w -248562.000000 -248562 --fcsr: 0x6 -+fcsr: 0x2 - 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-45786.000000 -45786 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w 456.000000 456 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w 34.000000 34 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w 45786.000000 45786 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w 1752065.000000 1752065 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w 107.000000 107 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w -45667.000000 -45667 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w -7.000000 -7 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w -347856.000000 -347856 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w -2147483648.000000 -2147483648 --fcsr: 0x7 -+fcsr: 0x3 - cvt.s.w 268435440.000000 268435455 - fcsr: 0x1007 - cvt.s.w 23.000000 23 --fcsr: 0x7 -+fcsr: 0x3 - roundig mode: near - cvt.w.s 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s 456 456.250000 - fcsr: 0x1004 - cvt.w.s 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s 1384 1384.500000 - fcsr: 0x1004 - cvt.w.s -7 -7.250000 - fcsr: 0x1004 - cvt.w.s 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s -5786 -5786.250000 - fcsr: 0x1004 - cvt.w.s 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s 0 0.015625 - fcsr: 0x1004 - cvt.w.s 0 0.031250 -@@ -1196,23 +1196,23 @@ - cvt.w.s -45786 -45786.500000 - fcsr: 0x1004 - cvt.w.s 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s 34 34.031250 - fcsr: 0x1004 - cvt.w.s 45787 45786.750000 - fcsr: 0x1004 - cvt.w.s 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s -45667 -45667.250000 - fcsr: 0x1004 - cvt.w.s -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s -347856 -347856.500000 - fcsr: 0x1004 - cvt.w.s 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.s -1 -1.250000 - fcsr: 0x1004 - cvt.w.s 23 23.062500 -@@ -1219,23 +1219,23 @@ - fcsr: 0x1004 - roundig mode: zero - cvt.w.s 0 0.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s 456 456.250000 - fcsr: 0x1005 - cvt.w.s 3 3.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s -1 -1.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s 1384 1384.500000 - fcsr: 0x1005 - cvt.w.s -7 -7.250000 - fcsr: 0x1005 - cvt.w.s 1000000000 1000000000.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s -5786 -5786.250000 - fcsr: 0x1005 - cvt.w.s 1752 1752.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s 0 0.015625 - fcsr: 0x1005 - cvt.w.s 0 0.031250 -@@ -1245,23 +1245,23 @@ - cvt.w.s -45786 -45786.500000 - fcsr: 0x1005 - cvt.w.s 456 456.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s 34 34.031250 - fcsr: 0x1005 - cvt.w.s 45786 45786.750000 - fcsr: 0x1005 - cvt.w.s 1752065 1752065.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s 107 107.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s -45667 -45667.250000 - fcsr: 0x1005 - cvt.w.s -7 -7.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s -347856 -347856.500000 - fcsr: 0x1005 - cvt.w.s 356047 356047.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.s -1 -1.250000 - fcsr: 0x1005 - cvt.w.s 23 23.062500 -@@ -1268,23 +1268,23 @@ - fcsr: 0x1005 - roundig mode: +inf - cvt.w.s 0 0.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s 457 456.250000 - fcsr: 0x1006 - cvt.w.s 3 3.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s -1 -1.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s 1385 1384.500000 - fcsr: 0x1006 - cvt.w.s -7 -7.250000 - fcsr: 0x1006 - cvt.w.s 1000000000 1000000000.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s -5786 -5786.250000 - fcsr: 0x1006 - cvt.w.s 1752 1752.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s 1 0.015625 - fcsr: 0x1006 - cvt.w.s 1 0.031250 -@@ -1294,23 +1294,23 @@ - cvt.w.s -45786 -45786.500000 - fcsr: 0x1006 - cvt.w.s 456 456.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s 35 34.031250 - fcsr: 0x1006 - cvt.w.s 45787 45786.750000 - fcsr: 0x1006 - cvt.w.s 1752065 1752065.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s 107 107.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s -45667 -45667.250000 - fcsr: 0x1006 - cvt.w.s -7 -7.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s -347856 -347856.500000 - fcsr: 0x1006 - cvt.w.s 356047 356047.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.s -1 -1.250000 - fcsr: 0x1006 - cvt.w.s 24 23.062500 -@@ -1317,23 +1317,23 @@ - fcsr: 0x1006 - roundig mode: -inf - cvt.w.s 0 0.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s 456 456.250000 - fcsr: 0x1007 - cvt.w.s 3 3.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s -1 -1.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s 1384 1384.500000 - fcsr: 0x1007 - cvt.w.s -8 -7.250000 - fcsr: 0x1007 - cvt.w.s 1000000000 1000000000.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s -5787 -5786.250000 - fcsr: 0x1007 - cvt.w.s 1752 1752.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s 0 0.015625 - fcsr: 0x1007 - cvt.w.s 0 0.031250 -@@ -1343,23 +1343,23 @@ - cvt.w.s -45787 -45786.500000 - fcsr: 0x1007 - cvt.w.s 456 456.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s 34 34.031250 - fcsr: 0x1007 - cvt.w.s 45786 45786.750000 - fcsr: 0x1007 - cvt.w.s 1752065 1752065.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s 107 107.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s -45668 -45667.250000 - fcsr: 0x1007 - cvt.w.s -7 -7.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s -347857 -347856.500000 - fcsr: 0x1007 - cvt.w.s 356047 356047.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.s -2 -1.250000 - fcsr: 0x1007 - cvt.w.s 23 23.062500 -@@ -1366,23 +1366,23 @@ - fcsr: 0x1007 - roundig mode: near - cvt.w.d 0 0.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d 456 456.250000 - fcsr: 0x1004 - cvt.w.d 3 3.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d -1 -1.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d 1384 1384.500000 - fcsr: 0x1004 - cvt.w.d -7 -7.250000 - fcsr: 0x1004 - cvt.w.d 1000000000 1000000000.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d -5786 -5786.250000 - fcsr: 0x1004 - cvt.w.d 1752 1752.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d 0 0.015625 - fcsr: 0x1004 - cvt.w.d 0 0.031250 -@@ -1392,23 +1392,23 @@ - cvt.w.d -45786 -45786.500000 - fcsr: 0x1004 - cvt.w.d 456 456.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d 34 34.031250 - fcsr: 0x1004 - cvt.w.d 45787 45786.750000 - fcsr: 0x1004 - cvt.w.d 1752065 1752065.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d 107 107.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d -45667 -45667.250000 - fcsr: 0x1004 - cvt.w.d -7 -7.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d -347856 -347856.500000 - fcsr: 0x1004 - cvt.w.d 356047 356047.000000 --fcsr: 0x4 -+fcsr: 0x0 - cvt.w.d -1 -1.250000 - fcsr: 0x1004 - cvt.w.d 23 23.062500 -@@ -1415,23 +1415,23 @@ - fcsr: 0x1004 - roundig mode: zero - cvt.w.d 0 0.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d 456 456.250000 - fcsr: 0x1005 - cvt.w.d 3 3.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d -1 -1.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d 1384 1384.500000 - fcsr: 0x1005 - cvt.w.d -7 -7.250000 - fcsr: 0x1005 - cvt.w.d 1000000000 1000000000.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d -5786 -5786.250000 - fcsr: 0x1005 - cvt.w.d 1752 1752.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d 0 0.015625 - fcsr: 0x1005 - cvt.w.d 0 0.031250 -@@ -1441,23 +1441,23 @@ - cvt.w.d -45786 -45786.500000 - fcsr: 0x1005 - cvt.w.d 456 456.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d 34 34.031250 - fcsr: 0x1005 - cvt.w.d 45786 45786.750000 - fcsr: 0x1005 - cvt.w.d 1752065 1752065.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d 107 107.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d -45667 -45667.250000 - fcsr: 0x1005 - cvt.w.d -7 -7.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d -347856 -347856.500000 - fcsr: 0x1005 - cvt.w.d 356047 356047.000000 --fcsr: 0x5 -+fcsr: 0x1 - cvt.w.d -1 -1.250000 - fcsr: 0x1005 - cvt.w.d 23 23.062500 -@@ -1464,23 +1464,23 @@ - fcsr: 0x1005 - roundig mode: +inf - cvt.w.d 0 0.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d 457 456.250000 - fcsr: 0x1006 - cvt.w.d 3 3.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d -1 -1.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d 1385 1384.500000 - fcsr: 0x1006 - cvt.w.d -7 -7.250000 - fcsr: 0x1006 - cvt.w.d 1000000000 1000000000.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d -5786 -5786.250000 - fcsr: 0x1006 - cvt.w.d 1752 1752.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d 1 0.015625 - fcsr: 0x1006 - cvt.w.d 1 0.031250 -@@ -1490,23 +1490,23 @@ - cvt.w.d -45786 -45786.500000 - fcsr: 0x1006 - cvt.w.d 456 456.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d 35 34.031250 - fcsr: 0x1006 - cvt.w.d 45787 45786.750000 - fcsr: 0x1006 - cvt.w.d 1752065 1752065.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d 107 107.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d -45667 -45667.250000 - fcsr: 0x1006 - cvt.w.d -7 -7.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d -347856 -347856.500000 - fcsr: 0x1006 - cvt.w.d 356047 356047.000000 --fcsr: 0x6 -+fcsr: 0x2 - cvt.w.d -1 -1.250000 - fcsr: 0x1006 - cvt.w.d 24 23.062500 -@@ -1513,23 +1513,23 @@ - fcsr: 0x1006 - roundig mode: -inf - cvt.w.d 0 0.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d 456 456.250000 - fcsr: 0x1007 - cvt.w.d 3 3.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d -1 -1.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d 1384 1384.500000 - fcsr: 0x1007 - cvt.w.d -8 -7.250000 - fcsr: 0x1007 - cvt.w.d 1000000000 1000000000.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d -5787 -5786.250000 - fcsr: 0x1007 - cvt.w.d 1752 1752.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d 0 0.015625 - fcsr: 0x1007 - cvt.w.d 0 0.031250 -@@ -1539,23 +1539,23 @@ - cvt.w.d -45787 -45786.500000 - fcsr: 0x1007 - cvt.w.d 456 456.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d 34 34.031250 - fcsr: 0x1007 - cvt.w.d 45786 45786.750000 - fcsr: 0x1007 - cvt.w.d 1752065 1752065.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d 107 107.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d -45668 -45667.250000 - fcsr: 0x1007 - cvt.w.d -7 -7.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d -347857 -347856.500000 - fcsr: 0x1007 - cvt.w.d 356047 356047.000000 --fcsr: 0x7 -+fcsr: 0x3 - cvt.w.d -2 -1.250000 - fcsr: 0x1007 - cvt.w.d 23 23.062500 -Index: none/tests/mips32/round_fpu64.c -=================================================================== ---- none/tests/mips32/round_fpu64.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/round_fpu64.c (.../trunk) (revision 13981) -@@ -0,0 +1,204 @@ -+#include -+#include -+#include -+#include -+ -+#define MAX_ARR 24 -+#define PERROR \ -+ printf("This test is testing mips32r2 instructions in fpu64 mode.\n"); -+#define FLAGS_RM_MASK 0xFFFFFFFF -+ -+typedef enum { -+ CVTLS, CVTLD, ROUNDLS, ROUNDLD, -+ TRUNCLS, TRUNCLD, FLOORLS, FLOORLD, -+ CEILLS, CEILLD -+} flt_round_op_t; -+ -+const char *flt_round_op_names[] = { -+ "cvt.l.s", "cvt.l.d", "round.l.s", "round.l.d", -+ "trunc.l.s", "trunc.l.d", "floor.l.s", "floor.l.d" -+ "ceil.l.s", "ceil.l.d" -+}; -+ -+typedef enum { -+ TO_NEAREST=0, TO_ZERO, TO_PLUS_INFINITY, TO_MINUS_INFINITY } round_mode_t; -+char *round_mode_name[] = { "near", "zero", "+inf", "-inf" }; -+ -+const float fs_f[] = { -+ 0, 456.25, 3, -1, -+ 1384.5, -7.25, 1000000000, -5786.25, -+ 1752, 0.015625, 0.03125, -248562.75, -+ -45786.5, 456, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7, -+ -347856.5, 356047, -1.25, 23.0625 -+}; -+ -+const double fs_d[] = { -+ 0, 456.25, 3, -1, -+ 1384.5, -7.25, 1000000000, -5786.25, -+ 1752, 0.015625, 0.03125, -24856226678933.75, -+ -45786.5, 456, 34.03125, 45786.75, -+ 1752065, 107, -45667.25, -7, -+ -347856.5, 356047, -1.25, 23.0625 -+}; -+ -+#define UNOPsl(op) \ -+ __asm__ __volatile__( \ -+ op" $f0, %2" "\n\t" \ -+ "sdc1 $f0, 0(%1)" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ : "=r" (fcsr) \ -+ : "r"(&fd_l), "f"(fs_f[i]) \ -+ : "$f0" \ -+ ); -+ -+#define UNOPdl(op) \ -+ __asm__ __volatile__( \ -+ op" $f0, %2" "\n\t" \ -+ "sdc1 $f0, 0(%1)" "\n\t" \ -+ "cfc1 %0, $31" "\n\t" \ -+ : "=r" (fcsr) \ -+ : "r"(&fd_l), "f"(fs_d[i]) \ -+ : "$f0" \ -+ ); -+ -+#define TEST_FPU64 \ -+ __asm__ __volatile__( \ -+ "cvt.l.s $f0, $f0" "\n\t" \ -+ : \ -+ : \ -+ : "$f0" \ -+ ); -+ -+#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64) -+void set_rounding_mode(round_mode_t mode) -+{ -+ switch(mode) { -+ case TO_NEAREST: -+ __asm__ volatile("ctc1 $zero, $31" "\n\t"); -+ break; -+ case TO_ZERO: -+ __asm__ volatile("li $t0, 0x1" "\n\t" -+ "ctc1 $t0, $31" "\n\t"); -+ break; -+ case TO_PLUS_INFINITY: -+ __asm__ volatile("li $t0, 0x2" "\n\t" -+ "ctc1 $t0, $31" "\n\t"); -+ break; -+ case TO_MINUS_INFINITY: -+ __asm__ volatile("li $t0, 0x3" "\n\t" -+ "ctc1 $t0, $31" "\n\t"); -+ break; -+ } -+} -+ -+struct test { -+ void (*test)(void); -+ int sig; -+ int code; -+}; -+ -+static void handler(int sig) -+{ -+ PERROR; -+ exit(0); -+} -+ -+int FCSRRoundingMode(flt_round_op_t op) -+{ -+ long long int fd_l; -+ int i; -+ int fcsr = 0; -+ round_mode_t rm; -+ for (rm = TO_NEAREST; rm <= TO_MINUS_INFINITY; rm ++) { -+ printf("roundig mode: %s\n", round_mode_name[rm]); -+ for (i = 0; i < MAX_ARR; i++) { -+ set_rounding_mode(rm); -+ switch(op) { -+ case CVTLS: -+ UNOPsl("cvt.l.s"); -+ printf("%s %lld %f\n", -+ flt_round_op_names[op], fd_l, fs_f[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case CVTLD: -+ UNOPdl("cvt.l.d"); -+ printf("%s %lld %lf\n", -+ flt_round_op_names[op], fd_l, fs_d[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case ROUNDLS: -+ UNOPsl("round.l.s"); -+ printf("%s %lld %f\n", -+ flt_round_op_names[op], fd_l, fs_f[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case ROUNDLD: -+ UNOPdl("round.l.d"); -+ printf("%s %lld %lf\n", -+ flt_round_op_names[op], fd_l, fs_d[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case TRUNCLS: -+ UNOPsl("trunc.l.s"); -+ printf("%s %lld %f\n", -+ flt_round_op_names[op], fd_l, fs_f[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case TRUNCLD: -+ UNOPdl("trunc.l.d"); -+ printf("%s %lld %lf\n", -+ flt_round_op_names[op], fd_l, fs_d[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case FLOORLS: -+ UNOPsl("floor.l.s"); -+ printf("%s %lld %f\n", -+ flt_round_op_names[op], fd_l, fs_f[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case FLOORLD: -+ UNOPdl("floor.l.d"); -+ printf("%s %lld %lf\n", -+ flt_round_op_names[op], fd_l, fs_d[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case CEILLS: -+ UNOPsl("ceil.l.s"); -+ printf("%s %lld %f\n", -+ flt_round_op_names[op], fd_l, fs_f[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ case CEILLD: -+ UNOPdl("ceil.l.d"); -+ printf("%s %lld %lf\n", -+ flt_round_op_names[op], fd_l, fs_d[i]); -+ printf("fcsr: 0x%x\n", fcsr & FLAGS_RM_MASK); -+ break; -+ default: -+ printf("error\n"); -+ break; -+ } -+ } -+ } -+ return 0; -+} -+#endif -+ -+ -+int main() -+{ -+#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64) -+ flt_round_op_t op; -+ signal(SIGILL, handler); -+ /* Test fpu64 mode. */ -+ TEST_FPU64; -+ printf("-------------------------- %s --------------------------\n", -+ "test FPU Conversion Operations Using the FCSR Rounding Mode"); -+ for (op = CVTLS; op <= CEILLD; op++) -+ FCSRRoundingMode(op); -+#else -+ PERROR; -+#endif -+ return 0; -+} -Index: none/tests/mips32/round_fpu64.stderr.exp -=================================================================== -Index: none/tests/mips32/round_fpu64.stdout.exp -=================================================================== ---- none/tests/mips32/round_fpu64.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/round_fpu64.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,1961 @@ -+-------------------------- test FPU Conversion Operations Using the FCSR Rounding Mode -------------------------- -+roundig mode: near -+cvt.l.s 0 0.000000 -+fcsr: 0x0 -+cvt.l.s 456 456.250000 -+fcsr: 0x1004 -+cvt.l.s 3 3.000000 -+fcsr: 0x0 -+cvt.l.s -1 -1.000000 -+fcsr: 0x0 -+cvt.l.s 1384 1384.500000 -+fcsr: 0x1004 -+cvt.l.s -7 -7.250000 -+fcsr: 0x1004 -+cvt.l.s 1000000000 1000000000.000000 -+fcsr: 0x0 -+cvt.l.s -5786 -5786.250000 -+fcsr: 0x1004 -+cvt.l.s 1752 1752.000000 -+fcsr: 0x0 -+cvt.l.s 0 0.015625 -+fcsr: 0x1004 -+cvt.l.s 0 0.031250 -+fcsr: 0x1004 -+cvt.l.s -248563 -248562.750000 -+fcsr: 0x1004 -+cvt.l.s -45786 -45786.500000 -+fcsr: 0x1004 -+cvt.l.s 456 456.000000 -+fcsr: 0x0 -+cvt.l.s 34 34.031250 -+fcsr: 0x1004 -+cvt.l.s 45787 45786.750000 -+fcsr: 0x1004 -+cvt.l.s 1752065 1752065.000000 -+fcsr: 0x0 -+cvt.l.s 107 107.000000 -+fcsr: 0x0 -+cvt.l.s -45667 -45667.250000 -+fcsr: 0x1004 -+cvt.l.s -7 -7.000000 -+fcsr: 0x0 -+cvt.l.s -347856 -347856.500000 -+fcsr: 0x1004 -+cvt.l.s 356047 356047.000000 -+fcsr: 0x0 -+cvt.l.s -1 -1.250000 -+fcsr: 0x1004 -+cvt.l.s 23 23.062500 -+fcsr: 0x1004 -+roundig mode: zero -+cvt.l.s 0 0.000000 -+fcsr: 0x1 -+cvt.l.s 456 456.250000 -+fcsr: 0x1005 -+cvt.l.s 3 3.000000 -+fcsr: 0x1 -+cvt.l.s -1 -1.000000 -+fcsr: 0x1 -+cvt.l.s 1384 1384.500000 -+fcsr: 0x1005 -+cvt.l.s -7 -7.250000 -+fcsr: 0x1005 -+cvt.l.s 1000000000 1000000000.000000 -+fcsr: 0x1 -+cvt.l.s -5786 -5786.250000 -+fcsr: 0x1005 -+cvt.l.s 1752 1752.000000 -+fcsr: 0x1 -+cvt.l.s 0 0.015625 -+fcsr: 0x1005 -+cvt.l.s 0 0.031250 -+fcsr: 0x1005 -+cvt.l.s -248562 -248562.750000 -+fcsr: 0x1005 -+cvt.l.s -45786 -45786.500000 -+fcsr: 0x1005 -+cvt.l.s 456 456.000000 -+fcsr: 0x1 -+cvt.l.s 34 34.031250 -+fcsr: 0x1005 -+cvt.l.s 45786 45786.750000 -+fcsr: 0x1005 -+cvt.l.s 1752065 1752065.000000 -+fcsr: 0x1 -+cvt.l.s 107 107.000000 -+fcsr: 0x1 -+cvt.l.s -45667 -45667.250000 -+fcsr: 0x1005 -+cvt.l.s -7 -7.000000 -+fcsr: 0x1 -+cvt.l.s -347856 -347856.500000 -+fcsr: 0x1005 -+cvt.l.s 356047 356047.000000 -+fcsr: 0x1 -+cvt.l.s -1 -1.250000 -+fcsr: 0x1005 -+cvt.l.s 23 23.062500 -+fcsr: 0x1005 -+roundig mode: +inf -+cvt.l.s 0 0.000000 -+fcsr: 0x2 -+cvt.l.s 457 456.250000 -+fcsr: 0x1006 -+cvt.l.s 3 3.000000 -+fcsr: 0x2 -+cvt.l.s -1 -1.000000 -+fcsr: 0x2 -+cvt.l.s 1385 1384.500000 -+fcsr: 0x1006 -+cvt.l.s -7 -7.250000 -+fcsr: 0x1006 -+cvt.l.s 1000000000 1000000000.000000 -+fcsr: 0x2 -+cvt.l.s -5786 -5786.250000 -+fcsr: 0x1006 -+cvt.l.s 1752 1752.000000 -+fcsr: 0x2 -+cvt.l.s 1 0.015625 -+fcsr: 0x1006 -+cvt.l.s 1 0.031250 -+fcsr: 0x1006 -+cvt.l.s -248562 -248562.750000 -+fcsr: 0x1006 -+cvt.l.s -45786 -45786.500000 -+fcsr: 0x1006 -+cvt.l.s 456 456.000000 -+fcsr: 0x2 -+cvt.l.s 35 34.031250 -+fcsr: 0x1006 -+cvt.l.s 45787 45786.750000 -+fcsr: 0x1006 -+cvt.l.s 1752065 1752065.000000 -+fcsr: 0x2 -+cvt.l.s 107 107.000000 -+fcsr: 0x2 -+cvt.l.s -45667 -45667.250000 -+fcsr: 0x1006 -+cvt.l.s -7 -7.000000 -+fcsr: 0x2 -+cvt.l.s -347856 -347856.500000 -+fcsr: 0x1006 -+cvt.l.s 356047 356047.000000 -+fcsr: 0x2 -+cvt.l.s -1 -1.250000 -+fcsr: 0x1006 -+cvt.l.s 24 23.062500 -+fcsr: 0x1006 -+roundig mode: -inf -+cvt.l.s 0 0.000000 -+fcsr: 0x3 -+cvt.l.s 456 456.250000 -+fcsr: 0x1007 -+cvt.l.s 3 3.000000 -+fcsr: 0x3 -+cvt.l.s -1 -1.000000 -+fcsr: 0x3 -+cvt.l.s 1384 1384.500000 -+fcsr: 0x1007 -+cvt.l.s -8 -7.250000 -+fcsr: 0x1007 -+cvt.l.s 1000000000 1000000000.000000 -+fcsr: 0x3 -+cvt.l.s -5787 -5786.250000 -+fcsr: 0x1007 -+cvt.l.s 1752 1752.000000 -+fcsr: 0x3 -+cvt.l.s 0 0.015625 -+fcsr: 0x1007 -+cvt.l.s 0 0.031250 -+fcsr: 0x1007 -+cvt.l.s -248563 -248562.750000 -+fcsr: 0x1007 -+cvt.l.s -45787 -45786.500000 -+fcsr: 0x1007 -+cvt.l.s 456 456.000000 -+fcsr: 0x3 -+cvt.l.s 34 34.031250 -+fcsr: 0x1007 -+cvt.l.s 45786 45786.750000 -+fcsr: 0x1007 -+cvt.l.s 1752065 1752065.000000 -+fcsr: 0x3 -+cvt.l.s 107 107.000000 -+fcsr: 0x3 -+cvt.l.s -45668 -45667.250000 -+fcsr: 0x1007 -+cvt.l.s -7 -7.000000 -+fcsr: 0x3 -+cvt.l.s -347857 -347856.500000 -+fcsr: 0x1007 -+cvt.l.s 356047 356047.000000 -+fcsr: 0x3 -+cvt.l.s -2 -1.250000 -+fcsr: 0x1007 -+cvt.l.s 23 23.062500 -+fcsr: 0x1007 -+roundig mode: near -+cvt.l.d 0 0.000000 -+fcsr: 0x0 -+cvt.l.d 456 456.250000 -+fcsr: 0x1004 -+cvt.l.d 3 3.000000 -+fcsr: 0x0 -+cvt.l.d -1 -1.000000 -+fcsr: 0x0 -+cvt.l.d 1384 1384.500000 -+fcsr: 0x1004 -+cvt.l.d -7 -7.250000 -+fcsr: 0x1004 -+cvt.l.d 1000000000 1000000000.000000 -+fcsr: 0x0 -+cvt.l.d -5786 -5786.250000 -+fcsr: 0x1004 -+cvt.l.d 1752 1752.000000 -+fcsr: 0x0 -+cvt.l.d 0 0.015625 -+fcsr: 0x1004 -+cvt.l.d 0 0.031250 -+fcsr: 0x1004 -+cvt.l.d -24856226678934 -24856226678933.750000 -+fcsr: 0x1004 -+cvt.l.d -45786 -45786.500000 -+fcsr: 0x1004 -+cvt.l.d 456 456.000000 -+fcsr: 0x0 -+cvt.l.d 34 34.031250 -+fcsr: 0x1004 -+cvt.l.d 45787 45786.750000 -+fcsr: 0x1004 -+cvt.l.d 1752065 1752065.000000 -+fcsr: 0x0 -+cvt.l.d 107 107.000000 -+fcsr: 0x0 -+cvt.l.d -45667 -45667.250000 -+fcsr: 0x1004 -+cvt.l.d -7 -7.000000 -+fcsr: 0x0 -+cvt.l.d -347856 -347856.500000 -+fcsr: 0x1004 -+cvt.l.d 356047 356047.000000 -+fcsr: 0x0 -+cvt.l.d -1 -1.250000 -+fcsr: 0x1004 -+cvt.l.d 23 23.062500 -+fcsr: 0x1004 -+roundig mode: zero -+cvt.l.d 0 0.000000 -+fcsr: 0x1 -+cvt.l.d 456 456.250000 -+fcsr: 0x1005 -+cvt.l.d 3 3.000000 -+fcsr: 0x1 -+cvt.l.d -1 -1.000000 -+fcsr: 0x1 -+cvt.l.d 1384 1384.500000 -+fcsr: 0x1005 -+cvt.l.d -7 -7.250000 -+fcsr: 0x1005 -+cvt.l.d 1000000000 1000000000.000000 -+fcsr: 0x1 -+cvt.l.d -5786 -5786.250000 -+fcsr: 0x1005 -+cvt.l.d 1752 1752.000000 -+fcsr: 0x1 -+cvt.l.d 0 0.015625 -+fcsr: 0x1005 -+cvt.l.d 0 0.031250 -+fcsr: 0x1005 -+cvt.l.d -24856226678933 -24856226678933.750000 -+fcsr: 0x1005 -+cvt.l.d -45786 -45786.500000 -+fcsr: 0x1005 -+cvt.l.d 456 456.000000 -+fcsr: 0x1 -+cvt.l.d 34 34.031250 -+fcsr: 0x1005 -+cvt.l.d 45786 45786.750000 -+fcsr: 0x1005 -+cvt.l.d 1752065 1752065.000000 -+fcsr: 0x1 -+cvt.l.d 107 107.000000 -+fcsr: 0x1 -+cvt.l.d -45667 -45667.250000 -+fcsr: 0x1005 -+cvt.l.d -7 -7.000000 -+fcsr: 0x1 -+cvt.l.d -347856 -347856.500000 -+fcsr: 0x1005 -+cvt.l.d 356047 356047.000000 -+fcsr: 0x1 -+cvt.l.d -1 -1.250000 -+fcsr: 0x1005 -+cvt.l.d 23 23.062500 -+fcsr: 0x1005 -+roundig mode: +inf -+cvt.l.d 0 0.000000 -+fcsr: 0x2 -+cvt.l.d 457 456.250000 -+fcsr: 0x1006 -+cvt.l.d 3 3.000000 -+fcsr: 0x2 -+cvt.l.d -1 -1.000000 -+fcsr: 0x2 -+cvt.l.d 1385 1384.500000 -+fcsr: 0x1006 -+cvt.l.d -7 -7.250000 -+fcsr: 0x1006 -+cvt.l.d 1000000000 1000000000.000000 -+fcsr: 0x2 -+cvt.l.d -5786 -5786.250000 -+fcsr: 0x1006 -+cvt.l.d 1752 1752.000000 -+fcsr: 0x2 -+cvt.l.d 1 0.015625 -+fcsr: 0x1006 -+cvt.l.d 1 0.031250 -+fcsr: 0x1006 -+cvt.l.d -24856226678933 -24856226678933.750000 -+fcsr: 0x1006 -+cvt.l.d -45786 -45786.500000 -+fcsr: 0x1006 -+cvt.l.d 456 456.000000 -+fcsr: 0x2 -+cvt.l.d 35 34.031250 -+fcsr: 0x1006 -+cvt.l.d 45787 45786.750000 -+fcsr: 0x1006 -+cvt.l.d 1752065 1752065.000000 -+fcsr: 0x2 -+cvt.l.d 107 107.000000 -+fcsr: 0x2 -+cvt.l.d -45667 -45667.250000 -+fcsr: 0x1006 -+cvt.l.d -7 -7.000000 -+fcsr: 0x2 -+cvt.l.d -347856 -347856.500000 -+fcsr: 0x1006 -+cvt.l.d 356047 356047.000000 -+fcsr: 0x2 -+cvt.l.d -1 -1.250000 -+fcsr: 0x1006 -+cvt.l.d 24 23.062500 -+fcsr: 0x1006 -+roundig mode: -inf -+cvt.l.d 0 0.000000 -+fcsr: 0x3 -+cvt.l.d 456 456.250000 -+fcsr: 0x1007 -+cvt.l.d 3 3.000000 -+fcsr: 0x3 -+cvt.l.d -1 -1.000000 -+fcsr: 0x3 -+cvt.l.d 1384 1384.500000 -+fcsr: 0x1007 -+cvt.l.d -8 -7.250000 -+fcsr: 0x1007 -+cvt.l.d 1000000000 1000000000.000000 -+fcsr: 0x3 -+cvt.l.d -5787 -5786.250000 -+fcsr: 0x1007 -+cvt.l.d 1752 1752.000000 -+fcsr: 0x3 -+cvt.l.d 0 0.015625 -+fcsr: 0x1007 -+cvt.l.d 0 0.031250 -+fcsr: 0x1007 -+cvt.l.d -24856226678934 -24856226678933.750000 -+fcsr: 0x1007 -+cvt.l.d -45787 -45786.500000 -+fcsr: 0x1007 -+cvt.l.d 456 456.000000 -+fcsr: 0x3 -+cvt.l.d 34 34.031250 -+fcsr: 0x1007 -+cvt.l.d 45786 45786.750000 -+fcsr: 0x1007 -+cvt.l.d 1752065 1752065.000000 -+fcsr: 0x3 -+cvt.l.d 107 107.000000 -+fcsr: 0x3 -+cvt.l.d -45668 -45667.250000 -+fcsr: 0x1007 -+cvt.l.d -7 -7.000000 -+fcsr: 0x3 -+cvt.l.d -347857 -347856.500000 -+fcsr: 0x1007 -+cvt.l.d 356047 356047.000000 -+fcsr: 0x3 -+cvt.l.d -2 -1.250000 -+fcsr: 0x1007 -+cvt.l.d 23 23.062500 -+fcsr: 0x1007 -+roundig mode: near -+round.l.s 0 0.000000 -+fcsr: 0x0 -+round.l.s 456 456.250000 -+fcsr: 0x1004 -+round.l.s 3 3.000000 -+fcsr: 0x0 -+round.l.s -1 -1.000000 -+fcsr: 0x0 -+round.l.s 1384 1384.500000 -+fcsr: 0x1004 -+round.l.s -7 -7.250000 -+fcsr: 0x1004 -+round.l.s 1000000000 1000000000.000000 -+fcsr: 0x0 -+round.l.s -5786 -5786.250000 -+fcsr: 0x1004 -+round.l.s 1752 1752.000000 -+fcsr: 0x0 -+round.l.s 0 0.015625 -+fcsr: 0x1004 -+round.l.s 0 0.031250 -+fcsr: 0x1004 -+round.l.s -248563 -248562.750000 -+fcsr: 0x1004 -+round.l.s -45786 -45786.500000 -+fcsr: 0x1004 -+round.l.s 456 456.000000 -+fcsr: 0x0 -+round.l.s 34 34.031250 -+fcsr: 0x1004 -+round.l.s 45787 45786.750000 -+fcsr: 0x1004 -+round.l.s 1752065 1752065.000000 -+fcsr: 0x0 -+round.l.s 107 107.000000 -+fcsr: 0x0 -+round.l.s -45667 -45667.250000 -+fcsr: 0x1004 -+round.l.s -7 -7.000000 -+fcsr: 0x0 -+round.l.s -347856 -347856.500000 -+fcsr: 0x1004 -+round.l.s 356047 356047.000000 -+fcsr: 0x0 -+round.l.s -1 -1.250000 -+fcsr: 0x1004 -+round.l.s 23 23.062500 -+fcsr: 0x1004 -+roundig mode: zero -+round.l.s 0 0.000000 -+fcsr: 0x1 -+round.l.s 456 456.250000 -+fcsr: 0x1005 -+round.l.s 3 3.000000 -+fcsr: 0x1 -+round.l.s -1 -1.000000 -+fcsr: 0x1 -+round.l.s 1384 1384.500000 -+fcsr: 0x1005 -+round.l.s -7 -7.250000 -+fcsr: 0x1005 -+round.l.s 1000000000 1000000000.000000 -+fcsr: 0x1 -+round.l.s -5786 -5786.250000 -+fcsr: 0x1005 -+round.l.s 1752 1752.000000 -+fcsr: 0x1 -+round.l.s 0 0.015625 -+fcsr: 0x1005 -+round.l.s 0 0.031250 -+fcsr: 0x1005 -+round.l.s -248563 -248562.750000 -+fcsr: 0x1005 -+round.l.s -45786 -45786.500000 -+fcsr: 0x1005 -+round.l.s 456 456.000000 -+fcsr: 0x1 -+round.l.s 34 34.031250 -+fcsr: 0x1005 -+round.l.s 45787 45786.750000 -+fcsr: 0x1005 -+round.l.s 1752065 1752065.000000 -+fcsr: 0x1 -+round.l.s 107 107.000000 -+fcsr: 0x1 -+round.l.s -45667 -45667.250000 -+fcsr: 0x1005 -+round.l.s -7 -7.000000 -+fcsr: 0x1 -+round.l.s -347856 -347856.500000 -+fcsr: 0x1005 -+round.l.s 356047 356047.000000 -+fcsr: 0x1 -+round.l.s -1 -1.250000 -+fcsr: 0x1005 -+round.l.s 23 23.062500 -+fcsr: 0x1005 -+roundig mode: +inf -+round.l.s 0 0.000000 -+fcsr: 0x2 -+round.l.s 456 456.250000 -+fcsr: 0x1006 -+round.l.s 3 3.000000 -+fcsr: 0x2 -+round.l.s -1 -1.000000 -+fcsr: 0x2 -+round.l.s 1384 1384.500000 -+fcsr: 0x1006 -+round.l.s -7 -7.250000 -+fcsr: 0x1006 -+round.l.s 1000000000 1000000000.000000 -+fcsr: 0x2 -+round.l.s -5786 -5786.250000 -+fcsr: 0x1006 -+round.l.s 1752 1752.000000 -+fcsr: 0x2 -+round.l.s 0 0.015625 -+fcsr: 0x1006 -+round.l.s 0 0.031250 -+fcsr: 0x1006 -+round.l.s -248563 -248562.750000 -+fcsr: 0x1006 -+round.l.s -45786 -45786.500000 -+fcsr: 0x1006 -+round.l.s 456 456.000000 -+fcsr: 0x2 -+round.l.s 34 34.031250 -+fcsr: 0x1006 -+round.l.s 45787 45786.750000 -+fcsr: 0x1006 -+round.l.s 1752065 1752065.000000 -+fcsr: 0x2 -+round.l.s 107 107.000000 -+fcsr: 0x2 -+round.l.s -45667 -45667.250000 -+fcsr: 0x1006 -+round.l.s -7 -7.000000 -+fcsr: 0x2 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-1.250000 -+fcsr: 0x1004 -+near 24 23.062500 -+fcsr: 0x1004 -+roundig mode: zero -+near 0 0.000000 -+fcsr: 0x1 -+near 457 456.250000 -+fcsr: 0x1005 -+near 3 3.000000 -+fcsr: 0x1 -+near -1 -1.000000 -+fcsr: 0x1 -+near 1385 1384.500000 -+fcsr: 0x1005 -+near -7 -7.250000 -+fcsr: 0x1005 -+near 1000000000 1000000000.000000 -+fcsr: 0x1 -+near -5786 -5786.250000 -+fcsr: 0x1005 -+near 1752 1752.000000 -+fcsr: 0x1 -+near 1 0.015625 -+fcsr: 0x1005 -+near 1 0.031250 -+fcsr: 0x1005 -+near -24856226678933 -24856226678933.750000 -+fcsr: 0x1005 -+near -45786 -45786.500000 -+fcsr: 0x1005 -+near 456 456.000000 -+fcsr: 0x1 -+near 35 34.031250 -+fcsr: 0x1005 -+near 45787 45786.750000 -+fcsr: 0x1005 -+near 1752065 1752065.000000 -+fcsr: 0x1 -+near 107 107.000000 -+fcsr: 0x1 -+near -45667 -45667.250000 -+fcsr: 0x1005 -+near -7 -7.000000 -+fcsr: 0x1 -+near -347856 -347856.500000 -+fcsr: 0x1005 -+near 356047 356047.000000 -+fcsr: 0x1 -+near -1 -1.250000 -+fcsr: 0x1005 -+near 24 23.062500 -+fcsr: 0x1005 -+roundig mode: +inf -+near 0 0.000000 -+fcsr: 0x2 -+near 457 456.250000 -+fcsr: 0x1006 -+near 3 3.000000 -+fcsr: 0x2 -+near -1 -1.000000 -+fcsr: 0x2 -+near 1385 1384.500000 -+fcsr: 0x1006 -+near -7 -7.250000 -+fcsr: 0x1006 -+near 1000000000 1000000000.000000 -+fcsr: 0x2 -+near -5786 -5786.250000 -+fcsr: 0x1006 -+near 1752 1752.000000 -+fcsr: 0x2 -+near 1 0.015625 -+fcsr: 0x1006 -+near 1 0.031250 -+fcsr: 0x1006 -+near -24856226678933 -24856226678933.750000 -+fcsr: 0x1006 -+near -45786 -45786.500000 -+fcsr: 0x1006 -+near 456 456.000000 -+fcsr: 0x2 -+near 35 34.031250 -+fcsr: 0x1006 -+near 45787 45786.750000 -+fcsr: 0x1006 -+near 1752065 1752065.000000 -+fcsr: 0x2 -+near 107 107.000000 -+fcsr: 0x2 -+near -45667 -45667.250000 -+fcsr: 0x1006 -+near -7 -7.000000 -+fcsr: 0x2 -+near -347856 -347856.500000 -+fcsr: 0x1006 -+near 356047 356047.000000 -+fcsr: 0x2 -+near -1 -1.250000 -+fcsr: 0x1006 -+near 24 23.062500 -+fcsr: 0x1006 -+roundig mode: -inf -+near 0 0.000000 -+fcsr: 0x3 -+near 457 456.250000 -+fcsr: 0x1007 -+near 3 3.000000 -+fcsr: 0x3 -+near -1 -1.000000 -+fcsr: 0x3 -+near 1385 1384.500000 -+fcsr: 0x1007 -+near -7 -7.250000 -+fcsr: 0x1007 -+near 1000000000 1000000000.000000 -+fcsr: 0x3 -+near -5786 -5786.250000 -+fcsr: 0x1007 -+near 1752 1752.000000 -+fcsr: 0x3 -+near 1 0.015625 -+fcsr: 0x1007 -+near 1 0.031250 -+fcsr: 0x1007 -+near -24856226678933 -24856226678933.750000 -+fcsr: 0x1007 -+near -45786 -45786.500000 -+fcsr: 0x1007 -+near 456 456.000000 -+fcsr: 0x3 -+near 35 34.031250 -+fcsr: 0x1007 -+near 45787 45786.750000 -+fcsr: 0x1007 -+near 1752065 1752065.000000 -+fcsr: 0x3 -+near 107 107.000000 -+fcsr: 0x3 -+near -45667 -45667.250000 -+fcsr: 0x1007 -+near -7 -7.000000 -+fcsr: 0x3 -+near -347856 -347856.500000 -+fcsr: 0x1007 -+near 356047 356047.000000 -+fcsr: 0x3 -+near -1 -1.250000 -+fcsr: 0x1007 -+near 24 23.062500 -+fcsr: 0x1007 -Index: none/tests/mips32/round_fpu64.stdout.exp-fpu32 -=================================================================== ---- none/tests/mips32/round_fpu64.stdout.exp-fpu32 (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/round_fpu64.stdout.exp-fpu32 (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+This test is testing mips32r2 instructions in fpu64 mode. -Index: none/tests/mips32/round_fpu64.vgtest -=================================================================== ---- none/tests/mips32/round_fpu64.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/round_fpu64.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prog: round_fpu64 -+vgopts: -q -Index: none/tests/mips32/test_fcsr.c -=================================================================== ---- none/tests/mips32/test_fcsr.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/test_fcsr.c (.../trunk) (revision 13981) -@@ -3,26 +3,21 @@ - int main () - { - int out [] = {0, 0}; -+ unsigned long long in [] = {0x405EE0A3D70A3D71ULL, 0x3FF0000000000000ULL}; - __asm__ volatile("cfc1 $a1, $31" "\n\t" -- "li $t0, 0xd70a3d71" "\n\t" -- "mtc1 $t0, $f0" "\n\t" -- "li $t0, 0x405ee0a3" "\n\t" -- "mtc1 $t0, $f1" "\n\t" -+ "ldc1 $f0, 0(%0)" "\n\t" - "ctc1 $zero, $31" "\n\t" - "round.w.d $f0, $f0" "\n\t" - "cfc1 $a2, $31" "\n\t" -- "sw $a2, 0(%0)" "\n\t" -- "li $t0, 0x00000000" "\n\t" -- "mtc1 $t0, $f0" "\n\t" -- "li $t0, 0x3ff00000" "\n\t" -- "mtc1 $t0, $f1" "\n\t" -+ "sw $a2, 0(%1)" "\n\t" -+ "ldc1 $f0, 8(%0)" "\n\t" - "ctc1 $zero, $31" "\n\t" - "round.w.d $f0, $f0" "\n\t" - "cfc1 $a2, $31" "\n\t" -- "sw $a2, 4(%0)" "\n\t" -+ "sw $a2, 4(%1)" "\n\t" - "ctc1 $a1, $31" "\n\t" - : -- : "r" (out) -+ : "r" (in), "r" (out) - : "a1", "a2", "t0", "$f0", "$f1" - ); - printf("FCSR::1: 0x%x, 2: 0x%x\n", out[0], out[1]); -Index: none/tests/mips32/test_math.cpp -=================================================================== ---- none/tests/mips32/test_math.cpp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/test_math.cpp (.../trunk) (revision 13981) -@@ -0,0 +1,115 @@ -+#include -+#include -+#include -+#include -+#include -+ -+static void DivideByZero() { -+ // volatile to prevent compiler optimizations. -+ volatile float zero = 0.0f; -+ volatile float result __attribute__((unused)) = 123.0f / zero; -+} -+ -+int main () { -+ /* Testing lrint. */ -+ fesetround(FE_UPWARD); // lrint/lrintf/lrintl obey the rounding mode. -+ printf("fesetround(FE_UPWARD)\n"); -+ printf("lrint(1234.01): %ld\n", lrint(1234.01)); -+ printf("lrintf(1234.01f): %ld\n", lrintf(1234.01f)); -+ printf("lrintl(1234.01): %ld\n", lrintl(1234.01)); -+ fesetround(FE_TOWARDZERO); // lrint/lrintf/lrintl obey the rounding mode. -+ printf("fesetround(FE_TOWARDZERO)\n"); -+ printf("lrint(1234.01): %ld\n", lrint(1234.01)); -+ printf("lrintf(1234.01f): %ld\n", lrintf(1234.01f)); -+ printf("lrintl(1234.01): %ld\n", lrintl(1234.01)); -+ fesetround(FE_UPWARD); // llrint/llrintf/llrintl obey the rounding mode. -+ printf("fesetround(FE_UPWARD)\n"); -+ printf("llrint(1234.01): %lld\n", llrint(1234.01)); -+ printf("llrintf(1234.01f): %lld\n", llrintf(1234.01f)); -+ printf("llrintf(1234.01f): %lld\n", llrintl(1234.01)); -+ fesetround(FE_TOWARDZERO); // llrint/llrintf/llrintl obey the rounding mode. -+ printf("fesetround(FE_TOWARDZERO)\n"); -+ printf("llrint(1234.01): %lld\n", llrint(1234.01)); -+ printf("llrintf(1234.01f): %lld\n", llrintf(1234.01f)); -+ printf("llrintl(1234.01): %lld\n", llrintl(1234.01)); -+ -+ /* Tesing rint. */ -+ fesetround(FE_UPWARD); // rint/rintf/rintl obey the rounding mode. -+ printf("fesetround(FE_UPWARD)\n"); -+ feclearexcept(FE_ALL_EXCEPT); // rint/rintf/rintl do set the FE_INEXACT flag. -+ printf("feclearexcept(FE_ALL_EXCEPT)\n"); -+ printf("rint(1234.0): %f\n", rint(1234.0)); -+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n", -+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT)); -+ printf("rint(1234.01): %f\n", rint(1234.01)); -+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n", -+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT)); -+ -+ feclearexcept(FE_ALL_EXCEPT); // rint/rintf/rintl do set the FE_INEXACT flag. -+ printf("feclearexcept(FE_ALL_EXCEPT)\n"); -+ printf("rintf(1234.0f): %f\n", rintf(1234.0f)); -+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n", -+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT)); -+ printf("rintf(1234.01f): %f\n", rintf(1234.01f)); -+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n", -+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT)); -+ -+ feclearexcept(FE_ALL_EXCEPT); // rint/rintf/rintl do set the FE_INEXACT flag. -+ printf("feclearexcept(FE_ALL_EXCEPT)\n"); -+ printf("rintl(1234.0): %Lf\n", rintl(1234.0)); -+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n", -+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT)); -+ printf("rintl(1234.01): %Lf\n", rintl(1234.01)); -+ printf("(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): %d\n", -+ (fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT)); -+ -+ fesetround(FE_TOWARDZERO); // rint/rintf obey the rounding mode. -+ printf("fesetround(FE_TOWARDZERO)\n"); -+ printf("rint(1234.01): %f\n", rint(1234.01)); -+ printf("rintf(1234.01f): %f\n", rintf(1234.01f)); -+ printf("rintl(1234.01): %Lf\n", rintl(1234.01)); -+ -+ /* Testing nearbyint. */ -+ fesetround(FE_UPWARD); // nearbyint/nearbyintf/nearbyintl obey the rounding mode. -+ printf("fesetround(FE_UPWARD)\n"); -+ feclearexcept(FE_ALL_EXCEPT); // nearbyint/nearbyintf/nearbyintl don't set the FE_INEXACT flag. -+ printf("feclearexcept(FE_ALL_EXCEPT)\n"); -+ printf("nearbyint(1234.0): %f\n", nearbyint(1234.0)); -+ printf("nearbyint(1234.01): %f\n", nearbyint(1234.01)); -+ -+ feclearexcept(FE_ALL_EXCEPT); -+ printf("feclearexcept(FE_ALL_EXCEPT)\n"); -+ printf("nearbyintf(1234.0f): %f\n", nearbyintf(1234.0f)); -+ printf("nearbyintf(1234.01f): %f\n", nearbyintf(1234.01f)); -+ -+ feclearexcept(FE_ALL_EXCEPT); // nearbyint/nearbyintf/nearbyintl don't set the FE_INEXACT flag. -+ printf("feclearexcept(FE_ALL_EXCEPT)\n"); -+ printf("nearbyintl(1234.0f): %Lf\n", nearbyintl(1234.0f)); -+ printf("nearbyintl(1234.01f): %Lf\n", nearbyintl(1234.01f)); -+ -+ fesetround(FE_TOWARDZERO); // nearbyint/nearbyintf/nearbyintl obey the rounding mode. -+ printf("fesetround(FE_TOWARDZERO)\n"); -+ printf("nearbyint(1234.01): %f\n", nearbyint(1234.01)); -+ printf("nearbyintf(1234.01f): %f\n", nearbyintf(1234.01f)); -+ printf("nearbyintl(1234.01): %Lf\n", nearbyintl(1234.01)); -+ -+ /* Test log. */ -+ printf("log(M_E): %lf\n", log(M_E)); -+ -+ /* Test tgamma. */ -+ printf("tgamma(5.0): %lf\n", tgamma(5.0)); -+ -+ /* Test cbrt. */ -+ printf("cbrt(27.0): %lf\n", cbrt(27.0)); -+ -+ /* Test dividing by zero. */ -+ // Clearing clears. -+ printf("feclearexcept(FE_ALL_EXCEPT): %d\n", feclearexcept(FE_ALL_EXCEPT)); -+ -+ // Dividing by zero sets FE_DIVBYZERO. -+ DivideByZero(); -+ int raised = fetestexcept(FE_DIVBYZERO | FE_OVERFLOW); -+ printf("raised: %d\n", raised); -+ -+ return 0; -+} -Index: none/tests/mips32/test_math.stderr.exp -=================================================================== -Index: none/tests/mips32/test_math.stdout.exp -=================================================================== ---- none/tests/mips32/test_math.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/test_math.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,55 @@ -+fesetround(FE_UPWARD) -+lrint(1234.01): 1235 -+lrintf(1234.01f): 1235 -+lrintl(1234.01): 1235 -+fesetround(FE_TOWARDZERO) -+lrint(1234.01): 1234 -+lrintf(1234.01f): 1234 -+lrintl(1234.01): 1234 -+fesetround(FE_UPWARD) -+llrint(1234.01): 1235 -+llrintf(1234.01f): 1235 -+llrintf(1234.01f): 1235 -+fesetround(FE_TOWARDZERO) -+llrint(1234.01): 1234 -+llrintf(1234.01f): 1234 -+llrintl(1234.01): 1234 -+fesetround(FE_UPWARD) -+feclearexcept(FE_ALL_EXCEPT) -+rint(1234.0): 1234.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0 -+rint(1234.01): 1235.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4 -+feclearexcept(FE_ALL_EXCEPT) -+rintf(1234.0f): 1234.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0 -+rintf(1234.01f): 1235.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4 -+feclearexcept(FE_ALL_EXCEPT) -+rintl(1234.0): 1234.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0 -+rintl(1234.01): 1235.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4 -+fesetround(FE_TOWARDZERO) -+rint(1234.01): 1234.000000 -+rintf(1234.01f): 1234.000000 -+rintl(1234.01): 1234.000000 -+fesetround(FE_UPWARD) -+feclearexcept(FE_ALL_EXCEPT) -+nearbyint(1234.0): 1234.000000 -+nearbyint(1234.01): 1235.000000 -+feclearexcept(FE_ALL_EXCEPT) -+nearbyintf(1234.0f): 1234.000000 -+nearbyintf(1234.01f): 1235.000000 -+feclearexcept(FE_ALL_EXCEPT) -+nearbyintl(1234.0f): 1234.000000 -+nearbyintl(1234.01f): 1235.000000 -+fesetround(FE_TOWARDZERO) -+nearbyint(1234.01): 1234.000000 -+nearbyintf(1234.01f): 1234.000000 -+nearbyintl(1234.01): 1234.000000 -+log(M_E): 1.000000 -+tgamma(5.0): 24.000000 -+cbrt(27.0): 3.000000 -+feclearexcept(FE_ALL_EXCEPT): 0 -+raised: 32 -Index: none/tests/mips32/test_math.vgtest -=================================================================== ---- none/tests/mips32/test_math.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips32/test_math.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prog: test_math -+vgopts: -q -Index: none/tests/mips32/vfp.c -=================================================================== ---- none/tests/mips32/vfp.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips32/vfp.c (.../trunk) (revision 13981) -@@ -43,7 +43,9 @@ - 0, 0, 0, 0, - 0, 0, 0, 0 - }; -+ - // ldc1 $f0, 0($t1) -+#if (__mips_fpr==64) - #define TESTINSN5LOAD(instruction, RTval, offset, RT) \ - { \ - double out; \ -@@ -55,14 +57,35 @@ - instruction "\n\t" \ - "mov.d %0, $" #RT "\n\t" \ - "mfc1 %1, $" #RT "\n\t" \ -+ "mfhc1 %2, $" #RT "\n\t" \ -+ : "=&f" (out), "=&r" (out1), "=&r" (out2) \ -+ : "r" (mem), "r" (RTval) \ -+ : "cc", "memory" \ -+ ); \ -+ printf("%s :: ft 0x%x%x\n", \ -+ instruction, out1, out2); \ -+} -+#else -+#define TESTINSN5LOAD(instruction, RTval, offset, RT) \ -+{ \ -+ double out; \ -+ int out1; \ -+ int out2; \ -+ __asm__ volatile( \ -+ "move $t1, %3\n\t" \ -+ "li $t0, " #RTval"\n\t" \ -+ instruction "\n\t" \ -+ "mov.d %0, $" #RT "\n\t" \ -+ "mfc1 %1, $" #RT "\n\t" \ - "mfc1 %2, $f1\n\t" \ - : "=&f" (out), "=&r" (out1), "=&r" (out2) \ -- : "r" (mem), "r" (RTval) \ -- : "cc", "memory" \ -- ); \ -+ : "r" (mem), "r" (RTval) \ -+ : "cc", "memory" \ -+ ); \ - printf("%s :: ft 0x%x%x\n", \ - instruction, out1, out2); \ - } -+#endif - - // lwc1 $f0, 0($t1) - #define TESTINSN5LOADw(instruction, RTval, offset, RT) \ -@@ -76,9 +99,9 @@ - "mov.d %0, $" #RT "\n\t" \ - "mfc1 %1, $" #RT "\n\t" \ - : "=&f" (out), "=&r" (out1) \ -- : "r" (mem), "r" (RTval) \ -- : "cc", "memory" \ -- ); \ -+ : "r" (mem), "r" (RTval) \ -+ : "cc", "memory" \ -+ ); \ - printf("%s :: ft 0x%x\n", \ - instruction, out1); \ - } -@@ -93,14 +116,15 @@ - instruction "\n\t" \ - "mfc1 %0, $" #fd "\n\t" \ - : "=&r" (out) \ -- : "r" (mem) \ -- : "cc", "memory" \ -- ); \ -+ : "r" (mem) \ -+ : "cc", "memory" \ -+ ); \ - printf("%s :: ft 0x%x\n", \ - instruction, out); \ - } - - // ldxc1 $f0, $a3($v0) -+#if (__mips_fpr==64) - #define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \ - { \ - int out1; \ -@@ -110,14 +134,34 @@ - "li $" #index ", " #indexVal"\n\t" \ - instruction "\n\t" \ - "mfc1 %0, $" #fd "\n\t" \ -+ "mfhc1 %1, $" #fd "\n\t" \ -+ : "=&r" (out1), "=&r" (out2) \ -+ : "r" (mem) \ -+ : "cc", "memory" \ -+ ); \ -+ printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \ -+ instruction, out1, out2); \ -+} -+#else -+#define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \ -+{ \ -+ int out1; \ -+ int out2; \ -+ __asm__ volatile( \ -+ "move $" #base ", %2\n\t" \ -+ "li $" #index ", " #indexVal"\n\t" \ -+ instruction "\n\t" \ -+ "mfc1 %0, $" #fd "\n\t" \ - "mfc1 %1, $f1\n\t" \ - : "=&r" (out1), "=&r" (out2) \ -- : "r" (mem) \ -- : "cc", "memory" \ -- ); \ -+ : "r" (mem) \ -+ : "cc", "memory" \ -+ ); \ - printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \ - instruction, out1, out2); \ - } -+#endif -+ - // sdc1 $f0, 0($t0) - #define TESTINST1(offset) \ - { \ -@@ -129,9 +173,9 @@ - "sdc1 $f0, "#offset"($t0) \n\t" \ - "lw %0, "#offset"($t0)\n\t" \ - : "=&r" (out) \ -- : "r" (mem1), "r" (fs_d) \ -- : "t1", "t0", "cc", "memory" \ -- ); \ -+ : "r" (mem1), "r" (fs_d) \ -+ : "t1", "t0", "cc", "memory" \ -+ ); \ - printf("sdc1 $f0, 0($t0) :: out: 0x%x\n", \ - out); \ - } -@@ -151,9 +195,9 @@ - "addi $t0, $t0, 4 \n\t" \ - "lw %1, "#offset"($t0)\n\t" \ - : "=&r" (out), "=&r" (out1) \ -- : "r" (mem1), "r" (fs_d) \ -- : "t2", "t1", "t0", "cc", "memory" \ -- ); \ -+ : "r" (mem1), "r" (fs_d) \ -+ : "t2", "t1", "t0", "cc", "memory" \ -+ ); \ - printf("sdc1 $f0, #t2($t0) :: out: 0x%x : out1: 0x%x\n", \ - out, out1); \ - } -@@ -169,9 +213,9 @@ - "swc1 $f0, "#offset"($t0) \n\t" \ - "lw %0, "#offset"($t0)\n\t" \ - : "=&r" (out) \ -- : "r" (mem1f), "r" (fs_f) \ -- : "t1", "t0", "cc", "memory" \ -- ); \ -+ : "r" (mem1f), "r" (fs_f) \ -+ : "t1", "t0", "cc", "memory" \ -+ ); \ - printf("swc1 $f0, 0($t0) :: out: 0x%x\n", \ - out); \ - } -@@ -188,9 +232,9 @@ - "swxc1 $f0, $t2($t0) \n\t" \ - "lw %0, "#offset"($t0)\n\t" \ - : "=&r" (out) \ -- : "r" (mem1f), "r" (fs_f) \ -- : "t2", "t1", "t0", "cc", "memory" \ -- ); \ -+ : "r" (mem1f), "r" (fs_f) \ -+ : "t2", "t1", "t0", "cc", "memory" \ -+ ); \ - printf("swxc1 $f0, 0($t0) :: out: 0x%x\n", \ - out); \ - } -@@ -364,7 +408,7 @@ - TESTINST1(64); - ppMem(mem1, 16); - --#if (__mips==32) && (__mips_isa_rev>=2) -+#if (__mips==32) && (__mips_isa_rev>=2) - printf("SDXC1\n"); - TESTINST1a(0); - TESTINST1a(8); -@@ -390,7 +434,7 @@ - TESTINST2(64); - ppMemF(mem1f, 16); - --#if (__mips==32) && (__mips_isa_rev>=2) -+#if (__mips==32) && (__mips_isa_rev>=2) - printf("SWXC1\n"); - TESTINST2a(0); - TESTINST2a(8); -Index: none/tests/mips64 -=================================================================== ---- none/tests/mips64 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips64 (.../trunk) (revision 13981) - -Property changes on: none/tests/mips64 -___________________________________________________________________ -Modified: svn:ignore -## -1,22 +1,28 ## - Makefile - Makefile.in - .deps --move_instructions --extract_insert_bit_field --logical_instructions --fpu_branches --rotate_swap - allexec --load_store_unaligned - arithmetic_instruction -+branch_and_jump_instructions -+branches -+cvm_ins -+cvm_lx_ins -+extract_insert_bit_field - fpu_arithmetic --unaligned_load -+fpu_control_word -+fpu_branches -+fpu_load_store -+load_indexed_instructions -+load_store - load_store_multiple --test_block_size -+load_store_unaligned -+logical_instructions -+move_instructions -+rotate_swap - round --branch_and_jump_instructions --fpu_control_word --branches --load_store - shift_instructions --fpu_load_store -+test_block_size -+test_fcsr -+test_math -+unaligned_load -+unaligned_load_store -Index: none/tests/mips64/Makefile.am -=================================================================== ---- none/tests/mips64/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips64/Makefile.am (.../trunk) (revision 13981) -@@ -10,7 +10,11 @@ - branch_and_jump_instructions.stdout.exp \ - branch_and_jump_instructions.stderr.exp branch_and_jump_instructions.vgtest \ - branches.stdout.exp branches.stderr.exp branches.vgtest \ -- cvm_ins.stdout.exp cvm_ins.stderr.exp cvm_ins.vgtest \ -+ cvm_ins.stdout.exp cvm_ins.stdout.exp-non-octeon \ -+ cvm_ins.stderr.exp cvm_ins.vgtest \ -+ cvm_lx_ins.stdout.exp-LE cvm_lx_ins.stdout.exp-BE \ -+ cvm_lx_ins.stdout.exp-non-octeon \ -+ cvm_lx_ins.stderr.exp cvm_lx_ins.vgtest \ - extract_insert_bit_field.stdout.exp-mips64 \ - extract_insert_bit_field.stdout.exp-mips64r2 \ - extract_insert_bit_field.stderr.exp extract_insert_bit_field.vgtest \ -@@ -20,6 +24,10 @@ - fpu_control_word.vgtest \ - fpu_load_store.stdout.exp-BE fpu_load_store.stdout.exp-LE \ - fpu_load_store.stderr.exp fpu_load_store.vgtest \ -+ load_indexed_instructions.stdout.exp-BE \ -+ load_indexed_instructions.stdout.exp-LE \ -+ load_indexed_instructions.stdout.exp-non-octeon \ -+ load_indexed_instructions.stderr.exp load_indexed_instructions.vgtest \ - load_store.stdout.exp-BE load_store.stdout.exp-LE load_store.stderr.exp \ - load_store.vgtest \ - load_store_multiple.stdout.exp-BE load_store_multiple.stdout.exp-LE \ -@@ -37,12 +45,13 @@ - shift_instructions.stderr.exp shift_instructions.vgtest \ - test_block_size.stdout.exp test_block_size.stderr.exp \ - test_block_size.vgtest \ -+ test_fcsr.stdout.exp test_fcsr.stderr.exp \ -+ test_fcsr.vgtest \ -+ test_math.stdout.exp test_math.stderr.exp test_math.vgtest \ - unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \ - unaligned_load.stderr.exp unaligned_load.vgtest \ - unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \ - unaligned_load_store.stderr.exp unaligned_load_store.vgtest \ -- test_fcsr.stdout.exp test_fcsr.stderr.exp \ -- test_fcsr.vgtest \ - const.h macro_fpu.h macro_int.h macro_load_store.h rounding_mode.h - - check_PROGRAMS = \ -@@ -51,11 +60,13 @@ - branch_and_jump_instructions \ - branches \ - cvm_ins \ -+ cvm_lx_ins \ - extract_insert_bit_field \ - fpu_arithmetic \ - fpu_branches \ - fpu_control_word \ - fpu_load_store \ -+ load_indexed_instructions \ - load_store \ - load_store_multiple \ - load_store_unaligned \ -@@ -65,9 +76,10 @@ - round \ - shift_instructions \ - test_block_size \ -+ test_fcsr \ -+ test_math \ - unaligned_load \ -- unaligned_load_store \ -- test_fcsr -+ unaligned_load_store - - AM_CFLAGS += @FLAG_M64@ - AM_CXXFLAGS += @FLAG_M64@ -@@ -75,5 +87,10 @@ - - allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ - --cvm_ins_CFLAGS = $(AM_CFLAGS) -g -O0 -march=octeon -+cvm_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON@ -+cvm_lx_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@ -+load_indexed_instructions_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@ - fpu_arithmetic_CFLAGS = $(AM_CFLAGS) -lm -+ -+# C++ tests -+test_math_SOURCES = test_math.cpp -Index: none/tests/mips64/cvm_ins.c -=================================================================== ---- none/tests/mips64/cvm_ins.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/mips64/cvm_ins.c (.../trunk) (revision 13981) -@@ -120,28 +120,29 @@ - - int main() - { -+#if (_MIPS_ARCH_OCTEON) - int i, j; - cvm_op op; - for (op = EXTS; op <= SEQ; op++) { -- switch(op) { -+ switch(op) { - case EXTS: { /* To extract and sign-extend a bit field that starts - from the lower 32 bits of a register. */ -- for(i = 0; i <= 255; i+=4) -- TESTINST1("exts $t1, $t2, 1, 7", reg_val[i], t1, t2, 1, 7); -- break; -+ for(i = 0; i <= 255; i+=4) -+ TESTINST1("exts $t1, $t2, 1, 7", reg_val[i], t1, t2, 1, 7); -+ break; - } - - case EXTS32: { /* To extract and sign-extend a bit field that starts - from the upper 32 bits of a register. */ -- for(i = 0; i <= 255; i+=4) -- TESTINST1("exts32 $t1, $t2, 1 , 7", reg_val[i], t1, t2,1,7); -- break; -+ for(i = 0; i <= 255; i+=4) -+ TESTINST1("exts32 $t1, $t2, 1 , 7", reg_val[i], t1, t2, 1, 7); -+ break; - } - - case CINS:{ /* To insert a bit field that starts in the lower 32 bits - of a register. */ - for(i = 0; i <= 255; i+=4) -- TESTINST1("cins $t1, $t2, 2 , 9", reg_val[i], t1, t2,2,9); -+ TESTINST1("cins $t1, $t2, 2 , 9", reg_val[i], t1, t2, 2, 9); - break; - } - -@@ -153,10 +154,10 @@ - } - - case SEQ: { /* To record the result of an equals comparison. */ -- for(i = 0; i <= 255; i+=4) -- for(j = 0; j <= 255; j+=4) -- TESTINST2("seq $t1, $t2 ,$t3 ", reg_val[i], reg_val[j], -- t1, t2, t3); -+ for(i = 0; i <= 255; i+=4) -+ for(j = 0; j <= 255; j+=4) -+ TESTINST2("seq $t1, $t2 ,$t3 ", reg_val[i], reg_val[j], -+ t1, t2, t3); - break; - } - -@@ -192,5 +193,6 @@ - } - } - } -+#endif - return 0; - } -Index: none/tests/mips64/cvm_ins.stdout.exp-non-octeon -=================================================================== -Index: none/tests/mips64/cvm_lx_ins.c -=================================================================== ---- none/tests/mips64/cvm_lx_ins.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/cvm_lx_ins.c (.../trunk) (revision 13981) -@@ -0,0 +1,117 @@ -+#include -+const int reg_val[256] = { -+ 0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L, -+ 0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L, -+ 0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L, -+ 0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL, -+ 0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L, -+ 0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L, -+ 0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L, -+ 0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL, -+ 0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L, -+ 0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L, -+ 0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L, -+ 0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL, -+ 0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L, -+ 0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L, -+ 0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L, -+ 0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL, -+ 0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL, -+ 0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L, -+ 0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L, -+ 0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL, -+ 0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL, -+ 0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L, -+ 0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L, -+ 0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL, -+ 0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL, -+ 0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L, -+ 0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L, -+ 0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL, -+ 0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL, -+ 0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L, -+ 0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L, -+ 0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL, -+ 0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L, -+ 0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL, -+ 0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL, -+ 0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L, -+ 0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L, -+ 0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL, -+ 0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL, -+ 0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L, -+ 0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L, -+ 0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL, -+ 0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL, -+ 0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L, -+ 0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L, -+ 0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL, -+ 0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL, -+ 0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L, -+ 0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L, -+ 0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL, -+ 0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L, -+ 0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L, -+ 0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L, -+ 0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL, -+ 0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L, -+ 0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L, -+ 0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L, -+ 0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL, -+ 0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L, -+ 0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L, -+ 0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L, -+ 0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL, -+ 0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L, -+ 0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L -+}; -+ -+#define TEST1(instruction, offset, mem) \ -+{ \ -+ unsigned long out = 0; \ -+ __asm__ volatile( \ -+ "move $t0, %1" "\n\t" \ -+ "move $t1, %2" "\n\t" \ -+ instruction" $t2, $t1($t0)" "\n\t" \ -+ "move %0, $t2" "\n\t" \ -+ : "=&r" (out) \ -+ : "r" (mem) , "r" (offset) \ -+ : "t0", "t1", "t2", "memory" \ -+ ); \ -+ printf("%s :: offset: 0x%x, out: 0x%lx\n", \ -+ instruction, offset, out); \ -+} -+ -+typedef enum { -+ lhux, lwux, lbx -+} cvm_op; -+ -+int main() -+{ -+#if (_MIPS_ARCH_OCTEON2) -+ int i; -+ cvm_op op; -+ for (op = lhux; op <= lbx; op++) { -+ switch(op) { -+ case lhux: { // LHUX rd, index(base) (Cavium OCTEON) -+ for(i = 4; i <= 255; i += 4) -+ TEST1("lhux", i, reg_val); -+ break; -+ } -+ case lwux: { // LWUX rd, index(base) (Cavium OCTEON) -+ for(i = 4; i <= 255; i += 4) -+ TEST1("lwux", i, reg_val); -+ break; -+ } -+ case lbx: { // LBX rd, index(base) (Cavium OCTEON) -+ for(i = 4; i <= 255; i += 4) -+ TEST1("lbx", i, reg_val); -+ break; -+ } -+ default: -+ printf("Nothing to be executed \n"); -+ } -+ } -+#endif -+ return 0; -+} -Index: none/tests/mips64/cvm_lx_ins.stderr.exp -=================================================================== -Index: none/tests/mips64/cvm_lx_ins.stdout.exp-BE -=================================================================== ---- none/tests/mips64/cvm_lx_ins.stdout.exp-BE (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/cvm_lx_ins.stdout.exp-BE (.../trunk) (revision 13981) -@@ -0,0 +1,189 @@ -+lhux :: offset: 0x4, out: 0x4c1 -+lhux :: offset: 0x8, out: 0x982 -+lhux :: offset: 0xc, out: 0xd43 -+lhux :: offset: 0x10, out: 0x1304 -+lhux :: offset: 0x14, out: 0x17c5 -+lhux :: offset: 0x18, out: 0x1a86 -+lhux :: offset: 0x1c, out: 0x1e47 -+lhux :: offset: 0x20, out: 0x2608 -+lhux :: offset: 0x24, out: 0x22c9 -+lhux :: offset: 0x28, out: 0x2f8a -+lhux :: offset: 0x2c, out: 0x2b4b -+lhux :: offset: 0x30, out: 0x350c -+lhux :: offset: 0x34, out: 0x31cd -+lhux :: offset: 0x38, out: 0x3c8e -+lhux :: offset: 0x3c, out: 0x384f -+lhux :: offset: 0x40, out: 0x4c11 -+lhux :: offset: 0x44, out: 0x48d0 -+lhux :: offset: 0x48, out: 0x4593 -+lhux :: offset: 0x4c, out: 0x4152 -+lhux :: offset: 0x50, out: 0x5f15 -+lhux :: offset: 0x54, out: 0x5bd4 -+lhux :: offset: 0x58, out: 0x5697 -+lhux :: offset: 0x5c, out: 0x5256 -+lhux :: offset: 0x60, out: 0x6a19 -+lhux :: offset: 0x64, out: 0x6ed8 -+lhux :: offset: 0x68, out: 0x639b -+lhux :: offset: 0x6c, out: 0x675a -+lhux :: offset: 0x70, out: 0x791d -+lhux :: offset: 0x74, out: 0x7ddc -+lhux :: offset: 0x78, out: 0x709f -+lhux :: offset: 0x7c, out: 0x745e -+lhux :: offset: 0x80, out: 0x9823 -+lhux :: offset: 0x84, out: 0x9ce2 -+lhux :: offset: 0x88, out: 0x91a1 -+lhux :: offset: 0x8c, out: 0x9560 -+lhux :: offset: 0x90, out: 0x8b27 -+lhux :: offset: 0x94, out: 0x8fe6 -+lhux :: offset: 0x98, out: 0x82a5 -+lhux :: offset: 0x9c, out: 0x8664 -+lhux :: offset: 0xa0, out: 0xbe2b -+lhux :: offset: 0xa4, out: 0xbaea -+lhux :: offset: 0xa8, out: 0xb7a9 -+lhux :: offset: 0xac, out: 0xb368 -+lhux :: offset: 0xb0, out: 0xad2f -+lhux :: offset: 0xb4, out: 0xa9ee -+lhux :: offset: 0xb8, out: 0xa4ad -+lhux :: offset: 0xbc, out: 0xa06c -+lhux :: offset: 0xc0, out: 0xd432 -+lhux :: offset: 0xc4, out: 0xd0f3 -+lhux :: offset: 0xc8, out: 0xddb0 -+lhux :: offset: 0xcc, out: 0xd971 -+lhux :: offset: 0xd0, out: 0xc736 -+lhux :: offset: 0xd4, out: 0xc3f7 -+lhux :: offset: 0xd8, out: 0xceb4 -+lhux :: offset: 0xdc, out: 0xca75 -+lhux :: offset: 0xe0, out: 0xf23a -+lhux :: offset: 0xe4, out: 0xf6fb -+lhux :: offset: 0xe8, out: 0xfbb8 -+lhux :: offset: 0xec, out: 0xff79 -+lhux :: offset: 0xf0, out: 0xe13e -+lhux :: offset: 0xf4, out: 0xe5ff -+lhux :: offset: 0xf8, out: 0xe8bc -+lhux :: offset: 0xfc, out: 0xec7d -+lwux :: offset: 0x4, out: 0x4c11db7 -+lwux :: offset: 0x8, out: 0x9823b6e -+lwux :: offset: 0xc, out: 0xd4326d9 -+lwux :: offset: 0x10, out: 0x130476dc -+lwux :: offset: 0x14, out: 0x17c56b6b -+lwux :: offset: 0x18, out: 0x1a864db2 -+lwux :: offset: 0x1c, out: 0x1e475005 -+lwux :: offset: 0x20, out: 0x2608edb8 -+lwux :: offset: 0x24, out: 0x22c9f00f -+lwux :: offset: 0x28, out: 0x2f8ad6d6 -+lwux :: offset: 0x2c, out: 0x2b4bcb61 -+lwux :: offset: 0x30, out: 0x350c9b64 -+lwux :: offset: 0x34, out: 0x31cd86d3 -+lwux :: offset: 0x38, out: 0x3c8ea00a -+lwux :: offset: 0x3c, out: 0x384fbdbd -+lwux :: offset: 0x40, out: 0x4c11db70 -+lwux :: offset: 0x44, out: 0x48d0c6c7 -+lwux :: offset: 0x48, out: 0x4593e01e -+lwux :: offset: 0x4c, out: 0x4152fda9 -+lwux :: offset: 0x50, out: 0x5f15adac -+lwux :: offset: 0x54, out: 0x5bd4b01b -+lwux :: offset: 0x58, out: 0x569796c2 -+lwux :: offset: 0x5c, out: 0x52568b75 -+lwux :: offset: 0x60, out: 0x6a1936c8 -+lwux :: offset: 0x64, out: 0x6ed82b7f -+lwux :: offset: 0x68, out: 0x639b0da6 -+lwux :: offset: 0x6c, out: 0x675a1011 -+lwux :: offset: 0x70, out: 0x791d4014 -+lwux :: offset: 0x74, out: 0x7ddc5da3 -+lwux :: offset: 0x78, out: 0x709f7b7a -+lwux :: offset: 0x7c, out: 0x745e66cd -+lwux :: offset: 0x80, out: 0x9823b6e0 -+lwux :: offset: 0x84, out: 0x9ce2ab57 -+lwux :: offset: 0x88, out: 0x91a18d8e -+lwux :: offset: 0x8c, out: 0x95609039 -+lwux :: offset: 0x90, out: 0x8b27c03c -+lwux :: offset: 0x94, out: 0x8fe6dd8b -+lwux :: offset: 0x98, out: 0x82a5fb52 -+lwux :: offset: 0x9c, out: 0x8664e6e5 -+lwux :: offset: 0xa0, out: 0xbe2b5b58 -+lwux :: offset: 0xa4, out: 0xbaea46ef -+lwux :: offset: 0xa8, out: 0xb7a96036 -+lwux :: offset: 0xac, out: 0xb3687d81 -+lwux :: offset: 0xb0, out: 0xad2f2d84 -+lwux :: offset: 0xb4, out: 0xa9ee3033 -+lwux :: offset: 0xb8, out: 0xa4ad16ea -+lwux :: offset: 0xbc, out: 0xa06c0b5d -+lwux :: offset: 0xc0, out: 0xd4326d90 -+lwux :: offset: 0xc4, out: 0xd0f37027 -+lwux :: offset: 0xc8, out: 0xddb056fe -+lwux :: offset: 0xcc, out: 0xd9714b49 -+lwux :: offset: 0xd0, out: 0xc7361b4c -+lwux :: offset: 0xd4, out: 0xc3f706fb -+lwux :: offset: 0xd8, out: 0xceb42022 -+lwux :: offset: 0xdc, out: 0xca753d95 -+lwux :: offset: 0xe0, out: 0xf23a8028 -+lwux :: offset: 0xe4, out: 0xf6fb9d9f -+lwux :: offset: 0xe8, out: 0xfbb8bb46 -+lwux :: offset: 0xec, out: 0xff79a6f1 -+lwux :: offset: 0xf0, out: 0xe13ef6f4 -+lwux :: offset: 0xf4, out: 0xe5ffeb43 -+lwux :: offset: 0xf8, out: 0xe8bccd9a -+lwux :: offset: 0xfc, out: 0xec7dd02d -+lbx :: offset: 0x4, out: 0x4 -+lbx :: offset: 0x8, out: 0x9 -+lbx :: offset: 0xc, out: 0xd -+lbx :: offset: 0x10, out: 0x13 -+lbx :: offset: 0x14, out: 0x17 -+lbx :: offset: 0x18, out: 0x1a -+lbx :: offset: 0x1c, out: 0x1e -+lbx :: offset: 0x20, out: 0x26 -+lbx :: offset: 0x24, out: 0x22 -+lbx :: offset: 0x28, out: 0x2f -+lbx :: offset: 0x2c, out: 0x2b -+lbx :: offset: 0x30, out: 0x35 -+lbx :: offset: 0x34, out: 0x31 -+lbx :: offset: 0x38, out: 0x3c -+lbx :: offset: 0x3c, out: 0x38 -+lbx :: offset: 0x40, out: 0x4c -+lbx :: offset: 0x44, out: 0x48 -+lbx :: offset: 0x48, out: 0x45 -+lbx :: offset: 0x4c, out: 0x41 -+lbx :: offset: 0x50, out: 0x5f -+lbx :: offset: 0x54, out: 0x5b -+lbx :: offset: 0x58, out: 0x56 -+lbx :: offset: 0x5c, out: 0x52 -+lbx :: offset: 0x60, out: 0x6a -+lbx :: offset: 0x64, out: 0x6e -+lbx :: offset: 0x68, out: 0x63 -+lbx :: offset: 0x6c, out: 0x67 -+lbx :: offset: 0x70, out: 0x79 -+lbx :: offset: 0x74, out: 0x7d -+lbx :: offset: 0x78, out: 0x70 -+lbx :: offset: 0x7c, out: 0x74 -+lbx :: offset: 0x80, out: 0xffffffffffffff98 -+lbx :: offset: 0x84, out: 0xffffffffffffff9c -+lbx :: offset: 0x88, out: 0xffffffffffffff91 -+lbx :: offset: 0x8c, out: 0xffffffffffffff95 -+lbx :: offset: 0x90, out: 0xffffffffffffff8b -+lbx :: offset: 0x94, out: 0xffffffffffffff8f -+lbx :: offset: 0x98, out: 0xffffffffffffff82 -+lbx :: offset: 0x9c, out: 0xffffffffffffff86 -+lbx :: offset: 0xa0, out: 0xffffffffffffffbe -+lbx :: offset: 0xa4, out: 0xffffffffffffffba -+lbx :: offset: 0xa8, out: 0xffffffffffffffb7 -+lbx :: offset: 0xac, out: 0xffffffffffffffb3 -+lbx :: offset: 0xb0, out: 0xffffffffffffffad -+lbx :: offset: 0xb4, out: 0xffffffffffffffa9 -+lbx :: offset: 0xb8, out: 0xffffffffffffffa4 -+lbx :: offset: 0xbc, out: 0xffffffffffffffa0 -+lbx :: offset: 0xc0, out: 0xffffffffffffffd4 -+lbx :: offset: 0xc4, out: 0xffffffffffffffd0 -+lbx :: offset: 0xc8, out: 0xffffffffffffffdd -+lbx :: offset: 0xcc, out: 0xffffffffffffffd9 -+lbx :: offset: 0xd0, out: 0xffffffffffffffc7 -+lbx :: offset: 0xd4, out: 0xffffffffffffffc3 -+lbx :: offset: 0xd8, out: 0xffffffffffffffce -+lbx :: offset: 0xdc, out: 0xffffffffffffffca -+lbx :: offset: 0xe0, out: 0xfffffffffffffff2 -+lbx :: offset: 0xe4, out: 0xfffffffffffffff6 -+lbx :: offset: 0xe8, out: 0xfffffffffffffffb -+lbx :: offset: 0xec, out: 0xffffffffffffffff -+lbx :: offset: 0xf0, out: 0xffffffffffffffe1 -+lbx :: offset: 0xf4, out: 0xffffffffffffffe5 -+lbx :: offset: 0xf8, out: 0xffffffffffffffe8 -+lbx :: offset: 0xfc, out: 0xffffffffffffffec -Index: none/tests/mips64/cvm_lx_ins.stdout.exp-LE -=================================================================== ---- none/tests/mips64/cvm_lx_ins.stdout.exp-LE (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/cvm_lx_ins.stdout.exp-LE (.../trunk) (revision 13981) -@@ -0,0 +1,189 @@ -+lhux :: offset: 0x4, out: 0x1db7 -+lhux :: offset: 0x8, out: 0x3b6e -+lhux :: offset: 0xc, out: 0x26d9 -+lhux :: offset: 0x10, out: 0x76dc -+lhux :: offset: 0x14, out: 0x6b6b -+lhux :: offset: 0x18, out: 0x4db2 -+lhux :: offset: 0x1c, out: 0x5005 -+lhux :: offset: 0x20, out: 0xedb8 -+lhux :: offset: 0x24, out: 0xf00f -+lhux :: offset: 0x28, out: 0xd6d6 -+lhux :: offset: 0x2c, out: 0xcb61 -+lhux :: offset: 0x30, out: 0x9b64 -+lhux :: offset: 0x34, out: 0x86d3 -+lhux :: offset: 0x38, out: 0xa00a -+lhux :: offset: 0x3c, out: 0xbdbd -+lhux :: offset: 0x40, out: 0xdb70 -+lhux :: offset: 0x44, out: 0xc6c7 -+lhux :: offset: 0x48, out: 0xe01e -+lhux :: offset: 0x4c, out: 0xfda9 -+lhux :: offset: 0x50, out: 0xadac -+lhux :: offset: 0x54, out: 0xb01b -+lhux :: offset: 0x58, out: 0x96c2 -+lhux :: offset: 0x5c, out: 0x8b75 -+lhux :: offset: 0x60, out: 0x36c8 -+lhux :: offset: 0x64, out: 0x2b7f -+lhux :: offset: 0x68, out: 0xda6 -+lhux :: offset: 0x6c, out: 0x1011 -+lhux :: offset: 0x70, out: 0x4014 -+lhux :: offset: 0x74, out: 0x5da3 -+lhux :: offset: 0x78, out: 0x7b7a -+lhux :: offset: 0x7c, out: 0x66cd -+lhux :: offset: 0x80, out: 0xb6e0 -+lhux :: offset: 0x84, out: 0xab57 -+lhux :: offset: 0x88, out: 0x8d8e -+lhux :: offset: 0x8c, out: 0x9039 -+lhux :: offset: 0x90, out: 0xc03c -+lhux :: offset: 0x94, out: 0xdd8b -+lhux :: offset: 0x98, out: 0xfb52 -+lhux :: offset: 0x9c, out: 0xe6e5 -+lhux :: offset: 0xa0, out: 0x5b58 -+lhux :: offset: 0xa4, out: 0x46ef -+lhux :: offset: 0xa8, out: 0x6036 -+lhux :: offset: 0xac, out: 0x7d81 -+lhux :: offset: 0xb0, out: 0x2d84 -+lhux :: offset: 0xb4, out: 0x3033 -+lhux :: offset: 0xb8, out: 0x16ea -+lhux :: offset: 0xbc, out: 0xb5d -+lhux :: offset: 0xc0, out: 0x6d90 -+lhux :: offset: 0xc4, out: 0x7027 -+lhux :: offset: 0xc8, out: 0x56fe -+lhux :: offset: 0xcc, out: 0x4b49 -+lhux :: offset: 0xd0, out: 0x1b4c -+lhux :: offset: 0xd4, out: 0x6fb -+lhux :: offset: 0xd8, out: 0x2022 -+lhux :: offset: 0xdc, out: 0x3d95 -+lhux :: offset: 0xe0, out: 0x8028 -+lhux :: offset: 0xe4, out: 0x9d9f -+lhux :: offset: 0xe8, out: 0xbb46 -+lhux :: offset: 0xec, out: 0xa6f1 -+lhux :: offset: 0xf0, out: 0xf6f4 -+lhux :: offset: 0xf4, out: 0xeb43 -+lhux :: offset: 0xf8, out: 0xcd9a -+lhux :: offset: 0xfc, out: 0xd02d -+lwux :: offset: 0x4, out: 0x4c11db7 -+lwux :: offset: 0x8, out: 0x9823b6e -+lwux :: offset: 0xc, out: 0xd4326d9 -+lwux :: offset: 0x10, out: 0x130476dc -+lwux :: offset: 0x14, out: 0x17c56b6b -+lwux :: offset: 0x18, out: 0x1a864db2 -+lwux :: offset: 0x1c, out: 0x1e475005 -+lwux :: offset: 0x20, out: 0x2608edb8 -+lwux :: offset: 0x24, out: 0x22c9f00f -+lwux :: offset: 0x28, out: 0x2f8ad6d6 -+lwux :: offset: 0x2c, out: 0x2b4bcb61 -+lwux :: offset: 0x30, out: 0x350c9b64 -+lwux :: offset: 0x34, out: 0x31cd86d3 -+lwux :: offset: 0x38, out: 0x3c8ea00a -+lwux :: offset: 0x3c, out: 0x384fbdbd -+lwux :: offset: 0x40, out: 0x4c11db70 -+lwux :: offset: 0x44, out: 0x48d0c6c7 -+lwux :: offset: 0x48, out: 0x4593e01e -+lwux :: offset: 0x4c, out: 0x4152fda9 -+lwux :: offset: 0x50, out: 0x5f15adac -+lwux :: offset: 0x54, out: 0x5bd4b01b -+lwux :: offset: 0x58, out: 0x569796c2 -+lwux :: offset: 0x5c, out: 0x52568b75 -+lwux :: offset: 0x60, out: 0x6a1936c8 -+lwux :: offset: 0x64, out: 0x6ed82b7f -+lwux :: offset: 0x68, out: 0x639b0da6 -+lwux :: offset: 0x6c, out: 0x675a1011 -+lwux :: offset: 0x70, out: 0x791d4014 -+lwux :: offset: 0x74, out: 0x7ddc5da3 -+lwux :: offset: 0x78, out: 0x709f7b7a -+lwux :: offset: 0x7c, out: 0x745e66cd -+lwux :: offset: 0x80, out: 0x9823b6e0 -+lwux :: offset: 0x84, out: 0x9ce2ab57 -+lwux :: offset: 0x88, out: 0x91a18d8e -+lwux :: offset: 0x8c, out: 0x95609039 -+lwux :: offset: 0x90, out: 0x8b27c03c -+lwux :: offset: 0x94, out: 0x8fe6dd8b -+lwux :: offset: 0x98, out: 0x82a5fb52 -+lwux :: offset: 0x9c, out: 0x8664e6e5 -+lwux :: offset: 0xa0, out: 0xbe2b5b58 -+lwux :: offset: 0xa4, out: 0xbaea46ef -+lwux :: offset: 0xa8, out: 0xb7a96036 -+lwux :: offset: 0xac, out: 0xb3687d81 -+lwux :: offset: 0xb0, out: 0xad2f2d84 -+lwux :: offset: 0xb4, out: 0xa9ee3033 -+lwux :: offset: 0xb8, out: 0xa4ad16ea -+lwux :: offset: 0xbc, out: 0xa06c0b5d -+lwux :: offset: 0xc0, out: 0xd4326d90 -+lwux :: offset: 0xc4, out: 0xd0f37027 -+lwux :: offset: 0xc8, out: 0xddb056fe -+lwux :: offset: 0xcc, out: 0xd9714b49 -+lwux :: offset: 0xd0, out: 0xc7361b4c -+lwux :: offset: 0xd4, out: 0xc3f706fb -+lwux :: offset: 0xd8, out: 0xceb42022 -+lwux :: offset: 0xdc, out: 0xca753d95 -+lwux :: offset: 0xe0, out: 0xf23a8028 -+lwux :: offset: 0xe4, out: 0xf6fb9d9f -+lwux :: offset: 0xe8, out: 0xfbb8bb46 -+lwux :: offset: 0xec, out: 0xff79a6f1 -+lwux :: offset: 0xf0, out: 0xe13ef6f4 -+lwux :: offset: 0xf4, out: 0xe5ffeb43 -+lwux :: offset: 0xf8, out: 0xe8bccd9a -+lwux :: offset: 0xfc, out: 0xec7dd02d -+lbx :: offset: 0x4, out: 0xffffffffffffffb7 -+lbx :: offset: 0x8, out: 0x6e -+lbx :: offset: 0xc, out: 0xffffffffffffffd9 -+lbx :: offset: 0x10, out: 0xffffffffffffffdc -+lbx :: offset: 0x14, out: 0x6b -+lbx :: offset: 0x18, out: 0xffffffffffffffb2 -+lbx :: offset: 0x1c, out: 0x5 -+lbx :: offset: 0x20, out: 0xffffffffffffffb8 -+lbx :: offset: 0x24, out: 0xf -+lbx :: offset: 0x28, out: 0xffffffffffffffd6 -+lbx :: offset: 0x2c, out: 0x61 -+lbx :: offset: 0x30, out: 0x64 -+lbx :: offset: 0x34, out: 0xffffffffffffffd3 -+lbx :: offset: 0x38, out: 0xa -+lbx :: offset: 0x3c, out: 0xffffffffffffffbd -+lbx :: offset: 0x40, out: 0x70 -+lbx :: offset: 0x44, out: 0xffffffffffffffc7 -+lbx :: offset: 0x48, out: 0x1e -+lbx :: offset: 0x4c, out: 0xffffffffffffffa9 -+lbx :: offset: 0x50, out: 0xffffffffffffffac -+lbx :: offset: 0x54, out: 0x1b -+lbx :: offset: 0x58, out: 0xffffffffffffffc2 -+lbx :: offset: 0x5c, out: 0x75 -+lbx :: offset: 0x60, out: 0xffffffffffffffc8 -+lbx :: offset: 0x64, out: 0x7f -+lbx :: offset: 0x68, out: 0xffffffffffffffa6 -+lbx :: offset: 0x6c, out: 0x11 -+lbx :: offset: 0x70, out: 0x14 -+lbx :: offset: 0x74, out: 0xffffffffffffffa3 -+lbx :: offset: 0x78, out: 0x7a -+lbx :: offset: 0x7c, out: 0xffffffffffffffcd -+lbx :: offset: 0x80, out: 0xffffffffffffffe0 -+lbx :: offset: 0x84, out: 0x57 -+lbx :: offset: 0x88, out: 0xffffffffffffff8e -+lbx :: offset: 0x8c, out: 0x39 -+lbx :: offset: 0x90, out: 0x3c -+lbx :: offset: 0x94, out: 0xffffffffffffff8b -+lbx :: offset: 0x98, out: 0x52 -+lbx :: offset: 0x9c, out: 0xffffffffffffffe5 -+lbx :: offset: 0xa0, out: 0x58 -+lbx :: offset: 0xa4, out: 0xffffffffffffffef -+lbx :: offset: 0xa8, out: 0x36 -+lbx :: offset: 0xac, out: 0xffffffffffffff81 -+lbx :: offset: 0xb0, out: 0xffffffffffffff84 -+lbx :: offset: 0xb4, out: 0x33 -+lbx :: offset: 0xb8, out: 0xffffffffffffffea -+lbx :: offset: 0xbc, out: 0x5d -+lbx :: offset: 0xc0, out: 0xffffffffffffff90 -+lbx :: offset: 0xc4, out: 0x27 -+lbx :: offset: 0xc8, out: 0xfffffffffffffffe -+lbx :: offset: 0xcc, out: 0x49 -+lbx :: offset: 0xd0, out: 0x4c -+lbx :: offset: 0xd4, out: 0xfffffffffffffffb -+lbx :: offset: 0xd8, out: 0x22 -+lbx :: offset: 0xdc, out: 0xffffffffffffff95 -+lbx :: offset: 0xe0, out: 0x28 -+lbx :: offset: 0xe4, out: 0xffffffffffffff9f -+lbx :: offset: 0xe8, out: 0x46 -+lbx :: offset: 0xec, out: 0xfffffffffffffff1 -+lbx :: offset: 0xf0, out: 0xfffffffffffffff4 -+lbx :: offset: 0xf4, out: 0x43 -+lbx :: offset: 0xf8, out: 0xffffffffffffff9a -+lbx :: offset: 0xfc, out: 0x2d -Index: none/tests/mips64/cvm_lx_ins.stdout.exp-non-octeon -=================================================================== -Index: none/tests/mips64/cvm_lx_ins.vgtest -=================================================================== ---- none/tests/mips64/cvm_lx_ins.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/cvm_lx_ins.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+prog: cvm_lx_ins -+prereq: ../../../tests/mips_features cavium-octeon2 -+vgopts: -q -Index: none/tests/mips64/load_indexed_instructions.c -=================================================================== ---- none/tests/mips64/load_indexed_instructions.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/load_indexed_instructions.c (.../trunk) (revision 13981) -@@ -0,0 +1,105 @@ -+#include -+const int reg_val[256] = { -+ 0x00000000L, 0x04c11db7L, 0x09823b6eL, 0x0d4326d9L, -+ 0x130476dcL, 0x17c56b6bL, 0x1a864db2L, 0x1e475005L, -+ 0x2608edb8L, 0x22c9f00fL, 0x2f8ad6d6L, 0x2b4bcb61L, -+ 0x350c9b64L, 0x31cd86d3L, 0x3c8ea00aL, 0x384fbdbdL, -+ 0x4c11db70L, 0x48d0c6c7L, 0x4593e01eL, 0x4152fda9L, -+ 0x5f15adacL, 0x5bd4b01bL, 0x569796c2L, 0x52568b75L, -+ 0x6a1936c8L, 0x6ed82b7fL, 0x639b0da6L, 0x675a1011L, -+ 0x791d4014L, 0x7ddc5da3L, 0x709f7b7aL, 0x745e66cdL, -+ 0x9823b6e0L, 0x9ce2ab57L, 0x91a18d8eL, 0x95609039L, -+ 0x8b27c03cL, 0x8fe6dd8bL, 0x82a5fb52L, 0x8664e6e5L, -+ 0xbe2b5b58L, 0xbaea46efL, 0xb7a96036L, 0xb3687d81L, -+ 0xad2f2d84L, 0xa9ee3033L, 0xa4ad16eaL, 0xa06c0b5dL, -+ 0xd4326d90L, 0xd0f37027L, 0xddb056feL, 0xd9714b49L, -+ 0xc7361b4cL, 0xc3f706fbL, 0xceb42022L, 0xca753d95L, -+ 0xf23a8028L, 0xf6fb9d9fL, 0xfbb8bb46L, 0xff79a6f1L, -+ 0xe13ef6f4L, 0xe5ffeb43L, 0xe8bccd9aL, 0xec7dd02dL, -+ 0x34867077L, 0x30476dc0L, 0x3d044b19L, 0x39c556aeL, -+ 0x278206abL, 0x23431b1cL, 0x2e003dc5L, 0x2ac12072L, -+ 0x128e9dcfL, 0x164f8078L, 0x1b0ca6a1L, 0x1fcdbb16L, -+ 0x018aeb13L, 0x054bf6a4L, 0x0808d07dL, 0x0cc9cdcaL, -+ 0x7897ab07L, 0x7c56b6b0L, 0x71159069L, 0x75d48ddeL, -+ 0x6b93dddbL, 0x6f52c06cL, 0x6211e6b5L, 0x66d0fb02L, -+ 0x5e9f46bfL, 0x5a5e5b08L, 0x571d7dd1L, 0x53dc6066L, -+ 0x4d9b3063L, 0x495a2dd4L, 0x44190b0dL, 0x40d816baL, -+ 0xaca5c697L, 0xa864db20L, 0xa527fdf9L, 0xa1e6e04eL, -+ 0xbfa1b04bL, 0xbb60adfcL, 0xb6238b25L, 0xb2e29692L, -+ 0x8aad2b2fL, 0x8e6c3698L, 0x832f1041L, 0x87ee0df6L, -+ 0x99a95df3L, 0x9d684044L, 0x902b669dL, 0x94ea7b2aL, -+ 0xe0b41de7L, 0xe4750050L, 0xe9362689L, 0xedf73b3eL, -+ 0xf3b06b3bL, 0xf771768cL, 0xfa325055L, 0xfef34de2L, -+ 0xc6bcf05fL, 0xc27dede8L, 0xcf3ecb31L, 0xcbffd686L, -+ 0xd5b88683L, 0xd1799b34L, 0xdc3abdedL, 0xd8fba05aL, -+ 0x690ce0eeL, 0x6dcdfd59L, 0x608edb80L, 0x644fc637L, -+ 0x7a089632L, 0x7ec98b85L, 0x738aad5cL, 0x774bb0ebL, -+ 0x4f040d56L, 0x4bc510e1L, 0x46863638L, 0x42472b8fL, -+ 0x5c007b8aL, 0x58c1663dL, 0x558240e4L, 0x51435d53L, -+ 0x251d3b9eL, 0x21dc2629L, 0x2c9f00f0L, 0x285e1d47L, -+ 0x36194d42L, 0x32d850f5L, 0x3f9b762cL, 0x3b5a6b9bL, -+ 0x0315d626L, 0x07d4cb91L, 0x0a97ed48L, 0x0e56f0ffL, -+ 0x1011a0faL, 0x14d0bd4dL, 0x19939b94L, 0x1d528623L, -+ 0xf12f560eL, 0xf5ee4bb9L, 0xf8ad6d60L, 0xfc6c70d7L, -+ 0xe22b20d2L, 0xe6ea3d65L, 0xeba91bbcL, 0xef68060bL, -+ 0xd727bbb6L, 0xd3e6a601L, 0xdea580d8L, 0xda649d6fL, -+ 0xc423cd6aL, 0xc0e2d0ddL, 0xcda1f604L, 0xc960ebb3L, -+ 0xbd3e8d7eL, 0xb9ff90c9L, 0xb4bcb610L, 0xb07daba7L, -+ 0xae3afba2L, 0xaafbe615L, 0xa7b8c0ccL, 0xa379dd7bL, -+ 0x9b3660c6L, 0x9ff77d71L, 0x92b45ba8L, 0x9675461fL, -+ 0x8832161aL, 0x8cf30badL, 0x81b02d74L, 0x857130c3L, -+ 0x5d8a9099L, 0x594b8d2eL, 0x5408abf7L, 0x50c9b640L, -+ 0x4e8ee645L, 0x4a4ffbf2L, 0x470cdd2bL, 0x43cdc09cL, -+ 0x7b827d21L, 0x7f436096L, 0x7200464fL, 0x76c15bf8L, -+ 0x68860bfdL, 0x6c47164aL, 0x61043093L, 0x65c52d24L, -+ 0x119b4be9L, 0x155a565eL, 0x18197087L, 0x1cd86d30L, -+ 0x029f3d35L, 0x065e2082L, 0x0b1d065bL, 0x0fdc1becL, -+ 0x3793a651L, 0x3352bbe6L, 0x3e119d3fL, 0x3ad08088L, -+ 0x2497d08dL, 0x2056cd3aL, 0x2d15ebe3L, 0x29d4f654L, -+ 0xc5a92679L, 0xc1683bceL, 0xcc2b1d17L, 0xc8ea00a0L, -+ 0xd6ad50a5L, 0xd26c4d12L, 0xdf2f6bcbL, 0xdbee767cL, -+ 0xe3a1cbc1L, 0xe760d676L, 0xea23f0afL, 0xeee2ed18L, -+ 0xf0a5bd1dL, 0xf464a0aaL, 0xf9278673L, 0xfde69bc4L, -+ 0x89b8fd09L, 0x8d79e0beL, 0x803ac667L, 0x84fbdbd0L, -+ 0x9abc8bd5L, 0x9e7d9662L, 0x933eb0bbL, 0x97ffad0cL, -+ 0xafb010b1L, 0xab710d06L, 0xa6322bdfL, 0xa2f33668L, -+ 0xbcb4666dL, 0xb8757bdaL, 0xb5365d03L, 0xb1f740b4L -+}; -+ -+/* -+Test 1 macro is used for ldx instructions. After executing each instructions -+the macro performs following operations: -+ -+1: Move arguments to registers. -+2: Execute instruction. -+3: Move result from register. */ -+ -+#define TEST1(instruction, offset, mem) \ -+{ \ -+ unsigned long out = 0; \ -+ __asm__ volatile( \ -+ "move $t0, %1" "\n\t" \ -+ "move $t1, %2" "\n\t" \ -+ instruction" $t2, $t1($t0)" "\n\t" \ -+ "move %0, $t2" "\n\t" \ -+ : "=&r" (out) \ -+ : "r" (mem) , "r" (offset) \ -+ : "t0", "t1", "t2", "cc", "memory" \ -+ ); \ -+ printf("%s :: offset: 0x%x, out: 0x%lx\n", \ -+ instruction, offset, out); \ -+} -+ -+int main() -+{ -+#if (_MIPS_ARCH_OCTEON2) || (__mips_dsp) -+ int i; -+ for(i = 8; i <= 255; i += 8) -+ TEST1("ldx", i, reg_val); -+ for(i = 8; i <= 255; i += 8) -+ TEST1("lbux", i, reg_val); -+ for(i = 8; i <= 255; i += 8) -+ TEST1("lwx", i, reg_val); -+#endif -+ return 0; -+} -Index: none/tests/mips64/load_indexed_instructions.stderr.exp -=================================================================== -Index: none/tests/mips64/load_indexed_instructions.stdout.exp-BE -=================================================================== ---- none/tests/mips64/load_indexed_instructions.stdout.exp-BE (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/load_indexed_instructions.stdout.exp-BE (.../trunk) (revision 13981) -@@ -0,0 +1,93 @@ -+ldx :: offset: 0x8, out: 0x9823b6e0d4326d9 -+ldx :: offset: 0x10, out: 0x130476dc17c56b6b -+ldx :: offset: 0x18, out: 0x1a864db21e475005 -+ldx :: offset: 0x20, out: 0x2608edb822c9f00f -+ldx :: offset: 0x28, out: 0x2f8ad6d62b4bcb61 -+ldx :: offset: 0x30, out: 0x350c9b6431cd86d3 -+ldx :: offset: 0x38, out: 0x3c8ea00a384fbdbd -+ldx :: offset: 0x40, out: 0x4c11db7048d0c6c7 -+ldx :: offset: 0x48, out: 0x4593e01e4152fda9 -+ldx :: offset: 0x50, out: 0x5f15adac5bd4b01b -+ldx :: offset: 0x58, out: 0x569796c252568b75 -+ldx :: offset: 0x60, out: 0x6a1936c86ed82b7f -+ldx :: offset: 0x68, out: 0x639b0da6675a1011 -+ldx :: offset: 0x70, out: 0x791d40147ddc5da3 -+ldx :: offset: 0x78, out: 0x709f7b7a745e66cd -+ldx :: offset: 0x80, out: 0x9823b6e09ce2ab57 -+ldx :: offset: 0x88, out: 0x91a18d8e95609039 -+ldx :: offset: 0x90, out: 0x8b27c03c8fe6dd8b -+ldx :: offset: 0x98, out: 0x82a5fb528664e6e5 -+ldx :: offset: 0xa0, out: 0xbe2b5b58baea46ef -+ldx :: offset: 0xa8, out: 0xb7a96036b3687d81 -+ldx :: offset: 0xb0, out: 0xad2f2d84a9ee3033 -+ldx :: offset: 0xb8, out: 0xa4ad16eaa06c0b5d -+ldx :: offset: 0xc0, out: 0xd4326d90d0f37027 -+ldx :: offset: 0xc8, out: 0xddb056fed9714b49 -+ldx :: offset: 0xd0, out: 0xc7361b4cc3f706fb -+ldx :: offset: 0xd8, out: 0xceb42022ca753d95 -+ldx :: offset: 0xe0, out: 0xf23a8028f6fb9d9f -+ldx :: offset: 0xe8, out: 0xfbb8bb46ff79a6f1 -+ldx :: offset: 0xf0, out: 0xe13ef6f4e5ffeb43 -+ldx :: offset: 0xf8, out: 0xe8bccd9aec7dd02d -+lbux :: offset: 0x8, out: 0x9 -+lbux :: offset: 0x10, out: 0x13 -+lbux :: offset: 0x18, out: 0x1a -+lbux :: offset: 0x20, out: 0x26 -+lbux :: offset: 0x28, out: 0x2f -+lbux :: offset: 0x30, out: 0x35 -+lbux :: offset: 0x38, out: 0x3c -+lbux :: offset: 0x40, out: 0x4c -+lbux :: offset: 0x48, out: 0x45 -+lbux :: offset: 0x50, out: 0x5f -+lbux :: offset: 0x58, out: 0x56 -+lbux :: offset: 0x60, out: 0x6a -+lbux :: offset: 0x68, out: 0x63 -+lbux :: offset: 0x70, out: 0x79 -+lbux :: offset: 0x78, out: 0x70 -+lbux :: offset: 0x80, out: 0x98 -+lbux :: offset: 0x88, out: 0x91 -+lbux :: offset: 0x90, out: 0x8b -+lbux :: offset: 0x98, out: 0x82 -+lbux :: offset: 0xa0, out: 0xbe -+lbux :: offset: 0xa8, out: 0xb7 -+lbux :: offset: 0xb0, out: 0xad -+lbux :: offset: 0xb8, out: 0xa4 -+lbux :: offset: 0xc0, out: 0xd4 -+lbux :: offset: 0xc8, out: 0xdd -+lbux :: offset: 0xd0, out: 0xc7 -+lbux :: offset: 0xd8, out: 0xce -+lbux :: offset: 0xe0, out: 0xf2 -+lbux :: offset: 0xe8, out: 0xfb -+lbux :: offset: 0xf0, out: 0xe1 -+lbux :: offset: 0xf8, out: 0xe8 -+lwx :: offset: 0x8, out: 0x9823b6e -+lwx :: offset: 0x10, out: 0x130476dc -+lwx :: offset: 0x18, out: 0x1a864db2 -+lwx :: offset: 0x20, out: 0x2608edb8 -+lwx :: offset: 0x28, out: 0x2f8ad6d6 -+lwx :: offset: 0x30, out: 0x350c9b64 -+lwx :: offset: 0x38, out: 0x3c8ea00a -+lwx :: offset: 0x40, out: 0x4c11db70 -+lwx :: offset: 0x48, out: 0x4593e01e -+lwx :: offset: 0x50, out: 0x5f15adac -+lwx :: offset: 0x58, out: 0x569796c2 -+lwx :: offset: 0x60, out: 0x6a1936c8 -+lwx :: offset: 0x68, out: 0x639b0da6 -+lwx :: offset: 0x70, out: 0x791d4014 -+lwx :: offset: 0x78, out: 0x709f7b7a -+lwx :: offset: 0x80, out: 0xffffffff9823b6e0 -+lwx :: offset: 0x88, out: 0xffffffff91a18d8e -+lwx :: offset: 0x90, out: 0xffffffff8b27c03c -+lwx :: offset: 0x98, out: 0xffffffff82a5fb52 -+lwx :: offset: 0xa0, out: 0xffffffffbe2b5b58 -+lwx :: offset: 0xa8, out: 0xffffffffb7a96036 -+lwx :: offset: 0xb0, out: 0xffffffffad2f2d84 -+lwx :: offset: 0xb8, out: 0xffffffffa4ad16ea -+lwx :: offset: 0xc0, out: 0xffffffffd4326d90 -+lwx :: offset: 0xc8, out: 0xffffffffddb056fe -+lwx :: offset: 0xd0, out: 0xffffffffc7361b4c -+lwx :: offset: 0xd8, out: 0xffffffffceb42022 -+lwx :: offset: 0xe0, out: 0xfffffffff23a8028 -+lwx :: offset: 0xe8, out: 0xfffffffffbb8bb46 -+lwx :: offset: 0xf0, out: 0xffffffffe13ef6f4 -+lwx :: offset: 0xf8, out: 0xffffffffe8bccd9a -Index: none/tests/mips64/load_indexed_instructions.stdout.exp-LE -=================================================================== ---- none/tests/mips64/load_indexed_instructions.stdout.exp-LE (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/load_indexed_instructions.stdout.exp-LE (.../trunk) (revision 13981) -@@ -0,0 +1,93 @@ -+ldx :: offset: 0x8, out: 0xd4326d909823b6e -+ldx :: offset: 0x10, out: 0x17c56b6b130476dc -+ldx :: offset: 0x18, out: 0x1e4750051a864db2 -+ldx :: offset: 0x20, out: 0x22c9f00f2608edb8 -+ldx :: offset: 0x28, out: 0x2b4bcb612f8ad6d6 -+ldx :: offset: 0x30, out: 0x31cd86d3350c9b64 -+ldx :: offset: 0x38, out: 0x384fbdbd3c8ea00a -+ldx :: offset: 0x40, out: 0x48d0c6c74c11db70 -+ldx :: offset: 0x48, out: 0x4152fda94593e01e -+ldx :: offset: 0x50, out: 0x5bd4b01b5f15adac -+ldx :: offset: 0x58, out: 0x52568b75569796c2 -+ldx :: offset: 0x60, out: 0x6ed82b7f6a1936c8 -+ldx :: offset: 0x68, out: 0x675a1011639b0da6 -+ldx :: offset: 0x70, out: 0x7ddc5da3791d4014 -+ldx :: offset: 0x78, out: 0x745e66cd709f7b7a -+ldx :: offset: 0x80, out: 0x9ce2ab579823b6e0 -+ldx :: offset: 0x88, out: 0x9560903991a18d8e -+ldx :: offset: 0x90, out: 0x8fe6dd8b8b27c03c -+ldx :: offset: 0x98, out: 0x8664e6e582a5fb52 -+ldx :: offset: 0xa0, out: 0xbaea46efbe2b5b58 -+ldx :: offset: 0xa8, out: 0xb3687d81b7a96036 -+ldx :: offset: 0xb0, out: 0xa9ee3033ad2f2d84 -+ldx :: offset: 0xb8, out: 0xa06c0b5da4ad16ea -+ldx :: offset: 0xc0, out: 0xd0f37027d4326d90 -+ldx :: offset: 0xc8, out: 0xd9714b49ddb056fe -+ldx :: offset: 0xd0, out: 0xc3f706fbc7361b4c -+ldx :: offset: 0xd8, out: 0xca753d95ceb42022 -+ldx :: offset: 0xe0, out: 0xf6fb9d9ff23a8028 -+ldx :: offset: 0xe8, out: 0xff79a6f1fbb8bb46 -+ldx :: offset: 0xf0, out: 0xe5ffeb43e13ef6f4 -+ldx :: offset: 0xf8, out: 0xec7dd02de8bccd9a -+lbux :: offset: 0x8, out: 0x6e -+lbux :: offset: 0x10, out: 0xdc -+lbux :: offset: 0x18, out: 0xb2 -+lbux :: offset: 0x20, out: 0xb8 -+lbux :: offset: 0x28, out: 0xd6 -+lbux :: offset: 0x30, out: 0x64 -+lbux :: offset: 0x38, out: 0xa -+lbux :: offset: 0x40, out: 0x70 -+lbux :: offset: 0x48, out: 0x1e -+lbux :: offset: 0x50, out: 0xac -+lbux :: offset: 0x58, out: 0xc2 -+lbux :: offset: 0x60, out: 0xc8 -+lbux :: offset: 0x68, out: 0xa6 -+lbux :: offset: 0x70, out: 0x14 -+lbux :: offset: 0x78, out: 0x7a -+lbux :: offset: 0x80, out: 0xe0 -+lbux :: offset: 0x88, out: 0x8e -+lbux :: offset: 0x90, out: 0x3c -+lbux :: offset: 0x98, out: 0x52 -+lbux :: offset: 0xa0, out: 0x58 -+lbux :: offset: 0xa8, out: 0x36 -+lbux :: offset: 0xb0, out: 0x84 -+lbux :: offset: 0xb8, out: 0xea -+lbux :: offset: 0xc0, out: 0x90 -+lbux :: offset: 0xc8, out: 0xfe -+lbux :: offset: 0xd0, out: 0x4c -+lbux :: offset: 0xd8, out: 0x22 -+lbux :: offset: 0xe0, out: 0x28 -+lbux :: offset: 0xe8, out: 0x46 -+lbux :: offset: 0xf0, out: 0xf4 -+lbux :: offset: 0xf8, out: 0x9a -+lwx :: offset: 0x8, out: 0x9823b6e -+lwx :: offset: 0x10, out: 0x130476dc -+lwx :: offset: 0x18, out: 0x1a864db2 -+lwx :: offset: 0x20, out: 0x2608edb8 -+lwx :: offset: 0x28, out: 0x2f8ad6d6 -+lwx :: offset: 0x30, out: 0x350c9b64 -+lwx :: offset: 0x38, out: 0x3c8ea00a -+lwx :: offset: 0x40, out: 0x4c11db70 -+lwx :: offset: 0x48, out: 0x4593e01e -+lwx :: offset: 0x50, out: 0x5f15adac -+lwx :: offset: 0x58, out: 0x569796c2 -+lwx :: offset: 0x60, out: 0x6a1936c8 -+lwx :: offset: 0x68, out: 0x639b0da6 -+lwx :: offset: 0x70, out: 0x791d4014 -+lwx :: offset: 0x78, out: 0x709f7b7a -+lwx :: offset: 0x80, out: 0xffffffff9823b6e0 -+lwx :: offset: 0x88, out: 0xffffffff91a18d8e -+lwx :: offset: 0x90, out: 0xffffffff8b27c03c -+lwx :: offset: 0x98, out: 0xffffffff82a5fb52 -+lwx :: offset: 0xa0, out: 0xffffffffbe2b5b58 -+lwx :: offset: 0xa8, out: 0xffffffffb7a96036 -+lwx :: offset: 0xb0, out: 0xffffffffad2f2d84 -+lwx :: offset: 0xb8, out: 0xffffffffa4ad16ea -+lwx :: offset: 0xc0, out: 0xffffffffd4326d90 -+lwx :: offset: 0xc8, out: 0xffffffffddb056fe -+lwx :: offset: 0xd0, out: 0xffffffffc7361b4c -+lwx :: offset: 0xd8, out: 0xffffffffceb42022 -+lwx :: offset: 0xe0, out: 0xfffffffff23a8028 -+lwx :: offset: 0xe8, out: 0xfffffffffbb8bb46 -+lwx :: offset: 0xf0, out: 0xffffffffe13ef6f4 -+lwx :: offset: 0xf8, out: 0xffffffffe8bccd9a -Index: none/tests/mips64/load_indexed_instructions.stdout.exp-non-octeon -=================================================================== -Index: none/tests/mips64/load_indexed_instructions.vgtest -=================================================================== ---- none/tests/mips64/load_indexed_instructions.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/load_indexed_instructions.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+prog: load_indexed_instructions -+prereq: ../../../tests/mips_features cavium-octeon2 -+vgopts: -q -Index: none/tests/mips64/test_math.cpp -=================================================================== ---- none/tests/mips64/test_math.cpp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/test_math.cpp (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+link ../mips32/test_math.cpp -\ No newline at end of file - -Property changes on: none/tests/mips64/test_math.cpp -___________________________________________________________________ -Added: svn:special -## -0,0 +1 ## -+* -\ No newline at end of property -Index: none/tests/mips64/test_math.stderr.exp -=================================================================== -Index: none/tests/mips64/test_math.stdout.exp -=================================================================== ---- none/tests/mips64/test_math.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/test_math.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,55 @@ -+fesetround(FE_UPWARD) -+lrint(1234.01): 1235 -+lrintf(1234.01f): 1235 -+lrintl(1234.01): 1234 -+fesetround(FE_TOWARDZERO) -+lrint(1234.01): 1234 -+lrintf(1234.01f): 1234 -+lrintl(1234.01): 1234 -+fesetround(FE_UPWARD) -+llrint(1234.01): 1235 -+llrintf(1234.01f): 1235 -+llrintf(1234.01f): 1234 -+fesetround(FE_TOWARDZERO) -+llrint(1234.01): 1234 -+llrintf(1234.01f): 1234 -+llrintl(1234.01): 1234 -+fesetround(FE_UPWARD) -+feclearexcept(FE_ALL_EXCEPT) -+rint(1234.0): 1234.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0 -+rint(1234.01): 1235.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4 -+feclearexcept(FE_ALL_EXCEPT) -+rintf(1234.0f): 1234.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0 -+rintf(1234.01f): 1235.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 4 -+feclearexcept(FE_ALL_EXCEPT) -+rintl(1234.0): 1234.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0 -+rintl(1234.01): 1234.000000 -+(fetestexcept(FE_ALL_EXCEPT) & FE_INEXACT): 0 -+fesetround(FE_TOWARDZERO) -+rint(1234.01): 1234.000000 -+rintf(1234.01f): 1234.000000 -+rintl(1234.01): 1234.000000 -+fesetround(FE_UPWARD) -+feclearexcept(FE_ALL_EXCEPT) -+nearbyint(1234.0): 1234.000000 -+nearbyint(1234.01): 1235.000000 -+feclearexcept(FE_ALL_EXCEPT) -+nearbyintf(1234.0f): 1234.000000 -+nearbyintf(1234.01f): 1235.000000 -+feclearexcept(FE_ALL_EXCEPT) -+nearbyintl(1234.0f): 1234.000000 -+nearbyintl(1234.01f): 1234.000000 -+fesetround(FE_TOWARDZERO) -+nearbyint(1234.01): 1234.000000 -+nearbyintf(1234.01f): 1234.000000 -+nearbyintl(1234.01): 1234.000000 -+log(M_E): 1.000000 -+tgamma(5.0): 24.000000 -+cbrt(27.0): 3.000000 -+feclearexcept(FE_ALL_EXCEPT): 0 -+raised: 32 -Index: none/tests/mips64/test_math.vgtest -=================================================================== ---- none/tests/mips64/test_math.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/mips64/test_math.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+link ../mips32/test_math.vgtest -\ No newline at end of file - -Property changes on: none/tests/mips64/test_math.vgtest -___________________________________________________________________ -Added: svn:special -## -0,0 +1 ## -+* -\ No newline at end of property -Index: none/tests/ppc32 -=================================================================== ---- none/tests/ppc32 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/ppc32 (.../trunk) (revision 13981) - -Property changes on: none/tests/ppc32 -___________________________________________________________________ -Modified: svn:ignore -## -32,3 +32,7 ## - test_isa_2_06_part3 - test_isa_2_07_part1 - test_isa_2_07_part2 -+data-cache-instructions -+ldst_multiple -+test_tm -+test_touch_tm -Index: none/tests/ppc32/Makefile.am -=================================================================== ---- none/tests/ppc32/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/ppc32/Makefile.am (.../trunk) (revision 13981) -@@ -43,7 +43,9 @@ - jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.vgtest \ - test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \ - test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \ -- test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest -+ test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \ -+ ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \ -+ data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest - - - check_PROGRAMS = \ -@@ -59,7 +61,9 @@ - test_isa_2_07_part1 \ - test_isa_2_07_part2 \ - test_tm \ -- test_touch_tm -+ test_touch_tm \ -+ ldst_multiple \ -+ data-cache-instructions - - AM_CFLAGS += @FLAG_M32@ - AM_CXXFLAGS += @FLAG_M32@ -Index: none/tests/ppc32/data-cache-instructions.c -=================================================================== ---- none/tests/ppc32/data-cache-instructions.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/data-cache-instructions.c (.../trunk) (revision 13981) -@@ -0,0 +1,96 @@ -+/******************************************************************************* -+ * Derived from the test case for the "dcbzl" instruction support by -+ * Dave Goodell * -+ * (see: Bug 135264 - dcbzl instruction missing) -+ * and: coregrind/m_machine.c/find_ppc_dcbz_sz() -+ ******************************************************************************/ -+ -+/* ensure we have posix_memalign */ -+#define _POSIX_C_SOURCE 200112L -+ -+#include -+#include -+#include -+#include -+ -+static int query_block_size(void) -+{ -+#define MAX_DCBZL_SZB (128) /* largest known effect of dcbzl */ -+ char *test_block = NULL; -+ register char *rb asm ("r14"); -+ int block_size, test_block_size = 4 * MAX_DCBZL_SZB, err; -+ char *p; -+ -+ err = posix_memalign ((void **)&test_block, MAX_DCBZL_SZB, test_block_size); -+ if (err) { -+ fprintf(stderr, "posix_memalign() failed (err = %d [%s])\n", err, strerror(err)); -+ return err; -+ } -+ -+ rb = test_block; -+ -+ memset(rb, 0xff, test_block_size); -+ asm volatile ("dcbzl 0, %[RB]" : : [RB] "r" (rb)); -+ for (block_size = 0, p = rb; (p - rb) < test_block_size; p++) -+ if (!*p) -+ block_size++; -+ assert(block_size == 16 || block_size == 32 || block_size == 64 || block_size == 128); -+ -+ free(test_block); -+ return block_size; -+} -+ -+/* Test dcbzl at addr in buffer given dcbzl_block_size */ -+static void test_dcbzl_at(char *addr, char *buffer, int block_size) -+{ -+ int i; -+ -+ /* Note: Assumption is that the length of buffer is three times the block_size. */ -+ memset(buffer, 0xff, 3 * block_size); -+ asm volatile ("dcbzl %[RA], %[RB]" : : [RA] "r" (0), [RB] "r" (addr)); -+ for (i = 0; i < block_size; i++) { -+ assert(buffer[i] == 0xff); -+ assert(buffer[block_size + i] == 0x00); -+ assert(buffer[2 * block_size + i] == 0xff); -+ } -+} -+ -+/* Test for insn: dcbzl */ -+static int test_dcbzl(void) -+{ -+ int err; -+ char *buffer = NULL; -+ int buffer_size; -+ int block_size; -+ -+ block_size = query_block_size(); -+ assert(block_size == 16 || block_size == 32 || block_size == 64 || block_size == 128); -+ buffer_size = 3 * block_size; -+ err = posix_memalign((void **) &buffer, block_size, buffer_size); -+ if (err) { -+ fprintf(stderr, "posix_memalign() failed (err = %d [%s])\n", err, strerror(err)); -+ return err; -+ } -+ -+ /* check at aligned address within the test block */ -+ test_dcbzl_at(&buffer[block_size], buffer, block_size); -+ fprintf(stdout, "Passed dcbzl test at aligned address within the test block.\n"); -+ -+ /* check at un-aligned (1 modulo block_size) address within the test block */ -+ test_dcbzl_at(&buffer[block_size+1], buffer, block_size); -+ fprintf(stdout, "Passed dcbzl test at un-aligned (1 modulo block_size) address within the test block.\n"); -+ -+ /* check at un-aligned ((block_size - 1) modulo block_size) address within the test block */ -+ test_dcbzl_at(&buffer[2 * block_size - 1], buffer, block_size); -+ fprintf(stdout, "Passed dcbzl test at un-aligned ((block_size - 1) modulo block_size) address within the test block.\n"); -+ -+ free(buffer); -+ return 0; -+} -+ -+int main(int argc, char **argv) -+{ -+ int status; -+ status = test_dcbzl (); -+ return status; -+} -Index: none/tests/ppc32/data-cache-instructions.stderr.exp -=================================================================== ---- none/tests/ppc32/data-cache-instructions.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/data-cache-instructions.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+ -+ -Index: none/tests/ppc32/data-cache-instructions.stdout.exp -=================================================================== ---- none/tests/ppc32/data-cache-instructions.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/data-cache-instructions.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+Passed dcbzl test at aligned address within the test block. -+Passed dcbzl test at un-aligned (1 modulo block_size) address within the test block. -+Passed dcbzl test at un-aligned ((block_size - 1) modulo block_size) address within the test block. -Index: none/tests/ppc32/data-cache-instructions.vgtest -=================================================================== ---- none/tests/ppc32/data-cache-instructions.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/data-cache-instructions.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prereq: ../../../tests/power_insn_available dcbzl -+prog: data-cache-instructions -Index: none/tests/ppc32/ldst_multiple.c -=================================================================== ---- none/tests/ppc32/ldst_multiple.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/ldst_multiple.c (.../trunk) (revision 13981) -@@ -0,0 +1,191 @@ -+#include -+#include -+ -+#ifndef __powerpc64__ -+typedef uint32_t HWord_t; -+#else -+typedef uint64_t HWord_t; -+#endif -+ -+typedef void (*test_func_t)(); -+ -+typedef struct test_table { -+ test_func_t func; -+ char *name; -+} test_table_t; -+ -+static uint32_t values[] = { -+ 0x6efbcfdf, -+ 0xd16c2fd4, -+ 0xf9dc1743, -+ 0xa5aa0bd4, -+ 0x6c8f0c14, -+ 0x69a24188, -+ 0x53b57f1b, -+}; -+ -+register HWord_t r27 asm("r27"); -+register HWord_t r28 asm("r28"); -+register HWord_t r29 asm("r29"); -+register HWord_t r30 asm("r30"); -+register HWord_t r31 asm("r31"); -+ -+register HWord_t r14 asm("r14"); -+ -+HWord_t temp[5]; -+ -+#ifdef __powerpc64__ -+ -+#define SAVE_REGS(addr) \ -+ asm volatile( \ -+ " std 27, 0(%0) \n" \ -+ " std 28, 8(%0) \n" \ -+ " std 29, 16(%0) \n" \ -+ " std 30, 24(%0) \n" \ -+ " std 31, 32(%0) \n" \ -+ ::"b"(addr)) -+ -+#define RESTORE_REGS(addr) \ -+ asm volatile( \ -+ " ld 27, 0(%0) \n" \ -+ " ld 28, 8(%0) \n" \ -+ " ld 29, 16(%0) \n" \ -+ " ld 30, 24(%0) \n" \ -+ " ld 31, 32(%0) \n" \ -+ ::"b"(addr)) -+ -+#else /* !__powerpc64__ */ -+ -+#define SAVE_REGS(addr) \ -+ asm volatile( \ -+ " stw 27, 0(%0) \n" \ -+ " stw 28, 4(%0) \n" \ -+ " stw 29, 8(%0) \n" \ -+ " stw 30, 12(%0) \n" \ -+ " stw 31, 16(%0) \n" \ -+ ::"b"(addr)) -+ -+#define RESTORE_REGS(addr) \ -+ asm volatile( \ -+ " lwz 27, 0(%0) \n" \ -+ " lwz 28, 4(%0) \n" \ -+ " lwz 29, 8(%0) \n" \ -+ " lwz 30, 12(%0) \n" \ -+ " lwz 31, 16(%0) \n" \ -+ ::"b"(addr)) -+ -+#endif /* __powerpc64__ */ -+ -+/* -+ * gcc is not happy if we modify r31 (the frame pointer) behind its back -+ * so we omit it -+ */ -+static void __attribute__((optimize("-fomit-frame-pointer"))) test_lmw(void) -+{ -+ r14 = (HWord_t)values; -+ -+ /* save r27 - r31 */ -+ SAVE_REGS(temp); -+ -+ /* load r27 - r31 */ -+ asm volatile( -+ " lmw %r27, 0(%r14) \n"); -+ -+#ifdef __powerpc64__ -+ printf("lmw => %016lx %016lx %016lx %016lx %016lx\n", -+#else -+ printf("lmw => %08x %08x %08x %08x %08x\n", -+#endif -+ r27, r28, r29, r30, r31); -+ -+ /* -+ * test load multiple with nonzero immediate offset -+ * load the last two values into r30 - r31. -+ * r27 - r29 should remain the same -+ */ -+ asm volatile( -+ " lmw %r30, 20(%r14) \n"); -+ -+#ifdef __powerpc64__ -+ printf("lmw => %016lx %016lx %016lx %016lx %016lx\n", -+#else -+ printf("lmw => %08x %08x %08x %08x %08x\n", -+#endif -+ r27, r28, r29, r30, r31); -+ -+ /* restore r27 - r31 */ -+ RESTORE_REGS(temp); -+} -+ -+/* -+ * gcc is not happy if we modify r31 (the frame pointer) behind its back -+ * so we omit it -+ */ -+static void __attribute__((optimize("-fomit-frame-pointer"))) test_stmw(void) -+{ -+ uint32_t result[7] = { 0 }; -+ int i; -+ -+ SAVE_REGS(temp); -+ -+#ifdef __powerpc64__ -+ asm volatile( -+ " lwz 27, 0(%0) \n" \ -+ " lwz 28, 4(%0) \n" \ -+ " lwz 29, 8(%0) \n" \ -+ " lwz 30, 12(%0) \n" \ -+ " lwz 31, 16(%0) \n" \ -+ ::"b"(values)); -+#else -+ RESTORE_REGS(values); -+#endif -+ -+ r14 = (HWord_t)&result; -+ -+ /* store r27 - r31 */ -+ asm volatile( -+ " stmw %r27, 0(%r14) \n"); -+ -+ printf("stmw => "); -+ for (i = 0; i < sizeof(result) / sizeof(result[0]); i++) -+ printf("%08x ", result[i]); -+ -+ printf("\n"); -+ -+ /* -+ * test store multiple with nonzero immediate offset -+ * store r30 - r31 into the last two places in the array -+ * the rest of the array should remain the same -+ */ -+ asm volatile( -+ " stmw %r30, 20(%r14) \n"); -+ -+ printf("stmw => "); -+ for (i = 0; i < sizeof(result) / sizeof(result[0]); i++) -+ printf("%08x ", result[i]); -+ -+ printf("\n"); -+ -+ RESTORE_REGS(temp); -+} -+ -+static test_table_t all_tests[] = { -+ { &test_lmw, -+ "Test Load Multiple instruction" }, -+ { &test_stmw, -+ "Test Store Multiple instruction" }, -+ { NULL, NULL }, -+}; -+ -+int main(void) -+{ -+ test_func_t func; -+ int i = 0; -+ -+ while ((func = all_tests[i].func)) { -+ (*func)(); -+ i++; -+ } -+ -+ return 0; -+} -Index: none/tests/ppc32/ldst_multiple.stderr.exp -=================================================================== ---- none/tests/ppc32/ldst_multiple.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/ldst_multiple.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+ -+ -Index: none/tests/ppc32/ldst_multiple.stdout.exp -=================================================================== ---- none/tests/ppc32/ldst_multiple.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/ldst_multiple.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,4 @@ -+lmw => 6efbcfdf d16c2fd4 f9dc1743 a5aa0bd4 6c8f0c14 -+lmw => 6efbcfdf d16c2fd4 f9dc1743 69a24188 53b57f1b -+stmw => 6efbcfdf d16c2fd4 f9dc1743 a5aa0bd4 6c8f0c14 00000000 00000000 -+stmw => 6efbcfdf d16c2fd4 f9dc1743 a5aa0bd4 6c8f0c14 a5aa0bd4 6c8f0c14 -Index: none/tests/ppc32/ldst_multiple.vgtest -=================================================================== ---- none/tests/ppc32/ldst_multiple.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc32/ldst_multiple.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+prog: ldst_multiple -Index: none/tests/ppc64 -=================================================================== ---- none/tests/ppc64 (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/ppc64 (.../trunk) (revision 13981) - -Property changes on: none/tests/ppc64 -___________________________________________________________________ -Modified: svn:ignore -## -24,3 +24,7 ## - test_isa_2_07_part1 - test_isa_2_07_part2 - allexec -+data-cache-instructions -+ldst_multiple -+test_tm -+test_touch_tm -Index: none/tests/ppc64/Makefile.am -=================================================================== ---- none/tests/ppc64/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/ppc64/Makefile.am (.../trunk) (revision 13981) -@@ -31,7 +31,9 @@ - jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.vgtest \ - test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \ - test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \ -- test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest -+ test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \ -+ ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \ -+ data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest - - check_PROGRAMS = \ - allexec \ -@@ -39,7 +41,7 @@ - power6_mf_gpr test_isa_2_06_part1 test_isa_2_06_part2 \ - test_isa_2_06_part3 test_dfp1 test_dfp2 test_dfp3 test_dfp4 \ - test_dfp5 test_isa_2_07_part1 test_isa_2_07_part2 \ -- test_tm test_touch_tm -+ test_tm test_touch_tm ldst_multiple data-cache-instructions - - AM_CFLAGS += @FLAG_M64@ - AM_CXXFLAGS += @FLAG_M64@ -Index: none/tests/ppc64/data-cache-instructions.c -=================================================================== ---- none/tests/ppc64/data-cache-instructions.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/data-cache-instructions.c (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+link ../ppc32/data-cache-instructions.c -\ No newline at end of file - -Property changes on: none/tests/ppc64/data-cache-instructions.c -___________________________________________________________________ -Added: svn:special -## -0,0 +1 ## -+* -\ No newline at end of property -Index: none/tests/ppc64/data-cache-instructions.stderr.exp -=================================================================== ---- none/tests/ppc64/data-cache-instructions.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/data-cache-instructions.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+ -+ -Index: none/tests/ppc64/data-cache-instructions.stdout.exp -=================================================================== ---- none/tests/ppc64/data-cache-instructions.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/data-cache-instructions.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+Passed dcbzl test at aligned address within the test block. -+Passed dcbzl test at un-aligned (1 modulo block_size) address within the test block. -+Passed dcbzl test at un-aligned ((block_size - 1) modulo block_size) address within the test block. -Index: none/tests/ppc64/data-cache-instructions.vgtest -=================================================================== ---- none/tests/ppc64/data-cache-instructions.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/data-cache-instructions.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+prereq: ../../../tests/power_insn_available dcbzl -+prog: data-cache-instructions -Index: none/tests/ppc64/ldst_multiple.c -=================================================================== ---- none/tests/ppc64/ldst_multiple.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/ldst_multiple.c (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+link ../ppc32/ldst_multiple.c -\ No newline at end of file - -Property changes on: none/tests/ppc64/ldst_multiple.c -___________________________________________________________________ -Added: svn:special -## -0,0 +1 ## -+* -\ No newline at end of property -Index: none/tests/ppc64/ldst_multiple.stderr.exp -=================================================================== ---- none/tests/ppc64/ldst_multiple.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/ldst_multiple.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+ -+ -Index: none/tests/ppc64/ldst_multiple.stdout.exp -=================================================================== ---- none/tests/ppc64/ldst_multiple.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/ldst_multiple.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,4 @@ -+lmw => 000000006efbcfdf 00000000d16c2fd4 00000000f9dc1743 00000000a5aa0bd4 000000006c8f0c14 -+lmw => 000000006efbcfdf 00000000d16c2fd4 00000000f9dc1743 0000000069a24188 0000000053b57f1b -+stmw => 6efbcfdf d16c2fd4 f9dc1743 a5aa0bd4 6c8f0c14 00000000 00000000 -+stmw => 6efbcfdf d16c2fd4 f9dc1743 a5aa0bd4 6c8f0c14 a5aa0bd4 6c8f0c14 -Index: none/tests/ppc64/ldst_multiple.vgtest -=================================================================== ---- none/tests/ppc64/ldst_multiple.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/ppc64/ldst_multiple.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+prog: ldst_multiple -Index: none/tests/s390x -=================================================================== ---- none/tests/s390x (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/s390x (.../trunk) (revision 13981) - -Property changes on: none/tests/s390x -___________________________________________________________________ -Modified: svn:ignore -## -122,3 +122,4 ## - dfpconv - srnmt - pfpo -+rxsbg -Index: none/tests/s390x/Makefile.am -=================================================================== ---- none/tests/s390x/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/s390x/Makefile.am (.../trunk) (revision 13981) -@@ -11,7 +11,7 @@ - ex_sig ex_clone cu14 cu14_1 cu41 fpconv ecag fpext fpext_warn \ - rounding-1 rounding-2 rounding-3 rounding-4 rounding-5 bfp-1 \ - bfp-2 bfp-3 bfp-4 srnm srnmb comp-1 comp-2 exrl tmll tm stmg \ -- ex clst mvc test_fork test_sig rounding-6 \ -+ ex clst mvc test_fork test_sig rounding-6 rxsbg\ - spechelper-alr spechelper-algr \ - spechelper-slr spechelper-slgr \ - spechelper-cr spechelper-clr \ -Index: none/tests/s390x/rxsbg.c -=================================================================== ---- none/tests/s390x/rxsbg.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/s390x/rxsbg.c (.../trunk) (revision 13981) -@@ -0,0 +1,78 @@ -+#include -+#include "opcodes.h" -+ -+#define DO_RXSBG(insn, _r1, _r2, i3, i4, i5) \ -+({ \ -+ register unsigned long r1 asm ("1") = _r1; \ -+ register unsigned long r2 asm ("2") = _r2; \ -+ int cc; \ -+ asm volatile( insn(1,2, i3, i4, i5) \ -+ "ipm %1\n" \ -+ "srl %1,28\n" \ -+ : "+d" (r1), "=d" (cc) \ -+ : "d" (r1), "d" (r2) \ -+ : "cc"); \ -+ printf(#insn " r1(==%16.16lX),r2(==%16.16lX),0x" #i3 ",0x" #i4 ",0x" #i5 " = %16.16lX (cc=%d)\n", _r1, _r2, r1, cc); \ -+}) -+ -+#define r1sweep(i, r2, i3, i4, i5) \ -+({ \ -+ DO_RXSBG(i, 000000000000000000ul, r2, i3, i4, i5); \ -+ DO_RXSBG(i, 0x0000ffffccccaaaaul, r2, i3, i4, i5); \ -+ DO_RXSBG(i, 0xfffffffffffffffful, r2, i3, i4, i5); \ -+}) -+ -+#define r2sweep(i, i3, i4, i5) \ -+({ \ -+ r1sweep(i, 0x0000000000000000ul, i3, i4, i5); \ -+ r1sweep(i, 0x5555ccccffff0000ul, i3, i4, i5); \ -+ r1sweep(i, 0xfffffffffffffffful, i3, i4, i5); \ -+}) -+ -+ -+/* min/max z=0/1 and some random number in the middle */ -+#define i3sweep(i, i4, i5) \ -+({ \ -+ r2sweep(i, 00, i4, i5); \ -+ r2sweep(i, 14, i4, i5); \ -+ r2sweep(i, 3f, i4, i5); \ -+ r2sweep(i, 80, i4, i5); \ -+ r2sweep(i, a1, i4, i5); \ -+ r2sweep(i, bf, i4, i5); \ -+}) -+ -+/* min/max t=0/1 and some random number in the middle */ -+#define i4sweep(i, i5) \ -+({ \ -+ i3sweep(i, 00, i5); \ -+ i3sweep(i, 2a, i5); \ -+ i3sweep(i, 3f, i5); \ -+ i3sweep(i, 80, i5); \ -+ i3sweep(i, 9e, i5); \ -+ i3sweep(i, bf, i5); \ -+}) -+ -+/* min/max and other shifts */ -+#define i5sweep(i) \ -+({ \ -+ i4sweep(i, 00); \ -+ i4sweep(i, 01); \ -+ i4sweep(i, 13); \ -+ i4sweep(i, 3e); \ -+ i4sweep(i, 3f); \ -+}) -+ -+ -+ -+ -+ -+ -+int main() -+{ -+ i5sweep(RISBG); -+ i5sweep(RNSBG); -+ i5sweep(ROSBG); -+ i5sweep(RXSBG); -+ -+ return 0; -+} -Index: none/tests/s390x/rxsbg.stderr.exp -=================================================================== ---- none/tests/s390x/rxsbg.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/s390x/rxsbg.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+ -+ -Index: none/tests/s390x/rxsbg.stdout.exp -=================================================================== ---- none/tests/s390x/rxsbg.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/s390x/rxsbg.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,6480 @@ -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x00 = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x00 = 7FFFF00000000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 0000FCCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 7FFFFCCCFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x00 = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x00 = 7FFFFFFF80000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000FFFFFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 7FFFFFFFFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x00 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x00 = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x00 = 0000F000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x00 = FFFFF000001FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 00000CCCFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 0000FCCCFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = FFFFFCCCFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 00000FFFFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x00 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x00 = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x00 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x00 = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 5555CCCCFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 5555CCCCFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 5555CCCCFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000FFFF800CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x00 = FFFFFFFF801FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x00 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x00 = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 5555CCCCFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 5555CCCCFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 5555CCCCFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x00 = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x00 = FFFFF00000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 0000FCCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = FFFFFCCCFFFF0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x00 = FFFFFFFF80000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000FFFFFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = FFFFFFFFFFFF0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 800000007FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 5555CCCC7FFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 5555CCCC7FFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 5555CCCC7FFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 5555CCCC00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 5555CCCCFFFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 000000007FFF0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 000000007FFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x01 = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x01 = 7FFFF00000000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 80000999FFFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 8000F999FFFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = FFFFF999FFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x01 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x01 = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x01 = 7FFFFFFF80000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 800000007FFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 8000FFFFFFFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = FFFFFFFFFFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x01 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x01 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x01 = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x01 = 0000F000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x01 = FFFFF000001FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 00000999FFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 0000F999FFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = FFFFF999FFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 00000FFFFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x01 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x01 = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x01 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x01 = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = AAAB9999FFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = AAAB9999FFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000FFFF800CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x01 = FFFFFFFF801FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x01 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x01 = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = AAAB9999FFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = AAAB9999FFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x01 = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x01 = FFFFF00000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 00000999FFFE0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 0000F999FFFE0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = FFFFF999FFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x01 = FFFFFFFF80000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 000000007FFE0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000FFFFFFFE0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = FFFFFFFFFFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 800000007FFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 800000007FFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 800000007FFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 800000007FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = AAAB99987FFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = AAAB99987FFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = AAAB99987FFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = AAAB999800000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 000000007FFE0000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 000000007FFE0000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 000000007FFE0000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 000000007FFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x13 = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x13 = 7FFFF00000000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 0000FFF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 7FFFFFF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x13 = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x13 = 7FFFFFFF80000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000FFFF8002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 7FFFFFFF8002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x13 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x13 = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF8000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF8001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x13 = 0000F000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x13 = FFFFF000001FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 00000FF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 0000FFF8000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = FFFFFFF8001FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 00000FFFFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x13 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x13 = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF8000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF8001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x13 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x13 = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 6667FFF8000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 6667FFF8001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000FFFF800CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x13 = FFFFFFFF801FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000FFFF800CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = FFFFFFFF801FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x13 = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x13 = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 6667FFF8000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 6667FFF8001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x13 = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x13 = FFFFF00000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 0000FFF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = FFFFFFF80002AAAE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x13 = FFFFFFFF80000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000FFFF8002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = FFFFFFFF8002AAAE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 800000007FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 6667FFF800000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 6667FFF80002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 000000000002AAAE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 000000007FFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3e = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3e = 7FFFF00000000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 0000F3333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 7FFFF3333FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3e = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3e = 7FFFFFFF80000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000FFFFBFFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 7FFFFFFFBFFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3e = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3e = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3e = 0000F000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3e = FFFFF000001FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 000003333FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 0000F3333FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = FFFFF3333FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 00000FFFFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3e = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3e = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3e = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3e = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 155573333FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 155573333FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 155573333FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000FFFF800CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3e = FFFFFFFF801FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 000000003FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000FFFFBFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = FFFFFFFFBFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3e = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3e = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 155573333FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 155573333FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 155573333FFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3e = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3e = FFFFF00000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 0000F3333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = FFFFF3333FFFC000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3e = FFFFFFFF80000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000FFFFBFFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = FFFFFFFFBFFFC000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 800000007FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 155573323FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 155573323FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 155573323FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 1555733200000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 155573333FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 000000003FFFC000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 000000007FFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3f = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3f = 7FFFF00000000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 0000F6667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 7FFFF6667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 8000FFFFCCCCAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3f = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3f = 7FFFFFFF80000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000FFFFFFFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 7FFFFFFFFFFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 8000FFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 8000FFFFCCCCAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3f = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3f = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3f = 0000F000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3f = FFFFF000001FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 000006667FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 0000F6667FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = FFFFF6667FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 00000FFFFFE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3f = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3f = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3f = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3f = 00000000001FFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 2AAAE6667FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 2AAAE6667FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 2AAAE6667FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFE00000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFECAAAA (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000FFFF800CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3f = FFFFFFFF801FFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 000000007FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000FFFFFFECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3f = 00000000000CAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3f = 00000000001FFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 2AAAE6667FE00000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 2AAAE6667FECAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 2AAAE6667FFFFFFE (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFE00001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFECAAAB (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3f = 0000F00000000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3f = FFFFF00000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 0000F6667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = FFFFF6667FFF8000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000FFFF80000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3f = FFFFFFFF80000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000FFFFFFFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = FFFFFFFFFFFF8000 (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000FFFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=1) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAB (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 8000000000000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 800000007FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 800000007FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 8000000000000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFE7FFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 2AAAE66600000000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 2AAAE6667FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 000000007FFF8000 (cc=2) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 000000007FFFFFFF (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 000000007FFFFFFF (cc=2) -+RISBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RISBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000001 (cc=2) -+RISBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000001 (cc=2) -+RISBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000001 (cc=2) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x00 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x00 = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 0000FCCCCCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 7FFFFCCCFFFF0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x00 = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x00 = 00000000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 0000CCCCCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x00 = 0000F000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x00 = FFFFF000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 0000FCCCCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = FFFFFCCCFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x00 = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x00 = 00000000001FFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 0000CCCCCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 0000CCCCCCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x00 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x00 = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 0000FCCCCCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = FFFFFCCCFFFF0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x00 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x00 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x00 = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 0000FCCCCCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 7FFFFCCCFFFF0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x00 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x00 = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x00 = 00000001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 0000CCCDCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCDFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x00 = 0000F001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x00 = FFFFF001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 0000FCCDCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = FFFFFCCDFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x00 = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x00 = 00000001FFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 0000CCCDCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCDFFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 0000CCCCCCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x00 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x00 = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 0000FCCCCCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = FFFFFCCCFFFF0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x01 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x01 = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 0000F999CCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = FFFFF999FFFE0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x01 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x01 = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x01 = 00000000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = 00009999CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x01 = 0000F000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x01 = FFFFF000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 0000F999CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = FFFFF999FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x01 = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x01 = 00000000001FFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = 00009999CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = 00009999CCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x01 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x01 = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 0000F999CCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = FFFFF999FFFE0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x01 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x01 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x01 = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 0000F999CCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = FFFFF999FFFE0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x01 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = FFFFFFFFFFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x01 = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x01 = 00000001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = 00009999CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB9999FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x01 = 0000F001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x01 = FFFFF001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000F999CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = FFFFF999FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x01 = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x01 = 00000001FFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = 00009999CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB9999FFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = 00009999CCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x01 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x01 = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 0000F999CCCC0000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = FFFFF999FFFE0000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x13 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x13 = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 0000FFF80000AAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 7FFFFFF80002AAAE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x13 = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x13 = 00000000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 0000FFF8000CAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF8001FFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x13 = 0000F000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x13 = FFFFF000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 0000FFF8000CAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = FFFFFFF8001FFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x13 = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x13 = 00000000001FFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 0000FFF8000CAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF8001FFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 0000FFF80000AAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x13 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x13 = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 0000FFF80000AAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = FFFFFFF80002AAAE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x13 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x13 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x13 = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 0000FFF80000AAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 7FFFFFF80002AAAE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x13 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x13 = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x13 = 00000001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 0000FFF9CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF9FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x13 = 0000F001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x13 = FFFFF001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 0000FFF9CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = FFFFFFF9FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x13 = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x13 = 00000001FFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 0000FFF9CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF9FFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 0000FFF80000AAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x13 = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x13 = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 0000FFF80000AAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = FFFFFFF80002AAAE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3e = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3e = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 0000F3330CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 7FFFF3333FFFC000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3e = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3e = 00000000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 000073330CCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3e = 0000F000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3e = FFFFF000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 0000F3330CCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = FFFFF3333FFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3e = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3e = 00000000001FFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 000073330CCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 000073330CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3e = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3e = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 0000F3330CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = FFFFF3333FFFC000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3e = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3e = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3e = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 0000F3330CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 7FFFF3333FFFC000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3e = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3e = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3e = 00000001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 00007333CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 15557333FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3e = 0000F001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3e = FFFFF001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000F333CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = FFFFF333FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3e = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3e = 00000001FFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 00007333CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 15557333FFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 000073330CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3e = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3e = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 0000F3330CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = FFFFF3333FFFC000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3f = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3f = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 0000F6664CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 7FFFF6667FFF8000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3f = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3f = 00000000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 0000E6664CCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3f = 0000F000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3f = FFFFF000001FFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 0000F6664CCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = FFFFF6667FFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3f = 00000000000CAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3f = 00000000001FFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 0000E6664CCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 0000E6664CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3f = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3f = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 0000F6664CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = FFFFF6667FFF8000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3f = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 7FFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3f = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3f = 7FFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 0000F6664CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 7FFFF6667FFF8000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3f = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 7FFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3f = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3f = 00000001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 0000E667CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE667FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3f = 0000F001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3f = FFFFF001FFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000F667CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = FFFFF667FFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3f = 00000001CCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3f = 00000001FFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 0000E667CCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE667FFFFFFFE (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 0000E6664CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3f = 0000F00000000000 (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3f = FFFFF00000000000 (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 0000F6664CCC8000 (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = FFFFF6667FFF8000 (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFE (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RNSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RNSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RNSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RNSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 00000CCCFFFF0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 00000CCCFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 00000FFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFE00001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFECAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 00000CCCFFFF0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 80000999FFFE0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 8000FFFFFFFEAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAABFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 00000999FFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 00000FFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAABFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFE00001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFECAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAABFFFFFFFEAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 00000999FFFE0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 0000FFFFFFFEAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 8000FFFFFFFEAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAABFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAABFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAABFFFFFFFEAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 0000FFFFFFFEAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 00000FF80002AAAE (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 0000FFFFCCCEAAAE (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 00000FF800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 00000FFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFE00001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFECAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFFFCCCEAAAE (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 00000FF80002AAAE (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 0000FFFFCCCEAAAE (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 0000FFFFCCCEAAAE (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFFFCCCEAAAE (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 0000FFFFCCCEAAAE (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 000003333FFFC000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 0000FFFFFFFFEAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 1555FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 000003333FE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 00000FFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 1555FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFE00001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFECAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 1555FFFFFFFFEAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 000003333FFFC000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 0000FFFFFFFFEAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 0000FFFFFFFFEAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 1555FFFFFFFFEAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 0000FFFFFFFFEAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 000006667FFF8000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 000006667FE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 00000FFFFFE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 0000FFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FE00000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAFFFFFFECAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFE00001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFECAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAFFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 000006667FFF8000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 8000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAFFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAFFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 0000FFFFFFFFAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 0000FFFFFFFFFFFF (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAB (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+ROSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000000 (cc=1) -+ROSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+ROSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x00 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 00000CCCFFFF0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = 0000F3333333AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x00 = FFFFF3330000FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x00 = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x00 = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 5555CCCCFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = 55553333332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x00 = AAAA3333001FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFFFFFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = FFFF0000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x00 = 00000000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 00000CCCFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = 0000F333332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x00 = FFFFF333001FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 00000FFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = 0000F000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x00 = FFFFF000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 5555CCCCFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = 55553333332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x00 = AAAA3333001FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFFFFFFFFE00001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = FFFF0000332CAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x00 = 00000000001FFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 5555CCCCFFFF0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = 555533333333AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x00 = AAAA33330000FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 00000CCCFFFF0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = 0000F3333333AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x00 = FFFFF3330000FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x00 = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x00 = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x00 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 00000CCCFFFF0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = 0000F3333333AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x00 = FFFFF3330000FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x00 = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x00 = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 5555CCCC00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = 55553333CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x00 = AAAA3333FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFFFFFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = FFFF0001CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x00 = 00000001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 00000CCC00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = 0000F333CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x00 = FFFFF333FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 00000FFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = 0000F001CCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x00 = FFFFF001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 5555CCCC00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = 55553333CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x00 = AAAA3333FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFFFFFE00000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = FFFF0001CCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x00 = 00000001FFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 5555CCCCFFFF0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = 555533333333AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x00 = AAAA33330000FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 00000CCCFFFF0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = 0000F3333333AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x00 = FFFFF3330000FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x00 = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x00 = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x00 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 80000999FFFE0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 8000F6663332AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x01 = 7FFFF6660001FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x01 = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x01 = 7FFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x01 = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = AAAB6666332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x01 = 55546666001FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFFFFFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = FFFF0000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x01 = 00000000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 00000999FFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = 0000F666332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x01 = FFFFF666001FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 00000FFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = 0000F000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x01 = FFFFF000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB9999FFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = AAAB6666332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x01 = 55546666001FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFFFFFFFFE00001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = FFFF0000332CAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x01 = 00000000001FFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB9999FFFE0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = AAAB66663332AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x01 = 555466660001FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 00000999FFFE0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = 0000F6663332AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x01 = FFFFF6660001FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x01 = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x01 = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x01 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x01 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 80000999FFFE0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 8000F6663332AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x01 = 7FFFF6660001FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x01 = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x01 = 7FFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x01 = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB999800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = AAAB6667CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x01 = 55546667FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFFFFFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = FFFF0001CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x01 = 00000001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000099800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = 0000F667CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x01 = FFFFF667FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 00000FFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = 0000F001CCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x01 = FFFFF001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB999800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = AAAB6667CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x01 = 55546667FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFFFFFE00000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = FFFF0001CCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x01 = 00000001FFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB9999FFFE0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = AAAB66663332AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x01 = 555466660001FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 00000999FFFE0000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = 0000F6663332AAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x01 = FFFFF6660001FFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x01 = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x01 = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x01 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x13 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 00000FF80002AAAE (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = 0000F007CCCE0004 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x13 = FFFFF007FFFD5551 (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x13 = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x13 = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 6667FFF800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 66670007CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x13 = 99980007FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFFFFFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = FFFF0000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x13 = 00000000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 00000FF800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = 0000F007CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x13 = FFFFF007FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 00000FFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = 0000F000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x13 = FFFFF000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 6667FFF800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 66670007CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x13 = 99980007FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFFFFFFFFE00001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = FFFF0000332CAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x13 = 00000000001FFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 6667FFF80002AAAE (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 66670007CCCE0004 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x13 = 99980007FFFD5551 (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 00000FF80002AAAE (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = 0000F007CCCE0004 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x13 = FFFFF007FFFD5551 (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x13 = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x13 = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x13 = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 00000FF80002AAAE (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = 0000F007CCCE0004 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x13 = FFFFF007FFFD5551 (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x13 = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x13 = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 6667FFF800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 66670007CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x13 = 99980007FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFFFFFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = FFFF0001CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x13 = 00000001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 00000FF800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = 0000F007CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x13 = FFFFF007FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 00000FFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = 0000F001CCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x13 = FFFFF001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 6667FFF800000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 66670007CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x13 = 99980007FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFFFFFE00000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = FFFF0001CCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x13 = 00000001FFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 6667FFF80002AAAE (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 66670007CCCE0004 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x13 = 99980007FFFD5551 (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 00000FF80002AAAE (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = 0000F007CCCE0004 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x13 = FFFFF007FFFD5551 (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x13 = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x13 = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x13 = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3e = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 000003333FFFC000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = 0000FCCCF3336AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3e = FFFFFCCCC0003FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3e = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3e = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 155573333FE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = 15558CCCF32CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3e = EAAA8CCCC01FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFFFFFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = FFFF0000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3e = 00000000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 000003333FE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = 0000FCCCF32CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3e = FFFFFCCCC01FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 00000FFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = 0000F000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3e = FFFFF000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 155573333FE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = 15558CCCF32CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3e = EAAA8CCCC01FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFFFFFFFFE00001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = FFFF0000332CAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3e = 00000000001FFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 155573333FFFC000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = 15558CCCF3336AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3e = EAAA8CCCC0003FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 000003333FFFC000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = 0000FCCCF3336AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3e = FFFFFCCCC0003FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3e = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3e = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3e = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 000003333FFFC000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = 0000FCCCF3336AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3e = FFFFFCCCC0003FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3e = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3e = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 1555733200000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = 15558CCDCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3e = EAAA8CCDFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFFFFFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = FFFF0001CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3e = 00000001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000033200000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = 0000FCCDCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3e = FFFFFCCDFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 00000FFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = 0000F001CCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3e = FFFFF001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 1555733200000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = 15558CCDCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3e = EAAA8CCDFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFFFFFE00000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = FFFF0001CCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3e = 00000001FFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 155573333FFFC000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = 15558CCCF3336AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3e = EAAA8CCCC0003FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 000003333FFFC000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = 0000FCCCF3336AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3e = FFFFFCCCC0003FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3e = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3e = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3e = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x00,0x3f = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 000006667FFF8000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = 0000F999B3332AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x00,0x3f = FFFFF99980007FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x00,0x3f = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x00,0x3f = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x00,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x2a,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAAE6667FE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = 2AAA1999B32CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x2a,0x3f = D5551999801FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFFFFFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = FFFF0000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x2a,0x3f = 00000000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x2a,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 000006667FE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = 0000F999B32CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x2a,0x3f = FFFFF999801FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 00000FFFFFE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = 0000F000332CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x2a,0x3f = FFFFF000001FFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x2a,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAAE6667FE00000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = 2AAA1999B32CAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x2a,0x3f = D5551999801FFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFFFFFFFFE00001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = FFFF0000332CAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x2a,0x3f = 00000000001FFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x2a,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x2a,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAAE6667FFF8000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = 2AAA1999B3332AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x3f,0x3f = D555199980007FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 000006667FFF8000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = 0000F999B3332AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x3f,0x3f = FFFFF99980007FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x3f,0x3f = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x3f,0x3f = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x3f,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 8000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x80,0x3f = 7FFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 000006667FFF8000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = 0000F999B3332AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x80,0x3f = FFFFF99980007FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 80000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 8000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x80,0x3f = 7FFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 8000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x80,0x3f = 7FFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x80,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0x9e,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAAE66600000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = 2AAA1999CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0x9e,0x3f = D5551999FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFFFFFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = FFFF0001CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0x9e,0x3f = 00000001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0x9e,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000066600000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = 0000F999CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0x9e,0x3f = FFFFF999FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 00000FFE00000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = 0000F001CCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0x9e,0x3f = FFFFF001FFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAAE66600000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = 2AAA1999CCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0x9e,0x3f = D5551999FFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFFFFFE00000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = FFFF0001CCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0x9e,0x3f = 00000001FFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0x9e,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0x9e,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x00,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAAE6667FFF8000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = 2AAA1999B3332AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x00,0xbf,0x3f = D555199980007FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = FFFF000033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x00,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x14,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x14,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x14,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 000006667FFF8000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = 0000F999B3332AAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x14,0xbf,0x3f = FFFFF99980007FFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 00000FFFFFFFFFFF (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = 0000F00033335555 (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x14,0xbf,0x3f = FFFFF00000000000 (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000000000000001 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = 0000FFFFCCCCAAAB (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x3f,0xbf,0x3f = FFFFFFFFFFFFFFFE (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0x80,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0x80,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xa1,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0) -+RXSBG r1(==0000000000000000),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==0000000000000000),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==0000000000000000),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000000000000000 (cc=0) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=0) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==5555CCCCFFFF0000),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=1) -+RXSBG r1(==0000000000000000),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000000000000000 (cc=1) -+RXSBG r1(==0000FFFFCCCCAAAA),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = 0000FFFFCCCCAAAA (cc=1) -+RXSBG r1(==FFFFFFFFFFFFFFFF),r2(==FFFFFFFFFFFFFFFF),0xbf,0xbf,0x3f = FFFFFFFFFFFFFFFF (cc=0) -Index: none/tests/s390x/rxsbg.vgtest -=================================================================== ---- none/tests/s390x/rxsbg.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/s390x/rxsbg.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+prog: rxsbg -Index: none/tests/x86/Makefile.am -=================================================================== ---- none/tests/x86/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ none/tests/x86/Makefile.am (.../trunk) (revision 13981) -@@ -61,6 +61,7 @@ - ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \ - ssse3_misaligned.vgtest ssse3_misaligned.c \ - x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \ -+ x87trigOOR.vgtest x87trigOOR.stdout.exp x87trigOOR.stderr.exp \ - yield.stderr.exp yield.stdout.exp yield.disabled \ - xadd.stdout.exp xadd.stderr.exp xadd.vgtest - -@@ -94,6 +95,7 @@ - shift_ndep \ - smc1 \ - x86locked \ -+ x87trigOOR \ - yield \ - xadd - if BUILD_SSSE3_TESTS -Index: none/tests/x86/x87trigOOR.c -=================================================================== ---- none/tests/x86/x87trigOOR.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/x86/x87trigOOR.c (.../trunk) (revision 13981) -@@ -0,0 +1,159 @@ -+ -+/* Tests out of range handling for FSIN, FCOS, FSINCOS and FPTAN. Be -+ careful with the inline assembly -- this program is compiled as -+ both a 32-bit and 64-bit test. */ -+ -+#include -+#include -+#include -+ -+typedef unsigned short int UShort; -+typedef unsigned int UInt; -+typedef double Double; -+typedef unsigned long long int ULong; -+ -+typedef struct { Double arg; Double st0; Double st1; UShort fpusw; } Res; -+ -+#define SHIFT_C3 14 -+#define SHIFT_C2 10 -+#define SHIFT_C1 9 -+#define SHIFT_C0 8 -+ -+ -+#define my_offsetof(type,memb) ((int)(unsigned long int)&((type*)0)->memb) -+ -+void do_fsin ( /*OUT*/Res* r, double d ) -+{ -+ assert(my_offsetof(Res,arg) == 0); -+ assert(my_offsetof(Res,st0) == 8); -+ assert(my_offsetof(Res,st1) == 16); -+ assert(my_offsetof(Res,fpusw) == 24); -+ memset(r, 0, sizeof(*r)); -+ r->arg = d; -+ __asm__ __volatile__( -+ "finit" "\n\t" -+ "fldpi" "\n\t" -+ "fldl 0(%0)" "\n\t" // .arg -+ "fsin" "\n\t" -+ "fstsw %%ax" "\n\t" -+ "fstpl 8(%0)" "\n\t" // .st0 -+ "fstpl 16(%0)" "\n\t" // .st1 -+ "movw %%ax, 24(%0)" "\n\t" // .fpusw -+ "finit" "\n" -+ : : "r"(r) : "eax","cc","memory" -+ ); -+} -+ -+void do_fcos ( /*OUT*/Res* r, double d ) -+{ -+ assert(my_offsetof(Res,arg) == 0); -+ assert(my_offsetof(Res,st0) == 8); -+ assert(my_offsetof(Res,st1) == 16); -+ assert(my_offsetof(Res,fpusw) == 24); -+ memset(r, 0, sizeof(*r)); -+ r->arg = d; -+ __asm__ __volatile__( -+ "finit" "\n\t" -+ "fldpi" "\n\t" -+ "fldl 0(%0)" "\n\t" // .arg -+ "fcos" "\n\t" -+ "fstsw %%ax" "\n\t" -+ "fstpl 8(%0)" "\n\t" // .st0 -+ "fstpl 16(%0)" "\n\t" // .st1 -+ "movw %%ax, 24(%0)" "\n\t" // .fpusw -+ "finit" "\n" -+ : : "r"(r) : "eax","cc","memory" -+ ); -+} -+ -+void do_fsincos ( /*OUT*/Res* r, double d ) -+{ -+ assert(my_offsetof(Res,arg) == 0); -+ assert(my_offsetof(Res,st0) == 8); -+ assert(my_offsetof(Res,st1) == 16); -+ assert(my_offsetof(Res,fpusw) == 24); -+ memset(r, 0, sizeof(*r)); -+ r->arg = d; -+ __asm__ __volatile__( -+ "finit" "\n\t" -+ "fldpi" "\n\t" -+ "fldl 0(%0)" "\n\t" // .arg -+ "fsincos" "\n\t" -+ "fstsw %%ax" "\n\t" -+ "fstpl 8(%0)" "\n\t" // .st0 -+ "fstpl 16(%0)" "\n\t" // .st1 -+ "movw %%ax, 24(%0)" "\n\t" // .fpusw -+ "finit" "\n" -+ : : "r"(r) : "eax","cc","memory" -+ ); -+} -+ -+void do_fptan ( /*OUT*/Res* r, double d ) -+{ -+ assert(my_offsetof(Res,arg) == 0); -+ assert(my_offsetof(Res,st0) == 8); -+ assert(my_offsetof(Res,st1) == 16); -+ assert(my_offsetof(Res,fpusw) == 24); -+ memset(r, 0, sizeof(*r)); -+ r->arg = d; -+ __asm__ __volatile__( -+ "finit" "\n\t" -+ "fldpi" "\n\t" -+ "fldl 0(%0)" "\n\t" // .arg -+ "fptan" "\n\t" -+ "fstsw %%ax" "\n\t" -+ "fstpl 8(%0)" "\n\t" // .st0 -+ "fstpl 16(%0)" "\n\t" // .st1 -+ "movw %%ax, 24(%0)" "\n\t" // .fpusw -+ "finit" "\n" -+ : : "r"(r) : "eax","cc","memory" -+ ); -+} -+ -+ -+void try ( char* name, void(*fn)(Res*,double), double d ) -+{ -+ Res r; -+ fn(&r, d); -+ // Mask out all except C2 (range) -+ r.fpusw &= (1 << SHIFT_C2); -+ printf("%s %16e --> %16e %16e %04x\n", -+ name, r.arg, r.st0, r.st1, (UInt)r.fpusw); -+} -+ -+int main ( void ) -+{ -+ Double limit = 9223372036854775808.0; // 2^63 -+ -+ char* names[4] = { "fsin ", "fcos ", "fsincos", "fptan " }; -+ void(*fns[4])(Res*,double) = { do_fsin, do_fcos, do_fsincos, do_fptan }; -+ -+ int i; -+ for (i = 0; i < 4; i++) { -+ char* name = names[i]; -+ void (*fn)(Res*,double) = fns[i]; -+ -+ try( name, fn, 0.0 ); -+ try( name, fn, 0.123 ); -+ try( name, fn, -0.456 ); -+ try( name, fn, 37.0 ); -+ try( name, fn, -53.0 ); -+ printf("\n"); -+ -+ try( name, fn, limit * 0.900000 ); -+ try( name, fn, limit * 0.999999 ); -+ try( name, fn, limit * 1.000000 ); -+ try( name, fn, limit * 1.000001 ); -+ try( name, fn, limit * 1.100000 ); -+ printf("\n"); -+ -+ try( name, fn, -limit * 0.900000 ); -+ try( name, fn, -limit * 0.999999 ); -+ try( name, fn, -limit * 1.000000 ); -+ try( name, fn, -limit * 1.000001 ); -+ try( name, fn, -limit * 1.100000 ); -+ printf("\n"); -+ } -+ -+ return 0; -+} -Index: none/tests/x86/x87trigOOR.stderr.exp -=================================================================== ---- none/tests/x86/x87trigOOR.stderr.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/x86/x87trigOOR.stderr.exp (.../trunk) (revision 13981) -@@ -0,0 +1,2 @@ -+ -+ -Index: none/tests/x86/x87trigOOR.stdout.exp -=================================================================== ---- none/tests/x86/x87trigOOR.stdout.exp (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/x86/x87trigOOR.stdout.exp (.../trunk) (revision 13981) -@@ -0,0 +1,72 @@ -+fsin 0.000000e+00 --> 0.000000e+00 3.141593e+00 0000 -+fsin 1.230000e-01 --> 1.226901e-01 3.141593e+00 0000 -+fsin -4.560000e-01 --> -4.403604e-01 3.141593e+00 0000 -+fsin 3.700000e+01 --> -6.435381e-01 3.141593e+00 0000 -+fsin -5.300000e+01 --> -3.959252e-01 3.141593e+00 0000 -+ -+fsin 8.301035e+18 --> -1.249775e-01 3.141593e+00 0000 -+fsin 9.223363e+18 --> 2.344065e-01 3.141593e+00 0000 -+fsin 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fsin 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fsin 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fsin -8.301035e+18 --> 1.249775e-01 3.141593e+00 0000 -+fsin -9.223363e+18 --> -2.344065e-01 3.141593e+00 0000 -+fsin -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fsin -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fsin -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -+fcos 0.000000e+00 --> 1.000000e+00 3.141593e+00 0000 -+fcos 1.230000e-01 --> 9.924450e-01 3.141593e+00 0000 -+fcos -4.560000e-01 --> 8.978211e-01 3.141593e+00 0000 -+fcos 3.700000e+01 --> 7.654141e-01 3.141593e+00 0000 -+fcos -5.300000e+01 --> -9.182828e-01 3.141593e+00 0000 -+ -+fcos 8.301035e+18 --> -9.921596e-01 3.141593e+00 0000 -+fcos 9.223363e+18 --> 9.721387e-01 3.141593e+00 0000 -+fcos 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fcos 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fcos 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fcos -8.301035e+18 --> -9.921596e-01 3.141593e+00 0000 -+fcos -9.223363e+18 --> 9.721387e-01 3.141593e+00 0000 -+fcos -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fcos -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fcos -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -+fsincos 0.000000e+00 --> 1.000000e+00 0.000000e+00 0000 -+fsincos 1.230000e-01 --> 9.924450e-01 1.226901e-01 0000 -+fsincos -4.560000e-01 --> 8.978211e-01 -4.403604e-01 0000 -+fsincos 3.700000e+01 --> 7.654141e-01 -6.435381e-01 0000 -+fsincos -5.300000e+01 --> -9.182828e-01 -3.959252e-01 0000 -+ -+fsincos 8.301035e+18 --> -9.921596e-01 -1.249775e-01 0000 -+fsincos 9.223363e+18 --> 9.721387e-01 2.344065e-01 0000 -+fsincos 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fsincos 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fsincos 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fsincos -8.301035e+18 --> -9.921596e-01 1.249775e-01 0000 -+fsincos -9.223363e+18 --> 9.721387e-01 -2.344065e-01 0000 -+fsincos -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fsincos -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fsincos -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -+fptan 0.000000e+00 --> 1.000000e+00 0.000000e+00 0000 -+fptan 1.230000e-01 --> 1.000000e+00 1.236241e-01 0000 -+fptan -4.560000e-01 --> 1.000000e+00 -4.904767e-01 0000 -+fptan 3.700000e+01 --> 1.000000e+00 -8.407713e-01 0000 -+fptan -5.300000e+01 --> 1.000000e+00 4.311582e-01 0000 -+ -+fptan 8.301035e+18 --> 1.000000e+00 1.259651e-01 0000 -+fptan 9.223363e+18 --> 1.000000e+00 2.411246e-01 0000 -+fptan 9.223372e+18 --> 9.223372e+18 3.141593e+00 0400 -+fptan 9.223381e+18 --> 9.223381e+18 3.141593e+00 0400 -+fptan 1.014571e+19 --> 1.014571e+19 3.141593e+00 0400 -+ -+fptan -8.301035e+18 --> 1.000000e+00 -1.259651e-01 0000 -+fptan -9.223363e+18 --> 1.000000e+00 -2.411246e-01 0000 -+fptan -9.223372e+18 --> -9.223372e+18 3.141593e+00 0400 -+fptan -9.223381e+18 --> -9.223381e+18 3.141593e+00 0400 -+fptan -1.014571e+19 --> -1.014571e+19 3.141593e+00 0400 -+ -Index: none/tests/x86/x87trigOOR.vgtest -=================================================================== ---- none/tests/x86/x87trigOOR.vgtest (.../tags/VALGRIND_3_9_0) (revision 0) -+++ none/tests/x86/x87trigOOR.vgtest (.../trunk) (revision 13981) -@@ -0,0 +1 @@ -+prog: x87trigOOR -Index: shared/Makefile.am -=================================================================== ---- shared/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 0) -+++ shared/Makefile.am (.../trunk) (revision 13981) -@@ -0,0 +1,3 @@ -+# We need to list all source files here to make sure they are included in -+# the make dist target. -+EXTRA_DIST = vg_replace_strmem.c -Index: shared/vg_replace_strmem.c -=================================================================== ---- shared/vg_replace_strmem.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ shared/vg_replace_strmem.c (.../trunk) (revision 13981) -@@ -0,0 +1,1845 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Replacements for strcpy(), memcpy() et al, which run on the ---*/ -+/*--- simulated CPU. ---*/ -+/*--- mc_replace_strmem.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind. -+ -+ Copyright (C) 2000-2013 Julian Seward -+ jseward@acm.org -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#include "pub_tool_basics.h" -+#include "pub_tool_poolalloc.h" -+#include "pub_tool_hashtable.h" -+#include "pub_tool_redir.h" -+#include "pub_tool_tooliface.h" -+#include "pub_tool_clreq.h" -+ -+/* --------------------------------------------------------------------- -+ We have our own versions of these functions for two reasons: -+ (a) it allows us to do overlap checking -+ (b) some of the normal versions are hyper-optimised, which fools -+ Memcheck and cause spurious value warnings. Our versions are -+ simpler. -+ (c) the glibc SSE-variants can read past the end of the input data -+ ranges. This can cause false-positive Memcheck / Helgrind / DRD -+ reports. -+ -+ Note that overenthusiastic use of PLT bypassing by the glibc people also -+ means that we need to patch multiple versions of some of the functions to -+ our own implementations. -+ -+ THEY RUN ON THE SIMD CPU! -+ ------------------------------------------------------------------ */ -+ -+/* Assignment of behavioural equivalence class tags: 2NNNP is intended -+ to be reserved for str/mem intercepts. Current usage: -+ -+ 20010 STRRCHR -+ 20020 STRCHR -+ 20030 STRCAT -+ 20040 STRNCAT -+ 20050 STRLCAT -+ 20060 STRNLEN -+ 20070 STRLEN -+ 20080 STRCPY -+ 20090 STRNCPY -+ 20100 STRLCPY -+ 20110 STRNCMP -+ 20120 STRCASECMP -+ 20130 STRNCASECMP -+ 20140 STRCASECMP_L -+ 20150 STRNCASECMP_L -+ 20160 STRCMP -+ 20170 MEMCHR -+ -+ 20180 MEMCPY if there's a conflict between memcpy and -+ 20181 MEMMOVE memmove, prefer memmove -+ -+ 20190 MEMCMP -+ 20200 STPCPY -+ 20210 MEMSET -+ 2022P unused (was previously MEMMOVE) -+ 20230 BCOPY -+ 20240 GLIBC25___MEMMOVE_CHK -+ 20250 GLIBC232_STRCHRNUL -+ 20260 GLIBC232_RAWMEMCHR -+ 20270 GLIBC25___STRCPY_CHK -+ 20280 GLIBC25___STPCPY_CHK -+ 20290 GLIBC25_MEMPCPY -+ 20300 GLIBC26___MEMCPY_CHK -+ 20310 STRSTR -+ 20320 STRPBRK -+ 20330 STRCSPN -+ 20340 STRSPN -+ 20350 STRCASESTR -+ 20360 MEMRCHR -+ 20370 WCSLEN -+ 20380 WCSCMP -+ 20390 WCSCPY -+ 20400 WCSCHR -+ 20410 WCSRCHR -+ 20420 STPNCPY -+*/ -+ -+ -+/* Figure out if [dst .. dst+dstlen-1] overlaps with -+ [src .. src+srclen-1]. -+ We assume that the address ranges do not wrap around -+ (which is safe since on Linux addresses >= 0xC0000000 -+ are not accessible and the program will segfault in this -+ circumstance, presumably). -+*/ -+static inline -+Bool is_overlap ( void* dst, const void* src, SizeT dstlen, SizeT srclen ) -+{ -+ Addr loS, hiS, loD, hiD; -+ -+ if (dstlen == 0 || srclen == 0) -+ return False; -+ -+ loS = (Addr)src; -+ loD = (Addr)dst; -+ hiS = loS + srclen - 1; -+ hiD = loD + dstlen - 1; -+ -+ /* So figure out if [loS .. hiS] overlaps with [loD .. hiD]. */ -+ if (loS < loD) { -+ return !(hiS < loD); -+ } -+ else if (loD < loS) { -+ return !(hiD < loS); -+ } -+ else { -+ /* They start at same place. Since we know neither of them has -+ zero length, they must overlap. */ -+ return True; -+ } -+} -+ -+ -+/* Call here to exit if we can't continue. On Android we can't call -+ _exit for some reason, so we have to blunt-instrument it. */ -+__attribute__ ((__noreturn__)) -+static inline void my_exit ( int x ) -+{ -+# if defined(VGPV_arm_linux_android) || defined(VGPV_mips32_linux_android) \ -+ || defined(VGPV_mips32_linux_android) -+ __asm__ __volatile__(".word 0xFFFFFFFF"); -+ while (1) {} -+# elif defined(VGPV_x86_linux_android) -+ __asm__ __volatile__("ud2"); -+ while (1) {} -+# else -+ extern __attribute__ ((__noreturn__)) void _exit(int status); -+ _exit(x); -+# endif -+} -+ -+ -+// This is a macro rather than a function because we don't want to have an -+// extra function in the stack trace. -+#ifndef RECORD_OVERLAP_ERROR -+#define RECORD_OVERLAP_ERROR(s, src, dst, len) do { } while (0) -+#endif -+#ifndef VALGRIND_CHECK_VALUE_IS_DEFINED -+#define VALGRIND_CHECK_VALUE_IS_DEFINED(__lvalue) 1 -+#endif -+ -+ -+/*---------------------- strrchr ----------------------*/ -+ -+#define STRRCHR(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20010,soname,fnname)( const char* s, int c ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20010,soname,fnname)( const char* s, int c ) \ -+ { \ -+ HChar ch = (HChar)c; \ -+ const HChar* p = s; \ -+ const HChar* last = NULL; \ -+ while (True) { \ -+ if (*p == ch) last = p; \ -+ if (*p == 0) return (HChar *)last; \ -+ p++; \ -+ } \ -+ } -+ -+// Apparently rindex() is the same thing as strrchr() -+#if defined(VGO_linux) -+ STRRCHR(VG_Z_LIBC_SONAME, strrchr) -+ STRRCHR(VG_Z_LIBC_SONAME, rindex) -+ STRRCHR(VG_Z_LIBC_SONAME, __GI_strrchr) -+ STRRCHR(VG_Z_LIBC_SONAME, __strrchr_sse2) -+ STRRCHR(VG_Z_LIBC_SONAME, __strrchr_sse2_no_bsf) -+ STRRCHR(VG_Z_LIBC_SONAME, __strrchr_sse42) -+ STRRCHR(VG_Z_LD_LINUX_SO_2, rindex) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) -+ STRRCHR(NONE, __dl_strrchr); /* in /system/bin/linker */ -+#endif -+ -+#elif defined(VGO_darwin) -+ //STRRCHR(VG_Z_LIBC_SONAME, strrchr) -+ //STRRCHR(VG_Z_LIBC_SONAME, rindex) -+ //STRRCHR(VG_Z_DYLD, strrchr) -+ //STRRCHR(VG_Z_DYLD, rindex) -+ STRRCHR(VG_Z_LIBC_SONAME, strrchr) -+ -+#endif -+ -+ -+/*---------------------- strchr ----------------------*/ -+ -+#define STRCHR(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20020,soname,fnname) ( const char* s, int c ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20020,soname,fnname) ( const char* s, int c ) \ -+ { \ -+ HChar ch = (HChar)c ; \ -+ const HChar* p = s; \ -+ while (True) { \ -+ if (*p == ch) return (HChar *)p; \ -+ if (*p == 0) return NULL; \ -+ p++; \ -+ } \ -+ } -+ -+// Apparently index() is the same thing as strchr() -+#if defined(VGO_linux) -+ STRCHR(VG_Z_LIBC_SONAME, strchr) -+ STRCHR(VG_Z_LIBC_SONAME, __GI_strchr) -+ STRCHR(VG_Z_LIBC_SONAME, __strchr_sse2) -+ STRCHR(VG_Z_LIBC_SONAME, __strchr_sse2_no_bsf) -+ STRCHR(VG_Z_LIBC_SONAME, index) -+# if !defined(VGP_x86_linux) -+ STRCHR(VG_Z_LD_LINUX_SO_2, strchr) -+ STRCHR(VG_Z_LD_LINUX_SO_2, index) -+ STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, strchr) -+ STRCHR(VG_Z_LD_LINUX_X86_64_SO_2, index) -+# endif -+ -+#elif defined(VGO_darwin) -+ //STRCHR(VG_Z_LIBC_SONAME, strchr) -+ //STRCHR(VG_Z_LIBC_SONAME, index) -+ //STRCHR(VG_Z_DYLD, strchr) -+ //STRCHR(VG_Z_DYLD, index) -+ STRCHR(VG_Z_LIBC_SONAME, strchr) -+ -+#endif -+ -+ -+/*---------------------- strcat ----------------------*/ -+ -+#define STRCAT(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20030,soname,fnname) \ -+ ( char* dst, const char* src ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20030,soname,fnname) \ -+ ( char* dst, const char* src ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_orig = dst; \ -+ while (*dst) dst++; \ -+ while (*src) *dst++ = *src++; \ -+ *dst = 0; \ -+ \ -+ /* This is a bit redundant, I think; any overlap and the strcat will */ \ -+ /* go forever... or until a seg fault occurs. */ \ -+ if (is_overlap(dst_orig, \ -+ src_orig, \ -+ (Addr)dst-(Addr)dst_orig+1, \ -+ (Addr)src-(Addr)src_orig+1)) \ -+ RECORD_OVERLAP_ERROR("strcat", dst_orig, src_orig, 0); \ -+ \ -+ return dst_orig; \ -+ } -+ -+#if defined(VGO_linux) -+ STRCAT(VG_Z_LIBC_SONAME, strcat) -+ STRCAT(VG_Z_LIBC_SONAME, __GI_strcat) -+ -+#elif defined(VGO_darwin) -+ //STRCAT(VG_Z_LIBC_SONAME, strcat) -+ -+#endif -+ -+ -+/*---------------------- strncat ----------------------*/ -+ -+#define STRNCAT(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20040,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20040,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_orig = dst; \ -+ SizeT m = 0; \ -+ \ -+ while (*dst) dst++; \ -+ while (m < n && *src) { m++; *dst++ = *src++; } /* concat <= n chars */ \ -+ *dst = 0; /* always add null */ \ -+ \ -+ /* This checks for overlap after copying, unavoidable without */ \ -+ /* pre-counting lengths... should be ok */ \ -+ if (is_overlap(dst_orig, \ -+ src_orig, \ -+ (Addr)dst-(Addr)dst_orig+1, \ -+ (Addr)src-(Addr)src_orig+1)) \ -+ RECORD_OVERLAP_ERROR("strncat", dst_orig, src_orig, n); \ -+ \ -+ return dst_orig; \ -+ } -+ -+#if defined(VGO_linux) -+ STRNCAT(VG_Z_LIBC_SONAME, strncat) -+ -+#elif defined(VGO_darwin) -+ //STRNCAT(VG_Z_LIBC_SONAME, strncat) -+ //STRNCAT(VG_Z_DYLD, strncat) -+ -+#endif -+ -+ -+/*---------------------- strlcat ----------------------*/ -+ -+/* Append src to dst. n is the size of dst's buffer. dst is guaranteed -+ to be nul-terminated after the copy, unless n <= strlen(dst_orig). -+ Returns min(n, strlen(dst_orig)) + strlen(src_orig). -+ Truncation occurred if retval >= n. -+*/ -+#define STRLCAT(soname, fnname) \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20050,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ); \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20050,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_orig = dst; \ -+ SizeT m = 0; \ -+ \ -+ while (m < n && *dst) { m++; dst++; } \ -+ if (m < n) { \ -+ /* Fill as far as dst_orig[n-2], then nul-terminate. */ \ -+ while (m < n-1 && *src) { m++; *dst++ = *src++; } \ -+ *dst = 0; \ -+ } else { \ -+ /* No space to copy anything to dst. m == n */ \ -+ } \ -+ /* Finish counting min(n, strlen(dst_orig)) + strlen(src_orig) */ \ -+ while (*src) { m++; src++; } \ -+ /* This checks for overlap after copying, unavoidable without */ \ -+ /* pre-counting lengths... should be ok */ \ -+ if (is_overlap(dst_orig, \ -+ src_orig, \ -+ (Addr)dst-(Addr)dst_orig+1, \ -+ (Addr)src-(Addr)src_orig+1)) \ -+ RECORD_OVERLAP_ERROR("strlcat", dst_orig, src_orig, n); \ -+ \ -+ return m; \ -+ } -+ -+#if defined(VGO_linux) -+ -+#elif defined(VGO_darwin) -+ //STRLCAT(VG_Z_LIBC_SONAME, strlcat) -+ //STRLCAT(VG_Z_DYLD, strlcat) -+ STRLCAT(VG_Z_LIBC_SONAME, strlcat) -+ -+#endif -+ -+ -+/*---------------------- strnlen ----------------------*/ -+ -+#define STRNLEN(soname, fnname) \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20060,soname,fnname) \ -+ ( const char* str, SizeT n ); \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20060,soname,fnname) \ -+ ( const char* str, SizeT n ) \ -+ { \ -+ SizeT i = 0; \ -+ while (i < n && str[i] != 0) i++; \ -+ return i; \ -+ } -+ -+#if defined(VGO_linux) -+ STRNLEN(VG_Z_LIBC_SONAME, strnlen) -+ STRNLEN(VG_Z_LIBC_SONAME, __GI_strnlen) -+ -+#elif defined(VGO_darwin) -+ //STRNLEN(VG_Z_LIBC_SONAME, strnlen) -+ -+#endif -+ -+ -+/*---------------------- strlen ----------------------*/ -+ -+// Note that this replacement often doesn't get used because gcc inlines -+// calls to strlen() with its own built-in version. This can be very -+// confusing if you aren't expecting it. Other small functions in -+// this file may also be inline by gcc. -+ -+#define STRLEN(soname, fnname) \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20070,soname,fnname) \ -+ ( const char* str ); \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20070,soname,fnname) \ -+ ( const char* str ) \ -+ { \ -+ SizeT i = 0; \ -+ while (str[i] != 0) i++; \ -+ return i; \ -+ } -+ -+#if defined(VGO_linux) -+ STRLEN(VG_Z_LIBC_SONAME, strlen) -+ STRLEN(VG_Z_LIBC_SONAME, __GI_strlen) -+ STRLEN(VG_Z_LIBC_SONAME, __strlen_sse2) -+ STRLEN(VG_Z_LIBC_SONAME, __strlen_sse2_no_bsf) -+ STRLEN(VG_Z_LIBC_SONAME, __strlen_sse42) -+ STRLEN(VG_Z_LD_LINUX_SO_2, strlen) -+ STRLEN(VG_Z_LD_LINUX_X86_64_SO_2, strlen) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) -+ STRLEN(NONE, __dl_strlen); /* in /system/bin/linker */ -+# endif -+ -+#elif defined(VGO_darwin) -+ //STRLEN(VG_Z_LIBC_SONAME, strlen) -+ STRLEN(VG_Z_LIBC_SONAME, strlen) -+ -+#endif -+ -+ -+/*---------------------- strcpy ----------------------*/ -+ -+#define STRCPY(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20080,soname,fnname) \ -+ ( char* dst, const char* src ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20080,soname,fnname) \ -+ ( char* dst, const char* src ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_orig = dst; \ -+ \ -+ while (*src) *dst++ = *src++; \ -+ *dst = 0; \ -+ \ -+ /* This checks for overlap after copying, unavoidable without */ \ -+ /* pre-counting length... should be ok */ \ -+ if (is_overlap(dst_orig, \ -+ src_orig, \ -+ (Addr)dst-(Addr)dst_orig+1, \ -+ (Addr)src-(Addr)src_orig+1)) \ -+ RECORD_OVERLAP_ERROR("strcpy", dst_orig, src_orig, 0); \ -+ \ -+ return dst_orig; \ -+ } -+ -+#if defined(VGO_linux) -+ STRCPY(VG_Z_LIBC_SONAME, strcpy) -+ STRCPY(VG_Z_LIBC_SONAME, __GI_strcpy) -+ -+#elif defined(VGO_darwin) -+ //STRCPY(VG_Z_LIBC_SONAME, strcpy) -+ //STRCPY(VG_Z_DYLD, strcpy) -+ STRCPY(VG_Z_LIBC_SONAME, strcpy) -+ -+#endif -+ -+ -+/*---------------------- strncpy ----------------------*/ -+ -+#define STRNCPY(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20090,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20090,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_orig = dst; \ -+ SizeT m = 0; \ -+ \ -+ while (m < n && *src) { m++; *dst++ = *src++; } \ -+ /* Check for overlap after copying; all n bytes of dst are relevant, */ \ -+ /* but only m+1 bytes of src if terminator was found */ \ -+ if (is_overlap(dst_orig, src_orig, n, (m < n) ? m+1 : n)) \ -+ RECORD_OVERLAP_ERROR("strncpy", dst, src, n); \ -+ while (m++ < n) *dst++ = 0; /* must pad remainder with nulls */ \ -+ \ -+ return dst_orig; \ -+ } -+ -+#if defined(VGO_linux) -+ STRNCPY(VG_Z_LIBC_SONAME, strncpy) -+ STRNCPY(VG_Z_LIBC_SONAME, __GI_strncpy) -+ STRNCPY(VG_Z_LIBC_SONAME, __strncpy_sse2) -+ STRNCPY(VG_Z_LIBC_SONAME, __strncpy_sse2_unaligned) -+ -+#elif defined(VGO_darwin) -+ //STRNCPY(VG_Z_LIBC_SONAME, strncpy) -+ //STRNCPY(VG_Z_DYLD, strncpy) -+ STRNCPY(VG_Z_LIBC_SONAME, strncpy) -+ -+#endif -+ -+ -+/*---------------------- strlcpy ----------------------*/ -+ -+/* Copy up to n-1 bytes from src to dst. Then nul-terminate dst if n > 0. -+ Returns strlen(src). Does not zero-fill the remainder of dst. */ -+#define STRLCPY(soname, fnname) \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20100,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ); \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20100,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_orig = dst; \ -+ SizeT m = 0; \ -+ \ -+ while (m < n-1 && *src) { m++; *dst++ = *src++; } \ -+ /* m non-nul bytes have now been copied, and m <= n-1. */ \ -+ /* Check for overlap after copying; all n bytes of dst are relevant, */ \ -+ /* but only m+1 bytes of src if terminator was found */ \ -+ if (is_overlap(dst_orig, src_orig, n, (m < n) ? m+1 : n)) \ -+ RECORD_OVERLAP_ERROR("strlcpy", dst, src, n); \ -+ /* Nul-terminate dst. */ \ -+ if (n > 0) *dst = 0; \ -+ /* Finish counting strlen(src). */ \ -+ while (*src) src++; \ -+ return src - src_orig; \ -+ } -+ -+#if defined(VGO_linux) -+ -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) -+ STRLCPY(VG_Z_LIBC_SONAME, strlcpy); -+#endif -+ -+#elif defined(VGO_darwin) -+ //STRLCPY(VG_Z_LIBC_SONAME, strlcpy) -+ //STRLCPY(VG_Z_DYLD, strlcpy) -+ STRLCPY(VG_Z_LIBC_SONAME, strlcpy) -+ -+#endif -+ -+ -+/*---------------------- strncmp ----------------------*/ -+ -+#define STRNCMP(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20110,soname,fnname) \ -+ ( const char* s1, const char* s2, SizeT nmax ); \ -+ int VG_REPLACE_FUNCTION_EZU(20110,soname,fnname) \ -+ ( const char* s1, const char* s2, SizeT nmax ) \ -+ { \ -+ SizeT n = 0; \ -+ while (True) { \ -+ if (n >= nmax) return 0; \ -+ if (*s1 == 0 && *s2 == 0) return 0; \ -+ if (*s1 == 0) return -1; \ -+ if (*s2 == 0) return 1; \ -+ \ -+ if (*(const UChar*)s1 < *(const UChar*)s2) return -1; \ -+ if (*(const UChar*)s1 > *(const UChar*)s2) return 1; \ -+ \ -+ s1++; s2++; n++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ STRNCMP(VG_Z_LIBC_SONAME, strncmp) -+ STRNCMP(VG_Z_LIBC_SONAME, __GI_strncmp) -+ STRNCMP(VG_Z_LIBC_SONAME, __strncmp_sse2) -+ STRNCMP(VG_Z_LIBC_SONAME, __strncmp_sse42) -+ -+#elif defined(VGO_darwin) -+ //STRNCMP(VG_Z_LIBC_SONAME, strncmp) -+ //STRNCMP(VG_Z_DYLD, strncmp) -+ STRNCMP(VG_Z_LIBC_SONAME, strncmp) -+ -+#endif -+ -+ -+/*---------------------- strcasecmp ----------------------*/ -+ -+#define STRCASECMP(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20120,soname,fnname) \ -+ ( const char* s1, const char* s2 ); \ -+ int VG_REPLACE_FUNCTION_EZU(20120,soname,fnname) \ -+ ( const char* s1, const char* s2 ) \ -+ { \ -+ extern int tolower(int); \ -+ register UChar c1; \ -+ register UChar c2; \ -+ while (True) { \ -+ c1 = tolower(*(const UChar *)s1); \ -+ c2 = tolower(*(const UChar *)s2); \ -+ if (c1 != c2) break; \ -+ if (c1 == 0) break; \ -+ s1++; s2++; \ -+ } \ -+ if ((UChar)c1 < (UChar)c2) return -1; \ -+ if ((UChar)c1 > (UChar)c2) return 1; \ -+ return 0; \ -+ } -+ -+#if defined(VGO_linux) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) -+ STRCASECMP(VG_Z_LIBC_SONAME, strcasecmp) -+ STRCASECMP(VG_Z_LIBC_SONAME, __GI_strcasecmp) -+# endif -+ -+#elif defined(VGO_darwin) -+ //STRCASECMP(VG_Z_LIBC_SONAME, strcasecmp) -+ -+#endif -+ -+ -+/*---------------------- strncasecmp ----------------------*/ -+ -+#define STRNCASECMP(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20130,soname,fnname) \ -+ ( const char* s1, const char* s2, SizeT nmax ); \ -+ int VG_REPLACE_FUNCTION_EZU(20130,soname,fnname) \ -+ ( const char* s1, const char* s2, SizeT nmax ) \ -+ { \ -+ extern int tolower(int); \ -+ SizeT n = 0; \ -+ while (True) { \ -+ if (n >= nmax) return 0; \ -+ if (*s1 == 0 && *s2 == 0) return 0; \ -+ if (*s1 == 0) return -1; \ -+ if (*s2 == 0) return 1; \ -+ \ -+ if (tolower(*(const UChar *)s1) \ -+ < tolower(*(const UChar*)s2)) return -1; \ -+ if (tolower(*(const UChar *)s1) \ -+ > tolower(*(const UChar *)s2)) return 1; \ -+ \ -+ s1++; s2++; n++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) -+ STRNCASECMP(VG_Z_LIBC_SONAME, strncasecmp) -+ STRNCASECMP(VG_Z_LIBC_SONAME, __GI_strncasecmp) -+# endif -+ -+#elif defined(VGO_darwin) -+ //STRNCASECMP(VG_Z_LIBC_SONAME, strncasecmp) -+ //STRNCASECMP(VG_Z_DYLD, strncasecmp) -+ -+#endif -+ -+ -+/*---------------------- strcasecmp_l ----------------------*/ -+ -+#define STRCASECMP_L(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20140,soname,fnname) \ -+ ( const char* s1, const char* s2, void* locale ); \ -+ int VG_REPLACE_FUNCTION_EZU(20140,soname,fnname) \ -+ ( const char* s1, const char* s2, void* locale ) \ -+ { \ -+ extern int tolower_l(int, void*) __attribute__((weak)); \ -+ register UChar c1; \ -+ register UChar c2; \ -+ while (True) { \ -+ c1 = tolower_l(*(const UChar *)s1, locale); \ -+ c2 = tolower_l(*(const UChar *)s2, locale); \ -+ if (c1 != c2) break; \ -+ if (c1 == 0) break; \ -+ s1++; s2++; \ -+ } \ -+ if ((UChar)c1 < (UChar)c2) return -1; \ -+ if ((UChar)c1 > (UChar)c2) return 1; \ -+ return 0; \ -+ } -+ -+#if defined(VGO_linux) -+ STRCASECMP_L(VG_Z_LIBC_SONAME, strcasecmp_l) -+ STRCASECMP_L(VG_Z_LIBC_SONAME, __GI_strcasecmp_l) -+ STRCASECMP_L(VG_Z_LIBC_SONAME, __GI___strcasecmp_l) -+ -+#elif defined(VGO_darwin) -+ //STRCASECMP_L(VG_Z_LIBC_SONAME, strcasecmp_l) -+ -+#endif -+ -+ -+/*---------------------- strncasecmp_l ----------------------*/ -+ -+#define STRNCASECMP_L(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20150,soname,fnname) \ -+ ( const char* s1, const char* s2, SizeT nmax, void* locale ); \ -+ int VG_REPLACE_FUNCTION_EZU(20150,soname,fnname) \ -+ ( const char* s1, const char* s2, SizeT nmax, void* locale ) \ -+ { \ -+ extern int tolower_l(int, void*) __attribute__((weak)); \ -+ SizeT n = 0; \ -+ while (True) { \ -+ if (n >= nmax) return 0; \ -+ if (*s1 == 0 && *s2 == 0) return 0; \ -+ if (*s1 == 0) return -1; \ -+ if (*s2 == 0) return 1; \ -+ \ -+ if (tolower_l(*(const UChar *)s1, locale) \ -+ < tolower_l(*(const UChar *)s2, locale)) return -1; \ -+ if (tolower_l(*(const UChar *)s1, locale) \ -+ > tolower_l(*(const UChar *)s2, locale)) return 1; \ -+ \ -+ s1++; s2++; n++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ STRNCASECMP_L(VG_Z_LIBC_SONAME, strncasecmp_l) -+ STRNCASECMP_L(VG_Z_LIBC_SONAME, __GI_strncasecmp_l) -+ STRNCASECMP_L(VG_Z_LIBC_SONAME, __GI___strncasecmp_l) -+ -+#elif defined(VGO_darwin) -+ //STRNCASECMP_L(VG_Z_LIBC_SONAME, strncasecmp_l) -+ //STRNCASECMP_L(VG_Z_DYLD, strncasecmp_l) -+ -+#endif -+ -+ -+/*---------------------- strcmp ----------------------*/ -+ -+#define STRCMP(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20160,soname,fnname) \ -+ ( const char* s1, const char* s2 ); \ -+ int VG_REPLACE_FUNCTION_EZU(20160,soname,fnname) \ -+ ( const char* s1, const char* s2 ) \ -+ { \ -+ register UChar c1; \ -+ register UChar c2; \ -+ while (True) { \ -+ c1 = *(const UChar *)s1; \ -+ c2 = *(const UChar *)s2; \ -+ if (c1 != c2) break; \ -+ if (c1 == 0) break; \ -+ s1++; s2++; \ -+ } \ -+ if ((UChar)c1 < (UChar)c2) return -1; \ -+ if ((UChar)c1 > (UChar)c2) return 1; \ -+ return 0; \ -+ } -+ -+#if defined(VGO_linux) -+ STRCMP(VG_Z_LIBC_SONAME, strcmp) -+ STRCMP(VG_Z_LIBC_SONAME, __GI_strcmp) -+ STRCMP(VG_Z_LIBC_SONAME, __strcmp_sse2) -+ STRCMP(VG_Z_LIBC_SONAME, __strcmp_sse42) -+ STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp) -+ STRCMP(VG_Z_LD64_SO_1, strcmp) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) -+ STRCMP(NONE, __dl_strcmp); /* in /system/bin/linker */ -+# endif -+ -+#elif defined(VGO_darwin) -+ //STRCMP(VG_Z_LIBC_SONAME, strcmp) -+ STRCMP(VG_Z_LIBC_SONAME, strcmp) -+ -+#endif -+ -+ -+/*---------------------- memchr ----------------------*/ -+ -+#define MEMCHR(soname, fnname) \ -+ void* VG_REPLACE_FUNCTION_EZU(20170,soname,fnname) \ -+ (const void *s, int c, SizeT n); \ -+ void* VG_REPLACE_FUNCTION_EZU(20170,soname,fnname) \ -+ (const void *s, int c, SizeT n) \ -+ { \ -+ SizeT i; \ -+ UChar c0 = (UChar)c; \ -+ UChar* p = (UChar*)s; \ -+ for (i = 0; i < n; i++) \ -+ if (p[i] == c0) return (void*)(&p[i]); \ -+ return NULL; \ -+ } -+ -+#if defined(VGO_linux) -+ MEMCHR(VG_Z_LIBC_SONAME, memchr) -+ MEMCHR(VG_Z_LIBC_SONAME, __GI_memchr) -+ -+#elif defined(VGO_darwin) -+ //MEMCHR(VG_Z_LIBC_SONAME, memchr) -+ //MEMCHR(VG_Z_DYLD, memchr) -+ -+#endif -+ -+ -+/*---------------------- memrchr ----------------------*/ -+ -+#define MEMRCHR(soname, fnname) \ -+ void* VG_REPLACE_FUNCTION_EZU(20360,soname,fnname) \ -+ (const void *s, int c, SizeT n); \ -+ void* VG_REPLACE_FUNCTION_EZU(20360,soname,fnname) \ -+ (const void *s, int c, SizeT n) \ -+ { \ -+ SizeT i; \ -+ UChar c0 = (UChar)c; \ -+ UChar* p = (UChar*)s; \ -+ for (i = 0; i < n; i++) \ -+ if (p[n-1-i] == c0) return (void*)(&p[n-1-i]); \ -+ return NULL; \ -+ } -+ -+#if defined(VGO_linux) -+ MEMRCHR(VG_Z_LIBC_SONAME, memrchr) -+ -+#elif defined(VGO_darwin) -+ //MEMRCHR(VG_Z_LIBC_SONAME, memrchr) -+ //MEMRCHR(VG_Z_DYLD, memrchr) -+ -+#endif -+ -+ -+/*---------------------- memcpy ----------------------*/ -+ -+#define MEMMOVE_OR_MEMCPY(becTag, soname, fnname, do_ol_check) \ -+ void* VG_REPLACE_FUNCTION_EZZ(becTag,soname,fnname) \ -+ ( void *dst, const void *src, SizeT len ); \ -+ void* VG_REPLACE_FUNCTION_EZZ(becTag,soname,fnname) \ -+ ( void *dst, const void *src, SizeT len ) \ -+ { \ -+ if (do_ol_check && is_overlap(dst, src, len, len)) \ -+ RECORD_OVERLAP_ERROR("memcpy", dst, src, len); \ -+ \ -+ const Addr WS = sizeof(UWord); /* 8 or 4 */ \ -+ const Addr WM = WS - 1; /* 7 or 3 */ \ -+ \ -+ if (len > 0) { \ -+ if (dst < src || !is_overlap(dst, src, len, len)) { \ -+ \ -+ /* Copying backwards. */ \ -+ SizeT n = len; \ -+ Addr d = (Addr)dst; \ -+ Addr s = (Addr)src; \ -+ \ -+ if (((s^d) & WM) == 0) { \ -+ /* s and d have same UWord alignment. */ \ -+ /* Pull up to a UWord boundary. */ \ -+ while ((s & WM) != 0 && n >= 1) \ -+ { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ -+ /* Copy UWords. */ \ -+ while (n >= WS) \ -+ { *(UWord*)d = *(UWord*)s; s += WS; d += WS; n -= WS; } \ -+ if (n == 0) \ -+ return dst; \ -+ } \ -+ if (((s|d) & 1) == 0) { \ -+ /* Both are 16-aligned; copy what we can thusly. */ \ -+ while (n >= 2) \ -+ { *(UShort*)d = *(UShort*)s; s += 2; d += 2; n -= 2; } \ -+ } \ -+ /* Copy leftovers, or everything if misaligned. */ \ -+ while (n >= 1) \ -+ { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \ -+ \ -+ } else if (dst > src) { \ -+ \ -+ SizeT n = len; \ -+ Addr d = ((Addr)dst) + n; \ -+ Addr s = ((Addr)src) + n; \ -+ \ -+ /* Copying forwards. */ \ -+ if (((s^d) & WM) == 0) { \ -+ /* s and d have same UWord alignment. */ \ -+ /* Back down to a UWord boundary. */ \ -+ while ((s & WM) != 0 && n >= 1) \ -+ { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ -+ /* Copy UWords. */ \ -+ while (n >= WS) \ -+ { s -= WS; d -= WS; *(UWord*)d = *(UWord*)s; n -= WS; } \ -+ if (n == 0) \ -+ return dst; \ -+ } \ -+ if (((s|d) & 1) == 0) { \ -+ /* Both are 16-aligned; copy what we can thusly. */ \ -+ while (n >= 2) \ -+ { s -= 2; d -= 2; *(UShort*)d = *(UShort*)s; n -= 2; } \ -+ } \ -+ /* Copy leftovers, or everything if misaligned. */ \ -+ while (n >= 1) \ -+ { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \ -+ \ -+ } \ -+ } \ -+ \ -+ return dst; \ -+ } -+ -+#define MEMMOVE(soname, fnname) \ -+ MEMMOVE_OR_MEMCPY(20181, soname, fnname, 0) -+ -+#define MEMCPY(soname, fnname) \ -+ MEMMOVE_OR_MEMCPY(20180, soname, fnname, 1) -+ -+#if defined(VGO_linux) -+ /* For older memcpy we have to use memmove-like semantics and skip -+ the overlap check; sigh; see #275284. */ -+ MEMMOVE(VG_Z_LIBC_SONAME, memcpyZAGLIBCZu2Zd2Zd5) /* memcpy@GLIBC_2.2.5 */ -+ MEMCPY(VG_Z_LIBC_SONAME, memcpyZAZAGLIBCZu2Zd14) /* memcpy@@GLIBC_2.14 */ -+ MEMCPY(VG_Z_LIBC_SONAME, memcpy) /* fallback case */ -+ MEMCPY(VG_Z_LIBC_SONAME, __GI_memcpy) -+ MEMCPY(VG_Z_LIBC_SONAME, __memcpy_sse2) -+ MEMCPY(VG_Z_LD_SO_1, memcpy) /* ld.so.1 */ -+ MEMCPY(VG_Z_LD64_SO_1, memcpy) /* ld64.so.1 */ -+ /* icc9 blats these around all over the place. Not only in the main -+ executable but various .so's. They are highly tuned and read -+ memory beyond the source boundary (although work correctly and -+ never go across page boundaries), so give errors when run -+ natively, at least for misaligned source arg. Just intercepting -+ in the exe only until we understand more about the problem. See -+ http://bugs.kde.org/show_bug.cgi?id=139776 -+ */ -+ MEMCPY(NONE, ZuintelZufastZumemcpy) -+ -+#elif defined(VGO_darwin) -+# if DARWIN_VERS <= DARWIN_10_6 -+ MEMCPY(VG_Z_LIBC_SONAME, memcpy) -+# endif -+ MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse3x) /* memcpy$VARIANT$sse3x */ -+ MEMCPY(VG_Z_LIBC_SONAME, memcpyZDVARIANTZDsse42) /* memcpy$VARIANT$sse42 */ -+ -+#endif -+ -+ -+/*---------------------- memcmp ----------------------*/ -+ -+#define MEMCMP(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20190,soname,fnname) \ -+ ( const void *s1V, const void *s2V, SizeT n ); \ -+ int VG_REPLACE_FUNCTION_EZU(20190,soname,fnname) \ -+ ( const void *s1V, const void *s2V, SizeT n ) \ -+ { \ -+ int res; \ -+ UChar a0; \ -+ UChar b0; \ -+ const UChar* s1 = s1V; \ -+ const UChar* s2 = s2V; \ -+ \ -+ while (n != 0) { \ -+ a0 = s1[0]; \ -+ b0 = s2[0]; \ -+ s1 += 1; \ -+ s2 += 1; \ -+ res = ((int)a0) - ((int)b0); \ -+ if (res != 0) \ -+ return res; \ -+ n -= 1; \ -+ } \ -+ return 0; \ -+ } -+ -+#if defined(VGO_linux) -+ MEMCMP(VG_Z_LIBC_SONAME, memcmp) -+ MEMCMP(VG_Z_LIBC_SONAME, __GI_memcmp) -+ MEMCMP(VG_Z_LIBC_SONAME, __memcmp_sse2) -+ MEMCMP(VG_Z_LIBC_SONAME, __memcmp_sse4_1) -+ MEMCMP(VG_Z_LIBC_SONAME, bcmp) -+ MEMCMP(VG_Z_LD_SO_1, bcmp) -+ -+#elif defined(VGO_darwin) -+ //MEMCMP(VG_Z_LIBC_SONAME, memcmp) -+ //MEMCMP(VG_Z_LIBC_SONAME, bcmp) -+ //MEMCMP(VG_Z_DYLD, memcmp) -+ //MEMCMP(VG_Z_DYLD, bcmp) -+ -+#endif -+ -+ -+/*---------------------- stpcpy ----------------------*/ -+ -+/* Copy SRC to DEST, returning the address of the terminating '\0' in -+ DEST. (minor variant of strcpy) */ -+#define STPCPY(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20200,soname,fnname) \ -+ ( char* dst, const char* src ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20200,soname,fnname) \ -+ ( char* dst, const char* src ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_orig = dst; \ -+ \ -+ while (*src) *dst++ = *src++; \ -+ *dst = 0; \ -+ \ -+ /* This checks for overlap after copying, unavoidable without */ \ -+ /* pre-counting length... should be ok */ \ -+ if (is_overlap(dst_orig, \ -+ src_orig, \ -+ (Addr)dst-(Addr)dst_orig+1, \ -+ (Addr)src-(Addr)src_orig+1)) \ -+ RECORD_OVERLAP_ERROR("stpcpy", dst_orig, src_orig, 0); \ -+ \ -+ return dst; \ -+ } -+ -+#if defined(VGO_linux) -+ STPCPY(VG_Z_LIBC_SONAME, stpcpy) -+ STPCPY(VG_Z_LIBC_SONAME, __GI_stpcpy) -+ STPCPY(VG_Z_LIBC_SONAME, __stpcpy_sse2) -+ STPCPY(VG_Z_LIBC_SONAME, __stpcpy_sse2_unaligned) -+ STPCPY(VG_Z_LD_LINUX_SO_2, stpcpy) -+ STPCPY(VG_Z_LD_LINUX_X86_64_SO_2, stpcpy) -+ -+#elif defined(VGO_darwin) -+ //STPCPY(VG_Z_LIBC_SONAME, stpcpy) -+ //STPCPY(VG_Z_DYLD, stpcpy) -+ -+#endif -+ -+ -+/*---------------------- stpncpy ----------------------*/ -+ -+#define STPNCPY(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20420,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ); \ -+ char* VG_REPLACE_FUNCTION_EZU(20420,soname,fnname) \ -+ ( char* dst, const char* src, SizeT n ) \ -+ { \ -+ const HChar* src_orig = src; \ -+ HChar* dst_str = dst; \ -+ SizeT m = 0; \ -+ \ -+ while (m < n && *src) { m++; *dst++ = *src++; } \ -+ /* Check for overlap after copying; all n bytes of dst are relevant, */ \ -+ /* but only m+1 bytes of src if terminator was found */ \ -+ if (is_overlap(dst_str, src_orig, n, (m < n) ? m+1 : n)) \ -+ RECORD_OVERLAP_ERROR("stpncpy", dst, src, n); \ -+ dst_str = dst; \ -+ while (m++ < n) *dst++ = 0; /* must pad remainder with nulls */ \ -+ \ -+ return dst_str; \ -+ } -+ -+#if defined(VGO_linux) -+ STPNCPY(VG_Z_LIBC_SONAME, stpncpy) -+#endif -+ -+ -+/*---------------------- memset ----------------------*/ -+ -+/* Why are we bothering to intercept this? It seems entirely -+ pointless. */ -+ -+#define MEMSET(soname, fnname) \ -+ void* VG_REPLACE_FUNCTION_EZU(20210,soname,fnname) \ -+ (void *s, Int c, SizeT n); \ -+ void* VG_REPLACE_FUNCTION_EZU(20210,soname,fnname) \ -+ (void *s, Int c, SizeT n) \ -+ { \ -+ if (sizeof(void*) == 8) { \ -+ Addr a = (Addr)s; \ -+ ULong c8 = (c & 0xFF); \ -+ c8 = (c8 << 8) | c8; \ -+ c8 = (c8 << 16) | c8; \ -+ c8 = (c8 << 32) | c8; \ -+ while ((a & 7) != 0 && n >= 1) \ -+ { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -+ while (n >= 8) \ -+ { *(ULong*)a = c8; a += 8; n -= 8; } \ -+ while (n >= 1) \ -+ { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -+ return s; \ -+ } else { \ -+ Addr a = (Addr)s; \ -+ UInt c4 = (c & 0xFF); \ -+ c4 = (c4 << 8) | c4; \ -+ c4 = (c4 << 16) | c4; \ -+ while ((a & 3) != 0 && n >= 1) \ -+ { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -+ while (n >= 4) \ -+ { *(UInt*)a = c4; a += 4; n -= 4; } \ -+ while (n >= 1) \ -+ { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \ -+ return s; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ MEMSET(VG_Z_LIBC_SONAME, memset) -+ -+#elif defined(VGO_darwin) -+ //MEMSET(VG_Z_LIBC_SONAME, memset) -+ //MEMSET(VG_Z_DYLD, memset) -+ MEMSET(VG_Z_LIBC_SONAME, memset) -+ -+#endif -+ -+ -+/*---------------------- memmove ----------------------*/ -+ -+/* memmove -- use the MEMMOVE defn above. */ -+ -+#if defined(VGO_linux) -+ MEMMOVE(VG_Z_LIBC_SONAME, memmove) -+ MEMMOVE(VG_Z_LIBC_SONAME, __GI_memmove) -+ -+#elif defined(VGO_darwin) -+# if DARWIN_VERS <= DARWIN_10_6 -+ MEMMOVE(VG_Z_LIBC_SONAME, memmove) -+# endif -+ MEMMOVE(VG_Z_LIBC_SONAME, memmoveZDVARIANTZDsse3x) /* memmove$VARIANT$sse3x */ -+ MEMMOVE(VG_Z_LIBC_SONAME, memmoveZDVARIANTZDsse42) /* memmove$VARIANT$sse42 */ -+ -+#endif -+ -+ -+/*---------------------- bcopy ----------------------*/ -+ -+#define BCOPY(soname, fnname) \ -+ void VG_REPLACE_FUNCTION_EZU(20230,soname,fnname) \ -+ (const void *srcV, void *dstV, SizeT n); \ -+ void VG_REPLACE_FUNCTION_EZU(20230,soname,fnname) \ -+ (const void *srcV, void *dstV, SizeT n) \ -+ { \ -+ SizeT i; \ -+ HChar* dst = dstV; \ -+ const HChar* src = srcV; \ -+ if (dst < src) { \ -+ for (i = 0; i < n; i++) \ -+ dst[i] = src[i]; \ -+ } \ -+ else \ -+ if (dst > src) { \ -+ for (i = 0; i < n; i++) \ -+ dst[n-i-1] = src[n-i-1]; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ BCOPY(VG_Z_LIBC_SONAME, bcopy) -+ -+#elif defined(VGO_darwin) -+ //BCOPY(VG_Z_LIBC_SONAME, bcopy) -+ //BCOPY(VG_Z_DYLD, bcopy) -+ -+#endif -+ -+ -+/*-------------------- memmove_chk --------------------*/ -+ -+/* glibc 2.5 variant of memmove which checks the dest is big enough. -+ There is no specific part of glibc that this is copied from. */ -+#define GLIBC25___MEMMOVE_CHK(soname, fnname) \ -+ void* VG_REPLACE_FUNCTION_EZU(20240,soname,fnname) \ -+ (void *dstV, const void *srcV, SizeT n, SizeT destlen); \ -+ void* VG_REPLACE_FUNCTION_EZU(20240,soname,fnname) \ -+ (void *dstV, const void *srcV, SizeT n, SizeT destlen) \ -+ { \ -+ SizeT i; \ -+ HChar* dst = dstV; \ -+ const HChar* src = srcV; \ -+ if (destlen < n) \ -+ goto badness; \ -+ if (dst < src) { \ -+ for (i = 0; i < n; i++) \ -+ dst[i] = src[i]; \ -+ } \ -+ else \ -+ if (dst > src) { \ -+ for (i = 0; i < n; i++) \ -+ dst[n-i-1] = src[n-i-1]; \ -+ } \ -+ return dst; \ -+ badness: \ -+ VALGRIND_PRINTF_BACKTRACE( \ -+ "*** memmove_chk: buffer overflow detected ***: " \ -+ "program terminated\n"); \ -+ my_exit(127); \ -+ /*NOTREACHED*/ \ -+ return NULL; \ -+ } -+ -+#if defined(VGO_linux) -+ GLIBC25___MEMMOVE_CHK(VG_Z_LIBC_SONAME, __memmove_chk) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*-------------------- strchrnul --------------------*/ -+ -+/* Find the first occurrence of C in S or the final NUL byte. */ -+#define GLIBC232_STRCHRNUL(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20250,soname,fnname) \ -+ (const char* s, int c_in); \ -+ char* VG_REPLACE_FUNCTION_EZU(20250,soname,fnname) \ -+ (const char* s, int c_in) \ -+ { \ -+ UChar c = (UChar) c_in; \ -+ UChar* char_ptr = (UChar *)s; \ -+ while (1) { \ -+ if (*char_ptr == 0) return (HChar *)char_ptr; \ -+ if (*char_ptr == c) return (HChar *)char_ptr; \ -+ char_ptr++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ GLIBC232_STRCHRNUL(VG_Z_LIBC_SONAME, strchrnul) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- rawmemchr ----------------------*/ -+ -+/* Find the first occurrence of C in S. */ -+#define GLIBC232_RAWMEMCHR(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20260,soname,fnname) \ -+ (const char* s, int c_in); \ -+ char* VG_REPLACE_FUNCTION_EZU(20260,soname,fnname) \ -+ (const char* s, int c_in) \ -+ { \ -+ UChar c = (UChar) c_in; \ -+ UChar* char_ptr = (UChar *)s; \ -+ while (1) { \ -+ if (*char_ptr == c) return (HChar *)char_ptr; \ -+ char_ptr++; \ -+ } \ -+ } -+ -+#if defined (VGO_linux) -+ GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, rawmemchr) -+ GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, __GI___rawmemchr) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- strcpy_chk ----------------------*/ -+ -+/* glibc variant of strcpy that checks the dest is big enough. -+ Copied from glibc-2.5/debug/test-strcpy_chk.c. */ -+#define GLIBC25___STRCPY_CHK(soname,fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20270,soname,fnname) \ -+ (char* dst, const char* src, SizeT len); \ -+ char* VG_REPLACE_FUNCTION_EZU(20270,soname,fnname) \ -+ (char* dst, const char* src, SizeT len) \ -+ { \ -+ HChar* ret = dst; \ -+ if (! len) \ -+ goto badness; \ -+ while ((*dst++ = *src++) != '\0') \ -+ if (--len == 0) \ -+ goto badness; \ -+ return ret; \ -+ badness: \ -+ VALGRIND_PRINTF_BACKTRACE( \ -+ "*** strcpy_chk: buffer overflow detected ***: " \ -+ "program terminated\n"); \ -+ my_exit(127); \ -+ /*NOTREACHED*/ \ -+ return NULL; \ -+ } -+ -+#if defined(VGO_linux) -+ GLIBC25___STRCPY_CHK(VG_Z_LIBC_SONAME, __strcpy_chk) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- stpcpy_chk ----------------------*/ -+ -+/* glibc variant of stpcpy that checks the dest is big enough. -+ Copied from glibc-2.5/debug/test-stpcpy_chk.c. */ -+#define GLIBC25___STPCPY_CHK(soname,fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20280,soname,fnname) \ -+ (char* dst, const char* src, SizeT len); \ -+ char* VG_REPLACE_FUNCTION_EZU(20280,soname,fnname) \ -+ (char* dst, const char* src, SizeT len) \ -+ { \ -+ if (! len) \ -+ goto badness; \ -+ while ((*dst++ = *src++) != '\0') \ -+ if (--len == 0) \ -+ goto badness; \ -+ return dst - 1; \ -+ badness: \ -+ VALGRIND_PRINTF_BACKTRACE( \ -+ "*** stpcpy_chk: buffer overflow detected ***: " \ -+ "program terminated\n"); \ -+ my_exit(127); \ -+ /*NOTREACHED*/ \ -+ return NULL; \ -+ } -+ -+#if defined(VGO_linux) -+ GLIBC25___STPCPY_CHK(VG_Z_LIBC_SONAME, __stpcpy_chk) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- mempcpy ----------------------*/ -+ -+/* mempcpy */ -+#define GLIBC25_MEMPCPY(soname, fnname) \ -+ void* VG_REPLACE_FUNCTION_EZU(20290,soname,fnname) \ -+ ( void *dst, const void *src, SizeT len ); \ -+ void* VG_REPLACE_FUNCTION_EZU(20290,soname,fnname) \ -+ ( void *dst, const void *src, SizeT len ) \ -+ { \ -+ register HChar *d; \ -+ register HChar *s; \ -+ SizeT len_saved = len; \ -+ \ -+ if (len == 0) \ -+ return dst; \ -+ \ -+ if (is_overlap(dst, src, len, len)) \ -+ RECORD_OVERLAP_ERROR("mempcpy", dst, src, len); \ -+ \ -+ if ( dst > src ) { \ -+ d = (char *)dst + len - 1; \ -+ s = (char *)src + len - 1; \ -+ while ( len-- ) { \ -+ *d-- = *s--; \ -+ } \ -+ } else if ( dst < src ) { \ -+ d = (char *)dst; \ -+ s = (char *)src; \ -+ while ( len-- ) { \ -+ *d++ = *s++; \ -+ } \ -+ } \ -+ return (void*)( ((char*)dst) + len_saved ); \ -+ } -+ -+#if defined(VGO_linux) -+ GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy) -+ GLIBC25_MEMPCPY(VG_Z_LD_SO_1, mempcpy) /* ld.so.1 */ -+ GLIBC25_MEMPCPY(VG_Z_LD_LINUX_SO_3, mempcpy) /* ld-linux.so.3 */ -+ GLIBC25_MEMPCPY(VG_Z_LD_LINUX_X86_64_SO_2, mempcpy) /* ld-linux-x86-64.so.2 */ -+ -+#elif defined(VGO_darwin) -+ //GLIBC25_MEMPCPY(VG_Z_LIBC_SONAME, mempcpy) -+ -+#endif -+ -+ -+/*-------------------- memcpy_chk --------------------*/ -+ -+#define GLIBC26___MEMCPY_CHK(soname, fnname) \ -+ void* VG_REPLACE_FUNCTION_EZU(20300,soname,fnname) \ -+ (void* dst, const void* src, SizeT len, SizeT dstlen ); \ -+ void* VG_REPLACE_FUNCTION_EZU(20300,soname,fnname) \ -+ (void* dst, const void* src, SizeT len, SizeT dstlen ) \ -+ { \ -+ register HChar *d; \ -+ register const HChar *s; \ -+ \ -+ if (dstlen < len) goto badness; \ -+ \ -+ if (len == 0) \ -+ return dst; \ -+ \ -+ if (is_overlap(dst, src, len, len)) \ -+ RECORD_OVERLAP_ERROR("memcpy_chk", dst, src, len); \ -+ \ -+ if ( dst > src ) { \ -+ d = (HChar *)dst + len - 1; \ -+ s = (const HChar *)src + len - 1; \ -+ while ( len-- ) { \ -+ *d-- = *s--; \ -+ } \ -+ } else if ( dst < src ) { \ -+ d = (HChar *)dst; \ -+ s = (const HChar *)src; \ -+ while ( len-- ) { \ -+ *d++ = *s++; \ -+ } \ -+ } \ -+ return dst; \ -+ badness: \ -+ VALGRIND_PRINTF_BACKTRACE( \ -+ "*** memcpy_chk: buffer overflow detected ***: " \ -+ "program terminated\n"); \ -+ my_exit(127); \ -+ /*NOTREACHED*/ \ -+ return NULL; \ -+ } -+ -+#if defined(VGO_linux) -+ GLIBC26___MEMCPY_CHK(VG_Z_LIBC_SONAME, __memcpy_chk) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- strstr ----------------------*/ -+ -+#define STRSTR(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20310,soname,fnname) \ -+ (const char* haystack, const char* needle); \ -+ char* VG_REPLACE_FUNCTION_EZU(20310,soname,fnname) \ -+ (const char* haystack, const char* needle) \ -+ { \ -+ const HChar* h = haystack; \ -+ const HChar* n = needle; \ -+ \ -+ /* find the length of n, not including terminating zero */ \ -+ UWord nlen = 0; \ -+ while (n[nlen]) nlen++; \ -+ \ -+ /* if n is the empty string, match immediately. */ \ -+ if (nlen == 0) return (HChar *)h; \ -+ \ -+ /* assert(nlen >= 1); */ \ -+ HChar n0 = n[0]; \ -+ \ -+ while (1) { \ -+ const HChar hh = *h; \ -+ if (hh == 0) return NULL; \ -+ if (hh != n0) { h++; continue; } \ -+ \ -+ UWord i; \ -+ for (i = 0; i < nlen; i++) { \ -+ if (n[i] != h[i]) \ -+ break; \ -+ } \ -+ /* assert(i >= 0 && i <= nlen); */ \ -+ if (i == nlen) \ -+ return (HChar *)h; \ -+ \ -+ h++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ STRSTR(VG_Z_LIBC_SONAME, strstr) -+ STRSTR(VG_Z_LIBC_SONAME, __strstr_sse2) -+ STRSTR(VG_Z_LIBC_SONAME, __strstr_sse42) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- strpbrk ----------------------*/ -+ -+#define STRPBRK(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20320,soname,fnname) \ -+ (const char* sV, const char* acceptV); \ -+ char* VG_REPLACE_FUNCTION_EZU(20320,soname,fnname) \ -+ (const char* sV, const char* acceptV) \ -+ { \ -+ const HChar* s = sV; \ -+ const HChar* accept = acceptV; \ -+ \ -+ /* find the length of 'accept', not including terminating zero */ \ -+ UWord nacc = 0; \ -+ while (accept[nacc]) nacc++; \ -+ \ -+ /* if n is the empty string, fail immediately. */ \ -+ if (nacc == 0) return NULL; \ -+ \ -+ /* assert(nacc >= 1); */ \ -+ while (1) { \ -+ UWord i; \ -+ HChar sc = *s; \ -+ if (sc == 0) \ -+ break; \ -+ for (i = 0; i < nacc; i++) { \ -+ if (sc == accept[i]) \ -+ return (HChar *)s; \ -+ } \ -+ s++; \ -+ } \ -+ \ -+ return NULL; \ -+ } -+ -+#if defined(VGO_linux) -+ STRPBRK(VG_Z_LIBC_SONAME, strpbrk) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- strcspn ----------------------*/ -+ -+#define STRCSPN(soname, fnname) \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20330,soname,fnname) \ -+ (const char* sV, const char* rejectV); \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20330,soname,fnname) \ -+ (const char* sV, const char* rejectV) \ -+ { \ -+ const HChar* s = sV; \ -+ const HChar* reject = rejectV; \ -+ \ -+ /* find the length of 'reject', not including terminating zero */ \ -+ UWord nrej = 0; \ -+ while (reject[nrej]) nrej++; \ -+ \ -+ UWord len = 0; \ -+ while (1) { \ -+ UWord i; \ -+ HChar sc = *s; \ -+ if (sc == 0) \ -+ break; \ -+ for (i = 0; i < nrej; i++) { \ -+ if (sc == reject[i]) \ -+ break; \ -+ } \ -+ /* assert(i >= 0 && i <= nrej); */ \ -+ if (i < nrej) \ -+ break; \ -+ s++; \ -+ len++; \ -+ } \ -+ \ -+ return len; \ -+ } -+ -+#if defined(VGO_linux) -+ STRCSPN(VG_Z_LIBC_SONAME, strcspn) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- strspn ----------------------*/ -+ -+#define STRSPN(soname, fnname) \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20340,soname,fnname) \ -+ (const char* sV, const char* acceptV); \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20340,soname,fnname) \ -+ (const char* sV, const char* acceptV) \ -+ { \ -+ const UChar* s = (const UChar *)sV; \ -+ const UChar* accept = (const UChar *)acceptV; \ -+ \ -+ /* find the length of 'accept', not including terminating zero */ \ -+ UWord nacc = 0; \ -+ while (accept[nacc]) nacc++; \ -+ if (nacc == 0) return 0; \ -+ \ -+ UWord len = 0; \ -+ while (1) { \ -+ UWord i; \ -+ HChar sc = *s; \ -+ if (sc == 0) \ -+ break; \ -+ for (i = 0; i < nacc; i++) { \ -+ if (sc == accept[i]) \ -+ break; \ -+ } \ -+ /* assert(i >= 0 && i <= nacc); */ \ -+ if (i == nacc) \ -+ break; \ -+ s++; \ -+ len++; \ -+ } \ -+ \ -+ return len; \ -+ } -+ -+#if defined(VGO_linux) -+ STRSPN(VG_Z_LIBC_SONAME, strspn) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- strcasestr ----------------------*/ -+ -+#define STRCASESTR(soname, fnname) \ -+ char* VG_REPLACE_FUNCTION_EZU(20350,soname,fnname) \ -+ (const char* haystack, const char* needle); \ -+ char* VG_REPLACE_FUNCTION_EZU(20350,soname,fnname) \ -+ (const char* haystack, const char* needle) \ -+ { \ -+ extern int tolower(int); \ -+ const HChar* h = haystack; \ -+ const HChar* n = needle; \ -+ \ -+ /* find the length of n, not including terminating zero */ \ -+ UWord nlen = 0; \ -+ while (n[nlen]) nlen++; \ -+ \ -+ /* if n is the empty string, match immediately. */ \ -+ if (nlen == 0) return (HChar *)h; \ -+ \ -+ /* assert(nlen >= 1); */ \ -+ UChar n0 = tolower(n[0]); \ -+ \ -+ while (1) { \ -+ UChar hh = tolower(*h); \ -+ if (hh == 0) return NULL; \ -+ if (hh != n0) { h++; continue; } \ -+ \ -+ UWord i; \ -+ for (i = 0; i < nlen; i++) { \ -+ if (tolower(n[i]) != tolower(h[i])) \ -+ break; \ -+ } \ -+ /* assert(i >= 0 && i <= nlen); */ \ -+ if (i == nlen) \ -+ return (HChar *)h; \ -+ \ -+ h++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) -+ STRCASESTR(VG_Z_LIBC_SONAME, strcasestr) -+# endif -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+ -+/*---------------------- wcslen ----------------------*/ -+ -+// This is a wchar_t equivalent to strlen. Unfortunately -+// we don't have wchar_t available here, but it looks like -+// a 32 bit int on Linux. I don't know if that is also -+// valid on MacOSX. -+ -+#define WCSLEN(soname, fnname) \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \ -+ ( const UInt* str ); \ -+ SizeT VG_REPLACE_FUNCTION_EZU(20370,soname,fnname) \ -+ ( const UInt* str ) \ -+ { \ -+ SizeT i = 0; \ -+ while (str[i] != 0) i++; \ -+ return i; \ -+ } -+ -+#if defined(VGO_linux) -+ WCSLEN(VG_Z_LIBC_SONAME, wcslen) -+ -+#elif defined(VGO_darwin) -+ -+#endif -+ -+/*---------------------- wcscmp ----------------------*/ -+ -+// This is a wchar_t equivalent to strcmp. We don't -+// have wchar_t available here, but in the GNU C Library -+// wchar_t is always 32 bits wide and wcscmp uses signed -+// comparison, not unsigned as in strcmp function. -+ -+#define WCSCMP(soname, fnname) \ -+ int VG_REPLACE_FUNCTION_EZU(20380,soname,fnname) \ -+ ( const Int* s1, const Int* s2 ); \ -+ int VG_REPLACE_FUNCTION_EZU(20380,soname,fnname) \ -+ ( const Int* s1, const Int* s2 ) \ -+ { \ -+ register Int c1; \ -+ register Int c2; \ -+ while (True) { \ -+ c1 = *s1; \ -+ c2 = *s2; \ -+ if (c1 != c2) break; \ -+ if (c1 == 0) break; \ -+ s1++; s2++; \ -+ } \ -+ if (c1 < c2) return -1; \ -+ if (c1 > c2) return 1; \ -+ return 0; \ -+ } -+ -+#if defined(VGO_linux) -+ WCSCMP(VG_Z_LIBC_SONAME, wcscmp) -+#endif -+ -+/*---------------------- wcscpy ----------------------*/ -+ -+// This is a wchar_t equivalent to strcpy. We don't -+// have wchar_t available here, but in the GNU C Library -+// wchar_t is always 32 bits wide. -+ -+#define WCSCPY(soname, fnname) \ -+ Int* VG_REPLACE_FUNCTION_EZU(20390,soname,fnname) \ -+ ( Int* dst, const Int* src ); \ -+ Int* VG_REPLACE_FUNCTION_EZU(20390,soname,fnname) \ -+ ( Int* dst, const Int* src ) \ -+ { \ -+ const Int* src_orig = src; \ -+ Int* dst_orig = dst; \ -+ \ -+ while (*src) *dst++ = *src++; \ -+ *dst = 0; \ -+ \ -+ /* This checks for overlap after copying, unavoidable without */ \ -+ /* pre-counting length... should be ok */ \ -+ if (is_overlap(dst_orig, \ -+ src_orig, \ -+ (Addr)dst-(Addr)dst_orig+1, \ -+ (Addr)src-(Addr)src_orig+1)) \ -+ RECORD_OVERLAP_ERROR("wcscpy", dst_orig, src_orig, 0); \ -+ \ -+ return dst_orig; \ -+ } -+ -+#if defined(VGO_linux) -+ WCSCPY(VG_Z_LIBC_SONAME, wcscpy) -+#endif -+ -+ -+/*---------------------- wcschr ----------------------*/ -+ -+// This is a wchar_t equivalent to strchr. We don't -+// have wchar_t available here, but in the GNU C Library -+// wchar_t is always 32 bits wide. -+ -+#define WCSCHR(soname, fnname) \ -+ Int* VG_REPLACE_FUNCTION_EZU(20400,soname,fnname) ( const Int* s, Int c ); \ -+ Int* VG_REPLACE_FUNCTION_EZU(20400,soname,fnname) ( const Int* s, Int c ) \ -+ { \ -+ Int* p = (Int*)s; \ -+ while (True) { \ -+ if (*p == c) return p; \ -+ if (*p == 0) return NULL; \ -+ p++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ WCSCHR(VG_Z_LIBC_SONAME, wcschr) -+#endif -+/*---------------------- wcsrchr ----------------------*/ -+ -+// This is a wchar_t equivalent to strrchr. We don't -+// have wchar_t available here, but in the GNU C Library -+// wchar_t is always 32 bits wide. -+ -+#define WCSRCHR(soname, fnname) \ -+ Int* VG_REPLACE_FUNCTION_EZU(20410,soname,fnname)( const Int* s, Int c ); \ -+ Int* VG_REPLACE_FUNCTION_EZU(20410,soname,fnname)( const Int* s, Int c ) \ -+ { \ -+ Int* p = (Int*) s; \ -+ Int* last = NULL; \ -+ while (True) { \ -+ if (*p == c) last = p; \ -+ if (*p == 0) return last; \ -+ p++; \ -+ } \ -+ } -+ -+#if defined(VGO_linux) -+ WCSRCHR(VG_Z_LIBC_SONAME, wcsrchr) -+#endif -+ -+/*------------------------------------------------------------*/ -+/*--- Improve definedness checking of process environment ---*/ -+/*------------------------------------------------------------*/ -+ -+#if defined(VGO_linux) -+ -+/* If these wind up getting generated via a macro, so that multiple -+ versions of each function exist (as above), use the _EZU variants -+ to assign equivalance class tags. */ -+ -+/*---------------------- putenv ----------------------*/ -+ -+int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, putenv) (char* string); -+int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, putenv) (char* string) -+{ -+ OrigFn fn; -+ Word result; -+ const HChar* p = string; -+ VALGRIND_GET_ORIG_FN(fn); -+ /* Now by walking over the string we magically produce -+ traces when hitting undefined memory. */ -+ if (p) -+ while (*p++) -+ __asm__ __volatile__("" ::: "memory"); -+ CALL_FN_W_W(result, fn, string); -+ return result; -+} -+ -+ -+/*---------------------- unsetenv ----------------------*/ -+ -+int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, unsetenv) (const char* name); -+int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, unsetenv) (const char* name) -+{ -+ OrigFn fn; -+ Word result; -+ const HChar* p = name; -+ VALGRIND_GET_ORIG_FN(fn); -+ /* Now by walking over the string we magically produce -+ traces when hitting undefined memory. */ -+ if (p) -+ while (*p++) -+ __asm__ __volatile__("" ::: "memory"); -+ CALL_FN_W_W(result, fn, name); -+ return result; -+} -+ -+ -+/*---------------------- setenv ----------------------*/ -+ -+/* setenv */ -+int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, setenv) -+ (const char* name, const char* value, int overwrite); -+int VG_WRAP_FUNCTION_ZU(VG_Z_LIBC_SONAME, setenv) -+ (const char* name, const char* value, int overwrite) -+{ -+ OrigFn fn; -+ Word result; -+ const HChar* p; -+ VALGRIND_GET_ORIG_FN(fn); -+ /* Now by walking over the string we magically produce -+ traces when hitting undefined memory. */ -+ if (name) -+ for (p = name; *p; p++) -+ __asm__ __volatile__("" ::: "memory"); -+ if (value) -+ for (p = value; *p; p++) -+ __asm__ __volatile__("" ::: "memory"); -+ (void) VALGRIND_CHECK_VALUE_IS_DEFINED (overwrite); -+ CALL_FN_W_WWW(result, fn, name, value, overwrite); -+ return result; -+} -+ -+#endif /* defined(VGO_linux) */ -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ - -Property changes on: shared/vg_replace_strmem.c -___________________________________________________________________ -Added: svn:keywords -## -0,0 +1 ## -+author date id revision -\ No newline at end of property -Added: svn:eol-style -## -0,0 +1 ## -+native -\ No newline at end of property -Index: tests -=================================================================== ---- tests (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ tests (.../trunk) (revision 13981) - -Property changes on: tests -___________________________________________________________________ -Modified: svn:ignore -## -12,3 +12,4 ## - s390x_features - mips_features - mips32_features -+power_insn_available -Index: tests/Makefile.am -=================================================================== ---- tests/Makefile.am (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ tests/Makefile.am (.../trunk) (revision 13981) -@@ -30,7 +30,8 @@ - true \ - x86_amd64_features \ - s390x_features \ -- mips_features -+ mips_features \ -+ power_insn_available - - AM_CFLAGS += $(AM_FLAG_M3264_PRI) - AM_CXXFLAGS += $(AM_FLAG_M3264_PRI) -Index: tests/arch_test.c -=================================================================== ---- tests/arch_test.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ tests/arch_test.c (.../trunk) (revision 13981) -@@ -60,6 +60,9 @@ - #elif defined(VGP_arm_linux) - if ( 0 == strcmp( arch, "arm" ) ) return True; - -+#elif defined(VGP_arm64_linux) -+ if ( 0 == strcmp( arch, "arm64" ) ) return True; -+ - #elif defined(VGP_mips32_linux) - if ( 0 == strcmp( arch, "mips32" ) ) return True; - -Index: tests/check_headers_and_includes -=================================================================== ---- tests/check_headers_and_includes (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ tests/check_headers_and_includes (.../trunk) (revision 13981) -@@ -14,9 +14,10 @@ - - use strict; - use warnings; -+use File::Basename; - use Getopt::Long; - --my $this_script = "check_headers_and_includes"; -+my $this_script = basename($0); - - # The list of top-level directories is divided into three sets: - # -@@ -41,6 +42,7 @@ - "helgrind", => 1, - "callgrind" => 1, - "cachegrind" => 1, -+ "shared" => 1, - "exp-bbv" => 1, - "exp-dhat" => 1, - "exp-sgcheck" => 1 -@@ -147,18 +149,6 @@ - } - - #--------------------------------------------------------------------- --# Given a path name strip leading directories. --#--------------------------------------------------------------------- --sub basename { -- my ($path_name) = @_; -- my $file = $path_name; -- -- $file =~ s/^.*\///; -- -- return $file; --} -- --#--------------------------------------------------------------------- - # Return 1, if file is located in /include - #--------------------------------------------------------------------- - sub is_coregrind_export_header { -Index: tests/filter_stderr_basic -=================================================================== ---- tests/filter_stderr_basic (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ tests/filter_stderr_basic (.../trunk) (revision 13981) -@@ -47,6 +47,10 @@ - # complete list of messages in the bash source file siglist.c. - perl -n -e 'print if !/^(Segmentation fault|Alarm clock|Aborted|Bus error)( \(core dumped\))?$/' | - -+# Translate intercepted glibc functions back to their canonical name -+perl -p -e "s/: memcpy\@\@?GLIBC_[.1-9]+ \(vg_replace_strmem.c:...\)/: memcpy \(vg_replace_strmem.c:...\)/" | -+sed -e "s/: \(__GI_\|__\|\)\(memcmp\|memcpy\|strcpy\|strncpy\|strchr\|strrchr\)\(\|_sse4_1\|_sse42\|_sse2_unaligned\) (vg_replace_strmem.c:/: \2 (vg_replace_strmem.c:/" | -+ - # Remove any ": dumping core" message as the user might have a - # limit set that prevents the core dump - sed "s/\(signal [0-9]* (SIG[A-Z]*)\): dumping core/\1/" | -Index: tests/mips_features.c -=================================================================== ---- tests/mips_features.c (.../tags/VALGRIND_3_9_0) (revision 13981) -+++ tests/mips_features.c (.../trunk) (revision 13981) -@@ -47,7 +47,7 @@ - static int go(char *feature) - { - int cpuinfo; -- if ( (strcmp(feature, "mips32-dsp") == 0)) { -+ if (strcmp(feature, "mips32-dsp") == 0) { - const char *dsp = "dsp"; - cpuinfo = mipsCPUInfo(dsp); - if (cpuinfo == 1) { -@@ -55,7 +55,7 @@ - } else{ - return FEATURE_NOT_PRESENT; - } -- } else if ((strcmp(feature, "mips32-dspr2") == 0)) { -+ } else if (strcmp(feature, "mips32-dspr2") == 0) { - const char *dsp2 = "dsp2"; - cpuinfo = mipsCPUInfo(dsp2); - if (cpuinfo == 1) { -@@ -63,7 +63,7 @@ - } else{ - return FEATURE_NOT_PRESENT; - } -- } else if ((strcmp(feature, "cavium-octeon") == 0)) { -+ } else if (strcmp(feature, "cavium-octeon") == 0) { - const char *cavium = "Cavium Octeon"; - cpuinfo = mipsCPUInfo(cavium); - if (cpuinfo == 1) { -@@ -71,6 +71,20 @@ - } else{ - return FEATURE_NOT_PRESENT; - } -+ } else if (strcmp(feature, "cavium-octeon2") == 0) { -+ const char *cavium2 = "Cavium Octeon II"; -+ cpuinfo = mipsCPUInfo(cavium2); -+ if (cpuinfo == 1) { -+ return FEATURE_PRESENT; -+ } else{ -+ return FEATURE_NOT_PRESENT; -+ } -+ } else if (strcmp(feature, "mips-be") == 0) { -+#if defined (_MIPSEB) -+ return FEATURE_PRESENT; -+#else -+ return FEATURE_NOT_PRESENT; -+#endif - } else { - return UNRECOGNISED_FEATURE; - } -Index: tests/power_insn_available.c -=================================================================== ---- tests/power_insn_available.c (.../tags/VALGRIND_3_9_0) (revision 0) -+++ tests/power_insn_available.c (.../trunk) (revision 13981) -@@ -0,0 +1,92 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+typedef enum exit_codes_ { -+ -+#if defined(VGA_ppc32) || defined(VGA_ppc64) -+ /* If the insn that got queried for: exists */ -+ POWER_INSN_AVAILABLE = 0, -+ /* If the insn that got queried for: does not exist on this platform */ -+ POWER_INSN_UNAVAILABLE = 1, -+ /* If the insn that got queried for: does not exist in the vocabulary of this program */ -+ POWER_INSN_UNRECOGNIZED = 2, -+ -+ /* Note: Please keep USAGE_ERROR last. */ -+ USAGE_ERROR -+#else -+ /* When not on a POWER system: */ -+ NOT_POWER_ARCH = 255, -+#endif -+ -+} exit_code; -+ -+#if defined(VGA_ppc32) || defined(VGA_ppc64) -+/* Signal Handling support for unsupported instructions. */ -+static jmp_buf unsup_insn_env; -+static void unsup_insn_handler(int signal_number) -+{ -+ if (signal_number == SIGILL) -+ longjmp(unsup_insn_env, 1); -+ return; -+} -+static struct sigaction unsup_insn_action = (struct sigaction) { -+ .sa_handler = &unsup_insn_handler, -+}; -+ -+/* Instruction existence tests. */ -+static bool dcbzl_available(void) -+{ -+#define MAX_DCBZL_SZB (128) /* largest known effect of dcbzl */ -+ char *test_block = NULL; -+ register char *rb asm ("r14"); -+ int err; -+ bool dcbzl_exists = false; -+ -+ err = posix_memalign ((void **)&test_block, MAX_DCBZL_SZB, 4 * MAX_DCBZL_SZB); -+ if (err) { -+ fprintf(stderr, "posix_memalign() failed (err = %d [%s])\n", err, strerror(err)); -+ return err; -+ } -+ -+ rb = test_block; -+ -+ if (setjmp(unsup_insn_env) != 0) -+ dcbzl_exists = false; -+ else { -+ sigaction(SIGILL, &unsup_insn_action, NULL); -+ asm volatile ("dcbzl 0, %[RB]" : : [RB] "r" (rb)); -+ dcbzl_exists = true; -+ } -+ -+ free(test_block); -+ return dcbzl_exists; -+} -+#endif -+ -+/* main() */ -+int main(int argc, char **argv) -+{ -+ exit_code status; -+ -+#if defined(VGA_ppc32) || defined(VGA_ppc64) -+ char *insn; -+ if (argc != 2) { -+ fprintf(stderr, "usage: power_insn_available \n" ); -+ exit(USAGE_ERROR); -+ } -+ -+ insn = argv[1]; -+ if (strcmp (insn, "dcbzl") == 0) -+ status = ((dcbzl_available ()) ? POWER_INSN_AVAILABLE : POWER_INSN_UNAVAILABLE); -+ else -+ /* power_insn_available has not been taught anything about this insn yet. */ -+ status = POWER_INSN_UNRECOGNIZED; -+#else -+ status = NOT_POWER_ARCH; -+#endif -+ return status; -+} diff --git a/glibc-2.19.patch b/glibc-2.19.patch deleted file mode 100644 index 117b17b..0000000 --- a/glibc-2.19.patch +++ /dev/null @@ -1,18 +0,0 @@ -Index: valgrind-3.9.0/configure.ac -=================================================================== ---- valgrind-3.9.0.orig/configure.ac -+++ valgrind-3.9.0/configure.ac -@@ -939,6 +939,13 @@ case "${GLIBC_VERSION}" in - DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}" - DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}" - ;; -+ 2.19) -+ AC_MSG_RESULT(2.19 family) -+ AC_DEFINE([GLIBC_2_19], 1, [Define to 1 if you're using glibc 2.19.x]) -+ DEFAULT_SUPP="glibc-2.X.supp ${DEFAULT_SUPP}" -+ DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}" -+ DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}" -+ ;; - darwin) - AC_MSG_RESULT(Darwin) - AC_DEFINE([DARWIN_LIBC], 1, [Define to 1 if you're using Darwin]) diff --git a/r13767.diff b/r13767.diff deleted file mode 100644 index f9ac2ac..0000000 --- a/r13767.diff +++ /dev/null @@ -1,349 +0,0 @@ ------------------------------------------------------------------------- -r13767 | dejanj | 2013-12-27 10:06:55 +0100 (Fr, 27. Dez 2013) | 4 Zeilen - -mips32: Adding mips32/Android support to Valgrind. - -Necessary changes to Valgrind to support mips32 on Android. - ------------------------------------------------------------------------- -Index: coregrind/vg_preloaded.c -=================================================================== ---- coregrind/vg_preloaded.c.orig -+++ coregrind/vg_preloaded.c -@@ -57,7 +57,8 @@ void VG_NOTIFY_ON_LOAD(freeres)( void ); - void VG_NOTIFY_ON_LOAD(freeres)( void ) - { - # if !defined(__UCLIBC__) \ -- && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+ && !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - extern void __libc_freeres(void); - __libc_freeres(); - # endif -Index: coregrind/m_options.c -=================================================================== ---- coregrind/m_options.c.orig -+++ coregrind/m_options.c -@@ -47,7 +47,8 @@ VexControl VG_(clo_vex_control); - Bool VG_(clo_error_limit) = True; - Int VG_(clo_error_exitcode) = 0; - --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - VgVgdb VG_(clo_vgdb) = Vg_VgdbNo; // currently disabled on Android - #else - VgVgdb VG_(clo_vgdb) = Vg_VgdbYes; -Index: coregrind/vgdb.c -=================================================================== ---- coregrind/vgdb.c.orig -+++ coregrind/vgdb.c -@@ -1643,7 +1643,8 @@ void received_signal (int signum) - sigpipe++; - } else if (signum == SIGALRM) { - sigalrm++; --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* Android has no pthread_cancel. As it also does not have - PTRACE_INVOKER, there is no need for cleanup action. - So, we just do nothing. */ -Index: coregrind/m_replacemalloc/vg_replace_malloc.c -=================================================================== ---- coregrind/m_replacemalloc/vg_replace_malloc.c.orig -+++ coregrind/m_replacemalloc/vg_replace_malloc.c -@@ -116,7 +116,7 @@ - __attribute__ ((__noreturn__)) - static inline void my_exit ( int x ) - { --# if defined(VGPV_arm_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_mips32_linux_android) - __asm__ __volatile__(".word 0xFFFFFFFF"); - while (1) {} - # elif defined(VGPV_x86_linux_android) -@@ -131,7 +131,8 @@ static inline void my_exit ( int x ) - /* Same problem with getpagesize. */ - static inline int my_getpagesize ( void ) - { --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - return 4096; /* kludge - link failure on Android, for some reason */ - # else - extern int getpagesize (void); -@@ -939,7 +940,8 @@ static inline void trigger_memcheck_erro - MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_usable_size); - MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, malloc_size); - MALLOC_USABLE_SIZE(SO_SYN_MALLOC, malloc_size); --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - MALLOC_USABLE_SIZE(VG_Z_LIBC_SONAME, dlmalloc_usable_size); - MALLOC_USABLE_SIZE(SO_SYN_MALLOC, dlmalloc_usable_size); - # endif -Index: coregrind/m_coredump/coredump-elf.c -=================================================================== ---- coregrind/m_coredump/coredump-elf.c.orig -+++ coregrind/m_coredump/coredump-elf.c -@@ -136,7 +136,8 @@ static void fill_phdr(ESZ(Phdr) *phdr, c - phdr->p_align = VKI_PAGE_SIZE; - } - --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* Android's libc doesn't provide a definition for this. Hence: */ - typedef - struct { -@@ -159,7 +160,8 @@ static UInt note_size(const struct note - + VG_ROUNDUP(n->note.n_descsz, 4); - } - --#if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+#if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - static void add_note(struct note **list, const HChar *name, UInt type, - const void *data, UInt datasz) - { -@@ -605,7 +607,8 @@ void make_elf_coredump(ThreadId tid, con - continue; - - # if defined(VGP_x86_linux) --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - { - vki_elf_fpxregset_t xfpu; - fill_xfpu(&VG_(threads)[i], &xfpu); -@@ -615,18 +618,21 @@ void make_elf_coredump(ThreadId tid, con - # endif - - fill_fpu(&VG_(threads)[i], &fpu); --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - add_note(¬elist, "CORE", NT_FPREGSET, &fpu, sizeof(fpu)); - # endif - - fill_prstatus(&VG_(threads)[i], &prstatus, si); --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - add_note(¬elist, "CORE", NT_PRSTATUS, &prstatus, sizeof(prstatus)); - # endif - } - - fill_prpsinfo(&VG_(threads)[tid], &prpsinfo); --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - add_note(¬elist, "CORE", NT_PRPSINFO, &prpsinfo, sizeof(prpsinfo)); - # endif - -Index: coregrind/m_ume/main.c -=================================================================== ---- coregrind/m_ume/main.c.orig -+++ coregrind/m_ume/main.c -@@ -199,7 +199,8 @@ static Bool is_binary_file(const HChar* - // will refuse to (eg. scripts lacking a "#!" prefix). - static Int do_exec_shell_followup(Int ret, const HChar* exe_name, ExeInfo* info) - { --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - const HChar* default_interp_name = "/system/bin/sh"; - # else - const HChar* default_interp_name = "/bin/sh"; -Index: coregrind/m_syswrap/syswrap-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-linux.c.orig -+++ coregrind/m_syswrap/syswrap-linux.c -@@ -6764,7 +6764,8 @@ PRE(sys_ioctl) - /* These just take an int by value */ - break; - --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* ashmem */ - case VKI_ASHMEM_GET_SIZE: - case VKI_ASHMEM_SET_SIZE: -@@ -6957,7 +6958,8 @@ POST(sys_ioctl) - - /* --- BEGIN special IOCTL handlers for specific Android hardware --- */ - --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - - # if defined(ANDROID_HARDWARE_nexus_s) - -@@ -7875,7 +7877,8 @@ POST(sys_ioctl) - } - break; - --# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+# if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - /* ashmem */ - case VKI_ASHMEM_GET_SIZE: - case VKI_ASHMEM_SET_SIZE: -Index: coregrind/m_syswrap/syswrap-main.c -=================================================================== ---- coregrind/m_syswrap/syswrap-main.c.orig -+++ coregrind/m_syswrap/syswrap-main.c -@@ -467,7 +467,15 @@ void getSyscallArgsFromGuestState ( /*OU - #elif defined(VGP_mips32_linux) - VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla; - canonical->sysno = gst->guest_r2; // v0 -- if (canonical->sysno != __NR_syscall) { -+ if (canonical->sysno == __NR_exit) { -+ canonical->arg1 = gst->guest_r4; // a0 -+ canonical->arg2 = 0; -+ canonical->arg3 = 0; -+ canonical->arg4 = 0; -+ canonical->arg5 = 0; -+ canonical->arg6 = 0; -+ canonical->arg8 = 0; -+ } else if (canonical->sysno != __NR_syscall) { - canonical->arg1 = gst->guest_r4; // a0 - canonical->arg2 = gst->guest_r5; // a1 - canonical->arg3 = gst->guest_r6; // a2 -Index: coregrind/m_initimg/initimg-linux.c -=================================================================== ---- coregrind/m_initimg/initimg-linux.c.orig -+++ coregrind/m_initimg/initimg-linux.c -@@ -640,7 +640,9 @@ Addr setup_client_stack( void* init_sp, - case AT_GID: - case AT_EGID: - case AT_CLKTCK: --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) \ -+ && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - case AT_FPUCW: /* missing on android */ - # endif - /* All these are pointerless, so we don't need to do -@@ -670,7 +672,8 @@ Addr setup_client_stack( void* init_sp, - So, keep the AT_BASE on android for now. - ??? Need to dig in depth about AT_BASE/GDB interaction */ - # if !defined(VGPV_arm_linux_android) \ -- && !defined(VGPV_x86_linux_android) -+ && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - auxv->a_type = AT_IGNORE; - # endif - auxv->u.a_val = info->interp_base; -Index: coregrind/m_debuginfo/readstabs.c -=================================================================== ---- coregrind/m_debuginfo/readstabs.c.orig -+++ coregrind/m_debuginfo/readstabs.c -@@ -36,7 +36,8 @@ - - /* "on Linux (except android), or on Darwin" */ - #if (defined(VGO_linux) && \ -- !(defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android)) \ -+ !(defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android)) \ - || defined(VGO_darwin)) - - #include "pub_core_basics.h" -Index: coregrind/launcher-linux.c -=================================================================== ---- coregrind/launcher-linux.c.orig -+++ coregrind/launcher-linux.c -@@ -222,7 +222,9 @@ static const char *select_platform(const - platform = "mips64-linux"; - } - } else if (header[EI_DATA] == ELFDATA2MSB) { --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) -+# if !defined(VGPV_arm_linux_android) \ -+ && !defined(VGPV_x86_linux_android) \ -+ && !defined(VGPV_mips32_linux_android) - if (ehdr->e_machine == EM_PPC64 && - (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || - ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { -Index: include/vki/vki-linux.h -=================================================================== ---- include/vki/vki-linux.h.orig -+++ include/vki/vki-linux.h -@@ -2865,7 +2865,8 @@ struct vki_getcpu_cache { - // From kernel/common/include/linux/ashmem.h - //---------------------------------------------------------------------- - --#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) -+#if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -+ || defined(VGPV_mips32_linux_android) - - #define VKI_ASHMEM_NAME_LEN 256 - -Index: configure.ac -=================================================================== ---- configure.ac.orig -+++ configure.ac -@@ -957,9 +957,9 @@ DEFAULT_SUPP="exp-sgcheck.supp ${DEFAULT - # Normally the PLAT = (ARCH, OS) characterisation of the platform is enough. - # But there are times where we need a bit more control. The motivating - # and currently only case is Android: this is almost identical to --# {x86,arm}-linux, but not quite. So this introduces the concept of platform --# variant tags, which get passed in the compile as -DVGPV___ --# along with the main -DVGP__ definition. -+# {x86,arm,mips}-linux, but not quite. So this introduces the concept of -+# platform variant tags, which get passed in the compile as -+# -DVGPV___ along with the main -DVGP__ definition. - # - # In almost all cases, the bit is "vanilla". But for Android - # it is "android" instead. -Index: README.android -=================================================================== ---- README.android.orig -+++ README.android -@@ -13,6 +13,12 @@ ARM: - x86: - Android 4.0.3 running on android x86 emulator. - -+mips32: -+ Android 4.1.2 running on android mips emulator. -+ Android 4.2.2 running on android mips emulator. -+ Android 4.3 running on android mips emulator. -+ Android 4.0.4 running on BROADCOM bcm7425 -+ - On android-arm, GDBserver might insert breaks at wrong addresses. - Feedback on this welcome. - -@@ -70,6 +76,10 @@ export AR=$NDKROOT/toolchains/x86-4.4.3/ - export LD=$NDKROOT/toolchains/x86-4.4.3/prebuilt/linux-x86/bin/i686-android-linux-ld - export CC=$NDKROOT/toolchains/x86-4.4.3/prebuilt/linux-x86/bin/i686-android-linux-gcc - -+# For MIPS32 -+export AR=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-ar -+export LD=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-ld -+export CC=$NDKROOT/toolchains/mipsel-linux-android-4.8/prebuilt/linux-x86_64/bin/mipsel-linux-android-gcc - - # Do configuration stuff. Don't mess with the --prefix in the - # configure command below, even if you think it's wrong. -@@ -97,6 +107,13 @@ CPPFLAGS="--sysroot=$NDKROOT/platforms/a - --host=i686-android-linux --target=i686-android-linux \ - --with-tmpdir=/sdcard - -+# for MIPS32 -+CPPFLAGS="--sysroot=$NDKROOT/platforms/android-18/arch-mips -DANDROID_HARDWARE_$HWKIND" \ -+ CFLAGS="--sysroot=$NDKROOT/platforms/android-18/arch-mips" \ -+ ./configure --prefix=/data/local/Inst \ -+ --host=mipsel-linux-android --target=mipsel-linux-android \ -+ --with-tmpdir=/sdcard -+ - # At the end of the configure run, a few lines of details - # are printed. Make sure that you see these two lines: - # -@@ -108,6 +125,10 @@ CPPFLAGS="--sysroot=$NDKROOT/platforms/a - # Platform variant: android - # Primary -DVGPV string: -DVGPV_x86_linux_android=1 - # -+# For mips32: -+# Platform variant: android -+# Primary -DVGPV string: -DVGPV_mips32_linux_android=1 -+# - # If you see anything else at this point, something is wrong, and - # either the build will fail, or will succeed but you'll get something - # which won't work. diff --git a/r13770.diff b/r13770.diff deleted file mode 100644 index 590a8b2..0000000 --- a/r13770.diff +++ /dev/null @@ -1,6551 +0,0 @@ ------------------------------------------------------------------------- -r13770 | sewardj | 2014-01-12 13:54:00 +0100 (So, 12. Jan 2014) | 2 Zeilen - -Add support for ARMv8 AArch64 (the 64 bit ARM instruction set). - ------------------------------------------------------------------------- -Index: configure.ac -=================================================================== ---- configure.ac.orig -+++ configure.ac -@@ -195,6 +195,11 @@ case "${host_cpu}" in - ARCH_MAX="arm" - ;; - -+ aarch64*) -+ AC_MSG_RESULT([ok (${host_cpu})]) -+ ARCH_MAX="arm64" -+ ;; -+ - mips) - AC_MSG_RESULT([ok (${host_cpu})]) - ARCH_MAX="mips32" -@@ -559,6 +564,35 @@ case "$ARCH_MAX-$VGCONF_OS" in - valt_load_address_sec_inner="0xUNSET" - AC_MSG_RESULT([ok (${host_cpu}-${host_os})]) - ;; -+ arm64-linux) -+ valt_load_address_sec_norml="0xUNSET" -+ valt_load_address_sec_inner="0xUNSET" -+ if test x$vg_cv_only64bit = xyes; then -+ VGCONF_ARCH_PRI="arm64" -+ VGCONF_ARCH_SEC="" -+ VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX" -+ VGCONF_PLATFORM_SEC_CAPS="" -+ valt_load_address_pri_norml="0x38000000" -+ valt_load_address_pri_inner="0x28000000" -+ elif test x$vg_cv_only32bit = xyes; then -+ VGCONF_ARCH_PRI="arm" -+ VGCONF_ARCH_SEC="" -+ VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX" -+ VGCONF_PLATFORM_SEC_CAPS="" -+ valt_load_address_pri_norml="0x38000000" -+ valt_load_address_pri_inner="0x28000000" -+ else -+ VGCONF_ARCH_PRI="arm64" -+ VGCONF_ARCH_SEC="arm" -+ VGCONF_PLATFORM_PRI_CAPS="ARM64_LINUX" -+ VGCONF_PLATFORM_SEC_CAPS="ARM_LINUX" -+ valt_load_address_pri_norml="0x38000000" -+ valt_load_address_pri_inner="0x28000000" -+ valt_load_address_sec_norml="0x38000000" -+ valt_load_address_sec_inner="0x28000000" -+ fi -+ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) -+ ;; - s390x-linux) - VGCONF_ARCH_PRI="s390x" - VGCONF_ARCH_SEC="" -@@ -624,7 +658,10 @@ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC3 - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC64, - test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM, -- test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX ) -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ -+ -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX ) -+AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM64, -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_S390X, - test x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_MIPS32, -@@ -645,7 +682,10 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX) - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM_LINUX, -- test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX) -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ -+ -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX) -+AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM64_LINUX, -+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX) - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_S390X_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xS390X_LINUX) -@@ -653,7 +693,6 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ - test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX) - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX) -- - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_DARWIN, - test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xX86_DARWIN) -@@ -670,6 +709,7 @@ AM_CONDITIONAL(VGCONF_OS_IS_LINUX, - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ -+ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX) -@@ -2406,6 +2446,7 @@ if test x$VGCONF_PLATFORM_PRI_CAPS = xX8 - mflag_primary=$FLAG_M32 - elif test x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ -+ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX ; then - mflag_primary=$FLAG_M64 - elif test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN ; then -Index: drd/drd_bitmap.h -=================================================================== ---- drd/drd_bitmap.h.orig -+++ drd/drd_bitmap.h -@@ -140,7 +140,7 @@ Addr make_address(const UWord a1, const - || defined(VGA_mips32) - #define BITS_PER_BITS_PER_UWORD 5 - #elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_s390x) \ -- || defined(VGA_mips64) -+ || defined(VGA_mips64) || defined(VGA_arm64) - #define BITS_PER_BITS_PER_UWORD 6 - #else - #error Unknown platform. -Index: drd/drd_load_store.c -=================================================================== ---- drd/drd_load_store.c.orig -+++ drd/drd_load_store.c -@@ -47,6 +47,8 @@ - #define STACK_POINTER_OFFSET OFFSET_ppc64_GPR1 - #elif defined(VGA_arm) - #define STACK_POINTER_OFFSET OFFSET_arm_R13 -+#elif defined(VGA_arm64) -+#define STACK_POINTER_OFFSET OFFSET_arm64_SP - #elif defined(VGA_s390x) - #define STACK_POINTER_OFFSET OFFSET_s390x_r15 - #elif defined(VGA_mips32) -Index: coregrind/m_main.c -=================================================================== ---- coregrind/m_main.c.orig -+++ coregrind/m_main.c -@@ -2021,6 +2021,8 @@ Int valgrind_main ( Int argc, HChar **ar - iters = 5; - # elif defined(VGP_arm_linux) - iters = 5; -+# elif defined(VGP_arm64_linux) -+ iters = 5; - # elif defined(VGP_s390x_linux) - iters = 10; - # elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -@@ -2908,6 +2910,31 @@ asm("\n" - "\t.word "VG_STRINGIFY(VG_STACK_GUARD_SZB)"\n" - "\t.word "VG_STRINGIFY(VG_STACK_ACTIVE_SZB)"\n" - ); -+#elif defined(VGP_arm64_linux) -+asm("\n" -+ "\t.text\n" -+ "\t.align 2\n" -+ "\t.type _start,#function\n" -+ "\t.global _start\n" -+ "_start:\n" -+ "\tadrp x0, vgPlain_interim_stack\n" -+ "\tadd x0, x0, :lo12:vgPlain_interim_stack\n" -+ // The next 2 assume that VG_STACK_GUARD_SZB fits in 32 bits -+ "\tmov x1, (("VG_STRINGIFY(VG_STACK_GUARD_SZB)") >> 0) & 0xFFFF\n" -+ "\tmovk x1, (("VG_STRINGIFY(VG_STACK_GUARD_SZB)") >> 16) & 0xFFFF," -+ " lsl 16\n" -+ "\tadd x0, x0, x1\n" -+ // The next 2 assume that VG_STACK_ACTIVE_SZB fits in 32 bits -+ "\tmov x1, (("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)") >> 0) & 0xFFFF\n" -+ "\tmovk x1, (("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)") >> 16) & 0xFFFF," -+ " lsl 16\n" -+ "\tadd x0, x0, x1\n" -+ "\tand x0, x0, -16\n" -+ "\tmov x1, sp\n" -+ "\tmov sp, x0\n" -+ "\tmov x0, x1\n" -+ "\tb _start_in_C_linux\n" -+); - #elif defined(VGP_mips32_linux) - asm("\n" - "\t.type _gp_disp,@object\n" -@@ -3033,7 +3060,8 @@ void _start_in_C_linux ( UWord* pArgc ) - - the_iicii.sp_at_startup = (Addr)pArgc; - --# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -+ || defined(VGP_arm64_linux) - { - /* ppc/ppc64 can be configured with different page sizes. - Determine this early. This is an ugly hack and really should -Index: coregrind/m_libcassert.c -=================================================================== ---- coregrind/m_libcassert.c.orig -+++ coregrind/m_libcassert.c -@@ -136,6 +136,25 @@ - (srP)->misc.ARM.r11 = block[4]; \ - (srP)->misc.ARM.r7 = block[5]; \ - } -+#elif defined(VGP_arm64_linux) -+# define GET_STARTREGS(srP) \ -+ { ULong block[4]; \ -+ __asm__ __volatile__( \ -+ "adr x19, 0;" \ -+ "str x19, [%0, #+0];" /* pc */ \ -+ "mov x19, sp;" \ -+ "str x19, [%0, #+8];" /* sp */ \ -+ "str x29, [%0, #+16];" /* fp */ \ -+ "str x30, [%0, #+24];" /* lr */ \ -+ : /* out */ \ -+ : /* in */ "r"(&block[0]) \ -+ : /* trash */ "memory","x19" \ -+ ); \ -+ (srP)->r_pc = block[0]; \ -+ (srP)->r_sp = block[1]; \ -+ (srP)->misc.ARM64.x29 = block[2]; \ -+ (srP)->misc.ARM64.x30 = block[3]; \ -+ } - #elif defined(VGP_s390x_linux) - # define GET_STARTREGS(srP) \ - { ULong ia, sp, fp, lr; \ -Index: coregrind/m_libcproc.c -=================================================================== ---- coregrind/m_libcproc.c.orig -+++ coregrind/m_libcproc.c -@@ -458,8 +458,14 @@ Int VG_(gettid)(void) - * the /proc/self link is pointing... - */ - -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, -+ (UWord)"/proc/self", -+ (UWord)pid, sizeof(pid)); -+# else - res = VG_(do_syscall3)(__NR_readlink, (UWord)"/proc/self", - (UWord)pid, sizeof(pid)); -+# endif - if (!sr_isError(res) && sr_Res(res) > 0) { - HChar* s; - pid[sr_Res(res)] = '\0'; -@@ -552,7 +558,7 @@ Int VG_(getgroups)( Int size, UInt* list - # elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_arm_linux) \ - || defined(VGO_darwin) || defined(VGP_s390x_linux) \ -- || defined(VGP_mips32_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_arm64_linux) - SysRes sres; - sres = VG_(do_syscall2)(__NR_getgroups, size, (Addr)list); - if (sr_isError(sres)) -@@ -763,6 +769,121 @@ void VG_(invalidate_icache) ( void *ptr, - Addr endaddr = startaddr + nbytes; - VG_(do_syscall2)(__NR_ARM_cacheflush, startaddr, endaddr); - -+# elif defined(VGP_arm64_linux) -+ // This arm64_linux section of this function VG_(invalidate_icache) -+ // is copied from -+ // https://github.com/armvixl/vixl/blob/master/src/a64/cpu-a64.cc -+ // which has the following copyright notice: -+ /* -+ Copyright 2013, ARM Limited -+ All rights reserved. -+ -+ Redistribution and use in source and binary forms, with or without -+ modification, are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright notice, -+ this list of conditions and the following disclaimer in the documentation -+ and/or other materials provided with the distribution. -+ * Neither the name of ARM Limited nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND -+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE -+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ // Ask what the I and D line sizes are -+ UInt cache_type_register; -+ // Copy the content of the cache type register to a core register. -+ __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT -+ : [ctr] "=r" (cache_type_register)); -+ -+ const Int kDCacheLineSizeShift = 16; -+ const Int kICacheLineSizeShift = 0; -+ const UInt kDCacheLineSizeMask = 0xf << kDCacheLineSizeShift; -+ const UInt kICacheLineSizeMask = 0xf << kICacheLineSizeShift; -+ -+ // The cache type register holds the size of the I and D caches as a power of -+ // two. -+ const UInt dcache_line_size_power_of_two = -+ (cache_type_register & kDCacheLineSizeMask) >> kDCacheLineSizeShift; -+ const UInt icache_line_size_power_of_two = -+ (cache_type_register & kICacheLineSizeMask) >> kICacheLineSizeShift; -+ -+ const UInt dcache_line_size_ = 1 << dcache_line_size_power_of_two; -+ const UInt icache_line_size_ = 1 << icache_line_size_power_of_two; -+ -+ Addr start = (Addr)ptr; -+ // Sizes will be used to generate a mask big enough to cover a pointer. -+ Addr dsize = (Addr)dcache_line_size_; -+ Addr isize = (Addr)icache_line_size_; -+ -+ // Cache line sizes are always a power of 2. -+ Addr dstart = start & ~(dsize - 1); -+ Addr istart = start & ~(isize - 1); -+ Addr end = start + nbytes; -+ -+ __asm__ __volatile__ ( -+ // Clean every line of the D cache containing the target data. -+ "0: \n\t" -+ // dc : Data Cache maintenance -+ // c : Clean -+ // va : by (Virtual) Address -+ // u : to the point of Unification -+ // The point of unification for a processor is the point by which the -+ // instruction and data caches are guaranteed to see the same copy of a -+ // memory location. See ARM DDI 0406B page B2-12 for more information. -+ "dc cvau, %[dline] \n\t" -+ "add %[dline], %[dline], %[dsize] \n\t" -+ "cmp %[dline], %[end] \n\t" -+ "b.lt 0b \n\t" -+ // Barrier to make sure the effect of the code above is visible to the rest -+ // of the world. -+ // dsb : Data Synchronisation Barrier -+ // ish : Inner SHareable domain -+ // The point of unification for an Inner Shareable shareability domain is -+ // the point by which the instruction and data caches of all the processors -+ // in that Inner Shareable shareability domain are guaranteed to see the -+ // same copy of a memory location. See ARM DDI 0406B page B2-12 for more -+ // information. -+ "dsb ish \n\t" -+ // Invalidate every line of the I cache containing the target data. -+ "1: \n\t" -+ // ic : instruction cache maintenance -+ // i : invalidate -+ // va : by address -+ // u : to the point of unification -+ "ic ivau, %[iline] \n\t" -+ "add %[iline], %[iline], %[isize] \n\t" -+ "cmp %[iline], %[end] \n\t" -+ "b.lt 1b \n\t" -+ // Barrier to make sure the effect of the code above is visible to the rest -+ // of the world. -+ "dsb ish \n\t" -+ // Barrier to ensure any prefetching which happened before this code is -+ // discarded. -+ // isb : Instruction Synchronisation Barrier -+ "isb \n\t" -+ : [dline] "+r" (dstart), -+ [iline] "+r" (istart) -+ : [dsize] "r" (dsize), -+ [isize] "r" (isize), -+ [end] "r" (end) -+ // This code does not write to memory but without the dependency gcc might -+ // move this code before the code is generated. -+ : "cc", "memory" -+ ); -+ - # elif defined(VGA_mips32) || defined(VGA_mips64) - SysRes sres = VG_(do_syscall3)(__NR_cacheflush, (UWord) ptr, - (UWord) nbytes, (UWord) 3); -Index: coregrind/m_cache.c -=================================================================== ---- coregrind/m_cache.c.orig -+++ coregrind/m_cache.c -@@ -539,7 +539,7 @@ get_cache_info(VexArchInfo *vai) - } - - #elif defined(VGA_arm) || defined(VGA_ppc32) || defined(VGA_ppc64) || \ -- defined(VGA_mips32) || defined(VGA_mips64) -+ defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) - - static Bool - get_cache_info(VexArchInfo *vai) -Index: coregrind/m_redir.c -=================================================================== ---- coregrind/m_redir.c.orig -+++ coregrind/m_redir.c -@@ -1318,7 +1318,27 @@ void VG_(redir_initialise) ( void ) - complain_about_stripped_glibc_ldso - ); - } -- /* nothing so far */ -+ -+# elif defined(VGP_arm64_linux) -+ /* If we're using memcheck, use these intercepts right from -+ the start, otherwise ld.so makes a lot of noise. */ -+ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { -+ // add_hardwired_spec( -+ // "ld-linux.so.3", "strlen", -+ // (Addr)&VG_(arm_linux_REDIR_FOR_strlen), -+ // complain_about_stripped_glibc_ldso -+ // ); -+ // //add_hardwired_spec( -+ // // "ld-linux.so.3", "index", -+ // // (Addr)&VG_(arm_linux_REDIR_FOR_index), -+ // // NULL -+ // //); -+ // add_hardwired_spec( -+ // "ld-linux.so.3", "memcpy", -+ // (Addr)&VG_(arm_linux_REDIR_FOR_memcpy), -+ // complain_about_stripped_glibc_ldso -+ // ); -+ } - - # elif defined(VGP_x86_darwin) - /* If we're using memcheck, use these intercepts right from -Index: coregrind/m_libcfile.c -=================================================================== ---- coregrind/m_libcfile.c.orig -+++ coregrind/m_libcfile.c -@@ -116,8 +116,12 @@ SysRes VG_(mknod) ( const HChar* pathnam - } - - SysRes VG_(open) ( const HChar* pathname, Int flags, Int mode ) --{ --# if defined(VGO_linux) -+{ -+# if defined(VGP_arm64_linux) -+ /* ARM64 wants to use __NR_openat rather than __NR_open. */ -+ SysRes res = VG_(do_syscall4)(__NR_openat, -+ VKI_AT_FDCWD, (UWord)pathname, flags, mode); -+# elif defined(VGO_linux) - SysRes res = VG_(do_syscall3)(__NR_open, - (UWord)pathname, flags, mode); - # elif defined(VGO_darwin) -@@ -204,6 +208,9 @@ Int VG_(pipe) ( Int fd[2] ) - } else { - return -1; - } -+# elif defined(VGP_arm64_linux) -+ SysRes res = VG_(do_syscall2)(__NR_pipe2, (UWord)fd, 0); -+ return sr_isError(res) ? -1 : 0; - # elif defined(VGO_linux) - SysRes res = VG_(do_syscall1)(__NR_pipe, (UWord)fd); - return sr_isError(res) ? -1 : 0; -@@ -289,8 +296,14 @@ SysRes VG_(stat) ( const HChar* file_nam - } - } - # endif /* defined(__NR_stat64) */ -+ /* This is the fallback ("vanilla version"). */ - { struct vki_stat buf; -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall3)(__NR3264_fstatat, VKI_AT_FDCWD, -+ (UWord)file_name, (UWord)&buf); -+# else - res = VG_(do_syscall2)(__NR_stat, (UWord)file_name, (UWord)&buf); -+# endif - if (!sr_isError(res)) - TRANSLATE_TO_vg_stat(vgbuf, &buf); - return res; -@@ -385,7 +398,12 @@ Int VG_(rename) ( const HChar* old_name, - - Int VG_(unlink) ( const HChar* file_name ) - { -+# if defined(VGP_arm64_linux) -+ SysRes res = VG_(do_syscall2)(__NR_unlinkat, VKI_AT_FDCWD, -+ (UWord)file_name); -+# else - SysRes res = VG_(do_syscall1)(__NR_unlink, (UWord)file_name); -+# endif - return sr_isError(res) ? (-1) : 0; - } - -@@ -474,7 +492,12 @@ Int VG_(readlink) (const HChar* path, HC - { - SysRes res; - /* res = readlink( path, buf, bufsiz ); */ -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, -+ (UWord)path, (UWord)buf, bufsiz); -+# else - res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz); -+# endif - return sr_isError(res) ? -1 : sr_Res(res); - } - -@@ -509,7 +532,11 @@ Int VG_(access) ( const HChar* path, Boo - UWord w = (irusr ? VKI_R_OK : 0) - | (iwusr ? VKI_W_OK : 0) - | (ixusr ? VKI_X_OK : 0); -+# if defined(VGP_arm64_linux) -+ SysRes res = VG_(do_syscall3)(__NR_faccessat, VKI_AT_FDCWD, (UWord)path, w); -+# else - SysRes res = VG_(do_syscall2)(__NR_access, (UWord)path, w); -+# endif - return sr_isError(res) ? 1 : 0; - - # if defined(VGO_linux) -@@ -624,7 +651,8 @@ SysRes VG_(pread) ( Int fd, void* buf, I - return res; - # elif defined(VGP_amd64_linux) \ - || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset); - return res; - # elif defined(VGP_amd64_darwin) -@@ -877,7 +905,8 @@ Int VG_(socket) ( Int domain, Int type, - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)(__NR_socket, domain, type, protocol ); - return sr_isError(res) ? -1 : sr_Res(res); -@@ -916,7 +945,8 @@ Int my_connect ( Int sockfd, struct vki_ - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)(__NR_connect, sockfd, (UWord)serv_addr, addrlen); - return sr_isError(res) ? -1 : sr_Res(res); -@@ -955,7 +985,8 @@ Int VG_(write_socket)( Int sd, const voi - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall6)(__NR_sendto, sd, (UWord)msg, - count, VKI_MSG_NOSIGNAL, 0,0); -@@ -985,7 +1016,7 @@ Int VG_(getsockname) ( Int sd, struct vk - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)( __NR_getsockname, - (UWord)sd, (UWord)name, (UWord)namelen ); -@@ -1016,7 +1047,7 @@ Int VG_(getpeername) ( Int sd, struct vk - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall3)( __NR_getpeername, - (UWord)sd, (UWord)name, (UWord)namelen ); -@@ -1049,7 +1080,8 @@ Int VG_(getsockopt) ( Int sd, Int level, - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall5)( __NR_getsockopt, - (UWord)sd, (UWord)level, (UWord)optname, -@@ -1085,7 +1117,8 @@ Int VG_(setsockopt) ( Int sd, Int level, - return sr_isError(res) ? -1 : sr_Res(res); - - # elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - SysRes res; - res = VG_(do_syscall5)( __NR_setsockopt, - (UWord)sd, (UWord)level, (UWord)optname, -Index: coregrind/pub_core_aspacemgr.h -=================================================================== ---- coregrind/pub_core_aspacemgr.h.orig -+++ coregrind/pub_core_aspacemgr.h -@@ -345,7 +345,8 @@ extern Bool VG_(am_relocate_nooverlap_cl - // protects such stacks. - - #if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - # define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages - # define VG_STACK_ACTIVE_SZB (4096 * 256) // 1Mb - #else -Index: coregrind/pub_core_machine.h -=================================================================== ---- coregrind/pub_core_machine.h.orig -+++ coregrind/pub_core_machine.h -@@ -66,6 +66,11 @@ - # define VG_ELF_MACHINE EM_ARM - # define VG_ELF_CLASS ELFCLASS32 - # undef VG_PLAT_USES_PPCTOC -+#elif defined(VGP_arm64_linux) -+# define VG_ELF_DATA2XXX ELFDATA2LSB -+# define VG_ELF_MACHINE EM_AARCH64 -+# define VG_ELF_CLASS ELFCLASS64 -+# undef VG_PLAT_USES_PPCTOC - #elif defined(VGO_darwin) - # undef VG_ELF_DATA2XXX - # undef VG_ELF_MACHINE -@@ -122,6 +127,10 @@ - # define VG_INSTR_PTR guest_R15T - # define VG_STACK_PTR guest_R13 - # define VG_FRAME_PTR guest_R11 -+#elif defined(VGA_arm64) -+# define VG_INSTR_PTR guest_PC -+# define VG_STACK_PTR guest_SP -+# define VG_FRAME_PTR guest_SP // FIXME: is this right? - #elif defined(VGA_s390x) - # define VG_INSTR_PTR guest_IA - # define VG_STACK_PTR guest_SP -Index: coregrind/pub_core_syscall.h -=================================================================== ---- coregrind/pub_core_syscall.h.orig -+++ coregrind/pub_core_syscall.h -@@ -76,6 +76,7 @@ extern SysRes VG_(mk_SysRes_amd64_linux) - extern SysRes VG_(mk_SysRes_ppc32_linux) ( UInt val, UInt cr0so ); - extern SysRes VG_(mk_SysRes_ppc64_linux) ( ULong val, ULong cr0so ); - extern SysRes VG_(mk_SysRes_arm_linux) ( Int val ); -+extern SysRes VG_(mk_SysRes_arm64_linux) ( Long val ); - extern SysRes VG_(mk_SysRes_x86_darwin) ( UChar scclass, Bool isErr, - UInt wHI, UInt wLO ); - extern SysRes VG_(mk_SysRes_amd64_darwin)( UChar scclass, Bool isErr, -Index: coregrind/launcher-linux.c -=================================================================== ---- coregrind/launcher-linux.c.orig -+++ coregrind/launcher-linux.c -@@ -57,6 +57,10 @@ - #define EM_X86_64 62 // elf.h doesn't define this on some older systems - #endif - -+#ifndef EM_AARCH64 -+#define EM_AARCH64 183 // ditto -+#endif -+ - /* Report fatal errors */ - __attribute__((noreturn)) - static void barf ( const char *format, ... ) -@@ -220,6 +224,10 @@ static const char *select_platform(const - (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || - ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { - platform = "mips64-linux"; -+ } else if (ehdr->e_machine == EM_AARCH64 && -+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || -+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { -+ platform = "arm64-linux"; - } - } else if (header[EI_DATA] == ELFDATA2MSB) { - # if !defined(VGPV_arm_linux_android) \ -@@ -309,12 +317,13 @@ int main(int argc, char** argv, char** e - target, because on most ppc64-linux setups, the basic /bin, - /usr/bin, etc, stuff is built in 32-bit mode, not 64-bit - mode. */ -- if ((0==strcmp(VG_PLATFORM,"x86-linux")) || -- (0==strcmp(VG_PLATFORM,"amd64-linux")) || -- (0==strcmp(VG_PLATFORM,"ppc32-linux")) || -- (0==strcmp(VG_PLATFORM,"ppc64-linux")) || -- (0==strcmp(VG_PLATFORM,"arm-linux")) || -- (0==strcmp(VG_PLATFORM,"s390x-linux")) || -+ if ((0==strcmp(VG_PLATFORM,"x86-linux")) || -+ (0==strcmp(VG_PLATFORM,"amd64-linux")) || -+ (0==strcmp(VG_PLATFORM,"ppc32-linux")) || -+ (0==strcmp(VG_PLATFORM,"ppc64-linux")) || -+ (0==strcmp(VG_PLATFORM,"arm-linux")) || -+ (0==strcmp(VG_PLATFORM,"arm64-linux")) || -+ (0==strcmp(VG_PLATFORM,"s390x-linux")) || - (0==strcmp(VG_PLATFORM,"mips32-linux")) || - (0==strcmp(VG_PLATFORM,"mips64-linux"))) - default_platform = VG_PLATFORM; -Index: coregrind/m_trampoline.S -=================================================================== ---- coregrind/m_trampoline.S.orig -+++ coregrind/m_trampoline.S -@@ -519,9 +519,9 @@ VG_(trampoline_stuff_end): - # undef UD2_1024 - # undef UD2_PAGE - --/*---------------- ppc32-linux ----------------*/ -- --#elif defined(VGP_arm_linux) -+/*---------------- arm-linux ----------------*/ -+#else -+#if defined(VGP_arm_linux) - - # define UD2_4 .word 0xFFFFFFFF - # define UD2_16 UD2_4 ; UD2_4 ; UD2_4 ; UD2_4 -@@ -680,6 +680,45 @@ VG_(trampoline_stuff_end): - # undef UD2_1024 - # undef UD2_PAGE - -+/*---------------- arm64-linux ----------------*/ -+#else -+#if defined(VGP_arm64_linux) -+ -+# define UD2_4 .word 0xFFFFFFFF -+# define UD2_16 UD2_4 ; UD2_4 ; UD2_4 ; UD2_4 -+# define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16 -+# define UD2_256 UD2_64 ; UD2_64 ; UD2_64 ; UD2_64 -+# define UD2_1024 UD2_256 ; UD2_256 ; UD2_256 ; UD2_256 -+# define UD2_PAGE UD2_1024 ; UD2_1024 ; UD2_1024 ; UD2_1024 -+ -+ /* a leading page of unexecutable code */ -+ UD2_PAGE -+ -+.global VG_(trampoline_stuff_start) -+VG_(trampoline_stuff_start): -+ -+.global VG_(arm64_linux_SUBST_FOR_rt_sigreturn) -+.type VG_(arm64_linux_SUBST_FOR_rt_sigreturn),#function -+VG_(arm64_linux_SUBST_FOR_rt_sigreturn): -+ mov x8, # __NR_rt_sigreturn -+ svc #0 -+ .long 0xFFFFFFFF /*illegal insn*/ -+.size VG_(arm64_linux_SUBST_FOR_rt_sigreturn), \ -+ .-VG_(arm64_linux_SUBST_FOR_rt_sigreturn) -+ -+.global VG_(trampoline_stuff_end) -+VG_(trampoline_stuff_end): -+ -+ /* and a trailing page of unexecutable code */ -+ UD2_PAGE -+ -+# undef UD2_4 -+# undef UD2_16 -+# undef UD2_64 -+# undef UD2_256 -+# undef UD2_1024 -+# undef UD2_PAGE -+ - /*---------------- x86-darwin ----------------*/ - #else - #if defined(VGP_x86_darwin) -@@ -1142,6 +1181,8 @@ VG_(trampoline_stuff_end): - #endif - #endif - #endif -+#endif -+#endif - #endif - #endif - #endif -Index: coregrind/m_coredump/coredump-elf.c -=================================================================== ---- coregrind/m_coredump/coredump-elf.c.orig -+++ coregrind/m_coredump/coredump-elf.c -@@ -233,7 +233,7 @@ static void fill_prpsinfo(const ThreadSt - } - - static void fill_prstatus(const ThreadState *tst, -- struct vki_elf_prstatus *prs, -+ /*OUT*/struct vki_elf_prstatus *prs, - const vki_siginfo_t *si) - { - struct vki_user_regs_struct *regs; -@@ -252,12 +252,11 @@ static void fill_prstatus(const ThreadSt - prs->pr_pgrp = VG_(getpgrp)(); - prs->pr_sid = VG_(getpgrp)(); - --#ifdef VGP_s390x_linux -+#if defined(VGP_s390x_linux) - /* prs->pr_reg has struct type. Need to take address. */ - regs = (struct vki_user_regs_struct *)&(prs->pr_reg); - #else - regs = (struct vki_user_regs_struct *)prs->pr_reg; -- - vg_assert(sizeof(*regs) == sizeof(prs->pr_reg)); - #endif - -@@ -302,10 +301,6 @@ static void fill_prstatus(const ThreadSt - regs->r14 = arch->vex.guest_R14; - regs->r15 = arch->vex.guest_R15; - --//:: regs->cs = arch->vex.guest_CS; --//:: regs->fs = arch->vex.guest_FS; --//:: regs->gs = arch->vex.guest_GS; -- - #elif defined(VGP_ppc32_linux) - # define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -367,6 +362,10 @@ static void fill_prstatus(const ThreadSt - regs->ARM_pc = arch->vex.guest_R15T; - regs->ARM_cpsr = LibVEX_GuestARM_get_cpsr( &arch->vex ); - -+#elif defined(VGP_arm64_linux) -+ (void)arch; -+ I_die_here; -+ - #elif defined(VGP_s390x_linux) - # define DO(n) regs->gprs[n] = arch->vex.guest_r##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -377,6 +376,7 @@ static void fill_prstatus(const ThreadSt - DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); - # undef DO - regs->orig_gpr2 = arch->vex.guest_r2; -+ - #elif defined(VGP_mips32_linux) - # define DO(n) regs->MIPS_r##n = arch->vex.guest_r##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -386,6 +386,7 @@ static void fill_prstatus(const ThreadSt - # undef DO - regs->MIPS_hi = arch->vex.guest_HI; - regs->MIPS_lo = arch->vex.guest_LO; -+ - #elif defined(VGP_mips64_linux) - # define DO(n) regs->MIPS_r##n = arch->vex.guest_r##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -395,6 +396,7 @@ static void fill_prstatus(const ThreadSt - # undef DO - regs->MIPS_hi = arch->vex.guest_HI; - regs->MIPS_lo = arch->vex.guest_LO; -+ - #else - # error Unknown ELF platform - #endif -@@ -470,6 +472,9 @@ static void fill_fpu(const ThreadState * - #elif defined(VGP_arm_linux) - // umm ... - -+#elif defined(VGP_arm64_linux) -+ I_die_here; -+ - #elif defined(VGP_s390x_linux) - # define DO(n) fpu->fprs[n].ui = arch->vex.guest_f##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -@@ -606,16 +611,13 @@ void make_elf_coredump(ThreadId tid, con - if (VG_(threads)[i].status == VgTs_Empty) - continue; - --# if defined(VGP_x86_linux) --# if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -- && !defined(VGPV_mips32_linux_android) -+# if defined(VGP_x86_linux) && !defined(VGPV_x86_linux_android) - { - vki_elf_fpxregset_t xfpu; - fill_xfpu(&VG_(threads)[i], &xfpu); - add_note(¬elist, "LINUX", NT_PRXFPREG, &xfpu, sizeof(xfpu)); - } - # endif --# endif - - fill_fpu(&VG_(threads)[i], &fpu); - # if !defined(VGPV_arm_linux_android) && !defined(VGPV_x86_linux_android) \ -Index: coregrind/m_machine.c -=================================================================== ---- coregrind/m_machine.c.orig -+++ coregrind/m_machine.c -@@ -97,6 +97,11 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/U - = VG_(threads)[tid].arch.vex.guest_R11; - regs->misc.ARM.r7 - = VG_(threads)[tid].arch.vex.guest_R7; -+# elif defined(VGA_arm64) -+ regs->r_pc = VG_(threads)[tid].arch.vex.guest_PC; -+ regs->r_sp = VG_(threads)[tid].arch.vex.guest_SP; -+ regs->misc.ARM64.x29 = VG_(threads)[tid].arch.vex.guest_X29; -+ regs->misc.ARM64.x30 = VG_(threads)[tid].arch.vex.guest_X30; - # elif defined(VGA_s390x) - regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_IA; - regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_SP; -@@ -127,38 +132,6 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/U - # endif - } - -- --void VG_(set_syscall_return_shadows) ( ThreadId tid, -- /* shadow vals for the result */ -- UWord s1res, UWord s2res, -- /* shadow vals for the error val */ -- UWord s1err, UWord s2err ) --{ --# if defined(VGP_x86_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_EAX = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_EAX = s2res; --# elif defined(VGP_amd64_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_RAX = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_RAX = s2res; --# elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_GPR3 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_GPR3 = s2res; --# elif defined(VGP_arm_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_R0 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_R0 = s2res; --# elif defined(VGO_darwin) -- // GrP fixme darwin syscalls may return more values (2 registers plus error) --# elif defined(VGP_s390x_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_r2 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_r2 = s2res; --# elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -- VG_(threads)[tid].arch.vex_shadow1.guest_r2 = s1res; -- VG_(threads)[tid].arch.vex_shadow2.guest_r2 = s2res; --# else --# error "Unknown plat" --# endif --} -- - void - VG_(get_shadow_regs_area) ( ThreadId tid, - /*DST*/UChar* dst, -@@ -339,6 +312,9 @@ static void apply_to_GPs_of_tid(ThreadId - (*f)(tid, "r29", vex->guest_r29); - (*f)(tid, "r30", vex->guest_r30); - (*f)(tid, "r31", vex->guest_r31); -+#elif defined(VGA_arm64) -+ (void)vex; /* temporarily avoid unused-var warning from gcc */ -+ I_die_here; - #else - # error Unknown arch - #endif -@@ -1193,7 +1169,7 @@ Bool VG_(machine_get_hwcaps)( void ) - - #elif defined(VGA_s390x) - --#include "libvex_s390x_common.h" -+# include "libvex_s390x_common.h" - - { - /* Instruction set detection code borrowed from ppc above. */ -@@ -1440,6 +1416,18 @@ Bool VG_(machine_get_hwcaps)( void ) - return True; - } - -+#elif defined(VGA_arm64) -+ { -+ va = VexArchARM64; -+ -+ /* So far there are no variants. */ -+ vai.hwcaps = 0; -+ -+ VG_(machine_get_cache_info)(&vai); -+ -+ return True; -+ } -+ - #elif defined(VGA_mips32) - { - va = VexArchMIPS32; -@@ -1649,6 +1637,10 @@ Int VG_(machine_get_size_of_largest_gues - assume we always do. */ - return 16; - -+# elif defined(VGA_arm64) -+ /* ARM64 always has Neon, AFAICS. */ -+ return 16; -+ - # elif defined(VGA_mips32) - /* The guest state implies 4, but that can't really be true, can - it? */ -@@ -1671,7 +1663,7 @@ void* VG_(fnptr_to_fnentry)( void* f ) - || defined(VGP_arm_linux) \ - || defined(VGP_ppc32_linux) || defined(VGO_darwin) \ - || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - return f; - # elif defined(VGP_ppc64_linux) - /* ppc64-linux uses the AIX scheme, in which f is a pointer to a -Index: coregrind/m_syscall.c -=================================================================== ---- coregrind/m_syscall.c.orig -+++ coregrind/m_syscall.c -@@ -128,6 +128,18 @@ SysRes VG_(mk_SysRes_arm_linux) ( Int va - return res; - } - -+SysRes VG_(mk_SysRes_arm64_linux) ( Long val ) { -+ SysRes res; -+ res._valEx = 0; /* unused except on mips-linux */ -+ res._isError = val >= -4095 && val <= -1; -+ if (res._isError) { -+ res._val = (ULong)(-val); -+ } else { -+ res._val = (ULong)val; -+ } -+ return res; -+} -+ - /* MIPS uses a3 != 0 to flag an error */ - SysRes VG_(mk_SysRes_mips32_linux) ( UWord v0, UWord v1, UWord a3 ) { - SysRes res; -@@ -437,6 +449,34 @@ asm( - ".previous\n" - ); - -+#elif defined(VGP_arm64_linux) -+/* I think the conventions are: -+ args in r0 r1 r2 r3 r4 r5 -+ sysno in r8 -+ return value in r0, w/ same conventions as x86-linux, viz r0 in -+ -4096 .. -1 is an error value. All other values are success -+ values. -+ -+ r0 to r5 remain unchanged, but syscall_no is in r6 and needs -+ to be moved to r8 (??) -+*/ -+extern UWord do_syscall_WRK ( -+ UWord a1, UWord a2, UWord a3, -+ UWord a4, UWord a5, UWord a6, -+ UWord syscall_no -+ ); -+asm( -+".text\n" -+".globl do_syscall_WRK\n" -+"do_syscall_WRK:\n" -+" mov x8, x6\n" -+" mov x6, 0\n" -+" mov x7, 0\n" -+" svc 0\n" -+" ret\n" -+".previous\n" -+); -+ - #elif defined(VGP_x86_darwin) - - /* Incoming args (syscall number + up to 8 args) come in on the stack -@@ -696,6 +736,10 @@ SysRes VG_(do_syscall) ( UWord sysno, UW - UWord val = do_syscall_WRK(a1,a2,a3,a4,a5,a6,sysno); - return VG_(mk_SysRes_arm_linux)( val ); - -+# elif defined(VGP_arm64_linux) -+ UWord val = do_syscall_WRK(a1,a2,a3,a4,a5,a6,sysno); -+ return VG_(mk_SysRes_arm64_linux)( val ); -+ - # elif defined(VGP_x86_darwin) - UInt wLO = 0, wHI = 0, err = 0; - ULong u64; -Index: coregrind/pub_core_mallocfree.h -=================================================================== ---- coregrind/pub_core_mallocfree.h.orig -+++ coregrind/pub_core_mallocfree.h -@@ -77,7 +77,8 @@ typedef Int ArenaId; - defined(VGP_s390x_linux) || \ - defined(VGP_mips64_linux) || \ - defined(VGP_x86_darwin) || \ -- defined(VGP_amd64_darwin) -+ defined(VGP_amd64_darwin) || \ -+ defined(VGP_arm64_linux) - # define VG_MIN_MALLOC_SZB 16 - #else - # error Unknown platform -Index: coregrind/m_debuginfo/readelf.c -=================================================================== ---- coregrind/m_debuginfo/readelf.c.orig -+++ coregrind/m_debuginfo/readelf.c -@@ -2088,7 +2088,8 @@ Bool ML_(read_elf_debug_info) ( struct _ - /* PLT is different on different platforms, it seems. */ - # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ - || defined(VGP_arm_linux) || defined (VGP_s390x_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ -+ || defined(VGP_arm64_linux) - /* Accept .plt where mapped as rx (code) */ - if (0 == VG_(strcmp)(name, ".plt")) { - if (inrx && !di->plt_present) { -Index: coregrind/m_debuginfo/debuginfo.c -=================================================================== ---- coregrind/m_debuginfo/debuginfo.c.orig -+++ coregrind/m_debuginfo/debuginfo.c -@@ -825,7 +825,8 @@ ULong VG_(di_notify_mmap)( Addr a, Bool - || defined(VGA_mips64) - is_rx_map = seg->hasR && seg->hasX; - is_rw_map = seg->hasR && seg->hasW; --# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) -+# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) \ -+ || defined(VGA_arm64) - is_rx_map = seg->hasR && seg->hasX && !seg->hasW; - is_rw_map = seg->hasR && seg->hasW && !seg->hasX; - # elif defined(VGP_s390x_linux) -@@ -2251,6 +2252,8 @@ UWord evalCfiExpr ( XArray* exprs, Int i - case Creg_IA_BP: return eec->uregs->fp; - case Creg_MIPS_RA: return eec->uregs->ra; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ I_die_here; - # else - # error "Unsupported arch" - # endif -@@ -2495,6 +2498,8 @@ static Addr compute_cfa ( D3UnwindRegs* - cfa = cfsi->cfa_off + uregs->fp; - break; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ I_die_here; - # else - # error "Unsupported arch" - # endif -@@ -2591,6 +2596,8 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindR - # elif defined(VGA_mips32) || defined(VGA_mips64) - ipHere = uregsHere->pc; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ I_die_here; - # else - # error "Unknown arch" - # endif -@@ -2671,6 +2678,8 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindR - COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi->sp_how, cfsi->sp_off); - COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi->fp_how, cfsi->fp_off); - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGP_arm64_linux) -+ I_die_here; - # else - # error "Unknown arch" - # endif -Index: coregrind/m_debuginfo/storage.c -=================================================================== ---- coregrind/m_debuginfo/storage.c.orig -+++ coregrind/m_debuginfo/storage.c -@@ -195,6 +195,8 @@ void ML_(ppDiCfSI) ( XArray* /* of CfiEx - SHOW_HOW(si->sp_how, si->sp_off); - VG_(printf)(" FP="); - SHOW_HOW(si->fp_how, si->fp_off); -+# elif defined(VGA_arm64) -+ I_die_here; - # else - # error "Unknown arch" - # endif -Index: coregrind/m_debuginfo/priv_storage.h -=================================================================== ---- coregrind/m_debuginfo/priv_storage.h.orig -+++ coregrind/m_debuginfo/priv_storage.h -@@ -277,6 +277,18 @@ typedef - Int fp_off; - } - DiCfSI; -+#elif defined(VGA_arm64) -+/* Be generic until we know more about what's needed. */ -+typedef -+ struct { -+ Addr base; -+ UInt len; -+ UChar cfa_how; /* a CFIC_ value */ -+ UChar ra_how; /* a CFIR_ value */ -+ Int cfa_off; -+ Int ra_off; -+ } -+ DiCfSI; - #else - # error "Unknown arch" - #endif -Index: coregrind/m_debuginfo/d3basics.c -=================================================================== ---- coregrind/m_debuginfo/d3basics.c.orig -+++ coregrind/m_debuginfo/d3basics.c -@@ -420,6 +420,8 @@ static Bool get_Dwarf_Reg( /*OUT*/Addr* - # elif defined(VGP_mips64_linux) - if (regno == 29) { *a = regs->sp; return True; } - if (regno == 30) { *a = regs->fp; return True; } -+# elif defined(VGP_arm64_linux) -+ I_die_here; - # else - # error "Unknown platform" - # endif -Index: coregrind/m_debuginfo/readdwarf.c -=================================================================== ---- coregrind/m_debuginfo/readdwarf.c.orig -+++ coregrind/m_debuginfo/readdwarf.c -@@ -1841,6 +1841,10 @@ void ML_(read_debuginfo_dwarf1) ( - # define FP_REG 12 - # define SP_REG 13 - # define RA_REG_DEFAULT 14 //??? -+#elif defined(VGP_arm64_linux) -+# define FP_REG 29 //??? -+# define SP_REG 31 //??? -+# define RA_REG_DEFAULT 30 //??? - #elif defined(VGP_x86_darwin) - # define FP_REG 5 - # define SP_REG 4 -@@ -2179,6 +2183,8 @@ static Bool summarise_context( /*OUT*/Di - si->cfa_how = CFIC_IA_SPREL; - # elif defined(VGA_arm) - si->cfa_how = CFIC_ARM_R13REL; -+# elif defined(VGA_arm64) -+ I_die_here; - # else - si->cfa_how = 0; /* invalid */ - # endif -@@ -2206,6 +2212,8 @@ static Bool summarise_context( /*OUT*/Di - si->cfa_how = CFIC_ARM_R7REL; - si->cfa_off = ctxs->cfa_off; - } -+# elif defined(VGA_arm64) -+ if (1) { I_die_here; } // do we need any arm64 specifics here? - # endif - else { - why = 1; -@@ -2249,6 +2257,7 @@ static Bool summarise_context( /*OUT*/Di - why = 2; goto failed; /* otherwise give up */ \ - } - -+ - # if defined(VGA_x86) || defined(VGA_amd64) - - /* --- entire tail of this fn specialised for x86/amd64 --- */ -@@ -2339,9 +2348,10 @@ static Bool summarise_context( /*OUT*/Di - - return True; - -- - # elif defined(VGA_s390x) - -+ /* --- entire tail of this fn specialised for s390 --- */ -+ - SUMMARISE_HOW(si->ra_how, si->ra_off, - ctxs->reg[ctx->ra_reg] ); - SUMMARISE_HOW(si->fp_how, si->fp_off, -@@ -2387,7 +2397,6 @@ static Bool summarise_context( /*OUT*/Di - - return True; - -- - # elif defined(VGA_mips32) || defined(VGA_mips64) - - /* --- entire tail of this fn specialised for mips --- */ -@@ -2431,9 +2440,12 @@ static Bool summarise_context( /*OUT*/Di - - return True; - -- -+# elif defined(VGA_arm64) -+ I_die_here; - - # elif defined(VGA_ppc32) || defined(VGA_ppc64) -+ /* These don't use CFI based unwinding (is that really true?) */ -+ - # else - # error "Unknown arch" - # endif -@@ -2521,6 +2533,8 @@ static Int copy_convert_CfiExpr_tree ( X - return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_BP ); - if (dwreg == srcuc->ra_reg) - return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP ); -+# elif defined(VGA_arm64) -+ I_die_here; - # elif defined(VGA_ppc32) || defined(VGA_ppc64) - # else - # error "Unknown arch" -Index: coregrind/m_stacktrace.c -=================================================================== ---- coregrind/m_stacktrace.c.orig -+++ coregrind/m_stacktrace.c -@@ -1034,6 +1034,24 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId - - #endif - -+/* ------------------------ arm64 ------------------------- */ -+ -+#if defined(VGP_arm64_linux) -+ -+UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, -+ /*OUT*/Addr* ips, UInt max_n_ips, -+ /*OUT*/Addr* sps, /*OUT*/Addr* fps, -+ UnwindStartRegs* startRegs, -+ Addr fp_max_orig ) -+{ -+ ips[0] = startRegs->r_pc; -+ if (sps) sps[0] = startRegs->r_sp; -+ if (fps) fps[0] = startRegs->misc.ARM64.x29; -+ return 1; -+} -+ -+#endif -+ - /* ------------------------ s390x ------------------------- */ - - #if defined(VGP_s390x_linux) -Index: coregrind/m_signals.c -=================================================================== ---- coregrind/m_signals.c.orig -+++ coregrind/m_signals.c -@@ -386,6 +386,19 @@ typedef struct SigQueue { - (srP)->misc.ARM.r7 = (uc)->uc_mcontext.arm_r7; \ - } - -+#elif defined(VGP_arm64_linux) -+# define VG_UCONTEXT_INSTR_PTR(uc) ((UWord)((uc)->uc_mcontext.pc)) -+# define VG_UCONTEXT_STACK_PTR(uc) ((UWord)((uc)->uc_mcontext.sp)) -+# define VG_UCONTEXT_SYSCALL_SYSRES(uc) \ -+ /* Convert the value in uc_mcontext.regs[0] into a SysRes. */ \ -+ VG_(mk_SysRes_arm64_linux)( (uc)->uc_mcontext.regs[0] ) -+# define VG_UCONTEXT_TO_UnwindStartRegs(srP, uc) \ -+ { (srP)->r_pc = (uc)->uc_mcontext.pc; \ -+ (srP)->r_sp = (uc)->uc_mcontext.sp; \ -+ (srP)->misc.ARM64.x29 = (uc)->uc_mcontext.regs[29]; \ -+ (srP)->misc.ARM64.x30 = (uc)->uc_mcontext.regs[30]; \ -+ } -+ - #elif defined(VGP_x86_darwin) - - static inline Addr VG_UCONTEXT_INSTR_PTR( void* ucV ) { -@@ -862,6 +875,15 @@ extern void my_sigreturn(void); - " svc 0x00000000\n" \ - ".previous\n" - -+#elif defined(VGP_arm64_linux) -+# define _MY_SIGRETURN(name) \ -+ ".text\n" \ -+ ".globl my_sigreturn\n" \ -+ "my_sigreturn:\n\t" \ -+ " mov x8, #" #name "\n\t" \ -+ " svc 0x0\n" \ -+ ".previous\n" -+ - #elif defined(VGP_x86_darwin) - # define _MY_SIGRETURN(name) \ - ".text\n" \ -@@ -980,8 +1002,7 @@ static void handle_SCSS_change ( Bool fo - # if !defined(VGP_ppc32_linux) && \ - !defined(VGP_x86_darwin) && !defined(VGP_amd64_darwin) && \ - !defined(VGP_mips32_linux) && !defined(VGP_mips64_linux) -- vg_assert(ksa_old.sa_restorer -- == my_sigreturn); -+ vg_assert(ksa_old.sa_restorer == my_sigreturn); - # endif - VG_(sigaddset)( &ksa_old.sa_mask, VKI_SIGKILL ); - VG_(sigaddset)( &ksa_old.sa_mask, VKI_SIGSTOP ); -Index: coregrind/pub_core_threadstate.h -=================================================================== ---- coregrind/pub_core_threadstate.h.orig -+++ coregrind/pub_core_threadstate.h -@@ -88,6 +88,8 @@ typedef - typedef VexGuestPPC64State VexGuestArchState; - #elif defined(VGA_arm) - typedef VexGuestARMState VexGuestArchState; -+#elif defined(VGA_arm64) -+ typedef VexGuestARM64State VexGuestArchState; - #elif defined(VGA_s390x) - typedef VexGuestS390XState VexGuestArchState; - #elif defined(VGA_mips32) -Index: coregrind/m_aspacemgr/aspacemgr-common.c -=================================================================== ---- coregrind/m_aspacemgr/aspacemgr-common.c.orig -+++ coregrind/m_aspacemgr/aspacemgr-common.c -@@ -152,15 +152,19 @@ SysRes VG_(am_do_mmap_NO_NOTIFY)( Addr s - { - SysRes res; - aspacem_assert(VG_IS_PAGE_ALIGNED(offset)); --# if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_arm_linux) -+ -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall6)(__NR3264_mmap, (UWord)start, length, -+ prot, flags, fd, offset); -+# elif defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -+ || defined(VGP_arm_linux) - /* mmap2 uses 4096 chunks even if actual page size is bigger. */ - aspacem_assert((offset % 4096) == 0); - res = VG_(do_syscall6)(__NR_mmap2, (UWord)start, length, - prot, flags, fd, offset / 4096); - # elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length, - prot, flags, fd, offset); - # elif defined(VGP_x86_darwin) -@@ -242,8 +246,14 @@ SysRes ML_(am_do_relocate_nooverlap_mapp - /* --- Pertaining to files --- */ - - SysRes ML_(am_open) ( const HChar* pathname, Int flags, Int mode ) --{ -+{ -+# if defined(VGP_arm64_linux) -+ /* ARM64 wants to use __NR_openat rather than __NR_open. */ -+ SysRes res = VG_(do_syscall4)(__NR_openat, -+ VKI_AT_FDCWD, (UWord)pathname, flags, mode); -+# else - SysRes res = VG_(do_syscall3)(__NR_open, (UWord)pathname, flags, mode); -+# endif - return res; - } - -@@ -261,7 +271,12 @@ void ML_(am_close) ( Int fd ) - Int ML_(am_readlink)(HChar* path, HChar* buf, UInt bufsiz) - { - SysRes res; -+# if defined(VGP_arm64_linux) -+ res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD, -+ (UWord)path, (UWord)buf, bufsiz); -+# else - res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz); -+# endif - return sr_isError(res) ? -1 : sr_Res(res); - } - -Index: coregrind/pub_core_trampoline.h -=================================================================== ---- coregrind/pub_core_trampoline.h.orig -+++ coregrind/pub_core_trampoline.h -@@ -103,6 +103,10 @@ extern UInt VG_(arm_linux_REDIR_FOR_str - extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int ); - #endif - -+#if defined(VGP_arm64_linux) -+extern Addr VG_(arm64_linux_SUBST_FOR_rt_sigreturn); -+#endif -+ - #if defined(VGP_x86_darwin) - extern Addr VG_(x86_darwin_SUBST_FOR_sigreturn); - extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* ); -Index: coregrind/m_debugger.c -=================================================================== ---- coregrind/m_debugger.c.orig -+++ coregrind/m_debugger.c -@@ -232,6 +232,47 @@ static Int ptrace_setregs(Int pid, VexGu - uregs.ARM_cpsr = LibVEX_GuestARM_get_cpsr(vex); - return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs); - -+#elif defined(VGP_arm64_linux) -+ I_die_here; -+ //ATC -+ struct vki_user_pt_regs uregs; -+ VG_(memset)(&uregs, 0, sizeof(uregs)); -+ uregs.regs[0] = vex->guest_X0; -+ uregs.regs[1] = vex->guest_X1; -+ uregs.regs[2] = vex->guest_X2; -+ uregs.regs[3] = vex->guest_X3; -+ uregs.regs[4] = vex->guest_X4; -+ uregs.regs[5] = vex->guest_X5; -+ uregs.regs[6] = vex->guest_X6; -+ uregs.regs[7] = vex->guest_X7; -+ uregs.regs[8] = vex->guest_X8; -+ uregs.regs[9] = vex->guest_X9; -+ uregs.regs[10] = vex->guest_X10; -+ uregs.regs[11] = vex->guest_X11; -+ uregs.regs[12] = vex->guest_X12; -+ uregs.regs[13] = vex->guest_X13; -+ uregs.regs[14] = vex->guest_X14; -+ uregs.regs[15] = vex->guest_X15; -+ uregs.regs[16] = vex->guest_X16; -+ uregs.regs[17] = vex->guest_X17; -+ uregs.regs[18] = vex->guest_X18; -+ uregs.regs[19] = vex->guest_X19; -+ uregs.regs[20] = vex->guest_X20; -+ uregs.regs[21] = vex->guest_X21; -+ uregs.regs[22] = vex->guest_X22; -+ uregs.regs[23] = vex->guest_X23; -+ uregs.regs[24] = vex->guest_X24; -+ uregs.regs[25] = vex->guest_X25; -+ uregs.regs[26] = vex->guest_X26; -+ uregs.regs[27] = vex->guest_X27; -+ uregs.regs[28] = vex->guest_X28; -+ uregs.regs[29] = vex->guest_X29; -+ uregs.regs[30] = vex->guest_X30; -+ uregs.sp = vex->guest_SP; -+ uregs.pc = vex->guest_PC; -+ uregs.pstate = LibVEX_GuestARM64_get_nzcv(vex); /* is this correct? */ -+ return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs); -+ - #elif defined(VGP_x86_darwin) - I_die_here; - -Index: coregrind/pub_core_transtab_asm.h -=================================================================== ---- coregrind/pub_core_transtab_asm.h.orig -+++ coregrind/pub_core_transtab_asm.h -@@ -37,10 +37,10 @@ - On x86/amd64, the cache index is computed as - 'address[VG_TT_FAST_BITS-1 : 0]'. - -- On ppc32/ppc64, the bottom two bits of instruction addresses are -- zero, which means that function causes only 1/4 of the entries to -- ever be used. So instead the function is '(address >>u -- 2)[VG_TT_FAST_BITS-1 : 0]' on those targets. -+ On ppc32/ppc64/mips32/mips64/arm64, the bottom two bits of -+ instruction addresses are zero, which means that function causes -+ only 1/4 of the entries to ever be used. So instead the function -+ is '(address >>u 2)[VG_TT_FAST_BITS-1 : 0]' on those targets. - - On ARM we shift by 1, since Thumb insns can be of size 2, hence to - minimise collisions and maximise cache utilisation we need to take -@@ -63,7 +63,7 @@ - # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK) - - #elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_mips32) \ -- || defined(VGA_mips64) -+ || defined(VGA_mips64) || defined(VGA_arm64) - # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK) - - #else -Index: coregrind/m_syswrap/syscall-arm64-linux.S -=================================================================== ---- /dev/null -+++ coregrind/m_syswrap/syscall-arm64-linux.S -@@ -0,0 +1,180 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Support for doing system calls. syscall-arm64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_vkiscnums_asm.h" -+#include "libvex_guest_offsets.h" -+ -+ -+/*----------------------------------------------------------------*/ -+/* -+ Perform a syscall for the client. This will run a syscall -+ with the client's specific per-thread signal mask. -+ -+ The structure of this function is such that, if the syscall is -+ interrupted by a signal, we can determine exactly what -+ execution state we were in with respect to the execution of -+ the syscall by examining the value of IP in the signal -+ handler. This means that we can always do the appropriate -+ thing to precisely emulate the kernel's signal/syscall -+ interactions. -+ -+ The syscall number is taken from the argument, even though it -+ should also be in guest_state->guest_X8. The syscall result -+ is written back to guest_state->guest_X0 on completion. -+ -+ Returns 0 if the syscall was successfully called (even if the -+ syscall itself failed), or a nonzero error code in the lowest -+ 8 bits if one of the sigprocmasks failed (there's no way to -+ determine which one failed). And there's no obvious way to -+ recover from that either, but nevertheless we want to know. -+ -+ VG_(fixup_guest_state_after_syscall_interrupted) does the -+ thread state fixup in the case where we were interrupted by a -+ signal. -+ -+ Prototype: -+ -+ UWord ML_(do_syscall_for_client_WRK)( -+ Int syscallno, // x0 -+ void* guest_state, // x1 -+ const vki_sigset_t *sysmask, // x2 -+ const vki_sigset_t *postmask, // x3 -+ Int nsigwords) // x4 -+*/ -+/* from vki-arm64-linux.h */ -+#define VKI_SIG_SETMASK 2 -+ -+.globl ML_(do_syscall_for_client_WRK) -+ML_(do_syscall_for_client_WRK): -+ -+ /* Stash callee-saves and our args on the stack */ -+ stp x29, x30, [sp, #-16]! -+ stp x27, x28, [sp, #-16]! -+ stp x25, x26, [sp, #-16]! -+ stp x23, x24, [sp, #-16]! -+ stp x21, x22, [sp, #-16]! -+ stp x19, x20, [sp, #-16]! -+ stp x4, x5, [sp, #-16]! -+ stp x2, x3, [sp, #-16]! -+ stp x0, x1, [sp, #-16]! -+ -+1: -+ -+ mov x8, #__NR_rt_sigprocmask -+ mov x0, #VKI_SIG_SETMASK -+ mov x1, x2 /* sysmask */ -+ mov x2, x3 /* postmask */ -+ mov x3, x4 /* nsigwords */ -+ svc 0x00000000 -+ -+ -+ ldr x5, [sp, #8] /* saved x1 == guest_state */ -+ -+ ldr x8, [sp, #0] /* saved x0 == syscall# */ -+ ldr x0, [x5, #OFFSET_arm64_X0] -+ ldr x1, [x5, #OFFSET_arm64_X1] -+ ldr x2, [x5, #OFFSET_arm64_X2] -+ ldr x3, [x5, #OFFSET_arm64_X3] -+ ldr x4, [x5, #OFFSET_arm64_X4] -+ ldr x5, [x5, #OFFSET_arm64_X5] -+ -+2: svc 0x00000000 -+3: -+ ldr x5, [sp, #8] /* saved x1 == guest_state */ -+ str x0, [x5, #OFFSET_arm64_X0] -+ -+4: -+ mov x8, #__NR_rt_sigprocmask -+ mov x0, #VKI_SIG_SETMASK -+ ldr x1, [sp, #24] /* saved x3 == postmask */ -+ mov x2, #0 -+ ldr x3, [sp, #32] /* saved x4 == nsigwords */ -+ svc 0x00000000 -+ -+ cmp x0, #0 -+ blt 7f -+ -+5: /* Success: return zero */ -+ mov x0, #0 -+ ldp xzr, x1, [sp], #16 -+ ldp x2, x3, [sp], #16 -+ ldp x4, x5, [sp], #16 -+ ldp x19, x20, [sp], #16 -+ ldp x21, x22, [sp], #16 -+ ldp x23, x24, [sp], #16 -+ ldp x25, x26, [sp], #16 -+ ldp x27, x28, [sp], #16 -+ ldp x29, x30, [sp], #16 -+ ret -+ -+7: /* Failure: return 0x8000 | error code */ -+ orr x0, x0, #0x8000 -+ ldp xzr, x1, [sp], #16 -+ ldp x2, x3, [sp], #16 -+ ldp x4, x5, [sp], #16 -+ ldp x19, x20, [sp], #16 -+ ldp x21, x22, [sp], #16 -+ ldp x23, x24, [sp], #16 -+ ldp x25, x26, [sp], #16 -+ ldp x27, x28, [sp], #16 -+ ldp x29, x30, [sp], #16 -+ ret -+ -+ -+ -+.section .rodata -+/* export the ranges so that -+ VG_(fixup_guest_state_after_syscall_interrupted) can do the -+ right thing */ -+ -+.globl ML_(blksys_setup) -+.globl ML_(blksys_restart) -+.globl ML_(blksys_complete) -+.globl ML_(blksys_committed) -+.globl ML_(blksys_finished) -+ML_(blksys_setup): .quad 1b -+ML_(blksys_restart): .quad 2b -+ML_(blksys_complete): .quad 3b -+ML_(blksys_committed): .quad 4b -+ML_(blksys_finished): .quad 5b -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",%progbits -+ -+.previous -+ -+#endif // defined(VGP_arm_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_syswrap/syswrap-main.c -=================================================================== ---- coregrind/m_syswrap/syswrap-main.c.orig -+++ coregrind/m_syswrap/syswrap-main.c -@@ -70,6 +70,7 @@ - arm r7 r0 r1 r2 r3 r4 r5 n/a n/a r0 (== ARG1) - mips32 v0 a0 a1 a2 a3 stack stack n/a n/a v0 (== NUM) - mips64 v0 a0 a1 a2 a3 a4 a5 a6 a7 v0 (== NUM) -+ arm64 x8 x0 x1 x2 x3 x4 x5 n/a n/a x0 ?? (== ARG1??) - - On s390x the svc instruction is used for system calls. The system call - number is encoded in the instruction (8 bit immediate field). Since Linux -@@ -464,6 +465,18 @@ void getSyscallArgsFromGuestState ( /*OU - canonical->arg7 = 0; - canonical->arg8 = 0; - -+#elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ canonical->sysno = gst->guest_X8; -+ canonical->arg1 = gst->guest_X0; -+ canonical->arg2 = gst->guest_X1; -+ canonical->arg3 = gst->guest_X2; -+ canonical->arg4 = gst->guest_X3; -+ canonical->arg5 = gst->guest_X4; -+ canonical->arg6 = gst->guest_X5; -+ canonical->arg7 = 0; -+ canonical->arg8 = 0; -+ - #elif defined(VGP_mips32_linux) - VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla; - canonical->sysno = gst->guest_r2; // v0 -@@ -694,6 +707,16 @@ void putSyscallArgsIntoGuestState ( /*IN - gst->guest_R4 = canonical->arg5; - gst->guest_R5 = canonical->arg6; - -+#elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ gst->guest_X8 = canonical->sysno; -+ gst->guest_X0 = canonical->arg1; -+ gst->guest_X1 = canonical->arg2; -+ gst->guest_X2 = canonical->arg3; -+ gst->guest_X3 = canonical->arg4; -+ gst->guest_X4 = canonical->arg5; -+ gst->guest_X5 = canonical->arg6; -+ - #elif defined(VGP_x86_darwin) - VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; - UWord *stack = (UWord *)gst->guest_ESP; -@@ -746,8 +769,8 @@ void putSyscallArgsIntoGuestState ( /*IN - gst->guest_r5 = canonical->arg2; - gst->guest_r6 = canonical->arg3; - gst->guest_r7 = canonical->arg4; -- *((UInt*) (gst->guest_r29 + 16)) = canonical->arg5; // 16(guest_GPR29/sp) -- *((UInt*) (gst->guest_r29 + 20)) = canonical->arg6; // 20(sp) -+ *((UInt*) (gst->guest_r29 + 16)) = canonical->arg5; // 16(guest_GPR29/sp) -+ *((UInt*) (gst->guest_r29 + 20)) = canonical->arg6; // 20(sp) - } else { - canonical->arg8 = 0; - gst->guest_r2 = __NR_syscall; -@@ -755,9 +778,9 @@ void putSyscallArgsIntoGuestState ( /*IN - gst->guest_r5 = canonical->arg1; - gst->guest_r6 = canonical->arg2; - gst->guest_r7 = canonical->arg3; -- *((UInt*) (gst->guest_r29 + 16)) = canonical->arg4; // 16(guest_GPR29/sp) -- *((UInt*) (gst->guest_r29 + 20)) = canonical->arg5; // 20(sp) -- *((UInt*) (gst->guest_r29 + 24)) = canonical->arg6; // 24(sp) -+ *((UInt*) (gst->guest_r29 + 16)) = canonical->arg4; // 16(guest_GPR29/sp) -+ *((UInt*) (gst->guest_r29 + 20)) = canonical->arg5; // 20(sp) -+ *((UInt*) (gst->guest_r29 + 24)) = canonical->arg6; // 24(sp) - } - - #elif defined(VGP_mips64_linux) -@@ -807,6 +830,11 @@ void getSyscallStatusFromGuestState ( /* - canonical->sres = VG_(mk_SysRes_arm_linux)( gst->guest_R0 ); - canonical->what = SsComplete; - -+# elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ canonical->sres = VG_(mk_SysRes_arm64_linux)( gst->guest_X0 ); -+ canonical->what = SsComplete; -+ - # elif defined(VGP_mips32_linux) - VexGuestMIPS32State* gst = (VexGuestMIPS32State*)gst_vanilla; - UInt v0 = gst->guest_r2; // v0 -@@ -980,6 +1008,20 @@ void putSyscallStatusIntoGuestState ( /* - VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, - OFFSET_arm_R0, sizeof(UWord) ); - -+# elif defined(VGP_arm64_linux) -+ VexGuestARM64State* gst = (VexGuestARM64State*)gst_vanilla; -+ vg_assert(canonical->what == SsComplete); -+ if (sr_isError(canonical->sres)) { -+ /* This isn't exactly right, in that really a Failure with res -+ not in the range 1 .. 4095 is unrepresentable in the -+ Linux-arm64 scheme. Oh well. */ -+ gst->guest_X0 = - (Long)sr_Err(canonical->sres); -+ } else { -+ gst->guest_X0 = sr_Res(canonical->sres); -+ } -+ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, -+ OFFSET_arm64_X0, sizeof(UWord) ); -+ - #elif defined(VGP_x86_darwin) - VexGuestX86State* gst = (VexGuestX86State*)gst_vanilla; - SysRes sres = canonical->sres; -@@ -1104,6 +1146,8 @@ void putSyscallStatusIntoGuestState ( /* - static - void getSyscallArgLayout ( /*OUT*/SyscallArgLayout* layout ) - { -+ VG_(bzero_inline)(layout, sizeof(*layout)); -+ - #if defined(VGP_x86_linux) - layout->o_sysno = OFFSET_x86_EAX; - layout->o_arg1 = OFFSET_x86_EBX; -@@ -1159,6 +1203,17 @@ void getSyscallArgLayout ( /*OUT*/Syscal - layout->uu_arg7 = -1; /* impossible value */ - layout->uu_arg8 = -1; /* impossible value */ - -+#elif defined(VGP_arm64_linux) -+ layout->o_sysno = OFFSET_arm64_X8; -+ layout->o_arg1 = OFFSET_arm64_X0; -+ layout->o_arg2 = OFFSET_arm64_X1; -+ layout->o_arg3 = OFFSET_arm64_X2; -+ layout->o_arg4 = OFFSET_arm64_X3; -+ layout->o_arg5 = OFFSET_arm64_X4; -+ layout->o_arg6 = OFFSET_arm64_X5; -+ layout->uu_arg7 = -1; /* impossible value */ -+ layout->uu_arg8 = -1; /* impossible value */ -+ - #elif defined(VGP_mips32_linux) - layout->o_sysno = OFFSET_mips32_r2; - layout->o_arg1 = OFFSET_mips32_r4; -@@ -1990,6 +2045,10 @@ void ML_(fixup_guest_state_to_restart_sy - vg_assert(valid); - } - -+#elif defined(VGP_arm64_linux) -+ // probably simplest to copy the ppc version -+ I_die_here; -+ - #elif defined(VGP_x86_darwin) - arch->vex.guest_EIP = arch->vex.guest_IP_AT_SYSCALL; - -Index: coregrind/m_syswrap/syswrap-arm64-linux.c -=================================================================== ---- /dev/null -+++ coregrind/m_syswrap/syswrap-arm64-linux.c -@@ -0,0 +1,1341 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Platform-specific syscalls stuff. syswrap-arm64-linux.c -----*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics.h" -+#include "pub_core_vki.h" -+#include "pub_core_vkiscnums.h" -+#include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy -+#include "pub_core_threadstate.h" -+#include "pub_core_aspacemgr.h" -+//ZZ #include "pub_core_debuglog.h" -+//ZZ #include "pub_core_libcbase.h" -+#include "pub_core_libcassert.h" -+#include "pub_core_libcprint.h" -+//ZZ #include "pub_core_libcproc.h" -+//ZZ #include "pub_core_libcsignal.h" -+#include "pub_core_options.h" -+//ZZ #include "pub_core_scheduler.h" -+#include "pub_core_sigframe.h" // For VG_(sigframe_destroy)() -+//ZZ #include "pub_core_signals.h" -+#include "pub_core_syscall.h" -+#include "pub_core_syswrap.h" -+#include "pub_core_tooliface.h" -+//ZZ #include "pub_core_stacks.h" // VG_(register_stack) -+//ZZ #include "pub_core_transtab.h" // VG_(discard_translations) -+ -+#include "priv_types_n_macros.h" -+#include "priv_syswrap-generic.h" /* for decls of generic wrappers */ -+#include "priv_syswrap-linux.h" /* for decls of linux-ish wrappers */ -+//ZZ #include "priv_syswrap-main.h" -+ -+ -+/* --------------------------------------------------------------------- -+ clone() handling -+ ------------------------------------------------------------------ */ -+ -+/* Call f(arg1), but first switch stacks, using 'stack' as the new -+ stack, and use 'retaddr' as f's return-to address. Also, clear all -+ the integer registers before entering f.*/ -+__attribute__((noreturn)) -+void ML_(call_on_new_stack_0_1) ( Addr stack, -+ Addr retaddr, -+ void (*f)(Word), -+ Word arg1 ); -+// r0 = stack -+// r1 = retaddr -+// r2 = f -+// r3 = arg1 -+asm( -+".text\n" -+".globl vgModuleLocal_call_on_new_stack_0_1\n" -+"vgModuleLocal_call_on_new_stack_0_1:\n" -+" mov sp, x0\n\t" /* Stack pointer */ -+" mov x30, x1\n\t" /* Return address (x30 is LR) */ -+" mov x0, x3\n\t" /* First argument */ -+" mov x9, x2\n\t" /* 'f': x9 won't be zeroed at start of f. Oh well. */ -+" mov x1, #0\n\t" /* Clear our GPRs */ -+" mov x2, #0\n\t" -+" mov x3, #0\n\t" -+" mov x4, #0\n\t" -+" mov x5, #0\n\t" -+" mov x6, #0\n\t" -+" mov x7, #0\n\t" -+" mov x8, #0\n\t" -+/* don't zero out x9 */ -+" mov x10, #0\n\t" -+" mov x11, #0\n\t" -+" mov x12, #0\n\t" -+" mov x13, #0\n\t" -+" mov x14, #0\n\t" -+" mov x15, #0\n\t" -+" mov x16, #0\n\t" -+" mov x17, #0\n\t" -+" mov x18, #0\n\t" -+" mov x19, #0\n\t" -+" mov x20, #0\n\t" -+" mov x21, #0\n\t" -+" mov x22, #0\n\t" -+" mov x23, #0\n\t" -+" mov x24, #0\n\t" -+" mov x25, #0\n\t" -+" mov x26, #0\n\t" -+" mov x27, #0\n\t" -+" mov x28, #0\n\t" -+" mov x29, sp\n\t" /* FP = SP, in the absence of better suggestions */ -+" br x9\n\t" -+".previous\n" -+); -+ -+ -+//ZZ #define __NR_CLONE VG_STRINGIFY(__NR_clone) -+//ZZ #define __NR_EXIT VG_STRINGIFY(__NR_exit) -+//ZZ -+//ZZ extern -+//ZZ ULong do_syscall_clone_arm_linux ( Word (*fn)(void *), -+//ZZ void* stack, -+//ZZ Int flags, -+//ZZ void* arg, -+//ZZ Int* child_tid, -+//ZZ Int* parent_tid, -+//ZZ void* tls ); -+//ZZ asm( -+//ZZ ".text\n" -+//ZZ ".globl do_syscall_clone_arm_linux\n" -+//ZZ "do_syscall_clone_arm_linux:\n" -+//ZZ -+//ZZ /*Setup child stack */ -+//ZZ " str r0, [r1, #-4]!\n" -+//ZZ " str r3, [r1, #-4]!\n" -+//ZZ " push {r4,r7}\n" -+//ZZ " mov r0, r2\n" /* arg1: flags */ -+//ZZ /* r1 (arg2) is already our child's stack */ -+//ZZ " ldr r2, [sp, #12]\n" // parent tid -+//ZZ " ldr r3, [sp, #16]\n" // tls -+//ZZ " ldr r4, [sp, #8]\n" // Child tid -+//ZZ " mov r7, #"__NR_CLONE"\n" -+//ZZ " svc 0x00000000\n" -+//ZZ " cmp r0, #0\n" -+//ZZ " beq 1f\n" -+//ZZ -+//ZZ /* Parent */ -+//ZZ " pop {r4,r7}\n" -+//ZZ " bx lr\n" -+//ZZ -+//ZZ "1:\n" /*child*/ -+//ZZ " mov lr, pc\n" -+//ZZ " pop {r0,pc}\n" -+//ZZ /* Retval from child is already in r0 */ -+//ZZ " mov r7, #"__NR_EXIT"\n" -+//ZZ " svc 0x00000000\n" -+//ZZ /* Urh.. why did exit return? */ -+//ZZ " .long 0\n" -+//ZZ " .previous\n" -+//ZZ ); -+//ZZ -+//ZZ #undef __NR_CLONE -+//ZZ #undef __NR_EXIT -+//ZZ -+//ZZ // forward declarations -+//ZZ static void setup_child ( ThreadArchState*, ThreadArchState* ); -+//ZZ static void assign_guest_tls(ThreadId ctid, Addr tlsptr); -+//ZZ static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ); -+//ZZ -+//ZZ /* -+//ZZ When a client clones, we need to keep track of the new thread. This means: -+//ZZ 1. allocate a ThreadId+ThreadState+stack for the the thread -+//ZZ -+//ZZ 2. initialize the thread's new VCPU state -+//ZZ -+//ZZ 3. create the thread using the same args as the client requested, -+//ZZ but using the scheduler entrypoint for IP, and a separate stack -+//ZZ for SP. -+//ZZ */ -+//ZZ static SysRes do_clone ( ThreadId ptid, -+//ZZ UInt flags, Addr sp, -+//ZZ Int *parent_tidptr, -+//ZZ Int *child_tidptr, -+//ZZ Addr child_tls) -+//ZZ { -+//ZZ const Bool debug = False; -+//ZZ -+//ZZ ThreadId ctid = VG_(alloc_ThreadState)(); -+//ZZ ThreadState* ptst = VG_(get_ThreadState)(ptid); -+//ZZ ThreadState* ctst = VG_(get_ThreadState)(ctid); -+//ZZ UInt r0; -+//ZZ UWord *stack; -+//ZZ NSegment const* seg; -+//ZZ SysRes res; -+//ZZ vki_sigset_t blockall, savedmask; -+//ZZ -+//ZZ VG_(sigfillset)(&blockall); -+//ZZ -+//ZZ vg_assert(VG_(is_running_thread)(ptid)); -+//ZZ vg_assert(VG_(is_valid_tid)(ctid)); -+//ZZ -+//ZZ stack = (UWord*)ML_(allocstack)(ctid); -+//ZZ -+//ZZ if(stack == NULL) { -+//ZZ res = VG_(mk_SysRes_Error)( VKI_ENOMEM ); -+//ZZ goto out; -+//ZZ } -+//ZZ -+//ZZ setup_child( &ctst->arch, &ptst->arch ); -+//ZZ -+//ZZ ctst->arch.vex.guest_R0 = 0; -+//ZZ if(sp != 0) -+//ZZ ctst->arch.vex.guest_R13 = sp; -+//ZZ -+//ZZ ctst->os_state.parent = ptid; -+//ZZ -+//ZZ ctst->sig_mask = ptst->sig_mask; -+//ZZ ctst->tmp_sig_mask = ptst->sig_mask; -+//ZZ -+//ZZ /* Start the child with its threadgroup being the same as the -+//ZZ parent's. This is so that any exit_group calls that happen -+//ZZ after the child is created but before it sets its -+//ZZ os_state.threadgroup field for real (in thread_wrapper in -+//ZZ syswrap-linux.c), really kill the new thread. a.k.a this avoids -+//ZZ a race condition in which the thread is unkillable (via -+//ZZ exit_group) because its threadgroup is not set. The race window -+//ZZ is probably only a few hundred or a few thousand cycles long. -+//ZZ See #226116. */ -+//ZZ ctst->os_state.threadgroup = ptst->os_state.threadgroup; -+//ZZ -+//ZZ seg = VG_(am_find_nsegment)((Addr)sp); -+//ZZ if (seg && seg->kind != SkResvn) { -+//ZZ ctst->client_stack_highest_word = (Addr)VG_PGROUNDUP(sp); -+//ZZ ctst->client_stack_szB = ctst->client_stack_highest_word - seg->start; -+//ZZ -+//ZZ VG_(register_stack)(seg->start, ctst->client_stack_highest_word); -+//ZZ -+//ZZ if (debug) -+//ZZ VG_(printf)("tid %d: guessed client stack range %#lx-%#lx\n", -+//ZZ ctid, seg->start, VG_PGROUNDUP(sp)); -+//ZZ } else { -+//ZZ VG_(message)(Vg_UserMsg, "!? New thread %d starts with sp+%#lx) unmapped\n", ctid, sp); -+//ZZ ctst->client_stack_szB = 0; -+//ZZ } -+//ZZ -+//ZZ vg_assert(VG_(owns_BigLock_LL)(ptid)); -+//ZZ VG_TRACK ( pre_thread_ll_create, ptid, ctid ); -+//ZZ -+//ZZ if (flags & VKI_CLONE_SETTLS) { -+//ZZ /* Just assign the tls pointer in the guest TPIDRURO. */ -+//ZZ assign_guest_tls(ctid, child_tls); -+//ZZ } -+//ZZ -+//ZZ flags &= ~VKI_CLONE_SETTLS; -+//ZZ -+//ZZ VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, &savedmask); -+//ZZ -+//ZZ r0 = do_syscall_clone_arm_linux( -+//ZZ ML_(start_thread_NORETURN), stack, flags, &VG_(threads)[ctid], -+//ZZ child_tidptr, parent_tidptr, NULL -+//ZZ ); -+//ZZ //VG_(printf)("AFTER SYSCALL, %x and %x CHILD: %d PARENT: %d\n",child_tidptr, parent_tidptr,*child_tidptr,*parent_tidptr); -+//ZZ -+//ZZ res = VG_(mk_SysRes_arm_linux)( r0 ); -+//ZZ -+//ZZ VG_(sigprocmask)(VKI_SIG_SETMASK, &savedmask, NULL); -+//ZZ -+//ZZ out: -+//ZZ if (sr_isError(res)) { -+//ZZ VG_(cleanup_thread)(&ctst->arch); -+//ZZ ctst->status = VgTs_Empty; -+//ZZ VG_TRACK( pre_thread_ll_exit, ctid ); -+//ZZ } -+//ZZ -+//ZZ return res; -+//ZZ } -+ -+ -+ -+/* --------------------------------------------------------------------- -+ More thread stuff -+ ------------------------------------------------------------------ */ -+ -+// ARM64 doesn't have any architecture specific thread stuff that -+// needs to be cleaned up -+void VG_(cleanup_thread) ( ThreadArchState* arch ) -+{ -+} -+ -+//ZZ void setup_child ( /*OUT*/ ThreadArchState *child, -+//ZZ /*IN*/ ThreadArchState *parent ) -+//ZZ { -+//ZZ child->vex = parent->vex; -+//ZZ child->vex_shadow1 = parent->vex_shadow1; -+//ZZ child->vex_shadow2 = parent->vex_shadow2; -+//ZZ } -+//ZZ -+//ZZ static void assign_guest_tls(ThreadId tid, Addr tlsptr) -+//ZZ { -+//ZZ VG_(threads)[tid].arch.vex.guest_TPIDRURO = tlsptr; -+//ZZ } -+//ZZ -+//ZZ /* Assigns tlsptr to the guest TPIDRURO. -+//ZZ If needed for the specific hardware, really executes -+//ZZ the set_tls syscall. -+//ZZ */ -+//ZZ static SysRes sys_set_tls ( ThreadId tid, Addr tlsptr ) -+//ZZ { -+//ZZ assign_guest_tls(tid, tlsptr); -+//ZZ #if defined(ANDROID_HARDWARE_emulator) -+//ZZ /* Android emulator does not provide an hw tls register. -+//ZZ So, the tls register is emulated by the kernel. -+//ZZ This emulated value is set by the __NR_ARM_set_tls syscall. -+//ZZ The emulated value must be read by the kernel helper function -+//ZZ located at 0xffff0fe0. -+//ZZ -+//ZZ The emulated tlsptr is located at 0xffff0ff0 -+//ZZ (so slightly after the kernel helper function). -+//ZZ Note that applications are not supposed to read this directly. -+//ZZ -+//ZZ For compatibility : if there is a hw tls register, the kernel -+//ZZ will put at 0xffff0fe0 the instructions to read it, so -+//ZZ as to have old applications calling the kernel helper -+//ZZ working properly. -+//ZZ -+//ZZ For having emulated guest TLS working correctly with -+//ZZ Valgrind, it is needed to execute the syscall to set -+//ZZ the emulated TLS value in addition to the assignment -+//ZZ of TPIDRURO. -+//ZZ -+//ZZ Note: the below means that if we need thread local storage -+//ZZ for Valgrind host, then there will be a conflict between -+//ZZ the need of the guest tls and of the host tls. -+//ZZ If all the guest code would cleanly call 0xffff0fe0, -+//ZZ then we might maybe intercept this. However, at least -+//ZZ __libc_preinit reads directly 0xffff0ff0. -+//ZZ */ -+//ZZ /* ??? might call the below if auxv->u.a_val & VKI_HWCAP_TLS ??? -+//ZZ Unclear if real hardware having tls hw register sets -+//ZZ VKI_HWCAP_TLS. */ -+//ZZ return VG_(do_syscall1) (__NR_ARM_set_tls, tlsptr); -+//ZZ #else -+//ZZ return VG_(mk_SysRes_Success)( 0 ); -+//ZZ #endif -+//ZZ } -+ -+/* --------------------------------------------------------------------- -+ PRE/POST wrappers for arm/Linux-specific syscalls -+ ------------------------------------------------------------------ */ -+ -+#define PRE(name) DEFN_PRE_TEMPLATE(arm64_linux, name) -+#define POST(name) DEFN_POST_TEMPLATE(arm64_linux, name) -+ -+//ZZ /* Add prototypes for the wrappers declared here, so that gcc doesn't -+//ZZ harass us for not having prototypes. Really this is a kludge -- -+//ZZ the right thing to do is to make these wrappers 'static' since they -+//ZZ aren't visible outside this file, but that requires even more macro -+//ZZ magic. */ -+//ZZ -+DECL_TEMPLATE(arm64_linux, sys_mmap); -+//ZZ DECL_TEMPLATE(arm_linux, sys_stat64); -+//ZZ DECL_TEMPLATE(arm_linux, sys_lstat64); -+//ZZ DECL_TEMPLATE(arm_linux, sys_fstatat64); -+//ZZ DECL_TEMPLATE(arm_linux, sys_fstat64); -+DECL_TEMPLATE(arm64_linux, sys_clone); -+//ZZ DECL_TEMPLATE(arm_linux, sys_sigreturn); -+DECL_TEMPLATE(arm64_linux, sys_rt_sigreturn); -+//ZZ DECL_TEMPLATE(arm_linux, sys_sigsuspend); -+//ZZ DECL_TEMPLATE(arm_linux, sys_set_tls); -+//ZZ DECL_TEMPLATE(arm_linux, sys_cacheflush); -+//ZZ DECL_TEMPLATE(arm_linux, sys_ptrace); -+//ZZ -+//ZZ PRE(sys_mmap2) -+//ZZ { -+//ZZ SysRes r; -+//ZZ -+//ZZ // Exactly like old_mmap() except: -+//ZZ // - all 6 args are passed in regs, rather than in a memory-block. -+//ZZ // - the file offset is specified in pagesize units rather than bytes, -+//ZZ // so that it can be used for files bigger than 2^32 bytes. -+//ZZ // pagesize or 4K-size units in offset? For ppc32/64-linux, this is -+//ZZ // 4K-sized. Assert that the page size is 4K here for safety. -+//ZZ vg_assert(VKI_PAGE_SIZE == 4096); -+//ZZ PRINT("sys_mmap2 ( %#lx, %llu, %ld, %ld, %ld, %ld )", -+//ZZ ARG1, (ULong)ARG2, ARG3, ARG4, ARG5, ARG6 ); -+//ZZ PRE_REG_READ6(long, "mmap2", -+//ZZ unsigned long, start, unsigned long, length, -+//ZZ unsigned long, prot, unsigned long, flags, -+//ZZ unsigned long, fd, unsigned long, offset); -+//ZZ -+//ZZ r = ML_(generic_PRE_sys_mmap)( tid, ARG1, ARG2, ARG3, ARG4, ARG5, -+//ZZ 4096 * (Off64T)ARG6 ); -+//ZZ SET_STATUS_from_SysRes(r); -+//ZZ } -+ -+// ARM64 FIXME is this correct? -+PRE(sys_mmap) -+{ -+ SysRes r; -+ -+ PRINT("sys_mmap ( %#lx, %llu, %ld, %ld, %d, %ld )", -+ ARG1, (ULong)ARG2, ARG3, ARG4, (Int)ARG5, ARG6 ); -+ PRE_REG_READ6(long, "mmap", -+ unsigned long, start, unsigned long, length, -+ unsigned long, prot, unsigned long, flags, -+ unsigned long, fd, unsigned long, offset); -+ -+ r = ML_(generic_PRE_sys_mmap)( tid, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6 ); -+ SET_STATUS_from_SysRes(r); -+} -+ -+//ZZ -+//ZZ // XXX: lstat64/fstat64/stat64 are generic, but not necessarily -+//ZZ // applicable to every architecture -- I think only to 32-bit archs. -+//ZZ // We're going to need something like linux/core_os32.h for such -+//ZZ // things, eventually, I think. --njn -+//ZZ PRE(sys_lstat64) -+//ZZ { -+//ZZ PRINT("sys_lstat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); -+//ZZ PRE_REG_READ2(long, "lstat64", char *, file_name, struct stat64 *, buf); -+//ZZ PRE_MEM_RASCIIZ( "lstat64(file_name)", ARG1 ); -+//ZZ PRE_MEM_WRITE( "lstat64(buf)", ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_lstat64) -+//ZZ { -+//ZZ vg_assert(SUCCESS); -+//ZZ if (RES == 0) { -+//ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ PRE(sys_stat64) -+//ZZ { -+//ZZ PRINT("sys_stat64 ( %#lx(%s), %#lx )",ARG1,(char*)ARG1,ARG2); -+//ZZ PRE_REG_READ2(long, "stat64", char *, file_name, struct stat64 *, buf); -+//ZZ PRE_MEM_RASCIIZ( "stat64(file_name)", ARG1 ); -+//ZZ PRE_MEM_WRITE( "stat64(buf)", ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_stat64) -+//ZZ { -+//ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ PRE(sys_fstatat64) -+//ZZ { -+//ZZ PRINT("sys_fstatat64 ( %ld, %#lx(%s), %#lx )",ARG1,ARG2,(char*)ARG2,ARG3); -+//ZZ PRE_REG_READ3(long, "fstatat64", -+//ZZ int, dfd, char *, file_name, struct stat64 *, buf); -+//ZZ PRE_MEM_RASCIIZ( "fstatat64(file_name)", ARG2 ); -+//ZZ PRE_MEM_WRITE( "fstatat64(buf)", ARG3, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_fstatat64) -+//ZZ { -+//ZZ POST_MEM_WRITE( ARG3, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ PRE(sys_fstat64) -+//ZZ { -+//ZZ PRINT("sys_fstat64 ( %ld, %#lx )",ARG1,ARG2); -+//ZZ PRE_REG_READ2(long, "fstat64", unsigned long, fd, struct stat64 *, buf); -+//ZZ PRE_MEM_WRITE( "fstat64(buf)", ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+//ZZ -+//ZZ POST(sys_fstat64) -+//ZZ { -+//ZZ POST_MEM_WRITE( ARG2, sizeof(struct vki_stat64) ); -+//ZZ } -+ -+PRE(sys_clone) -+{ -+ UInt cloneflags; -+ -+ PRINT("sys_clone ( %lx, %#lx, %#lx, %#lx, %#lx )",ARG1,ARG2,ARG3,ARG4,ARG5); -+ PRE_REG_READ5(int, "clone", -+ unsigned long, flags, -+ void *, child_stack, -+ int *, parent_tidptr, -+ void *, child_tls, -+ int *, child_tidptr); -+ -+ if (ARG1 & VKI_CLONE_PARENT_SETTID) { -+ PRE_MEM_WRITE("clone(parent_tidptr)", ARG3, sizeof(Int)); -+ if (!VG_(am_is_valid_for_client)(ARG3, sizeof(Int), -+ VKI_PROT_WRITE)) { -+ SET_STATUS_Failure( VKI_EFAULT ); -+ return; -+ } -+ } -+ if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) { -+ PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int)); -+ if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int), -+ VKI_PROT_WRITE)) { -+ SET_STATUS_Failure( VKI_EFAULT ); -+ return; -+ } -+ } -+//ZZ if (ARG1 & VKI_CLONE_SETTLS) { -+//ZZ PRE_MEM_READ("clone(tls_user_desc)", ARG4, sizeof(vki_modify_ldt_t)); -+//ZZ if (!VG_(am_is_valid_for_client)(ARG4, sizeof(vki_modify_ldt_t), -+//ZZ VKI_PROT_READ)) { -+//ZZ SET_STATUS_Failure( VKI_EFAULT ); -+//ZZ return; -+//ZZ } -+//ZZ } -+ -+ cloneflags = ARG1; -+ -+ if (!ML_(client_signal_OK)(ARG1 & VKI_CSIGNAL)) { -+ SET_STATUS_Failure( VKI_EINVAL ); -+ return; -+ } -+ -+ /* Only look at the flags we really care about */ -+ switch (cloneflags & (VKI_CLONE_VM | VKI_CLONE_FS -+ | VKI_CLONE_FILES | VKI_CLONE_VFORK)) { -+//ZZ case VKI_CLONE_VM | VKI_CLONE_FS | VKI_CLONE_FILES: -+//ZZ /* thread creation */ -+//ZZ SET_STATUS_from_SysRes( -+//ZZ do_clone(tid, -+//ZZ ARG1, /* flags */ -+//ZZ (Addr)ARG2, /* child ESP */ -+//ZZ (Int *)ARG3, /* parent_tidptr */ -+//ZZ (Int *)ARG5, /* child_tidptr */ -+//ZZ (Addr)ARG4)); /* set_tls */ -+//ZZ break; -+ -+ case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ -+ /* FALLTHROUGH - assume vfork == fork */ -+ cloneflags &= ~(VKI_CLONE_VFORK | VKI_CLONE_VM); -+ -+ case 0: /* plain fork */ -+ SET_STATUS_from_SysRes( -+ ML_(do_fork_clone)(tid, -+ cloneflags, /* flags */ -+ (Int *)ARG3, /* parent_tidptr */ -+ (Int *)ARG5)); /* child_tidptr */ -+ break; -+ -+ default: -+ /* should we just ENOSYS? */ -+ VG_(message)(Vg_UserMsg, ""); -+ VG_(message)(Vg_UserMsg, "Unsupported clone() flags: 0x%lx", ARG1); -+ VG_(message)(Vg_UserMsg, ""); -+ VG_(message)(Vg_UserMsg, "The only supported clone() uses are:"); -+ VG_(message)(Vg_UserMsg, " - via a threads library (LinuxThreads or NPTL)"); -+ VG_(message)(Vg_UserMsg, " - via the implementation of fork or vfork"); -+ VG_(message)(Vg_UserMsg, " - for the Quadrics Elan3 user-space driver"); -+ VG_(unimplemented) -+ ("Valgrind does not support general clone()."); -+ } -+ -+ if (SUCCESS) { -+ if (ARG1 & VKI_CLONE_PARENT_SETTID) -+ POST_MEM_WRITE(ARG3, sizeof(Int)); -+ if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) -+ POST_MEM_WRITE(ARG5, sizeof(Int)); -+ -+ /* Thread creation was successful; let the child have the chance -+ to run */ -+ *flags |= SfYieldAfter; -+ } -+} -+ -+//ZZ PRE(sys_sigreturn) -+//ZZ { -+//ZZ /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -+//ZZ an explanation of what follows. */ -+//ZZ -+//ZZ PRINT("sys_sigreturn ( )"); -+//ZZ -+//ZZ vg_assert(VG_(is_valid_tid)(tid)); -+//ZZ vg_assert(tid >= 1 && tid < VG_N_THREADS); -+//ZZ vg_assert(VG_(is_running_thread)(tid)); -+//ZZ -+//ZZ /* Restore register state from frame and remove it */ -+//ZZ VG_(sigframe_destroy)(tid, False); -+//ZZ -+//ZZ /* Tell the driver not to update the guest state with the "result", -+//ZZ and set a bogus result to keep it happy. */ -+//ZZ *flags |= SfNoWriteResult; -+//ZZ SET_STATUS_Success(0); -+//ZZ -+//ZZ /* Check to see if any signals arose as a result of this. */ -+//ZZ *flags |= SfPollAfter; -+//ZZ } -+ -+PRE(sys_rt_sigreturn) -+{ -+ /* See comments on PRE(sys_rt_sigreturn) in syswrap-amd64-linux.c for -+ an explanation of what follows. */ -+ -+ PRINT("rt_sigreturn ( )"); -+ -+ vg_assert(VG_(is_valid_tid)(tid)); -+ vg_assert(tid >= 1 && tid < VG_N_THREADS); -+ vg_assert(VG_(is_running_thread)(tid)); -+ -+ /* Restore register state from frame and remove it */ -+ VG_(sigframe_destroy)(tid, True); -+ -+ /* Tell the driver not to update the guest state with the "result", -+ and set a bogus result to keep it happy. */ -+ *flags |= SfNoWriteResult; -+ SET_STATUS_Success(0); -+ -+ /* Check to see if any signals arose as a result of this. */ -+ *flags |= SfPollAfter; -+} -+ -+//ZZ /* NB: clone of x86-linux version, and ppc32-linux has an almost -+//ZZ identical one. */ -+//ZZ PRE(sys_sigsuspend) -+//ZZ { -+//ZZ /* The C library interface to sigsuspend just takes a pointer to -+//ZZ a signal mask but this system call has three arguments - the first -+//ZZ two don't appear to be used by the kernel and are always passed as -+//ZZ zero by glibc and the third is the first word of the signal mask -+//ZZ so only 32 signals are supported. -+//ZZ -+//ZZ In fact glibc normally uses rt_sigsuspend if it is available as -+//ZZ that takes a pointer to the signal mask so supports more signals. -+//ZZ */ -+//ZZ *flags |= SfMayBlock; -+//ZZ PRINT("sys_sigsuspend ( %ld, %ld, %ld )", ARG1,ARG2,ARG3 ); -+//ZZ PRE_REG_READ3(int, "sigsuspend", -+//ZZ int, history0, int, history1, -+//ZZ vki_old_sigset_t, mask); -+//ZZ } -+//ZZ -+//ZZ /* Very much ARM specific */ -+//ZZ -+//ZZ PRE(sys_set_tls) -+//ZZ { -+//ZZ PRINT("set_tls (%lx)",ARG1); -+//ZZ PRE_REG_READ1(long, "set_tls", unsigned long, addr); -+//ZZ -+//ZZ SET_STATUS_from_SysRes( sys_set_tls( tid, ARG1 ) ); -+//ZZ } -+//ZZ -+//ZZ PRE(sys_cacheflush) -+//ZZ { -+//ZZ PRINT("cacheflush (%lx, %#lx, %#lx)",ARG1,ARG2,ARG3); -+//ZZ PRE_REG_READ3(long, "cacheflush", void*, addrlow,void*, addrhigh,int, flags); -+//ZZ VG_(discard_translations)( (Addr64)ARG1, -+//ZZ ((ULong)ARG2) - ((ULong)ARG1) + 1ULL/*paranoia*/, -+//ZZ "PRE(sys_cacheflush)" ); -+//ZZ SET_STATUS_Success(0); -+//ZZ } -+//ZZ -+//ZZ // ARG3 is only used for pointers into the traced process's address -+//ZZ // space and for offsets into the traced process's struct -+//ZZ // user_regs_struct. It is never a pointer into this process's memory -+//ZZ // space, and we should therefore not check anything it points to. -+//ZZ PRE(sys_ptrace) -+//ZZ { -+//ZZ PRINT("sys_ptrace ( %ld, %ld, %#lx, %#lx )", ARG1,ARG2,ARG3,ARG4); -+//ZZ PRE_REG_READ4(int, "ptrace", -+//ZZ long, request, long, pid, long, addr, long, data); -+//ZZ switch (ARG1) { -+//ZZ case VKI_PTRACE_PEEKTEXT: -+//ZZ case VKI_PTRACE_PEEKDATA: -+//ZZ case VKI_PTRACE_PEEKUSR: -+//ZZ PRE_MEM_WRITE( "ptrace(peek)", ARG4, -+//ZZ sizeof (long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getregs)", ARG4, -+//ZZ sizeof (struct vki_user_regs_struct)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETFPREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_fp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETWMMXREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getwmmxregs)", ARG4, -+//ZZ VKI_IWMMXT_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETCRUNCHREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getcrunchregs)", ARG4, -+//ZZ VKI_CRUNCH_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETVFPREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(getvfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_vfp) ); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETHBPREGS: -+//ZZ PRE_MEM_WRITE( "ptrace(gethbpregs)", ARG4, -+//ZZ sizeof (unsigned long) ); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETREGS: -+//ZZ PRE_MEM_READ( "ptrace(setregs)", ARG4, -+//ZZ sizeof (struct vki_user_regs_struct)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETFPREGS: -+//ZZ PRE_MEM_READ( "ptrace(setfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_fp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETWMMXREGS: -+//ZZ PRE_MEM_READ( "ptrace(setwmmxregs)", ARG4, -+//ZZ VKI_IWMMXT_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETCRUNCHREGS: -+//ZZ PRE_MEM_READ( "ptrace(setcrunchregs)", ARG4, -+//ZZ VKI_CRUNCH_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETVFPREGS: -+//ZZ PRE_MEM_READ( "ptrace(setvfpregs)", ARG4, -+//ZZ sizeof (struct vki_user_vfp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETHBPREGS: -+//ZZ PRE_MEM_READ( "ptrace(sethbpregs)", ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GET_THREAD_AREA: -+//ZZ PRE_MEM_WRITE( "ptrace(get_thread_area)", ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETEVENTMSG: -+//ZZ PRE_MEM_WRITE( "ptrace(geteventmsg)", ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETSIGINFO: -+//ZZ PRE_MEM_WRITE( "ptrace(getsiginfo)", ARG4, sizeof(vki_siginfo_t)); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETSIGINFO: -+//ZZ PRE_MEM_READ( "ptrace(setsiginfo)", ARG4, sizeof(vki_siginfo_t)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGSET: -+//ZZ ML_(linux_PRE_getregset)(tid, ARG3, ARG4); -+//ZZ break; -+//ZZ case VKI_PTRACE_SETREGSET: -+//ZZ ML_(linux_PRE_setregset)(tid, ARG3, ARG4); -+//ZZ break; -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ POST(sys_ptrace) -+//ZZ { -+//ZZ switch (ARG1) { -+//ZZ case VKI_PTRACE_PEEKTEXT: -+//ZZ case VKI_PTRACE_PEEKDATA: -+//ZZ case VKI_PTRACE_PEEKUSR: -+//ZZ POST_MEM_WRITE( ARG4, sizeof (long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGS: -+//ZZ POST_MEM_WRITE( ARG4, sizeof (struct vki_user_regs_struct)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETFPREGS: -+//ZZ POST_MEM_WRITE( ARG4, sizeof (struct vki_user_fp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETWMMXREGS: -+//ZZ POST_MEM_WRITE( ARG4, VKI_IWMMXT_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETCRUNCHREGS: -+//ZZ POST_MEM_WRITE( ARG4, VKI_CRUNCH_SIZE); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETVFPREGS: -+//ZZ POST_MEM_WRITE( ARG4, sizeof(struct vki_user_vfp)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GET_THREAD_AREA: -+//ZZ case VKI_PTRACE_GETHBPREGS: -+//ZZ case VKI_PTRACE_GETEVENTMSG: -+//ZZ POST_MEM_WRITE( ARG4, sizeof(unsigned long)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETSIGINFO: -+//ZZ /* XXX: This is a simplification. Different parts of the -+//ZZ * siginfo_t are valid depending on the type of signal. -+//ZZ */ -+//ZZ POST_MEM_WRITE( ARG4, sizeof(vki_siginfo_t)); -+//ZZ break; -+//ZZ case VKI_PTRACE_GETREGSET: -+//ZZ ML_(linux_POST_getregset)(tid, ARG3, ARG4); -+//ZZ break; -+//ZZ default: -+//ZZ break; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ #undef PRE -+//ZZ #undef POST -+ -+/* --------------------------------------------------------------------- -+ The arm64/Linux syscall table -+ ------------------------------------------------------------------ */ -+ -+//ZZ #if 0 -+//ZZ #define __NR_OABI_SYSCALL_BASE 0x900000 -+//ZZ #else -+//ZZ #define __NR_OABI_SYSCALL_BASE 0x0 -+//ZZ #endif -+ -+#define PLAX_(sysno, name) WRAPPER_ENTRY_X_(arm64_linux, sysno, name) -+#define PLAXY(sysno, name) WRAPPER_ENTRY_XY(arm64_linux, sysno, name) -+ -+// This table maps from __NR_xxx syscall numbers (from -+// linux/include/asm-arm/unistd.h) to the appropriate PRE/POST sys_foo() -+// wrappers on arm64 (as per sys_call_table in linux/arch/arm/kernel/entry.S). -+// -+// For those syscalls not handled by Valgrind, the annotation indicate its -+// arch/OS combination, eg. */* (generic), */Linux (Linux only), ?/? -+// (unknown). -+ -+static SyscallTableEntry syscall_main_table[] = { -+ LINXY(__NR_getxattr, sys_getxattr), // 8 -+ LINXY(__NR_lgetxattr, sys_lgetxattr), // 9 -+ GENXY(__NR_getcwd, sys_getcwd), // 17 -+ LINXY(__NR_dup3, sys_dup3), // 24 -+ -+ // FIXME IS THIS CORRECT? -+ LINXY(__NR3264_fcntl, sys_fcntl), // 25 -+ -+ LINXY(__NR_ioctl, sys_ioctl), // 29 -+ LINX_(__NR_mkdirat, sys_mkdirat), // 34 -+ LINX_(__NR_unlinkat, sys_unlinkat), // 35 -+ -+ // FIXME IS THIS CORRECT? it may well not be. -+ GENXY(__NR3264_statfs, sys_statfs), // 43 -+ -+ LINX_(__NR_faccessat, sys_faccessat), // 48 -+ GENX_(__NR_chdir, sys_chdir), // 49 -+ LINXY(__NR_openat, sys_openat), // 56 -+ GENXY(__NR_close, sys_close), // 57 -+ LINXY(__NR_pipe2, sys_pipe2), // 59 -+ GENXY(__NR_getdents64, sys_getdents64), // 61 -+ -+ // FIXME IS THIS CORRECT? -+ LINX_(__NR3264_lseek, sys_lseek), // 62 -+ -+ GENXY(__NR_read, sys_read), // 63 -+ GENX_(__NR_write, sys_write), // 64 -+ GENX_(__NR_writev, sys_writev), // 66 -+ -+ LINX_(__NR_readlinkat, sys_readlinkat), // 78 -+ -+ // FIXME IS THIS CORRECT? -+ LINXY(__NR3264_fstatat, sys_newfstatat), // 79 -+ GENXY(__NR3264_fstat, sys_newfstat), // 80 -+ -+ LINX_(__NR_exit_group, sys_exit_group), // 94 -+ LINX_(__NR_set_tid_address, sys_set_tid_address), // 96 -+ LINXY(__NR_futex, sys_futex), // 98 -+ LINX_(__NR_set_robust_list, sys_set_robust_list), // 99 -+ LINXY(__NR_clock_gettime, sys_clock_gettime), // 113 -+ LINX_(__NR_tgkill, sys_tgkill), // 131 */Linux -+ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 134 -+ LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 135 -+ PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139 -+ GENX_(__NR_getpgid, sys_getpgid), // 155 -+ GENXY(__NR_uname, sys_newuname), // 160 -+ GENXY(__NR_getrlimit, sys_old_getrlimit), // 163 -+ GENXY(__NR_getrusage, sys_getrusage), // 165 -+ GENXY(__NR_gettimeofday, sys_gettimeofday), // 169 -+ GENX_(__NR_getpid, sys_getpid), // 172 -+ GENX_(__NR_getppid, sys_getppid), // 173 -+ GENX_(__NR_getuid, sys_getuid), // 174 -+ GENX_(__NR_geteuid, sys_geteuid), // 175 -+ GENX_(__NR_getgid, sys_getgid), // 176 -+ GENX_(__NR_getegid, sys_getegid), // 177 -+ LINX_(__NR_gettid, sys_gettid), // 178 -+ LINXY(__NR_socket, sys_socket), // 198 -+ LINX_(__NR_connect, sys_connect), // 203 -+ GENX_(__NR_brk, sys_brk), // 214 -+ GENXY(__NR_munmap, sys_munmap), // 215 -+ PLAX_(__NR_clone, sys_clone), // 220 -+ GENX_(__NR_execve, sys_execve), // 221 -+ -+ // FIXME IS THIS CORRECT? -+ PLAX_(__NR3264_mmap, sys_mmap), // 222 -+ -+ GENXY(__NR_mprotect, sys_mprotect), // 226 -+ GENXY(__NR_wait4, sys_wait4), // 260 -+ -+// The numbers below are bogus. (See comment further down.) -+// When pulling entries above this line, change the numbers -+// to be correct. -+ -+//ZZ GENX_(__NR_exit, sys_exit), // 93 -+//ZZ //zz // (restart_syscall) // 0 -+//ZZ GENX_(__NR_fork, sys_fork), // 2 -+//ZZ -+//ZZ GENXY(__NR_open, sys_open), // 5 -+//ZZ // GENXY(__NR_waitpid, sys_waitpid), // 7 -+//ZZ GENXY(__NR_creat, sys_creat), // 8 -+//ZZ GENX_(__NR_link, sys_link), // 9 -+//ZZ -+//ZZ GENX_(__NR_unlink, sys_unlink), // 10 -+//ZZ GENXY(__NR_time, sys_time), // 13 -+//ZZ GENX_(__NR_mknod, sys_mknod), // 14 -+//ZZ -+//ZZ GENX_(__NR_chmod, sys_chmod), // 15 -+//ZZ //zz LINX_(__NR_lchown, sys_lchown16), // 16 -+//ZZ // GENX_(__NR_break, sys_ni_syscall), // 17 -+//ZZ //zz // (__NR_oldstat, sys_stat), // 18 (obsolete) -+//ZZ LINX_(__NR_lseek, sys_lseek), // 19 -+//ZZ -+//ZZ GENX_(__NR_getpid, sys_getpid), // 20 -+//ZZ LINX_(__NR_mount, sys_mount), // 21 -+//ZZ LINX_(__NR_umount, sys_oldumount), // 22 -+//ZZ LINX_(__NR_setuid, sys_setuid16), // 23 ## P -+//ZZ LINX_(__NR_getuid, sys_getuid16), // 24 ## P -+//ZZ //zz -+//ZZ //zz // (__NR_stime, sys_stime), // 25 * (SVr4,SVID,X/OPEN) -+//ZZ PLAXY(__NR_ptrace, sys_ptrace), // 26 -+//ZZ GENX_(__NR_alarm, sys_alarm), // 27 -+//ZZ //zz // (__NR_oldfstat, sys_fstat), // 28 * L -- obsolete -+//ZZ GENX_(__NR_pause, sys_pause), // 29 -+//ZZ -+//ZZ LINX_(__NR_utime, sys_utime), // 30 -+//ZZ // GENX_(__NR_stty, sys_ni_syscall), // 31 -+//ZZ // GENX_(__NR_gtty, sys_ni_syscall), // 32 -+//ZZ GENX_(__NR_access, sys_access), // 33 -+//ZZ GENX_(__NR_nice, sys_nice), // 34 -+//ZZ -+//ZZ // GENX_(__NR_ftime, sys_ni_syscall), // 35 -+//ZZ GENX_(__NR_sync, sys_sync), // 36 -+//ZZ GENX_(__NR_kill, sys_kill), // 37 -+//ZZ GENX_(__NR_rename, sys_rename), // 38 -+//ZZ GENX_(__NR_mkdir, sys_mkdir), // 39 -+//ZZ -+//ZZ GENX_(__NR_rmdir, sys_rmdir), // 40 -+//ZZ GENXY(__NR_dup, sys_dup), // 41 -+//ZZ LINXY(__NR_pipe, sys_pipe), // 42 -+//ZZ GENXY(__NR_times, sys_times), // 43 -+//ZZ // GENX_(__NR_prof, sys_ni_syscall), // 44 -+ -+//ZZ LINX_(__NR_setgid, sys_setgid16), // 46 -+//ZZ LINX_(__NR_getgid, sys_getgid16), // 47 -+//ZZ //zz // (__NR_signal, sys_signal), // 48 */* (ANSI C) -+//ZZ LINX_(__NR_geteuid, sys_geteuid16), // 49 -+//ZZ -+//ZZ LINX_(__NR_getegid, sys_getegid16), // 50 -+//ZZ GENX_(__NR_acct, sys_acct), // 51 -+//ZZ LINX_(__NR_umount2, sys_umount), // 52 -+//ZZ // GENX_(__NR_lock, sys_ni_syscall), // 53 -+//ZZ -+//ZZ LINXY(__NR_fcntl, sys_fcntl), // 55 -+//ZZ // GENX_(__NR_mpx, sys_ni_syscall), // 56 -+//ZZ GENX_(__NR_setpgid, sys_setpgid), // 57 -+//ZZ // GENX_(__NR_ulimit, sys_ni_syscall), // 58 -+//ZZ //zz // (__NR_oldolduname, sys_olduname), // 59 Linux -- obsolete -+//ZZ //zz -+//ZZ GENX_(__NR_umask, sys_umask), // 60 -+//ZZ GENX_(__NR_chroot, sys_chroot), // 61 -+//ZZ //zz // (__NR_ustat, sys_ustat) // 62 SVr4 -- deprecated -+//ZZ GENXY(__NR_dup2, sys_dup2), // 63 -+//ZZ GENX_(__NR_getppid, sys_getppid), // 64 -+//ZZ -+//ZZ GENX_(__NR_getpgrp, sys_getpgrp), // 65 -+//ZZ GENX_(__NR_setsid, sys_setsid), // 66 -+//ZZ LINXY(__NR_sigaction, sys_sigaction), // 67 -+//ZZ //zz // (__NR_sgetmask, sys_sgetmask), // 68 */* (ANSI C) -+//ZZ //zz // (__NR_ssetmask, sys_ssetmask), // 69 */* (ANSI C) -+//ZZ //zz -+//ZZ LINX_(__NR_setreuid, sys_setreuid16), // 70 -+//ZZ LINX_(__NR_setregid, sys_setregid16), // 71 -+//ZZ PLAX_(__NR_sigsuspend, sys_sigsuspend), // 72 -+//ZZ LINXY(__NR_sigpending, sys_sigpending), // 73 -+//ZZ //zz // (__NR_sethostname, sys_sethostname), // 74 */* -+//ZZ //zz -+//ZZ GENX_(__NR_setrlimit, sys_setrlimit), // 75 -+//ZZ GENXY(__NR_getrlimit, sys_old_getrlimit), // 76 -+//ZZ GENX_(__NR_settimeofday, sys_settimeofday), // 79 -+//ZZ -+//ZZ LINXY(__NR_getgroups, sys_getgroups16), // 80 -+//ZZ LINX_(__NR_setgroups, sys_setgroups16), // 81 -+//ZZ // PLAX_(__NR_select, old_select), // 82 -+//ZZ GENX_(__NR_symlink, sys_symlink), // 83 -+//ZZ //zz // (__NR_oldlstat, sys_lstat), // 84 -- obsolete -+//ZZ //zz -+//ZZ GENX_(__NR_readlink, sys_readlink), // 85 -+//ZZ //zz // (__NR_uselib, sys_uselib), // 86 */Linux -+//ZZ //zz // (__NR_swapon, sys_swapon), // 87 */Linux -+//ZZ //zz // (__NR_reboot, sys_reboot), // 88 */Linux -+//ZZ //zz // (__NR_readdir, old_readdir), // 89 -- superseded -+//ZZ //zz -+//ZZ // _____(__NR_mmap, old_mmap), // 90 -+//ZZ GENXY(__NR_munmap, sys_munmap), // 91 -+//ZZ GENX_(__NR_truncate, sys_truncate), // 92 -+//ZZ GENX_(__NR_ftruncate, sys_ftruncate), // 93 -+//ZZ GENX_(__NR_fchmod, sys_fchmod), // 94 -+//ZZ -+//ZZ LINX_(__NR_fchown, sys_fchown16), // 95 -+//ZZ GENX_(__NR_getpriority, sys_getpriority), // 96 -+//ZZ GENX_(__NR_setpriority, sys_setpriority), // 97 -+//ZZ // GENX_(__NR_profil, sys_ni_syscall), // 98 -+//ZZ GENXY(__NR_statfs, sys_statfs), // 99 -+//ZZ -+//ZZ GENXY(__NR_fstatfs, sys_fstatfs), // 100 -+//ZZ // LINX_(__NR_ioperm, sys_ioperm), // 101 -+//ZZ LINXY(__NR_socketcall, sys_socketcall), // 102 -+//ZZ LINXY(__NR_syslog, sys_syslog), // 103 -+//ZZ GENXY(__NR_setitimer, sys_setitimer), // 104 -+//ZZ -+//ZZ GENXY(__NR_getitimer, sys_getitimer), // 105 -+//ZZ GENXY(__NR_stat, sys_newstat), // 106 -+//ZZ GENXY(__NR_lstat, sys_newlstat), // 107 -+//ZZ GENXY(__NR_fstat, sys_newfstat), // 108 -+//ZZ //zz // (__NR_olduname, sys_uname), // 109 -- obsolete -+//ZZ //zz -+//ZZ // GENX_(__NR_iopl, sys_iopl), // 110 -+//ZZ LINX_(__NR_vhangup, sys_vhangup), // 111 -+//ZZ // GENX_(__NR_idle, sys_ni_syscall), // 112 -+//ZZ // PLAXY(__NR_vm86old, sys_vm86old), // 113 __NR_syscall... weird -+//ZZ //zz -+//ZZ //zz // (__NR_swapoff, sys_swapoff), // 115 */Linux -+//ZZ LINXY(__NR_sysinfo, sys_sysinfo), // 116 -+//ZZ // _____(__NR_ipc, sys_ipc), // 117 -+//ZZ GENX_(__NR_fsync, sys_fsync), // 118 -+//ZZ PLAX_(__NR_sigreturn, sys_sigreturn), // 119 ?/Linux -+//ZZ -+//ZZ //zz // (__NR_setdomainname, sys_setdomainname), // 121 */*(?) -+//ZZ // PLAX_(__NR_modify_ldt, sys_modify_ldt), // 123 -+//ZZ //zz LINXY(__NR_adjtimex, sys_adjtimex), // 124 -+//ZZ //zz -+//ZZ LINXY(__NR_sigprocmask, sys_sigprocmask), // 126 -+//ZZ //zz // Nb: create_module() was removed 2.4-->2.6 -+//ZZ // GENX_(__NR_create_module, sys_ni_syscall), // 127 -+//ZZ LINX_(__NR_init_module, sys_init_module), // 128 -+//ZZ LINX_(__NR_delete_module, sys_delete_module), // 129 -+//ZZ //zz -+//ZZ //zz // Nb: get_kernel_syms() was removed 2.4-->2.6 -+//ZZ // GENX_(__NR_get_kernel_syms, sys_ni_syscall), // 130 -+//ZZ LINX_(__NR_quotactl, sys_quotactl), // 131 -+//ZZ GENX_(__NR_getpgid, sys_getpgid), // 132 -+//ZZ GENX_(__NR_fchdir, sys_fchdir), // 133 -+//ZZ //zz // (__NR_bdflush, sys_bdflush), // 134 */Linux -+//ZZ //zz -+//ZZ //zz // (__NR_sysfs, sys_sysfs), // 135 SVr4 -+//ZZ LINX_(__NR_personality, sys_personality), // 136 -+//ZZ // GENX_(__NR_afs_syscall, sys_ni_syscall), // 137 -+//ZZ LINX_(__NR_setfsuid, sys_setfsuid16), // 138 -+//ZZ LINX_(__NR_setfsgid, sys_setfsgid16), // 139 -+//ZZ -+//ZZ LINXY(__NR__llseek, sys_llseek), // 140 -+//ZZ GENXY(__NR_getdents, sys_getdents), // 141 -+//ZZ GENX_(__NR__newselect, sys_select), // 142 -+//ZZ GENX_(__NR_flock, sys_flock), // 143 -+//ZZ GENX_(__NR_msync, sys_msync), // 144 -+//ZZ -+//ZZ GENXY(__NR_readv, sys_readv), // 145 -+//ZZ GENX_(__NR_getsid, sys_getsid), // 147 -+//ZZ GENX_(__NR_fdatasync, sys_fdatasync), // 148 -+//ZZ LINXY(__NR__sysctl, sys_sysctl), // 149 -+//ZZ -+//ZZ GENX_(__NR_mlock, sys_mlock), // 150 -+//ZZ GENX_(__NR_munlock, sys_munlock), // 151 -+//ZZ GENX_(__NR_mlockall, sys_mlockall), // 152 -+//ZZ LINX_(__NR_munlockall, sys_munlockall), // 153 -+//ZZ LINXY(__NR_sched_setparam, sys_sched_setparam), // 154 -+//ZZ -+//ZZ LINXY(__NR_sched_getparam, sys_sched_getparam), // 155 -+//ZZ LINX_(__NR_sched_setscheduler, sys_sched_setscheduler), // 156 -+//ZZ LINX_(__NR_sched_getscheduler, sys_sched_getscheduler), // 157 -+//ZZ LINX_(__NR_sched_yield, sys_sched_yield), // 158 -+//ZZ LINX_(__NR_sched_get_priority_max, sys_sched_get_priority_max),// 159 -+//ZZ -+//ZZ LINX_(__NR_sched_get_priority_min, sys_sched_get_priority_min),// 160 -+//ZZ //zz //LINX?(__NR_sched_rr_get_interval, sys_sched_rr_get_interval), // 161 */* -+//ZZ GENXY(__NR_nanosleep, sys_nanosleep), // 162 -+//ZZ GENX_(__NR_mremap, sys_mremap), // 163 -+//ZZ LINX_(__NR_setresuid, sys_setresuid16), // 164 -+//ZZ -+//ZZ LINXY(__NR_getresuid, sys_getresuid16), // 165 -+//ZZ // PLAXY(__NR_vm86, sys_vm86), // 166 x86/Linux-only -+//ZZ // GENX_(__NR_query_module, sys_ni_syscall), // 167 -+//ZZ GENXY(__NR_poll, sys_poll), // 168 -+//ZZ //zz // (__NR_nfsservctl, sys_nfsservctl), // 169 */Linux -+//ZZ //zz -+//ZZ LINX_(__NR_setresgid, sys_setresgid16), // 170 -+//ZZ LINXY(__NR_getresgid, sys_getresgid16), // 171 -+//ZZ LINXY(__NR_prctl, sys_prctl), // 172 -+//ZZ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 174 -+//ZZ -+//ZZ LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 176 -+//ZZ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait),// 177 -+//ZZ LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo),// 178 -+//ZZ LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 179 -+//ZZ -+//ZZ GENXY(__NR_pread64, sys_pread64), // 180 -+//ZZ GENX_(__NR_pwrite64, sys_pwrite64), // 181 -+//ZZ LINX_(__NR_chown, sys_chown16), // 182 -+//ZZ LINXY(__NR_capget, sys_capget), // 184 -+//ZZ -+//ZZ LINX_(__NR_capset, sys_capset), // 185 -+//ZZ GENXY(__NR_sigaltstack, sys_sigaltstack), // 186 -+//ZZ LINXY(__NR_sendfile, sys_sendfile), // 187 -+//ZZ // GENXY(__NR_getpmsg, sys_getpmsg), // 188 -+//ZZ // GENX_(__NR_putpmsg, sys_putpmsg), // 189 -+//ZZ -+//ZZ // Nb: we treat vfork as fork -+//ZZ GENX_(__NR_vfork, sys_fork), // 190 -+//ZZ GENXY(__NR_ugetrlimit, sys_getrlimit), // 191 -+//ZZ GENX_(__NR_truncate64, sys_truncate64), // 193 -+//ZZ GENX_(__NR_ftruncate64, sys_ftruncate64), // 194 -+//ZZ -+//ZZ PLAXY(__NR_stat64, sys_stat64), // 195 -+//ZZ PLAXY(__NR_lstat64, sys_lstat64), // 196 -+//ZZ PLAXY(__NR_fstat64, sys_fstat64), // 197 -+//ZZ GENX_(__NR_lchown32, sys_lchown), // 198 -+//ZZ GENX_(__NR_getuid32, sys_getuid), // 199 -+//ZZ -+//ZZ GENX_(__NR_getgid32, sys_getgid), // 200 -+//ZZ GENX_(__NR_geteuid32, sys_geteuid), // 201 -+//ZZ GENX_(__NR_getegid32, sys_getegid), // 202 -+//ZZ GENX_(__NR_setreuid32, sys_setreuid), // 203 -+//ZZ GENX_(__NR_setregid32, sys_setregid), // 204 -+//ZZ -+//ZZ GENXY(__NR_getgroups32, sys_getgroups), // 205 -+//ZZ GENX_(__NR_setgroups32, sys_setgroups), // 206 -+//ZZ GENX_(__NR_fchown32, sys_fchown), // 207 -+//ZZ LINX_(__NR_setresuid32, sys_setresuid), // 208 -+//ZZ LINXY(__NR_getresuid32, sys_getresuid), // 209 -+//ZZ -+//ZZ LINX_(__NR_setresgid32, sys_setresgid), // 210 -+//ZZ LINXY(__NR_getresgid32, sys_getresgid), // 211 -+//ZZ GENX_(__NR_chown32, sys_chown), // 212 -+//ZZ GENX_(__NR_setuid32, sys_setuid), // 213 -+//ZZ GENX_(__NR_setgid32, sys_setgid), // 214 -+//ZZ -+//ZZ LINX_(__NR_setfsuid32, sys_setfsuid), // 215 -+//ZZ LINX_(__NR_setfsgid32, sys_setfsgid), // 216 -+//ZZ //zz // (__NR_pivot_root, sys_pivot_root), // 217 */Linux -+//ZZ GENXY(__NR_mincore, sys_mincore), // 218 -+//ZZ GENX_(__NR_madvise, sys_madvise), // 219 -+//ZZ -+//ZZ LINXY(__NR_fcntl64, sys_fcntl64), // 221 -+//ZZ // GENX_(222, sys_ni_syscall), // 222 -+//ZZ // PLAXY(223, sys_syscall223), // 223 // sys_bproc? -+//ZZ -+//ZZ LINX_(__NR_readahead, sys_readahead), // 225 */Linux -+//ZZ LINX_(__NR_setxattr, sys_setxattr), // 226 -+//ZZ LINX_(__NR_lsetxattr, sys_lsetxattr), // 227 -+//ZZ LINX_(__NR_fsetxattr, sys_fsetxattr), // 228 -+//ZZ -+//ZZ LINXY(__NR_fgetxattr, sys_fgetxattr), // 231 -+//ZZ LINXY(__NR_listxattr, sys_listxattr), // 232 -+//ZZ LINXY(__NR_llistxattr, sys_llistxattr), // 233 -+//ZZ LINXY(__NR_flistxattr, sys_flistxattr), // 234 -+//ZZ -+//ZZ LINX_(__NR_removexattr, sys_removexattr), // 235 -+//ZZ LINX_(__NR_lremovexattr, sys_lremovexattr), // 236 -+//ZZ LINX_(__NR_fremovexattr, sys_fremovexattr), // 237 -+//ZZ LINXY(__NR_tkill, sys_tkill), // 238 */Linux -+//ZZ LINXY(__NR_sendfile64, sys_sendfile64), // 239 -+//ZZ -+//ZZ LINXY(__NR_futex, sys_futex), // 240 -+//ZZ LINX_(__NR_sched_setaffinity, sys_sched_setaffinity), // 241 -+//ZZ LINXY(__NR_sched_getaffinity, sys_sched_getaffinity), // 242 -+//ZZ // PLAX_(__NR_set_thread_area, sys_set_thread_area), // 243 -+//ZZ // PLAX_(__NR_get_thread_area, sys_get_thread_area), // 244 -+//ZZ -+//ZZ LINXY(__NR_io_setup, sys_io_setup), // 245 -+//ZZ LINX_(__NR_io_destroy, sys_io_destroy), // 246 -+//ZZ LINXY(__NR_io_getevents, sys_io_getevents), // 247 -+//ZZ LINX_(__NR_io_submit, sys_io_submit), // 248 -+//ZZ LINXY(__NR_io_cancel, sys_io_cancel), // 249 -+//ZZ -+//ZZ // LINX_(__NR_fadvise64, sys_fadvise64), // 250 */(Linux?) -+//ZZ GENX_(251, sys_ni_syscall), // 251 -+//ZZ // GENXY(__NR_lookup_dcookie, sys_lookup_dcookie), // 253 -+//ZZ LINXY(__NR_epoll_create, sys_epoll_create), // 254 -+//ZZ -+//ZZ LINX_(__NR_epoll_ctl, sys_epoll_ctl), // 255 -+//ZZ LINXY(__NR_epoll_wait, sys_epoll_wait), // 256 -+//ZZ //zz // (__NR_remap_file_pages, sys_remap_file_pages), // 257 */Linux -+//ZZ LINX_(__NR_set_tid_address, sys_set_tid_address), // 258 -+//ZZ LINXY(__NR_timer_create, sys_timer_create), // 259 -+//ZZ -+//ZZ LINXY(__NR_timer_settime, sys_timer_settime), // (timer_create+1) -+//ZZ LINXY(__NR_timer_gettime, sys_timer_gettime), // (timer_create+2) -+//ZZ LINX_(__NR_timer_getoverrun, sys_timer_getoverrun),//(timer_create+3) -+//ZZ LINX_(__NR_timer_delete, sys_timer_delete), // (timer_create+4) -+//ZZ LINX_(__NR_clock_settime, sys_clock_settime), // (timer_create+5) -+//ZZ -+//ZZ LINXY(__NR_clock_getres, sys_clock_getres), // (timer_create+7) -+//ZZ LINXY(__NR_clock_nanosleep, sys_clock_nanosleep),// (timer_create+8) */* -+//ZZ GENXY(__NR_statfs64, sys_statfs64), // 268 -+//ZZ GENXY(__NR_fstatfs64, sys_fstatfs64), // 269 -+//ZZ -+//ZZ GENX_(__NR_utimes, sys_utimes), // 271 -+//ZZ // LINX_(__NR_fadvise64_64, sys_fadvise64_64), // 272 */(Linux?) -+//ZZ GENX_(__NR_vserver, sys_ni_syscall), // 273 -+//ZZ LINX_(__NR_mbind, sys_mbind), // 274 ?/? -+//ZZ -+//ZZ LINXY(__NR_get_mempolicy, sys_get_mempolicy), // 275 ?/? -+//ZZ LINX_(__NR_set_mempolicy, sys_set_mempolicy), // 276 ?/? -+//ZZ LINXY(__NR_mq_open, sys_mq_open), // 277 -+//ZZ LINX_(__NR_mq_unlink, sys_mq_unlink), // (mq_open+1) -+//ZZ LINX_(__NR_mq_timedsend, sys_mq_timedsend), // (mq_open+2) -+//ZZ -+//ZZ LINXY(__NR_mq_timedreceive, sys_mq_timedreceive),// (mq_open+3) -+//ZZ LINX_(__NR_mq_notify, sys_mq_notify), // (mq_open+4) -+//ZZ LINXY(__NR_mq_getsetattr, sys_mq_getsetattr), // (mq_open+5) -+//ZZ LINXY(__NR_waitid, sys_waitid), // 280 -+//ZZ -+//ZZ LINX_(__NR_bind, sys_bind), // 282 -+//ZZ LINX_(__NR_listen, sys_listen), // 284 -+//ZZ LINXY(__NR_accept, sys_accept), // 285 -+//ZZ LINXY(__NR_getsockname, sys_getsockname), // 286 -+//ZZ LINXY(__NR_getpeername, sys_getpeername), // 287 -+//ZZ LINXY(__NR_socketpair, sys_socketpair), // 288 -+//ZZ LINX_(__NR_send, sys_send), -+//ZZ LINX_(__NR_sendto, sys_sendto), // 290 -+//ZZ LINXY(__NR_recv, sys_recv), -+//ZZ LINXY(__NR_recvfrom, sys_recvfrom), // 292 -+//ZZ LINX_(__NR_shutdown, sys_shutdown), // 293 -+//ZZ LINX_(__NR_setsockopt, sys_setsockopt), // 294 -+//ZZ LINXY(__NR_getsockopt, sys_getsockopt), // 295 -+//ZZ LINX_(__NR_sendmsg, sys_sendmsg), // 296 -+//ZZ LINXY(__NR_recvmsg, sys_recvmsg), // 297 -+//ZZ LINX_(__NR_semop, sys_semop), // 298 -+//ZZ LINX_(__NR_semget, sys_semget), // 299 -+//ZZ LINXY(__NR_semctl, sys_semctl), // 300 -+//ZZ LINX_(__NR_msgget, sys_msgget), -+//ZZ LINX_(__NR_msgsnd, sys_msgsnd), -+//ZZ LINXY(__NR_msgrcv, sys_msgrcv), -+//ZZ LINXY(__NR_msgctl, sys_msgctl), // 304 -+//ZZ LINX_(__NR_semtimedop, sys_semtimedop), // 312 -+//ZZ -+//ZZ LINX_(__NR_add_key, sys_add_key), // 286 -+//ZZ LINX_(__NR_request_key, sys_request_key), // 287 -+//ZZ LINXY(__NR_keyctl, sys_keyctl), // not 288... -+//ZZ // LINX_(__NR_ioprio_set, sys_ioprio_set), // 289 -+//ZZ -+//ZZ // LINX_(__NR_ioprio_get, sys_ioprio_get), // 290 -+//ZZ LINX_(__NR_inotify_init, sys_inotify_init), // 291 -+//ZZ LINX_(__NR_inotify_add_watch, sys_inotify_add_watch), // 292 -+//ZZ LINX_(__NR_inotify_rm_watch, sys_inotify_rm_watch), // 293 -+//ZZ // LINX_(__NR_migrate_pages, sys_migrate_pages), // 294 -+//ZZ -+//ZZ LINX_(__NR_mknodat, sys_mknodat), // 297 -+//ZZ LINX_(__NR_fchownat, sys_fchownat), // 298 -+//ZZ LINX_(__NR_futimesat, sys_futimesat), // 326 on arm -+//ZZ -+//ZZ PLAXY(__NR_fstatat64, sys_fstatat64), // 300 -+//ZZ LINX_(__NR_renameat, sys_renameat), // 302 -+//ZZ LINX_(__NR_linkat, sys_linkat), // 303 -+//ZZ LINX_(__NR_symlinkat, sys_symlinkat), // 304 -+//ZZ -+//ZZ LINX_(__NR_fchmodat, sys_fchmodat), // -+//ZZ LINXY(__NR_shmat, wrap_sys_shmat), //305 -+//ZZ LINXY(__NR_shmdt, sys_shmdt), //306 -+//ZZ LINX_(__NR_shmget, sys_shmget), //307 -+//ZZ LINXY(__NR_shmctl, sys_shmctl), // 308 -+//ZZ // LINX_(__NR_pselect6, sys_pselect6), // -+//ZZ -+//ZZ // LINX_(__NR_unshare, sys_unshare), // 310 -+//ZZ LINX_(__NR_set_robust_list, sys_set_robust_list), // 311 -+//ZZ LINXY(__NR_get_robust_list, sys_get_robust_list), // 312 -+//ZZ // LINX_(__NR_splice, sys_ni_syscall), // 313 -+//ZZ // LINX_(__NR_sync_file_range, sys_sync_file_range), // 314 -+//ZZ -+//ZZ // LINX_(__NR_tee, sys_ni_syscall), // 315 -+//ZZ // LINX_(__NR_vmsplice, sys_ni_syscall), // 316 -+//ZZ LINXY(__NR_move_pages, sys_move_pages), // 317 -+//ZZ // LINX_(__NR_getcpu, sys_ni_syscall), // 318 -+//ZZ -+//ZZ LINX_(__NR_utimensat, sys_utimensat), // 320 -+//ZZ LINXY(__NR_signalfd, sys_signalfd), // 321 -+//ZZ LINXY(__NR_timerfd_create, sys_timerfd_create), // 322 -+//ZZ LINX_(__NR_eventfd, sys_eventfd), // 323 -+//ZZ -+//ZZ LINXY(__NR_timerfd_settime, sys_timerfd_settime), // 325 -+//ZZ LINXY(__NR_timerfd_gettime, sys_timerfd_gettime), // 326 -+//ZZ -+//ZZ /////////////// -+//ZZ -+//ZZ // JRS 2010-Jan-03: I believe that all the numbers listed -+//ZZ // in comments in the table prior to this point (eg "// 326", -+//ZZ // etc) are bogus since it looks to me like they are copied -+//ZZ // verbatim from syswrap-x86-linux.c and they certainly do not -+//ZZ // correspond to what's in include/vki/vki-scnums-arm-linux.h. -+//ZZ // From here onwards, please ensure the numbers are correct. -+//ZZ -+//ZZ LINX_(__NR_pselect6, sys_pselect6), // 335 -+//ZZ LINXY(__NR_ppoll, sys_ppoll), // 336 -+//ZZ -+//ZZ LINXY(__NR_epoll_pwait, sys_epoll_pwait), // 346 -+//ZZ -+//ZZ LINX_(__NR_fallocate, sys_fallocate), // 352 -+//ZZ -+//ZZ LINXY(__NR_signalfd4, sys_signalfd4), // 355 -+//ZZ LINX_(__NR_eventfd2, sys_eventfd2), // 356 -+//ZZ LINXY(__NR_epoll_create1, sys_epoll_create1), // 357 -+//ZZ LINXY(__NR_inotify_init1, sys_inotify_init1), // 360 -+//ZZ LINXY(__NR_preadv, sys_preadv), // 361 -+//ZZ LINX_(__NR_pwritev, sys_pwritev), // 362 -+//ZZ LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 363 -+//ZZ LINXY(__NR_perf_event_open, sys_perf_event_open), // 364 -+//ZZ -+//ZZ LINXY(__NR_accept4, sys_accept4), // 366 -+//ZZ -+//ZZ LINXY(__NR_name_to_handle_at, sys_name_to_handle_at),// 370 -+//ZZ LINXY(__NR_open_by_handle_at, sys_open_by_handle_at) // 371 -+}; -+ -+ -+//ZZ /* These are not in the main table because there indexes are not small -+//ZZ integers, but rather values close to one million. So their -+//ZZ inclusion would force the main table to be huge (about 8 MB). */ -+//ZZ -+//ZZ static SyscallTableEntry ste___ARM_set_tls -+//ZZ = { WRAPPER_PRE_NAME(arm_linux,sys_set_tls), NULL }; -+//ZZ -+//ZZ static SyscallTableEntry ste___ARM_cacheflush -+//ZZ = { WRAPPER_PRE_NAME(arm_linux,sys_cacheflush), NULL }; -+ -+SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno ) -+{ -+ const UInt syscall_main_table_size -+ = sizeof(syscall_main_table) / sizeof(syscall_main_table[0]); -+ -+ /* Is it in the contiguous initial section of the table? */ -+ if (sysno < syscall_main_table_size) { -+ SyscallTableEntry* sys = &syscall_main_table[sysno]; -+ if (sys->before == NULL) -+ return NULL; /* no entry */ -+ else -+ return sys; -+ } -+ -+//ZZ /* Check if it's one of the out-of-line entries. */ -+//ZZ switch (sysno) { -+//ZZ case __NR_ARM_set_tls: return &ste___ARM_set_tls; -+//ZZ case __NR_ARM_cacheflush: return &ste___ARM_cacheflush; -+//ZZ default: break; -+//ZZ } -+ -+ /* Can't find a wrapper */ -+ return NULL; -+} -+ -+#endif // defined(VGP_arm64_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end syswrap-arm64-linux.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_syswrap/syscall-arm-linux.S -=================================================================== ---- coregrind/m_syswrap/syscall-arm-linux.S.orig -+++ coregrind/m_syswrap/syscall-arm-linux.S -@@ -112,7 +112,7 @@ ML_(do_syscall_for_client_WRK): - ldr r3, [sp, #32] /* nsigwords */ - svc 0x00000000 - -- cmp r0, #0 -+ cmp r0, #0 - blt 7f - add sp, sp, #4 /* r0 contains return value */ - -Index: coregrind/m_syswrap/syswrap-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-linux.c.orig -+++ coregrind/m_syswrap/syswrap-linux.c -@@ -209,6 +209,8 @@ static void run_a_thread_NORETURN ( Word - /* This releases the run lock */ - VG_(exit_thread)(tid); - vg_assert(tst->status == VgTs_Zombie); -+ vg_assert(sizeof(tst->status) == 4); -+ vg_assert(sizeof(tst->os_state.exitcode) == sizeof(Word)); - - INNER_REQUEST (VALGRIND_STACK_DEREGISTER (registered_vgstack_id)); - -@@ -264,6 +266,16 @@ static void run_a_thread_NORETURN ( Word - : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) - : "r0", "r7" - ); -+#elif defined(VGP_arm64_linux) -+ asm volatile ( -+ "str %w1, %0\n" /* set tst->status = VgTs_Empty (32-bit store) */ -+ "mov x8, %2\n" /* set %r7 = __NR_exit */ -+ "ldr x0, %3\n" /* set %r0 = tst->os_state.exitcode */ -+ "svc 0x00000000\n" /* exit(tst->os_state.exitcode) */ -+ : "=m" (tst->status) -+ : "r" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) -+ : "r0", "r7" -+ ); - #elif defined(VGP_s390x_linux) - asm volatile ( - "st %1, %0\n" /* set tst->status = VgTs_Empty */ -@@ -276,7 +288,7 @@ static void run_a_thread_NORETURN ( Word - #elif defined(VGP_mips32_linux) || defined(VGP_mips64_linux) - asm volatile ( - "sw %1, %0\n\t" /* set tst->status = VgTs_Empty */ -- "li $2, %2\n\t" /* set v0 = __NR_exit */ -+ "li $2, %2\n\t" /* set v0 = __NR_exit */ - "lw $4, %3\n\t" /* set a0 = tst->os_state.exitcode */ - "syscall\n\t" /* exit(tst->os_state.exitcode) */ - "nop" -@@ -428,7 +440,7 @@ SysRes ML_(do_fork_clone) ( ThreadId tid - #if defined(VGP_x86_linux) \ - || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - res = VG_(do_syscall5)( __NR_clone, flags, - (UWord)NULL, (UWord)parent_tidptr, - (UWord)NULL, (UWord)child_tidptr ); -Index: coregrind/m_syswrap/priv_types_n_macros.h -=================================================================== ---- coregrind/m_syswrap/priv_types_n_macros.h.orig -+++ coregrind/m_syswrap/priv_types_n_macros.h -@@ -92,7 +92,7 @@ typedef - # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ - || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ - || defined(VGP_arm_linux) || defined(VGP_s390x_linux) \ -- || defined(VGP_mips64_linux) -+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - Int o_arg1; - Int o_arg2; - Int o_arg3; -Index: coregrind/m_debuglog.c -=================================================================== ---- coregrind/m_debuglog.c.orig -+++ coregrind/m_debuglog.c -@@ -103,6 +103,7 @@ static UInt local_sys_getpid ( void ) - } - - #elif defined(VGP_amd64_linux) -+ - __attribute__((noinline)) - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { -@@ -267,6 +268,42 @@ static UInt local_sys_getpid ( void ) - return __res; - } - -+#elif defined(VGP_arm64_linux) -+ -+static UInt local_sys_write_stderr ( const HChar* buf, Int n ) -+{ -+ volatile ULong block[2]; -+ block[0] = (ULong)buf; -+ block[1] = (ULong)n; -+ __asm__ volatile ( -+ "mov x0, #2\n\t" /* stderr */ -+ "ldr x1, [%0]\n\t" /* buf */ -+ "ldr x2, [%0, #8]\n\t" /* n */ -+ "mov x8, #"VG_STRINGIFY(__NR_write)"\n\t" -+ "svc 0x0\n" /* write() */ -+ "str x0, [%0]\n\t" -+ : -+ : "r" (block) -+ : "x0","x1","x2","x7" -+ ); -+ if (block[0] < 0) -+ block[0] = -1; -+ return (UInt)block[0]; -+} -+ -+static UInt local_sys_getpid ( void ) -+{ -+ UInt __res; -+ __asm__ volatile ( -+ "mov x8, #"VG_STRINGIFY(__NR_getpid)"\n" -+ "svc 0x0\n" /* getpid() */ -+ "mov %0, x0\n" -+ : "=r" (__res) -+ : -+ : "x0", "x8" ); -+ return (UInt)__res; -+} -+ - #elif defined(VGP_x86_darwin) - - /* We would use VG_DARWIN_SYSNO_TO_KERNEL instead of VG_DARWIN_SYSNO_INDEX -@@ -350,6 +387,7 @@ static UInt local_sys_getpid ( void ) - } - - #elif defined(VGP_s390x_linux) -+ - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { - register Int r2 asm("2") = 2; /* file descriptor STDERR */ -@@ -391,6 +429,7 @@ static UInt local_sys_getpid ( void ) - } - - #elif defined(VGP_mips32_linux) -+ - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { - volatile Int block[2]; -@@ -428,6 +467,7 @@ static UInt local_sys_getpid ( void ) - } - - #elif defined(VGP_mips64_linux) -+ - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { - volatile Long block[2]; -Index: coregrind/m_vki.c -=================================================================== ---- coregrind/m_vki.c.orig -+++ coregrind/m_vki.c -@@ -42,7 +42,8 @@ - /* ppc32/64-linux determines page size at startup, hence m_vki is - the logical place to store that info. */ - --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -+ || defined(VGP_arm64_linux) - unsigned long VKI_PAGE_SHIFT = 12; - unsigned long VKI_PAGE_SIZE = 1UL << 12; - #endif -Index: coregrind/m_options.c -=================================================================== ---- coregrind/m_options.c.orig -+++ coregrind/m_options.c -@@ -48,7 +48,8 @@ Bool VG_(clo_error_limit) = True; - Int VG_(clo_error_exitcode) = 0; - - #if defined(VGPV_arm_linux_android) || defined(VGPV_x86_linux_android) \ -- || defined(VGPV_mips32_linux_android) -+ || defined(VGPV_mips32_linux_android) \ -+ || defined(VGP_arm64_linux) // temporarily disabled on arm64-linux - VgVgdb VG_(clo_vgdb) = Vg_VgdbNo; // currently disabled on Android - #else - VgVgdb VG_(clo_vgdb) = Vg_VgdbYes; -Index: coregrind/m_scheduler/scheduler.c -=================================================================== ---- coregrind/m_scheduler/scheduler.c.orig -+++ coregrind/m_scheduler/scheduler.c -@@ -790,12 +790,21 @@ static void do_pre_run_checks ( ThreadSt - vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow2.guest_D1)); - # endif - -+# if defined(VGA_arm64) -+ vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex.guest_X0)); -+ vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow1.guest_X0)); -+ vg_assert(VG_IS_8_ALIGNED(& tst->arch.vex_shadow2.guest_X0)); -+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_Q0)); -+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_Q0)); -+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_Q0)); -+# endif -+ - # if defined(VGA_s390x) - /* no special requirements */ - # endif - - # if defined(VGA_mips32) || defined(VGA_mips64) -- /* no special requirements */ -+ /* no special requirements */ - # endif - } - -@@ -1598,6 +1607,9 @@ void VG_(nuke_all_threads_except) ( Thre - #elif defined(VGA_arm) - # define VG_CLREQ_ARGS guest_R4 - # define VG_CLREQ_RET guest_R3 -+#elif defined(VGA_arm64) -+# define VG_CLREQ_ARGS guest_X4 -+# define VG_CLREQ_RET guest_X3 - #elif defined (VGA_s390x) - # define VG_CLREQ_ARGS guest_r2 - # define VG_CLREQ_RET guest_r3 -Index: coregrind/m_gdbserver/target.c -=================================================================== ---- coregrind/m_gdbserver/target.c.orig -+++ coregrind/m_gdbserver/target.c -@@ -641,6 +641,8 @@ void valgrind_initialize_target(void) - amd64_init_architecture(&the_low_target); - #elif defined(VGA_arm) - arm_init_architecture(&the_low_target); -+#elif defined(VGA_arm64) -+ arm_init_architecture(&the_low_target); - #elif defined(VGA_ppc32) - ppc32_init_architecture(&the_low_target); - #elif defined(VGA_ppc64) -@@ -652,6 +654,6 @@ void valgrind_initialize_target(void) - #elif defined(VGA_mips64) - mips64_init_architecture(&the_low_target); - #else -- architecture missing in target.c valgrind_initialize_target -+ #error "architecture missing in target.c valgrind_initialize_target" - #endif - } -Index: coregrind/m_gdbserver/valgrind_low.h -=================================================================== ---- coregrind/m_gdbserver/valgrind_low.h.orig -+++ coregrind/m_gdbserver/valgrind_low.h -@@ -73,6 +73,7 @@ struct valgrind_target_ops - extern void x86_init_architecture (struct valgrind_target_ops *target); - extern void amd64_init_architecture (struct valgrind_target_ops *target); - extern void arm_init_architecture (struct valgrind_target_ops *target); -+extern void arm64_init_architecture (struct valgrind_target_ops *target); - extern void ppc32_init_architecture (struct valgrind_target_ops *target); - extern void ppc64_init_architecture (struct valgrind_target_ops *target); - extern void s390x_init_architecture (struct valgrind_target_ops *target); -Index: coregrind/m_gdbserver/valgrind-low-arm64.c -=================================================================== ---- /dev/null -+++ coregrind/m_gdbserver/valgrind-low-arm64.c -@@ -0,0 +1,307 @@ -+/* Low level interface to valgrind, for the remote server for GDB integrated -+ in valgrind. -+ Copyright (C) 2011 -+ Free Software Foundation, Inc. -+ -+ This file is part of VALGRIND. -+ It has been inspired from a file from gdbserver in gdb 6.6. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street, Fifth Floor, -+ Boston, MA 02110-1301, USA. */ -+ -+#include "server.h" -+#include "target.h" -+#include "regdef.h" -+#include "regcache.h" -+ -+#include "pub_core_aspacemgr.h" -+#include "pub_tool_machine.h" -+#include "pub_core_threadstate.h" -+#include "pub_core_transtab.h" -+#include "pub_core_gdbserver.h" -+#include "pub_core_debuginfo.h" -+ -+#include "valgrind_low.h" -+ -+#include "libvex_guest_arm64.h" -+ -+//ZZ static struct reg regs[] = { -+//ZZ { "r0", 0, 32 }, -+//ZZ { "r1", 32, 32 }, -+//ZZ { "r2", 64, 32 }, -+//ZZ { "r3", 96, 32 }, -+//ZZ { "r4", 128, 32 }, -+//ZZ { "r5", 160, 32 }, -+//ZZ { "r6", 192, 32 }, -+//ZZ { "r7", 224, 32 }, -+//ZZ { "r8", 256, 32 }, -+//ZZ { "r9", 288, 32 }, -+//ZZ { "r10", 320, 32 }, -+//ZZ { "r11", 352, 32 }, -+//ZZ { "r12", 384, 32 }, -+//ZZ { "sp", 416, 32 }, -+//ZZ { "lr", 448, 32 }, -+//ZZ { "pc", 480, 32 }, -+//ZZ { "", 512, 0 }, // It seems these entries are needed -+//ZZ { "", 512, 0 }, // as previous versions of arm <-> gdb placed -+//ZZ { "", 512, 0 }, // some floating point registers here. So, cpsr -+//ZZ { "", 512, 0 }, // must be register 25. -+//ZZ { "", 512, 0 }, -+//ZZ { "", 512, 0 }, -+//ZZ { "", 512, 0 }, -+//ZZ { "", 512, 0 }, -+//ZZ { "", 512, 0 }, -+//ZZ { "cpsr", 512, 32 }, -+//ZZ { "d0", 544, 64 }, -+//ZZ { "d1", 608, 64 }, -+//ZZ { "d2", 672, 64 }, -+//ZZ { "d3", 736, 64 }, -+//ZZ { "d4", 800, 64 }, -+//ZZ { "d5", 864, 64 }, -+//ZZ { "d6", 928, 64 }, -+//ZZ { "d7", 992, 64 }, -+//ZZ { "d8", 1056, 64 }, -+//ZZ { "d9", 1120, 64 }, -+//ZZ { "d10", 1184, 64 }, -+//ZZ { "d11", 1248, 64 }, -+//ZZ { "d12", 1312, 64 }, -+//ZZ { "d13", 1376, 64 }, -+//ZZ { "d14", 1440, 64 }, -+//ZZ { "d15", 1504, 64 }, -+//ZZ { "d16", 1568, 64 }, -+//ZZ { "d17", 1632, 64 }, -+//ZZ { "d18", 1696, 64 }, -+//ZZ { "d19", 1760, 64 }, -+//ZZ { "d20", 1824, 64 }, -+//ZZ { "d21", 1888, 64 }, -+//ZZ { "d22", 1952, 64 }, -+//ZZ { "d23", 2016, 64 }, -+//ZZ { "d24", 2080, 64 }, -+//ZZ { "d25", 2144, 64 }, -+//ZZ { "d26", 2208, 64 }, -+//ZZ { "d27", 2272, 64 }, -+//ZZ { "d28", 2336, 64 }, -+//ZZ { "d29", 2400, 64 }, -+//ZZ { "d30", 2464, 64 }, -+//ZZ { "d31", 2528, 64 }, -+//ZZ { "fpscr", 2592, 32 } -+//ZZ }; -+//ZZ static const char *expedite_regs[] = { "r11", "sp", "pc", 0 }; -+//ZZ #define num_regs (sizeof (regs) / sizeof (regs[0])) -+//ZZ -+//ZZ static -+//ZZ CORE_ADDR get_pc (void) -+//ZZ { -+//ZZ unsigned long pc; -+//ZZ -+//ZZ collect_register_by_name ("pc", &pc); -+//ZZ -+//ZZ dlog(1, "stop pc is %p\n", (void *) pc); -+//ZZ return pc; -+//ZZ } -+//ZZ -+//ZZ static -+//ZZ void set_pc (CORE_ADDR newpc) -+//ZZ { -+//ZZ Bool mod; -+//ZZ supply_register_by_name ("pc", &newpc, &mod); -+//ZZ if (mod) -+//ZZ dlog(1, "set pc to %p\n", C2v (newpc)); -+//ZZ else -+//ZZ dlog(1, "set pc not changed %p\n", C2v (newpc)); -+//ZZ } -+//ZZ -+//ZZ Addr thumb_pc (Addr pc) -+//ZZ { -+//ZZ // If the thumb bit (bit 0) is already set, we trust it. -+//ZZ if (pc & 1) { -+//ZZ dlog (1, "%p = thumb (bit0 is set)\n", C2v (pc)); -+//ZZ return pc; -+//ZZ } -+//ZZ -+//ZZ // Here, bit 0 is not set. -+//ZZ // For a pc aligned on 4 bytes, we have to use the debug -+//ZZ // info to determine the thumb-ness. -+//ZZ // else (aligned on 2 bytes), we trust this is a thumb -+//ZZ // address and we set the thumb bit. -+//ZZ -+//ZZ if (pc & 2) { -+//ZZ dlog (1, "bit0 not set, bit1 set => %p = thumb\n", C2v (pc)); -+//ZZ return pc | 1; -+//ZZ } -+//ZZ -+//ZZ // pc aligned on 4 bytes. We need to use debug info. -+//ZZ { -+//ZZ HChar fnname[200]; // ??? max size -+//ZZ Addr entrypoint; -+//ZZ Addr ptoc; // unused but needed. -+//ZZ // If this is a thumb instruction, we need to ask -+//ZZ // the debug info with the bit0 set -+//ZZ // (why can't debug info do that for us ???) -+//ZZ // (why if this is a 4 bytes thumb instruction ???) -+//ZZ if (VG_(get_fnname_raw) (pc | 1, fnname, 200)) { -+//ZZ if (VG_(lookup_symbol_SLOW)( "*", fnname, &entrypoint, &ptoc )) { -+//ZZ dlog (1, "fnname %s lookupsym %p => %p %s.\n", -+//ZZ fnname, C2v(entrypoint), C2v(pc), -+//ZZ (entrypoint & 1 ? "thumb" : "arm")); -+//ZZ if (entrypoint & 1) -+//ZZ return pc | 1; -+//ZZ else -+//ZZ return pc; -+//ZZ -+//ZZ } else { -+//ZZ dlog (1, "%p fnname %s lookupsym failed?. Assume arm\n", -+//ZZ C2v (pc), fnname); -+//ZZ return pc; -+//ZZ } -+//ZZ } else { -+//ZZ // Can't find function name. We assume this is arm -+//ZZ dlog (1, "%p unknown fnname?. Assume arm\n", C2v (pc)); -+//ZZ return pc; -+//ZZ } -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ /* store registers in the guest state (gdbserver_to_valgrind) -+//ZZ or fetch register from the guest state (valgrind_to_gdbserver). */ -+//ZZ static -+//ZZ void transfer_register (ThreadId tid, int abs_regno, void * buf, -+//ZZ transfer_direction dir, int size, Bool *mod) -+//ZZ { -+//ZZ ThreadState* tst = VG_(get_ThreadState)(tid); -+//ZZ int set = abs_regno / num_regs; -+//ZZ int regno = abs_regno % num_regs; -+//ZZ *mod = False; -+//ZZ -+//ZZ VexGuestARMState* arm = (VexGuestARMState*) get_arch (set, tst); -+//ZZ -+//ZZ switch (regno) { -+//ZZ // numbers here have to match the order of regs above -+//ZZ // Attention: gdb order does not match valgrind order. -+//ZZ case 0: VG_(transfer) (&arm->guest_R0, buf, dir, size, mod); break; -+//ZZ case 1: VG_(transfer) (&arm->guest_R1, buf, dir, size, mod); break; -+//ZZ case 2: VG_(transfer) (&arm->guest_R2, buf, dir, size, mod); break; -+//ZZ case 3: VG_(transfer) (&arm->guest_R3, buf, dir, size, mod); break; -+//ZZ case 4: VG_(transfer) (&arm->guest_R4, buf, dir, size, mod); break; -+//ZZ case 5: VG_(transfer) (&arm->guest_R5, buf, dir, size, mod); break; -+//ZZ case 6: VG_(transfer) (&arm->guest_R6, buf, dir, size, mod); break; -+//ZZ case 7: VG_(transfer) (&arm->guest_R7, buf, dir, size, mod); break; -+//ZZ case 8: VG_(transfer) (&arm->guest_R8, buf, dir, size, mod); break; -+//ZZ case 9: VG_(transfer) (&arm->guest_R9, buf, dir, size, mod); break; -+//ZZ case 10: VG_(transfer) (&arm->guest_R10, buf, dir, size, mod); break; -+//ZZ case 11: VG_(transfer) (&arm->guest_R11, buf, dir, size, mod); break; -+//ZZ case 12: VG_(transfer) (&arm->guest_R12, buf, dir, size, mod); break; -+//ZZ case 13: VG_(transfer) (&arm->guest_R13, buf, dir, size, mod); break; -+//ZZ case 14: VG_(transfer) (&arm->guest_R14, buf, dir, size, mod); break; -+//ZZ case 15: { -+//ZZ VG_(transfer) (&arm->guest_R15T, buf, dir, size, mod); -+//ZZ if (dir == gdbserver_to_valgrind && *mod) { -+//ZZ // If gdb is changing the PC, we have to set the thumb bit -+//ZZ // if needed. -+//ZZ arm->guest_R15T = thumb_pc(arm->guest_R15T); -+//ZZ } -+//ZZ break; -+//ZZ } -+//ZZ case 16: -+//ZZ case 17: -+//ZZ case 18: -+//ZZ case 19: -+//ZZ case 20: /* 9 "empty registers". See struct reg regs above. */ -+//ZZ case 21: -+//ZZ case 22: -+//ZZ case 23: -+//ZZ case 24: *mod = False; break; -+//ZZ case 25: { -+//ZZ UInt cpsr = LibVEX_GuestARM_get_cpsr (arm); -+//ZZ if (dir == valgrind_to_gdbserver) { -+//ZZ VG_(transfer) (&cpsr, buf, dir, size, mod); -+//ZZ } else { -+//ZZ # if 0 -+//ZZ UInt newcpsr; -+//ZZ VG_(transfer) (&newcpsr, buf, dir, size, mod); -+//ZZ *mod = newcpsr != cpsr; -+//ZZ // GDBTD ???? see FIXME in guest_arm_helpers.c -+//ZZ LibVEX_GuestARM_put_flags (newcpsr, arm); -+//ZZ # else -+//ZZ *mod = False; -+//ZZ # endif -+//ZZ } -+//ZZ break; -+//ZZ } -+//ZZ case 26: VG_(transfer) (&arm->guest_D0, buf, dir, size, mod); break; -+//ZZ case 27: VG_(transfer) (&arm->guest_D1, buf, dir, size, mod); break; -+//ZZ case 28: VG_(transfer) (&arm->guest_D2, buf, dir, size, mod); break; -+//ZZ case 29: VG_(transfer) (&arm->guest_D3, buf, dir, size, mod); break; -+//ZZ case 30: VG_(transfer) (&arm->guest_D4, buf, dir, size, mod); break; -+//ZZ case 31: VG_(transfer) (&arm->guest_D5, buf, dir, size, mod); break; -+//ZZ case 32: VG_(transfer) (&arm->guest_D6, buf, dir, size, mod); break; -+//ZZ case 33: VG_(transfer) (&arm->guest_D7, buf, dir, size, mod); break; -+//ZZ case 34: VG_(transfer) (&arm->guest_D8, buf, dir, size, mod); break; -+//ZZ case 35: VG_(transfer) (&arm->guest_D9, buf, dir, size, mod); break; -+//ZZ case 36: VG_(transfer) (&arm->guest_D10, buf, dir, size, mod); break; -+//ZZ case 37: VG_(transfer) (&arm->guest_D11, buf, dir, size, mod); break; -+//ZZ case 38: VG_(transfer) (&arm->guest_D12, buf, dir, size, mod); break; -+//ZZ case 39: VG_(transfer) (&arm->guest_D13, buf, dir, size, mod); break; -+//ZZ case 40: VG_(transfer) (&arm->guest_D14, buf, dir, size, mod); break; -+//ZZ case 41: VG_(transfer) (&arm->guest_D15, buf, dir, size, mod); break; -+//ZZ case 42: VG_(transfer) (&arm->guest_D16, buf, dir, size, mod); break; -+//ZZ case 43: VG_(transfer) (&arm->guest_D17, buf, dir, size, mod); break; -+//ZZ case 44: VG_(transfer) (&arm->guest_D18, buf, dir, size, mod); break; -+//ZZ case 45: VG_(transfer) (&arm->guest_D19, buf, dir, size, mod); break; -+//ZZ case 46: VG_(transfer) (&arm->guest_D20, buf, dir, size, mod); break; -+//ZZ case 47: VG_(transfer) (&arm->guest_D21, buf, dir, size, mod); break; -+//ZZ case 48: VG_(transfer) (&arm->guest_D22, buf, dir, size, mod); break; -+//ZZ case 49: VG_(transfer) (&arm->guest_D23, buf, dir, size, mod); break; -+//ZZ case 50: VG_(transfer) (&arm->guest_D24, buf, dir, size, mod); break; -+//ZZ case 51: VG_(transfer) (&arm->guest_D25, buf, dir, size, mod); break; -+//ZZ case 52: VG_(transfer) (&arm->guest_D26, buf, dir, size, mod); break; -+//ZZ case 53: VG_(transfer) (&arm->guest_D27, buf, dir, size, mod); break; -+//ZZ case 54: VG_(transfer) (&arm->guest_D28, buf, dir, size, mod); break; -+//ZZ case 55: VG_(transfer) (&arm->guest_D29, buf, dir, size, mod); break; -+//ZZ case 56: VG_(transfer) (&arm->guest_D30, buf, dir, size, mod); break; -+//ZZ case 57: VG_(transfer) (&arm->guest_D31, buf, dir, size, mod); break; -+//ZZ case 58: VG_(transfer) (&arm->guest_FPSCR, buf, dir, size, mod); break; -+//ZZ default: vg_assert(0); -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static -+//ZZ const char* target_xml (Bool shadow_mode) -+//ZZ { -+//ZZ if (shadow_mode) { -+//ZZ return "arm-with-vfpv3-valgrind.xml"; -+//ZZ } else { -+//ZZ return "arm-with-vfpv3.xml"; -+//ZZ } -+//ZZ } -+//ZZ -+//ZZ static struct valgrind_target_ops low_target = { -+//ZZ num_regs, -+//ZZ regs, -+//ZZ 13, //SP -+//ZZ transfer_register, -+//ZZ get_pc, -+//ZZ set_pc, -+//ZZ "arm", -+//ZZ target_xml -+//ZZ }; -+ -+void arm64_init_architecture (struct valgrind_target_ops *target) -+{ -+ vg_assert(0); // IMPLEMENT ME -+ //ZZ *target = low_target; -+ //ZZ set_register_cache (regs, num_regs); -+ //ZZ gdbserver_expedite_regs = expedite_regs; -+} -Index: coregrind/pub_core_debuginfo.h -=================================================================== ---- coregrind/pub_core_debuginfo.h.orig -+++ coregrind/pub_core_debuginfo.h -@@ -118,6 +118,10 @@ typedef - typedef - struct { Addr r15; Addr r14; Addr r13; Addr r12; Addr r11; Addr r7; } - D3UnwindRegs; -+#elif defined(VGA_arm64) -+typedef -+ struct { Addr pc; Addr sp; Addr lr; Addr fp; } /* PC, 31, 30, 29 */ -+ D3UnwindRegs; - #elif defined(VGA_ppc32) || defined(VGA_ppc64) - typedef - UChar /* should be void, but gcc complains at use points */ -Index: coregrind/pub_core_basics.h -=================================================================== ---- coregrind/pub_core_basics.h.orig -+++ coregrind/pub_core_basics.h -@@ -58,6 +58,8 @@ - # include "libvex_guest_ppc64.h" - #elif defined(VGA_arm) - # include "libvex_guest_arm.h" -+#elif defined(VGA_arm64) -+# include "libvex_guest_arm64.h" - #elif defined(VGA_s390x) - # include "libvex_guest_s390x.h" - #elif defined(VGA_mips32) -@@ -109,6 +111,11 @@ typedef - UInt r7; - } ARM; - struct { -+ // FIXME ARM64 is this correct? -+ ULong x29; /* FP */ -+ ULong x30; /* LR */ -+ } ARM64; -+ struct { - ULong r_fp; - ULong r_lr; - } S390X; -Index: coregrind/Makefile.am -=================================================================== ---- coregrind/Makefile.am.orig -+++ coregrind/Makefile.am -@@ -314,6 +314,7 @@ COREGRIND_SOURCES_COMMON = \ - m_dispatch/dispatch-ppc32-linux.S \ - m_dispatch/dispatch-ppc64-linux.S \ - m_dispatch/dispatch-arm-linux.S \ -+ m_dispatch/dispatch-arm64-linux.S \ - m_dispatch/dispatch-s390x-linux.S \ - m_dispatch/dispatch-mips32-linux.S \ - m_dispatch/dispatch-mips64-linux.S \ -@@ -330,6 +331,7 @@ COREGRIND_SOURCES_COMMON = \ - m_gdbserver/valgrind-low-x86.c \ - m_gdbserver/valgrind-low-amd64.c \ - m_gdbserver/valgrind-low-arm.c \ -+ m_gdbserver/valgrind-low-arm64.c \ - m_gdbserver/valgrind-low-ppc32.c \ - m_gdbserver/valgrind-low-ppc64.c \ - m_gdbserver/valgrind-low-s390x.c \ -@@ -353,6 +355,7 @@ COREGRIND_SOURCES_COMMON = \ - m_sigframe/sigframe-ppc32-linux.c \ - m_sigframe/sigframe-ppc64-linux.c \ - m_sigframe/sigframe-arm-linux.c \ -+ m_sigframe/sigframe-arm64-linux.c \ - m_sigframe/sigframe-s390x-linux.c \ - m_sigframe/sigframe-mips32-linux.c \ - m_sigframe/sigframe-mips64-linux.c \ -@@ -363,6 +366,7 @@ COREGRIND_SOURCES_COMMON = \ - m_syswrap/syscall-ppc32-linux.S \ - m_syswrap/syscall-ppc64-linux.S \ - m_syswrap/syscall-arm-linux.S \ -+ m_syswrap/syscall-arm64-linux.S \ - m_syswrap/syscall-s390x-linux.S \ - m_syswrap/syscall-mips32-linux.S \ - m_syswrap/syscall-mips64-linux.S \ -@@ -378,6 +382,7 @@ COREGRIND_SOURCES_COMMON = \ - m_syswrap/syswrap-ppc32-linux.c \ - m_syswrap/syswrap-ppc64-linux.c \ - m_syswrap/syswrap-arm-linux.c \ -+ m_syswrap/syswrap-arm64-linux.c \ - m_syswrap/syswrap-s390x-linux.c \ - m_syswrap/syswrap-mips32-linux.c \ - m_syswrap/syswrap-mips64-linux.c \ -Index: coregrind/m_sigframe/sigframe-arm64-linux.c -=================================================================== ---- /dev/null -+++ coregrind/m_sigframe/sigframe-arm64-linux.c -@@ -0,0 +1,337 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Create/destroy signal delivery frames. ---*/ -+/*--- sigframe-arm64-linux.c ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics.h" -+#include "pub_core_vki.h" -+//ZZ #include "pub_core_vkiscnums.h" -+#include "pub_core_libcsetjmp.h" // to keep _threadstate.h happy -+#include "pub_core_threadstate.h" -+#include "pub_core_aspacemgr.h" -+#include "pub_core_libcbase.h" -+#include "pub_core_libcassert.h" -+#include "pub_core_libcprint.h" -+#include "pub_core_machine.h" -+#include "pub_core_options.h" -+#include "pub_core_sigframe.h" -+#include "pub_core_signals.h" -+#include "pub_core_tooliface.h" -+#include "pub_core_trampoline.h" -+//ZZ #include "pub_core_transtab.h" // VG_(discard_translations) -+ -+ -+/* This uses the hack of dumping the vex guest state along with both -+ shadows in the frame, and restoring it afterwards from there, -+ rather than pulling it out of the ucontext. That means that signal -+ handlers which modify the ucontext and then return, expecting their -+ modifications to take effect, will have those modifications -+ ignored. This could be fixed properly with an hour or so more -+ effort. */ -+ -+/* This also always does the 'has siginfo' behaviour whether or -+ not it is requested. */ -+ -+struct vg_sig_private { -+ UInt magicPI; -+ UInt sigNo_private; -+ VexGuestARM64State vex; -+ VexGuestARM64State vex_shadow1; -+ VexGuestARM64State vex_shadow2; -+}; -+ -+struct sigframe { -+ struct vki_ucontext uc; -+ unsigned long retcode[2]; -+ struct vg_sig_private vp; -+}; -+ -+struct rt_sigframe { -+ vki_siginfo_t info; -+ struct sigframe sig; -+}; -+ -+static Bool extend ( ThreadState *tst, Addr addr, SizeT size ) -+{ -+ ThreadId tid = tst->tid; -+ NSegment const* stackseg = NULL; -+ -+ if (VG_(extend_stack)(addr, tst->client_stack_szB)) { -+ stackseg = VG_(am_find_nsegment)(addr); -+ if (0 && stackseg) -+ VG_(printf)("frame=%#lx seg=%#lx-%#lx\n", -+ addr, stackseg->start, stackseg->end); -+ } -+ -+ if (stackseg == NULL || !stackseg->hasR || !stackseg->hasW) { -+ VG_(message)( -+ Vg_UserMsg, -+ "Can't extend stack to %#lx during signal delivery for thread %d:", -+ addr, tid); -+ if (stackseg == NULL) -+ VG_(message)(Vg_UserMsg, " no stack segment"); -+ else -+ VG_(message)(Vg_UserMsg, " too small or bad protection modes"); -+ -+ /* set SIGSEGV to default handler */ -+ VG_(set_default_handler)(VKI_SIGSEGV); -+ VG_(synth_fault_mapping)(tid, addr); -+ -+ /* The whole process should be about to die, since the default -+ action of SIGSEGV to kill the whole process. */ -+ return False; -+ } -+ -+ /* For tracking memory events, indicate the entire frame has been -+ allocated. */ -+ VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB, -+ size + VG_STACK_REDZONE_SZB, tid ); -+ -+ return True; -+} -+ -+static void synth_ucontext( ThreadId tid, const vki_siginfo_t *si, -+ UWord trapno, UWord err, const vki_sigset_t *set, -+ struct vki_ucontext *uc) -+{ -+ -+ ThreadState *tst = VG_(get_ThreadState)(tid); -+ struct vki_sigcontext *sc = &uc->uc_mcontext; -+ -+ VG_(memset)(uc, 0, sizeof(*uc)); -+ -+ uc->uc_flags = 0; -+ uc->uc_link = 0; -+ uc->uc_sigmask = *set; -+ uc->uc_stack = tst->altstack; -+ -+# define SC2(reg) sc->regs[reg] = tst->arch.vex.guest_X##reg -+ SC2(0); SC2(1); SC2(2); SC2(3); -+ SC2(4); SC2(5); SC2(6); SC2(7); -+ SC2(8); SC2(9); SC2(10); SC2(11); -+ SC2(12); SC2(13); SC2(14); SC2(15); -+ SC2(16); SC2(17); SC2(18); SC2(19); -+ SC2(20); SC2(21); SC2(22); SC2(23); -+ SC2(24); SC2(25); SC2(26); SC2(27); -+ SC2(28); SC2(29); SC2(30); -+# undef SC2 -+ sc->sp = tst->arch.vex.guest_SP; -+ sc->pc = tst->arch.vex.guest_PC; -+ sc->pstate = 0; /* slack .. could do better */ -+ -+ //sc->trap_no = trapno; -+ //sc->error_code = err; -+ sc->fault_address = (ULong)si->_sifields._sigfault._addr; -+} -+ -+ -+static void build_sigframe(ThreadState *tst, -+ struct sigframe *frame, -+ const vki_siginfo_t *siginfo, -+ const struct vki_ucontext *siguc, -+ void *handler, UInt flags, -+ const vki_sigset_t *mask, -+ void *restorer) -+{ -+ UWord trapno; -+ UWord err; -+ Int sigNo = siginfo->si_signo; -+ struct vg_sig_private *priv = &frame->vp; -+ -+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal handler frame", -+ (Addr)frame, offsetof(struct sigframe, vp)); -+ -+ if (siguc) { -+ trapno = 0; //siguc->uc_mcontext.trap_no; -+ err = 0; //siguc->uc_mcontext.error_code; -+ } else { -+ trapno = 0; -+ err = 0; -+ } -+ -+ synth_ucontext(tst->tid, siginfo, trapno, err, mask, &frame->uc); -+ -+ VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, -+ (Addr)frame, offsetof(struct sigframe, vp)); -+ -+ priv->magicPI = 0x31415927; -+ priv->sigNo_private = sigNo; -+ priv->vex = tst->arch.vex; -+ priv->vex_shadow1 = tst->arch.vex_shadow1; -+ priv->vex_shadow2 = tst->arch.vex_shadow2; -+} -+ -+ -+/* EXPORTED */ -+void VG_(sigframe_create)( ThreadId tid, -+ Addr sp_top_of_frame, -+ const vki_siginfo_t *siginfo, -+ const struct vki_ucontext *siguc, -+ void *handler, -+ UInt flags, -+ const vki_sigset_t *mask, -+ void *restorer ) -+{ -+ ThreadState *tst; -+ Addr sp = sp_top_of_frame; -+ Int sigNo = siginfo->si_signo; -+ UInt size; -+ -+ tst = VG_(get_ThreadState)(tid); -+ -+ size = sizeof(struct rt_sigframe); -+ -+ sp -= size; -+ sp = VG_ROUNDDN(sp, 16); -+ -+ if (!extend(tst, sp, size)) -+ return; // Give up. No idea if this is correct -+ -+ struct rt_sigframe *rsf = (struct rt_sigframe *)sp; -+ -+ /* Track our writes to siginfo */ -+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, /* VVVVV */ -+ "signal handler siginfo", (Addr)rsf, -+ offsetof(struct rt_sigframe, sig)); -+ -+ VG_(memcpy)(&rsf->info, siginfo, sizeof(vki_siginfo_t)); -+ -+ if (sigNo == VKI_SIGILL && siginfo->si_code > 0) { -+ rsf->info._sifields._sigfault._addr -+ = (Addr*)(tst)->arch.vex.guest_PC; -+ } -+ VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, /* ^^^^^ */ -+ (Addr)rsf, offsetof(struct rt_sigframe, sig)); -+ -+ build_sigframe(tst, &rsf->sig, siginfo, siguc, -+ handler, flags, mask, restorer); -+ tst->arch.vex.guest_X1 = (Addr)&rsf->info; -+ tst->arch.vex.guest_X2 = (Addr)&rsf->sig.uc; -+ -+ VG_(set_SP)(tid, sp); -+ VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, -+ sizeof(Addr)); -+ tst->arch.vex.guest_X0 = sigNo; -+ -+ if (flags & VKI_SA_RESTORER) -+ tst->arch.vex.guest_X30 = (Addr)restorer; -+ else -+ tst->arch.vex.guest_X30 -+ = (Addr)&VG_(arm64_linux_SUBST_FOR_rt_sigreturn); -+ -+ tst->arch.vex.guest_PC = (Addr)handler; -+} -+ -+ -+/*------------------------------------------------------------*/ -+/*--- Destroying signal frames ---*/ -+/*------------------------------------------------------------*/ -+ -+/* EXPORTED */ -+void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) -+{ -+ ThreadState *tst; -+ struct vg_sig_private *priv; -+ Addr sp; -+ UInt frame_size; -+//ZZ struct vki_sigcontext *mc; -+ Int sigNo; -+ Bool has_siginfo = isRT; -+ -+ vg_assert(VG_(is_valid_tid)(tid)); -+ tst = VG_(get_ThreadState)(tid); -+ sp = tst->arch.vex.guest_SP; -+ -+//ZZ if (has_siginfo) { -+ struct rt_sigframe *frame = (struct rt_sigframe *)sp; -+ frame_size = sizeof(*frame); -+ //mc = &frame->sig.uc.uc_mcontext; -+ priv = &frame->sig.vp; -+ vg_assert(priv->magicPI == 0x31415927); -+ tst->sig_mask = frame->sig.uc.uc_sigmask; -+//ZZ } else { -+//ZZ struct sigframe *frame = (struct sigframe *)sp; -+//ZZ frame_size = sizeof(*frame); -+//ZZ mc = &frame->uc.uc_mcontext; -+//ZZ priv = &frame->vp; -+//ZZ vg_assert(priv->magicPI == 0x31415927); -+//ZZ tst->sig_mask = frame->uc.uc_sigmask; -+//ZZ //VG_(printf)("Setting signmask to %08x%08x\n", -+//ZZ // tst->sig_mask[0],tst->sig_mask[1]); -+//ZZ } -+ tst->tmp_sig_mask = tst->sig_mask; -+ -+ sigNo = priv->sigNo_private; -+ -+//ZZ //XXX: restore regs -+//ZZ # define REST(reg,REG) tst->arch.vex.guest_##REG = mc->arm_##reg; -+//ZZ REST(r0,R0); -+//ZZ REST(r1,R1); -+//ZZ REST(r2,R2); -+//ZZ REST(r3,R3); -+//ZZ REST(r4,R4); -+//ZZ REST(r5,R5); -+//ZZ REST(r6,R6); -+//ZZ REST(r7,R7); -+//ZZ REST(r8,R8); -+//ZZ REST(r9,R9); -+//ZZ REST(r10,R10); -+//ZZ REST(fp,R11); -+//ZZ REST(ip,R12); -+//ZZ REST(sp,R13); -+//ZZ REST(lr,R14); -+//ZZ REST(pc,R15T); -+//ZZ # undef REST -+ -+ /* Uh, the next line makes all the REST() above pointless. */ -+ tst->arch.vex = priv->vex; -+ -+ tst->arch.vex_shadow1 = priv->vex_shadow1; -+ tst->arch.vex_shadow2 = priv->vex_shadow2; -+ -+ VG_TRACK( die_mem_stack_signal, sp - VG_STACK_REDZONE_SZB, -+ frame_size + VG_STACK_REDZONE_SZB ); -+ -+ if (VG_(clo_trace_signals)) -+ VG_(message)(Vg_DebugMsg, -+ "vg_pop_signal_frame (thread %d): " -+ "isRT=%d valid magic; PC=%#llx\n", -+ tid, has_siginfo, tst->arch.vex.guest_PC); -+ -+ /* tell the tools */ -+ VG_TRACK( post_deliver_signal, tid, sigNo ); -+} -+ -+#endif // defined(VGP_arm_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end sigframe-arm64-linux.c ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_dispatch/dispatch-arm64-linux.S -=================================================================== ---- /dev/null -+++ coregrind/m_dispatch/dispatch-arm64-linux.S -@@ -0,0 +1,241 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- The core dispatch loop, for jumping to a code address. ---*/ -+/*--- dispatch-arm64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_arm64_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_dispatch_asm.h" -+#include "pub_core_transtab_asm.h" -+#include "libvex_guest_offsets.h" /* for OFFSET_arm_R* */ -+ -+ -+/*------------------------------------------------------------*/ -+/*--- ---*/ -+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/ -+/*--- used to run all translations, ---*/ -+/*--- including no-redir ones. ---*/ -+/*--- ---*/ -+/*------------------------------------------------------------*/ -+ -+/*----------------------------------------------------*/ -+/*--- Entry and preamble (set everything up) ---*/ -+/*----------------------------------------------------*/ -+ -+/* signature: -+void VG_(disp_run_translations)( UWord* two_words, -+ void* guest_state, -+ Addr host_addr ); -+*/ -+.text -+.global VG_(disp_run_translations) -+VG_(disp_run_translations): -+ /* x0 holds two_words -+ x1 holds guest_state -+ x2 holds host_addr -+ */ -+ /* Push the callee-saved registers. Unclear if x19/x20 are -+ callee-saved, but be on the safe side. Note this sequence -+ maintains 16-alignment of sp. Also save x0 since it will -+ be needed in the postamble. */ -+ stp x29, x30, [sp, #-16]! -+ stp x27, x28, [sp, #-16]! -+ stp x25, x26, [sp, #-16]! -+ stp x23, x24, [sp, #-16]! -+ stp x21, x22, [sp, #-16]! -+ stp x19, x20, [sp, #-16]! -+ stp x0, xzr, [sp, #-16]! -+ -+ /* set FPSCR to vex-required default value */ -+ // FIXME -+ // mov r4, #0 -+ // fmxr fpscr, r4 -+ -+ /* Set up the guest state pointer */ -+ mov x21, x1 -+ -+ /* and jump into the code cache. Chained translations in -+ the code cache run, until for whatever reason, they can't -+ continue. When that happens, the translation in question -+ will jump (or call) to one of the continuation points -+ VG_(cp_...) below. */ -+ br x2 -+ /* NOTREACHED */ -+ -+/*----------------------------------------------------*/ -+/*--- Postamble and exit. ---*/ -+/*----------------------------------------------------*/ -+ -+postamble: -+ /* At this point, r1 and r2 contain two -+ words to be returned to the caller. r1 -+ holds a TRC value, and r2 optionally may -+ hold another word (for CHAIN_ME exits, the -+ address of the place to patch.) */ -+ -+ /* We're leaving. Check that nobody messed with -+ FPSCR in ways we don't expect. */ -+ // FIXME -+ // fmrx r4, fpscr -+ // bic r4, #0xF8000000 /* mask out NZCV and QC */ -+ // bic r4, #0x0000009F /* mask out IDC,IXC,UFC,OFC,DZC,IOC */ -+ // cmp r4, #0 -+ // beq remove_frame /* we're OK */ -+ /* otherwise we have an invariant violation */ -+ // movw r1, #VG_TRC_INVARIANT_FAILED -+ // movw r2, #0 -+ /* fall through */ -+ -+remove_frame: -+ /* Restore int regs, including importantly x0 (two_words), -+ but not x1 */ -+ ldp x0, xzr, [sp], #16 -+ ldp x19, x20, [sp], #16 -+ ldp x21, x22, [sp], #16 -+ ldp x23, x24, [sp], #16 -+ ldp x25, x26, [sp], #16 -+ ldp x27, x28, [sp], #16 -+ ldp x29, x30, [sp], #16 -+ -+ /* Stash return values */ -+ str x1, [x0, #0] -+ str x2, [x0, #8] -+ ret -+ -+/*----------------------------------------------------*/ -+/*--- Continuation points ---*/ -+/*----------------------------------------------------*/ -+ -+/* ------ Chain me to slow entry point ------ */ -+.global VG_(disp_cp_chain_me_to_slowEP) -+VG_(disp_cp_chain_me_to_slowEP): -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_S, RA) */ -+ mov x1, #VG_TRC_CHAIN_ME_TO_SLOW_EP -+ mov x2, x30 // 30 == LR -+ /* 4 = movw x9, disp_cp_chain_me_to_slowEP[15:0] -+ 4 = movk x9, disp_cp_chain_me_to_slowEP[31:16], lsl 16 -+ 4 = movk x9, disp_cp_chain_me_to_slowEP[47:32], lsl 32 -+ 4 = movk x9, disp_cp_chain_me_to_slowEP[63:48], lsl 48 -+ 4 = blr x9 -+ */ -+ sub x2, x2, #4+4+4+4+4 -+ b postamble -+ -+/* ------ Chain me to fast entry point ------ */ -+.global VG_(disp_cp_chain_me_to_fastEP) -+VG_(disp_cp_chain_me_to_fastEP): -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_F, RA) */ -+ mov x1, #VG_TRC_CHAIN_ME_TO_FAST_EP -+ mov x2, x30 // 30 == LR -+ /* 4 = movw x9, disp_cp_chain_me_to_fastEP[15:0] -+ 4 = movk x9, disp_cp_chain_me_to_fastEP[31:16], lsl 16 -+ 4 = movk x9, disp_cp_chain_me_to_fastEP[47:32], lsl 32 -+ 4 = movk x9, disp_cp_chain_me_to_fastEP[63:48], lsl 48 -+ 4 = blr x9 -+ */ -+ sub x2, x2, #4+4+4+4+4 -+ b postamble -+ -+/* ------ Indirect but boring jump ------ */ -+.global VG_(disp_cp_xindir) -+VG_(disp_cp_xindir): -+ /* Where are we going? */ -+ ldr x0, [x21, #OFFSET_arm64_PC] -+ -+ /* stats only */ -+ adrp x1, VG_(stats__n_xindirs_32) -+ add x1, x1, :lo12:VG_(stats__n_xindirs_32) -+ ldr w2, [x1, #0] -+ add w2, w2, #1 -+ str w2, [x1, #0] -+ -+ /* try a fast lookup in the translation cache */ -+ // x0 = next guest, x1,x2,x3,x4 scratch -+ mov x1, #VG_TT_FAST_MASK // x1 = VG_TT_FAST_MASK -+ and x2, x1, x0, LSR #2 // x2 = entry # = (x1 & (x0 >> 2)) -+ -+ adrp x4, VG_(tt_fast) -+ add x4, x4, :lo12:VG_(tt_fast) // x4 = &VG_(tt_fast) -+ -+ add x1, x4, x2, LSL #4 // r1 = &tt_fast[entry#] -+ -+ ldp x4, x5, [x1, #0] // x4 = .guest, x5 = .host -+ -+ cmp x4, x0 -+ -+ // jump to host if lookup succeeded -+ bne fast_lookup_failed -+ br x5 -+ /*NOTREACHED*/ -+ -+fast_lookup_failed: -+ /* RM ME -- stats only */ -+ adrp x1, VG_(stats__n_xindir_misses_32) -+ add x1, x1, :lo12:VG_(stats__n_xindir_misses_32) -+ ldr w2, [x1, #0] -+ add w2, w2, #1 -+ str w2, [x1, #0] -+ -+ mov x1, #VG_TRC_INNER_FASTMISS -+ mov x2, #0 -+ b postamble -+ -+/* ------ Assisted jump ------ */ -+.global VG_(disp_cp_xassisted) -+VG_(disp_cp_xassisted): -+ /* x21 contains the TRC */ -+ mov x1, x21 -+ mov x2, #0 -+ b postamble -+ -+/* ------ Event check failed ------ */ -+.global VG_(disp_cp_evcheck_fail) -+VG_(disp_cp_evcheck_fail): -+ mov x1, #VG_TRC_INNER_COUNTERZERO -+ mov x2, #0 -+ b postamble -+ -+ -+.size VG_(disp_run_translations), .-VG_(disp_run_translations) -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",%progbits -+ -+#endif // defined(VGP_arm64_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end dispatch-arm64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_initimg/initimg-linux.c -=================================================================== ---- coregrind/m_initimg/initimg-linux.c.orig -+++ coregrind/m_initimg/initimg-linux.c -@@ -1052,7 +1052,7 @@ void VG_(ii_finalise_image)( IIFinaliseI - arch->vex.guest_GPR2 = iifii.initial_client_TOC; - arch->vex.guest_CIA = iifii.initial_client_IP; - --# elif defined(VGP_arm_linux) -+# elif defined(VGP_arm_linux) - /* Zero out the initial state, and set up the simulated FPU in a - sane way. */ - LibVEX_GuestARM_initialise(&arch->vex); -@@ -1068,6 +1068,17 @@ void VG_(ii_finalise_image)( IIFinaliseI - // FIXME jrs: what's this for? - arch->vex.guest_R1 = iifii.initial_client_SP; - -+# elif defined(VGP_arm64_linux) -+ /* Zero out the initial state. */ -+ LibVEX_GuestARM64_initialise(&arch->vex); -+ -+ /* Zero out the shadow areas. */ -+ VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestARM64State)); -+ VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestARM64State)); -+ -+ arch->vex.guest_SP = iifii.initial_client_SP; -+ arch->vex.guest_PC = iifii.initial_client_IP; -+ - # elif defined(VGP_s390x_linux) - vg_assert(0 == sizeof(VexGuestS390XState) % 16); - -Index: memcheck/mc_machine.c -=================================================================== ---- memcheck/mc_machine.c.orig -+++ memcheck/mc_machine.c -@@ -76,6 +76,11 @@ - # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARMState) - #endif - -+#if defined(VGA_arm64) -+# include "libvex_guest_arm64.h" -+# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARM64State) -+#endif -+ - #if defined(VGA_mips32) - # include "libvex_guest_mips32.h" - # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestMIPS32State) -@@ -957,6 +962,27 @@ static Int get_otrack_shadow_offset_wrk - # undef GOF - # undef SZB - -+ /* --------------------- arm64 --------------------- */ -+ -+# elif defined(VGA_arm64) -+ -+# define GOF(_fieldname) \ -+ (offsetof(VexGuestARM64State,guest_##_fieldname)) -+# define SZB(_fieldname) \ -+ (sizeof(((VexGuestARM64State*)0)->guest_##_fieldname)) -+ -+ Int o = offset; -+ Int sz = szB; -+ tl_assert(sz > 0); -+ tl_assert(host_is_little_endian()); -+ (void)o; // RMME -- just to stop gcc warning that o is unused -+ -+ VG_(printf)("MC_(get_otrack_shadow_offset)(arm64)(off=%d,sz=%d)\n", -+ offset,szB); -+ tl_assert(0); -+# undef GOF -+# undef SZB -+ - /* --------------------- mips32 --------------------- */ - - # elif defined(VGA_mips32) -@@ -1242,6 +1268,13 @@ IRType MC_(get_otrack_reg_array_equiv_in - ppIRRegArray(arr); - VG_(printf)("\n"); - tl_assert(0); -+ -+ /* --------------------- arm64 --------------------- */ -+# elif defined(VGA_arm64) -+ VG_(printf)("get_reg_array_equiv_int_type(arm64): unhandled: "); -+ ppIRRegArray(arr); -+ VG_(printf)("\n"); -+ tl_assert(0); - - /* --------------------- s390x --------------------- */ - # elif defined(VGA_s390x) -Index: Makefile.all.am -=================================================================== ---- Makefile.all.am.orig -+++ Makefile.all.am -@@ -156,6 +156,10 @@ AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @ - AM_CCASFLAGS_ARM_LINUX = @FLAG_M32@ \ - -marm -mcpu=cortex-a8 -g - -+AM_FLAG_M3264_ARM64_LINUX = @FLAG_M64@ -+AM_CFLAGS_ARM64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -+AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g -+ - AM_FLAG_M3264_X86_DARWIN = -arch i386 - AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \ - -mmacosx-version-min=10.5 \ -@@ -213,6 +217,7 @@ PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD - PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ - PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ -+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386 - PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64 - PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -Index: cachegrind/cg_branchpred.c -=================================================================== ---- cachegrind/cg_branchpred.c.orig -+++ cachegrind/cg_branchpred.c -@@ -44,12 +44,12 @@ - - /* How many bits at the bottom of an instruction address are - guaranteed to be zero? */ --#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm) \ -- || defined(VGA_mips32) || defined(VGA_mips64) -+#if defined(VGA_ppc32) || defined(VGA_ppc64) \ -+ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) - # define N_IADDR_LO_ZERO_BITS 2 - #elif defined(VGA_x86) || defined(VGA_amd64) - # define N_IADDR_LO_ZERO_BITS 0 --#elif defined(VGA_s390x) -+#elif defined(VGA_s390x) || defined(VGA_arm) - # define N_IADDR_LO_ZERO_BITS 1 - #else - # error "Unsupported architecture" -Index: cachegrind/cg_arch.c -=================================================================== ---- cachegrind/cg_arch.c.orig -+++ cachegrind/cg_arch.c -@@ -367,6 +367,14 @@ configure_caches(cache_t *I1c, cache_t * - *D1c = (cache_t) { 16384, 4, 64 }; - *LLc = (cache_t) { 262144, 8, 64 }; - -+#elif defined(VGA_arm64) -+ -+ // Copy the 32-bit ARM version until such time as we have -+ // some real hardware to run on -+ *I1c = (cache_t) { 16384, 4, 64 }; -+ *D1c = (cache_t) { 16384, 4, 64 }; -+ *LLc = (cache_t) { 262144, 8, 64 }; -+ - #elif defined(VGA_s390x) - // - // Here is the cache data from older machine models: -Index: ARM64_TIDYUPS.txt -=================================================================== ---- /dev/null -+++ ARM64_TIDYUPS.txt -@@ -0,0 +1,178 @@ -+ -+## HOW TO Cross-CONFIGURE -+ -+export CC=aarch64-linux-gnu-gcc -+export LD=aarch64-linux-gnu-ld -+export AR=aarch64-linux-gnu-ar -+ -+./autogen.sh -+./configure --prefix=`pwd`/Inst --host=aarch64-unknown-linux --enable-only64bit -+ -+############################################################## -+ -+UnwindStartRegs -- what should that contain? -+ -+ -+ -+vki-arm64-linux.h: vki_sigaction_base -+ -+I really don't think that __vki_sigrestore_t sa_restorer -+should be present. Adding it surely puts sa_mask at a wrong -+offset compared to (kernel) reality. But not having it causes -+compilation of m_signals.c to fail in hard to understand ways, -+so adding it temporarily. -+ -+ -+m_trampoline.S: what's the unexecutable-insn value? 0xFFFFFFFF -+is there at the moment, but 0x00000000 is probably what it should be. -+Also, fix indentation/tab-vs-space stuff -+ -+ -+./include/vki/vki-arm64-linux.h: uses __uint128_t. Should change -+it to __vki_uint128_t, but what's the defn of that? -+ -+ -+ -+m_debuginfo/priv_storage.h: need proper defn of DiCfSI -+ -+ -+readdwarf.c: is this correct? -+#elif defined(VGP_arm64_linux) -+# define FP_REG 29 //??? -+# define SP_REG 31 //??? -+# define RA_REG_DEFAULT 30 //??? -+ -+ -+vki-arm64-linux.h: -+re linux-3.10.5/include/uapi/asm-generic/sembuf.h -+I'd say the amd64 version has padding it shouldn't have. Check? -+ -+ -+ -+syswrap-linux.c run_a_thread_NORETURN assembly sections -+seems like tst->os_state.exitcode has word type -+in which case the ppc64_linux use of lwz to read it, is wrong -+ -+ -+ -+syswrap-linux.c ML_(do_fork_clone) -+assuming that VGP_arm64_linux is the same as VGP_arm_linux here -+ -+ -+ -+dispatch-arm64-linux.S: FIXME: set up FP control state before -+entering generated code. Also fix screwy indentation. -+ -+dispatcher-ery general: what's a good (predictor-friendly) way to -+branch to a register? -+ -+ -+ -+in vki-arm64-scnums.h -+//#if __BITS_PER_LONG == 64 && !defined(__SYSCALL_COMPAT) -+Probably want to reenable that and clean up accordingly -+ -+ -+ -+putIRegXXorZR: figure out a way that the computed value is actually -+used, so as to keep any memory reads that might generate it, alive. -+(else the simulation can lose exceptions). At least, for writes to -+the zero register generated by loads .. or .. can anything other -+integer instructions, that write to a register, cause exceptions? -+ -+ -+ -+loads/stores: generate stack alignment checks as necessary -+ -+ -+ -+fix barrier insns: ISB, DMB -+ -+ -+ -+fix atomic loads/stores -+ -+ -+ -+FMADD/FMSUB/FNMADD/FNMSUB: generate and use the relevant fused -+IROps so as to avoid double rounding -+ -+ -+ -+ARM64Instr_Call getRegUsage: re-check relative to what -+getAllocableRegs_ARM64 makes available -+ -+ -+ -+Make dispatch-arm64-linux.S save any callee-saved Q regs -+I think what is required is to save D8-D15 and nothing more than that. -+ -+ -+ -+wrapper for __NR3264_fstat -- correct? -+ -+ -+ -+PRE(sys_clone): get rid of references to vki_modify_ldt_t -+and the definition of it in vki-arm64-linux.h. Ditto for -+32 bit arm. -+ -+ -+ -+sigframe-arm64-linux.c: build_sigframe: references to nonexistent -+siguc->uc_mcontext.trap_no, siguc->uc_mcontext.error_code have been -+replaced by zero. Also in synth_ucontext. -+ -+ -+ -+m_debugger.c: -+uregs.pstate = LibVEX_GuestARM64_get_nzcv(vex); /* is this correct? */ -+Is that remotely correct? -+ -+ -+ -+host_arm64_defs.c: emit_ARM64INstr: -+ARM64in_VDfromX and ARM64in_VQfromXX: use simple top-half zeroing -+MOVs to vector registers instead of INS Vd.D[0], Xreg, to avoid false -+dependencies on the top half of the register. (Or at least check -+the semantocs of INS Vd.D[0] to see if it zeroes out the top.) -+ -+ -+ -+preferredVectorSubTypeFromSize: review perf effects and decide -+on a types-for-subparts policy -+ -+ -+ -+fold_IRExpr_Unop: add a reduction rule for this -+1Sto64(CmpNEZ64( Or64(GET:I64(1192),GET:I64(1184)) )) -+vis 1Sto64(CmpNEZ64(x)) --> CmpwNEZ64(x) -+ -+ -+ -+check insn selection for memcheck-only primops: -+Left64 CmpwNEZ64 V128to64 V128HIto64 1Sto64 CmpNEZ64 CmpNEZ32 -+widen_z_8_to_64 1Sto32 Left32 32HLto64 CmpwNEZ32 CmpNEZ8 -+ -+ -+ -+isel: get rid of various cases where zero is put into a register -+and just use xzr instead. Especially for CmpNEZ64/32. And for -+writing zeroes into the CC thunk fields. -+ -+ -+ -+/* Keep this list in sync with that in iselNext below */ -+/* Keep this list in sync with that for Ist_Exit above */ -+uh .. they are not in sync -+ -+ -+ -+very stupid: -+imm64 x23, 0xFFFFFFFFFFFFFFA0 -+17 F4 9F D2 F7 FF BF F2 F7 FF DF F2 F7 FF FF F2 -+ -+ -+ -+valgrind.h: fix VALGRIND_ALIGN_STACK/VALGRIND_RESTORE_STACK, -+also add CFI annotations -Index: include/pub_tool_machine.h -=================================================================== ---- include/pub_tool_machine.h.orig -+++ include/pub_tool_machine.h -@@ -67,6 +67,12 @@ - # define VG_CLREQ_SZB 20 - # define VG_STACK_REDZONE_SZB 0 - -+#elif defined(VGP_arm64_linux) -+# define VG_MIN_INSTR_SZB 4 -+# define VG_MAX_INSTR_SZB 4 -+# define VG_CLREQ_SZB 20 -+# define VG_STACK_REDZONE_SZB 0 -+ - #elif defined(VGP_s390x_linux) - # define VG_MIN_INSTR_SZB 2 - # define VG_MAX_INSTR_SZB 6 -@@ -124,14 +130,6 @@ VG_(set_shadow_regs_area) ( ThreadId tid - /*DST*/Int shadowNo, PtrdiffT offset, SizeT size, - /*SRC*/const UChar* src ); - --// Sets the shadow values for the syscall return value register(s). --// This is platform specific. --void VG_(set_syscall_return_shadows) ( ThreadId tid, -- /* shadow vals for the result */ -- UWord s1res, UWord s2res, -- /* shadow vals for the error val */ -- UWord s1err, UWord s2err ); -- - // Apply a function 'f' to all the general purpose registers in all the - // current threads. This is all live threads, or (when the process is exiting) - // all threads that were instructed to die by the thread calling exit. -Index: include/vki/vki-arm64-linux.h -=================================================================== ---- /dev/null -+++ include/vki/vki-arm64-linux.h -@@ -0,0 +1,678 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- ARM64/Linux-specific kernel interface. vki-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VKI_ARM64_LINUX_H -+#define __VKI_ARM64_LINUX_H -+ -+// ARM64 is little-endian. -+#define VKI_LITTLE_ENDIAN 1 -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/int-ll64.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned char __vki_u8; -+ -+typedef __signed__ short __vki_s16; -+typedef unsigned short __vki_u16; -+ -+typedef __signed__ int __vki_s32; -+typedef unsigned int __vki_u32; -+ -+typedef __signed__ long long __vki_s64; -+typedef unsigned long long __vki_u64; -+ -+typedef unsigned short vki_u16; -+ -+typedef unsigned int vki_u32; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/arch/arm64/include/asm/page.h -+//---------------------------------------------------------------------- -+ -+/* Looks like arm64 can do both 4k and 64k pages, so we -+ use the at-startup detection scheme that ppc32/64 do. */ -+extern UWord VKI_PAGE_SHIFT; -+extern UWord VKI_PAGE_SIZE; -+#define VKI_MAX_PAGE_SHIFT 16 -+#define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/arch/arm64/include/asm/shmparam.h -+//---------------------------------------------------------------------- -+ -+// Trying to make sense of this .. it seems as if, for doing -+// shared memory with 64 bit processes, VKI_PAGE_SIZE is good -+// enough. But if sharing with a 32 bit process then we need -+// the old-style 16k value (4 * VKI_PAGE_SIZE) to be safe. -+// (From reading between the lines of arch/arm64/include/asm/shmparam.h) -+#define VKI_SHMLBA (4 * VKI_PAGE_SIZE) -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/signal.h -+//---------------------------------------------------------------------- -+ -+#define _VKI_NSIG 64 -+#define _VKI_NSIG_BPW 64 -+#define _VKI_NSIG_WORDS (_VKI_NSIG / _VKI_NSIG_BPW) -+ -+typedef unsigned long vki_old_sigset_t; -+ -+typedef struct { -+ unsigned long sig[_VKI_NSIG_WORDS]; -+} vki_sigset_t; -+ -+#define VKI_SIGHUP 1 -+#define VKI_SIGINT 2 -+#define VKI_SIGQUIT 3 -+#define VKI_SIGILL 4 -+#define VKI_SIGTRAP 5 -+#define VKI_SIGABRT 6 -+#define VKI_SIGBUS 7 -+#define VKI_SIGFPE 8 -+#define VKI_SIGKILL 9 -+#define VKI_SIGUSR1 10 -+#define VKI_SIGSEGV 11 -+#define VKI_SIGUSR2 12 -+#define VKI_SIGPIPE 13 -+#define VKI_SIGALRM 14 -+#define VKI_SIGTERM 15 -+#define VKI_SIGSTKFLT 16 -+#define VKI_SIGCHLD 17 -+#define VKI_SIGCONT 18 -+#define VKI_SIGSTOP 19 -+#define VKI_SIGTSTP 20 -+#define VKI_SIGTTIN 21 -+#define VKI_SIGTTOU 22 -+#define VKI_SIGURG 23 -+#define VKI_SIGXCPU 24 -+#define VKI_SIGXFSZ 25 -+#define VKI_SIGVTALRM 26 -+#define VKI_SIGPROF 27 -+#define VKI_SIGWINCH 28 -+#define VKI_SIGIO 29 -+#define VKI_SIGPWR 30 -+#define VKI_SIGSYS 31 -+#define VKI_SIGUNUSED 31 -+ -+#define VKI_SIGRTMIN 32 -+#define VKI_SIGRTMAX _VKI_NSIG -+ -+#define VKI_SA_NOCLDSTOP 0x00000001 -+#define VKI_SA_NOCLDWAIT 0x00000002 -+#define VKI_SA_SIGINFO 0x00000004 -+#define VKI_SA_ONSTACK 0x08000000 -+#define VKI_SA_RESTART 0x10000000 -+#define VKI_SA_NODEFER 0x40000000 -+#define VKI_SA_RESETHAND 0x80000000 -+ -+#define VKI_SA_NOMASK VKI_SA_NODEFER -+#define VKI_SA_ONESHOT VKI_SA_RESETHAND -+ -+// This is obsolete and should not be defined for new archs -+#define VKI_SA_RESTORER 0x04000000 -+ -+#define VKI_SS_ONSTACK 1 -+#define VKI_SS_DISABLE 2 -+ -+#define VKI_MINSIGSTKSZ 2048 -+ -+#define VKI_SIG_BLOCK 0 /* for blocking signals */ -+#define VKI_SIG_UNBLOCK 1 /* for unblocking signals */ -+#define VKI_SIG_SETMASK 2 /* for setting the signal mask */ -+ -+typedef void __vki_signalfn_t(int); -+typedef __vki_signalfn_t __user *__vki_sighandler_t; -+ -+typedef void __vki_restorefn_t(void); -+typedef __vki_restorefn_t __user *__vki_sigrestore_t; -+ -+#define VKI_SIG_DFL ((__vki_sighandler_t)0) /* default signal handling */ -+#define VKI_SIG_IGN ((__vki_sighandler_t)1) /* ignore signal */ -+ -+struct vki_sigaction_base { -+ // [[Nb: a 'k' prefix is added to "sa_handler" because -+ // bits/sigaction.h (which gets dragged in somehow via signal.h) -+ // #defines it as something else. Since that is done for glibc's -+ // purposes, which we don't care about here, we use our own name.]] -+ __vki_sighandler_t ksa_handler; -+ unsigned long sa_flags; -+ __vki_sigrestore_t sa_restorer; // I don't think arm64 has this -+ vki_sigset_t sa_mask; /* mask last for extensibility */ -+}; -+ -+/* On Linux we use the same type for passing sigactions to -+ and from the kernel. Hence: */ -+typedef struct vki_sigaction_base vki_sigaction_toK_t; -+typedef struct vki_sigaction_base vki_sigaction_fromK_t; -+ -+ -+typedef struct vki_sigaltstack { -+ void __user *ss_sp; -+ int ss_flags; -+ vki_size_t ss_size; -+} vki_stack_t; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/arch/arm64/include/uapi/asm/sigcontext.h -+//---------------------------------------------------------------------- -+ -+struct vki_sigcontext { -+ __vki_u64 fault_address; -+ /* AArch64 registers */ -+ __vki_u64 regs[31]; -+ __vki_u64 sp; -+ __vki_u64 pc; -+ __vki_u64 pstate; -+ /* 4K reserved for FP/SIMD state and future expansion */ -+ __vki_u8 __reserved[4096] __attribute__((__aligned__(16))); -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/uapi/include/asm-generic/mman-common.h -+//---------------------------------------------------------------------- -+ -+#define VKI_PROT_READ 0x1 /* page can be read */ -+#define VKI_PROT_WRITE 0x2 /* page can be written */ -+#define VKI_PROT_EXEC 0x4 /* page can be executed */ -+#define VKI_PROT_NONE 0x0 /* page can not be accessed */ -+#define VKI_PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ -+#define VKI_PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ -+ -+#define VKI_MAP_SHARED 0x01 /* Share changes */ -+#define VKI_MAP_PRIVATE 0x02 /* Changes are private */ -+#define VKI_MAP_FIXED 0x10 /* Interpret addr exactly */ -+#define VKI_MAP_ANONYMOUS 0x20 /* don't use a file */ -+#define VKI_MAP_NORESERVE 0x4000 /* don't check for reservations */ -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/uapi/include/asm-generic/fcntl.h -+//---------------------------------------------------------------------- -+ -+#define VKI_O_ACCMODE 03 -+#define VKI_O_RDONLY 00 -+#define VKI_O_WRONLY 01 -+#define VKI_O_RDWR 02 -+#define VKI_O_CREAT 0100 /* not fcntl */ -+#define VKI_O_EXCL 0200 /* not fcntl */ -+#define VKI_O_TRUNC 01000 /* not fcntl */ -+#define VKI_O_APPEND 02000 -+#define VKI_O_NONBLOCK 04000 -+#define VKI_O_LARGEFILE 0100000 -+ -+#define VKI_AT_FDCWD -100 -+ -+#define VKI_F_DUPFD 0 /* dup */ -+#define VKI_F_GETFD 1 /* get close_on_exec */ -+#define VKI_F_SETFD 2 /* set/clear close_on_exec */ -+#define VKI_F_GETFL 3 /* get file->f_flags */ -+#define VKI_F_SETFL 4 /* set file->f_flags */ -+#define VKI_F_GETLK 5 -+#define VKI_F_SETLK 6 -+#define VKI_F_SETLKW 7 -+ -+#define VKI_F_SETOWN 8 /* for sockets. */ -+#define VKI_F_GETOWN 9 /* for sockets. */ -+#define VKI_F_SETSIG 10 /* for sockets. */ -+#define VKI_F_GETSIG 11 /* for sockets. */ -+ -+#define VKI_F_SETOWN_EX 15 -+#define VKI_F_GETOWN_EX 16 -+ -+#define VKI_F_OWNER_TID 0 -+#define VKI_F_OWNER_PID 1 -+#define VKI_F_OWNER_PGRP 2 -+ -+struct vki_f_owner_ex { -+ int type; -+ __vki_kernel_pid_t pid; -+}; -+ -+#define VKI_FD_CLOEXEC 1 /* actually anything with low bit set goes */ -+ -+#define VKI_F_LINUX_SPECIFIC_BASE 1024 -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/resource.h -+//---------------------------------------------------------------------- -+ -+#define VKI_RLIMIT_DATA 2 /* max data size */ -+#define VKI_RLIMIT_STACK 3 /* max stack size */ -+#define VKI_RLIMIT_CORE 4 /* max core file size */ -+#define VKI_RLIMIT_NOFILE 7 /* max number of open files */ -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/socket.h -+//---------------------------------------------------------------------- -+ -+#define VKI_SOL_SOCKET 1 -+ -+#define VKI_SO_TYPE 3 -+ -+#define VKI_SO_ATTACH_FILTER 26 -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/sockios.h -+//---------------------------------------------------------------------- -+ -+#define VKI_SIOCSPGRP 0x8902 -+#define VKI_SIOCGPGRP 0x8904 -+#define VKI_SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -+#define VKI_SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/stat.h -+//---------------------------------------------------------------------- -+ -+struct vki_stat { -+ unsigned long st_dev; -+ unsigned long st_ino; -+ unsigned int st_mode; -+ unsigned int st_nlink; -+ unsigned int st_uid; -+ unsigned int st_gid; -+ unsigned long st_rdev; -+ unsigned long __pad1; -+ long st_size; -+ int st_blksize; -+ int __pad2; -+ long st_blocks; -+ long st_atime; -+ unsigned long st_atime_nsec; -+ long st_mtime; -+ unsigned long st_mtime_nsec; -+ long st_ctime; -+ unsigned long st_ctime_nsec; -+ unsigned int __unused4; -+ unsigned int __unused5; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/statfs.h -+//---------------------------------------------------------------------- -+ -+struct vki_statfs { -+ long f_type; -+ long f_bsize; -+ long f_blocks; -+ long f_bfree; -+ long f_bavail; -+ long f_files; -+ long f_ffree; -+ __vki_kernel_fsid_t f_fsid; -+ long f_namelen; -+ long f_frsize; -+ long f_flags; -+ long f_spare[4]; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/termios.h -+//---------------------------------------------------------------------- -+ -+struct vki_winsize { -+ unsigned short ws_row; -+ unsigned short ws_col; -+ unsigned short ws_xpixel; -+ unsigned short ws_ypixel; -+}; -+ -+#define VKI_NCC 8 -+struct vki_termio { -+ unsigned short c_iflag; /* input mode flags */ -+ unsigned short c_oflag; /* output mode flags */ -+ unsigned short c_cflag; /* control mode flags */ -+ unsigned short c_lflag; /* local mode flags */ -+ unsigned char c_line; /* line discipline */ -+ unsigned char c_cc[VKI_NCC]; /* control characters */ -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/termbits.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned char vki_cc_t; -+typedef unsigned int vki_tcflag_t; -+ -+#define VKI_NCCS 19 -+struct vki_termios { -+ vki_tcflag_t c_iflag; /* input mode flags */ -+ vki_tcflag_t c_oflag; /* output mode flags */ -+ vki_tcflag_t c_cflag; /* control mode flags */ -+ vki_tcflag_t c_lflag; /* local mode flags */ -+ vki_cc_t c_line; /* line discipline */ -+ vki_cc_t c_cc[VKI_NCCS]; /* control characters */ -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/ioctl.h -+//---------------------------------------------------------------------- -+ -+#define _VKI_IOC_NRBITS 8 -+#define _VKI_IOC_TYPEBITS 8 -+#define _VKI_IOC_SIZEBITS 14 -+#define _VKI_IOC_DIRBITS 2 -+ -+#define _VKI_IOC_SIZEMASK ((1 << _VKI_IOC_SIZEBITS)-1) -+#define _VKI_IOC_DIRMASK ((1 << _VKI_IOC_DIRBITS)-1) -+ -+#define _VKI_IOC_NRSHIFT 0 -+#define _VKI_IOC_TYPESHIFT (_VKI_IOC_NRSHIFT+_VKI_IOC_NRBITS) -+#define _VKI_IOC_SIZESHIFT (_VKI_IOC_TYPESHIFT+_VKI_IOC_TYPEBITS) -+#define _VKI_IOC_DIRSHIFT (_VKI_IOC_SIZESHIFT+_VKI_IOC_SIZEBITS) -+ -+#define _VKI_IOC_NONE 0U -+#define _VKI_IOC_WRITE 1U -+#define _VKI_IOC_READ 2U -+ -+#define _VKI_IOC(dir,type,nr,size) \ -+ (((dir) << _VKI_IOC_DIRSHIFT) | \ -+ ((type) << _VKI_IOC_TYPESHIFT) | \ -+ ((nr) << _VKI_IOC_NRSHIFT) | \ -+ ((size) << _VKI_IOC_SIZESHIFT)) -+ -+#define _VKI_IO(type,nr) _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0) -+#define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),sizeof(size)) -+#define _VKI_IOW(type,nr,size) _VKI_IOC(_VKI_IOC_WRITE,(type),(nr),sizeof(size)) -+#define _VKI_IOWR(type,nr,size) _VKI_IOC(_VKI_IOC_READ|_VKI_IOC_WRITE,(type),(nr),sizeof(size)) -+ -+#define _VKI_IOC_DIR(nr) (((nr) >> _VKI_IOC_DIRSHIFT) & _VKI_IOC_DIRMASK) -+#define _VKI_IOC_SIZE(nr) (((nr) >> _VKI_IOC_SIZESHIFT) & _VKI_IOC_SIZEMASK) -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/ioctls.h -+//---------------------------------------------------------------------- -+ -+#define VKI_TCGETS 0x5401 -+#define VKI_TCSETS 0x5402 -+#define VKI_TCSETSW 0x5403 -+#define VKI_TCSETSF 0x5404 -+#define VKI_TCGETA 0x5405 -+#define VKI_TCSETA 0x5406 -+#define VKI_TCSETAW 0x5407 -+#define VKI_TCSETAF 0x5408 -+#define VKI_TCSBRK 0x5409 -+#define VKI_TCXONC 0x540A -+#define VKI_TCFLSH 0x540B -+#define VKI_TIOCSCTTY 0x540E -+#define VKI_TIOCGPGRP 0x540F -+#define VKI_TIOCSPGRP 0x5410 -+#define VKI_TIOCOUTQ 0x5411 -+#define VKI_TIOCGWINSZ 0x5413 -+#define VKI_TIOCSWINSZ 0x5414 -+#define VKI_TIOCMGET 0x5415 -+#define VKI_TIOCMBIS 0x5416 -+#define VKI_TIOCMBIC 0x5417 -+#define VKI_TIOCMSET 0x5418 -+#define VKI_FIONREAD 0x541B -+#define VKI_TIOCLINUX 0x541C -+#define VKI_FIONBIO 0x5421 -+#define VKI_TCSBRKP 0x5425 -+#define VKI_TIOCGPTN _VKI_IOR('T',0x30, unsigned int) -+#define VKI_TIOCSPTLCK _VKI_IOW('T',0x31, int) -+ -+#define VKI_FIONCLEX 0x5450 -+#define VKI_FIOCLEX 0x5451 -+#define VKI_FIOASYNC 0x5452 -+#define VKI_TIOCSERGETLSR 0x5459 -+ -+#define VKI_TIOCGICOUNT 0x545D -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/poll.h -+//---------------------------------------------------------------------- -+ -+#define VKI_POLLIN 0x0001 -+ -+struct vki_pollfd { -+ int fd; -+ short events; -+ short revents; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/arch/arm64/include/uapi/asm/ptrace.h -+//---------------------------------------------------------------------- -+ -+//ZZ struct vki_user_i387_struct { -+//ZZ unsigned short cwd; -+//ZZ unsigned short swd; -+//ZZ unsigned short twd; /* Note this is not the same as the 32bit/x87/FSAVE twd */ -+//ZZ unsigned short fop; -+//ZZ __vki_u64 rip; -+//ZZ __vki_u64 rdp; -+//ZZ __vki_u32 mxcsr; -+//ZZ __vki_u32 mxcsr_mask; -+//ZZ __vki_u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ -+//ZZ __vki_u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ -+//ZZ __vki_u32 padding[24]; -+//ZZ }; -+//ZZ -+//ZZ struct vki_user_regs_struct { -+//ZZ unsigned long r15,r14,r13,r12,rbp,rbx,r11,r10; -+//ZZ unsigned long r9,r8,rax,rcx,rdx,rsi,rdi,orig_rax; -+//ZZ unsigned long rip,cs,eflags; -+//ZZ unsigned long rsp,ss; -+//ZZ unsigned long fs_base, gs_base; -+//ZZ unsigned long ds,es,fs,gs; -+//ZZ }; -+ -+struct vki_user_pt_regs { -+ __vki_u64 regs[31]; -+ __vki_u64 sp; -+ __vki_u64 pc; -+ __vki_u64 pstate; -+}; -+ -+/* I think that the new name in the kernel for these is "user_pt_regs" -+ and the old name is "user_regs_struct". Unfortunately can't clone -+ a 'struct' type using 'typedef' and still have a 'struct' type, so -+ use a blunter instrument instead. */ -+#define vki_user_regs_struct vki_user_pt_regs -+ -+struct vki_user_fpsimd_state { -+ __uint128_t vregs[32]; -+ __vki_u32 fpsr; -+ __vki_u32 fpcr; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/arch/arm64/include/asm/elf.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned long vki_elf_greg_t; -+ -+#define VKI_ELF_NGREG (sizeof (struct vki_user_pt_regs) / sizeof(vki_elf_greg_t)) -+typedef vki_elf_greg_t vki_elf_gregset_t[VKI_ELF_NGREG]; -+ -+typedef struct vki_user_fpsimd_state vki_elf_fpregset_t; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/ucontext.h -+//---------------------------------------------------------------------- -+ -+struct vki_ucontext { -+ unsigned long uc_flags; -+ struct vki_ucontext *uc_link; -+ vki_stack_t uc_stack; -+ struct vki_sigcontext uc_mcontext; -+ vki_sigset_t uc_sigmask; -+}; -+ -+//ZZ //---------------------------------------------------------------------- -+//ZZ // From linux-2.6.9/include/asm-x86_64/segment.h -+//ZZ //---------------------------------------------------------------------- -+//ZZ -+//ZZ #define VKI_GDT_ENTRY_TLS_ENTRIES 3 -+//ZZ -+//ZZ #define VKI_GDT_ENTRY_TLS_MIN 11 -+//ZZ #define VKI_GDT_ENTRY_TLS_MAX 13 -+//ZZ -+//ZZ //---------------------------------------------------------------------- -+//ZZ // From linux-2.6.11.9/include/asm-x86_64/prctl.h -+//ZZ //---------------------------------------------------------------------- -+//ZZ -+//ZZ #define VKI_ARCH_SET_GS 0x1001 -+//ZZ #define VKI_ARCH_SET_FS 0x1002 -+//ZZ #define VKI_ARCH_GET_FS 0x1003 -+//ZZ #define VKI_ARCH_GET_GS 0x1004 -+//ZZ -+//ZZ //---------------------------------------------------------------------- -+//ZZ // From linux-2.6.9/include/asm-x86_64/ldt.h -+//ZZ //---------------------------------------------------------------------- -+//ZZ -+//ZZ // I think this LDT stuff will have to be reinstated for amd64, but I'm not -+//ZZ // certain. (Nb: The sys_arch_prctl seems to have replaced -+//ZZ // [gs]et_thread_area syscalls.) -+//ZZ // -+//ZZ // Note that the type here is very slightly different to the -+//ZZ // type for x86 (the final 'lm' field is added); I'm not sure about the -+//ZZ // significance of that... --njn -+//ZZ -+//ZZ /* [[Nb: This is the structure passed to the modify_ldt syscall. Just so as -+//ZZ to confuse and annoy everyone, this is _not_ the same as an -+//ZZ VgLdtEntry and has to be translated into such. The logic for doing -+//ZZ so, in vg_ldt.c, is copied from the kernel sources.]] */ -+//ZZ /* Note also that a comment in ldt.h indicates that the below -+//ZZ contains several fields ignored on 64bit, and that modify_ldt -+//ZZ is rather for 32bit. */ -+//ZZ struct vki_user_desc { -+//ZZ unsigned int entry_number; -+//ZZ unsigned long base_addr; -+//ZZ unsigned int limit; -+//ZZ unsigned int seg_32bit:1; -+//ZZ unsigned int contents:2; -+//ZZ unsigned int read_exec_only:1; -+//ZZ unsigned int limit_in_pages:1; -+//ZZ unsigned int seg_not_present:1; -+//ZZ unsigned int useable:1; -+//ZZ unsigned int lm:1; -+//ZZ }; -+//ZZ -+//ZZ // [[Nb: for our convenience within Valgrind, use a more specific name]] -+//ZZ typedef struct vki_user_desc vki_modify_ldt_t; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/asm-generic/ipcbuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_ipc64_perm -+{ -+ __vki_kernel_key_t key; -+ __vki_kernel_uid32_t uid; -+ __vki_kernel_gid32_t gid; -+ __vki_kernel_uid32_t cuid; -+ __vki_kernel_gid32_t cgid; -+ __vki_kernel_mode_t mode; -+ unsigned char __pad1[4 - sizeof(__vki_kernel_mode_t)]; -+ unsigned short seq; -+ unsigned short __pad2; -+ unsigned long __unused1; -+ unsigned long __unused2; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/sembuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_semid64_ds { -+ struct vki_ipc64_perm sem_perm; /* permissions .. see ipc.h */ -+ __vki_kernel_time_t sem_otime; /* last semop time */ -+ __vki_kernel_time_t sem_ctime; /* last change time */ -+ unsigned long sem_nsems; /* no. of semaphores in array */ -+ unsigned long __unused3; -+ unsigned long __unused4; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/msgbuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_msqid64_ds { -+ struct vki_ipc64_perm msg_perm; -+ __vki_kernel_time_t msg_stime; /* last msgsnd time */ -+ __vki_kernel_time_t msg_rtime; /* last msgrcv time */ -+ __vki_kernel_time_t msg_ctime; /* last change time */ -+ unsigned long msg_cbytes; /* current number of bytes on queue */ -+ unsigned long msg_qnum; /* number of messages in queue */ -+ unsigned long msg_qbytes; /* max number of bytes on queue */ -+ __vki_kernel_pid_t msg_lspid; /* pid of last msgsnd */ -+ __vki_kernel_pid_t msg_lrpid; /* last receive pid */ -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.10.5/include/uapi/asm-generic/shmbuf.h -+//---------------------------------------------------------------------- -+ -+struct vki_shmid64_ds { -+ struct vki_ipc64_perm shm_perm; /* operation perms */ -+ vki_size_t shm_segsz; /* size of segment (bytes) */ -+ __vki_kernel_time_t shm_atime; /* last attach time */ -+ __vki_kernel_time_t shm_dtime; /* last detach time */ -+ __vki_kernel_time_t shm_ctime; /* last change time */ -+ __vki_kernel_pid_t shm_cpid; /* pid of creator */ -+ __vki_kernel_pid_t shm_lpid; /* pid of last operator */ -+ unsigned long shm_nattch; /* no. of current attaches */ -+ unsigned long __unused4; -+ unsigned long __unused5; -+}; -+ -+struct vki_shminfo64 { -+ unsigned long shmmax; -+ unsigned long shmmin; -+ unsigned long shmmni; -+ unsigned long shmseg; -+ unsigned long shmall; -+ unsigned long __unused1; -+ unsigned long __unused2; -+ unsigned long __unused3; -+ unsigned long __unused4; -+}; -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/arch/arm64/include/asm/ptrace.h -+//---------------------------------------------------------------------- -+ -+#define VKI_PTRACE_GETREGS 12 -+#define VKI_PTRACE_SETREGS 13 -+//#define VKI_PTRACE_GETFPREGS 14 -+//#define VKI_PTRACE_SETFPREGS 15 -+ -+//---------------------------------------------------------------------- -+// And that's it! -+//---------------------------------------------------------------------- -+ -+#endif // __VKI_ARM64_LINUX_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/vki/vki-ppc64-linux.h -=================================================================== ---- include/vki/vki-ppc64-linux.h.orig -+++ include/vki/vki-ppc64-linux.h -@@ -64,8 +64,8 @@ typedef unsigned int vki_u32; - - /* PAGE_SHIFT determines the page size, unfortunately - page size might vary between 32-bit and 64-bit ppc kernels */ --extern unsigned long VKI_PAGE_SHIFT; --extern unsigned long VKI_PAGE_SIZE; -+extern UWord VKI_PAGE_SHIFT; -+extern UWord VKI_PAGE_SIZE; - #define VKI_MAX_PAGE_SHIFT 16 - #define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) - -Index: include/vki/vki-linux.h -=================================================================== ---- include/vki/vki-linux.h.orig -+++ include/vki/vki-linux.h -@@ -89,6 +89,8 @@ - # include "vki-posixtypes-ppc64-linux.h" - #elif defined(VGA_arm) - # include "vki-posixtypes-arm-linux.h" -+#elif defined(VGA_arm64) -+# include "vki-posixtypes-arm64-linux.h" - #elif defined(VGA_s390x) - # include "vki-posixtypes-s390x-linux.h" - #elif defined(VGA_mips32) -@@ -213,6 +215,8 @@ typedef unsigned int vki_uint; - # include "vki-ppc64-linux.h" - #elif defined(VGA_arm) - # include "vki-arm-linux.h" -+#elif defined(VGA_arm64) -+# include "vki-arm64-linux.h" - #elif defined(VGA_s390x) - # include "vki-s390x-linux.h" - #elif defined(VGA_mips32) -Index: include/vki/vki-posixtypes-arm64-linux.h -=================================================================== ---- /dev/null -+++ include/vki/vki-posixtypes-arm64-linux.h -@@ -0,0 +1,68 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- arm64/Linux-specific kernel interface: posix types. ---*/ -+/*--- vki-posixtypes-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VKI_POSIXTYPES_ARM64_LINUX_H -+#define __VKI_POSIXTYPES_ARM64_LINUX_H -+ -+//---------------------------------------------------------------------- -+// From linux-3.9.9/include/uapi/asm-generic/posix_types.h -+//---------------------------------------------------------------------- -+ -+typedef unsigned int __vki_kernel_mode_t; -+typedef long __vki_kernel_off_t; -+typedef int __vki_kernel_pid_t; -+typedef int __vki_kernel_ipc_pid_t; -+typedef unsigned int __vki_kernel_uid_t; -+typedef unsigned int __vki_kernel_gid_t; -+typedef unsigned long __vki_kernel_size_t; -+typedef long __vki_kernel_time_t; -+typedef long __vki_kernel_suseconds_t; -+typedef long __vki_kernel_clock_t; -+typedef int __vki_kernel_timer_t; -+typedef int __vki_kernel_clockid_t; -+typedef char * __vki_kernel_caddr_t; -+typedef unsigned int __vki_kernel_uid32_t; -+typedef unsigned int __vki_kernel_gid32_t; -+ -+typedef unsigned int __vki_kernel_old_uid_t; -+typedef unsigned int __vki_kernel_old_gid_t; -+ -+typedef long long __vki_kernel_loff_t; -+ -+typedef struct { -+ int val[2]; -+} __vki_kernel_fsid_t; -+ -+#endif // __VKI_POSIXTYPES_ARM64_LINUX_H -+ -+/*--------------------------------------------------------------------*/ -+/*--- end vki-posixtypes-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/vki/vki-ppc32-linux.h -=================================================================== ---- include/vki/vki-ppc32-linux.h.orig -+++ include/vki/vki-ppc32-linux.h -@@ -63,8 +63,8 @@ typedef struct { - - /* PAGE_SHIFT determines the page size, unfortunately - page size might vary between 32-bit and 64-bit ppc kernels */ --extern unsigned long VKI_PAGE_SHIFT; --extern unsigned long VKI_PAGE_SIZE; -+extern UWord VKI_PAGE_SHIFT; -+extern UWord VKI_PAGE_SIZE; - #define VKI_MAX_PAGE_SHIFT 16 - #define VKI_MAX_PAGE_SIZE (1UL << VKI_MAX_PAGE_SHIFT) - -Index: include/vki/vki-scnums-arm64-linux.h -=================================================================== ---- /dev/null -+++ include/vki/vki-scnums-arm64-linux.h -@@ -0,0 +1,510 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- System call numbers for arm64-linux. ---*/ -+/*--- vki-scnums-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2013-2013 OpenWorks -+ info@open-works.net -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#ifndef __VKI_SCNUMS_ARM64_LINUX_H -+#define __VKI_SCNUMS_ARM64_LINUX_H -+ -+// From linux-3.10.5/arch/arm64/include/uapi/asm/unistd.h -+// is a #include of -+// linux-3.10.5/include/uapi/asm-generic/unistd.h -+ -+#define __NR_io_setup 0 -+#define __NR_io_destroy 1 -+#define __NR_io_submit 2 -+#define __NR_io_cancel 3 -+#define __NR_io_getevents 4 -+#define __NR_setxattr 5 -+#define __NR_lsetxattr 6 -+#define __NR_fsetxattr 7 -+#define __NR_getxattr 8 -+#define __NR_lgetxattr 9 -+#define __NR_fgetxattr 10 -+#define __NR_listxattr 11 -+#define __NR_llistxattr 12 -+#define __NR_flistxattr 13 -+#define __NR_removexattr 14 -+#define __NR_lremovexattr 15 -+#define __NR_fremovexattr 16 -+#define __NR_getcwd 17 -+#define __NR_lookup_dcookie 18 -+#define __NR_eventfd2 19 -+#define __NR_epoll_create1 20 -+#define __NR_epoll_ctl 21 -+#define __NR_epoll_pwait 22 -+#define __NR_dup 23 -+#define __NR_dup3 24 -+#define __NR3264_fcntl 25 -+#define __NR_inotify_init1 26 -+#define __NR_inotify_add_watch 27 -+#define __NR_inotify_rm_watch 28 -+#define __NR_ioctl 29 -+#define __NR_ioprio_set 30 -+#define __NR_ioprio_get 31 -+#define __NR_flock 32 -+#define __NR_mknodat 33 -+#define __NR_mkdirat 34 -+#define __NR_unlinkat 35 -+#define __NR_symlinkat 36 -+#define __NR_linkat 37 -+#define __NR_renameat 38 -+#define __NR_umount2 39 -+#define __NR_mount 40 -+#define __NR_pivot_root 41 -+#define __NR_nfsservctl 42 -+#define __NR3264_statfs 43 -+#define __NR3264_fstatfs 44 -+#define __NR3264_truncate 45 -+#define __NR3264_ftruncate 46 -+#define __NR_fallocate 47 -+#define __NR_faccessat 48 -+#define __NR_chdir 49 -+#define __NR_fchdir 50 -+#define __NR_chroot 51 -+#define __NR_fchmod 52 -+#define __NR_fchmodat 53 -+#define __NR_fchownat 54 -+#define __NR_fchown 55 -+#define __NR_openat 56 -+#define __NR_close 57 -+#define __NR_vhangup 58 -+#define __NR_pipe2 59 -+#define __NR_quotactl 60 -+#define __NR_getdents64 61 -+#define __NR3264_lseek 62 -+#define __NR_read 63 -+#define __NR_write 64 -+#define __NR_readv 65 -+#define __NR_writev 66 -+#define __NR_pread64 67 -+#define __NR_pwrite64 68 -+#define __NR_preadv 69 -+#define __NR_pwritev 70 -+#define __NR3264_sendfile 71 -+#define __NR_pselect6 72 -+#define __NR_ppoll 73 -+#define __NR_signalfd4 74 -+#define __NR_vmsplice 75 -+#define __NR_splice 76 -+#define __NR_tee 77 -+#define __NR_readlinkat 78 -+#define __NR3264_fstatat 79 -+#define __NR3264_fstat 80 -+#define __NR_sync 81 -+#define __NR_fsync 82 -+#define __NR_fdatasync 83 -+ -+//#ifdef __ARCH_WANT_SYNC_FILE_RANGE2 -+//#define __NR_sync_file_range2 84 -+//#else -+#define __NR_sync_file_range 84 -+//#endif -+ -+#define __NR_timerfd_create 85 -+#define __NR_timerfd_settime 86 -+#define __NR_timerfd_gettime 87 -+#define __NR_utimensat 88 -+#define __NR_acct 89 -+#define __NR_capget 90 -+#define __NR_capset 91 -+#define __NR_personality 92 -+#define __NR_exit 93 -+#define __NR_exit_group 94 -+#define __NR_waitid 95 -+#define __NR_set_tid_address 96 -+#define __NR_unshare 97 -+#define __NR_futex 98 -+#define __NR_set_robust_list 99 -+#define __NR_get_robust_list 100 -+#define __NR_nanosleep 101 -+#define __NR_getitimer 102 -+#define __NR_setitimer 103 -+#define __NR_kexec_load 104 -+#define __NR_init_module 105 -+#define __NR_delete_module 106 -+#define __NR_timer_create 107 -+#define __NR_timer_gettime 108 -+#define __NR_timer_getoverrun 109 -+#define __NR_timer_settime 110 -+#define __NR_timer_delete 111 -+#define __NR_clock_settime 112 -+#define __NR_clock_gettime 113 -+#define __NR_clock_getres 114 -+#define __NR_clock_nanosleep 115 -+#define __NR_syslog 116 -+#define __NR_ptrace 117 -+#define __NR_sched_setparam 118 -+#define __NR_sched_setscheduler 119 -+#define __NR_sched_getscheduler 120 -+#define __NR_sched_getparam 121 -+#define __NR_sched_setaffinity 122 -+#define __NR_sched_getaffinity 123 -+#define __NR_sched_yield 124 -+#define __NR_sched_get_priority_max 125 -+#define __NR_sched_get_priority_min 126 -+#define __NR_sched_rr_get_interval 127 -+#define __NR_restart_syscall 128 -+#define __NR_kill 129 -+#define __NR_tkill 130 -+#define __NR_tgkill 131 -+#define __NR_sigaltstack 132 -+#define __NR_rt_sigsuspend 133 -+#define __NR_rt_sigaction 134 -+#define __NR_rt_sigprocmask 135 -+#define __NR_rt_sigpending 136 -+#define __NR_rt_sigtimedwait 137 -+#define __NR_rt_sigqueueinfo 138 -+#define __NR_rt_sigreturn 139 -+#define __NR_setpriority 140 -+#define __NR_getpriority 141 -+#define __NR_reboot 142 -+#define __NR_setregid 143 -+#define __NR_setgid 144 -+#define __NR_setreuid 145 -+#define __NR_setuid 146 -+#define __NR_setresuid 147 -+#define __NR_getresuid 148 -+#define __NR_setresgid 149 -+#define __NR_getresgid 150 -+#define __NR_setfsuid 151 -+#define __NR_setfsgid 152 -+#define __NR_times 153 -+#define __NR_setpgid 154 -+#define __NR_getpgid 155 -+#define __NR_getsid 156 -+#define __NR_setsid 157 -+#define __NR_getgroups 158 -+#define __NR_setgroups 159 -+#define __NR_uname 160 -+#define __NR_sethostname 161 -+#define __NR_setdomainname 162 -+#define __NR_getrlimit 163 -+#define __NR_setrlimit 164 -+#define __NR_getrusage 165 -+#define __NR_umask 166 -+#define __NR_prctl 167 -+#define __NR_getcpu 168 -+#define __NR_gettimeofday 169 -+#define __NR_settimeofday 170 -+#define __NR_adjtimex 171 -+#define __NR_getpid 172 -+#define __NR_getppid 173 -+#define __NR_getuid 174 -+#define __NR_geteuid 175 -+#define __NR_getgid 176 -+#define __NR_getegid 177 -+#define __NR_gettid 178 -+#define __NR_sysinfo 179 -+#define __NR_mq_open 180 -+#define __NR_mq_unlink 181 -+#define __NR_mq_timedsend 182 -+#define __NR_mq_timedreceive 183 -+#define __NR_mq_notify 184 -+#define __NR_mq_getsetattr 185 -+#define __NR_msgget 186 -+#define __NR_msgctl 187 -+#define __NR_msgrcv 188 -+#define __NR_msgsnd 189 -+#define __NR_semget 190 -+#define __NR_semctl 191 -+#define __NR_semtimedop 192 -+#define __NR_semop 193 -+#define __NR_shmget 194 -+#define __NR_shmctl 195 -+#define __NR_shmat 196 -+#define __NR_shmdt 197 -+#define __NR_socket 198 -+#define __NR_socketpair 199 -+#define __NR_bind 200 -+#define __NR_listen 201 -+#define __NR_accept 202 -+#define __NR_connect 203 -+#define __NR_getsockname 204 -+#define __NR_getpeername 205 -+#define __NR_sendto 206 -+#define __NR_recvfrom 207 -+#define __NR_setsockopt 208 -+#define __NR_getsockopt 209 -+#define __NR_shutdown 210 -+#define __NR_sendmsg 211 -+#define __NR_recvmsg 212 -+#define __NR_readahead 213 -+#define __NR_brk 214 -+#define __NR_munmap 215 -+#define __NR_mremap 216 -+#define __NR_add_key 217 -+#define __NR_request_key 218 -+#define __NR_keyctl 219 -+#define __NR_clone 220 -+#define __NR_execve 221 -+#define __NR3264_mmap 222 -+#define __NR3264_fadvise64 223 -+#define __NR_swapon 224 -+#define __NR_swapoff 225 -+#define __NR_mprotect 226 -+#define __NR_msync 227 -+#define __NR_mlock 228 -+#define __NR_munlock 229 -+#define __NR_mlockall 230 -+#define __NR_munlockall 231 -+#define __NR_mincore 232 -+#define __NR_madvise 233 -+#define __NR_remap_file_pages 234 -+#define __NR_mbind 235 -+#define __NR_get_mempolicy 236 -+#define __NR_set_mempolicy 237 -+#define __NR_migrate_pages 238 -+#define __NR_move_pages 239 -+#define __NR_rt_tgsigqueueinfo 240 -+#define __NR_perf_event_open 241 -+#define __NR_accept4 242 -+#define __NR_recvmmsg 243 -+ -+///* -+// * Architectures may provide up to 16 syscalls of their own -+// * starting with this value. -+// */ -+//#define __NR_arch_specific_syscall 244 -+ -+#define __NR_wait4 260 -+#define __NR_prlimit64 261 -+#define __NR_fanotify_init 262 -+#define __NR_fanotify_mark 263 -+#define __NR_name_to_handle_at 264 -+#define __NR_open_by_handle_at 265 -+#define __NR_clock_adjtime 266 -+#define __NR_syncfs 267 -+#define __NR_setns 268 -+#define __NR_sendmmsg 269 -+#define __NR_process_vm_readv 270 -+#define __NR_process_vm_writev 271 -+#define __NR_kcmp 272 -+#define __NR_finit_module 273 -+ -+#undef __NR_syscalls -+#define __NR_syscalls 274 -+ -+///* -+// * All syscalls below here should go away really, -+// * these are provided for both review and as a porting -+// * help for the C library version. -+//* -+// * Last chance: are any of these important enough to -+// * enable by default? -+// */ -+//#ifdef __ARCH_WANT_SYSCALL_NO_AT -+//ZZZZ#define __NR_open 1024 -+//#define __NR_link 1025 -+//__SYSCALL(__NR_link, sys_link) -+//#define __NR_unlink 1026 -+#define __NR_mknod 1027 -+//#define __NR_chmod 1028 -+//__SYSCALL(__NR_chmod, sys_chmod) -+//#define __NR_chown 1029 -+//__SYSCALL(__NR_chown, sys_chown) -+//#define __NR_mkdir 1030 -+//__SYSCALL(__NR_mkdir, sys_mkdir) -+//#define __NR_rmdir 1031 -+//__SYSCALL(__NR_rmdir, sys_rmdir) -+//#define __NR_lchown 1032 -+//__SYSCALL(__NR_lchown, sys_lchown) -+#define __NR_access 1033 -+#define __NR_rename 1034 -+//#define __NR_readlink 1035 -+//#define __NR_symlink 1036 -+//__SYSCALL(__NR_symlink, sys_symlink) -+//#define __NR_utimes 1037 -+//__SYSCALL(__NR_utimes, sys_utimes) -+//#define __NR3264_stat 1038 -+//__SC_3264(__NR3264_stat, sys_stat64, sys_newstat) -+//#define __NR3264_lstat 1039 -+//__SC_3264(__NR3264_lstat, sys_lstat64, sys_newlstat) -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR3264_lstat+1) -+//#endif /* __ARCH_WANT_SYSCALL_NO_AT */ -+// -+//#ifdef __ARCH_WANT_SYSCALL_NO_FLAGS -+#define __NR_pipe 1040 -+#define __NR_dup2 1041 -+//#define __NR_epoll_create 1042 -+//__SYSCALL(__NR_epoll_create, sys_epoll_create) -+//#define __NR_inotify_init 1043 -+//__SYSCALL(__NR_inotify_init, sys_inotify_init) -+//#define __NR_eventfd 1044 -+//__SYSCALL(__NR_eventfd, sys_eventfd) -+//#define __NR_signalfd 1045 -+//__SYSCALL(__NR_signalfd, sys_signalfd) -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR_signalfd+1) -+//#endif /* __ARCH_WANT_SYSCALL_NO_FLAGS */ -+// -+/* #if (__BITS_PER_LONG == 32 || defined(__SYSCALL_COMPAT)) && \ -+ defined(__ARCH_WANT_SYSCALL_OFF_T) -+*/ -+//#define __NR_sendfile 1046 -+//__SYSCALL(__NR_sendfile, sys_sendfile) -+//#define __NR_ftruncate 1047 -+//__SYSCALL(__NR_ftruncate, sys_ftruncate) -+//#define __NR_truncate 1048 -+//__SYSCALL(__NR_truncate, sys_truncate) -+#define __NR_stat 1049 -+//#define __NR_lstat 1050 -+//__SYSCALL(__NR_lstat, sys_newlstat) -+//ZZ#define __NR_fstat 1051 -+//#define __NR_fcntl 1052 -+//#define __NR_fadvise64 1053 -+//#define __ARCH_WANT_SYS_FADVISE64 -+//__SYSCALL(__NR_fadvise64, sys_fadvise64) -+//#define __NR_newfstatat 1054 -+//#define __ARCH_WANT_SYS_NEWFSTATAT -+//__SYSCALL(__NR_newfstatat, sys_newfstatat) -+//#define __NR_fstatfs 1055 -+//__SYSCALL(__NR_fstatfs, sys_fstatfs) -+//#define __NR_statfs 1056 -+//__SYSCALL(__NR_statfs, sys_statfs) -+#define __NR_lseek 1057 -+#define __NR_mmap 1058 -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR_mmap+1) -+//#endif /* 32 bit off_t syscalls */ -+// -+//#ifdef __ARCH_WANT_SYSCALL_DEPRECATED -+//#define __NR_alarm 1059 -+//#define __ARCH_WANT_SYS_ALARM -+//__SYSCALL(__NR_alarm, sys_alarm) -+#define __NR_getpgrp 1060 -+//#define __ARCH_WANT_SYS_GETPGRP -+//__SYSCALL(__NR_getpgrp, sys_getpgrp) -+//#define __NR_pause 1061 -+//#define __ARCH_WANT_SYS_PAUSE -+//__SYSCALL(__NR_pause, sys_pause) -+//#define __NR_time 1062 -+//#define __ARCH_WANT_SYS_TIME -+//#define __ARCH_WANT_COMPAT_SYS_TIME -+//__SYSCALL(__NR_time, sys_time) -+//#define __NR_utime 1063 -+//#define __ARCH_WANT_SYS_UTIME -+//__SYSCALL(__NR_utime, sys_utime) -+// -+//#define __NR_creat 1064 -+//__SYSCALL(__NR_creat, sys_creat) -+#define __NR_getdents 1065 -+//#define __NR_futimesat 1066 -+//__SYSCALL(__NR_futimesat, sys_futimesat) -+//#define __NR_select 1067 -+//#define __ARCH_WANT_SYS_SELECT -+//__SYSCALL(__NR_select, sys_select) -+#define __NR_poll 1068 -+//#define __NR_epoll_wait 1069 -+//__SYSCALL(__NR_epoll_wait, sys_epoll_wait) -+//#define __NR_ustat 1070 -+//__SYSCALL(__NR_ustat, sys_ustat) -+//#define __NR_vfork 1071 -+//__SYSCALL(__NR_vfork, sys_vfork) -+//#define __NR_oldwait4 1072 -+//__SYSCALL(__NR_oldwait4, sys_wait4) -+//#define __NR_recv 1073 -+//__SYSCALL(__NR_recv, sys_recv) -+//#define __NR_send 1074 -+//__SYSCALL(__NR_send, sys_send) -+//#define __NR_bdflush 1075 -+//__SYSCALL(__NR_bdflush, sys_bdflush) -+//#define __NR_umount 1076 -+//__SYSCALL(__NR_umount, sys_oldumount) -+//#define __ARCH_WANT_SYS_OLDUMOUNT -+//#define __NR_uselib 1077 -+//__SYSCALL(__NR_uselib, sys_uselib) -+//#define __NR__sysctl 1078 -+//__SYSCALL(__NR__sysctl, sys_sysctl) -+// -+#define __NR_fork 1079 -+//#ifdef CONFIG_MMU -+//__SYSCALL(__NR_fork, sys_fork) -+//#else -+//__SYSCALL(__NR_fork, sys_ni_syscall) -+//#endif /* CONFIG_MMU */ -+// -+//#undef __NR_syscalls -+//#define __NR_syscalls (__NR_fork+1) -+// -+//#endif /* __ARCH_WANT_SYSCALL_DEPRECATED */ -+// -+///* -+// * 32 bit systems traditionally used different -+// * syscalls for off_t and loff_t arguments, while -+// * 64 bit systems only need the off_t version. -+// * For new 32 bit platforms, there is no need to -+// * implement the old 32 bit off_t syscalls, so -+// * they take different names. -+// * Here we map the numbers so that both versions -+// * use the same syscall table layout. -+// */ -+//#if __BITS_PER_LONG == 64 && !defined(__SYSCALL_COMPAT) -+#define __NR_fcntl __NR3264_fcntl -+//#define __NR_statfs __NR3264_statfs -+//#define __NR_fstatfs __NR3264_fstatfs -+//#define __NR_truncate __NR3264_truncate -+//#define __NR_ftruncate __NR3264_ftruncate -+//#define __NR_lseek __NR3264_lseek -+//#define __NR_sendfile __NR3264_sendfile -+//#define __NR_newfstatat __NR3264_fstatat -+#define __NR_fstat __NR3264_fstat -+//#define __NR_mmap __NR3264_mmap -+//#define __NR_fadvise64 __NR3264_fadvise64 -+//#ifdef __NR3264_stat -+//#define __NR_stat __NR3264_stat -+//#define __NR_lstat __NR3264_lstat -+//#endif -+//#else -+//#define __NR_fcntl64 __NR3264_fcntl -+//#define __NR_statfs64 __NR3264_statfs -+//#define __NR_fstatfs64 __NR3264_fstatfs -+//#define __NR_truncate64 __NR3264_truncate -+//#define __NR_ftruncate64 __NR3264_ftruncate -+//#define __NR_llseek __NR3264_lseek -+//#define __NR_sendfile64 __NR3264_sendfile -+//#define __NR_fstatat64 __NR3264_fstatat -+//#define __NR_fstat64 __NR3264_fstat -+//#define __NR_mmap2 __NR3264_mmap -+//#define __NR_fadvise64_64 __NR3264_fadvise64 -+//#ifdef __NR3264_stat -+//#define __NR_stat64 __NR3264_stat -+//#define __NR_lstat64 __NR3264_lstat -+//#endif -+//#endif -+ -+#endif /* __VKI_SCNUMS_ARM64_LINUX_H */ -+ -+/*--------------------------------------------------------------------*/ -+/*--- end vki-scnums-arm64-linux.h ---*/ -+/*--------------------------------------------------------------------*/ -Index: include/valgrind.h -=================================================================== ---- include/valgrind.h.orig -+++ include/valgrind.h -@@ -117,6 +117,7 @@ - #undef PLAT_ppc32_linux - #undef PLAT_ppc64_linux - #undef PLAT_arm_linux -+#undef PLAT_arm64_linux - #undef PLAT_s390x_linux - #undef PLAT_mips32_linux - #undef PLAT_mips64_linux -@@ -139,16 +140,16 @@ - # define PLAT_ppc32_linux 1 - #elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) - # define PLAT_ppc64_linux 1 --#elif defined(__linux__) && defined(__arm__) -+#elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__) - # define PLAT_arm_linux 1 -+#elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__) -+# define PLAT_arm64_linux 1 - #elif defined(__linux__) && defined(__s390__) && defined(__s390x__) - # define PLAT_s390x_linux 1 --#elif defined(__linux__) && defined(__mips__) --#if (__mips==64) -+#elif defined(__linux__) && defined(__mips__) && (__mips==64) - # define PLAT_mips64_linux 1 --#else -+#elif defined(__linux__) && defined(__mips__) && (__mips!=64) - # define PLAT_mips32_linux 1 --#endif - #else - /* If we're not compiling for our target platform, don't generate - any inline asms. */ -@@ -654,6 +655,74 @@ typedef - - #endif /* PLAT_arm_linux */ - -+/* ------------------------ arm64-linux ------------------------- */ -+ -+#if defined(PLAT_arm64_linux) -+ -+typedef -+ struct { -+ unsigned long long int nraddr; /* where's the code? */ -+ } -+ OrigFn; -+ -+#define __SPECIAL_INSTRUCTION_PREAMBLE \ -+ "ror x12, x12, #3 ; ror x12, x12, #13 \n\t" \ -+ "ror x12, x12, #51 ; ror x12, x12, #61 \n\t" -+ -+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ -+ _zzq_default, _zzq_request, \ -+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ -+ \ -+ __extension__ \ -+ ({volatile unsigned long long int _zzq_args[6]; \ -+ volatile unsigned long long int _zzq_result; \ -+ _zzq_args[0] = (unsigned long long int)(_zzq_request); \ -+ _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \ -+ _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \ -+ _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \ -+ _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \ -+ _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \ -+ __asm__ volatile("mov x3, %1\n\t" /*default*/ \ -+ "mov x4, %2\n\t" /*ptr*/ \ -+ __SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* X3 = client_request ( X4 ) */ \ -+ "orr x10, x10, x10\n\t" \ -+ "mov %0, x3" /*result*/ \ -+ : "=r" (_zzq_result) \ -+ : "r" (_zzq_default), "r" (&_zzq_args[0]) \ -+ : "cc","memory", "x3", "x4"); \ -+ _zzq_result; \ -+ }) -+ -+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ -+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ -+ unsigned long long int __addr; \ -+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* X3 = guest_NRADDR */ \ -+ "orr x11, x11, x11\n\t" \ -+ "mov %0, x3" \ -+ : "=r" (__addr) \ -+ : \ -+ : "cc", "memory", "x3" \ -+ ); \ -+ _zzq_orig->nraddr = __addr; \ -+ } -+ -+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ __SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* branch-and-link-to-noredir X8 */ \ -+ "orr x12, x12, x12\n\t" -+ -+#define VALGRIND_VEX_INJECT_IR() \ -+ do { \ -+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ -+ "orr x9, x9, x9\n\t" \ -+ : : : "cc", "memory" \ -+ ); \ -+ } while (0) -+ -+#endif /* PLAT_arm64_linux */ -+ - /* ------------------------ s390x-linux ------------------------ */ - - #if defined(PLAT_s390x_linux) -@@ -3470,6 +3539,143 @@ typedef - - #endif /* PLAT_arm_linux */ - -+/* ------------------------ arm64-linux ------------------------ */ -+ -+#if defined(PLAT_arm64_linux) -+ -+/* These regs are trashed by the hidden call. */ -+#define __CALLER_SAVED_REGS \ -+ "x0", "x1", "x2", "x3","x4", "x5", "x6", "x7", "x8", "x9", \ -+ "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", \ -+ "x18", "x19", "x20", \ -+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", \ -+ "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", \ -+ "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", \ -+ "v26", "v27", "v28", "v29", "v30", "v31" -+ -+#define VALGRIND_ALIGN_STACK /* FIXME! */ -+#define VALGRIND_RESTORE_STACK /* FIXME! */ -+ -+/* These CALL_FN_ macros assume that on arm64-linux, -+ sizeof(unsigned long) == 8. */ -+ -+#define CALL_FN_W_v(lval, orig) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[1]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r10" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_W(lval, orig, arg1) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[2]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS/*, "r10"*/ \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS/*, "r10"*/ \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[4]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0\n" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS/*, "r10"*/ \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[5]; \ -+ volatile unsigned long _res; \ -+ _argvec[0] = (unsigned long)_orig.nraddr; \ -+ _argvec[1] = (unsigned long)(arg1); \ -+ _argvec[2] = (unsigned long)(arg2); \ -+ _argvec[3] = (unsigned long)(arg3); \ -+ _argvec[4] = (unsigned long)(arg4); \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "ldr x0, [%1, #8] \n\t" \ -+ "ldr x1, [%1, #16] \n\t" \ -+ "ldr x2, [%1, #24] \n\t" \ -+ "ldr x3, [%1, #32] \n\t" \ -+ "ldr x8, [%1] \n\t" /* target->x8 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_X8 \ -+ VALGRIND_RESTORE_STACK \ -+ "mov %0, x0" \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "0" (&_argvec[0]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS/*, "r10"*/ \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#endif /* PLAT_arm64_linux */ -+ - /* ------------------------- s390x-linux ------------------------- */ - - #if defined(PLAT_s390x_linux) -Index: include/pub_tool_basics.h -=================================================================== ---- include/pub_tool_basics.h.orig -+++ include/pub_tool_basics.h -@@ -269,7 +269,8 @@ static inline Bool sr_EQ ( SysRes sr1, S - #undef VG_LITTLEENDIAN - - #if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \ -- || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEL)) -+ || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEL)) \ -+ || defined(VGA_arm64) - # define VG_LITTLEENDIAN 1 - #elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \ - || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEB)) -@@ -283,7 +284,8 @@ static inline Bool sr_EQ ( SysRes sr1, S - # define VG_REGPARM(n) __attribute__((regparm(n))) - #elif defined(VGA_amd64) || defined(VGA_ppc32) \ - || defined(VGA_ppc64) || defined(VGA_arm) || defined(VGA_s390x) \ -- || defined(VGA_mips32) || defined(VGA_mips64) -+ || defined(VGA_mips32) || defined(VGA_mips64) \ -+ || defined(VGA_arm64) - # define VG_REGPARM(n) /* */ - #else - # error Unknown arch -Index: include/pub_tool_vkiscnums_asm.h -=================================================================== ---- include/pub_tool_vkiscnums_asm.h.orig -+++ include/pub_tool_vkiscnums_asm.h -@@ -51,6 +51,9 @@ - #elif defined(VGP_arm_linux) - # include "vki/vki-scnums-arm-linux.h" - -+#elif defined(VGP_arm64_linux) -+# include "vki/vki-scnums-arm64-linux.h" -+ - #elif defined(VGP_mips32_linux) - # include "vki/vki-scnums-mips32-linux.h" - -Index: Makefile.tool.am -=================================================================== ---- Makefile.tool.am.orig -+++ Makefile.tool.am -@@ -52,6 +52,9 @@ TOOL_LDFLAGS_PPC64_LINUX = \ - TOOL_LDFLAGS_ARM_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ - -+TOOL_LDFLAGS_ARM64_LINUX = \ -+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+ - TOOL_LDFLAGS_S390X_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - -@@ -105,6 +108,9 @@ LIBREPLACEMALLOC_PPC64_LINUX = \ - LIBREPLACEMALLOC_ARM_LINUX = \ - $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a - -+LIBREPLACEMALLOC_ARM64_LINUX = \ -+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm64-linux.a -+ - LIBREPLACEMALLOC_X86_DARWIN = \ - $(top_builddir)/coregrind/libreplacemalloc_toolpreload-x86-darwin.a - -@@ -145,6 +151,11 @@ LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \ - $(LIBREPLACEMALLOC_ARM_LINUX) \ - -Wl,--no-whole-archive - -+LIBREPLACEMALLOC_LDFLAGS_ARM64_LINUX = \ -+ -Wl,--whole-archive \ -+ $(LIBREPLACEMALLOC_ARM64_LINUX) \ -+ -Wl,--no-whole-archive -+ - LIBREPLACEMALLOC_LDFLAGS_X86_DARWIN = \ - $(LIBREPLACEMALLOC_X86_DARWIN) - -Index: docs/internals/register-uses.txt -=================================================================== ---- docs/internals/register-uses.txt.orig -+++ docs/internals/register-uses.txt -@@ -134,6 +134,46 @@ insns have reg+offset forms for offsets - often isn't enough. - - -+arm64-linux -+~~~~~~~~~~~ -+ -+Reg Callee Arg -+Name Saves? Reg? Comment Vex-uses? -+--------------------------------------------------------------- -+r0 int#0 ret#0 (??) -+r1 int#1 ret#1 (??) -+r2-7 int#2..7 -+r8 "Indirect res loc reg" -+r9 "Temporary regs" chaining scratch -+r10-15 "Temporary regs" avail -+r16(IP0) -+r17(IP1) -+r18 "Platform reg" -+r19-20 maybe "Temporary regs" -+r21 y "Callee saved" GSP -+r22-28 y "Callee saved" -+r29(FP) y -+r30(LR) y -+ -+NZCV "Status register" -+ -+Is there a TLS register? -+ -+x21 is the GSP. x9 is a scratch chaining/spill temp. Neither -+are available to the register allocator. -+ -+Q registers: -+It's a little awkward. Basically, D registers are the same as ARM, -+so d0-d7 and d16-d31 are caller-saved, but d8-d15 are callee-saved. -+ -+Q registers are the same, except that the upper 64 bits of q8-q15 -+are caller-saved. -+ -+The idea is that you only need to preserve D registers, not Q -+registers. -+ -+ -+ - s390x-linux - ~~~~~~~~~~~ - -Index: Makefile.vex.am -=================================================================== ---- Makefile.vex.am.orig -+++ Makefile.vex.am -@@ -24,6 +24,7 @@ pkginclude_HEADERS = \ - pub/libvex_guest_ppc32.h \ - pub/libvex_guest_ppc64.h \ - pub/libvex_guest_arm.h \ -+ pub/libvex_guest_arm64.h \ - pub/libvex_guest_s390x.h \ - pub/libvex_guest_mips32.h \ - pub/libvex_guest_mips64.h \ -@@ -42,6 +43,7 @@ noinst_HEADERS = \ - priv/guest_amd64_defs.h \ - priv/guest_ppc_defs.h \ - priv/guest_arm_defs.h \ -+ priv/guest_arm64_defs.h \ - priv/guest_s390_defs.h \ - priv/guest_mips_defs.h \ - priv/host_generic_regs.h \ -@@ -53,6 +55,7 @@ noinst_HEADERS = \ - priv/host_amd64_defs.h \ - priv/host_ppc_defs.h \ - priv/host_arm_defs.h \ -+ priv/host_arm64_defs.h \ - priv/host_s390_defs.h \ - priv/s390_disasm.h \ - priv/s390_defs.h \ -@@ -71,6 +74,7 @@ pub/libvex_guest_offsets.h: auxprogs/gen - pub/libvex_guest_ppc32.h \ - pub/libvex_guest_ppc64.h \ - pub/libvex_guest_arm.h \ -+ pub/libvex_guest_arm64.h \ - pub/libvex_guest_s390x.h \ - pub/libvex_guest_mips32.h \ - pub/libvex_guest_mips64.h -@@ -114,6 +118,8 @@ LIBVEX_SOURCES_COMMON = \ - priv/guest_ppc_toIR.c \ - priv/guest_arm_helpers.c \ - priv/guest_arm_toIR.c \ -+ priv/guest_arm64_helpers.c \ -+ priv/guest_arm64_toIR.c \ - priv/guest_s390_helpers.c \ - priv/guest_s390_toIR.c \ - priv/guest_mips_helpers.c \ -@@ -132,6 +138,8 @@ LIBVEX_SOURCES_COMMON = \ - priv/host_ppc_isel.c \ - priv/host_arm_defs.c \ - priv/host_arm_isel.c \ -+ priv/host_arm64_defs.c \ -+ priv/host_arm64_isel.c \ - priv/host_s390_defs.c \ - priv/host_s390_isel.c \ - priv/s390_disasm.c \ -Index: coregrind/vgdb.c -=================================================================== ---- coregrind/vgdb.c.orig -+++ coregrind/vgdb.c -@@ -80,7 +80,7 @@ - can be "waken up". PTRACEINVOKER implies some architecture - specific code and/or some OS specific code. */ - #if defined(VGA_arm) || defined(VGA_x86) || defined(VGA_amd64) \ -- || defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \ -+ || defined(VGA_ppc32) || defined(VGA_ppc64le) || defined(VGA_ppc64be) || defined(VGA_s390x) \ - || defined(VGA_mips32) || defined(VGA_mips64) - #define PTRACEINVOKER - #else -@@ -911,7 +911,7 @@ Bool invoke_gdbserver (int pid) - sp = user_mod.regs.uregs[13]; - #elif defined(VGA_ppc32) - sp = user_mod.regs.gpr[1]; --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - sp = user_mod.regs.gpr[1]; - #elif defined(VGA_s390x) - sp = user_mod.regs.gprs[15]; -@@ -975,7 +975,7 @@ Bool invoke_gdbserver (int pid) - I_die_here : not x86 or amd64 in x86/amd64 section/ - #endif - --#elif defined(VGA_ppc32) || defined(VGA_ppc64) -+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - user_mod.regs.nip = shared32->invoke_gdbserver; - user_mod.regs.trap = -1L; - /* put check arg in register 3 */ -@@ -1042,7 +1042,7 @@ Bool invoke_gdbserver (int pid) - assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe - #elif defined(VGA_ppc32) - assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - Addr64 func_addr; - Addr64 toc_addr; - int rw; diff --git a/r14184.diff b/r14184.diff deleted file mode 100644 index cc6888f..0000000 --- a/r14184.diff +++ /dev/null @@ -1,397 +0,0 @@ ------------------------------------------------------------------------- -r14184 | sewardj | 2014-07-24 14:45:24 +0200 (Do, 24. Jul 2014) | 8 Zeilen - -Track vex r2910 (infrastructural improvements in representation of -endianness in VEX). - -In short: in m_machine.c, VG_(machine_get_hwcaps), get the endianness -of the host, and pass it through to all places (in VEX) where it is -required. - - ------------------------------------------------------------------------- -Index: coregrind/m_transtab.c -=================================================================== ---- coregrind/m_transtab.c.orig -+++ coregrind/m_transtab.c -@@ -747,8 +747,11 @@ void VG_(tt_tc_do_chaining) ( void* from - Bool to_fastEP ) - { - /* Get the CPU info established at startup. */ -- VexArch vex_arch = VexArch_INVALID; -- VG_(machine_get_VexArchInfo)( &vex_arch, NULL ); -+ VexArch arch_host = VexArch_INVALID; -+ VexArchInfo archinfo_host; -+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); -+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); -+ VexEndness endness_host = archinfo_host.endness; - - // host_code is where we're patching to. So it needs to - // take into account, whether we're jumping to the slow -@@ -757,7 +760,8 @@ void VG_(tt_tc_do_chaining) ( void* from - // the slow (tcptr) entry point. - TTEntry* to_tte = index_tte(to_sNo, to_tteNo); - void* host_code = ((UChar*)to_tte->tcptr) -- + (to_fastEP ? LibVEX_evCheckSzB(vex_arch) : 0); -+ + (to_fastEP ? LibVEX_evCheckSzB(arch_host, -+ endness_host) : 0); - - // stay sane -- the patch point (dst) is in this sector's code cache - vg_assert( (UChar*)host_code >= (UChar*)sectors[to_sNo].tc ); -@@ -789,7 +793,7 @@ void VG_(tt_tc_do_chaining) ( void* from - since it is host-dependent. */ - VexInvalRange vir - = LibVEX_Chain( -- vex_arch, -+ arch_host, endness_host, - from__patch_addr, - VG_(fnptr_to_fnentry)( - to_fastEP ? &VG_(disp_cp_chain_me_to_fastEP) -@@ -833,7 +837,7 @@ void VG_(tt_tc_do_chaining) ( void* from - addresses of the destination block (that is, the block that owns - this InEdge). */ - __attribute__((noinline)) --static void unchain_one ( VexArch vex_arch, -+static void unchain_one ( VexArch arch_host, VexEndness endness_host, - InEdge* ie, - void* to_fastEPaddr, void* to_slowEPaddr ) - { -@@ -858,7 +862,7 @@ static void unchain_one ( VexArch vex_ar - // place_to_jump_to_EXPECTED really is the current dst, and - // asserts if it isn't. - VexInvalRange vir -- = LibVEX_UnChain( vex_arch, place_to_patch, -+ = LibVEX_UnChain( arch_host, endness_host, place_to_patch, - place_to_jump_to_EXPECTED, disp_cp_chain_me ); - VG_(invalidate_icache)( (void*)vir.start, vir.len ); - } -@@ -868,13 +872,14 @@ static void unchain_one ( VexArch vex_ar - succs of its associated blocks accordingly. This includes undoing - any chained jumps to this block. */ - static --void unchain_in_preparation_for_deletion ( VexArch vex_arch, -+void unchain_in_preparation_for_deletion ( VexArch arch_host, -+ VexEndness endness_host, - UInt here_sNo, UInt here_tteNo ) - { - if (DEBUG_TRANSTAB) - VG_(printf)("QQQ unchain_in_prep %u.%u...\n", here_sNo, here_tteNo); - UWord i, j, n, m; -- Int evCheckSzB = LibVEX_evCheckSzB(vex_arch); -+ Int evCheckSzB = LibVEX_evCheckSzB(arch_host, endness_host); - TTEntry* here_tte = index_tte(here_sNo, here_tteNo); - if (DEBUG_TRANSTAB) - VG_(printf)("... QQQ tt.entry 0x%llu tt.tcptr 0x%p\n", -@@ -888,7 +893,7 @@ void unchain_in_preparation_for_deletion - // Undo the chaining. - UChar* here_slow_EP = (UChar*)here_tte->tcptr; - UChar* here_fast_EP = here_slow_EP + evCheckSzB; -- unchain_one(vex_arch, ie, here_fast_EP, here_slow_EP); -+ unchain_one(arch_host, endness_host, ie, here_fast_EP, here_slow_EP); - // Find the corresponding entry in the "from" node's out_edges, - // and remove it. - TTEntry* from_tte = index_tte(ie->from_sNo, ie->from_tteNo); -@@ -1427,8 +1432,11 @@ static void initialiseSector ( Int sno ) - vg_assert(sec->tc_next != NULL); - n_dump_count += sec->tt_n_inuse; - -- VexArch vex_arch = VexArch_INVALID; -- VG_(machine_get_VexArchInfo)( &vex_arch, NULL ); -+ VexArch arch_host = VexArch_INVALID; -+ VexArchInfo archinfo_host; -+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); -+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); -+ VexEndness endness_host = archinfo_host.endness; - - /* Visit each just-about-to-be-abandoned translation. */ - if (DEBUG_TRANSTAB) VG_(printf)("QQQ unlink-entire-sector: %d START\n", -@@ -1444,7 +1452,8 @@ static void initialiseSector ( Int sno ) - sec->tt[i].entry, - sec->tt[i].vge ); - } -- unchain_in_preparation_for_deletion(vex_arch, sno, i); -+ unchain_in_preparation_for_deletion(arch_host, -+ endness_host, sno, i); - } else { - vg_assert(sec->tt[i].n_tte2ec == 0); - } -@@ -1508,8 +1517,7 @@ void VG_(add_to_transtab)( VexGuestExten - UInt code_len, - Bool is_self_checking, - Int offs_profInc, -- UInt n_guest_instrs, -- VexArch arch_host ) -+ UInt n_guest_instrs ) - { - Int tcAvailQ, reqdQ, y, i; - ULong *tcptr, *tcptr2; -@@ -1627,8 +1635,13 @@ void VG_(add_to_transtab)( VexGuestExten - /* Patch in the profile counter location, if necessary. */ - if (offs_profInc != -1) { - vg_assert(offs_profInc >= 0 && offs_profInc < code_len); -+ VexArch arch_host = VexArch_INVALID; -+ VexArchInfo archinfo_host; -+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); -+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); -+ VexEndness endness_host = archinfo_host.endness; - VexInvalRange vir -- = LibVEX_PatchProfInc( arch_host, -+ = LibVEX_PatchProfInc( arch_host, endness_host, - dstP + offs_profInc, - §ors[y].tt[i].count ); - VG_(invalidate_icache)( (void*)vir.start, vir.len ); -@@ -1775,7 +1788,7 @@ Bool overlaps ( Addr64 start, ULong rang - /* Delete a tt entry, and update all the eclass data accordingly. */ - - static void delete_tte ( /*MOD*/Sector* sec, UInt secNo, Int tteno, -- VexArch vex_arch ) -+ VexArch arch_host, VexEndness endness_host ) - { - Int i, ec_num, ec_idx; - TTEntry* tte; -@@ -1789,7 +1802,7 @@ static void delete_tte ( /*MOD*/Sector* - vg_assert(tte->n_tte2ec >= 1 && tte->n_tte2ec <= 3); - - /* Unchain .. */ -- unchain_in_preparation_for_deletion(vex_arch, secNo, tteno); -+ unchain_in_preparation_for_deletion(arch_host, endness_host, secNo, tteno); - - /* Deal with the ec-to-tte links first. */ - for (i = 0; i < tte->n_tte2ec; i++) { -@@ -1829,7 +1842,8 @@ static - Bool delete_translations_in_sector_eclass ( /*MOD*/Sector* sec, UInt secNo, - Addr64 guest_start, ULong range, - Int ec, -- VexArch vex_arch ) -+ VexArch arch_host, -+ VexEndness endness_host ) - { - Int i; - UShort tteno; -@@ -1853,7 +1867,7 @@ Bool delete_translations_in_sector_eclas - - if (overlaps( guest_start, range, &tte->vge )) { - anyDeld = True; -- delete_tte( sec, secNo, (Int)tteno, vex_arch ); -+ delete_tte( sec, secNo, (Int)tteno, arch_host, endness_host ); - } - - } -@@ -1868,7 +1882,8 @@ Bool delete_translations_in_sector_eclas - static - Bool delete_translations_in_sector ( /*MOD*/Sector* sec, UInt secNo, - Addr64 guest_start, ULong range, -- VexArch vex_arch ) -+ VexArch arch_host, -+ VexEndness endness_host ) - { - Int i; - Bool anyDeld = False; -@@ -1877,7 +1892,7 @@ Bool delete_translations_in_sector ( /*M - if (sec->tt[i].status == InUse - && overlaps( guest_start, range, &sec->tt[i].vge )) { - anyDeld = True; -- delete_tte( sec, secNo, i, vex_arch ); -+ delete_tte( sec, secNo, i, arch_host, endness_host ); - } - } - -@@ -1907,8 +1922,11 @@ void VG_(discard_translations) ( Addr64 - if (range == 0) - return; - -- VexArch vex_arch = VexArch_INVALID; -- VG_(machine_get_VexArchInfo)( &vex_arch, NULL ); -+ VexArch arch_host = VexArch_INVALID; -+ VexArchInfo archinfo_host; -+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host)); -+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host ); -+ VexEndness endness_host = archinfo_host.endness; - - /* There are two different ways to do this. - -@@ -1950,11 +1968,11 @@ void VG_(discard_translations) ( Addr64 - continue; - anyDeleted |= delete_translations_in_sector_eclass( - sec, sno, guest_start, range, ec, -- vex_arch -+ arch_host, endness_host - ); - anyDeleted |= delete_translations_in_sector_eclass( - sec, sno, guest_start, range, ECLASS_MISC, -- vex_arch -+ arch_host, endness_host - ); - } - -@@ -1970,7 +1988,9 @@ void VG_(discard_translations) ( Addr64 - if (sec->tc == NULL) - continue; - anyDeleted |= delete_translations_in_sector( -- sec, sno, guest_start, range, vex_arch ); -+ sec, sno, guest_start, range, -+ arch_host, endness_host -+ ); - } - - } -Index: coregrind/m_main.c -=================================================================== ---- coregrind/m_main.c.orig -+++ coregrind/m_main.c -@@ -1391,9 +1391,10 @@ static void print_preamble ( Bool loggin - VG_(machine_get_VexArchInfo)( &vex_arch, &vex_archinfo ); - VG_(message)( - Vg_DebugMsg, -- "Arch and hwcaps: %s, %s\n", -- LibVEX_ppVexArch ( vex_arch ), -- LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps ) -+ "Arch and hwcaps: %s, %s, %s\n", -+ LibVEX_ppVexArch ( vex_arch ), -+ LibVEX_ppVexEndness ( vex_archinfo.endness ), -+ LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps ) - ); - VG_(message)( - Vg_DebugMsg, -Index: coregrind/pub_core_transtab.h -=================================================================== ---- coregrind/pub_core_transtab.h.orig -+++ coregrind/pub_core_transtab.h -@@ -83,8 +83,7 @@ void VG_(add_to_transtab)( VexGuestExten - UInt code_len, - Bool is_self_checking, - Int offs_profInc, -- UInt n_guest_instrs, -- VexArch arch_host ); -+ UInt n_guest_instrs ); - - extern - void VG_(tt_tc_do_chaining) ( void* from__patch_addr, -Index: coregrind/m_machine.c -=================================================================== ---- coregrind/m_machine.c.orig -+++ coregrind/m_machine.c -@@ -739,6 +739,7 @@ Bool VG_(machine_get_hwcaps)( void ) - have_mmxext = True; - - va = VexArchX86; -+ vai.endness = VexEndnessLE; - if (have_sse2 && have_sse1 && have_mmxext) { - vai.hwcaps = VEX_HWCAPS_X86_MMXEXT; - vai.hwcaps |= VEX_HWCAPS_X86_SSE1; -@@ -857,14 +858,15 @@ Bool VG_(machine_get_hwcaps)( void ) - have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */ - } - -- va = VexArchAMD64; -- vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0) -- | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0) -- | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0) -- | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0) -- | (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0) -- | (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0) -- | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0); -+ va = VexArchAMD64; -+ vai.endness = VexEndnessLE; -+ vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0) -+ | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0) -+ | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0) -+ | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0) -+ | (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0) -+ | (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0) -+ | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0); - - VG_(machine_get_cache_info)(&vai); - -@@ -1013,6 +1015,7 @@ Bool VG_(machine_get_hwcaps)( void ) - VG_(machine_ppc32_has_VMX) = have_V ? 1 : 0; - - va = VexArchPPC32; -+ vai.endness = VexEndnessBE; - - vai.hwcaps = 0; - if (have_F) vai.hwcaps |= VEX_HWCAPS_PPC32_F; -@@ -1151,6 +1154,9 @@ Bool VG_(machine_get_hwcaps)( void ) - VG_(machine_ppc64_has_VMX) = have_V ? 1 : 0; - - va = VexArchPPC64; -+ // CARLL fixme: when the time comes, copy .endness setting code -+ // from the VGA_mips32 case -+ vai.endness = VexEndnessBE; - - vai.hwcaps = 0; - if (have_V) vai.hwcaps |= VEX_HWCAPS_PPC64_V; -@@ -1243,6 +1249,7 @@ Bool VG_(machine_get_hwcaps)( void ) - r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL); - vg_assert(r == 0); - va = VexArchS390X; -+ vai.endness = VexEndnessBE; - - vai.hwcaps = model; - if (have_STFLE) vai.hwcaps |= VEX_HWCAPS_S390X_STFLE; -@@ -1404,6 +1411,7 @@ Bool VG_(machine_get_hwcaps)( void ) - VG_(machine_arm_archlevel) = archlevel; - - va = VexArchARM; -+ vai.endness = VexEndnessLE; - - vai.hwcaps = VEX_ARM_ARCHLEVEL(archlevel); - if (have_VFP3) vai.hwcaps |= VEX_HWCAPS_ARM_VFP3; -@@ -1419,6 +1427,7 @@ Bool VG_(machine_get_hwcaps)( void ) - #elif defined(VGA_arm64) - { - va = VexArchARM64; -+ vai.endness = VexEndnessLE; - - /* So far there are no variants. */ - vai.hwcaps = 0; -@@ -1437,6 +1446,14 @@ Bool VG_(machine_get_hwcaps)( void ) - - vai.hwcaps = model; - -+# if defined(VKI_LITTLE_ENDIAN) -+ vai.endness = VexEndnessLE; -+# elif defined(VKI_BIG_ENDIAN) -+ vai.endness = VexEndnessBE; -+# else -+ vai.endness = VexEndness_INVALID; -+# endif -+ - /* Same instruction set detection algorithm as for ppc32/arm... */ - vki_sigset_t saved_set, tmp_set; - vki_sigaction_fromK_t saved_sigill_act; -@@ -1506,11 +1523,19 @@ Bool VG_(machine_get_hwcaps)( void ) - { - va = VexArchMIPS64; - UInt model = VG_(get_machine_model)(); -- if (model== -1) -+ if (model == -1) - return False; - - vai.hwcaps = model; - -+# if defined(VKI_LITTLE_ENDIAN) -+ vai.endness = VexEndnessLE; -+# elif defined(VKI_BIG_ENDIAN) -+ vai.endness = VexEndnessBE; -+# else -+ vai.endness = VexEndness_INVALID; -+# endif -+ - VG_(machine_get_cache_info)(&vai); - - return True; -Index: coregrind/m_translate.c -=================================================================== ---- coregrind/m_translate.c.orig -+++ coregrind/m_translate.c -@@ -1641,8 +1641,7 @@ Bool VG_(translate) ( ThreadId tid, - tmpbuf_used, - tres.n_sc_extents > 0, - tres.offs_profInc, -- tres.n_guest_instrs, -- vex_arch ); -+ tres.n_guest_instrs ); - } else { - vg_assert(tres.offs_profInc == -1); /* -1 == unset */ - VG_(add_to_unredir_transtab)( &vge, diff --git a/r14238.diff b/r14238.diff deleted file mode 100644 index e123f7b..0000000 --- a/r14238.diff +++ /dev/null @@ -1,2098 +0,0 @@ ------------------------------------------------------------------------- -r14238 | carll | 2014-08-08 01:17:29 +0200 (Fr, 08. Aug 2014) | 25 Zeilen - -This commit is for Bugzilla 334384. The Bugzilla contains patch 1 of 3 -to add PPC64 LE support. The other two patches can be found in Bugzillas -334834 and 334836. The commit does not have a VEX commit associated with it. - -POWER PC, add initial Little Endian support - -The IBM POWER processor now supports both Big Endian and Little Endian. -This patch renames the #defines with the name ppc64 to ppc64be for the BE -specific code. This patch adds the Little Endian #define ppc64le to the - -Additionally, a few functions are renamed to remove BE from the name if the -function is used by BE and LE. Functions that are BE specific have BE put -in the name. - -The goals of this patch is to make sure #defines, function names and -variables consistently use PPC64/ppc64 if it refers to BE and LE, -PPC64BE/ppc64be if it is specific to BE, PPC64LE/ppc64le if it is LE -specific. The patch does not break the code for PPC64 Big Endian. - -The test files memcheck/tests/atomic_incs.c, tests/power_insn_available.c -and tests/power_insn_available.c are also updated to the new #define -definition for PPC64 BE. - -Signed-off-by: Carl Love - ------------------------------------------------------------------------- -Index: Makefile.tool.am -=================================================================== ---- Makefile.tool.am.orig -+++ Makefile.tool.am -@@ -46,7 +46,10 @@ TOOL_LDFLAGS_AMD64_LINUX = \ - TOOL_LDFLAGS_PPC32_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ - --TOOL_LDFLAGS_PPC64_LINUX = \ -+TOOL_LDFLAGS_PPC64BE_LINUX = \ -+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+ -+TOOL_LDFLAGS_PPC64LE_LINUX = \ - $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - - TOOL_LDFLAGS_ARM_LINUX = \ -@@ -102,8 +105,11 @@ LIBREPLACEMALLOC_AMD64_LINUX = \ - LIBREPLACEMALLOC_PPC32_LINUX = \ - $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a - --LIBREPLACEMALLOC_PPC64_LINUX = \ -- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a -+LIBREPLACEMALLOC_PPC64BE_LINUX = \ -+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64be-linux.a -+ -+LIBREPLACEMALLOC_PPC64LE_LINUX = \ -+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64le-linux.a - - LIBREPLACEMALLOC_ARM_LINUX = \ - $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a -@@ -141,9 +147,14 @@ LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \ - $(LIBREPLACEMALLOC_PPC32_LINUX) \ - -Wl,--no-whole-archive - --LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \ -+LIBREPLACEMALLOC_LDFLAGS_PPC64BE_LINUX = \ -+ -Wl,--whole-archive \ -+ $(LIBREPLACEMALLOC_PPC64BE_LINUX) \ -+ -Wl,--no-whole-archive -+ -+LIBREPLACEMALLOC_LDFLAGS_PPC64LE_LINUX = \ - -Wl,--whole-archive \ -- $(LIBREPLACEMALLOC_PPC64_LINUX) \ -+ $(LIBREPLACEMALLOC_PPC64LE_LINUX) \ - -Wl,--no-whole-archive - - LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \ -Index: helgrind/tests/annotate_hbefore.c -=================================================================== ---- helgrind/tests/annotate_hbefore.c.orig -+++ helgrind/tests/annotate_hbefore.c -@@ -20,7 +20,7 @@ - - typedef unsigned long int UWord; - --#if defined(VGA_ppc64) -+#if defined(VGA_ppc64be) || defined(VGA_ppc64le) - - // ppc64 - /* return 1 if success, 0 if failure */ -Index: drd/drd_bitmap.h -=================================================================== ---- drd/drd_bitmap.h.orig -+++ drd/drd_bitmap.h -@@ -139,8 +139,8 @@ Addr make_address(const UWord a1, const - #if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_arm) \ - || defined(VGA_mips32) - #define BITS_PER_BITS_PER_UWORD 5 --#elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_s390x) \ -- || defined(VGA_mips64) || defined(VGA_arm64) -+#elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ -+ || defined(VGA_s390x) || defined(VGA_mips64) || defined(VGA_arm64) - #define BITS_PER_BITS_PER_UWORD 6 - #else - #error Unknown platform. -Index: drd/tests/unit_bitmap.c -=================================================================== ---- drd/tests/unit_bitmap.c.orig -+++ drd/tests/unit_bitmap.c -@@ -83,7 +83,8 @@ struct { Addr address; SizeT size; BmAcc - { 0x00ffffffULL, 1, eLoad }, - { 0xffffffffULL - (((1 << ADDR_LSB_BITS) + 1) << ADDR_IGNORED_BITS), - 1, eStore }, --#if defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) -+#if defined(VGP_amd64_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - { 0xffffffffULL - (1 << ADDR_LSB_BITS << ADDR_IGNORED_BITS), - 1, eStore }, - { 0xffffffffULL, 1, eStore }, -Index: drd/drd_load_store.c -=================================================================== ---- drd/drd_load_store.c.orig -+++ drd/drd_load_store.c -@@ -43,7 +43,7 @@ - #define STACK_POINTER_OFFSET OFFSET_amd64_RSP - #elif defined(VGA_ppc32) - #define STACK_POINTER_OFFSET OFFSET_ppc32_GPR1 --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - #define STACK_POINTER_OFFSET OFFSET_ppc64_GPR1 - #elif defined(VGA_arm) - #define STACK_POINTER_OFFSET OFFSET_arm_R13 -Index: coregrind/m_trampoline.S -=================================================================== ---- coregrind/m_trampoline.S.orig -+++ coregrind/m_trampoline.S -@@ -416,7 +416,7 @@ VG_(trampoline_stuff_end): - - /*---------------- ppc64-linux ----------------*/ - #else --#if defined(VGP_ppc64_linux) -+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - # define UD2_16 trap ; trap ; trap; trap - # define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16 -Index: coregrind/pub_core_mallocfree.h -=================================================================== ---- coregrind/pub_core_mallocfree.h.orig -+++ coregrind/pub_core_mallocfree.h -@@ -71,13 +71,14 @@ typedef Int ArenaId; - // for any AltiVec- or SSE-related type. This matches the Darwin libc. - // Also, use 16 bytes for any PPC variant, since 16 is required to make - // Altiveccery work right. --#elif defined(VGP_amd64_linux) || \ -- defined(VGP_ppc32_linux) || \ -- defined(VGP_ppc64_linux) || \ -- defined(VGP_s390x_linux) || \ -- defined(VGP_mips64_linux) || \ -- defined(VGP_x86_darwin) || \ -- defined(VGP_amd64_darwin) || \ -+#elif defined(VGP_amd64_linux) || \ -+ defined(VGP_ppc32_linux) || \ -+ defined(VGP_ppc64be_linux) || \ -+ defined(VGP_ppc64le_linux) || \ -+ defined(VGP_s390x_linux) || \ -+ defined(VGP_mips64_linux) || \ -+ defined(VGP_x86_darwin) || \ -+ defined(VGP_amd64_darwin) || \ - defined(VGP_arm64_linux) - # define VG_MIN_MALLOC_SZB 16 - #else -Index: coregrind/m_debuginfo/priv_storage.h -=================================================================== ---- coregrind/m_debuginfo/priv_storage.h.orig -+++ coregrind/m_debuginfo/priv_storage.h -@@ -232,7 +232,7 @@ typedef - Int r7_off; - } - DiCfSI; --#elif defined(VGA_ppc32) || defined(VGA_ppc64) -+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - /* Just have a struct with the common fields in, so that code that - processes the common fields doesn't have to be ifdef'd against - VGP_/VGA_ symbols. These are not used in any way on ppc32/64-linux -Index: coregrind/m_debuginfo/readmacho.c -=================================================================== ---- coregrind/m_debuginfo/readmacho.c.orig -+++ coregrind/m_debuginfo/readmacho.c -@@ -197,8 +197,8 @@ static DiSlice map_image_aboard ( DebugI - f++, arch_be_ioff += sizeof(struct fat_arch)) { - # if defined(VGA_ppc) - Int cputype = CPU_TYPE_POWERPC; --# elif defined(VGA_ppc64) -- Int cputype = CPU_TYPE_POWERPC64; -+# elif defined(VGA_ppc64be) -+ Int cputype = CPU_TYPE_POWERPC64BE; - # elif defined(VGA_x86) - Int cputype = CPU_TYPE_X86; - # elif defined(VGA_amd64) -Index: coregrind/m_debuginfo/d3basics.c -=================================================================== ---- coregrind/m_debuginfo/d3basics.c.orig -+++ coregrind/m_debuginfo/d3basics.c -@@ -406,7 +406,7 @@ static Bool get_Dwarf_Reg( /*OUT*/Addr* - if (regno == 7/*RSP*/) { *a = regs->sp; return True; } - # elif defined(VGP_ppc32_linux) - if (regno == 1/*SP*/) { *a = regs->sp; return True; } --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - if (regno == 1/*SP*/) { *a = regs->sp; return True; } - # elif defined(VGP_arm_linux) - if (regno == 13) { *a = regs->sp; return True; } -@@ -863,7 +863,8 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UCh - if (!regs) - FAIL("evaluate_Dwarf3_Expr: " - "DW_OP_call_frame_cfa but no reg info"); --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - /* Valgrind on ppc32/ppc64 currently doesn't use unwind info. */ - uw1 = ML_(read_Addr)((UChar*)regs->sp); - #else -Index: coregrind/m_debuginfo/readdwarf.c -=================================================================== ---- coregrind/m_debuginfo/readdwarf.c.orig -+++ coregrind/m_debuginfo/readdwarf.c -@@ -1833,7 +1833,7 @@ void ML_(read_debuginfo_dwarf1) ( - # define FP_REG 1 - # define SP_REG 1 - # define RA_REG_DEFAULT 65 --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - # define FP_REG 1 - # define SP_REG 1 - # define RA_REG_DEFAULT 65 -@@ -1873,8 +1873,9 @@ void ML_(read_debuginfo_dwarf1) ( - arm-linux (320) seems ludicrously high, but the ARM IHI 0040A page - 7 (DWARF for the ARM Architecture) specifies that values up to 320 - might exist, for Neon/VFP-v3. */ --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) || defined(VGP_mips32_linux) \ -+ || defined(VGP_mips64_linux) - # define N_CFI_REGS 72 - #elif defined(VGP_arm_linux) - # define N_CFI_REGS 320 -@@ -2443,7 +2444,7 @@ static Bool summarise_context( /*OUT*/Di - # elif defined(VGA_arm64) - I_die_here; - --# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - /* These don't use CFI based unwinding (is that really true?) */ - - # else -@@ -2535,7 +2536,8 @@ static Int copy_convert_CfiExpr_tree ( X - return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP ); - # elif defined(VGA_arm64) - I_die_here; --# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \ -+ || defined(VGA_ppc64le) - # else - # error "Unknown arch" - # endif -@@ -3702,7 +3704,8 @@ void ML_(read_callframe_info_dwarf3) - if (!is_ehframe) - vg_assert(frame_avma == 0); - --# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - /* These targets don't use CFI-based stack unwinding. */ - return; - # endif -Index: coregrind/m_debuginfo/debuginfo.c -=================================================================== ---- coregrind/m_debuginfo/debuginfo.c.orig -+++ coregrind/m_debuginfo/debuginfo.c -@@ -825,8 +825,8 @@ ULong VG_(di_notify_mmap)( Addr a, Bool - || defined(VGA_mips64) - is_rx_map = seg->hasR && seg->hasX; - is_rw_map = seg->hasR && seg->hasW; --# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) \ -- || defined(VGA_arm64) -+# elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ -+ || defined(VGA_arm) || defined(VGA_arm64) - is_rx_map = seg->hasR && seg->hasX && !seg->hasW; - is_rw_map = seg->hasR && seg->hasW && !seg->hasX; - # elif defined(VGP_s390x_linux) -@@ -1611,7 +1611,7 @@ Bool get_sym_name ( Bool do_cxx_demangli - return True; - } - --/* ppc64-linux only: find the TOC pointer (R2 value) that should be in -+/* ppc64be-linux only: find the TOC pointer (R2 value) that should be in - force at the entry point address of the function containing - guest_code_addr. Returns 0 if not known. */ - Addr VG_(get_tocptr) ( Addr guest_code_addr ) -@@ -2251,7 +2251,8 @@ UWord evalCfiExpr ( XArray* exprs, Int i - case Creg_IA_SP: return eec->uregs->sp; - case Creg_IA_BP: return eec->uregs->fp; - case Creg_MIPS_RA: return eec->uregs->ra; --# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \ -+ || defined(VGA_ppc64le) - # elif defined(VGP_arm64_linux) - I_die_here; - # else -@@ -2497,7 +2498,7 @@ static Addr compute_cfa ( D3UnwindRegs* - case CFIC_IA_BPREL: - cfa = cfsi->cfa_off + uregs->fp; - break; --# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - # elif defined(VGP_arm64_linux) - I_die_here; - # else -@@ -2595,7 +2596,7 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindR - ipHere = uregsHere->ia; - # elif defined(VGA_mips32) || defined(VGA_mips64) - ipHere = uregsHere->pc; --# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - # elif defined(VGP_arm64_linux) - I_die_here; - # else -@@ -2677,7 +2678,7 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindR - COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi->ra_how, cfsi->ra_off); - COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi->sp_how, cfsi->sp_off); - COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi->fp_how, cfsi->fp_off); --# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - # elif defined(VGP_arm64_linux) - I_die_here; - # else -Index: coregrind/m_debuginfo/readelf.c -=================================================================== ---- coregrind/m_debuginfo/readelf.c.orig -+++ coregrind/m_debuginfo/readelf.c -@@ -204,19 +204,19 @@ void show_raw_elf_symbol ( DiImage* strt - .data, size of .data + size of .bss). I don't know if this is - really correct/justifiable, or not. - -- For ppc64-linux it's more complex. If the symbol is seen to be in -+ For ppc64be-linux it's more complex. If the symbol is seen to be in - the .opd section, it is taken to be a function descriptor, and so - a dereference is attempted, in order to get hold of the real entry - point address. Also as part of the dereference, there is an attempt - to calculate the TOC pointer (R2 value) associated with the symbol. - -- To support the ppc64-linux pre-"dotless" ABI (prior to gcc 4.0.0), -+ To support the ppc64be-linux pre-"dotless" ABI (prior to gcc 4.0.0), - if the symbol is seen to be outside the .opd section and its name - starts with a dot, an .opd deference is not attempted, and no TOC - pointer is calculated, but the the leading dot is removed from the - name. - -- As a result, on ppc64-linux, the caller of this function may have -+ As a result, on ppc64be-linux, the caller of this function may have - to piece together the real size, address, name of the symbol from - multiple calls to this function. Ugly and confusing. - */ -@@ -229,22 +229,22 @@ Bool get_elf_symbol_info ( - DiSlice* escn_strtab, /* holds the name */ - Addr sym_svma, /* address as stated in the object file */ - Bool symtab_in_debug, /* symbol table is in the debug file */ -- DiSlice* escn_opd, /* the .opd (ppc64-linux only) */ -+ DiSlice* escn_opd, /* the .opd (ppc64be-linux only) */ - PtrdiffT opd_bias, /* for biasing AVMAs found in .opd */ - /* OUTPUTS */ - DiOffT* sym_name_out_ioff, /* name (in strtab) we should record */ - Addr* sym_avma_out, /* addr we should record */ - Int* sym_size_out, /* symbol size */ -- Addr* sym_tocptr_out, /* ppc64-linux only: R2 value to be -+ Addr* sym_tocptr_out, /* ppc64be-linux only: R2 value to be - used on entry */ -- Bool* from_opd_out, /* ppc64-linux only: did we deref an -+ Bool* from_opd_out, /* ppc64be-linux only: did we deref an - .opd entry? */ - Bool* is_text_out, /* is this a text symbol? */ - Bool* is_ifunc /* is this a STT_GNU_IFUNC function ?*/ - ) - { - Bool plausible; --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - Bool is_in_opd; - # endif - Bool in_text, in_data, in_sdata, in_rodata, in_bss, in_sbss; -@@ -374,9 +374,9 @@ Bool get_elf_symbol_info ( - } - # endif - --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - /* Allow STT_NOTYPE in the very special case where we're running on -- ppc64-linux and the symbol is one which the .opd-chasing hack -+ ppc64be-linux and the symbol is one which the .opd-chasing hack - below will chase. */ - if (!plausible - && *is_text_out -@@ -473,7 +473,7 @@ Bool get_elf_symbol_info ( - return False; - } - -- /* ppc64-linux nasty hack: if the symbol is in an .opd section, -+ /* ppc64be-linux nasty hack: if the symbol is in an .opd section, - then really what we have is the address of a function - descriptor. So use the first word of that as the function's - text. -@@ -481,7 +481,8 @@ Bool get_elf_symbol_info ( - See thread starting at - http://gcc.gnu.org/ml/gcc-patches/2004-08/msg00557.html - */ --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) -+ /* Host and guest may have different Endianess, used by BE only */ - is_in_opd = False; - # endif - -@@ -489,7 +490,7 @@ Bool get_elf_symbol_info ( - && di->opd_size > 0 - && *sym_avma_out >= di->opd_avma - && *sym_avma_out < di->opd_avma + di->opd_size) { --# if !defined(VGP_ppc64_linux) -+# if !defined(VGP_ppc64be_linux) - if (TRACE_SYMTAB_ENABLED) { - HChar* sym_name = ML_(img_strdup)(escn_strtab->img, - "di.gesi.6", sym_name_ioff); -@@ -584,7 +585,7 @@ Bool get_elf_symbol_info ( - - /* Here's yet another ppc64-linux hack. Get rid of leading dot if - the symbol is outside .opd. */ --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - if (di->opd_size > 0 - && !is_in_opd - && *sym_name_out_ioff != DiOffT_INVALID -@@ -668,7 +669,7 @@ Bool get_elf_symbol_info ( - } - } - --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - /* It's crucial that we never add symbol addresses in the .opd - section. This would completely mess up function redirection and - intercepting. This assert ensures that any symbols that make it -@@ -692,7 +693,7 @@ void read_elf_symtab__normal( - struct _DebugInfo* di, const HChar* tab_name, - DiSlice* escn_symtab, - DiSlice* escn_strtab, -- DiSlice* escn_opd, /* ppc64-linux only */ -+ DiSlice* escn_opd, /* ppc64be-linux only */ - Bool symtab_in_debug - ) - { -@@ -768,7 +769,7 @@ void read_elf_symtab__normal( - - - /* Read an ELF symbol table (normal or dynamic). This one is for -- ppc64-linux, which requires special treatment. */ -+ ppc64be-linux, which requires special treatment. */ - - typedef - struct { -@@ -806,7 +807,7 @@ static Word cmp_TempSymKey ( TempSymKey* - - static - __attribute__((unused)) /* not referred to on all targets */ --void read_elf_symtab__ppc64_linux( -+void read_elf_symtab__ppc64be_linux( - struct _DebugInfo* di, const HChar* tab_name, - DiSlice* escn_symtab, - DiSlice* escn_strtab, -@@ -830,7 +831,7 @@ void read_elf_symtab__ppc64_linux( - return; - } - -- TRACE_SYMTAB("\n--- Reading (ELF, ppc64-linux) %s (%lld entries) ---\n", -+ TRACE_SYMTAB("\n--- Reading (ELF, ppc64be-linux) %s (%lld entries) ---\n", - tab_name, escn_symtab->szB/sizeof(ElfXX_Sym) ); - - oset = VG_(OSetGen_Create)( offsetof(TempSym,key), -@@ -2113,7 +2114,7 @@ Bool ML_(read_elf_debug_info) ( struct _ - BAD(".plt"); - } - } --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - /* Accept .plt where mapped as rw (data), or unmapped */ - if (0 == VG_(strcmp)(name, ".plt")) { - if (inrw && !di->plt_present) { -@@ -2226,7 +2227,7 @@ Bool ML_(read_elf_debug_info) ( struct _ - DiSlice dwarf1d_escn = DiSlice_INVALID; // .debug (dwarf1) - DiSlice dwarf1l_escn = DiSlice_INVALID; // .line (dwarf1) - DiSlice opd_escn = DiSlice_INVALID; // .opd (dwarf2, -- // ppc64-linux) -+ // ppc64be-linux) - DiSlice ehframe_escn[N_EHFRAME_SECTS]; // .eh_frame (dwarf2) - - for (i = 0; i < N_EHFRAME_SECTS; i++) -@@ -2729,8 +2730,8 @@ Bool ML_(read_elf_debug_info) ( struct _ - void (*read_elf_symtab)(struct _DebugInfo*, const HChar*, - DiSlice*, DiSlice*, DiSlice*, Bool); - Bool symtab_in_debug; --# if defined(VGP_ppc64_linux) -- read_elf_symtab = read_elf_symtab__ppc64_linux; -+# if defined(VGP_ppc64be_linux) -+ read_elf_symtab = read_elf_symtab__ppc64be_linux; - # else - read_elf_symtab = read_elf_symtab__normal; - # endif -@@ -2772,7 +2773,7 @@ Bool ML_(read_elf_debug_info) ( struct _ - seems OK though. Also skip on Android. */ - # if !defined(VGP_amd64_linux) \ - && !defined(VGP_s390x_linux) \ -- && !defined(VGP_ppc64_linux) \ -+ && !defined(VGP_ppc64be_linux) \ - && !defined(VGPV_arm_linux_android) \ - && !defined(VGPV_x86_linux_android) \ - && !defined(VGP_mips64_linux) -Index: coregrind/m_debuginfo/storage.c -=================================================================== ---- coregrind/m_debuginfo/storage.c.orig -+++ coregrind/m_debuginfo/storage.c -@@ -189,7 +189,7 @@ void ML_(ppDiCfSI) ( XArray* /* of CfiEx - SHOW_HOW(si->r11_how, si->r11_off); - VG_(printf)(" R7="); - SHOW_HOW(si->r7_how, si->r7_off); --# elif defined(VGA_ppc32) || defined(VGA_ppc64) -+# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - # elif defined(VGA_s390x) || defined(VGA_mips32) || defined(VGA_mips64) - VG_(printf)(" SP="); - SHOW_HOW(si->sp_how, si->sp_off); -Index: coregrind/m_stacktrace.c -=================================================================== ---- coregrind/m_stacktrace.c.orig -+++ coregrind/m_stacktrace.c -@@ -620,7 +620,8 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId - - /* -----------------------ppc32/64 ---------------------- */ - --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - - UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known, - /*OUT*/Addr* ips, UInt max_n_ips, -@@ -629,7 +630,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId - Addr fp_max_orig ) - { - Bool lr_is_first_RA = False; --# if defined(VG_PLAT_USES_PPCTOC) -+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - Word redir_stack_size = 0; - Word redirs_used = 0; - # endif -@@ -648,7 +649,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId - Addr fp = sp; - # if defined(VGP_ppc32_linux) - Addr lr = startRegs->misc.PPC32.r_lr; --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - Addr lr = startRegs->misc.PPC64.r_lr; - # endif - Addr fp_min = sp; -@@ -684,7 +685,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId - /* fp is %r1. ip is %cia. Note, ppc uses r1 as both the stack and - frame pointers. */ - --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - redir_stack_size = VEX_GUEST_PPC64_REDIR_STACK_SIZE; - redirs_used = 0; - # endif -@@ -740,7 +741,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId - /* On ppc64-linux (ppc64-elf, really), the lr save - slot is 2 words back from sp, whereas on ppc32-elf(?) it's - only one word back. */ --# if defined(VG_PLAT_USES_PPCTOC) -+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - const Int lr_offset = 2; - # else - const Int lr_offset = 1; -@@ -759,7 +760,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId - else - ip = (((UWord*)fp)[lr_offset]); - --# if defined(VG_PLAT_USES_PPCTOC) -+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - /* Nasty hack to do with function replacement/wrapping on - ppc64-linux. If LR points to our magic return stub, - then we are in a wrapped or intercepted function, in -Index: coregrind/m_translate.c -=================================================================== ---- coregrind/m_translate.c.orig -+++ coregrind/m_translate.c -@@ -868,7 +868,7 @@ static Bool chase_into_ok ( void* closur - if (addr != VG_(redir_do_lookup)(addr, NULL)) - goto dontchase; - --# if defined(VG_PLAT_USES_PPCTOC) -+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - /* This needs to be at the start of its own block. Don't chase. Re - ULong_to_Ptr, be careful to ensure we only compare 32 bits on a - 32-bit target.*/ -@@ -918,7 +918,7 @@ static IRExpr* mkU32 ( UInt n ) { - return IRExpr_Const(IRConst_U32(n)); - } - --#if defined(VG_PLAT_USES_PPCTOC) -+#if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - static IRExpr* mkU8 ( UChar n ) { - return IRExpr_Const(IRConst_U8(n)); - } -@@ -941,7 +941,7 @@ static void gen_PUSH ( IRSB* bb, IRExpr* - IRTemp t1; - IRExpr* one; - --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - Int stack_size = VEX_GUEST_PPC64_REDIR_STACK_SIZE; - Int offB_REDIR_SP = offsetof(VexGuestPPC64State,guest_REDIR_SP); - Int offB_REDIR_STACK = offsetof(VexGuestPPC64State,guest_REDIR_STACK); -@@ -1035,7 +1035,7 @@ static void gen_PUSH ( IRSB* bb, IRExpr* - - static IRTemp gen_POP ( IRSB* bb ) - { --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - Int stack_size = VEX_GUEST_PPC64_REDIR_STACK_SIZE; - Int offB_REDIR_SP = offsetof(VexGuestPPC64State,guest_REDIR_SP); - Int offB_REDIR_STACK = offsetof(VexGuestPPC64State,guest_REDIR_STACK); -@@ -1127,7 +1127,7 @@ static IRTemp gen_POP ( IRSB* bb ) - - static void gen_push_and_set_LR_R2 ( IRSB* bb, Addr64 new_R2_value ) - { --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - Addr64 bogus_RA = (Addr64)&VG_(ppctoc_magic_redirect_return_stub); - Int offB_GPR2 = offsetof(VexGuestPPC64State,guest_GPR2); - Int offB_LR = offsetof(VexGuestPPC64State,guest_LR); -@@ -1143,7 +1143,7 @@ static void gen_push_and_set_LR_R2 ( IRS - - static void gen_pop_R2_LR_then_bLR ( IRSB* bb ) - { --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - Int offB_GPR2 = offsetof(VexGuestPPC64State,guest_GPR2); - Int offB_LR = offsetof(VexGuestPPC64State,guest_LR); - Int offB_CIA = offsetof(VexGuestPPC64State,guest_CIA); -@@ -1277,7 +1277,7 @@ Bool mk_preamble__set_NRADDR_to_nraddr ( - Int offB_GPR25 = offsetof(VexGuestMIPS64State, guest_r25); - addStmtToIRSB(bb, IRStmt_Put(offB_GPR25, mkU64(closure->readdr))); - # endif --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - addStmtToIRSB( - bb, - IRStmt_Put( -@@ -1513,7 +1513,7 @@ Bool VG_(translate) ( ThreadId tid, - vex_abiinfo.guest_ppc_zap_RZ_at_bl = NULL; - vex_abiinfo.host_ppc32_regalign_int64_args = True; - # endif --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - vex_abiinfo.guest_ppc_zap_RZ_at_blr = True; - vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True; - vex_abiinfo.host_ppc_calls_use_fndescrs = True; -Index: coregrind/m_signals.c -=================================================================== ---- coregrind/m_signals.c.orig -+++ coregrind/m_signals.c -@@ -348,7 +348,7 @@ typedef struct SigQueue { - (srP)->misc.PPC32.r_lr = (uc)->uc_regs->mc_gregs[VKI_PT_LNK]; \ - } - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - # define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_NIP]) - # define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_R1]) - /* Dubious hack: if there is an error, only consider the lowest 8 -@@ -851,7 +851,7 @@ extern void my_sigreturn(void); - " sc\n" \ - ".previous\n" - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) - # define _MY_SIGRETURN(name) \ - ".align 2\n" \ - ".globl my_sigreturn\n" \ -Index: coregrind/pub_core_trampoline.h -=================================================================== ---- coregrind/pub_core_trampoline.h.orig -+++ coregrind/pub_core_trampoline.h -@@ -81,7 +81,7 @@ extern UInt VG_(ppc32_linux_REDIR_FOR_s - extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int ); - #endif - --#if defined(VGP_ppc64_linux) -+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - extern Addr VG_(ppc64_linux_SUBST_FOR_rt_sigreturn); - extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* ); - extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int ); -Index: coregrind/m_debugger.c -=================================================================== ---- coregrind/m_debugger.c.orig -+++ coregrind/m_debugger.c -@@ -152,7 +152,7 @@ static Int ptrace_setregs(Int pid, VexGu - (void*)LibVEX_GuestPPC32_get_XER(vex)); - return rc; - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - Int rc = 0; - /* FRJ: copied nearly verbatim from the ppc32 case. I compared the - vki-ppc64-linux.h with its ppc32 counterpart and saw no -Index: coregrind/pub_core_transtab_asm.h -=================================================================== ---- coregrind/pub_core_transtab_asm.h.orig -+++ coregrind/pub_core_transtab_asm.h -@@ -62,8 +62,8 @@ - #elif defined(VGA_s390x) || defined(VGA_arm) - # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK) - --#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_mips32) \ -- || defined(VGA_mips64) || defined(VGA_arm64) -+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ -+ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) - # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK) - - #else -Index: coregrind/m_scheduler/scheduler.c -=================================================================== ---- coregrind/m_scheduler/scheduler.c.orig -+++ coregrind/m_scheduler/scheduler.c -@@ -766,7 +766,7 @@ static void do_pre_run_checks ( ThreadSt - vg_assert(VG_IS_8_ALIGNED(offsetof(VexGuestAMD64State,guest_RIP))); - # endif - --# if defined(VGA_ppc32) || defined(VGA_ppc64) -+# if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - /* ppc guest_state vector regs must be 16 byte aligned for - loads/stores. This is important! */ - vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VSR0)); -@@ -1601,7 +1601,7 @@ void VG_(nuke_all_threads_except) ( Thre - #elif defined(VGA_amd64) - # define VG_CLREQ_ARGS guest_RAX - # define VG_CLREQ_RET guest_RDX --#elif defined(VGA_ppc32) || defined(VGA_ppc64) -+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - # define VG_CLREQ_ARGS guest_GPR4 - # define VG_CLREQ_RET guest_GPR3 - #elif defined(VGA_arm) -Index: coregrind/m_gdbserver/target.c -=================================================================== ---- coregrind/m_gdbserver/target.c.orig -+++ coregrind/m_gdbserver/target.c -@@ -645,7 +645,7 @@ void valgrind_initialize_target(void) - arm_init_architecture(&the_low_target); - #elif defined(VGA_ppc32) - ppc32_init_architecture(&the_low_target); --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - ppc64_init_architecture(&the_low_target); - #elif defined(VGA_s390x) - s390x_init_architecture(&the_low_target); -Index: coregrind/pub_core_debuginfo.h -=================================================================== ---- coregrind/pub_core_debuginfo.h.orig -+++ coregrind/pub_core_debuginfo.h -@@ -122,7 +122,7 @@ typedef - typedef - struct { Addr pc; Addr sp; Addr lr; Addr fp; } /* PC, 31, 30, 29 */ - D3UnwindRegs; --#elif defined(VGA_ppc32) || defined(VGA_ppc64) -+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - typedef - UChar /* should be void, but gcc complains at use points */ - D3UnwindRegs; -Index: coregrind/m_dispatch/dispatch-ppc64-linux.S -=================================================================== ---- coregrind/m_dispatch/dispatch-ppc64-linux.S.orig -+++ coregrind/m_dispatch/dispatch-ppc64-linux.S -@@ -28,7 +28,7 @@ - The GNU General Public License is contained in the file COPYING. - */ - --#if defined(VGP_ppc64_linux) -+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - #include "pub_core_basics_asm.h" - #include "pub_core_dispatch_asm.h" -@@ -193,7 +193,7 @@ VG_(disp_run_translations): - /* 88(sp) used later to load fpscr with zero */ - /* 48:87(sp) free */ - -- /* Linkage Area (reserved) -+ /* Linkage Area (reserved) BE ABI - 40(sp) : TOC - 32(sp) : link editor doubleword - 24(sp) : compiler doubleword -@@ -530,7 +530,7 @@ VG_(disp_cp_evcheck_fail): - /* Let the linker know we don't need an executable stack */ - .section .note.GNU-stack,"",@progbits - --#endif // defined(VGP_ppc64_linux) -+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - /*--------------------------------------------------------------------*/ - /*--- end ---*/ -Index: coregrind/m_initimg/initimg-linux.c -=================================================================== ---- coregrind/m_initimg/initimg-linux.c.orig -+++ coregrind/m_initimg/initimg-linux.c -@@ -366,7 +366,7 @@ struct auxv *find_auxv(UWord* sp) - sp++; - sp++; - --#if defined(VGA_ppc32) || defined(VGA_ppc64) -+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - # if defined AT_IGNOREPPC - while (*sp == AT_IGNOREPPC) // skip AT_IGNOREPPC entries - sp += 2; -@@ -457,7 +457,8 @@ Addr setup_client_stack( void* init_sp, - auxsize += sizeof(*cauxv); - } - --# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - auxsize += 2 * sizeof(*cauxv); - # endif - -@@ -614,7 +615,8 @@ Addr setup_client_stack( void* init_sp, - // We do not take ULong* (as ULong 8 bytes on a 32 bits), - // => we take UWord* - --# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - auxv[0].a_type = AT_IGNOREPPC; - auxv[0].u.a_val = AT_IGNOREPPC; - auxv[1].a_type = AT_IGNOREPPC; -@@ -719,7 +721,7 @@ Addr setup_client_stack( void* init_sp, - "PPC32 icache line size %u (type %u)\n", - (UInt)auxv->u.a_val, (UInt)auxv->a_type ); - } --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - /* acquire cache info */ - if (auxv->u.a_val > 0) { - VG_(machine_ppc64_set_clszB)( auxv->u.a_val ); -@@ -730,7 +732,8 @@ Addr setup_client_stack( void* init_sp, - # endif - break; - --# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - case AT_IGNOREPPC: - break; - # endif -@@ -750,7 +753,8 @@ Addr setup_client_stack( void* init_sp, - auxv->a_type = AT_IGNORE; - break; - --# if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64_linux) -+# if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64be_linux) \ -+ && !defined(VGP_ppc64le_linux) - case AT_SYSINFO_EHDR: { - /* Trash this, because we don't reproduce it */ - const NSegment* ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr); -@@ -1036,7 +1040,7 @@ void VG_(ii_finalise_image)( IIFinaliseI - arch->vex.guest_GPR1 = iifii.initial_client_SP; - arch->vex.guest_CIA = iifii.initial_client_IP; - --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - vg_assert(0 == sizeof(VexGuestPPC64State) % 16); - - /* Zero out the initial state, and set up the simulated FPU in a -Index: coregrind/m_main.c -=================================================================== ---- coregrind/m_main.c.orig -+++ coregrind/m_main.c -@@ -2016,7 +2016,8 @@ Int valgrind_main ( Int argc, HChar **ar - - # if defined(VGP_x86_linux) - iters = 10; --# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) -+# elif defined(VGP_amd64_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - iters = 10; - # elif defined(VGP_ppc32_linux) - iters = 5; -@@ -2570,7 +2571,7 @@ void shutdown_actions_NORETURN( ThreadId - static void final_tidyup(ThreadId tid) - { - #if !defined(VGO_darwin) --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - Addr r2; - # endif - Addr __libc_freeres_wrapper = VG_(client___libc_freeres_wrapper); -@@ -2582,7 +2583,7 @@ static void final_tidyup(ThreadId tid) - 0 == __libc_freeres_wrapper ) - return; /* can't/won't do it */ - --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - r2 = VG_(get_tocptr)( __libc_freeres_wrapper ); - if (r2 == 0) { - VG_(message)(Vg_UserMsg, -@@ -2600,12 +2601,12 @@ static void final_tidyup(ThreadId tid) - "Caught __NR_exit; running __libc_freeres()\n"); - - /* set thread context to point to libc_freeres_wrapper */ -- /* ppc64-linux note: __libc_freeres_wrapper gives us the real -+ /* ppc64be-linux note: __libc_freeres_wrapper gives us the real - function entry point, not a fn descriptor, so can use it - directly. However, we need to set R2 (the toc pointer) - appropriately. */ - VG_(set_IP)(tid, __libc_freeres_wrapper); --# if defined(VGP_ppc64_linux) -+# if defined(VGP_ppc64be_linux) - VG_(threads)[tid].arch.vex.guest_GPR2 = r2; - # endif - /* mips-linux note: we need to set t9 */ -@@ -2802,7 +2803,7 @@ asm("\n" - "\ttrap\n" - ".previous\n" - ); --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) - asm("\n" - /* PPC64 ELF ABI says '_start' points to a function descriptor. - So we must have one, and that is what goes into the .opd section. */ -@@ -3061,10 +3062,10 @@ void _start_in_C_linux ( UWord* pArgc ) - - the_iicii.sp_at_startup = (Addr)pArgc; - --# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -- || defined(VGP_arm64_linux) -+# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux) - { -- /* ppc/ppc64 can be configured with different page sizes. -+ /* ppc32/ppc64 can be configured with different page sizes. - Determine this early. This is an ugly hack and really should - be moved into valgrind_main. */ - UWord *sp = &pArgc[1+argc+1]; -Index: coregrind/m_libcassert.c -=================================================================== ---- coregrind/m_libcassert.c.orig -+++ coregrind/m_libcassert.c -@@ -96,7 +96,7 @@ - (srP)->r_sp = (ULong)r1; \ - (srP)->misc.PPC32.r_lr = lr; \ - } --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - # define GET_STARTREGS(srP) \ - { ULong cia, r1, lr; \ - __asm__ __volatile__( \ -Index: coregrind/m_libcfile.c -=================================================================== ---- coregrind/m_libcfile.c.orig -+++ coregrind/m_libcfile.c -@@ -649,8 +649,8 @@ SysRes VG_(pread) ( Int fd, void* buf, I - res = VG_(do_syscall6)(__NR_pread64, fd, (UWord)buf, count, - 0, 0, offset); - return res; --# elif defined(VGP_amd64_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \ -+# elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGP_mips64_linux) \ - || defined(VGP_arm64_linux) - res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset); -@@ -895,7 +895,8 @@ static Int parse_inet_addr_and_port ( co - Int VG_(socket) ( Int domain, Int type, Int protocol ) - { - # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_s390x_linux) - SysRes res; - UWord args[3]; - args[0] = domain; -@@ -935,7 +936,8 @@ static - Int my_connect ( Int sockfd, struct vki_sockaddr_in* serv_addr, Int addrlen ) - { - # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_s390x_linux) - SysRes res; - UWord args[3]; - args[0] = sockfd; -@@ -974,7 +976,8 @@ Int VG_(write_socket)( Int sd, const voi - SIGPIPE */ - - # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_s390x_linux) - SysRes res; - UWord args[4]; - args[0] = sd; -@@ -1005,7 +1008,8 @@ Int VG_(write_socket)( Int sd, const voi - Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen) - { - # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_s390x_linux) \ - || defined(VGP_mips32_linux) - SysRes res; - UWord args[3]; -@@ -1036,7 +1040,8 @@ Int VG_(getsockname) ( Int sd, struct vk - Int VG_(getpeername) ( Int sd, struct vki_sockaddr *name, Int *namelen) - { - # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_s390x_linux) \ - || defined(VGP_mips32_linux) - SysRes res; - UWord args[3]; -@@ -1068,7 +1073,8 @@ Int VG_(getsockopt) ( Int sd, Int level, - Int *optlen) - { - # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_s390x_linux) - SysRes res; - UWord args[5]; - args[0] = sd; -@@ -1105,7 +1111,8 @@ Int VG_(setsockopt) ( Int sd, Int level, - Int optlen) - { - # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \ -- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ -+ || defined(VGP_s390x_linux) - SysRes res; - UWord args[5]; - args[0] = sd; -Index: coregrind/launcher-linux.c -=================================================================== ---- coregrind/launcher-linux.c.orig -+++ coregrind/launcher-linux.c -@@ -236,7 +236,7 @@ static const char *select_platform(const - if (ehdr->e_machine == EM_PPC64 && - (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || - ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { -- platform = "ppc64-linux"; -+ platform = "ppc64be-linux"; - } - else - if (ehdr->e_machine == EM_S390 && -@@ -320,7 +320,7 @@ int main(int argc, char** argv, char** e - if ((0==strcmp(VG_PLATFORM,"x86-linux")) || - (0==strcmp(VG_PLATFORM,"amd64-linux")) || - (0==strcmp(VG_PLATFORM,"ppc32-linux")) || -- (0==strcmp(VG_PLATFORM,"ppc64-linux")) || -+ (0==strcmp(VG_PLATFORM,"ppc64be-linux")) || - (0==strcmp(VG_PLATFORM,"arm-linux")) || - (0==strcmp(VG_PLATFORM,"arm64-linux")) || - (0==strcmp(VG_PLATFORM,"s390x-linux")) || -Index: coregrind/m_coredump/coredump-elf.c -=================================================================== ---- coregrind/m_coredump/coredump-elf.c.orig -+++ coregrind/m_coredump/coredump-elf.c -@@ -322,7 +322,7 @@ static void fill_prstatus(const ThreadSt - regs->dsisr = 0; - regs->result = 0; - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) - # define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n - DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); - DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); -@@ -458,7 +458,7 @@ static void fill_fpu(const ThreadState * - DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31); - # undef DO - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - /* The guest state has the FPR fields declared as ULongs, so need - to fish out the values without converting them. - NOTE: The 32 FP registers map to the first 32 VSX registers.*/ -Index: coregrind/m_machine.c -=================================================================== ---- coregrind/m_machine.c.orig -+++ coregrind/m_machine.c -@@ -81,7 +81,7 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/U - regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_GPR1; - regs->misc.PPC32.r_lr - = VG_(threads)[tid].arch.vex.guest_LR; --# elif defined(VGA_ppc64) -+# elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - regs->r_pc = VG_(threads)[tid].arch.vex.guest_CIA; - regs->r_sp = VG_(threads)[tid].arch.vex.guest_GPR1; - regs->misc.PPC64.r_lr -@@ -212,7 +212,7 @@ static void apply_to_GPs_of_tid(ThreadId - (*f)(tid, "R13", vex->guest_R13); - (*f)(tid, "R14", vex->guest_R14); - (*f)(tid, "R15", vex->guest_R15); --#elif defined(VGA_ppc32) || defined(VGA_ppc64) -+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - (*f)(tid, "GPR0" , vex->guest_GPR0 ); - (*f)(tid, "GPR1" , vex->guest_GPR1 ); - (*f)(tid, "GPR2" , vex->guest_GPR2 ); -@@ -413,7 +413,7 @@ UInt VG_(machine_x86_have_mxcsr) = 0; - UInt VG_(machine_ppc32_has_FP) = 0; - UInt VG_(machine_ppc32_has_VMX) = 0; - #endif --#if defined(VGA_ppc64) -+#if defined(VGA_ppc64be) || defined(VGA_ppc64le) - ULong VG_(machine_ppc64_has_VMX) = 0; - #endif - #if defined(VGA_arm) -@@ -423,7 +423,7 @@ Int VG_(machine_arm_archlevel) = 4; - - /* For hwcaps detection on ppc32/64, s390x, and arm we'll need to do SIGILL - testing, so we need a VG_MINIMAL_JMP_BUF. */ --#if defined(VGA_ppc32) || defined(VGA_ppc64) \ -+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ - || defined(VGA_arm) || defined(VGA_s390x) || defined(VGA_mips32) - #include "pub_core_libcsetjmp.h" - static VG_MINIMAL_JMP_BUF(env_unsup_insn); -@@ -441,7 +441,7 @@ static void handler_unsup_insn ( Int x ) - * Not very defensive: assumes that as long as the dcbz/dcbzl - * instructions don't raise a SIGILL, that they will zero an aligned, - * contiguous block of memory of a sensible size. */ --#if defined(VGA_ppc32) || defined(VGA_ppc64) -+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - static void find_ppc_dcbz_sz(VexArchInfo *arch_info) - { - Int dcbz_szB = 0; -@@ -494,7 +494,7 @@ static void find_ppc_dcbz_sz(VexArchInfo - dcbz_szB, dcbzl_szB); - # undef MAX_DCBZL_SZB - } --#endif /* defined(VGA_ppc32) || defined(VGA_ppc64) */ -+#endif /* defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) */ - - #ifdef VGA_s390x - -@@ -1033,7 +1033,7 @@ Bool VG_(machine_get_hwcaps)( void ) - return True; - } - --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be)|| defined(VGA_ppc64le) - { - /* Same instruction set detection algorithm as for ppc32. */ - vki_sigset_t saved_set, tmp_set; -@@ -1147,7 +1147,7 @@ Bool VG_(machine_get_hwcaps)( void ) - (Int)have_F, (Int)have_V, (Int)have_FX, - (Int)have_GX, (Int)have_VX, (Int)have_DFP, - (Int)have_isa_2_07); -- /* on ppc64, if we don't even have FP, just give up. */ -+ /* on ppc64be, if we don't even have FP, just give up. */ - if (!have_F) - return False; - -@@ -1565,7 +1565,7 @@ void VG_(machine_ppc32_set_clszB)( Int s - - - /* Notify host cpu instruction cache line size. */ --#if defined(VGA_ppc64) -+#if defined(VGA_ppc64be)|| defined(VGA_ppc64le) - void VG_(machine_ppc64_set_clszB)( Int szB ) - { - vg_assert(hwcaps_done); -@@ -1647,7 +1647,7 @@ Int VG_(machine_get_size_of_largest_gues - if (vai.hwcaps & VEX_HWCAPS_PPC32_DFP) return 16; - return 8; - --# elif defined(VGA_ppc64) -+# elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - /* 8 if boring; 16 if signs of Altivec or other exotic stuff */ - if (vai.hwcaps & VEX_HWCAPS_PPC64_V) return 16; - if (vai.hwcaps & VEX_HWCAPS_PPC64_VX) return 16; -@@ -1685,12 +1685,12 @@ Int VG_(machine_get_size_of_largest_gues - void* VG_(fnptr_to_fnentry)( void* f ) - { - # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ -- || defined(VGP_arm_linux) \ -- || defined(VGP_ppc32_linux) || defined(VGO_darwin) \ -+ || defined(VGP_arm_linux) || defined(VGO_darwin) \ -+ || defined(VGP_ppc32_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ - || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - return f; --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) - /* ppc64-linux uses the AIX scheme, in which f is a pointer to a - 3-word function descriptor, of which the first word is the entry - address. */ -Index: coregrind/m_syscall.c -=================================================================== ---- coregrind/m_syscall.c.orig -+++ coregrind/m_syscall.c -@@ -386,7 +386,7 @@ asm( - ".previous\n" - ); - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) - /* Due to the need to return 65 bits of result, this is completely - different from the ppc32 case. The single arg register points to a - 7-word block containing the syscall # and the 6 args. The syscall -@@ -720,7 +720,7 @@ SysRes VG_(do_syscall) ( UWord sysno, UW - UInt cr0so = (UInt)(ret); - return VG_(mk_SysRes_ppc32_linux)( val, cr0so ); - --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - ULong argblock[7]; - argblock[0] = sysno; - argblock[1] = a1; -Index: coregrind/m_ume/macho.c -=================================================================== ---- coregrind/m_ume/macho.c.orig -+++ coregrind/m_ume/macho.c -@@ -699,8 +699,8 @@ load_fat_file(int fd, vki_off_t offset, - - #if defined(VGA_ppc32) - good_arch = CPU_TYPE_POWERPC; --#elif defined(VGA_ppc64) -- good_arch = CPU_TYPE_POWERPC64; -+#elif defined(VGA_ppc64be) -+ good_arch = CPU_TYPE_POWERPC64BE; - #elif defined(VGA_x86) - good_arch = CPU_TYPE_I386; - #elif defined(VGA_amd64) -Index: coregrind/m_ume/elf.c -=================================================================== ---- coregrind/m_ume/elf.c.orig -+++ coregrind/m_ume/elf.c -@@ -511,9 +511,9 @@ Int VG_(load_ELF)(Int fd, const HChar* n - info->exe_base = minaddr + ebase; - info->exe_end = maxaddr + ebase; - --#if defined(VGP_ppc64_linux) -- /* On PPC64, a func ptr is represented by a TOC entry ptr. This -- TOC entry contains three words; the first word is the function -+#if defined(VGP_ppc64be_linux) -+ /* On PPC64BE, ELF ver 1, a func ptr is represented by a TOC entry ptr. -+ This TOC entry contains three words; the first word is the function - address, the second word is the TOC ptr (r2), and the third word - is the static chain value. */ - info->init_ip = ((ULong*)entry)[0]; -Index: coregrind/launcher-darwin.c -=================================================================== ---- coregrind/launcher-darwin.c.orig -+++ coregrind/launcher-darwin.c -@@ -59,11 +59,11 @@ static struct { - const char *apple_name; // e.g. x86_64 - const char *valgrind_name; // e.g. amd64 - } valid_archs[] = { -- { CPU_TYPE_X86, "i386", "x86" }, -- { CPU_TYPE_X86_64, "x86_64", "amd64" }, -- { CPU_TYPE_ARM, "arm", "arm" }, -- { CPU_TYPE_POWERPC, "ppc", "ppc32" }, -- { CPU_TYPE_POWERPC64, "ppc64", "ppc64" }, -+ { CPU_TYPE_X86, "i386", "x86" }, -+ { CPU_TYPE_X86_64, "x86_64", "amd64" }, -+ { CPU_TYPE_ARM, "arm", "arm" }, -+ { CPU_TYPE_POWERPC, "ppc", "ppc32" }, -+ { CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" }, - }; - static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]); - -Index: coregrind/pub_core_threadstate.h -=================================================================== ---- coregrind/pub_core_threadstate.h.orig -+++ coregrind/pub_core_threadstate.h -@@ -84,7 +84,7 @@ typedef - typedef VexGuestAMD64State VexGuestArchState; - #elif defined(VGA_ppc32) - typedef VexGuestPPC32State VexGuestArchState; --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - typedef VexGuestPPC64State VexGuestArchState; - #elif defined(VGA_arm) - typedef VexGuestARMState VexGuestArchState; -Index: coregrind/m_aspacemgr/aspacemgr-common.c -=================================================================== ---- coregrind/m_aspacemgr/aspacemgr-common.c.orig -+++ coregrind/m_aspacemgr/aspacemgr-common.c -@@ -162,7 +162,8 @@ SysRes VG_(am_do_mmap_NO_NOTIFY)( Addr s - aspacem_assert((offset % 4096) == 0); - res = VG_(do_syscall6)(__NR_mmap2, (UWord)start, length, - prot, flags, fd, offset / 4096); --# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \ -+# elif defined(VGP_amd64_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \ - || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length, -Index: coregrind/m_syswrap/syswrap-main.c -=================================================================== ---- coregrind/m_syswrap/syswrap-main.c.orig -+++ coregrind/m_syswrap/syswrap-main.c -@@ -441,7 +441,7 @@ void getSyscallArgsFromGuestState ( /*OU - canonical->arg7 = 0; - canonical->arg8 = 0; - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla; - canonical->sysno = gst->guest_GPR0; - canonical->arg1 = gst->guest_GPR3; -@@ -687,7 +687,7 @@ void putSyscallArgsIntoGuestState ( /*IN - gst->guest_GPR7 = canonical->arg5; - gst->guest_GPR8 = canonical->arg6; - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla; - gst->guest_GPR0 = canonical->sysno; - gst->guest_GPR3 = canonical->arg1; -@@ -818,7 +818,7 @@ void getSyscallStatusFromGuestState ( /* - canonical->sres = VG_(mk_SysRes_ppc32_linux)( gst->guest_GPR3, cr0so ); - canonical->what = SsComplete; - --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla; - UInt cr = LibVEX_GuestPPC64_get_CR( gst ); - UInt cr0so = (cr >> 28) & 1; -@@ -976,7 +976,7 @@ void putSyscallStatusIntoGuestState ( /* - VG_TRACK( post_reg_write, Vg_CoreSysCall, tid, - OFFSET_ppc32_CR0_0, sizeof(UChar) ); - --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla; - UInt old_cr = LibVEX_GuestPPC64_get_CR(gst); - vg_assert(canonical->what == SsComplete); -@@ -1181,7 +1181,7 @@ void getSyscallArgLayout ( /*OUT*/Syscal - layout->uu_arg7 = -1; /* impossible value */ - layout->uu_arg8 = -1; /* impossible value */ - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - layout->o_sysno = OFFSET_ppc64_GPR0; - layout->o_arg1 = OFFSET_ppc64_GPR3; - layout->o_arg2 = OFFSET_ppc64_GPR4; -@@ -1987,7 +1987,7 @@ void ML_(fixup_guest_state_to_restart_sy - vg_assert(p[0] == 0x0F && p[1] == 0x05); - } - --#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) - arch->vex.guest_CIA -= 4; // sizeof(ppc32 instr) - - /* Make sure our caller is actually sane, and we're really backing -Index: coregrind/m_syswrap/syswrap-ppc64-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-ppc64-linux.c.orig -+++ coregrind/m_syswrap/syswrap-ppc64-linux.c -@@ -28,7 +28,7 @@ - The GNU General Public License is contained in the file COPYING. - */ - --#if defined(VGP_ppc64_linux) -+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - #include "pub_core_basics.h" - #include "pub_core_vki.h" -@@ -1072,7 +1072,7 @@ SyscallTableEntry* ML_(get_linux_syscall - return NULL; - } - --#endif // defined(VGP_ppc64_linux) -+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - /*--------------------------------------------------------------------*/ - /*--- end ---*/ -Index: coregrind/m_syswrap/syswrap-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-linux.c.orig -+++ coregrind/m_syswrap/syswrap-linux.c -@@ -244,7 +244,8 @@ static void run_a_thread_NORETURN ( Word - : "n" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode) - : "rax", "rdi" - ); --#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - { UInt vgts_empty = (UInt)VgTs_Empty; - asm volatile ( - "stw %1,%0\n\t" /* set tst->status = VgTs_Empty */ -@@ -385,7 +386,7 @@ void VG_(main_thread_wrapper_NORETURN)(T - sp -= 16; - sp &= ~0xF; - *(UWord *)sp = 0; --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - /* make a stack frame */ - sp -= 112; - sp &= ~((Addr)0xF); -@@ -438,7 +439,8 @@ SysRes ML_(do_fork_clone) ( ThreadId tid - /* Since this is the fork() form of clone, we don't need all that - VG_(clone) stuff */ - #if defined(VGP_x86_linux) \ -- || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -+ || defined(VGP_ppc32_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \ - || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - res = VG_(do_syscall5)( __NR_clone, flags, -Index: coregrind/m_syswrap/priv_types_n_macros.h -=================================================================== ---- coregrind/m_syswrap/priv_types_n_macros.h.orig -+++ coregrind/m_syswrap/priv_types_n_macros.h -@@ -90,7 +90,8 @@ typedef - // field names), the s_arg value is the offset from the stack pointer. - Int o_sysno; - # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \ -- || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -+ || defined(VGP_ppc32_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGP_arm_linux) || defined(VGP_s390x_linux) \ - || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) - Int o_arg1; -Index: coregrind/m_syswrap/syscall-ppc64-linux.S -=================================================================== ---- coregrind/m_syswrap/syscall-ppc64-linux.S.orig -+++ coregrind/m_syswrap/syscall-ppc64-linux.S -@@ -27,7 +27,7 @@ - The GNU General Public License is contained in the file COPYING. - */ - --#if defined(VGP_ppc64_linux) -+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - #include "pub_core_basics_asm.h" - #include "pub_core_vkiscnums_asm.h" -@@ -165,7 +165,7 @@ ML_(blksys_finished): .quad 5b - /* Let the linker know we don't need an executable stack */ - .section .note.GNU-stack,"",@progbits - --#endif // defined(VGP_ppc64_linux) -+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - /*--------------------------------------------------------------------*/ - /*--- end ---*/ -Index: coregrind/m_debuglog.c -=================================================================== ---- coregrind/m_debuglog.c.orig -+++ coregrind/m_debuglog.c -@@ -189,7 +189,7 @@ static UInt local_sys_getpid ( void ) - return __res; - } - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - static UInt local_sys_write_stderr ( const HChar* buf, Int n ) - { -Index: coregrind/m_vki.c -=================================================================== ---- coregrind/m_vki.c.orig -+++ coregrind/m_vki.c -@@ -42,8 +42,8 @@ - /* ppc32/64-linux determines page size at startup, hence m_vki is - the logical place to store that info. */ - --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -- || defined(VGP_arm64_linux) -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux) - unsigned long VKI_PAGE_SHIFT = 12; - unsigned long VKI_PAGE_SIZE = 1UL << 12; - #endif -Index: coregrind/pub_core_basics.h -=================================================================== ---- coregrind/pub_core_basics.h.orig -+++ coregrind/pub_core_basics.h -@@ -54,7 +54,7 @@ - # include "libvex_guest_amd64.h" - #elif defined(VGA_ppc32) - # include "libvex_guest_ppc32.h" --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - # include "libvex_guest_ppc64.h" - #elif defined(VGA_arm) - # include "libvex_guest_arm.h" -Index: coregrind/m_sigframe/sigframe-ppc64-linux.c -=================================================================== ---- coregrind/m_sigframe/sigframe-ppc64-linux.c.orig -+++ coregrind/m_sigframe/sigframe-ppc64-linux.c -@@ -31,7 +31,7 @@ - The GNU General Public License is contained in the file COPYING. - */ - --#if defined(VGP_ppc64_linux) -+#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - #include "pub_core_basics.h" - #include "pub_core_vki.h" -@@ -388,7 +388,7 @@ void VG_(sigframe_destroy)( ThreadId tid - VG_TRACK( post_deliver_signal, tid, sigNo ); - } - --#endif // defined(VGP_ppc64_linux) -+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - /*--------------------------------------------------------------------*/ - /*--- end ---*/ -Index: coregrind/m_libcsetjmp.c -=================================================================== ---- coregrind/m_libcsetjmp.c.orig -+++ coregrind/m_libcsetjmp.c -@@ -149,7 +149,7 @@ __asm__( - - /* ------------ ppc64-linux ------------ */ - --#if defined(VGP_ppc64_linux) -+#if defined(VGP_ppc64be_linux) - - __asm__( - ".section \".toc\",\"aw\"" "\n" -@@ -270,7 +270,7 @@ __asm__( - ".previous" "\n" - ); - --#endif /* VGP_ppc64_linux */ -+#endif /* VGP_ppc64be_linux */ - - - /* ------------ amd64-{linux,darwin} ------------ */ -Index: coregrind/m_libcproc.c -=================================================================== ---- coregrind/m_libcproc.c.orig -+++ coregrind/m_libcproc.c -@@ -555,8 +555,8 @@ Int VG_(getgroups)( Int size, UInt* list - list[i] = (UInt)list16[i]; - return sr_Res(sres); - --# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \ -- || defined(VGP_arm_linux) \ -+# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGO_darwin) || defined(VGP_s390x_linux) \ - || defined(VGP_mips32_linux) || defined(VGP_arm64_linux) - SysRes sres; -@@ -741,7 +741,7 @@ void VG_(invalidate_icache) ( void *ptr, - // If I-caches are coherent, nothing needs to be done here - if (vai.hwcache_info.icaches_maintain_coherence) return; - --# if defined(VGA_ppc32) || defined(VGA_ppc64) -+# if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) - Addr startaddr = (Addr) ptr; - Addr endaddr = startaddr + nbytes; - Addr cls; -Index: coregrind/m_cache.c -=================================================================== ---- coregrind/m_cache.c.orig -+++ coregrind/m_cache.c -@@ -538,7 +538,8 @@ get_cache_info(VexArchInfo *vai) - return ret == 0 ? True : False; - } - --#elif defined(VGA_arm) || defined(VGA_ppc32) || defined(VGA_ppc64) || \ -+#elif defined(VGA_arm) || defined(VGA_ppc32) || \ -+ defined(VGA_ppc64be) || defined(VGA_ppc64le) || \ - defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) - - static Bool -Index: coregrind/m_redir.c -=================================================================== ---- coregrind/m_redir.c.orig -+++ coregrind/m_redir.c -@@ -1278,7 +1278,7 @@ void VG_(redir_initialise) ( void ) - ); - } - --# elif defined(VGP_ppc64_linux) -+# elif defined(VGP_ppc64be_linux) - /* If we're using memcheck, use these intercepts right from - the start, otherwise ld.so makes a lot of noise. */ - if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { -Index: coregrind/pub_core_aspacemgr.h -=================================================================== ---- coregrind/pub_core_aspacemgr.h.orig -+++ coregrind/pub_core_aspacemgr.h -@@ -344,7 +344,8 @@ extern Bool VG_(am_relocate_nooverlap_cl - // stacks. The address space manager provides and suitably - // protects such stacks. - --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \ -+#if defined(VGP_ppc32_linux) \ -+ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \ - || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \ - || defined(VGP_arm64_linux) - # define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages -Index: coregrind/pub_core_machine.h -=================================================================== ---- coregrind/pub_core_machine.h.orig -+++ coregrind/pub_core_machine.h -@@ -56,7 +56,7 @@ - # define VG_ELF_MACHINE EM_PPC - # define VG_ELF_CLASS ELFCLASS32 - # undef VG_PLAT_USES_PPCTOC --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) - # define VG_ELF_DATA2XXX ELFDATA2MSB - # define VG_ELF_MACHINE EM_PPC64 - # define VG_ELF_CLASS ELFCLASS64 -@@ -119,7 +119,7 @@ - # define VG_INSTR_PTR guest_CIA - # define VG_STACK_PTR guest_GPR1 - # define VG_FRAME_PTR guest_GPR1 // No frame ptr for PPC --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - # define VG_INSTR_PTR guest_CIA - # define VG_STACK_PTR guest_GPR1 - # define VG_FRAME_PTR guest_GPR1 // No frame ptr for PPC -@@ -233,7 +233,7 @@ extern Bool VG_(machine_get_cache_info)( - extern void VG_(machine_ppc32_set_clszB)( Int ); - #endif - --#if defined(VGA_ppc64) -+#if defined(VGA_ppc64be) || defined(VGA_ppc64le) - extern void VG_(machine_ppc64_set_clszB)( Int ); - #endif - -@@ -265,7 +265,7 @@ extern UInt VG_(machine_ppc32_has_VMX); - /* PPC64: set to 1 if Altivec instructions are supported in - user-space, else 0. Is referenced from assembly code, so do not - change from a 64-bit int. */ --#if defined(VGA_ppc64) -+#if defined(VGA_ppc64be) || defined(VGA_ppc64le) - extern ULong VG_(machine_ppc64_has_VMX); - #endif - -Index: Makefile.all.am -=================================================================== ---- Makefile.all.am.orig -+++ Makefile.all.am -@@ -212,15 +212,16 @@ if VGCONF_PLATVARIANT_IS_ANDROID - PRELOAD_LDFLAGS_COMMON_LINUX += -nostdlib - endif - --PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ --PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ --PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ --PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ --PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ --PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ --PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386 --PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64 --PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ --PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ --PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ -+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ -+PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ -+PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386 -+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64 -+PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ -+PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@ -+PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@ - -Index: tests/arch_test.c -=================================================================== ---- tests/arch_test.c.orig -+++ tests/arch_test.c -@@ -48,7 +48,7 @@ static Bool go(char* arch) - #elif defined(VGP_ppc32_linux) - if ( 0 == strcmp( arch, "ppc32" ) ) return True; - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) - if ( 0 == strcmp( arch, "ppc64" ) ) return True; - #if defined(VGA_SEC_ppc32) - if ( 0 == strcmp( arch, "ppc32" ) ) return True; -Index: include/valgrind.h -=================================================================== ---- include/valgrind.h.orig -+++ include/valgrind.h -@@ -115,7 +115,7 @@ - #undef PLAT_x86_linux - #undef PLAT_amd64_linux - #undef PLAT_ppc32_linux --#undef PLAT_ppc64_linux -+#undef PLAT_ppc64be_linux - #undef PLAT_arm_linux - #undef PLAT_arm64_linux - #undef PLAT_s390x_linux -@@ -138,8 +138,9 @@ - # define PLAT_amd64_linux 1 - #elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__) - # define PLAT_ppc32_linux 1 --#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) --# define PLAT_ppc64_linux 1 -+#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF != 2 -+/* Big Endian uses ELF version 1 */ -+# define PLAT_ppc64be_linux 1 - #elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__) - # define PLAT_arm_linux 1 - #elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__) -@@ -510,7 +511,7 @@ typedef - - /* ------------------------ ppc64-linux ------------------------ */ - --#if defined(PLAT_ppc64_linux) -+#if defined(PLAT_ppc64be_linux) - - typedef - struct { -@@ -585,7 +586,8 @@ typedef - ); \ - } while (0) - --#endif /* PLAT_ppc64_linux */ -+#endif /* PLAT_ppc64be_linux */ -+ - - /* ------------------------- arm-linux ------------------------- */ - -@@ -2525,7 +2527,7 @@ typedef - - /* ------------------------ ppc64-linux ------------------------ */ - --#if defined(PLAT_ppc64_linux) -+#if defined(PLAT_ppc64be_linux) - - /* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */ - -@@ -3078,7 +3080,7 @@ typedef - lval = (__typeof__(lval)) _res; \ - } while (0) - --#endif /* PLAT_ppc64_linux */ -+#endif /* PLAT_ppc64be_linux */ - - /* ------------------------- arm-linux ------------------------- */ - -@@ -5627,7 +5629,7 @@ VALGRIND_PRINTF_BACKTRACE(const char *fo - #undef PLAT_x86_linux - #undef PLAT_amd64_linux - #undef PLAT_ppc32_linux --#undef PLAT_ppc64_linux -+#undef PLAT_ppc64be_linux - #undef PLAT_arm_linux - #undef PLAT_s390x_linux - #undef PLAT_mips32_linux -Index: include/pub_tool_vkiscnums_asm.h -=================================================================== ---- include/pub_tool_vkiscnums_asm.h.orig -+++ include/pub_tool_vkiscnums_asm.h -@@ -42,7 +42,7 @@ - #elif defined(VGP_ppc32_linux) - # include "vki/vki-scnums-ppc32-linux.h" - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - # include "vki/vki-scnums-ppc64-linux.h" - - #elif defined(VGP_s390x_linux) -Index: include/pub_tool_libcsetjmp.h -=================================================================== ---- include/pub_tool_libcsetjmp.h.orig -+++ include/pub_tool_libcsetjmp.h -@@ -82,7 +82,7 @@ __attribute__((noreturn)) - void VG_MINIMAL_LONGJMP(VG_MINIMAL_JMP_BUF(_env)); - - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - - #define VG_MINIMAL_JMP_BUF(_name) ULong _name [32+1+1] - __attribute__((returns_twice)) -Index: include/vki/vki-linux.h -=================================================================== ---- include/vki/vki-linux.h.orig -+++ include/vki/vki-linux.h -@@ -85,7 +85,7 @@ - # include "vki-posixtypes-amd64-linux.h" - #elif defined(VGA_ppc32) - # include "vki-posixtypes-ppc32-linux.h" --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - # include "vki-posixtypes-ppc64-linux.h" - #elif defined(VGA_arm) - # include "vki-posixtypes-arm-linux.h" -@@ -211,7 +211,7 @@ typedef unsigned int vki_uint; - # include "vki-amd64-linux.h" - #elif defined(VGA_ppc32) - # include "vki-ppc32-linux.h" --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - # include "vki-ppc64-linux.h" - #elif defined(VGA_arm) - # include "vki-arm-linux.h" -Index: include/pub_tool_basics.h -=================================================================== ---- include/pub_tool_basics.h.orig -+++ include/pub_tool_basics.h -@@ -270,9 +270,9 @@ static inline Bool sr_EQ ( SysRes sr1, S - - #if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \ - || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEL)) \ -- || defined(VGA_arm64) -+ || defined(VGA_arm64) || defined(VGA_ppc64le) - # define VG_LITTLEENDIAN 1 --#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \ -+#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_s390x) \ - || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEB)) - # define VG_BIGENDIAN 1 - #else -@@ -283,7 +283,8 @@ static inline Bool sr_EQ ( SysRes sr1, S - #if defined(VGA_x86) - # define VG_REGPARM(n) __attribute__((regparm(n))) - #elif defined(VGA_amd64) || defined(VGA_ppc32) \ -- || defined(VGA_ppc64) || defined(VGA_arm) || defined(VGA_s390x) \ -+ || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ -+ || defined(VGA_arm) || defined(VGA_s390x) \ - || defined(VGA_mips32) || defined(VGA_mips64) \ - || defined(VGA_arm64) - # define VG_REGPARM(n) /* */ -Index: include/pub_tool_machine.h -=================================================================== ---- include/pub_tool_machine.h.orig -+++ include/pub_tool_machine.h -@@ -53,7 +53,7 @@ - # define VG_CLREQ_SZB 20 - # define VG_STACK_REDZONE_SZB 0 - --#elif defined(VGP_ppc64_linux) -+#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) - # define VG_MIN_INSTR_SZB 4 - # define VG_MAX_INSTR_SZB 4 - # define VG_CLREQ_SZB 20 -Index: configure.ac -=================================================================== ---- configure.ac.orig -+++ configure.ac -@@ -163,6 +163,18 @@ AC_MSG_CHECKING([for a supported CPU]) - # is a 64-bit capable PowerPC, then it must be set to ppc64 and not ppc32. - # Ditto for amd64. It is used for more configuration below, but is not used - # outside this file. -+# -+# Power PC returns powerpc for Big Endian. This was not changed when Little -+# Endian support was added to the 64-bit architecture. The 64-bit Little -+# Endian systems explicitly state le in the host_cpu. For clarity in the -+# Valgrind code, the ARCH_MAX name will state LE or BE for the endianess of -+# the 64-bit system. Big Endian is the only mode supported on 32-bit Power PC. -+# The abreviation PPC or ppc refers to 32-bit and 64-bit systems with either -+# Endianess. The name PPC64 or ppc64 to 64-bit systems of either Endianess. -+# The names ppc64be or PPC64BE refer to only 64-bit systems that are Big -+# Endian. Similarly, ppc64le or PPC64LE refer to only 64-bit systems that are -+# Little Endian. -+ - case "${host_cpu}" in - i?86) - AC_MSG_RESULT([ok (${host_cpu})]) -@@ -175,8 +187,15 @@ case "${host_cpu}" in - ;; - - powerpc64) -+ # this only referrs to 64-bit Big Endian - AC_MSG_RESULT([ok (${host_cpu})]) -- ARCH_MAX="ppc64" -+ ARCH_MAX="ppc64be" -+ ;; -+ -+ powerpc64le) -+ # this only referrs to 64-bit Little Endian -+ AC_MSG_RESULT([ok (${host_cpu})]) -+ ARCH_MAX="ppc64le" - ;; - - powerpc) -@@ -371,7 +390,7 @@ esac - # does not support building 32 bit programs - - case "$ARCH_MAX-$VGCONF_OS" in -- amd64-linux|ppc64-linux) -+ amd64-linux|ppc64be-linux) - AC_MSG_CHECKING([for 32 bit build support]) - safe_CFLAGS=$CFLAGS - CFLAGS="-m32" -@@ -489,13 +508,13 @@ case "$ARCH_MAX-$VGCONF_OS" in - valt_load_address_sec_inner="0xUNSET" - AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) - ;; -- ppc64-linux) -+ ppc64be-linux) - valt_load_address_sec_norml="0xUNSET" - valt_load_address_sec_inner="0xUNSET" - if test x$vg_cv_only64bit = xyes; then -- VGCONF_ARCH_PRI="ppc64" -+ VGCONF_ARCH_PRI="ppc64be" - VGCONF_ARCH_SEC="" -- VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX" -+ VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX" - VGCONF_PLATFORM_SEC_CAPS="" - valt_load_address_pri_norml="0x38000000" - valt_load_address_pri_inner="0x28000000" -@@ -507,9 +526,9 @@ case "$ARCH_MAX-$VGCONF_OS" in - valt_load_address_pri_norml="0x38000000" - valt_load_address_pri_inner="0x28000000" - else -- VGCONF_ARCH_PRI="ppc64" -+ VGCONF_ARCH_PRI="ppc64be" - VGCONF_ARCH_SEC="ppc32" -- VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX" -+ VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX" - VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX" - valt_load_address_pri_norml="0x38000000" - valt_load_address_pri_inner="0x28000000" -@@ -518,6 +537,18 @@ case "$ARCH_MAX-$VGCONF_OS" in - fi - AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) - ;; -+ ppc64le-linux) -+ # Little Endian is only supported on PPC64 -+ valt_load_address_sec_norml="0xUNSET" -+ valt_load_address_sec_inner="0xUNSET" -+ VGCONF_ARCH_PRI="ppc64le" -+ VGCONF_ARCH_SEC="" -+ VGCONF_PLATFORM_PRI_CAPS="PPC64LE_LINUX" -+ VGCONF_PLATFORM_SEC_CAPS="" -+ valt_load_address_pri_norml="0x38000000" -+ valt_load_address_pri_inner="0x28000000" -+ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})]) -+ ;; - # Darwin gets identified as 32-bit even when it supports 64-bit. - # (Not sure why, possibly because 'uname' returns "i386"?) Just about - # all Macs support both 32-bit and 64-bit, so we just build both. If -@@ -656,7 +687,8 @@ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC3 - test x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xPPC32_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC64, -- test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX ) -+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX \ -+ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX ) - AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM, - test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX ) -@@ -679,8 +711,10 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xPPC32_LINUX) --AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX, -- test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX) -+AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64BE_LINUX, -+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX) -+AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64LE_LINUX, -+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX) - AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ - -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX) -@@ -707,7 +741,8 @@ AM_CONDITIONAL(VGCONF_OS_IS_LINUX, - test x$VGCONF_PLATFORM_PRI_CAPS = xX86_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \ -- -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \ -+ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX \ -+ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \ - -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \ -Index: memcheck/tests/unit_libcbase.c -=================================================================== ---- memcheck/tests/unit_libcbase.c.orig -+++ memcheck/tests/unit_libcbase.c -@@ -56,7 +56,8 @@ void test_VG_STREQN(void) - } - - // On PPC/Linux VKI_PAGE_SIZE is a variable, not a macro. --#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \ -+ || defined(VGP_ppc64le_linux) - unsigned long VKI_PAGE_SIZE = 1UL << 12; - #endif - -Index: memcheck/tests/atomic_incs.c -=================================================================== ---- memcheck/tests/atomic_incs.c.orig -+++ memcheck/tests/atomic_incs.c -@@ -62,7 +62,7 @@ __attribute__((noinline)) void atomic_ad - : /*trash*/ "memory", "cc", "r15" - ); - } while (success != 1); --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) - /* Nasty hack. Does correctly atomically do *p += n, but only if p - is 8-aligned -- guaranteed by caller. */ - unsigned long success; -@@ -243,7 +243,7 @@ __attribute__((noinline)) void atomic_ad - : /*trash*/ "memory", "cc", "r15" - ); - } while (success != 1); --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) - /* Nasty hack. Does correctly atomically do *p += n, but only if p - is 8-aligned -- guaranteed by caller. */ - unsigned long success; -@@ -421,7 +421,7 @@ __attribute__((noinline)) void atomic_ad - : /*trash*/ "memory", "cc", "r15" - ); - } while (success != 1); --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) - /* Nasty hack. Does correctly atomically do *p += n, but only if p - is 8-aligned -- guaranteed by caller. */ - unsigned long success; -@@ -520,7 +520,7 @@ __attribute__((noinline)) void atomic_ad - "lock; addq %%rbx,(%%rax)" "\n" - : : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx" - ); --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) - unsigned long success; - do { - __asm__ __volatile__( -Index: memcheck/mc_machine.c -=================================================================== ---- memcheck/mc_machine.c.orig -+++ memcheck/mc_machine.c -@@ -61,7 +61,7 @@ - # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC32State) - #endif - --#if defined(VGA_ppc64) -+#if defined(VGA_ppc64be) || defined(VGA_ppc64le) - # include "libvex_guest_ppc64.h" - # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC64State) - #endif -@@ -150,7 +150,7 @@ static Int get_otrack_shadow_offset_wrk - { - /* -------------------- ppc64 -------------------- */ - --# if defined(VGA_ppc64) -+# if defined(VGA_ppc64be) || defined(VGA_ppc64le) - - # define GOF(_fieldname) \ - (offsetof(VexGuestPPC64State,guest_##_fieldname)) -@@ -160,7 +160,6 @@ static Int get_otrack_shadow_offset_wrk - Int sz = szB; - Int o = offset; - tl_assert(sz > 0); -- tl_assert(host_is_big_endian()); - - if (sz == 8 || sz == 4) { - /* The point of this is to achieve -@@ -1201,7 +1200,7 @@ static Int get_otrack_shadow_offset_wrk - IRType MC_(get_otrack_reg_array_equiv_int_type) ( IRRegArray* arr ) - { - /* -------------------- ppc64 -------------------- */ --# if defined(VGA_ppc64) -+# if defined(VGA_ppc64be) || defined(VGA_ppc64le) - /* The redir stack. */ - if (arr->base == offsetof(VexGuestPPC64State,guest_REDIR_STACK[0]) - && arr->elemTy == Ity_I64 -Index: cachegrind/cg_branchpred.c -=================================================================== ---- cachegrind/cg_branchpred.c.orig -+++ cachegrind/cg_branchpred.c -@@ -44,7 +44,7 @@ - - /* How many bits at the bottom of an instruction address are - guaranteed to be zero? */ --#if defined(VGA_ppc32) || defined(VGA_ppc64) \ -+#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \ - || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) - # define N_IADDR_LO_ZERO_BITS 2 - #elif defined(VGA_x86) || defined(VGA_amd64) -Index: cachegrind/cg_arch.c -=================================================================== ---- cachegrind/cg_arch.c.orig -+++ cachegrind/cg_arch.c -@@ -353,7 +353,7 @@ configure_caches(cache_t *I1c, cache_t * - *D1c = (cache_t) { 65536, 2, 64 }; - *LLc = (cache_t) { 262144, 8, 64 }; - --#elif defined(VGA_ppc64) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - - // Default cache configuration - *I1c = (cache_t) { 65536, 2, 64 }; diff --git a/r14239.diff b/r14239.diff deleted file mode 100644 index b0db2b9..0000000 --- a/r14239.diff +++ /dev/null @@ -1,4283 +0,0 @@ ------------------------------------------------------------------------- -r14239 | carll | 2014-08-08 01:35:54 +0200 (Fr, 08. Aug 2014) | 23 Zeilen - -This commit is for Bugzilla 334834. The Bugzilla contains patch 2 of 3 -to add PPC64 LE support. The other two patches can be found in Bugzillas -334384 and 334836. - -POWER PC, add the functional Little Endian support, patch 2 - -The IBM POWER processor now supports both Big Endian and Little Endian. -The ABI for Little Endian also changes. Specifically, the function -descriptor is not used, the stack size changed, accessing the TOC -changed. Functions now have a local and a global entry point. Register -r2 contains the TOC for local calls and register r12 contains the TOC -for global calls. This patch makes the functional changes to the -Valgrind tool. The patch makes the changes needed for the -none/tests/ppc32 and none/tests/ppc64 Makefile.am. A number of the -ppc specific tests have Endian dependencies that are not fixed in -this patch. They are fixed in the next patch. - -Per Julian's comments renamed coregrind/m_dispatch/dispatch-ppc64-linux.S -to coregrind/m_dispatch/dispatch-ppc64be-linux.S Created new file for LE -coregrind/m_dispatch/dispatch-ppc64le-linux.S. The same was done for -coregrind/m_syswrap/syscall-ppc-linux.S. - -Signed-off-by: Carl Love ------------------------------------------------------------------------- -Index: coregrind/Makefile.am -=================================================================== ---- coregrind/Makefile.am.orig -+++ coregrind/Makefile.am -@@ -313,7 +313,8 @@ COREGRIND_SOURCES_COMMON = \ - m_dispatch/dispatch-x86-linux.S \ - m_dispatch/dispatch-amd64-linux.S \ - m_dispatch/dispatch-ppc32-linux.S \ -- m_dispatch/dispatch-ppc64-linux.S \ -+ m_dispatch/dispatch-ppc64be-linux.S \ -+ m_dispatch/dispatch-ppc64le-linux.S \ - m_dispatch/dispatch-arm-linux.S \ - m_dispatch/dispatch-arm64-linux.S \ - m_dispatch/dispatch-s390x-linux.S \ -@@ -365,7 +366,8 @@ COREGRIND_SOURCES_COMMON = \ - m_syswrap/syscall-x86-linux.S \ - m_syswrap/syscall-amd64-linux.S \ - m_syswrap/syscall-ppc32-linux.S \ -- m_syswrap/syscall-ppc64-linux.S \ -+ m_syswrap/syscall-ppc64be-linux.S \ -+ m_syswrap/syscall-ppc64le-linux.S \ - m_syswrap/syscall-arm-linux.S \ - m_syswrap/syscall-arm64-linux.S \ - m_syswrap/syscall-s390x-linux.S \ -Index: coregrind/launcher-linux.c -=================================================================== ---- coregrind/launcher-linux.c.orig -+++ coregrind/launcher-linux.c -@@ -228,6 +228,10 @@ static const char *select_platform(const - (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || - ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { - platform = "arm64-linux"; -+ } else if (ehdr->e_machine == EM_PPC64 && -+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV || -+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) { -+ platform = "ppc64le-linux"; - } - } else if (header[EI_DATA] == ELFDATA2MSB) { - # if !defined(VGPV_arm_linux_android) \ -@@ -321,6 +325,7 @@ int main(int argc, char** argv, char** e - (0==strcmp(VG_PLATFORM,"amd64-linux")) || - (0==strcmp(VG_PLATFORM,"ppc32-linux")) || - (0==strcmp(VG_PLATFORM,"ppc64be-linux")) || -+ (0==strcmp(VG_PLATFORM,"ppc64le-linux")) || - (0==strcmp(VG_PLATFORM,"arm-linux")) || - (0==strcmp(VG_PLATFORM,"arm64-linux")) || - (0==strcmp(VG_PLATFORM,"s390x-linux")) || -Index: coregrind/m_translate.c -=================================================================== ---- coregrind/m_translate.c.orig -+++ coregrind/m_translate.c -@@ -1118,6 +1118,10 @@ static IRTemp gen_POP ( IRSB* bb ) - return res; - } - -+#endif -+ -+#if defined(VG_PLAT_USES_PPCTOC) -+ - /* Generate code to push LR and R2 onto this thread's redir stack, - then set R2 to the new value (which is the TOC pointer to be used - for the duration of the replacement function, as determined by -@@ -1140,6 +1144,9 @@ static void gen_push_and_set_LR_R2 ( IRS - # error Platform is not TOC-afflicted, fortunately - # endif - } -+#endif -+ -+#if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - - static void gen_pop_R2_LR_then_bLR ( IRSB* bb ) - { -@@ -1166,6 +1173,9 @@ static void gen_pop_R2_LR_then_bLR ( IRS - # error Platform is not TOC-afflicted, fortunately - # endif - } -+#endif -+ -+#if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - - static - Bool mk_preamble__ppctoc_magic_return_stub ( void* closureV, IRSB* bb ) -@@ -1187,6 +1197,30 @@ Bool mk_preamble__ppctoc_magic_return_st - } - #endif - -+#if defined(VGP_ppc64le_linux) -+/* Generate code to push LR and R2 onto this thread's redir stack. -+ Need to save R2 in case we redirect to a global entry point. The -+ value of R2 is not preserved when entering the global entry point. -+ Need to make sure R2 gets restored on return. Set LR to the magic -+ return stub, so we get to intercept the return and restore R2 and -+ L2 to the values saved here. -+ -+ The existing infrastruture for the TOC enabled architectures is -+ being exploited here. So, we need to enable a number of the -+ code sections used by VG_PLAT_USES_PPCTOC. -+*/ -+ -+static void gen_push_R2_and_set_LR ( IRSB* bb ) -+{ -+ Addr64 bogus_RA = (Addr64)&VG_(ppctoc_magic_redirect_return_stub); -+ Int offB_GPR2 = offsetof(VexGuestPPC64State,guest_GPR2); -+ Int offB_LR = offsetof(VexGuestPPC64State,guest_LR); -+ gen_PUSH( bb, IRExpr_Get(offB_LR, Ity_I64) ); -+ gen_PUSH( bb, IRExpr_Get(offB_GPR2, Ity_I64) ); -+ addStmtToIRSB( bb, IRStmt_Put( offB_LR, mkU64( bogus_RA )) ); -+} -+# endif -+ - /* --------------- END helpers for with-TOC platforms --------------- */ - - -@@ -1244,6 +1278,19 @@ Bool mk_preamble__set_NRADDR_to_zero ( v - gen_push_and_set_LR_R2 ( bb, VG_(get_tocptr)( closure->readdr ) ); - } - # endif -+ -+#if defined(VGP_ppc64le_linux) -+ VgCallbackClosure* closure = (VgCallbackClosure*)closureV; -+ Int offB_GPR12 = offsetof(VexGuestArchState, guest_GPR12); -+ addStmtToIRSB(bb, IRStmt_Put(offB_GPR12, mkU64(closure->readdr))); -+ addStmtToIRSB(bb, -+ IRStmt_Put( -+ offsetof(VexGuestArchState,guest_NRADDR_GPR2), -+ VG_WORDSIZE==8 ? mkU64(0) : mkU32(0) -+ ) -+ ); -+ gen_push_R2_and_set_LR ( bb ); -+#endif - return False; - } - -@@ -1277,7 +1324,7 @@ Bool mk_preamble__set_NRADDR_to_nraddr ( - Int offB_GPR25 = offsetof(VexGuestMIPS64State, guest_r25); - addStmtToIRSB(bb, IRStmt_Put(offB_GPR25, mkU64(closure->readdr))); - # endif --# if defined(VGP_ppc64be_linux) -+# if defined(VG_PLAT_USES_PPCTOC) && !defined(VGP_ppc64le_linux) - addStmtToIRSB( - bb, - IRStmt_Put( -@@ -1288,6 +1335,22 @@ Bool mk_preamble__set_NRADDR_to_nraddr ( - ); - gen_push_and_set_LR_R2 ( bb, VG_(get_tocptr)( closure->readdr ) ); - # endif -+#if defined(VGP_ppc64le_linux) -+ /* This saves the r2 before leaving the function. We need to move -+ * guest_NRADDR_GPR2 back to R2 on return. -+ */ -+ Int offB_GPR12 = offsetof(VexGuestArchState, guest_GPR12); -+ addStmtToIRSB( -+ bb, -+ IRStmt_Put( -+ offsetof(VexGuestArchState,guest_NRADDR_GPR2), -+ IRExpr_Get(offsetof(VexGuestArchState,guest_GPR2), -+ VG_WORDSIZE==8 ? Ity_I64 : Ity_I32) -+ ) -+ ); -+ addStmtToIRSB(bb, IRStmt_Put(offB_GPR12, mkU64(closure->readdr))); -+ gen_push_R2_and_set_LR ( bb ); -+#endif - return False; - } - -@@ -1475,7 +1538,8 @@ Bool VG_(translate) ( ThreadId tid, - if (kind == T_Redir_Wrap) - preamble_fn = mk_preamble__set_NRADDR_to_nraddr; - --# if defined(VG_PLAT_USES_PPCTOC) -+ /* LE we setup the LR */ -+# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux) - if (ULong_to_Ptr(nraddr) - == (void*)&VG_(ppctoc_magic_redirect_return_stub)) { - /* If entering the special return stub, this means a wrapped or -@@ -1518,6 +1582,11 @@ Bool VG_(translate) ( ThreadId tid, - vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True; - vex_abiinfo.host_ppc_calls_use_fndescrs = True; - # endif -+# if defined(VGP_ppc64le_linux) -+ vex_abiinfo.guest_ppc_zap_RZ_at_blr = True; -+ vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True; -+ vex_abiinfo.host_ppc_calls_use_fndescrs = False; -+# endif - - /* Set up closure args. */ - closure.tid = tid; -Index: coregrind/launcher-darwin.c -=================================================================== ---- coregrind/launcher-darwin.c.orig -+++ coregrind/launcher-darwin.c -@@ -64,6 +64,7 @@ static struct { - { CPU_TYPE_ARM, "arm", "arm" }, - { CPU_TYPE_POWERPC, "ppc", "ppc32" }, - { CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" }, -+ { CPU_TYPE_POWERPC64LE, "ppc64le", "ppc64le" }, - }; - static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]); - -Index: coregrind/m_sigframe/sigframe-ppc64-linux.c -=================================================================== ---- coregrind/m_sigframe/sigframe-ppc64-linux.c.orig -+++ coregrind/m_sigframe/sigframe-ppc64-linux.c -@@ -252,7 +252,11 @@ void VG_(sigframe_create)( ThreadId tid, - # undef DO - - frame->uc.uc_mcontext.gp_regs[VKI_PT_NIP] = tst->arch.vex.guest_CIA; -- frame->uc.uc_mcontext.gp_regs[VKI_PT_MSR] = 0xf032; /* pretty arbitrary */ -+#ifdef VGP_ppc64le_linux -+ frame->uc.uc_mcontext.gp_regs[VKI_PT_MSR] = 0xf033; /* pretty arbitrary */ -+#else -+ frame->uc.uc_mcontext.gp_regs[VKI_PT_MSR] = 0xf032; /* pretty arbitrary */ -+#endif - frame->uc.uc_mcontext.gp_regs[VKI_PT_ORIG_R3] = tst->arch.vex.guest_GPR3; - frame->uc.uc_mcontext.gp_regs[VKI_PT_CTR] = tst->arch.vex.guest_CTR; - frame->uc.uc_mcontext.gp_regs[VKI_PT_LNK] = tst->arch.vex.guest_LR; -@@ -302,9 +306,13 @@ void VG_(sigframe_create)( ThreadId tid, - - /* Handler is in fact a standard ppc64-linux function descriptor, - so extract the function entry point and also the toc ptr to use. */ -+#if defined(VGP_ppc64be_linux) - SET_SIGNAL_GPR(tid, 2, (Addr) ((ULong*)handler)[1]); - tst->arch.vex.guest_CIA = (Addr) ((ULong*)handler)[0]; -- -+#else -+ SET_SIGNAL_GPR(tid, 12, (Addr) handler); -+ tst->arch.vex.guest_CIA = (Addr) handler; -+#endif - priv = &frame->priv; - priv->magicPI = 0x31415927; - priv->sigNo_private = sigNo; -Index: coregrind/m_syswrap/syscall-ppc64-linux.S -=================================================================== ---- coregrind/m_syswrap/syscall-ppc64-linux.S -+++ /dev/null -@@ -1,172 +0,0 @@ -- --/*--------------------------------------------------------------------*/ --/*--- Support for doing system calls. syscall-ppc64-linux.S ---*/ --/*--------------------------------------------------------------------*/ -- --/* -- This file is part of Valgrind, a dynamic binary instrumentation -- framework. -- -- Copyright (C) 2005-2013 Paul Mackerras -- -- This program is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License as -- published by the Free Software Foundation; either version 2 of the -- License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -- 02111-1307, USA. -- -- The GNU General Public License is contained in the file COPYING. --*/ -- --#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) -- --#include "pub_core_basics_asm.h" --#include "pub_core_vkiscnums_asm.h" --#include "libvex_guest_offsets.h" -- -- --/*----------------------------------------------------------------*/ --/* -- Perform a syscall for the client. This will run a syscall -- with the client's specific per-thread signal mask. -- -- The structure of this function is such that, if the syscall is -- interrupted by a signal, we can determine exactly what -- execution state we were in with respect to the execution of -- the syscall by examining the value of NIP in the signal -- handler. This means that we can always do the appropriate -- thing to precisely emulate the kernel's signal/syscall -- interactions. -- -- The syscall number is taken from the argument, even though it -- should also be in regs->m_gpr[0]. The syscall result is written -- back to regs->m_gpr[3]/m_xer/m_result on completion. -- -- Returns 0 if the syscall was successfully called (even if the -- syscall itself failed), or a nonzero error code in the lowest -- 8 bits if one of the sigprocmasks failed (there's no way to -- determine which one failed). And there's no obvious way to -- recover from that either, but nevertheless we want to know. -- -- VG_(fixup_guest_state_after_syscall_interrupted) does the -- thread state fixup in the case where we were interrupted by a -- signal. -- -- Prototype: -- -- UWord ML_(do_syscall_for_client_WRK)( -- Int syscallno, // r3 -- void* guest_state, // r4 -- const vki_sigset_t *sysmask, // r5 -- const vki_sigset_t *postmask, // r6 -- Int sigsetSzB) // r7 --*/ --/* from vki_arch.h */ --#define VKI_SIG_SETMASK 2 -- --.align 2 --.globl ML_(do_syscall_for_client_WRK) --.section ".opd","aw" --.align 3 --ML_(do_syscall_for_client_WRK): --.quad .ML_(do_syscall_for_client_WRK),.TOC.@tocbase,0 --.previous --.type .ML_(do_syscall_for_client_WRK),@function --.globl .ML_(do_syscall_for_client_WRK) --.ML_(do_syscall_for_client_WRK): -- /* make a stack frame */ -- stdu 1,-80(1) -- std 31,72(1) -- std 30,64(1) -- std 29,56(1) -- std 28,48(1) -- mr 31,3 /* syscall number */ -- mr 30,4 /* guest_state */ -- mr 29,6 /* postmask */ -- mr 28,7 /* sigsetSzB */ -- -- /* set the signal mask for doing the system call */ -- /* set up for sigprocmask(SIG_SETMASK, sysmask, postmask) */ --1: li 0,__NR_rt_sigprocmask -- li 3,VKI_SIG_SETMASK -- mr 4,5 -- mr 5,6 -- mr 6,7 -- sc /* set the mask */ -- bso 7f /* if the sigprocmask fails */ -- -- /* load up syscall args from the threadstate */ -- ld 3,OFFSET_ppc64_GPR3(30) -- ld 4,OFFSET_ppc64_GPR4(30) -- ld 5,OFFSET_ppc64_GPR5(30) -- ld 6,OFFSET_ppc64_GPR6(30) -- ld 7,OFFSET_ppc64_GPR7(30) -- ld 8,OFFSET_ppc64_GPR8(30) -- mr 0,31 /* syscall number */ --2: sc /* do the syscall */ -- -- /* put the result back in the threadstate */ --3: std 3,OFFSET_ppc64_GPR3(30) /* gst->GPR3 = sc result */ -- /* copy cr0.so back to simulated state */ -- mfcr 5 /* r5 = CR */ -- rlwinm 5,5,4,31,31 /* r5 = (CR >> 28) & 1 */ -- stb 5,OFFSET_ppc64_CR0_0(30) /* gst->CR0.SO = cr0.so */ -- -- /* block signals again */ -- /* set up for sigprocmask(SIG_SETMASK, postmask, NULL) */ --4: li 0,__NR_rt_sigprocmask -- li 3,VKI_SIG_SETMASK -- mr 4,29 -- li 5,0 -- mr 6,28 -- sc /* set the mask */ -- bso 7f /* if the sigprocmask fails */ -- /* now safe from signals */ -- li 3,0 /* SUCCESS */ -- -- /* pop off stack frame */ --5: ld 28,48(1) -- ld 29,56(1) -- ld 30,64(1) -- ld 31,72(1) -- addi 1,1,80 -- blr -- -- /* failure: return 0x8000 | error code */ --7: ori 3,3,0x8000 /* FAILURE -- ensure return value is nonzero */ -- b 5b -- --.section .rodata --/* export the ranges so that -- VG_(fixup_guest_state_after_syscall_interrupted) can do the -- right thing */ -- --.globl ML_(blksys_setup) --.globl ML_(blksys_restart) --.globl ML_(blksys_complete) --.globl ML_(blksys_committed) --.globl ML_(blksys_finished) --ML_(blksys_setup): .quad 1b --ML_(blksys_restart): .quad 2b --ML_(blksys_complete): .quad 3b --ML_(blksys_committed): .quad 4b --ML_(blksys_finished): .quad 5b -- -- --/* Let the linker know we don't need an executable stack */ --.section .note.GNU-stack,"",@progbits -- --#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) -- --/*--------------------------------------------------------------------*/ --/*--- end ---*/ --/*--------------------------------------------------------------------*/ -Index: coregrind/m_syswrap/syscall-ppc64be-linux.S -=================================================================== ---- /dev/null -+++ coregrind/m_syswrap/syscall-ppc64be-linux.S -@@ -0,0 +1,172 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Support for doing system calls. syscall-ppc64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2005-2013 Paul Mackerras -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_ppc64be_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_vkiscnums_asm.h" -+#include "libvex_guest_offsets.h" -+ -+ -+/*----------------------------------------------------------------*/ -+/* -+ Perform a syscall for the client. This will run a syscall -+ with the client's specific per-thread signal mask. -+ -+ The structure of this function is such that, if the syscall is -+ interrupted by a signal, we can determine exactly what -+ execution state we were in with respect to the execution of -+ the syscall by examining the value of NIP in the signal -+ handler. This means that we can always do the appropriate -+ thing to precisely emulate the kernel's signal/syscall -+ interactions. -+ -+ The syscall number is taken from the argument, even though it -+ should also be in regs->m_gpr[0]. The syscall result is written -+ back to regs->m_gpr[3]/m_xer/m_result on completion. -+ -+ Returns 0 if the syscall was successfully called (even if the -+ syscall itself failed), or a nonzero error code in the lowest -+ 8 bits if one of the sigprocmasks failed (there's no way to -+ determine which one failed). And there's no obvious way to -+ recover from that either, but nevertheless we want to know. -+ -+ VG_(fixup_guest_state_after_syscall_interrupted) does the -+ thread state fixup in the case where we were interrupted by a -+ signal. -+ -+ Prototype: -+ -+ UWord ML_(do_syscall_for_client_WRK)( -+ Int syscallno, // r3 -+ void* guest_state, // r4 -+ const vki_sigset_t *sysmask, // r5 -+ const vki_sigset_t *postmask, // r6 -+ Int sigsetSzB) // r7 -+*/ -+/* from vki_arch.h */ -+#define VKI_SIG_SETMASK 2 -+ -+.align 2 -+.globl ML_(do_syscall_for_client_WRK) -+.section ".opd","aw" -+.align 3 -+ML_(do_syscall_for_client_WRK): -+.quad .ML_(do_syscall_for_client_WRK),.TOC.@tocbase,0 -+.previous -+.type .ML_(do_syscall_for_client_WRK),@function -+.globl .ML_(do_syscall_for_client_WRK) -+.ML_(do_syscall_for_client_WRK): -+ /* make a stack frame */ -+ stdu 1,-80(1) -+ std 31,72(1) -+ std 30,64(1) -+ std 29,56(1) -+ std 28,48(1) -+ mr 31,3 /* syscall number */ -+ mr 30,4 /* guest_state */ -+ mr 29,6 /* postmask */ -+ mr 28,7 /* sigsetSzB */ -+ -+ /* set the signal mask for doing the system call */ -+ /* set up for sigprocmask(SIG_SETMASK, sysmask, postmask) */ -+1: li 0,__NR_rt_sigprocmask -+ li 3,VKI_SIG_SETMASK -+ mr 4,5 -+ mr 5,6 -+ mr 6,7 -+ sc /* set the mask */ -+ bso 7f /* if the sigprocmask fails */ -+ -+ /* load up syscall args from the threadstate */ -+ ld 3,OFFSET_ppc64_GPR3(30) -+ ld 4,OFFSET_ppc64_GPR4(30) -+ ld 5,OFFSET_ppc64_GPR5(30) -+ ld 6,OFFSET_ppc64_GPR6(30) -+ ld 7,OFFSET_ppc64_GPR7(30) -+ ld 8,OFFSET_ppc64_GPR8(30) -+ mr 0,31 /* syscall number */ -+2: sc /* do the syscall */ -+ -+ /* put the result back in the threadstate */ -+3: std 3,OFFSET_ppc64_GPR3(30) /* gst->GPR3 = sc result */ -+ /* copy cr0.so back to simulated state */ -+ mfcr 5 /* r5 = CR */ -+ rlwinm 5,5,4,31,31 /* r5 = (CR >> 28) & 1 */ -+ stb 5,OFFSET_ppc64_CR0_0(30) /* gst->CR0.SO = cr0.so */ -+ -+ /* block signals again */ -+ /* set up for sigprocmask(SIG_SETMASK, postmask, NULL) */ -+4: li 0,__NR_rt_sigprocmask -+ li 3,VKI_SIG_SETMASK -+ mr 4,29 -+ li 5,0 -+ mr 6,28 -+ sc /* set the mask */ -+ bso 7f /* if the sigprocmask fails */ -+ /* now safe from signals */ -+ li 3,0 /* SUCCESS */ -+ -+ /* pop off stack frame */ -+5: ld 28,48(1) -+ ld 29,56(1) -+ ld 30,64(1) -+ ld 31,72(1) -+ addi 1,1,80 -+ blr -+ -+ /* failure: return 0x8000 | error code */ -+7: ori 3,3,0x8000 /* FAILURE -- ensure return value is nonzero */ -+ b 5b -+ -+.section .rodata -+/* export the ranges so that -+ VG_(fixup_guest_state_after_syscall_interrupted) can do the -+ right thing */ -+ -+.globl ML_(blksys_setup) -+.globl ML_(blksys_restart) -+.globl ML_(blksys_complete) -+.globl ML_(blksys_committed) -+.globl ML_(blksys_finished) -+ML_(blksys_setup): .quad 1b -+ML_(blksys_restart): .quad 2b -+ML_(blksys_complete): .quad 3b -+ML_(blksys_committed): .quad 4b -+ML_(blksys_finished): .quad 5b -+ -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",@progbits -+ -+#endif // defined(VGP_ppc64be_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_syswrap/syswrap-main.c -=================================================================== ---- coregrind/m_syswrap/syswrap-main.c.orig -+++ coregrind/m_syswrap/syswrap-main.c -@@ -2006,6 +2006,25 @@ void ML_(fixup_guest_state_to_restart_sy - vg_assert(p[0] == 0x44 && p[1] == 0x0 && p[2] == 0x0 && p[3] == 0x2); - } - -+#elif defined(VGP_ppc64le_linux) -+ arch->vex.guest_CIA -= 4; // sizeof(ppc32 instr) -+ -+ /* Make sure our caller is actually sane, and we're really backing -+ back over a syscall. -+ -+ sc == 44 00 00 02 -+ */ -+ { -+ UChar *p = (UChar *)arch->vex.guest_CIA; -+ -+ if (p[3] != 0x44 || p[2] != 0x0 || p[1] != 0x0 || p[0] != 0x02) -+ VG_(message)(Vg_DebugMsg, -+ "?! restarting over syscall at %#llx %02x %02x %02x %02x\n", -+ arch->vex.guest_CIA + 0ULL, p[3], p[2], p[1], p[0]); -+ -+ vg_assert(p[3] == 0x44 && p[2] == 0x0 && p[1] == 0x0 && p[0] == 0x2); -+ } -+ - #elif defined(VGP_arm_linux) - if (arch->vex.guest_R15T & 1) { - // Thumb mode. SVC is a encoded as -Index: coregrind/m_syswrap/syswrap-ppc64-linux.c -=================================================================== ---- coregrind/m_syswrap/syswrap-ppc64-linux.c.orig -+++ coregrind/m_syswrap/syswrap-ppc64-linux.c -@@ -78,6 +78,7 @@ void ML_(call_on_new_stack_0_1) ( Addr s - address, the second word is the TOC ptr (r2), and the third word is - the static chain value. */ - asm( -+#if defined(VGP_ppc64be_linux) - " .align 2\n" - " .globl vgModuleLocal_call_on_new_stack_0_1\n" - " .section \".opd\",\"aw\"\n" -@@ -126,6 +127,55 @@ asm( - " mtcr 0\n\t" // CAB: Need this? - " bctr\n\t" // jump to dst - " trap\n" // should never get here -+#else -+// ppc64le_linux -+" .align 2\n" -+" .globl vgModuleLocal_call_on_new_stack_0_1\n" -+"vgModuleLocal_call_on_new_stack_0_1:\n" -+" .type .vgModuleLocal_call_on_new_stack_0_1,@function\n" -+"#if _CALL_ELF == 2 \n" -+"0: addis 2,12,.TOC.-0b@ha\n" -+" addi 2,2,.TOC.-0b@l\n" -+"#endif\n" -+".localentry vgModuleLocal_call_on_new_stack_0_1, .-vgModuleLocal_call_on_new_stack_0_1\n" -+" mr %r1,%r3\n\t" // stack to %sp -+" mtlr %r4\n\t" // retaddr to %lr -+" mtctr %r5\n\t" // f_ptr to count reg -+" mr %r3,%r6\n\t" // arg1 to %r3 -+" li 0,0\n\t" // zero all GP regs -+" li 4,0\n\t" -+" li 5,0\n\t" -+" li 6,0\n\t" -+" li 7,0\n\t" -+" li 8,0\n\t" -+" li 9,0\n\t" -+" li 10,0\n\t" -+" li 11,0\n\t" -+" li 12,0\n\t" -+" li 13,0\n\t" -+" li 14,0\n\t" -+" li 15,0\n\t" -+" li 16,0\n\t" -+" li 17,0\n\t" -+" li 18,0\n\t" -+" li 19,0\n\t" -+" li 20,0\n\t" -+" li 21,0\n\t" -+" li 22,0\n\t" -+" li 23,0\n\t" -+" li 24,0\n\t" -+" li 25,0\n\t" -+" li 26,0\n\t" -+" li 27,0\n\t" -+" li 28,0\n\t" -+" li 29,0\n\t" -+" li 30,0\n\t" -+" li 31,0\n\t" -+" mtxer 0\n\t" // CAB: Need this? -+" mtcr 0\n\t" // CAB: Need this? -+" bctr\n\t" // jump to dst -+" trap\n" // should never get here -+#endif - ); - - -@@ -170,6 +220,7 @@ ULong do_syscall_clone_ppc64_linux ( Wor - Int* parent_tid, - void/*vki_modify_ldt_t*/ * ); - asm( -+#if defined(VGP_ppc64be_linux) - " .align 2\n" - " .globl do_syscall_clone_ppc64_linux\n" - " .section \".opd\",\"aw\"\n" -@@ -240,6 +291,78 @@ asm( - " ld 31,56(1)\n" - " addi 1,1,64\n" - " blr\n" -+#else -+" .align 2\n" -+" .globl do_syscall_clone_ppc64_linux\n" -+" .type do_syscall_clone_ppc64_linux,@function\n" -+"do_syscall_clone_ppc64_linux:\n" -+" .globl .do_syscall_clone_ppc64_linux\n" -+".do_syscall_clone_ppc64_linux:\n" -+"#if _CALL_ELF == 2 \n" -+"0: addis 2,12,.TOC.-0b@ha \n" -+" addi 2,2,.TOC.-0b@l \n" -+"#endif \n" -+" .localentry do_syscall_clone_ppc64_linux, .-do_syscall_clone_ppc64_linux \n" -+" stdu 1,-64(1)\n" -+" std 29,40(1)\n" -+" std 30,48(1)\n" -+" std 31,56(1)\n" -+" mr 30,3\n" // preserve fn -+" mr 31,6\n" // preserve arg -+ -+ // setup child stack -+" rldicr 4,4, 0,59\n" // trim sp to multiple of 16 bytes -+ // (r4 &= ~0xF) -+" li 0,0\n" -+" stdu 0,-32(4)\n" // make initial stack frame -+" mr 29,4\n" // preserve sp -+ -+ // setup syscall -+" li 0,"__NR_CLONE"\n" // syscall number -+" mr 3,5\n" // syscall arg1: flags -+ // r4 already setup // syscall arg2: child_stack -+" mr 5,8\n" // syscall arg3: parent_tid -+" mr 6,13\n" // syscall arg4: REAL THREAD tls -+" mr 7,7\n" // syscall arg5: child_tid -+" mr 8,8\n" // syscall arg6: ???? -+" mr 9,9\n" // syscall arg7: ???? -+ -+" sc\n" // clone() -+ -+" mfcr 4\n" // CR now in low half r4 -+" sldi 4,4,32\n" // CR now in hi half r4 -+ -+" sldi 3,3,32\n" -+" srdi 3,3,32\n" // zero out hi half r3 -+ -+" or 3,3,4\n" // r3 = CR : syscall-retval -+" cmpwi 3,0\n" // child if retval == 0 (note, cmpw) -+" bne 1f\n" // jump if !child -+ -+ /* CHILD - call thread function */ -+ /* Note: 2.4 kernel doesn't set the child stack pointer, -+ so we do it here. -+ That does leave a small window for a signal to be delivered -+ on the wrong stack, unfortunately. */ -+" mr 1,29\n" -+" mtctr 30\n" // ctr reg = fn -+" mr 3,31\n" // r3 = arg -+" bctrl\n" // call fn() -+ -+ // exit with result -+" li 0,"__NR_EXIT"\n" -+" sc\n" -+ -+ // Exit returned?! -+" .long 0\n" -+ -+ // PARENT or ERROR - return -+"1: ld 29,40(1)\n" -+" ld 30,48(1)\n" -+" ld 31,56(1)\n" -+" addi 1,1,64\n" -+" blr\n" -+#endif - ); - - #undef __NR_CLONE -Index: coregrind/m_syswrap/syscall-ppc64le-linux.S -=================================================================== ---- /dev/null -+++ coregrind/m_syswrap/syscall-ppc64le-linux.S -@@ -0,0 +1,189 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- Support for doing system calls. syscall-ppc64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2005-2013 Paul Mackerras -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_ppc64le_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_vkiscnums_asm.h" -+#include "libvex_guest_offsets.h" -+ -+ -+/*----------------------------------------------------------------*/ -+/* -+ Perform a syscall for the client. This will run a syscall -+ with the client's specific per-thread signal mask. -+ -+ The structure of this function is such that, if the syscall is -+ interrupted by a signal, we can determine exactly what -+ execution state we were in with respect to the execution of -+ the syscall by examining the value of NIP in the signal -+ handler. This means that we can always do the appropriate -+ thing to precisely emulate the kernel's signal/syscall -+ interactions. -+ -+ The syscall number is taken from the argument, even though it -+ should also be in regs->m_gpr[0]. The syscall result is written -+ back to regs->m_gpr[3]/m_xer/m_result on completion. -+ -+ Returns 0 if the syscall was successfully called (even if the -+ syscall itself failed), or a nonzero error code in the lowest -+ 8 bits if one of the sigprocmasks failed (there's no way to -+ determine which one failed). And there's no obvious way to -+ recover from that either, but nevertheless we want to know. -+ -+ VG_(fixup_guest_state_after_syscall_interrupted) does the -+ thread state fixup in the case where we were interrupted by a -+ signal. -+ -+ Prototype: -+ -+ UWord ML_(do_syscall_for_client_WRK)( -+ Int syscallno, // r3 -+ void* guest_state, // r4 -+ const vki_sigset_t *sysmask, // r5 -+ const vki_sigset_t *postmask, // r6 -+ Int sigsetSzB) // r7 -+*/ -+/* from vki_arch.h */ -+#define VKI_SIG_SETMASK 2 -+ -+.align 2 -+.globl ML_(do_syscall_for_client_WRK) -+#if _CALL_ELF == 2 -+.type .ML_(do_syscall_for_client_WRK),@function -+ML_(do_syscall_for_client_WRK): -+0: addis 2,12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry ML_(do_syscall_for_client_WRK), .-ML_(do_syscall_for_client_WRK) -+#else -+.section ".opd","aw" -+.align 3 -+ML_(do_syscall_for_client_WRK): -+.quad .ML_(do_syscall_for_client_WRK),.TOC.@tocbase,0 -+.previous -+#endif -+#if _CALL_ELF == 2 -+0: addis 2,12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry ML_(do_syscall_for_client_WRK), .-ML_(do_syscall_for_client_WRK) -+#endif -+.type .ML_(do_syscall_for_client_WRK),@function -+.globl .ML_(do_syscall_for_client_WRK) -+.ML_(do_syscall_for_client_WRK): -+ /* make a stack frame */ -+ stdu 1,-80(1) -+ std 31,72(1) -+ std 30,64(1) -+ std 29,56(1) -+ std 28,48(1) -+ mr 31,3 /* syscall number */ -+ mr 30,4 /* guest_state */ -+ mr 29,6 /* postmask */ -+ mr 28,7 /* sigsetSzB */ -+ -+ /* set the signal mask for doing the system call */ -+ /* set up for sigprocmask(SIG_SETMASK, sysmask, postmask) */ -+1: li 0,__NR_rt_sigprocmask -+ li 3,VKI_SIG_SETMASK -+ mr 4,5 -+ mr 5,6 -+ mr 6,7 -+ sc /* set the mask */ -+ bso 7f /* if the sigprocmask fails */ -+ -+ /* load up syscall args from the threadstate */ -+ ld 3,OFFSET_ppc64_GPR3(30) -+ ld 4,OFFSET_ppc64_GPR4(30) -+ ld 5,OFFSET_ppc64_GPR5(30) -+ ld 6,OFFSET_ppc64_GPR6(30) -+ ld 7,OFFSET_ppc64_GPR7(30) -+ ld 8,OFFSET_ppc64_GPR8(30) -+ mr 0,31 /* syscall number */ -+2: sc /* do the syscall */ -+ -+ /* put the result back in the threadstate */ -+3: std 3,OFFSET_ppc64_GPR3(30) /* gst->GPR3 = sc result */ -+ /* copy cr0.so back to simulated state */ -+ mfcr 5 /* r5 = CR */ -+ rlwinm 5,5,4,31,31 /* r5 = (CR >> 28) & 1 */ -+ stb 5,OFFSET_ppc64_CR0_0(30) /* gst->CR0.SO = cr0.so */ -+ -+ /* block signals again */ -+ /* set up for sigprocmask(SIG_SETMASK, postmask, NULL) */ -+4: li 0,__NR_rt_sigprocmask -+ li 3,VKI_SIG_SETMASK -+ mr 4,29 -+ li 5,0 -+ mr 6,28 -+ sc /* set the mask */ -+ bso 7f /* if the sigprocmask fails */ -+ /* now safe from signals */ -+ li 3,0 /* SUCCESS */ -+ -+ /* pop off stack frame */ -+5: ld 28,48(1) -+ ld 29,56(1) -+ ld 30,64(1) -+ ld 31,72(1) -+ addi 1,1,80 -+ blr -+ -+ /* failure: return 0x8000 | error code */ -+7: ori 3,3,0x8000 /* FAILURE -- ensure return value is nonzero */ -+ b 5b -+#if _CALL_ELF == 2 -+ .size .ML_(do_syscall_for_client_WRK),.-.ML_(do_syscall_for_client_WRK) -+#else -+ .size .ML_(do_syscall_for_client_WRK),.-.ML_(do_syscall_for_client_WRK) -+#endif -+.section .rodata -+/* export the ranges so that -+ VG_(fixup_guest_state_after_syscall_interrupted) can do the -+ right thing */ -+ -+.globl ML_(blksys_setup) -+.globl ML_(blksys_restart) -+.globl ML_(blksys_complete) -+.globl ML_(blksys_committed) -+.globl ML_(blksys_finished) -+ML_(blksys_setup): .quad 1b -+ML_(blksys_restart): .quad 2b -+ML_(blksys_complete): .quad 3b -+ML_(blksys_committed): .quad 4b -+ML_(blksys_finished): .quad 5b -+ -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",@progbits -+ -+#endif defined(VGP_ppc64le_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/pub_core_machine.h -=================================================================== ---- coregrind/pub_core_machine.h.orig -+++ coregrind/pub_core_machine.h -@@ -61,6 +61,11 @@ - # define VG_ELF_MACHINE EM_PPC64 - # define VG_ELF_CLASS ELFCLASS64 - # define VG_PLAT_USES_PPCTOC 1 -+#elif defined(VGP_ppc64le_linux) -+# define VG_ELF_DATA2XXX ELFDATA2LSB -+# define VG_ELF_MACHINE EM_PPC64 -+# define VG_ELF_CLASS ELFCLASS64 -+# undef VG_PLAT_USES_PPCTOC - #elif defined(VGP_arm_linux) - # define VG_ELF_DATA2XXX ELFDATA2LSB - # define VG_ELF_MACHINE EM_ARM -Index: coregrind/m_debuginfo/priv_storage.h -=================================================================== ---- coregrind/m_debuginfo/priv_storage.h.orig -+++ coregrind/m_debuginfo/priv_storage.h -@@ -70,7 +70,8 @@ - typedef - struct { - Addr addr; /* lowest address of entity */ -- Addr tocptr; /* ppc64-linux only: value that R2 should have */ -+ Addr tocptr; /* ppc64be-linux only: value that R2 should have */ -+ Addr local_ep; /* address for local entry point, ppc64le */ - HChar* pri_name; /* primary name, never NULL */ - HChar** sec_names; /* NULL, or a NULL term'd array of other names */ - // XXX: this could be shrunk (on 32-bit platforms) by using 30 -@@ -745,7 +746,7 @@ struct _DebugInfo { - Bool gotplt_present; - Addr gotplt_avma; - SizeT gotplt_size; -- /* .opd -- needed on ppc64-linux for finding symbols */ -+ /* .opd -- needed on ppc64be-linux for finding symbols */ - Bool opd_present; - Addr opd_avma; - SizeT opd_size; -Index: coregrind/m_debuginfo/readmacho.c -=================================================================== ---- coregrind/m_debuginfo/readmacho.c.orig -+++ coregrind/m_debuginfo/readmacho.c -@@ -199,6 +199,8 @@ static DiSlice map_image_aboard ( DebugI - Int cputype = CPU_TYPE_POWERPC; - # elif defined(VGA_ppc64be) - Int cputype = CPU_TYPE_POWERPC64BE; -+# elif defined(VGA_ppc64le) -+ Int cputype = CPU_TYPE_POWERPC64LE; - # elif defined(VGA_x86) - Int cputype = CPU_TYPE_X86; - # elif defined(VGA_amd64) -Index: coregrind/m_debuginfo/readelf.c -=================================================================== ---- coregrind/m_debuginfo/readelf.c.orig -+++ coregrind/m_debuginfo/readelf.c -@@ -240,7 +240,10 @@ Bool get_elf_symbol_info ( - Bool* from_opd_out, /* ppc64be-linux only: did we deref an - .opd entry? */ - Bool* is_text_out, /* is this a text symbol? */ -- Bool* is_ifunc /* is this a STT_GNU_IFUNC function ?*/ -+ Bool* is_ifunc, /* is this a STT_GNU_IFUNC function ?*/ -+ Addr* sym_local_ep /* addr for local entry point. PPC64 LE -+ supports a local and global entry points. -+ Use this value to return the entry point. */ - ) - { - Bool plausible; -@@ -258,6 +261,8 @@ Bool get_elf_symbol_info ( - *sym_tocptr_out = 0; /* unknown/inapplicable */ - *from_opd_out = False; - *is_ifunc = False; -+ *sym_local_ep = 0; /* unknown/inapplicable */ -+ - /* Get the symbol size, but restrict it to fit in a signed 32 bit - int. Also, deal with the stupid case of negative size by making - the size be 1. Note that sym->st_size has type UWord, -@@ -670,14 +675,57 @@ Bool get_elf_symbol_info ( - } - - # if defined(VGP_ppc64be_linux) -- /* It's crucial that we never add symbol addresses in the .opd -- section. This would completely mess up function redirection and -- intercepting. This assert ensures that any symbols that make it -- into the symbol table on ppc64-linux don't point into .opd. */ - if (di->opd_present && di->opd_size > 0) { - vg_assert(*sym_avma_out + *sym_size_out <= di->opd_avma - || *sym_avma_out >= di->opd_avma + di->opd_size); - } -+#endif -+ -+# if defined(VGP_ppc64le_linux) -+ /* PPC64 LE ABI uses three bits in the st_other field to indicate the number -+ * of instructions between the function's global and local entry points. An -+ * offset of 0 indicates that there is one entry point. The value must be: -+ * -+ * 0 - one entry point, local and global are the same -+ * 1 - reserved -+ * 2 - local entry point is one instruction after the global entry point -+ * 3 - local entry point is two instructions after the global entry point -+ * 4 - local entry point is four instructions after the global entry point -+ * 5 - local entry point is eight instructions after the global entry point -+ * 6 - local entry point is sixteen two instructions after the global entry point -+ * 7 - reserved -+ * -+ * The extract the three bit field from the other field. -+ * (other_field & STO_PPC64_LOCAL_MASK) >> STO_PPC_LOCAL_BIT -+ * -+ * where the #define values are given in include/elf/powerpc.h file for -+ * the PPC binutils. -+ * -+ * coversion of the three bit field to bytes is given by -+ * -+ * ((1 << bit_field) >> 2) << 2 -+ */ -+ -+ #define STO_PPC64_LOCAL_BIT 5 -+ #define STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT) -+ { -+ unsigned int bit_field, dist_to_local_entry; -+ /* extract the other filed */ -+ bit_field = (sym->st_other & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT; -+ -+ if ((bit_field > 0) && (bit_field < 7)) { -+ /* store the local entry point address */ -+ dist_to_local_entry = ((1 << bit_field) >> 2) << 2; -+ *sym_local_ep = *sym_avma_out + dist_to_local_entry; -+ -+ if (TRACE_SYMTAB_ENABLED) { -+ HChar* sym_name = ML_(img_strdup)(escn_strtab->img, -+ "di.gesi.5", sym_name_ioff); -+ VG_(printf)("Local entry point: %s at %#010x\n", -+ sym_name, (unsigned int)*sym_local_ep); -+ } -+ } -+ } - # endif - - /* Acquire! */ -@@ -686,7 +734,7 @@ Bool get_elf_symbol_info ( - - - /* Read an ELF symbol table (normal or dynamic). This one is for the -- "normal" case ({x86,amd64,ppc32,arm,mips32,mips64}-linux). */ -+ "normal" case ({x86,amd64,ppc32,arm,mips32,mips64, ppc64le}-linux). */ - static - __attribute__((unused)) /* not referred to on all targets */ - void read_elf_symtab__normal( -@@ -725,6 +773,7 @@ void read_elf_symtab__normal( - Addr sym_avma_really = 0; - Int sym_size = 0; - Addr sym_tocptr = 0; -+ Addr local_ep = 0; - Bool from_opd = False, is_text = False, is_ifunc = False; - DiOffT sym_name_really = DiOffT_INVALID; - if (get_elf_symbol_info(di, &sym, sym_name, escn_strtab, -@@ -734,7 +783,8 @@ void read_elf_symtab__normal( - &sym_avma_really, - &sym_size, - &sym_tocptr, -- &from_opd, &is_text, &is_ifunc)) { -+ &from_opd, &is_text, &is_ifunc, -+ &local_ep)) { - - DiSym disym; - VG_(memset)(&disym, 0, sizeof(disym)); -@@ -742,6 +792,7 @@ void read_elf_symtab__normal( - "di.res__n.1", sym_name_really); - disym.addr = sym_avma_really; - disym.tocptr = sym_tocptr; -+ disym.local_ep = local_ep; - disym.pri_name = ML_(addStr) ( di, cstr, -1 ); - disym.sec_names = NULL; - disym.size = sym_size; -@@ -749,7 +800,7 @@ void read_elf_symtab__normal( - disym.isIFunc = is_ifunc; - if (cstr) { ML_(dinfo_free)(cstr); cstr = NULL; } - vg_assert(disym.pri_name); -- vg_assert(disym.tocptr == 0); /* has no role except on ppc64-linux */ -+ vg_assert(disym.tocptr == 0); /* has no role except on ppc64be-linux */ - ML_(addSym) ( di, &disym ); - - if (TRACE_SYMTAB_ENABLED) { -@@ -761,6 +812,10 @@ void read_elf_symtab__normal( - (Int)disym.size, - (HChar*)disym.pri_name - ); -+ if (local_ep != 0) { -+ TRACE_SYMTAB(" local entry point %#010lx\n", -+ local_ep) -+ } - } - - } -@@ -856,6 +911,7 @@ void read_elf_symtab__ppc64be_linux( - Addr sym_avma_really = 0; - Int sym_size = 0; - Addr sym_tocptr = 0; -+ Addr sym_local_ep = 0; - Bool from_opd = False, is_text = False, is_ifunc = False; - DiOffT sym_name_really = DiOffT_INVALID; - DiSym disym; -@@ -867,7 +923,8 @@ void read_elf_symtab__ppc64be_linux( - &sym_avma_really, - &sym_size, - &sym_tocptr, -- &from_opd, &is_text, &is_ifunc)) { -+ &from_opd, &is_text, &is_ifunc, -+ &sym_local_ep)) { - - /* Check if we've seen this (name,addr) key before. */ - key.addr = sym_avma_really; -@@ -2774,6 +2831,7 @@ Bool ML_(read_elf_debug_info) ( struct _ - # if !defined(VGP_amd64_linux) \ - && !defined(VGP_s390x_linux) \ - && !defined(VGP_ppc64be_linux) \ -+ && !defined(VGP_ppc64le_linux) \ - && !defined(VGPV_arm_linux_android) \ - && !defined(VGPV_x86_linux_android) \ - && !defined(VGP_mips64_linux) -Index: coregrind/m_debuginfo/debuginfo.c -=================================================================== ---- coregrind/m_debuginfo/debuginfo.c.orig -+++ coregrind/m_debuginfo/debuginfo.c -@@ -1,4 +1,5 @@ - -+ - /*--------------------------------------------------------------------*/ - /*--- Top level management of symbols and debugging information. ---*/ - /*--- debuginfo.c ---*/ -@@ -3983,6 +3984,7 @@ void VG_(DebugInfo_syms_getidx) ( const - Int idx, - /*OUT*/Addr* avma, - /*OUT*/Addr* tocptr, -+ /*OUT*/Addr* local_ep, - /*OUT*/UInt* size, - /*OUT*/HChar** pri_name, - /*OUT*/HChar*** sec_names, -@@ -3992,6 +3994,7 @@ void VG_(DebugInfo_syms_getidx) ( const - vg_assert(idx >= 0 && idx < si->symtab_used); - if (avma) *avma = si->symtab[idx].addr; - if (tocptr) *tocptr = si->symtab[idx].tocptr; -+ if (local_ep) *local_ep = si->symtab[idx].local_ep; - if (size) *size = si->symtab[idx].size; - if (pri_name) *pri_name = si->symtab[idx].pri_name; - if (sec_names) *sec_names = (HChar **)si->symtab[idx].sec_names; // FIXME -Index: coregrind/m_signals.c -=================================================================== ---- coregrind/m_signals.c.orig -+++ coregrind/m_signals.c -@@ -866,6 +866,23 @@ extern void my_sigreturn(void); - " li 0, " #name "\n" \ - " sc\n" - -+#elif defined(VGP_ppc64le_linux) -+/* Little Endian supports ELF version 2. In the future, it may -+ * support other versions. -+ */ -+# define _MY_SIGRETURN(name) \ -+ ".align 2\n" \ -+ ".globl my_sigreturn\n" \ -+ ".type .my_sigreturn,@function\n" \ -+ "my_sigreturn:\n" \ -+ "#if _CALL_ELF == 2 \n" \ -+ "0: addis 2,12,.TOC.-0b@ha\n" \ -+ " addi 2,2,.TOC.-0b@l\n" \ -+ " .localentry my_sigreturn,.-my_sigreturn\n" \ -+ "#endif \n" \ -+ " sc\n" \ -+ " .size my_sigreturn,.-my_sigreturn\n" -+ - #elif defined(VGP_arm_linux) - # define _MY_SIGRETURN(name) \ - ".text\n" \ -Index: coregrind/m_redir.c -=================================================================== ---- coregrind/m_redir.c.orig -+++ coregrind/m_redir.c -@@ -397,7 +397,7 @@ void VG_(redir_notify_new_DebugInfo)( De - TopSpec* newts; - HChar* sym_name_pri; - HChar** sym_names_sec; -- Addr sym_addr, sym_toc; -+ Addr sym_addr, sym_toc, local_ep; - HChar demangled_sopatt[N_DEMANGLED]; - HChar demangled_fnpatt[N_DEMANGLED]; - Bool check_ppcTOCs = False; -@@ -499,7 +499,7 @@ void VG_(redir_notify_new_DebugInfo)( De - - nsyms = VG_(DebugInfo_syms_howmany)( newdi ); - for (i = 0; i < nsyms; i++) { -- VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc, -+ VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc, &local_ep, - NULL, &sym_name_pri, &sym_names_sec, - &isText, NULL ); - /* Set up to conveniently iterate over all names for this symbol. */ -@@ -592,7 +592,7 @@ void VG_(redir_notify_new_DebugInfo)( De - - if (check_ppcTOCs) { - for (i = 0; i < nsyms; i++) { -- VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc, -+ VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc, &local_ep, - NULL, &sym_name_pri, &sym_names_sec, - &isText, NULL ); - HChar* twoslots[2]; -@@ -755,7 +755,9 @@ void generate_and_add_actives ( - of trashing the caches less. */ - nsyms = VG_(DebugInfo_syms_howmany)( di ); - for (i = 0; i < nsyms; i++) { -- VG_(DebugInfo_syms_getidx)( di, i, &sym_addr, NULL, -+ Addr local_ep = 0; -+ -+ VG_(DebugInfo_syms_getidx)( di, i, &sym_addr, NULL, &local_ep, - NULL, &sym_name_pri, &sym_names_sec, - &isText, &isIFunc ); - HChar* twoslots[2]; -@@ -783,6 +785,18 @@ void generate_and_add_actives ( - act.isIFunc = isIFunc; - sp->done = True; - maybe_add_active( act ); -+ -+ /* If the function being wrapped has a local entry point -+ * redirect it to the global entry point. The redirection -+ * must save and setup r2 then setup r12 for the new function. -+ * On return, r2 must be restored. Local entry points used -+ * used in PPC64 Little Endian. -+ */ -+ if (local_ep != 0) { -+ act.from_addr = local_ep; -+ maybe_add_active( act ); -+ } -+ - } - } /* for (sp = specs; sp; sp = sp->next) */ - -@@ -1298,6 +1312,27 @@ void VG_(redir_initialise) ( void ) - ); - } - -+# elif defined(VGP_ppc64le_linux) -+ /* If we're using memcheck, use these intercepts right from -+ * the start, otherwise ld.so makes a lot of noise. -+ */ -+ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { -+ -+ /* this is mandatory - can't sanely continue without it */ -+ add_hardwired_spec( -+ "ld64.so.2", "strlen", -+ (Addr)&VG_(ppc64_linux_REDIR_FOR_strlen), -+ complain_about_stripped_glibc_ldso -+ ); -+ -+ add_hardwired_spec( -+ "ld64.so.2", "index", -+ (Addr)&VG_(ppc64_linux_REDIR_FOR_strchr), -+ NULL /* not mandatory - so why bother at all? */ -+ /* glibc-2.5 (FC6, ppc64) seems fine without it */ -+ ); -+ } -+ - # elif defined(VGP_arm_linux) - /* If we're using memcheck, use these intercepts right from - the start, otherwise ld.so makes a lot of noise. */ -@@ -1551,7 +1586,7 @@ static void handle_require_text_symbols - Bool isText = False; - HChar* sym_name_pri = NULL; - HChar** sym_names_sec = NULL; -- VG_(DebugInfo_syms_getidx)( di, j, NULL, NULL, -+ VG_(DebugInfo_syms_getidx)( di, j, NULL, NULL, NULL, - NULL, &sym_name_pri, &sym_names_sec, - &isText, NULL ); - HChar* twoslots[2]; -Index: coregrind/m_ume/elf.c -=================================================================== ---- coregrind/m_ume/elf.c.orig -+++ coregrind/m_ume/elf.c -@@ -520,6 +520,10 @@ Int VG_(load_ELF)(Int fd, const HChar* n - info->init_toc = ((ULong*)entry)[1]; - info->init_ip += interp_offset; - info->init_toc += interp_offset; -+#elif defined(VGP_ppc64le_linux) -+ /* On PPC64LE, ELF ver 2. API doesn't use a func ptr */ -+ info->init_ip = (Addr)entry; -+ info->init_toc = 0; /* meaningless on this platform */ - #else - info->init_ip = (Addr)entry; - info->init_toc = 0; /* meaningless on this platform */ -Index: coregrind/m_ume/macho.c -=================================================================== ---- coregrind/m_ume/macho.c.orig -+++ coregrind/m_ume/macho.c -@@ -701,6 +701,8 @@ load_fat_file(int fd, vki_off_t offset, - good_arch = CPU_TYPE_POWERPC; - #elif defined(VGA_ppc64be) - good_arch = CPU_TYPE_POWERPC64BE; -+#elif defined(VGA_ppc64le) -+ good_arch = CPU_TYPE_POWERPC64LE; - #elif defined(VGA_x86) - good_arch = CPU_TYPE_I386; - #elif defined(VGA_amd64) -Index: coregrind/m_dispatch/dispatch-ppc64-linux.S -=================================================================== ---- coregrind/m_dispatch/dispatch-ppc64-linux.S -+++ /dev/null -@@ -1,537 +0,0 @@ -- --/*--------------------------------------------------------------------*/ --/*--- The core dispatch loop, for jumping to a code address. ---*/ --/*--- dispatch-ppc64-linux.S ---*/ --/*--------------------------------------------------------------------*/ -- --/* -- This file is part of Valgrind, a dynamic binary instrumentation -- framework. -- -- Copyright (C) 2005-2013 Cerion Armour-Brown -- -- This program is free software; you can redistribute it and/or -- modify it under the terms of the GNU General Public License as -- published by the Free Software Foundation; either version 2 of the -- License, or (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -- 02111-1307, USA. -- -- The GNU General Public License is contained in the file COPYING. --*/ -- --#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) -- --#include "pub_core_basics_asm.h" --#include "pub_core_dispatch_asm.h" --#include "pub_core_transtab_asm.h" --#include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */ -- -- --/* References to globals via the TOC */ -- --/* -- .globl vgPlain_tt_fast -- .lcomm vgPlain_tt_fast,4,4 -- .type vgPlain_tt_fast, @object --*/ --.section ".toc","aw" --.tocent__vgPlain_tt_fast: -- .tc vgPlain_tt_fast[TC],vgPlain_tt_fast --.tocent__vgPlain_stats__n_xindirs_32: -- .tc vgPlain_stats__n_xindirs_32[TC],vgPlain_stats__n_xindirs_32 --.tocent__vgPlain_stats__n_xindir_misses_32: -- .tc vgPlain_stats__n_xindir_misses_32[TC],vgPlain_stats__n_xindir_misses_32 --.tocent__vgPlain_machine_ppc64_has_VMX: -- .tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX -- --/*------------------------------------------------------------*/ --/*--- ---*/ --/*--- The dispatch loop. VG_(disp_run_translations) is ---*/ --/*--- used to run all translations, ---*/ --/*--- including no-redir ones. ---*/ --/*--- ---*/ --/*------------------------------------------------------------*/ -- --/*----------------------------------------------------*/ --/*--- Entry and preamble (set everything up) ---*/ --/*----------------------------------------------------*/ -- --/* signature: --void VG_(disp_run_translations)( UWord* two_words, -- void* guest_state, -- Addr host_addr ); --*/ -- --.section ".text" --.align 2 --.globl VG_(disp_run_translations) --.section ".opd","aw" --.align 3 --VG_(disp_run_translations): --.quad .VG_(disp_run_translations),.TOC.@tocbase,0 --.previous --.type .VG_(disp_run_translations),@function --.globl .VG_(disp_run_translations) --.VG_(disp_run_translations): -- /* r3 holds two_words */ -- /* r4 holds guest_state */ -- /* r5 holds host_addr */ -- -- /* ----- entry point to VG_(disp_run_translations) ----- */ -- /* PPC64 ABI saves LR->16(prt_sp), CR->8(prt_sp)) */ -- -- /* Save lr, cr */ -- mflr 6 -- std 6,16(1) -- mfcr 6 -- std 6,8(1) -- -- /* New stack frame */ -- stdu 1,-624(1) /* sp should maintain 16-byte alignment */ -- -- /* General reg save area : 152 bytes */ -- std 31,472(1) -- std 30,464(1) -- std 29,456(1) -- std 28,448(1) -- std 27,440(1) -- std 26,432(1) -- std 25,424(1) -- std 24,416(1) -- std 23,408(1) -- std 22,400(1) -- std 21,392(1) -- std 20,384(1) -- std 19,376(1) -- std 18,368(1) -- std 17,360(1) -- std 16,352(1) -- std 15,344(1) -- std 14,336(1) -- std 13,328(1) -- std 3,104(1) /* save two_words for later */ -- -- /* Save callee-saved registers... */ -- /* Floating-point reg save area : 144 bytes */ -- stfd 31,616(1) -- stfd 30,608(1) -- stfd 29,600(1) -- stfd 28,592(1) -- stfd 27,584(1) -- stfd 26,576(1) -- stfd 25,568(1) -- stfd 24,560(1) -- stfd 23,552(1) -- stfd 22,544(1) -- stfd 21,536(1) -- stfd 20,528(1) -- stfd 19,520(1) -- stfd 18,512(1) -- stfd 17,504(1) -- stfd 16,496(1) -- stfd 15,488(1) -- stfd 14,480(1) -- -- /* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI. -- The Linux kernel might not actually use VRSAVE for its intended -- purpose, but it should be harmless to preserve anyway. */ -- /* r3, r4, r5 are live here, so use r6 */ -- ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -- ld 6,0(6) -- cmpldi 6,0 -- beq .LafterVMX1 -- -- /* VRSAVE save word : 32 bytes */ -- mfspr 6,256 /* vrsave reg is spr number 256 */ -- stw 6,324(1) -- -- /* Alignment padding : 4 bytes */ -- -- /* Vector reg save area (quadword aligned) : 192 bytes */ -- li 6,304 -- stvx 31,6,1 -- li 6,288 -- stvx 30,6,1 -- li 6,272 -- stvx 29,6,1 -- li 6,256 -- stvx 28,6,1 -- li 6,240 -- stvx 27,6,1 -- li 6,224 -- stvx 26,6,1 -- li 6,208 -- stvx 25,6,1 -- li 6,192 -- stvx 24,6,1 -- li 6,176 -- stvx 23,6,1 -- li 6,160 -- stvx 22,6,1 -- li 6,144 -- stvx 21,6,1 -- li 6,128 -- stvx 20,6,1 --.LafterVMX1: -- -- /* Local variable space... */ -- -- /* r3 holds two_words */ -- /* r4 holds guest_state */ -- /* r5 holds host_addr */ -- -- /* 96(sp) used later to check FPSCR[RM] */ -- /* 88(sp) used later to load fpscr with zero */ -- /* 48:87(sp) free */ -- -- /* Linkage Area (reserved) BE ABI -- 40(sp) : TOC -- 32(sp) : link editor doubleword -- 24(sp) : compiler doubleword -- 16(sp) : LR -- 8(sp) : CR -- 0(sp) : back-chain -- */ -- -- /* set host FPU control word to the default mode expected -- by VEX-generated code. See comments in libvex.h for -- more info. */ -- /* => get zero into f3 (tedious) -- fsub 3,3,3 is not a reliable way to do this, since if -- f3 holds a NaN or similar then we don't necessarily -- wind up with zero. */ -- li 6,0 -- stw 6,88(1) -- lfs 3,88(1) -- mtfsf 0xFF,3 /* fpscr = lo32 of f3 */ -- -- /* set host AltiVec control word to the default mode expected -- by VEX-generated code. */ -- ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -- ld 6,0(6) -- cmpldi 6,0 -- beq .LafterVMX2 -- -- vspltisw 3,0x0 /* generate zero */ -- mtvscr 3 --.LafterVMX2: -- -- /* make a stack frame for the code we are calling */ -- stdu 1,-48(1) -- -- /* Set up the guest state ptr */ -- mr 31,4 /* r31 (generated code gsp) = r4 */ -- -- /* and jump into the code cache. Chained translations in -- the code cache run, until for whatever reason, they can't -- continue. When that happens, the translation in question -- will jump (or call) to one of the continuation points -- VG_(cp_...) below. */ -- mtctr 5 -- bctr -- /*NOTREACHED*/ -- --/*----------------------------------------------------*/ --/*--- Postamble and exit. ---*/ --/*----------------------------------------------------*/ -- --.postamble: -- /* At this point, r6 and r7 contain two -- words to be returned to the caller. r6 -- holds a TRC value, and r7 optionally may -- hold another word (for CHAIN_ME exits, the -- address of the place to patch.) */ -- -- /* undo the "make a stack frame for the code we are calling" */ -- addi 1,1,48 -- -- /* We're leaving. Check that nobody messed with -- VSCR or FPSCR in ways we don't expect. */ -- /* Using r11 - value used again further on, so don't trash! */ -- ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -- ld 11,0(11) -- -- /* Set fpscr back to a known state, since vex-generated code -- may have messed with fpscr[rm]. */ -- li 5,0 -- addi 1,1,-16 -- stw 5,0(1) -- lfs 3,0(1) -- addi 1,1,16 -- mtfsf 0xFF,3 /* fpscr = f3 */ -- -- cmpldi 11,0 /* Do we have altivec? */ -- beq .LafterVMX8 -- -- /* Check VSCR[NJ] == 1 */ -- /* first generate 4x 0x00010000 */ -- vspltisw 4,0x1 /* 4x 0x00000001 */ -- vspltisw 5,0x0 /* zero */ -- vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */ -- /* retrieve VSCR and mask wanted bits */ -- mfvscr 7 -- vand 7,7,6 /* gives NJ flag */ -- vspltw 7,7,0x3 /* flags-word to all lanes */ -- vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */ -- bt 24,.invariant_violation /* branch if all_equal */ -- --.LafterVMX8: -- /* otherwise we're OK */ -- b .remove_frame -- --.invariant_violation: -- li 6,VG_TRC_INVARIANT_FAILED -- li 7,0 -- /* fall through */ -- --.remove_frame: -- /* r11 already holds VG_(machine_ppc32_has_VMX) value */ -- cmplwi 11,0 -- beq .LafterVMX9 -- -- /* Restore Altivec regs. -- Use r5 as scratch since r6/r7 are live. */ -- /* VRSAVE */ -- lwz 5,324(1) -- mfspr 5,256 /* VRSAVE reg is spr number 256 */ -- -- /* Vector regs */ -- li 5,304 -- lvx 31,5,1 -- li 5,288 -- lvx 30,5,1 -- li 5,272 -- lvx 29,5,1 -- li 5,256 -- lvx 28,5,1 -- li 5,240 -- lvx 27,5,1 -- li 5,224 -- lvx 26,5,1 -- li 5,208 -- lvx 25,5,1 -- li 5,192 -- lvx 24,5,1 -- li 5,176 -- lvx 23,5,1 -- li 5,160 -- lvx 22,5,1 -- li 5,144 -- lvx 21,5,1 -- li 5,128 -- lvx 20,5,1 --.LafterVMX9: -- -- /* Restore FP regs */ -- /* Floating-point regs */ -- lfd 31,616(1) -- lfd 30,608(1) -- lfd 29,600(1) -- lfd 28,592(1) -- lfd 27,584(1) -- lfd 26,576(1) -- lfd 25,568(1) -- lfd 24,560(1) -- lfd 23,552(1) -- lfd 22,544(1) -- lfd 21,536(1) -- lfd 20,528(1) -- lfd 19,520(1) -- lfd 18,512(1) -- lfd 17,504(1) -- lfd 16,496(1) -- lfd 15,488(1) -- lfd 14,480(1) -- -- /* restore int regs, including importantly r3 (two_words) */ -- ld 31,472(1) -- ld 30,464(1) -- ld 29,456(1) -- ld 28,448(1) -- ld 27,440(1) -- ld 26,432(1) -- ld 25,424(1) -- ld 24,416(1) -- ld 23,408(1) -- ld 22,400(1) -- ld 21,392(1) -- ld 20,384(1) -- ld 19,376(1) -- ld 18,368(1) -- ld 17,360(1) -- ld 16,352(1) -- ld 15,344(1) -- ld 14,336(1) -- ld 13,328(1) -- ld 3,104(1) -- /* Stash return values */ -- std 6,0(3) -- std 7,8(3) -- -- /* restore lr & sp, and leave */ -- ld 0,632(1) /* stack_size + 8 */ -- mtcr 0 -- ld 0,640(1) /* stack_size + 16 */ -- mtlr 0 -- addi 1,1,624 /* stack_size */ -- blr -- -- --/*----------------------------------------------------*/ --/*--- Continuation points ---*/ --/*----------------------------------------------------*/ -- --/* ------ Chain me to slow entry point ------ */ -- .section ".text" -- .align 2 -- .globl VG_(disp_cp_chain_me_to_slowEP) -- .section ".opd","aw" -- .align 3 --VG_(disp_cp_chain_me_to_slowEP): -- .quad .VG_(disp_cp_chain_me_to_slowEP),.TOC.@tocbase,0 -- .previous -- .type .VG_(disp_cp_chain_me_to_slowEP),@function -- .globl .VG_(disp_cp_chain_me_to_slowEP) --.VG_(disp_cp_chain_me_to_slowEP): -- /* We got called. The return address indicates -- where the patching needs to happen. Collect -- the return address and, exit back to C land, -- handing the caller the pair (Chain_me_S, RA) */ -- li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP -- mflr 7 -- /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_slowEP -- 4 = mtctr r30 -- 4 = btctr -- */ -- subi 7,7,20+4+4 -- b .postamble -- --/* ------ Chain me to fast entry point ------ */ -- .section ".text" -- .align 2 -- .globl VG_(disp_cp_chain_me_to_fastEP) -- .section ".opd","aw" -- .align 3 --VG_(disp_cp_chain_me_to_fastEP): -- .quad .VG_(disp_cp_chain_me_to_fastEP),.TOC.@tocbase,0 -- .previous -- .type .VG_(disp_cp_chain_me_to_fastEP),@function -- .globl .VG_(disp_cp_chain_me_to_fastEP) --.VG_(disp_cp_chain_me_to_fastEP): -- /* We got called. The return address indicates -- where the patching needs to happen. Collect -- the return address and, exit back to C land, -- handing the caller the pair (Chain_me_S, RA) */ -- li 6, VG_TRC_CHAIN_ME_TO_FAST_EP -- mflr 7 -- /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_fastEP -- 4 = mtctr r30 -- 4 = btctr -- */ -- subi 7,7,20+4+4 -- b .postamble -- --/* ------ Indirect but boring jump ------ */ -- .section ".text" -- .align 2 -- .globl VG_(disp_cp_xindir) -- .section ".opd","aw" -- .align 3 --VG_(disp_cp_xindir): -- .quad .VG_(disp_cp_xindir),.TOC.@tocbase,0 -- .previous -- .type .VG_(disp_cp_xindir),@function -- .globl .VG_(disp_cp_xindir) --.VG_(disp_cp_xindir): -- /* Where are we going? */ -- ld 3,OFFSET_ppc64_CIA(31) -- -- /* stats only */ -- ld 5, .tocent__vgPlain_stats__n_xindirs_32@toc(2) -- lwz 6,0(5) -- addi 6,6,1 -- stw 6,0(5) -- -- /* r5 = &VG_(tt_fast) */ -- ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */ -- -- /* try a fast lookup in the translation cache */ -- /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry) -- = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */ -- rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */ -- sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */ -- add 5,5,4 /* & VG_(tt_fast)[entry#] */ -- ld 6,0(5) /* .guest */ -- ld 7,8(5) /* .host */ -- cmpd 3,6 -- bne .fast_lookup_failed -- -- /* Found a match. Jump to .host. */ -- mtctr 7 -- bctr -- --.fast_lookup_failed: -- /* stats only */ -- ld 5, .tocent__vgPlain_stats__n_xindir_misses_32@toc(2) -- lwz 6,0(5) -- addi 6,6,1 -- stw 6,0(5) -- -- li 6,VG_TRC_INNER_FASTMISS -- li 7,0 -- b .postamble -- /*NOTREACHED*/ -- --/* ------ Assisted jump ------ */ --.section ".text" -- .align 2 -- .globl VG_(disp_cp_xassisted) -- .section ".opd","aw" -- .align 3 --VG_(disp_cp_xassisted): -- .quad .VG_(disp_cp_xassisted),.TOC.@tocbase,0 -- .previous -- .type .VG_(disp_cp_xassisted),@function -- .globl .VG_(disp_cp_xassisted) --.VG_(disp_cp_xassisted): -- /* r31 contains the TRC */ -- mr 6,31 -- li 7,0 -- b .postamble -- --/* ------ Event check failed ------ */ -- .section ".text" -- .align 2 -- .globl VG_(disp_cp_evcheck_fail) -- .section ".opd","aw" -- .align 3 --VG_(disp_cp_evcheck_fail): -- .quad .VG_(disp_cp_evcheck_fail),.TOC.@tocbase,0 -- .previous -- .type .VG_(disp_cp_evcheck_fail),@function -- .globl .VG_(disp_cp_evcheck_fail) --.VG_(disp_cp_evcheck_fail): -- li 6,VG_TRC_INNER_COUNTERZERO -- li 7,0 -- b .postamble -- -- --.size .VG_(disp_run_translations), .-.VG_(disp_run_translations) -- --/* Let the linker know we don't need an executable stack */ --.section .note.GNU-stack,"",@progbits -- --#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) -- --/*--------------------------------------------------------------------*/ --/*--- end ---*/ --/*--------------------------------------------------------------------*/ -Index: coregrind/m_dispatch/dispatch-ppc64be-linux.S -=================================================================== ---- /dev/null -+++ coregrind/m_dispatch/dispatch-ppc64be-linux.S -@@ -0,0 +1,537 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- The core dispatch loop, for jumping to a code address. ---*/ -+/*--- dispatch-ppc64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2005-2013 Cerion Armour-Brown -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_ppc64be_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_dispatch_asm.h" -+#include "pub_core_transtab_asm.h" -+#include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */ -+ -+ -+/* References to globals via the TOC */ -+ -+/* -+ .globl vgPlain_tt_fast -+ .lcomm vgPlain_tt_fast,4,4 -+ .type vgPlain_tt_fast, @object -+*/ -+.section ".toc","aw" -+.tocent__vgPlain_tt_fast: -+ .tc vgPlain_tt_fast[TC],vgPlain_tt_fast -+.tocent__vgPlain_stats__n_xindirs_32: -+ .tc vgPlain_stats__n_xindirs_32[TC],vgPlain_stats__n_xindirs_32 -+.tocent__vgPlain_stats__n_xindir_misses_32: -+ .tc vgPlain_stats__n_xindir_misses_32[TC],vgPlain_stats__n_xindir_misses_32 -+.tocent__vgPlain_machine_ppc64_has_VMX: -+ .tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX -+ -+/*------------------------------------------------------------*/ -+/*--- ---*/ -+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/ -+/*--- used to run all translations, ---*/ -+/*--- including no-redir ones. ---*/ -+/*--- ---*/ -+/*------------------------------------------------------------*/ -+ -+/*----------------------------------------------------*/ -+/*--- Entry and preamble (set everything up) ---*/ -+/*----------------------------------------------------*/ -+ -+/* signature: -+void VG_(disp_run_translations)( UWord* two_words, -+ void* guest_state, -+ Addr host_addr ); -+*/ -+ -+.section ".text" -+.align 2 -+.globl VG_(disp_run_translations) -+.section ".opd","aw" -+.align 3 -+VG_(disp_run_translations): -+.quad .VG_(disp_run_translations),.TOC.@tocbase,0 -+.previous -+.type .VG_(disp_run_translations),@function -+.globl .VG_(disp_run_translations) -+.VG_(disp_run_translations): -+ /* r3 holds two_words */ -+ /* r4 holds guest_state */ -+ /* r5 holds host_addr */ -+ -+ /* ----- entry point to VG_(disp_run_translations) ----- */ -+ /* PPC64 ABI saves LR->16(prt_sp), CR->8(prt_sp)) */ -+ -+ /* Save lr, cr */ -+ mflr 6 -+ std 6,16(1) -+ mfcr 6 -+ std 6,8(1) -+ -+ /* New stack frame */ -+ stdu 1,-624(1) /* sp should maintain 16-byte alignment */ -+ -+ /* General reg save area : 152 bytes */ -+ std 31,472(1) -+ std 30,464(1) -+ std 29,456(1) -+ std 28,448(1) -+ std 27,440(1) -+ std 26,432(1) -+ std 25,424(1) -+ std 24,416(1) -+ std 23,408(1) -+ std 22,400(1) -+ std 21,392(1) -+ std 20,384(1) -+ std 19,376(1) -+ std 18,368(1) -+ std 17,360(1) -+ std 16,352(1) -+ std 15,344(1) -+ std 14,336(1) -+ std 13,328(1) -+ std 3,104(1) /* save two_words for later */ -+ -+ /* Save callee-saved registers... */ -+ /* Floating-point reg save area : 144 bytes */ -+ stfd 31,616(1) -+ stfd 30,608(1) -+ stfd 29,600(1) -+ stfd 28,592(1) -+ stfd 27,584(1) -+ stfd 26,576(1) -+ stfd 25,568(1) -+ stfd 24,560(1) -+ stfd 23,552(1) -+ stfd 22,544(1) -+ stfd 21,536(1) -+ stfd 20,528(1) -+ stfd 19,520(1) -+ stfd 18,512(1) -+ stfd 17,504(1) -+ stfd 16,496(1) -+ stfd 15,488(1) -+ stfd 14,480(1) -+ -+ /* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI. -+ The Linux kernel might not actually use VRSAVE for its intended -+ purpose, but it should be harmless to preserve anyway. */ -+ /* r3, r4, r5 are live here, so use r6 */ -+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -+ ld 6,0(6) -+ cmpldi 6,0 -+ beq .LafterVMX1 -+ -+ /* VRSAVE save word : 32 bytes */ -+ mfspr 6,256 /* vrsave reg is spr number 256 */ -+ stw 6,324(1) -+ -+ /* Alignment padding : 4 bytes */ -+ -+ /* Vector reg save area (quadword aligned) : 192 bytes */ -+ li 6,304 -+ stvx 31,6,1 -+ li 6,288 -+ stvx 30,6,1 -+ li 6,272 -+ stvx 29,6,1 -+ li 6,256 -+ stvx 28,6,1 -+ li 6,240 -+ stvx 27,6,1 -+ li 6,224 -+ stvx 26,6,1 -+ li 6,208 -+ stvx 25,6,1 -+ li 6,192 -+ stvx 24,6,1 -+ li 6,176 -+ stvx 23,6,1 -+ li 6,160 -+ stvx 22,6,1 -+ li 6,144 -+ stvx 21,6,1 -+ li 6,128 -+ stvx 20,6,1 -+.LafterVMX1: -+ -+ /* Local variable space... */ -+ -+ /* r3 holds two_words */ -+ /* r4 holds guest_state */ -+ /* r5 holds host_addr */ -+ -+ /* 96(sp) used later to check FPSCR[RM] */ -+ /* 88(sp) used later to load fpscr with zero */ -+ /* 48:87(sp) free */ -+ -+ /* Linkage Area (reserved) BE ABI -+ 40(sp) : TOC -+ 32(sp) : link editor doubleword -+ 24(sp) : compiler doubleword -+ 16(sp) : LR -+ 8(sp) : CR -+ 0(sp) : back-chain -+ */ -+ -+ /* set host FPU control word to the default mode expected -+ by VEX-generated code. See comments in libvex.h for -+ more info. */ -+ /* => get zero into f3 (tedious) -+ fsub 3,3,3 is not a reliable way to do this, since if -+ f3 holds a NaN or similar then we don't necessarily -+ wind up with zero. */ -+ li 6,0 -+ stw 6,88(1) -+ lfs 3,88(1) -+ mtfsf 0xFF,3 /* fpscr = lo32 of f3 */ -+ -+ /* set host AltiVec control word to the default mode expected -+ by VEX-generated code. */ -+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -+ ld 6,0(6) -+ cmpldi 6,0 -+ beq .LafterVMX2 -+ -+ vspltisw 3,0x0 /* generate zero */ -+ mtvscr 3 -+.LafterVMX2: -+ -+ /* make a stack frame for the code we are calling */ -+ stdu 1,-48(1) -+ -+ /* Set up the guest state ptr */ -+ mr 31,4 /* r31 (generated code gsp) = r4 */ -+ -+ /* and jump into the code cache. Chained translations in -+ the code cache run, until for whatever reason, they can't -+ continue. When that happens, the translation in question -+ will jump (or call) to one of the continuation points -+ VG_(cp_...) below. */ -+ mtctr 5 -+ bctr -+ /*NOTREACHED*/ -+ -+/*----------------------------------------------------*/ -+/*--- Postamble and exit. ---*/ -+/*----------------------------------------------------*/ -+ -+.postamble: -+ /* At this point, r6 and r7 contain two -+ words to be returned to the caller. r6 -+ holds a TRC value, and r7 optionally may -+ hold another word (for CHAIN_ME exits, the -+ address of the place to patch.) */ -+ -+ /* undo the "make a stack frame for the code we are calling" */ -+ addi 1,1,48 -+ -+ /* We're leaving. Check that nobody messed with -+ VSCR or FPSCR in ways we don't expect. */ -+ /* Using r11 - value used again further on, so don't trash! */ -+ ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -+ ld 11,0(11) -+ -+ /* Set fpscr back to a known state, since vex-generated code -+ may have messed with fpscr[rm]. */ -+ li 5,0 -+ addi 1,1,-16 -+ stw 5,0(1) -+ lfs 3,0(1) -+ addi 1,1,16 -+ mtfsf 0xFF,3 /* fpscr = f3 */ -+ -+ cmpldi 11,0 /* Do we have altivec? */ -+ beq .LafterVMX8 -+ -+ /* Check VSCR[NJ] == 1 */ -+ /* first generate 4x 0x00010000 */ -+ vspltisw 4,0x1 /* 4x 0x00000001 */ -+ vspltisw 5,0x0 /* zero */ -+ vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */ -+ /* retrieve VSCR and mask wanted bits */ -+ mfvscr 7 -+ vand 7,7,6 /* gives NJ flag */ -+ vspltw 7,7,0x3 /* flags-word to all lanes */ -+ vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */ -+ bt 24,.invariant_violation /* branch if all_equal */ -+ -+.LafterVMX8: -+ /* otherwise we're OK */ -+ b .remove_frame -+ -+.invariant_violation: -+ li 6,VG_TRC_INVARIANT_FAILED -+ li 7,0 -+ /* fall through */ -+ -+.remove_frame: -+ /* r11 already holds VG_(machine_ppc32_has_VMX) value */ -+ cmplwi 11,0 -+ beq .LafterVMX9 -+ -+ /* Restore Altivec regs. -+ Use r5 as scratch since r6/r7 are live. */ -+ /* VRSAVE */ -+ lwz 5,324(1) -+ mfspr 5,256 /* VRSAVE reg is spr number 256 */ -+ -+ /* Vector regs */ -+ li 5,304 -+ lvx 31,5,1 -+ li 5,288 -+ lvx 30,5,1 -+ li 5,272 -+ lvx 29,5,1 -+ li 5,256 -+ lvx 28,5,1 -+ li 5,240 -+ lvx 27,5,1 -+ li 5,224 -+ lvx 26,5,1 -+ li 5,208 -+ lvx 25,5,1 -+ li 5,192 -+ lvx 24,5,1 -+ li 5,176 -+ lvx 23,5,1 -+ li 5,160 -+ lvx 22,5,1 -+ li 5,144 -+ lvx 21,5,1 -+ li 5,128 -+ lvx 20,5,1 -+.LafterVMX9: -+ -+ /* Restore FP regs */ -+ /* Floating-point regs */ -+ lfd 31,616(1) -+ lfd 30,608(1) -+ lfd 29,600(1) -+ lfd 28,592(1) -+ lfd 27,584(1) -+ lfd 26,576(1) -+ lfd 25,568(1) -+ lfd 24,560(1) -+ lfd 23,552(1) -+ lfd 22,544(1) -+ lfd 21,536(1) -+ lfd 20,528(1) -+ lfd 19,520(1) -+ lfd 18,512(1) -+ lfd 17,504(1) -+ lfd 16,496(1) -+ lfd 15,488(1) -+ lfd 14,480(1) -+ -+ /* restore int regs, including importantly r3 (two_words) */ -+ ld 31,472(1) -+ ld 30,464(1) -+ ld 29,456(1) -+ ld 28,448(1) -+ ld 27,440(1) -+ ld 26,432(1) -+ ld 25,424(1) -+ ld 24,416(1) -+ ld 23,408(1) -+ ld 22,400(1) -+ ld 21,392(1) -+ ld 20,384(1) -+ ld 19,376(1) -+ ld 18,368(1) -+ ld 17,360(1) -+ ld 16,352(1) -+ ld 15,344(1) -+ ld 14,336(1) -+ ld 13,328(1) -+ ld 3,104(1) -+ /* Stash return values */ -+ std 6,0(3) -+ std 7,8(3) -+ -+ /* restore lr & sp, and leave */ -+ ld 0,632(1) /* stack_size + 8 */ -+ mtcr 0 -+ ld 0,640(1) /* stack_size + 16 */ -+ mtlr 0 -+ addi 1,1,624 /* stack_size */ -+ blr -+ -+ -+/*----------------------------------------------------*/ -+/*--- Continuation points ---*/ -+/*----------------------------------------------------*/ -+ -+/* ------ Chain me to slow entry point ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_chain_me_to_slowEP) -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_chain_me_to_slowEP): -+ .quad .VG_(disp_cp_chain_me_to_slowEP),.TOC.@tocbase,0 -+ .previous -+ .type .VG_(disp_cp_chain_me_to_slowEP),@function -+ .globl .VG_(disp_cp_chain_me_to_slowEP) -+.VG_(disp_cp_chain_me_to_slowEP): -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_S, RA) */ -+ li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP -+ mflr 7 -+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_slowEP -+ 4 = mtctr r30 -+ 4 = btctr -+ */ -+ subi 7,7,20+4+4 -+ b .postamble -+ -+/* ------ Chain me to fast entry point ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_chain_me_to_fastEP) -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_chain_me_to_fastEP): -+ .quad .VG_(disp_cp_chain_me_to_fastEP),.TOC.@tocbase,0 -+ .previous -+ .type .VG_(disp_cp_chain_me_to_fastEP),@function -+ .globl .VG_(disp_cp_chain_me_to_fastEP) -+.VG_(disp_cp_chain_me_to_fastEP): -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_S, RA) */ -+ li 6, VG_TRC_CHAIN_ME_TO_FAST_EP -+ mflr 7 -+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_fastEP -+ 4 = mtctr r30 -+ 4 = btctr -+ */ -+ subi 7,7,20+4+4 -+ b .postamble -+ -+/* ------ Indirect but boring jump ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_xindir) -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_xindir): -+ .quad .VG_(disp_cp_xindir),.TOC.@tocbase,0 -+ .previous -+ .type .VG_(disp_cp_xindir),@function -+ .globl .VG_(disp_cp_xindir) -+.VG_(disp_cp_xindir): -+ /* Where are we going? */ -+ ld 3,OFFSET_ppc64_CIA(31) -+ -+ /* stats only */ -+ ld 5, .tocent__vgPlain_stats__n_xindirs_32@toc(2) -+ lwz 6,0(5) -+ addi 6,6,1 -+ stw 6,0(5) -+ -+ /* r5 = &VG_(tt_fast) */ -+ ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */ -+ -+ /* try a fast lookup in the translation cache */ -+ /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry) -+ = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */ -+ rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */ -+ sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */ -+ add 5,5,4 /* & VG_(tt_fast)[entry#] */ -+ ld 6,0(5) /* .guest */ -+ ld 7,8(5) /* .host */ -+ cmpd 3,6 -+ bne .fast_lookup_failed -+ -+ /* Found a match. Jump to .host. */ -+ mtctr 7 -+ bctr -+ -+.fast_lookup_failed: -+ /* stats only */ -+ ld 5, .tocent__vgPlain_stats__n_xindir_misses_32@toc(2) -+ lwz 6,0(5) -+ addi 6,6,1 -+ stw 6,0(5) -+ -+ li 6,VG_TRC_INNER_FASTMISS -+ li 7,0 -+ b .postamble -+ /*NOTREACHED*/ -+ -+/* ------ Assisted jump ------ */ -+.section ".text" -+ .align 2 -+ .globl VG_(disp_cp_xassisted) -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_xassisted): -+ .quad .VG_(disp_cp_xassisted),.TOC.@tocbase,0 -+ .previous -+ .type .VG_(disp_cp_xassisted),@function -+ .globl .VG_(disp_cp_xassisted) -+.VG_(disp_cp_xassisted): -+ /* r31 contains the TRC */ -+ mr 6,31 -+ li 7,0 -+ b .postamble -+ -+/* ------ Event check failed ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_evcheck_fail) -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_evcheck_fail): -+ .quad .VG_(disp_cp_evcheck_fail),.TOC.@tocbase,0 -+ .previous -+ .type .VG_(disp_cp_evcheck_fail),@function -+ .globl .VG_(disp_cp_evcheck_fail) -+.VG_(disp_cp_evcheck_fail): -+ li 6,VG_TRC_INNER_COUNTERZERO -+ li 7,0 -+ b .postamble -+ -+ -+.size .VG_(disp_run_translations), .-.VG_(disp_run_translations) -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",@progbits -+ -+#endif // defined(VGP_ppc64be_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_dispatch/dispatch-ppc64le-linux.S -=================================================================== ---- /dev/null -+++ coregrind/m_dispatch/dispatch-ppc64le-linux.S -@@ -0,0 +1,630 @@ -+ -+/*--------------------------------------------------------------------*/ -+/*--- The core dispatch loop, for jumping to a code address. ---*/ -+/*--- dispatch-ppc64-linux.S ---*/ -+/*--------------------------------------------------------------------*/ -+ -+/* -+ This file is part of Valgrind, a dynamic binary instrumentation -+ framework. -+ -+ Copyright (C) 2005-2013 Cerion Armour-Brown -+ -+ This program is free software; you can redistribute it and/or -+ modify it under the terms of the GNU General Public License as -+ published by the Free Software Foundation; either version 2 of the -+ License, or (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, but -+ WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307, USA. -+ -+ The GNU General Public License is contained in the file COPYING. -+*/ -+ -+#if defined(VGP_ppc64le_linux) -+ -+#include "pub_core_basics_asm.h" -+#include "pub_core_dispatch_asm.h" -+#include "pub_core_transtab_asm.h" -+#include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */ -+ -+/* NOTE: PPC64 supports Big Endian and Little Endian. It also supports the -+ ELF version 1 and ELF version 2 APIs. -+ -+ Currently LE uses ELF version 2 and BE uses ELF version 1. However, -+ BE and LE may support the other ELF version in the future. So, the -+ _CALL_ELF is used in the assembly function to enable code for a -+ specific ELF version independently of the Enianess of the machine. -+ The test "#if _CALL_ELF == 2" checks if ELF version 2 is being used. -+*/ -+ -+/* References to globals via the TOC */ -+ -+/* -+ .globl vgPlain_tt_fast -+ .lcomm vgPlain_tt_fast,4,4 -+ .type vgPlain_tt_fast, @object -+*/ -+.section ".toc","aw" -+.tocent__vgPlain_tt_fast: -+ .tc vgPlain_tt_fast[TC],vgPlain_tt_fast -+.tocent__vgPlain_stats__n_xindirs_32: -+ .tc vgPlain_stats__n_xindirs_32[TC],vgPlain_stats__n_xindirs_32 -+.tocent__vgPlain_stats__n_xindir_misses_32: -+ .tc vgPlain_stats__n_xindir_misses_32[TC],vgPlain_stats__n_xindir_misses_32 -+.tocent__vgPlain_machine_ppc64_has_VMX: -+ .tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX -+ -+/*------------------------------------------------------------*/ -+/*--- ---*/ -+/*--- The dispatch loop. VG_(disp_run_translations) is ---*/ -+/*--- used to run all translations, ---*/ -+/*--- including no-redir ones. ---*/ -+/*--- ---*/ -+/*------------------------------------------------------------*/ -+ -+/*----------------------------------------------------*/ -+/*--- Entry and preamble (set everything up) ---*/ -+/*----------------------------------------------------*/ -+ -+/* signature: -+void VG_(disp_run_translations)( UWord* two_words, -+ void* guest_state, -+ Addr host_addr ); -+*/ -+ -+.section ".text" -+.align 2 -+.globl VG_(disp_run_translations) -+#if _CALL_ELF == 2 -+.type VG_(disp_run_translations),@function -+VG_(disp_run_translations): -+.type .VG_(disp_run_translations),@function -+#else -+.section ".opd","aw" -+.align 3 -+VG_(disp_run_translations): -+.quad .VG_(disp_run_translations),.TOC.@tocbase,0 -+.previous -+.type .VG_(disp_run_translations),@function -+#endif -+.globl .VG_(disp_run_translations) -+.VG_(disp_run_translations): -+#if _CALL_ELF == 2 -+0: addis 2, 12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(disp_run_translations), .-VG_(disp_run_translations) -+#endif -+ -+ /* r3 holds two_words */ -+ /* r4 holds guest_state */ -+ /* r5 holds host_addr */ -+ -+ /* ----- entry point to VG_(disp_run_translations) ----- */ -+ /* PPC64 ABI saves LR->16(prt_sp), CR->8(prt_sp)) */ -+ -+ /* Save lr, cr */ -+ mflr 6 -+ std 6,16(1) -+ mfcr 6 -+ std 6,8(1) -+ -+ /* New stack frame */ -+ stdu 1,-624(1) /* sp should maintain 16-byte alignment */ -+ -+ /* General reg save area : 152 bytes */ -+ std 31,472(1) -+ std 30,464(1) -+ std 29,456(1) -+ std 28,448(1) -+ std 27,440(1) -+ std 26,432(1) -+ std 25,424(1) -+ std 24,416(1) -+ std 23,408(1) -+ std 22,400(1) -+ std 21,392(1) -+ std 20,384(1) -+ std 19,376(1) -+ std 18,368(1) -+ std 17,360(1) -+ std 16,352(1) -+ std 15,344(1) -+ std 14,336(1) -+ std 13,328(1) -+ std 3,104(1) /* save two_words for later */ -+ -+ /* Save callee-saved registers... */ -+ /* Floating-point reg save area : 144 bytes */ -+ stfd 31,616(1) -+ stfd 30,608(1) -+ stfd 29,600(1) -+ stfd 28,592(1) -+ stfd 27,584(1) -+ stfd 26,576(1) -+ stfd 25,568(1) -+ stfd 24,560(1) -+ stfd 23,552(1) -+ stfd 22,544(1) -+ stfd 21,536(1) -+ stfd 20,528(1) -+ stfd 19,520(1) -+ stfd 18,512(1) -+ stfd 17,504(1) -+ stfd 16,496(1) -+ stfd 15,488(1) -+ stfd 14,480(1) -+ -+ /* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI. -+ The Linux kernel might not actually use VRSAVE for its intended -+ purpose, but it should be harmless to preserve anyway. */ -+ /* r3, r4, r5 are live here, so use r6 */ -+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -+ ld 6,0(6) -+ cmpldi 6,0 -+ beq .LafterVMX1 -+ -+ /* VRSAVE save word : 32 bytes */ -+ mfspr 6,256 /* vrsave reg is spr number 256 */ -+ stw 6,324(1) -+ -+ /* Alignment padding : 4 bytes */ -+ -+ /* Vector reg save area (quadword aligned) : 192 bytes */ -+ li 6,304 -+ stvx 31,6,1 -+ li 6,288 -+ stvx 30,6,1 -+ li 6,272 -+ stvx 29,6,1 -+ li 6,256 -+ stvx 28,6,1 -+ li 6,240 -+ stvx 27,6,1 -+ li 6,224 -+ stvx 26,6,1 -+ li 6,208 -+ stvx 25,6,1 -+ li 6,192 -+ stvx 24,6,1 -+ li 6,176 -+ stvx 23,6,1 -+ li 6,160 -+ stvx 22,6,1 -+ li 6,144 -+ stvx 21,6,1 -+ li 6,128 -+ stvx 20,6,1 -+.LafterVMX1: -+ -+ /* Local variable space... */ -+ -+ /* r3 holds two_words */ -+ /* r4 holds guest_state */ -+ /* r5 holds host_addr */ -+ -+ /* 96(sp) used later to check FPSCR[RM] */ -+ /* 88(sp) used later to load fpscr with zero */ -+ /* 48:87(sp) free */ -+ -+ /* Linkage Area (reserved) BE ABI -+ 40(sp) : TOC -+ 32(sp) : link editor doubleword -+ 24(sp) : compiler doubleword -+ 16(sp) : LR -+ 8(sp) : CR -+ 0(sp) : back-chain -+ */ -+ -+ /* set host FPU control word to the default mode expected -+ by VEX-generated code. See comments in libvex.h for -+ more info. */ -+ /* => get zero into f3 (tedious) -+ fsub 3,3,3 is not a reliable way to do this, since if -+ f3 holds a NaN or similar then we don't necessarily -+ wind up with zero. */ -+ li 6,0 -+ stw 6,88(1) -+ lfs 3,88(1) -+ mtfsf 0xFF,3 /* fpscr = lo32 of f3 */ -+ -+ /* set host AltiVec control word to the default mode expected -+ by VEX-generated code. */ -+ ld 6,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -+ ld 6,0(6) -+ cmpldi 6,0 -+ beq .LafterVMX2 -+ -+ vspltisw 3,0x0 /* generate zero */ -+ mtvscr 3 -+.LafterVMX2: -+ -+ /* make a stack frame for the code we are calling */ -+ stdu 1,-48(1) -+ -+ /* Set up the guest state ptr */ -+ mr 31,4 /* r31 (generated code gsp) = r4 */ -+#if _CALL_ELF == 2 -+/* for the LE ABI need to setup r2 and r12 */ -+0: addis 2, 12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+#endif -+ -+ /* and jump into the code cache. Chained translations in -+ the code cache run, until for whatever reason, they can't -+ continue. When that happens, the translation in question -+ will jump (or call) to one of the continuation points -+ VG_(cp_...) below. */ -+ mtctr 5 -+ bctr -+ /*NOTREACHED*/ -+ -+/*----------------------------------------------------*/ -+/*--- Postamble and exit. ---*/ -+/*----------------------------------------------------*/ -+ -+.postamble: -+ /* At this point, r6 and r7 contain two -+ words to be returned to the caller. r6 -+ holds a TRC value, and r7 optionally may -+ hold another word (for CHAIN_ME exits, the -+ address of the place to patch.) */ -+ -+ /* undo the "make a stack frame for the code we are calling" */ -+ addi 1,1,48 -+ -+ /* We're leaving. Check that nobody messed with -+ VSCR or FPSCR in ways we don't expect. */ -+ /* Using r11 - value used again further on, so don't trash! */ -+ ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@toc(2) -+ ld 11,0(11) -+ -+ /* Set fpscr back to a known state, since vex-generated code -+ may have messed with fpscr[rm]. */ -+ li 5,0 -+ addi 1,1,-16 -+ stw 5,0(1) -+ lfs 3,0(1) -+ addi 1,1,16 -+ mtfsf 0xFF,3 /* fpscr = f3 */ -+ -+ cmpldi 11,0 /* Do we have altivec? */ -+ beq .LafterVMX8 -+ -+ /* Check VSCR[NJ] == 1 */ -+ /* first generate 4x 0x00010000 */ -+ vspltisw 4,0x1 /* 4x 0x00000001 */ -+ vspltisw 5,0x0 /* zero */ -+ vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */ -+ /* retrieve VSCR and mask wanted bits */ -+ mfvscr 7 -+ vand 7,7,6 /* gives NJ flag */ -+ vspltw 7,7,0x3 /* flags-word to all lanes */ -+ vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */ -+ bt 24,.invariant_violation /* branch if all_equal */ -+ -+.LafterVMX8: -+ /* otherwise we're OK */ -+ b .remove_frame -+ -+.invariant_violation: -+ li 6,VG_TRC_INVARIANT_FAILED -+ li 7,0 -+ /* fall through */ -+ -+.remove_frame: -+ /* r11 already holds VG_(machine_ppc32_has_VMX) value */ -+ cmplwi 11,0 -+ beq .LafterVMX9 -+ -+ /* Restore Altivec regs. -+ Use r5 as scratch since r6/r7 are live. */ -+ /* VRSAVE */ -+ lwz 5,324(1) -+ mfspr 5,256 /* VRSAVE reg is spr number 256 */ -+ -+ /* Vector regs */ -+ li 5,304 -+ lvx 31,5,1 -+ li 5,288 -+ lvx 30,5,1 -+ li 5,272 -+ lvx 29,5,1 -+ li 5,256 -+ lvx 28,5,1 -+ li 5,240 -+ lvx 27,5,1 -+ li 5,224 -+ lvx 26,5,1 -+ li 5,208 -+ lvx 25,5,1 -+ li 5,192 -+ lvx 24,5,1 -+ li 5,176 -+ lvx 23,5,1 -+ li 5,160 -+ lvx 22,5,1 -+ li 5,144 -+ lvx 21,5,1 -+ li 5,128 -+ lvx 20,5,1 -+.LafterVMX9: -+ -+ /* Restore FP regs */ -+ /* Floating-point regs */ -+ lfd 31,616(1) -+ lfd 30,608(1) -+ lfd 29,600(1) -+ lfd 28,592(1) -+ lfd 27,584(1) -+ lfd 26,576(1) -+ lfd 25,568(1) -+ lfd 24,560(1) -+ lfd 23,552(1) -+ lfd 22,544(1) -+ lfd 21,536(1) -+ lfd 20,528(1) -+ lfd 19,520(1) -+ lfd 18,512(1) -+ lfd 17,504(1) -+ lfd 16,496(1) -+ lfd 15,488(1) -+ lfd 14,480(1) -+ -+ /* restore int regs, including importantly r3 (two_words) */ -+ ld 31,472(1) -+ ld 30,464(1) -+ ld 29,456(1) -+ ld 28,448(1) -+ ld 27,440(1) -+ ld 26,432(1) -+ ld 25,424(1) -+ ld 24,416(1) -+ ld 23,408(1) -+ ld 22,400(1) -+ ld 21,392(1) -+ ld 20,384(1) -+ ld 19,376(1) -+ ld 18,368(1) -+ ld 17,360(1) -+ ld 16,352(1) -+ ld 15,344(1) -+ ld 14,336(1) -+ ld 13,328(1) -+ ld 3,104(1) -+ /* Stash return values */ -+ std 6,0(3) -+ std 7,8(3) -+ -+ /* restore lr & sp, and leave */ -+ ld 0,632(1) /* stack_size + 8 */ -+ mtcr 0 -+ ld 0,640(1) /* stack_size + 16 */ -+ mtlr 0 -+ addi 1,1,624 /* stack_size */ -+ blr -+#if _CALL_ELF == 2 -+ .size VG_(disp_run_translations),.-VG_(disp_run_translations) -+#endif -+ -+ -+/*----------------------------------------------------*/ -+/*--- Continuation points ---*/ -+/*----------------------------------------------------*/ -+ -+/* ------ Chain me to slow entry point ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_chain_me_to_slowEP) -+#if _CALL_ELF == 2 -+ .type VG_(disp_cp_chain_me_to_slowEP),@function -+ VG_(disp_cp_chain_me_to_slowEP): -+#else -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_chain_me_to_slowEP): -+ .quad .VG_(disp_cp_chain_me_to_slowEP),.TOC.@tocbase,0 -+ .previous -+#endif -+ .type .VG_(disp_cp_chain_me_to_slowEP),@function -+ .globl .VG_(disp_cp_chain_me_to_slowEP) -+.VG_(disp_cp_chain_me_to_slowEP): -+#if _CALL_ELF == 2 -+0: addis 2, 12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(disp_cp_chain_me_to_slowEP), .-VG_(disp_cp_chain_me_to_slowEP) -+#endif -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_S, RA) */ -+ li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP -+ mflr 7 -+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_slowEP -+ 4 = mtctr r30 -+ 4 = btctr -+ */ -+ subi 7,7,20+4+4 -+ b .postamble -+#if _CALL_ELF == 2 -+ .size VG_(disp_cp_chain_me_to_slowEP),.-VG_(disp_cp_chain_me_to_slowEP) -+#endif -+ -+/* ------ Chain me to fast entry point ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_chain_me_to_fastEP) -+#if _CALL_ELF == 2 -+ .type VG_(disp_cp_chain_me_to_fastEP),@function -+VG_(disp_cp_chain_me_to_fastEP): -+#else -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_chain_me_to_fastEP): -+ .quad .VG_(disp_cp_chain_me_to_fastEP),.TOC.@tocbase,0 -+ .previous -+#endif -+ .type .VG_(disp_cp_chain_me_to_fastEP),@function -+ .globl .VG_(disp_cp_chain_me_to_fastEP) -+.VG_(disp_cp_chain_me_to_fastEP): -+#if _CALL_ELF == 2 -+0: addis 2, 12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(disp_cp_chain_me_to_fastEP), .-VG_(disp_cp_chain_me_to_fastEP) -+#endif -+ /* We got called. The return address indicates -+ where the patching needs to happen. Collect -+ the return address and, exit back to C land, -+ handing the caller the pair (Chain_me_S, RA) */ -+ li 6, VG_TRC_CHAIN_ME_TO_FAST_EP -+ mflr 7 -+ /* 20 = imm64-fixed5 r30, disp_cp_chain_me_to_fastEP -+ 4 = mtctr r30 -+ 4 = btctr -+ */ -+ subi 7,7,20+4+4 -+ b .postamble -+#if _CALL_ELF == 2 -+ .size VG_(disp_cp_chain_me_to_fastEP),.-VG_(disp_cp_chain_me_to_fastEP) -+#endif -+ -+/* ------ Indirect but boring jump ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_xindir) -+#if _CALL_ELF == 2 -+ .type VG_(disp_cp_xindir),@function -+VG_(disp_cp_xindir): -+#else -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_xindir): -+ .quad .VG_(disp_cp_xindir),.TOC.@tocbase,0 -+ .previous -+#endif -+ .type .VG_(disp_cp_xindir),@function -+ .globl .VG_(disp_cp_xindir) -+.VG_(disp_cp_xindir): -+#if _CALL_ELF == 2 -+0: addis 2, 12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(disp_cp_xindir), .-VG_(disp_cp_xindir) -+#endif -+ /* Where are we going? */ -+ ld 3,OFFSET_ppc64_CIA(31) -+ -+ /* stats only */ -+ ld 5, .tocent__vgPlain_stats__n_xindirs_32@toc(2) -+ lwz 6,0(5) -+ addi 6,6,1 -+ stw 6,0(5) -+ -+ /* r5 = &VG_(tt_fast) */ -+ ld 5, .tocent__vgPlain_tt_fast@toc(2) /* &VG_(tt_fast) */ -+ -+ /* try a fast lookup in the translation cache */ -+ /* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry) -+ = ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */ -+ rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */ -+ sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */ -+ add 5,5,4 /* & VG_(tt_fast)[entry#] */ -+ ld 6,0(5) /* .guest */ -+ ld 7,8(5) /* .host */ -+ cmpd 3,6 -+ bne .fast_lookup_failed -+ -+ /* Found a match. Jump to .host. */ -+ mtctr 7 -+ bctr -+#if _CALL_ELF == 2 -+ .size VG_(disp_cp_xindir),.-VG_(disp_cp_xindir) -+#endif -+ -+.fast_lookup_failed: -+ /* stats only */ -+ ld 5, .tocent__vgPlain_stats__n_xindir_misses_32@toc(2) -+ lwz 6,0(5) -+ addi 6,6,1 -+ stw 6,0(5) -+ -+ li 6,VG_TRC_INNER_FASTMISS -+ li 7,0 -+ b .postamble -+ /*NOTREACHED*/ -+ -+/* ------ Assisted jump ------ */ -+.section ".text" -+ .align 2 -+ .globl VG_(disp_cp_xassisted) -+#if _CALL_ELF == 2 -+ .type VG_(disp_cp_xassisted),@function -+VG_(disp_cp_xassisted): -+#else -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_xassisted): -+ .quad .VG_(disp_cp_xassisted),.TOC.@tocbase,0 -+ .previous -+#endif -+#if _CALL_ELF == 2 -+0: addis 2, 12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(disp_cp_xassisted), .-VG_(disp_cp_xassisted) -+#endif -+ .type .VG_(disp_cp_xassisted),@function -+ .globl .VG_(disp_cp_xassisted) -+.VG_(disp_cp_xassisted): -+ /* r31 contains the TRC */ -+ mr 6,31 -+ li 7,0 -+ b .postamble -+#if _CALL_ELF == 2 -+ .size VG_(disp_cp_xassisted),.-VG_(disp_cp_xassisted) -+#endif -+ -+/* ------ Event check failed ------ */ -+ .section ".text" -+ .align 2 -+ .globl VG_(disp_cp_evcheck_fail) -+#if _CALL_ELF == 2 -+ .type VG_(disp_cp_evcheck_fail),@function -+VG_(disp_cp_evcheck_fail): -+#else -+ .section ".opd","aw" -+ .align 3 -+VG_(disp_cp_evcheck_fail): -+ .quad .VG_(disp_cp_evcheck_fail),.TOC.@tocbase,0 -+ .previous -+#endif -+#if _CALL_ELF == 2 -+0: addis 2, 12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(disp_cp_evcheck_fail), .-VG_(disp_cp_evcheck_fail) -+#endif -+ .type .VG_(disp_cp_evcheck_fail),@function -+ .globl .VG_(disp_cp_evcheck_fail) -+.VG_(disp_cp_evcheck_fail): -+ li 6,VG_TRC_INNER_COUNTERZERO -+ li 7,0 -+ b .postamble -+#if _CALL_ELF == 2 -+ .size VG_(disp_cp_evcheck_fail),.-VG_(disp_cp_evcheck_fail) -+#endif -+ -+.size .VG_(disp_run_translations), .-.VG_(disp_run_translations) -+ -+/* Let the linker know we don't need an executable stack */ -+.section .note.GNU-stack,"",@progbits -+ -+#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) -+ -+/*--------------------------------------------------------------------*/ -+/*--- end ---*/ -+/*--------------------------------------------------------------------*/ -Index: coregrind/m_libcsetjmp.c -=================================================================== ---- coregrind/m_libcsetjmp.c.orig -+++ coregrind/m_libcsetjmp.c -@@ -158,7 +158,6 @@ __asm__( - ".align 2" "\n" - ".p2align 4,,15" "\n" - ".globl VG_MINIMAL_SETJMP" "\n" -- - ".section \".opd\",\"aw\"" "\n" - ".align 3" "\n" - "VG_MINIMAL_SETJMP:" "\n" -@@ -267,9 +266,114 @@ __asm__( - "" "\n" - - ".previous" "\n" --".previous" "\n" - ); - -+#elif defined(VGP_ppc64le_linux) -+__asm__( -+".section \".toc\",\"aw\"" "\n" -+ -+".section \".text\"" "\n" -+".align 2" "\n" -+".p2align 4,,15" "\n" -+".globl VG_MINIMAL_SETJMP" "\n" -+".type VG_MINIMAL_SETJMP,@function" "\n" -+"VG_MINIMAL_SETJMP:" "\n" -+" .localentry VG_MINIMAL_SETJMP, .-VG_MINIMAL_SETJMP" "\n" -+" std 0, 0(3)" "\n" -+" std 1, 8(3)" "\n" -+" std 2, 16(3)" "\n" -+" std 3, 24(3)" "\n" -+" std 4, 32(3)" "\n" -+" std 5, 40(3)" "\n" -+" std 6, 48(3)" "\n" -+" std 7, 56(3)" "\n" -+" std 8, 64(3)" "\n" -+" std 9, 72(3)" "\n" -+" std 10, 80(3)" "\n" -+" std 11, 88(3)" "\n" -+" std 12, 96(3)" "\n" -+" std 13, 104(3)" "\n" -+" std 14, 112(3)" "\n" -+" std 15, 120(3)" "\n" -+" std 16, 128(3)" "\n" -+" std 17, 136(3)" "\n" -+" std 18, 144(3)" "\n" -+" std 19, 152(3)" "\n" -+" std 20, 160(3)" "\n" -+" std 21, 168(3)" "\n" -+" std 22, 176(3)" "\n" -+" std 23, 184(3)" "\n" -+" std 24, 192(3)" "\n" -+" std 25, 200(3)" "\n" -+" std 26, 208(3)" "\n" -+" std 27, 216(3)" "\n" -+" std 28, 224(3)" "\n" -+" std 29, 232(3)" "\n" -+" std 30, 240(3)" "\n" -+" std 31, 248(3)" "\n" -+// must use a caller-save register here as scratch, hence r4 -+" mflr 4" "\n" -+" std 4, 256(3)" "\n" -+" mfcr 4" "\n" -+" std 4, 264(3)" "\n" -+" li 3, 0" "\n" -+" blr" "\n" -+"" "\n" -+ -+ -+".globl VG_MINIMAL_LONGJMP" "\n" -+".type VG_MINIMAL_LONGJMP, @function" "\n" -+"VG_MINIMAL_LONGJMP:" "\n" -+" .localentry VG_MINIMAL_LONGJMP, .-VG_MINIMAL_LONGJMP" "\n" -+ // do r4 = 1 -+ // and park it in the restore slot for r3 (the ret reg) -+" li 4, 1" "\n" -+" std 4, 24(3)" "\n" -+ // restore everything except r3 -+ // then r3 last of all -+ // then blr -+" ld 0, 256(3)" "\n" -+" mtlr 0" "\n" -+" ld 0, 264(3)" "\n" -+" mtcr 0" "\n" -+" ld 0, 0(3)" "\n" -+" ld 1, 8(3)" "\n" -+" ld 2, 16(3)" "\n" -+ // r3 is done at the end -+" ld 4, 32(3)" "\n" -+" ld 5, 40(3)" "\n" -+" ld 6, 48(3)" "\n" -+" ld 7, 56(3)" "\n" -+" ld 8, 64(3)" "\n" -+" ld 9, 72(3)" "\n" -+" ld 10, 80(3)" "\n" -+" ld 11, 88(3)" "\n" -+" ld 12, 96(3)" "\n" -+" ld 13, 104(3)" "\n" -+" ld 14, 112(3)" "\n" -+" ld 15, 120(3)" "\n" -+" ld 16, 128(3)" "\n" -+" ld 17, 136(3)" "\n" -+" ld 18, 144(3)" "\n" -+" ld 19, 152(3)" "\n" -+" ld 20, 160(3)" "\n" -+" ld 21, 168(3)" "\n" -+" ld 22, 176(3)" "\n" -+" ld 23, 184(3)" "\n" -+" ld 24, 192(3)" "\n" -+" ld 25, 200(3)" "\n" -+" ld 26, 208(3)" "\n" -+" ld 27, 216(3)" "\n" -+" ld 28, 224(3)" "\n" -+" ld 29, 232(3)" "\n" -+" ld 30, 240(3)" "\n" -+" ld 31, 248(3)" "\n" -+" ld 3, 24(3)" "\n" -+" blr" "\n" -+"" "\n" -+ -+".previous" "\n" -+); - #endif /* VGP_ppc64be_linux */ - - -Index: coregrind/m_machine.c -=================================================================== ---- coregrind/m_machine.c.orig -+++ coregrind/m_machine.c -@@ -1154,9 +1154,13 @@ Bool VG_(machine_get_hwcaps)( void ) - VG_(machine_ppc64_has_VMX) = have_V ? 1 : 0; - - va = VexArchPPC64; -- // CARLL fixme: when the time comes, copy .endness setting code -- // from the VGA_mips32 case -+# if defined(VKI_LITTLE_ENDIAN) -+ vai.endness = VexEndnessLE; -+# elif defined(VKI_BIG_ENDIAN) - vai.endness = VexEndnessBE; -+# else -+ vai.endness = VexEndness_INVALID; -+# endif - - vai.hwcaps = 0; - if (have_V) vai.hwcaps |= VEX_HWCAPS_PPC64_V; -Index: coregrind/m_syscall.c -=================================================================== ---- coregrind/m_syscall.c.orig -+++ coregrind/m_syscall.c -@@ -422,6 +422,45 @@ asm( - " blr\n" - ); - -+#elif defined(VGP_ppc64le_linux) -+/* Due to the need to return 65 bits of result, this is completely -+ different from the ppc32 case. The single arg register points to a -+ 7-word block containing the syscall # and the 6 args. The syscall -+ result proper is put in [0] of the block, and %cr0.so is in the -+ bottom bit of [1]. */ -+extern void do_syscall_WRK ( ULong* argblock ); -+/* Little Endian supports ELF version 2. In the future, it may support -+ * other versions as well. -+ */ -+asm( -+".align 2\n" -+".globl do_syscall_WRK\n" -+".type do_syscall_WRK,@function\n" -+"do_syscall_WRK:\n" -+"#if _CALL_ELF == 2" "\n" -+"0: addis 2,12,.TOC.-0b@ha\n" -+" addi 2,2,.TOC.-0b@l\n" -+" .localentry do_syscall_WRK, .-do_syscall_WRK\n" -+"#endif" "\n" -+" std 3,-16(1)\n" /* stash arg */ -+" ld 8, 48(3)\n" /* sc arg 6 */ -+" ld 7, 40(3)\n" /* sc arg 5 */ -+" ld 6, 32(3)\n" /* sc arg 4 */ -+" ld 5, 24(3)\n" /* sc arg 3 */ -+" ld 4, 16(3)\n" /* sc arg 2 */ -+" ld 0, 0(3)\n" /* sc number */ -+" ld 3, 8(3)\n" /* sc arg 1 */ -+" sc\n" /* result in r3 and cr0.so */ -+" ld 5,-16(1)\n" /* reacquire argblock ptr (r5 is caller-save) */ -+" std 3,0(5)\n" /* argblock[0] = r3 */ -+" mfcr 3\n" -+" srwi 3,3,28\n" -+" andi. 3,3,1\n" -+" std 3,8(5)\n" /* argblock[1] = cr0.s0 & 1 */ -+" blr\n" -+" .size do_syscall_WRK, .-do_syscall_WRK\n" -+); -+ - #elif defined(VGP_arm_linux) - /* I think the conventions are: - args in r0 r1 r2 r3 r4 r5 -Index: coregrind/m_initimg/initimg-linux.c -=================================================================== ---- coregrind/m_initimg/initimg-linux.c.orig -+++ coregrind/m_initimg/initimg-linux.c -@@ -1055,6 +1055,9 @@ void VG_(ii_finalise_image)( IIFinaliseI - arch->vex.guest_GPR1 = iifii.initial_client_SP; - arch->vex.guest_GPR2 = iifii.initial_client_TOC; - arch->vex.guest_CIA = iifii.initial_client_IP; -+#if defined(VGP_ppc64le_linux) -+ arch->vex.guest_GPR12 = iifii.initial_client_IP; -+#endif - - # elif defined(VGP_arm_linux) - /* Zero out the initial state, and set up the simulated FPU in a -Index: coregrind/m_trampoline.S -=================================================================== ---- coregrind/m_trampoline.S.orig -+++ coregrind/m_trampoline.S -@@ -444,6 +444,12 @@ VG_(ppctoc_magic_redirect_return_stub): - /* this function is written using the "dotless" ABI convention */ - .align 2 - .globl VG_(ppc64_linux_REDIR_FOR_strlen) -+#if !defined VGP_ppc64be_linux || _CALL_ELF == 2 -+ /* Little Endian uses ELF version 2 */ -+ .type VG_(ppc64_linux_REDIR_FOR_strlen),@function -+VG_(ppc64_linux_REDIR_FOR_strlen): -+#else -+ /* Big Endian uses ELF version 1 */ - .section ".opd","aw" - .align 3 - VG_(ppc64_linux_REDIR_FOR_strlen): -@@ -454,6 +460,12 @@ VG_(ppc64_linux_REDIR_FOR_strlen): - .type VG_(ppc64_linux_REDIR_FOR_strlen), @function - - .L.VG_(ppc64_linux_REDIR_FOR_strlen): -+#endif -+#if _CALL_ELF == 2 -+0: addis 2,12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(ppc64_linux_REDIR_FOR_strlen), .-VG_(ppc64_linux_REDIR_FOR_strlen) -+#endif - mr 9,3 - lbz 0,0(3) - li 3,0 -@@ -467,6 +479,12 @@ VG_(ppc64_linux_REDIR_FOR_strlen): - cmpwi 7,0,0 - bne 7,.L01 - blr -+ -+#if !defined VGP_ppc64be_linux || _CALL_ELF == 2 -+ .size VG_(ppc64_linux_REDIR_FOR_strlen),.-VG_(ppc64_linux_REDIR_FOR_strlen) -+#else -+ .size VG_(ppc64_linux_REDIR_FOR_strlen),.-.L.VG_(ppc64_linux_REDIR_FOR_strlen) -+#endif - .long 0 - .byte 0,0,0,0,0,0,0,0 - .L0end: -@@ -474,6 +492,10 @@ VG_(ppc64_linux_REDIR_FOR_strlen): - /* this function is written using the "dotless" ABI convention */ - .align 2 - .globl VG_(ppc64_linux_REDIR_FOR_strchr) -+#if !defined VGP_ppc64be_linux || _CALL_ELF == 2 -+ .type VG_(ppc64_linux_REDIR_FOR_strchr),@function -+VG_(ppc64_linux_REDIR_FOR_strchr): -+#else - .section ".opd","aw" - .align 3 - VG_(ppc64_linux_REDIR_FOR_strchr): -@@ -482,8 +504,14 @@ VG_(ppc64_linux_REDIR_FOR_strchr): - .size VG_(ppc64_linux_REDIR_FOR_strchr), \ - .L1end-.L.VG_(ppc64_linux_REDIR_FOR_strchr) - .type VG_(ppc64_linux_REDIR_FOR_strchr),@function -- -+ - .L.VG_(ppc64_linux_REDIR_FOR_strchr): -+#endif -+#if _CALL_ELF == 2 -+0: addis 2,12,.TOC.-0b@ha -+ addi 2,2,.TOC.-0b@l -+ .localentry VG_(ppc64_linux_REDIR_FOR_strchr), .-VG_(ppc64_linux_REDIR_FOR_strchr) -+#endif - lbz 0,0(3) - rldicl 4,4,0,56 - cmpw 7,4,0 -@@ -491,6 +519,11 @@ VG_(ppc64_linux_REDIR_FOR_strchr): - cmpdi 7,0,0 - bne 7,.L18 - b .L14 -+#if !defined VGP_ppc64be_linux || _CALL_ELF == 2 -+ .size VG_(ppc64_linux_REDIR_FOR_strchr),.-VG_(ppc64_linux_REDIR_FOR_strchr) -+#else -+ .size VG_(ppc64_linux_REDIR_FOR_strchr),.-.L.VG_(ppc64_linux_REDIR_FOR_strchr) -+#endif - .L19: - beq 6,.L14 - .L18: -Index: coregrind/m_coredump/coredump-elf.c -=================================================================== ---- coregrind/m_coredump/coredump-elf.c.orig -+++ coregrind/m_coredump/coredump-elf.c -@@ -343,6 +343,27 @@ static void fill_prstatus(const ThreadSt - regs->dsisr = 0; - regs->result = 0; - -+#elif defined(VGP_ppc64le_linux) -+# define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n -+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7); -+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15); -+ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23); -+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31); -+# undef DO -+ -+ regs->nip = arch->vex.guest_CIA; -+ regs->msr = 0xf033; /* pretty arbitrary */ -+ regs->orig_gpr3 = arch->vex.guest_GPR3; -+ regs->ctr = arch->vex.guest_CTR; -+ regs->link = arch->vex.guest_LR; -+ regs->xer = LibVEX_GuestPPC64_get_XER( &((ThreadArchState*)arch)->vex ); -+ regs->ccr = LibVEX_GuestPPC64_get_CR( &((ThreadArchState*)arch)->vex ); -+ /* regs->mq = 0; */ -+ regs->trap = 0; -+ regs->dar = 0; /* should be fault address? */ -+ regs->dsisr = 0; -+ regs->result = 0; -+ - #elif defined(VGP_arm_linux) - regs->ARM_r0 = arch->vex.guest_R0; - regs->ARM_r1 = arch->vex.guest_R1; -Index: coregrind/m_main.c -=================================================================== ---- coregrind/m_main.c.orig -+++ coregrind/m_main.c -@@ -2608,6 +2608,10 @@ static void final_tidyup(ThreadId tid) - VG_(set_IP)(tid, __libc_freeres_wrapper); - # if defined(VGP_ppc64be_linux) - VG_(threads)[tid].arch.vex.guest_GPR2 = r2; -+# elif defined(VGP_ppc64le_linux) -+ /* setting GPR2 but not really needed, GPR12 is needed */ -+ VG_(threads)[tid].arch.vex.guest_GPR2 = __libc_freeres_wrapper; -+ VG_(threads)[tid].arch.vex.guest_GPR12 = __libc_freeres_wrapper; - # endif - /* mips-linux note: we need to set t9 */ - # if defined(VGP_mips32_linux) || defined(VGP_mips64_linux) -@@ -2847,6 +2851,51 @@ asm("\n" - "\tmtctr 14\n" - "\tbctrl\n" - "\tnop\n" -+ "\ttrap\n" -+); -+#elif defined(VGP_ppc64le_linux) -+/* Little Endian uses ELF version 2 but in the future may also -+ * support other ELF versions. -+ */ -+asm("\n" -+ "\t.align 2\n" -+ "\t.global _start\n" -+ "\t.type _start,@function\n" -+ "_start:\n" -+ "#if _CALL_ELF == 2 \n" -+ "0: addis 2,12,.TOC.-0b@ha\n" -+ " addi 2,2,.TOC.-0b@l\n" -+ " .localentry _start, .-_start\n" -+ "#endif \n" -+ /* set up the new stack in r16 */ -+ "\tlis 16, vgPlain_interim_stack@highest\n" -+ "\tori 16,16,vgPlain_interim_stack@higher\n" -+ "\tsldi 16,16,32\n" -+ "\toris 16,16,vgPlain_interim_stack@h\n" -+ "\tori 16,16,vgPlain_interim_stack@l\n" -+ "\txor 17,17,17\n" -+ "\tlis 17,("VG_STRINGIFY(VG_STACK_GUARD_SZB)" >> 16)\n" -+ "\tori 17,17,("VG_STRINGIFY(VG_STACK_GUARD_SZB)" & 0xFFFF)\n" -+ "\txor 18,18,18\n" -+ "\tlis 18,("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)" >> 16)\n" -+ "\tori 18,18,("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)" & 0xFFFF)\n" -+ "\tadd 16,17,16\n" -+ "\tadd 16,18,16\n" -+ "\trldicr 16,16,0,59\n" -+ /* now r16 = &vgPlain_interim_stack + VG_STACK_GUARD_SZB + -+ VG_STACK_ACTIVE_SZB rounded down to the nearest 16-byte -+ boundary. And r1 is the original SP. Set the SP to r16 and -+ call _start_in_C_linux, passing it the initial SP. */ -+ "\tmr 3,1\n" -+ "\tmr 1,16\n" -+ "\tlis 14, _start_in_C_linux@highest\n" -+ "\tori 14,14,_start_in_C_linux@higher\n" -+ "\tsldi 14,14,32\n" -+ "\toris 14,14,_start_in_C_linux@h\n" -+ "\tori 14,14,_start_in_C_linux@l\n" -+ "\tmtctr 14\n" -+ "\tbctrl\n" -+ "\tnop\n" - "\ttrap\n" - ); - #elif defined(VGP_s390x_linux) -Index: tests/arch_test.c -=================================================================== ---- tests/arch_test.c.orig -+++ tests/arch_test.c -@@ -27,6 +27,7 @@ char* all_archs[] = { - "amd64", - "ppc32", - "ppc64", -+ "ppc64le", - "arm", - "s390x", - "mips32", -@@ -54,6 +55,9 @@ static Bool go(char* arch) - if ( 0 == strcmp( arch, "ppc32" ) ) return True; - #endif - -+#elif defined(VGP_ppc64le_linux) -+ if ( 0 == strcmp( arch, "ppc64" ) ) return True; -+ - #elif defined(VGP_s390x_linux) - if ( 0 == strcmp( arch, "s390x" ) ) return True; - -Index: memcheck/mc_machine.c -=================================================================== ---- memcheck/mc_machine.c.orig -+++ memcheck/mc_machine.c -@@ -167,7 +167,11 @@ static Int get_otrack_shadow_offset_wrk - return GOF(GPRn); - by testing ox instead of o, and setting ox back 4 bytes when sz == 4. - */ -+#if defined(VGA_ppc64le) -+ Int ox = o; -+#else - Int ox = sz == 8 ? o : (o - 4); -+#endif - if (ox == GOF(GPR0)) return ox; - if (ox == GOF(GPR1)) return ox; - if (ox == GOF(GPR2)) return ox; -@@ -367,7 +371,11 @@ static Int get_otrack_shadow_offset_wrk - Int o = offset; - Int sz = szB; - tl_assert(sz > 0); -+#if defined(VGA_ppc64) - tl_assert(host_is_big_endian()); -+#elif defined(VGA_ppc64le) -+ tl_assert(host_is_little_endian()); -+#endif - - if (o == GOF(GPR0) && sz == 4) return o; - if (o == GOF(GPR1) && sz == 4) return o; -Index: helgrind/hg_main.c -=================================================================== ---- helgrind/hg_main.c.orig -+++ helgrind/hg_main.c -@@ -4425,6 +4425,7 @@ static Bool is_in_dynamic_linker_shared_ - if (VG_STREQ(soname, VG_U_LD_LINUX_SO_2)) return True; - if (VG_STREQ(soname, VG_U_LD_LINUX_X86_64_SO_2)) return True; - if (VG_STREQ(soname, VG_U_LD64_SO_1)) return True; -+ if (VG_STREQ(soname, VG_U_LD64_SO_2)) return True; - if (VG_STREQ(soname, VG_U_LD_SO_1)) return True; - # elif defined(VGO_darwin) - if (VG_STREQ(soname, VG_U_DYLD)) return True; -Index: include/pub_tool_debuginfo.h -=================================================================== ---- include/pub_tool_debuginfo.h.orig -+++ include/pub_tool_debuginfo.h -@@ -219,6 +219,7 @@ void VG_(DebugInfo_syms_getidx) ( const - Int idx, - /*OUT*/Addr* avma, - /*OUT*/Addr* tocptr, -+ /*OUT*/Addr* local_ep, - /*OUT*/UInt* size, - /*OUT*/HChar** pri_name, - /*OUT*/HChar*** sec_names, -Index: include/valgrind.h -=================================================================== ---- include/valgrind.h.orig -+++ include/valgrind.h -@@ -116,6 +116,7 @@ - #undef PLAT_amd64_linux - #undef PLAT_ppc32_linux - #undef PLAT_ppc64be_linux -+#undef PLAT_ppc64le_linux - #undef PLAT_arm_linux - #undef PLAT_arm64_linux - #undef PLAT_s390x_linux -@@ -141,6 +142,9 @@ - #elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF != 2 - /* Big Endian uses ELF version 1 */ - # define PLAT_ppc64be_linux 1 -+#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF == 2 -+/* Little Endian uses ELF version 2 */ -+# define PLAT_ppc64le_linux 1 - #elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__) - # define PLAT_arm_linux 1 - #elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__) -@@ -588,6 +592,82 @@ typedef - - #endif /* PLAT_ppc64be_linux */ - -+#if defined(PLAT_ppc64le_linux) -+ -+typedef -+ struct { -+ unsigned long long int nraddr; /* where's the code? */ -+ unsigned long long int r2; /* what tocptr do we need? */ -+ } -+ OrigFn; -+ -+#define __SPECIAL_INSTRUCTION_PREAMBLE \ -+ "rotldi 0,0,3 ; rotldi 0,0,13\n\t" \ -+ "rotldi 0,0,61 ; rotldi 0,0,51\n\t" -+ -+#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \ -+ _zzq_default, _zzq_request, \ -+ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \ -+ \ -+ __extension__ \ -+ ({ unsigned long long int _zzq_args[6]; \ -+ unsigned long long int _zzq_result; \ -+ unsigned long long int* _zzq_ptr; \ -+ _zzq_args[0] = (unsigned long long int)(_zzq_request); \ -+ _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \ -+ _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \ -+ _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \ -+ _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \ -+ _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \ -+ _zzq_ptr = _zzq_args; \ -+ __asm__ volatile("mr 3,%1\n\t" /*default*/ \ -+ "mr 4,%2\n\t" /*ptr*/ \ -+ __SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* %R3 = client_request ( %R4 ) */ \ -+ "or 1,1,1\n\t" \ -+ "mr %0,3" /*result*/ \ -+ : "=b" (_zzq_result) \ -+ : "b" (_zzq_default), "b" (_zzq_ptr) \ -+ : "cc", "memory", "r3", "r4"); \ -+ _zzq_result; \ -+ }) -+ -+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \ -+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \ -+ unsigned long long int __addr; \ -+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* %R3 = guest_NRADDR */ \ -+ "or 2,2,2\n\t" \ -+ "mr %0,3" \ -+ : "=b" (__addr) \ -+ : \ -+ : "cc", "memory", "r3" \ -+ ); \ -+ _zzq_orig->nraddr = __addr; \ -+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* %R3 = guest_NRADDR_GPR2 */ \ -+ "or 4,4,4\n\t" \ -+ "mr %0,3" \ -+ : "=b" (__addr) \ -+ : \ -+ : "cc", "memory", "r3" \ -+ ); \ -+ _zzq_orig->r2 = __addr; \ -+ } -+ -+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ __SPECIAL_INSTRUCTION_PREAMBLE \ -+ /* branch-and-link-to-noredir *%R12 */ \ -+ "or 3,3,3\n\t" -+ -+#define VALGRIND_VEX_INJECT_IR() \ -+ do { \ -+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \ -+ "or 5,5,5\n\t" \ -+ ); \ -+ } while (0) -+ -+#endif /* PLAT_ppc64le_linux */ - - /* ------------------------- arm-linux ------------------------- */ - -@@ -3082,6 +3162,562 @@ typedef - - #endif /* PLAT_ppc64be_linux */ - -+/* ------------------------- ppc64le-linux ----------------------- */ -+#if defined(PLAT_ppc64le_linux) -+ -+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */ -+ -+/* These regs are trashed by the hidden call. */ -+#define __CALLER_SAVED_REGS \ -+ "lr", "ctr", "xer", \ -+ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \ -+ "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ -+ "r11", "r12", "r13" -+ -+/* Macros to save and align the stack before making a function -+ call and restore it afterwards as gcc may not keep the stack -+ pointer aligned if it doesn't realise calls are being made -+ to other functions. */ -+ -+#define VALGRIND_ALIGN_STACK \ -+ "mr 28,1\n\t" \ -+ "rldicr 1,1,0,59\n\t" -+#define VALGRIND_RESTORE_STACK \ -+ "mr 1,28\n\t" -+ -+/* These CALL_FN_ macros assume that on ppc64-linux, sizeof(unsigned -+ long) == 8. */ -+ -+#define CALL_FN_W_v(lval, orig) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+0]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_W(lval, orig, arg1) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+1]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WW(lval, orig, arg1,arg2) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+2]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+3]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+4]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+5]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+6]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ _argvec[2+6] = (unsigned long)arg6; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+7]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ _argvec[2+6] = (unsigned long)arg6; \ -+ _argvec[2+7] = (unsigned long)arg7; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \ -+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+8]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ _argvec[2+6] = (unsigned long)arg6; \ -+ _argvec[2+7] = (unsigned long)arg7; \ -+ _argvec[2+8] = (unsigned long)arg8; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \ -+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \ -+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+9]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ _argvec[2+6] = (unsigned long)arg6; \ -+ _argvec[2+7] = (unsigned long)arg7; \ -+ _argvec[2+8] = (unsigned long)arg8; \ -+ _argvec[2+9] = (unsigned long)arg9; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "addi 1,1,-128\n\t" /* expand stack frame */ \ -+ /* arg9 */ \ -+ "ld 3,72(12)\n\t" \ -+ "std 3,96(1)\n\t" \ -+ /* args1-8 */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \ -+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \ -+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9,arg10) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+10]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ _argvec[2+6] = (unsigned long)arg6; \ -+ _argvec[2+7] = (unsigned long)arg7; \ -+ _argvec[2+8] = (unsigned long)arg8; \ -+ _argvec[2+9] = (unsigned long)arg9; \ -+ _argvec[2+10] = (unsigned long)arg10; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "addi 1,1,-128\n\t" /* expand stack frame */ \ -+ /* arg10 */ \ -+ "ld 3,80(12)\n\t" \ -+ "std 3,104(1)\n\t" \ -+ /* arg9 */ \ -+ "ld 3,72(12)\n\t" \ -+ "std 3,96(1)\n\t" \ -+ /* args1-8 */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \ -+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \ -+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9,arg10,arg11) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+11]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ _argvec[2+6] = (unsigned long)arg6; \ -+ _argvec[2+7] = (unsigned long)arg7; \ -+ _argvec[2+8] = (unsigned long)arg8; \ -+ _argvec[2+9] = (unsigned long)arg9; \ -+ _argvec[2+10] = (unsigned long)arg10; \ -+ _argvec[2+11] = (unsigned long)arg11; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "addi 1,1,-144\n\t" /* expand stack frame */ \ -+ /* arg11 */ \ -+ "ld 3,88(12)\n\t" \ -+ "std 3,112(1)\n\t" \ -+ /* arg10 */ \ -+ "ld 3,80(12)\n\t" \ -+ "std 3,104(1)\n\t" \ -+ /* arg9 */ \ -+ "ld 3,72(12)\n\t" \ -+ "std 3,96(1)\n\t" \ -+ /* args1-8 */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \ -+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \ -+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \ -+ arg7,arg8,arg9,arg10,arg11,arg12) \ -+ do { \ -+ volatile OrigFn _orig = (orig); \ -+ volatile unsigned long _argvec[3+12]; \ -+ volatile unsigned long _res; \ -+ /* _argvec[0] holds current r2 across the call */ \ -+ _argvec[1] = (unsigned long)_orig.r2; \ -+ _argvec[2] = (unsigned long)_orig.nraddr; \ -+ _argvec[2+1] = (unsigned long)arg1; \ -+ _argvec[2+2] = (unsigned long)arg2; \ -+ _argvec[2+3] = (unsigned long)arg3; \ -+ _argvec[2+4] = (unsigned long)arg4; \ -+ _argvec[2+5] = (unsigned long)arg5; \ -+ _argvec[2+6] = (unsigned long)arg6; \ -+ _argvec[2+7] = (unsigned long)arg7; \ -+ _argvec[2+8] = (unsigned long)arg8; \ -+ _argvec[2+9] = (unsigned long)arg9; \ -+ _argvec[2+10] = (unsigned long)arg10; \ -+ _argvec[2+11] = (unsigned long)arg11; \ -+ _argvec[2+12] = (unsigned long)arg12; \ -+ __asm__ volatile( \ -+ VALGRIND_ALIGN_STACK \ -+ "mr 12,%1\n\t" \ -+ "std 2,-16(12)\n\t" /* save tocptr */ \ -+ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \ -+ "addi 1,1,-144\n\t" /* expand stack frame */ \ -+ /* arg12 */ \ -+ "ld 3,96(12)\n\t" \ -+ "std 3,120(1)\n\t" \ -+ /* arg11 */ \ -+ "ld 3,88(12)\n\t" \ -+ "std 3,112(1)\n\t" \ -+ /* arg10 */ \ -+ "ld 3,80(12)\n\t" \ -+ "std 3,104(1)\n\t" \ -+ /* arg9 */ \ -+ "ld 3,72(12)\n\t" \ -+ "std 3,96(1)\n\t" \ -+ /* args1-8 */ \ -+ "ld 3, 8(12)\n\t" /* arg1->r3 */ \ -+ "ld 4, 16(12)\n\t" /* arg2->r4 */ \ -+ "ld 5, 24(12)\n\t" /* arg3->r5 */ \ -+ "ld 6, 32(12)\n\t" /* arg4->r6 */ \ -+ "ld 7, 40(12)\n\t" /* arg5->r7 */ \ -+ "ld 8, 48(12)\n\t" /* arg6->r8 */ \ -+ "ld 9, 56(12)\n\t" /* arg7->r9 */ \ -+ "ld 10, 64(12)\n\t" /* arg8->r10 */ \ -+ "ld 12, 0(12)\n\t" /* target->r12 */ \ -+ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \ -+ "mr 12,%1\n\t" \ -+ "mr %0,3\n\t" \ -+ "ld 2,-16(12)\n\t" /* restore tocptr */ \ -+ VALGRIND_RESTORE_STACK \ -+ : /*out*/ "=r" (_res) \ -+ : /*in*/ "r" (&_argvec[2]) \ -+ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \ -+ ); \ -+ lval = (__typeof__(lval)) _res; \ -+ } while (0) -+ -+#endif /* PLAT_ppc64le_linux */ -+ - /* ------------------------- arm-linux ------------------------- */ - - #if defined(PLAT_arm_linux) -@@ -5630,6 +6266,7 @@ VALGRIND_PRINTF_BACKTRACE(const char *fo - #undef PLAT_amd64_linux - #undef PLAT_ppc32_linux - #undef PLAT_ppc64be_linux -+#undef PLAT_ppc64le_linux - #undef PLAT_arm_linux - #undef PLAT_s390x_linux - #undef PLAT_mips32_linux -Index: include/pub_tool_redir.h -=================================================================== ---- include/pub_tool_redir.h.orig -+++ include/pub_tool_redir.h -@@ -284,6 +284,7 @@ - - #define VG_Z_LD64_SO_1 ld64ZdsoZd1 // ld64.so.1 - #define VG_U_LD64_SO_1 "ld64.so.1" -+#define VG_U_LD64_SO_2 "ld64.so.2" // PPC LE loader - - #define VG_Z_LD_SO_1 ldZdsoZd1 // ld.so.1 - #define VG_U_LD_SO_1 "ld.so.1" -Index: include/vki/vki-ppc64-linux.h -=================================================================== ---- include/vki/vki-ppc64-linux.h.orig -+++ include/vki/vki-ppc64-linux.h -@@ -31,9 +31,11 @@ - #ifndef __VKI_PPC64_LINUX_H - #define __VKI_PPC64_LINUX_H - --// ppc64 is big-endian. -+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) - #define VKI_BIG_ENDIAN 1 -- -+#elif defined(VGP_ppc64le_linux) -+#define VKI_LITTLE_ENDIAN 1 -+#endif - //---------------------------------------------------------------------- - // From linux-2.6.13/include/asm-ppc64/types.h - //---------------------------------------------------------------------- diff --git a/r14240.diff b/r14240.diff deleted file mode 100644 index b494d11..0000000 --- a/r14240.diff +++ /dev/null @@ -1,25958 +0,0 @@ ------------------------------------------------------------------------- -r14240 | carll | 2014-08-08 01:49:27 +0200 (Fr, 08. Aug 2014) | 18 Zeilen - -This commit is for Bugzilla 334836. The Bugzilla contains patch 3 of 3 -to add PPC64 LE support. The other two patches can be found in Bugzillas -334384 and 334834. Note, there are no VEX changes in this patch. - - -PP64 Little Endian test case fixes. - -This patch adds new LE and BE expect files where needed. In other -cases, the test was fixed to run correctly on LE and BE using based on -testing to see which platform is being used. - -Where practical, the test cases have been changed so that the output -produced for BE and LE will be identical. The test cases that require -a major rewrite to make the output identical for BE and LE simply -had an additional expect file added. - -Signed-off-by: Carl Love - ------------------------------------------------------------------------- -Index: helgrind/tests/tc11_XCHG.c -=================================================================== ---- helgrind/tests/tc11_XCHG.c.orig -+++ helgrind/tests/tc11_XCHG.c -@@ -14,7 +14,7 @@ - #undef PLAT_x86_linux - #undef PLAT_amd64_linux - #undef PLAT_ppc32_linux --#undef PLAT_ppc64_linux -+#undef PLAT_ppc64be_linux - #undef PLAT_arm_linux - #undef PLAT_s390x_linux - #undef PLAT_mips32_linux -Index: coregrind/launcher-darwin.c -=================================================================== ---- coregrind/launcher-darwin.c.orig -+++ coregrind/launcher-darwin.c -@@ -64,7 +64,6 @@ static struct { - { CPU_TYPE_ARM, "arm", "arm" }, - { CPU_TYPE_POWERPC, "ppc", "ppc32" }, - { CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" }, -- { CPU_TYPE_POWERPC64LE, "ppc64le", "ppc64le" }, - }; - static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]); - -Index: none/tests/ppc64/lsw.vgtest -=================================================================== ---- none/tests/ppc64/lsw.vgtest.orig -+++ none/tests/ppc64/lsw.vgtest -@@ -1 +1,2 @@ -+prereq: ../../../tests/is_ppc64_BE - prog: lsw -Index: none/tests/ppc64/jm-vmx.stdout.exp-LE -=================================================================== ---- /dev/null -+++ none/tests/ppc64/jm-vmx.stdout.exp-LE -@@ -0,0 +1,3614 @@ -+PPC altivec integer arith insns with three args: -+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmhaddshs: => 010403160538076a09ad0c000f970f9a (00000000) -+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhaddshs: => f1f4f406f628f85afa9dfcf00087008a (00000000) -+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000) -+ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000) -+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000) -+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000) -+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmhaddshs: => 028d042605cf078909520b2c0e0f0e11 (00000000) -+ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhaddshs: => f37df516f6bff879fa42fc1cfeffff01 (00000000) -+ -+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmhraddshs: => 010403160538076b09ad0c000f980f9a (00000000) -+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhraddshs: => f1f4f406f628f85bfa9dfcf00088008a (00000000) -+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000) -+ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000) -+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000) -+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000) -+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmhraddshs: => 028d042605d0078909530b2c0e0f0e11 (00000000) -+ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmhraddshs: => f37df516f6c0f879fa43fc1cfeffff01 (00000000) -+ -+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmladduhm: => 05061b14412a7748bd6e139c7ab6b2f0 (00000000) -+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmladduhm: => f5f60c04321a6838ae5e048c6ba6a3e0 (00000000) -+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000) -+ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000) -+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000) -+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000) -+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmladduhm: => 89c62394cd6a8748512e2b1c14161010 (00000000) -+ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmladduhm: => 7ab61484be5a7838421e1c0c05060100 (00000000) -+ -+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumubm: => 01020322050607b6090a0cca0e0d1121 (00000000) -+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumubm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000) -+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000) -+ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000) -+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000) -+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000) -+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumubm: => 010599e20509bc76090ddf8a0e10fe21 (00000000) -+ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumubm: => f1f68ad2f5faad66f9fed07aff01ef11 (00000000) -+ -+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhm: => 010c1f180550b36c09d5c8000f981f99 (00000000) -+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhm: => f1fd1008f641a45cfac6b8f000891089 (00000000) -+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) -+ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000) -+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) -+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000) -+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhm: => ce24ac58e1874facf52a73400a071619 (00000000) -+ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhm: => bf159d48d278409ce61b6430faf80709 (00000000) -+ -+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshs: => 010c1f180550b36c09d5c8000f981f99 (00000000) -+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshs: => f1fd1008f641a45cfac6b8f000891089 (00000000) -+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) -+ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) -+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) -+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) -+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshs: => 0258ac5805ab4fac093e73400e0f1619 (00000000) -+ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshs: => f3499d48f69c409cfa2f6430ff000709 (00000000) -+ -+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhs: => 010c1f180550b36c09d5c8000f981f99 (00000000) -+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhs: => f1fd1008f641a45cfac6b8f0ffffffff (00000000) -+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) -+ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000) -+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000) -+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000) -+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000) -+ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000) -+ -+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsummbm: => 01020322050607b6090a0cca0e0d1121 (00000000) -+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsummbm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000) -+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsummbm: => 01020c8205062016090a342a0e0d45a1 (00000000) -+ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsummbm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000) -+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsummbm: => 0102028205060616090a0a2a0e0d0da1 (00000000) -+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsummbm: => f1f2f372f5f6f706f9fafb1afefdfe91 (00000000) -+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsummbm: => 0101cfe20505e2760909f58a0e0d0621 (00000000) -+ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsummbm: => f1f2c0d2f5f6d366f9fae67afefdf711 (00000000) -+ -+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshm: => 010c1f180550b36c09d5c8000f981f99 (00000000) -+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshm: => f1fd1008f641a45cfac6b8f000891089 (00000000) -+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) -+ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) -+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000) -+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000) -+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmsumshm: => 0258ac5805ab4fac093e73400e0f1619 (00000000) -+ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmsumshm: => f3499d48f69c409cfa2f6430ff000709 (00000000) -+ -+PPC altivec integer logical insns with three args: -+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000) -+ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000) -+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000) -+ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000) -+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000) -+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000) -+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000) -+ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000) -+ -+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) -+ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) -+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) -+ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) -+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) -+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000) -+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) -+ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000) -+ -+PPC altivec integer arith insns with two args: -+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vaddubm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vaddubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) -+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) -+ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddubm: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000) -+ -+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vadduhm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vadduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) -+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) -+ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduhm: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000) -+ -+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vadduwm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vadduwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) -+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) -+ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduwm: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000) -+ -+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vaddubs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vaddubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000) -+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000) -+ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddubs: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vadduhs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vadduhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) -+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) -+ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduhs: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vadduws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vadduws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vadduws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) -+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000) -+ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vadduws: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vaddsbs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) -+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000) -+ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddsbs: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000) -+ -+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vaddshs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) -+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000) -+ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddshs: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000) -+ -+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vaddsws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vaddsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) -+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000) -+ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddsws: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000) -+ -+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vaddcuw: => 00000000 00000000 00000000 00000000 (00000000) -+ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000) -+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000) -+ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vaddcuw: => 00000001 00000001 00000001 00000001 (00000000) -+ -+ vsububm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsububm: => 00000000 00000000 00000000 00000000 (00000000) -+ vsububm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsububm: => 10101010 10101010 10101010 10101010 (00000000) -+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsububm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsububm: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuhm: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000) -+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubuhm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuwm: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000) -+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubuwm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsububs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsububs: => 00000000 00000000 00000000 00000000 (00000000) -+ vsububs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsububs: => 00000000 00000000 00000000 00000000 (00000000) -+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsububs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsububs: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubuhs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubuws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubuws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubuws: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubsbs: => 10101010 10101010 10101010 10101010 (00000000) -+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubsbs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubshs: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000) -+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubshs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubshs: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubsws: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000) -+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubsws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubsws: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000) -+ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubcuw: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000) -+ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000) -+ -+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmuloub: => 00040010 00240040 00640090 00a900e1 (00000000) -+ vmuloub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000) -+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000) -+ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmuloub: => e4c4e890 ec64f040 f424f810 fa09fe01 (00000000) -+ -+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmulouh: => 00091810 00317040 007a0890 00c5a4e1 (00000000) -+ vmulouh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000) -+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000) -+ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulouh: => e8792090 f0308040 f8082010 fdff0201 (00000000) -+ -+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmulosb: => 00040010 00240040 00640090 00a900e1 (00000000) -+ vmulosb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000) -+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000) -+ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulosb: => 00c40090 00640040 00240010 00090001 (00000000) -+ -+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmulosh: => 00091810 00317040 007a0890 00c5a4e1 (00000000) -+ vmulosh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000) -+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000) -+ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulosh: => 00912090 00408040 00102010 00010201 (00000000) -+ -+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmuleub: => 00010009 00190031 00510079 00c400c4 (00000000) -+ vmuleub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000) -+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000) -+ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmuleub: => e2e1e6a9 ea79ee51 f231f619 fc04fc04 (00000000) -+ -+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmuleuh: => 00010404 00193c24 0051b464 00c56ca9 (00000000) -+ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000) -+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000) -+ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmuleuh: => e4a988c4 ec50c864 f4184824 fdfb0609 (00000000) -+ -+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmulesb: => 00010009 00190031 00510079 00c400c4 (00000000) -+ vmulesb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000) -+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000) -+ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulesb: => 00e100a9 00790051 00310019 00040004 (00000000) -+ -+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmulesh: => 00010404 00193c24 0051b464 00c56ca9 (00000000) -+ vmulesh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000) -+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000) -+ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmulesh: => 00c588c4 0064c864 00244824 00010609 (00000000) -+ -+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsumsws: => 1e21262b 00000000 00000000 00000000 (00000000) -+ vsumsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsumsws: => 0f12171b 00000000 00000000 00000000 (00000000) -+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsumsws: => e1e4e9eb 00000000 00000000 00000000 (00000000) -+ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsumsws: => d2d5dadb 00000000 00000000 00000000 (00000000) -+ -+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsum2sws: => 070a0d10 00000000 20212427 00000000 (00000000) -+ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum2sws: => f7fafe00 00000000 11121517 00000000 (00000000) -+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsum2sws: => e8ebeef0 00000000 02030607 00000000 (00000000) -+ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum2sws: => d9dcdfe0 00000000 f2f3f6f7 00000000 (00000000) -+ -+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsum4ubs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000) -+ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum4ubs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000) -+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsum4ubs: => 010206ce 05060ae2 090a0ef6 0e0d1207 (00000000) -+ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum4ubs: => f1f2f7be f5f6fbd2 f9faffe6 fefe02f7 (00000000) -+ -+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsum4sbs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000) -+ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum4sbs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000) -+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsum4sbs: => 010202ce 050606e2 090a0af6 0e0d0e07 (00000000) -+ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum4sbs: => f1f2f3be f5f6f7d2 f9fafbe6 fefdfef7 (00000000) -+ -+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsum4shs: => 0102070a 05061316 090a1f22 0e0d2a2b (00000000) -+ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum4shs: => f1f2f7fa f5f70406 f9fb1012 fefe1b1b (00000000) -+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsum4shs: => 0101e8ea 0505f4f6 090a0102 0e0d0c0b (00000000) -+ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsum4shs: => f1f2d9da f5f6e5e6 f9faf1f2 fefdfcfb (00000000) -+ -+ vavgub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vavgub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vavgub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) -+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) -+ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vavguh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vavguh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vavguh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) -+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) -+ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavguh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vavguw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vavguw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vavguw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) -+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000) -+ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavguw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vavgsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vavgsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000) -+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000) -+ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vavgsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vavgsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000) -+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000) -+ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vavgsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vavgsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000) -+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000) -+ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vavgsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmaxub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmaxuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmaxuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmaxsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vminub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vminuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vminuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vminsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vminsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vminsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vminsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vminsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vminsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vminsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+PPC altivec integer logical insns with two args: -+ vand: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vand: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vand: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vor: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ vxor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vxor: => 00000000 00000000 00000000 00000000 (00000000) -+ vxor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vxor: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vandc: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vandc: => 00000000 00000000 00000000 00000000 (00000000) -+ vandc: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vandc: => 00000000 00000000 00000000 00000000 (00000000) -+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vandc: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vandc: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vnor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vnor: => fefdfcfb faf9f8f7 f6f5f4f3 f1f2f1f0 (00000000) -+ vnor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000) -+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000) -+ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000) -+ -+ vrlb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000) -+ vrlb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000) -+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000) -+ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000) -+ -+ vrlh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000) -+ vrlh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000) -+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000) -+ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000) -+ -+ vrlw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vrlw: => 10203040 06070805 a0b0c090 87078706 (00000000) -+ vrlw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vrlw: => 30401020 08050607 c090a0b0 87068707 (00000000) -+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vrlw: => 1f2f3f4f f6f7f8f5 afbfcf9f ff7fff7e (00000000) -+ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vrlw: => 3f4f1f2f f8f5f6f7 cf9fafbf ff7eff7f (00000000) -+ -+ vslb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000) -+ vslb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000) -+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000) -+ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000) -+ -+ vslh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000) -+ vslh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslh: => 04083040 41800800 2800c000 a0008000 (00000000) -+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000) -+ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000) -+ -+ vslw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vslw: => 10203040 06070800 a0b0c000 87078000 (00000000) -+ vslw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslw: => 30400000 08000000 c0000000 80000000 (00000000) -+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vslw: => 1f2f3f40 f6f7f800 afbfc000 ff7f8000 (00000000) -+ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslw: => 3f400000 f8000000 c0000000 80000000 (00000000) -+ -+ vsrb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsrb: => 00000000 00000008 04020100 00000000 (00000000) -+ vsrb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrb: => 00000000 00000008 04020100 00000000 (00000000) -+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000) -+ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000) -+ -+ vsrh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsrh: => 00400030 00140007 00020000 00000000 (00000000) -+ vsrh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrh: => 00400030 00140007 00020000 00000000 (00000000) -+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000) -+ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000) -+ -+ vsrw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsrw: => 00102030 00050607 000090a0 00001c1a (00000000) -+ vsrw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrw: => 00000010 00000005 00000000 00000000 (00000000) -+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsrw: => 0f1f2f3f 00f5f6f7 000f9faf 0001fdfb (00000000) -+ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrw: => 00000f1f 000000f5 0000000f 00000001 (00000000) -+ -+ vsrab: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsrab: => 00000000 00000008 04020100 00000000 (00000000) -+ vsrab: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrab: => 00000000 00000008 04020100 00000000 (00000000) -+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000) -+ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000) -+ -+ vsrah: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsrah: => 00400030 00140007 00020000 00000000 (00000000) -+ vsrah: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrah: => 00400030 00140007 00020000 00000000 (00000000) -+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000) -+ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000) -+ -+ vsraw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsraw: => 00102030 00050607 000090a0 00001c1a (00000000) -+ vsraw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsraw: => 00000010 00000005 00000000 00000000 (00000000) -+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsraw: => ff1f2f3f fff5f6f7 ffff9faf fffffdfb (00000000) -+ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsraw: => ffffff1f fffffff5 ffffffff ffffffff (00000000) -+ -+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkuhum: => 06080204 0d0f0a0c 06080204 0d0f0a0c (00000000) -+ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuhum: => f6f8f2f4 fdfffafc 06080204 0d0f0a0c (00000000) -+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkuhum: => 06080204 0d0f0a0c f6f8f2f4 fdfffafc (00000000) -+ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuhum: => f6f8f2f4 fdfffafc f6f8f2f4 fdfffafc (00000000) -+ -+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkuwum: => 07080304 0e0f0b0c 07080304 0e0f0b0c (00000000) -+ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuwum: => f7f8f3f4 fefffbfc 07080304 0e0f0b0c (00000000) -+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkuwum: => 07080304 0e0f0b0c f7f8f3f4 fefffbfc (00000000) -+ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuwum: => f7f8f3f4 fefffbfc f7f8f3f4 fefffbfc (00000000) -+ -+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkshus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkshus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkshus: => 00000000 00000000 ffffffff ffffffff (00000000) -+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkshus: => ffffffff ffffffff 00000000 00000000 (00000000) -+ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkshus: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkswus: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vpkswus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkswus: => 00000000 00000000 ffffffff ffffffff (00000000) -+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkswus: => ffffffff ffffffff 00000000 00000000 (00000000) -+ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkswus: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkshss: => 7f7f7f7f 7f7f7f7f 7f7f7f7f 7f7f7f7f (00000000) -+ vpkshss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkshss: => 80808080 80808080 7f7f7f7f 7f7f7f7f (00000000) -+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkshss: => 7f7f7f7f 7f7f7f7f 80808080 80808080 (00000000) -+ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkshss: => 80808080 80808080 80808080 80808080 (00000000) -+ -+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkswss: => 7fff7fff 7fff7fff 7fff7fff 7fff7fff (00000000) -+ vpkswss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkswss: => 80008000 80008000 7fff7fff 7fff7fff (00000000) -+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkswss: => 7fff7fff 7fff7fff 80008000 80008000 (00000000) -+ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkswss: => 80008000 80008000 80008000 80008000 (00000000) -+ -+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vpkpx: => 80018000 04218421 80018000 04218421 (00000000) -+ vpkpx: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkpx: => fbdffbde 7fffffff 80018000 04218421 (00000000) -+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vpkpx: => 80018000 04218421 fbdffbde 7fffffff (00000000) -+ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vpkpx: => fbdffbde 7fffffff fbdffbde 7fffffff (00000000) -+ -+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmrghb: => 0b0b0c0c 09090a0a 0e0e0f0f 0e0e0d0d (00000000) -+ vmrghb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrghb: => 0bfb0cfc 09f90afa 0efe0fff 0efe0dfd (00000000) -+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmrghb: => fb0bfc0c f909fa0a fe0eff0f fe0efd0d (00000000) -+ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrghb: => fbfbfcfc f9f9fafa fefeffff fefefdfd (00000000) -+ -+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmrghh: => 0b0c0b0c 090a090a 0e0f0e0f 0e0d0e0d (00000000) -+ vmrghh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrghh: => 0b0cfbfc 090af9fa 0e0ffeff 0e0dfefd (00000000) -+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmrghh: => fbfc0b0c f9fa090a feff0e0f fefd0e0d (00000000) -+ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrghh: => fbfcfbfc f9faf9fa fefffeff fefdfefd (00000000) -+ -+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmrghw: => 090a0b0c 090a0b0c 0e0d0e0f 0e0d0e0f (00000000) -+ vmrghw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrghw: => f9fafbfc 090a0b0c fefdfeff 0e0d0e0f (00000000) -+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmrghw: => 090a0b0c f9fafbfc 0e0d0e0f fefdfeff (00000000) -+ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrghw: => f9fafbfc f9fafbfc fefdfeff fefdfeff (00000000) -+ -+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmrglb: => 03030404 01010202 07070808 05050606 (00000000) -+ vmrglb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrglb: => 03f304f4 01f102f2 07f708f8 05f506f6 (00000000) -+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmrglb: => f303f404 f101f202 f707f808 f505f606 (00000000) -+ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrglb: => f3f3f4f4 f1f1f2f2 f7f7f8f8 f5f5f6f6 (00000000) -+ -+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmrglh: => 03040304 01020102 07080708 05060506 (00000000) -+ vmrglh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrglh: => 0304f3f4 0102f1f2 0708f7f8 0506f5f6 (00000000) -+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmrglh: => f3f40304 f1f20102 f7f80708 f5f60506 (00000000) -+ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrglh: => f3f4f3f4 f1f2f1f2 f7f8f7f8 f5f6f5f6 (00000000) -+ -+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vmrglw: => 01020304 01020304 05060708 05060708 (00000000) -+ vmrglw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrglw: => f1f2f3f4 01020304 f5f6f7f8 05060708 (00000000) -+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vmrglw: => 01020304 f1f2f3f4 05060708 f5f6f7f8 (00000000) -+ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vmrglw: => f1f2f3f4 f1f2f3f4 f5f6f7f8 f5f6f7f8 (00000000) -+ -+ vslo: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vslo: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vslo: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslo: => 00000000 00000000 00000000 03040000 (00000000) -+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vslo: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vslo: => 00000000 00000000 00000000 f3f40000 (00000000) -+ -+ vsro: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vsro: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vsro: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsro: => 00000e0d 00000000 00000000 00000000 (00000000) -+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vsro: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vsro: => 0000fefd 00000000 00000000 00000000 (00000000) -+ -+PPC altivec integer logical insns with one arg: -+ vupkhsb: 01020304 05060708 090a0b0c 0e0d0e0f -+ vupkhsb: => 000b000c 0009000a 000e000f 000e000d (00000000) -+ vupkhsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff -+ vupkhsb: => fffbfffc fff9fffa fffeffff fffefffd (00000000) -+ -+ vupkhsh: 01020304 05060708 090a0b0c 0e0d0e0f -+ vupkhsh: => 00000b0c 0000090a 00000e0f 00000e0d (00000000) -+ vupkhsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff -+ vupkhsh: => fffffbfc fffff9fa fffffeff fffffefd (00000000) -+ -+ vupkhpx: 01020304 05060708 090a0b0c 0e0d0e0f -+ vupkhpx: => 0002180c 0002080a 0003100f 0003100d (00000000) -+ vupkhpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff -+ vupkhpx: => ff1e1f1c ff1e0f1a ff1f171f ff1f171d (00000000) -+ -+ vupklsb: 01020304 05060708 090a0b0c 0e0d0e0f -+ vupklsb: => 00030004 00010002 00070008 00050006 (00000000) -+ vupklsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff -+ vupklsb: => fff3fff4 fff1fff2 fff7fff8 fff5fff6 (00000000) -+ -+ vupklsh: 01020304 05060708 090a0b0c 0e0d0e0f -+ vupklsh: => 00000304 00000102 00000708 00000506 (00000000) -+ vupklsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff -+ vupklsh: => fffff3f4 fffff1f2 fffff7f8 fffff5f6 (00000000) -+ -+ vupklpx: 01020304 05060708 090a0b0c 0e0d0e0f -+ vupklpx: => 00001804 00000802 00011808 00010806 (00000000) -+ vupklpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff -+ vupklpx: => ff1c1f14 ff1c0f12 ff1d1f18 ff1d0f16 (00000000) -+ -+Altivec integer compare insns: -+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtub: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuh: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuw: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsb: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsh: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsw: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+Altivec integer compare insns with flags update: -+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtub.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuh.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtuw.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsb.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsh.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsw.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ -+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ -+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f -+ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff -+ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ -+Altivec integer special insns: -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000 -+ vsl: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101 -+ vsl: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000) -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202 -+ vsl: => 04080c10 14181c20 24282c30 3834383c (00000000) -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303 -+ vsl: => 08101820 28303840 48505860 70687078 (00000000) -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404 -+ vsl: => 10203040 50607080 90a0b0c0 e0d0e0f0 (00000000) -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505 -+ vsl: => 20406080 a0c0e100 21416180 c1a1c1e1 (00000000) -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606 -+ vsl: => 4080c100 4181c200 4282c301 834383c2 (00000000) -+ vsl: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707 -+ vsl: => 81018200 83038400 85058602 06870784 (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000 -+ vsl: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101 -+ vsl: => e3e5e7e8 ebedeff1 f3f5f7f9 fdfbfdff (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202 -+ vsl: => c7cbcfd0 d7dbdfe3 e7ebeff3 fbf7fbff (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303 -+ vsl: => 8f979fa0 afb7bfc7 cfd7dfe7 f7eff7ff (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404 -+ vsl: => 1f2f3f40 5f6f7f8f 9fafbfcf efdfefff (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505 -+ vsl: => 3e5e7e80 bedeff1e 3f5f7f9e dfbfdfff (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606 -+ vsl: => 7cbcfd00 7dbdfe3c 7ebeff3d bf7fbffe (00000000) -+ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707 -+ vsl: => f979fa00 fb7bfc78 fd7dfe7a 7eff7ffc (00000000) -+ -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000 -+ vsr: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101 -+ vsr: => 00810182 02830384 84850586 07068707 (00000000) -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202 -+ vsr: => 004080c1 014181c2 c24282c3 03834383 (00000000) -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303 -+ vsr: => 00204060 80a0c0e1 e1214161 01c1a1c1 (00000000) -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404 -+ vsr: => 80102030 c0506070 f090a0b0 00e0d0e0 (00000000) -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505 -+ vsr: => 40081018 60283038 78485058 00706870 (00000000) -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606 -+ vsr: => 2004080c 3014181c 3c24282c 00383438 (00000000) -+ vsr: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707 -+ vsr: => 10020406 180a0c0e 1e121416 001c1a1c (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000 -+ vsr: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101 -+ vsr: => 78f979fa 7afb7bfc fcfd7dfe 7f7eff7f (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202 -+ vsr: => 3c7cbcfd 3d7dbdfe fe7ebeff 3fbf7fbf (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303 -+ vsr: => 1e3e5e7e 9ebedeff ff3f5f7f 1fdfbfdf (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404 -+ vsr: => 8f1f2f3f cf5f6f7f ff9fafbf 0fefdfef (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505 -+ vsr: => c78f979f e7afb7bf ffcfd7df 07f7eff7 (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606 -+ vsr: => e3c7cbcf f3d7dbdf ffe7ebef 03fbf7fb (00000000) -+ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707 -+ vsr: => f1e3e5e7 f9ebedef fff3f5f7 01fdfbfd (00000000) -+ -+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 0 -+ vspltb: => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000) -+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 3 -+ vspltb: => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000) -+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 6 -+ vspltb: => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000) -+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 9 -+ vspltb: => 06060606 06060606 06060606 06060606 (00000000) -+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 12 -+ vspltb: => 01010101 01010101 01010101 01010101 (00000000) -+ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 15 -+ vspltb: => 04040404 04040404 04040404 04040404 (00000000) -+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0 -+ vspltb: => fefefefe fefefefe fefefefe fefefefe (00000000) -+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3 -+ vspltb: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6 -+ vspltb: => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000) -+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9 -+ vspltb: => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000) -+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12 -+ vspltb: => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000) -+ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15 -+ vspltb: => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000) -+ -+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 0 -+ vsplth: => 0e0d0e0d 0e0d0e0d 0e0d0e0d 0e0d0e0d (00000000) -+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 3 -+ vsplth: => 0b0c0b0c 0b0c0b0c 0b0c0b0c 0b0c0b0c (00000000) -+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 6 -+ vsplth: => 01020102 01020102 01020102 01020102 (00000000) -+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 9 -+ vsplth: => 0e0f0e0f 0e0f0e0f 0e0f0e0f 0e0f0e0f (00000000) -+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 12 -+ vsplth: => 05060506 05060506 05060506 05060506 (00000000) -+ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 15 -+ vsplth: => 03040304 03040304 03040304 03040304 (00000000) -+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0 -+ vsplth: => fefdfefd fefdfefd fefdfefd fefdfefd (00000000) -+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3 -+ vsplth: => fbfcfbfc fbfcfbfc fbfcfbfc fbfcfbfc (00000000) -+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6 -+ vsplth: => f1f2f1f2 f1f2f1f2 f1f2f1f2 f1f2f1f2 (00000000) -+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9 -+ vsplth: => fefffeff fefffeff fefffeff fefffeff (00000000) -+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12 -+ vsplth: => f5f6f5f6 f5f6f5f6 f5f6f5f6 f5f6f5f6 (00000000) -+ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15 -+ vsplth: => f3f4f3f4 f3f4f3f4 f3f4f3f4 f3f4f3f4 (00000000) -+ -+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 0 -+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000) -+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 3 -+ vspltw: => 01020304 01020304 01020304 01020304 (00000000) -+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 6 -+ vspltw: => 05060708 05060708 05060708 05060708 (00000000) -+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 9 -+ vspltw: => 090a0b0c 090a0b0c 090a0b0c 090a0b0c (00000000) -+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 12 -+ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000) -+ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 15 -+ vspltw: => 01020304 01020304 01020304 01020304 (00000000) -+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0 -+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000) -+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3 -+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000) -+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6 -+ vspltw: => f5f6f7f8 f5f6f7f8 f5f6f7f8 f5f6f7f8 (00000000) -+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9 -+ vspltw: => f9fafbfc f9fafbfc f9fafbfc f9fafbfc (00000000) -+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12 -+ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000) -+ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15 -+ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000) -+ -+ vspltisb: 0 => 00000000 00000000 00000000 00000000 (00000000) -+ vspltisb: 1 => 01010101 01010101 01010101 01010101 (00000000) -+ vspltisb: 2 => 02020202 02020202 02020202 02020202 (00000000) -+ vspltisb: 3 => 03030303 03030303 03030303 03030303 (00000000) -+ vspltisb: 4 => 04040404 04040404 04040404 04040404 (00000000) -+ vspltisb: 5 => 05050505 05050505 05050505 05050505 (00000000) -+ vspltisb: 6 => 06060606 06060606 06060606 06060606 (00000000) -+ vspltisb: 7 => 07070707 07070707 07070707 07070707 (00000000) -+ vspltisb: 8 => 08080808 08080808 08080808 08080808 (00000000) -+ vspltisb: 9 => 09090909 09090909 09090909 09090909 (00000000) -+ vspltisb: 10 => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000) -+ vspltisb: 11 => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000) -+ vspltisb: 12 => 0c0c0c0c 0c0c0c0c 0c0c0c0c 0c0c0c0c (00000000) -+ vspltisb: 13 => 0d0d0d0d 0d0d0d0d 0d0d0d0d 0d0d0d0d (00000000) -+ vspltisb: 14 => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000) -+ vspltisb: 15 => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000) -+ vspltisb: 16 => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000) -+ vspltisb: 17 => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000) -+ vspltisb: 18 => f2f2f2f2 f2f2f2f2 f2f2f2f2 f2f2f2f2 (00000000) -+ vspltisb: 19 => f3f3f3f3 f3f3f3f3 f3f3f3f3 f3f3f3f3 (00000000) -+ vspltisb: 20 => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000) -+ vspltisb: 21 => f5f5f5f5 f5f5f5f5 f5f5f5f5 f5f5f5f5 (00000000) -+ vspltisb: 22 => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000) -+ vspltisb: 23 => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000) -+ vspltisb: 24 => f8f8f8f8 f8f8f8f8 f8f8f8f8 f8f8f8f8 (00000000) -+ vspltisb: 25 => f9f9f9f9 f9f9f9f9 f9f9f9f9 f9f9f9f9 (00000000) -+ vspltisb: 26 => fafafafa fafafafa fafafafa fafafafa (00000000) -+ vspltisb: 27 => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000) -+ vspltisb: 28 => fcfcfcfc fcfcfcfc fcfcfcfc fcfcfcfc (00000000) -+ vspltisb: 29 => fdfdfdfd fdfdfdfd fdfdfdfd fdfdfdfd (00000000) -+ vspltisb: 30 => fefefefe fefefefe fefefefe fefefefe (00000000) -+ vspltisb: 31 => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vspltish: 0 => 00000000 00000000 00000000 00000000 (00000000) -+ vspltish: 1 => 00010001 00010001 00010001 00010001 (00000000) -+ vspltish: 2 => 00020002 00020002 00020002 00020002 (00000000) -+ vspltish: 3 => 00030003 00030003 00030003 00030003 (00000000) -+ vspltish: 4 => 00040004 00040004 00040004 00040004 (00000000) -+ vspltish: 5 => 00050005 00050005 00050005 00050005 (00000000) -+ vspltish: 6 => 00060006 00060006 00060006 00060006 (00000000) -+ vspltish: 7 => 00070007 00070007 00070007 00070007 (00000000) -+ vspltish: 8 => 00080008 00080008 00080008 00080008 (00000000) -+ vspltish: 9 => 00090009 00090009 00090009 00090009 (00000000) -+ vspltish: 10 => 000a000a 000a000a 000a000a 000a000a (00000000) -+ vspltish: 11 => 000b000b 000b000b 000b000b 000b000b (00000000) -+ vspltish: 12 => 000c000c 000c000c 000c000c 000c000c (00000000) -+ vspltish: 13 => 000d000d 000d000d 000d000d 000d000d (00000000) -+ vspltish: 14 => 000e000e 000e000e 000e000e 000e000e (00000000) -+ vspltish: 15 => 000f000f 000f000f 000f000f 000f000f (00000000) -+ vspltish: 16 => fff0fff0 fff0fff0 fff0fff0 fff0fff0 (00000000) -+ vspltish: 17 => fff1fff1 fff1fff1 fff1fff1 fff1fff1 (00000000) -+ vspltish: 18 => fff2fff2 fff2fff2 fff2fff2 fff2fff2 (00000000) -+ vspltish: 19 => fff3fff3 fff3fff3 fff3fff3 fff3fff3 (00000000) -+ vspltish: 20 => fff4fff4 fff4fff4 fff4fff4 fff4fff4 (00000000) -+ vspltish: 21 => fff5fff5 fff5fff5 fff5fff5 fff5fff5 (00000000) -+ vspltish: 22 => fff6fff6 fff6fff6 fff6fff6 fff6fff6 (00000000) -+ vspltish: 23 => fff7fff7 fff7fff7 fff7fff7 fff7fff7 (00000000) -+ vspltish: 24 => fff8fff8 fff8fff8 fff8fff8 fff8fff8 (00000000) -+ vspltish: 25 => fff9fff9 fff9fff9 fff9fff9 fff9fff9 (00000000) -+ vspltish: 26 => fffafffa fffafffa fffafffa fffafffa (00000000) -+ vspltish: 27 => fffbfffb fffbfffb fffbfffb fffbfffb (00000000) -+ vspltish: 28 => fffcfffc fffcfffc fffcfffc fffcfffc (00000000) -+ vspltish: 29 => fffdfffd fffdfffd fffdfffd fffdfffd (00000000) -+ vspltish: 30 => fffefffe fffefffe fffefffe fffefffe (00000000) -+ vspltish: 31 => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vspltisw: 0 => 00000000 00000000 00000000 00000000 (00000000) -+ vspltisw: 1 => 00000001 00000001 00000001 00000001 (00000000) -+ vspltisw: 2 => 00000002 00000002 00000002 00000002 (00000000) -+ vspltisw: 3 => 00000003 00000003 00000003 00000003 (00000000) -+ vspltisw: 4 => 00000004 00000004 00000004 00000004 (00000000) -+ vspltisw: 5 => 00000005 00000005 00000005 00000005 (00000000) -+ vspltisw: 6 => 00000006 00000006 00000006 00000006 (00000000) -+ vspltisw: 7 => 00000007 00000007 00000007 00000007 (00000000) -+ vspltisw: 8 => 00000008 00000008 00000008 00000008 (00000000) -+ vspltisw: 9 => 00000009 00000009 00000009 00000009 (00000000) -+ vspltisw: 10 => 0000000a 0000000a 0000000a 0000000a (00000000) -+ vspltisw: 11 => 0000000b 0000000b 0000000b 0000000b (00000000) -+ vspltisw: 12 => 0000000c 0000000c 0000000c 0000000c (00000000) -+ vspltisw: 13 => 0000000d 0000000d 0000000d 0000000d (00000000) -+ vspltisw: 14 => 0000000e 0000000e 0000000e 0000000e (00000000) -+ vspltisw: 15 => 0000000f 0000000f 0000000f 0000000f (00000000) -+ vspltisw: 16 => fffffff0 fffffff0 fffffff0 fffffff0 (00000000) -+ vspltisw: 17 => fffffff1 fffffff1 fffffff1 fffffff1 (00000000) -+ vspltisw: 18 => fffffff2 fffffff2 fffffff2 fffffff2 (00000000) -+ vspltisw: 19 => fffffff3 fffffff3 fffffff3 fffffff3 (00000000) -+ vspltisw: 20 => fffffff4 fffffff4 fffffff4 fffffff4 (00000000) -+ vspltisw: 21 => fffffff5 fffffff5 fffffff5 fffffff5 (00000000) -+ vspltisw: 22 => fffffff6 fffffff6 fffffff6 fffffff6 (00000000) -+ vspltisw: 23 => fffffff7 fffffff7 fffffff7 fffffff7 (00000000) -+ vspltisw: 24 => fffffff8 fffffff8 fffffff8 fffffff8 (00000000) -+ vspltisw: 25 => fffffff9 fffffff9 fffffff9 fffffff9 (00000000) -+ vspltisw: 26 => fffffffa fffffffa fffffffa fffffffa (00000000) -+ vspltisw: 27 => fffffffb fffffffb fffffffb fffffffb (00000000) -+ vspltisw: 28 => fffffffc fffffffc fffffffc fffffffc (00000000) -+ vspltisw: 29 => fffffffd fffffffd fffffffd fffffffd (00000000) -+ vspltisw: 30 => fffffffe fffffffe fffffffe fffffffe (00000000) -+ vspltisw: 31 => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0 -+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000) -+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 14 -+ vsldoi: => 07080102 0b0c0506 0e0f090a 03040e0d] (00000000) -+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0 -+ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000) -+ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14 -+ vsldoi: => f7f8f1f2 fbfcf5f6 fefff9fa 0304fefd] (00000000) -+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0 -+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000) -+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 14 -+ vsldoi: => 07080102 0b0c0506 0e0f090a f3f40e0d] (00000000) -+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0 -+ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000) -+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14 -+ vsldoi: => f7f8f1f2 fbfcf5f6 fefff9fa f3f4fefd] (00000000) -+ -+ lvsl 3, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000) -+ lvsl 4, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000) -+ lvsl 5, 0 => 0x14131211100f0e0d 0x0c0b0a0908070605 (00000000) -+ lvsl 6, 0 => 0x1514131211100f0e 0x0d0c0b0a09080706 (00000000) -+ lvsl 7, 0 => 0x161514131211100f 0x0e0d0c0b0a090807 (00000000) -+ lvsl 8, 0 => 0x1716151413121110 0x0f0e0d0c0b0a0908 (00000000) -+ lvsl 9, 0 => 0x1817161514131211 0x100f0e0d0c0b0a09 (00000000) -+ lvsl a, 0 => 0x1918171615141312 0x11100f0e0d0c0b0a (00000000) -+ lvsl b, 0 => 0x1a19181716151413 0x1211100f0e0d0c0b (00000000) -+ lvsl c, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000) -+ lvsl d, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000) -+ lvsl e, 0 => 0x1d1c1b1a19181716 0x1514131211100f0e (00000000) -+ lvsl f, 0 => 0x1e1d1c1b1a191817 0x161514131211100f (00000000) -+ lvsl 0, 0 => 0x0f0e0d0c0b0a0908 0x0706050403020100 (00000000) -+ lvsl 1, 0 => 0x100f0e0d0c0b0a09 0x0807060504030201 (00000000) -+ lvsl 2, 0 => 0x11100f0e0d0c0b0a 0x0908070605040302 (00000000) -+ lvsl 3, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000) -+ lvsl 4, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000) -+ -+ lvsr 3, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000) -+ lvsr 4, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000) -+ lvsr 5, 0 => 0x1a19181716151413 0x1211100f0e0d0c0b (00000000) -+ lvsr 6, 0 => 0x1918171615141312 0x11100f0e0d0c0b0a (00000000) -+ lvsr 7, 0 => 0x1817161514131211 0x100f0e0d0c0b0a09 (00000000) -+ lvsr 8, 0 => 0x1716151413121110 0x0f0e0d0c0b0a0908 (00000000) -+ lvsr 9, 0 => 0x161514131211100f 0x0e0d0c0b0a090807 (00000000) -+ lvsr a, 0 => 0x1514131211100f0e 0x0d0c0b0a09080706 (00000000) -+ lvsr b, 0 => 0x14131211100f0e0d 0x0c0b0a0908070605 (00000000) -+ lvsr c, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000) -+ lvsr d, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000) -+ lvsr e, 0 => 0x11100f0e0d0c0b0a 0x0908070605040302 (00000000) -+ lvsr f, 0 => 0x100f0e0d0c0b0a09 0x0807060504030201 (00000000) -+ lvsr 0, 0 => 0x1f1e1d1c1b1a1918 0x1716151413121110 (00000000) -+ lvsr 1, 0 => 0x1e1d1c1b1a191817 0x161514131211100f (00000000) -+ lvsr 2, 0 => 0x1d1c1b1a19181716 0x1514131211100f0e (00000000) -+ lvsr 3, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000) -+ lvsr 4, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000) -+ -+Altivec load insns with two register args: -+ lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 00000000 00000000 00000000 (00000000) -+ lvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05000000 00000000 00000000 (00000000) -+ lvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 000d0000 (00000000) -+ lvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 00000000 00000000 00000000 (00000000) -+ lvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5000000 00000000 00000000 (00000000) -+ lvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 00fd0000 (00000000) -+ -+ lvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 00000000 00000000 00000000 (00000000) -+ lvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060000 00000000 00000000 (00000000) -+ lvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0000 (00000000) -+ lvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 00000000 00000000 00000000 (00000000) -+ lvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f60000 00000000 00000000 (00000000) -+ lvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefd0000 (00000000) -+ -+ lvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000) -+ lvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060708 00000000 00000000 (00000000) -+ lvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0e0f (00000000) -+ lvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000) -+ lvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f6f7f8 00000000 00000000 (00000000) -+ lvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefdfeff (00000000) -+ -+ lvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ lvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ lvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ lvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ lvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ lvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ lvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ lvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ lvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ lvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ lvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ lvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+Altivec store insns with three register args: -+ stvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 00000000 00000000 00000000 (00000000) -+ stvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 05000000 00000000 00000000 (00000000) -+ stvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 05000000 00000000 000d0000 (00000000) -+ stvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 00000000 00000000 00000000 (00000000) -+ stvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 f5000000 00000000 00000000 (00000000) -+ stvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 f5000000 00000000 00fd0000 (00000000) -+ -+ stvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 00000000 00000000 00000000 (00000000) -+ stvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 05060000 00000000 00000000 (00000000) -+ stvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 05060000 00000000 0e0d0000 (00000000) -+ stvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 00000000 00000000 00000000 (00000000) -+ stvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 f5f60000 00000000 00000000 (00000000) -+ stvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 f5f60000 00000000 fefd0000 (00000000) -+ -+ stvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000) -+ stvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 00000000 (00000000) -+ stvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 0e0d0e0f (00000000) -+ stvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000) -+ stvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 00000000 (00000000) -+ stvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 fefdfeff (00000000) -+ -+ stvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ stvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ stvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ stvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ stvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ stvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+ stvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ stvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ stvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000) -+ stvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000) -+ -+Altivec floating point arith insns with two args: -+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 033fffff 033fffff 033fffff 033fffff (00000000) -+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => d1bfffff d1bfffff d1bfffff d1bfffff (00000000) -+ vaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 51bfffff 51bfffff 51bfffff 51bfffff (00000000) -+ vsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 833fffff 833fffff 833fffff 833fffff (00000000) -+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000) -+ vsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000) -+ vsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vmaxfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vmaxfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000) -+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vmaxfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vmaxfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vmaxfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 80000000 80000000 80000000 80000000 (00000000) -+ vmaxfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vmaxfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vmaxfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaxfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vminfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vminfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vminfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vminfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000) -+ vminfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000) -+ vminfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vminfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vminfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vminfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 80000000 80000000 80000000 80000000 (00000000) -+ vminfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vminfp: => 80000000 80000000 80000000 80000000 (00000000) -+ vminfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000) -+ vminfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vminfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vminfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vminfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vminfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vminfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vminfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vminfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+Altivec floating point arith insns with three args: -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) -+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff -+ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ -+Altivec floating point arith insns with one arg: -+ vrfin: 02bfffff 02bfffff 02bfffff 02bfffff -+ vrfin: => 00000000 00000000 00000000 00000000 (00000000) -+ vrfin: 513fffff 513fffff 513fffff 513fffff -+ vrfin: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vrfin: 82bfffff 82bfffff 82bfffff 82bfffff -+ vrfin: => 80000000 80000000 80000000 80000000 (00000000) -+ vrfin: d13fffff d13fffff d13fffff d13fffff -+ vrfin: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vrfin: 00000000 00000000 00000000 00000000 -+ vrfin: => 00000000 00000000 00000000 00000000 (00000000) -+ vrfin: 80000000 80000000 80000000 80000000 -+ vrfin: => 80000000 80000000 80000000 80000000 (00000000) -+ vrfin: 7f800000 7f800000 7f800000 7f800000 -+ vrfin: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vrfin: ff800000 ff800000 ff800000 ff800000 -+ vrfin: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vrfin: 7fffffff 7fffffff 7fffffff 7fffffff -+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfin: ffffffff ffffffff ffffffff ffffffff -+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vrfin: 7fbfffff 7fbfffff 7fbfffff 7fbfffff -+ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfin: ffbfffff ffbfffff ffbfffff ffbfffff -+ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vrfiz: 02bfffff 02bfffff 02bfffff 02bfffff -+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000) -+ vrfiz: 513fffff 513fffff 513fffff 513fffff -+ vrfiz: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vrfiz: 82bfffff 82bfffff 82bfffff 82bfffff -+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000) -+ vrfiz: d13fffff d13fffff d13fffff d13fffff -+ vrfiz: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vrfiz: 00000000 00000000 00000000 00000000 -+ vrfiz: => 00000000 00000000 00000000 00000000 (00000000) -+ vrfiz: 80000000 80000000 80000000 80000000 -+ vrfiz: => 80000000 80000000 80000000 80000000 (00000000) -+ vrfiz: 7f800000 7f800000 7f800000 7f800000 -+ vrfiz: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vrfiz: ff800000 ff800000 ff800000 ff800000 -+ vrfiz: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vrfiz: 7fffffff 7fffffff 7fffffff 7fffffff -+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfiz: ffffffff ffffffff ffffffff ffffffff -+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vrfiz: 7fbfffff 7fbfffff 7fbfffff 7fbfffff -+ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfiz: ffbfffff ffbfffff ffbfffff ffbfffff -+ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vrfip: 02bfffff 02bfffff 02bfffff 02bfffff -+ vrfip: => 3f800000 3f800000 3f800000 3f800000 (00000000) -+ vrfip: 513fffff 513fffff 513fffff 513fffff -+ vrfip: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vrfip: 82bfffff 82bfffff 82bfffff 82bfffff -+ vrfip: => 80000000 80000000 80000000 80000000 (00000000) -+ vrfip: d13fffff d13fffff d13fffff d13fffff -+ vrfip: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vrfip: 00000000 00000000 00000000 00000000 -+ vrfip: => 00000000 00000000 00000000 00000000 (00000000) -+ vrfip: 80000000 80000000 80000000 80000000 -+ vrfip: => 80000000 80000000 80000000 80000000 (00000000) -+ vrfip: 7f800000 7f800000 7f800000 7f800000 -+ vrfip: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vrfip: ff800000 ff800000 ff800000 ff800000 -+ vrfip: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vrfip: 7fffffff 7fffffff 7fffffff 7fffffff -+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfip: ffffffff ffffffff ffffffff ffffffff -+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vrfip: 7fbfffff 7fbfffff 7fbfffff 7fbfffff -+ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfip: ffbfffff ffbfffff ffbfffff ffbfffff -+ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vrfim: 02bfffff 02bfffff 02bfffff 02bfffff -+ vrfim: => 00000000 00000000 00000000 00000000 (00000000) -+ vrfim: 513fffff 513fffff 513fffff 513fffff -+ vrfim: => 513fffff 513fffff 513fffff 513fffff (00000000) -+ vrfim: 82bfffff 82bfffff 82bfffff 82bfffff -+ vrfim: => bf800000 bf800000 bf800000 bf800000 (00000000) -+ vrfim: d13fffff d13fffff d13fffff d13fffff -+ vrfim: => d13fffff d13fffff d13fffff d13fffff (00000000) -+ vrfim: 00000000 00000000 00000000 00000000 -+ vrfim: => 00000000 00000000 00000000 00000000 (00000000) -+ vrfim: 80000000 80000000 80000000 80000000 -+ vrfim: => 80000000 80000000 80000000 80000000 (00000000) -+ vrfim: 7f800000 7f800000 7f800000 7f800000 -+ vrfim: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vrfim: ff800000 ff800000 ff800000 ff800000 -+ vrfim: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vrfim: 7fffffff 7fffffff 7fffffff 7fffffff -+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfim: ffffffff ffffffff ffffffff ffffffff -+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vrfim: 7fbfffff 7fbfffff 7fbfffff 7fbfffff -+ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) -+ vrfim: ffbfffff ffbfffff ffbfffff ffbfffff -+ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ -+ vrefp: 02bfffff 02bfffff 02bfffff 02bfffff -+ vrefp: => 7c2a8000 7c2a8000 7c2a8000 7c2a8000 (00000000) -+ vrefp: 513fffff 513fffff 513fffff 513fffff -+ vrefp: => 2daa8000 2daa8000 2daa8000 2daa8000 (00000000) -+ vrefp: 82bfffff 82bfffff 82bfffff 82bfffff -+ vrefp: => fc2a8000 fc2a8000 fc2a8000 fc2a8000 (00000000) -+ vrefp: d13fffff d13fffff d13fffff d13fffff -+ vrefp: => adaa8000 adaa8000 adaa8000 adaa8000 (00000000) -+ vrefp: 00000000 00000000 00000000 00000000 -+ vrefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vrefp: 80000000 80000000 80000000 80000000 -+ vrefp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vrefp: 7f800000 7f800000 7f800000 7f800000 -+ vrefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vrefp: ff800000 ff800000 ff800000 ff800000 -+ vrefp: => 80000000 80000000 80000000 80000000 (00000000) -+ vrefp: 7fffffff 7fffffff 7fffffff 7fffffff -+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000) -+ vrefp: ffffffff ffffffff ffffffff ffffffff -+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000) -+ vrefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff -+ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000) -+ vrefp: ffbfffff ffbfffff ffbfffff ffbfffff -+ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000) -+ -+ vrsqrtefp: 02bfffff 02bfffff 02bfffff 02bfffff -+ vrsqrtefp: => 5dd10000 5dd10000 5dd10000 5dd10000 (00000000) -+ vrsqrtefp: 513fffff 513fffff 513fffff 513fffff -+ vrsqrtefp: => 3693c000 3693c000 3693c000 3693c000 (00000000) -+ vrsqrtefp: 82bfffff 82bfffff 82bfffff 82bfffff -+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vrsqrtefp: d13fffff d13fffff d13fffff d13fffff -+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vrsqrtefp: 00000000 00000000 00000000 00000000 -+ vrsqrtefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) -+ vrsqrtefp: 80000000 80000000 80000000 80000000 -+ vrsqrtefp: => ff800000 ff800000 ff800000 ff800000 (00000000) -+ vrsqrtefp: 7f800000 7f800000 7f800000 7f800000 -+ vrsqrtefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vrsqrtefp: ff800000 ff800000 ff800000 ff800000 -+ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) -+ vrsqrtefp: 7fffffff 7fffffff 7fffffff 7fffffff -+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000) -+ vrsqrtefp: ffffffff ffffffff ffffffff ffffffff -+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000) -+ vrsqrtefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff -+ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000) -+ vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff -+ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000) -+ -+Altivec floating point compare insns: -+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgtfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpeqfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000) -+ vcmpgefp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000) -+ -+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000) -+ vcmpbfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ -+Altivec floating point compare insns with flags update: -+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpeqfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080) -+ vcmpgefp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020) -+ -+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000) -+ vcmpbfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000) -+ vcmpbfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020) -+ vcmpbfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000 -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff -+ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000) -+ -+Altivec float special insns: -+ vcfux: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000) -+ vcfux: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000) -+ vcfux: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000) -+ vcfux: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000) -+ vcfux: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000) -+ vcfux: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000) -+ vcfux: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000) -+ vcfux: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000) -+ vcfux: 82bfffff (-2.821186e-37), 0 => 4f02c000 ( 2.193621e+09) (00000000) -+ vcfux: 82bfffff (-2.821186e-37), 9 => 4a82c000 ( 4.284416e+06) (00000000) -+ vcfux: 82bfffff (-2.821186e-37), 18 => 4602c000 ( 8.368000e+03) (00000000) -+ vcfux: 82bfffff (-2.821186e-37), 27 => 4182c000 ( 1.634375e+01) (00000000) -+ vcfux: d13fffff (-5.153960e+10), 0 => 4f514000 ( 3.510632e+09) (00000000) -+ vcfux: d13fffff (-5.153960e+10), 9 => 4ad14000 ( 6.856704e+06) (00000000) -+ vcfux: d13fffff (-5.153960e+10), 18 => 46514000 ( 1.339200e+04) (00000000) -+ vcfux: d13fffff (-5.153960e+10), 27 => 41d14000 ( 2.615625e+01) (00000000) -+ vcfux: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vcfux: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vcfux: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vcfux: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vcfux: 80000000 (-0.000000e+00), 0 => 4f000000 ( 2.147484e+09) (00000000) -+ vcfux: 80000000 (-0.000000e+00), 9 => 4a800000 ( 4.194304e+06) (00000000) -+ vcfux: 80000000 (-0.000000e+00), 18 => 46000000 ( 8.192000e+03) (00000000) -+ vcfux: 80000000 (-0.000000e+00), 27 => 41800000 ( 1.600000e+01) (00000000) -+ vcfux: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000) -+ vcfux: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000) -+ vcfux: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000) -+ vcfux: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000) -+ vcfux: ff800000 ( -inf), 0 => 4f7f8000 ( 4.286579e+09) (00000000) -+ vcfux: ff800000 ( -inf), 9 => 4aff8000 ( 8.372224e+06) (00000000) -+ vcfux: ff800000 ( -inf), 18 => 467f8000 ( 1.635200e+04) (00000000) -+ vcfux: ff800000 ( -inf), 27 => 41ff8000 ( 3.193750e+01) (00000000) -+ vcfux: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000) -+ vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000) -+ vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000) -+ vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000) -+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000) -+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000) -+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000) -+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000) -+ vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000) -+ vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000) -+ vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000) -+ vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000) -+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000) -+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000) -+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000) -+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000) -+ -+ vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000) -+ vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000) -+ vcfsx: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000) -+ vcfsx: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000) -+ vcfsx: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000) -+ vcfsx: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000) -+ vcfsx: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000) -+ vcfsx: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000) -+ vcfsx: 82bfffff (-2.821186e-37), 0 => cefa8000 (-2.101346e+09) (00000000) -+ vcfsx: 82bfffff (-2.821186e-37), 9 => ca7a8000 (-4.104192e+06) (00000000) -+ vcfsx: 82bfffff (-2.821186e-37), 18 => c5fa8000 (-8.016000e+03) (00000000) -+ vcfsx: 82bfffff (-2.821186e-37), 27 => c17a8000 (-1.565625e+01) (00000000) -+ vcfsx: d13fffff (-5.153960e+10), 0 => ce3b0000 (-7.843348e+08) (00000000) -+ vcfsx: d13fffff (-5.153960e+10), 9 => c9bb0000 (-1.531904e+06) (00000000) -+ vcfsx: d13fffff (-5.153960e+10), 18 => c53b0000 (-2.992000e+03) (00000000) -+ vcfsx: d13fffff (-5.153960e+10), 27 => c0bb0000 (-5.843750e+00) (00000000) -+ vcfsx: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vcfsx: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vcfsx: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vcfsx: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vcfsx: 80000000 (-0.000000e+00), 0 => cf000000 (-2.147484e+09) (00000000) -+ vcfsx: 80000000 (-0.000000e+00), 9 => ca800000 (-4.194304e+06) (00000000) -+ vcfsx: 80000000 (-0.000000e+00), 18 => c6000000 (-8.192000e+03) (00000000) -+ vcfsx: 80000000 (-0.000000e+00), 27 => c1800000 (-1.600000e+01) (00000000) -+ vcfsx: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000) -+ vcfsx: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000) -+ vcfsx: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000) -+ vcfsx: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000) -+ vcfsx: ff800000 ( -inf), 0 => cb000000 (-8.388608e+06) (00000000) -+ vcfsx: ff800000 ( -inf), 9 => c6800000 (-1.638400e+04) (00000000) -+ vcfsx: ff800000 ( -inf), 18 => c2000000 (-3.200000e+01) (00000000) -+ vcfsx: ff800000 ( -inf), 27 => bd800000 (-6.250000e-02) (00000000) -+ vcfsx: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000) -+ vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000) -+ vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000) -+ vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000) -+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000) -+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000) -+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000) -+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000) -+ vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000) -+ vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000) -+ vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000) -+ vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000) -+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000) -+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000) -+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000) -+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000) -+ -+ vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000) -+ vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: d13fffff (-5.153960e+10), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: d13fffff (-5.153960e+10), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: d13fffff (-5.153960e+10), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: d13fffff (-5.153960e+10), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000) -+ vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ff800000 ( -inf), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ -+ vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 513fffff ( 5.153960e+10), 0 => 7fffffff ( nan) (00000000) -+ vctsxs: 513fffff ( 5.153960e+10), 9 => 7fffffff ( nan) (00000000) -+ vctsxs: 513fffff ( 5.153960e+10), 18 => 7fffffff ( nan) (00000000) -+ vctsxs: 513fffff ( 5.153960e+10), 27 => 7fffffff ( nan) (00000000) -+ vctsxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: d13fffff (-5.153960e+10), 0 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: d13fffff (-5.153960e+10), 9 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: d13fffff (-5.153960e+10), 18 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: d13fffff (-5.153960e+10), 27 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7f800000 ( inf), 0 => 7fffffff ( nan) (00000000) -+ vctsxs: 7f800000 ( inf), 9 => 7fffffff ( nan) (00000000) -+ vctsxs: 7f800000 ( inf), 18 => 7fffffff ( nan) (00000000) -+ vctsxs: 7f800000 ( inf), 27 => 7fffffff ( nan) (00000000) -+ vctsxs: ff800000 ( -inf), 0 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: ff800000 ( -inf), 9 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: ff800000 ( -inf), 18 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: ff800000 ( -inf), 27 => 80000000 (-0.000000e+00) (00000000) -+ vctsxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ -+All done. Tested 165 different instructions -Index: none/tests/ppc64/jm-vmx.stdout.exp -=================================================================== ---- none/tests/ppc64/jm-vmx.stdout.exp.orig -+++ none/tests/ppc64/jm-vmx.stdout.exp -@@ -1407,43 +1407,43 @@ Altivec integer special insns: - vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14 - vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000) - -- lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000) -- lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000) -- lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000) -- lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000) -- lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000) -- lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000) -- lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000) -- lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000) -- lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000) -- lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000) -- lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000) -- lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000) -- lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000) -- lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000) -- lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000) -- lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000) -- lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000) -- lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000) -- -- lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000) -- lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000) -- lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000) -- lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000) -- lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000) -- lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000) -- lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000) -- lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000) -- lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000) -- lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000) -- lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000) -- lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000) -- lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000) -- lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000) -- lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000) -- lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000) -- lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000) -- lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000) -+ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000) -+ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000) -+ lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000) -+ lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000) -+ lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000) -+ lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000) -+ lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000) -+ lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000) -+ lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000) -+ lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000) -+ lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000) -+ lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000) -+ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000) -+ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000) -+ lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000) -+ lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000) -+ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000) -+ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000) -+ -+ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000) -+ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000) -+ lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000) -+ lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000) -+ lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000) -+ lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000) -+ lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000) -+ lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000) -+ lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000) -+ lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000) -+ lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000) -+ lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000) -+ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000) -+ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000) -+ lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000) -+ lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000) -+ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000) -+ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000) - - Altivec load insns with two register args: - lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000) -@@ -3451,18 +3451,18 @@ Altivec float special insns: - vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000) - vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000) - vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000) -- vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000) -- vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000) -- vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000) -- vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000) -+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000) -+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000) -+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000) -+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000) - vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000) - vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000) - vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000) - vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000) -- vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000) -- vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000) -- vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000) -- vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000) -+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000) -+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000) -+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000) -+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000) - - vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000) - vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000) -@@ -3500,27 +3500,27 @@ Altivec float special insns: - vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000) - vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000) - vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000) -- vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000) -- vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000) -- vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000) -- vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000) -+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000) -+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000) -+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000) -+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000) - vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000) - vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000) - vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000) - vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000) -- vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000) -- vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000) -- vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000) -- vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000) -+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000) -+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000) -+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000) -+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000) - - vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000) - vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) -@@ -3537,10 +3537,10 @@ Altivec float special insns: - vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000) -- vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000) -- vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000) -- vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000) -+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000) - vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000) -@@ -3549,18 +3549,18 @@ Altivec float special insns: - vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - - vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) -@@ -3598,17 +3598,17 @@ Altivec float special insns: - vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - - All done. Tested 165 different instructions -Index: none/tests/ppc64/jm-fp.stdout.exp-BE2 -=================================================================== ---- /dev/null -+++ none/tests/ppc64/jm-fp.stdout.exp-BE2 -@@ -0,0 +1,1533 @@ -+PPC floating point arith insns with three args: -+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns -+ with three args with flags update: -+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns with two args: -+ fadd 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns -+ with two args with flags update: -+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point compare insns (two args): -+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns with one arg: -+ fres 0010000000000001 => 7ff0000000000000 -+ fres 00100094e0000359 => 7ff0000000000000 -+ fres 3fe0000000000001 => 4000000000000000 -+ fres 3fe00094e0000359 => 3ffff00000000000 -+ fres 8010000000000001 => fff0000000000000 -+ fres 80100094e0000359 => fff0000000000000 -+ fres bfe0000000000001 => c000000000000000 -+ fres bfe00094e0000359 => bffff00000000000 -+ fres 0000000000000000 => 7ff0000000000000 -+ fres 8000000000000000 => fff0000000000000 -+ fres 7ff0000000000000 => 0000000000000000 -+ fres fff0000000000000 => 8000000000000000 -+ fres 7ff7ffffffffffff => 7ffff00000000000 -+ fres fff7ffffffffffff => fffff00000000000 -+ fres 7ff8000000000000 => 7ff8000000000000 -+ fres fff8000000000000 => fff8000000000000 -+ -+ frsqrte 0010000000000001 => 5fdf000000000000 -+ frsqrte 00100094e0000359 => 5fdf000000000000 -+ frsqrte 3fe0000000000001 => 3ff6000000000000 -+ frsqrte 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte 8010000000000001 => 7ff8000000000000 -+ frsqrte 80100094e0000359 => 7ff8000000000000 -+ frsqrte bfe0000000000001 => 7ff8000000000000 -+ frsqrte bfe00094e0000359 => 7ff8000000000000 -+ frsqrte 0000000000000000 => 7ff0000000000000 -+ frsqrte 8000000000000000 => fff0000000000000 -+ frsqrte 7ff0000000000000 => 0000000000000000 -+ frsqrte fff0000000000000 => 7ff8000000000000 -+ frsqrte 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte fff7ffffffffffff => ffff000000000000 -+ frsqrte 7ff8000000000000 => 7ff8000000000000 -+ frsqrte fff8000000000000 => fff8000000000000 -+ -+ frsp 0010000000000001 => 0000000000000000 -+ frsp 00100094e0000359 => 0000000000000000 -+ frsp 3fe0000000000001 => 3fe0000000000000 -+ frsp 3fe00094e0000359 => 3fe00094e0000000 -+ frsp 8010000000000001 => 8000000000000000 -+ frsp 80100094e0000359 => 8000000000000000 -+ frsp bfe0000000000001 => bfe0000000000000 -+ frsp bfe00094e0000359 => bfe00094e0000000 -+ frsp 0000000000000000 => 0000000000000000 -+ frsp 8000000000000000 => 8000000000000000 -+ frsp 7ff0000000000000 => 7ff0000000000000 -+ frsp fff0000000000000 => fff0000000000000 -+ frsp 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp fff7ffffffffffff => ffffffffe0000000 -+ frsp 7ff8000000000000 => 7ff8000000000000 -+ frsp fff8000000000000 => fff8000000000000 -+ -+ fctiw 0010000000000001 => 0000000000000000 -+ fctiw 00100094e0000359 => 0000000000000000 -+ fctiw 3fe0000000000001 => 0000000000000001 -+ fctiw 3fe00094e0000359 => 0000000000000001 -+ fctiw 8010000000000001 => 0000000000000000 -+ fctiw 80100094e0000359 => 0000000000000000 -+ fctiw bfe0000000000001 => 00000000ffffffff -+ fctiw bfe00094e0000359 => 00000000ffffffff -+ fctiw 0000000000000000 => 0000000000000000 -+ fctiw 8000000000000000 => 0000000000000000 -+ fctiw 7ff0000000000000 => 000000007fffffff -+ fctiw fff0000000000000 => 0000000080000000 -+ fctiw 7ff7ffffffffffff => 0000000080000000 -+ fctiw fff7ffffffffffff => 0000000080000000 -+ fctiw 7ff8000000000000 => 0000000080000000 -+ fctiw fff8000000000000 => 0000000080000000 -+ -+ fctiwz 0010000000000001 => 0000000000000000 -+ fctiwz 00100094e0000359 => 0000000000000000 -+ fctiwz 3fe0000000000001 => 0000000000000000 -+ fctiwz 3fe00094e0000359 => 0000000000000000 -+ fctiwz 8010000000000001 => 0000000000000000 -+ fctiwz 80100094e0000359 => 0000000000000000 -+ fctiwz bfe0000000000001 => 0000000000000000 -+ fctiwz bfe00094e0000359 => 0000000000000000 -+ fctiwz 0000000000000000 => 0000000000000000 -+ fctiwz 8000000000000000 => 0000000000000000 -+ fctiwz 7ff0000000000000 => 000000007fffffff -+ fctiwz fff0000000000000 => 0000000080000000 -+ fctiwz 7ff7ffffffffffff => 0000000080000000 -+ fctiwz fff7ffffffffffff => 0000000080000000 -+ fctiwz 7ff8000000000000 => 0000000080000000 -+ fctiwz fff8000000000000 => 0000000080000000 -+ -+ fmr 0010000000000001 => 0010000000000001 -+ fmr 00100094e0000359 => 00100094e0000359 -+ fmr 3fe0000000000001 => 3fe0000000000001 -+ fmr 3fe00094e0000359 => 3fe00094e0000359 -+ fmr 8010000000000001 => 8010000000000001 -+ fmr 80100094e0000359 => 80100094e0000359 -+ fmr bfe0000000000001 => bfe0000000000001 -+ fmr bfe00094e0000359 => bfe00094e0000359 -+ fmr 0000000000000000 => 0000000000000000 -+ fmr 8000000000000000 => 8000000000000000 -+ fmr 7ff0000000000000 => 7ff0000000000000 -+ fmr fff0000000000000 => fff0000000000000 -+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr fff7ffffffffffff => fff7ffffffffffff -+ fmr 7ff8000000000000 => 7ff8000000000000 -+ fmr fff8000000000000 => fff8000000000000 -+ -+ fneg 0010000000000001 => 8010000000000001 -+ fneg 00100094e0000359 => 80100094e0000359 -+ fneg 3fe0000000000001 => bfe0000000000001 -+ fneg 3fe00094e0000359 => bfe00094e0000359 -+ fneg 8010000000000001 => 0010000000000001 -+ fneg 80100094e0000359 => 00100094e0000359 -+ fneg bfe0000000000001 => 3fe0000000000001 -+ fneg bfe00094e0000359 => 3fe00094e0000359 -+ fneg 0000000000000000 => 8000000000000000 -+ fneg 8000000000000000 => 0000000000000000 -+ fneg 7ff0000000000000 => fff0000000000000 -+ fneg fff0000000000000 => 7ff0000000000000 -+ fneg 7ff7ffffffffffff => fff7ffffffffffff -+ fneg fff7ffffffffffff => 7ff7ffffffffffff -+ fneg 7ff8000000000000 => fff8000000000000 -+ fneg fff8000000000000 => 7ff8000000000000 -+ -+ fabs 0010000000000001 => 0010000000000001 -+ fabs 00100094e0000359 => 00100094e0000359 -+ fabs 3fe0000000000001 => 3fe0000000000001 -+ fabs 3fe00094e0000359 => 3fe00094e0000359 -+ fabs 8010000000000001 => 0010000000000001 -+ fabs 80100094e0000359 => 00100094e0000359 -+ fabs bfe0000000000001 => 3fe0000000000001 -+ fabs bfe00094e0000359 => 3fe00094e0000359 -+ fabs 0000000000000000 => 0000000000000000 -+ fabs 8000000000000000 => 0000000000000000 -+ fabs 7ff0000000000000 => 7ff0000000000000 -+ fabs fff0000000000000 => 7ff0000000000000 -+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs fff7ffffffffffff => 7ff7ffffffffffff -+ fabs 7ff8000000000000 => 7ff8000000000000 -+ fabs fff8000000000000 => 7ff8000000000000 -+ -+ fnabs 0010000000000001 => 8010000000000001 -+ fnabs 00100094e0000359 => 80100094e0000359 -+ fnabs 3fe0000000000001 => bfe0000000000001 -+ fnabs 3fe00094e0000359 => bfe00094e0000359 -+ fnabs 8010000000000001 => 8010000000000001 -+ fnabs 80100094e0000359 => 80100094e0000359 -+ fnabs bfe0000000000001 => bfe0000000000001 -+ fnabs bfe00094e0000359 => bfe00094e0000359 -+ fnabs 0000000000000000 => 8000000000000000 -+ fnabs 8000000000000000 => 8000000000000000 -+ fnabs 7ff0000000000000 => fff0000000000000 -+ fnabs fff0000000000000 => fff0000000000000 -+ fnabs 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs fff7ffffffffffff => fff7ffffffffffff -+ fnabs 7ff8000000000000 => fff8000000000000 -+ fnabs fff8000000000000 => fff8000000000000 -+ -+ fsqrt 0010000000000001 => 2000000000000000 -+ fsqrt 00100094e0000359 => 2000004a6f52dd4a -+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd -+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df -+ fsqrt 8010000000000001 => 7ff8000000000000 -+ fsqrt 80100094e0000359 => 7ff8000000000000 -+ fsqrt bfe0000000000001 => 7ff8000000000000 -+ fsqrt bfe00094e0000359 => 7ff8000000000000 -+ fsqrt 0000000000000000 => 0000000000000000 -+ fsqrt 8000000000000000 => 8000000000000000 -+ fsqrt 7ff0000000000000 => 7ff0000000000000 -+ fsqrt fff0000000000000 => 7ff8000000000000 -+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff -+ fsqrt fff7ffffffffffff => ffffffffffffffff -+ fsqrt 7ff8000000000000 => 7ff8000000000000 -+ fsqrt fff8000000000000 => fff8000000000000 -+ -+ fcfid 0010000000000001 => 4330000000000001 -+ fcfid 00100094e0000359 => 43300094e0000359 -+ fcfid 3fe0000000000001 => 43cff00000000000 -+ fcfid 3fe00094e0000359 => 43cff0004a700002 -+ fcfid 8010000000000001 => c3dffc0000000000 -+ fcfid 80100094e0000359 => c3dffbffdac7ffff -+ fcfid bfe0000000000001 => c3d0080000000000 -+ fcfid bfe00094e0000359 => c3d007ffdac7ffff -+ fcfid 0000000000000000 => 0000000000000000 -+ fcfid 8000000000000000 => c3e0000000000000 -+ fcfid 7ff0000000000000 => 43dffc0000000000 -+ fcfid fff0000000000000 => c330000000000000 -+ fcfid 7ff7ffffffffffff => 43dffe0000000000 -+ fcfid fff7ffffffffffff => c320000000000002 -+ fcfid 7ff8000000000000 => 43dffe0000000000 -+ fcfid fff8000000000000 => c320000000000000 -+ -+ fctid 0010000000000001 => 0000000000000000 -+ fctid 00100094e0000359 => 0000000000000000 -+ fctid 3fe0000000000001 => 0000000000000001 -+ fctid 3fe00094e0000359 => 0000000000000001 -+ fctid 8010000000000001 => 0000000000000000 -+ fctid 80100094e0000359 => 0000000000000000 -+ fctid bfe0000000000001 => ffffffffffffffff -+ fctid bfe00094e0000359 => ffffffffffffffff -+ fctid 0000000000000000 => 0000000000000000 -+ fctid 8000000000000000 => 0000000000000000 -+ fctid 7ff0000000000000 => 7fffffffffffffff -+ fctid fff0000000000000 => 8000000000000000 -+ fctid 7ff7ffffffffffff => 8000000000000000 -+ fctid fff7ffffffffffff => 8000000000000000 -+ fctid 7ff8000000000000 => 8000000000000000 -+ fctid fff8000000000000 => 8000000000000000 -+ -+ fctidz 0010000000000001 => 0000000000000000 -+ fctidz 00100094e0000359 => 0000000000000000 -+ fctidz 3fe0000000000001 => 0000000000000000 -+ fctidz 3fe00094e0000359 => 0000000000000000 -+ fctidz 8010000000000001 => 0000000000000000 -+ fctidz 80100094e0000359 => 0000000000000000 -+ fctidz bfe0000000000001 => 0000000000000000 -+ fctidz bfe00094e0000359 => 0000000000000000 -+ fctidz 0000000000000000 => 0000000000000000 -+ fctidz 8000000000000000 => 0000000000000000 -+ fctidz 7ff0000000000000 => 7fffffffffffffff -+ fctidz fff0000000000000 => 8000000000000000 -+ fctidz 7ff7ffffffffffff => 8000000000000000 -+ fctidz fff7ffffffffffff => 8000000000000000 -+ fctidz 7ff8000000000000 => 8000000000000000 -+ fctidz fff8000000000000 => 8000000000000000 -+ -+PPC floating point arith insns -+ with one arg with flags update: -+ fres. 0010000000000001 => 7ff0000000000000 -+ fres. 00100094e0000359 => 7ff0000000000000 -+ fres. 3fe0000000000001 => 4000000000000000 -+ fres. 3fe00094e0000359 => 3ffff00000000000 -+ fres. 8010000000000001 => fff0000000000000 -+ fres. 80100094e0000359 => fff0000000000000 -+ fres. bfe0000000000001 => c000000000000000 -+ fres. bfe00094e0000359 => bffff00000000000 -+ fres. 0000000000000000 => 7ff0000000000000 -+ fres. 8000000000000000 => fff0000000000000 -+ fres. 7ff0000000000000 => 0000000000000000 -+ fres. fff0000000000000 => 8000000000000000 -+ fres. 7ff7ffffffffffff => 7ffff00000000000 -+ fres. fff7ffffffffffff => fffff00000000000 -+ fres. 7ff8000000000000 => 7ff8000000000000 -+ fres. fff8000000000000 => fff8000000000000 -+ -+ frsqrte. 0010000000000001 => 5fdf000000000000 -+ frsqrte. 00100094e0000359 => 5fdf000000000000 -+ frsqrte. 3fe0000000000001 => 3ff6000000000000 -+ frsqrte. 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte. 8010000000000001 => 7ff8000000000000 -+ frsqrte. 80100094e0000359 => 7ff8000000000000 -+ frsqrte. bfe0000000000001 => 7ff8000000000000 -+ frsqrte. bfe00094e0000359 => 7ff8000000000000 -+ frsqrte. 0000000000000000 => 7ff0000000000000 -+ frsqrte. 8000000000000000 => fff0000000000000 -+ frsqrte. 7ff0000000000000 => 0000000000000000 -+ frsqrte. fff0000000000000 => 7ff8000000000000 -+ frsqrte. 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte. fff7ffffffffffff => ffff000000000000 -+ frsqrte. 7ff8000000000000 => 7ff8000000000000 -+ frsqrte. fff8000000000000 => fff8000000000000 -+ -+ frsp. 0010000000000001 => 0000000000000000 -+ frsp. 00100094e0000359 => 0000000000000000 -+ frsp. 3fe0000000000001 => 3fe0000000000000 -+ frsp. 3fe00094e0000359 => 3fe00094e0000000 -+ frsp. 8010000000000001 => 8000000000000000 -+ frsp. 80100094e0000359 => 8000000000000000 -+ frsp. bfe0000000000001 => bfe0000000000000 -+ frsp. bfe00094e0000359 => bfe00094e0000000 -+ frsp. 0000000000000000 => 0000000000000000 -+ frsp. 8000000000000000 => 8000000000000000 -+ frsp. 7ff0000000000000 => 7ff0000000000000 -+ frsp. fff0000000000000 => fff0000000000000 -+ frsp. 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp. fff7ffffffffffff => ffffffffe0000000 -+ frsp. 7ff8000000000000 => 7ff8000000000000 -+ frsp. fff8000000000000 => fff8000000000000 -+ -+ fctiw. 0010000000000001 => 0000000000000000 -+ fctiw. 00100094e0000359 => 0000000000000000 -+ fctiw. 3fe0000000000001 => 0000000000000001 -+ fctiw. 3fe00094e0000359 => 0000000000000001 -+ fctiw. 8010000000000001 => 0000000000000000 -+ fctiw. 80100094e0000359 => 0000000000000000 -+ fctiw. bfe0000000000001 => 00000000ffffffff -+ fctiw. bfe00094e0000359 => 00000000ffffffff -+ fctiw. 0000000000000000 => 0000000000000000 -+ fctiw. 8000000000000000 => 0000000000000000 -+ fctiw. 7ff0000000000000 => 000000007fffffff -+ fctiw. fff0000000000000 => 0000000080000000 -+ fctiw. 7ff7ffffffffffff => 0000000080000000 -+ fctiw. fff7ffffffffffff => 0000000080000000 -+ fctiw. 7ff8000000000000 => 0000000080000000 -+ fctiw. fff8000000000000 => 0000000080000000 -+ -+ fctiwz. 0010000000000001 => 0000000000000000 -+ fctiwz. 00100094e0000359 => 0000000000000000 -+ fctiwz. 3fe0000000000001 => 0000000000000000 -+ fctiwz. 3fe00094e0000359 => 0000000000000000 -+ fctiwz. 8010000000000001 => 0000000000000000 -+ fctiwz. 80100094e0000359 => 0000000000000000 -+ fctiwz. bfe0000000000001 => 0000000000000000 -+ fctiwz. bfe00094e0000359 => 0000000000000000 -+ fctiwz. 0000000000000000 => 0000000000000000 -+ fctiwz. 8000000000000000 => 0000000000000000 -+ fctiwz. 7ff0000000000000 => 000000007fffffff -+ fctiwz. fff0000000000000 => 0000000080000000 -+ fctiwz. 7ff7ffffffffffff => 0000000080000000 -+ fctiwz. fff7ffffffffffff => 0000000080000000 -+ fctiwz. 7ff8000000000000 => 0000000080000000 -+ fctiwz. fff8000000000000 => 0000000080000000 -+ -+ fmr. 0010000000000001 => 0010000000000001 -+ fmr. 00100094e0000359 => 00100094e0000359 -+ fmr. 3fe0000000000001 => 3fe0000000000001 -+ fmr. 3fe00094e0000359 => 3fe00094e0000359 -+ fmr. 8010000000000001 => 8010000000000001 -+ fmr. 80100094e0000359 => 80100094e0000359 -+ fmr. bfe0000000000001 => bfe0000000000001 -+ fmr. bfe00094e0000359 => bfe00094e0000359 -+ fmr. 0000000000000000 => 0000000000000000 -+ fmr. 8000000000000000 => 8000000000000000 -+ fmr. 7ff0000000000000 => 7ff0000000000000 -+ fmr. fff0000000000000 => fff0000000000000 -+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr. fff7ffffffffffff => fff7ffffffffffff -+ fmr. 7ff8000000000000 => 7ff8000000000000 -+ fmr. fff8000000000000 => fff8000000000000 -+ -+ fneg. 0010000000000001 => 8010000000000001 -+ fneg. 00100094e0000359 => 80100094e0000359 -+ fneg. 3fe0000000000001 => bfe0000000000001 -+ fneg. 3fe00094e0000359 => bfe00094e0000359 -+ fneg. 8010000000000001 => 0010000000000001 -+ fneg. 80100094e0000359 => 00100094e0000359 -+ fneg. bfe0000000000001 => 3fe0000000000001 -+ fneg. bfe00094e0000359 => 3fe00094e0000359 -+ fneg. 0000000000000000 => 8000000000000000 -+ fneg. 8000000000000000 => 0000000000000000 -+ fneg. 7ff0000000000000 => fff0000000000000 -+ fneg. fff0000000000000 => 7ff0000000000000 -+ fneg. 7ff7ffffffffffff => fff7ffffffffffff -+ fneg. fff7ffffffffffff => 7ff7ffffffffffff -+ fneg. 7ff8000000000000 => fff8000000000000 -+ fneg. fff8000000000000 => 7ff8000000000000 -+ -+ fabs. 0010000000000001 => 0010000000000001 -+ fabs. 00100094e0000359 => 00100094e0000359 -+ fabs. 3fe0000000000001 => 3fe0000000000001 -+ fabs. 3fe00094e0000359 => 3fe00094e0000359 -+ fabs. 8010000000000001 => 0010000000000001 -+ fabs. 80100094e0000359 => 00100094e0000359 -+ fabs. bfe0000000000001 => 3fe0000000000001 -+ fabs. bfe00094e0000359 => 3fe00094e0000359 -+ fabs. 0000000000000000 => 0000000000000000 -+ fabs. 8000000000000000 => 0000000000000000 -+ fabs. 7ff0000000000000 => 7ff0000000000000 -+ fabs. fff0000000000000 => 7ff0000000000000 -+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs. fff7ffffffffffff => 7ff7ffffffffffff -+ fabs. 7ff8000000000000 => 7ff8000000000000 -+ fabs. fff8000000000000 => 7ff8000000000000 -+ -+ fnabs. 0010000000000001 => 8010000000000001 -+ fnabs. 00100094e0000359 => 80100094e0000359 -+ fnabs. 3fe0000000000001 => bfe0000000000001 -+ fnabs. 3fe00094e0000359 => bfe00094e0000359 -+ fnabs. 8010000000000001 => 8010000000000001 -+ fnabs. 80100094e0000359 => 80100094e0000359 -+ fnabs. bfe0000000000001 => bfe0000000000001 -+ fnabs. bfe00094e0000359 => bfe00094e0000359 -+ fnabs. 0000000000000000 => 8000000000000000 -+ fnabs. 8000000000000000 => 8000000000000000 -+ fnabs. 7ff0000000000000 => fff0000000000000 -+ fnabs. fff0000000000000 => fff0000000000000 -+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs. fff7ffffffffffff => fff7ffffffffffff -+ fnabs. 7ff8000000000000 => fff8000000000000 -+ fnabs. fff8000000000000 => fff8000000000000 -+ -+ fcfid. 0010000000000001 => 4330000000000001 -+ fcfid. 00100094e0000359 => 43300094e0000359 -+ fcfid. 3fe0000000000001 => 43cff00000000000 -+ fcfid. 3fe00094e0000359 => 43cff0004a700002 -+ fcfid. 8010000000000001 => c3dffc0000000000 -+ fcfid. 80100094e0000359 => c3dffbffdac7ffff -+ fcfid. bfe0000000000001 => c3d0080000000000 -+ fcfid. bfe00094e0000359 => c3d007ffdac7ffff -+ fcfid. 0000000000000000 => 0000000000000000 -+ fcfid. 8000000000000000 => c3e0000000000000 -+ fcfid. 7ff0000000000000 => 43dffc0000000000 -+ fcfid. fff0000000000000 => c330000000000000 -+ fcfid. 7ff7ffffffffffff => 43dffe0000000000 -+ fcfid. fff7ffffffffffff => c320000000000002 -+ fcfid. 7ff8000000000000 => 43dffe0000000000 -+ fcfid. fff8000000000000 => c320000000000000 -+ -+ fctid. 0010000000000001 => 0000000000000000 -+ fctid. 00100094e0000359 => 0000000000000000 -+ fctid. 3fe0000000000001 => 0000000000000001 -+ fctid. 3fe00094e0000359 => 0000000000000001 -+ fctid. 8010000000000001 => 0000000000000000 -+ fctid. 80100094e0000359 => 0000000000000000 -+ fctid. bfe0000000000001 => ffffffffffffffff -+ fctid. bfe00094e0000359 => ffffffffffffffff -+ fctid. 0000000000000000 => 0000000000000000 -+ fctid. 8000000000000000 => 0000000000000000 -+ fctid. 7ff0000000000000 => 7fffffffffffffff -+ fctid. fff0000000000000 => 8000000000000000 -+ fctid. 7ff7ffffffffffff => 8000000000000000 -+ fctid. fff7ffffffffffff => 8000000000000000 -+ fctid. 7ff8000000000000 => 8000000000000000 -+ fctid. fff8000000000000 => 8000000000000000 -+ -+ fctidz. 0010000000000001 => 0000000000000000 -+ fctidz. 00100094e0000359 => 0000000000000000 -+ fctidz. 3fe0000000000001 => 0000000000000000 -+ fctidz. 3fe00094e0000359 => 0000000000000000 -+ fctidz. 8010000000000001 => 0000000000000000 -+ fctidz. 80100094e0000359 => 0000000000000000 -+ fctidz. bfe0000000000001 => 0000000000000000 -+ fctidz. bfe00094e0000359 => 0000000000000000 -+ fctidz. 0000000000000000 => 0000000000000000 -+ fctidz. 8000000000000000 => 0000000000000000 -+ fctidz. 7ff0000000000000 => 7fffffffffffffff -+ fctidz. fff0000000000000 => 8000000000000000 -+ fctidz. 7ff7ffffffffffff => 8000000000000000 -+ fctidz. fff7ffffffffffff => 8000000000000000 -+ fctidz. 7ff8000000000000 => 8000000000000000 -+ fctidz. fff8000000000000 => 8000000000000000 -+ -+PPC floating point status register manipulation insns: -+PPC floating point status register manipulation insns -+ with flags update: -+PPC float load insns -+ with one register + one 16 bits immediate args with flags update: -+ lfs 0010000000000001, 65416 => 37e0000000000000, 0 -+ lfs 00100094e0000359, 65424 => 37e0009400000000, 0 -+ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0 -+ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0 -+ lfs 8010000000000001, 65448 => b7e0000000000000, 0 -+ lfs 80100094e0000359, 65456 => b7e0009400000000, 0 -+ lfs bfe0000000000001, 65464 => bffc000000000000, 0 -+ lfs bfe00094e0000359, 65472 => bffc001280000000, 0 -+ lfs 0000000000000000, 65480 => 0000000000000000, 0 -+ lfs 8000000000000000, 65488 => 8000000000000000, 0 -+ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0 -+ lfs fff0000000000000, 65504 => fffe000000000000, 0 -+ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0 -+ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0 -+ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0 -+ lfs 0010000000000001, 0 => 37e0000000000000, 0 -+ lfs 00100094e0000359, 8 => 37e0009400000000, 0 -+ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0 -+ lfs 3fe00094e0000359, 24 => 3ffc001280000000, 0 -+ lfs 8010000000000001, 32 => b7e0000000000000, 0 -+ lfs 80100094e0000359, 40 => b7e0009400000000, 0 -+ lfs bfe0000000000001, 48 => bffc000000000000, 0 -+ lfs bfe00094e0000359, 56 => bffc001280000000, 0 -+ lfs 0000000000000000, 64 => 0000000000000000, 0 -+ lfs 8000000000000000, 72 => 8000000000000000, 0 -+ lfs 7ff0000000000000, 80 => 7ffe000000000000, 0 -+ lfs fff0000000000000, 88 => fffe000000000000, 0 -+ lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0 -+ lfs fff7ffffffffffff, 104 => fffeffffe0000000, 0 -+ lfs 7ff8000000000000, 112 => 7fff000000000000, 0 -+ lfs fff8000000000000, 120 => ffff000000000000, 0 -+ -+ lfsu 0010000000000001, 65416 => 37e0000000000000, -120 -+ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112 -+ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104 -+ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96 -+ lfsu 8010000000000001, 65448 => b7e0000000000000, -88 -+ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80 -+ lfsu bfe0000000000001, 65464 => bffc000000000000, -72 -+ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64 -+ lfsu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfsu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40 -+ lfsu fff0000000000000, 65504 => fffe000000000000, -32 -+ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24 -+ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16 -+ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8 -+ lfsu 0010000000000001, 0 => 37e0000000000000, 0 -+ lfsu 00100094e0000359, 8 => 37e0009400000000, 8 -+ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16 -+ lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 24 -+ lfsu 8010000000000001, 32 => b7e0000000000000, 32 -+ lfsu 80100094e0000359, 40 => b7e0009400000000, 40 -+ lfsu bfe0000000000001, 48 => bffc000000000000, 48 -+ lfsu bfe00094e0000359, 56 => bffc001280000000, 56 -+ lfsu 0000000000000000, 64 => 0000000000000000, 64 -+ lfsu 8000000000000000, 72 => 8000000000000000, 72 -+ lfsu 7ff0000000000000, 80 => 7ffe000000000000, 80 -+ lfsu fff0000000000000, 88 => fffe000000000000, 88 -+ lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96 -+ lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 104 -+ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112 -+ lfsu fff8000000000000, 120 => ffff000000000000, 120 -+ -+ lfd 0010000000000001, 65416 => 0010000000000001, 0 -+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 65448 => 8010000000000001, 0 -+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 65480 => 0000000000000000, 0 -+ lfd 8000000000000000, 65488 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 65504 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0 -+ lfd 0010000000000001, 0 => 0010000000000001, 0 -+ lfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 32 => 8010000000000001, 0 -+ lfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 64 => 0000000000000000, 0 -+ lfd 8000000000000000, 72 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 88 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdu 0010000000000001, 65416 => 0010000000000001, -120 -+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112 -+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104 -+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96 -+ lfdu 8010000000000001, 65448 => 8010000000000001, -88 -+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80 -+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72 -+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64 -+ lfdu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfdu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40 -+ lfdu fff0000000000000, 65504 => fff0000000000000, -32 -+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24 -+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16 -+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8 -+ lfdu 0010000000000001, 0 => 0010000000000001, 0 -+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdu 8010000000000001, 32 => 8010000000000001, 32 -+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdu 0000000000000000, 64 => 0000000000000000, 64 -+ lfdu 8000000000000000, 72 => 8000000000000000, 72 -+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdu fff0000000000000, 88 => fff0000000000000, 88 -+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float load insns with two register args: -+ lfsx 0010000000000001, -120 => 37e0000000000000, 0 -+ lfsx 00100094e0000359, -112 => 37e0009400000000, 0 -+ lfsx 3fe0000000000001, -104 => 3ffc000000000000, 0 -+ lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 0 -+ lfsx 8010000000000001, -88 => b7e0000000000000, 0 -+ lfsx 80100094e0000359, -80 => b7e0009400000000, 0 -+ lfsx bfe0000000000001, -72 => bffc000000000000, 0 -+ lfsx bfe00094e0000359, -64 => bffc001280000000, 0 -+ lfsx 0000000000000000, -56 => 0000000000000000, 0 -+ lfsx 8000000000000000, -48 => 8000000000000000, 0 -+ lfsx 7ff0000000000000, -40 => 7ffe000000000000, 0 -+ lfsx fff0000000000000, -32 => fffe000000000000, 0 -+ lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0 -+ lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 0 -+ lfsx 7ff8000000000000, -8 => 7fff000000000000, 0 -+ lfsx 0010000000000001, 0 => 37e0000000000000, 0 -+ lfsx 00100094e0000359, 8 => 37e0009400000000, 0 -+ lfsx 3fe0000000000001, 16 => 3ffc000000000000, 0 -+ lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 0 -+ lfsx 8010000000000001, 32 => b7e0000000000000, 0 -+ lfsx 80100094e0000359, 40 => b7e0009400000000, 0 -+ lfsx bfe0000000000001, 48 => bffc000000000000, 0 -+ lfsx bfe00094e0000359, 56 => bffc001280000000, 0 -+ lfsx 0000000000000000, 64 => 0000000000000000, 0 -+ lfsx 8000000000000000, 72 => 8000000000000000, 0 -+ lfsx 7ff0000000000000, 80 => 7ffe000000000000, 0 -+ lfsx fff0000000000000, 88 => fffe000000000000, 0 -+ lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0 -+ lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 0 -+ lfsx 7ff8000000000000, 112 => 7fff000000000000, 0 -+ lfsx fff8000000000000, 120 => ffff000000000000, 0 -+ -+ lfsux 0010000000000001, -120 => 37e0000000000000, -120 -+ lfsux 00100094e0000359, -112 => 37e0009400000000, -112 -+ lfsux 3fe0000000000001, -104 => 3ffc000000000000, -104 -+ lfsux 3fe00094e0000359, -96 => 3ffc001280000000, -96 -+ lfsux 8010000000000001, -88 => b7e0000000000000, -88 -+ lfsux 80100094e0000359, -80 => b7e0009400000000, -80 -+ lfsux bfe0000000000001, -72 => bffc000000000000, -72 -+ lfsux bfe00094e0000359, -64 => bffc001280000000, -64 -+ lfsux 0000000000000000, -56 => 0000000000000000, -56 -+ lfsux 8000000000000000, -48 => 8000000000000000, -48 -+ lfsux 7ff0000000000000, -40 => 7ffe000000000000, -40 -+ lfsux fff0000000000000, -32 => fffe000000000000, -32 -+ lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24 -+ lfsux fff7ffffffffffff, -16 => fffeffffe0000000, -16 -+ lfsux 7ff8000000000000, -8 => 7fff000000000000, -8 -+ lfsux 0010000000000001, 0 => 37e0000000000000, 0 -+ lfsux 00100094e0000359, 8 => 37e0009400000000, 8 -+ lfsux 3fe0000000000001, 16 => 3ffc000000000000, 16 -+ lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 24 -+ lfsux 8010000000000001, 32 => b7e0000000000000, 32 -+ lfsux 80100094e0000359, 40 => b7e0009400000000, 40 -+ lfsux bfe0000000000001, 48 => bffc000000000000, 48 -+ lfsux bfe00094e0000359, 56 => bffc001280000000, 56 -+ lfsux 0000000000000000, 64 => 0000000000000000, 64 -+ lfsux 8000000000000000, 72 => 8000000000000000, 72 -+ lfsux 7ff0000000000000, 80 => 7ffe000000000000, 80 -+ lfsux fff0000000000000, 88 => fffe000000000000, 88 -+ lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96 -+ lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 104 -+ lfsux 7ff8000000000000, 112 => 7fff000000000000, 112 -+ lfsux fff8000000000000, 120 => ffff000000000000, 120 -+ -+ lfdx 0010000000000001, -120 => 0010000000000001, 0 -+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, -88 => 8010000000000001, 0 -+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, -56 => 0000000000000000, 0 -+ lfdx 8000000000000000, -48 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, -32 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ lfdx 0010000000000001, 0 => 0010000000000001, 0 -+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, 32 => 8010000000000001, 0 -+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, 64 => 0000000000000000, 0 -+ lfdx 8000000000000000, 72 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, 88 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdux 0010000000000001, -120 => 0010000000000001, -120 -+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112 -+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ lfdux 8010000000000001, -88 => 8010000000000001, -88 -+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80 -+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72 -+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ lfdux 0000000000000000, -56 => 0000000000000000, -56 -+ lfdux 8000000000000000, -48 => 8000000000000000, -48 -+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ lfdux fff0000000000000, -32 => fff0000000000000, -32 -+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ lfdux 0010000000000001, 0 => 0010000000000001, 0 -+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdux 8010000000000001, 32 => 8010000000000001, 32 -+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdux 0000000000000000, 64 => 0000000000000000, 64 -+ lfdux 8000000000000000, 72 => 8000000000000000, 72 -+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdux fff0000000000000, 88 => fff0000000000000, 88 -+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns -+ with one register + one 16 bits immediate args with flags update: -+ stfs 0010000000000001, -56 => 0000000000000000, 0 -+ stfs 00100094e0000359, -48 => 0000000000000000, 0 -+ stfs 3fe0000000000001, -40 => 3f00000000000000, 0 -+ stfs 3fe00094e0000359, -32 => 3f0004a700000000, 0 -+ stfs 8010000000000001, -24 => 8000000000000000, 0 -+ stfs 80100094e0000359, -16 => 8000000000000000, 0 -+ stfs bfe0000000000001, -8 => bf00000000000000, 0 -+ stfs 0010000000000001, 0 => 0000000000000000, 0 -+ stfs 00100094e0000359, 8 => 0000000000000000, 0 -+ stfs 3fe0000000000001, 16 => 3f00000000000000, 0 -+ stfs 3fe00094e0000359, 24 => 3f0004a700000000, 0 -+ stfs 8010000000000001, 32 => 8000000000000000, 0 -+ stfs 80100094e0000359, 40 => 8000000000000000, 0 -+ stfs bfe0000000000001, 48 => bf00000000000000, 0 -+ stfs bfe00094e0000359, 56 => bf0004a700000000, 0 -+ -+ stfsu 0010000000000001, -56 => 0000000000000000, -56 -+ stfsu 00100094e0000359, -48 => 0000000000000000, -48 -+ stfsu 3fe0000000000001, -40 => 3f00000000000000, -40 -+ stfsu 3fe00094e0000359, -32 => 3f0004a700000000, -32 -+ stfsu 8010000000000001, -24 => 8000000000000000, -24 -+ stfsu 80100094e0000359, -16 => 8000000000000000, -16 -+ stfsu bfe0000000000001, -8 => bf00000000000000, -8 -+ stfsu 0010000000000001, 0 => 0000000000000000, 0 -+ stfsu 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsu 3fe0000000000001, 16 => 3f00000000000000, 16 -+ stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 24 -+ stfsu 8010000000000001, 32 => 8000000000000000, 32 -+ stfsu 80100094e0000359, 40 => 8000000000000000, 40 -+ stfsu bfe0000000000001, 48 => bf00000000000000, 48 -+ stfsu bfe00094e0000359, 56 => bf0004a700000000, 56 -+ -+ stfd 0010000000000001, -120 => 0010000000000001, 0 -+ stfd 00100094e0000359, -112 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, -88 => 8010000000000001, 0 -+ stfd 80100094e0000359, -80 => 80100094e0000359, 0 -+ stfd bfe0000000000001, -72 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ stfd 0000000000000000, -56 => 0000000000000000, 0 -+ stfd 8000000000000000, -48 => 8000000000000000, 0 -+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ stfd fff0000000000000, -32 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ stfd 0010000000000001, 0 => 0010000000000001, 0 -+ stfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, 32 => 8010000000000001, 0 -+ stfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfd 0000000000000000, 64 => 0000000000000000, 0 -+ stfd 8000000000000000, 72 => 8000000000000000, 0 -+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfd fff0000000000000, 88 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdu 0010000000000001, -120 => 0010000000000001, -120 -+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112 -+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ stfdu 8010000000000001, -88 => 8010000000000001, -88 -+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80 -+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72 -+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ stfdu 0000000000000000, -56 => 0000000000000000, -56 -+ stfdu 8000000000000000, -48 => 8000000000000000, -48 -+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ stfdu fff0000000000000, -32 => fff0000000000000, -32 -+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ stfdu 0010000000000001, 0 => 0010000000000001, 0 -+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdu 8010000000000001, 32 => 8010000000000001, 32 -+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdu 0000000000000000, 64 => 0000000000000000, 64 -+ stfdu 8000000000000000, 72 => 8000000000000000, 72 -+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdu fff0000000000000, 88 => fff0000000000000, 88 -+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns with three register args: -+ stfsx 0010000000000001, 0 => 0000000000000000, 0 -+ stfsx 00100094e0000359, 8 => 0000000000000000, 0 -+ stfsx 3fe0000000000001, 16 => 3f00000000000000, 0 -+ stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 0 -+ stfsx 8010000000000001, 32 => 8000000000000000, 0 -+ stfsx 80100094e0000359, 40 => 8000000000000000, 0 -+ stfsx bfe0000000000001, 48 => bf00000000000000, 0 -+ stfsx bfe00094e0000359, 56 => bf0004a700000000, 0 -+ -+ stfsux 0010000000000001, 0 => 0000000000000000, 0 -+ stfsux 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsux 3fe0000000000001, 16 => 3f00000000000000, 16 -+ stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 24 -+ stfsux 8010000000000001, 32 => 8000000000000000, 32 -+ stfsux 80100094e0000359, 40 => 8000000000000000, 40 -+ stfsux bfe0000000000001, 48 => bf00000000000000, 48 -+ stfsux bfe00094e0000359, 56 => bf0004a700000000, 56 -+ -+ stfdx 0010000000000001, 0 => 0010000000000001, 0 -+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfdx 8010000000000001, 32 => 8010000000000001, 0 -+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfdx 0000000000000000, 64 => 0000000000000000, 0 -+ stfdx 8000000000000000, 72 => 8000000000000000, 0 -+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfdx fff0000000000000, 88 => fff0000000000000, 0 -+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdux 0010000000000001, 0 => 0010000000000001, 0 -+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdux 8010000000000001, 32 => 8010000000000001, 32 -+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdux 0000000000000000, 64 => 0000000000000000, 64 -+ stfdux 8000000000000000, 72 => 8000000000000000, 72 -+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdux fff0000000000000, 88 => fff0000000000000, 88 -+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+All done. Tested 77 different instructions -Index: none/tests/ppc64/round.stdout.exp-RM-fix -=================================================================== ---- /dev/null -+++ none/tests/ppc64/round.stdout.exp-RM-fix -@@ -0,0 +1,2384 @@ -+-------------------------- test denormalized convert -------------------------- -+near:PASSED:(double)(0x1p-148 ) = 0x1.cp-149 -+near:PASSED:(double)(0x1p-149 ) = 0x1.4p-149 -+zero:PASSED:(double)(0x1p-149 ) = 0x1.cp-149 -+zero:PASSED:(double)(0x1p-149 ) = 0x1.4p-149 -++inf:PASSED:(double)(0x1p-148 ) = 0x1.cp-149 -++inf:PASSED:(double)(0x1p-148 ) = 0x1.4p-149 -+-inf:PASSED:(double)(0x1p-149 ) = 0x1.cp-149 -+-inf:PASSED:(double)(0x1p-149 ) = 0x1.4p-149 -+-------------------------- test normalized convert -------------------------- -+near:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126 -+near:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126 -+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126 -+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126 -++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126 -++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000028p-126 -+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126 -+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126 -+-------------------------- test (float)int convert -------------------------- -+near:PASSED:(float)( int) 67047421 = 67047420.0 -+near:PASSED:(float)(long) 67047421 = 67047420.0 -+near:PASSED:(float)( int) 67047423 = 67047424.0 -+near:PASSED:(float)(long) 67047423 = 67047424.0 -+zero:PASSED:(float)( int) 67047421 = 67047420.0 -+zero:PASSED:(float)(long) 67047421 = 67047420.0 -+zero:PASSED:(float)( int) 67047423 = 67047420.0 -+zero:PASSED:(float)(long) 67047423 = 67047420.0 -++inf:PASSED:(float)( int) 67047421 = 67047424.0 -++inf:PASSED:(float)(long) 67047421 = 67047424.0 -++inf:PASSED:(float)( int) 67047423 = 67047424.0 -++inf:PASSED:(float)(long) 67047423 = 67047424.0 -+-inf:PASSED:(float)( int) 67047421 = 67047420.0 -+-inf:PASSED:(float)(long) 67047421 = 67047420.0 -+-inf:PASSED:(float)( int) 67047423 = 67047420.0 -+-inf:PASSED:(float)(long) 67047423 = 67047420.0 -+near:PASSED:(float)( int)-67047421 = -67047420.0 -+near:PASSED:(float)(long)-67047421 = -67047420.0 -+near:PASSED:(float)( int)-67047423 = -67047424.0 -+near:PASSED:(float)(long)-67047423 = -67047424.0 -+zero:PASSED:(float)( int)-67047421 = -67047420.0 -+zero:PASSED:(float)(long)-67047421 = -67047420.0 -+zero:PASSED:(float)( int)-67047423 = -67047420.0 -+zero:PASSED:(float)(long)-67047423 = -67047420.0 -++inf:PASSED:(float)( int)-67047421 = -67047420.0 -++inf:PASSED:(float)(long)-67047421 = -67047420.0 -++inf:PASSED:(float)( int)-67047423 = -67047420.0 -++inf:PASSED:(float)(long)-67047423 = -67047420.0 -+-inf:PASSED:(float)( int)-67047421 = -67047424.0 -+-inf:PASSED:(float)(long)-67047421 = -67047424.0 -+-inf:PASSED:(float)( int)-67047423 = -67047424.0 -+-inf:PASSED:(float)(long)-67047423 = -67047424.0 -+-------------------------- test (float)int convert -------------------------- -+near:PASSED:(float)( int) 67047421 = 67047420.0 -+near:PASSED:(float)(long) 67047421 = 67047420.0 -+near:PASSED:(float)( int) 67047423 = 67047424.0 -+near:PASSED:(float)(long) 67047423 = 67047424.0 -+zero:PASSED:(float)( int) 67047421 = 67047420.0 -+zero:PASSED:(float)(long) 67047421 = 67047420.0 -+zero:PASSED:(float)( int) 67047423 = 67047420.0 -+zero:PASSED:(float)(long) 67047423 = 67047420.0 -++inf:PASSED:(float)( int) 67047421 = 67047424.0 -++inf:PASSED:(float)(long) 67047421 = 67047424.0 -++inf:PASSED:(float)( int) 67047423 = 67047424.0 -++inf:PASSED:(float)(long) 67047423 = 67047424.0 -+-inf:PASSED:(float)( int) 67047421 = 67047420.0 -+-inf:PASSED:(float)(long) 67047421 = 67047420.0 -+-inf:PASSED:(float)( int) 67047423 = 67047420.0 -+-inf:PASSED:(float)(long) 67047423 = 67047420.0 -+near:PASSED:(float)( int)-67047421 = -67047420.0 -+near:PASSED:(float)(long)-67047421 = -67047420.0 -+near:PASSED:(float)( int)-67047423 = -67047424.0 -+near:PASSED:(float)(long)-67047423 = -67047424.0 -+zero:PASSED:(float)( int)-67047421 = -67047420.0 -+zero:PASSED:(float)(long)-67047421 = -67047420.0 -+zero:PASSED:(float)( int)-67047423 = -67047420.0 -+zero:PASSED:(float)(long)-67047423 = -67047420.0 -++inf:PASSED:(float)( int)-67047421 = -67047420.0 -++inf:PASSED:(float)(long)-67047421 = -67047420.0 -++inf:PASSED:(float)( int)-67047423 = -67047420.0 -++inf:PASSED:(float)(long)-67047423 = -67047420.0 -+-inf:PASSED:(float)( int)-67047421 = -67047424.0 -+-inf:PASSED:(float)(long)-67047421 = -67047424.0 -+-inf:PASSED:(float)( int)-67047423 = -67047424.0 -+-inf:PASSED:(float)(long)-67047423 = -67047424.0 -+-------------------------- test (double)long convert -------------------------- -+near:PASSED:(double)( 36012304344547325) = 36012304344547324.0 -+near:PASSED:(double)( 36012304344547327) = 36012304344547328.0 -+zero:PASSED:(double)( 36012304344547325) = 36012304344547324.0 -+zero:PASSED:(double)( 36012304344547327) = 36012304344547324.0 -++inf:PASSED:(double)( 36012304344547325) = 36012304344547328.0 -++inf:PASSED:(double)( 36012304344547327) = 36012304344547328.0 -+-inf:PASSED:(double)( 36012304344547325) = 36012304344547324.0 -+-inf:PASSED:(double)( 36012304344547327) = 36012304344547324.0 -+near:PASSED:(double)(-36012304344547325) = -36012304344547324.0 -+near:PASSED:(double)(-36012304344547327) = -36012304344547328.0 -+zero:PASSED:(double)(-36012304344547325) = -36012304344547324.0 -+zero:PASSED:(double)(-36012304344547327) = -36012304344547324.0 -++inf:PASSED:(double)(-36012304344547325) = -36012304344547324.0 -++inf:PASSED:(double)(-36012304344547327) = -36012304344547324.0 -+-inf:PASSED:(double)(-36012304344547325) = -36012304344547328.0 -+-inf:PASSED:(double)(-36012304344547327) = -36012304344547328.0 -+-------------------------- test rounding of float operators without guard bits -------------------------- -+near:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149 -+near:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148 -+near:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149 -+near:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148 -+zero:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149 -+zero:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149 -+zero:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149 -+zero:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149 -++inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149 -++inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149 -++inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-148 -++inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148 -+-inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-148 -+-inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148 -+-inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149 -+-inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149 -+near:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149 -+near:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148 -+near:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149 -+near:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148 -+zero:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149 -+zero:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149 -+zero:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149 -+zero:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149 -++inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149 -++inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149 -++inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-148 -++inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148 -+-inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-148 -+-inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148 -+-inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149 -+-inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149 -+near:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149 -+near:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148 -+near:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149 -+near:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148 -+zero:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149 -+zero:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149 -+zero:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149 -+zero:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149 -++inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149 -++inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149 -++inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-148 -++inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148 -+-inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-148 -+-inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148 -+-inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149 -+-inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149 -+near:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149 -+near:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148 -+near:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149 -+near:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148 -+zero:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149 -+zero:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149 -+zero:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149 -+zero:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149 -++inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149 -++inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149 -++inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-148 -++inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148 -+-inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-148 -+-inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148 -+-inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149 -+-inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149 -+-------------------------- test rounding of float operators with guard bits -------------------------- -+near:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0 -+zero:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0 -++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0 -+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0 -+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0 -+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0 -+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0 -++inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0 -+-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+near:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+near:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+near:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+near:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+near:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+near:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+near:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+near:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+near:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+near:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+near:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+near:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+near:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148 -+near:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148 -+near:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0 -++inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0 -++inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -++inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec6p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92494p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+-inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f8p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+-inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+-inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+-------------------------- test rounding of double operators with guard bits -------------------------- -+near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0 -+near:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -+near:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0 -+near:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -+near:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -+near:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -+near:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -+near:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -+near:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0 -+near:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -+near:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0 -+near:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -+near:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -+near:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -+near:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -+near:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -+near:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0 -+near:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -+near:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0 -+near:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -+near:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -+near:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -+near:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -+near:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -+near:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0 -+near:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -+near:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0 -+near:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -+near:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -+near:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -+near:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -+near:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -+near:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0 -+zero:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -+zero:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0 -+zero:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -+zero:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -+zero:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -+zero:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0 -+zero:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -+zero:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -+zero:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -+zero:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0 -+zero:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -+zero:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -+zero:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0 -+zero:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -+zero:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -+zero:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -+zero:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -+zero:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0 -+zero:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -+zero:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -+zero:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -+zero:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0 -+zero:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -+zero:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -+zero:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -+zero:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0 -+zero:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -+zero:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -+zero:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0 -+zero:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -+zero:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -+zero:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -++inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -++inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0 -++inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -++inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -++inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -++inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0 -++inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -++inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -++inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -++inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0 -++inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -++inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -++inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0 -++inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -++inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -++inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -++inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -++inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -++inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -++inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -++inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0 -++inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -++inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -++inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0 -++inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -++inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -++inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -++inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0 -++inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -++inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -++inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -++inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0 -+-inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -+-inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -+-inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -+-inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -+-inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0 -+-inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -+-inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -+-inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0 -+-inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -+-inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -+-inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -+-inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0 -+-inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -+-inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -+-inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -+-inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0 -+-inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -+-inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0 -+-inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -+-inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -+-inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -+-inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0 -+-inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -+-inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -+-inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -+-inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0 -+-inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -+-inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -+-inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0 -+-inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -+-inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -+-inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -+-62/62 -+near:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -+near:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0 -+-66/62 -+near:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0 -+-100/62 -+near:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0 -+near:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0 -+-102/62 -+near:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0 -+-106/62 -+near:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0 -+-108/62 -+near:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0 -+-108/108 -+near:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -+near:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0 -+-114/62 -+near:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0 -+-116/62 -+near:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0 -+near:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022 -+-118/62 -+near:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0 -+-90/62 -+near:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0 -+-92/62 -+near:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0 -+62/62 -+near:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -+near:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0 -+66/62 -+near:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0 -+100/62 -+near:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0 -+near:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0 -+102/62 -+near:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0 -+106/62 -+near:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0 -+108/62 -+near:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0 -+108/108 -+near:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -+near:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0 -+114/62 -+near:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0 -+116/62 -+near:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0 -+near:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022 -+118/62 -+near:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0 -+90/62 -+near:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0 -+92/62 -+near:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0 -+-62/62 -+zero:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -+zero:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0 -+-66/62 -+zero:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0 -+-100/62 -+zero:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0 -+zero:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0 -+-102/62 -+zero:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0 -+-106/62 -+zero:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0 -+-108/62 -+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0 -+-108/108 -+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -+zero:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0 -+-114/62 -+zero:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0 -+-116/62 -+zero:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0 -+zero:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022 -+-118/62 -+zero:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0 -+-90/62 -+zero:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0 -+-92/62 -+zero:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0 -+62/62 -+zero:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -+zero:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0 -+66/62 -+zero:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0 -+100/62 -+zero:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0 -+zero:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0 -+102/62 -+zero:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0 -+106/62 -+zero:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0 -+108/62 -+zero:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0 -+108/108 -+zero:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -+zero:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0 -+114/62 -+zero:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0 -+116/62 -+zero:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0 -+zero:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022 -+118/62 -+zero:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0 -+90/62 -+zero:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0 -+92/62 -+zero:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0 -+-62/62 -++inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -++inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0 -+-66/62 -++inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0 -+-100/62 -++inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0 -++inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0 -+-102/62 -++inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0 -+-106/62 -++inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0 -+-108/62 -++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0 -+-108/108 -++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -++inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0 -+-114/62 -++inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0 -+-116/62 -++inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0 -++inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022 -+-118/62 -++inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0 -+-90/62 -++inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0 -+-92/62 -++inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0 -+62/62 -++inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -++inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421085p+0 -+66/62 -++inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842109p+0 -+100/62 -++inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cfp+0 -++inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022 -+102/62 -++inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0 -+106/62 -++inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0 -+108/62 -++inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0 -+108/108 -++inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -++inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce8p+0 -+114/62 -++inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6cp+0 -+116/62 -++inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdfp+0 -++inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022 -+118/62 -++inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0 -+90/62 -++inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0 -+92/62 -++inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0 -+-62/62 -+-inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -+-inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421085p+0 -+-66/62 -+-inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842109p+0 -+-100/62 -+-inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cfp+0 -+-inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022 -+-102/62 -+-inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0 -+-106/62 -+-inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0 -+-108/62 -+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0 -+-108/108 -+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -+-inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce8p+0 -+-114/62 -+-inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6cp+0 -+-116/62 -+-inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdfp+0 -+-inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022 -+-118/62 -+-inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0 -+-90/62 -+-inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0 -+-92/62 -+-inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0 -+62/62 -+-inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -+-inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0 -+66/62 -+-inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0 -+100/62 -+-inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0 -+-inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0 -+102/62 -+-inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0 -+106/62 -+-inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0 -+108/62 -+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0 -+108/108 -+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -+-inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0 -+114/62 -+-inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0 -+116/62 -+-inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0 -+-inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022 -+118/62 -+-inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0 -+90/62 -+-inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0 -+92/62 -+-inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0 -+near:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -++inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -++inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -++inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -++inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -++inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+-inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+-inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+-inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+-inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+-inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+-inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -++inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -++inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -++inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -++inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -++inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+-inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+-inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+-inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+-inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+-inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+-inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -++inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -++inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -++inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -++inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -++inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+-inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+-inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+-inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+-inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+-inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -++inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -++inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -++inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -++inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -++inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+-inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+-inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+-inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+-inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+-inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1 -+near:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0 -+near:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0 -+near:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1 -+near:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0 -+near:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0 -+near:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1 -+near:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0 -+near:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1 -+near:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1 -+near:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0 -+near:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1 -+near:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1 -+near:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0 -+zero:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1 -+zero:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0 -+zero:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0 -+zero:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1 -+zero:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0 -+zero:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0 -+zero:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1 -+zero:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0 -+zero:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1 -+zero:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1 -+zero:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0 -+zero:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1 -+zero:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1 -+zero:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0 -++inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049fp-1 -++inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6ep+0 -++inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3cp+0 -++inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0938p-1 -++inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b3p+0 -++inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7484p+0 -++inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7dp-1 -++inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0 -++inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1 -++inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1 -++inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0 -++inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1 -++inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1 -++inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0 -+-inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1 -+-inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0 -+-inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0 -+-inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1 -+-inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0 -+-inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0 -+-inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1 -+-inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0 -+-inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1 -+-inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1 -+-inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0 -+-inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1 -+-inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1 -+-inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0 -Index: none/tests/ppc64/jm-fp.stdout.exp-LE2 -=================================================================== ---- /dev/null -+++ none/tests/ppc64/jm-fp.stdout.exp-LE2 -@@ -0,0 +1,1533 @@ -+PPC floating point arith insns with three args: -+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns -+ with three args with flags update: -+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns with two args: -+ fadd 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns -+ with two args with flags update: -+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point compare insns (two args): -+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns with one arg: -+ fres 0010000000000001 => 7ff0000000000000 -+ fres 00100094e0000359 => 7ff0000000000000 -+ fres 3fe0000000000001 => 4000000000000000 -+ fres 3fe00094e0000359 => 3ffff00000000000 -+ fres 8010000000000001 => fff0000000000000 -+ fres 80100094e0000359 => fff0000000000000 -+ fres bfe0000000000001 => c000000000000000 -+ fres bfe00094e0000359 => bffff00000000000 -+ fres 0000000000000000 => 7ff0000000000000 -+ fres 8000000000000000 => fff0000000000000 -+ fres 7ff0000000000000 => 0000000000000000 -+ fres fff0000000000000 => 8000000000000000 -+ fres 7ff7ffffffffffff => 7ffff00000000000 -+ fres fff7ffffffffffff => fffff00000000000 -+ fres 7ff8000000000000 => 7ff8000000000000 -+ fres fff8000000000000 => fff8000000000000 -+ -+ frsqrte 0010000000000001 => 5fdf000000000000 -+ frsqrte 00100094e0000359 => 5fdf000000000000 -+ frsqrte 3fe0000000000001 => 3ff6000000000000 -+ frsqrte 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte 8010000000000001 => 7ff8000000000000 -+ frsqrte 80100094e0000359 => 7ff8000000000000 -+ frsqrte bfe0000000000001 => 7ff8000000000000 -+ frsqrte bfe00094e0000359 => 7ff8000000000000 -+ frsqrte 0000000000000000 => 7ff0000000000000 -+ frsqrte 8000000000000000 => fff0000000000000 -+ frsqrte 7ff0000000000000 => 0000000000000000 -+ frsqrte fff0000000000000 => 7ff8000000000000 -+ frsqrte 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte fff7ffffffffffff => ffff000000000000 -+ frsqrte 7ff8000000000000 => 7ff8000000000000 -+ frsqrte fff8000000000000 => fff8000000000000 -+ -+ frsp 0010000000000001 => 0000000000000000 -+ frsp 00100094e0000359 => 0000000000000000 -+ frsp 3fe0000000000001 => 3fe0000000000000 -+ frsp 3fe00094e0000359 => 3fe00094e0000000 -+ frsp 8010000000000001 => 8000000000000000 -+ frsp 80100094e0000359 => 8000000000000000 -+ frsp bfe0000000000001 => bfe0000000000000 -+ frsp bfe00094e0000359 => bfe00094e0000000 -+ frsp 0000000000000000 => 0000000000000000 -+ frsp 8000000000000000 => 8000000000000000 -+ frsp 7ff0000000000000 => 7ff0000000000000 -+ frsp fff0000000000000 => fff0000000000000 -+ frsp 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp fff7ffffffffffff => ffffffffe0000000 -+ frsp 7ff8000000000000 => 7ff8000000000000 -+ frsp fff8000000000000 => fff8000000000000 -+ -+ fctiw 0010000000000001 => 0000000000000000 -+ fctiw 00100094e0000359 => 0000000000000000 -+ fctiw 3fe0000000000001 => 0000000000000001 -+ fctiw 3fe00094e0000359 => 0000000000000001 -+ fctiw 8010000000000001 => 0000000000000000 -+ fctiw 80100094e0000359 => 0000000000000000 -+ fctiw bfe0000000000001 => 00000000ffffffff -+ fctiw bfe00094e0000359 => 00000000ffffffff -+ fctiw 0000000000000000 => 0000000000000000 -+ fctiw 8000000000000000 => 0000000000000000 -+ fctiw 7ff0000000000000 => 000000007fffffff -+ fctiw fff0000000000000 => 0000000080000000 -+ fctiw 7ff7ffffffffffff => 0000000080000000 -+ fctiw fff7ffffffffffff => 0000000080000000 -+ fctiw 7ff8000000000000 => 0000000080000000 -+ fctiw fff8000000000000 => 0000000080000000 -+ -+ fctiwz 0010000000000001 => 0000000000000000 -+ fctiwz 00100094e0000359 => 0000000000000000 -+ fctiwz 3fe0000000000001 => 0000000000000000 -+ fctiwz 3fe00094e0000359 => 0000000000000000 -+ fctiwz 8010000000000001 => 0000000000000000 -+ fctiwz 80100094e0000359 => 0000000000000000 -+ fctiwz bfe0000000000001 => 0000000000000000 -+ fctiwz bfe00094e0000359 => 0000000000000000 -+ fctiwz 0000000000000000 => 0000000000000000 -+ fctiwz 8000000000000000 => 0000000000000000 -+ fctiwz 7ff0000000000000 => 000000007fffffff -+ fctiwz fff0000000000000 => 0000000080000000 -+ fctiwz 7ff7ffffffffffff => 0000000080000000 -+ fctiwz fff7ffffffffffff => 0000000080000000 -+ fctiwz 7ff8000000000000 => 0000000080000000 -+ fctiwz fff8000000000000 => 0000000080000000 -+ -+ fmr 0010000000000001 => 0010000000000001 -+ fmr 00100094e0000359 => 00100094e0000359 -+ fmr 3fe0000000000001 => 3fe0000000000001 -+ fmr 3fe00094e0000359 => 3fe00094e0000359 -+ fmr 8010000000000001 => 8010000000000001 -+ fmr 80100094e0000359 => 80100094e0000359 -+ fmr bfe0000000000001 => bfe0000000000001 -+ fmr bfe00094e0000359 => bfe00094e0000359 -+ fmr 0000000000000000 => 0000000000000000 -+ fmr 8000000000000000 => 8000000000000000 -+ fmr 7ff0000000000000 => 7ff0000000000000 -+ fmr fff0000000000000 => fff0000000000000 -+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr fff7ffffffffffff => fff7ffffffffffff -+ fmr 7ff8000000000000 => 7ff8000000000000 -+ fmr fff8000000000000 => fff8000000000000 -+ -+ fneg 0010000000000001 => 8010000000000001 -+ fneg 00100094e0000359 => 80100094e0000359 -+ fneg 3fe0000000000001 => bfe0000000000001 -+ fneg 3fe00094e0000359 => bfe00094e0000359 -+ fneg 8010000000000001 => 0010000000000001 -+ fneg 80100094e0000359 => 00100094e0000359 -+ fneg bfe0000000000001 => 3fe0000000000001 -+ fneg bfe00094e0000359 => 3fe00094e0000359 -+ fneg 0000000000000000 => 8000000000000000 -+ fneg 8000000000000000 => 0000000000000000 -+ fneg 7ff0000000000000 => fff0000000000000 -+ fneg fff0000000000000 => 7ff0000000000000 -+ fneg 7ff7ffffffffffff => fff7ffffffffffff -+ fneg fff7ffffffffffff => 7ff7ffffffffffff -+ fneg 7ff8000000000000 => fff8000000000000 -+ fneg fff8000000000000 => 7ff8000000000000 -+ -+ fabs 0010000000000001 => 0010000000000001 -+ fabs 00100094e0000359 => 00100094e0000359 -+ fabs 3fe0000000000001 => 3fe0000000000001 -+ fabs 3fe00094e0000359 => 3fe00094e0000359 -+ fabs 8010000000000001 => 0010000000000001 -+ fabs 80100094e0000359 => 00100094e0000359 -+ fabs bfe0000000000001 => 3fe0000000000001 -+ fabs bfe00094e0000359 => 3fe00094e0000359 -+ fabs 0000000000000000 => 0000000000000000 -+ fabs 8000000000000000 => 0000000000000000 -+ fabs 7ff0000000000000 => 7ff0000000000000 -+ fabs fff0000000000000 => 7ff0000000000000 -+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs fff7ffffffffffff => 7ff7ffffffffffff -+ fabs 7ff8000000000000 => 7ff8000000000000 -+ fabs fff8000000000000 => 7ff8000000000000 -+ -+ fnabs 0010000000000001 => 8010000000000001 -+ fnabs 00100094e0000359 => 80100094e0000359 -+ fnabs 3fe0000000000001 => bfe0000000000001 -+ fnabs 3fe00094e0000359 => bfe00094e0000359 -+ fnabs 8010000000000001 => 8010000000000001 -+ fnabs 80100094e0000359 => 80100094e0000359 -+ fnabs bfe0000000000001 => bfe0000000000001 -+ fnabs bfe00094e0000359 => bfe00094e0000359 -+ fnabs 0000000000000000 => 8000000000000000 -+ fnabs 8000000000000000 => 8000000000000000 -+ fnabs 7ff0000000000000 => fff0000000000000 -+ fnabs fff0000000000000 => fff0000000000000 -+ fnabs 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs fff7ffffffffffff => fff7ffffffffffff -+ fnabs 7ff8000000000000 => fff8000000000000 -+ fnabs fff8000000000000 => fff8000000000000 -+ -+ fsqrt 0010000000000001 => 2000000000000000 -+ fsqrt 00100094e0000359 => 2000004a6f52dd4a -+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd -+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df -+ fsqrt 8010000000000001 => 7ff8000000000000 -+ fsqrt 80100094e0000359 => 7ff8000000000000 -+ fsqrt bfe0000000000001 => 7ff8000000000000 -+ fsqrt bfe00094e0000359 => 7ff8000000000000 -+ fsqrt 0000000000000000 => 0000000000000000 -+ fsqrt 8000000000000000 => 8000000000000000 -+ fsqrt 7ff0000000000000 => 7ff0000000000000 -+ fsqrt fff0000000000000 => 7ff8000000000000 -+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff -+ fsqrt fff7ffffffffffff => ffffffffffffffff -+ fsqrt 7ff8000000000000 => 7ff8000000000000 -+ fsqrt fff8000000000000 => fff8000000000000 -+ -+ fcfid 0010000000000001 => 4330000000000001 -+ fcfid 00100094e0000359 => 43300094e0000359 -+ fcfid 3fe0000000000001 => 43cff00000000000 -+ fcfid 3fe00094e0000359 => 43cff0004a700002 -+ fcfid 8010000000000001 => c3dffc0000000000 -+ fcfid 80100094e0000359 => c3dffbffdac7ffff -+ fcfid bfe0000000000001 => c3d0080000000000 -+ fcfid bfe00094e0000359 => c3d007ffdac7ffff -+ fcfid 0000000000000000 => 0000000000000000 -+ fcfid 8000000000000000 => c3e0000000000000 -+ fcfid 7ff0000000000000 => 43dffc0000000000 -+ fcfid fff0000000000000 => c330000000000000 -+ fcfid 7ff7ffffffffffff => 43dffe0000000000 -+ fcfid fff7ffffffffffff => c320000000000002 -+ fcfid 7ff8000000000000 => 43dffe0000000000 -+ fcfid fff8000000000000 => c320000000000000 -+ -+ fctid 0010000000000001 => 0000000000000000 -+ fctid 00100094e0000359 => 0000000000000000 -+ fctid 3fe0000000000001 => 0000000000000001 -+ fctid 3fe00094e0000359 => 0000000000000001 -+ fctid 8010000000000001 => 0000000000000000 -+ fctid 80100094e0000359 => 0000000000000000 -+ fctid bfe0000000000001 => ffffffffffffffff -+ fctid bfe00094e0000359 => ffffffffffffffff -+ fctid 0000000000000000 => 0000000000000000 -+ fctid 8000000000000000 => 0000000000000000 -+ fctid 7ff0000000000000 => 7fffffffffffffff -+ fctid fff0000000000000 => 8000000000000000 -+ fctid 7ff7ffffffffffff => 8000000000000000 -+ fctid fff7ffffffffffff => 8000000000000000 -+ fctid 7ff8000000000000 => 8000000000000000 -+ fctid fff8000000000000 => 8000000000000000 -+ -+ fctidz 0010000000000001 => 0000000000000000 -+ fctidz 00100094e0000359 => 0000000000000000 -+ fctidz 3fe0000000000001 => 0000000000000000 -+ fctidz 3fe00094e0000359 => 0000000000000000 -+ fctidz 8010000000000001 => 0000000000000000 -+ fctidz 80100094e0000359 => 0000000000000000 -+ fctidz bfe0000000000001 => 0000000000000000 -+ fctidz bfe00094e0000359 => 0000000000000000 -+ fctidz 0000000000000000 => 0000000000000000 -+ fctidz 8000000000000000 => 0000000000000000 -+ fctidz 7ff0000000000000 => 7fffffffffffffff -+ fctidz fff0000000000000 => 8000000000000000 -+ fctidz 7ff7ffffffffffff => 8000000000000000 -+ fctidz fff7ffffffffffff => 8000000000000000 -+ fctidz 7ff8000000000000 => 8000000000000000 -+ fctidz fff8000000000000 => 8000000000000000 -+ -+PPC floating point arith insns -+ with one arg with flags update: -+ fres. 0010000000000001 => 7ff0000000000000 -+ fres. 00100094e0000359 => 7ff0000000000000 -+ fres. 3fe0000000000001 => 4000000000000000 -+ fres. 3fe00094e0000359 => 3ffff00000000000 -+ fres. 8010000000000001 => fff0000000000000 -+ fres. 80100094e0000359 => fff0000000000000 -+ fres. bfe0000000000001 => c000000000000000 -+ fres. bfe00094e0000359 => bffff00000000000 -+ fres. 0000000000000000 => 7ff0000000000000 -+ fres. 8000000000000000 => fff0000000000000 -+ fres. 7ff0000000000000 => 0000000000000000 -+ fres. fff0000000000000 => 8000000000000000 -+ fres. 7ff7ffffffffffff => 7ffff00000000000 -+ fres. fff7ffffffffffff => fffff00000000000 -+ fres. 7ff8000000000000 => 7ff8000000000000 -+ fres. fff8000000000000 => fff8000000000000 -+ -+ frsqrte. 0010000000000001 => 5fdf000000000000 -+ frsqrte. 00100094e0000359 => 5fdf000000000000 -+ frsqrte. 3fe0000000000001 => 3ff6000000000000 -+ frsqrte. 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte. 8010000000000001 => 7ff8000000000000 -+ frsqrte. 80100094e0000359 => 7ff8000000000000 -+ frsqrte. bfe0000000000001 => 7ff8000000000000 -+ frsqrte. bfe00094e0000359 => 7ff8000000000000 -+ frsqrte. 0000000000000000 => 7ff0000000000000 -+ frsqrte. 8000000000000000 => fff0000000000000 -+ frsqrte. 7ff0000000000000 => 0000000000000000 -+ frsqrte. fff0000000000000 => 7ff8000000000000 -+ frsqrte. 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte. fff7ffffffffffff => ffff000000000000 -+ frsqrte. 7ff8000000000000 => 7ff8000000000000 -+ frsqrte. fff8000000000000 => fff8000000000000 -+ -+ frsp. 0010000000000001 => 0000000000000000 -+ frsp. 00100094e0000359 => 0000000000000000 -+ frsp. 3fe0000000000001 => 3fe0000000000000 -+ frsp. 3fe00094e0000359 => 3fe00094e0000000 -+ frsp. 8010000000000001 => 8000000000000000 -+ frsp. 80100094e0000359 => 8000000000000000 -+ frsp. bfe0000000000001 => bfe0000000000000 -+ frsp. bfe00094e0000359 => bfe00094e0000000 -+ frsp. 0000000000000000 => 0000000000000000 -+ frsp. 8000000000000000 => 8000000000000000 -+ frsp. 7ff0000000000000 => 7ff0000000000000 -+ frsp. fff0000000000000 => fff0000000000000 -+ frsp. 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp. fff7ffffffffffff => ffffffffe0000000 -+ frsp. 7ff8000000000000 => 7ff8000000000000 -+ frsp. fff8000000000000 => fff8000000000000 -+ -+ fctiw. 0010000000000001 => 0000000000000000 -+ fctiw. 00100094e0000359 => 0000000000000000 -+ fctiw. 3fe0000000000001 => 0000000000000001 -+ fctiw. 3fe00094e0000359 => 0000000000000001 -+ fctiw. 8010000000000001 => 0000000000000000 -+ fctiw. 80100094e0000359 => 0000000000000000 -+ fctiw. bfe0000000000001 => 00000000ffffffff -+ fctiw. bfe00094e0000359 => 00000000ffffffff -+ fctiw. 0000000000000000 => 0000000000000000 -+ fctiw. 8000000000000000 => 0000000000000000 -+ fctiw. 7ff0000000000000 => 000000007fffffff -+ fctiw. fff0000000000000 => 0000000080000000 -+ fctiw. 7ff7ffffffffffff => 0000000080000000 -+ fctiw. fff7ffffffffffff => 0000000080000000 -+ fctiw. 7ff8000000000000 => 0000000080000000 -+ fctiw. fff8000000000000 => 0000000080000000 -+ -+ fctiwz. 0010000000000001 => 0000000000000000 -+ fctiwz. 00100094e0000359 => 0000000000000000 -+ fctiwz. 3fe0000000000001 => 0000000000000000 -+ fctiwz. 3fe00094e0000359 => 0000000000000000 -+ fctiwz. 8010000000000001 => 0000000000000000 -+ fctiwz. 80100094e0000359 => 0000000000000000 -+ fctiwz. bfe0000000000001 => 0000000000000000 -+ fctiwz. bfe00094e0000359 => 0000000000000000 -+ fctiwz. 0000000000000000 => 0000000000000000 -+ fctiwz. 8000000000000000 => 0000000000000000 -+ fctiwz. 7ff0000000000000 => 000000007fffffff -+ fctiwz. fff0000000000000 => 0000000080000000 -+ fctiwz. 7ff7ffffffffffff => 0000000080000000 -+ fctiwz. fff7ffffffffffff => 0000000080000000 -+ fctiwz. 7ff8000000000000 => 0000000080000000 -+ fctiwz. fff8000000000000 => 0000000080000000 -+ -+ fmr. 0010000000000001 => 0010000000000001 -+ fmr. 00100094e0000359 => 00100094e0000359 -+ fmr. 3fe0000000000001 => 3fe0000000000001 -+ fmr. 3fe00094e0000359 => 3fe00094e0000359 -+ fmr. 8010000000000001 => 8010000000000001 -+ fmr. 80100094e0000359 => 80100094e0000359 -+ fmr. bfe0000000000001 => bfe0000000000001 -+ fmr. bfe00094e0000359 => bfe00094e0000359 -+ fmr. 0000000000000000 => 0000000000000000 -+ fmr. 8000000000000000 => 8000000000000000 -+ fmr. 7ff0000000000000 => 7ff0000000000000 -+ fmr. fff0000000000000 => fff0000000000000 -+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr. fff7ffffffffffff => fff7ffffffffffff -+ fmr. 7ff8000000000000 => 7ff8000000000000 -+ fmr. fff8000000000000 => fff8000000000000 -+ -+ fneg. 0010000000000001 => 8010000000000001 -+ fneg. 00100094e0000359 => 80100094e0000359 -+ fneg. 3fe0000000000001 => bfe0000000000001 -+ fneg. 3fe00094e0000359 => bfe00094e0000359 -+ fneg. 8010000000000001 => 0010000000000001 -+ fneg. 80100094e0000359 => 00100094e0000359 -+ fneg. bfe0000000000001 => 3fe0000000000001 -+ fneg. bfe00094e0000359 => 3fe00094e0000359 -+ fneg. 0000000000000000 => 8000000000000000 -+ fneg. 8000000000000000 => 0000000000000000 -+ fneg. 7ff0000000000000 => fff0000000000000 -+ fneg. fff0000000000000 => 7ff0000000000000 -+ fneg. 7ff7ffffffffffff => fff7ffffffffffff -+ fneg. fff7ffffffffffff => 7ff7ffffffffffff -+ fneg. 7ff8000000000000 => fff8000000000000 -+ fneg. fff8000000000000 => 7ff8000000000000 -+ -+ fabs. 0010000000000001 => 0010000000000001 -+ fabs. 00100094e0000359 => 00100094e0000359 -+ fabs. 3fe0000000000001 => 3fe0000000000001 -+ fabs. 3fe00094e0000359 => 3fe00094e0000359 -+ fabs. 8010000000000001 => 0010000000000001 -+ fabs. 80100094e0000359 => 00100094e0000359 -+ fabs. bfe0000000000001 => 3fe0000000000001 -+ fabs. bfe00094e0000359 => 3fe00094e0000359 -+ fabs. 0000000000000000 => 0000000000000000 -+ fabs. 8000000000000000 => 0000000000000000 -+ fabs. 7ff0000000000000 => 7ff0000000000000 -+ fabs. fff0000000000000 => 7ff0000000000000 -+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs. fff7ffffffffffff => 7ff7ffffffffffff -+ fabs. 7ff8000000000000 => 7ff8000000000000 -+ fabs. fff8000000000000 => 7ff8000000000000 -+ -+ fnabs. 0010000000000001 => 8010000000000001 -+ fnabs. 00100094e0000359 => 80100094e0000359 -+ fnabs. 3fe0000000000001 => bfe0000000000001 -+ fnabs. 3fe00094e0000359 => bfe00094e0000359 -+ fnabs. 8010000000000001 => 8010000000000001 -+ fnabs. 80100094e0000359 => 80100094e0000359 -+ fnabs. bfe0000000000001 => bfe0000000000001 -+ fnabs. bfe00094e0000359 => bfe00094e0000359 -+ fnabs. 0000000000000000 => 8000000000000000 -+ fnabs. 8000000000000000 => 8000000000000000 -+ fnabs. 7ff0000000000000 => fff0000000000000 -+ fnabs. fff0000000000000 => fff0000000000000 -+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs. fff7ffffffffffff => fff7ffffffffffff -+ fnabs. 7ff8000000000000 => fff8000000000000 -+ fnabs. fff8000000000000 => fff8000000000000 -+ -+ fcfid. 0010000000000001 => 4330000000000001 -+ fcfid. 00100094e0000359 => 43300094e0000359 -+ fcfid. 3fe0000000000001 => 43cff00000000000 -+ fcfid. 3fe00094e0000359 => 43cff0004a700002 -+ fcfid. 8010000000000001 => c3dffc0000000000 -+ fcfid. 80100094e0000359 => c3dffbffdac7ffff -+ fcfid. bfe0000000000001 => c3d0080000000000 -+ fcfid. bfe00094e0000359 => c3d007ffdac7ffff -+ fcfid. 0000000000000000 => 0000000000000000 -+ fcfid. 8000000000000000 => c3e0000000000000 -+ fcfid. 7ff0000000000000 => 43dffc0000000000 -+ fcfid. fff0000000000000 => c330000000000000 -+ fcfid. 7ff7ffffffffffff => 43dffe0000000000 -+ fcfid. fff7ffffffffffff => c320000000000002 -+ fcfid. 7ff8000000000000 => 43dffe0000000000 -+ fcfid. fff8000000000000 => c320000000000000 -+ -+ fctid. 0010000000000001 => 0000000000000000 -+ fctid. 00100094e0000359 => 0000000000000000 -+ fctid. 3fe0000000000001 => 0000000000000001 -+ fctid. 3fe00094e0000359 => 0000000000000001 -+ fctid. 8010000000000001 => 0000000000000000 -+ fctid. 80100094e0000359 => 0000000000000000 -+ fctid. bfe0000000000001 => ffffffffffffffff -+ fctid. bfe00094e0000359 => ffffffffffffffff -+ fctid. 0000000000000000 => 0000000000000000 -+ fctid. 8000000000000000 => 0000000000000000 -+ fctid. 7ff0000000000000 => 7fffffffffffffff -+ fctid. fff0000000000000 => 8000000000000000 -+ fctid. 7ff7ffffffffffff => 8000000000000000 -+ fctid. fff7ffffffffffff => 8000000000000000 -+ fctid. 7ff8000000000000 => 8000000000000000 -+ fctid. fff8000000000000 => 8000000000000000 -+ -+ fctidz. 0010000000000001 => 0000000000000000 -+ fctidz. 00100094e0000359 => 0000000000000000 -+ fctidz. 3fe0000000000001 => 0000000000000000 -+ fctidz. 3fe00094e0000359 => 0000000000000000 -+ fctidz. 8010000000000001 => 0000000000000000 -+ fctidz. 80100094e0000359 => 0000000000000000 -+ fctidz. bfe0000000000001 => 0000000000000000 -+ fctidz. bfe00094e0000359 => 0000000000000000 -+ fctidz. 0000000000000000 => 0000000000000000 -+ fctidz. 8000000000000000 => 0000000000000000 -+ fctidz. 7ff0000000000000 => 7fffffffffffffff -+ fctidz. fff0000000000000 => 8000000000000000 -+ fctidz. 7ff7ffffffffffff => 8000000000000000 -+ fctidz. fff7ffffffffffff => 8000000000000000 -+ fctidz. 7ff8000000000000 => 8000000000000000 -+ fctidz. fff8000000000000 => 8000000000000000 -+ -+PPC floating point status register manipulation insns: -+PPC floating point status register manipulation insns -+ with flags update: -+PPC float load insns -+ with one register + one 16 bits immediate args with flags update: -+ lfs 0010000000000001, 65416 => 36a0000000000000, 0 -+ lfs 00100094e0000359, 65424 => c400006b20000000, 0 -+ lfs 3fe0000000000001, 65432 => 36a0000000000000, 0 -+ lfs 3fe00094e0000359, 65440 => c400006b20000000, 0 -+ lfs 8010000000000001, 65448 => 36a0000000000000, 0 -+ lfs 80100094e0000359, 65456 => c400006b20000000, 0 -+ lfs bfe0000000000001, 65464 => 36a0000000000000, 0 -+ lfs bfe00094e0000359, 65472 => c400006b20000000, 0 -+ lfs 0000000000000000, 65480 => 0000000000000000, 0 -+ lfs 8000000000000000, 65488 => 0000000000000000, 0 -+ lfs 7ff0000000000000, 65496 => 0000000000000000, 0 -+ lfs fff0000000000000, 65504 => 0000000000000000, 0 -+ lfs 7ff7ffffffffffff, 65512 => ffffffffe0000000, 0 -+ lfs fff7ffffffffffff, 65520 => ffffffffe0000000, 0 -+ lfs 7ff8000000000000, 65528 => 0000000000000000, 0 -+ lfs 0010000000000001, 0 => 36a0000000000000, 0 -+ lfs 00100094e0000359, 8 => c400006b20000000, 0 -+ lfs 3fe0000000000001, 16 => 36a0000000000000, 0 -+ lfs 3fe00094e0000359, 24 => c400006b20000000, 0 -+ lfs 8010000000000001, 32 => 36a0000000000000, 0 -+ lfs 80100094e0000359, 40 => c400006b20000000, 0 -+ lfs bfe0000000000001, 48 => 36a0000000000000, 0 -+ lfs bfe00094e0000359, 56 => c400006b20000000, 0 -+ lfs 0000000000000000, 64 => 0000000000000000, 0 -+ lfs 8000000000000000, 72 => 0000000000000000, 0 -+ lfs 7ff0000000000000, 80 => 0000000000000000, 0 -+ lfs fff0000000000000, 88 => 0000000000000000, 0 -+ lfs 7ff7ffffffffffff, 96 => ffffffffe0000000, 0 -+ lfs fff7ffffffffffff, 104 => ffffffffe0000000, 0 -+ lfs 7ff8000000000000, 112 => 0000000000000000, 0 -+ lfs fff8000000000000, 120 => 0000000000000000, 0 -+ -+ lfsu 0010000000000001, 65416 => 36a0000000000000, -120 -+ lfsu 00100094e0000359, 65424 => c400006b20000000, -112 -+ lfsu 3fe0000000000001, 65432 => 36a0000000000000, -104 -+ lfsu 3fe00094e0000359, 65440 => c400006b20000000, -96 -+ lfsu 8010000000000001, 65448 => 36a0000000000000, -88 -+ lfsu 80100094e0000359, 65456 => c400006b20000000, -80 -+ lfsu bfe0000000000001, 65464 => 36a0000000000000, -72 -+ lfsu bfe00094e0000359, 65472 => c400006b20000000, -64 -+ lfsu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfsu 8000000000000000, 65488 => 0000000000000000, -48 -+ lfsu 7ff0000000000000, 65496 => 0000000000000000, -40 -+ lfsu fff0000000000000, 65504 => 0000000000000000, -32 -+ lfsu 7ff7ffffffffffff, 65512 => ffffffffe0000000, -24 -+ lfsu fff7ffffffffffff, 65520 => ffffffffe0000000, -16 -+ lfsu 7ff8000000000000, 65528 => 0000000000000000, -8 -+ lfsu 0010000000000001, 0 => 36a0000000000000, 0 -+ lfsu 00100094e0000359, 8 => c400006b20000000, 8 -+ lfsu 3fe0000000000001, 16 => 36a0000000000000, 16 -+ lfsu 3fe00094e0000359, 24 => c400006b20000000, 24 -+ lfsu 8010000000000001, 32 => 36a0000000000000, 32 -+ lfsu 80100094e0000359, 40 => c400006b20000000, 40 -+ lfsu bfe0000000000001, 48 => 36a0000000000000, 48 -+ lfsu bfe00094e0000359, 56 => c400006b20000000, 56 -+ lfsu 0000000000000000, 64 => 0000000000000000, 64 -+ lfsu 8000000000000000, 72 => 0000000000000000, 72 -+ lfsu 7ff0000000000000, 80 => 0000000000000000, 80 -+ lfsu fff0000000000000, 88 => 0000000000000000, 88 -+ lfsu 7ff7ffffffffffff, 96 => ffffffffe0000000, 96 -+ lfsu fff7ffffffffffff, 104 => ffffffffe0000000, 104 -+ lfsu 7ff8000000000000, 112 => 0000000000000000, 112 -+ lfsu fff8000000000000, 120 => 0000000000000000, 120 -+ -+ lfd 0010000000000001, 65416 => 0010000000000001, 0 -+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 65448 => 8010000000000001, 0 -+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 65480 => 0000000000000000, 0 -+ lfd 8000000000000000, 65488 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 65504 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0 -+ lfd 0010000000000001, 0 => 0010000000000001, 0 -+ lfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 32 => 8010000000000001, 0 -+ lfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 64 => 0000000000000000, 0 -+ lfd 8000000000000000, 72 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 88 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdu 0010000000000001, 65416 => 0010000000000001, -120 -+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112 -+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104 -+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96 -+ lfdu 8010000000000001, 65448 => 8010000000000001, -88 -+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80 -+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72 -+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64 -+ lfdu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfdu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40 -+ lfdu fff0000000000000, 65504 => fff0000000000000, -32 -+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24 -+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16 -+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8 -+ lfdu 0010000000000001, 0 => 0010000000000001, 0 -+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdu 8010000000000001, 32 => 8010000000000001, 32 -+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdu 0000000000000000, 64 => 0000000000000000, 64 -+ lfdu 8000000000000000, 72 => 8000000000000000, 72 -+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdu fff0000000000000, 88 => fff0000000000000, 88 -+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float load insns with two register args: -+ lfsx 0010000000000001, -120 => 36a0000000000000, 0 -+ lfsx 00100094e0000359, -112 => c400006b20000000, 0 -+ lfsx 3fe0000000000001, -104 => 36a0000000000000, 0 -+ lfsx 3fe00094e0000359, -96 => c400006b20000000, 0 -+ lfsx 8010000000000001, -88 => 36a0000000000000, 0 -+ lfsx 80100094e0000359, -80 => c400006b20000000, 0 -+ lfsx bfe0000000000001, -72 => 36a0000000000000, 0 -+ lfsx bfe00094e0000359, -64 => c400006b20000000, 0 -+ lfsx 0000000000000000, -56 => 0000000000000000, 0 -+ lfsx 8000000000000000, -48 => 0000000000000000, 0 -+ lfsx 7ff0000000000000, -40 => 0000000000000000, 0 -+ lfsx fff0000000000000, -32 => 0000000000000000, 0 -+ lfsx 7ff7ffffffffffff, -24 => ffffffffe0000000, 0 -+ lfsx fff7ffffffffffff, -16 => ffffffffe0000000, 0 -+ lfsx 7ff8000000000000, -8 => 0000000000000000, 0 -+ lfsx 0010000000000001, 0 => 36a0000000000000, 0 -+ lfsx 00100094e0000359, 8 => c400006b20000000, 0 -+ lfsx 3fe0000000000001, 16 => 36a0000000000000, 0 -+ lfsx 3fe00094e0000359, 24 => c400006b20000000, 0 -+ lfsx 8010000000000001, 32 => 36a0000000000000, 0 -+ lfsx 80100094e0000359, 40 => c400006b20000000, 0 -+ lfsx bfe0000000000001, 48 => 36a0000000000000, 0 -+ lfsx bfe00094e0000359, 56 => c400006b20000000, 0 -+ lfsx 0000000000000000, 64 => 0000000000000000, 0 -+ lfsx 8000000000000000, 72 => 0000000000000000, 0 -+ lfsx 7ff0000000000000, 80 => 0000000000000000, 0 -+ lfsx fff0000000000000, 88 => 0000000000000000, 0 -+ lfsx 7ff7ffffffffffff, 96 => ffffffffe0000000, 0 -+ lfsx fff7ffffffffffff, 104 => ffffffffe0000000, 0 -+ lfsx 7ff8000000000000, 112 => 0000000000000000, 0 -+ lfsx fff8000000000000, 120 => 0000000000000000, 0 -+ -+ lfsux 0010000000000001, -120 => 36a0000000000000, -120 -+ lfsux 00100094e0000359, -112 => c400006b20000000, -112 -+ lfsux 3fe0000000000001, -104 => 36a0000000000000, -104 -+ lfsux 3fe00094e0000359, -96 => c400006b20000000, -96 -+ lfsux 8010000000000001, -88 => 36a0000000000000, -88 -+ lfsux 80100094e0000359, -80 => c400006b20000000, -80 -+ lfsux bfe0000000000001, -72 => 36a0000000000000, -72 -+ lfsux bfe00094e0000359, -64 => c400006b20000000, -64 -+ lfsux 0000000000000000, -56 => 0000000000000000, -56 -+ lfsux 8000000000000000, -48 => 0000000000000000, -48 -+ lfsux 7ff0000000000000, -40 => 0000000000000000, -40 -+ lfsux fff0000000000000, -32 => 0000000000000000, -32 -+ lfsux 7ff7ffffffffffff, -24 => ffffffffe0000000, -24 -+ lfsux fff7ffffffffffff, -16 => ffffffffe0000000, -16 -+ lfsux 7ff8000000000000, -8 => 0000000000000000, -8 -+ lfsux 0010000000000001, 0 => 36a0000000000000, 0 -+ lfsux 00100094e0000359, 8 => c400006b20000000, 8 -+ lfsux 3fe0000000000001, 16 => 36a0000000000000, 16 -+ lfsux 3fe00094e0000359, 24 => c400006b20000000, 24 -+ lfsux 8010000000000001, 32 => 36a0000000000000, 32 -+ lfsux 80100094e0000359, 40 => c400006b20000000, 40 -+ lfsux bfe0000000000001, 48 => 36a0000000000000, 48 -+ lfsux bfe00094e0000359, 56 => c400006b20000000, 56 -+ lfsux 0000000000000000, 64 => 0000000000000000, 64 -+ lfsux 8000000000000000, 72 => 0000000000000000, 72 -+ lfsux 7ff0000000000000, 80 => 0000000000000000, 80 -+ lfsux fff0000000000000, 88 => 0000000000000000, 88 -+ lfsux 7ff7ffffffffffff, 96 => ffffffffe0000000, 96 -+ lfsux fff7ffffffffffff, 104 => ffffffffe0000000, 104 -+ lfsux 7ff8000000000000, 112 => 0000000000000000, 112 -+ lfsux fff8000000000000, 120 => 0000000000000000, 120 -+ -+ lfdx 0010000000000001, -120 => 0010000000000001, 0 -+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, -88 => 8010000000000001, 0 -+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, -56 => 0000000000000000, 0 -+ lfdx 8000000000000000, -48 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, -32 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ lfdx 0010000000000001, 0 => 0010000000000001, 0 -+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, 32 => 8010000000000001, 0 -+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, 64 => 0000000000000000, 0 -+ lfdx 8000000000000000, 72 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, 88 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdux 0010000000000001, -120 => 0010000000000001, -120 -+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112 -+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ lfdux 8010000000000001, -88 => 8010000000000001, -88 -+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80 -+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72 -+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ lfdux 0000000000000000, -56 => 0000000000000000, -56 -+ lfdux 8000000000000000, -48 => 8000000000000000, -48 -+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ lfdux fff0000000000000, -32 => fff0000000000000, -32 -+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ lfdux 0010000000000001, 0 => 0010000000000001, 0 -+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdux 8010000000000001, 32 => 8010000000000001, 32 -+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdux 0000000000000000, 64 => 0000000000000000, 64 -+ lfdux 8000000000000000, 72 => 8000000000000000, 72 -+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdux fff0000000000000, 88 => fff0000000000000, 88 -+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns -+ with one register + one 16 bits immediate args with flags update: -+ stfs 0010000000000001, -56 => 0000000000000000, 0 -+ stfs 00100094e0000359, -48 => 0000000000000000, 0 -+ stfs 3fe0000000000001, -40 => 000000003f000000, 0 -+ stfs 3fe00094e0000359, -32 => 000000003f0004a7, 0 -+ stfs 8010000000000001, -24 => 0000000080000000, 0 -+ stfs 80100094e0000359, -16 => 0000000080000000, 0 -+ stfs bfe0000000000001, -8 => 00000000bf000000, 0 -+ stfs 0010000000000001, 0 => 0000000000000000, 0 -+ stfs 00100094e0000359, 8 => 0000000000000000, 0 -+ stfs 3fe0000000000001, 16 => 000000003f000000, 0 -+ stfs 3fe00094e0000359, 24 => 000000003f0004a7, 0 -+ stfs 8010000000000001, 32 => 0000000080000000, 0 -+ stfs 80100094e0000359, 40 => 0000000080000000, 0 -+ stfs bfe0000000000001, 48 => 00000000bf000000, 0 -+ stfs bfe00094e0000359, 56 => 00000000bf0004a7, 0 -+ -+ stfsu 0010000000000001, -56 => 0000000000000000, -56 -+ stfsu 00100094e0000359, -48 => 0000000000000000, -48 -+ stfsu 3fe0000000000001, -40 => 000000003f000000, -40 -+ stfsu 3fe00094e0000359, -32 => 000000003f0004a7, -32 -+ stfsu 8010000000000001, -24 => 0000000080000000, -24 -+ stfsu 80100094e0000359, -16 => 0000000080000000, -16 -+ stfsu bfe0000000000001, -8 => 00000000bf000000, -8 -+ stfsu 0010000000000001, 0 => 0000000000000000, 0 -+ stfsu 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsu 3fe0000000000001, 16 => 000000003f000000, 16 -+ stfsu 3fe00094e0000359, 24 => 000000003f0004a7, 24 -+ stfsu 8010000000000001, 32 => 0000000080000000, 32 -+ stfsu 80100094e0000359, 40 => 0000000080000000, 40 -+ stfsu bfe0000000000001, 48 => 00000000bf000000, 48 -+ stfsu bfe00094e0000359, 56 => 00000000bf0004a7, 56 -+ -+ stfd 0010000000000001, -120 => 0010000000000001, 0 -+ stfd 00100094e0000359, -112 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, -88 => 8010000000000001, 0 -+ stfd 80100094e0000359, -80 => 80100094e0000359, 0 -+ stfd bfe0000000000001, -72 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ stfd 0000000000000000, -56 => 0000000000000000, 0 -+ stfd 8000000000000000, -48 => 8000000000000000, 0 -+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ stfd fff0000000000000, -32 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ stfd 0010000000000001, 0 => 0010000000000001, 0 -+ stfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, 32 => 8010000000000001, 0 -+ stfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfd 0000000000000000, 64 => 0000000000000000, 0 -+ stfd 8000000000000000, 72 => 8000000000000000, 0 -+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfd fff0000000000000, 88 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdu 0010000000000001, -120 => 0010000000000001, -120 -+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112 -+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ stfdu 8010000000000001, -88 => 8010000000000001, -88 -+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80 -+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72 -+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ stfdu 0000000000000000, -56 => 0000000000000000, -56 -+ stfdu 8000000000000000, -48 => 8000000000000000, -48 -+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ stfdu fff0000000000000, -32 => fff0000000000000, -32 -+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ stfdu 0010000000000001, 0 => 0010000000000001, 0 -+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdu 8010000000000001, 32 => 8010000000000001, 32 -+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdu 0000000000000000, 64 => 0000000000000000, 64 -+ stfdu 8000000000000000, 72 => 8000000000000000, 72 -+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdu fff0000000000000, 88 => fff0000000000000, 88 -+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns with three register args: -+ stfsx 0010000000000001, 0 => 0000000000000000, 0 -+ stfsx 00100094e0000359, 8 => 0000000000000000, 0 -+ stfsx 3fe0000000000001, 16 => 000000003f000000, 0 -+ stfsx 3fe00094e0000359, 24 => 000000003f0004a7, 0 -+ stfsx 8010000000000001, 32 => 0000000080000000, 0 -+ stfsx 80100094e0000359, 40 => 0000000080000000, 0 -+ stfsx bfe0000000000001, 48 => 00000000bf000000, 0 -+ stfsx bfe00094e0000359, 56 => 00000000bf0004a7, 0 -+ -+ stfsux 0010000000000001, 0 => 0000000000000000, 0 -+ stfsux 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsux 3fe0000000000001, 16 => 000000003f000000, 16 -+ stfsux 3fe00094e0000359, 24 => 000000003f0004a7, 24 -+ stfsux 8010000000000001, 32 => 0000000080000000, 32 -+ stfsux 80100094e0000359, 40 => 0000000080000000, 40 -+ stfsux bfe0000000000001, 48 => 00000000bf000000, 48 -+ stfsux bfe00094e0000359, 56 => 00000000bf0004a7, 56 -+ -+ stfdx 0010000000000001, 0 => 0010000000000001, 0 -+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfdx 8010000000000001, 32 => 8010000000000001, 0 -+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfdx 0000000000000000, 64 => 0000000000000000, 0 -+ stfdx 8000000000000000, 72 => 8000000000000000, 0 -+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfdx fff0000000000000, 88 => fff0000000000000, 0 -+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdux 0010000000000001, 0 => 0010000000000001, 0 -+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdux 8010000000000001, 32 => 8010000000000001, 32 -+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdux 0000000000000000, 64 => 0000000000000000, 64 -+ stfdux 8000000000000000, 72 => 8000000000000000, 72 -+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdux fff0000000000000, 88 => fff0000000000000, 88 -+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+All done. Tested 77 different instructions -Index: none/tests/ppc64/round.c -=================================================================== ---- none/tests/ppc64/round.c.orig -+++ none/tests/ppc64/round.c -@@ -49,19 +49,32 @@ typedef unsigned int fpscr_t; - typedef union { - float flt; - struct { -+#if defined(VGP_ppc64le_linux) -+ unsigned int frac:23; -+ unsigned int exp:8; -+ unsigned int sign:1; -+#else - unsigned int sign:1; - unsigned int exp:8; - unsigned int frac:23; -+#endif - } layout; - } flt_overlay; - - typedef union { - double dbl; - struct { -+#if defined(VGP_ppc64le_linux) -+ unsigned int frac_lo:32; -+ unsigned int frac_hi:20; -+ unsigned int exp:11; -+ unsigned int sign:1; -+#else - unsigned int sign:1; - unsigned int exp:11; - unsigned int frac_hi:20; - unsigned int frac_lo:32; -+#endif - } layout; - struct { - unsigned int hi; -@@ -227,7 +240,7 @@ init() - F.layout.frac = 1; - denorm_small = F.flt; /* == 2^(-149) */ - if (debug) { -- print_double("float small", F.flt); -+ print_single("float small", &F.flt); - } - - D.layout.sign = 0; -Index: none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE -=================================================================== ---- /dev/null -+++ none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE -@@ -0,0 +1,1044 @@ -+Test VSX load/store instructions -+lxsdx: 01234567 89abcdef => 01234567 89abcdef -+lxsdx: 8899aabb 91929394 => 8899aabb 91929394 -+ -+lxsdx: 01234567 89abcdef => 01234567 89abcdef -+lxsdx: 89abcdef 00112233 => 89abcdef 00112233 -+lxsdx: 8899aabb 91929394 => 8899aabb 91929394 -+lxsdx: 91929394 a1a2a3a4 => 91929394 a1a2a3a4 -+ -+lxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef -+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => a1a2a3a4 b1b2b3b4 8899aabb 91929394 -+ -+lxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef -+lxvd2x: 89abcdef 00112233 44556677 8899aabb => 44556677 8899aabb 89abcdef 00112233 -+lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => a1a2a3a4 b1b2b3b4 8899aabb 91929394 -+lxvd2x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => b1b2b3b4 c1c2c3c4 91929394 a1a2a3a4 -+ -+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef -+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394 -+ -+lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef -+lxvdsx: 89abcdef 00112233 89abcdef 00112233 => 89abcdef 00112233 89abcdef 00112233 -+lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394 -+lxvdsx: 91929394 a1a2a3a4 91929394 a1a2a3a4 => 91929394 a1a2a3a4 91929394 a1a2a3a4 -+ -+lxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567 -+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => b1b2b3b4 a1a2a3a4 91929394 8899aabb -+ -+lxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567 -+lxvw4x: 89abcdef 00112233 44556677 8899aabb => 8899aabb 44556677 00112233 89abcdef -+lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => b1b2b3b4 a1a2a3a4 91929394 8899aabb -+lxvw4x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => c1c2c3c4 b1b2b3b4 a1a2a3a4 91929394 -+ -+stxsdx: 01234567 89abcdef => 00112233 44556677 -+ -+stxsdx: 01234567 89abcdef => 00112233 44556677 -+ -+stxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef -+ -+stxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef -+ -+stxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567 -+ -+stxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567 -+ -+Test VSX logic instructions -+xxlxor: 01234567 89abcdef 00112233 44556677 xxlxor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89baefdc 18395e7b a1b38197 f5e7d5c3 -+xxlxor: 89abcdef 00112233 44556677 8899aabb xxlxor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 18395e7b a1b38197 f5e7d5c3 495b697f -+xxlxor: 00112233 44556677 8899aabb 91929394 xxlxor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b38197 f5e7d5c3 495b697f 40404040 -+xxlxor: 44556677 8899aabb 91929394 a1a2a3a4 xxlxor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5e7d5c3 495b697f 40404040 dbc9fe9a -+xxlor: 01234567 89abcdef 00112233 44556677 xxlor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89bbefff 99bbdfff a1b3a3b7 f5f7f7f7 -+xxlor: 89abcdef 00112233 44556677 8899aabb xxlor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 99bbdfff a1b3a3b7 f5f7f7f7 c9dbebff -+xxlor: 00112233 44556677 8899aabb 91929394 xxlor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b3a3b7 f5f7f7f7 c9dbebff d1d2d3d4 -+xxlor: 44556677 8899aabb 91929394 a1a2a3a4 xxlor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5f7f7f7 c9dbebff d1d2d3d4 fbebffbe -+xxlnor: 01234567 89abcdef 00112233 44556677 xxlnor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 76441000 66442000 5e4c5c48 0a080808 -+xxlnor: 89abcdef 00112233 44556677 8899aabb xxlnor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 66442000 5e4c5c48 0a080808 36241400 -+xxlnor: 00112233 44556677 8899aabb 91929394 xxlnor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 5e4c5c48 0a080808 36241400 2e2d2c2b -+xxlnor: 44556677 8899aabb 91929394 a1a2a3a4 xxlnor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 0a080808 36241400 2e2d2c2b 04140041 -+xxland: 01234567 89abcdef 00112233 44556677 xxland 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 00010023 81828184 00002220 00102234 -+xxland: 89abcdef 00112233 44556677 8899aabb xxland 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 81828184 00002220 00102234 80808280 -+xxland: 00112233 44556677 8899aabb 91929394 xxland a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00002220 00102234 80808280 91929394 -+xxland: 44556677 8899aabb 91929394 a1a2a3a4 xxland b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 00102234 80808280 91929394 20220124 -+xxlandc: 01234567 89abcdef 00112233 44556677 xxlandc 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 01224544 08294c6b 00110013 44454443 -+xxlandc: 89abcdef 00112233 44556677 8899aabb xxlandc 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 08294c6b 00110013 44454443 0819283b -+xxlandc: 00112233 44556677 8899aabb 91929394 xxlandc a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00110013 44454443 0819283b 00000000 -+xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280 -+ -+Test ldbrx instruction -+ldbrx: 67 45 23 01 ef cd ab 89 (reverse) => 89 ab cd ef 01 23 45 67 -+ldbrx: ef cd ab 89 33 22 11 00 (reverse) => 00 11 22 33 89 ab cd ef -+ldbrx: 33 22 11 00 77 66 55 44 (reverse) => 44 55 66 77 00 11 22 33 -+ -+Test popcntd instruction -+popcntd: 0x9182736405504536 => 24 -+ -+Test lfiwzx instruction -+lfiwzx: 19088743 => 19088743.00 -+lfiwzx: 2309737967 => 2309737967.00 -+lfiwzx: 1122867 => 1122867.00 -+ -+Test P7 floating point convert instructions -+fcfids 0010000000000001 => (raw sp) 59800000) -+fcfids 00100094e0000359 => (raw sp) 598004a7) -+fcfids 3fe0000000000001 => (raw sp) 5e7f8000) -+fcfids 3fe00094e0000359 => (raw sp) 5e7f8002) -+fcfids 8010000000000001 => (raw sp) deffe000) -+fcfids 80100094e0000359 => (raw sp) deffdfff) -+fcfids bfe0000000000001 => (raw sp) de804000) -+fcfids bfe00094e0000359 => (raw sp) de803fff) -+fcfids 0020000000000b01 => (raw sp) 5a000000) -+fcfids 00000000203f0b3d => (raw sp) 4e00fc2d) -+fcfids 00000000005a203d => (raw sp) 4ab4407a) -+fcfids 8020000000000b01 => (raw sp) deffc000) -+fcfids 80000000203f0b3d => (raw sp) df000000) -+ -+fcfidus 0010000000000001 => (raw sp) 59800000) -+fcfidus 00100094e0000359 => (raw sp) 598004a7) -+fcfidus 3fe0000000000001 => (raw sp) 5e7f8000) -+fcfidus 3fe00094e0000359 => (raw sp) 5e7f8002) -+fcfidus 8010000000000001 => (raw sp) 5f001000) -+fcfidus 80100094e0000359 => (raw sp) 5f001001) -+fcfidus bfe0000000000001 => (raw sp) 5f3fe000) -+fcfidus bfe00094e0000359 => (raw sp) 5f3fe001) -+fcfidus 0020000000000b01 => (raw sp) 5a000000) -+fcfidus 00000000203f0b3d => (raw sp) 4e00fc2d) -+fcfidus 00000000005a203d => (raw sp) 4ab4407a) -+fcfidus 8020000000000b01 => (raw sp) 5f002000) -+fcfidus 80000000203f0b3d => (raw sp) 5f000000) -+ -+fcfidu 0010000000000001 => (raw sp) 4330000000000001) -+fcfidu 00100094e0000359 => (raw sp) 43300094e0000359) -+fcfidu 3fe0000000000001 => (raw sp) 43cff00000000000) -+fcfidu 3fe00094e0000359 => (raw sp) 43cff0004a700002) -+fcfidu 8010000000000001 => (raw sp) 43e0020000000000) -+fcfidu 80100094e0000359 => (raw sp) 43e00200129c0000) -+fcfidu bfe0000000000001 => (raw sp) 43e7fc0000000000) -+fcfidu bfe00094e0000359 => (raw sp) 43e7fc00129c0000) -+fcfidu 0020000000000b01 => (raw sp) 4340000000000580) -+fcfidu 00000000203f0b3d => (raw sp) 41c01f859e800000) -+fcfidu 00000000005a203d => (raw sp) 4156880f40000000) -+fcfidu 8020000000000b01 => (raw sp) 43e0040000000001) -+fcfidu 80000000203f0b3d => (raw sp) 43e00000000407e1) -+ -+Test ftdiv instruction -+ftdiv: 3fd8000000000000 <=> 404f000000000000 ? 8 (CRx) -+ftdiv: 7ff7ffffffffffff <=> 404f000000000000 ? a (CRx) -+ftdiv: 404f000000000000 <=> fff8000000000000 ? a (CRx) -+ftdiv: 3fd8000000000000 <=> 0018000000b77501 ? a (CRx) -+ftdiv: 404f000000000000 <=> 7fe800000000051b ? a (CRx) -+ftdiv: 7fe800000000051b <=> 3fd8000000000000 ? a (CRx) -+ftdiv: 3fd8000000000000 <=> 7fe800000000051b ? a (CRx) -+ftdiv: 0123214569900000 <=> 3fd8000000000000 ? a (CRx) -+ftdiv: 7ff0000000000000 <=> 404f000000000000 ? e (CRx) -+ftdiv: fff0000000000000 <=> 404f000000000000 ? e (CRx) -+ftdiv: 404f000000000000 <=> 7ff0000000000000 ? e (CRx) -+ftdiv: 3fd8000000000000 <=> 8008340000078000 ? e (CRx) -+ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx) -+ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx) -+ -+Test VSX move instructions -+xsabsdp: X[B]: 0011223344556677 => 0011223344556677 -+xsabsdp: X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4 -+xsabsdp: X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778 -+ -+xscpsgndp: X[A]: 0011223344556677 X[B]: 0011223344556677 => 0011223344556677 -+xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: 0011223344556677 => 8011223344556677 -+xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: 0011223344556677 => 0011223344556677 -+xscpsgndp: X[A]: 0011223344556677 X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4 -+xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: a1a2a3a4b1b2b3b4 => a1a2a3a4b1b2b3b4 -+xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4 -+xscpsgndp: X[A]: 0011223344556677 X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778 -+xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778 -+xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778 -+ -+xsnabsdp: X[B]: 0011223344556677 => 8011223344556677 -+xsnabsdp: X[B]: a1a2a3a4b1b2b3b4 => a1a2a3a4b1b2b3b4 -+xsnabsdp: X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778 -+ -+xsnegdp: X[B]: 0011223344556677 => 8011223344556677 -+xsnegdp: X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4 -+xsnegdp: X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778 -+ -+Test VSX permute instructions -+xxmrghw: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[77777777,33333333,88888888,44444444] -+xxmrghw: -+ XA[00112233,44556677,8899aabb,ccddeeff] -+ XB[11111111,22222222,33333333,44444444] -+ => XT[33333333,8899aabb,44444444,ccddeeff] -+xxmrglw: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[55555555,11111111,66666666,22222222] -+xxmrglw: -+ XA[00112233,44556677,8899aabb,ccddeeff] -+ XB[11111111,22222222,33333333,44444444] -+ => XT[11111111,00112233,22222222,44556677] -+xxpermdi DM=00: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[77777777,88888888,33333333,44444444] -+xxpermdi DM=01: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[55555555,66666666,33333333,44444444] -+xxpermdi DM=10: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[77777777,88888888,11111111,22222222] -+xxpermdi DM=11: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[55555555,66666666,11111111,22222222] -+xxsldwi SHW=0: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[11111111,22222222,33333333,44444444] -+xxsldwi SHW=1: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[88888888,11111111,22222222,33333333] -+xxsldwi SHW=2: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[77777777,88888888,11111111,22222222] -+xxsldwi SHW=3: -+ XA[11111111,22222222,33333333,44444444] -+ XB[55555555,66666666,77777777,88888888] -+ => XT[66666666,77777777,88888888,11111111] -+ -+Test VSX floating point instructions -+#0: xscmpudp fff0000000000000 <=> fff0000000000000 ? 2 (CRx) -+#1: xscmpudp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx) -+#2: xscmpudp fff0000000000000 <=> 8000000000000000 ? 8 (CRx) -+#3: xscmpudp fff0000000000000 <=> 0000000000000000 ? 8 (CRx) -+#4: xscmpudp fff0000000000000 <=> 0123214569900000 ? 8 (CRx) -+#5: xscmpudp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx) -+#6: xscmpudp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#7: xscmpudp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#8: xscmpudp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx) -+#9: xscmpudp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx) -+#10: xscmpudp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx) -+#11: xscmpudp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx) -+#12: xscmpudp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx) -+#13: xscmpudp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx) -+#14: xscmpudp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx) -+#15: xscmpudp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx) -+#16: xscmpudp 8000000000000000 <=> fff0000000000000 ? 4 (CRx) -+#17: xscmpudp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#18: xscmpudp 8000000000000000 <=> 8000000000000000 ? 2 (CRx) -+#19: xscmpudp 8000000000000000 <=> 0000000000000000 ? 2 (CRx) -+#20: xscmpudp 8000000000000000 <=> 0123214569900000 ? 8 (CRx) -+#21: xscmpudp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx) -+#22: xscmpudp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#23: xscmpudp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#24: xscmpudp 0000000000000000 <=> fff0000000000000 ? 4 (CRx) -+#25: xscmpudp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#26: xscmpudp 0000000000000000 <=> 8000000000000000 ? 2 (CRx) -+#27: xscmpudp 0000000000000000 <=> 0000000000000000 ? 2 (CRx) -+#28: xscmpudp 0000000000000000 <=> 0123214569900000 ? 8 (CRx) -+#29: xscmpudp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx) -+#30: xscmpudp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#31: xscmpudp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#32: xscmpudp 0123214569900000 <=> fff0000000000000 ? 4 (CRx) -+#33: xscmpudp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#34: xscmpudp 0123214569900000 <=> 8000000000000000 ? 4 (CRx) -+#35: xscmpudp 0123214569900000 <=> 0000000000000000 ? 4 (CRx) -+#36: xscmpudp 0123214569900000 <=> 404f000000000000 ? 8 (CRx) -+#37: xscmpudp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx) -+#38: xscmpudp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#39: xscmpudp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx) -+#40: xscmpudp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx) -+#41: xscmpudp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#42: xscmpudp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx) -+#43: xscmpudp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx) -+#44: xscmpudp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx) -+#45: xscmpudp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx) -+#46: xscmpudp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#47: xscmpudp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#48: xscmpudp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx) -+#49: xscmpudp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx) -+#50: xscmpudp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx) -+#51: xscmpudp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx) -+#52: xscmpudp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx) -+#53: xscmpudp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx) -+#54: xscmpudp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx) -+#55: xscmpudp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx) -+#56: xscmpudp fff8000000000000 <=> fff0000000000000 ? 1 (CRx) -+#57: xscmpudp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx) -+#58: xscmpudp fff8000000000000 <=> 8000000000000000 ? 1 (CRx) -+#59: xscmpudp fff8000000000000 <=> 0000000000000000 ? 1 (CRx) -+#60: xscmpudp fff8000000000000 <=> 0123214569900000 ? 1 (CRx) -+#61: xscmpudp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx) -+#62: xscmpudp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#63: xscmpudp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+ -+#0: xscmpodp fff0000000000000 <=> fff0000000000000 ? 2 (CRx) -+#1: xscmpodp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx) -+#2: xscmpodp fff0000000000000 <=> 8000000000000000 ? 8 (CRx) -+#3: xscmpodp fff0000000000000 <=> 0000000000000000 ? 8 (CRx) -+#4: xscmpodp fff0000000000000 <=> 0123214569900000 ? 8 (CRx) -+#5: xscmpodp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx) -+#6: xscmpodp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#7: xscmpodp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#8: xscmpodp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx) -+#9: xscmpodp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx) -+#10: xscmpodp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx) -+#11: xscmpodp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx) -+#12: xscmpodp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx) -+#13: xscmpodp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx) -+#14: xscmpodp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx) -+#15: xscmpodp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx) -+#16: xscmpodp 8000000000000000 <=> fff0000000000000 ? 4 (CRx) -+#17: xscmpodp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#18: xscmpodp 8000000000000000 <=> 8000000000000000 ? 2 (CRx) -+#19: xscmpodp 8000000000000000 <=> 0000000000000000 ? 2 (CRx) -+#20: xscmpodp 8000000000000000 <=> 0123214569900000 ? 8 (CRx) -+#21: xscmpodp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx) -+#22: xscmpodp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#23: xscmpodp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#24: xscmpodp 0000000000000000 <=> fff0000000000000 ? 4 (CRx) -+#25: xscmpodp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#26: xscmpodp 0000000000000000 <=> 8000000000000000 ? 2 (CRx) -+#27: xscmpodp 0000000000000000 <=> 0000000000000000 ? 2 (CRx) -+#28: xscmpodp 0000000000000000 <=> 0123214569900000 ? 8 (CRx) -+#29: xscmpodp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx) -+#30: xscmpodp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#31: xscmpodp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#32: xscmpodp 0123214569900000 <=> fff0000000000000 ? 4 (CRx) -+#33: xscmpodp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#34: xscmpodp 0123214569900000 <=> 8000000000000000 ? 4 (CRx) -+#35: xscmpodp 0123214569900000 <=> 0000000000000000 ? 4 (CRx) -+#36: xscmpodp 0123214569900000 <=> 404f000000000000 ? 8 (CRx) -+#37: xscmpodp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx) -+#38: xscmpodp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#39: xscmpodp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx) -+#40: xscmpodp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx) -+#41: xscmpodp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx) -+#42: xscmpodp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx) -+#43: xscmpodp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx) -+#44: xscmpodp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx) -+#45: xscmpodp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx) -+#46: xscmpodp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#47: xscmpodp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+#48: xscmpodp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx) -+#49: xscmpodp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx) -+#50: xscmpodp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx) -+#51: xscmpodp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx) -+#52: xscmpodp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx) -+#53: xscmpodp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx) -+#54: xscmpodp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx) -+#55: xscmpodp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx) -+#56: xscmpodp fff8000000000000 <=> fff0000000000000 ? 1 (CRx) -+#57: xscmpodp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx) -+#58: xscmpodp fff8000000000000 <=> 8000000000000000 ? 1 (CRx) -+#59: xscmpodp fff8000000000000 <=> 0000000000000000 ? 1 (CRx) -+#60: xscmpodp fff8000000000000 <=> 0123214569900000 ? 1 (CRx) -+#61: xscmpodp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx) -+#62: xscmpodp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx) -+#63: xscmpodp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx) -+ -+#0: xsadddp fff0000000000000 fff0000000000000 = fff0000000000000 -+#1: xsadddp fff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#2: xsadddp fff0000000000000 8000000000000000 = fff0000000000000 -+#3: xsadddp fff0000000000000 0000000000000000 = fff0000000000000 -+#4: xsadddp fff0000000000000 0123214569900000 = fff0000000000000 -+#5: xsadddp fff0000000000000 7ff0000000000000 = 7ff8000000000000 -+#6: xsadddp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#7: xsadddp fff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#8: xsadddp c0d0650f5a07b353 fff0000000000000 = fff0000000000000 -+#9: xsadddp c0d0650f5a07b353 c0d0650f5a07b353 = c0e0650f5a07b353 -+#10: xsadddp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353 -+#11: xsadddp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353 -+#12: xsadddp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353 -+#13: xsadddp c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000 -+#14: xsadddp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff -+#15: xsadddp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000 -+#16: xsadddp 8000000000000000 fff0000000000000 = fff0000000000000 -+#17: xsadddp 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353 -+#18: xsadddp 8000000000000000 8000000000000000 = 8000000000000000 -+#19: xsadddp 8000000000000000 0000000000000000 = 0000000000000000 -+#20: xsadddp 8000000000000000 0123214569900000 = 0123214569900000 -+#21: xsadddp 8000000000000000 7ff0000000000000 = 7ff0000000000000 -+#22: xsadddp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#23: xsadddp 8000000000000000 7ff8000000000000 = 7ff8000000000000 -+#24: xsadddp 0000000000000000 fff0000000000000 = fff0000000000000 -+#25: xsadddp 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353 -+#26: xsadddp 0000000000000000 8000000000000000 = 0000000000000000 -+#27: xsadddp 0000000000000000 0000000000000000 = 0000000000000000 -+#28: xsadddp 0000000000000000 0123214569900000 = 0123214569900000 -+#29: xsadddp 0000000000000000 7ff0000000000000 = 7ff0000000000000 -+#30: xsadddp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#31: xsadddp 0000000000000000 7ff8000000000000 = 7ff8000000000000 -+#32: xsadddp 0123214569900000 fff0000000000000 = fff0000000000000 -+#33: xsadddp 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353 -+#34: xsadddp 0123214569900000 8000000000000000 = 0123214569900000 -+#35: xsadddp 0123214569900000 0000000000000000 = 0123214569900000 -+#36: xsadddp 0123214569900000 404f000000000000 = 404f000000000000 -+#37: xsadddp 0123214569900000 7ff0000000000000 = 7ff0000000000000 -+#38: xsadddp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff -+#39: xsadddp 0123214569900000 7ff8000000000000 = 7ff8000000000000 -+#40: xsadddp 7ff0000000000000 fff0000000000000 = 7ff8000000000000 -+#41: xsadddp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#42: xsadddp 7ff0000000000000 8000000000000000 = 7ff0000000000000 -+#43: xsadddp 7ff0000000000000 0000000000000000 = 7ff0000000000000 -+#44: xsadddp 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#45: xsadddp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000 -+#46: xsadddp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#47: xsadddp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#48: xsadddp fff7ffffffffffff fff0000000000000 = ffffffffffffffff -+#49: xsadddp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#50: xsadddp fff7ffffffffffff 8000000000000000 = ffffffffffffffff -+#51: xsadddp fff7ffffffffffff 0000000000000000 = ffffffffffffffff -+#52: xsadddp fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#53: xsadddp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff -+#54: xsadddp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff -+#55: xsadddp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff -+#56: xsadddp fff8000000000000 fff0000000000000 = fff8000000000000 -+#57: xsadddp fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#58: xsadddp fff8000000000000 8000000000000000 = fff8000000000000 -+#59: xsadddp fff8000000000000 0000000000000000 = fff8000000000000 -+#60: xsadddp fff8000000000000 0123214569900000 = fff8000000000000 -+#61: xsadddp fff8000000000000 7ff0000000000000 = fff8000000000000 -+#62: xsadddp fff8000000000000 7ff7ffffffffffff = fff8000000000000 -+#63: xsadddp fff8000000000000 7ff8000000000000 = fff8000000000000 -+ -+#0: xsdivdp fff0000000000000 fff0000000000000 = 7ff8000000000000 -+#1: xsdivdp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#2: xsdivdp fff0000000000000 8000000000000000 = 7ff0000000000000 -+#3: xsdivdp fff0000000000000 0000000000000000 = fff0000000000000 -+#4: xsdivdp fff0000000000000 0123214569900000 = fff0000000000000 -+#5: xsdivdp fff0000000000000 7ff0000000000000 = 7ff8000000000000 -+#6: xsdivdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#7: xsdivdp fff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#8: xsdivdp c0d0650f5a07b353 fff0000000000000 = 0000000000000000 -+#9: xsdivdp c0d0650f5a07b353 c0d0650f5a07b353 = 3ff0000000000000 -+#10: xsdivdp c0d0650f5a07b353 8000000000000000 = 7ff0000000000000 -+#11: xsdivdp c0d0650f5a07b353 0000000000000000 = fff0000000000000 -+#12: xsdivdp c0d0650f5a07b353 0123214569900000 = ff9b6cb57ca13c00 -+#13: xsdivdp c0d0650f5a07b353 7ff0000000000000 = 8000000000000000 -+#14: xsdivdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff -+#15: xsdivdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000 -+#16: xsdivdp 8000000000000000 fff0000000000000 = 0000000000000000 -+#17: xsdivdp 8000000000000000 c0d0650f5a07b353 = 0000000000000000 -+#18: xsdivdp 8000000000000000 8000000000000000 = 7ff8000000000000 -+#19: xsdivdp 8000000000000000 0000000000000000 = 7ff8000000000000 -+#20: xsdivdp 8000000000000000 0123214569900000 = 8000000000000000 -+#21: xsdivdp 8000000000000000 7ff0000000000000 = 8000000000000000 -+#22: xsdivdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#23: xsdivdp 8000000000000000 7ff8000000000000 = 7ff8000000000000 -+#24: xsdivdp 0000000000000000 fff0000000000000 = 8000000000000000 -+#25: xsdivdp 0000000000000000 c0d0650f5a07b353 = 8000000000000000 -+#26: xsdivdp 0000000000000000 8000000000000000 = 7ff8000000000000 -+#27: xsdivdp 0000000000000000 0000000000000000 = 7ff8000000000000 -+#28: xsdivdp 0000000000000000 0123214569900000 = 0000000000000000 -+#29: xsdivdp 0000000000000000 7ff0000000000000 = 0000000000000000 -+#30: xsdivdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#31: xsdivdp 0000000000000000 7ff8000000000000 = 7ff8000000000000 -+#32: xsdivdp 0123214569900000 fff0000000000000 = 8000000000000000 -+#33: xsdivdp 0123214569900000 c0d0650f5a07b353 = 8042ab59d8b6ec87 -+#34: xsdivdp 0123214569900000 8000000000000000 = fff0000000000000 -+#35: xsdivdp 0123214569900000 0000000000000000 = 7ff0000000000000 -+#36: xsdivdp 0123214569900000 404f000000000000 = 00c3bf3f64b5ad6b -+#37: xsdivdp 0123214569900000 7ff0000000000000 = 0000000000000000 -+#38: xsdivdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff -+#39: xsdivdp 0123214569900000 7ff8000000000000 = 7ff8000000000000 -+#40: xsdivdp 7ff0000000000000 fff0000000000000 = 7ff8000000000000 -+#41: xsdivdp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#42: xsdivdp 7ff0000000000000 8000000000000000 = fff0000000000000 -+#43: xsdivdp 7ff0000000000000 0000000000000000 = 7ff0000000000000 -+#44: xsdivdp 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#45: xsdivdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000 -+#46: xsdivdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#47: xsdivdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#48: xsdivdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff -+#49: xsdivdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#50: xsdivdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff -+#51: xsdivdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff -+#52: xsdivdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#53: xsdivdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff -+#54: xsdivdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff -+#55: xsdivdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff -+#56: xsdivdp fff8000000000000 fff0000000000000 = fff8000000000000 -+#57: xsdivdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#58: xsdivdp fff8000000000000 8000000000000000 = fff8000000000000 -+#59: xsdivdp fff8000000000000 0000000000000000 = fff8000000000000 -+#60: xsdivdp fff8000000000000 0123214569900000 = fff8000000000000 -+#61: xsdivdp fff8000000000000 7ff0000000000000 = fff8000000000000 -+#62: xsdivdp fff8000000000000 7ff7ffffffffffff = fff8000000000000 -+#63: xsdivdp fff8000000000000 7ff8000000000000 = fff8000000000000 -+ -+#0: xsmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000 -+#1: xsmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000 -+#2: xsmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#3: xsmaddadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000 -+#4: xsmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#5: xsmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000 -+#6: xsmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#7: xsmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000 -+#8: xsmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = fff0000000000000 -+#9: xsmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353 -+#10: xsmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7 -+#11: xsmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f -+#12: xsmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7 -+#13: xsmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = 7ff0000000000000 -+#14: xsmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff -+#15: xsmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000 -+#16: xsmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = fff0000000000000 -+#17: xsmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = c0d0650f5a07b353 -+#18: xsmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000 -+#19: xsmaddadp 0000000000000000 8000000000000000 0123214569900000 = 0000000000000000 -+#20: xsmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 0123214569900000 -+#21: xsmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = 7ff0000000000000 -+#22: xsmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#23: xsmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000 -+#24: xsmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = fff0000000000000 -+#25: xsmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = c0d0650f5a07b353 -+#26: xsmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 8000000000000000 -+#27: xsmaddadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000 -+#28: xsmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 0123214569900000 -+#29: xsmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = 7ff0000000000000 -+#30: xsmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#31: xsmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000 -+#32: xsmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = fff0000000000000 -+#33: xsmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = c0d0650f5a07b353 -+#34: xsmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f -+#35: xsmaddadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000 -+#36: xsmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = 404f000000000000 -+#37: xsmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = 7ff0000000000000 -+#38: xsmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff -+#39: xsmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000 -+#40: xsmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#41: xsmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#42: xsmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#43: xsmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#44: xsmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#45: xsmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#46: xsmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#47: xsmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000 -+#48: xsmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#49: xsmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#50: xsmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#51: xsmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#52: xsmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#53: xsmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#54: xsmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#55: xsmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#56: xsmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#57: xsmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000 -+#58: xsmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#59: xsmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+#60: xsmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#61: xsmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+#62: xsmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#63: xsmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+ -+#0: xsmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000 -+#1: xsmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#2: xsmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000 -+#3: xsmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000 -+#4: xsmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000 -+#5: xsmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000 -+#6: xsmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#7: xsmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#8: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = fff0000000000000 -+#9: xsmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c0d0650f5a07b353 -+#10: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7 -+#11: xsmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f -+#12: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7 -+#13: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000 -+#14: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff -+#15: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000 -+#16: xsmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = fff0000000000000 -+#17: xsmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353 -+#18: xsmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000 -+#19: xsmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 0000000000000000 -+#20: xsmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 0123214569900000 -+#21: xsmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = 7ff0000000000000 -+#22: xsmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#23: xsmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000 -+#24: xsmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = fff0000000000000 -+#25: xsmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353 -+#26: xsmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 8000000000000000 -+#27: xsmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000 -+#28: xsmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 0123214569900000 -+#29: xsmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = 7ff0000000000000 -+#30: xsmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#31: xsmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000 -+#32: xsmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = fff0000000000000 -+#33: xsmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353 -+#34: xsmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f -+#35: xsmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000 -+#36: xsmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = 404f000000000000 -+#37: xsmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = 7ff0000000000000 -+#38: xsmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff -+#39: xsmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000 -+#40: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = fff0000000000000 -+#41: xsmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#42: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000 -+#43: xsmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000 -+#44: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000 -+#45: xsmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff0000000000000 -+#46: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#47: xsmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#48: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff -+#49: xsmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#50: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff -+#51: xsmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff -+#52: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#53: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff -+#54: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff -+#55: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff -+#56: xsmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000 -+#57: xsmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#58: xsmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000 -+#59: xsmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000 -+#60: xsmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000 -+#61: xsmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000 -+#62: xsmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000 -+#63: xsmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000 -+ -+#0: xsmsubadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#1: xsmsubadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000 -+#2: xsmsubadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#3: xsmsubadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000 -+#4: xsmsubadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#5: xsmsubadp 7ff0000000000000 fff0000000000000 0123214569900000 = fff0000000000000 -+#6: xsmsubadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#7: xsmsubadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000 -+#8: xsmsubadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000 -+#9: xsmsubadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353 -+#10: xsmsubadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7 -+#11: xsmsubadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f -+#12: xsmsubadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7 -+#13: xsmsubadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000 -+#14: xsmsubadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff -+#15: xsmsubadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000 -+#16: xsmsubadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#17: xsmsubadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353 -+#18: xsmsubadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000 -+#19: xsmsubadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000 -+#20: xsmsubadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000 -+#21: xsmsubadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000 -+#22: xsmsubadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#23: xsmsubadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000 -+#24: xsmsubadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#25: xsmsubadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353 -+#26: xsmsubadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000 -+#27: xsmsubadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000 -+#28: xsmsubadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000 -+#29: xsmsubadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000 -+#30: xsmsubadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#31: xsmsubadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000 -+#32: xsmsubadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000 -+#33: xsmsubadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353 -+#34: xsmsubadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f -+#35: xsmsubadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000 -+#36: xsmsubadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000 -+#37: xsmsubadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000 -+#38: xsmsubadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff -+#39: xsmsubadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000 -+#40: xsmsubadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff8000000000000 -+#41: xsmsubadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#42: xsmsubadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#43: xsmsubadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#44: xsmsubadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#45: xsmsubadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000 -+#46: xsmsubadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#47: xsmsubadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000 -+#48: xsmsubadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#49: xsmsubadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#50: xsmsubadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#51: xsmsubadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#52: xsmsubadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#53: xsmsubadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#54: xsmsubadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#55: xsmsubadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#56: xsmsubadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#57: xsmsubadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000 -+#58: xsmsubadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#59: xsmsubadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+#60: xsmsubadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#61: xsmsubadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+#62: xsmsubadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#63: xsmsubadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+ -+#0: xsmsubmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff0000000000000 -+#1: xsmsubmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#2: xsmsubmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000 -+#3: xsmsubmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000 -+#4: xsmsubmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000 -+#5: xsmsubmdp 0123214569900000 fff0000000000000 7ff0000000000000 = fff0000000000000 -+#6: xsmsubmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#7: xsmsubmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#8: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000 -+#9: xsmsubmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353 -+#10: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7 -+#11: xsmsubmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f -+#12: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7 -+#13: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000 -+#14: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff -+#15: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000 -+#16: xsmsubmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000 -+#17: xsmsubmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#18: xsmsubmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000 -+#19: xsmsubmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000 -+#20: xsmsubmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000 -+#21: xsmsubmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000 -+#22: xsmsubmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#23: xsmsubmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000 -+#24: xsmsubmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000 -+#25: xsmsubmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#26: xsmsubmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000 -+#27: xsmsubmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000 -+#28: xsmsubmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000 -+#29: xsmsubmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000 -+#30: xsmsubmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#31: xsmsubmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000 -+#32: xsmsubmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000 -+#33: xsmsubmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#34: xsmsubmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f -+#35: xsmsubmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000 -+#36: xsmsubmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000 -+#37: xsmsubmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000 -+#38: xsmsubmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff -+#39: xsmsubmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000 -+#40: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff8000000000000 -+#41: xsmsubmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#42: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000 -+#43: xsmsubmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000 -+#44: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000 -+#45: xsmsubmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff8000000000000 -+#46: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#47: xsmsubmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#48: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff -+#49: xsmsubmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#50: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff -+#51: xsmsubmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff -+#52: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#53: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff -+#54: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff -+#55: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff -+#56: xsmsubmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000 -+#57: xsmsubmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#58: xsmsubmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000 -+#59: xsmsubmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000 -+#60: xsmsubmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000 -+#61: xsmsubmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000 -+#62: xsmsubmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000 -+#63: xsmsubmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000 -+ -+#0: xsnmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000 -+#1: xsnmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000 -+#2: xsnmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#3: xsnmaddadp 0000000000000000 fff0000000000000 0123214569900000 = 7ff0000000000000 -+#4: xsnmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#5: xsnmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000 -+#6: xsnmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#7: xsnmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000 -+#8: xsnmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000 -+#9: xsnmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353 -+#10: xsnmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7 -+#11: xsnmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 02039a19ca8fcb5f -+#12: xsnmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7 -+#13: xsnmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000 -+#14: xsnmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff -+#15: xsnmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000 -+#16: xsnmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#17: xsnmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353 -+#18: xsnmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 8000000000000000 -+#19: xsnmaddadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000 -+#20: xsnmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000 -+#21: xsnmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000 -+#22: xsnmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#23: xsnmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000 -+#24: xsnmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#25: xsnmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353 -+#26: xsnmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000 -+#27: xsnmaddadp 0000000000000000 0000000000000000 0123214569900000 = 8000000000000000 -+#28: xsnmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000 -+#29: xsnmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000 -+#30: xsnmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#31: xsnmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000 -+#32: xsnmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000 -+#33: xsnmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353 -+#34: xsnmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 02039a19ca8fcb5f -+#35: xsnmaddadp 0000000000000000 0123214569900000 0123214569900000 = 8000000000000000 -+#36: xsnmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000 -+#37: xsnmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000 -+#38: xsnmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff -+#39: xsnmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000 -+#40: xsnmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#41: xsnmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000 -+#42: xsnmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#43: xsnmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = fff0000000000000 -+#44: xsnmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#45: xsnmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = fff0000000000000 -+#46: xsnmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff -+#47: xsnmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000 -+#48: xsnmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#49: xsnmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#50: xsnmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#51: xsnmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#52: xsnmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#53: xsnmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#54: xsnmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#55: xsnmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#56: xsnmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#57: xsnmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000 -+#58: xsnmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#59: xsnmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+#60: xsnmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#61: xsnmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+#62: xsnmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#63: xsnmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000 -+ -+#0: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000 -+#1: xsnmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#2: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = fff0000000000000 -+#3: xsnmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = 7ff0000000000000 -+#4: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000 -+#5: xsnmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000 -+#6: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#7: xsnmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#8: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000 -+#9: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353 -+#10: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = c1b0cc9d05eec2a7 -+#11: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 02039a19ca8fcb5f -+#12: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c1b0cc9d05eec2a7 -+#13: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000 -+#14: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff -+#15: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000 -+#16: xsnmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000 -+#17: xsnmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#18: xsnmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 8000000000000000 -+#19: xsnmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000 -+#20: xsnmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000 -+#21: xsnmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000 -+#22: xsnmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#23: xsnmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000 -+#24: xsnmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000 -+#25: xsnmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#26: xsnmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000 -+#27: xsnmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 8000000000000000 -+#28: xsnmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000 -+#29: xsnmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000 -+#30: xsnmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#31: xsnmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000 -+#32: xsnmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000 -+#33: xsnmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#34: xsnmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 02039a19ca8fcb5f -+#35: xsnmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 8000000000000000 -+#36: xsnmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000 -+#37: xsnmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000 -+#38: xsnmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff -+#39: xsnmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000 -+#40: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff0000000000000 -+#41: xsnmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#42: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = 7ff0000000000000 -+#43: xsnmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = fff0000000000000 -+#44: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#45: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = fff0000000000000 -+#46: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#47: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#48: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff -+#49: xsnmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#50: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff -+#51: xsnmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff -+#52: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#53: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff -+#54: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff -+#55: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff -+#56: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000 -+#57: xsnmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#58: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000 -+#59: xsnmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000 -+#60: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000 -+#61: xsnmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000 -+#62: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000 -+#63: xsnmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000 -+ -+#0: xsmuldp fff0000000000000 fff0000000000000 = 7ff0000000000000 -+#1: xsmuldp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#2: xsmuldp fff0000000000000 8000000000000000 = 7ff8000000000000 -+#3: xsmuldp fff0000000000000 0000000000000000 = 7ff8000000000000 -+#4: xsmuldp fff0000000000000 0123214569900000 = fff0000000000000 -+#5: xsmuldp fff0000000000000 7ff0000000000000 = fff0000000000000 -+#6: xsmuldp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#7: xsmuldp fff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#8: xsmuldp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000 -+#9: xsmuldp c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7 -+#10: xsmuldp c0d0650f5a07b353 8000000000000000 = 0000000000000000 -+#11: xsmuldp c0d0650f5a07b353 0000000000000000 = 8000000000000000 -+#12: xsmuldp c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f -+#13: xsmuldp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000 -+#14: xsmuldp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff -+#15: xsmuldp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000 -+#16: xsmuldp 8000000000000000 fff0000000000000 = 7ff8000000000000 -+#17: xsmuldp 8000000000000000 c0d0650f5a07b353 = 0000000000000000 -+#18: xsmuldp 8000000000000000 8000000000000000 = 0000000000000000 -+#19: xsmuldp 8000000000000000 0000000000000000 = 8000000000000000 -+#20: xsmuldp 8000000000000000 0123214569900000 = 8000000000000000 -+#21: xsmuldp 8000000000000000 7ff0000000000000 = 7ff8000000000000 -+#22: xsmuldp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#23: xsmuldp 8000000000000000 7ff8000000000000 = 7ff8000000000000 -+#24: xsmuldp 0000000000000000 fff0000000000000 = 7ff8000000000000 -+#25: xsmuldp 0000000000000000 c0d0650f5a07b353 = 8000000000000000 -+#26: xsmuldp 0000000000000000 8000000000000000 = 8000000000000000 -+#27: xsmuldp 0000000000000000 0000000000000000 = 0000000000000000 -+#28: xsmuldp 0000000000000000 0123214569900000 = 0000000000000000 -+#29: xsmuldp 0000000000000000 7ff0000000000000 = 7ff8000000000000 -+#30: xsmuldp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#31: xsmuldp 0000000000000000 7ff8000000000000 = 7ff8000000000000 -+#32: xsmuldp 0123214569900000 fff0000000000000 = fff0000000000000 -+#33: xsmuldp 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f -+#34: xsmuldp 0123214569900000 8000000000000000 = 8000000000000000 -+#35: xsmuldp 0123214569900000 0000000000000000 = 0000000000000000 -+#36: xsmuldp 0123214569900000 404f000000000000 = 0182883b3e438000 -+#37: xsmuldp 0123214569900000 7ff0000000000000 = 7ff0000000000000 -+#38: xsmuldp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff -+#39: xsmuldp 0123214569900000 7ff8000000000000 = 7ff8000000000000 -+#40: xsmuldp 7ff0000000000000 fff0000000000000 = fff0000000000000 -+#41: xsmuldp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#42: xsmuldp 7ff0000000000000 8000000000000000 = 7ff8000000000000 -+#43: xsmuldp 7ff0000000000000 0000000000000000 = 7ff8000000000000 -+#44: xsmuldp 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#45: xsmuldp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000 -+#46: xsmuldp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#47: xsmuldp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#48: xsmuldp fff7ffffffffffff fff0000000000000 = ffffffffffffffff -+#49: xsmuldp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#50: xsmuldp fff7ffffffffffff 8000000000000000 = ffffffffffffffff -+#51: xsmuldp fff7ffffffffffff 0000000000000000 = ffffffffffffffff -+#52: xsmuldp fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#53: xsmuldp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff -+#54: xsmuldp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff -+#55: xsmuldp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff -+#56: xsmuldp fff8000000000000 fff0000000000000 = fff8000000000000 -+#57: xsmuldp fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#58: xsmuldp fff8000000000000 8000000000000000 = fff8000000000000 -+#59: xsmuldp fff8000000000000 0000000000000000 = fff8000000000000 -+#60: xsmuldp fff8000000000000 0123214569900000 = fff8000000000000 -+#61: xsmuldp fff8000000000000 7ff0000000000000 = fff8000000000000 -+#62: xsmuldp fff8000000000000 7ff7ffffffffffff = fff8000000000000 -+#63: xsmuldp fff8000000000000 7ff8000000000000 = fff8000000000000 -+ -+#0: xssubdp fff0000000000000 fff0000000000000 = 7ff8000000000000 -+#1: xssubdp fff0000000000000 c0d0650f5a07b353 = fff0000000000000 -+#2: xssubdp fff0000000000000 8000000000000000 = fff0000000000000 -+#3: xssubdp fff0000000000000 0000000000000000 = fff0000000000000 -+#4: xssubdp fff0000000000000 0123214569900000 = fff0000000000000 -+#5: xssubdp fff0000000000000 7ff0000000000000 = fff0000000000000 -+#6: xssubdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#7: xssubdp fff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#8: xssubdp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000 -+#9: xssubdp c0d0650f5a07b353 c0d0650f5a07b353 = 0000000000000000 -+#10: xssubdp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353 -+#11: xssubdp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353 -+#12: xssubdp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353 -+#13: xssubdp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000 -+#14: xssubdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff -+#15: xssubdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000 -+#16: xssubdp 8000000000000000 fff0000000000000 = 7ff0000000000000 -+#17: xssubdp 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#18: xssubdp 8000000000000000 8000000000000000 = 0000000000000000 -+#19: xssubdp 8000000000000000 0000000000000000 = 8000000000000000 -+#20: xssubdp 8000000000000000 0123214569900000 = 8123214569900000 -+#21: xssubdp 8000000000000000 7ff0000000000000 = fff0000000000000 -+#22: xssubdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#23: xssubdp 8000000000000000 7ff8000000000000 = 7ff8000000000000 -+#24: xssubdp 0000000000000000 fff0000000000000 = 7ff0000000000000 -+#25: xssubdp 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#26: xssubdp 0000000000000000 8000000000000000 = 0000000000000000 -+#27: xssubdp 0000000000000000 0000000000000000 = 0000000000000000 -+#28: xssubdp 0000000000000000 0123214569900000 = 8123214569900000 -+#29: xssubdp 0000000000000000 7ff0000000000000 = fff0000000000000 -+#30: xssubdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#31: xssubdp 0000000000000000 7ff8000000000000 = 7ff8000000000000 -+#32: xssubdp 0123214569900000 fff0000000000000 = 7ff0000000000000 -+#33: xssubdp 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353 -+#34: xssubdp 0123214569900000 8000000000000000 = 0123214569900000 -+#35: xssubdp 0123214569900000 0000000000000000 = 0123214569900000 -+#36: xssubdp 0123214569900000 404f000000000000 = c04f000000000000 -+#37: xssubdp 0123214569900000 7ff0000000000000 = fff0000000000000 -+#38: xssubdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff -+#39: xssubdp 0123214569900000 7ff8000000000000 = 7ff8000000000000 -+#40: xssubdp 7ff0000000000000 fff0000000000000 = 7ff0000000000000 -+#41: xssubdp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000 -+#42: xssubdp 7ff0000000000000 8000000000000000 = 7ff0000000000000 -+#43: xssubdp 7ff0000000000000 0000000000000000 = 7ff0000000000000 -+#44: xssubdp 7ff0000000000000 0123214569900000 = 7ff0000000000000 -+#45: xssubdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000 -+#46: xssubdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff -+#47: xssubdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000 -+#48: xssubdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff -+#49: xssubdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff -+#50: xssubdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff -+#51: xssubdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff -+#52: xssubdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff -+#53: xssubdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff -+#54: xssubdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff -+#55: xssubdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff -+#56: xssubdp fff8000000000000 fff0000000000000 = fff8000000000000 -+#57: xssubdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000 -+#58: xssubdp fff8000000000000 8000000000000000 = fff8000000000000 -+#59: xssubdp fff8000000000000 0000000000000000 = fff8000000000000 -+#60: xssubdp fff8000000000000 0123214569900000 = fff8000000000000 -+#61: xssubdp fff8000000000000 7ff0000000000000 = fff8000000000000 -+#62: xssubdp fff8000000000000 7ff7ffffffffffff = fff8000000000000 -+#63: xssubdp fff8000000000000 7ff8000000000000 = fff8000000000000 -+ -+ -+Test VSX scalar integer conversion instructions -+#0: xscvdpsxds 3fd8000000000000 => 0000000000000000 -+#1: xscvdpsxds 404f000000000000 => 000000000000003e -+#2: xscvdpsxds 0018000000b77501 => 0000000000000000 -+#3: xscvdpsxds 7fe800000000051b => 7fffffffffffffff -+#4: xscvdpsxds 0123214569900000 => 0000000000000000 -+#5: xscvdpsxds 0000000000000000 => 0000000000000000 -+#6: xscvdpsxds 8000000000000000 => 0000000000000000 -+#7: xscvdpsxds 7ff0000000000000 => 7fffffffffffffff -+#8: xscvdpsxds fff0000000000000 => 8000000000000000 -+#9: xscvdpsxds 7ff7ffffffffffff => 8000000000000000 -+#10: xscvdpsxds fff7ffffffffffff => 8000000000000000 -+#11: xscvdpsxds 7ff8000000000000 => 8000000000000000 -+#12: xscvdpsxds fff8000000000000 => 8000000000000000 -+#13: xscvdpsxds 8008340000078000 => 0000000000000000 -+#14: xscvdpsxds c0d0650f5a07b353 => ffffffffffffbe6c -+ -+#0: xscvsxddp 3fd8000000000000 => 43cfec0000000000 -+#1: xscvsxddp 404f000000000000 => 43d013c000000000 -+#2: xscvsxddp 0018000000b77501 => 4338000000b77501 -+#3: xscvsxddp 7fe800000000051b => 43dffa0000000001 -+#4: xscvsxddp 0123214569900000 => 4372321456990000 -+#5: xscvsxddp 0000000000000000 => 0000000000000000 -+#6: xscvsxddp 8000000000000000 => c3e0000000000000 -+#7: xscvsxddp 7ff0000000000000 => 43dffc0000000000 -+#8: xscvsxddp fff0000000000000 => c330000000000000 -+#9: xscvsxddp 7ff7ffffffffffff => 43dffe0000000000 -+#10: xscvsxddp fff7ffffffffffff => c320000000000002 -+#11: xscvsxddp 7ff8000000000000 => 43dffe0000000000 -+#12: xscvsxddp fff8000000000000 => c320000000000000 -+#13: xscvsxddp 8008340000078000 => c3dffdf2fffffe20 -+#14: xscvsxddp c0d0650f5a07b353 => c3cf97cd7852fc26 -+ -+#0: xscvuxddp 3fd8000000000000 => 43cfec0000000000 -+#1: xscvuxddp 404f000000000000 => 43d013c000000000 -+#2: xscvuxddp 0018000000b77501 => 4338000000b77501 -+#3: xscvuxddp 7fe800000000051b => 43dffa0000000001 -+#4: xscvuxddp 0123214569900000 => 4372321456990000 -+#5: xscvuxddp 0000000000000000 => 0000000000000000 -+#6: xscvuxddp 8000000000000000 => 43e0000000000000 -+#7: xscvuxddp 7ff0000000000000 => 43dffc0000000000 -+#8: xscvuxddp fff0000000000000 => 43effe0000000000 -+#9: xscvuxddp 7ff7ffffffffffff => 43dffe0000000000 -+#10: xscvuxddp fff7ffffffffffff => 43efff0000000000 -+#11: xscvuxddp 7ff8000000000000 => 43dffe0000000000 -+#12: xscvuxddp fff8000000000000 => 43efff0000000000 -+#13: xscvuxddp 8008340000078000 => 43e00106800000f0 -+#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6 -+ -+ -Index: none/tests/ppc64/jm-fp.stdout.exp -=================================================================== ---- none/tests/ppc64/jm-fp.stdout.exp.orig -+++ none/tests/ppc64/jm-fp.stdout.exp -@@ -692,11 +692,11 @@ PPC floating point compare insns (two ar - PPC floating point arith insns with one arg: - fres 0010000000000001 => 7ff0000000000000 - fres 00100094e0000359 => 7ff0000000000000 -- fres 3fe0000000000001 => 4000000000000000 -+ fres 3fe0000000000001 => 3ffff00000000000 - fres 3fe00094e0000359 => 3ffff00000000000 - fres 8010000000000001 => fff0000000000000 - fres 80100094e0000359 => fff0000000000000 -- fres bfe0000000000001 => c000000000000000 -+ fres bfe0000000000001 => bffff00000000000 - fres bfe00094e0000359 => bffff00000000000 - fres 0000000000000000 => 7ff0000000000000 - fres 8000000000000000 => fff0000000000000 -@@ -915,11 +915,11 @@ PPC floating point arith insns - with one arg with flags update: - fres. 0010000000000001 => 7ff0000000000000 - fres. 00100094e0000359 => 7ff0000000000000 -- fres. 3fe0000000000001 => 4000000000000000 -+ fres. 3fe0000000000001 => 3ffff00000000000 - fres. 3fe00094e0000359 => 3ffff00000000000 - fres. 8010000000000001 => fff0000000000000 - fres. 80100094e0000359 => fff0000000000000 -- fres. bfe0000000000001 => c000000000000000 -+ fres. bfe0000000000001 => bffff00000000000 - fres. bfe00094e0000359 => bffff00000000000 - fres. 0000000000000000 => 7ff0000000000000 - fres. 8000000000000000 => fff0000000000000 -@@ -1122,21 +1122,21 @@ PPC floating point status register manip - with flags update: - PPC float load insns - with one register + one 16 bits immediate args with flags update: -- lfs 0010000000000001, -120 => 37e0000000000000, 0 -- lfs 00100094e0000359, -112 => 37e0009400000000, 0 -- lfs 3fe0000000000001, -104 => 3ffc000000000000, 0 -- lfs 3fe00094e0000359, -96 => 3ffc001280000000, 0 -- lfs 8010000000000001, -88 => b7e0000000000000, 0 -- lfs 80100094e0000359, -80 => b7e0009400000000, 0 -- lfs bfe0000000000001, -72 => bffc000000000000, 0 -- lfs bfe00094e0000359, -64 => bffc001280000000, 0 -- lfs 0000000000000000, -56 => 0000000000000000, 0 -- lfs 8000000000000000, -48 => 8000000000000000, 0 -- lfs 7ff0000000000000, -40 => 7ffe000000000000, 0 -- lfs fff0000000000000, -32 => fffe000000000000, 0 -- lfs 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0 -- lfs fff7ffffffffffff, -16 => fffeffffe0000000, 0 -- lfs 7ff8000000000000, -8 => 7fff000000000000, 0 -+ lfs 0010000000000001, 65416 => 37e0000000000000, 0 -+ lfs 00100094e0000359, 65424 => 37e0009400000000, 0 -+ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0 -+ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0 -+ lfs 8010000000000001, 65448 => b7e0000000000000, 0 -+ lfs 80100094e0000359, 65456 => b7e0009400000000, 0 -+ lfs bfe0000000000001, 65464 => bffc000000000000, 0 -+ lfs bfe00094e0000359, 65472 => bffc001280000000, 0 -+ lfs 0000000000000000, 65480 => 0000000000000000, 0 -+ lfs 8000000000000000, 65488 => 8000000000000000, 0 -+ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0 -+ lfs fff0000000000000, 65504 => fffe000000000000, 0 -+ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0 -+ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0 -+ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0 - lfs 0010000000000001, 0 => 37e0000000000000, 0 - lfs 00100094e0000359, 8 => 37e0009400000000, 0 - lfs 3fe0000000000001, 16 => 3ffc000000000000, 0 -@@ -1154,21 +1154,21 @@ PPC float load insns - lfs 7ff8000000000000, 112 => 7fff000000000000, 0 - lfs fff8000000000000, 120 => ffff000000000000, 0 - -- lfsu 0010000000000001, -120 => 37e0000000000000, -120 -- lfsu 00100094e0000359, -112 => 37e0009400000000, -112 -- lfsu 3fe0000000000001, -104 => 3ffc000000000000, -104 -- lfsu 3fe00094e0000359, -96 => 3ffc001280000000, -96 -- lfsu 8010000000000001, -88 => b7e0000000000000, -88 -- lfsu 80100094e0000359, -80 => b7e0009400000000, -80 -- lfsu bfe0000000000001, -72 => bffc000000000000, -72 -- lfsu bfe00094e0000359, -64 => bffc001280000000, -64 -- lfsu 0000000000000000, -56 => 0000000000000000, -56 -- lfsu 8000000000000000, -48 => 8000000000000000, -48 -- lfsu 7ff0000000000000, -40 => 7ffe000000000000, -40 -- lfsu fff0000000000000, -32 => fffe000000000000, -32 -- lfsu 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24 -- lfsu fff7ffffffffffff, -16 => fffeffffe0000000, -16 -- lfsu 7ff8000000000000, -8 => 7fff000000000000, -8 -+ lfsu 0010000000000001, 65416 => 37e0000000000000, -120 -+ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112 -+ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104 -+ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96 -+ lfsu 8010000000000001, 65448 => b7e0000000000000, -88 -+ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80 -+ lfsu bfe0000000000001, 65464 => bffc000000000000, -72 -+ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64 -+ lfsu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfsu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40 -+ lfsu fff0000000000000, 65504 => fffe000000000000, -32 -+ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24 -+ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16 -+ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8 - lfsu 0010000000000001, 0 => 37e0000000000000, 0 - lfsu 00100094e0000359, 8 => 37e0009400000000, 8 - lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16 -@@ -1186,21 +1186,21 @@ PPC float load insns - lfsu 7ff8000000000000, 112 => 7fff000000000000, 112 - lfsu fff8000000000000, 120 => ffff000000000000, 120 - -- lfd 0010000000000001, -120 => 0010000000000001, 0 -- lfd 00100094e0000359, -112 => 00100094e0000359, 0 -- lfd 3fe0000000000001, -104 => 3fe0000000000001, 0 -- lfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -- lfd 8010000000000001, -88 => 8010000000000001, 0 -- lfd 80100094e0000359, -80 => 80100094e0000359, 0 -- lfd bfe0000000000001, -72 => bfe0000000000001, 0 -- lfd bfe00094e0000359, -64 => bfe00094e0000359, 0 -- lfd 0000000000000000, -56 => 0000000000000000, 0 -- lfd 8000000000000000, -48 => 8000000000000000, 0 -- lfd 7ff0000000000000, -40 => 7ff0000000000000, 0 -- lfd fff0000000000000, -32 => fff0000000000000, 0 -- lfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -- lfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -- lfd 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ lfd 0010000000000001, 65416 => 0010000000000001, 0 -+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 65448 => 8010000000000001, 0 -+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 65480 => 0000000000000000, 0 -+ lfd 8000000000000000, 65488 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 65504 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0 - lfd 0010000000000001, 0 => 0010000000000001, 0 - lfd 00100094e0000359, 8 => 00100094e0000359, 0 - lfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -@@ -1218,21 +1218,21 @@ PPC float load insns - lfd 7ff8000000000000, 112 => 7ff8000000000000, 0 - lfd fff8000000000000, 120 => fff8000000000000, 0 - -- lfdu 0010000000000001, -120 => 0010000000000001, -120 -- lfdu 00100094e0000359, -112 => 00100094e0000359, -112 -- lfdu 3fe0000000000001, -104 => 3fe0000000000001, -104 -- lfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -- lfdu 8010000000000001, -88 => 8010000000000001, -88 -- lfdu 80100094e0000359, -80 => 80100094e0000359, -80 -- lfdu bfe0000000000001, -72 => bfe0000000000001, -72 -- lfdu bfe00094e0000359, -64 => bfe00094e0000359, -64 -- lfdu 0000000000000000, -56 => 0000000000000000, -56 -- lfdu 8000000000000000, -48 => 8000000000000000, -48 -- lfdu 7ff0000000000000, -40 => 7ff0000000000000, -40 -- lfdu fff0000000000000, -32 => fff0000000000000, -32 -- lfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -- lfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -- lfdu 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ lfdu 0010000000000001, 65416 => 0010000000000001, -120 -+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112 -+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104 -+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96 -+ lfdu 8010000000000001, 65448 => 8010000000000001, -88 -+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80 -+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72 -+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64 -+ lfdu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfdu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40 -+ lfdu fff0000000000000, 65504 => fff0000000000000, -32 -+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24 -+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16 -+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8 - lfdu 0010000000000001, 0 => 0010000000000001, 0 - lfdu 00100094e0000359, 8 => 00100094e0000359, 8 - lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -Index: none/tests/ppc64/test_isa_2_07_part2.c -=================================================================== ---- none/tests/ppc64/test_isa_2_07_part2.c.orig -+++ none/tests/ppc64/test_isa_2_07_part2.c -@@ -40,6 +40,12 @@ typedef uint32_t HWord_t; - typedef uint64_t HWord_t; - #endif /* __powerpc64__ */ - -+#ifdef VGP_ppc64le_linux -+#define isLE 1 -+#else -+#define isLE 0 -+#endif -+ - register HWord_t r14 __asm__ ("r14"); - register HWord_t r15 __asm__ ("r15"); - register HWord_t r16 __asm__ ("r16"); -@@ -341,6 +347,16 @@ static unsigned int viargs[] __attribute - #define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0]) - #define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4) - -+ -+static unsigned long long vdargs[] __attribute__ ((aligned (16))) = { -+ 0x0102030405060708ULL, -+ 0x090A0B0C0E0D0E0FULL, -+ 0xF1F2F3F4F5F6F7F8ULL, -+ 0xF9FAFBFCFEFDFEFFULL -+}; -+#define NUM_VDARGS_INTS (sizeof vdargs/sizeof vdargs[0]) -+#define NUM_VDARGS_VECS (NUM_VDARGS_INTS/2) -+ - typedef void (*test_func_t)(void); - - struct test_table -@@ -727,7 +743,7 @@ static vx_fp_test_basic_t vx_fp_tests[] - - static vx_fp_test2_t - vsx_one_fp_arg_tests[] = { -- { &test_xscvdpspn, "xscvdpspn", NULL, 20, SINGLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"}, -+ { &test_xscvdpspn, "xscvdpspn", NULL, 20, DOUBLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"}, - { &test_xscvspdpn, "xscvspdpn", NULL, 20, SINGLE_TEST, VX_DEFAULT, "conv"}, - { &test_xsresp, "xsresp", NULL, 20, DOUBLE_TEST, VX_ESTIMATE, "1/x"}, - { &test_xsrsp, "xsrsp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "round"}, -@@ -749,7 +765,7 @@ ldst_tests[] = { - { &test_stxsspx, "stxsspx", DOUBLE_TEST_SINGLE_RES, vstg, 0, VSX_STORE }, - { &test_stxsiwx, "stxsiwx", SINGLE_TEST_SINGLE_RES, vstg, 4, VSX_STORE }, - { &test_lxsiwax, "lxsiwax", SINGLE_TEST, viargs, 0, VSX_LOAD }, -- { &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 1, VSX_LOAD }, -+ { &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 4, VSX_LOAD }, - { &test_lxsspx, "lxsspx", SINGLE_TEST, NULL, 0, VSX_LOAD }, - { NULL, NULL, 0, NULL, 0, 0 } }; - -@@ -881,8 +897,19 @@ static void test_vx_fp_ops(void) - test_func_t func; - int k; - char * test_name = (char *)malloc(20); -- k = 0; -+ void * vecA_void_ptr, * vecB_void_ptr, * vecOut_void_ptr; -+ -+ if (isLE) { -+ vecA_void_ptr = (void *)&vec_inA + 8; -+ vecB_void_ptr = (void *)&vec_inB + 8; -+ vecOut_void_ptr = (void *)&vec_out + 8; -+ } else { -+ vecA_void_ptr = (void *)&vec_inA; -+ vecB_void_ptr = (void *)&vec_inB; -+ vecOut_void_ptr = (void *)&vec_out; -+ } - -+ k = 0; - build_special_fargs_table(); - while ((func = vx_fp_tests[k].test_func)) { - int i, repeat = 0; -@@ -932,8 +959,8 @@ again: - pv = (unsigned int *)&vec_out; - - // Only need to copy one doubleword into each vector's element 0 -- memcpy(&vec_inA, inA, 8); -- memcpy(&vec_inB, inB, 8); -+ memcpy(vecA_void_ptr, inA, 8); -+ memcpy(vecB_void_ptr, inB, 8); - - // clear vec_out - for (idx = 0; idx < 4; idx++, pv++) -@@ -963,18 +990,20 @@ again: - * src2 <= VSX[XT] - * src3 <= VSX[XB] - */ -- memcpy(&vec_out, inB, 8); // src2 -- memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3 -+ memcpy(vecOut_void_ptr, inB, 8); // src2 -+ memcpy(vecB_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3 - frbp = (unsigned long long *)&spec_fargs[extra_arg_idx]; - } else { - // Don't need to init src2, as it's done before the switch() -- memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3 -+ memcpy(vecOut_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3 - } -- memcpy(&vsr_XT, &vec_out, 8); -+ memcpy(&vsr_XT, vecOut_void_ptr, 8); - } - - (*func)(); - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - - if (test_type == VX_FP_OTHER) - printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name, -@@ -1033,6 +1062,8 @@ static void test_vsx_one_fp_arg(void) - { - test_func_t func; - int k; -+ void * vecB_void_ptr; -+ - k = 0; - build_special_fargs_table(); - -@@ -1047,26 +1078,13 @@ static void test_vsx_one_fp_arg(void) - /* size of result */ - Bool dp_res = IS_DP_RESULT(test_group.precision); - Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False; -- Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False; -- Bool sparse_sp = False; -- int stride = dp ? 2 : 4; -- int loops = is_scalar ? 1 : stride; -- stride = is_scalar ? 1: stride; -- -- /* For conversions of single to double, the 128-bit input register is sparsely populated: -- * |___ SP___|_Unused_|___SP___|__Unused__| // for vector op -- * or -- * |___ SP___|_Unused_|_Unused_|__Unused__| // for scalar op -- * -- * For the vector op case, we need to adjust stride from '4' to '2', since -- * we'll only be loading two values per loop into the input register. -- */ -- if (!dp && !is_scalar && test_group.test_type == VX_CONV_TO_DOUBLE) { -- sparse_sp = True; -- stride = 2; -+ -+ vecB_void_ptr = (void *)&vec_inB; -+ if (isLE) { -+ vecB_void_ptr += dp? 8 : 12; - } - -- for (i = 0; i < test_group.num_tests; i+=stride) { -+ for (i = 0; i < test_group.num_tests; i++) { - unsigned int * pv; - void * inB; - -@@ -1076,13 +1094,26 @@ static void test_vsx_one_fp_arg(void) - *pv = 0; - - if (dp) { -- int j; -+ int vec_out_idx; - unsigned long long * frB_dp; -- for (j = 0; j < loops; j++) { -- inB = (void *)&spec_fargs[i + j]; -- // copy double precision FP into vector element i -- memcpy(((void *)&vec_inB) + (j * 8), inB, 8); -+ if (isLE) -+ vec_out_idx = dp_res ? 1 : 3; -+ else -+ vec_out_idx = 0; -+ -+ if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) { -+ /* Take a single-precision value stored in double word element 0 -+ * of src in double-precision format and convert to single- -+ * precision and store in word element 0 of dst. -+ */ -+ double input = spec_sp_fargs[i]; -+ memcpy(vecB_void_ptr, (void *)&input, 8); -+ } else { -+ inB = (void *)&spec_fargs[i]; -+ // copy double precision FP into input vector element 0 -+ memcpy(vecB_void_ptr, inB, 8); - } -+ - // execute test insn - (*func)(); - if (dp_res) -@@ -1090,56 +1121,34 @@ static void test_vsx_one_fp_arg(void) - else - dst_sp = (unsigned int *) &vec_out; - -- printf("#%d: %s ", i/stride, test_group.name); -- for (j = 0; j < loops; j++) { -- if (j) -- printf("; "); -- frB_dp = (unsigned long long *)&spec_fargs[i + j]; -- printf("%s(%016llx)", test_group.op, *frB_dp); -- if (test_group.test_type == VX_ESTIMATE) -- { -- Bool res; -- res = check_reciprocal_estimate(is_sqrt, i + j, j); -- printf(" ==> %s)", res ? "PASS" : "FAIL"); -- } else if (dp_res) { -- printf(" = %016llx", dst_dp[j]); -- } else { -- printf(" = %08x", dst_sp[j]); -- } -+ printf("#%d: %s ", i, test_group.name); -+ frB_dp = (unsigned long long *)&spec_fargs[i]; -+ printf("%s(%016llx)", test_group.op, *frB_dp); -+ if (test_group.test_type == VX_ESTIMATE) -+ { -+ Bool res; -+ res = check_reciprocal_estimate(is_sqrt, i, vec_out_idx); -+ printf(" ==> %s)", res ? "PASS" : "FAIL"); -+ } else if (dp_res) { -+ printf(" = %016llx", dst_dp[vec_out_idx]); -+ } else { -+ printf(" = %08x", dst_sp[vec_out_idx]); - } -+ - printf("\n"); - } else { // single precision test type -- int j; -+ int vec_out_idx; -+ if (isLE) -+ vec_out_idx = dp_res ? 1 : 3; -+ else -+ vec_out_idx = 0; - // Clear input vector - pv = (unsigned int *)&vec_inB; - for (idx = 0; idx < 4; idx++, pv++) - *pv = 0; -- -- if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) { -- /* Take a single-precision value stored in double word element 0 -- * of src in double-precision format and convert to single- -- * precision and store in word element 0 of dst. -- */ -- double input = spec_sp_fargs[i]; -- memcpy(((void *)&vec_inB), (void *)&input, 8); -- } else { -- int skip_slot; -- if (sparse_sp) { -- skip_slot = 1; -- loops = 2; -- } else { -- skip_slot = 0; -- } -- for (j = 0; j < loops; j++) { -- inB = (void *)&spec_sp_fargs[i + j]; -- // copy single precision FP into vector element i -- -- if (skip_slot && j > 0) -- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4); -- else -- memcpy(((void *)&vec_inB) + (j * 4), inB, 4); -- } -- } -+ inB = (void *)&spec_sp_fargs[i]; -+ // copy single precision FP into input vector element i -+ memcpy(vecB_void_ptr, inB, 4); - // execute test insn - (*func)(); - if (dp_res) -@@ -1147,16 +1156,13 @@ static void test_vsx_one_fp_arg(void) - else - dst_sp = (unsigned int *) &vec_out; - // print result -- printf("#%d: %s ", i/stride, test_group.name); -- for (j = 0; j < loops; j++) { -- if (j) -- printf("; "); -- printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i + j])); -+ printf("#%d: %s ", i, test_group.name); -+ printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i])); - if (dp_res) -- printf(" = %016llx", dst_dp[j]); -+ printf(" = %016llx", dst_dp[vec_out_idx]); - else -- printf(" = %08x", dst_sp[j]); -- } -+ printf(" = %08x", dst_sp[vec_out_idx]); -+ - printf("\n"); - } - } -@@ -1170,6 +1176,15 @@ static void test_vsx_two_fp_arg(void) - { - test_func_t func; - int k = 0; -+ void * vecA_void_ptr, * vecB_void_ptr; -+ -+ if (isLE) { -+ vecA_void_ptr = (void *)&vec_inA + 8; -+ vecB_void_ptr = (void *)&vec_inB + 8; -+ } else { -+ vecA_void_ptr = (void *)&vec_inA; -+ vecB_void_ptr = (void *)&vec_inB; -+ } - - build_special_fargs_table(); - while ((func = vx_simple_scalar_fp_tests[k].test_func)) { -@@ -1191,10 +1206,12 @@ static void test_vsx_two_fp_arg(void) - frap = (unsigned long long *)&spec_fargs[aTest.fra_idx]; - frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx]; - // Only need to copy one doubleword into each vector's element 0 -- memcpy(&vec_inA, inA, 8); -- memcpy(&vec_inB, inB, 8); -+ memcpy(vecA_void_ptr, inA, 8); -+ memcpy(vecB_void_ptr, inB, 8); - (*func)(); - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name, - *frap, *frbp, *dst); - } -@@ -1214,84 +1231,91 @@ static void _do_store_test (ldst_test_t - unsigned int *dst32; - unsigned int i, idx; - unsigned int * pv = (unsigned int *) storeTest.base_addr; -+ void * vecA_void_ptr; -+ -+ if (isLE) { -+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES) -+ vecA_void_ptr = (void *)&vec_inA + 8; -+ } else { -+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES) -+ vecA_void_ptr = (void *)&vec_inA + 4; -+ else -+ vecA_void_ptr = (void *)&vec_inA; -+ } - - func = storeTest.test_func; - r14 = (HWord_t) storeTest.base_addr; - r15 = (HWord_t) storeTest.offset; - -- if (storeTest.precision == DOUBLE_TEST_SINGLE_RES) { -- /* source is single precision stored in double precision format */ -- /* test some of the pre-defined single precision values */ -- for (i = 0; i < nb_special_fargs; i+=3) { -- // clear out storage destination -- for (idx = 0; idx < 4; idx++) -- *(pv + idx) = 0; -- -- printf( "%s:", storeTest.name ); -+ /* test some of the pre-defined single precision values */ -+ for (i = 0; i < nb_special_fargs; i+=3) { -+ // clear out storage destination -+ for (idx = 0; idx < 4; idx++) -+ *(pv + idx) = 0; -+ -+ printf( "%s:", storeTest.name ); -+ if (storeTest.precision == SINGLE_TEST_SINGLE_RES) -+ { -+ unsigned int * arg_ptr = (unsigned int *)&spec_sp_fargs[i]; -+ memcpy(vecA_void_ptr, arg_ptr, sizeof(unsigned int)); -+ printf(" %08x ==> ", *arg_ptr); -+ } else { - unsigned long long * dp; - double input = spec_sp_fargs[i]; - dp = (unsigned long long *)&input; -- memcpy(&vec_inA, dp, sizeof(unsigned long long)); -+ memcpy(vecA_void_ptr, dp, sizeof(unsigned long long)); - printf(" %016llx ==> ", *dp); -- -- // execute test insn -- (*func)(); -- dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset); -- printf( "%08x\n", *dst32); - } -- } else { -- // source is an integer word -- for (i = 0; i < NUM_VIARGS_INTS; i++) { -- // clear out storage destination -- for (idx = 0; idx < 4; idx++) -- *(pv + idx) = 0; -- printf( "%s:", storeTest.name ); -- unsigned int * pi = (unsigned int *)&vec_inA; -- memcpy(pi + 1, &viargs[i], sizeof(unsigned int)); -- printf(" %08x ==> ", *(pi + 1)); - -- // execute test insn -- (*func)(); -- dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset); -- printf( "%08x\n", *dst32); -- } -+ // execute test insn -+ (*func)(); -+ dst32 = (unsigned int*)(storeTest.base_addr); -+ dst32 += (storeTest.offset/sizeof(int)); -+ printf( "%08x\n", *dst32); - } -+ - printf("\n"); - } - --static void _do_load_test(ldst_test_t storeTest) -+static void _do_load_test(ldst_test_t loadTest) - { - test_func_t func; - unsigned int i; - unsigned long long * dst_dp; - -- func = storeTest.test_func; -- r15 = (HWord_t) storeTest.offset; -+ func = loadTest.test_func; -+ r15 = (HWord_t) loadTest.offset; - -- if (storeTest.base_addr == NULL) { -+ if (loadTest.base_addr == NULL) { - /* Test lxsspx: source is single precision value, so let's */ - /* test some of the pre-defined single precision values. */ -- for (i = 0; i + storeTest.offset < nb_special_fargs; i+=3) { -- unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + storeTest.offset]; -- printf( "%s:", storeTest.name ); -+ int num_loops = (loadTest.offset == 0) ? nb_special_fargs : (nb_special_fargs - (loadTest.offset/sizeof(int))); -+ for (i = 0; i < num_loops; i+=3) { -+ unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + (loadTest.offset/sizeof(int))]; -+ printf( "%s:", loadTest.name ); - printf(" %08x ==> ", *sp); - r14 = (HWord_t)&spec_sp_fargs[i]; - - // execute test insn - (*func)(); - dst_dp = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst_dp++; - printf("%016llx\n", *dst_dp); - } - } else { - // source is an integer word -- for (i = 0; i < NUM_VIARGS_INTS; i++) { -- printf( "%s:", storeTest.name ); -- r14 = (HWord_t)&viargs[i + storeTest.offset]; -- printf(" %08x ==> ", viargs[i + storeTest.offset]); -+ int num_loops = (loadTest.offset == 0) ? NUM_VIARGS_INTS : (NUM_VIARGS_INTS - (loadTest.offset/sizeof(int))); -+ for (i = 0; i < num_loops; i++) { -+ printf( "%s:", loadTest.name ); -+ r14 = (HWord_t)&viargs[i]; -+ printf(" %08x ==> ", viargs[i + (loadTest.offset/sizeof(int))]); - - // execute test insn - (*func)(); - dst_dp = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst_dp++; - printf("%016llx\n", *dst_dp); - } - } -@@ -1318,24 +1342,32 @@ static void test_xs_conv_ops(void) - - test_func_t func; - int k = 0; -+ void * vecB_void_ptr; -+ -+ if (isLE) -+ vecB_void_ptr = (void *)&vec_inB + 8; -+ else -+ vecB_void_ptr = (void *)&vec_inB; - - build_special_fargs_table(); - while ((func = xs_conv_tests[k].test_func)) { - int i; - unsigned long long * dst; - xs_conv_test_t test_group = xs_conv_tests[k]; -- for (i = 0; i < NUM_VIARGS_INTS; i++) { -- unsigned int * inB, * pv; -+ for (i = 0; i < NUM_VDARGS_INTS; i++) { -+ unsigned long long * inB, * pv; - int idx; -- inB = (unsigned int *)&viargs[i]; -- memcpy(&vec_inB, inB, 4); -- pv = (unsigned int *)&vec_out; -+ inB = (unsigned long long *)&vdargs[i]; -+ memcpy(vecB_void_ptr, inB, 8); -+ pv = (unsigned long long *)&vec_out; - // clear vec_out -- for (idx = 0; idx < 4; idx++, pv++) -- *pv = 0; -+ for (idx = 0; idx < 2; idx++, pv++) -+ *pv = 0ULL; - (*func)(); - dst = (unsigned long long *) &vec_out; -- printf("#%d: %s %08x => %016llx\n", i, test_group.name, viargs[i], *dst); -+ if (isLE) -+ dst++; -+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, vdargs[i], *dst); - } - k++; - printf("\n"); -Index: none/tests/ppc64/jm_vec_isa_2_07.stdout.exp -=================================================================== ---- none/tests/ppc64/jm_vec_isa_2_07.stdout.exp.orig -+++ none/tests/ppc64/jm_vec_isa_2_07.stdout.exp -@@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0 - vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0 - vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000 - --vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a -+vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000 - vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000 --vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea -+vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000 - vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000 - - vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000 -Index: none/tests/ppc64/jm-fp.stdout.exp-LE -=================================================================== ---- /dev/null -+++ none/tests/ppc64/jm-fp.stdout.exp-LE -@@ -0,0 +1,1533 @@ -+PPC floating point arith insns with three args: -+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns -+ with three args with flags update: -+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns with two args: -+ fadd 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns -+ with two args with flags update: -+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point compare insns (two args): -+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns with one arg: -+ fres 0010000000000001 => 7ff0000000000000 -+ fres 00100094e0000359 => 7ff0000000000000 -+ fres 3fe0000000000001 => 3ffff00000000000 -+ fres 3fe00094e0000359 => 3ffff00000000000 -+ fres 8010000000000001 => fff0000000000000 -+ fres 80100094e0000359 => fff0000000000000 -+ fres bfe0000000000001 => bffff00000000000 -+ fres bfe00094e0000359 => bffff00000000000 -+ fres 0000000000000000 => 7ff0000000000000 -+ fres 8000000000000000 => fff0000000000000 -+ fres 7ff0000000000000 => 0000000000000000 -+ fres fff0000000000000 => 8000000000000000 -+ fres 7ff7ffffffffffff => 7ffff00000000000 -+ fres fff7ffffffffffff => fffff00000000000 -+ fres 7ff8000000000000 => 7ff8000000000000 -+ fres fff8000000000000 => fff8000000000000 -+ -+ frsqrte 0010000000000001 => 5fdf000000000000 -+ frsqrte 00100094e0000359 => 5fdf000000000000 -+ frsqrte 3fe0000000000001 => 3ff6000000000000 -+ frsqrte 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte 8010000000000001 => 7ff8000000000000 -+ frsqrte 80100094e0000359 => 7ff8000000000000 -+ frsqrte bfe0000000000001 => 7ff8000000000000 -+ frsqrte bfe00094e0000359 => 7ff8000000000000 -+ frsqrte 0000000000000000 => 7ff0000000000000 -+ frsqrte 8000000000000000 => fff0000000000000 -+ frsqrte 7ff0000000000000 => 0000000000000000 -+ frsqrte fff0000000000000 => 7ff8000000000000 -+ frsqrte 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte fff7ffffffffffff => ffff000000000000 -+ frsqrte 7ff8000000000000 => 7ff8000000000000 -+ frsqrte fff8000000000000 => fff8000000000000 -+ -+ frsp 0010000000000001 => 0000000000000000 -+ frsp 00100094e0000359 => 0000000000000000 -+ frsp 3fe0000000000001 => 3fe0000000000000 -+ frsp 3fe00094e0000359 => 3fe00094e0000000 -+ frsp 8010000000000001 => 8000000000000000 -+ frsp 80100094e0000359 => 8000000000000000 -+ frsp bfe0000000000001 => bfe0000000000000 -+ frsp bfe00094e0000359 => bfe00094e0000000 -+ frsp 0000000000000000 => 0000000000000000 -+ frsp 8000000000000000 => 8000000000000000 -+ frsp 7ff0000000000000 => 7ff0000000000000 -+ frsp fff0000000000000 => fff0000000000000 -+ frsp 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp fff7ffffffffffff => ffffffffe0000000 -+ frsp 7ff8000000000000 => 7ff8000000000000 -+ frsp fff8000000000000 => fff8000000000000 -+ -+ fctiw 0010000000000001 => 0000000000000000 -+ fctiw 00100094e0000359 => 0000000000000000 -+ fctiw 3fe0000000000001 => 0000000000000001 -+ fctiw 3fe00094e0000359 => 0000000000000001 -+ fctiw 8010000000000001 => 0000000000000000 -+ fctiw 80100094e0000359 => 0000000000000000 -+ fctiw bfe0000000000001 => 00000000ffffffff -+ fctiw bfe00094e0000359 => 00000000ffffffff -+ fctiw 0000000000000000 => 0000000000000000 -+ fctiw 8000000000000000 => 0000000000000000 -+ fctiw 7ff0000000000000 => 000000007fffffff -+ fctiw fff0000000000000 => 0000000080000000 -+ fctiw 7ff7ffffffffffff => 0000000080000000 -+ fctiw fff7ffffffffffff => 0000000080000000 -+ fctiw 7ff8000000000000 => 0000000080000000 -+ fctiw fff8000000000000 => 0000000080000000 -+ -+ fctiwz 0010000000000001 => 0000000000000000 -+ fctiwz 00100094e0000359 => 0000000000000000 -+ fctiwz 3fe0000000000001 => 0000000000000000 -+ fctiwz 3fe00094e0000359 => 0000000000000000 -+ fctiwz 8010000000000001 => 0000000000000000 -+ fctiwz 80100094e0000359 => 0000000000000000 -+ fctiwz bfe0000000000001 => 0000000000000000 -+ fctiwz bfe00094e0000359 => 0000000000000000 -+ fctiwz 0000000000000000 => 0000000000000000 -+ fctiwz 8000000000000000 => 0000000000000000 -+ fctiwz 7ff0000000000000 => 000000007fffffff -+ fctiwz fff0000000000000 => 0000000080000000 -+ fctiwz 7ff7ffffffffffff => 0000000080000000 -+ fctiwz fff7ffffffffffff => 0000000080000000 -+ fctiwz 7ff8000000000000 => 0000000080000000 -+ fctiwz fff8000000000000 => 0000000080000000 -+ -+ fmr 0010000000000001 => 0010000000000001 -+ fmr 00100094e0000359 => 00100094e0000359 -+ fmr 3fe0000000000001 => 3fe0000000000001 -+ fmr 3fe00094e0000359 => 3fe00094e0000359 -+ fmr 8010000000000001 => 8010000000000001 -+ fmr 80100094e0000359 => 80100094e0000359 -+ fmr bfe0000000000001 => bfe0000000000001 -+ fmr bfe00094e0000359 => bfe00094e0000359 -+ fmr 0000000000000000 => 0000000000000000 -+ fmr 8000000000000000 => 8000000000000000 -+ fmr 7ff0000000000000 => 7ff0000000000000 -+ fmr fff0000000000000 => fff0000000000000 -+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr fff7ffffffffffff => fff7ffffffffffff -+ fmr 7ff8000000000000 => 7ff8000000000000 -+ fmr fff8000000000000 => fff8000000000000 -+ -+ fneg 0010000000000001 => 8010000000000001 -+ fneg 00100094e0000359 => 80100094e0000359 -+ fneg 3fe0000000000001 => bfe0000000000001 -+ fneg 3fe00094e0000359 => bfe00094e0000359 -+ fneg 8010000000000001 => 0010000000000001 -+ fneg 80100094e0000359 => 00100094e0000359 -+ fneg bfe0000000000001 => 3fe0000000000001 -+ fneg bfe00094e0000359 => 3fe00094e0000359 -+ fneg 0000000000000000 => 8000000000000000 -+ fneg 8000000000000000 => 0000000000000000 -+ fneg 7ff0000000000000 => fff0000000000000 -+ fneg fff0000000000000 => 7ff0000000000000 -+ fneg 7ff7ffffffffffff => fff7ffffffffffff -+ fneg fff7ffffffffffff => 7ff7ffffffffffff -+ fneg 7ff8000000000000 => fff8000000000000 -+ fneg fff8000000000000 => 7ff8000000000000 -+ -+ fabs 0010000000000001 => 0010000000000001 -+ fabs 00100094e0000359 => 00100094e0000359 -+ fabs 3fe0000000000001 => 3fe0000000000001 -+ fabs 3fe00094e0000359 => 3fe00094e0000359 -+ fabs 8010000000000001 => 0010000000000001 -+ fabs 80100094e0000359 => 00100094e0000359 -+ fabs bfe0000000000001 => 3fe0000000000001 -+ fabs bfe00094e0000359 => 3fe00094e0000359 -+ fabs 0000000000000000 => 0000000000000000 -+ fabs 8000000000000000 => 0000000000000000 -+ fabs 7ff0000000000000 => 7ff0000000000000 -+ fabs fff0000000000000 => 7ff0000000000000 -+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs fff7ffffffffffff => 7ff7ffffffffffff -+ fabs 7ff8000000000000 => 7ff8000000000000 -+ fabs fff8000000000000 => 7ff8000000000000 -+ -+ fnabs 0010000000000001 => 8010000000000001 -+ fnabs 00100094e0000359 => 80100094e0000359 -+ fnabs 3fe0000000000001 => bfe0000000000001 -+ fnabs 3fe00094e0000359 => bfe00094e0000359 -+ fnabs 8010000000000001 => 8010000000000001 -+ fnabs 80100094e0000359 => 80100094e0000359 -+ fnabs bfe0000000000001 => bfe0000000000001 -+ fnabs bfe00094e0000359 => bfe00094e0000359 -+ fnabs 0000000000000000 => 8000000000000000 -+ fnabs 8000000000000000 => 8000000000000000 -+ fnabs 7ff0000000000000 => fff0000000000000 -+ fnabs fff0000000000000 => fff0000000000000 -+ fnabs 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs fff7ffffffffffff => fff7ffffffffffff -+ fnabs 7ff8000000000000 => fff8000000000000 -+ fnabs fff8000000000000 => fff8000000000000 -+ -+ fsqrt 0010000000000001 => 2000000000000000 -+ fsqrt 00100094e0000359 => 2000004a6f52dd4a -+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd -+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df -+ fsqrt 8010000000000001 => 7ff8000000000000 -+ fsqrt 80100094e0000359 => 7ff8000000000000 -+ fsqrt bfe0000000000001 => 7ff8000000000000 -+ fsqrt bfe00094e0000359 => 7ff8000000000000 -+ fsqrt 0000000000000000 => 0000000000000000 -+ fsqrt 8000000000000000 => 8000000000000000 -+ fsqrt 7ff0000000000000 => 7ff0000000000000 -+ fsqrt fff0000000000000 => 7ff8000000000000 -+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff -+ fsqrt fff7ffffffffffff => ffffffffffffffff -+ fsqrt 7ff8000000000000 => 7ff8000000000000 -+ fsqrt fff8000000000000 => fff8000000000000 -+ -+ fcfid 0010000000000001 => 4330000000000001 -+ fcfid 00100094e0000359 => 43300094e0000359 -+ fcfid 3fe0000000000001 => 43cff00000000000 -+ fcfid 3fe00094e0000359 => 43cff0004a700002 -+ fcfid 8010000000000001 => c3dffc0000000000 -+ fcfid 80100094e0000359 => c3dffbffdac7ffff -+ fcfid bfe0000000000001 => c3d0080000000000 -+ fcfid bfe00094e0000359 => c3d007ffdac7ffff -+ fcfid 0000000000000000 => 0000000000000000 -+ fcfid 8000000000000000 => c3e0000000000000 -+ fcfid 7ff0000000000000 => 43dffc0000000000 -+ fcfid fff0000000000000 => c330000000000000 -+ fcfid 7ff7ffffffffffff => 43dffe0000000000 -+ fcfid fff7ffffffffffff => c320000000000002 -+ fcfid 7ff8000000000000 => 43dffe0000000000 -+ fcfid fff8000000000000 => c320000000000000 -+ -+ fctid 0010000000000001 => 0000000000000000 -+ fctid 00100094e0000359 => 0000000000000000 -+ fctid 3fe0000000000001 => 0000000000000001 -+ fctid 3fe00094e0000359 => 0000000000000001 -+ fctid 8010000000000001 => 0000000000000000 -+ fctid 80100094e0000359 => 0000000000000000 -+ fctid bfe0000000000001 => ffffffffffffffff -+ fctid bfe00094e0000359 => ffffffffffffffff -+ fctid 0000000000000000 => 0000000000000000 -+ fctid 8000000000000000 => 0000000000000000 -+ fctid 7ff0000000000000 => 7fffffffffffffff -+ fctid fff0000000000000 => 8000000000000000 -+ fctid 7ff7ffffffffffff => 8000000000000000 -+ fctid fff7ffffffffffff => 8000000000000000 -+ fctid 7ff8000000000000 => 8000000000000000 -+ fctid fff8000000000000 => 8000000000000000 -+ -+ fctidz 0010000000000001 => 0000000000000000 -+ fctidz 00100094e0000359 => 0000000000000000 -+ fctidz 3fe0000000000001 => 0000000000000000 -+ fctidz 3fe00094e0000359 => 0000000000000000 -+ fctidz 8010000000000001 => 0000000000000000 -+ fctidz 80100094e0000359 => 0000000000000000 -+ fctidz bfe0000000000001 => 0000000000000000 -+ fctidz bfe00094e0000359 => 0000000000000000 -+ fctidz 0000000000000000 => 0000000000000000 -+ fctidz 8000000000000000 => 0000000000000000 -+ fctidz 7ff0000000000000 => 7fffffffffffffff -+ fctidz fff0000000000000 => 8000000000000000 -+ fctidz 7ff7ffffffffffff => 8000000000000000 -+ fctidz fff7ffffffffffff => 8000000000000000 -+ fctidz 7ff8000000000000 => 8000000000000000 -+ fctidz fff8000000000000 => 8000000000000000 -+ -+PPC floating point arith insns -+ with one arg with flags update: -+ fres. 0010000000000001 => 7ff0000000000000 -+ fres. 00100094e0000359 => 7ff0000000000000 -+ fres. 3fe0000000000001 => 3ffff00000000000 -+ fres. 3fe00094e0000359 => 3ffff00000000000 -+ fres. 8010000000000001 => fff0000000000000 -+ fres. 80100094e0000359 => fff0000000000000 -+ fres. bfe0000000000001 => bffff00000000000 -+ fres. bfe00094e0000359 => bffff00000000000 -+ fres. 0000000000000000 => 7ff0000000000000 -+ fres. 8000000000000000 => fff0000000000000 -+ fres. 7ff0000000000000 => 0000000000000000 -+ fres. fff0000000000000 => 8000000000000000 -+ fres. 7ff7ffffffffffff => 7ffff00000000000 -+ fres. fff7ffffffffffff => fffff00000000000 -+ fres. 7ff8000000000000 => 7ff8000000000000 -+ fres. fff8000000000000 => fff8000000000000 -+ -+ frsqrte. 0010000000000001 => 5fdf000000000000 -+ frsqrte. 00100094e0000359 => 5fdf000000000000 -+ frsqrte. 3fe0000000000001 => 3ff6000000000000 -+ frsqrte. 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte. 8010000000000001 => 7ff8000000000000 -+ frsqrte. 80100094e0000359 => 7ff8000000000000 -+ frsqrte. bfe0000000000001 => 7ff8000000000000 -+ frsqrte. bfe00094e0000359 => 7ff8000000000000 -+ frsqrte. 0000000000000000 => 7ff0000000000000 -+ frsqrte. 8000000000000000 => fff0000000000000 -+ frsqrte. 7ff0000000000000 => 0000000000000000 -+ frsqrte. fff0000000000000 => 7ff8000000000000 -+ frsqrte. 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte. fff7ffffffffffff => ffff000000000000 -+ frsqrte. 7ff8000000000000 => 7ff8000000000000 -+ frsqrte. fff8000000000000 => fff8000000000000 -+ -+ frsp. 0010000000000001 => 0000000000000000 -+ frsp. 00100094e0000359 => 0000000000000000 -+ frsp. 3fe0000000000001 => 3fe0000000000000 -+ frsp. 3fe00094e0000359 => 3fe00094e0000000 -+ frsp. 8010000000000001 => 8000000000000000 -+ frsp. 80100094e0000359 => 8000000000000000 -+ frsp. bfe0000000000001 => bfe0000000000000 -+ frsp. bfe00094e0000359 => bfe00094e0000000 -+ frsp. 0000000000000000 => 0000000000000000 -+ frsp. 8000000000000000 => 8000000000000000 -+ frsp. 7ff0000000000000 => 7ff0000000000000 -+ frsp. fff0000000000000 => fff0000000000000 -+ frsp. 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp. fff7ffffffffffff => ffffffffe0000000 -+ frsp. 7ff8000000000000 => 7ff8000000000000 -+ frsp. fff8000000000000 => fff8000000000000 -+ -+ fctiw. 0010000000000001 => 0000000000000000 -+ fctiw. 00100094e0000359 => 0000000000000000 -+ fctiw. 3fe0000000000001 => 0000000000000001 -+ fctiw. 3fe00094e0000359 => 0000000000000001 -+ fctiw. 8010000000000001 => 0000000000000000 -+ fctiw. 80100094e0000359 => 0000000000000000 -+ fctiw. bfe0000000000001 => 00000000ffffffff -+ fctiw. bfe00094e0000359 => 00000000ffffffff -+ fctiw. 0000000000000000 => 0000000000000000 -+ fctiw. 8000000000000000 => 0000000000000000 -+ fctiw. 7ff0000000000000 => 000000007fffffff -+ fctiw. fff0000000000000 => 0000000080000000 -+ fctiw. 7ff7ffffffffffff => 0000000080000000 -+ fctiw. fff7ffffffffffff => 0000000080000000 -+ fctiw. 7ff8000000000000 => 0000000080000000 -+ fctiw. fff8000000000000 => 0000000080000000 -+ -+ fctiwz. 0010000000000001 => 0000000000000000 -+ fctiwz. 00100094e0000359 => 0000000000000000 -+ fctiwz. 3fe0000000000001 => 0000000000000000 -+ fctiwz. 3fe00094e0000359 => 0000000000000000 -+ fctiwz. 8010000000000001 => 0000000000000000 -+ fctiwz. 80100094e0000359 => 0000000000000000 -+ fctiwz. bfe0000000000001 => 0000000000000000 -+ fctiwz. bfe00094e0000359 => 0000000000000000 -+ fctiwz. 0000000000000000 => 0000000000000000 -+ fctiwz. 8000000000000000 => 0000000000000000 -+ fctiwz. 7ff0000000000000 => 000000007fffffff -+ fctiwz. fff0000000000000 => 0000000080000000 -+ fctiwz. 7ff7ffffffffffff => 0000000080000000 -+ fctiwz. fff7ffffffffffff => 0000000080000000 -+ fctiwz. 7ff8000000000000 => 0000000080000000 -+ fctiwz. fff8000000000000 => 0000000080000000 -+ -+ fmr. 0010000000000001 => 0010000000000001 -+ fmr. 00100094e0000359 => 00100094e0000359 -+ fmr. 3fe0000000000001 => 3fe0000000000001 -+ fmr. 3fe00094e0000359 => 3fe00094e0000359 -+ fmr. 8010000000000001 => 8010000000000001 -+ fmr. 80100094e0000359 => 80100094e0000359 -+ fmr. bfe0000000000001 => bfe0000000000001 -+ fmr. bfe00094e0000359 => bfe00094e0000359 -+ fmr. 0000000000000000 => 0000000000000000 -+ fmr. 8000000000000000 => 8000000000000000 -+ fmr. 7ff0000000000000 => 7ff0000000000000 -+ fmr. fff0000000000000 => fff0000000000000 -+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr. fff7ffffffffffff => fff7ffffffffffff -+ fmr. 7ff8000000000000 => 7ff8000000000000 -+ fmr. fff8000000000000 => fff8000000000000 -+ -+ fneg. 0010000000000001 => 8010000000000001 -+ fneg. 00100094e0000359 => 80100094e0000359 -+ fneg. 3fe0000000000001 => bfe0000000000001 -+ fneg. 3fe00094e0000359 => bfe00094e0000359 -+ fneg. 8010000000000001 => 0010000000000001 -+ fneg. 80100094e0000359 => 00100094e0000359 -+ fneg. bfe0000000000001 => 3fe0000000000001 -+ fneg. bfe00094e0000359 => 3fe00094e0000359 -+ fneg. 0000000000000000 => 8000000000000000 -+ fneg. 8000000000000000 => 0000000000000000 -+ fneg. 7ff0000000000000 => fff0000000000000 -+ fneg. fff0000000000000 => 7ff0000000000000 -+ fneg. 7ff7ffffffffffff => fff7ffffffffffff -+ fneg. fff7ffffffffffff => 7ff7ffffffffffff -+ fneg. 7ff8000000000000 => fff8000000000000 -+ fneg. fff8000000000000 => 7ff8000000000000 -+ -+ fabs. 0010000000000001 => 0010000000000001 -+ fabs. 00100094e0000359 => 00100094e0000359 -+ fabs. 3fe0000000000001 => 3fe0000000000001 -+ fabs. 3fe00094e0000359 => 3fe00094e0000359 -+ fabs. 8010000000000001 => 0010000000000001 -+ fabs. 80100094e0000359 => 00100094e0000359 -+ fabs. bfe0000000000001 => 3fe0000000000001 -+ fabs. bfe00094e0000359 => 3fe00094e0000359 -+ fabs. 0000000000000000 => 0000000000000000 -+ fabs. 8000000000000000 => 0000000000000000 -+ fabs. 7ff0000000000000 => 7ff0000000000000 -+ fabs. fff0000000000000 => 7ff0000000000000 -+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs. fff7ffffffffffff => 7ff7ffffffffffff -+ fabs. 7ff8000000000000 => 7ff8000000000000 -+ fabs. fff8000000000000 => 7ff8000000000000 -+ -+ fnabs. 0010000000000001 => 8010000000000001 -+ fnabs. 00100094e0000359 => 80100094e0000359 -+ fnabs. 3fe0000000000001 => bfe0000000000001 -+ fnabs. 3fe00094e0000359 => bfe00094e0000359 -+ fnabs. 8010000000000001 => 8010000000000001 -+ fnabs. 80100094e0000359 => 80100094e0000359 -+ fnabs. bfe0000000000001 => bfe0000000000001 -+ fnabs. bfe00094e0000359 => bfe00094e0000359 -+ fnabs. 0000000000000000 => 8000000000000000 -+ fnabs. 8000000000000000 => 8000000000000000 -+ fnabs. 7ff0000000000000 => fff0000000000000 -+ fnabs. fff0000000000000 => fff0000000000000 -+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs. fff7ffffffffffff => fff7ffffffffffff -+ fnabs. 7ff8000000000000 => fff8000000000000 -+ fnabs. fff8000000000000 => fff8000000000000 -+ -+ fcfid. 0010000000000001 => 4330000000000001 -+ fcfid. 00100094e0000359 => 43300094e0000359 -+ fcfid. 3fe0000000000001 => 43cff00000000000 -+ fcfid. 3fe00094e0000359 => 43cff0004a700002 -+ fcfid. 8010000000000001 => c3dffc0000000000 -+ fcfid. 80100094e0000359 => c3dffbffdac7ffff -+ fcfid. bfe0000000000001 => c3d0080000000000 -+ fcfid. bfe00094e0000359 => c3d007ffdac7ffff -+ fcfid. 0000000000000000 => 0000000000000000 -+ fcfid. 8000000000000000 => c3e0000000000000 -+ fcfid. 7ff0000000000000 => 43dffc0000000000 -+ fcfid. fff0000000000000 => c330000000000000 -+ fcfid. 7ff7ffffffffffff => 43dffe0000000000 -+ fcfid. fff7ffffffffffff => c320000000000002 -+ fcfid. 7ff8000000000000 => 43dffe0000000000 -+ fcfid. fff8000000000000 => c320000000000000 -+ -+ fctid. 0010000000000001 => 0000000000000000 -+ fctid. 00100094e0000359 => 0000000000000000 -+ fctid. 3fe0000000000001 => 0000000000000001 -+ fctid. 3fe00094e0000359 => 0000000000000001 -+ fctid. 8010000000000001 => 0000000000000000 -+ fctid. 80100094e0000359 => 0000000000000000 -+ fctid. bfe0000000000001 => ffffffffffffffff -+ fctid. bfe00094e0000359 => ffffffffffffffff -+ fctid. 0000000000000000 => 0000000000000000 -+ fctid. 8000000000000000 => 0000000000000000 -+ fctid. 7ff0000000000000 => 7fffffffffffffff -+ fctid. fff0000000000000 => 8000000000000000 -+ fctid. 7ff7ffffffffffff => 8000000000000000 -+ fctid. fff7ffffffffffff => 8000000000000000 -+ fctid. 7ff8000000000000 => 8000000000000000 -+ fctid. fff8000000000000 => 8000000000000000 -+ -+ fctidz. 0010000000000001 => 0000000000000000 -+ fctidz. 00100094e0000359 => 0000000000000000 -+ fctidz. 3fe0000000000001 => 0000000000000000 -+ fctidz. 3fe00094e0000359 => 0000000000000000 -+ fctidz. 8010000000000001 => 0000000000000000 -+ fctidz. 80100094e0000359 => 0000000000000000 -+ fctidz. bfe0000000000001 => 0000000000000000 -+ fctidz. bfe00094e0000359 => 0000000000000000 -+ fctidz. 0000000000000000 => 0000000000000000 -+ fctidz. 8000000000000000 => 0000000000000000 -+ fctidz. 7ff0000000000000 => 7fffffffffffffff -+ fctidz. fff0000000000000 => 8000000000000000 -+ fctidz. 7ff7ffffffffffff => 8000000000000000 -+ fctidz. fff7ffffffffffff => 8000000000000000 -+ fctidz. 7ff8000000000000 => 8000000000000000 -+ fctidz. fff8000000000000 => 8000000000000000 -+ -+PPC floating point status register manipulation insns: -+PPC floating point status register manipulation insns -+ with flags update: -+PPC float load insns -+ with one register + one 16 bits immediate args with flags update: -+ lfs 0010000000000001, 65416 => 36a0000000000000, 0 -+ lfs 00100094e0000359, 65424 => c400006b20000000, 0 -+ lfs 3fe0000000000001, 65432 => 36a0000000000000, 0 -+ lfs 3fe00094e0000359, 65440 => c400006b20000000, 0 -+ lfs 8010000000000001, 65448 => 36a0000000000000, 0 -+ lfs 80100094e0000359, 65456 => c400006b20000000, 0 -+ lfs bfe0000000000001, 65464 => 36a0000000000000, 0 -+ lfs bfe00094e0000359, 65472 => c400006b20000000, 0 -+ lfs 0000000000000000, 65480 => 0000000000000000, 0 -+ lfs 8000000000000000, 65488 => 0000000000000000, 0 -+ lfs 7ff0000000000000, 65496 => 0000000000000000, 0 -+ lfs fff0000000000000, 65504 => 0000000000000000, 0 -+ lfs 7ff7ffffffffffff, 65512 => ffffffffe0000000, 0 -+ lfs fff7ffffffffffff, 65520 => ffffffffe0000000, 0 -+ lfs 7ff8000000000000, 65528 => 0000000000000000, 0 -+ lfs 0010000000000001, 0 => 36a0000000000000, 0 -+ lfs 00100094e0000359, 8 => c400006b20000000, 0 -+ lfs 3fe0000000000001, 16 => 36a0000000000000, 0 -+ lfs 3fe00094e0000359, 24 => c400006b20000000, 0 -+ lfs 8010000000000001, 32 => 36a0000000000000, 0 -+ lfs 80100094e0000359, 40 => c400006b20000000, 0 -+ lfs bfe0000000000001, 48 => 36a0000000000000, 0 -+ lfs bfe00094e0000359, 56 => c400006b20000000, 0 -+ lfs 0000000000000000, 64 => 0000000000000000, 0 -+ lfs 8000000000000000, 72 => 0000000000000000, 0 -+ lfs 7ff0000000000000, 80 => 0000000000000000, 0 -+ lfs fff0000000000000, 88 => 0000000000000000, 0 -+ lfs 7ff7ffffffffffff, 96 => ffffffffe0000000, 0 -+ lfs fff7ffffffffffff, 104 => ffffffffe0000000, 0 -+ lfs 7ff8000000000000, 112 => 0000000000000000, 0 -+ lfs fff8000000000000, 120 => 0000000000000000, 0 -+ -+ lfsu 0010000000000001, 65416 => 36a0000000000000, -120 -+ lfsu 00100094e0000359, 65424 => c400006b20000000, -112 -+ lfsu 3fe0000000000001, 65432 => 36a0000000000000, -104 -+ lfsu 3fe00094e0000359, 65440 => c400006b20000000, -96 -+ lfsu 8010000000000001, 65448 => 36a0000000000000, -88 -+ lfsu 80100094e0000359, 65456 => c400006b20000000, -80 -+ lfsu bfe0000000000001, 65464 => 36a0000000000000, -72 -+ lfsu bfe00094e0000359, 65472 => c400006b20000000, -64 -+ lfsu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfsu 8000000000000000, 65488 => 0000000000000000, -48 -+ lfsu 7ff0000000000000, 65496 => 0000000000000000, -40 -+ lfsu fff0000000000000, 65504 => 0000000000000000, -32 -+ lfsu 7ff7ffffffffffff, 65512 => ffffffffe0000000, -24 -+ lfsu fff7ffffffffffff, 65520 => ffffffffe0000000, -16 -+ lfsu 7ff8000000000000, 65528 => 0000000000000000, -8 -+ lfsu 0010000000000001, 0 => 36a0000000000000, 0 -+ lfsu 00100094e0000359, 8 => c400006b20000000, 8 -+ lfsu 3fe0000000000001, 16 => 36a0000000000000, 16 -+ lfsu 3fe00094e0000359, 24 => c400006b20000000, 24 -+ lfsu 8010000000000001, 32 => 36a0000000000000, 32 -+ lfsu 80100094e0000359, 40 => c400006b20000000, 40 -+ lfsu bfe0000000000001, 48 => 36a0000000000000, 48 -+ lfsu bfe00094e0000359, 56 => c400006b20000000, 56 -+ lfsu 0000000000000000, 64 => 0000000000000000, 64 -+ lfsu 8000000000000000, 72 => 0000000000000000, 72 -+ lfsu 7ff0000000000000, 80 => 0000000000000000, 80 -+ lfsu fff0000000000000, 88 => 0000000000000000, 88 -+ lfsu 7ff7ffffffffffff, 96 => ffffffffe0000000, 96 -+ lfsu fff7ffffffffffff, 104 => ffffffffe0000000, 104 -+ lfsu 7ff8000000000000, 112 => 0000000000000000, 112 -+ lfsu fff8000000000000, 120 => 0000000000000000, 120 -+ -+ lfd 0010000000000001, 65416 => 0010000000000001, 0 -+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 65448 => 8010000000000001, 0 -+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 65480 => 0000000000000000, 0 -+ lfd 8000000000000000, 65488 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 65504 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0 -+ lfd 0010000000000001, 0 => 0010000000000001, 0 -+ lfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 32 => 8010000000000001, 0 -+ lfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 64 => 0000000000000000, 0 -+ lfd 8000000000000000, 72 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 88 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdu 0010000000000001, 65416 => 0010000000000001, -120 -+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112 -+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104 -+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96 -+ lfdu 8010000000000001, 65448 => 8010000000000001, -88 -+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80 -+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72 -+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64 -+ lfdu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfdu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40 -+ lfdu fff0000000000000, 65504 => fff0000000000000, -32 -+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24 -+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16 -+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8 -+ lfdu 0010000000000001, 0 => 0010000000000001, 0 -+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdu 8010000000000001, 32 => 8010000000000001, 32 -+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdu 0000000000000000, 64 => 0000000000000000, 64 -+ lfdu 8000000000000000, 72 => 8000000000000000, 72 -+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdu fff0000000000000, 88 => fff0000000000000, 88 -+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float load insns with two register args: -+ lfsx 0010000000000001, -120 => 36a0000000000000, 0 -+ lfsx 00100094e0000359, -112 => c400006b20000000, 0 -+ lfsx 3fe0000000000001, -104 => 36a0000000000000, 0 -+ lfsx 3fe00094e0000359, -96 => c400006b20000000, 0 -+ lfsx 8010000000000001, -88 => 36a0000000000000, 0 -+ lfsx 80100094e0000359, -80 => c400006b20000000, 0 -+ lfsx bfe0000000000001, -72 => 36a0000000000000, 0 -+ lfsx bfe00094e0000359, -64 => c400006b20000000, 0 -+ lfsx 0000000000000000, -56 => 0000000000000000, 0 -+ lfsx 8000000000000000, -48 => 0000000000000000, 0 -+ lfsx 7ff0000000000000, -40 => 0000000000000000, 0 -+ lfsx fff0000000000000, -32 => 0000000000000000, 0 -+ lfsx 7ff7ffffffffffff, -24 => ffffffffe0000000, 0 -+ lfsx fff7ffffffffffff, -16 => ffffffffe0000000, 0 -+ lfsx 7ff8000000000000, -8 => 0000000000000000, 0 -+ lfsx 0010000000000001, 0 => 36a0000000000000, 0 -+ lfsx 00100094e0000359, 8 => c400006b20000000, 0 -+ lfsx 3fe0000000000001, 16 => 36a0000000000000, 0 -+ lfsx 3fe00094e0000359, 24 => c400006b20000000, 0 -+ lfsx 8010000000000001, 32 => 36a0000000000000, 0 -+ lfsx 80100094e0000359, 40 => c400006b20000000, 0 -+ lfsx bfe0000000000001, 48 => 36a0000000000000, 0 -+ lfsx bfe00094e0000359, 56 => c400006b20000000, 0 -+ lfsx 0000000000000000, 64 => 0000000000000000, 0 -+ lfsx 8000000000000000, 72 => 0000000000000000, 0 -+ lfsx 7ff0000000000000, 80 => 0000000000000000, 0 -+ lfsx fff0000000000000, 88 => 0000000000000000, 0 -+ lfsx 7ff7ffffffffffff, 96 => ffffffffe0000000, 0 -+ lfsx fff7ffffffffffff, 104 => ffffffffe0000000, 0 -+ lfsx 7ff8000000000000, 112 => 0000000000000000, 0 -+ lfsx fff8000000000000, 120 => 0000000000000000, 0 -+ -+ lfsux 0010000000000001, -120 => 36a0000000000000, -120 -+ lfsux 00100094e0000359, -112 => c400006b20000000, -112 -+ lfsux 3fe0000000000001, -104 => 36a0000000000000, -104 -+ lfsux 3fe00094e0000359, -96 => c400006b20000000, -96 -+ lfsux 8010000000000001, -88 => 36a0000000000000, -88 -+ lfsux 80100094e0000359, -80 => c400006b20000000, -80 -+ lfsux bfe0000000000001, -72 => 36a0000000000000, -72 -+ lfsux bfe00094e0000359, -64 => c400006b20000000, -64 -+ lfsux 0000000000000000, -56 => 0000000000000000, -56 -+ lfsux 8000000000000000, -48 => 0000000000000000, -48 -+ lfsux 7ff0000000000000, -40 => 0000000000000000, -40 -+ lfsux fff0000000000000, -32 => 0000000000000000, -32 -+ lfsux 7ff7ffffffffffff, -24 => ffffffffe0000000, -24 -+ lfsux fff7ffffffffffff, -16 => ffffffffe0000000, -16 -+ lfsux 7ff8000000000000, -8 => 0000000000000000, -8 -+ lfsux 0010000000000001, 0 => 36a0000000000000, 0 -+ lfsux 00100094e0000359, 8 => c400006b20000000, 8 -+ lfsux 3fe0000000000001, 16 => 36a0000000000000, 16 -+ lfsux 3fe00094e0000359, 24 => c400006b20000000, 24 -+ lfsux 8010000000000001, 32 => 36a0000000000000, 32 -+ lfsux 80100094e0000359, 40 => c400006b20000000, 40 -+ lfsux bfe0000000000001, 48 => 36a0000000000000, 48 -+ lfsux bfe00094e0000359, 56 => c400006b20000000, 56 -+ lfsux 0000000000000000, 64 => 0000000000000000, 64 -+ lfsux 8000000000000000, 72 => 0000000000000000, 72 -+ lfsux 7ff0000000000000, 80 => 0000000000000000, 80 -+ lfsux fff0000000000000, 88 => 0000000000000000, 88 -+ lfsux 7ff7ffffffffffff, 96 => ffffffffe0000000, 96 -+ lfsux fff7ffffffffffff, 104 => ffffffffe0000000, 104 -+ lfsux 7ff8000000000000, 112 => 0000000000000000, 112 -+ lfsux fff8000000000000, 120 => 0000000000000000, 120 -+ -+ lfdx 0010000000000001, -120 => 0010000000000001, 0 -+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, -88 => 8010000000000001, 0 -+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, -56 => 0000000000000000, 0 -+ lfdx 8000000000000000, -48 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, -32 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ lfdx 0010000000000001, 0 => 0010000000000001, 0 -+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, 32 => 8010000000000001, 0 -+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, 64 => 0000000000000000, 0 -+ lfdx 8000000000000000, 72 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, 88 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdux 0010000000000001, -120 => 0010000000000001, -120 -+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112 -+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ lfdux 8010000000000001, -88 => 8010000000000001, -88 -+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80 -+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72 -+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ lfdux 0000000000000000, -56 => 0000000000000000, -56 -+ lfdux 8000000000000000, -48 => 8000000000000000, -48 -+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ lfdux fff0000000000000, -32 => fff0000000000000, -32 -+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ lfdux 0010000000000001, 0 => 0010000000000001, 0 -+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdux 8010000000000001, 32 => 8010000000000001, 32 -+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdux 0000000000000000, 64 => 0000000000000000, 64 -+ lfdux 8000000000000000, 72 => 8000000000000000, 72 -+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdux fff0000000000000, 88 => fff0000000000000, 88 -+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns -+ with one register + one 16 bits immediate args with flags update: -+ stfs 0010000000000001, -56 => 0000000000000000, 0 -+ stfs 00100094e0000359, -48 => 0000000000000000, 0 -+ stfs 3fe0000000000001, -40 => 000000003f000000, 0 -+ stfs 3fe00094e0000359, -32 => 000000003f0004a7, 0 -+ stfs 8010000000000001, -24 => 0000000080000000, 0 -+ stfs 80100094e0000359, -16 => 0000000080000000, 0 -+ stfs bfe0000000000001, -8 => 00000000bf000000, 0 -+ stfs 0010000000000001, 0 => 0000000000000000, 0 -+ stfs 00100094e0000359, 8 => 0000000000000000, 0 -+ stfs 3fe0000000000001, 16 => 000000003f000000, 0 -+ stfs 3fe00094e0000359, 24 => 000000003f0004a7, 0 -+ stfs 8010000000000001, 32 => 0000000080000000, 0 -+ stfs 80100094e0000359, 40 => 0000000080000000, 0 -+ stfs bfe0000000000001, 48 => 00000000bf000000, 0 -+ stfs bfe00094e0000359, 56 => 00000000bf0004a7, 0 -+ -+ stfsu 0010000000000001, -56 => 0000000000000000, -56 -+ stfsu 00100094e0000359, -48 => 0000000000000000, -48 -+ stfsu 3fe0000000000001, -40 => 000000003f000000, -40 -+ stfsu 3fe00094e0000359, -32 => 000000003f0004a7, -32 -+ stfsu 8010000000000001, -24 => 0000000080000000, -24 -+ stfsu 80100094e0000359, -16 => 0000000080000000, -16 -+ stfsu bfe0000000000001, -8 => 00000000bf000000, -8 -+ stfsu 0010000000000001, 0 => 0000000000000000, 0 -+ stfsu 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsu 3fe0000000000001, 16 => 000000003f000000, 16 -+ stfsu 3fe00094e0000359, 24 => 000000003f0004a7, 24 -+ stfsu 8010000000000001, 32 => 0000000080000000, 32 -+ stfsu 80100094e0000359, 40 => 0000000080000000, 40 -+ stfsu bfe0000000000001, 48 => 00000000bf000000, 48 -+ stfsu bfe00094e0000359, 56 => 00000000bf0004a7, 56 -+ -+ stfd 0010000000000001, -120 => 0010000000000001, 0 -+ stfd 00100094e0000359, -112 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, -88 => 8010000000000001, 0 -+ stfd 80100094e0000359, -80 => 80100094e0000359, 0 -+ stfd bfe0000000000001, -72 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ stfd 0000000000000000, -56 => 0000000000000000, 0 -+ stfd 8000000000000000, -48 => 8000000000000000, 0 -+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ stfd fff0000000000000, -32 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ stfd 0010000000000001, 0 => 0010000000000001, 0 -+ stfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, 32 => 8010000000000001, 0 -+ stfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfd 0000000000000000, 64 => 0000000000000000, 0 -+ stfd 8000000000000000, 72 => 8000000000000000, 0 -+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfd fff0000000000000, 88 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdu 0010000000000001, -120 => 0010000000000001, -120 -+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112 -+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ stfdu 8010000000000001, -88 => 8010000000000001, -88 -+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80 -+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72 -+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ stfdu 0000000000000000, -56 => 0000000000000000, -56 -+ stfdu 8000000000000000, -48 => 8000000000000000, -48 -+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ stfdu fff0000000000000, -32 => fff0000000000000, -32 -+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ stfdu 0010000000000001, 0 => 0010000000000001, 0 -+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdu 8010000000000001, 32 => 8010000000000001, 32 -+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdu 0000000000000000, 64 => 0000000000000000, 64 -+ stfdu 8000000000000000, 72 => 8000000000000000, 72 -+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdu fff0000000000000, 88 => fff0000000000000, 88 -+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns with three register args: -+ stfsx 0010000000000001, 0 => 0000000000000000, 0 -+ stfsx 00100094e0000359, 8 => 0000000000000000, 0 -+ stfsx 3fe0000000000001, 16 => 000000003f000000, 0 -+ stfsx 3fe00094e0000359, 24 => 000000003f0004a7, 0 -+ stfsx 8010000000000001, 32 => 0000000080000000, 0 -+ stfsx 80100094e0000359, 40 => 0000000080000000, 0 -+ stfsx bfe0000000000001, 48 => 00000000bf000000, 0 -+ stfsx bfe00094e0000359, 56 => 00000000bf0004a7, 0 -+ -+ stfsux 0010000000000001, 0 => 0000000000000000, 0 -+ stfsux 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsux 3fe0000000000001, 16 => 000000003f000000, 16 -+ stfsux 3fe00094e0000359, 24 => 000000003f0004a7, 24 -+ stfsux 8010000000000001, 32 => 0000000080000000, 32 -+ stfsux 80100094e0000359, 40 => 0000000080000000, 40 -+ stfsux bfe0000000000001, 48 => 00000000bf000000, 48 -+ stfsux bfe00094e0000359, 56 => 00000000bf0004a7, 56 -+ -+ stfdx 0010000000000001, 0 => 0010000000000001, 0 -+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfdx 8010000000000001, 32 => 8010000000000001, 0 -+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfdx 0000000000000000, 64 => 0000000000000000, 0 -+ stfdx 8000000000000000, 72 => 8000000000000000, 0 -+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfdx fff0000000000000, 88 => fff0000000000000, 0 -+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdux 0010000000000001, 0 => 0010000000000001, 0 -+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdux 8010000000000001, 32 => 8010000000000001, 32 -+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdux 0000000000000000, 64 => 0000000000000000, 64 -+ stfdux 8000000000000000, 72 => 8000000000000000, 72 -+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdux fff0000000000000, 88 => fff0000000000000, 88 -+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+All done. Tested 77 different instructions -Index: none/tests/ppc64/std_reg_imm.stdout.exp-LE -=================================================================== ---- /dev/null -+++ none/tests/ppc64/std_reg_imm.stdout.exp-LE -@@ -0,0 +1 @@ -+....8877665544332211............ -Index: none/tests/ppc64/jm-int.stdout.exp-LE -=================================================================== ---- /dev/null -+++ none/tests/ppc64/jm-int.stdout.exp-LE -@@ -0,0 +1,4773 @@ -+PPC integer arith insns with two args: -+ add 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ add 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ add 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ add 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ add 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000) -+ add 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000) -+ add ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ add ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000) -+ add ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000) -+ -+ addo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ addo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ addo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ addo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ addo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000) -+ addo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000) -+ addo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ addo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000) -+ addo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000) -+ -+ addc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ addc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ addc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ addc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ addc 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000) -+ addc 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000) -+ addc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ addc ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ addc ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ -+ addco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ addco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ addco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ addco 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ addco 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000) -+ addco 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000) -+ addco ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ addco ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ addco ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ -+ divw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divw 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000) -+ divw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ divwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divwo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000) -+ divwo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ divwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divwu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divwu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divwu ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divwu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ divwuo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divwuo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divwuo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divwuo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divwuo ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divwuo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ mulhw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mulhw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mulhw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhw 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (00000000 00000000) -+ mulhw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mulhw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mulhw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ mulhwu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mulhwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mulhwu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhwu 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (00000000 00000000) -+ mulhwu 0000001cbe991def, ffffffffffffffff => 00000000be991dee (00000000 00000000) -+ mulhwu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhwu ffffffffffffffff, 0000001cbe991def => 00000000be991dee (00000000 00000000) -+ mulhwu ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (00000000 00000000) -+ -+ mullw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mullw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mullw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mullw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mullw 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 00000000) -+ mullw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000) -+ mullw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mullw ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000) -+ mullw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ mullwo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mullwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mullwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mullwo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mullwo 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 c0000000) -+ mullwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000) -+ mullwo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mullwo ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000) -+ mullwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ subf 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ subf 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ subf 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ subf 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000) -+ subf 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ subf 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000) -+ subf ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ subf ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ subf ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ subfo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ subfo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ subfo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ subfo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000) -+ subfo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ subfo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000) -+ subfo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ subfo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ subfo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ subfc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000) -+ subfc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ subfc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ subfc 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000) -+ subfc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000) -+ subfc 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000) -+ subfc ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ subfc ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ subfc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+ subfco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000) -+ subfco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ subfco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ subfco 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000) -+ subfco 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000) -+ subfco 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000) -+ subfco ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ subfco ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ subfco ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+ mulhd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mulhd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mulhd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhd 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000) -+ mulhd 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ mulhd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhd ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ mulhd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ mulhdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mulhdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mulhdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhdu 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000) -+ mulhdu 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000) -+ mulhdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulhdu ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000) -+ mulhdu ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000) -+ -+ mulld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mulld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mulld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulld 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 00000000) -+ mulld 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000) -+ mulld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulld ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000) -+ mulld ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ mulldo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulldo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ mulldo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ mulldo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulldo 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 c0000000) -+ mulldo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000) -+ mulldo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ mulldo ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000) -+ mulldo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ divd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ divd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ divd 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divd 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000) -+ divd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ divd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divd ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ divdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ divdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ divdu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divdu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ divdu ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000) -+ divdu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ divdo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0000000) -+ divdo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divdo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divdo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0000000) -+ divdo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divdo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000) -+ divdo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0000000) -+ divdo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divdo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ divduo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0000000) -+ divduo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ divduo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divduo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0000000) -+ divduo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000) -+ divduo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ divduo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0000000) -+ divduo ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000) -+ divduo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+PPC integer arith insns with two args with flags update: -+ add. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ add. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ add. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ add. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ add. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000) -+ add. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000) -+ add. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ add. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000) -+ add. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000) -+ -+ addo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ addo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ addo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ addo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ addo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000) -+ addo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000) -+ addo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ addo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000) -+ addo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000) -+ -+ addc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ addc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ addc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ addc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ addc. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000) -+ addc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000) -+ addc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ addc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ addc. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ -+ addco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ addco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ addco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ addco. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ addco. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000) -+ addco. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000) -+ addco. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ addco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ addco. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ -+ divw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divw. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000) -+ divw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ divwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divwo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000) -+ divwo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ divwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divwu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divwu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divwu. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divwu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ divwuo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divwuo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divwuo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divwuo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divwuo. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divwuo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ mulhw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mulhw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mulhw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhw. 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (40000000 00000000) -+ mulhw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mulhw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mulhw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ mulhwu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mulhwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mulhwu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhwu. 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (80000000 00000000) -+ mulhwu. 0000001cbe991def, ffffffffffffffff => 00000000be991dee (80000000 00000000) -+ mulhwu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhwu. ffffffffffffffff, 0000001cbe991def => 00000000be991dee (80000000 00000000) -+ mulhwu. ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (80000000 00000000) -+ -+ mullw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mullw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mullw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mullw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mullw. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (40000000 00000000) -+ mullw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000) -+ mullw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mullw. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000) -+ mullw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ mullwo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mullwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mullwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mullwo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mullwo. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (50000000 c0000000) -+ mullwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000) -+ mullwo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mullwo. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000) -+ mullwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ subf. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ subf. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ subf. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ subf. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000) -+ subf. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ subf. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000) -+ subf. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ subf. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ subf. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ subfo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ subfo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ subfo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ subfo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000) -+ subfo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ subfo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000) -+ subfo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ subfo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ subfo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ subfc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000) -+ subfc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ subfc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ subfc. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000) -+ subfc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000) -+ subfc. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000) -+ subfc. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ subfc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ subfc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+ subfco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000) -+ subfco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ subfco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ subfco. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000) -+ subfco. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000) -+ subfco. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000) -+ subfco. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ subfco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ subfco. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+ mulhd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mulhd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mulhd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhd. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000) -+ mulhd. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ mulhd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhd. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ mulhd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ mulhdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mulhdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mulhdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhdu. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000) -+ mulhdu. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000) -+ mulhdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulhdu. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000) -+ mulhdu. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000) -+ -+ mulld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mulld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mulld. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulld. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (40000000 00000000) -+ mulld. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000) -+ mulld. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulld. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000) -+ mulld. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ mulldo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulldo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ mulldo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ mulldo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulldo. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (50000000 c0000000) -+ mulldo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000) -+ mulldo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ mulldo. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000) -+ mulldo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ divd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ divd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ divd. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divd. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000) -+ divd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ divd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divd. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ divdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ divdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ divdu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divdu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ divdu. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000) -+ divdu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ divdo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0000000) -+ divdo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divdo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divdo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0000000) -+ divdo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divdo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000) -+ divdo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0000000) -+ divdo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divdo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ divduo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0000000) -+ divduo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ divduo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divduo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0000000) -+ divduo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000) -+ divduo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ divduo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0000000) -+ divduo. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000) -+ divduo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+PPC integer arith insns with two args and carry: -+ adde 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ adde 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ adde 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000) -+ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000) -+ adde ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ adde ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ adde 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ adde 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ adde 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000) -+ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00000000) -+ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000) -+ adde ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000) -+ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ adde ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ -+ addeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ addeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000) -+ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000) -+ addeo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ addeo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ addeo 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ addeo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000) -+ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00000000) -+ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000) -+ addeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000) -+ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ addeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ -+ subfe 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ subfe 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000) -+ subfe 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000) -+ subfe ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ subfe ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ subfe 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000) -+ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ subfe 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000) -+ subfe 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000) -+ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000) -+ subfe ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ subfe ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+ subfeo 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ subfeo 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000) -+ subfeo 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000) -+ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ subfeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ subfeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000) -+ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ subfeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000) -+ subfeo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000) -+ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000) -+ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000) -+ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ subfeo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+PPC integer arith insns with two args and carry with flags update: -+ adde. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ adde. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000) -+ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000) -+ adde. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ adde. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ adde. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ adde. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000) -+ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00000000) -+ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000) -+ adde. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000) -+ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ adde. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ -+ addeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ addeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000) -+ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000) -+ addeo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ addeo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ addeo. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ addeo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000) -+ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00000000) -+ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000) -+ addeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000) -+ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ addeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ -+ subfe. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ subfe. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000) -+ subfe. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000) -+ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ subfe. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ subfe. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000) -+ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ subfe. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000) -+ subfe. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000) -+ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000) -+ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ subfe. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+ subfeo. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ subfeo. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000) -+ subfeo. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000) -+ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ subfeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ subfeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000) -+ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ subfeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000) -+ subfeo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000) -+ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000) -+ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000) -+ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ subfeo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+PPC integer logical insns with two args: -+ and 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ and 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ and 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ and 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ and 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ and 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000) -+ and ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ and ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ and ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ -+ andc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ andc 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ andc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ andc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ andc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ andc 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ andc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ andc ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ andc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ eqv 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ eqv 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ eqv 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ eqv 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000) -+ eqv 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ eqv 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000) -+ eqv ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ eqv ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ eqv ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ -+ nand 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ nand 0000000000000000, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ nand 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ nand 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ nand 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ nand 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000) -+ nand ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ nand ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ nand ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ nor 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ nor 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ nor 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ nor 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000) -+ nor 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ nor 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ nor ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ nor ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ nor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ or 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ or 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ or 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ or 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ or 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ or 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ or ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ or ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ or ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ -+ orc 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ orc 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ orc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ orc 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ orc 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ orc 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000) -+ orc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ orc ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000) -+ orc ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ -+ xor 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ xor 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ xor 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ xor 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ xor 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ xor 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000) -+ xor ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ xor ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ xor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ slw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ slw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ slw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ slw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000) -+ slw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ slw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ slw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000) -+ slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000) -+ sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000) -+ sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) -+ sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ -+ srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ srw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000) -+ srw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ srw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000) -+ srw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ sld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ sld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ sld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ sld 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ sld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ sld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ sld ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000) -+ srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ -+ srd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000) -+ srd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ srd 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000) -+ srd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ srd ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ srd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ srd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+PPC integer logical insns with two args with flags update: -+ and. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ and. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ and. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ and. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ and. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ and. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000) -+ and. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ and. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ and. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ -+ andc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ andc. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ andc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ andc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ andc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ andc. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ andc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ andc. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ andc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ eqv. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ eqv. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ eqv. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ eqv. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000) -+ eqv. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ eqv. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000) -+ eqv. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ eqv. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ eqv. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ -+ nand. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ nand. 0000000000000000, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ nand. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ nand. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ nand. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ nand. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000) -+ nand. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ nand. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ nand. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ nor. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ nor. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ nor. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ nor. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000) -+ nor. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ nor. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ nor. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ nor. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ nor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ or. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ or. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ or. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ or. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ or. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ or. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ or. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ or. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ or. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ -+ orc. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ orc. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ orc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ orc. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ orc. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ orc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000) -+ orc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ orc. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000) -+ orc. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ -+ xor. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ xor. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ xor. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ xor. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ xor. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ xor. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000) -+ xor. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ xor. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ xor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ slw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ slw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ slw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ slw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000) -+ slw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ slw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ slw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000) -+ slw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ slw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000) -+ sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000) -+ sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) -+ sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ -+ srw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ srw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ srw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000) -+ srw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ srw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000) -+ srw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ sld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ sld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ sld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ sld. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ sld. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ sld. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ sld. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ sld. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ sld. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000) -+ srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ -+ srd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000) -+ srd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ srd. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000) -+ srd. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srd. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ srd. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ srd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ srd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+PPC integer compare insns (two args): -+ cmpw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000) -+ cmpw 0000000000000000, 0000001cbe991def => 0000000000000000 (00400000 00000000) -+ cmpw 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000) -+ cmpw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00800000 00000000) -+ cmpw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000) -+ cmpw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000) -+ cmpw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000) -+ cmpw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000) -+ cmpw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000) -+ -+ cmplw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000) -+ cmplw 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000) -+ cmplw 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000) -+ cmplw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000) -+ cmplw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000) -+ cmplw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000) -+ cmplw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000) -+ cmplw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000) -+ cmplw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000) -+ -+ cmpd 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000) -+ cmpd 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000) -+ cmpd 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000) -+ cmpd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000) -+ cmpd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000) -+ cmpd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00400000 00000000) -+ cmpd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000) -+ cmpd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00800000 00000000) -+ cmpd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000) -+ -+ cmpld 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000) -+ cmpld 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000) -+ cmpld 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000) -+ cmpld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000) -+ cmpld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000) -+ cmpld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000) -+ cmpld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000) -+ cmpld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000) -+ cmpld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000) -+ -+PPC integer compare with immediate insns (two args): -+ cmpwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000) -+ cmpwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000) -+ cmpwi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000) -+ cmpwi 0000001cbe991def, 00000000 => 0000000000000000 (00800000 00000000) -+ cmpwi 0000001cbe991def, 000003e7 => 0000000000000000 (00800000 00000000) -+ cmpwi 0000001cbe991def, 0000ffff => 0000000000000000 (00800000 00000000) -+ cmpwi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000) -+ cmpwi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000) -+ cmpwi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000) -+ -+ cmplwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000) -+ cmplwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000) -+ cmplwi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000) -+ cmplwi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000) -+ cmplwi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000) -+ cmplwi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000) -+ cmplwi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000) -+ cmplwi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000) -+ cmplwi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000) -+ -+ cmpdi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000) -+ cmpdi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000) -+ cmpdi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000) -+ cmpdi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000) -+ cmpdi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000) -+ cmpdi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000) -+ cmpdi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000) -+ cmpdi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000) -+ cmpdi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000) -+ -+ cmpldi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000) -+ cmpldi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000) -+ cmpldi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000) -+ cmpldi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000) -+ cmpldi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000) -+ cmpldi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000) -+ cmpldi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000) -+ cmpldi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000) -+ cmpldi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000) -+ -+PPC integer arith insns -+ with one register + one 16 bits immediate args: -+ addi 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ addi 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000) -+ addi 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000) -+ addi 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000) -+ addi 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000) -+ addi 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 00000000) -+ addi ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000) -+ addi ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 00000000) -+ addi ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 00000000) -+ -+ addic 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ addic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000) -+ addic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000) -+ addic 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000) -+ addic 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000) -+ addic 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 20000000) -+ addic ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000) -+ addic ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 20000000) -+ addic ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 20000000) -+ -+ addis 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ addis 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000) -+ addis 0000000000000000, 0000ffff => ffffffffffff0000 (00000000 00000000) -+ addis 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000) -+ addis 0000001cbe991def, 000003e7 => 0000001cc2801def (00000000 00000000) -+ addis 0000001cbe991def, 0000ffff => 0000001cbe981def (00000000 00000000) -+ addis ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000) -+ addis ffffffffffffffff, 000003e7 => 0000000003e6ffff (00000000 00000000) -+ addis ffffffffffffffff, 0000ffff => fffffffffffeffff (00000000 00000000) -+ -+ mulli 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ mulli 0000000000000000, 000003e7 => 0000000000000000 (00000000 00000000) -+ mulli 0000000000000000, 0000ffff => 0000000000000000 (00000000 00000000) -+ mulli 0000001cbe991def, 00000000 => 0000000000000000 (00000000 00000000) -+ mulli 0000001cbe991def, 000003e7 => 0000702bc783cfa9 (00000000 00000000) -+ mulli 0000001cbe991def, 0000ffff => ffffffe34166e211 (00000000 00000000) -+ mulli ffffffffffffffff, 00000000 => 0000000000000000 (00000000 00000000) -+ mulli ffffffffffffffff, 000003e7 => fffffffffffffc19 (00000000 00000000) -+ mulli ffffffffffffffff, 0000ffff => 0000000000000001 (00000000 00000000) -+ -+ subfic 0000000000000000, 00000000 => 0000000000000000 (00000000 20000000) -+ subfic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 20000000) -+ subfic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 20000000) -+ subfic 0000001cbe991def, 00000000 => ffffffe34166e211 (00000000 00000000) -+ subfic 0000001cbe991def, 000003e7 => ffffffe34166e5f8 (00000000 00000000) -+ subfic 0000001cbe991def, 0000ffff => ffffffe34166e210 (00000000 20000000) -+ subfic ffffffffffffffff, 00000000 => 0000000000000001 (00000000 00000000) -+ subfic ffffffffffffffff, 000003e7 => 00000000000003e8 (00000000 00000000) -+ subfic ffffffffffffffff, 0000ffff => 0000000000000000 (00000000 20000000) -+ -+PPC integer arith insns -+ with one register + one 16 bits immediate args with flags update: -+ addic. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000) -+ addic. 0000000000000000, 000003e7 => 00000000000003e7 (40000000 00000000) -+ addic. 0000000000000000, 0000ffff => ffffffffffffffff (80000000 00000000) -+ addic. 0000001cbe991def, 00000000 => 0000001cbe991def (40000000 00000000) -+ addic. 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (40000000 00000000) -+ addic. 0000001cbe991def, 0000ffff => 0000001cbe991dee (40000000 20000000) -+ addic. ffffffffffffffff, 00000000 => ffffffffffffffff (80000000 00000000) -+ addic. ffffffffffffffff, 000003e7 => 00000000000003e6 (40000000 20000000) -+ addic. ffffffffffffffff, 0000ffff => fffffffffffffffe (80000000 20000000) -+ -+PPC integer logical insns -+ with one register + one 16 bits immediate args: -+ ori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ ori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000) -+ ori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000) -+ ori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000) -+ ori 0000001cbe991def, 000003e7 => 0000001cbe991fef (00000000 00000000) -+ ori 0000001cbe991def, 0000ffff => 0000001cbe99ffff (00000000 00000000) -+ ori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000) -+ ori ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000) -+ ori ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000) -+ -+ oris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ oris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000) -+ oris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000) -+ oris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000) -+ oris 0000001cbe991def, 000003e7 => 0000001cbfff1def (00000000 00000000) -+ oris 0000001cbe991def, 0000ffff => 0000001cffff1def (00000000 00000000) -+ oris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000) -+ oris ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000) -+ oris ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000) -+ -+ xori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ xori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000) -+ xori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000) -+ xori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000) -+ xori 0000001cbe991def, 000003e7 => 0000001cbe991e08 (00000000 00000000) -+ xori 0000001cbe991def, 0000ffff => 0000001cbe99e210 (00000000 00000000) -+ xori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000) -+ xori ffffffffffffffff, 000003e7 => fffffffffffffc18 (00000000 00000000) -+ xori ffffffffffffffff, 0000ffff => ffffffffffff0000 (00000000 00000000) -+ -+ xoris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000) -+ xoris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000) -+ xoris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000) -+ xoris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000) -+ xoris 0000001cbe991def, 000003e7 => 0000001cbd7e1def (00000000 00000000) -+ xoris 0000001cbe991def, 0000ffff => 0000001c41661def (00000000 00000000) -+ xoris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000) -+ xoris ffffffffffffffff, 000003e7 => fffffffffc18ffff (00000000 00000000) -+ xoris ffffffffffffffff, 0000ffff => ffffffff0000ffff (00000000 00000000) -+ -+PPC integer logical insns -+ with one register + one 16 bits immediate args with flags update: -+ andi. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000) -+ andi. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000) -+ andi. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000) -+ andi. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000) -+ andi. 0000001cbe991def, 000003e7 => 00000000000001e7 (40000000 00000000) -+ andi. 0000001cbe991def, 0000ffff => 0000000000001def (40000000 00000000) -+ andi. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000) -+ andi. ffffffffffffffff, 000003e7 => 00000000000003e7 (40000000 00000000) -+ andi. ffffffffffffffff, 0000ffff => 000000000000ffff (40000000 00000000) -+ -+ andis. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000) -+ andis. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000) -+ andis. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000) -+ andis. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000) -+ andis. 0000001cbe991def, 000003e7 => 0000000002810000 (40000000 00000000) -+ andis. 0000001cbe991def, 0000ffff => 00000000be990000 (40000000 00000000) -+ andis. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000) -+ andis. ffffffffffffffff, 000003e7 => 0000000003e70000 (40000000 00000000) -+ andis. ffffffffffffffff, 0000ffff => 00000000ffff0000 (40000000 00000000) -+ -+PPC condition register logical insns - two operands: -+ crand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ crand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ crand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ -+ crandc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crandc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crandc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ crandc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crandc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crandc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ crandc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crandc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crandc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ -+ creqv 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ creqv 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ creqv 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ creqv 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ creqv 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ creqv 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ creqv ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ creqv ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ creqv ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ -+ crnand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crnand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crnand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ crnand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crnand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crnand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ crnand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crnand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crnand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ -+ crnor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crnor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crnor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ crnor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crnor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crnor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ crnor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crnor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crnor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ -+ cror 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ cror 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ cror 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ cror 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ cror 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ cror 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ cror ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ cror ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ cror ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ -+ crorc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crorc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crorc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ crorc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crorc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crorc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ crorc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000) -+ crorc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000) -+ crorc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000) -+ -+ crxor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crxor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crxor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ crxor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crxor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crxor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ crxor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000) -+ crxor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000) -+ crxor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000) -+ -+PPC integer arith insns with one arg and carry: -+ addme 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ addme 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ addme ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ addme 0000000000000000 => 0000000000000000 (00000000 20000000) -+ addme 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ addme ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ -+ addmeo 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ addmeo 0000001cbe991def => 0000001cbe991dee (00000000 20000000) -+ addmeo ffffffffffffffff => fffffffffffffffe (00000000 20000000) -+ addmeo 0000000000000000 => 0000000000000000 (00000000 20000000) -+ addmeo 0000001cbe991def => 0000001cbe991def (00000000 20000000) -+ addmeo ffffffffffffffff => ffffffffffffffff (00000000 20000000) -+ -+ addze 0000000000000000 => 0000000000000000 (00000000 00000000) -+ addze 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ addze ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ addze 0000000000000000 => 0000000000000001 (00000000 00000000) -+ addze 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ addze ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+ addzeo 0000000000000000 => 0000000000000000 (00000000 00000000) -+ addzeo 0000001cbe991def => 0000001cbe991def (00000000 00000000) -+ addzeo ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ addzeo 0000000000000000 => 0000000000000001 (00000000 00000000) -+ addzeo 0000001cbe991def => 0000001cbe991df0 (00000000 00000000) -+ addzeo ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+ subfme 0000000000000000 => fffffffffffffffe (00000000 20000000) -+ subfme 0000001cbe991def => ffffffe34166e20f (00000000 20000000) -+ subfme ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ subfme 0000000000000000 => ffffffffffffffff (00000000 20000000) -+ subfme 0000001cbe991def => ffffffe34166e210 (00000000 20000000) -+ subfme ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+ subfmeo 0000000000000000 => fffffffffffffffe (00000000 20000000) -+ subfmeo 0000001cbe991def => ffffffe34166e20f (00000000 20000000) -+ subfmeo ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ subfmeo 0000000000000000 => ffffffffffffffff (00000000 20000000) -+ subfmeo 0000001cbe991def => ffffffe34166e210 (00000000 20000000) -+ subfmeo ffffffffffffffff => 0000000000000000 (00000000 20000000) -+ -+ subfze 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ subfze 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ subfze ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ subfze 0000000000000000 => 0000000000000000 (00000000 20000000) -+ subfze 0000001cbe991def => ffffffe34166e211 (00000000 00000000) -+ subfze ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ subfzeo 0000000000000000 => ffffffffffffffff (00000000 00000000) -+ subfzeo 0000001cbe991def => ffffffe34166e210 (00000000 00000000) -+ subfzeo ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ subfzeo 0000000000000000 => 0000000000000000 (00000000 20000000) -+ subfzeo 0000001cbe991def => ffffffe34166e211 (00000000 00000000) -+ subfzeo ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+PPC integer arith insns with one arg and carry with flags update: -+ addme. 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ addme. 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ addme. ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ addme. 0000000000000000 => 0000000000000000 (20000000 20000000) -+ addme. 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ addme. ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ -+ addmeo. 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ addmeo. 0000001cbe991def => 0000001cbe991dee (40000000 20000000) -+ addmeo. ffffffffffffffff => fffffffffffffffe (80000000 20000000) -+ addmeo. 0000000000000000 => 0000000000000000 (20000000 20000000) -+ addmeo. 0000001cbe991def => 0000001cbe991def (40000000 20000000) -+ addmeo. ffffffffffffffff => ffffffffffffffff (80000000 20000000) -+ -+ addze. 0000000000000000 => 0000000000000000 (20000000 00000000) -+ addze. 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ addze. ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ addze. 0000000000000000 => 0000000000000001 (40000000 00000000) -+ addze. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ addze. ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+ addzeo. 0000000000000000 => 0000000000000000 (20000000 00000000) -+ addzeo. 0000001cbe991def => 0000001cbe991def (40000000 00000000) -+ addzeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ addzeo. 0000000000000000 => 0000000000000001 (40000000 00000000) -+ addzeo. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000) -+ addzeo. ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+ subfme. 0000000000000000 => fffffffffffffffe (80000000 20000000) -+ subfme. 0000001cbe991def => ffffffe34166e20f (80000000 20000000) -+ subfme. ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ subfme. 0000000000000000 => ffffffffffffffff (80000000 20000000) -+ subfme. 0000001cbe991def => ffffffe34166e210 (80000000 20000000) -+ subfme. ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+ subfmeo. 0000000000000000 => fffffffffffffffe (80000000 20000000) -+ subfmeo. 0000001cbe991def => ffffffe34166e20f (80000000 20000000) -+ subfmeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ subfmeo. 0000000000000000 => ffffffffffffffff (80000000 20000000) -+ subfmeo. 0000001cbe991def => ffffffe34166e210 (80000000 20000000) -+ subfmeo. ffffffffffffffff => 0000000000000000 (20000000 20000000) -+ -+ subfze. 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ subfze. 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ subfze. ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ subfze. 0000000000000000 => 0000000000000000 (20000000 20000000) -+ subfze. 0000001cbe991def => ffffffe34166e211 (80000000 00000000) -+ subfze. ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ subfzeo. 0000000000000000 => ffffffffffffffff (80000000 00000000) -+ subfzeo. 0000001cbe991def => ffffffe34166e210 (80000000 00000000) -+ subfzeo. ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ subfzeo. 0000000000000000 => 0000000000000000 (20000000 20000000) -+ subfzeo. 0000001cbe991def => ffffffe34166e211 (80000000 00000000) -+ subfzeo. ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+PPC integer logical insns with one arg: -+ cntlzw 0000000000000000 => 0000000000000020 (00000000 00000000) -+ cntlzw 0000001cbe991def => 0000000000000000 (00000000 00000000) -+ cntlzw ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ extsb 0000000000000000 => 0000000000000000 (00000000 00000000) -+ extsb 0000001cbe991def => ffffffffffffffef (00000000 00000000) -+ extsb ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ -+ extsh 0000000000000000 => 0000000000000000 (00000000 00000000) -+ extsh 0000001cbe991def => 0000000000001def (00000000 00000000) -+ extsh ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ -+ neg 0000000000000000 => 0000000000000000 (00000000 00000000) -+ neg 0000001cbe991def => ffffffe34166e211 (00000000 00000000) -+ neg ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ nego 0000000000000000 => 0000000000000000 (00000000 00000000) -+ nego 0000001cbe991def => ffffffe34166e211 (00000000 00000000) -+ nego ffffffffffffffff => 0000000000000001 (00000000 00000000) -+ -+ cntlzd 0000000000000000 => 0000000000000040 (00000000 00000000) -+ cntlzd 0000001cbe991def => 000000000000001b (00000000 00000000) -+ cntlzd ffffffffffffffff => 0000000000000000 (00000000 00000000) -+ -+ extsw 0000000000000000 => 0000000000000000 (00000000 00000000) -+ extsw 0000001cbe991def => ffffffffbe991def (00000000 00000000) -+ extsw ffffffffffffffff => ffffffffffffffff (00000000 00000000) -+ -+PPC integer logical insns with one arg with flags update: -+ cntlzw. 0000000000000000 => 0000000000000020 (40000000 00000000) -+ cntlzw. 0000001cbe991def => 0000000000000000 (20000000 00000000) -+ cntlzw. ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ extsb. 0000000000000000 => 0000000000000000 (20000000 00000000) -+ extsb. 0000001cbe991def => ffffffffffffffef (80000000 00000000) -+ extsb. ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ -+ extsh. 0000000000000000 => 0000000000000000 (20000000 00000000) -+ extsh. 0000001cbe991def => 0000000000001def (40000000 00000000) -+ extsh. ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ -+ neg. 0000000000000000 => 0000000000000000 (20000000 00000000) -+ neg. 0000001cbe991def => ffffffe34166e211 (80000000 00000000) -+ neg. ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ nego. 0000000000000000 => 0000000000000000 (20000000 00000000) -+ nego. 0000001cbe991def => ffffffe34166e211 (80000000 00000000) -+ nego. ffffffffffffffff => 0000000000000001 (40000000 00000000) -+ -+ cntlzd. 0000000000000000 => 0000000000000040 (40000000 00000000) -+ cntlzd. 0000001cbe991def => 000000000000001b (40000000 00000000) -+ cntlzd. ffffffffffffffff => 0000000000000000 (20000000 00000000) -+ -+ extsw. 0000000000000000 => 0000000000000000 (20000000 00000000) -+ extsw. 0000001cbe991def => ffffffffbe991def (80000000 00000000) -+ extsw. ffffffffffffffff => ffffffffffffffff (80000000 00000000) -+ -+PPC logical insns with special forms: -+ rlwimi 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwimi 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwimi 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000) -+ rlwimi 0000001cbe991def, 0, 31, 0 => be991defbe991def (00000000 00000000) -+ rlwimi 0000001cbe991def, 0, 31, 31 => be991defbe991def (00000000 00000000) -+ rlwimi 0000001cbe991def, 31, 0, 0 => be991defbe991def (00000000 00000000) -+ rlwimi 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (00000000 00000000) -+ rlwimi 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (00000000 00000000) -+ rlwimi 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (00000000 00000000) -+ rlwimi ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (00000000 00000000) -+ rlwimi ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (00000000 00000000) -+ rlwimi ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (00000000 00000000) -+ rlwimi ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (00000000 00000000) -+ rlwimi ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (00000000 00000000) -+ rlwimi ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (00000000 00000000) -+ rlwimi ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (00000000 00000000) -+ rlwimi ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (00000000 00000000) -+ -+ rlwinm 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwinm 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwinm 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000) -+ rlwinm 0000001cbe991def, 0, 31, 0 => be991def80000001 (00000000 00000000) -+ rlwinm 0000001cbe991def, 0, 31, 31 => 0000000000000001 (00000000 00000000) -+ rlwinm 0000001cbe991def, 31, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwinm 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (00000000 00000000) -+ rlwinm 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (00000000 00000000) -+ rlwinm 0000001cbe991def, 31, 31, 31 => 0000000000000001 (00000000 00000000) -+ rlwinm ffffffffffffffff, 0, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwinm ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (00000000 00000000) -+ rlwinm ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (00000000 00000000) -+ rlwinm ffffffffffffffff, 0, 31, 31 => 0000000000000001 (00000000 00000000) -+ rlwinm ffffffffffffffff, 31, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwinm ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (00000000 00000000) -+ rlwinm ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (00000000 00000000) -+ rlwinm ffffffffffffffff, 31, 31, 31 => 0000000000000001 (00000000 00000000) -+ -+ rlwnm 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (00000000 00000000) -+ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000) -+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (00000000 00000000) -+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (00000000 00000000) -+ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (00000000 00000000) -+ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (00000000 00000000) -+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000) -+ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (00000000 00000000) -+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (00000000 00000000) -+ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000) -+ -+ srawi 0000000000000000, 0 => 0000000000000000 (00000000 00000000) -+ srawi 0000000000000000, 31 => 0000000000000000 (00000000 00000000) -+ srawi 0000001cbe991def, 0 => ffffffffbe991def (00000000 00000000) -+ srawi 0000001cbe991def, 31 => ffffffffffffffff (00000000 20000000) -+ srawi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000) -+ srawi ffffffffffffffff, 31 => ffffffffffffffff (00000000 20000000) -+ -+ mfcr (0000000000000000) => 0000000000000000 (00000000 00000000) -+ mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000) -+ mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000) -+ -+ mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000 -+ mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f -+ mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f -+ mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000 -+ mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def -+ mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff -+ mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000 -+ mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def -+ mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff -+ -+ -+ rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000) -+ rldcl 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (00000000 00000000) -+ rldcl 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (00000000 00000000) -+ rldcl 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (00000000 00000000) -+ rldcl 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (00000000 00000000) -+ rldcl ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (00000000 00000000) -+ rldcl ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000) -+ -+ rldcr 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000) -+ rldcr 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (00000000 00000000) -+ rldcr 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (00000000 00000000) -+ rldcr 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (00000000 00000000) -+ rldcr ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (00000000 00000000) -+ rldcr ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (00000000 00000000) -+ -+ rldic 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000) -+ rldic 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000) -+ rldic 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000) -+ rldic 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000) -+ rldic 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 0 => cbe991def0000000 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 7 => 01e991def0000000 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 14 => 000191def0000000 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 21 => 000001def0000000 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 28 => 0000000ef0000000 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 35 => 0000000010000000 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 42 => cbe991def0000001 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 49 => cbe991def0000001 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 56 => cbe991def0000001 (00000000 00000000) -+ rldic 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 0 => f4c8ef7800000000 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 7 => 00c8ef7800000000 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 14 => 0000ef7800000000 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 21 => 0000077800000000 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 28 => 0000000800000000 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (00000000 00000000) -+ rldic 0000001cbe991def, 35, 63 => f4c8ef7800000001 (00000000 00000000) -+ rldic 0000001cbe991def, 42, 0 => 6477bc0000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 42, 7 => 0077bc0000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 42, 14 => 0003bc0000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 42, 21 => 0000040000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 42, 28 => 6477bc00000072fa (00000000 00000000) -+ rldic 0000001cbe991def, 42, 35 => 6477bc00000072fa (00000000 00000000) -+ rldic 0000001cbe991def, 42, 42 => 6477bc00000072fa (00000000 00000000) -+ rldic 0000001cbe991def, 42, 49 => 6477bc00000072fa (00000000 00000000) -+ rldic 0000001cbe991def, 42, 56 => 6477bc00000000fa (00000000 00000000) -+ rldic 0000001cbe991def, 42, 63 => 6477bc0000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 0 => 3bde000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 7 => 01de000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 14 => 0002000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 21 => 3bde000000397d32 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 28 => 3bde000000397d32 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 35 => 3bde000000397d32 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 42 => 3bde000000397d32 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 49 => 3bde000000007d32 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 56 => 3bde000000000032 (00000000 00000000) -+ rldic 0000001cbe991def, 49, 63 => 3bde000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 56, 0 => ef00000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 56, 7 => 0100000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 56, 14 => ef0000001cbe991d (00000000 00000000) -+ rldic 0000001cbe991def, 56, 21 => ef0000001cbe991d (00000000 00000000) -+ rldic 0000001cbe991def, 56, 28 => ef0000001cbe991d (00000000 00000000) -+ rldic 0000001cbe991def, 56, 35 => ef0000001cbe991d (00000000 00000000) -+ rldic 0000001cbe991def, 56, 42 => ef000000003e991d (00000000 00000000) -+ rldic 0000001cbe991def, 56, 49 => ef0000000000191d (00000000 00000000) -+ rldic 0000001cbe991def, 56, 56 => ef0000000000001d (00000000 00000000) -+ rldic 0000001cbe991def, 56, 63 => ef00000000000001 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 42 => 80000000000c8ef7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 49 => 8000000000000ef7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 56 => 80000000000000f7 (00000000 00000000) -+ rldic 0000001cbe991def, 63, 63 => 8000000000000001 (00000000 00000000) -+ rldic ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000) -+ rldic ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 0 => ffffffffffffff80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 7 => 01ffffffffffff80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 14 => 0003ffffffffff80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 21 => 000007ffffffff80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 28 => 0000000fffffff80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 35 => 000000001fffff80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 42 => 00000000003fff80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 49 => 0000000000007f80 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 56 => 0000000000000080 (00000000 00000000) -+ rldic ffffffffffffffff, 7, 63 => ffffffffffffff81 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 0 => ffffffffffffc000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 7 => 01ffffffffffc000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 14 => 0003ffffffffc000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 21 => 000007ffffffc000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 28 => 0000000fffffc000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 35 => 000000001fffc000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 42 => 00000000003fc000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 49 => 0000000000004000 (00000000 00000000) -+ rldic ffffffffffffffff, 14, 56 => ffffffffffffc0ff (00000000 00000000) -+ rldic ffffffffffffffff, 14, 63 => ffffffffffffc001 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 0 => ffffffffffe00000 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 7 => 01ffffffffe00000 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 14 => 0003ffffffe00000 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 21 => 000007ffffe00000 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 28 => 0000000fffe00000 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 35 => 000000001fe00000 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 42 => 0000000000200000 (00000000 00000000) -+ rldic ffffffffffffffff, 21, 49 => ffffffffffe07fff (00000000 00000000) -+ rldic ffffffffffffffff, 21, 56 => ffffffffffe000ff (00000000 00000000) -+ rldic ffffffffffffffff, 21, 63 => ffffffffffe00001 (00000000 00000000) -+ rldic ffffffffffffffff, 28, 0 => fffffffff0000000 (00000000 00000000) -+ rldic ffffffffffffffff, 28, 7 => 01fffffff0000000 (00000000 00000000) -+ rldic ffffffffffffffff, 28, 14 => 0003fffff0000000 (00000000 00000000) -+ rldic ffffffffffffffff, 28, 21 => 000007fff0000000 (00000000 00000000) -+ rldic ffffffffffffffff, 28, 28 => 0000000ff0000000 (00000000 00000000) -+ rldic ffffffffffffffff, 28, 35 => 0000000010000000 (00000000 00000000) -+ rldic ffffffffffffffff, 28, 42 => fffffffff03fffff (00000000 00000000) -+ rldic ffffffffffffffff, 28, 49 => fffffffff0007fff (00000000 00000000) -+ rldic ffffffffffffffff, 28, 56 => fffffffff00000ff (00000000 00000000) -+ rldic ffffffffffffffff, 28, 63 => fffffffff0000001 (00000000 00000000) -+ rldic ffffffffffffffff, 35, 0 => fffffff800000000 (00000000 00000000) -+ rldic ffffffffffffffff, 35, 7 => 01fffff800000000 (00000000 00000000) -+ rldic ffffffffffffffff, 35, 14 => 0003fff800000000 (00000000 00000000) -+ rldic ffffffffffffffff, 35, 21 => 000007f800000000 (00000000 00000000) -+ rldic ffffffffffffffff, 35, 28 => 0000000800000000 (00000000 00000000) -+ rldic ffffffffffffffff, 35, 35 => fffffff81fffffff (00000000 00000000) -+ rldic ffffffffffffffff, 35, 42 => fffffff8003fffff (00000000 00000000) -+ rldic ffffffffffffffff, 35, 49 => fffffff800007fff (00000000 00000000) -+ rldic ffffffffffffffff, 35, 56 => fffffff8000000ff (00000000 00000000) -+ rldic ffffffffffffffff, 35, 63 => fffffff800000001 (00000000 00000000) -+ rldic ffffffffffffffff, 42, 0 => fffffc0000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 42, 7 => 01fffc0000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 42, 14 => 0003fc0000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 42, 21 => 0000040000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 42, 28 => fffffc0fffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 42, 35 => fffffc001fffffff (00000000 00000000) -+ rldic ffffffffffffffff, 42, 42 => fffffc00003fffff (00000000 00000000) -+ rldic ffffffffffffffff, 42, 49 => fffffc0000007fff (00000000 00000000) -+ rldic ffffffffffffffff, 42, 56 => fffffc00000000ff (00000000 00000000) -+ rldic ffffffffffffffff, 42, 63 => fffffc0000000001 (00000000 00000000) -+ rldic ffffffffffffffff, 49, 0 => fffe000000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 49, 7 => 01fe000000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 49, 14 => 0002000000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 49, 21 => fffe07ffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 49, 28 => fffe000fffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 49, 35 => fffe00001fffffff (00000000 00000000) -+ rldic ffffffffffffffff, 49, 42 => fffe0000003fffff (00000000 00000000) -+ rldic ffffffffffffffff, 49, 49 => fffe000000007fff (00000000 00000000) -+ rldic ffffffffffffffff, 49, 56 => fffe0000000000ff (00000000 00000000) -+ rldic ffffffffffffffff, 49, 63 => fffe000000000001 (00000000 00000000) -+ rldic ffffffffffffffff, 56, 0 => ff00000000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 56, 7 => 0100000000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 56, 14 => ff03ffffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 56, 21 => ff0007ffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 56, 28 => ff00000fffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 56, 35 => ff0000001fffffff (00000000 00000000) -+ rldic ffffffffffffffff, 56, 42 => ff000000003fffff (00000000 00000000) -+ rldic ffffffffffffffff, 56, 49 => ff00000000007fff (00000000 00000000) -+ rldic ffffffffffffffff, 56, 56 => ff000000000000ff (00000000 00000000) -+ rldic ffffffffffffffff, 56, 63 => ff00000000000001 (00000000 00000000) -+ rldic ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000) -+ rldic ffffffffffffffff, 63, 7 => 81ffffffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 14 => 8003ffffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 21 => 800007ffffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 28 => 8000000fffffffff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 35 => 800000001fffffff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 42 => 80000000003fffff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 49 => 8000000000007fff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 56 => 80000000000000ff (00000000 00000000) -+ rldic ffffffffffffffff, 63, 63 => 8000000000000001 (00000000 00000000) -+ -+ rldicl 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000) -+ rldicl 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000) -+ rldicl 0000001cbe991def, 7, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 14, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 49 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 56 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 21, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 0 => cbe991def0000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 7 => 01e991def0000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 14 => 000191def0000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 21 => 000001def0000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 28 => 0000000ef0000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 35 => 0000000010000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 42 => 0000000000000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 49 => 0000000000000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 56 => 0000000000000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 28, 63 => 0000000000000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 14 => 0000ef78000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 21 => 00000778000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 28 => 00000008000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 35 => 00000000000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 42 => 00000000000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 49 => 00000000000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 56 => 00000000000000e5 (00000000 00000000) -+ rldicl 0000001cbe991def, 35, 63 => 0000000000000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 0 => 6477bc00000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 7 => 0077bc00000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 14 => 0003bc00000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 21 => 00000400000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 28 => 00000000000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 35 => 00000000000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 42 => 00000000000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 49 => 00000000000072fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 56 => 00000000000000fa (00000000 00000000) -+ rldicl 0000001cbe991def, 42, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 0 => 3bde000000397d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 7 => 01de000000397d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 14 => 0002000000397d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 21 => 0000000000397d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 28 => 0000000000397d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 35 => 0000000000397d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 42 => 0000000000397d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 49 => 0000000000007d32 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 56 => 0000000000000032 (00000000 00000000) -+ rldicl 0000001cbe991def, 49, 63 => 0000000000000000 (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 0 => ef0000001cbe991d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 7 => 010000001cbe991d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 14 => 000000001cbe991d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 21 => 000000001cbe991d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 28 => 000000001cbe991d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 35 => 000000001cbe991d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 42 => 00000000003e991d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 49 => 000000000000191d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 56 => 000000000000001d (00000000 00000000) -+ rldicl 0000001cbe991def, 56, 63 => 0000000000000001 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 42 => 00000000000c8ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 49 => 0000000000000ef7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 56 => 00000000000000f7 (00000000 00000000) -+ rldicl 0000001cbe991def, 63, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 7, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 14, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 21, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 28, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 35, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 42, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 49, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 56, 63 => 0000000000000001 (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 7 => 01ffffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 14 => 0003ffffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 21 => 000007ffffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 28 => 0000000fffffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 35 => 000000001fffffff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 42 => 00000000003fffff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 49 => 0000000000007fff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 56 => 00000000000000ff (00000000 00000000) -+ rldicl ffffffffffffffff, 63, 63 => 0000000000000001 (00000000 00000000) -+ -+ rldicr 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000) -+ rldicr 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 21 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 28 => 0000001800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 35 => 0000001cb0000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 42 => 0000001cbe800000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 49 => 0000001cbe990000 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 56 => 0000001cbe991d80 (00000000 00000000) -+ rldicr 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 14 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 21 => 00000c0000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 28 => 00000e5800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 35 => 00000e5f40000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 42 => 00000e5f4c800000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (00000000 00000000) -+ rldicr 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 7 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 14 => 0006000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 21 => 00072c0000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 28 => 00072fa000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 35 => 00072fa640000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 42 => 00072fa647600000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 49 => 00072fa6477bc000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000) -+ rldicr 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 7 => 0300000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 14 => 0396000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 21 => 0397d00000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 28 => 0397d32000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 35 => 0397d323b0000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 42 => 0397d323bde00000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000) -+ rldicr 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 0 => 8000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 7 => cb00000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 14 => cbe8000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 21 => cbe9900000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 28 => cbe991d800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 35 => cbe991def0000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 42 => cbe991def0000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 49 => cbe991def0000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 56 => cbe991def0000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 0 => 8000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 7 => f400000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 14 => f4c8000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 21 => f4c8ec0000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 28 => f4c8ef7800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 35 => f4c8ef7800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 42 => f4c8ef7800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 49 => f4c8ef7800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 56 => f4c8ef7800000080 (00000000 00000000) -+ rldicr 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 7 => 6400000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 14 => 6476000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 21 => 6477bc0000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 28 => 6477bc0000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 35 => 6477bc0000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 42 => 6477bc0000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 49 => 6477bc0000004000 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 56 => 6477bc0000007280 (00000000 00000000) -+ rldicr 0000001cbe991def, 42, 63 => 6477bc00000072fa (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 0 => 0000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 7 => 3b00000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 14 => 3bde000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 21 => 3bde000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 28 => 3bde000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 35 => 3bde000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 42 => 3bde000000200000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 49 => 3bde000000394000 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 56 => 3bde000000397d00 (00000000 00000000) -+ rldicr 0000001cbe991def, 49, 63 => 3bde000000397d32 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 0 => 8000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 7 => ef00000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 14 => ef00000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 21 => ef00000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 28 => ef00000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 35 => ef00000010000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 42 => ef0000001ca00000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 49 => ef0000001cbe8000 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 56 => ef0000001cbe9900 (00000000 00000000) -+ rldicr 0000001cbe991def, 56, 63 => ef0000001cbe991d (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 7 => 8000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 14 => 8000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 21 => 8000000000000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 28 => 8000000800000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 35 => 8000000e50000000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 42 => 8000000e5f400000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (00000000 00000000) -+ rldicr 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 7 => ff00000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 14 => fffe000000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 21 => fffffc0000000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 28 => fffffff800000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 35 => fffffffff0000000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 42 => ffffffffffe00000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 49 => ffffffffffffc000 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 56 => ffffffffffffff80 (00000000 00000000) -+ rldicr ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000) -+ -+ rldimi 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000) -+ rldimi 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 28 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 35 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 42 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 49 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 56 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (00000000 00000000) -+ rldimi 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 56 => 00072fa6477bf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 14, 63 => 00072fa6477bf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 0 => cbe991defdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 7 => cbe991defdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 14 => cbe991defdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 21 => cbe991defdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 28 => cbe991defdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 35 => cbe991defdfb8000 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 42 => cbe991defdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 49 => cbe991defdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 56 => cbe991defdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 28, 63 => cbe991defdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 28 => 6477bf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 35 => 6477bf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 42 => 6477bf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 49 => 6477bf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 56 => 6477bf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 42, 63 => 6477bf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 0 => efdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 7 => efdfb80000397d32 (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 14 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 21 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 28 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 35 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 42 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 49 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 56 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 56, 63 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 0 => efdc00001cbe991d (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 7 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 14 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 21 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 28 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 35 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 42 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 49 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 56 => ffffffffffffffff (00000000 00000000) -+ rldimi ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000) -+ -+ sradi 0000000000000000, 0 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 7 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 14 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 21 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 28 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 35 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 42 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 49 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 56 => 0000000000000000 (00000000 00000000) -+ sradi 0000000000000000, 63 => 0000000000000000 (00000000 00000000) -+ sradi 0000001cbe991def, 0 => 0000001cbe991def (00000000 00000000) -+ sradi 0000001cbe991def, 7 => 00000000397d323b (00000000 00000000) -+ sradi 0000001cbe991def, 14 => 000000000072fa64 (00000000 00000000) -+ sradi 0000001cbe991def, 21 => 000000000000e5f4 (00000000 00000000) -+ sradi 0000001cbe991def, 28 => 00000000000001cb (00000000 00000000) -+ sradi 0000001cbe991def, 35 => 0000000000000003 (00000000 00000000) -+ sradi 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000) -+ sradi 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000) -+ sradi 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000) -+ sradi 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000) -+ sradi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000) -+ sradi ffffffffffffffff, 7 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 14 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 21 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 28 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 35 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 42 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 49 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 56 => ffffffffffffffff (00000000 20000000) -+ sradi ffffffffffffffff, 63 => ffffffffffffffff (00000000 20000000) -+ -+PPC logical insns with special forms with flags update: -+ rlwimi. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwimi. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwimi. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000) -+ rlwimi. 0000001cbe991def, 0, 31, 0 => be991defbe991def (80000000 00000000) -+ rlwimi. 0000001cbe991def, 0, 31, 31 => be991defbe991def (80000000 00000000) -+ rlwimi. 0000001cbe991def, 31, 0, 0 => be991defbe991def (80000000 00000000) -+ rlwimi. 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (80000000 00000000) -+ rlwimi. 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (80000000 00000000) -+ rlwimi. 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (80000000 00000000) -+ rlwimi. ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (80000000 00000000) -+ rlwimi. ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (80000000 00000000) -+ rlwimi. ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (80000000 00000000) -+ rlwimi. ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (80000000 00000000) -+ rlwimi. ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (80000000 00000000) -+ rlwimi. ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (80000000 00000000) -+ rlwimi. ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (80000000 00000000) -+ rlwimi. ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (80000000 00000000) -+ -+ rlwinm. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwinm. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwinm. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000) -+ rlwinm. 0000001cbe991def, 0, 31, 0 => be991def80000001 (80000000 00000000) -+ rlwinm. 0000001cbe991def, 0, 31, 31 => 0000000000000001 (40000000 00000000) -+ rlwinm. 0000001cbe991def, 31, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwinm. 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (40000000 00000000) -+ rlwinm. 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (80000000 00000000) -+ rlwinm. 0000001cbe991def, 31, 31, 31 => 0000000000000001 (40000000 00000000) -+ rlwinm. ffffffffffffffff, 0, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwinm. ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (40000000 00000000) -+ rlwinm. ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (80000000 00000000) -+ rlwinm. ffffffffffffffff, 0, 31, 31 => 0000000000000001 (40000000 00000000) -+ rlwinm. ffffffffffffffff, 31, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwinm. ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (40000000 00000000) -+ rlwinm. ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (80000000 00000000) -+ rlwinm. ffffffffffffffff, 31, 31, 31 => 0000000000000001 (40000000 00000000) -+ -+ rlwnm. 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwnm. 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (40000000 00000000) -+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (80000000 00000000) -+ rlwnm. 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000) -+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (40000000 00000000) -+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (80000000 00000000) -+ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000) -+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (40000000 00000000) -+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (80000000 00000000) -+ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000) -+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwnm. ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (40000000 00000000) -+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (80000000 00000000) -+ rlwnm. ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000) -+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (40000000 00000000) -+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (80000000 00000000) -+ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (40000000 00000000) -+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000) -+ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (40000000 00000000) -+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (80000000 00000000) -+ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000) -+ -+ srawi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000) -+ srawi. 0000000000000000, 31 => 0000000000000000 (20000000 00000000) -+ srawi. 0000001cbe991def, 0 => ffffffffbe991def (80000000 00000000) -+ srawi. 0000001cbe991def, 31 => ffffffffffffffff (80000000 20000000) -+ srawi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000) -+ srawi. ffffffffffffffff, 31 => ffffffffffffffff (80000000 20000000) -+ -+ mcrf 0, 0 (0000000000000000) => (00000000 00000000) -+ mcrf 0, 7 (0000000000000000) => (00000000 00000000) -+ mcrf 7, 0 (0000000000000000) => (00000000 00000000) -+ mcrf 7, 7 (0000000000000000) => (00000000 00000000) -+ mcrf 0, 0 (0000001cbe991def) => (be991def 00000000) -+ mcrf 0, 7 (0000001cbe991def) => (fe991def 00000000) -+ mcrf 7, 0 (0000001cbe991def) => (be991deb 00000000) -+ mcrf 7, 7 (0000001cbe991def) => (be991def 00000000) -+ mcrf 0, 0 (ffffffffffffffff) => (ffffffff 00000000) -+ mcrf 0, 7 (ffffffffffffffff) => (ffffffff 00000000) -+ mcrf 7, 0 (ffffffffffffffff) => (ffffffff 00000000) -+ mcrf 7, 7 (ffffffffffffffff) => (ffffffff 00000000) -+ -+ mcrxr 0 (00000000) => (00000000 00000000) -+ mcrxr 1 (00000000) => (00000000 00000000) -+ mcrxr 2 (00000000) => (00000000 00000000) -+ mcrxr 3 (00000000) => (00000000 00000000) -+ mcrxr 4 (00000000) => (00000000 00000000) -+ mcrxr 5 (00000000) => (00000000 00000000) -+ mcrxr 6 (00000000) => (00000000 00000000) -+ mcrxr 7 (00000000) => (00000000 00000000) -+ mcrxr 0 (10000000) => (00000000 00000000) -+ mcrxr 1 (10000000) => (00000000 00000000) -+ mcrxr 2 (10000000) => (00000000 00000000) -+ mcrxr 3 (10000000) => (00000000 00000000) -+ mcrxr 4 (10000000) => (00000000 00000000) -+ mcrxr 5 (10000000) => (00000000 00000000) -+ mcrxr 6 (10000000) => (00000000 00000000) -+ mcrxr 7 (10000000) => (00000000 00000000) -+ mcrxr 0 (20000000) => (20000000 00000000) -+ mcrxr 1 (20000000) => (02000000 00000000) -+ mcrxr 2 (20000000) => (00200000 00000000) -+ mcrxr 3 (20000000) => (00020000 00000000) -+ mcrxr 4 (20000000) => (00002000 00000000) -+ mcrxr 5 (20000000) => (00000200 00000000) -+ mcrxr 6 (20000000) => (00000020 00000000) -+ mcrxr 7 (20000000) => (00000002 00000000) -+ mcrxr 0 (30000000) => (20000000 00000000) -+ mcrxr 1 (30000000) => (02000000 00000000) -+ mcrxr 2 (30000000) => (00200000 00000000) -+ mcrxr 3 (30000000) => (00020000 00000000) -+ mcrxr 4 (30000000) => (00002000 00000000) -+ mcrxr 5 (30000000) => (00000200 00000000) -+ mcrxr 6 (30000000) => (00000020 00000000) -+ mcrxr 7 (30000000) => (00000002 00000000) -+ mcrxr 0 (40000000) => (40000000 00000000) -+ mcrxr 1 (40000000) => (04000000 00000000) -+ mcrxr 2 (40000000) => (00400000 00000000) -+ mcrxr 3 (40000000) => (00040000 00000000) -+ mcrxr 4 (40000000) => (00004000 00000000) -+ mcrxr 5 (40000000) => (00000400 00000000) -+ mcrxr 6 (40000000) => (00000040 00000000) -+ mcrxr 7 (40000000) => (00000004 00000000) -+ mcrxr 0 (50000000) => (40000000 00000000) -+ mcrxr 1 (50000000) => (04000000 00000000) -+ mcrxr 2 (50000000) => (00400000 00000000) -+ mcrxr 3 (50000000) => (00040000 00000000) -+ mcrxr 4 (50000000) => (00004000 00000000) -+ mcrxr 5 (50000000) => (00000400 00000000) -+ mcrxr 6 (50000000) => (00000040 00000000) -+ mcrxr 7 (50000000) => (00000004 00000000) -+ mcrxr 0 (60000000) => (60000000 00000000) -+ mcrxr 1 (60000000) => (06000000 00000000) -+ mcrxr 2 (60000000) => (00600000 00000000) -+ mcrxr 3 (60000000) => (00060000 00000000) -+ mcrxr 4 (60000000) => (00006000 00000000) -+ mcrxr 5 (60000000) => (00000600 00000000) -+ mcrxr 6 (60000000) => (00000060 00000000) -+ mcrxr 7 (60000000) => (00000006 00000000) -+ mcrxr 0 (70000000) => (60000000 00000000) -+ mcrxr 1 (70000000) => (06000000 00000000) -+ mcrxr 2 (70000000) => (00600000 00000000) -+ mcrxr 3 (70000000) => (00060000 00000000) -+ mcrxr 4 (70000000) => (00006000 00000000) -+ mcrxr 5 (70000000) => (00000600 00000000) -+ mcrxr 6 (70000000) => (00000060 00000000) -+ mcrxr 7 (70000000) => (00000006 00000000) -+ mcrxr 0 (80000000) => (80000000 00000000) -+ mcrxr 1 (80000000) => (08000000 00000000) -+ mcrxr 2 (80000000) => (00800000 00000000) -+ mcrxr 3 (80000000) => (00080000 00000000) -+ mcrxr 4 (80000000) => (00008000 00000000) -+ mcrxr 5 (80000000) => (00000800 00000000) -+ mcrxr 6 (80000000) => (00000080 00000000) -+ mcrxr 7 (80000000) => (00000008 00000000) -+ mcrxr 0 (90000000) => (80000000 00000000) -+ mcrxr 1 (90000000) => (08000000 00000000) -+ mcrxr 2 (90000000) => (00800000 00000000) -+ mcrxr 3 (90000000) => (00080000 00000000) -+ mcrxr 4 (90000000) => (00008000 00000000) -+ mcrxr 5 (90000000) => (00000800 00000000) -+ mcrxr 6 (90000000) => (00000080 00000000) -+ mcrxr 7 (90000000) => (00000008 00000000) -+ mcrxr 0 (a0000000) => (a0000000 00000000) -+ mcrxr 1 (a0000000) => (0a000000 00000000) -+ mcrxr 2 (a0000000) => (00a00000 00000000) -+ mcrxr 3 (a0000000) => (000a0000 00000000) -+ mcrxr 4 (a0000000) => (0000a000 00000000) -+ mcrxr 5 (a0000000) => (00000a00 00000000) -+ mcrxr 6 (a0000000) => (000000a0 00000000) -+ mcrxr 7 (a0000000) => (0000000a 00000000) -+ mcrxr 0 (b0000000) => (a0000000 00000000) -+ mcrxr 1 (b0000000) => (0a000000 00000000) -+ mcrxr 2 (b0000000) => (00a00000 00000000) -+ mcrxr 3 (b0000000) => (000a0000 00000000) -+ mcrxr 4 (b0000000) => (0000a000 00000000) -+ mcrxr 5 (b0000000) => (00000a00 00000000) -+ mcrxr 6 (b0000000) => (000000a0 00000000) -+ mcrxr 7 (b0000000) => (0000000a 00000000) -+ mcrxr 0 (c0000000) => (c0000000 00000000) -+ mcrxr 1 (c0000000) => (0c000000 00000000) -+ mcrxr 2 (c0000000) => (00c00000 00000000) -+ mcrxr 3 (c0000000) => (000c0000 00000000) -+ mcrxr 4 (c0000000) => (0000c000 00000000) -+ mcrxr 5 (c0000000) => (00000c00 00000000) -+ mcrxr 6 (c0000000) => (000000c0 00000000) -+ mcrxr 7 (c0000000) => (0000000c 00000000) -+ mcrxr 0 (d0000000) => (c0000000 00000000) -+ mcrxr 1 (d0000000) => (0c000000 00000000) -+ mcrxr 2 (d0000000) => (00c00000 00000000) -+ mcrxr 3 (d0000000) => (000c0000 00000000) -+ mcrxr 4 (d0000000) => (0000c000 00000000) -+ mcrxr 5 (d0000000) => (00000c00 00000000) -+ mcrxr 6 (d0000000) => (000000c0 00000000) -+ mcrxr 7 (d0000000) => (0000000c 00000000) -+ mcrxr 0 (e0000000) => (e0000000 00000000) -+ mcrxr 1 (e0000000) => (0e000000 00000000) -+ mcrxr 2 (e0000000) => (00e00000 00000000) -+ mcrxr 3 (e0000000) => (000e0000 00000000) -+ mcrxr 4 (e0000000) => (0000e000 00000000) -+ mcrxr 5 (e0000000) => (00000e00 00000000) -+ mcrxr 6 (e0000000) => (000000e0 00000000) -+ mcrxr 7 (e0000000) => (0000000e 00000000) -+ mcrxr 0 (f0000000) => (e0000000 00000000) -+ mcrxr 1 (f0000000) => (0e000000 00000000) -+ mcrxr 2 (f0000000) => (00e00000 00000000) -+ mcrxr 3 (f0000000) => (000e0000 00000000) -+ mcrxr 4 (f0000000) => (0000e000 00000000) -+ mcrxr 5 (f0000000) => (00000e00 00000000) -+ mcrxr 6 (f0000000) => (000000e0 00000000) -+ mcrxr 7 (f0000000) => (0000000e 00000000) -+ -+ mtcrf 0, 0000000000000000 => (00000000 00000000) -+ mtcrf 99, 0000000000000000 => (00000000 00000000) -+ mtcrf 198, 0000000000000000 => (00000000 00000000) -+ mtcrf 0, 0000001cbe991def => (00000000 00000000) -+ mtcrf 99, 0000001cbe991def => (0e9000ef 00000000) -+ mtcrf 198, 0000001cbe991def => (be000de0 00000000) -+ mtcrf 0, ffffffffffffffff => (00000000 00000000) -+ mtcrf 99, ffffffffffffffff => (0ff000ff 00000000) -+ mtcrf 198, ffffffffffffffff => (ff000ff0 00000000) -+ -+ rldcl. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (80000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (40000000 00000000) -+ rldcl. 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (40000000 00000000) -+ rldcl. 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (80000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (80000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (40000000 00000000) -+ rldcl. ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (40000000 00000000) -+ rldcl. ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000) -+ -+ rldcr. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (20000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (40000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (40000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (40000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (40000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (40000000 00000000) -+ rldcr. 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (40000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (80000000 00000000) -+ rldcr. 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (80000000 00000000) -+ rldcr. 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (80000000 00000000) -+ rldcr. ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (80000000 00000000) -+ rldcr. ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (80000000 00000000) -+ -+ rldic. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000) -+ rldic. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000) -+ rldic. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000) -+ rldic. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000) -+ rldic. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000) -+ rldic. 0000001cbe991def, 28, 0 => cbe991def0000000 (80000000 00000000) -+ rldic. 0000001cbe991def, 28, 7 => 01e991def0000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 28, 14 => 000191def0000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 28, 21 => 000001def0000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 28, 28 => 0000000ef0000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 28, 35 => 0000000010000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 28, 42 => cbe991def0000001 (80000000 00000000) -+ rldic. 0000001cbe991def, 28, 49 => cbe991def0000001 (80000000 00000000) -+ rldic. 0000001cbe991def, 28, 56 => cbe991def0000001 (80000000 00000000) -+ rldic. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000) -+ rldic. 0000001cbe991def, 35, 0 => f4c8ef7800000000 (80000000 00000000) -+ rldic. 0000001cbe991def, 35, 7 => 00c8ef7800000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 35, 14 => 0000ef7800000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 35, 21 => 0000077800000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 35, 28 => 0000000800000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (80000000 00000000) -+ rldic. 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (80000000 00000000) -+ rldic. 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (80000000 00000000) -+ rldic. 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (80000000 00000000) -+ rldic. 0000001cbe991def, 35, 63 => f4c8ef7800000001 (80000000 00000000) -+ rldic. 0000001cbe991def, 42, 0 => 6477bc0000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 7 => 0077bc0000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 14 => 0003bc0000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 21 => 0000040000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 28 => 6477bc00000072fa (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 35 => 6477bc00000072fa (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 42 => 6477bc00000072fa (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 49 => 6477bc00000072fa (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 56 => 6477bc00000000fa (40000000 00000000) -+ rldic. 0000001cbe991def, 42, 63 => 6477bc0000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 0 => 3bde000000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 7 => 01de000000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 14 => 0002000000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 21 => 3bde000000397d32 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 28 => 3bde000000397d32 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 35 => 3bde000000397d32 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 42 => 3bde000000397d32 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 49 => 3bde000000007d32 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 56 => 3bde000000000032 (40000000 00000000) -+ rldic. 0000001cbe991def, 49, 63 => 3bde000000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 56, 0 => ef00000000000000 (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 7 => 0100000000000000 (40000000 00000000) -+ rldic. 0000001cbe991def, 56, 14 => ef0000001cbe991d (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 21 => ef0000001cbe991d (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 28 => ef0000001cbe991d (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 35 => ef0000001cbe991d (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 42 => ef000000003e991d (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 49 => ef0000000000191d (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 56 => ef0000000000001d (80000000 00000000) -+ rldic. 0000001cbe991def, 56, 63 => ef00000000000001 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 42 => 80000000000c8ef7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 49 => 8000000000000ef7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 56 => 80000000000000f7 (80000000 00000000) -+ rldic. 0000001cbe991def, 63, 63 => 8000000000000001 (80000000 00000000) -+ rldic. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000) -+ rldic. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 0 => ffffffffffffff80 (80000000 00000000) -+ rldic. ffffffffffffffff, 7, 7 => 01ffffffffffff80 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 14 => 0003ffffffffff80 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 21 => 000007ffffffff80 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 28 => 0000000fffffff80 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 35 => 000000001fffff80 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 42 => 00000000003fff80 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 49 => 0000000000007f80 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 56 => 0000000000000080 (40000000 00000000) -+ rldic. ffffffffffffffff, 7, 63 => ffffffffffffff81 (80000000 00000000) -+ rldic. ffffffffffffffff, 14, 0 => ffffffffffffc000 (80000000 00000000) -+ rldic. ffffffffffffffff, 14, 7 => 01ffffffffffc000 (40000000 00000000) -+ rldic. ffffffffffffffff, 14, 14 => 0003ffffffffc000 (40000000 00000000) -+ rldic. ffffffffffffffff, 14, 21 => 000007ffffffc000 (40000000 00000000) -+ rldic. ffffffffffffffff, 14, 28 => 0000000fffffc000 (40000000 00000000) -+ rldic. ffffffffffffffff, 14, 35 => 000000001fffc000 (40000000 00000000) -+ rldic. ffffffffffffffff, 14, 42 => 00000000003fc000 (40000000 00000000) -+ rldic. ffffffffffffffff, 14, 49 => 0000000000004000 (40000000 00000000) -+ rldic. ffffffffffffffff, 14, 56 => ffffffffffffc0ff (80000000 00000000) -+ rldic. ffffffffffffffff, 14, 63 => ffffffffffffc001 (80000000 00000000) -+ rldic. ffffffffffffffff, 21, 0 => ffffffffffe00000 (80000000 00000000) -+ rldic. ffffffffffffffff, 21, 7 => 01ffffffffe00000 (40000000 00000000) -+ rldic. ffffffffffffffff, 21, 14 => 0003ffffffe00000 (40000000 00000000) -+ rldic. ffffffffffffffff, 21, 21 => 000007ffffe00000 (40000000 00000000) -+ rldic. ffffffffffffffff, 21, 28 => 0000000fffe00000 (40000000 00000000) -+ rldic. ffffffffffffffff, 21, 35 => 000000001fe00000 (40000000 00000000) -+ rldic. ffffffffffffffff, 21, 42 => 0000000000200000 (40000000 00000000) -+ rldic. ffffffffffffffff, 21, 49 => ffffffffffe07fff (80000000 00000000) -+ rldic. ffffffffffffffff, 21, 56 => ffffffffffe000ff (80000000 00000000) -+ rldic. ffffffffffffffff, 21, 63 => ffffffffffe00001 (80000000 00000000) -+ rldic. ffffffffffffffff, 28, 0 => fffffffff0000000 (80000000 00000000) -+ rldic. ffffffffffffffff, 28, 7 => 01fffffff0000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 28, 14 => 0003fffff0000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 28, 21 => 000007fff0000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 28, 28 => 0000000ff0000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 28, 35 => 0000000010000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 28, 42 => fffffffff03fffff (80000000 00000000) -+ rldic. ffffffffffffffff, 28, 49 => fffffffff0007fff (80000000 00000000) -+ rldic. ffffffffffffffff, 28, 56 => fffffffff00000ff (80000000 00000000) -+ rldic. ffffffffffffffff, 28, 63 => fffffffff0000001 (80000000 00000000) -+ rldic. ffffffffffffffff, 35, 0 => fffffff800000000 (80000000 00000000) -+ rldic. ffffffffffffffff, 35, 7 => 01fffff800000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 35, 14 => 0003fff800000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 35, 21 => 000007f800000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 35, 28 => 0000000800000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 35, 35 => fffffff81fffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 35, 42 => fffffff8003fffff (80000000 00000000) -+ rldic. ffffffffffffffff, 35, 49 => fffffff800007fff (80000000 00000000) -+ rldic. ffffffffffffffff, 35, 56 => fffffff8000000ff (80000000 00000000) -+ rldic. ffffffffffffffff, 35, 63 => fffffff800000001 (80000000 00000000) -+ rldic. ffffffffffffffff, 42, 0 => fffffc0000000000 (80000000 00000000) -+ rldic. ffffffffffffffff, 42, 7 => 01fffc0000000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 42, 14 => 0003fc0000000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 42, 21 => 0000040000000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 42, 28 => fffffc0fffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 42, 35 => fffffc001fffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 42, 42 => fffffc00003fffff (80000000 00000000) -+ rldic. ffffffffffffffff, 42, 49 => fffffc0000007fff (80000000 00000000) -+ rldic. ffffffffffffffff, 42, 56 => fffffc00000000ff (80000000 00000000) -+ rldic. ffffffffffffffff, 42, 63 => fffffc0000000001 (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 0 => fffe000000000000 (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 7 => 01fe000000000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 49, 14 => 0002000000000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 49, 21 => fffe07ffffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 28 => fffe000fffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 35 => fffe00001fffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 42 => fffe0000003fffff (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 49 => fffe000000007fff (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 56 => fffe0000000000ff (80000000 00000000) -+ rldic. ffffffffffffffff, 49, 63 => fffe000000000001 (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 0 => ff00000000000000 (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 7 => 0100000000000000 (40000000 00000000) -+ rldic. ffffffffffffffff, 56, 14 => ff03ffffffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 21 => ff0007ffffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 28 => ff00000fffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 35 => ff0000001fffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 42 => ff000000003fffff (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 49 => ff00000000007fff (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 56 => ff000000000000ff (80000000 00000000) -+ rldic. ffffffffffffffff, 56, 63 => ff00000000000001 (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 7 => 81ffffffffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 14 => 8003ffffffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 21 => 800007ffffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 28 => 8000000fffffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 35 => 800000001fffffff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 42 => 80000000003fffff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 49 => 8000000000007fff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 56 => 80000000000000ff (80000000 00000000) -+ rldic. ffffffffffffffff, 63, 63 => 8000000000000001 (80000000 00000000) -+ -+ rldicl. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000) -+ rldicl. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000) -+ rldicl. 0000001cbe991def, 7, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 14, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 14, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000) -+ rldicl. 0000001cbe991def, 21, 49 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 21, 56 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 21, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 28, 0 => cbe991def0000001 (80000000 00000000) -+ rldicl. 0000001cbe991def, 28, 7 => 01e991def0000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 14 => 000191def0000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 21 => 000001def0000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 28 => 0000000ef0000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 35 => 0000000010000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 42 => 0000000000000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 49 => 0000000000000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 56 => 0000000000000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 28, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (80000000 00000000) -+ rldicl. 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 14 => 0000ef78000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 21 => 00000778000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 28 => 00000008000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 35 => 00000000000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 42 => 00000000000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 49 => 00000000000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 56 => 00000000000000e5 (40000000 00000000) -+ rldicl. 0000001cbe991def, 35, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 0 => 6477bc00000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 7 => 0077bc00000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 14 => 0003bc00000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 21 => 00000400000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 28 => 00000000000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 35 => 00000000000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 42 => 00000000000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 49 => 00000000000072fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 56 => 00000000000000fa (40000000 00000000) -+ rldicl. 0000001cbe991def, 42, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 49, 0 => 3bde000000397d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 7 => 01de000000397d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 14 => 0002000000397d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 21 => 0000000000397d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 28 => 0000000000397d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 35 => 0000000000397d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 42 => 0000000000397d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 49 => 0000000000007d32 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 56 => 0000000000000032 (40000000 00000000) -+ rldicl. 0000001cbe991def, 49, 63 => 0000000000000000 (20000000 00000000) -+ rldicl. 0000001cbe991def, 56, 0 => ef0000001cbe991d (80000000 00000000) -+ rldicl. 0000001cbe991def, 56, 7 => 010000001cbe991d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 14 => 000000001cbe991d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 21 => 000000001cbe991d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 28 => 000000001cbe991d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 35 => 000000001cbe991d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 42 => 00000000003e991d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 49 => 000000000000191d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 56 => 000000000000001d (40000000 00000000) -+ rldicl. 0000001cbe991def, 56, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldicl. 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 42 => 00000000000c8ef7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 49 => 0000000000000ef7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 56 => 00000000000000f7 (40000000 00000000) -+ rldicl. 0000001cbe991def, 63, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 7, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 7, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 14, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 14, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 21, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 21, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 28, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 28, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 35, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 35, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 42, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 42, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 49, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 49, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 56, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 56, 63 => 0000000000000001 (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000) -+ rldicl. ffffffffffffffff, 63, 7 => 01ffffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 14 => 0003ffffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 21 => 000007ffffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 28 => 0000000fffffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 35 => 000000001fffffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 42 => 00000000003fffff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 49 => 0000000000007fff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 56 => 00000000000000ff (40000000 00000000) -+ rldicl. ffffffffffffffff, 63, 63 => 0000000000000001 (40000000 00000000) -+ -+ rldicr. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 0, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 0, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 0, 21 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 0, 28 => 0000001800000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 0, 35 => 0000001cb0000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 0, 42 => 0000001cbe800000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 0, 49 => 0000001cbe990000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 0, 56 => 0000001cbe991d80 (40000000 00000000) -+ rldicr. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000) -+ rldicr. 0000001cbe991def, 7, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 7, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 7, 14 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 7, 21 => 00000c0000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 7, 28 => 00000e5800000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 7, 35 => 00000e5f40000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 7, 42 => 00000e5f4c800000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (40000000 00000000) -+ rldicr. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 14, 7 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 14, 14 => 0006000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 21 => 00072c0000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 28 => 00072fa000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 35 => 00072fa640000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 42 => 00072fa647600000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 49 => 00072fa6477bc000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 21, 7 => 0300000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 14 => 0396000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 21 => 0397d00000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 28 => 0397d32000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 35 => 0397d323b0000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 42 => 0397d323bde00000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 28, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 7 => cb00000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 14 => cbe8000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 21 => cbe9900000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 28 => cbe991d800000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 35 => cbe991def0000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 42 => cbe991def0000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 49 => cbe991def0000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 56 => cbe991def0000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 7 => f400000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 14 => f4c8000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 21 => f4c8ec0000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 28 => f4c8ef7800000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 35 => f4c8ef7800000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 42 => f4c8ef7800000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 49 => f4c8ef7800000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 56 => f4c8ef7800000080 (80000000 00000000) -+ rldicr. 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (80000000 00000000) -+ rldicr. 0000001cbe991def, 42, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 42, 7 => 6400000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 14 => 6476000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 21 => 6477bc0000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 28 => 6477bc0000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 35 => 6477bc0000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 42 => 6477bc0000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 49 => 6477bc0000004000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 56 => 6477bc0000007280 (40000000 00000000) -+ rldicr. 0000001cbe991def, 42, 63 => 6477bc00000072fa (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 0 => 0000000000000000 (20000000 00000000) -+ rldicr. 0000001cbe991def, 49, 7 => 3b00000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 14 => 3bde000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 21 => 3bde000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 28 => 3bde000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 35 => 3bde000000000000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 42 => 3bde000000200000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 49 => 3bde000000394000 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 56 => 3bde000000397d00 (40000000 00000000) -+ rldicr. 0000001cbe991def, 49, 63 => 3bde000000397d32 (40000000 00000000) -+ rldicr. 0000001cbe991def, 56, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 7 => ef00000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 14 => ef00000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 21 => ef00000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 28 => ef00000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 35 => ef00000010000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 42 => ef0000001ca00000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 49 => ef0000001cbe8000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 56 => ef0000001cbe9900 (80000000 00000000) -+ rldicr. 0000001cbe991def, 56, 63 => ef0000001cbe991d (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 7 => 8000000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 14 => 8000000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 21 => 8000000000000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 28 => 8000000800000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 35 => 8000000e50000000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 42 => 8000000e5f400000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (80000000 00000000) -+ rldicr. 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 7 => ff00000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 14 => fffe000000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 21 => fffffc0000000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 28 => fffffff800000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 35 => fffffffff0000000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 42 => ffffffffffe00000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 49 => ffffffffffffc000 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 56 => ffffffffffffff80 (80000000 00000000) -+ rldicr. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000) -+ -+ rldimi. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000) -+ rldimi. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 28 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 35 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 42 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 49 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 56 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (40000000 00000000) -+ rldimi. 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 56 => 00072fa6477bf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 14, 63 => 00072fa6477bf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (40000000 00000000) -+ rldimi. 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (40000000 00000000) -+ rldimi. 0000001cbe991def, 28, 0 => cbe991defdfb8000 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 7 => cbe991defdfb8000 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 14 => cbe991defdfb8000 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 21 => cbe991defdfb8000 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 28 => cbe991defdfb8000 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 35 => cbe991defdfb8000 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 42 => cbe991defdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 49 => cbe991defdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 56 => cbe991defdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 28, 63 => cbe991defdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (80000000 00000000) -+ rldimi. 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (80000000 00000000) -+ rldimi. 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 28 => 6477bf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 35 => 6477bf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 42 => 6477bf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 49 => 6477bf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 56 => 6477bf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 42, 63 => 6477bf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (40000000 00000000) -+ rldimi. 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (40000000 00000000) -+ rldimi. 0000001cbe991def, 56, 0 => efdfb80000397d32 (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 7 => efdfb80000397d32 (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 14 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 21 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 28 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 35 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 42 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 49 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 56 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 56, 63 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 0 => efdc00001cbe991d (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 7 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 14 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 21 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 28 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 35 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 42 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 49 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 56 => ffffffffffffffff (80000000 00000000) -+ rldimi. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000) -+ -+ sradi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 7 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 14 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 21 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 28 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 35 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 42 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 49 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 56 => 0000000000000000 (20000000 00000000) -+ sradi. 0000000000000000, 63 => 0000000000000000 (20000000 00000000) -+ sradi. 0000001cbe991def, 0 => 0000001cbe991def (40000000 00000000) -+ sradi. 0000001cbe991def, 7 => 00000000397d323b (40000000 00000000) -+ sradi. 0000001cbe991def, 14 => 000000000072fa64 (40000000 00000000) -+ sradi. 0000001cbe991def, 21 => 000000000000e5f4 (40000000 00000000) -+ sradi. 0000001cbe991def, 28 => 00000000000001cb (40000000 00000000) -+ sradi. 0000001cbe991def, 35 => 0000000000000003 (40000000 00000000) -+ sradi. 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000) -+ sradi. 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000) -+ sradi. 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000) -+ sradi. 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000) -+ sradi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000) -+ sradi. ffffffffffffffff, 7 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 14 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 21 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 28 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 35 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 42 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 49 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 56 => ffffffffffffffff (80000000 20000000) -+ sradi. ffffffffffffffff, 63 => ffffffffffffffff (80000000 20000000) -+ -+PPC integer load insns -+ with one register + one 16 bits immediate args with flags update: -+ lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -+ lbz 15, (ffffffffffffffff) => 0000000000000000, 0 (00000000 00000000) -+ lbz 1, (00000000ffffffff) => 00000000000000ff, 0 (00000000 00000000) -+ lbz -7, (00000000be991def) => 000000000000001d, 0 (00000000 00000000) -+ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ -+ lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000) -+ lbzu 15, (ffffffffffffffff) => 0000000000000000, 15 (00000000 00000000) -+ lbzu 1, (00000000ffffffff) => 00000000000000ff, 1 (00000000 00000000) -+ lbzu -7, (00000000be991def) => 000000000000001d, -7 (00000000 00000000) -+ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) -+ -+ lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lha 7, (0000001cbe991def) => ffffffffffffef00, 0 (00000000 00000000) -+ lha 15, (ffffffffffffffff) => ffffffffffffff00, 0 (00000000 00000000) -+ lha 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ lha -7, (00000000be991def) => ffffffffffff991d, 0 (00000000 00000000) -+ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ -+ lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lhau 7, (0000001cbe991def) => ffffffffffffef00, 7 (00000000 00000000) -+ lhau 15, (ffffffffffffffff) => ffffffffffffff00, 15 (00000000 00000000) -+ lhau 1, (00000000ffffffff) => ffffffffffffffff, 1 (00000000 00000000) -+ lhau -7, (00000000be991def) => ffffffffffff991d, -7 (00000000 00000000) -+ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) -+ -+ lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lhz 7, (0000001cbe991def) => 000000000000ef00, 0 (00000000 00000000) -+ lhz 15, (ffffffffffffffff) => 000000000000ff00, 0 (00000000 00000000) -+ lhz 1, (00000000ffffffff) => 000000000000ffff, 0 (00000000 00000000) -+ lhz -7, (00000000be991def) => 000000000000991d, 0 (00000000 00000000) -+ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ -+ lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lhzu 7, (0000001cbe991def) => 000000000000ef00, 7 (00000000 00000000) -+ lhzu 15, (ffffffffffffffff) => 000000000000ff00, 15 (00000000 00000000) -+ lhzu 1, (00000000ffffffff) => 000000000000ffff, 1 (00000000 00000000) -+ lhzu -7, (00000000be991def) => 000000000000991d, -7 (00000000 00000000) -+ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) -+ -+ lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lwz 7, (0000001cbe991def) => 00000000991def00, 0 (00000000 00000000) -+ lwz 15, (ffffffffffffffff) => 00000000ffffff00, 0 (00000000 00000000) -+ lwz 1, (00000000ffffffff) => 00000000ffffffff, 0 (00000000 00000000) -+ lwz -7, (00000000be991def) => 000000001cbe991d, 0 (00000000 00000000) -+ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ -+ lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lwzu 7, (0000001cbe991def) => 00000000991def00, 7 (00000000 00000000) -+ lwzu 15, (ffffffffffffffff) => 00000000ffffff00, 15 (00000000 00000000) -+ lwzu 1, (00000000ffffffff) => 00000000ffffffff, 1 (00000000 00000000) -+ lwzu -7, (00000000be991def) => 000000001cbe991d, -7 (00000000 00000000) -+ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) -+ -+ ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ ld 7, (0000001cbe991def) => be991def00000000, 0 (00000000 00000000) -+ ld 15, (ffffffffffffffff) => ffffffff0000001c, 0 (00000000 00000000) -+ ld 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ ld -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000) -+ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) -+ -+ ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ ldu 7, (0000001cbe991def) => be991def00000000, 4 (00000000 00000000) -+ ldu 15, (ffffffffffffffff) => ffffffff0000001c, 12 (00000000 00000000) -+ ldu 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ ldu -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000) -+ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) -+ -+ lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -+ lwa 15, (ffffffffffffffff) => 000000000000001c, 0 (00000000 00000000) -+ lwa 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ lwa -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000) -+ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) -+ -+PPC integer load insns with two register args: -+ lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lbzx 8, (0000001cbe991def) => 00000000000000ef, 0 (00000000 00000000) -+ lbzx 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000) -+ -+ lbzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lbzux 8, (0000001cbe991def) => 00000000000000ef, 8 (00000000 00000000) -+ lbzux 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000) -+ -+ lhax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lhax 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000) -+ lhax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ -+ lhaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lhaux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000) -+ lhaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000) -+ -+ lhzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lhzx 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000) -+ lhzx 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000) -+ -+ lhzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lhzux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000) -+ lhzux 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000) -+ -+ lwzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lwzx 8, (0000001cbe991def) => 00000000be991def, 0 (00000000 00000000) -+ lwzx 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000) -+ -+ lwzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lwzux 8, (0000001cbe991def) => 00000000be991def, 8 (00000000 00000000) -+ lwzux 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000) -+ -+ ldx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ ldx 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000) -+ ldx 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ -+ ldux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ ldux 8, (0000001cbe991def) => 0000001cbe991def, 8 (00000000 00000000) -+ ldux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000) -+ -+ lwax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lwax 8, (0000001cbe991def) => ffffffffbe991def, 0 (00000000 00000000) -+ lwax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ -+ lwaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -+ lwaux 8, (0000001cbe991def) => ffffffffbe991def, 8 (00000000 00000000) -+ lwaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000) -+ -+PPC integer store insns -+ with one register + one 16 bits immediate args with flags update: -+ stb 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stb 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000) -+ stb ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000) -+ stb 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000) -+ stb 0000001cbe991def, -8 => 00000000000000ef, 0 (00000000 00000000) -+ stb ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000) -+ -+ stbu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stbu 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000) -+ stbu ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000) -+ stbu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000) -+ stbu 0000001cbe991def, -8 => 00000000000000ef, -8 (00000000 00000000) -+ stbu ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000) -+ -+ sth 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ sth 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000) -+ sth ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000) -+ sth 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000) -+ sth 0000001cbe991def, -8 => 0000000000001def, 0 (00000000 00000000) -+ sth ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000) -+ -+ sthu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ sthu 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000) -+ sthu ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000) -+ sthu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000) -+ sthu 0000001cbe991def, -8 => 0000000000001def, -8 (00000000 00000000) -+ sthu ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000) -+ -+ stw 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stw 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000) -+ stw ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000) -+ stw 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000) -+ stw 0000001cbe991def, -8 => 00000000be991def, 0 (00000000 00000000) -+ stw ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000) -+ -+ stwu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stwu 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000) -+ stwu ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000) -+ stwu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000) -+ stwu 0000001cbe991def, -8 => 00000000be991def, -8 (00000000 00000000) -+ stwu ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000) -+ -+ std 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ std 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000) -+ std ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000) -+ std 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000) -+ std 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000) -+ std ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000) -+ -+ stdu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stdu 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000) -+ stdu ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000) -+ stdu 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000) -+ stdu 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000) -+ stdu ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000) -+ -+PPC integer store insns with three register args: -+ stbx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stbx 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000) -+ stbx ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000) -+ -+ stbux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stbux 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000) -+ stbux ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000) -+ -+ sthx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ sthx 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000) -+ sthx ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000) -+ -+ sthux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ sthux 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000) -+ sthux ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000) -+ -+ stwx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stwx 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000) -+ stwx ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000) -+ -+ stwux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stwux 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000) -+ stwux ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000) -+ -+ stdx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stdx 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000) -+ stdx ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000) -+ -+ stdux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000) -+ stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000) -+ stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000) -+ -+PPC integer population count with one register args, no flags: -+ popcntb 0000000000000000 => 0000000000000000 (00000000 00000000) -+ popcntb 0000001cbe991def => 0000000306040407 (00000000 00000000) -+ popcntb ffffffffffffffff => 0808080808080808 (00000000 00000000) -+ -+All done. Tested 210 different instructions -Index: none/tests/ppc64/jm-int.stdout.exp -=================================================================== ---- none/tests/ppc64/jm-int.stdout.exp.orig -+++ none/tests/ppc64/jm-int.stdout.exp -@@ -4549,81 +4549,81 @@ PPC logical insns with special forms wit - PPC integer load insns - with one register + one 16 bits immediate args with flags update: - lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lbz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -- lbz 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000) -- lbz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lbz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -- lbz 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000) -+ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -+ lbz 15, (ffffffffffffffff) => 00000000000000ef, 0 (00000000 00000000) -+ lbz 1, (00000000ffffffff) => 00000000000000ff, 0 (00000000 00000000) -+ lbz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000) -+ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) - - lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lbzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000) -- lbzu 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000) -- lbzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) -- lbzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000) -- lbzu 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000) -+ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000) -+ lbzu 15, (ffffffffffffffff) => 00000000000000ef, 15 (00000000 00000000) -+ lbzu 1, (00000000ffffffff) => 00000000000000ff, 1 (00000000 00000000) -+ lbzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000) -+ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) - - lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lha 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -- lha 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -- lha -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lha -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -- lha 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ lha 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -+ lha 15, (ffffffffffffffff) => ffffffffffffefff, 0 (00000000 00000000) -+ lha 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ lha -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000) -+ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) - - lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lhau 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000) -- lhau 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000) -- lhau -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) -- lhau -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000) -- lhau 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ lhau 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000) -+ lhau 15, (ffffffffffffffff) => ffffffffffffefff, 15 (00000000 00000000) -+ lhau 1, (00000000ffffffff) => ffffffffffffffff, 1 (00000000 00000000) -+ lhau -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000) -+ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) - - lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lhz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -- lhz 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000) -- lhz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lhz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -- lhz 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000) -+ lhz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -+ lhz 15, (ffffffffffffffff) => 000000000000efff, 0 (00000000 00000000) -+ lhz 1, (00000000ffffffff) => 000000000000ffff, 0 (00000000 00000000) -+ lhz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000) -+ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) - - lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lhzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000) -- lhzu 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000) -- lhzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) -- lhzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000) -- lhzu 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000) -+ lhzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000) -+ lhzu 15, (ffffffffffffffff) => 000000000000efff, 15 (00000000 00000000) -+ lhzu 1, (00000000ffffffff) => 000000000000ffff, 1 (00000000 00000000) -+ lhzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000) -+ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) - - lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lwz 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000) -- lwz 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000) -- lwz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lwz -8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000) -- lwz 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000) -+ lwz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -+ lwz 15, (ffffffffffffffff) => 00000000efffffff, 0 (00000000 00000000) -+ lwz 1, (00000000ffffffff) => 00000000ffffffff, 0 (00000000 00000000) -+ lwz -7, (00000000be991def) => 0000000000001cbe, 0 (00000000 00000000) -+ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) - - lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lwzu 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000) -- lwzu 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000) -- lwzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) -- lwzu -8, (0000001cbe991def) => 000000000000001c, -8 (00000000 00000000) -- lwzu 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000) -+ lwzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000) -+ lwzu 15, (ffffffffffffffff) => 00000000efffffff, 15 (00000000 00000000) -+ lwzu 1, (00000000ffffffff) => 00000000ffffffff, 1 (00000000 00000000) -+ lwzu -7, (00000000be991def) => 0000000000001cbe, -7 (00000000 00000000) -+ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000) - - ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- ld 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000) -- ld 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -- ld -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- ld -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000) -- ld 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ ld 7, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000) -+ ld 15, (ffffffffffffffff) => be991defffffffff, 0 (00000000 00000000) -+ ld 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ ld -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000) -+ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) - - ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- ldu 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000) -- ldu 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -- ldu -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- ldu -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000) -- ldu 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ ldu 7, (0000001cbe991def) => 000000000000001c, 4 (00000000 00000000) -+ ldu 15, (ffffffffffffffff) => be991defffffffff, 12 (00000000 00000000) -+ ldu 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ ldu -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000) -+ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) - - lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lwa 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000) -- lwa 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -- lwa -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -- lwa -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000) -- lwa 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000) -+ lwa 15, (ffffffffffffffff) => ffffffffbe991def, 0 (00000000 00000000) -+ lwa 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000) -+ lwa -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000) -+ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000) - - PPC integer load insns with two register args: - lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000) -Index: none/tests/ppc64/test_isa_2_06_part1.stdout.exp -=================================================================== ---- none/tests/ppc64/test_isa_2_06_part1.stdout.exp.orig -+++ none/tests/ppc64/test_isa_2_06_part1.stdout.exp -@@ -66,9 +66,9 @@ xxlandc: 00112233 44556677 8899aabb 9192 - xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280 - - Test ldbrx instruction --ldbrx: 01 23 45 67 89 ab cd (reverse) => ef cd ab 89 67 45 23 01 --ldbrx: 89 ab cd ef 00 11 22 (reverse) => 33 22 11 00 ef cd ab 89 --ldbrx: 00 11 22 33 44 55 66 (reverse) => 77 66 55 44 33 22 11 00 -+ldbrx: 01 23 45 67 89 ab cd ef (reverse) => ef cd ab 89 67 45 23 01 -+ldbrx: 89 ab cd ef 00 11 22 33 (reverse) => 33 22 11 00 ef cd ab 89 -+ldbrx: 00 11 22 33 44 55 66 77 (reverse) => 77 66 55 44 33 22 11 00 - - Test popcntd instruction - popcntd: 0x9182736405504536 => 24 -@@ -138,13 +138,27 @@ ftdiv: 0000000000000000 <=> 000000000000 - ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx) - - Test VSX move instructions --xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394 -- --xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef -- --xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb -- --xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4 -+xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef -+xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942 -+xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4 -+ -+xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef -+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef -+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef -+xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942 -+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942 -+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942 -+xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4 -+xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4 -+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4 -+ -+xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef -+xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942 -+xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4 -+ -+xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef -+xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942 -+xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4 - - Test VSX permute instructions - xxmrghw: -@@ -1028,4 +1042,3 @@ Test VSX scalar integer conversion instr - #14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6 - - --Testcase PASSED -Index: none/tests/ppc64/test_isa_2_07_part2.stdout.exp -=================================================================== ---- none/tests/ppc64/test_isa_2_07_part2.stdout.exp.orig -+++ none/tests/ppc64/test_isa_2_07_part2.stdout.exp -@@ -651,26 +651,26 @@ Test VSX floating point instructions - - - Test VSX vector and scalar single argument instructions --#0: xscvdpspn conv(3ec00000) = 3ec00000 --#1: xscvdpspn conv(42780000) = 42780000 --#2: xscvdpspn conv(00000000) = 00000000 --#3: xscvdpspn conv(7f800000) = 7f800000 --#4: xscvdpspn conv(00000000) = 00000000 --#5: xscvdpspn conv(00000000) = 00000000 --#6: xscvdpspn conv(80000000) = 80000000 --#7: xscvdpspn conv(7f800000) = 7f800000 --#8: xscvdpspn conv(ff800000) = ff800000 --#9: xscvdpspn conv(7fbfffff) = 7fbfffff --#10: xscvdpspn conv(ffbfffff) = ffbfffff --#11: xscvdpspn conv(7fc00000) = 7fc00000 --#12: xscvdpspn conv(ffc00000) = ffc00000 --#13: xscvdpspn conv(80000000) = 80000000 --#14: xscvdpspn conv(c683287b) = c683287b --#15: xscvdpspn conv(49192c2d) = 49192c2d --#16: xscvdpspn conv(49c1288d) = 49c1288d --#17: xscvdpspn conv(418977ad) = 418977ad --#18: xscvdpspn conv(428a5faf) = 428a5faf --#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc -+#0: xscvdpspn conv(3fd8000000000000) = 3ec00000 -+#1: xscvdpspn conv(404f000000000000) = 42780000 -+#2: xscvdpspn conv(0018000000b77501) = 00000000 -+#3: xscvdpspn conv(7fe800000000051b) = 7f800000 -+#4: xscvdpspn conv(0123214569900000) = 00000000 -+#5: xscvdpspn conv(0000000000000000) = 00000000 -+#6: xscvdpspn conv(8000000000000000) = 80000000 -+#7: xscvdpspn conv(7ff0000000000000) = 7f800000 -+#8: xscvdpspn conv(fff0000000000000) = ff800000 -+#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff -+#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff -+#11: xscvdpspn conv(7ff8000000000000) = 7fc00000 -+#12: xscvdpspn conv(fff8000000000000) = ffc00000 -+#13: xscvdpspn conv(8008340000078000) = 80000000 -+#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b -+#15: xscvdpspn conv(41232585a9900000) = 49192c2d -+#16: xscvdpspn conv(41382511a2000000) = 49c1288d -+#17: xscvdpspn conv(40312ef5a9300000) = 418977ad -+#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf -+#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc - - #0: xscvspdpn conv(3ec00000) = 3fd8000000000000 - #1: xscvspdpn conv(42780000) = 404f000000000000 -@@ -783,23 +783,15 @@ Test VSX logic instructions - #2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988 - - Test VSX scalar integer conversion instructions --#0: xscvsxdsp 80000001 => c3e0000000000000 --#1: xscvsxdsp 89abcdef => c3dd950c80000000 --#2: xscvsxdsp 00112233 => 4331223380000000 --#3: xscvsxdsp 74556677 => 43dd1559a0000000 --#4: xscvsxdsp 00001abb => 42babb89a0000000 --#5: xscvsxdsp 00000001 => 41f89abce0000000 --#6: xscvsxdsp 31929394 => 43c8c949c0000000 --#7: xscvsxdsp a1a2a3a4 => c3d7975720000000 -- --#0: xscvuxdsp 80000001 => 43e0000000000000 --#1: xscvuxdsp 89abcdef => 43e13579c0000000 --#2: xscvuxdsp 00112233 => 4331223380000000 --#3: xscvuxdsp 74556677 => 43dd1559a0000000 --#4: xscvuxdsp 00001abb => 42babb89a0000000 --#5: xscvuxdsp 00000001 => 41f89abce0000000 --#6: xscvuxdsp 31929394 => 43c8c949c0000000 --#7: xscvuxdsp a1a2a3a4 => 43e4345480000000 -+#0: xscvsxdsp 0102030405060708 => 4370203040000000 -+#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000 -+#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000 -+#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000 -+ -+#0: xscvuxdsp 0102030405060708 => 4370203040000000 -+#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000 -+#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000 -+#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000 - - - Test VSX load/store dp to sp instructions -@@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d - stxsspx: 40514bf5e0000000 ==> 428a5faf - - --stxsiwx: 80000001 ==> 80000001 --stxsiwx: 89abcdef ==> 89abcdef --stxsiwx: 00112233 ==> 00112233 --stxsiwx: 74556677 ==> 74556677 --stxsiwx: 00001abb ==> 00001abb --stxsiwx: 00000001 ==> 00000001 --stxsiwx: 31929394 ==> 31929394 --stxsiwx: a1a2a3a4 ==> a1a2a3a4 -+stxsiwx: 3ec00000 ==> 3ec00000 -+stxsiwx: 7f800000 ==> 7f800000 -+stxsiwx: 80000000 ==> 80000000 -+stxsiwx: 7fbfffff ==> 7fbfffff -+stxsiwx: ffc00000 ==> ffc00000 -+stxsiwx: 49192c2d ==> 49192c2d -+stxsiwx: 428a5faf ==> 428a5faf - - - lxsiwax: 80000001 ==> ffffffff80000001 -@@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394 - lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4 - - --lxsiwzx: 89abcdef ==> 00000000abcdef00 --lxsiwzx: 00112233 ==> 0000000011223374 --lxsiwzx: 74556677 ==> 0000000055667700 --lxsiwzx: 00001abb ==> 00000000001abb00 --lxsiwzx: 00000001 ==> 0000000000000131 --lxsiwzx: 31929394 ==> 00000000929394a1 --lxsiwzx: a1a2a3a4 ==> 00000000a2a3a400 --lxsiwzx: 00000000 ==> 0000000000000010 -+lxsiwzx: 89abcdef ==> 0000000089abcdef -+lxsiwzx: 00112233 ==> 0000000000112233 -+lxsiwzx: 74556677 ==> 0000000074556677 -+lxsiwzx: 00001abb ==> 0000000000001abb -+lxsiwzx: 00000001 ==> 0000000000000001 -+lxsiwzx: 31929394 ==> 0000000031929394 -+lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4 - - - lxsspx: 3ec00000 ==> 3fd8000000000000 -Index: none/tests/ppc64/test_isa_2_07_part1.c -=================================================================== ---- none/tests/ppc64/test_isa_2_07_part1.c.orig -+++ none/tests/ppc64/test_isa_2_07_part1.c -@@ -135,6 +135,12 @@ typedef uint64_t HWord_t; - #define ZERO 0ULL - #endif /* __powerpc64__ */ - -+#ifdef VGP_ppc64le_linux -+#define isLE 1 -+#else -+#define isLE 0 -+#endif -+ - typedef uint64_t Word_t; - - enum { -@@ -1116,7 +1122,10 @@ static void mfvs(const char* name, test_ - - for (i=0; i < NB_VDARGS; i++) { - r14 = ZERO; -- vec_inA = (vector unsigned long long){ vdargs[i], 0ULL }; -+ if (isLE) -+ vec_inA = (vector unsigned long long){ 0ULL, vdargs[i] }; -+ else -+ vec_inA = (vector unsigned long long){ vdargs[i], 0ULL }; - - (*func)(); - result = r14; -@@ -1139,6 +1148,8 @@ static void mtvs(const char* name, test_ - - (*func)(); - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - printf("%s: %016llx => %016llx\n", name, vdargs[i], *dst); - } - } -@@ -1154,13 +1165,16 @@ static void mtvs2s(const char* name, tes - for (i=0; i < NB_VDARGS; i++) { - // Only the lower half of the vdarg doubleword arg will be used as input by mtvsrwa - unsigned int * src = (unsigned int *)&vdargs[i]; -- src++; -+ if (!isLE) -+ src++; - r14 = vdargs[i]; - vec_out = (vector unsigned long long){ 0ULL, 0ULL }; - - (*func)(); - // Only doubleword 0 is used in output - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - printf("%s: %08x => %016llx\n", name, *src, *dst); - } - } -@@ -1222,16 +1236,27 @@ static void test_av_dint_two_args (const - unsigned int * dst_int; - int i,j; - int family = test_flags & PPC_FAMILY; -- int is_vpkudum; -+ int is_vpkudum, is_vpmsumd; - if (strcmp(name, "vpkudum") == 0) - is_vpkudum = 1; - else - is_vpkudum = 0; - -+ if (strcmp(name, "vpmsumd") == 0) -+ is_vpmsumd = 1; -+ else -+ is_vpmsumd = 0; -+ - for (i = 0; i < NB_VDARGS; i+=2) { -- vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] }; -+ if (isLE && family == PPC_ALTIVECQ) -+ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] }; -+ else -+ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] }; - for (j = 0; j < NB_VDARGS; j+=2) { -- vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] }; -+ if (isLE && family == PPC_ALTIVECQ) -+ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] }; -+ else -+ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] }; - vec_out = (vector unsigned long long){ 0,0 }; - - (*func)(); -@@ -1244,12 +1269,32 @@ static void test_av_dint_two_args (const - printf("Inputs: %08llx %08llx %08llx %08llx\n", vdargs[i] & 0x00000000ffffffffULL, - vdargs[i+1] & 0x00000000ffffffffULL, vdargs[j] & 0x00000000ffffffffULL, - vdargs[j+1] & 0x00000000ffffffffULL); -- printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1], -- dst_int[2], dst_int[3]); -+ if (isLE) -+ printf(" Output: %08x %08x %08x %08x\n", dst_int[2], dst_int[3], -+ dst_int[0], dst_int[1]); -+ else -+ printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1], -+ dst_int[2], dst_int[3]); -+ } else if (is_vpmsumd) { -+ printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]); -+ if (isLE) -+ printf(" ==> %016llx\n", dst[1]); -+ else -+ printf(" ==> %016llx\n", dst[0]); -+ printf("\t%016llx @@ %016llx ", vdargs[i+1], vdargs[j+1]); -+ if (isLE) -+ printf(" ==> %016llx\n", dst[0]); -+ else -+ printf(" ==> %016llx\n", dst[1]); - } else if (family == PPC_ALTIVECQ) { -- printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n", -- vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], -- dst[0], dst[1]); -+ if (isLE) -+ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n", -+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], -+ dst[1], dst[0]); -+ else -+ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n", -+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], -+ dst[0], dst[1]); - } else { - printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]); - printf(" ==> %016llx\n", dst[0]); -@@ -1311,9 +1356,15 @@ static void test_av_bcd (const char* nam - int i, j; - - for (i = 0; i < NUM_VBCD_VALS; i+=2) { -- vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i +1 ] }; -+ if (isLE) -+ vec_inA = (vector unsigned long long){ vbcd_args[i+1], vbcd_args[i] }; -+ else -+ vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i+1] }; - for (j = 0; j < NUM_VBCD_VALS; j+=2) { -- vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j +1 ] }; -+ if (isLE) -+ vec_inB = (vector unsigned long long){ vbcd_args[j+1], vbcd_args[j] }; -+ else -+ vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j+1] }; - vec_out = (vector unsigned long long){ 0, 0 }; - - for (PS_bit = 0; PS_bit < 2; PS_bit++) { -@@ -1323,7 +1374,10 @@ static void test_av_bcd (const char* nam - printf("%016llx || %016llx @@ %016llx || %016llx", - vbcd_args[i], vbcd_args[i + 1], - vbcd_args[j], vbcd_args[j + 1]); -- printf(" ==> %016llx || %016llx\n", dst[0], dst[1]); -+ if (isLE) -+ printf(" ==> %016llx || %016llx\n", dst[1], dst[0]); -+ else -+ printf(" ==> %016llx || %016llx\n", dst[0], dst[1]); - } - } - } -@@ -1349,8 +1403,12 @@ static void test_av_dint_to_int_two_args - printf("%016llx, %016llx @@ %016llx, %016llx ", - vdargs_x[i], vdargs_x[i+1], - vdargs_x[j], vdargs_x[j+1]); -- printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1], -- dst_int[2], dst_int[3]); -+ if (isLE) -+ printf(" ==> %08x %08x %08x %08x\n", dst_int[2], dst_int[3], -+ dst_int[0], dst_int[1]); -+ else -+ printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1], -+ dst_int[2], dst_int[3]); - } - } - } -@@ -1365,16 +1423,26 @@ static void test_av_wint_two_args_dres ( - int i,j; - - for (i = 0; i < NB_VWARGS; i+=4) { -- vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] }; -+ if (isLE) -+ vec_inA_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] }; -+ else -+ vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] }; - for (j = 0; j < NB_VWARGS; j+=4) { -- vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] }; -+ if (isLE) -+ vec_inB_wd = (vector unsigned int){ vwargs[j+3], vwargs[j+2], vwargs[j+1], vwargs[j] }; -+ else -+ vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] }; - vec_out = (vector unsigned long long){ 0, 0 }; - - (*func)(); - dst = (unsigned long long *)&vec_out; - printf("%s: ", name); -- printf("%08x %08x %08x %08x ==> %016llx %016llx\n", -- vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]); -+ if (isLE) -+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n", -+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]); -+ else -+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n", -+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]); - } - } - } -@@ -1387,14 +1455,21 @@ static void test_av_wint_one_arg_dres (c - unsigned long long * dst; - int i; - for (i = 0; i < NB_VWARGS; i+=4) { -- vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] }; -+ if (isLE) -+ vec_inB_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] }; -+ else -+ vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] }; - vec_out = (vector unsigned long long){ 0, 0 }; - - (*func)(); - dst = (unsigned long long *)&vec_out; - printf("%s: ", name); -- printf("%08x %08x %08x %08x ==> %016llx %016llx\n", -- vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]); -+ if (isLE) -+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n", -+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]); -+ else -+ printf("%08x %08x %08x %08x ==> %016llx %016llx\n", -+ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]); - } - } - -@@ -1556,28 +1631,52 @@ static void test_av_dint_three_args (con - 0xf000000000000000ULL, 0xf000000000000001ULL - }; - for (i = 0; i < NB_VDARGS; i+=2) { -- vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] }; -+ if (isLE) -+ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] }; -+ else -+ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] }; - for (j = 0; j < NB_VDARGS; j+=2) { -- vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] }; -+ if (isLE) -+ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] }; -+ else -+ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] }; - for (k = 0; k < 4; k+=2) { -- if (family == PPC_ALTIVECQ) -- vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] }; -- else -- vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] }; -+ if (family == PPC_ALTIVECQ) { -+ if (isLE) -+ vec_inC = (vector unsigned long long){ cin_vals[k+1], cin_vals[k] }; -+ else -+ vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] }; -+ } else { -+ if (isLE) -+ vec_inC = (vector unsigned long long){ vdargs[k+1], vdargs[k] }; -+ else -+ vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] }; -+ } - vec_out = (vector unsigned long long){ 0,0 }; - - (*func)(); - dst = (unsigned long long*)&vec_out; - printf("%s: ", name); - if (family == PPC_ALTIVECQ) { -- printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n", -- vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1], -- dst[0], dst[1]); -+ if (isLE) -+ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n", -+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1], -+ dst[1], dst[0]); -+ else -+ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n", -+ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1], -+ dst[0], dst[1]); - } else { - printf("%016llx @@ %016llx @@ %016llx ", vdargs[i], vdargs[j], vdargs[k]); -- printf(" ==> %016llx\n", dst[0]); -+ if (isLE) -+ printf(" ==> %016llx\n", dst[1]); -+ else -+ printf(" ==> %016llx\n", dst[0]); - printf("\t%016llx @@ %016llx @@ %016llx ", vdargs[i+1], vdargs[j+1], vdargs[k+1]); -- printf(" ==> %016llx\n", dst[1]); -+ if (isLE) -+ printf(" ==> %016llx\n", dst[0]); -+ else -+ printf(" ==> %016llx\n", dst[1]); - } - } - } -Index: none/tests/ppc64/Makefile.am -=================================================================== ---- none/tests/ppc64/Makefile.am.orig -+++ none/tests/ppc64/Makefile.am -@@ -4,20 +4,20 @@ include $(top_srcdir)/Makefile.tool-test - dist_noinst_SCRIPTS = filter_stderr - - EXTRA_DIST = \ -- jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \ -- jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \ -- jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \ -+ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \ -+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \ -+ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \ - jm-vmx.vgtest \ - jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \ - lsw.stderr.exp lsw.stdout.exp lsw.vgtest \ -- std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \ -- round.stderr.exp round.stdout.exp round.vgtest \ -+ std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp std_reg_imm.stdout.exp-LE \ -+ round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix \ - twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \ - tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \ - opcodes.h \ - power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \ - power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \ -- test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \ -+ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest test_isa_2_06_part1.stdout.exp-LE \ - test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \ - test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \ - test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \ -@@ -83,33 +83,45 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS - test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \ - @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) - --test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \ -+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \ - @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) - - jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \ - @FLAG_M64@ $(ALTIVEC_FLAG) - --test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_DFP) - --test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_DFP) --test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_DFP) - --test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_DFP) - --test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_DFP) - --test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07) - --test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07) - --test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07) --test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07) -+ -+test_isa_2_06_part3_LDADD = -lm -+test_dfp1_LDADD = -lm -+test_dfp2_LDADD = -lm -+test_dfp3_LDADD = -lm -+test_dfp4_LDADD = -lm -+test_dfp5_LDADD = -lm -+test_isa_2_07_part1_LDADD = -lm -+test_isa_2_07_part2_LDADD = -lm -+test_tm_LDADD = -lm -+test_touch_tm_LDADD = -lm -+ -Index: none/tests/amd64/xadd.c -=================================================================== ---- none/tests/amd64/xadd.c.orig -+++ none/tests/amd64/xadd.c -@@ -9,7 +9,7 @@ - #undef PLAT_x86_linux - #undef PLAT_amd64_linux - #undef PLAT_ppc32_linux --#undef PLAT_ppc64_linux -+#undef PLAT_ppc64be_linux - - #if defined(__i386__) - # define PLAT_x86_linux 1 -Index: none/tests/ppc32/Makefile.am -=================================================================== ---- none/tests/ppc32/Makefile.am.orig -+++ none/tests/ppc32/Makefile.am -@@ -11,13 +11,13 @@ EXTRA_DIST = \ - ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \ - lsw.stderr.exp lsw.stdout.exp lsw.vgtest \ - jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \ -- jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \ -+ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \ - jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \ - jm-vmx.vgtest \ - jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \ - mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \ - mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \ -- round.stderr.exp round.stdout.exp round.vgtest \ -+ round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix\ - test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \ - test_fx.vgtest \ - test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \ -@@ -109,29 +109,41 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS - test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \ - @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) - --test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \ -+test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \ - @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) - --test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_DFP) --test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_DFP) --test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_DFP) - --test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_DFP) - --test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \ -+test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_DFP) - --test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07) - --test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07) - --test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07) --test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \ -+test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \ - @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07) -+ -+test_isa_2_06_part3_LDADD = -lm -+test_dfp1_LDADD = -lm -+test_dfp2_LDADD = -lm -+test_dfp3_LDADD = -lm -+test_dfp4_LDADD = -lm -+test_dfp5_LDADD = -lm -+test_isa_2_07_part1_LDADD = -lm -+test_isa_2_07_part2_LDADD = -lm -+test_tm_LDADD = -lm -+test_touch_tm_LDADD = -lm -+ -Index: none/tests/ppc32/jm-vmx.stdout.exp -=================================================================== ---- none/tests/ppc32/jm-vmx.stdout.exp.orig -+++ none/tests/ppc32/jm-vmx.stdout.exp -@@ -1407,43 +1407,43 @@ Altivec integer special insns: - vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14 - vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000) - -- lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000) -- lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000) -- lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000) -- lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000) -- lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000) -- lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000) -- lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000) -- lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000) -- lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000) -- lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000) -- lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000) -- lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000) -- lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000) -- lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000) -- lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000) -- lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000) -- lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000) -- lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000) -- -- lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000) -- lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000) -- lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000) -- lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000) -- lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000) -- lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000) -- lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000) -- lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000) -- lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000) -- lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000) -- lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000) -- lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000) -- lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000) -- lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000) -- lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000) -- lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000) -- lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000) -- lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000) -+ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000) -+ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000) -+ lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000) -+ lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000) -+ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000) -+ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000) -+ lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000) -+ lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000) -+ lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000) -+ lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000) -+ lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000) -+ lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000) -+ lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000) -+ lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000) -+ lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000) -+ lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000) -+ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000) -+ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000) -+ -+ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000) -+ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000) -+ lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000) -+ lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000) -+ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000) -+ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000) -+ lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000) -+ lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000) -+ lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000) -+ lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000) -+ lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000) -+ lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000) -+ lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000) -+ lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000) -+ lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000) -+ lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000) -+ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000) -+ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000) - - Altivec load insns with two register args: - lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000) -@@ -3451,18 +3451,18 @@ Altivec float special insns: - vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000) - vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000) - vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000) -- vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000) -- vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000) -- vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000) -- vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000) -+ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000) -+ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000) -+ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000) -+ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000) - vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000) - vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000) - vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000) - vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000) -- vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000) -- vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000) -- vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000) -- vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000) -+ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000) -+ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000) -+ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000) -+ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000) - - vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000) - vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000) -@@ -3500,27 +3500,27 @@ Altivec float special insns: - vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000) - vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000) - vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000) -- vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000) -- vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000) -- vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000) -- vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000) -+ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000) -+ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000) -+ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000) -+ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000) - vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000) - vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000) - vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000) - vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000) -- vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000) -- vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000) -- vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000) -- vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000) -+ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000) -+ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000) -+ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000) -+ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000) - - vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000) -- vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000) -+ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000) - vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000) -@@ -3537,10 +3537,10 @@ Altivec float special insns: - vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000) -- vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000) -- vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000) -- vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000) -+ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000) -+ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000) - vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000) -@@ -3549,18 +3549,18 @@ Altivec float special insns: - vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - - vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000) -@@ -3598,17 +3598,17 @@ Altivec float special insns: - vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) - vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000) -- vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) -+ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) - - All done. Tested 165 different instructions -Index: none/tests/ppc32/round.stdout.exp-RM-fix -=================================================================== ---- /dev/null -+++ none/tests/ppc32/round.stdout.exp-RM-fix -@@ -0,0 +1,2335 @@ -+-------------------------- test denormalized convert -------------------------- -+near:PASSED:(double)(0x1p-148 ) = 0x1.cp-149 -+near:PASSED:(double)(0x1p-149 ) = 0x1.4p-149 -+zero:PASSED:(double)(0x1p-149 ) = 0x1.cp-149 -+zero:PASSED:(double)(0x1p-149 ) = 0x1.4p-149 -++inf:PASSED:(double)(0x1p-148 ) = 0x1.cp-149 -++inf:PASSED:(double)(0x1p-148 ) = 0x1.4p-149 -+-inf:PASSED:(double)(0x1p-149 ) = 0x1.cp-149 -+-inf:PASSED:(double)(0x1p-149 ) = 0x1.4p-149 -+-------------------------- test normalized convert -------------------------- -+near:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126 -+near:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126 -+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126 -+zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126 -++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126 -++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000028p-126 -+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126 -+-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126 -+-------------------------- test (float)int convert -------------------------- -+near:PASSED:(float)( int) 67047421 = 67047420.0 -+near:PASSED:(float)( int) 67047423 = 67047424.0 -+zero:PASSED:(float)( int) 67047421 = 67047420.0 -+zero:PASSED:(float)( int) 67047423 = 67047420.0 -++inf:PASSED:(float)( int) 67047421 = 67047424.0 -++inf:PASSED:(float)( int) 67047423 = 67047424.0 -+-inf:PASSED:(float)( int) 67047421 = 67047420.0 -+-inf:PASSED:(float)( int) 67047423 = 67047420.0 -+near:PASSED:(float)( int)-67047421 = -67047420.0 -+near:PASSED:(float)( int)-67047423 = -67047424.0 -+zero:PASSED:(float)( int)-67047421 = -67047420.0 -+zero:PASSED:(float)( int)-67047423 = -67047420.0 -++inf:PASSED:(float)( int)-67047421 = -67047420.0 -++inf:PASSED:(float)( int)-67047423 = -67047420.0 -+-inf:PASSED:(float)( int)-67047421 = -67047424.0 -+-inf:PASSED:(float)( int)-67047423 = -67047424.0 -+-------------------------- test (float)int convert -------------------------- -+near:PASSED:(float)( int) 67047421 = 67047420.0 -+near:PASSED:(float)( int) 67047423 = 67047424.0 -+zero:PASSED:(float)( int) 67047421 = 67047420.0 -+zero:PASSED:(float)( int) 67047423 = 67047420.0 -++inf:PASSED:(float)( int) 67047421 = 67047424.0 -++inf:PASSED:(float)( int) 67047423 = 67047424.0 -+-inf:PASSED:(float)( int) 67047421 = 67047420.0 -+-inf:PASSED:(float)( int) 67047423 = 67047420.0 -+near:PASSED:(float)( int)-67047421 = -67047420.0 -+near:PASSED:(float)( int)-67047423 = -67047424.0 -+zero:PASSED:(float)( int)-67047421 = -67047420.0 -+zero:PASSED:(float)( int)-67047423 = -67047420.0 -++inf:PASSED:(float)( int)-67047421 = -67047420.0 -++inf:PASSED:(float)( int)-67047423 = -67047420.0 -+-inf:PASSED:(float)( int)-67047421 = -67047424.0 -+-inf:PASSED:(float)( int)-67047423 = -67047424.0 -+-------------------------- test rounding of float operators without guard bits -------------------------- -+near:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149 -+near:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148 -+near:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149 -+near:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148 -+zero:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149 -+zero:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149 -+zero:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149 -+zero:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149 -++inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149 -++inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149 -++inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-148 -++inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148 -+-inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-148 -+-inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148 -+-inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149 -+-inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149 -+near:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149 -+near:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148 -+near:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149 -+near:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148 -+zero:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149 -+zero:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149 -+zero:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149 -+zero:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149 -++inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149 -++inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149 -++inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-148 -++inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148 -+-inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-148 -+-inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148 -+-inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149 -+-inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149 -+near:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149 -+near:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148 -+near:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149 -+near:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148 -+zero:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149 -+zero:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149 -+zero:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149 -+zero:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149 -++inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149 -++inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149 -++inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-148 -++inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148 -+-inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-148 -+-inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148 -+-inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149 -+-inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149 -+near:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149 -+near:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148 -+near:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149 -+near:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148 -+zero:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149 -+zero:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149 -+zero:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149 -+zero:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149 -++inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149 -++inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149 -++inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-148 -++inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148 -+-inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-148 -+-inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148 -+-inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149 -+-inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149 -+-------------------------- test rounding of float operators with guard bits -------------------------- -+near:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0 -+near:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0 -+near:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0 -+near:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0 -+near:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0 -+near:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0 -+zero:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0 -+zero:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0 -+zero:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0 -++inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0 -++inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0 -+-inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0 -+-inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0 -+near:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0 -+near:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0 -+near:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0 -+zero:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0 -+zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0 -++inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0 -++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0 -+-inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 -+near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 -+near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0 -+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0 -+near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 -+near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 -+near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0 -+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0 -+near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0 -++inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0 -+-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+near:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+near:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+near:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+near:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+near:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+near:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0 -+near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+near:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+near:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+near:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+near:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+near:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+near:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+near:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148 -+near:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0 -+near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148 -+near:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+zero:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0 -+zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+zero:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+zero:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0 -+zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0 -++inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0 -++inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -++inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -+-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec6p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -+-inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92494p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+-inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f8p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+-inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0 -+-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148 -+-inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 -+-inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0 -+-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -+-inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -+near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -+near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -+near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -+near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0 -+-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+-------------------------- test rounding of double operators with guard bits -------------------------- -+near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0 -+near:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0 -+zero:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0 -++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0 -+-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0 -+near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0 -+near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0 -+zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0 -+zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0 -++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000002p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1.0000000000001p+0 -++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000002p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0 -+-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0 -+near:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -+near:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0 -+near:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -+near:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -+near:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -+near:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -+near:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -+near:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0 -+near:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -+near:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0 -+near:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -+near:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -+near:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -+near:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -+near:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -+near:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0 -+near:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -+near:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0 -+near:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -+near:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -+near:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -+near:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -+near:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -+near:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0 -+near:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -+near:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0 -+near:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -+near:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -+near:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -+near:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -+near:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -+near:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0 -+zero:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -+zero:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0 -+zero:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -+zero:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -+zero:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -+zero:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0 -+zero:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -+zero:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -+zero:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -+zero:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0 -+zero:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -+zero:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -+zero:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0 -+zero:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -+zero:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -+zero:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -+zero:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -+zero:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0 -+zero:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -+zero:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -+zero:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -+zero:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0 -+zero:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -+zero:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -+zero:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -+zero:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0 -+zero:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -+zero:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -+zero:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0 -+zero:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -+zero:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -+zero:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -++inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -++inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0 -++inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -++inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -++inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -++inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0 -++inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -++inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -++inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -++inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0 -++inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -++inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -++inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0 -++inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -++inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -++inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -++inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -++inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -++inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -++inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -++inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0 -++inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -++inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -++inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0 -++inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -++inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -++inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -++inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0 -++inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -++inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -++inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -++inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0 -+-inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0 -+-inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0 -+-inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0 -+-inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0 -+-inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0 -+-inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0 -+-inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0 -+-inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0 -+-inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0 -+-inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000bp+0 -+-inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000cp+0 -+-inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0 -+-inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0 -+-inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0 -+-inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0 -+-inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0 -+-inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0 -+-inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0 -+-inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0 -+-inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0 -+-inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0 -+-inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0 -+-inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0 -+-inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0 -+-inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0 -+-inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0 -+-inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0 -+-inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0 -+-inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0 -+-inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0 -+-inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0 -+-inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0 -+-62/62 -+near:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -+near:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0 -+-66/62 -+near:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0 -+-100/62 -+near:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0 -+near:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0 -+-102/62 -+near:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0 -+-106/62 -+near:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0 -+-108/62 -+near:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0 -+-108/108 -+near:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -+near:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0 -+-114/62 -+near:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0 -+-116/62 -+near:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0 -+near:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022 -+-118/62 -+near:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0 -+-90/62 -+near:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0 -+-92/62 -+near:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0 -+62/62 -+near:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -+near:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0 -+66/62 -+near:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0 -+100/62 -+near:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0 -+near:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0 -+102/62 -+near:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0 -+106/62 -+near:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0 -+108/62 -+near:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0 -+108/108 -+near:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -+near:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0 -+114/62 -+near:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0 -+116/62 -+near:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0 -+near:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022 -+118/62 -+near:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0 -+90/62 -+near:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0 -+92/62 -+near:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0 -+-62/62 -+zero:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -+zero:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0 -+-66/62 -+zero:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0 -+-100/62 -+zero:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0 -+zero:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0 -+-102/62 -+zero:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0 -+-106/62 -+zero:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0 -+-108/62 -+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0 -+-108/108 -+zero:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -+zero:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0 -+-114/62 -+zero:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0 -+-116/62 -+zero:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0 -+zero:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022 -+-118/62 -+zero:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0 -+-90/62 -+zero:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0 -+-92/62 -+zero:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0 -+62/62 -+zero:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -+zero:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0 -+66/62 -+zero:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0 -+100/62 -+zero:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0 -+zero:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0 -+102/62 -+zero:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0 -+106/62 -+zero:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0 -+108/62 -+zero:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0 -+108/108 -+zero:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -+zero:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0 -+114/62 -+zero:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0 -+116/62 -+zero:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0 -+zero:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022 -+118/62 -+zero:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0 -+90/62 -+zero:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0 -+92/62 -+zero:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0 -+-62/62 -++inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -++inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0 -+-66/62 -++inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0 -+-100/62 -++inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0 -++inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0 -+-102/62 -++inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0 -+-106/62 -++inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0 -+-108/62 -++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0 -+-108/108 -++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -++inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0 -+-114/62 -++inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0 -+-116/62 -++inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0 -++inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022 -+-118/62 -++inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0 -+-90/62 -++inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0 -+-92/62 -++inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0 -+62/62 -++inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -++inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421085p+0 -+66/62 -++inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842109p+0 -+100/62 -++inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cfp+0 -++inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022 -+102/62 -++inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0 -+106/62 -++inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0 -+108/62 -++inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0 -+108/108 -++inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -++inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce8p+0 -+114/62 -++inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6cp+0 -+116/62 -++inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdfp+0 -++inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022 -+118/62 -++inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0 -+90/62 -++inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0 -+92/62 -++inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0 -+-62/62 -+-inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0 -+-64/62 -+-inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421085p+0 -+-66/62 -+-inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842109p+0 -+-100/62 -+-inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cfp+0 -+-inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022 -+-102/62 -+-inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0 -+-106/62 -+-inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0 -+-108/62 -+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0 -+-108/108 -+-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0 -+-112/62 -+-inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce8p+0 -+-114/62 -+-inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6cp+0 -+-116/62 -+-inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdfp+0 -+-inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022 -+-118/62 -+-inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0 -+-90/62 -+-inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0 -+-92/62 -+-inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0 -+62/62 -+-inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0 -+64/62 -+-inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0 -+66/62 -+-inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0 -+100/62 -+-inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0 -+-inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0 -+102/62 -+-inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0 -+106/62 -+-inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0 -+108/62 -+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0 -+108/108 -+-inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0 -+112/62 -+-inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0 -+114/62 -+-inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0 -+116/62 -+-inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0 -+-inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022 -+118/62 -+-inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0 -+90/62 -+-inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0 -+92/62 -+-inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0 -+near:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -++inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -++inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -++inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -++inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -++inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+-inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+-inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+-inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+-inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+-inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+-inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -++inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -++inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -++inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -++inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -++inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+-inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+-inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+-inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+-inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+-inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+-inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0 -++inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0 -++inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -++inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0 -++inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -++inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+-inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+-inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0 -+-inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+-inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+-inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+near:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+near:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+near:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+near:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+near:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+near:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+near:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+near:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+near:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+near:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+near:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+near:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+near:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+near:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+near:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+near:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+near:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+near:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+near:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -+near:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+near:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+near:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+near:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+near:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+near:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+near:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+near:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -+near:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+near:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+near:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+near:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+zero:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -+zero:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+zero:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+zero:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+zero:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+zero:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -+zero:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+zero:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+zero:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+zero:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+zero:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+zero:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+zero:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+zero:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -+zero:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+zero:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+zero:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+zero:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+zero:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+zero:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+zero:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+zero:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+zero:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+zero:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+zero:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+zero:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+zero:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+zero:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+zero:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+zero:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+zero:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+zero:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0 -++inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -++inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -++inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -++inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -++inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0 -++inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -++inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -++inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -++inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -++inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -++inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -++inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -++inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0 -++inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -++inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -++inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -++inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -++inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -++inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0 -++inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -++inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -++inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -++inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -++inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -++inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -++inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -++inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0 -++inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -++inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -++inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -++inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0 -+-inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0 -+-inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0 -+-inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0 -+-inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0 -+-inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0 -+-inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0 -+-inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0 -+-inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0 -+-inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0 -+-inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0 -+-inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0 -+-inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0 -+-inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0 -+-inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0 -+-inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0 -+-inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0 -+-inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0 -+-inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0 -+-inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0 -+-inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0 -+-inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0 -+-inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0 -+-inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0 -+-inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0 -+-inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0 -+near:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1 -+near:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0 -+near:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0 -+near:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1 -+near:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0 -+near:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0 -+near:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1 -+near:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0 -+near:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1 -+near:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1 -+near:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0 -+near:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1 -+near:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1 -+near:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0 -+zero:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1 -+zero:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0 -+zero:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0 -+zero:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1 -+zero:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0 -+zero:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0 -+zero:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1 -+zero:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0 -+zero:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1 -+zero:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1 -+zero:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0 -+zero:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1 -+zero:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1 -+zero:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0 -++inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049fp-1 -++inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6ep+0 -++inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3cp+0 -++inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0938p-1 -++inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b3p+0 -++inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7484p+0 -++inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7dp-1 -++inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0 -++inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1 -++inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1 -++inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0 -++inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1 -++inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1 -++inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0 -+-inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1 -+-inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0 -+-inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0 -+-inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1 -+-inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0 -+-inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0 -+-inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1 -+-inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0 -+-inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1 -+-inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1 -+-inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0 -+-inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1 -+-inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1 -+-inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0 -Index: none/tests/ppc32/test_isa_2_07_part2.stdout.exp -=================================================================== ---- none/tests/ppc32/test_isa_2_07_part2.stdout.exp.orig -+++ none/tests/ppc32/test_isa_2_07_part2.stdout.exp -@@ -651,26 +651,26 @@ Test VSX floating point instructions - - - Test VSX vector and scalar single argument instructions --#0: xscvdpspn conv(3ec00000) = 3ec00000 --#1: xscvdpspn conv(42780000) = 42780000 --#2: xscvdpspn conv(00000000) = 00000000 --#3: xscvdpspn conv(7f800000) = 7f800000 --#4: xscvdpspn conv(00000000) = 00000000 --#5: xscvdpspn conv(00000000) = 00000000 --#6: xscvdpspn conv(80000000) = 80000000 --#7: xscvdpspn conv(7f800000) = 7f800000 --#8: xscvdpspn conv(ff800000) = ff800000 --#9: xscvdpspn conv(7fbfffff) = 7fbfffff --#10: xscvdpspn conv(ffbfffff) = ffbfffff --#11: xscvdpspn conv(7fc00000) = 7fc00000 --#12: xscvdpspn conv(ffc00000) = ffc00000 --#13: xscvdpspn conv(80000000) = 80000000 --#14: xscvdpspn conv(c683287b) = c683287b --#15: xscvdpspn conv(49192c2d) = 49192c2d --#16: xscvdpspn conv(49c1288d) = 49c1288d --#17: xscvdpspn conv(418977ad) = 418977ad --#18: xscvdpspn conv(428a5faf) = 428a5faf --#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc -+#0: xscvdpspn conv(3fd8000000000000) = 3ec00000 -+#1: xscvdpspn conv(404f000000000000) = 42780000 -+#2: xscvdpspn conv(0018000000b77501) = 00000000 -+#3: xscvdpspn conv(7fe800000000051b) = 7f800000 -+#4: xscvdpspn conv(0123214569900000) = 00000000 -+#5: xscvdpspn conv(0000000000000000) = 00000000 -+#6: xscvdpspn conv(8000000000000000) = 80000000 -+#7: xscvdpspn conv(7ff0000000000000) = 7f800000 -+#8: xscvdpspn conv(fff0000000000000) = ff800000 -+#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff -+#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff -+#11: xscvdpspn conv(7ff8000000000000) = 7fc00000 -+#12: xscvdpspn conv(fff8000000000000) = ffc00000 -+#13: xscvdpspn conv(8008340000078000) = 80000000 -+#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b -+#15: xscvdpspn conv(41232585a9900000) = 49192c2d -+#16: xscvdpspn conv(41382511a2000000) = 49c1288d -+#17: xscvdpspn conv(40312ef5a9300000) = 418977ad -+#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf -+#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc - - #0: xscvspdpn conv(3ec00000) = 3fd8000000000000 - #1: xscvspdpn conv(42780000) = 404f000000000000 -@@ -783,23 +783,15 @@ Test VSX logic instructions - #2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988 - - Test VSX scalar integer conversion instructions --#0: xscvsxdsp 80000001 => c3e0000000000000 --#1: xscvsxdsp 89abcdef => c3dd950c80000000 --#2: xscvsxdsp 00112233 => 4331223380000000 --#3: xscvsxdsp 74556677 => 43dd1559a0000000 --#4: xscvsxdsp 00001abb => 42babb89a0000000 --#5: xscvsxdsp 00000001 => 41f89abce0000000 --#6: xscvsxdsp 31929394 => 43c8c949c0000000 --#7: xscvsxdsp a1a2a3a4 => c3d7975720000000 -- --#0: xscvuxdsp 80000001 => 43e0000000000000 --#1: xscvuxdsp 89abcdef => 43e13579c0000000 --#2: xscvuxdsp 00112233 => 4331223380000000 --#3: xscvuxdsp 74556677 => 43dd1559a0000000 --#4: xscvuxdsp 00001abb => 42babb89a0000000 --#5: xscvuxdsp 00000001 => 41f89abce0000000 --#6: xscvuxdsp 31929394 => 43c8c949c0000000 --#7: xscvuxdsp a1a2a3a4 => 43e4345480000000 -+#0: xscvsxdsp 0102030405060708 => 4370203040000000 -+#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000 -+#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000 -+#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000 -+ -+#0: xscvuxdsp 0102030405060708 => 4370203040000000 -+#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000 -+#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000 -+#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000 - - - Test VSX load/store dp to sp instructions -@@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d - stxsspx: 40514bf5e0000000 ==> 428a5faf - - --stxsiwx: 80000001 ==> 80000001 --stxsiwx: 89abcdef ==> 89abcdef --stxsiwx: 00112233 ==> 00112233 --stxsiwx: 74556677 ==> 74556677 --stxsiwx: 00001abb ==> 00001abb --stxsiwx: 00000001 ==> 00000001 --stxsiwx: 31929394 ==> 31929394 --stxsiwx: a1a2a3a4 ==> a1a2a3a4 -+stxsiwx: 3ec00000 ==> 3ec00000 -+stxsiwx: 7f800000 ==> 7f800000 -+stxsiwx: 80000000 ==> 80000000 -+stxsiwx: 7fbfffff ==> 7fbfffff -+stxsiwx: ffc00000 ==> ffc00000 -+stxsiwx: 49192c2d ==> 49192c2d -+stxsiwx: 428a5faf ==> 428a5faf - - - lxsiwax: 80000001 ==> ffffffff80000001 -@@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394 - lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4 - - --lxsiwzx: 89abcdef ==> 00000000abcdef00 --lxsiwzx: 00112233 ==> 0000000011223374 --lxsiwzx: 74556677 ==> 0000000055667700 --lxsiwzx: 00001abb ==> 00000000001abb00 --lxsiwzx: 00000001 ==> 0000000000000131 --lxsiwzx: 31929394 ==> 00000000929394a1 --lxsiwzx: a1a2a3a4 ==> 00000000a2a3a410 --lxsiwzx: 10000b08 ==> 00000000000b0810 -+lxsiwzx: 89abcdef ==> 0000000089abcdef -+lxsiwzx: 00112233 ==> 0000000000112233 -+lxsiwzx: 74556677 ==> 0000000074556677 -+lxsiwzx: 00001abb ==> 0000000000001abb -+lxsiwzx: 00000001 ==> 0000000000000001 -+lxsiwzx: 31929394 ==> 0000000031929394 -+lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4 - - - lxsspx: 3ec00000 ==> 3fd8000000000000 -Index: none/tests/ppc32/test_isa_2_06_part2.c -=================================================================== ---- none/tests/ppc32/test_isa_2_06_part2.c.orig -+++ none/tests/ppc32/test_isa_2_06_part2.c -@@ -39,6 +39,13 @@ typedef uint64_t HWord_t; - typedef unsigned char Bool; - #define True 1 - #define False 0 -+ -+#ifdef VGP_ppc64le_linux -+#define isLE 1 -+#else -+#define isLE 0 -+#endif -+ - register HWord_t r14 __asm__ ("r14"); - register HWord_t r15 __asm__ ("r15"); - register HWord_t r16 __asm__ ("r16"); -@@ -798,8 +805,20 @@ static void test_xxspltw(void) - { - int uim; - unsigned long long * dst = NULL; -- unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL}; -- memcpy(&vec_inB, xb, 16); -+ unsigned int xb[] = { 0xfedc4321, 0x24681235, 0xf1e2d3c4, 0xe0057708}; -+ int i; -+ void * vecB_ptr = &vec_inB; -+ if (isLE) { -+ for (i = 3; i >=0; i--) { -+ memcpy(vecB_ptr, &xb[i], 4); -+ vecB_ptr+=4; -+ } -+ } else { -+ for (i = 0; i < 4; i++) { -+ memcpy(vecB_ptr, &xb[i], 4); -+ vecB_ptr+=4; -+ } -+ } - - for (uim = 0; uim < 4; uim++) { - switch (uim) { -@@ -817,7 +836,8 @@ static void test_xxspltw(void) - break; - } - dst = (unsigned long long *) &vec_out; -- printf("xxspltw 0x%016llx%016llx %d=> 0x%016llx", xb[0], xb[1], uim, *dst); -+ printf("xxspltw 0x%08x%08x%08x%08x %d=> 0x%016llx", xb[0], xb[1], -+ xb[2], xb[3], uim, *dst); - dst++; - printf("%016llx\n", *dst); - } -@@ -1226,22 +1246,33 @@ static void test_vx_simple_scalar_fp_ops - * (e.g. xssqrtdp). - */ - if (test_group.num_tests == nb_special_fargs && !test_group.targs) { -- void * inB; -+ void * inB, * vec_void_ptr = (void *)&vec_inB; - int i; -+ if (isLE) -+ vec_void_ptr += 8; - for (i = 0; i < nb_special_fargs; i++) { - inB = (void *)&spec_fargs[i]; - frbp = (unsigned long long *)&spec_fargs[i]; -- memcpy(&vec_inB, inB, 8); -+ memcpy(vec_void_ptr, inB, 8); - (*func)(); - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp, - convToWord ? (*dst & 0x00000000ffffffffULL) : *dst); - } - } else { -- void * inA, * inB; -+ void * inA, * inB, * vecA_void_ptr, * vecB_void_ptr; - unsigned int condreg, flags; - int isTdiv = (strstr(test_group.name, "xstdivdp") != NULL) ? 1 : 0; - int i; -+ if (isLE) { -+ vecA_void_ptr = (void *)&vec_inA + 8; -+ vecB_void_ptr = (void *)&vec_inB + 8; -+ } else { -+ vecA_void_ptr = (void *)&vec_inA; -+ vecB_void_ptr = (void *)&vec_inB; -+ } - for (i = 0; i < test_group.num_tests; i++) { - fp_test_args_t aTest = test_group.targs[i]; - inA = (void *)&spec_fargs[aTest.fra_idx]; -@@ -1249,8 +1280,8 @@ static void test_vx_simple_scalar_fp_ops - frap = (unsigned long long *)&spec_fargs[aTest.fra_idx]; - frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx]; - // Only need to copy one doubleword into each vector's element 0 -- memcpy(&vec_inA, inA, 8); -- memcpy(&vec_inB, inB, 8); -+ memcpy(vecA_void_ptr, inA, 8); -+ memcpy(vecB_void_ptr, inB, 8); - SET_FPSCR_ZERO; - SET_CR_XER_ZERO; - (*func)(); -@@ -1260,6 +1291,8 @@ static void test_vx_simple_scalar_fp_ops - printf("#%d: %s %016llx,%016llx => cr %x\n", i, test_group.name, *frap, *frbp, condreg); - } else { - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name, - *frap, *frbp, *dst); - } -@@ -1346,21 +1379,26 @@ again: - * src3 <= VSX[XB] - */ - if (scalar) { -+#ifdef VGP_ppc64le_linux -+#define VECTOR_ADDR(_v) ((void *)&_v) + 8 -+#else -+#define VECTOR_ADDR(_v) ((void *)&_v) -+#endif - // For scalar op, only need to copy one doubleword into each vector's element 0 - inA = (void *)&spec_fargs[aTest.fra_idx]; - inB = (void *)&spec_fargs[aTest.frb_idx]; - frap = (unsigned long long *)&spec_fargs[aTest.fra_idx]; -- memcpy(&vec_inA, inA, 8); -+ memcpy(VECTOR_ADDR(vec_inA), inA, 8); - if (repeat) { -- memcpy(&vec_out, inB, 8); // src2 -- memcpy(&vec_inB, &spec_fargs[fp_idx[0]], 8); //src3 -+ memcpy(VECTOR_ADDR(vec_out), inB, 8); // src2 -+ memcpy(VECTOR_ADDR(vec_inB), &spec_fargs[fp_idx[0]], 8); //src3 - frbp = (unsigned long long *)&spec_fargs[fp_idx[0]]; - } else { - frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx]; -- memcpy(&vec_inB, inB, 8); // src2 -- memcpy(&vec_out, &spec_fargs[fp_idx[0]], 8); //src3 -+ memcpy(VECTOR_ADDR(vec_inB), inB, 8); // src2 -+ memcpy(VECTOR_ADDR(vec_out), &spec_fargs[fp_idx[0]], 8); //src3 - } -- memcpy(vsr_XT, &vec_out, 8); -+ memcpy(vsr_XT, VECTOR_ADDR(vec_out), 8); - } else { - int j, loops = do_dp ? 2 : 4; - size_t len = do_dp ? 8 : 4; -@@ -1382,6 +1420,8 @@ again: - - (*func)(); - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - if (test_type < VX_VECTOR_FP_MULT_AND_OP2) - printf( "#%d: %s %s(%016llx,%016llx,%016llx) = %016llx\n", i, - test_name, test_group.op, vsr_XT[0], *frap, *frbp, *dst ); -Index: none/tests/ppc32/test_dfp4.c -=================================================================== ---- none/tests/ppc32/test_dfp4.c.orig -+++ none/tests/ppc32/test_dfp4.c -@@ -31,8 +31,13 @@ typedef union stuff { - _Decimal128 dec_val128; - unsigned long long u64_val; - struct { -+#if defined(VGP_ppc64le_linux) -+ unsigned long long vall; -+ unsigned long long valu; -+#else - unsigned long long valu; - unsigned long long vall; -+#endif - } u128; - } dfp_val_t; - -@@ -495,7 +500,6 @@ static void test_dfp_ClassAndGroupTest_o - test_val.u64_val = dfp64_vals[i]; - } else { - test_val.u128.valu = dfp128_vals[i * 2]; -- test_val.u64_val = test_val.u128.valu; - test_val.u128.vall = dfp128_vals[(i * 2) + 1]; - } - -@@ -509,11 +513,15 @@ again: - GET_CR(flags); - - condreg = ((flags >> (4 * (7-BF)))) & 0xf; -- printf("%s (DC/DG=%d) %s%016llx", test_def.name, data_class_OR_group, -- test_def.op, test_val.u64_val); -+ printf("%s (DC/DG=%d) %s", test_def.name, data_class_OR_group, -+ test_def.op); - if (test_def.precision == QUAD_TEST) { -- printf(" %016llx", test_val.u128.vall); -+ printf("%016llx %016llx", test_val.u128.valu, test_val.u128.vall); -+ } else { -+ printf("%016llx", test_val.u64_val); - } -+ -+ //%016llx - printf(" => %x (BF=%d)\n", condreg, BF); - } - if (repeat) { -@@ -562,10 +570,8 @@ again: - test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx]; - } else { - test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2]; -- test_val1.u64_val = test_val1.u128.valu; - test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1]; - test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2]; -- test_val2.u64_val = test_val2.u128.valu; - test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1]; - } - -@@ -575,13 +581,13 @@ again: - GET_CR(flags); - - condreg = ((flags >> (4 * (7-BF)))) & 0xf; -- printf("%s %016llx", test_def.name, test_val1.u64_val); -+ printf("%s ", test_def.name); - if (test_def.precision == LONG_TEST) { -- printf(" %s %016llx ", -- test_def.op, test_val2.u64_val); -+ printf("%016llx %s %016llx ", -+ test_val1.u64_val, test_def.op, test_val2.u64_val); - } else { -- printf(" %016llx %s %016llx %016llx ", -- test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall); -+ printf("%016llx %016llx %s %016llx %016llx ", -+ test_val1.u128.valu, test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall); - } - printf(" => %x (BF=%d)\n", condreg, BF); - } -Index: none/tests/ppc32/jm-insns.c -=================================================================== ---- none/tests/ppc32/jm-insns.c.orig -+++ none/tests/ppc32/jm-insns.c -@@ -260,6 +260,7 @@ asm(".section \".text\"\n" - "\t.previous\n" \ - ) - #else -+#if defined(VGP_ppc64be_linux) - #define ASSEMBLY_FUNC(__fname, __insn) \ - asm(".section \".text\"\n" \ - "\t.align 2\n" \ -@@ -275,6 +276,16 @@ asm(".section \".text\"\n" - "\t"__insn"\n" \ - "\tblr\n" \ - ) -+#elif defined(VGP_ppc64le_linux) -+#define ASSEMBLY_FUNC(__fname, __insn) \ -+asm(".section \".text\"\n" \ -+ "\t.align 2\n" \ -+ "\t.global "__fname"\n" \ -+ ""__fname":\n" \ -+ "\t"__insn"\n" \ -+ "\tblr\n" \ -+ ) -+#endif // VGP_ppc64 or VGP_ppc64le - #endif // #ifndef __powerpc64__ - - -@@ -4849,7 +4860,7 @@ static inline - test_func_t init_function( test_func_t p_func_F, uint32_t func_buf[] ) - { - uint32_t* p_func = (uint32_t*)p_func_F; --#ifndef __powerpc64__ -+#if !defined(__powerpc64__) || _CALL_ELF == 2 - func_buf[0] = p_func[0]; - func_buf[1] = p_func[1]; - return (test_func_t)&func_buf[0]; -@@ -5521,20 +5532,21 @@ static void test_int_ld_one_reg_imm16 (c - uint32_t* func_buf = get_rwx_area(); - volatile HWord_t res, base; - volatile uint32_t flags, xer; -- int i, offs, is_lwa=0; -+ int i, offs, shift_offset = 0; - - #ifdef __powerpc64__ -- is_lwa = strstr(name, "lwa") != NULL; -+ if (strstr(name, "lwa") || strstr(name, "ld") || strstr(name, "ldu")) -+ shift_offset = 1; - #endif - - // +ve d - base = (HWord_t)&iargs[0]; - for (i=0; i>2, 2, 14); - else - patch_op_imm16(&func_buf[0], offs); -@@ -5557,8 +5569,8 @@ static void test_int_ld_one_reg_imm16 (c - - // -ve d - base = (HWord_t)&iargs[nb_iargs-1]; -- for (i = -nb_iargs+1; i<=0; i++) { -- offs = i * sizeof(HWord_t); -+ for (i = 0; i > -nb_iargs; i--) { -+ offs = (i * sizeof(HWord_t)) + 1; - - /* Patch up the instruction */ - func = init_function( func, func_buf ); -@@ -5574,9 +5586,9 @@ static void test_int_ld_one_reg_imm16 (c - #ifndef __powerpc64__ - printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n", - #else -- printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n", -+ printf("%s %3d, (%016x) => %016llx, %3lld (%08x %08x)\n", - #endif -- name, offs, iargs[nb_iargs-1+i], res, r14-base, flags, xer); -+ name, offs, iargs[nb_iargs-1 + i], res, r14-base, flags, xer); - } - } - -@@ -5767,7 +5779,6 @@ static void test_float_three_args (const - /* Note: using nb_normal_fargs: - - not testing special values for these insns - */ -- - for (i=0; i %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]); -- printf("(%08x)\n", flags); -+ shift = ((unsigned int)i + *r15_in_ptr) & 0xf; -+ printf("%s %x, %3d", name, shift, 0); -+ printf(" => 0x"); -+ for (j = 0; j < 16; j++) { -+ printf("%02x", dst[j]); -+ if (j == 7) -+ printf(" 0x"); -+ } -+ -+ printf(" (%08x)\n", flags); - } - if (verbose) printf("\n"); - } -Index: none/tests/ppc32/test_isa_2_06_part3.c -=================================================================== ---- none/tests/ppc32/test_isa_2_06_part3.c.orig -+++ none/tests/ppc32/test_isa_2_06_part3.c -@@ -36,6 +36,12 @@ typedef uint32_t HWord_t; - typedef uint64_t HWord_t; - #endif /* __powerpc64__ */ - -+#ifdef VGP_ppc64le_linux -+#define isLE 1 -+#else -+#define isLE 0 -+#endif -+ - typedef unsigned char Bool; - #define True 1 - #define False 0 -@@ -1116,7 +1122,7 @@ static void test_vsx_one_fp_arg(void) - - for (i = 0; i < test_group.num_tests; i+=stride) { - unsigned int * pv; -- void * inB; -+ void * inB, * vecB_void_ptr = (void *)&vec_inB; - - pv = (unsigned int *)&vec_out; - // clear vec_out -@@ -1129,11 +1135,15 @@ static void test_vsx_one_fp_arg(void) - for (j = 0; j < loops; j++) { - inB = (void *)&spec_fargs[i + j]; - // copy double precision FP into vector element i -- memcpy(((void *)&vec_inB) + (j * 8), inB, 8); -+ if (isLE && is_scalar) -+ vecB_void_ptr += 8; -+ memcpy(vecB_void_ptr + (j * 8), inB, 8); - } - // execute test insn - (*func)(); - dst_dp = (unsigned long long *) &vec_out; -+ if (isLE && is_scalar) -+ dst_dp++; - printf("#%d: %s ", i/stride, test_group.name); - for (j = 0; j < loops; j++) { - if (j) -@@ -1141,7 +1151,7 @@ static void test_vsx_one_fp_arg(void) - frB_dp = (unsigned long long *)&spec_fargs[i + j]; - printf("%s(%016llx)", test_group.op, *frB_dp); - if (estimate) { -- Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, j); -+ Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 1: j); - printf(" ==> %s)", res ? "PASS" : "FAIL"); - /* For debugging . . . - printf(" ==> %s (res=%016llx)", res ? "PASS" : "FAIL", dst_dp[j]); -@@ -1162,29 +1172,36 @@ static void test_vsx_one_fp_arg(void) - } - printf("\n"); - } else { -- int j, skip_slot; -+ int j; - unsigned int * frB_sp, * dst_sp = NULL; - unsigned long long * dst_dp = NULL; -- if (sparse_sp) { -- skip_slot = 1; -+ if (sparse_sp) - loops = 2; -- } else { -- skip_slot = 0; -- } - for (j = 0; j < loops; j++) { - inB = (void *)&spec_sp_fargs[i + j]; - // copy single precision FP into vector element i -- if (skip_slot && j > 0) -- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4); -- else -- memcpy(((void *)&vec_inB) + (j * 4), inB, 4); -+ if (sparse_sp) { -+ if (isLE) -+ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4); -+ else -+ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4); -+ } else { -+ if (isLE && is_scalar) -+ vecB_void_ptr += 12; -+ memcpy(vecB_void_ptr + (j * 4), inB, 4); -+ } - } - // execute test insn - (*func)(); -- if (test_group.type == VX_CONV_TO_DOUBLE) -+ if (test_group.type == VX_CONV_TO_DOUBLE) { - dst_dp = (unsigned long long *) &vec_out; -- else -+ if (isLE && is_scalar) -+ dst_dp++; -+ } else { - dst_sp = (unsigned int *) &vec_out; -+ if (isLE && is_scalar) -+ dst_sp += 3; -+ } - // print result - printf("#%d: %s ", i/stride, test_group.name); - for (j = 0; j < loops; j++) { -@@ -1193,7 +1210,7 @@ static void test_vsx_one_fp_arg(void) - frB_sp = (unsigned int *)&spec_sp_fargs[i + j]; - printf("%s(%08x)", test_group.op, *frB_sp); - if (estimate) { -- Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, j); -+ Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 3 : j); - printf(" ==> %s)", res ? "PASS" : "FAIL"); - } else { - if (test_group.type == VX_CONV_TO_DOUBLE) -@@ -1275,23 +1292,24 @@ static void test_int_to_fp_convert(void) - } - printf("\n"); - } else { -- int j, skip_slot; -+ int j; - unsigned int * dst_sp = NULL; - unsigned int * targs = test_group.targs; - unsigned long long * dst_dp = NULL; -- if (sparse_sp) { -- skip_slot = 1; -+ void * vecB_void_ptr = (void *)&vec_inB; -+ if (sparse_sp) - loops = 2; -- } else { -- skip_slot = 0; -- } - for (j = 0; j < loops; j++) { - inB = (void *)&targs[i + j]; - // copy single word into vector element i -- if (skip_slot && j > 0) -- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4); -- else -- memcpy(((void *)&vec_inB) + (j * 4), inB, 4); -+ if (sparse_sp) { -+ if (isLE) -+ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4); -+ else -+ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4); -+ } else { -+ memcpy(vecB_void_ptr + (j * 4), inB, 4); -+ } - } - // execute test insn - (*func)(); -@@ -1441,7 +1459,7 @@ static void test_vx_tdivORtsqrt(void) - - for (i = 0; i < test_group.num_tests; i+=stride) { - unsigned int * pv; -- void * inB; -+ void * inB, * vecB_void_ptr = (void *)&vec_inB; - - pv = (unsigned int *)&vec_out; - // clear vec_out -@@ -1457,7 +1475,9 @@ static void test_vx_tdivORtsqrt(void) - for (j = 0; j < loops; j++) { - inB = (void *)&spec_fargs[i + j]; - // copy double precision FP into vector element i -- memcpy(((void *)&vec_inB) + (j * 8), inB, 8); -+ if (isLE && is_scalar) -+ vecB_void_ptr += 8; -+ memcpy(vecB_void_ptr + (j * 8), inB, 8); - } - } - // execute test insn -Index: none/tests/ppc32/jm_vec_isa_2_07.stdout.exp -=================================================================== ---- none/tests/ppc32/jm_vec_isa_2_07.stdout.exp.orig -+++ none/tests/ppc32/jm_vec_isa_2_07.stdout.exp -@@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0 - vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0 - vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000 - --vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a -+vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000 - vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000 --vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea -+vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000 - vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000 - - vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000 -Index: none/tests/ppc32/test_dfp5.c -=================================================================== ---- none/tests/ppc32/test_dfp5.c.orig -+++ none/tests/ppc32/test_dfp5.c -@@ -31,8 +31,13 @@ typedef union stuff { - _Decimal128 dec_val128; - unsigned long long u64_val; - struct { -+#if defined(VGP_ppc64le_linux) -+ unsigned long long vall; -+ unsigned long long valu; -+#else - unsigned long long valu; - unsigned long long vall; -+#endif - } u128; - } dfp_val_t; - -@@ -418,22 +423,20 @@ static void test_dfp_ddedpd_ops(void) - test_val.u64_val = dfp64_vals[i]; - } else { - test_val.u128.valu = dfp128_vals[i * 2]; -- test_val.u64_val = test_val.u128.valu; - test_val.u128.vall = dfp128_vals[(i * 2) + 1]; - } - - for (SP = 0; SP < 4; SP++) { - dfp_val_t result; - result = (*func)(SP, test_val); -- printf("%s (SP=%d) %s%016llx", test_def.name, SP, -- test_def.op, test_val.u64_val); -- if (test_def.precision == QUAD_TEST) { -- printf(" %016llx", test_val.u128.vall); -+ printf("%s (SP=%d) %s", test_def.name, SP, test_def.op); -+ if (test_def.precision == LONG_TEST) { -+ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val); -+ } else { -+ printf("%016llx %016llx ==> %016llx %016llx\n", -+ test_val.u128.valu, test_val.u128.vall, -+ result.u128.valu, result.u128.vall); - } -- if (test_def.precision == LONG_TEST) -- printf(" ==> %016llx\n", result.u64_val); -- else -- printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall); - } - } - k++; -@@ -484,20 +487,18 @@ static void test_dfp_denbcd_ops(void) - test_val.u64_val = bcd64_vals[i]; - } else { - test_val.u128.valu = bcd128_vals[i * 2]; -- test_val.u64_val = test_val.u128.valu; - test_val.u128.vall = bcd128_vals[(i * 2) + 1]; - } - - result = (*func)(S, test_val); -- printf("%s (S=%d) %s%016llx", test_def.name, S, -- test_def.op, test_val.u64_val); -- if (test_def.precision == QUAD_TEST) { -- printf(" %016llx", test_val.u128.vall); -+ printf("%s (S=%d) %s", test_def.name, S, test_def.op); -+ if (test_def.precision == LONG_TEST) { -+ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val); -+ } else { -+ printf("%016llx %016llx ==> %016llx %016llx\n", -+ test_val.u128.valu, test_val.u128.vall, -+ result.u128.valu, result.u128.vall); - } -- if (test_def.precision == LONG_TEST) -- printf(" ==> %016llx\n", result.u64_val); -- else -- printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall); - } - } - k++; -@@ -532,7 +533,6 @@ static void test_dfp_test_significance_o - test_valB.u64_val = dfp64_vals[i]; - } else { - test_valB.u128.valu = dfp128_vals[i * 2]; -- test_valB.u64_val = test_valB.u128.valu; - test_valB.u128.vall = dfp128_vals[(i * 2) + 1]; - } - -@@ -549,10 +549,11 @@ static void test_dfp_test_significance_o - GET_CR(flags); - - condreg = ((flags >> (4 * (7-BF)))) & 0xf; -- printf("%s (ref_sig=%d) %s%016llx", test_def.name, reference_sig, -- test_def.op, test_valB.u64_val); -- if (test_def.precision == QUAD_TEST) { -- printf(" %016llx", test_valB.u128.vall); -+ printf("%s (ref_sig=%d) %s", test_def.name, reference_sig, test_def.op); -+ if (test_def.precision == LONG_TEST) { -+ printf("%016llx", test_valB.u64_val); -+ } else { -+ printf("%016llx %016llx", test_valB.u128.valu, test_valB.u128.vall); - } - printf(" => %x (BF=%d)\n", condreg, BF); - } -Index: none/tests/ppc32/test_isa_2_06_part1.stdout.exp -=================================================================== ---- none/tests/ppc32/test_isa_2_06_part1.stdout.exp.orig -+++ none/tests/ppc32/test_isa_2_06_part1.stdout.exp -@@ -130,13 +130,27 @@ ftdiv: 0000000000000000 <=> 000000000000 - ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx) - - Test VSX move instructions --xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394 -- --xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef -- --xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb -- --xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4 -+xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef -+xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942 -+xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4 -+ -+xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef -+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef -+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef -+xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942 -+xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942 -+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942 -+xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4 -+xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4 -+xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4 -+ -+xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef -+xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942 -+xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4 -+ -+xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef -+xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942 -+xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4 - - Test VSX permute instructions - xxmrghw: -@@ -1020,4 +1034,3 @@ Test VSX scalar integer conversion instr - #14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6 - - --Testcase PASSED -Index: none/tests/ppc32/round.stdout.exp -=================================================================== ---- none/tests/ppc32/round.stdout.exp.orig -+++ none/tests/ppc32/round.stdout.exp -@@ -324,38 +324,38 @@ zero:PASSED:fsubs(1.125000 , 0x1.000 - +inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0 - +inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0 - +inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0 --+inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000004p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1.000002p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1.000002p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1.000002p+0 --+inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000004p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1.000002p+0 ---inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0 -++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0 -+-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0 - -inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0 - -inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0 - -inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0 -@@ -409,78 +409,78 @@ zero:PASSED:fmuls(-1.000000 , 0x1.2p+ - zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 - zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 - zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 --zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0 --zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0 --zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0 --zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0 -+zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0 - zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 - zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 - zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 - zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0 --zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0 --zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0 --zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0 -+zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0 - zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 - zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0 - zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 - zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 - zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 --zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0 --zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0 --zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0 --zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0 -+zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0 - zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 - zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 - zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 - zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0 --zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0 --zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0 --zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0 -+zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0 - +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 - +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0 - +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 - +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 - +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 --+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0 --+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0 --+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0 --+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0 -++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0 - +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0 - +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 - +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 - +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0 --+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0 --+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0 --+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0 -++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0 - +inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0 --+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 --+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 --+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 --+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0 -++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0 - +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0 - +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0 - +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0 - +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0 --+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 --+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 --+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0 --+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0 -++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0 - +inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0 - +inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0 - +inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0 - -inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0 ---inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0 ---inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0 ---inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0 ---inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0 -+-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0 - -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0 - -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0 - -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0 - -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0 ---inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0 ---inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0 ---inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0 ---inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0 -+-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0 - -inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0 - -inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0 - -inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0 -@@ -489,17 +489,17 @@ zero:PASSED:fmuls(1.000002 , 0x1.2p+ - -inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0 - -inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0 - -inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0 ---inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0 ---inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0 ---inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0 ---inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0 -+-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0 - -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0 - -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0 - -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0 - -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0 ---inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0 ---inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0 ---inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0 -+-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0 - near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 - near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 - near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -@@ -566,35 +566,35 @@ zero:PASSED:fdivs(0.000000 , 0x1p+3 - zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0 - +inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 - +inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0 --+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 - +inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0 --+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 - +inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0 --+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0 - +inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0 --+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 - +inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0 --+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 - +inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0 --+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 - +inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0 --+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149 -++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149 - +inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0 - +inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0 - +inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0 --+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 - +inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0 --+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 - +inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0 --+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 - +inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0 --+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149 - +inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0 --+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 - +inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0 --+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 - +inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0 --+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148 -++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148 - +inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0 - -inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0 - -inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0 -@@ -665,78 +665,78 @@ zero:PASSED:fmadds(-1.000000 , 0x1.2p - zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 - zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 - zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 --zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 --zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 --zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 --zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 - zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 - zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 - zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 - zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 --zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 --zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 --zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 - zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 - zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 - zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 - zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 - zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 --zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 --zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 --zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 --zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 - zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 - zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 - zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 - zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 --zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 --zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 --zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 - +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 - +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 - +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 - +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 - +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 --+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 --+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 --+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 --+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 - +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 - +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 - +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 - +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 --+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 --+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 --+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 - +inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 --+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 --+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 --+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 --+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 - +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 - +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 - +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 - +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 --+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 --+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 --+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 --+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 - +inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 - +inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 - +inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0 - -inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 ---inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 ---inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 ---inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 ---inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -+-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 - -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 - -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 - -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 - -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 ---inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 ---inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 ---inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 ---inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -+-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 - -inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 - -inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 - -inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0 -@@ -745,17 +745,17 @@ zero:PASSED:fmadds(1.000002 , 0x1.2p - -inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 - -inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 - -inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 ---inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 ---inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 ---inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 ---inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 - -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 - -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 - -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 - -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 ---inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 ---inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 ---inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 - near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 - near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 - near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -@@ -793,78 +793,78 @@ zero:PASSED:fmsubs(-1.000000 , 0x1.2p - zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 - zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 - zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 --zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 --zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 --zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 --zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 - zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 - zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 - zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 - zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 --zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 --zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 --zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 - zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 - zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 - zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 - zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 - zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 --zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 --zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 --zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 --zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 - zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 - zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 - zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 - zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 --zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 --zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 --zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 - +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 - +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 - +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 - +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 - +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 --+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 --+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 --+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 --+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 - +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 - +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 - +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 - +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 --+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 --+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 --+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 - +inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 --+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 --+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 --+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 --+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 - +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 - +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 - +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 - +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 --+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 --+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 --+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 --+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 - +inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 - +inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 - +inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0 - -inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 ---inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 ---inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 ---inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 ---inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -+-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 - -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 - -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 - -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 - -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 ---inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 ---inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 ---inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 ---inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -+-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 - -inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 - -inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 - -inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0 -@@ -873,17 +873,17 @@ zero:PASSED:fmsubs(1.000002 , 0x1.2p - -inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 - -inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 - -inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 ---inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 ---inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 ---inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 ---inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 - -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 - -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 - -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 - -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 ---inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 ---inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 ---inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 - near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 - near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 - near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -@@ -921,78 +921,78 @@ zero:PASSED:fnmadds(-1.000000 , 0x1.2 - zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 - zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 - zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 --zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 --zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 --zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 --zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 - zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 - zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 - zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 - zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 --zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 --zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 --zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 - zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0 - zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 - zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 - zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 - zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 --zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 --zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 --zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 --zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 - zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 - zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 - zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 - zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 --zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 --zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 --zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 - +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0 - +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 - +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 - +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 - +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 --+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 --+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 --+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 --+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 - +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 - +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 - +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 - +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 --+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 --+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 --+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 - +inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0 --+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 --+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 --+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 --+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0 -++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 - +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 - +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 - +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 - +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 --+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 --+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 --+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 --+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0 -++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 - +inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 - +inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 - +inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0 - -inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0 ---inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 ---inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 ---inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 ---inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0 -+-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0 - -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0 - -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0 - -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0 - -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0 ---inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 ---inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 ---inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 ---inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0 -+-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0 - -inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0 - -inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0 - -inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0 -@@ -1001,17 +1001,17 @@ zero:PASSED:fnmadds(1.000002 , 0x1.2 - -inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0 - -inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0 - -inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0 ---inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 ---inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 ---inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 ---inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0 - -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0 - -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0 - -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0 - -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0 ---inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 ---inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 ---inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0 - near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 - near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 - near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -@@ -1049,78 +1049,78 @@ zero:PASSED:fnmsubs(-1.000000 , 0x1.2 - zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 - zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 - zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 --zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 --zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 --zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 --zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -+zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 - zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 - zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 - zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 - zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 --zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 --zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 --zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -+zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 - zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0 - zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 - zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 - zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 - zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 --zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 --zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 --zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 --zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 - zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 - zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 - zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 - zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 --zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 --zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 --zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 - +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0 - +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 - +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 - +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 - +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 --+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 --+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 --+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 --+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 -++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 - +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 - +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 - +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 - +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 --+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 --+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 --+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 -++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 - +inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0 --+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 --+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 --+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 --+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0 -++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 - +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 - +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 - +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 - +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 --+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 --+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 --+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 --+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0 -++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 - +inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 - +inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 - +inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0 - -inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0 ---inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 ---inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 ---inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 ---inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0 -+-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0 - -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0 - -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0 - -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0 - -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0 ---inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 ---inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 ---inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 ---inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0 -+-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0 - -inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0 - -inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0 - -inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0 -@@ -1129,17 +1129,17 @@ zero:PASSED:fnmsubs(1.000002 , 0x1.2 - -inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0 - -inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0 - -inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0 ---inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 ---inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 ---inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 ---inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0 -+-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0 - -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0 - -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0 - -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0 - -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0 ---inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 ---inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 ---inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0 -+-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0 - -------------------------- test rounding of double operators with guard bits -------------------------- - near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0 - near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0 -Index: none/tests/ppc32/jm-fp.stdout.exp-BE2 -=================================================================== ---- /dev/null -+++ none/tests/ppc32/jm-fp.stdout.exp-BE2 -@@ -0,0 +1,1431 @@ -+PPC floating point arith insns with three args: -+ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns -+ with three args with flags update: -+ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000 -+ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300 -+ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300 -+ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100 -+ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00 -+ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000 -+ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100 -+ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100 -+ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000 -+ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00 -+ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000 -+ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100 -+ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00 -+ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000 -+ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300 -+ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100 -+ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300 -+ -+ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000 -+ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000 -+ -+ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000 -+ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100 -+ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000 -+ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300 -+ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00 -+ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300 -+ -+ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000 -+ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000 -+ -+PPC floating point arith insns with two args: -+ fadd 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns -+ with two args with flags update: -+ fadd. 0010000000000001, 0010000000000001 => 0020000000000001 -+ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358 -+ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadd. 8000000000000000, 0010000000000001 => 0010000000000001 -+ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359 -+ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadd. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fadd. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadd. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fadds. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fadds. 8000000000000000, 0010000000000001 => 0000000000000000 -+ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000 -+ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000 -+ fadds. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fadds. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fadds. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsub. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad -+ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359 -+ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001 -+ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001 -+ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsub. 8000000000000000, 0010000000000001 => 8010000000000001 -+ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359 -+ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsub. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fsub. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsub. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000 -+ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000 -+ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000 -+ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000 -+ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000 -+ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000 -+ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmul. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad -+ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179 -+ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001 -+ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad -+ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmul. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmul. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fmul. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmul. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000 -+ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000 -+ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000 -+ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000 -+ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000 -+ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000 -+ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000 -+ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000 -+ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000 -+ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22 -+ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358 -+ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000 -+ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000 -+ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22 -+ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff -+ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff -+ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000 -+ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000 -+ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000 -+ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000 -+ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000 -+ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000 -+ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000 -+ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000 -+ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000 -+ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000 -+ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000 -+ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000 -+ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000 -+ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000 -+ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000 -+ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000 -+ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point compare insns (two args): -+ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000 -+ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000 -+ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000 -+ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000 -+ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000 -+ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000 -+ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000 -+ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000 -+ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000 -+ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns with one arg: -+ fres 0010000000000001 => 7ff0000000000000 -+ fres 00100094e0000359 => 7ff0000000000000 -+ fres 3fe0000000000001 => 4000000000000000 -+ fres 3fe00094e0000359 => 3ffff00000000000 -+ fres 8010000000000001 => fff0000000000000 -+ fres 80100094e0000359 => fff0000000000000 -+ fres bfe0000000000001 => c000000000000000 -+ fres bfe00094e0000359 => bffff00000000000 -+ fres 0000000000000000 => 7ff0000000000000 -+ fres 8000000000000000 => fff0000000000000 -+ fres 7ff0000000000000 => 0000000000000000 -+ fres fff0000000000000 => 8000000000000000 -+ fres 7ff7ffffffffffff => 7ffff00000000000 -+ fres fff7ffffffffffff => fffff00000000000 -+ fres 7ff8000000000000 => 7ff8000000000000 -+ fres fff8000000000000 => fff8000000000000 -+ -+ frsqrte 0010000000000001 => 5fdf000000000000 -+ frsqrte 00100094e0000359 => 5fdf000000000000 -+ frsqrte 3fe0000000000001 => 3ff6000000000000 -+ frsqrte 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte 8010000000000001 => 7ff8000000000000 -+ frsqrte 80100094e0000359 => 7ff8000000000000 -+ frsqrte bfe0000000000001 => 7ff8000000000000 -+ frsqrte bfe00094e0000359 => 7ff8000000000000 -+ frsqrte 0000000000000000 => 7ff0000000000000 -+ frsqrte 8000000000000000 => fff0000000000000 -+ frsqrte 7ff0000000000000 => 0000000000000000 -+ frsqrte fff0000000000000 => 7ff8000000000000 -+ frsqrte 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte fff7ffffffffffff => ffff000000000000 -+ frsqrte 7ff8000000000000 => 7ff8000000000000 -+ frsqrte fff8000000000000 => fff8000000000000 -+ -+ frsp 0010000000000001 => 0000000000000000 -+ frsp 00100094e0000359 => 0000000000000000 -+ frsp 3fe0000000000001 => 3fe0000000000000 -+ frsp 3fe00094e0000359 => 3fe00094e0000000 -+ frsp 8010000000000001 => 8000000000000000 -+ frsp 80100094e0000359 => 8000000000000000 -+ frsp bfe0000000000001 => bfe0000000000000 -+ frsp bfe00094e0000359 => bfe00094e0000000 -+ frsp 0000000000000000 => 0000000000000000 -+ frsp 8000000000000000 => 8000000000000000 -+ frsp 7ff0000000000000 => 7ff0000000000000 -+ frsp fff0000000000000 => fff0000000000000 -+ frsp 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp fff7ffffffffffff => ffffffffe0000000 -+ frsp 7ff8000000000000 => 7ff8000000000000 -+ frsp fff8000000000000 => fff8000000000000 -+ -+ fctiw 0010000000000001 => 0000000000000000 -+ fctiw 00100094e0000359 => 0000000000000000 -+ fctiw 3fe0000000000001 => 0000000000000001 -+ fctiw 3fe00094e0000359 => 0000000000000001 -+ fctiw 8010000000000001 => 0000000000000000 -+ fctiw 80100094e0000359 => 0000000000000000 -+ fctiw bfe0000000000001 => 00000000ffffffff -+ fctiw bfe00094e0000359 => 00000000ffffffff -+ fctiw 0000000000000000 => 0000000000000000 -+ fctiw 8000000000000000 => 0000000000000000 -+ fctiw 7ff0000000000000 => 000000007fffffff -+ fctiw fff0000000000000 => 0000000080000000 -+ fctiw 7ff7ffffffffffff => 0000000080000000 -+ fctiw fff7ffffffffffff => 0000000080000000 -+ fctiw 7ff8000000000000 => 0000000080000000 -+ fctiw fff8000000000000 => 0000000080000000 -+ -+ fctiwz 0010000000000001 => 0000000000000000 -+ fctiwz 00100094e0000359 => 0000000000000000 -+ fctiwz 3fe0000000000001 => 0000000000000000 -+ fctiwz 3fe00094e0000359 => 0000000000000000 -+ fctiwz 8010000000000001 => 0000000000000000 -+ fctiwz 80100094e0000359 => 0000000000000000 -+ fctiwz bfe0000000000001 => 0000000000000000 -+ fctiwz bfe00094e0000359 => 0000000000000000 -+ fctiwz 0000000000000000 => 0000000000000000 -+ fctiwz 8000000000000000 => 0000000000000000 -+ fctiwz 7ff0000000000000 => 000000007fffffff -+ fctiwz fff0000000000000 => 0000000080000000 -+ fctiwz 7ff7ffffffffffff => 0000000080000000 -+ fctiwz fff7ffffffffffff => 0000000080000000 -+ fctiwz 7ff8000000000000 => 0000000080000000 -+ fctiwz fff8000000000000 => 0000000080000000 -+ -+ fmr 0010000000000001 => 0010000000000001 -+ fmr 00100094e0000359 => 00100094e0000359 -+ fmr 3fe0000000000001 => 3fe0000000000001 -+ fmr 3fe00094e0000359 => 3fe00094e0000359 -+ fmr 8010000000000001 => 8010000000000001 -+ fmr 80100094e0000359 => 80100094e0000359 -+ fmr bfe0000000000001 => bfe0000000000001 -+ fmr bfe00094e0000359 => bfe00094e0000359 -+ fmr 0000000000000000 => 0000000000000000 -+ fmr 8000000000000000 => 8000000000000000 -+ fmr 7ff0000000000000 => 7ff0000000000000 -+ fmr fff0000000000000 => fff0000000000000 -+ fmr 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr fff7ffffffffffff => fff7ffffffffffff -+ fmr 7ff8000000000000 => 7ff8000000000000 -+ fmr fff8000000000000 => fff8000000000000 -+ -+ fneg 0010000000000001 => 8010000000000001 -+ fneg 00100094e0000359 => 80100094e0000359 -+ fneg 3fe0000000000001 => bfe0000000000001 -+ fneg 3fe00094e0000359 => bfe00094e0000359 -+ fneg 8010000000000001 => 0010000000000001 -+ fneg 80100094e0000359 => 00100094e0000359 -+ fneg bfe0000000000001 => 3fe0000000000001 -+ fneg bfe00094e0000359 => 3fe00094e0000359 -+ fneg 0000000000000000 => 8000000000000000 -+ fneg 8000000000000000 => 0000000000000000 -+ fneg 7ff0000000000000 => fff0000000000000 -+ fneg fff0000000000000 => 7ff0000000000000 -+ fneg 7ff7ffffffffffff => fff7ffffffffffff -+ fneg fff7ffffffffffff => 7ff7ffffffffffff -+ fneg 7ff8000000000000 => fff8000000000000 -+ fneg fff8000000000000 => 7ff8000000000000 -+ -+ fabs 0010000000000001 => 0010000000000001 -+ fabs 00100094e0000359 => 00100094e0000359 -+ fabs 3fe0000000000001 => 3fe0000000000001 -+ fabs 3fe00094e0000359 => 3fe00094e0000359 -+ fabs 8010000000000001 => 0010000000000001 -+ fabs 80100094e0000359 => 00100094e0000359 -+ fabs bfe0000000000001 => 3fe0000000000001 -+ fabs bfe00094e0000359 => 3fe00094e0000359 -+ fabs 0000000000000000 => 0000000000000000 -+ fabs 8000000000000000 => 0000000000000000 -+ fabs 7ff0000000000000 => 7ff0000000000000 -+ fabs fff0000000000000 => 7ff0000000000000 -+ fabs 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs fff7ffffffffffff => 7ff7ffffffffffff -+ fabs 7ff8000000000000 => 7ff8000000000000 -+ fabs fff8000000000000 => 7ff8000000000000 -+ -+ fnabs 0010000000000001 => 8010000000000001 -+ fnabs 00100094e0000359 => 80100094e0000359 -+ fnabs 3fe0000000000001 => bfe0000000000001 -+ fnabs 3fe00094e0000359 => bfe00094e0000359 -+ fnabs 8010000000000001 => 8010000000000001 -+ fnabs 80100094e0000359 => 80100094e0000359 -+ fnabs bfe0000000000001 => bfe0000000000001 -+ fnabs bfe00094e0000359 => bfe00094e0000359 -+ fnabs 0000000000000000 => 8000000000000000 -+ fnabs 8000000000000000 => 8000000000000000 -+ fnabs 7ff0000000000000 => fff0000000000000 -+ fnabs fff0000000000000 => fff0000000000000 -+ fnabs 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs fff7ffffffffffff => fff7ffffffffffff -+ fnabs 7ff8000000000000 => fff8000000000000 -+ fnabs fff8000000000000 => fff8000000000000 -+ -+ fsqrt 0010000000000001 => 2000000000000000 -+ fsqrt 00100094e0000359 => 2000004a6f52dd4a -+ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd -+ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df -+ fsqrt 8010000000000001 => 7ff8000000000000 -+ fsqrt 80100094e0000359 => 7ff8000000000000 -+ fsqrt bfe0000000000001 => 7ff8000000000000 -+ fsqrt bfe00094e0000359 => 7ff8000000000000 -+ fsqrt 0000000000000000 => 0000000000000000 -+ fsqrt 8000000000000000 => 8000000000000000 -+ fsqrt 7ff0000000000000 => 7ff0000000000000 -+ fsqrt fff0000000000000 => 7ff8000000000000 -+ fsqrt 7ff7ffffffffffff => 7fffffffffffffff -+ fsqrt fff7ffffffffffff => ffffffffffffffff -+ fsqrt 7ff8000000000000 => 7ff8000000000000 -+ fsqrt fff8000000000000 => fff8000000000000 -+ -+PPC floating point arith insns -+ with one arg with flags update: -+ fres. 0010000000000001 => 7ff0000000000000 -+ fres. 00100094e0000359 => 7ff0000000000000 -+ fres. 3fe0000000000001 => 4000000000000000 -+ fres. 3fe00094e0000359 => 3ffff00000000000 -+ fres. 8010000000000001 => fff0000000000000 -+ fres. 80100094e0000359 => fff0000000000000 -+ fres. bfe0000000000001 => c000000000000000 -+ fres. bfe00094e0000359 => bffff00000000000 -+ fres. 0000000000000000 => 7ff0000000000000 -+ fres. 8000000000000000 => fff0000000000000 -+ fres. 7ff0000000000000 => 0000000000000000 -+ fres. fff0000000000000 => 8000000000000000 -+ fres. 7ff7ffffffffffff => 7ffff00000000000 -+ fres. fff7ffffffffffff => fffff00000000000 -+ fres. 7ff8000000000000 => 7ff8000000000000 -+ fres. fff8000000000000 => fff8000000000000 -+ -+ frsqrte. 0010000000000001 => 5fdf000000000000 -+ frsqrte. 00100094e0000359 => 5fdf000000000000 -+ frsqrte. 3fe0000000000001 => 3ff6000000000000 -+ frsqrte. 3fe00094e0000359 => 3ff6000000000000 -+ frsqrte. 8010000000000001 => 7ff8000000000000 -+ frsqrte. 80100094e0000359 => 7ff8000000000000 -+ frsqrte. bfe0000000000001 => 7ff8000000000000 -+ frsqrte. bfe00094e0000359 => 7ff8000000000000 -+ frsqrte. 0000000000000000 => 7ff0000000000000 -+ frsqrte. 8000000000000000 => fff0000000000000 -+ frsqrte. 7ff0000000000000 => 0000000000000000 -+ frsqrte. fff0000000000000 => 7ff8000000000000 -+ frsqrte. 7ff7ffffffffffff => 7fff000000000000 -+ frsqrte. fff7ffffffffffff => ffff000000000000 -+ frsqrte. 7ff8000000000000 => 7ff8000000000000 -+ frsqrte. fff8000000000000 => fff8000000000000 -+ -+ frsp. 0010000000000001 => 0000000000000000 -+ frsp. 00100094e0000359 => 0000000000000000 -+ frsp. 3fe0000000000001 => 3fe0000000000000 -+ frsp. 3fe00094e0000359 => 3fe00094e0000000 -+ frsp. 8010000000000001 => 8000000000000000 -+ frsp. 80100094e0000359 => 8000000000000000 -+ frsp. bfe0000000000001 => bfe0000000000000 -+ frsp. bfe00094e0000359 => bfe00094e0000000 -+ frsp. 0000000000000000 => 0000000000000000 -+ frsp. 8000000000000000 => 8000000000000000 -+ frsp. 7ff0000000000000 => 7ff0000000000000 -+ frsp. fff0000000000000 => fff0000000000000 -+ frsp. 7ff7ffffffffffff => 7fffffffe0000000 -+ frsp. fff7ffffffffffff => ffffffffe0000000 -+ frsp. 7ff8000000000000 => 7ff8000000000000 -+ frsp. fff8000000000000 => fff8000000000000 -+ -+ fctiw. 0010000000000001 => 0000000000000000 -+ fctiw. 00100094e0000359 => 0000000000000000 -+ fctiw. 3fe0000000000001 => 0000000000000001 -+ fctiw. 3fe00094e0000359 => 0000000000000001 -+ fctiw. 8010000000000001 => 0000000000000000 -+ fctiw. 80100094e0000359 => 0000000000000000 -+ fctiw. bfe0000000000001 => 00000000ffffffff -+ fctiw. bfe00094e0000359 => 00000000ffffffff -+ fctiw. 0000000000000000 => 0000000000000000 -+ fctiw. 8000000000000000 => 0000000000000000 -+ fctiw. 7ff0000000000000 => 000000007fffffff -+ fctiw. fff0000000000000 => 0000000080000000 -+ fctiw. 7ff7ffffffffffff => 0000000080000000 -+ fctiw. fff7ffffffffffff => 0000000080000000 -+ fctiw. 7ff8000000000000 => 0000000080000000 -+ fctiw. fff8000000000000 => 0000000080000000 -+ -+ fctiwz. 0010000000000001 => 0000000000000000 -+ fctiwz. 00100094e0000359 => 0000000000000000 -+ fctiwz. 3fe0000000000001 => 0000000000000000 -+ fctiwz. 3fe00094e0000359 => 0000000000000000 -+ fctiwz. 8010000000000001 => 0000000000000000 -+ fctiwz. 80100094e0000359 => 0000000000000000 -+ fctiwz. bfe0000000000001 => 0000000000000000 -+ fctiwz. bfe00094e0000359 => 0000000000000000 -+ fctiwz. 0000000000000000 => 0000000000000000 -+ fctiwz. 8000000000000000 => 0000000000000000 -+ fctiwz. 7ff0000000000000 => 000000007fffffff -+ fctiwz. fff0000000000000 => 0000000080000000 -+ fctiwz. 7ff7ffffffffffff => 0000000080000000 -+ fctiwz. fff7ffffffffffff => 0000000080000000 -+ fctiwz. 7ff8000000000000 => 0000000080000000 -+ fctiwz. fff8000000000000 => 0000000080000000 -+ -+ fmr. 0010000000000001 => 0010000000000001 -+ fmr. 00100094e0000359 => 00100094e0000359 -+ fmr. 3fe0000000000001 => 3fe0000000000001 -+ fmr. 3fe00094e0000359 => 3fe00094e0000359 -+ fmr. 8010000000000001 => 8010000000000001 -+ fmr. 80100094e0000359 => 80100094e0000359 -+ fmr. bfe0000000000001 => bfe0000000000001 -+ fmr. bfe00094e0000359 => bfe00094e0000359 -+ fmr. 0000000000000000 => 0000000000000000 -+ fmr. 8000000000000000 => 8000000000000000 -+ fmr. 7ff0000000000000 => 7ff0000000000000 -+ fmr. fff0000000000000 => fff0000000000000 -+ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fmr. fff7ffffffffffff => fff7ffffffffffff -+ fmr. 7ff8000000000000 => 7ff8000000000000 -+ fmr. fff8000000000000 => fff8000000000000 -+ -+ fneg. 0010000000000001 => 8010000000000001 -+ fneg. 00100094e0000359 => 80100094e0000359 -+ fneg. 3fe0000000000001 => bfe0000000000001 -+ fneg. 3fe00094e0000359 => bfe00094e0000359 -+ fneg. 8010000000000001 => 0010000000000001 -+ fneg. 80100094e0000359 => 00100094e0000359 -+ fneg. bfe0000000000001 => 3fe0000000000001 -+ fneg. bfe00094e0000359 => 3fe00094e0000359 -+ fneg. 0000000000000000 => 8000000000000000 -+ fneg. 8000000000000000 => 0000000000000000 -+ fneg. 7ff0000000000000 => fff0000000000000 -+ fneg. fff0000000000000 => 7ff0000000000000 -+ fneg. 7ff7ffffffffffff => fff7ffffffffffff -+ fneg. fff7ffffffffffff => 7ff7ffffffffffff -+ fneg. 7ff8000000000000 => fff8000000000000 -+ fneg. fff8000000000000 => 7ff8000000000000 -+ -+ fabs. 0010000000000001 => 0010000000000001 -+ fabs. 00100094e0000359 => 00100094e0000359 -+ fabs. 3fe0000000000001 => 3fe0000000000001 -+ fabs. 3fe00094e0000359 => 3fe00094e0000359 -+ fabs. 8010000000000001 => 0010000000000001 -+ fabs. 80100094e0000359 => 00100094e0000359 -+ fabs. bfe0000000000001 => 3fe0000000000001 -+ fabs. bfe00094e0000359 => 3fe00094e0000359 -+ fabs. 0000000000000000 => 0000000000000000 -+ fabs. 8000000000000000 => 0000000000000000 -+ fabs. 7ff0000000000000 => 7ff0000000000000 -+ fabs. fff0000000000000 => 7ff0000000000000 -+ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff -+ fabs. fff7ffffffffffff => 7ff7ffffffffffff -+ fabs. 7ff8000000000000 => 7ff8000000000000 -+ fabs. fff8000000000000 => 7ff8000000000000 -+ -+ fnabs. 0010000000000001 => 8010000000000001 -+ fnabs. 00100094e0000359 => 80100094e0000359 -+ fnabs. 3fe0000000000001 => bfe0000000000001 -+ fnabs. 3fe00094e0000359 => bfe00094e0000359 -+ fnabs. 8010000000000001 => 8010000000000001 -+ fnabs. 80100094e0000359 => 80100094e0000359 -+ fnabs. bfe0000000000001 => bfe0000000000001 -+ fnabs. bfe00094e0000359 => bfe00094e0000359 -+ fnabs. 0000000000000000 => 8000000000000000 -+ fnabs. 8000000000000000 => 8000000000000000 -+ fnabs. 7ff0000000000000 => fff0000000000000 -+ fnabs. fff0000000000000 => fff0000000000000 -+ fnabs. 7ff7ffffffffffff => fff7ffffffffffff -+ fnabs. fff7ffffffffffff => fff7ffffffffffff -+ fnabs. 7ff8000000000000 => fff8000000000000 -+ fnabs. fff8000000000000 => fff8000000000000 -+ -+PPC floating point status register manipulation insns: -+PPC floating point status register manipulation insns -+ with flags update: -+PPC float load insns -+ with one register + one 16 bits immediate args with flags update: -+ lfs 0010000000000001, 65416 => 37e0000000000000, 0 -+ lfs 00100094e0000359, 65424 => 37e0009400000000, 0 -+ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0 -+ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0 -+ lfs 8010000000000001, 65448 => b7e0000000000000, 0 -+ lfs 80100094e0000359, 65456 => b7e0009400000000, 0 -+ lfs bfe0000000000001, 65464 => bffc000000000000, 0 -+ lfs bfe00094e0000359, 65472 => bffc001280000000, 0 -+ lfs 0000000000000000, 65480 => 0000000000000000, 0 -+ lfs 8000000000000000, 65488 => 8000000000000000, 0 -+ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0 -+ lfs fff0000000000000, 65504 => fffe000000000000, 0 -+ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0 -+ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0 -+ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0 -+ lfs 0010000000000001, 0 => 37e0000000000000, 0 -+ lfs 00100094e0000359, 8 => 37e0009400000000, 0 -+ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0 -+ lfs 3fe00094e0000359, 24 => 3ffc001280000000, 0 -+ lfs 8010000000000001, 32 => b7e0000000000000, 0 -+ lfs 80100094e0000359, 40 => b7e0009400000000, 0 -+ lfs bfe0000000000001, 48 => bffc000000000000, 0 -+ lfs bfe00094e0000359, 56 => bffc001280000000, 0 -+ lfs 0000000000000000, 64 => 0000000000000000, 0 -+ lfs 8000000000000000, 72 => 8000000000000000, 0 -+ lfs 7ff0000000000000, 80 => 7ffe000000000000, 0 -+ lfs fff0000000000000, 88 => fffe000000000000, 0 -+ lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0 -+ lfs fff7ffffffffffff, 104 => fffeffffe0000000, 0 -+ lfs 7ff8000000000000, 112 => 7fff000000000000, 0 -+ lfs fff8000000000000, 120 => ffff000000000000, 0 -+ -+ lfsu 0010000000000001, 65416 => 37e0000000000000, -120 -+ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112 -+ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104 -+ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96 -+ lfsu 8010000000000001, 65448 => b7e0000000000000, -88 -+ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80 -+ lfsu bfe0000000000001, 65464 => bffc000000000000, -72 -+ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64 -+ lfsu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfsu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40 -+ lfsu fff0000000000000, 65504 => fffe000000000000, -32 -+ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24 -+ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16 -+ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8 -+ lfsu 0010000000000001, 0 => 37e0000000000000, 0 -+ lfsu 00100094e0000359, 8 => 37e0009400000000, 8 -+ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16 -+ lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 24 -+ lfsu 8010000000000001, 32 => b7e0000000000000, 32 -+ lfsu 80100094e0000359, 40 => b7e0009400000000, 40 -+ lfsu bfe0000000000001, 48 => bffc000000000000, 48 -+ lfsu bfe00094e0000359, 56 => bffc001280000000, 56 -+ lfsu 0000000000000000, 64 => 0000000000000000, 64 -+ lfsu 8000000000000000, 72 => 8000000000000000, 72 -+ lfsu 7ff0000000000000, 80 => 7ffe000000000000, 80 -+ lfsu fff0000000000000, 88 => fffe000000000000, 88 -+ lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96 -+ lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 104 -+ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112 -+ lfsu fff8000000000000, 120 => ffff000000000000, 120 -+ -+ lfd 0010000000000001, 65416 => 0010000000000001, 0 -+ lfd 00100094e0000359, 65424 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 65448 => 8010000000000001, 0 -+ lfd 80100094e0000359, 65456 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 65464 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 65480 => 0000000000000000, 0 -+ lfd 8000000000000000, 65488 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 65504 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0 -+ lfd 0010000000000001, 0 => 0010000000000001, 0 -+ lfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfd 8010000000000001, 32 => 8010000000000001, 0 -+ lfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfd 0000000000000000, 64 => 0000000000000000, 0 -+ lfd 8000000000000000, 72 => 8000000000000000, 0 -+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfd fff0000000000000, 88 => fff0000000000000, 0 -+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdu 0010000000000001, 65416 => 0010000000000001, -120 -+ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112 -+ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104 -+ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96 -+ lfdu 8010000000000001, 65448 => 8010000000000001, -88 -+ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80 -+ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72 -+ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64 -+ lfdu 0000000000000000, 65480 => 0000000000000000, -56 -+ lfdu 8000000000000000, 65488 => 8000000000000000, -48 -+ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40 -+ lfdu fff0000000000000, 65504 => fff0000000000000, -32 -+ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24 -+ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16 -+ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8 -+ lfdu 0010000000000001, 0 => 0010000000000001, 0 -+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdu 8010000000000001, 32 => 8010000000000001, 32 -+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdu 0000000000000000, 64 => 0000000000000000, 64 -+ lfdu 8000000000000000, 72 => 8000000000000000, 72 -+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdu fff0000000000000, 88 => fff0000000000000, 88 -+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float load insns with two register args: -+ lfsx 0010000000000001, -120 => 37e0000000000000, 0 -+ lfsx 00100094e0000359, -112 => 37e0009400000000, 0 -+ lfsx 3fe0000000000001, -104 => 3ffc000000000000, 0 -+ lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 0 -+ lfsx 8010000000000001, -88 => b7e0000000000000, 0 -+ lfsx 80100094e0000359, -80 => b7e0009400000000, 0 -+ lfsx bfe0000000000001, -72 => bffc000000000000, 0 -+ lfsx bfe00094e0000359, -64 => bffc001280000000, 0 -+ lfsx 0000000000000000, -56 => 0000000000000000, 0 -+ lfsx 8000000000000000, -48 => 8000000000000000, 0 -+ lfsx 7ff0000000000000, -40 => 7ffe000000000000, 0 -+ lfsx fff0000000000000, -32 => fffe000000000000, 0 -+ lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0 -+ lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 0 -+ lfsx 7ff8000000000000, -8 => 7fff000000000000, 0 -+ lfsx 0010000000000001, 0 => 37e0000000000000, 0 -+ lfsx 00100094e0000359, 8 => 37e0009400000000, 0 -+ lfsx 3fe0000000000001, 16 => 3ffc000000000000, 0 -+ lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 0 -+ lfsx 8010000000000001, 32 => b7e0000000000000, 0 -+ lfsx 80100094e0000359, 40 => b7e0009400000000, 0 -+ lfsx bfe0000000000001, 48 => bffc000000000000, 0 -+ lfsx bfe00094e0000359, 56 => bffc001280000000, 0 -+ lfsx 0000000000000000, 64 => 0000000000000000, 0 -+ lfsx 8000000000000000, 72 => 8000000000000000, 0 -+ lfsx 7ff0000000000000, 80 => 7ffe000000000000, 0 -+ lfsx fff0000000000000, 88 => fffe000000000000, 0 -+ lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0 -+ lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 0 -+ lfsx 7ff8000000000000, 112 => 7fff000000000000, 0 -+ lfsx fff8000000000000, 120 => ffff000000000000, 0 -+ -+ lfsux 0010000000000001, -120 => 37e0000000000000, -120 -+ lfsux 00100094e0000359, -112 => 37e0009400000000, -112 -+ lfsux 3fe0000000000001, -104 => 3ffc000000000000, -104 -+ lfsux 3fe00094e0000359, -96 => 3ffc001280000000, -96 -+ lfsux 8010000000000001, -88 => b7e0000000000000, -88 -+ lfsux 80100094e0000359, -80 => b7e0009400000000, -80 -+ lfsux bfe0000000000001, -72 => bffc000000000000, -72 -+ lfsux bfe00094e0000359, -64 => bffc001280000000, -64 -+ lfsux 0000000000000000, -56 => 0000000000000000, -56 -+ lfsux 8000000000000000, -48 => 8000000000000000, -48 -+ lfsux 7ff0000000000000, -40 => 7ffe000000000000, -40 -+ lfsux fff0000000000000, -32 => fffe000000000000, -32 -+ lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24 -+ lfsux fff7ffffffffffff, -16 => fffeffffe0000000, -16 -+ lfsux 7ff8000000000000, -8 => 7fff000000000000, -8 -+ lfsux 0010000000000001, 0 => 37e0000000000000, 0 -+ lfsux 00100094e0000359, 8 => 37e0009400000000, 8 -+ lfsux 3fe0000000000001, 16 => 3ffc000000000000, 16 -+ lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 24 -+ lfsux 8010000000000001, 32 => b7e0000000000000, 32 -+ lfsux 80100094e0000359, 40 => b7e0009400000000, 40 -+ lfsux bfe0000000000001, 48 => bffc000000000000, 48 -+ lfsux bfe00094e0000359, 56 => bffc001280000000, 56 -+ lfsux 0000000000000000, 64 => 0000000000000000, 64 -+ lfsux 8000000000000000, 72 => 8000000000000000, 72 -+ lfsux 7ff0000000000000, 80 => 7ffe000000000000, 80 -+ lfsux fff0000000000000, 88 => fffe000000000000, 88 -+ lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96 -+ lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 104 -+ lfsux 7ff8000000000000, 112 => 7fff000000000000, 112 -+ lfsux fff8000000000000, 120 => ffff000000000000, 120 -+ -+ lfdx 0010000000000001, -120 => 0010000000000001, 0 -+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, -88 => 8010000000000001, 0 -+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, -56 => 0000000000000000, 0 -+ lfdx 8000000000000000, -48 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, -32 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ lfdx 0010000000000001, 0 => 0010000000000001, 0 -+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ lfdx 8010000000000001, 32 => 8010000000000001, 0 -+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ lfdx 0000000000000000, 64 => 0000000000000000, 0 -+ lfdx 8000000000000000, 72 => 8000000000000000, 0 -+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ lfdx fff0000000000000, 88 => fff0000000000000, 0 -+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ lfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ lfdux 0010000000000001, -120 => 0010000000000001, -120 -+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112 -+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ lfdux 8010000000000001, -88 => 8010000000000001, -88 -+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80 -+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72 -+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ lfdux 0000000000000000, -56 => 0000000000000000, -56 -+ lfdux 8000000000000000, -48 => 8000000000000000, -48 -+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ lfdux fff0000000000000, -32 => fff0000000000000, -32 -+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ lfdux 0010000000000001, 0 => 0010000000000001, 0 -+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ lfdux 8010000000000001, 32 => 8010000000000001, 32 -+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ lfdux 0000000000000000, 64 => 0000000000000000, 64 -+ lfdux 8000000000000000, 72 => 8000000000000000, 72 -+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ lfdux fff0000000000000, 88 => fff0000000000000, 88 -+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ lfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns -+ with one register + one 16 bits immediate args with flags update: -+ stfs 0010000000000001, -56 => 0000000000000000, 0 -+ stfs 00100094e0000359, -48 => 0000000000000000, 0 -+ stfs 3fe0000000000001, -40 => 3f00000000000000, 0 -+ stfs 3fe00094e0000359, -32 => 3f0004a700000000, 0 -+ stfs 8010000000000001, -24 => 8000000000000000, 0 -+ stfs 80100094e0000359, -16 => 8000000000000000, 0 -+ stfs bfe0000000000001, -8 => bf00000000000000, 0 -+ stfs 0010000000000001, 0 => 0000000000000000, 0 -+ stfs 00100094e0000359, 8 => 0000000000000000, 0 -+ stfs 3fe0000000000001, 16 => 3f00000000000000, 0 -+ stfs 3fe00094e0000359, 24 => 3f0004a700000000, 0 -+ stfs 8010000000000001, 32 => 8000000000000000, 0 -+ stfs 80100094e0000359, 40 => 8000000000000000, 0 -+ stfs bfe0000000000001, 48 => bf00000000000000, 0 -+ stfs bfe00094e0000359, 56 => bf0004a700000000, 0 -+ -+ stfsu 0010000000000001, -56 => 0000000000000000, -56 -+ stfsu 00100094e0000359, -48 => 0000000000000000, -48 -+ stfsu 3fe0000000000001, -40 => 3f00000000000000, -40 -+ stfsu 3fe00094e0000359, -32 => 3f0004a700000000, -32 -+ stfsu 8010000000000001, -24 => 8000000000000000, -24 -+ stfsu 80100094e0000359, -16 => 8000000000000000, -16 -+ stfsu bfe0000000000001, -8 => bf00000000000000, -8 -+ stfsu 0010000000000001, 0 => 0000000000000000, 0 -+ stfsu 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsu 3fe0000000000001, 16 => 3f00000000000000, 16 -+ stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 24 -+ stfsu 8010000000000001, 32 => 8000000000000000, 32 -+ stfsu 80100094e0000359, 40 => 8000000000000000, 40 -+ stfsu bfe0000000000001, 48 => bf00000000000000, 48 -+ stfsu bfe00094e0000359, 56 => bf0004a700000000, 56 -+ -+ stfd 0010000000000001, -120 => 0010000000000001, 0 -+ stfd 00100094e0000359, -112 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, -88 => 8010000000000001, 0 -+ stfd 80100094e0000359, -80 => 80100094e0000359, 0 -+ stfd bfe0000000000001, -72 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0 -+ stfd 0000000000000000, -56 => 0000000000000000, 0 -+ stfd 8000000000000000, -48 => 8000000000000000, 0 -+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0 -+ stfd fff0000000000000, -32 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0 -+ stfd 0010000000000001, 0 => 0010000000000001, 0 -+ stfd 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfd 8010000000000001, 32 => 8010000000000001, 0 -+ stfd 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfd bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfd 0000000000000000, 64 => 0000000000000000, 0 -+ stfd 8000000000000000, 72 => 8000000000000000, 0 -+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfd fff0000000000000, 88 => fff0000000000000, 0 -+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfd fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdu 0010000000000001, -120 => 0010000000000001, -120 -+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112 -+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104 -+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96 -+ stfdu 8010000000000001, -88 => 8010000000000001, -88 -+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80 -+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72 -+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64 -+ stfdu 0000000000000000, -56 => 0000000000000000, -56 -+ stfdu 8000000000000000, -48 => 8000000000000000, -48 -+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40 -+ stfdu fff0000000000000, -32 => fff0000000000000, -32 -+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24 -+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16 -+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8 -+ stfdu 0010000000000001, 0 => 0010000000000001, 0 -+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdu 8010000000000001, 32 => 8010000000000001, 32 -+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdu 0000000000000000, 64 => 0000000000000000, 64 -+ stfdu 8000000000000000, 72 => 8000000000000000, 72 -+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdu fff0000000000000, 88 => fff0000000000000, 88 -+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdu fff8000000000000, 120 => fff8000000000000, 120 -+ -+PPC float store insns with three register args: -+ stfsx 0010000000000001, 0 => 0000000000000000, 0 -+ stfsx 00100094e0000359, 8 => 0000000000000000, 0 -+ stfsx 3fe0000000000001, 16 => 3f00000000000000, 0 -+ stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 0 -+ stfsx 8010000000000001, 32 => 8000000000000000, 0 -+ stfsx 80100094e0000359, 40 => 8000000000000000, 0 -+ stfsx bfe0000000000001, 48 => bf00000000000000, 0 -+ stfsx bfe00094e0000359, 56 => bf0004a700000000, 0 -+ -+ stfsux 0010000000000001, 0 => 0000000000000000, 0 -+ stfsux 00100094e0000359, 8 => 0000000000000000, 8 -+ stfsux 3fe0000000000001, 16 => 3f00000000000000, 16 -+ stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 24 -+ stfsux 8010000000000001, 32 => 8000000000000000, 32 -+ stfsux 80100094e0000359, 40 => 8000000000000000, 40 -+ stfsux bfe0000000000001, 48 => bf00000000000000, 48 -+ stfsux bfe00094e0000359, 56 => bf0004a700000000, 56 -+ -+ stfdx 0010000000000001, 0 => 0010000000000001, 0 -+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0 -+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0 -+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0 -+ stfdx 8010000000000001, 32 => 8010000000000001, 0 -+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0 -+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0 -+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0 -+ stfdx 0000000000000000, 64 => 0000000000000000, 0 -+ stfdx 8000000000000000, 72 => 8000000000000000, 0 -+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0 -+ stfdx fff0000000000000, 88 => fff0000000000000, 0 -+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0 -+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0 -+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0 -+ stfdx fff8000000000000, 120 => fff8000000000000, 0 -+ -+ stfdux 0010000000000001, 0 => 0010000000000001, 0 -+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8 -+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16 -+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24 -+ stfdux 8010000000000001, 32 => 8010000000000001, 32 -+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40 -+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48 -+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56 -+ stfdux 0000000000000000, 64 => 0000000000000000, 64 -+ stfdux 8000000000000000, 72 => 8000000000000000, 72 -+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80 -+ stfdux fff0000000000000, 88 => fff0000000000000, 88 -+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96 -+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104 -+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112 -+ stfdux fff8000000000000, 120 => fff8000000000000, 120 -+ -+All done. Tested 71 different instructions -Index: none/tests/ppc32/jm-int.stdout.exp -=================================================================== ---- none/tests/ppc32/jm-int.stdout.exp.orig -+++ none/tests/ppc32/jm-int.stdout.exp -@@ -1439,60 +1439,60 @@ PPC logical insns with special forms wit - PPC integer load insns - with one register + one 16 bits immediate args with flags update: - lbz 0, (00000000) => 00000000, 0 (00000000 00000000) -- lbz 4, (000f423f) => 00000000, 0 (00000000 00000000) -- lbz 8, (ffffffff) => 000000ff, 0 (00000000 00000000) -- lbz -8, (00000000) => 00000000, 0 (00000000 00000000) -- lbz -4, (000f423f) => 00000000, 0 (00000000 00000000) -- lbz 0, (ffffffff) => 000000ff, 0 (00000000 00000000) -+ lbz 3, (000f423f) => 00000000, 0 (00000000 00000000) -+ lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000) -+ lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000) -+ lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000) -+ lbz -7, (00000000) => 00000000, 0 (00000000 00000000) - - lbzu 0, (00000000) => 00000000, 0 (00000000 00000000) -- lbzu 4, (000f423f) => 00000000, 4 (00000000 00000000) -- lbzu 8, (ffffffff) => 000000ff, 8 (00000000 00000000) -- lbzu -8, (00000000) => 00000000, -8 (00000000 00000000) -- lbzu -4, (000f423f) => 00000000, -4 (00000000 00000000) -- lbzu 0, (ffffffff) => 000000ff, 0 (00000000 00000000) -+ lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000) -+ lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000) -+ lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000) -+ lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000) -+ lbzu -7, (00000000) => 00000000, -7 (00000000 00000000) - - lha 0, (00000000) => 00000000, 0 (00000000 00000000) -- lha 4, (000f423f) => 0000000f, 0 (00000000 00000000) -- lha 8, (ffffffff) => ffffffff, 0 (00000000 00000000) -- lha -8, (00000000) => 00000000, 0 (00000000 00000000) -- lha -4, (000f423f) => 0000000f, 0 (00000000 00000000) -- lha 0, (ffffffff) => ffffffff, 0 (00000000 00000000) -+ lha 3, (000f423f) => 00000000, 0 (00000000 00000000) -+ lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000) -+ lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000) -+ lha -3, (000f423f) => 00000f42, 0 (00000000 00000000) -+ lha -7, (00000000) => 00000000, 0 (00000000 00000000) - - lhau 0, (00000000) => 00000000, 0 (00000000 00000000) -- lhau 4, (000f423f) => 0000000f, 4 (00000000 00000000) -- lhau 8, (ffffffff) => ffffffff, 8 (00000000 00000000) -- lhau -8, (00000000) => 00000000, -8 (00000000 00000000) -- lhau -4, (000f423f) => 0000000f, -4 (00000000 00000000) -- lhau 0, (ffffffff) => ffffffff, 0 (00000000 00000000) -+ lhau 3, (000f423f) => 00000000, 3 (00000000 00000000) -+ lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000) -+ lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000) -+ lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000) -+ lhau -7, (00000000) => 00000000, -7 (00000000 00000000) - - lhz 0, (00000000) => 00000000, 0 (00000000 00000000) -- lhz 4, (000f423f) => 0000000f, 0 (00000000 00000000) -- lhz 8, (ffffffff) => 0000ffff, 0 (00000000 00000000) -- lhz -8, (00000000) => 00000000, 0 (00000000 00000000) -- lhz -4, (000f423f) => 0000000f, 0 (00000000 00000000) -- lhz 0, (ffffffff) => 0000ffff, 0 (00000000 00000000) -+ lhz 3, (000f423f) => 00000000, 0 (00000000 00000000) -+ lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000) -+ lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000) -+ lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000) -+ lhz -7, (00000000) => 00000000, 0 (00000000 00000000) - - lhzu 0, (00000000) => 00000000, 0 (00000000 00000000) -- lhzu 4, (000f423f) => 0000000f, 4 (00000000 00000000) -- lhzu 8, (ffffffff) => 0000ffff, 8 (00000000 00000000) -- lhzu -8, (00000000) => 00000000, -8 (00000000 00000000) -- lhzu -4, (000f423f) => 0000000f, -4 (00000000 00000000) -- lhzu 0, (ffffffff) => 0000ffff, 0 (00000000 00000000) -+ lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000) -+ lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000) -+ lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000) -+ lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000) -+ lhzu -7, (00000000) => 00000000, -7 (00000000 00000000) - - lwz 0, (00000000) => 00000000, 0 (00000000 00000000) -- lwz 4, (000f423f) => 000f423f, 0 (00000000 00000000) -- lwz 8, (ffffffff) => ffffffff, 0 (00000000 00000000) -- lwz -8, (00000000) => 00000000, 0 (00000000 00000000) -- lwz -4, (000f423f) => 000f423f, 0 (00000000 00000000) -- lwz 0, (ffffffff) => ffffffff, 0 (00000000 00000000) -+ lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000) -+ lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000) -+ lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000) -+ lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000) -+ lwz -7, (00000000) => 00000000, 0 (00000000 00000000) - - lwzu 0, (00000000) => 00000000, 0 (00000000 00000000) -- lwzu 4, (000f423f) => 000f423f, 4 (00000000 00000000) -- lwzu 8, (ffffffff) => ffffffff, 8 (00000000 00000000) -- lwzu -8, (00000000) => 00000000, -8 (00000000 00000000) -- lwzu -4, (000f423f) => 000f423f, -4 (00000000 00000000) -- lwzu 0, (ffffffff) => ffffffff, 0 (00000000 00000000) -+ lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000) -+ lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000) -+ lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000) -+ lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000) -+ lwzu -7, (00000000) => 00000000, -7 (00000000 00000000) - - PPC integer load insns with two register args: - lbzx 0 (00000000) => 00000000, 0 (00000000 00000000) -Index: none/tests/ppc32/test_isa_2_06_part1.c -=================================================================== ---- none/tests/ppc32/test_isa_2_06_part1.c.orig -+++ none/tests/ppc32/test_isa_2_06_part1.c -@@ -35,7 +35,12 @@ typedef uint32_t HWord_t; - typedef uint64_t HWord_t; - #endif /* __powerpc64__ */ - --static int errors; -+#ifdef VGP_ppc64le_linux -+#define isLE 1 -+#else -+#define isLE 0 -+#endif -+ - register HWord_t r14 __asm__ ("r14"); - register HWord_t r15 __asm__ ("r15"); - register HWord_t r16 __asm__ ("r16"); -@@ -193,74 +198,14 @@ static void build_fargs_table(void) - } - - --typedef struct ftdiv_test { -- int fra_idx; -- int frb_idx; -- int cr_flags; --} ftdiv_test_args_t; -- - typedef struct fp_test_args { - int fra_idx; - int frb_idx; - int cr_flags; -- unsigned long long dp_bin_result; - } fp_test_args_t; - --unsigned long long xscvuxddp_results[] = { -- 0x43cfec0000000000ULL, -- 0x43d013c000000000ULL, -- 0x4338000000b77501ULL, -- 0x43dffa0000000001ULL, -- 0x4372321456990000ULL, -- 0x0000000000000000ULL, -- 0x43e0000000000000ULL, -- 0x43dffc0000000000ULL, -- 0x43effe0000000000ULL, -- 0x43dffe0000000000ULL, -- 0x43efff0000000000ULL, -- 0x43dffe0000000000ULL, -- 0x43efff0000000000ULL, -- 0x43e00106800000f0ULL, -- 0x43e81a0ca1eb40f6ULL --}; -- --unsigned long long xscvsxddp_results[] = { -- 0x43cfec0000000000ULL, -- 0x43d013c000000000ULL, -- 0x4338000000b77501ULL, -- 0x43dffa0000000001ULL, -- 0x4372321456990000ULL, -- 0x0000000000000000ULL, -- 0xc3e0000000000000ULL, -- 0x43dffc0000000000ULL, -- 0xc330000000000000ULL, -- 0x43dffe0000000000ULL, -- 0xc320000000000002ULL, -- 0x43dffe0000000000ULL, -- 0xc320000000000000ULL, -- 0xc3dffdf2fffffe20ULL, -- 0xc3cf97cd7852fc26ULL, --}; -- --unsigned long long xscvdpsxds_results[] = { -- 0x0000000000000000ULL, -- 0x000000000000003eULL, -- 0x0000000000000000ULL, -- 0x7fffffffffffffffULL, -- 0x0000000000000000ULL, -- 0x0000000000000000ULL, -- 0x0000000000000000ULL, -- 0x7fffffffffffffffULL, -- 0x8000000000000000ULL, -- 0x8000000000000000ULL, -- 0x8000000000000000ULL, -- 0x8000000000000000ULL, -- 0x8000000000000000ULL, -- 0x0000000000000000ULL, -- 0xffffffffffffbe6cULL --}; - --ftdiv_test_args_t ftdiv_tests[] = { -+fp_test_args_t ftdiv_tests[] = { - {0, 1, 0x8}, - {9, 1, 0xa}, - {1, 12, 0xa}, -@@ -278,539 +223,539 @@ ftdiv_test_args_t ftdiv_tests[] = { - }; - - fp_test_args_t xscmpX_tests[] = { -- {8, 8, 0x2, 0ULL}, -- {8, 14, 0x8, 0ULL}, -- {8, 6, 0x8, 0ULL}, -- {8, 5, 0x8, 0ULL}, -- {8, 4, 0x8, 0ULL}, -- {8, 7, 0x8, 0ULL}, -- {8, 9, 0x1, 0ULL}, -- {8, 11, 0x1, 0ULL}, -- {14, 8, 0x4, 0ULL}, -- {14, 14, 0x2, 0ULL}, -- {14, 6, 0x8, 0ULL}, -- {14, 5, 0x8, 0ULL}, -- {14, 4, 0x8, 0ULL}, -- {14, 7, 0x8, 0ULL}, -- {14, 9, 0x1, 0ULL}, -- {14, 11, 0x1, 0ULL}, -- {6, 8, 0x4, 0ULL}, -- {6, 14, 0x4, 0ULL}, -- {6, 6, 0x2, 0ULL}, -- {6, 5, 0x2, 0ULL}, -- {6, 4, 0x8, 0ULL}, -- {6, 7, 0x8, 0ULL}, -- {6, 9, 0x1, 0ULL}, -- {6, 11, 0x1, 0ULL}, -- {5, 8, 0x4, 0ULL}, -- {5, 14, 0x4, 0ULL}, -- {5, 6, 0x2, 0ULL}, -- {5, 5, 0x2, 0ULL}, -- {5, 4, 0x8, 0ULL}, -- {5, 7, 0x8, 0ULL}, -- {5, 9, 0x1, 0ULL}, -- {5, 11, 0x1, 0ULL}, -- {4, 8, 0x4, 0ULL}, -- {4, 14, 0x4, 0ULL}, -- {4, 6, 0x4, 0ULL}, -- {4, 5, 0x4, 0ULL}, -- {4, 1, 0x8, 0ULL}, -- {4, 7, 0x8, 0ULL}, -- {4, 9, 0x1, 0ULL}, -- {4, 11, 0x1, 0ULL}, -- {7, 8, 0x4, 0ULL}, -- {7, 14, 0x4, 0ULL}, -- {7, 6, 0x4, 0ULL}, -- {7, 5, 0x4, 0ULL}, -- {7, 4, 0x4, 0ULL}, -- {7, 7, 0x2, 0ULL}, -- {7, 9, 0x1, 0ULL}, -- {7, 11, 0x1, 0ULL}, -- {10, 8, 0x1, 0ULL}, -- {10, 14, 0x1, 0ULL}, -- {10, 6, 0x1, 0ULL}, -- {10, 5, 0x1, 0ULL}, -- {10, 4, 0x1, 0ULL}, -- {10, 7, 0x1, 0ULL}, -- {10, 9, 0x1, 0ULL}, -- {10, 11, 0x1, 0ULL}, -- {12, 8, 0x1, 0ULL}, -- {12, 14, 0x1, 0ULL}, -- {12, 6, 0x1, 0ULL}, -- {12, 5, 0x1, 0ULL}, -- {12, 4, 0x1, 0ULL}, -- {12, 7, 0x1, 0ULL}, -- {12, 9, 0x1, 0ULL}, -- {12, 11, 0x1, 0ULL}, -+ {8, 8, 0x2}, -+ {8, 14, 0x8}, -+ {8, 6, 0x8}, -+ {8, 5, 0x8}, -+ {8, 4, 0x8}, -+ {8, 7, 0x8}, -+ {8, 9, 0x1}, -+ {8, 11, 0x1}, -+ {14, 8, 0x4}, -+ {14, 14, 0x2}, -+ {14, 6, 0x8}, -+ {14, 5, 0x8}, -+ {14, 4, 0x8}, -+ {14, 7, 0x8}, -+ {14, 9, 0x1}, -+ {14, 11, 0x1}, -+ {6, 8, 0x4}, -+ {6, 14, 0x4}, -+ {6, 6, 0x2}, -+ {6, 5, 0x2}, -+ {6, 4, 0x8}, -+ {6, 7, 0x8}, -+ {6, 9, 0x1}, -+ {6, 11, 0x1}, -+ {5, 8, 0x4}, -+ {5, 14, 0x4}, -+ {5, 6, 0x2}, -+ {5, 5, 0x2}, -+ {5, 4, 0x8}, -+ {5, 7, 0x8}, -+ {5, 9, 0x1}, -+ {5, 11, 0x1}, -+ {4, 8, 0x4}, -+ {4, 14, 0x4}, -+ {4, 6, 0x4}, -+ {4, 5, 0x4}, -+ {4, 1, 0x8}, -+ {4, 7, 0x8}, -+ {4, 9, 0x1}, -+ {4, 11, 0x1}, -+ {7, 8, 0x4}, -+ {7, 14, 0x4}, -+ {7, 6, 0x4}, -+ {7, 5, 0x4}, -+ {7, 4, 0x4}, -+ {7, 7, 0x2}, -+ {7, 9, 0x1}, -+ {7, 11, 0x1}, -+ {10, 8, 0x1}, -+ {10, 14, 0x1}, -+ {10, 6, 0x1}, -+ {10, 5, 0x1}, -+ {10, 4, 0x1}, -+ {10, 7, 0x1}, -+ {10, 9, 0x1}, -+ {10, 11, 0x1}, -+ {12, 8, 0x1}, -+ {12, 14, 0x1}, -+ {12, 6, 0x1}, -+ {12, 5, 0x1}, -+ {12, 4, 0x1}, -+ {12, 7, 0x1}, -+ {12, 9, 0x1}, -+ {12, 11, 0x1}, - }; - - fp_test_args_t xsadddp_tests[] = { -- {8, 8, 0x0, 0xfff0000000000000ULL}, -- {8, 14, 0x0, 0xfff0000000000000ULL}, -- {8, 6, 0x0, 0xfff0000000000000ULL}, -- {8, 5, 0x0, 0xfff0000000000000ULL}, -- {8, 4, 0x0, 0xfff0000000000000ULL}, -- {8, 7, 0x0, 0x7ff8000000000000ULL}, -- {8, 9, 0x0, 0x7fffffffffffffffULL}, -- {8, 11, 0x0, 0x7ff8000000000000ULL}, -- {14, 8, 0x0, 0xfff0000000000000ULL}, -- {14, 14, 0x0, 0xc0e0650f5a07b353ULL}, -- {14, 6, 0x0, 0xc0d0650f5a07b353ULL}, -- {14, 5, 0x0, 0xc0d0650f5a07b353ULL}, -- {14, 4, 0x0, 0xc0d0650f5a07b353ULL}, -- {14, 7, 0x0, 0x7ff0000000000000ULL}, -- {14, 9, 0x0, 0x7fffffffffffffffULL}, -- {14, 11, 0x0, 0x7ff8000000000000ULL}, -- {6, 8, 0x0, 0xfff0000000000000ULL}, -- {6, 14, 0x0, 0xc0d0650f5a07b353ULL}, -- {6, 6, 0x0, 0x8000000000000000ULL}, -- {6, 5, 0x0, 0x0000000000000000ULL}, -- {6, 4, 0x0, 0x0123214569900000ULL}, -- {6, 7, 0x0, 0x7ff0000000000000ULL}, -- {6, 9, 0x0, 0x7fffffffffffffffULL}, -- {6, 11, 0x0, 0x7ff8000000000000ULL}, -- {5, 8, 0x0, 0xfff0000000000000ULL}, -- {5, 14, 0x0, 0xc0d0650f5a07b353ULL}, -- {5, 6, 0x0, 0x0000000000000000ULL}, -- {5, 5, 0x0, 0x0000000000000000ULL}, -- {5, 4, 0x0, 0x0123214569900000ULL}, -- {5, 7, 0x0, 0x7ff0000000000000ULL}, -- {5, 9, 0x0, 0x7fffffffffffffffULL}, -- {5, 11, 0x0, 0x7ff8000000000000ULL}, -- {4, 8, 0x0, 0xfff0000000000000ULL}, -- {4, 14, 0x0, 0xc0d0650f5a07b353ULL}, -- {4, 6, 0x0, 0x0123214569900000ULL}, -- {4, 5, 0x0, 0x0123214569900000ULL}, -- {4, 1, 0x0, 0x404f000000000000ULL}, -- {4, 7, 0x0, 0x7ff0000000000000ULL}, -- {4, 9, 0x0, 0x7fffffffffffffffULL}, -- {4, 11, 0x0, 0x7ff8000000000000ULL}, -- {7, 8, 0x0, 0x7ff8000000000000ULL}, -- {7, 14, 0x0, 0x7ff0000000000000ULL}, -- {7, 6, 0x0, 0x7ff0000000000000ULL}, -- {7, 5, 0x0, 0x7ff0000000000000ULL}, -- {7, 4, 0x0, 0x7ff0000000000000ULL}, -- {7, 7, 0x0, 0x7ff0000000000000ULL}, -- {7, 9, 0x0, 0x7fffffffffffffffULL}, -- {7, 11, 0x0, 0x7ff8000000000000ULL}, -- {10, 8, 0x0, 0xffffffffffffffffULL}, -- {10, 14, 0x0, 0xffffffffffffffffULL}, -- {10, 6, 0x0, 0xffffffffffffffffULL}, -- {10, 5, 0x0, 0xffffffffffffffffULL}, -- {10, 4, 0x0, 0xffffffffffffffffULL}, -- {10, 7, 0x0, 0xffffffffffffffffULL}, -- {10, 9, 0x0, 0xffffffffffffffffULL}, -- {10, 11, 0x0, 0xffffffffffffffffULL}, -- {12, 8, 0x0, 0xfff8000000000000ULL}, -- {12, 14, 0x0, 0xfff8000000000000ULL}, -- {12, 6, 0x0, 0xfff8000000000000ULL}, -- {12, 5, 0x0, 0xfff8000000000000ULL}, -- {12, 4, 0x0, 0xfff8000000000000ULL}, -- {12, 7, 0x0, 0xfff8000000000000ULL}, -- {12, 9, 0x0, 0xfff8000000000000ULL}, -- {12, 11, 0x0, 0xfff8000000000000ULL}, -+ {8, 8, 0x0}, -+ {8, 14, 0x0}, -+ {8, 6, 0x0}, -+ {8, 5, 0x0}, -+ {8, 4, 0x0}, -+ {8, 7, 0x0}, -+ {8, 9, 0x0}, -+ {8, 11, 0x0}, -+ {14, 8, 0x0}, -+ {14, 14, 0x0}, -+ {14, 6, 0x0}, -+ {14, 5, 0x0}, -+ {14, 4, 0x0}, -+ {14, 7, 0x0}, -+ {14, 9, 0x0}, -+ {14, 11, 0x0}, -+ {6, 8, 0x0}, -+ {6, 14, 0x0}, -+ {6, 6, 0x0}, -+ {6, 5, 0x0}, -+ {6, 4, 0x0}, -+ {6, 7, 0x0}, -+ {6, 9, 0x0}, -+ {6, 11, 0x0}, -+ {5, 8, 0x0}, -+ {5, 14, 0x0}, -+ {5, 6, 0x0}, -+ {5, 5, 0x0}, -+ {5, 4, 0x0}, -+ {5, 7, 0x0}, -+ {5, 9, 0x0}, -+ {5, 11, 0x0}, -+ {4, 8, 0x0}, -+ {4, 14, 0x0}, -+ {4, 6, 0x0}, -+ {4, 5, 0x0}, -+ {4, 1, 0x0}, -+ {4, 7, 0x0}, -+ {4, 9, 0x0}, -+ {4, 11, 0x0}, -+ {7, 8, 0x0}, -+ {7, 14, 0x0}, -+ {7, 6, 0x0}, -+ {7, 5, 0x0}, -+ {7, 4, 0x0}, -+ {7, 7, 0x0}, -+ {7, 9, 0x0}, -+ {7, 11, 0x0}, -+ {10, 8, 0x0}, -+ {10, 14, 0x0}, -+ {10, 6, 0x0}, -+ {10, 5, 0x0}, -+ {10, 4, 0x0}, -+ {10, 7, 0x0}, -+ {10, 9, 0x0}, -+ {10, 11, 0x0}, -+ {12, 8, 0x0}, -+ {12, 14, 0x0}, -+ {12, 6, 0x0}, -+ {12, 5, 0x0}, -+ {12, 4, 0x0}, -+ {12, 7, 0x0}, -+ {12, 9, 0x0}, -+ {12, 11, 0x0}, - }; - - fp_test_args_t xsdivdp_tests[] = { -- {8, 8, 0x0, 0x7ff8000000000000ULL}, -- {8, 14, 0x0, 0x7ff0000000000000ULL}, -- {8, 6, 0x0, 0x7ff0000000000000ULL}, -- {8, 5, 0x0, 0xfff0000000000000ULL}, -- {8, 4, 0x0, 0xfff0000000000000ULL}, -- {8, 7, 0x0, 0x7ff8000000000000ULL}, -- {8, 9, 0x0, 0x7fffffffffffffffULL}, -- {8, 11, 0x0, 0x7ff8000000000000ULL}, -- {14, 8, 0x0, 0x0000000000000000ULL}, -- {14, 14, 0x0, 0x3ff0000000000000ULL}, -- {14, 6, 0x0, 0x7ff0000000000000ULL}, -- {14, 5, 0x0, 0xfff0000000000000ULL}, -- {14, 4, 0x0, 0xff9b6cb57ca13c00ULL}, -- {14, 7, 0x0, 0x8000000000000000ULL}, -- {14, 9, 0x0, 0x7fffffffffffffffULL}, -- {14, 11, 0x0, 0x7ff8000000000000ULL}, -- {6, 8, 0x0, 0x0000000000000000ULL}, -- {6, 14, 0x0, 0x0000000000000000ULL}, -- {6, 6, 0x0, 0x7ff8000000000000ULL}, -- {6, 5, 0x0, 0x7ff8000000000000ULL}, -- {6, 4, 0x0, 0x8000000000000000ULL}, -- {6, 7, 0x0, 0x8000000000000000ULL}, -- {6, 9, 0x0, 0x7fffffffffffffffULL}, -- {6, 11, 0x0, 0x7ff8000000000000ULL}, -- {5, 8, 0x0, 0x8000000000000000ULL}, -- {5, 14, 0x0, 0x8000000000000000ULL}, -- {5, 6, 0x0, 0x7ff8000000000000ULL}, -- {5, 5, 0x0, 0x7ff8000000000000ULL}, -- {5, 4, 0x0, 0x0000000000000000ULL}, -- {5, 7, 0x0, 0x0000000000000000ULL}, -- {5, 9, 0x0, 0x7fffffffffffffffULL}, -- {5, 11, 0x0, 0x7ff8000000000000ULL}, -- {4, 8, 0x0, 0x8000000000000000ULL}, -- {4, 14, 0x0, 0x8042ab59d8b6ec87ULL}, -- {4, 6, 0x0, 0xfff0000000000000ULL}, -- {4, 5, 0x0, 0x7ff0000000000000ULL}, -- {4, 1, 0x0, 0x00c3bf3f64b5ad6bULL}, -- {4, 7, 0x0, 0x0000000000000000ULL}, -- {4, 9, 0x0, 0x7fffffffffffffffULL}, -- {4, 11, 0x0, 0x7ff8000000000000ULL}, -- {7, 8, 0x0, 0x7ff8000000000000ULL}, -- {7, 14, 0x0, 0xfff0000000000000ULL}, -- {7, 6, 0x0, 0xfff0000000000000ULL}, -- {7, 5, 0x0, 0x7ff0000000000000ULL}, -- {7, 4, 0x0, 0x7ff0000000000000ULL}, -- {7, 7, 0x0, 0x7ff8000000000000ULL}, -- {7, 9, 0x0, 0x7fffffffffffffffULL}, -- {7, 11, 0x0, 0x7ff8000000000000ULL}, -- {10, 8, 0x0, 0xffffffffffffffffULL}, -- {10, 14, 0x0, 0xffffffffffffffffULL}, -- {10, 6, 0x0, 0xffffffffffffffffULL}, -- {10, 5, 0x0, 0xffffffffffffffffULL}, -- {10, 4, 0x0, 0xffffffffffffffffULL}, -- {10, 7, 0x0, 0xffffffffffffffffULL}, -- {10, 9, 0x0, 0xffffffffffffffffULL}, -- {10, 11, 0x0, 0xffffffffffffffffULL}, -- {12, 8, 0x0, 0xfff8000000000000ULL}, -- {12, 14, 0x0, 0xfff8000000000000ULL}, -- {12, 6, 0x0, 0xfff8000000000000ULL}, -- {12, 5, 0x0, 0xfff8000000000000ULL}, -- {12, 4, 0x0, 0xfff8000000000000ULL}, -- {12, 7, 0x0, 0xfff8000000000000ULL}, -- {12, 9, 0x0, 0xfff8000000000000ULL}, -- {12, 11, 0x0, 0xfff8000000000000ULL}, -+ {8, 8, 0x0}, -+ {8, 14, 0x0}, -+ {8, 6, 0x0}, -+ {8, 5, 0x0}, -+ {8, 4, 0x0}, -+ {8, 7, 0x0}, -+ {8, 9, 0x0}, -+ {8, 11, 0x0}, -+ {14, 8, 0x0}, -+ {14, 14, 0x0}, -+ {14, 6, 0x0}, -+ {14, 5, 0x0}, -+ {14, 4, 0x0}, -+ {14, 7, 0x0}, -+ {14, 9, 0x0}, -+ {14, 11, 0x0}, -+ {6, 8, 0x0}, -+ {6, 14, 0x0}, -+ {6, 6, 0x0}, -+ {6, 5, 0x0}, -+ {6, 4, 0x0}, -+ {6, 7, 0x0}, -+ {6, 9, 0x0}, -+ {6, 11, 0x0}, -+ {5, 8, 0x0}, -+ {5, 14, 0x0}, -+ {5, 6, 0x0}, -+ {5, 5, 0x0}, -+ {5, 4, 0x0}, -+ {5, 7, 0x0}, -+ {5, 9, 0x0}, -+ {5, 11, 0x0}, -+ {4, 8, 0x0}, -+ {4, 14, 0x0}, -+ {4, 6, 0x0}, -+ {4, 5, 0x0}, -+ {4, 1, 0x0}, -+ {4, 7, 0x0}, -+ {4, 9, 0x0}, -+ {4, 11, 0x0}, -+ {7, 8, 0x0}, -+ {7, 14, 0x0}, -+ {7, 6, 0x0}, -+ {7, 5, 0x0}, -+ {7, 4, 0x0}, -+ {7, 7, 0x0}, -+ {7, 9, 0x0}, -+ {7, 11, 0x0}, -+ {10, 8, 0x0}, -+ {10, 14, 0x0}, -+ {10, 6, 0x0}, -+ {10, 5, 0x0}, -+ {10, 4, 0x0}, -+ {10, 7, 0x0}, -+ {10, 9, 0x0}, -+ {10, 11, 0x0}, -+ {12, 8, 0x0}, -+ {12, 14, 0x0}, -+ {12, 6, 0x0}, -+ {12, 5, 0x0}, -+ {12, 4, 0x0}, -+ {12, 7, 0x0}, -+ {12, 9, 0x0}, -+ {12, 11, 0x0}, - }; - - fp_test_args_t xsmaddXdp_tests[] = { -- {8, 8, 0x0, 0x7ff8000000000000ULL}, -- {8, 14, 0x0, 0xfff0000000000000ULL}, -- {8, 6, 0x0, 0x7ff0000000000000ULL}, -- {8, 5, 0x0, 0xfff0000000000000ULL}, -- {8, 4, 0x0, 0x7ff0000000000000ULL}, -- {8, 7, 0x0, 0x7ff8000000000000ULL}, -- {8, 9, 0x0, 0x7fffffffffffffffULL}, -- {8, 11, 0x0, 0x7ff8000000000000ULL}, -- {14, 8, 0x0, 0xfff0000000000000ULL}, -- {14, 14, 0x0, 0xc0d0650f5a07b353ULL}, -- {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL}, -- {14, 5, 0x0, 0x82039a19ca8fcb5fULL}, -- {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL}, -- {14, 7, 0x0, 0x7ff0000000000000ULL}, -- {14, 9, 0x0, 0x7fffffffffffffffULL}, -- {14, 11, 0x0, 0x7ff8000000000000ULL}, -- {6, 8, 0x0, 0xfff0000000000000ULL}, -- {6, 14, 0x0, 0xc0d0650f5a07b353ULL}, -- {6, 6, 0x0, 0x0000000000000000ULL}, -- {6, 5, 0x0, 0x0000000000000000ULL}, -- {6, 4, 0x0, 0x0123214569900000ULL}, -- {6, 7, 0x0, 0x7ff0000000000000ULL}, -- {6, 9, 0x0, 0x7fffffffffffffffULL}, -- {6, 11, 0x0, 0x7ff8000000000000ULL}, -- {5, 8, 0x0, 0xfff0000000000000ULL}, -- {5, 14, 0x0, 0xc0d0650f5a07b353ULL}, -- {5, 6, 0x0, 0x8000000000000000ULL}, -- {5, 5, 0x0, 0x0000000000000000ULL}, -- {5, 4, 0x0, 0x0123214569900000ULL}, -- {5, 7, 0x0, 0x7ff0000000000000ULL}, -- {5, 9, 0x0, 0x7fffffffffffffffULL}, -- {5, 11, 0x0, 0x7ff8000000000000ULL}, -- {4, 8, 0x0, 0xfff0000000000000ULL}, -- {4, 14, 0x0, 0xc0d0650f5a07b353ULL}, -- {4, 6, 0x0, 0x82039a19ca8fcb5fULL}, -- {4, 5, 0x0, 0x0000000000000000ULL}, -- {4, 1, 0x0, 0x404f000000000000ULL}, -- {4, 7, 0x0, 0x7ff0000000000000ULL}, -- {4, 9, 0x0, 0x7fffffffffffffffULL}, -- {4, 11, 0x0, 0x7ff8000000000000ULL}, -- {7, 8, 0x0, 0xfff0000000000000ULL}, -- {7, 14, 0x0, 0x7ff0000000000000ULL}, -- {7, 6, 0x0, 0xfff0000000000000ULL}, -- {7, 5, 0x0, 0x7ff0000000000000ULL}, -- {7, 4, 0x0, 0xfff0000000000000ULL}, -- {7, 7, 0x0, 0x7ff0000000000000ULL}, -- {7, 9, 0x0, 0x7fffffffffffffffULL}, -- {7, 11, 0x0, 0x7ff8000000000000ULL}, -- {10, 8, 0x0, 0xffffffffffffffffULL}, -- {10, 14, 0x0, 0xffffffffffffffffULL}, -- {10, 6, 0x0, 0xffffffffffffffffULL}, -- {10, 5, 0x0, 0xffffffffffffffffULL}, -- {10, 4, 0x0, 0xffffffffffffffffULL}, -- {10, 7, 0x0, 0xffffffffffffffffULL}, -- {10, 9, 0x0, 0xffffffffffffffffULL}, -- {10, 11, 0x0, 0xffffffffffffffffULL}, -- {12, 8, 0x0, 0xfff8000000000000ULL}, -- {12, 14, 0x0, 0xfff8000000000000ULL}, -- {12, 6, 0x0, 0xfff8000000000000ULL}, -- {12, 5, 0x0, 0xfff8000000000000ULL}, -- {12, 4, 0x0, 0xfff8000000000000ULL}, -- {12, 7, 0x0, 0xfff8000000000000ULL}, -- {12, 9, 0x0, 0xfff8000000000000ULL}, -- {12, 11, 0x0, 0xfff8000000000000ULL}, -+ {8, 8, 0x0}, -+ {8, 14, 0x0}, -+ {8, 6, 0x0}, -+ {8, 5, 0x0}, -+ {8, 4, 0x0}, -+ {8, 7, 0x0}, -+ {8, 9, 0x0}, -+ {8, 11, 0x0}, -+ {14, 8, 0x0}, -+ {14, 14, 0x0}, -+ {14, 6, 0x0}, -+ {14, 5, 0x0}, -+ {14, 4, 0x0}, -+ {14, 7, 0x0}, -+ {14, 9, 0x0}, -+ {14, 11, 0x0}, -+ {6, 8, 0x0}, -+ {6, 14, 0x0}, -+ {6, 6, 0x0}, -+ {6, 5, 0x0}, -+ {6, 4, 0x0}, -+ {6, 7, 0x0}, -+ {6, 9, 0x0}, -+ {6, 11, 0x0}, -+ {5, 8, 0x0}, -+ {5, 14, 0x0}, -+ {5, 6, 0x0}, -+ {5, 5, 0x0}, -+ {5, 4, 0x0}, -+ {5, 7, 0x0}, -+ {5, 9, 0x0}, -+ {5, 11, 0x0}, -+ {4, 8, 0x0}, -+ {4, 14, 0x0}, -+ {4, 6, 0x0}, -+ {4, 5, 0x0}, -+ {4, 1, 0x0}, -+ {4, 7, 0x0}, -+ {4, 9, 0x0}, -+ {4, 11, 0x0}, -+ {7, 8, 0x0}, -+ {7, 14, 0x0}, -+ {7, 6, 0x0}, -+ {7, 5, 0x0}, -+ {7, 4, 0x0}, -+ {7, 7, 0x0}, -+ {7, 9, 0x0}, -+ {7, 11, 0x0}, -+ {10, 8, 0x0}, -+ {10, 14, 0x0}, -+ {10, 6, 0x0}, -+ {10, 5, 0x0}, -+ {10, 4, 0x0}, -+ {10, 7, 0x0}, -+ {10, 9, 0x0}, -+ {10, 11, 0x0}, -+ {12, 8, 0x0}, -+ {12, 14, 0x0}, -+ {12, 6, 0x0}, -+ {12, 5, 0x0}, -+ {12, 4, 0x0}, -+ {12, 7, 0x0}, -+ {12, 9, 0x0}, -+ {12, 11, 0x0}, - }; - - fp_test_args_t xsmsubXdp_tests[] = { -- {8, 8, 0x0, 0x7ff0000000000000ULL}, -- {8, 14, 0x0, 0xfff0000000000000ULL}, -- {8, 6, 0x0, 0x7ff0000000000000ULL}, -- {8, 5, 0x0, 0xfff0000000000000ULL}, -- {8, 4, 0x0, 0x7ff0000000000000ULL}, -- {8, 7, 0x0, 0xfff0000000000000ULL}, -- {8, 9, 0x0, 0x7fffffffffffffffULL}, -- {8, 11, 0x0, 0x7ff8000000000000ULL}, -- {14, 8, 0x0, 0x7ff0000000000000ULL}, -- {14, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL}, -- {14, 5, 0x0, 0x82039a19ca8fcb5fULL}, -- {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL}, -- {14, 7, 0x0, 0xfff0000000000000ULL}, -- {14, 9, 0x0, 0x7fffffffffffffffULL}, -- {14, 11, 0x0, 0x7ff8000000000000ULL}, -- {6, 8, 0x0, 0x7ff0000000000000ULL}, -- {6, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {6, 6, 0x0, 0x0000000000000000ULL}, -- {6, 5, 0x0, 0x8000000000000000ULL}, -- {6, 4, 0x0, 0x8123214569900000ULL}, -- {6, 7, 0x0, 0xfff0000000000000ULL}, -- {6, 9, 0x0, 0x7fffffffffffffffULL}, -- {6, 11, 0x0, 0x7ff8000000000000ULL}, -- {5, 8, 0x0, 0x7ff0000000000000ULL}, -- {5, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {5, 6, 0x0, 0x0000000000000000ULL}, -- {5, 5, 0x0, 0x0000000000000000ULL}, -- {5, 4, 0x0, 0x8123214569900000ULL}, -- {5, 7, 0x0, 0xfff0000000000000ULL}, -- {5, 9, 0x0, 0x7fffffffffffffffULL}, -- {5, 11, 0x0, 0x7ff8000000000000ULL}, -- {4, 8, 0x0, 0x7ff0000000000000ULL}, -- {4, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {4, 6, 0x0, 0x82039a19ca8fcb5fULL}, -- {4, 5, 0x0, 0x0000000000000000ULL}, -- {4, 1, 0x0, 0xc04f000000000000ULL}, -- {4, 7, 0x0, 0xfff0000000000000ULL}, -- {4, 9, 0x0, 0x7fffffffffffffffULL}, -- {4, 11, 0x0, 0x7ff8000000000000ULL}, -- {7, 8, 0x0, 0x7ff8000000000000ULL}, -- {7, 14, 0x0, 0x7ff0000000000000ULL}, -- {7, 6, 0x0, 0xfff0000000000000ULL}, -- {7, 5, 0x0, 0x7ff0000000000000ULL}, -- {7, 4, 0x0, 0xfff0000000000000ULL}, -- {7, 7, 0x0, 0x7ff8000000000000ULL}, -- {7, 9, 0x0, 0x7fffffffffffffffULL}, -- {7, 11, 0x0, 0x7ff8000000000000ULL}, -- {10, 8, 0x0, 0xffffffffffffffffULL}, -- {10, 14, 0x0, 0xffffffffffffffffULL}, -- {10, 6, 0x0, 0xffffffffffffffffULL}, -- {10, 5, 0x0, 0xffffffffffffffffULL}, -- {10, 4, 0x0, 0xffffffffffffffffULL}, -- {10, 7, 0x0, 0xffffffffffffffffULL}, -- {10, 9, 0x0, 0xffffffffffffffffULL}, -- {10, 11, 0x0, 0xffffffffffffffffULL}, -- {12, 8, 0x0, 0xfff8000000000000ULL}, -- {12, 14, 0x0, 0xfff8000000000000ULL}, -- {12, 6, 0x0, 0xfff8000000000000ULL}, -- {12, 5, 0x0, 0xfff8000000000000ULL}, -- {12, 4, 0x0, 0xfff8000000000000ULL}, -- {12, 7, 0x0, 0xfff8000000000000ULL}, -- {12, 9, 0x0, 0xfff8000000000000ULL}, -- {12, 11, 0x0, 0xfff8000000000000ULL}, -+ {8, 8, 0x0}, -+ {8, 14, 0x0}, -+ {8, 6, 0x0}, -+ {8, 5, 0x0}, -+ {8, 4, 0x0}, -+ {8, 7, 0x0}, -+ {8, 9, 0x0}, -+ {8, 11, 0x0}, -+ {14, 8, 0x0}, -+ {14, 14, 0x0}, -+ {14, 6, 0x0}, -+ {14, 5, 0x0}, -+ {14, 4, 0x0}, -+ {14, 7, 0x0}, -+ {14, 9, 0x0}, -+ {14, 11, 0x0}, -+ {6, 8, 0x0}, -+ {6, 14, 0x0}, -+ {6, 6, 0x0}, -+ {6, 5, 0x0}, -+ {6, 4, 0x0}, -+ {6, 7, 0x0}, -+ {6, 9, 0x0}, -+ {6, 11, 0x0}, -+ {5, 8, 0x0}, -+ {5, 14, 0x0}, -+ {5, 6, 0x0}, -+ {5, 5, 0x0}, -+ {5, 4, 0x0}, -+ {5, 7, 0x0}, -+ {5, 9, 0x0}, -+ {5, 11, 0x0}, -+ {4, 8, 0x0}, -+ {4, 14, 0x0}, -+ {4, 6, 0x0}, -+ {4, 5, 0x0}, -+ {4, 1, 0x0}, -+ {4, 7, 0x0}, -+ {4, 9, 0x0}, -+ {4, 11, 0x0}, -+ {7, 8, 0x0}, -+ {7, 14, 0x0}, -+ {7, 6, 0x0}, -+ {7, 5, 0x0}, -+ {7, 4, 0x0}, -+ {7, 7, 0x0}, -+ {7, 9, 0x0}, -+ {7, 11, 0x0}, -+ {10, 8, 0x0}, -+ {10, 14, 0x0}, -+ {10, 6, 0x0}, -+ {10, 5, 0x0}, -+ {10, 4, 0x0}, -+ {10, 7, 0x0}, -+ {10, 9, 0x0}, -+ {10, 11, 0x0}, -+ {12, 8, 0x0}, -+ {12, 14, 0x0}, -+ {12, 6, 0x0}, -+ {12, 5, 0x0}, -+ {12, 4, 0x0}, -+ {12, 7, 0x0}, -+ {12, 9, 0x0}, -+ {12, 11, 0x0}, - }; - - fp_test_args_t xsnmaddXdp_tests[] = { -- {8, 8, 0x0, 0x7ff8000000000000ULL}, -- {8, 14, 0x0, 0x7ff0000000000000ULL}, -- {8, 6, 0x0, 0xfff0000000000000ULL}, -- {8, 5, 0x0, 0x7ff0000000000000ULL}, -- {8, 4, 0x0, 0xfff0000000000000ULL}, -- {8, 7, 0x0, 0x7ff8000000000000ULL}, -- {8, 9, 0x0, 0x7fffffffffffffffULL}, -- {8, 11, 0x0, 0x7ff8000000000000ULL}, -- {14, 8, 0x0, 0x7ff0000000000000ULL}, -- {14, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {14, 6, 0x0, 0xc1b0cc9d05eec2a7ULL}, -- {14, 5, 0x0, 0x02039a19ca8fcb5fULL}, -- {14, 4, 0x0, 0xc1b0cc9d05eec2a7ULL}, -- {14, 7, 0x0, 0xfff0000000000000ULL}, -- {14, 9, 0x0, 0x7fffffffffffffffULL}, -- {14, 11, 0x0, 0x7ff8000000000000ULL}, -- {6, 8, 0x0, 0x7ff0000000000000ULL}, -- {6, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {6, 6, 0x0, 0x8000000000000000ULL}, -- {6, 5, 0x0, 0x8000000000000000ULL}, -- {6, 4, 0x0, 0x8123214569900000ULL}, -- {6, 7, 0x0, 0xfff0000000000000ULL}, -- {6, 9, 0x0, 0x7fffffffffffffffULL}, -- {6, 11, 0x0, 0x7ff8000000000000ULL}, -- {5, 8, 0x0, 0x7ff0000000000000ULL}, -- {5, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {5, 6, 0x0, 0x0000000000000000ULL}, -- {5, 5, 0x0, 0x8000000000000000ULL}, -- {5, 4, 0x0, 0x8123214569900000ULL}, -- {5, 7, 0x0, 0xfff0000000000000ULL}, -- {5, 9, 0x0, 0x7fffffffffffffffULL}, -- {5, 11, 0x0, 0x7ff8000000000000ULL}, -- {4, 8, 0x0, 0x7ff0000000000000ULL}, -- {4, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {4, 6, 0x0, 0x02039a19ca8fcb5fULL}, -- {4, 5, 0x0, 0x8000000000000000ULL}, -- {4, 1, 0x0, 0xc04f000000000000ULL}, -- {4, 7, 0x0, 0xfff0000000000000ULL}, -- {4, 9, 0x0, 0x7fffffffffffffffULL}, -- {4, 11, 0x0, 0x7ff8000000000000ULL}, -- {7, 8, 0x0, 0x7ff0000000000000ULL}, -- {7, 14, 0x0, 0xfff0000000000000ULL}, -- {7, 6, 0x0, 0x7ff0000000000000ULL}, -- {7, 5, 0x0, 0xfff0000000000000ULL}, -- {7, 4, 0x0, 0x7ff0000000000000ULL}, -- {7, 7, 0x0, 0xfff0000000000000ULL}, -- {7, 9, 0x0, 0x7fffffffffffffffULL}, -- {7, 11, 0x0, 0x7ff8000000000000ULL}, -- {10, 8, 0x0, 0xffffffffffffffffULL}, -- {10, 14, 0x0, 0xffffffffffffffffULL}, -- {10, 6, 0x0, 0xffffffffffffffffULL}, -- {10, 5, 0x0, 0xffffffffffffffffULL}, -- {10, 4, 0x0, 0xffffffffffffffffULL}, -- {10, 7, 0x0, 0xffffffffffffffffULL}, -- {10, 9, 0x0, 0xffffffffffffffffULL}, -- {10, 11, 0x0, 0xffffffffffffffffULL}, -- {12, 8, 0x0, 0xfff8000000000000ULL}, -- {12, 14, 0x0, 0xfff8000000000000ULL}, -- {12, 6, 0x0, 0xfff8000000000000ULL}, -- {12, 5, 0x0, 0xfff8000000000000ULL}, -- {12, 4, 0x0, 0xfff8000000000000ULL}, -- {12, 7, 0x0, 0xfff8000000000000ULL}, -- {12, 9, 0x0, 0xfff8000000000000ULL}, -- {12, 11, 0x0, 0xfff8000000000000ULL}, -+ {8, 8, 0x0}, -+ {8, 14, 0x0}, -+ {8, 6, 0x0}, -+ {8, 5, 0x0}, -+ {8, 4, 0x0}, -+ {8, 7, 0x0}, -+ {8, 9, 0x0}, -+ {8, 11, 0x0}, -+ {14, 8, 0x0}, -+ {14, 14, 0x0}, -+ {14, 6, 0x0}, -+ {14, 5, 0x0}, -+ {14, 4, 0x0}, -+ {14, 7, 0x0}, -+ {14, 9, 0x0}, -+ {14, 11, 0x0}, -+ {6, 8, 0x0}, -+ {6, 14, 0x0}, -+ {6, 6, 0x0}, -+ {6, 5, 0x0}, -+ {6, 4, 0x0}, -+ {6, 7, 0x0}, -+ {6, 9, 0x0}, -+ {6, 11, 0x0}, -+ {5, 8, 0x0}, -+ {5, 14, 0x0}, -+ {5, 6, 0x0}, -+ {5, 5, 0x0}, -+ {5, 4, 0x0}, -+ {5, 7, 0x0}, -+ {5, 9, 0x0}, -+ {5, 11, 0x0}, -+ {4, 8, 0x0}, -+ {4, 14, 0x0}, -+ {4, 6, 0x0}, -+ {4, 5, 0x0}, -+ {4, 1, 0x0}, -+ {4, 7, 0x0}, -+ {4, 9, 0x0}, -+ {4, 11, 0x0}, -+ {7, 8, 0x0}, -+ {7, 14, 0x0}, -+ {7, 6, 0x0}, -+ {7, 5, 0x0}, -+ {7, 4, 0x0}, -+ {7, 7, 0x0}, -+ {7, 9, 0x0}, -+ {7, 11, 0x0}, -+ {10, 8, 0x0}, -+ {10, 14, 0x0}, -+ {10, 6, 0x0}, -+ {10, 5, 0x0}, -+ {10, 4, 0x0}, -+ {10, 7, 0x0}, -+ {10, 9, 0x0}, -+ {10, 11, 0x0}, -+ {12, 8, 0x0}, -+ {12, 14, 0x0}, -+ {12, 6, 0x0}, -+ {12, 5, 0x0}, -+ {12, 4, 0x0}, -+ {12, 7, 0x0}, -+ {12, 9, 0x0}, -+ {12, 11, 0x0}, - }; - - fp_test_args_t xsmuldp_tests[] = { -- {8, 8, 0x0, 0x7ff0000000000000ULL}, -- {8, 14, 0x0, 0x7ff0000000000000ULL}, -- {8, 6, 0x0, 0x7ff8000000000000ULL}, -- {8, 5, 0x0, 0x7ff8000000000000ULL}, -- {8, 4, 0x0, 0xfff0000000000000ULL}, -- {8, 7, 0x0, 0xfff0000000000000ULL}, -- {8, 9, 0x0, 0x7fffffffffffffffULL}, -- {8, 11, 0x0, 0x7ff8000000000000ULL}, -- {14, 8, 0x0, 0x7ff0000000000000ULL}, -- {14, 14, 0x0, 0x41b0cc9d05eec2a7ULL}, -- {14, 6, 0x0, 0x0000000000000000ULL}, -- {14, 5, 0x0, 0x8000000000000000ULL}, -- {14, 4, 0x0, 0x82039a19ca8fcb5fULL}, -- {14, 7, 0x0, 0xfff0000000000000ULL}, -- {14, 9, 0x0, 0x7fffffffffffffffULL}, -- {14, 11, 0x0, 0x7ff8000000000000ULL}, -- {6, 8, 0x0, 0x7ff8000000000000ULL}, -- {6, 14, 0x0, 0x0000000000000000ULL}, -- {6, 6, 0x0, 0x0000000000000000ULL}, -- {6, 5, 0x0, 0x8000000000000000ULL}, -- {6, 4, 0x0, 0x8000000000000000ULL}, -- {6, 7, 0x0, 0x7ff8000000000000ULL}, -- {6, 9, 0x0, 0x7fffffffffffffffULL}, -- {6, 11, 0x0, 0x7ff8000000000000ULL}, -- {5, 8, 0x0, 0x7ff8000000000000ULL}, -- {5, 14, 0x0, 0x8000000000000000ULL}, -- {5, 6, 0x0, 0x8000000000000000ULL}, -- {5, 5, 0x0, 0x0000000000000000ULL}, -- {5, 4, 0x0, 0x0000000000000000ULL}, -- {5, 7, 0x0, 0x7ff8000000000000ULL}, -- {5, 9, 0x0, 0x7fffffffffffffffULL}, -- {5, 11, 0x0, 0x7ff8000000000000ULL}, -- {4, 8, 0x0, 0xfff0000000000000ULL}, -- {4, 14, 0x0, 0x82039a19ca8fcb5fULL}, -- {4, 6, 0x0, 0x8000000000000000ULL}, -- {4, 5, 0x0, 0x0000000000000000ULL}, -- {4, 1, 0x0, 0x0182883b3e438000ULL}, -- {4, 7, 0x0, 0x7ff0000000000000ULL}, -- {4, 9, 0x0, 0x7fffffffffffffffULL}, -- {4, 11, 0x0, 0x7ff8000000000000ULL}, -- {7, 8, 0x0, 0xfff0000000000000ULL}, -- {7, 14, 0x0, 0xfff0000000000000ULL}, -- {7, 6, 0x0, 0x7ff8000000000000ULL}, -- {7, 5, 0x0, 0x7ff8000000000000ULL}, -- {7, 4, 0x0, 0x7ff0000000000000ULL}, -- {7, 7, 0x0, 0x7ff0000000000000ULL}, -- {7, 9, 0x0, 0x7fffffffffffffffULL}, -- {7, 11, 0x0, 0x7ff8000000000000ULL}, -- {10, 8, 0x0, 0xffffffffffffffffULL}, -- {10, 14, 0x0, 0xffffffffffffffffULL}, -- {10, 6, 0x0, 0xffffffffffffffffULL}, -- {10, 5, 0x0, 0xffffffffffffffffULL}, -- {10, 4, 0x0, 0xffffffffffffffffULL}, -- {10, 7, 0x0, 0xffffffffffffffffULL}, -- {10, 9, 0x0, 0xffffffffffffffffULL}, -- {10, 11, 0x0, 0xffffffffffffffffULL}, -- {12, 8, 0x0, 0xfff8000000000000ULL}, -- {12, 14, 0x0, 0xfff8000000000000ULL}, -- {12, 6, 0x0, 0xfff8000000000000ULL}, -- {12, 5, 0x0, 0xfff8000000000000ULL}, -- {12, 4, 0x0, 0xfff8000000000000ULL}, -- {12, 7, 0x0, 0xfff8000000000000ULL}, -- {12, 9, 0x0, 0xfff8000000000000ULL}, -- {12, 11, 0x0, 0xfff8000000000000ULL}, -+ {8, 8, 0x0}, -+ {8, 14, 0x0}, -+ {8, 6, 0x0}, -+ {8, 5, 0x0}, -+ {8, 4, 0x0}, -+ {8, 7, 0x0}, -+ {8, 9, 0x0}, -+ {8, 11, 0x0}, -+ {14, 8, 0x0}, -+ {14, 14, 0x0}, -+ {14, 6, 0x0}, -+ {14, 5, 0x0}, -+ {14, 4, 0x0}, -+ {14, 7, 0x0}, -+ {14, 9, 0x0}, -+ {14, 11, 0x0}, -+ {6, 8, 0x0}, -+ {6, 14, 0x0}, -+ {6, 6, 0x0}, -+ {6, 5, 0x0}, -+ {6, 4, 0x0}, -+ {6, 7, 0x0}, -+ {6, 9, 0x0}, -+ {6, 11, 0x0}, -+ {5, 8, 0x0}, -+ {5, 14, 0x0}, -+ {5, 6, 0x0}, -+ {5, 5, 0x0}, -+ {5, 4, 0x0}, -+ {5, 7, 0x0}, -+ {5, 9, 0x0}, -+ {5, 11, 0x0}, -+ {4, 8, 0x0}, -+ {4, 14, 0x0}, -+ {4, 6, 0x0}, -+ {4, 5, 0x0}, -+ {4, 1, 0x0}, -+ {4, 7, 0x0}, -+ {4, 9, 0x0}, -+ {4, 11, 0x0}, -+ {7, 8, 0x0}, -+ {7, 14, 0x0}, -+ {7, 6, 0x0}, -+ {7, 5, 0x0}, -+ {7, 4, 0x0}, -+ {7, 7, 0x0}, -+ {7, 9, 0x0}, -+ {7, 11, 0x0}, -+ {10, 8, 0x0}, -+ {10, 14, 0x0}, -+ {10, 6, 0x0}, -+ {10, 5, 0x0}, -+ {10, 4, 0x0}, -+ {10, 7, 0x0}, -+ {10, 9, 0x0}, -+ {10, 11, 0x0}, -+ {12, 8, 0x0}, -+ {12, 14, 0x0}, -+ {12, 6, 0x0}, -+ {12, 5, 0x0}, -+ {12, 4, 0x0}, -+ {12, 7, 0x0}, -+ {12, 9, 0x0}, -+ {12, 11, 0x0}, - }; - - fp_test_args_t xssubdp_tests[] = { -- {8, 8, 0x0, 0x7ff8000000000000ULL}, -- {8, 14, 0x0, 0xfff0000000000000ULL}, -- {8, 6, 0x0, 0xfff0000000000000ULL}, -- {8, 5, 0x0, 0xfff0000000000000ULL}, -- {8, 4, 0x0, 0xfff0000000000000ULL}, -- {8, 7, 0x0, 0xfff0000000000000ULL}, -- {8, 9, 0x0, 0x7fffffffffffffffULL}, -- {8, 11, 0x0, 0x7ff8000000000000ULL}, -- {14, 8, 0x0, 0x7ff0000000000000ULL}, -- {14, 14, 0x0, 0x0000000000000000ULL}, -- {14, 6, 0x0, 0xc0d0650f5a07b353ULL}, -- {14, 5, 0x0, 0xc0d0650f5a07b353ULL}, -- {14, 4, 0x0, 0xc0d0650f5a07b353ULL}, -- {14, 7, 0x0, 0xfff0000000000000ULL}, -- {14, 9, 0x0, 0x7fffffffffffffffULL}, -- {14, 11, 0x0, 0x7ff8000000000000ULL}, -- {6, 8, 0x0, 0x7ff0000000000000ULL}, -- {6, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {6, 6, 0x0, 0x0000000000000000ULL}, -- {6, 5, 0x0, 0x8000000000000000ULL}, -- {6, 4, 0x0, 0x8123214569900000ULL}, -- {6, 7, 0x0, 0xfff0000000000000ULL}, -- {6, 9, 0x0, 0x7fffffffffffffffULL}, -- {6, 11, 0x0, 0x7ff8000000000000ULL}, -- {5, 8, 0x0, 0x7ff0000000000000ULL}, -- {5, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {5, 6, 0x0, 0x0000000000000000ULL}, -- {5, 5, 0x0, 0x0000000000000000ULL}, -- {5, 4, 0x0, 0x8123214569900000ULL}, -- {5, 7, 0x0, 0xfff0000000000000ULL}, -- {5, 9, 0x0, 0x7fffffffffffffffULL}, -- {5, 11, 0x0, 0x7ff8000000000000ULL}, -- {4, 8, 0x0, 0x7ff0000000000000ULL}, -- {4, 14, 0x0, 0x40d0650f5a07b353ULL}, -- {4, 6, 0x0, 0x0123214569900000ULL}, -- {4, 5, 0x0, 0x0123214569900000ULL}, -- {4, 1, 0x0, 0xc04f000000000000ULL}, -- {4, 7, 0x0, 0xfff0000000000000ULL}, -- {4, 9, 0x0, 0x7fffffffffffffffULL}, -- {4, 11, 0x0, 0x7ff8000000000000ULL}, -- {7, 8, 0x0, 0x7ff0000000000000ULL}, -- {7, 14, 0x0, 0x7ff0000000000000ULL}, -- {7, 6, 0x0, 0x7ff0000000000000ULL}, -- {7, 5, 0x0, 0x7ff0000000000000ULL}, -- {7, 4, 0x0, 0x7ff0000000000000ULL}, -- {7, 7, 0x0, 0x7ff8000000000000ULL}, -- {7, 9, 0x0, 0x7fffffffffffffffULL}, -- {7, 11, 0x0, 0x7ff8000000000000ULL}, -- {10, 8, 0x0, 0xffffffffffffffffULL}, -- {10, 14, 0x0, 0xffffffffffffffffULL}, -- {10, 6, 0x0, 0xffffffffffffffffULL}, -- {10, 5, 0x0, 0xffffffffffffffffULL}, -- {10, 4, 0x0, 0xffffffffffffffffULL}, -- {10, 7, 0x0, 0xffffffffffffffffULL}, -- {10, 9, 0x0, 0xffffffffffffffffULL}, -- {10, 11, 0x0, 0xffffffffffffffffULL}, -- {12, 8, 0x0, 0xfff8000000000000ULL}, -- {12, 14, 0x0, 0xfff8000000000000ULL}, -- {12, 6, 0x0, 0xfff8000000000000ULL}, -- {12, 5, 0x0, 0xfff8000000000000ULL}, -- {12, 4, 0x0, 0xfff8000000000000ULL}, -- {12, 7, 0x0, 0xfff8000000000000ULL}, -- {12, 9, 0x0, 0xfff8000000000000ULL}, -- {12, 11, 0x0, 0xfff8000000000000ULL}, -+ {8, 8, 0x0}, -+ {8, 14, 0x0}, -+ {8, 6, 0x0}, -+ {8, 5, 0x0}, -+ {8, 4, 0x0}, -+ {8, 7, 0x0}, -+ {8, 9, 0x0}, -+ {8, 11, 0x0}, -+ {14, 8, 0x0}, -+ {14, 14, 0x0}, -+ {14, 6, 0x0}, -+ {14, 5, 0x0}, -+ {14, 4, 0x0}, -+ {14, 7, 0x0}, -+ {14, 9, 0x0}, -+ {14, 11, 0x0}, -+ {6, 8, 0x0}, -+ {6, 14, 0x0}, -+ {6, 6, 0x0}, -+ {6, 5, 0x0}, -+ {6, 4, 0x0}, -+ {6, 7, 0x0}, -+ {6, 9, 0x0}, -+ {6, 11, 0x0}, -+ {5, 8, 0x0}, -+ {5, 14, 0x0}, -+ {5, 6, 0x0}, -+ {5, 5, 0x0}, -+ {5, 4, 0x0}, -+ {5, 7, 0x0}, -+ {5, 9, 0x0}, -+ {5, 11, 0x0}, -+ {4, 8, 0x0}, -+ {4, 14, 0x0}, -+ {4, 6, 0x0}, -+ {4, 5, 0x0}, -+ {4, 1, 0x0}, -+ {4, 7, 0x0}, -+ {4, 9, 0x0}, -+ {4, 11, 0x0}, -+ {7, 8, 0x0}, -+ {7, 14, 0x0}, -+ {7, 6, 0x0}, -+ {7, 5, 0x0}, -+ {7, 4, 0x0}, -+ {7, 7, 0x0}, -+ {7, 9, 0x0}, -+ {7, 11, 0x0}, -+ {10, 8, 0x0}, -+ {10, 14, 0x0}, -+ {10, 6, 0x0}, -+ {10, 5, 0x0}, -+ {10, 4, 0x0}, -+ {10, 7, 0x0}, -+ {10, 9, 0x0}, -+ {10, 11, 0x0}, -+ {12, 8, 0x0}, -+ {12, 14, 0x0}, -+ {12, 6, 0x0}, -+ {12, 5, 0x0}, -+ {12, 4, 0x0}, -+ {12, 7, 0x0}, -+ {12, 9, 0x0}, -+ {12, 11, 0x0}, - }; - - -@@ -1091,7 +1036,6 @@ struct xs_conv_test - { - test_func_t test_func; - const char *name; -- unsigned long long * results; - int num_tests; - }; - -@@ -1130,8 +1074,6 @@ struct vsx_move_test - { - test_func_t test_func; - const char *name; -- int xa_idx, xb_idx; -- unsigned long long expected_result; - }; - - struct vsx_permute_test -@@ -1140,7 +1082,6 @@ struct vsx_permute_test - const char *name; - unsigned int xa[4]; - unsigned int xb[4]; -- unsigned int expected_output[4]; - }; - - static vector unsigned int vec_out, vec_inA, vec_inB; -@@ -1402,13 +1343,13 @@ static logic_test_t logic_tests[] = { { - { &test_xxlnor, "xxlnor", VSX_NOR }, - { &test_xxland, "xxland", VSX_AND }, - { &test_xxlandc, "xxlandc", VSX_ANDC }, -- { NULL, NULL}}; -+ { NULL, NULL, 0}}; - --static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp", 0, 4, 0x0899aabb91929394ULL }, -- { &test_xscpsgndp, "xscpsgndp", 4, 0, 0x8123456789abcdefULL }, -- { &test_xsnabsdp, "xsnabsdp", 7, 3, 0xc45566778899aabbULL, }, -- { &test_xsnegdp, "xsnegdp", 0, 7, 0x31b2b3b4c1c2c3c4ULL, }, -- { NULL, NULL, 0, 0, 0 } -+static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp" }, -+ { &test_xscpsgndp, "xscpsgndp" }, -+ { &test_xsnabsdp, "xsnabsdp" }, -+ { &test_xsnegdp, "xsnegdp" }, -+ { NULL, NULL } - - }; - -@@ -1417,62 +1358,50 @@ static permute_test_t permute_tests[] = - { &test_xxmrghw, "xxmrghw", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x11111111, 0x55555555, 0x22222222, 0x66666666 } /* XT expected output */ - }, - { &test_xxmrghw, "xxmrghw", - { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff }, /* XA input */ - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XB input */ -- { 0x00112233, 0x11111111, 0x44556677, 0x22222222 } /* XT expected output */ - }, - { &test_xxmrglw, "xxmrglw", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x33333333, 0x77777777, 0x44444444, 0x88888888 } /* XT expected output */ - }, - { &test_xxmrglw, "xxmrglw", - { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff}, /* XA input */ - { 0x11111111, 0x22222222, 0x33333333, 0x44444444}, /* XB input */ -- { 0x8899aabb, 0x33333333, 0xccddeeff, 0x44444444} /* XT expected output */ - }, - { &test_xxpermdi_00, "xxpermdi DM=00", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x11111111, 0x22222222, 0x55555555, 0x66666666 } /* XT expected output */ - }, - { &test_xxpermdi_01, "xxpermdi DM=01", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x11111111, 0x22222222, 0x77777777, 0x88888888 } /* XT expected output */ - }, - { &test_xxpermdi_10, "xxpermdi DM=10", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */ - }, - { &test_xxpermdi_11, "xxpermdi DM=11", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x33333333, 0x44444444, 0x77777777, 0x88888888 } /* XT expected output */ - }, - { &test_xxsldwi_0, "xxsldwi SHW=0", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x11111111, 0x22222222, 0x33333333, 0x44444444 } /* XT expected output */ - }, - { &test_xxsldwi_1, "xxsldwi SHW=1", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x22222222, 0x33333333, 0x44444444, 0x55555555 } /* XT expected output */ - }, - { &test_xxsldwi_2, "xxsldwi SHW=2", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */ - }, - { &test_xxsldwi_3, "xxsldwi SHW=3", - { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */ - { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */ -- { 0x44444444, 0x55555555, 0x66666666, 0x77777777 } /* XT expected output */ - }, - { NULL, NULL } - }; -@@ -1497,16 +1426,16 @@ static vx_fp_test_t vx_fp_tests[] = { - }; - - static xs_conv_test_t xs_conv_tests[] = { -- { &test_xscvdpsxds, "xscvdpsxds", xscvdpsxds_results, 15}, -- { &test_xscvsxddp, "xscvsxddp", xscvsxddp_results, 15}, -- { &test_xscvuxddp, "xscvuxddp", xscvuxddp_results, 15}, -- { NULL, NULL, NULL, 0} -+ { &test_xscvdpsxds, "xscvdpsxds", 15}, -+ { &test_xscvsxddp, "xscvsxddp", 15}, -+ { &test_xscvuxddp, "xscvuxddp", 15}, -+ { NULL, NULL, 0} - }; - - #ifdef __powerpc64__ - static void test_ldbrx(void) - { -- int i, equality; -+ int i; - HWord_t reg_out; - unsigned char * byteIn, * byteOut; - r14 = (HWord_t)viargs; -@@ -1515,13 +1444,12 @@ static void test_ldbrx(void) - int j, k; - reg_out = 0; - r15 = i * 4; -- equality = 1; - __asm__ __volatile__ ("ldbrx %0, %1, %2" : "=r" (reg_out): "b" (r14),"r" (r15)); - byteIn = ((unsigned char *)(r14 + r15)); - byteOut = (unsigned char *)®_out; - - printf("ldbrx:"); -- for (k = 0; k < 7; k++) { -+ for (k = 0; k < 8; k++) { - printf( " %02x", (byteIn[k])); - } - printf(" (reverse) =>"); -@@ -1529,13 +1457,6 @@ static void test_ldbrx(void) - printf( " %02x", (byteOut[j])); - } - printf("\n"); -- for (j = 0, k = 7; j < 8; j++, k--) { -- equality &= (byteIn[k] == byteOut[j]); -- } -- if (!equality) { -- printf("FAILED: load with byte reversal is incorrect\n"); -- errors++; -- } - } - printf( "\n" ); - } -@@ -1545,18 +1466,9 @@ test_popcntd(void) - { - uint64_t res; - unsigned long long src = 0x9182736405504536ULL; -- int i, answer = 0; - r14 = src; - __asm__ __volatile__ ("popcntd %0, %1" : "=r" (res): "r" (r14)); -- for (i = 0; i < 64; i++) { -- answer += (r14 & 1ULL); -- r14 = r14 >> 1; -- } - printf("popcntd: 0x%llx => %d\n", src, (int)res); -- if (res!= answer) { -- printf("Error: unexpected result from popcntd\n"); -- errors++; -- } - printf( "\n" ); - } - #endif -@@ -1576,10 +1488,6 @@ test_lfiwzx(void) - src = ((unsigned int *)(r14 + r15)); - printf("lfiwzx: %u => %llu.00\n", *src, (unsigned long long)reg_out); - -- if (reg_out > 0xFFFFFFFFULL || *src != (unsigned int)reg_out) { -- printf("FAILED: integer load to FP register is incorrect\n"); -- errors++; -- } - } - printf( "\n" ); - } -@@ -1635,6 +1543,9 @@ static void test_vx_fp_ops(void) - again: - for (i = 0; i < test_group.num_tests; i++) { - unsigned int * inA, * inB, * pv; -+ double * dpA = (double *)&vec_inA; -+ double * dpB = (double *)&vec_inB; -+ double * dpT = (double *)&vec_out; - - fp_test_args_t aTest = test_group.targs[i]; - inA = (unsigned int *)&spec_fargs[aTest.fra_idx]; -@@ -1642,8 +1553,15 @@ again: - frap = (unsigned long long *)&spec_fargs[aTest.fra_idx]; - frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx]; - // Only need to copy one doubleword into each vector's element 0 -- memcpy(&vec_inA, inA, 8); -- memcpy(&vec_inB, inB, 8); -+ if (isLE) { -+ // With LE, vector element 0 is the second doubleword from the left -+ memset(dpA, 0, 8); -+ memset(dpB, 0, 8); -+ dpA++; -+ dpB++; -+ } -+ memcpy(dpA, inA, 8); -+ memcpy(dpB, inB, 8); - - switch (test_type) { - case VX_FP_CMP: -@@ -1656,7 +1574,6 @@ again: - // printf("\tFRA: %e; FRB: %e\n", spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx]); - if ( condreg != aTest.cr_flags) { - printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, condreg); -- errors++; - } - break; - case VX_FP_SMA: -@@ -1676,7 +1593,7 @@ again: - * VSX[XT] -- i.e., vec_out. For the xsmdp cases, VSX[XT] holds - * src3 and VSX[XB] holds src2; for the xsadp cases, VSX[XT] holds - * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test -- * data (input args, result) contain only two inputs, so I arbitrarily -+ * data (input args) contain only two inputs, so I arbitrarily - * use spec_fargs elements 4 and 14 (alternating) for the third source - * argument. We can use the same input data for a given pair of - * adp/mdp-type instructions by swapping the src2 and src3 arguments; thus -@@ -1688,8 +1605,6 @@ again: - else - extra_arg_idx = 14; - -- //memcpy(&vec_out, &spec_fargs[14], 8); -- - if (repeat) { - /* We're on the first time through of one of the VX_FP_SMx - * test types, meaning we're testing a xsadp case, thus we -@@ -1697,28 +1612,30 @@ again: - * src2 <= VSX[XT] - * src3 <= VSX[XB] - */ -- memcpy(&vec_out, inB, 8); // src2 -- memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3 -+ if (isLE) -+ dpT++; -+ memcpy(dpT, inB, 8); // src2 -+ memcpy(dpB, &spec_fargs[extra_arg_idx], 8); //src3 - frbp = (unsigned long long *)&spec_fargs[extra_arg_idx]; - } else { - // Don't need to init src2, as it's done before the switch() -- memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3 -+ if (isLE) -+ dpT++; -+ memcpy(dpT, &spec_fargs[extra_arg_idx], 8); //src3 - } -- memcpy(&vsr_XT, &vec_out, 8); -+ memcpy(&vsr_XT, dpT, 8); - } - - (*func)(); - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - if (test_type == VX_FP_OTHER) - printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name, *frap, *frbp, *dst); - else - printf( "#%d: %s %016llx %016llx %016llx = %016llx\n", i, - test_name, vsr_XT, *frap, *frbp, *dst ); - -- if ( *dst != aTest.dp_bin_result) { -- printf("Error: Expected result %016llx; actual result %016llx\n", aTest.dp_bin_result, *dst); -- errors++; -- } - /* - { - // Debug code. Keep this block commented out except when debugging. -@@ -1774,6 +1691,11 @@ static void test_xs_conv_ops(void) - - test_func_t func; - int k = 0; -+ double * dpB = (double *)&vec_inB; -+ if (isLE) { -+ memset(dpB, 0, 8); -+ dpB++; -+ } - - build_special_fargs_table(); - while ((func = xs_conv_tests[k].test_func)) { -@@ -1783,22 +1705,20 @@ static void test_xs_conv_ops(void) - for (i = 0; i < test_group.num_tests; i++) { - unsigned int * inB, * pv; - int idx; -- unsigned long long exp_result = test_group.results[i]; - inB = (unsigned int *)&spec_fargs[i]; - frbp = (unsigned long long *)&spec_fargs[i]; -- memcpy(&vec_inB, inB, 8); -+ -+ memcpy(dpB, inB, 8); - pv = (unsigned int *)&vec_out; - // clear vec_out - for (idx = 0; idx < 4; idx++, pv++) - *pv = 0; - (*func)(); - dst = (unsigned long long *) &vec_out; -+ if (isLE) -+ dst++; - printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp, *dst); - -- if ( *dst != exp_result) { -- printf("Error: Expected result %016llx; actual result %016llx\n", exp_result, *dst); -- errors++; -- } - } - k++; - printf("\n"); -@@ -1811,7 +1731,7 @@ static void do_load_test(ldst_test_t loa - test_func_t func; - unsigned int *src, *dst; - int splat = loadTest.type == VSX_LOAD_SPLAT ? 1: 0; -- int i, j, m, equality; -+ int i, j, m, k; - i = j = 0; - - func = loadTest.test_func; -@@ -1840,20 +1760,19 @@ static void do_load_test(ldst_test_t loa - printf( " %08x", src[splat ? m % 2 : m]); - } - printf( " =>"); -- for (m = 0; m < loadTest.num_words_to_process; m++) { -- printf( " %08x", dst[m]); -- } -- printf("\n"); -- equality = 1; -- for (m = 0; m < loadTest.num_words_to_process; m++) { -- equality = equality && (src[splat ? m % 2 : m] == dst[m]); -+ m = 0; -+ k = loadTest.num_words_to_process; -+ if (isLE) { -+ if (loadTest.num_words_to_process == 2) { -+ m = 2; -+ k += 2; -+ } - } - -- if (!equality) { -- printf("FAILED: loaded vector is incorrect\n"); -- errors++; -+ for (; m < k; m++) { -+ printf( " %08x", dst[m]); - } -- -+ printf("\n"); - if (j == 0 && loadTest.offset) { - again = 1; - j += loadTest.offset; -@@ -1868,7 +1787,7 @@ do_store_test ( ldst_test_t storeTest ) - { - test_func_t func; - unsigned int *src, *dst; -- int m, equality; -+ int m; - - func = storeTest.test_func; - r14 = (HWord_t) storeTest.base_addr; -@@ -1895,16 +1814,6 @@ do_store_test ( ldst_test_t storeTest ) - printf( " %08x", dst[m] ); - } - printf( "\n" ); -- equality = 1; -- for (m = 0; m < storeTest.num_words_to_process; m++) { -- equality = equality && (src[m] == dst[m]); -- } -- -- if (!equality) { -- printf( "FAILED: vector store result is incorrect\n" ); -- errors++; -- } -- - } - - -@@ -1932,7 +1841,7 @@ static void test_ftdiv(void) - num_tests = sizeof ftdiv_tests/sizeof ftdiv_tests[0]; - - for (i = 0; i < num_tests; i++) { -- ftdiv_test_args_t aTest = ftdiv_tests[i]; -+ fp_test_args_t aTest = ftdiv_tests[i]; - f14 = spec_fargs[aTest.fra_idx]; - f15 = spec_fargs[aTest.frb_idx]; - frap = (unsigned long long *)&spec_fargs[aTest.fra_idx]; -@@ -1946,7 +1855,6 @@ static void test_ftdiv(void) - // printf("\tFRA: %e; FRB: %e\n", f14, f15); - if ( crx != aTest.cr_flags) { - printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, crx); -- errors++; - } - } - printf( "\n" ); -@@ -1991,7 +1899,7 @@ static void test_vsx_logic(void) - { - logic_test_t aTest; - test_func_t func; -- int equality, k; -+ int k; - k = 0; - - while ((func = logic_tests[k].test_func)) { -@@ -2021,82 +1929,68 @@ static void test_vsx_logic(void) - printf( " %08x %08x %08x %08x", inB[0], inB[1], inB[2], inB[3]); - printf(" => %08x %08x %08x %08x\n", dst[0], dst[1], dst[2], dst[3]); - -- equality = 1; -- for (idx = 0; idx < 4; idx++) { -- switch (aTest.op) { -- case VSX_AND: -- equality &= (dst[idx] == (inA[idx] & inB[idx])); -- break; -- case VSX_ANDC: -- equality &= (dst[idx] == (inA[idx] & ~inB[idx])); -- break; -- case VSX_NOR: -- equality &= (dst[idx] == ~(inA[idx] | inB[idx])); -- break; -- case VSX_XOR: -- equality &= (dst[idx] == (inA[idx] ^ inB[idx])); -- break; -- case VSX_OR: -- equality &= (dst[idx] == (inA[idx] | inB[idx])); -- break; -- default: -- fprintf(stderr, "Error in test_vsx_logic(): unknown VSX logical op %d\n", aTest.op); -- exit(1); -- } -- } -- if (!equality) { -- printf( "FAILED: vector out is incorrect\n" ); -- errors++; -- } - } - k++; - } - printf( "\n" ); - } - -+static vector unsigned long long vec_args[] __attribute__ ((aligned (16))) = -+{ -+ { 0x0123456789abcdefULL, 0x0011223344556677ULL}, -+ { 0x8899aabb19293942ULL, 0xa1a2a3a4b1b2b3b4ULL}, -+ { 0xc1c2c3c4d1d2d3d4ULL, 0x7a6b5d3efc032778ULL} -+}; -+#define NUM_VEC_ARGS_LONGS (sizeof vec_args/sizeof vec_args[0]) -+ - static void test_move_ops (void) - { - move_test_t aTest; - test_func_t func; -- int equality, k; -+ int k; - k = 0; - - while ((func = move_tests[k].test_func)) { - unsigned int * pv; - int startA, startB; -- unsigned int * inA, * inB, * dst; -- unsigned long long exp_out; -+ unsigned long long * inA, * inB, * dst; -+ int use_vecA = (strcmp(move_tests[k].name, "xscpsgndp") == 0); - int idx; -+ inA = NULL; - aTest = move_tests[k]; -- exp_out = aTest.expected_result; -- startA = aTest.xa_idx; -- startB = aTest.xb_idx; -- pv = (unsigned int *)&vec_out; -- inA = &viargs[startA]; -- inB = &viargs[startB]; -- memcpy(&vec_inA, inA, sizeof(vector unsigned char)); -- memcpy(&vec_inB, inB, sizeof(vector unsigned char)); -- // clear vec_out -- for (idx = 0; idx < 4; idx++, pv++) -- *pv = 0; -+ for (startB = 0; startB < NUM_VEC_ARGS_LONGS; startB++) { -+ inB = (unsigned long long *)&vec_args[startB]; -+ memcpy(&vec_inB, inB, sizeof(vector unsigned char)); -+ if (isLE) -+ inB++; -+ startA = 0; -+repeat: -+ if (use_vecA) { -+ inA = (unsigned long long *)&vec_args[startA]; -+ memcpy(&vec_inA, inA, sizeof(vector unsigned char)); -+ startA++; -+ } -+ pv = (unsigned int *)&vec_out; -+ // clear vec_out -+ for (idx = 0; idx < 4; idx++, pv++) -+ *pv = 0; - -- // execute test insn -- (*func)(); -- dst = (unsigned int*) &vec_out; -+ // execute test insn -+ (*func)(); -+ dst = (unsigned long long *) &vec_out; -+ if (isLE) { -+ dst++; -+ inA++; -+ } - -- printf( "%s:", aTest.name); -- printf( " %08x %08x %s", inA[0], inA[1], aTest.name); -- printf( " %08x %08xx", inB[0], inB[1]); -- printf(" => %08x %08x\n", dst[0], dst[1]); -- -- equality = 1; -- pv = (unsigned int *)&exp_out; -- for (idx = 0; idx < 2; idx++) { -- equality &= (dst[idx] == pv[idx]); -- } -- if (!equality) { -- printf( "FAILED: vector out is incorrect\n" ); -- errors++; -+ printf( "%s:", aTest.name); -+ if (use_vecA) -+ printf( " X[A]: %016llx ", *inA); -+ printf( " X[B]: %016llx", *inB); -+ printf(" => %016llx\n", *dst); -+ -+ if (use_vecA && startA < NUM_VEC_ARGS_LONGS) -+ goto repeat; - } - k++; - printf( "\n" ); -@@ -2126,11 +2020,6 @@ static void test_permute_ops (void) - printf( " => XT[%08x,%08x,%08x,%08x]\n", - dst[0], dst[1], dst[2], dst[3]); - -- if (memcmp (dst, &aTest->expected_output, sizeof(vec_out))) -- { -- printf( "FAILED: vector out is incorrect\n" ); -- errors++; -- } - } - printf( "\n" ); - } -@@ -2177,10 +2066,6 @@ int main(int argc, char *argv[]) - (*func)(); - i++; - } -- if (errors) -- printf("Testcase FAILED with %d errors \n", errors); -- else -- printf("Testcase PASSED\n"); - - #endif // HAS _VSX - -Index: tests/is_ppc64_BE.c -=================================================================== ---- /dev/null -+++ tests/is_ppc64_BE.c -@@ -0,0 +1,14 @@ -+#include -+#include -+#include -+ -+// This program returns 0 if executing on ppc64 big endian; otherwise returns 1 -+ -+int main(void) -+{ -+#if defined(VGP_ppc64be_linux) -+ return 0; -+#else -+ return 1; -+#endif -+} -Index: tests/check_isa-2_06_cap -=================================================================== ---- tests/check_isa-2_06_cap.orig -+++ tests/check_isa-2_06_cap -@@ -1,7 +1,7 @@ - #!/bin/sh - - # We use this script to check whether or not the processor supports Power ISA 2.06 or later. --DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" -+DIR="$( cd "$( dirname "$0" )" && pwd )" - LD_SHOW_AUXV=1 $DIR/true | grep arch_2_06 > /dev/null 2>&1 - - if [ "$?" -ne "0" ]; then -Index: tests/check_isa-2_07_cap -=================================================================== ---- tests/check_isa-2_07_cap.orig -+++ tests/check_isa-2_07_cap -@@ -2,7 +2,7 @@ - - # We use this script to check whether or not the processor supports - # Power ISA 2.07. --DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" -+DIR="$( cd "$( dirname "$0" )" && pwd )" - LD_SHOW_AUXV=1 $DIR/true | grep arch_2_07 > /dev/null 2>&1 - - if [ "$?" -ne "0" ]; then -Index: memcheck/tests/atomic_incs.c -=================================================================== ---- memcheck/tests/atomic_incs.c.orig -+++ memcheck/tests/atomic_incs.c -@@ -79,6 +79,23 @@ __attribute__((noinline)) void atomic_ad - : /*trash*/ "memory", "cc", "r15" - ); - } while (success != 1); -+#elif defined(VGA_ppc64le) -+ /* Nasty hack. Does correctly atomically do *p += n, but only if p -+ is 8-aligned -- guaranteed by caller. */ -+ unsigned long success; -+ do { -+ __asm__ __volatile__( -+ "ldarx 15,0,%1" "\n\t" -+ "add 15,15,%2" "\n\t" -+ "stdcx. 15,0,%1" "\n\t" -+ "mfcr %0" "\n\t" -+ "srwi %0,%0,29" "\n\t" -+ "andi. %0,%0,1" "\n" -+ : /*out*/"=b"(success) -+ : /*in*/ "b"(p), "b"(((unsigned long)n)) -+ : /*trash*/ "memory", "cc", "r15" -+ ); -+ } while (success != 1); - #elif defined(VGA_arm) - unsigned int block[3] - = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF }; -@@ -260,6 +277,23 @@ __attribute__((noinline)) void atomic_ad - : /*trash*/ "memory", "cc", "r15" - ); - } while (success != 1); -+#elif defined(VGA_ppc64le) -+ /* Nasty hack. Does correctly atomically do *p += n, but only if p -+ is 8-aligned -- guaranteed by caller. */ -+ unsigned long success; -+ do { -+ __asm__ __volatile__( -+ "ldarx 15,0,%1" "\n\t" -+ "add 15,15,%2" "\n\t" -+ "stdcx. 15,0,%1" "\n\t" -+ "mfcr %0" "\n\t" -+ "srwi %0,%0,29" "\n\t" -+ "andi. %0,%0,1" "\n" -+ : /*out*/"=b"(success) -+ : /*in*/ "b"(p), "b"(((unsigned long)n)) -+ : /*trash*/ "memory", "cc", "r15" -+ ); -+ } while (success != 1); - #elif defined(VGA_arm) - unsigned int block[3] - = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF }; -@@ -438,6 +472,23 @@ __attribute__((noinline)) void atomic_ad - : /*trash*/ "memory", "cc", "r15" - ); - } while (success != 1); -+#elif defined(VGA_ppc64le) -+ /* Nasty hack. Does correctly atomically do *p += n, but only if p -+ is 8-aligned -- guaranteed by caller. */ -+ unsigned long success; -+ do { -+ __asm__ __volatile__( -+ "ldarx 15,0,%1" "\n\t" -+ "add 15,15,%2" "\n\t" -+ "stdcx. 15,0,%1" "\n\t" -+ "mfcr %0" "\n\t" -+ "srwi %0,%0,29" "\n\t" -+ "andi. %0,%0,1" "\n" -+ : /*out*/"=b"(success) -+ : /*in*/ "b"(p), "b"(((unsigned long)n)) -+ : /*trash*/ "memory", "cc", "r15" -+ ); -+ } while (success != 1); - #elif defined(VGA_arm) - unsigned int block[3] - = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF }; -@@ -520,7 +571,7 @@ __attribute__((noinline)) void atomic_ad - "lock; addq %%rbx,(%%rax)" "\n" - : : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx" - ); --#elif defined(VGA_ppc64be) -+#elif defined(VGA_ppc64be) || defined(VGA_ppc64le) - unsigned long success; - do { - __asm__ __volatile__( -Index: memcheck/tests/ppc64/power_ISA2_05.c -=================================================================== ---- memcheck/tests/ppc64/power_ISA2_05.c.orig -+++ memcheck/tests/ppc64/power_ISA2_05.c -@@ -41,19 +41,25 @@ void test_parity_instrs() - void test_lfiwax() - { - unsigned long base; -+ float foo_s; - - typedef struct { -+#if defined(VGP_ppc64le_linux) -+ unsigned int lo; -+ unsigned int hi; -+#else - unsigned int hi; - unsigned int lo; -+#endif - } int_pair_t; - - int_pair_t *ip; -- foo = -1024.0; -- base = (unsigned long) &foo; -+ foo_s = -1024.0; -+ base = (unsigned long) &foo_s; - - __asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base)); - ip = (int_pair_t *) & FRT1; -- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo); -+ printf("lfiwax (%f) => FRT=(%x, %x)\n", foo_s, ip->hi, ip->lo); - - - } -@@ -167,24 +173,27 @@ void test_fcpsgn() - void test_reservation() - { - -- int RT; -+ unsigned long long RT; - unsigned long base; - unsigned long offset; -- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; -+ long arrL[] __attribute__ ((aligned (8))) = { 0xdeadbeef00112233ULL, 0xbad0beef44556677ULL, 0xbeefdead8899aabbULL, 0xbeef0badccddeeffULL }; -+ int arrI[] __attribute__ ((aligned (4))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; - - -- base = (unsigned long) &arr; -- offset = (unsigned long) &arr[1] - base; -+ base = (unsigned long) &arrI; -+ offset = ((unsigned long) &arrI[1]) - base; - __asm__ volatile ("ori 20, %0, 0"::"r" (base)); - __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); - __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT)); -- printf("lwarx => %x\n", RT); -+ printf("lwarx => 0x%llx\n", RT); - - #ifdef __powerpc64__ -- offset = (unsigned long) &arr[1] - base; -+ base = (unsigned long) &arrL; -+ offset = ((unsigned long) &arrL[1]) - base; -+ __asm__ volatile ("ori 20, %0, 0"::"r" (base)); - __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); - __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT)); -- printf("ldarx => %x\n", RT); -+ printf("ldarx => 0x%llx\n", RT); - #endif - - } -Index: memcheck/tests/ppc64/power_ISA2_05.stdout.exp -=================================================================== ---- memcheck/tests/ppc64/power_ISA2_05.stdout.exp.orig -+++ memcheck/tests/ppc64/power_ISA2_05.stdout.exp -@@ -1,5 +1,5 @@ --lwarx => 0 --ldarx => bad0beef -+lwarx => 0xbad0beef -+ldarx => 0xbad0beef44556677 - fcpsgn sign=10.101010, base=11.111111 => 11.111111 - fcpsgn sign=10.101010, base=-0.000000 => 0.000000 - fcpsgn sign=10.101010, base=0.000000 => 0.000000 -@@ -20,7 +20,7 @@ lfdp (-1024.000000, 1025.000000) => F_hi - stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 - lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400 - stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800 --lfiwax (-1024.000000) => FRT=(ffffffff, c0900000) -+lfiwax (-1024.000000) => FRT=(ffffffff, c4800000) - prtyd (0) => parity=0 - prtyw (0) => parity=0 - prtyd (1) => parity=1 -Index: memcheck/tests/badjump.c -=================================================================== ---- memcheck/tests/badjump.c.orig -+++ memcheck/tests/badjump.c -@@ -2,7 +2,7 @@ - - int main ( void ) - { --#if defined(__powerpc64__) -+#if defined(__powerpc64__) && _CALL_ELF != 2 - /* on ppc64-linux, a function pointer points to a function - descriptor, not to the function's entry point. Hence to get - uniform behaviour on all supported targets - a jump to an diff --git a/r14246.diff b/r14246.diff deleted file mode 100644 index a5ae802..0000000 --- a/r14246.diff +++ /dev/null @@ -1,35 +0,0 @@ ------------------------------------------------------------------------- -r14246 | carll | 2014-08-09 00:29:10 +0200 (Sa, 09. Aug 2014) | 10 Zeilen - -This commit is for Bugzilla 334834. - -A performance regression was found due to the --02 -m64 flags not being included when compiling -the VEX PPC64 code. This commit fixes the Makefile -to pass the needed flags when compiling VEX PPC64 -code. - - - ------------------------------------------------------------------------- -Index: Makefile.all.am -=================================================================== ---- Makefile.all.am (Revision 14245) -+++ Makefile.all.am (Revision 14246) -@@ -163,9 +163,13 @@ AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@ - AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE) - AM_CCASFLAGS_PPC32_LINUX = @FLAG_M32@ -g - --AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@ --AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) --AM_CCASFLAGS_PPC64_LINUX = @FLAG_M64@ -g -+AM_FLAG_M3264_PPC64BE_LINUX = @FLAG_M64@ -+AM_CFLAGS_PPC64BE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -+AM_CCASFLAGS_PPC64BE_LINUX = @FLAG_M64@ -g -+ -+AM_FLAG_M3264_PPC64LE_LINUX = @FLAG_M64@ -+AM_CFLAGS_PPC64LE_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) -+AM_CCASFLAGS_PPC64LE_LINUX = @FLAG_M64@ -g - - AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@ - AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \ diff --git a/r2798.diff b/r2798.diff deleted file mode 100644 index 28e4835..0000000 --- a/r2798.diff +++ /dev/null @@ -1,33 +0,0 @@ ------------------------------------------------------------------------- -r2798 | cborntra | 2013-11-07 22:37:28 +0100 (Do, 07 Nov 2013) | 16 lines - -Fix Bug 327284. The condition code of risbg was not correct. -This instruction might be used by by gcc for masking out bits, -e.g. code like - n &= 3; - if (n == 0) - -might result in - risbg %r4,%r4,62,128+63,0 - je - -The old code set the condition code depending on the operand before -masking. Fix it. This patch also indicates that we need test suite -coverage for risbg and friends. - - - ------------------------------------------------------------------------- -Index: priv/guest_s390_toIR.c -=================================================================== ---- VEX/priv/guest_s390_toIR.c (revision 2797) -+++ VEX/priv/guest_s390_toIR.c (revision 2798) -@@ -7606,7 +7606,7 @@ s390_irgen_RISBG(UChar r1, UChar r2, UCh - put_gpr_dw0(r1, binop(Iop_And64, mkexpr(op2), mkU64(mask))); - } - assign(result, get_gpr_dw0(r1)); -- s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); -+ s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result); - - return "risbg"; - } diff --git a/valgrind-3.10.0.tar.bz2 b/valgrind-3.10.0.tar.bz2 new file mode 100644 index 0000000..b25b9a9 --- /dev/null +++ b/valgrind-3.10.0.tar.bz2 @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:03047f82dfc6985a4c7d9d2700e17bc05f5e1a0ca6ad902e5d6c81aeb720edc9 +size 10898253 diff --git a/valgrind-3.9.0.tar.bz2 b/valgrind-3.9.0.tar.bz2 deleted file mode 100644 index b5079ac..0000000 --- a/valgrind-3.9.0.tar.bz2 +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:e6af71a06bc2534541b07743e1d58dc3caf744f38205ca3e5b5a0bdf372ed6f0 -size 10003156 diff --git a/valgrind-r13948.diff b/valgrind-r13948.diff deleted file mode 100644 index 24c59bf..0000000 --- a/valgrind-r13948.diff +++ /dev/null @@ -1,111 +0,0 @@ ------------------------------------------------------------------------- -r13948 | mjw | 2014-05-09 13:41:46 +0200 (Fr, 09 Mai 2014) | 1 line - -Add test for MPX instructions and bnd prefix. Bug #333666. ------------------------------------------------------------------------- -Index: none/tests/amd64/mpx.c -=================================================================== ---- /dev/null -+++ none/tests/amd64/mpx.c -@@ -0,0 +1,38 @@ -+int -+main (int argc, char **argv) -+{ -+ // Since MPX is disabled all these are just NOPS. -+ // Some of these instructions are just random. -+ // Once the GCC support is merged creating real test cases will be easier. -+ // http://gcc.gnu.org/wiki/Intel%20MPX%20support%20in%20the%20GCC%20compiler -+ -+ // This is what ld.so does in _dl_runtime_resolve to save the bnds. -+ asm ("bndmov %bnd0, (%rsp)"); -+ asm ("bndmov %bnd1, 16(%rsp)"); -+ asm ("bndmov %bnd2, 32(%rsp)"); -+ asm ("bndmov %bnd3, 48(%rsp)"); -+ -+ // Create a bnd, check lower and upper... -+ asm ("bndmk (%rax,%rdx), %bnd0"); -+ asm ("bndcl (%rax,%rdi,4), %bnd0"); -+ asm ("bndcu 3(%rax,%rdi,4), %bnd0"); -+ asm ("bndcn 3(%rax,%rdi,4), %bnd0"); -+ -+ // Load bnd pointer and update... -+ asm ("bndldx 3(%rbx,%rdx), %bnd2"); -+ asm ("bndstx %bnd2, 3(,%r12,1)"); -+ -+ // "bnd" prefixed call, return and jmp... -+ asm ("bnd call foo\n\ -+ bnd jmp end\n\ -+ foo: bnd ret\n\ -+ end: nop"); -+ -+ // And set the bnds back... -+ asm ("bndmov 48(%rsp), %bnd3"); -+ asm ("bndmov 32(%rsp), %bnd2"); -+ asm ("bndmov 16(%rsp), %bnd1"); -+ asm ("bndmov (%rsp), %bnd0"); -+ -+ return 0; -+} -Index: none/tests/amd64/mpx.vgtest -=================================================================== ---- /dev/null -+++ none/tests/amd64/mpx.vgtest -@@ -0,0 +1,3 @@ -+prog: mpx -+prereq: test -x mpx -+vgopts: -q -Index: none/tests/amd64/Makefile.am -=================================================================== ---- none/tests/amd64/Makefile.am.orig -+++ none/tests/amd64/Makefile.am -@@ -56,6 +56,7 @@ EXTRA_DIST = \ - loopnel.stderr.exp loopnel.stdout.exp loopnel.vgtest \ - lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \ - movbe.stderr.exp movbe.stdout.exp movbe.vgtest \ -+ mpx.stderr.exp mpx.stdout.exp mpx.vgtest \ - nan80and64.stderr.exp nan80and64.stdout.exp nan80and64.vgtest \ - nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \ - nibz_bennee_mmap.vgtest \ -@@ -131,6 +132,10 @@ endif - if BUILD_MOVBE_TESTS - check_PROGRAMS += movbe - endif -+if BUILD_MPX_TESTS -+ check_PROGRAMS += mpx -+endif -+ - - # DDD: these need to be made to work on Darwin like the x86/ ones were. - if ! VGCONF_OS_IS_DARWIN -Index: configure.ac -=================================================================== ---- configure.ac.orig -+++ configure.ac -@@ -2242,6 +2242,27 @@ AC_MSG_RESULT([no]) - AM_CONDITIONAL(BUILD_FMA_TESTS, test x$ac_have_as_fma = xyes) - - -+# does the amd64 assembler understand MPX instructions? -+# Note, this doesn't generate a C-level symbol. It generates a -+# automake-level symbol (BUILD_MPX_TESTS), used in test Makefile.am's -+AC_MSG_CHECKING([if amd64 assembler knows the MPX instructions]) -+ -+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ -+ asm ("bndmov %bnd0,(%rsp)") -+]])], [ -+ac_have_as_mpx=yes -+AC_MSG_RESULT([yes]) -+], [ -+ac_have_as_mpx=no -+AC_MSG_RESULT([no]) -+]) -+ -+AM_CONDITIONAL(BUILD_MPX_TESTS, test x$ac_have_as_mpx = xyes) -+ -+ -+# Does the C compiler support the "ifunc" attribute -+# Note, this doesn't generate a C-level symbol. It generates a -+# automake-level symbol (BUILD_IFUNC_TESTS), used in test Makefile.am's - # does the x86/amd64 assembler understand MOVBE? - # Note, this doesn't generate a C-level symbol. It generates a - # automake-level symbol (BUILD_MOVBE_TESTS), used in test Makefile.am's diff --git a/valgrind.changes b/valgrind.changes index 293f434..a9df529 100644 --- a/valgrind.changes +++ b/valgrind.changes @@ -1,3 +1,28 @@ +------------------------------------------------------------------- +Tue Sep 16 15:39:34 UTC 2014 - schwab@suse.de + +- glibc-2.19.patch: already upstream, so remove +- Fix file list + +------------------------------------------------------------------- +Tue Sep 16 15:27:20 UTC 2014 - dmueller@suse.com + +- update to 3.10.0: + * Support for the 64-bit ARM Architecture (AArch64 ARMv8). This port + is mostly complete, and is usable, but some SIMD instructions are as + yet unsupported. + * Support for little-endian variant of the 64-bit POWER architecture. + * Support for Android on MIPS32. + * Support for 64bit FPU on MIPS32 platforms. + * Both 32- and 64-bit executables are supported on MacOSX 10.8 and 10.9. + * Configuration for and running on Android targets has changed. + See README.android in the source tree for details. + - drop VEX-r2803.diff, VEX-r2808.diff, VEX-r2816.diff, VEX-r2858.diff, + VEX-r2904.diff, VEX-r2910.diff, VEX-r2914.diff, VEX-r2915.diff, + VEX-r2916.diff, aarch64-VEX-support.diff, aarch64-support.diff, + r13767.diff, r13770.diff, r14184.diff, r14238.diff, r14239.diff, + r14240.diff, r14246.diff, r2798.diff, valgrind-r13948.diff + ------------------------------------------------------------------- Sun Aug 17 21:46:19 UTC 2014 - dmueller@suse.com diff --git a/valgrind.spec b/valgrind.spec index 2fe2b3a..776c197 100644 --- a/valgrind.spec +++ b/valgrind.spec @@ -33,35 +33,13 @@ Summary: Memory Management Debugger License: GPL-2.0+ Group: Development/Tools/Debuggers BuildRoot: %{_tmppath}/%{name}-%{version}-build -Version: 3.9.0 +Version: 3.10.0 Release: 0 Source0: http://valgrind.org/downloads/%{name}-%{version}.tar.bz2 # svn di svn://svn.valgrind.org/valgrind/tags/VALGRIND_3_5_0 svn://svn.valgrind.org/valgrind/branches/VALGRIND_3_5_BRANCH > 3_5_BRANCH.diff # svn di svn://svn.valgrind.org/vex/tags/VEX_3_5_0 svn://svn.valgrind.org/vex/branches/VEX_3_5_BRANCH > VEX_3_5_BRANCH.diff Patch1: jit-register-unregister.diff Patch2: armv6-support.diff -Patch3: r13767.diff -Patch4: r13770.diff -Patch5: glibc-2.19.patch -Patch6: r2798.diff -Patch7: aarch64-support.diff -Patch8: aarch64-VEX-support.diff -Patch9: VEX-r2858.diff -Patch10: valgrind-r13948.diff -# PPC64 LE support -Patch11: r14184.diff -Patch12: r14238.diff -Patch13: r14239.diff -Patch14: r14240.diff -Patch15: r14246.diff -Patch20: VEX-r2803.diff -Patch21: VEX-r2808.diff -Patch22: VEX-r2816.diff -Patch23: VEX-r2904.diff -Patch24: VEX-r2910.diff -Patch25: VEX-r2914.diff -Patch26: VEX-r2915.diff -Patch27: VEX-r2916.diff # during building the major version of glibc is built into the suppression file %define glibc_main_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f1) %define glibc_major_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f2) @@ -156,45 +134,8 @@ Authors: %prep %setup -q -n %{name}-%{version} -%ifarch aarch64 -cd VEX -%patch8 -cd .. -%else -%patch9 -%ifarch ppc64le -# PPC64LE -%patch20 -%patch21 -%patch22 -%patch23 -%patch24 -%patch25 -%patch26 -%patch27 -%endif -%endif %patch1 -%ifarch aarch64 -%patch7 -%else %patch2 -%patch3 -%ifarch ppc64le -%patch4 -%endif -%patch5 -p1 -%patch6 -%patch10 -%ifarch ppc64le -# PPC64LE -%patch11 -%patch12 -%patch13 -%patch14 -%patch15 -%endif -%endif %build %ifarch %arm @@ -252,7 +193,7 @@ cp -a README* NEWS AUTHORS COPYING COPYING.DOCS $RPM_BUILD_ROOT/%_defaultdocdir/ %_libdir/valgrind/*-ppc32-linux %endif %ifarch ppc64 -%_libdir/valgrind/*-ppc64-linux +%_libdir/valgrind/*-ppc64be-linux %endif %ifarch ppc64le %_libdir/valgrind/*-ppc64le-linux