- add VEX-r2858.diff, valgrind-r13948.diff for (bnc#883157)
OBS-URL: https://build.opensuse.org/package/show/devel:tools/valgrind?expand=0&rev=110
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233
VEX-r2858.diff
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233
VEX-r2858.diff
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------------------------------------------------------------------------
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r2858 | mjw | 2014-05-09 13:41:06 +0200 (Fr, 09 Mai 2014) | 6 lines
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Recognize MPX instructions and bnd prefix. Bug #333666.
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Recognize and parse operands of new MPX instructions BNDMK, BNDCL,
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BNDCU, BNDCN, BNDMOV, BNDLDX and BNDSTX. Also recognize bnd (F2) prefix
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for CALL (E8,FF/2), RET (C2,C3), JMP (EB,E9,FF/4) and Jcc (70-7F,0F 80-8F).
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All new MPX instructions are currently NOPs and the bnd prefix is ignored.
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------------------------------------------------------------------------
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Index: priv/guest_amd64_toIR.c
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===================================================================
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--- priv/guest_amd64_toIR.c (revision 2857)
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+++ priv/guest_amd64_toIR.c (revision 2858)
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@@ -767,10 +767,10 @@ static Bool have66orF2orF3 ( Prefix pfx
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return toBool( ! haveNo66noF2noF3(pfx) );
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}
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-/* Return True iff pfx has 66 or F2 set */
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-static Bool have66orF2 ( Prefix pfx )
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+/* Return True iff pfx has 66 or F3 set */
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+static Bool have66orF3 ( Prefix pfx )
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{
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- return toBool((pfx & (PFX_66|PFX_F2)) > 0);
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+ return toBool((pfx & (PFX_66|PFX_F3)) > 0);
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}
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/* Clear all the segment-override bits in a prefix. */
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@@ -4266,8 +4266,12 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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modrm = getUChar(delta);
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if (epartIsReg(modrm)) {
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- /* F2/XACQ and F3/XREL are always invalid in the non-mem case. */
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- if (haveF2orF3(pfx)) goto unhandledR;
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+ /* F2/XACQ and F3/XREL are always invalid in the non-mem case.
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+ F2/CALL and F2/JMP may have bnd prefix. */
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+ if (haveF2orF3(pfx)
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+ && ! (haveF2(pfx)
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+ && (gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4)))
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+ goto unhandledR;
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assign(t1, getIRegE(sz,pfx,modrm));
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switch (gregLO3ofRM(modrm)) {
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case 0: /* INC */
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@@ -4287,6 +4291,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 2: /* call Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledR;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, getIRegE(sz,pfx,modrm));
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@@ -4302,6 +4307,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 4: /* jmp Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledR;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, getIRegE(sz,pfx,modrm));
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@@ -4334,11 +4340,14 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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showSz ? nameISize(sz) : ' ',
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nameIRegE(sz, pfx, modrm));
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} else {
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- /* Decide if F2/XACQ or F3/XREL might be valid. */
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+ /* Decide if F2/XACQ, F3/XREL, F2/CALL or F2/JMP might be valid. */
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Bool validF2orF3 = haveF2orF3(pfx) ? False : True;
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if ((gregLO3ofRM(modrm) == 0/*INC*/ || gregLO3ofRM(modrm) == 1/*DEC*/)
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&& haveF2orF3(pfx) && !haveF2andF3(pfx) && haveLOCK(pfx)) {
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validF2orF3 = True;
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+ } else if ((gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4)
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+ && (haveF2(pfx) && !haveF3(pfx))) {
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+ validF2orF3 = True;
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}
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if (!validF2orF3) goto unhandledM;
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/* */
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@@ -4375,6 +4384,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 2: /* call Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledM;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, loadLE(Ity_I64,mkexpr(addr)));
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@@ -4390,6 +4400,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 4: /* JMP Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledM;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, loadLE(Ity_I64,mkexpr(addr)));
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@@ -19716,7 +19727,8 @@ Long dis_ESC_NONE (
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case 0x7F: { /* JGb/JNLEb (jump greater) */
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Long jmpDelta;
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const HChar* comment = "";
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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jmpDelta = getSDisp8(delta);
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vassert(-128 <= jmpDelta && jmpDelta < 128);
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d64 = (guest_RIP_bbstart+delta+1) + jmpDelta;
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@@ -20369,7 +20381,8 @@ Long dis_ESC_NONE (
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}
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case 0xC2: /* RET imm16 */
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- if (have66orF2orF3(pfx)) goto decode_failure;
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+ if (have66orF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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d64 = getUDisp16(delta);
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delta += 2;
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dis_ret(dres, vbi, d64);
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@@ -20377,8 +20390,9 @@ Long dis_ESC_NONE (
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return delta;
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case 0xC3: /* RET */
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- if (have66orF2(pfx)) goto decode_failure;
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+ if (have66(pfx)) goto decode_failure;
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/* F3 is acceptable on AMD. */
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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dis_ret(dres, vbi, 0);
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DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n");
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return delta;
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@@ -20782,7 +20796,8 @@ Long dis_ESC_NONE (
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}
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case 0xE8: /* CALL J4 */
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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d64 = getSDisp32(delta); delta += 4;
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d64 += (guest_RIP_bbstart+delta);
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/* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */
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@@ -20805,9 +20820,10 @@ Long dis_ESC_NONE (
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return delta;
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case 0xE9: /* Jv (jump, 16/32 offset) */
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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if (sz != 4)
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goto decode_failure; /* JRS added 2004 July 11 */
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta);
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delta += sz;
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if (resteerOkFn(callback_opaque,d64)) {
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@@ -20821,9 +20837,10 @@ Long dis_ESC_NONE (
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return delta;
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case 0xEB: /* Jb (jump, byte offset) */
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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if (sz != 4)
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goto decode_failure; /* JRS added 2004 July 11 */
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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d64 = (guest_RIP_bbstart+delta+1) + getSDisp8(delta);
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delta++;
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if (resteerOkFn(callback_opaque,d64)) {
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@@ -21241,7 +21258,8 @@ Long dis_ESC_0F (
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case 0x8F: { /* JGb/JNLEb (jump greater) */
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Long jmpDelta;
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const HChar* comment = "";
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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jmpDelta = getSDisp32(delta);
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d64 = (guest_RIP_bbstart+delta+4) + jmpDelta;
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delta += 4;
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@@ -21332,6 +21350,66 @@ Long dis_ESC_0F (
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}
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return delta;
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+ case 0x1A:
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+ case 0x1B: { /* Future MPX instructions, currently NOPs.
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+ BNDMK b, m F3 0F 1B
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+ BNDCL b, r/m F3 0F 1A
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+ BNDCU b, r/m F2 0F 1A
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+ BNDCN b, r/m F2 0F 1B
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+ BNDMOV b, b/m 66 0F 1A
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+ BNDMOV b/m, b 66 0F 1B
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+ BNDLDX b, mib 0F 1A
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+ BNDSTX mib, b 0F 1B */
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+
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+ /* All instructions have two operands. One operand is always the
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+ bnd register number (bnd0-bnd3, other register numbers are
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+ ignored when MPX isn't enabled, but should generate an
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+ exception if MPX is enabled) given by gregOfRexRM. The other
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+ operand is either a ModRM:reg, ModRM:r/m or a SIB encoded
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+ address, all of which can be decoded by using either
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+ eregOfRexRM or disAMode. */
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+
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+ modrm = getUChar(delta);
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+ int bnd = gregOfRexRM(pfx,modrm);
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+ const HChar *oper;
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+ if (epartIsReg(modrm)) {
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+ oper = nameIReg64 (eregOfRexRM(pfx,modrm));
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+ delta += 1;
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+ } else {
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+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
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+ delta += alen;
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+ oper = dis_buf;
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+ }
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+
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+ if (haveF3no66noF2 (pfx)) {
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+ if (opc == 0x1B) {
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+ DIP ("bndmk %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1A */ {
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+ DIP ("bndcl %s, %%bnd%d\n", oper, bnd);
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+ }
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+ } else if (haveF2no66noF3 (pfx)) {
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+ if (opc == 0x1A) {
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+ DIP ("bndcu %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1B */ {
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+ DIP ("bndcn %s, %%bnd%d\n", oper, bnd);
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+ }
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+ } else if (have66noF2noF3 (pfx)) {
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+ if (opc == 0x1A) {
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+ DIP ("bndmov %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1B */ {
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+ DIP ("bndmov %%bnd%d, %s\n", bnd, oper);
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+ }
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+ } else if (haveNo66noF2noF3 (pfx)) {
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+ if (opc == 0x1A) {
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+ DIP ("bndldx %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1B */ {
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+ DIP ("bndstx %%bnd%d, %s\n", bnd, oper);
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+ }
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+ } else goto decode_failure;
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+
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+ return delta;
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+ }
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+
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case 0xA2: { /* CPUID */
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/* Uses dirty helper:
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void amd64g_dirtyhelper_CPUID ( VexGuestAMD64State* )
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115
valgrind-r13948.diff
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115
valgrind-r13948.diff
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@ -0,0 +1,115 @@
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------------------------------------------------------------------------
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r13948 | mjw | 2014-05-09 13:41:46 +0200 (Fr, 09 Mai 2014) | 1 line
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Add test for MPX instructions and bnd prefix. Bug #333666.
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------------------------------------------------------------------------
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Index: none/tests/amd64/mpx.stderr.exp
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===================================================================
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Index: none/tests/amd64/mpx.c
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===================================================================
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--- none/tests/amd64/mpx.c (revision 0)
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+++ none/tests/amd64/mpx.c (revision 13948)
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@@ -0,0 +1,38 @@
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+int
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+main (int argc, char **argv)
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+{
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+ // Since MPX is disabled all these are just NOPS.
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+ // Some of these instructions are just random.
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+ // Once the GCC support is merged creating real test cases will be easier.
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+ // http://gcc.gnu.org/wiki/Intel%20MPX%20support%20in%20the%20GCC%20compiler
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+
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+ // This is what ld.so does in _dl_runtime_resolve to save the bnds.
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+ asm ("bndmov %bnd0, (%rsp)");
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+ asm ("bndmov %bnd1, 16(%rsp)");
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+ asm ("bndmov %bnd2, 32(%rsp)");
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+ asm ("bndmov %bnd3, 48(%rsp)");
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+
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+ // Create a bnd, check lower and upper...
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+ asm ("bndmk (%rax,%rdx), %bnd0");
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+ asm ("bndcl (%rax,%rdi,4), %bnd0");
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+ asm ("bndcu 3(%rax,%rdi,4), %bnd0");
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+ asm ("bndcn 3(%rax,%rdi,4), %bnd0");
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+
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+ // Load bnd pointer and update...
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+ asm ("bndldx 3(%rbx,%rdx), %bnd2");
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+ asm ("bndstx %bnd2, 3(,%r12,1)");
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+
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+ // "bnd" prefixed call, return and jmp...
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+ asm ("bnd call foo\n\
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+ bnd jmp end\n\
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+ foo: bnd ret\n\
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+ end: nop");
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+
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+ // And set the bnds back...
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+ asm ("bndmov 48(%rsp), %bnd3");
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+ asm ("bndmov 32(%rsp), %bnd2");
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+ asm ("bndmov 16(%rsp), %bnd1");
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+ asm ("bndmov (%rsp), %bnd0");
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+
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+ return 0;
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+}
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Index: none/tests/amd64/mpx.stdout.exp
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===================================================================
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Index: none/tests/amd64/mpx.vgtest
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===================================================================
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--- none/tests/amd64/mpx.vgtest (revision 0)
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+++ none/tests/amd64/mpx.vgtest (revision 13948)
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@@ -0,0 +1,3 @@
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+prog: mpx
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+prereq: test -x mpx
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+vgopts: -q
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Index: none/tests/amd64/Makefile.am
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===================================================================
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--- none/tests/amd64/Makefile.am (revision 13947)
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+++ none/tests/amd64/Makefile.am (revision 13948)
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@@ -56,6 +56,7 @@ EXTRA_DIST = \
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loopnel.stderr.exp loopnel.stdout.exp loopnel.vgtest \
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lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \
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movbe.stderr.exp movbe.stdout.exp movbe.vgtest \
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||||||
|
+ mpx.stderr.exp mpx.stdout.exp mpx.vgtest \
|
||||||
|
nan80and64.stderr.exp nan80and64.stdout.exp nan80and64.vgtest \
|
||||||
|
nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
|
||||||
|
nibz_bennee_mmap.vgtest \
|
||||||
|
@@ -133,6 +134,10 @@ endif
|
||||||
|
if BUILD_MOVBE_TESTS
|
||||||
|
check_PROGRAMS += movbe
|
||||||
|
endif
|
||||||
|
+if BUILD_MPX_TESTS
|
||||||
|
+ check_PROGRAMS += mpx
|
||||||
|
+endif
|
||||||
|
+
|
||||||
|
|
||||||
|
# DDD: these need to be made to work on Darwin like the x86/ ones were.
|
||||||
|
if ! VGCONF_OS_IS_DARWIN
|
||||||
|
Index: configure.ac
|
||||||
|
===================================================================
|
||||||
|
--- configure.ac (revision 13947)
|
||||||
|
+++ configure.ac (revision 13948)
|
||||||
|
@@ -2322,6 +2322,27 @@ AC_MSG_RESULT([no])
|
||||||
|
AM_CONDITIONAL(BUILD_FMA_TESTS, test x$ac_have_as_fma = xyes)
|
||||||
|
|
||||||
|
|
||||||
|
+# does the amd64 assembler understand MPX instructions?
|
||||||
|
+# Note, this doesn't generate a C-level symbol. It generates a
|
||||||
|
+# automake-level symbol (BUILD_MPX_TESTS), used in test Makefile.am's
|
||||||
|
+AC_MSG_CHECKING([if amd64 assembler knows the MPX instructions])
|
||||||
|
+
|
||||||
|
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
|
||||||
|
+ asm ("bndmov %bnd0,(%rsp)")
|
||||||
|
+]])], [
|
||||||
|
+ac_have_as_mpx=yes
|
||||||
|
+AC_MSG_RESULT([yes])
|
||||||
|
+], [
|
||||||
|
+ac_have_as_mpx=no
|
||||||
|
+AC_MSG_RESULT([no])
|
||||||
|
+])
|
||||||
|
+
|
||||||
|
+AM_CONDITIONAL(BUILD_MPX_TESTS, test x$ac_have_as_mpx = xyes)
|
||||||
|
+
|
||||||
|
+
|
||||||
|
+# Does the C compiler support the "ifunc" attribute
|
||||||
|
+# Note, this doesn't generate a C-level symbol. It generates a
|
||||||
|
+# automake-level symbol (BUILD_IFUNC_TESTS), used in test Makefile.am's
|
||||||
|
# does the x86/amd64 assembler understand MOVBE?
|
||||||
|
# Note, this doesn't generate a C-level symbol. It generates a
|
||||||
|
# automake-level symbol (BUILD_MOVBE_TESTS), used in test Makefile.am's
|
||||||
@ -1,3 +1,8 @@
|
|||||||
|
-------------------------------------------------------------------
|
||||||
|
Wed Jun 18 15:08:53 UTC 2014 - dmueller@suse.com
|
||||||
|
|
||||||
|
- add VEX-r2858.diff, valgrind-r13948.diff for (bnc#883157)
|
||||||
|
|
||||||
-------------------------------------------------------------------
|
-------------------------------------------------------------------
|
||||||
Sun May 18 12:34:01 UTC 2014 - schwab@suse.de
|
Sun May 18 12:34:01 UTC 2014 - schwab@suse.de
|
||||||
|
|
||||||
|
|||||||
@ -46,6 +46,8 @@ Patch5: glibc-2.19.patch
|
|||||||
Patch6: r2798.diff
|
Patch6: r2798.diff
|
||||||
Patch7: aarch64-support.diff
|
Patch7: aarch64-support.diff
|
||||||
Patch8: aarch64-VEX-support.diff
|
Patch8: aarch64-VEX-support.diff
|
||||||
|
Patch9: VEX-r2858.diff
|
||||||
|
Patch10: valgrind-r13948.diff
|
||||||
# during building the major version of glibc is built into the suppression file
|
# during building the major version of glibc is built into the suppression file
|
||||||
%define glibc_main_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f1)
|
%define glibc_main_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f1)
|
||||||
%define glibc_major_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f2)
|
%define glibc_major_version %(getconf GNU_LIBC_VERSION | cut -d' ' -f2 | cut -d. -f2)
|
||||||
@ -144,6 +146,7 @@ cd VEX
|
|||||||
%ifarch aarch64
|
%ifarch aarch64
|
||||||
%patch8
|
%patch8
|
||||||
%endif
|
%endif
|
||||||
|
%patch9
|
||||||
cd ..
|
cd ..
|
||||||
%patch1
|
%patch1
|
||||||
%ifnarch aarch64
|
%ifnarch aarch64
|
||||||
@ -155,6 +158,7 @@ cd ..
|
|||||||
%else
|
%else
|
||||||
%patch7
|
%patch7
|
||||||
%endif
|
%endif
|
||||||
|
%patch10
|
||||||
|
|
||||||
%build
|
%build
|
||||||
%ifarch %arm
|
%ifarch %arm
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user