Dirk Mueller
2fe4f7a04e
* Added ARM64 support for FreeBSD.
* ARM64 now supports dotprod instructions (sdot/udot).
* AMD64 better supports code build with -march=x86-64-v3.
fused-multiple-add instructions (fma) are now emulated more
accurately. And memcheck now handles __builtin_strcmp using 128/256
bit vectors with sse4.1, avx/avx2.
* S390X added support for NNPA (neural network processing assist)
facility vector instructions VCNF, VCLFNH, VCFN, VCLFNL, VCRNF and
NNPA (z16/arch14).
* X86 recognizes new binutils-2.42 nop patterns.
- drop VEX-x86-nop-pattern.patch (upstream)
- drop armv6-support.diff (obsolete)
OBS-URL: https://build.opensuse.org/package/show/devel:tools/valgrind?expand=0&rev=279
68 lines
2.5 KiB
Diff
68 lines
2.5 KiB
Diff
Index: valgrind-3.23.0/VEX/priv/guest_x86_toIR.c
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===================================================================
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--- valgrind-3.23.0.orig/VEX/priv/guest_x86_toIR.c
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+++ valgrind-3.23.0/VEX/priv/guest_x86_toIR.c
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@@ -12941,6 +12941,62 @@ DisResult disInstr_X86_WRK (
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/* --- start of the SSE4 decoder --- */
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/* ---------------------------------------------------- */
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+ /* 66 0F 3A 22 /r ib = PINSRD xmm1, r/m32, imm8
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+ Extract Doubleword int from gen.reg/mem32 and insert into xmm1 */
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+ if ( sz == 2
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+ && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) {
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+
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+ Int imm8_10;
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+ IRTemp src_elems = newTemp(Ity_I32);
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+ IRTemp src_vec = newTemp(Ity_V128);
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+ IRTemp z32 = newTemp(Ity_I32);
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+
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+ modrm = insn[3];
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+
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+ if ( epartIsReg( modrm ) ) {
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+ imm8_10 = (Int)(insn[3+1] & 3);
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+ assign( src_elems, getIReg( 4, eregOfRM(modrm) ) );
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+ delta += 3+1+1;
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+ DIP( "pinsrd $%d, %s,%s\n", imm8_10,
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+ nameIReg( 4, eregOfRM(modrm) ),
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+ nameXMMReg( gregOfRM(modrm) ) );
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+ } else {
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+ addr = disAMode( &alen, sorb, delta+3, dis_buf );
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+ imm8_10 = (Int)(insn[3+alen] & 3);
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+ assign( src_elems, loadLE( Ity_I32, mkexpr(addr) ) );
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+ delta += 3+alen+1;
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+ DIP( "pinsrd $%d, %s,%s\n",
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+ imm8_10, dis_buf, nameXMMReg( gregOfRM(modrm) ) );
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+ }
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+
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+ assign(z32, mkU32(0));
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+
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+ UShort mask = 0;
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+ switch (imm8_10) {
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+ case 3: mask = 0x0FFF;
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+ assign(src_vec, mk128from32s(src_elems, z32, z32, z32));
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+ break;
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+ case 2: mask = 0xF0FF;
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+ assign(src_vec, mk128from32s(z32, src_elems, z32, z32));
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+ break;
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+ case 1: mask = 0xFF0F;
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+ assign(src_vec, mk128from32s(z32, z32, src_elems, z32));
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+ break;
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+ case 0: mask = 0xFFF0;
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+ assign(src_vec, mk128from32s(z32, z32, z32, src_elems));
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+ break;
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+ default: vassert(0);
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+ }
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+
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+ putXMMReg( gregOfRM(modrm),
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+ binop( Iop_OrV128, mkexpr(src_vec),
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+ binop( Iop_AndV128,
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+ getXMMReg( gregOfRM(modrm) ),
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+ mkV128(mask) ) ) );
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+
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+ goto decode_success;
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+ }
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+
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/* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1
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(Partial implementation only -- only deal with cases where
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the rounding mode is specified directly by the immediate byte.)
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